diff --git a/.gitattributes b/.gitattributes index 1adae079ee9547f30e5f04eeccf692ace5fdc86a..65d6869f86e7fc733678148924b612e83902a120 100644 --- a/.gitattributes +++ b/.gitattributes @@ -81,3 +81,36 @@ snapshots/jotego_jtcores_pr1242/cores/pinpon/doc/Konami's[[:space:]]Ping[[:space snapshots/jotego_jtcores_pr1242/cores/contra/doc/007121.pdf filter=lfs diff=lfs merge=lfs -text snapshots/jotego_jtcores_pr1242/cores/s16b/doc/315-5195_schematics.pdf filter=lfs diff=lfs merge=lfs -text snapshots/jotego_jtcores_pr1242/cores/flstory/doc/msm5232.ods filter=lfs diff=lfs merge=lfs -text +snapshots/jotego_jtcores_pr1242/cores/aliens/doc/051960_schematics.pdf filter=lfs diff=lfs merge=lfs -text +snapshots/jotego_jtcores_pr1242/cores/aliens/doc/k052109_schematics.pdf filter=lfs diff=lfs merge=lfs -text +snapshots/jotego_jtcores_pr1242/cores/aliens/doc/051937_schematics.pdf filter=lfs diff=lfs merge=lfs -text +snapshots/jotego_jtcores_pr1242/cores/aliens/doc/k051962_schematics.pdf filter=lfs diff=lfs merge=lfs -text +snapshots/jotego_jtcores_pr1242/cores/aliens/doc/052591/k052591_schematics.pdf filter=lfs diff=lfs merge=lfs -text +snapshots/jotego_jtcores_pr1242/cores/s18/custom/shdancer/epr-12773b.a5 filter=lfs diff=lfs merge=lfs -text +snapshots/jotego_jtcores_pr1242/cores/s18/custom/shdancer/epr-12723.a8 filter=lfs diff=lfs merge=lfs -text +snapshots/jotego_jtcores_pr1242/cores/s18/custom/shdancer/mpr-12715.b4 filter=lfs diff=lfs merge=lfs -text +snapshots/jotego_jtcores_pr1242/cores/s18/custom/shdancer/mpr-12725.a10 filter=lfs diff=lfs merge=lfs -text +snapshots/jotego_jtcores_pr1242/cores/s18/custom/shdancer/epr-12987.a4 filter=lfs diff=lfs merge=lfs -text +snapshots/jotego_jtcores_pr1242/cores/s18/custom/shdancer/mpr-12717.b9 filter=lfs diff=lfs merge=lfs -text +snapshots/jotego_jtcores_pr1242/cores/s18/custom/shdancer/epr-12774b.a6 filter=lfs diff=lfs merge=lfs -text +snapshots/jotego_jtcores_pr1242/cores/s18/custom/shdancer/mpr-12714.b3 filter=lfs diff=lfs merge=lfs -text +snapshots/jotego_jtcores_pr1242/cores/s18/custom/shdancer/mpr-12724.a9 filter=lfs diff=lfs merge=lfs -text +snapshots/jotego_jtcores_pr1242/cores/s18/custom/shdancer/mpr-12713.b2 filter=lfs diff=lfs merge=lfs -text +snapshots/jotego_jtcores_pr1242/cores/s18/custom/shdancer/mpr-12726.a11 filter=lfs diff=lfs merge=lfs -text +snapshots/jotego_jtcores_pr1242/cores/s18/custom/shdancer/mpr-12719.b11 filter=lfs diff=lfs merge=lfs -text +snapshots/jotego_jtcores_pr1242/cores/s18/custom/shdancer/epr-12716.b8 filter=lfs diff=lfs merge=lfs -text +snapshots/jotego_jtcores_pr1242/cores/s18/custom/shdancer/mpr-12712.b1 filter=lfs diff=lfs merge=lfs -text +snapshots/jotego_jtcores_pr1242/cores/s18/custom/shdancer/mpr-12718.b10 filter=lfs diff=lfs merge=lfs -text +snapshots/jotego_jtcores_pr1242/cores/s18/custom/shdancer/shdancer1/epr-12771b.a5 filter=lfs diff=lfs merge=lfs -text +snapshots/jotego_jtcores_pr1242/cores/s18/custom/shdancer/shdancer1/epr-12720.a4 filter=lfs diff=lfs merge=lfs -text +snapshots/jotego_jtcores_pr1242/cores/s18/custom/shdancer/shdancer1/epr-12772b.a6 filter=lfs diff=lfs merge=lfs -text +snapshots/jotego_jtcores_pr1242/cores/s18/custom/shdancer/shdancbl/ic3 filter=lfs diff=lfs merge=lfs -text +snapshots/jotego_jtcores_pr1242/cores/s18/custom/shdancer/shdancbl/ic16 filter=lfs diff=lfs merge=lfs -text +snapshots/jotego_jtcores_pr1242/cores/s18/custom/shdancer/shdancbl/ic2 filter=lfs diff=lfs merge=lfs -text +snapshots/jotego_jtcores_pr1242/cores/s18/custom/shdancer/shdancbl/ic17 filter=lfs diff=lfs merge=lfs -text +snapshots/jotego_jtcores_pr1242/cores/s18/custom/shdancer/shdancbl/ic18 filter=lfs diff=lfs merge=lfs -text +snapshots/jotego_jtcores_pr1242/cores/s18/custom/shdancer/shdancbl/ic4 filter=lfs diff=lfs merge=lfs -text +snapshots/jotego_jtcores_pr1242/cores/s18/custom/shdancer/shdancerj/epr-12721b.a5 filter=lfs diff=lfs merge=lfs -text +snapshots/jotego_jtcores_pr1242/cores/s18/custom/shdancer/shdancerj/epr-12722b.a6 filter=lfs diff=lfs merge=lfs -text +snapshots/jotego_jtcores_pr1242/cores/riders/ver/glfgreat/z-tilemap filter=lfs diff=lfs merge=lfs -text +snapshots/jotego_jtcores_pr1242/cores/riders/ver/glfgreat/z-tiles filter=lfs diff=lfs merge=lfs -text diff --git a/snapshots/jotego_jtcores_pr1169/.github/FUNDING.yml b/snapshots/jotego_jtcores_pr1169/.github/FUNDING.yml new file mode 100644 index 0000000000000000000000000000000000000000..cdaf17a1a74a8b38bd555b4018a410b1e495c1d3 --- /dev/null +++ b/snapshots/jotego_jtcores_pr1169/.github/FUNDING.yml @@ -0,0 +1,3 @@ +github: jotego +patreon: jotego +custom: ["https://www.paypal.me/topapate"] diff --git a/snapshots/jotego_jtcores_pr1169/cores/.gitignore b/snapshots/jotego_jtcores_pr1169/cores/.gitignore new file mode 100644 index 0000000000000000000000000000000000000000..9138c5e9d7d0c4ad542345b0f76c4f749b6d9cb8 --- /dev/null +++ b/snapshots/jotego_jtcores_pr1169/cores/.gitignore @@ -0,0 +1,6 @@ +*.qsf +*.qpf +*.f +ref-* +long +trace.ses diff --git a/snapshots/jotego_jtcores_pr1169/cores/commnd/README.md b/snapshots/jotego_jtcores_pr1169/cores/commnd/README.md new file mode 100644 index 0000000000000000000000000000000000000000..4ce25d65db844593756b0a145c8de5e5873a1383 --- /dev/null +++ b/snapshots/jotego_jtcores_pr1169/cores/commnd/README.md @@ -0,0 +1,188 @@ +JTCommando FPGA clone of Commando arcade faithful to original hardware +====================================================================== + +Please, read the main README file too. + +You have just got an expensive $200 PCB according to eBay. You have in your hands +a faithful conversion of the circuits on the Commando PCB to FPGA. If you come from +the emulation world here are some of the things different from emulators: + +-Real CPU/GPU bus sharing with delays +-Sprites handled with DMA exactly as in the original hardware +-Palettes determined by the original PROMs +-Graphics priority handled according to the original PROM +-No lag between image and input. Data is being sent to the screen in real time. +-No lag between sound and image. All hardware runs in parallel with no time multiplexing. +-Sound sampling rate: 41.663 kHz (i.e. exactly the original, 125/3 kHz) + +These technical aspects mean that the game play will be different from an emulator +in a number of ways and that some hardware tricks that were not emulated will work +here as in the original hardware. + +The ROM Master +============== +The ROM Master, aka Bruno Silva, has provided us with a .bat file to generate the necessary ROM file using MAME ROM files. Please follow the instructions of the .bat file to generate the ROM. The game works will all known ROMs. + +RELEASE HISTORY +=============== +21st Nov 2019 + - Fixes bug in SDRAM controller +13rd Nov 2019 + * Fixed occasional sprite glitching + * Updated to latest JT12 sound module. Fixes bug in JT49 envelope duration + * Set JT49 compression to level 1 (29.1dB) +7th Oct 2019 + * Main Z80 is overclocked to avoid graphic glitches. Needs further debugging + * Updated to latest JT49 sound module. Fixes many bugs in SFX. + * Added 128MB RAM module support (MiSTer only) + +20th Jul 2019 BETA RELEASE + * Some graphical issues, likely to be due to a problem in the bus arbitrion implementation. These will be fixed in the final -and public- release. + +TEST MODE +========= +To enter test mode press several times the shot button while the initial legal message is being displayed. + +CREDITS +======= + +Brought to you by Jose Tejada, aka jotego. Meet me in twitter @topapate +Checkout my patreon page here: http://patreon.com/jotego + +Special thanks to all July '19 patrons. + +Tier +3 Patrons Thanks!! +======================== +40wattrange +Alan Steremberg +albconde +Alexander Kholodov +Allen Tipper +Andrew Moore +Andylithia +Andyways +Anthony Bolek +AtariSTFan +Blue1597 +Brett McAlpine +Brian Sallee +Bruno Silva +Buster D +Carl Hagström +Carlos Del Alamo +Christian Auby +Christian Bailey +Christopher Caswell +Christopher rumford +Dacide +Daniel Bauza +Daniel Hochman +Daniel Renner +DarkStar7 +Darren Newman +Dave Ross +David Colmenero +Don Gafford +Duane Hembrick +Dustin Hubbard +Ed Balan +Eoin Gibney +Fabio +Fay Dek +Filip Kindt +Francisco Javier Fuentes Moreno +Frank Wolf +Fred Fryolator +Fredrik Berglind +Frédéric Mahé +FULLSET +Funkycochise +furrtek +Geert Oost +Gonzalo López +Gregory Hogan +Henry R +James DeRose +James Sawford +Javier Martínez +JD +Jeff Gerstmann +Jeremy Glass +Jesus Garcia +Jo Tomiyori +Joe Kalwitz +Johannes Reß +John Klimek +John Silva +John Stringer +Joshua Witt +Juan Diego Sánchez Noguera +Jérôme Moreau +Keith Kelly +Ken ottosson +Kevin Bidwell +Kyle Troutman +Leslie Law +loloC2C +Manuel +Manuel Antoni +Manuel Astudillo +Manuel Fernández +Manuelfx +Marco Tavian +Mario Salvini +Mary Marshall +Matt Charlesworth +Matt Elder +Matthew Langtry +Matthew Young +Michael Stegen +Michael Troelsen +Michael's Workshop +Miguel Angel Rodriguez Jodar +Mike Holzinger +Mordecai The Walrus +Mr.B +Neil Maguire +Nicolas Hamel +Obiwantje +Oliver Jaksch +Oliver Wndmth +Oscar Jacobsson +Oscar Laguna Garcia +Owlnonymous +Phillip McMahon +Popov +Porkchop Express +PsyFX +QcRetro +remowilliams +RetroShop.pt +Rikard Bengtsson +Rob Young +robert fisher +Roman Buser +Ryan Fig +Rysha +Salvador Perugorria Lorente +Scralings +Sembiance +SJohansson +SmokeMonster +StalkS +Stefan Nordkvist +Stephen Marshall +Steven Wilson +Suvodip Mitra +Sweetlilmre +Thomas Tahsin-Bey +Tony Peters +type78 +UKShark +Ultrarobotninja +Violeta Martin Fernandez +Visa-Valtteri Pimiä +vladimir +Vorvek +Víctor Gomariz Ladrón de Guevara +William Clemens diff --git a/snapshots/jotego_jtcores_pr1169/cores/commnd/sym-lib-table b/snapshots/jotego_jtcores_pr1169/cores/commnd/sym-lib-table new file mode 100644 index 0000000000000000000000000000000000000000..9edbacb4062182562a1814bf99534d63ea8479d6 --- /dev/null +++ b/snapshots/jotego_jtcores_pr1169/cores/commnd/sym-lib-table @@ -0,0 +1,37 @@ +(sym_lib_table + (version 7) + (lib (name "arcade")(type "KiCad")(uri "${MODULES}/jtkicad/lib/arcade.kicad_sym")(options "0")(descr "arcade")) + (lib (name "yamaha")(type "KiCad")(uri "${MODULES}/jtkicad/lib/yamaha.kicad_sym")(options "0")(descr "yamaha")) + (lib (name "toshiba")(type "KiCad")(uri "${MODULES}/jtkicad/lib/toshiba.kicad_sym")(options "0")(descr "toshiba")) + (lib (name "toaplan")(type "KiCad")(uri "${MODULES}/jtkicad/lib/toaplan.kicad_sym")(options "0")(descr "toaplan")) + (lib (name "tms_texas")(type "KiCad")(uri "${MODULES}/jtkicad/lib/tms_texas.kicad_sym")(options "0")(descr "tms_texas")) + (lib (name "singapore")(type "KiCad")(uri "${MODULES}/jtkicad/lib/singapore.kicad_sym")(options "0")(descr "singapore")) + (lib (name "Singnetics")(type "KiCad")(uri "${MODULES}/jtkicad/lib/Signetics.kicad_sym")(options "0")(descr "Singnetics")) + (lib (name "Sharp")(type "KiCad")(uri "${MODULES}/jtkicad/lib/Sharp.kicad_sym")(options "0")(descr "Sharp")) + (lib (name "sega")(type "KiCad")(uri "${MODULES}/jtkicad/lib/sega.kicad_sym")(options "0")(descr "sega")) + (lib (name "seta")(type "KiCad")(uri "${MODULES}/jtkicad/lib/seta.kicad_sym")(options "0")(descr "seta")) + (lib (name "oki")(type "KiCad")(uri "${MODULES}/jtkicad/lib/oki.kicad_sym")(options "0")(descr "oki")) + (lib (name "NKD")(type "KiCad")(uri "${MODULES}/jtkicad/lib/NKD.kicad_sym")(options "0")(descr "NKD")) + (lib (name "Nec")(type "KiCad")(uri "${MODULES}/jtkicad/lib/Nec.kicad_sym")(options "0")(descr "Nec")) + (lib (name "Mod_KC_Symbols")(type "KiCad")(uri "${MODULES}/jtkicad/lib/Mod_KC_Symbols.kicad_sym")(options "0")(descr "Mod_KC_Symbols")) + (lib (name "mitsubishi")(type "KiCad")(uri "${MODULES}/jtkicad/lib/mitsubishi.kicad_sym")(options "0")(descr "mitsubishi")) + (lib (name "konami")(type "KiCad")(uri "${MODULES}/jtkicad/lib/konami.kicad_sym")(options "0")(descr "konami")) + (lib (name "jt74")(type "KiCad")(uri "${MODULES}/jtkicad/lib/jt74.kicad_sym")(options "0")(descr "jt74")) + (lib (name "Intel")(type "KiCad")(uri "${MODULES}/jtkicad/lib/Intel.kicad_sym")(options "0")(descr "Intel")) + (lib (name "hitachi")(type "KiCad")(uri "${MODULES}/jtkicad/lib/hitachi.kicad_sym")(options "0")(descr "hitachi")) + (lib (name "fujitsu")(type "KiCad")(uri "${MODULES}/jtkicad/lib/fujitsu.kicad_sym")(options "0")(descr "fujitsu")) + (lib (name "data_east")(type "KiCad")(uri "${MODULES}/jtkicad/lib/data_east.kicad_sym")(options "0")(descr "data_east")) + (lib (name "arduino")(type "KiCad")(uri "${MODULES}/jtkicad/lib/arduino.kicad_sym")(options "0")(descr "arduino")) + (lib (name "74extra")(type "KiCad")(uri "${MODULES}/jtkicad/lib/74extra.kicad_sym")(options "0")(descr "74extra")) + (lib (name "capcom")(type "KiCad")(uri "${MODULES}/jtkicad/lib/capcom.kicad_sym")(options "0")(descr "capcom")) + (lib (name "texas_instruments")(type "KiCad")(uri "${MODULES}/jtkicad/lib/texas_instruments.kicad_sym")(options "0")(descr "texas_instruments")) + (lib (name "namco")(type "KiCad")(uri "${MODULES}/jtkicad/lib/namco.kicad_sym")(options "0")(descr "namco")) + (lib (name "taito")(type "KiCad")(uri "${MODULES}/jtkicad/lib/taito.kicad_sym")(options "0")(descr "taito")) + (lib (name "ga_konami")(type "KiCad")(uri "${MODULES}/jtkicad/lib/ga_konami.kicad_sym")(options "0")(descr "Konami IC's - inside view")) + (lib (name "ga_fujitsu_av")(type "KiCad")(uri "${MODULES}/jtkicad/lib/ga_fujitsu_av.kicad_sym")(options "0")(descr "Fujitsu gate array cell library")) + (lib (name "ga_oki_msm70v0000")(type "KiCad")(uri "${MODULES}/jtkicad/lib/ga_oki_msm70v0000.kicad_sym")(options "0")(descr "OKI gate array cell library")) + (lib (name "jt_ram")(type "KiCad")(uri "${MODULES}/jtkicad/lib/jt_ram.kicad_sym")(options "0")(descr "RAM IC's")) + (lib (name "jt_rom")(type "KiCad")(uri "${MODULES}/jtkicad/lib/jt_rom.kicad_sym")(options "0")(descr "ROM IC's")) + (lib (name "jt_cpu")(type "KiCad")(uri "${MODULES}/jtkicad/lib/jt_cpu.kicad_sym")(options "0")(descr "CPU's")) + (lib (name "technos")(type "KiCad")(uri "${MODULES}/jtkicad/lib/technos.kicad_sym")(options "")(descr "")) +) diff --git a/snapshots/jotego_jtcores_pr1169/cores/cps15/README.md b/snapshots/jotego_jtcores_pr1169/cores/cps15/README.md new file mode 100644 index 0000000000000000000000000000000000000000..23e5dbcd3129e63f9826f7e33c45ebdf88253fa9 --- /dev/null +++ b/snapshots/jotego_jtcores_pr1169/cores/cps15/README.md @@ -0,0 +1,397 @@ +# JTCPS - FPGA Arcade Hardware + +You can show your appreciation through +* Patreon: https://patreon.com/jotego +* Paypal: https://paypal.me/topapate + +Capcom System 1/1.5/2 compatible verilog core for FPGA by Jose Tejada (jotego). + +# Original Documentation + +[The internet archive](www.archive.org) holds some schematics related to this work. + +* [Forgotten Worlds manual](https://archive.org/details/arcademanual_forgotten-worlds/page/n15/mode/2up) + +# Memory Requirements + +All CPS1 and CPS1.5 operate correctly on a 32MB SDRAM system. Some CPS2 games may require a 64MB module. Those games are listed as having a GFX ROM of 16MB or more below. Please check the CPS2 ROM size section. + +# Control + +MiSTer allows for gamepad redifinition. However, the keyboard can be used with more or less the same layout as MAME for MiST(er) platforms. Some important keys: + +-F12 OSD menu +-P Pause. Press 1P during pause to toggle the credits on and off +-5,6 1P coin, 2P coin +-1,2 1P, 2P + +For MiST, the first 6 gamepad buttons are used for game buttons, the next 2 buttons are used for credit and start buttons. If there is still one button left in the gamepad, it will be used for pause. + +There is an option to slow down the game (available only for CPS2). If you enable the 1P_hold_for_slow setting on the OSD, then while the 1P button is held the game will run at half the speed. Release the 1P button to go back to normal speed or disable the option in the OSD. Note that if the option is enabled the 2P, 3P and 4P buttons will also activate the slow down effect. + +# Setup + +## MiSTer + +Copy the RBF file to `_Arcade/cores` and the MRA files to `_Arcade`. Copy zipped MAME romsets to `_Arcade/mame`. Enjoy. + +It is also possible to keep the MAME romsets in `_Arcade/mame` but have the MRA files in `_CPS` and the RBF files in `_CPS/cores` + +The _rotate screen_ OSD option is ignored for horizontal games. + +## MiST + +You need to generate the .rom file using this (tool)[https://github.com/sebdel/mra-tools-c/tree/master/release]. Basically call it like this: + +`mra ghouls.mra -z rompath -A` + +And that will produce the .rom file and a .arc file. The .arc file can be used to start the core and directly load the game rom file. Note that the RBF name must be JTCPS1.RBF for it to work. The three files must be in the root folder. + +*Important*: make sure to have the latest firmware and latest version of the mra tool. + +Copy the RBF, .arc and .rom files to MiST and enjoy! + +Note that there is no screen rotation in MiST. Vertical games require you to turn your screen around. You can however flip the image through the OSD. + +Pang! 3 and all CPS 1.5/2 games did not use DIP switches to configure the game, but a small non-volatile RAM. You have to enter the test menu to configure it (via OSD). After you have configured the settings, save the contents using the OSD option *Save NVRAM*. A file will be created at the root of your SD card called game.RAM, where game will match the name of the .ROM file used with the game. + +# Issues + +Please report issues (here)[https://github.com/jotego/jtbin/issues]. + +## QSound Hiss + +The DSP16A clock enable must be an exact multiple of 30MHz. Otherwise the sampling period will not be constant, generating jitter. The effect of jitter is very obvious in the DAC used on MiST because when all sound goes silent an ugly transient occurs. That effect was not noticeable in MiSTer, which uses a different DAC. + +Even with the right clock enable, there is still hiss occasionally in MiST(er). Using the FPGA logic analyzer I could check that the period was indeed constant but hiss was present. + +# CPS-1 Audio + +The OKI PCM input clock is 1MHz, depending on the SS input setting, this gives two sampling frequencies: + +SS | Fs (Hz) | 4xFs | a | 1-a +---|---------|-------|---------|-------- +0 | 6097.5 | 24390 | 0.8200 | 0.1800 +1 | 7575.7 | 30303 | 0.8524 | 0.1476 + +The original board has a first-order low pass filter at 770 Hz, this can be implemented with a first order IIR filter: + +y[k] = a * y[k-1] + (1-a) * x[k] + +where a = exp(-wc/T ) +wc = 2*pi*770 = 4838 rad/s +T = 1/4Fs + +# QSound + +QSound requires its own firmware rom to work. In MAME this is called qsound.zip. QSound sampling frequency is 3746 ticks of the input clock, when the clock enable applied is 2/3. For a 90MHz input clock, this will result in the correct internal 30MHz and in a sampling frequency of 90MHz/3747=24,019.2Hz + +The original board had a digitally controlled amplifier. The volume set on this amplifier could be read back by the CPU and DSP. In order to control the value read by these devices, press and hold the coin button for 1P while pressing up or down (for more or less volume). Note that this does not have an actual effect on the sound output. + +# PAL Dumps +PAL dumps cam be obtained from MAME rom sets directly. Use the tool jedutil in order to extract the equations from them. The device is usually a gal16v8. For instance: + +``` +jedutil -view wl24b.1a gal16v8 +``` + +In order to see the equations for Willow's PAL. + +# Compilation +The core is compiled using jtcore from **JTFRAME**. Follow the instructions in the README file of (JTFRAME)[https://github.com/jotego/jtcores/tree/master/modules/jtframe] and then: + +``` +source setprj.sh +jtcore cps1 -mister +``` + +This will produce the mister file. + +## Static Time Analysis (STA) + +MiST and SiDi compilations produce STA clean files with the default seed. However the MiSTer RBF file with everything enabled doesn't always come STA clean. If you disable HDMI or sound during compilation the RBF file will normally be STA clean. Public binary distribution in [jtbin](https://github.com/jotego/jtbin) are either STA clean or violations are below 99ps. + +# MRA Format + +Offset | Length | Use +----------|--------|------------- + 0 / 0o | 2 | Sound CPU ROM* + 2 / 2o | 2 | PCM data* + 4 / 4o | 2 | GFX ROM* + 6 / 6o | 2 | QSound firmware* +10h / 20o | 18 | CPS-B configuration +22h / 42o | 1 | Game ID +23h / 43o | 2 | Bank offset +25h / 45o | 2 | Bank mask +27h / 47o | 1 | CPS-A board type (Pang! 3, etc.) +30h / 60o | 11 | Kabuki keys (CPS 1.5 only) +28h / 50o | 1 | CPS2 board type +2ch / 54o | 20 | CPS2 keys + +* All offset values are expressed in kilobytes and stored with MSB byte second + +The offset for each graphic bank is comprised of two bytes. Each offset data is packed in 4 bits, with the MSB used for bank 3: + +{ Offset_bank3, ..bank2, bank1, bank0 } = { byte 24h, byte 23h } + +The 4-bit offset makes the MSB of the 20-bit GFX ROM address. + +CPS-A board type format: + +Bits | Use +-------|---------------------------- +0 | CPU speed. 0=10MHz, 1=12MHz +3:1 | Enables additional inputs on CPS-B chip side +4 | High for charger games +5 | 0 = Disables Kabuki decryption + +CPS2 board type format: + +Bits | Use +-------|------- +1:0 | Controller type + +# SDRAM Usage + +## CPS 1/CPS 1.5 + + +SDRAM bank | Usage +-----------|------- +0 | RAM/VRAM/M68000 ROM +1 | Sound CPU/PCM samples +2 | GFX +3 | GFX + +## CPS 1.5 ROM Size + +The SDRAM layout is the same as for CPS 1. Although samples are much larger than in CPS 1 titles, they still fit in one SDRAM bank sharing space with the Z80 ROM. + +Game | CPU | Z80 | GFX | Q-Sound | +----------------------|---------|-------------|---------|---------| +Warriors of Fate | 1 MB | 128 kB | 4 MB | 2 MB | +Cadillacs & Dinosaurs | 1.5 MB | 128 kB | 4 MB | 2 MB | +The Punisher | 1.5 MB | 128 kB | 4 MB | 2 MB | +S.N. Slam Masters | 2.0 MB | 128 kB | 6 MB | 4 MB | +Muscle Bomber Duo | 2.0 MB | 128 kB | 6 MB | 4 MB | + + +## CPS 2 ROM Size + +It looks like the 16kB memory add-on is not used for regular games. Maybe it is used for +network connectivity only. + +Game | CPU | Z80 | GFX | Q-Sound |Obj base| Addon | Popularity +----------------------|---------|-------------|---------|---------|--------|-------|------------ +19XX | 2.5 MB | 128 kB | 10 MB | 4 MB | 7080 | No | 191 +1944 | 1.5 MB | 128 kB | 20 MB | 8 MB | 7080 | No | 161 +Alien vs Predator | 2.0 MB | 128 kB | 16 MB | 4 MB | 7000 | No | 637 +Armored Warriors | 4.0 MB | 256 kB | 20 MB | 4 MB | 7000 | No | 278 +Battle Circuit | 3.5 MB | 256 kB | 16 MB | 4 MB | 7080 | No | 87 +Capcom Sports Club | 2.5 MB | 128 kB | 8 MB | 4 MB | 7080 | No | 20 +Cyberbots | 4.0 MB | 256 kB | 32 MB | 4 MB | 7080 | No | 141 +Darkstalkers | 4.0 MB | 256 kB | 20 MB | 4 MB | 7080 | | 146 +Dimahoo | 2.0 MB | 256 kB | 16 MB | 8 MB | 7080 | No | 32 +DnD Shadow o. Mystara | 4.0 MB | 256 kB | 24 MB | 4 MB | 7080 | No | 336 +DnD Tower of Doom | 2.5 MB | 128 kB | 12 MB | 4 MB | 7080 | No | 108 +Eco Fighters | 2.0 MB | 128 kB | 12 MB | 4 MB | 7000 | | 64 +Giga Wing | 1.5 MB | 128 kB | 16 MB | 8 MB | 7080 | | 66 +Hyper SF II | 4.0 MB | 256 kB | 32 MB | 8 MB | 7080 | | 171 +Janpai | 1.0 MB | 128 kB | 16 MB | 4 MB | 7000 | | 15 +Jyangokushi | 0.5 MB | 128 kB | 16 MB | 4 MB | | | 1 +Mars Matrix | 1.5 MB | 128 kB | 32 MB | 8 MB | | No | 57 +Marvel Super Heroes | 4.0 MB | 256 kB | 32 MB | 4 MB | | | 165 +Marvel vs SF | 4.0 MB | 256 kB | 32 MB | 8 MB | | | 336 +Marvel vs CAPCOM | 4.0 MB | 256 kB | 32 MB | 8 MB | | | 377 +Megaman 2 | 1.5 MB | 256 kB | 8 MB | 4 MB | | | 225 +Darkstalker's revenge | 4.0 MB | 256 kB | 32 MB | 4 MB | | | 54 +Progear | 1.0 MB | 128 kB | 16 MB | 8 MB | 7080 | No | 72 +Puzz Loop 2 | 2.0 MB | 128 kB | 16 MB | 4 MB | 7000 | | 16 +Quiz Nanairo Dreams | 2.0 MB | 128 kB | 8 MB | 4 MB | | | 8 +Ring of Destruction | 3.0 MB | 256 kB | 18 MB | 4 MB | | | 293 +Slam Masters 2 | 3.0 MB | 256 kB | 18 MB | 4 MB | | | 291 +SF alpha 1 | 2.0 MB | 256 kB | 8 MB | 4 MB | 7000 | | 190 +SF alpha 2 | 3.0 MB | 256 kB | 20 MB | 4 MB | 7000 | | 218 +SF alpha 3 | 4.0 MB | 256 kB | 32 MB | 8 MB | 7000 | | 456 +SF zero 2 alpha | 3.0 MB | 256 kB | 20 MB | 4 MB | 7000 | | 293 +Super Gem Fighter | 2.5 MB | 256 kB | 20 MB | 8 MB | | | 252 +Super Puzzle Fighter 2| 1.0 MB | 256 kB | 4 MB | 4 MB | 7000 | | 210 +SF2 New Challengers | 2.5 MB | 128 kB | 12 MB | 4 MB | 7080 | No | 135 +SF2 Turbo | 3.5 MB | 256 kB | 16 MB | 4 MB | 7080 | |1200 +Vampire Savior 1 | 4.0 MB | 256 kB | 32 MB | 8 MB | | | 30 +Vampire Savior 2 | 4.0 MB | 256 kB | 32 MB | 8 MB | | | 26 +X-Men Children of A. | 4.0 MB | 256 kB | 32 MB | 4 MB | 7080 | No | 179 +X-Men vs SF | 3.5 MB | 256 kB | 32 MB | 4 MB | 7080 | No | 337 + +# Simulation + +## Game +1. Generate a rom file using the MRA tool +2. Update the symbolic link rom.bin in ver/game to point to it +3. If all goes well, `go.sh` should update the sdram.hex file + But if sdram.hex is a symbolic link to something else it might + fail. You can delete sdram.hex first so it gets recreated + + `go.sh` will fill up sdram.hex with zeros in order to avoid x's in + simulation. + +4. Apply patches if appropiate. The script `apply_patches.sh` can generate + some alternative hex files which skip some of the test code of the game + so it boots up more quickly + +5. While simulation is running, it is possible to update the output video + files by running `raw2jpg.sh` + +Some Verilog macros: + +1. FORCE_GRAY ignore palette and use a 4-bit gray scale for everything +2. REPORT_DELAY will print the average CPU delay at the end of each frame + in system ticks (number of 48MHz clocks) +3. JTCPS_TURBO forces turbo mode, speeding up -slightly- the game speed, especially on boot-up + +## Video + +Video only simulations can be done using mame dumps. Use the tool *cfg2mame* in the *ver/video* folder +to create two *.mame* files that can invoked from mame to dump the simulation data. Run the game in debug +mode but source from MAME the register file that *cfg2mame* creates. Then at the point of interest souce *vram.mame*. That creates the file vram.bin. Copy that file to a directory with the mame name of the game. Add a numerical index (see the other folders for examples). Create a hex file following the examples in +the other files too. Now you run go.sh like this: + +``` +go.sh -g game -s number -frame 2 +``` + +This will run the simulation for the folder *game* and looking for files with the *number* index. If you + need to look at the sprites too, you need to run more than one frame as the object DMA needs a frame to + fill in the data. + +# Support + +You can show your appreciation through +* Patreon: https://patreon.com/jotego +* Paypal: https://paypal.me/topapate + +# Licensing + +Contact the author for special licensing needs. Otherwise follow the GPLv3 license attached. + +# Patron Acknowledgement + +The following patrons supported the development of CPS1.5 +``` +3style Chris Harvey Joeri van Dooren Oliver Wndmth +80's spaceman cohge Johan Smolinski Oriez +Adam Davis Coldheat007 John Casey Oscar Laguna Garcia +Alan Shurvinton Dakken Jonathan Loor Oskar Sigvardsson +Alfredo Henriquez Dan Jonathan Tuttle Patrick Roman Fabri +Alonso J. Núñez Daniel Bauza Jorge Slowfret Paweł Mandes +Anders Rensberg Daniel Estreito Josiah Wilson Per Sweden +Andrea Chiavazza dannahan JPS (RetroFPGA) Phillip McMahon +Andreas Micklei Darren Wootton Juan E. Gayon PsyFX +Andrew Ajello Dasutin Justin D'Arcangelo Purple Tinker +Andrew Boudreau David Ashby Kitsuake Rachael Netz +Andrew Francomb David Fleetwood KnC RandomRetro +Andrew Moore David Jones Kyle Good RetroDriven +Andy Palmer David Mills Lee Osborne Richard Eng +Andyways derFunkenstein Leslie Law Richard Murillo +angel_killah DJ Lethal Lionel LENOBLE Richard Simpson +Angelo Kanaris Don Gafford Louis Martinez Robert Bergman +Anthony Monaco DrMnike Luc JOLY Robert Forbes +Anton Gale Ed Balan Magnus Kvevlander Robert MacLean +Antonio Villena Edward Rana Manuel Astudillo Robert Mullings +Aquijacks Eric J Faulkes Marcus Hogue Roman Buser +Arcade Express Filip Kindt Martin Di Palma rsn8887 +Arjan de Lang Francis B Matt Evans Ryan Fig +asdfgasfhsn Frank Hoedemakers Matt ODonnell Sassbasket Silvercloud +Bear S Frédéric Mahé Matthew Humphrey Sebastien Goutal +Ben Toman Gary Greenan Matthew Woodford Skeeter +Bender Gavin Matthew Young Sofia Rose +Bliz 452 Greg Max Schütz Spank Minister +Bob Gallardo Gregory Val Michael Deshaies Spencer Bradley +Brent Fraser Gus Douboulidis Michael Yount Stephen Goldberg +Brett T Davis Handheld Obsession Mick Stone Steven Wilson +brian burney Hard Rich Mike Jegenjan Steven Yedwab +Brian Sallee Henrik Nordström Mike Parks Thomas Irwin +Carrboroman HFSPlay MiSTerFPGA.co.uk Toby Boreham +Charles hyp36rmax mottzilla . Travis Brown +Chi Wai Tran Jacob Hoffman Nailbomb Trifle +Chris Jardine Jeff Roberts natalie Ulf Skutnabba +Chris smith Jeremy Hasse Neil St Clair Ultrarobotninja +Chris W Miller Jeremy Kelaher Nico Stamp Victor Bly +Christian Jesse Clark nonamebear Victor Fontanez +Christian Bailey Jim Knowler nullobject Víctor Gomariz Ladrón de Guevara +Christopher Gelatt Jo Tomiyori Oliver Jaksch Xzarian + yoaarond +``` +The following patrons supported the development of CPS2 +``` + 80's spaceman Adam Small Adam Zorzin +Adam is Adan Jacquez Adrian Labastida Adrian Nabarro +Alan Shurvinton Alexander Lash Alexander Upton Alfonso Clemente +Alonso J. Alvaro Paniagua Andrea Chiavazza Andreas Micklei +Andrew Boudreau Andrew Schmidt Angelo Kanaris Anthony Monaco +Anton Gale Antwon Aquijacks (Flashjacks Aqy +Arend Pronk Arthur Blough Arthur Fung BRCDEvg +Banane Bear S Ben Toman Bitmap Bureau +Bitmaps Retro Bliz 452 Brandon Peach Brandon Smith +Brandon Thomas Brent Fraser Brian Peek Brian Plummer +Bruno Freitas Bruno M C Cameron Tinker +Carrboroman Cesar Sandoval Charles Chris Chung +Chris Mzhickteno Chris Tuckwell Chris W Chris smith +Christian Bailey Clinton Cronin Cobra Clips Coldheat007 +Colin Colehour Colt83 DARK WEB Dan Doyle +Daniel Daniel Casadevall Daniel Fowler Daniel Page +Daniel Zetterman Darren Wootton Dasutin David Drury +David Filskov David Fleetwood David Jones Denis Brækhus +Diana Carolina Dimitris Zongas DrMnike Dre137 +Eric J Eric Schlappi Eric Walklet Five Year +Flavio Real Florian Raoult Focux Gluthecat +GohanX Gonzalo Lopez Goolio Greg +Gregory Val HFSPlay Handheld Obsession Henry +Ibrahim ItsBobDudes JOSE LUIS JR +Jack Sammons Jacob Hoffman Jacob Lawter James B +James Dingo James Kilgore Javier Rodas Jeff Roberts +Jeremy Hasse Jerry Suggs Jesse Clark Jesus Rodriguez +Jim Knowler Jockel Johan Smolinski John Figueroa +John Fletcher John Hood John Silva John Wilson +Jonah Phillips Jonathan Brochu Jonathan Loor Jonathan Tuttle +Jootec from Jorge Jork Sonkinfield Joseph Milazzo +Josh Emery Josh Mayer Josiah Wilson Justin D'Arcangelo +Kai Cherry Keith Gordon Kem Yos Ken Scott +Kendrick Hughes Kevin Gudgeirsson KnC KrzysFR +L.Rapter LFT Laurent Cooper Lee Grocott +Lee Osborne Luc JOLY Mack H Magnus Kvevlander +Manuel Astudillo Marco Emparan Mark Baffa Mark Davidson +Mark R MarthSR Martin Ansin Matheus +Matsu Matt Elder Matt Evans Matt Lichtenberg +Matt McCarthy Matt ODonnell Matthew Humphrey Matthew Woodford +MechaGG Megan Alnico MiSTerFPGA.co.uk Michael Berger +Michael C Michael Deshaies Michael Rea Mick Stone +Mike Jegenjan Mike Olson Mike Parks Mottzilla +NINE Nailbomb Narugawa Neil St +NerdyNester Nick Delia Nick G Nico Stamp +Nicolas Hurtado NonstopXiaowei OopsAllBerrys Oriez +Oskar Sigvardsson Parker Blackman Patrick Roman Paul Cunningham +Paul M Paulo M. Paweł Mandes PeFClic +Per Ole Philip Lai Philip Lawson Piafoman +Pierre-Emmanuel Martin Pontus Nyholm Rachael Netz Rachel Schaeffer +RandomRetro Raph_friend Raphael Melgar RayGun +Richard Eng Richard Murillo Richard Simpson Rick Ochoa +Ronald Dean Roro Ryan Ryan Fig +Ryan O'Malley Sam Hall Samuel Warner Schnookums +Sofia Rose Spank Minister SteelRush Stefan Krueger +Stephen R Steve Ikeguchi Steve Skrzyniarz Steven Hansen +Steven Yedwab Stuart Morton SuperBabyHix Taehyun Kim +Tales Dilli TealShark Terse The Collector +The Video Thomas Attanasio Thomas Capetanakis Thomas Irwin +Tobias Dossin Travis Brown Trifle Turboman UK +Ty B VickiViperZabel Victor Bly Victor Fontanez +Will Abbott William Clemens Yunus Soğukkanlı Zach Marquette +Zoltan Kovacs albertprime alejandro carlos angel_killah +arcadebros blackwine brian burney bruno_tapez +cbab chauviere benjamin dannahan datajerk +deathwombat derFunkenstein gunmakuma joshewah777 +kccheng kernelchagi liphy natalie +nonamebear retrod00d rsn8887 scapeghost +slayer213 taal.M tonitellezb troy coberly +yoaarond 종규 박 +``` \ No newline at end of file diff --git a/snapshots/jotego_jtcores_pr1169/cores/gng/README.md b/snapshots/jotego_jtcores_pr1169/cores/gng/README.md new file mode 100644 index 0000000000000000000000000000000000000000..480a77aa964435ee43cb4c89c157d6ec5c83ddfd --- /dev/null +++ b/snapshots/jotego_jtcores_pr1169/cores/gng/README.md @@ -0,0 +1,44 @@ +Release history +=============== + +18th Apr 2022 + * Makes color flash bug possible, like the original board + +21st Nov 2019 + * Fixes bug in SDRAM controller +13th Nov 2019 + * Fixed occasional sprite glitching + * Updated to latest JT12 sound module. Fixes bug in JT49 envelope duration + * Set JT49 compression to level 1 (29.1dB) +7th Oct 2019 + * Moved back to old scan doubler. Please use MiSTer custom filters if + the scroll is not smooth for you. + * Updated to latest JT49 sound module. Fixes many bugs in SFX. + * Added 128MB RAM module support (MiSTer only) + +13th Sept 2019 + * Fixed ogre sound + * Fixed sprite alignment + * Fixed bug that erased the first pixel of the sprite line buffer + * Added more DIP options through OSD menu + * Better scan doubler in MiSTer, although it requires a reset sometimes + * MiSTer core name changed to JTGNG, as was in MiST before + * MiST ROM file changed to follow the same format as MiSTer's + * Reduced SDRAM speed (48MHz) for greater robustness + +--- history of older releases is not shown here + + +Project Structure +================= + +This work has two separate parts: + +1. A verilog model of the original hardware, replicated from original schematics. This is found in the hdl folder. Some test benches are available in the "ver" (for verification) folder. Data sheets of parts used in the original design are located in the "doc" folder. This is interesting to understand how it worked. It can be used to repair broken boards too. + +2. A modern clone written in Verilog. It has been made with the MiST board in mind but the game itself (jtgng_game module) is highly portable. All components used aim to be cycle exact -some even sub-cycle exact- so the recreation is the most similar thing to having the original PCB you can get. + +Notes +===== + +Install LWTOOLS (http://lwtools.projects.l-w.ca/) to assemble m6809 source code for test cases. \ No newline at end of file diff --git a/snapshots/jotego_jtcores_pr1169/cores/mikie/README.md b/snapshots/jotego_jtcores_pr1169/cores/mikie/README.md new file mode 100644 index 0000000000000000000000000000000000000000..113b597e51bd515183715feb7d518a4879bacbbf --- /dev/null +++ b/snapshots/jotego_jtcores_pr1169/cores/mikie/README.md @@ -0,0 +1,143 @@ +*This repository has been consolidated in [JTGNG](https://github.com/jtgng)* +# JTKICKER/JTYIEAR FPGA core compatible with Kicker/Yie Ar Kung-fu hardware + +You have in your hands a faithful reproduction of Kicker's hardware. We have analysed the PCB and extracted full schematics from it. We burnt EPROMs with specific code designed to test the custom chips functionality. The discoveries found during this process have been reported to the MAME team. So we can improve the experience in emulators where possible too. + +You can show your appreciation through +* [Patreon](https://patreon.com/jotego) +* [Paypal](https://paypal.me/topapate) + +# Known Issues + +It hasn't been possible to assess whether the INTSHOW custom chip outputs the current scan line or the current vertical scroll position, as these values are the same for over a third of the line. And it is at that time when when the INTSHOW value is easy to read, as it is when the NMI interrupt comes in. In practice, it doesn't seem to matter. + +The relays used in the sound signal path in some games may be for altering the filter response or for shutting off a channel. The purpose is not clear and I still have to measure the effect on the board. + +# System Comparison + +Games based on 082, 083 and 503 graphic chips. All have a pixel clock of 6.144MHz derived from a 18.432MHz oscillator. + +Game | Date | ID | Palette PROM | 085 | CPU1 | CPU2 | PSG | VLM5030 | Sch | eBay price | YT views | +----------------|------------|-----|---------------|-----|------|----------|-------|----------|-----------------------------|---------------|-------------------| +Mega Zone | 1983 | No | Only output | No | 6809 | Z80+8039 | x1 | No | Yes, only 083 |25€ |10.614(2016) | +Yie Ar Kungfu |19/Nov/1984 |GX407| Only output | No | 6809 | | 74689 | Yes | Yes, only 082,083 |15€ cart |3.6 M (2013) NES | +Shaolin's Road |22/Mar/1985 |GX477| All elements | Yes | 6809 | | 74689 | No | Yes |97.13€ |27.664(2018) | +Track'n Field |10/Oct/1983 | No | All elements | No | | | | Yes | Partial-Blurred |7 a 60€ cart |2.7 M (2015) NES | +Hyper Sports |31/May/1984 | No | All elements | Yes | | | | Yes | Same as Road Fighter |80€ |41.562(2012) | +Road Fighter |22/Nov/1984 |GX461| All elements | | 6809 | Z80 | 74689 | Yes | Yes |15 a 70€ cart |4 M (2010) NES | +Super Basketball| 1984 |GX405| All elements | Yes | 6809 | Z80 | 74689 | Yes | Yes,with labels |159€ |23.494 (2014) | +Mikie |15/Nov/1984 | No | All elements | Yes | 6809 | Z80 |2x74689| No | Yes,with labels, small |11€ cart |50.381 (2010) | +Pandora's Palace| 1984 | No | Only output | Yes | | | | No | Yes,with labels | € |14.167 (2010) | +Ping Pong | |GX555| | | | | | | Extracted by JOTEGO |60€ |8.530 (2012) NES | +Roc'n Rope | 1984 | No | Only output | No | | | 8910 | No | Yes, only 082,083 |350€PCB 50€cart|43.873 (2011) | +Circus Charlie | 1984 | | | No | 6809 | Z80 | 74689 | No | Yes, 082, 602 |350€PCB 50€cart| 107k | + +Road Fighter uses the same board as Hyper Sports, but a ROM jumper in the video board is different, changing the ROM mapping. Road Fighter does not have the VLM5030 section soldered. + +# Test Mode + +* Super Basketball test mode is enabled by holding 1P and 2P while the game boots +* The upper 3 bits for DIP switches in Road Fighter/Hyper Sports are undocumented. Bit 16 sets the flip mode in Road Fighter and a different ROM mapping in Hyper Sports + +# Acknowledgement + +This development has been possible thanks to the board donated by Brian Schinzel and the following patrons: + +``` +8bits4ever Adam Leslie Adam Small Adam Zorzin +Adrian Labastida Alan Shurvinton Alda Alesio Alden +Alex Mandic Alexander Lash Alexander Upton Alfonso Clemente +Alvaro Paniagua Andrea Bogazzi Andrea Chiavazza Andreas Micklei +Andrew Boudreau Andrew Hannan Andrew P Gibson Andrew Schmidt +Angel Aguinaga Angelfred Angelo Kanaris Anselmo Moreno +Anthony Monaco Antoine Mariette Anton Gale Antwon +Aquijacks (Flashjacks Arend Pronk Arthur Blough Arthur Fung +Aurich Lawson BRCDEvg Banane Bear S +Ben Ben Sanborn Ben Toman Bitmap Bureau +Bitmaps Retro Bliz 452 Blue Abs Boris Pruessmann +Brandon Lennie Brandon Peach Brandon Smith Brandon Thomas +Brent Fraser Brian Peek Brian Plummer Bruno M +Bryan Adams Bryan Evans C Cameron Berkenpas +Cameron Tinker Carrboroman Cesar Sandoval Charles +Chris Chris Chung Chris D Chris Hoff +Chris Maguire Chris Mzhickteno Chris Tuckwell Chris W Miller +Chris smith Christian Bailey Clinton Cronin Cobra Clips +Colin Colehour Colin Edwards Colt83 Cory Stargel +DARK WEB DANGer Dan Doyle Daniel Daniel . +Daniel Casadevall Daniel Dongil Daniel Fowler Daniel Page +Daniel Tibi Daniel Zetterman Darren Newman Darren Wootton +Daryll David Dasutin Dave Douglas Dave Test +David Drury David Filskov David Fleetwood David Jones +Denis Brækhus Denny Letourneau Diana Carolina Didgeridoo +Didier Touron Dimitris Zongas Dr Catjail Dr. Octagon +DrMnike Dre137 Edward Mallett Eren Kotan +Eric Eric Gutt Eric J Faulkes Eric Walklet +Fabio Michelin Federico Five Year Guy Florian Raoult +Frank Schwab Fred Rojas Geddon GeorgeSpinner +Gluthecat GohanX Goolio Grant McNaught +Greg Greg Sargent Gregory Val HFSPlay +Handheld Obsession Henry Henry R Hentai Joe +Hugo Pinto ItsBobDudes JOSE LUIS JR +Jack Sammons Jacob Hoffman Jacob Lawter James Dingo +James Durden James Kilgore James Wilson Jason Baker +Jeff Roberts Jeremy Hasse Jerry Suggs Jesse Clark +Jim Knowler JimLahey Jimmy Dozier Jimmy Richards +Jockel Joel Albino Johan Smolinski John Figueroa +John Fletcher John Hood John Silva John T. Keen +John Wilson Johnny harvick Jonah Phillips Jonathan +Jonathan Brochu Jonathan Loor Jonathan Tuttle JonathanValls +Joost Peters Jootec from Jorge Jork Sonkinfield +Jose L Jose Lopez Josep Barbie Joseph Kulinski +Joseph Milazzo Joseph Mogavero Josh Emery Josh Mayer +Josh Yates-Walker Josiah Wilson Julian Baptiste Justin D'Arcangelo +Kai Cherry Kai Luotojoki Keith Gordon Kem Yos +Ken Scott Kevin Dayton Kevin Gudgeirsson KnC +Kricys KrzysFR Kyle Pedersen L.Rapter +Lakeside Laurent Cooper Lee Grocott Lee Osborne +Luis F Giron M Reznor MaDDoG Mack H +Madox Magnus Kvevlander Manuel Astudillo Marco Emparan +Mark Baffa Mark DeRidder MarthSR Martin Ansin +Matt Elder Matt Evans Matt Hargett Matt Heinrich +Matt Lichtenberg Matt McCarthy Matt Postema Matthew Pollard +Matthew Woodford MechaGG MiSTer Retro Michael Anderson +Michael Bariszlovits Michael Berger Michael C Michael Eggers +Michael Ferguson Michael Rea Michael_DKT Mike Holzinger +Mike Jegenjan Mike Olson Mike Parks Mottzilla +My War Nailbomb Narugawa Neil St Clair +NerdyNester Nic Kaiman Nick Delia Nick Gudauskas +Nico Stamp Nicolas Hurtado Niko NonstopXiaowei +Norman Wehrle Obvious Fakename OopsAllBerrys Or even +Oriez Oskar Sigvardsson PANICKED SCREECHING. Pascal Courtois +Patrick Roman Paul Paul Cunningham Paul Hoggett +Paulo M. Paweł Mandes PeFClic Pedro Santiago +Per Ole Philip Lai Philip Lawson Piafoman +Pierre-Emmanuel Martin Pontus Nyholm Rachael Netz Rachel Schaeffer +Ramon Gamaliel RandomRetro Raphael Melgar Raul3D +RayGun RetroRGB Rex Kung Rex Willer +Richard Eng Richard Murillo Richard Simpson Rick Ochoa +Riyad Twair Robert Daniel Robert Hayes Romain Dijoux +Ronald Dean Ronan Amicel Ruben Ryan +Ryan O'Malley SIDKidd64 Sam Hall Samuel Warner +Sang Hee Sascha Zupanek Schnookums Ser Erris +Shannon King Simon Osborne Spank Minister SteelRush +Stefan Krueger Stephen R Price Steve Ikeguchi Steve Lin +Steve Skrzyniarz Steve Tack Steven Hansen Steven Yedwab +Stuart Morton Sunder Raj SuperBabyHix Synbios +Syrotuck Taehyun Kim Taiki Hosoda Tales Dilli +Terse The Collector The Video TheLevelOfDetail . +Thomas Attanasio Thomas Irwin Thorias Timothy Bearup +Tobias Dossin Tom Milner Topher Campbell Travis Brown +Trifle Turboman UK Ty B VickiViperZabel +Victor Bly Victor Fontanez Will Abbott William Clemens +William Tryon Yunus Soğukkanlı Zach Marquette Zoltan Kovacs +albertprime alejandro carlos angel_killah arcadebros +benedict lindley blackwine brian burney cbab +chauviere benjamin circletheory datajerk deathr0w +deathwombat derFunkenstein gunmakuma jbrlll +jim br joshewah777 kamel rasennadja kccheng +kernelchagi keropi liphy meng po +metal natalie nonamebear pacoarcade +patrick pejic qzxcvbn retroPREZ retrod00d +rsn8887 slayer213 taal.M tonitellezb +troy coberly turbochop3300 type78 yoaarond +``` diff --git a/snapshots/jotego_jtcores_pr1169/cores/outrun/README.md b/snapshots/jotego_jtcores_pr1169/cores/outrun/README.md new file mode 100644 index 0000000000000000000000000000000000000000..22f03a3d87c518d1cbfc5b8a0c43dfd0177694d1 --- /dev/null +++ b/snapshots/jotego_jtcores_pr1169/cores/outrun/README.md @@ -0,0 +1,192 @@ +# JTOUTRUN + +You can show your appreciation through +* Patreon: https://patreon.com/jotego +* Paypal: https://paypal.me/topapate +* Github: https://github.com/sponsors/jotego + +This project aims to be compatible with SEGA Super Hang-On, Out Run and derivatives. + +# Licensing + +Contact the author for special licensing needs. Otherwise follow the GPLv3 license attached. + +# Patron Acknowledgement + +Apart from the directors and supported shown in the core credits screen, +the following patrons also supported the development of JTOUTRUN: + +``` +0x157fae8 3style 8bits4ever A Hernandez +A Murder Aaron Ray Adam Foster Adam Leslie +Adam Small Adam Zorzin Adrian Labastida Alan McGrath +Alan Shurvinton Alberta Dave Alda Alesio Alden +Alec Peden Alex Baldwin Alex Mandic Alexander Facchini +Alexander Lash Alexander Upton Alfonso Clemente Alfredo Henriquez +AllDarnDavey Allen Tipper Allen Tulowitzki Allister Fiend +Alvaro Paniagua Andrea Chiavazza Andreas Micklei Andrew Boudreau +Andrew Hannan Andrew Kaczrowski Andrew Schmidt Angel Aguinaga +Angelfred Angelo Kanaris AnotherJoe Anselmo Moreno +Anthony Cheng Anthony Monaco Antoine Mariette Anton Gale +Antwon Aquijacks (Flashjacks Arend Pronk Arjan de Lang +Arkadiusz Armin Hierstetter Arnulf Eide Arthur Blough +Arthur Fung Aunaste Aurich Lawson AzathothCultist +BRCDEvg Banane Barley Cheezers Bear S +Ben Ben Cullen Ben Mininberg Ben Tiefert +Ben Toman BigRedPimp Bit2018 Bitmap Bureau +Bitmaps Retro Bliz 452 Boris Pruessmann Brad Higginbotham +Brandon Lennie Brandon Peach Brandon Smith Brandon Thomas +Brandon Yoder Brandoon Brent Fraser Brian Birkinbine +Brian Peek Brian Plummer Brian Shiver Brianna Cluck +Bruce Fontaine Bruno Freitas Bruno Meyere Bruno Silva +Bryan Evans But what Byshop303 Cameron Berkenpas +Cameron Tinker Carlos Bailleres Carlos Gruberman Casey Hamann +Cedric Vioget Cesar Sandoval Chad Page Charles +Charles Paek Chris Chris Angelini Chris Babishoff +Chris Brentano Chris Chung Chris Coughlan Chris D +Chris Davis Chris Hauk Chris Hoff Chris King +Chris Maguire Chris Mzhickteno Chris Petroni Chris S +Chris Scully Chris Sewell Chris Tuckwell Chris W Miller +Chris Waltham Chris keesler Chris smith Christophe GARDES +Chuong Dang Clayton Anderson Clinton Cronin Clinton McCarty +Cobra Clips Coldheat007 Colin Colehour Collidingforces +Cory Sizemore Cosmic Savant Craig McLaughlin Crystal Cauley +Dakken Damien D Dan Kelley Dane Biegert +Daniel Daniel . Daniel Dongil Daniel Flowers +Daniel Fowler Daniel Ibanez Daniel Page Daniel Zee +Daniel Zetterman Daniele Pellegrini Danny Garfield Darren Attwood +Darren Wootton Daryll David Dasutin Dave Bennett +Dave Douglas Dave Nice David David Drury +David Fleetwood David Frost David Osborne David Stone +DeanoC Denis Brækhus Dennis Ranker Denny Letourneau +Devon Meunier Diana2Carolina Didgeridoo Didier Malenfant +Didier Touron Dimitris Zongas Douglas Alves Dr Catjail +Dr. Octagon DrMnike Dre137 Drew Roberts +Dubesinhower Dward Venegas Ed Edgar Fuentes +EdgarsDouble Edward Mallett Emile Denichaud Enthropy +Epixjava Eren Kotan Eric Eric Gutt +Eric J Faulkes Eric Schlappi Eric Schneider Eric Sorensen +Erik F34R FROELIGER Fabio Michelin +Fabrice Odero Fabricio Fahim Rahman Federico +Fernando Irons Five Year Guy Florian Raoult Focux +Francis B Franco Catrin Frank Brevoort Frank Hoedemakers +Frank Schwab Fred Rojas GA Gareth Young +Gavin C Geddon GeorgeSpinner GigaBoots +Girth305 Glenn Percival Gluthecat GohanX +Gord Allott Gordon Coughlin Grant McNaught Greg +Greg Sargent Gregory Val Grummkol Grzegorz {NineX} +Guillermo Tunon GuitarJedi Gutxi Haitz Guy Taylor +Gwaland HFSPlay HamsoloPlays Handheld Obsession +Hans Baier Harmonica Heinz Stampfli Henry +Henry R Hermes Yan Hilton Price Hugo Pinto +Hunter Ibrahim Igor Brodecki IndieKebab +ItalianGrandma ItsBobDudes JAMES D BOOTH JOSE LUIS +JSwan Jack Sammons Jacob Hoffman Jacob Lawter +Jakob Schmid James Boone James Dingo James Ervin +James Miller James Nivin James Trautner James Wilson +Janne Heikkarainen Jason Baker Jason Dee Jason Jacobs +Javier Heredia Jayson Larose Jeff Roberts Jeremie Barnes +Jeremy Hopkins Jeremy Kelaher Jerry Langwell Jerry Suggs +Jerry Yuan Jesse Clark Jesse Rankin Jesus Garcia +Jesus Rodriguez Jim Hendricks Jim Knowler JimLahey +Jimmy Dozier Jimmy Ecker Jimmy Kim Jimmy Richards +Jindo Fox Job van Jockel Joe Dinges +Joe Giuliano Joel Albino Johan Smolinski John Dawson +John Figueroa John Fletcher John Hood John K +John T. Keen John Torn John Wilson John Woods +Johnny harvick Jon Prusik Jonah Phillips Jonathan +Jonathan Brochu Jonathan Loor Jonathan Tuttle JonathanValls +Joost Peters Jorge Jorge Crisostomo Jork Sonkinfield +Jose Gabriel Jose L Jose Perez Josep Barbie +Joseph Campo Joseph Johnston Joseph Kulinski Joseph Milazzo +Joseph Mogavero Josh Hogan Josh Yates-Walker Juan Barriga +Juan Pablo Julian Baptiste Julien Perrot Justin D'Arcangelo +Justin Rudebaugh Kai Cherry Kai Luotojoki Kaiosten +Kaya Bear Keith Duncan Keith Gordon Kellerkind +Ken B Ken Scott Kendrick Hughes Kevin Dayton +Kevin Gudgeirsson Kevin Miller Kike Alcor Kimberley Fisher +KnC Konrad Kricys Kristian. +KrzysFR Kyle Pedersen Kyo Kim L.Rapter +LFT Lakeside Lance Bohy Lars Vonhof-Hunold +Lee Grocott Lee Osborne LoBai Zen Luc JOLY +Lucian Lucius Bono Luis F Giron M Reznor +MaDDoG Mack H Madox Magnus Aspling +Magnus Kvevlander Mane Function Manksalot Manuel Astudillo +Marc Nuernberger Marcello Medini Marco Marco Cuevas +Marco Emparan Mark Baffa Mark Floyd Mark Jeffers +Mark R Mark Saunders Markonnen MarthSR +Matheus Matt Bouverie Matt Elder Matt Evans +Matt Hargett Matt Heinrich Matt McCarthy Matt Postema +Matt Simonds Matt Vulcano Matthew Compston Matthew Heyman +Matthew J Matthew Woodford Matthieu Marchione Max +Max Power MechaGG Megan Alnico Mehdi Daouas +MiSTer Retro Michael Anderson Michael Bariszlovits Michael Berger +Michael Eggers Michael Maple Michael Petri Michael Rea +Michael_DKT Mick Stone Mickaël Renou Mike Holzinger +Mike Jegenjan Mike Olson Mottzilla Murray Sneddon +Mysterious Benefactor NINE Nadir Shabazz Nailbomb +Narugawa Nathan Souris Neil St Clair NerdyNester +Nic B. Nic Kaiman Nicholas Bold Nick Daniels +Nick Delia Nick Gudauskas Nico Stamp Nicolas Hurtado +Niko NonstopXiaowei Norman Wehrle Noyman29 +Obvious Fakename Odilio FRAGATA Oliver Heilmann Omar Najera +Omega16bit OopsAllBerrys Oriez Oskar Maria +Oskar Sigvardsson OtakuAnthony Oyvind Christiansen Pablo Avila-Estevez +Parker Blackman Pascal Courtois Patrick McCarron Patrick Roman +Paul Cunningham Paul Hoggett Paul Jr Paulo M. +Paulo Nascimento Paweł Mandes PeFClic Pedro Santiago +Per Ole Peter Mehes Philip Lai Philip Lawson +Piafoman Pierre-Emmanuel Martin Pontus Nyholm Potato +Prime1984 ProfessorAnon Pumpy Crumpy R Omar Leal +Rachel Schaeffer Ralph Barbagallo Ramon Gamaliel Ramon jimenez +RandomRetro Raph_friend Raphael Melgar Raul3D +Rautz RayGun ReTr0~g!GGles Reborn 187 +RetroRGB Retro_Brewz Rex Kung Rex Willer +Richard Eng Richard Murillo Richard Simpson Richard Smith +Rick Ochoa Riyad Twair Rob Mossefin Robert Hayes +Robin Hertzberg Romain Dijoux Romier Silvera Ronald Dean +Ronan Amicel Ronin Yojimbo Roro RoryDropkick +Ruben Rufo Sanchez Rune P Russ Crandall +Ryan Ryan Clark Ryan Fig Ryan Kasper +Ryan Wilson Ryne Weiss SIDKidd64 Saiyan +Sam Hall Samuel Pizarro Samuel Warner Sang Hee +Sascha Zupanek Sayit BELET Schnookums Scott Bender +Sean Lake Sean Quinn Ser Erris Seth Wickline +Shad Uttam Shannon King Shen mue Sherwood Hachtman +Shon Garraway Sigmund68k Simon Osborne Skeletex +Sonthaya Sonthaya Sonthayaya Siha Spank Minister Stadium ARTs +SteelRush Stefan Krueger Stephen Stephen Pagenstecher +Stephen R Price Steve Ikeguchi Steve Lin Steve Skrzyniarz +Steve Tack Steven A Steven Hansen Stoneman +Stuart Morton Sunder Raj SuperBabyHix Sweaty McNasty +Synbios TM421 TMoney Taehyun Kim +Tales Dilli Terse TgrMstr The Collector +The Video TheLevelOfDetail . Thomas Attanasio Thomas Irwin +Thomas Popper Thomas Ruf Thorias Tim Inman +Timothy Bearup Timothy Latunde Tobias Dossin Tom Milner +Tony Shong Topher Campbell Travis Brown Travis Kennington +Trifle Troy Trucker 69 Two Bards +Ty B Tyson Hanes VERHILLE Arnaud VickiViperZabel +Victor Bly Victor Emmanuel Victor Fontanez Vincent Lietart +WackyDelly Wesley Lyons Weston Boldt Will Abbott +William Clemens William Roussin William Tryon XC-3730C +Xaxius Yonghan Yoshi9288 Yunus Soğukkanlı +Z QL Zach Marquette Zane Zoltan Kovacs +aguijon alejandro carlos alexcom amdrgn +angel_killah arcadebros benedict lindley blackwine +brian burney cbab chauviere benjamin circletheory +dARKrEIGn dECKARD dannahan datajerk +deathwombat derFunkenstein dzponce11 eclipse +eltee fbmg ill_deez iunno +jbrlll jim br jonathan capparelli jose luis +jp juan jesus kadybat kccheng +kernelchagi kerobaros keropi liphy +mattcurrie mattyhochs meijin3 metal +moalthan myusernamewastaken natalie ogge_leander +ohmy ojwales olivier bernhard patrick pejic +patrick woodburn raoulvp retroboi rsn8887 +slayer213 sourdille spaceduck starman_jr +thomas winfrey tim rogers tonitellezb troy coberly +turbochop3300 twilitezoner type78 vampsthevampyre +yoaarond Δlain 종규 박 +``` \ No newline at end of file diff --git a/snapshots/jotego_jtcores_pr1169/cores/pinpon/README.md b/snapshots/jotego_jtcores_pr1169/cores/pinpon/README.md new file mode 100644 index 0000000000000000000000000000000000000000..113b597e51bd515183715feb7d518a4879bacbbf --- /dev/null +++ b/snapshots/jotego_jtcores_pr1169/cores/pinpon/README.md @@ -0,0 +1,143 @@ +*This repository has been consolidated in [JTGNG](https://github.com/jtgng)* +# JTKICKER/JTYIEAR FPGA core compatible with Kicker/Yie Ar Kung-fu hardware + +You have in your hands a faithful reproduction of Kicker's hardware. We have analysed the PCB and extracted full schematics from it. We burnt EPROMs with specific code designed to test the custom chips functionality. The discoveries found during this process have been reported to the MAME team. So we can improve the experience in emulators where possible too. + +You can show your appreciation through +* [Patreon](https://patreon.com/jotego) +* [Paypal](https://paypal.me/topapate) + +# Known Issues + +It hasn't been possible to assess whether the INTSHOW custom chip outputs the current scan line or the current vertical scroll position, as these values are the same for over a third of the line. And it is at that time when when the INTSHOW value is easy to read, as it is when the NMI interrupt comes in. In practice, it doesn't seem to matter. + +The relays used in the sound signal path in some games may be for altering the filter response or for shutting off a channel. The purpose is not clear and I still have to measure the effect on the board. + +# System Comparison + +Games based on 082, 083 and 503 graphic chips. All have a pixel clock of 6.144MHz derived from a 18.432MHz oscillator. + +Game | Date | ID | Palette PROM | 085 | CPU1 | CPU2 | PSG | VLM5030 | Sch | eBay price | YT views | +----------------|------------|-----|---------------|-----|------|----------|-------|----------|-----------------------------|---------------|-------------------| +Mega Zone | 1983 | No | Only output | No | 6809 | Z80+8039 | x1 | No | Yes, only 083 |25€ |10.614(2016) | +Yie Ar Kungfu |19/Nov/1984 |GX407| Only output | No | 6809 | | 74689 | Yes | Yes, only 082,083 |15€ cart |3.6 M (2013) NES | +Shaolin's Road |22/Mar/1985 |GX477| All elements | Yes | 6809 | | 74689 | No | Yes |97.13€ |27.664(2018) | +Track'n Field |10/Oct/1983 | No | All elements | No | | | | Yes | Partial-Blurred |7 a 60€ cart |2.7 M (2015) NES | +Hyper Sports |31/May/1984 | No | All elements | Yes | | | | Yes | Same as Road Fighter |80€ |41.562(2012) | +Road Fighter |22/Nov/1984 |GX461| All elements | | 6809 | Z80 | 74689 | Yes | Yes |15 a 70€ cart |4 M (2010) NES | +Super Basketball| 1984 |GX405| All elements | Yes | 6809 | Z80 | 74689 | Yes | Yes,with labels |159€ |23.494 (2014) | +Mikie |15/Nov/1984 | No | All elements | Yes | 6809 | Z80 |2x74689| No | Yes,with labels, small |11€ cart |50.381 (2010) | +Pandora's Palace| 1984 | No | Only output | Yes | | | | No | Yes,with labels | € |14.167 (2010) | +Ping Pong | |GX555| | | | | | | Extracted by JOTEGO |60€ |8.530 (2012) NES | +Roc'n Rope | 1984 | No | Only output | No | | | 8910 | No | Yes, only 082,083 |350€PCB 50€cart|43.873 (2011) | +Circus Charlie | 1984 | | | No | 6809 | Z80 | 74689 | No | Yes, 082, 602 |350€PCB 50€cart| 107k | + +Road Fighter uses the same board as Hyper Sports, but a ROM jumper in the video board is different, changing the ROM mapping. Road Fighter does not have the VLM5030 section soldered. + +# Test Mode + +* Super Basketball test mode is enabled by holding 1P and 2P while the game boots +* The upper 3 bits for DIP switches in Road Fighter/Hyper Sports are undocumented. Bit 16 sets the flip mode in Road Fighter and a different ROM mapping in Hyper Sports + +# Acknowledgement + +This development has been possible thanks to the board donated by Brian Schinzel and the following patrons: + +``` +8bits4ever Adam Leslie Adam Small Adam Zorzin +Adrian Labastida Alan Shurvinton Alda Alesio Alden +Alex Mandic Alexander Lash Alexander Upton Alfonso Clemente +Alvaro Paniagua Andrea Bogazzi Andrea Chiavazza Andreas Micklei +Andrew Boudreau Andrew Hannan Andrew P Gibson Andrew Schmidt +Angel Aguinaga Angelfred Angelo Kanaris Anselmo Moreno +Anthony Monaco Antoine Mariette Anton Gale Antwon +Aquijacks (Flashjacks Arend Pronk Arthur Blough Arthur Fung +Aurich Lawson BRCDEvg Banane Bear S +Ben Ben Sanborn Ben Toman Bitmap Bureau +Bitmaps Retro Bliz 452 Blue Abs Boris Pruessmann +Brandon Lennie Brandon Peach Brandon Smith Brandon Thomas +Brent Fraser Brian Peek Brian Plummer Bruno M +Bryan Adams Bryan Evans C Cameron Berkenpas +Cameron Tinker Carrboroman Cesar Sandoval Charles +Chris Chris Chung Chris D Chris Hoff +Chris Maguire Chris Mzhickteno Chris Tuckwell Chris W Miller +Chris smith Christian Bailey Clinton Cronin Cobra Clips +Colin Colehour Colin Edwards Colt83 Cory Stargel +DARK WEB DANGer Dan Doyle Daniel Daniel . +Daniel Casadevall Daniel Dongil Daniel Fowler Daniel Page +Daniel Tibi Daniel Zetterman Darren Newman Darren Wootton +Daryll David Dasutin Dave Douglas Dave Test +David Drury David Filskov David Fleetwood David Jones +Denis Brækhus Denny Letourneau Diana Carolina Didgeridoo +Didier Touron Dimitris Zongas Dr Catjail Dr. Octagon +DrMnike Dre137 Edward Mallett Eren Kotan +Eric Eric Gutt Eric J Faulkes Eric Walklet +Fabio Michelin Federico Five Year Guy Florian Raoult +Frank Schwab Fred Rojas Geddon GeorgeSpinner +Gluthecat GohanX Goolio Grant McNaught +Greg Greg Sargent Gregory Val HFSPlay +Handheld Obsession Henry Henry R Hentai Joe +Hugo Pinto ItsBobDudes JOSE LUIS JR +Jack Sammons Jacob Hoffman Jacob Lawter James Dingo +James Durden James Kilgore James Wilson Jason Baker +Jeff Roberts Jeremy Hasse Jerry Suggs Jesse Clark +Jim Knowler JimLahey Jimmy Dozier Jimmy Richards +Jockel Joel Albino Johan Smolinski John Figueroa +John Fletcher John Hood John Silva John T. Keen +John Wilson Johnny harvick Jonah Phillips Jonathan +Jonathan Brochu Jonathan Loor Jonathan Tuttle JonathanValls +Joost Peters Jootec from Jorge Jork Sonkinfield +Jose L Jose Lopez Josep Barbie Joseph Kulinski +Joseph Milazzo Joseph Mogavero Josh Emery Josh Mayer +Josh Yates-Walker Josiah Wilson Julian Baptiste Justin D'Arcangelo +Kai Cherry Kai Luotojoki Keith Gordon Kem Yos +Ken Scott Kevin Dayton Kevin Gudgeirsson KnC +Kricys KrzysFR Kyle Pedersen L.Rapter +Lakeside Laurent Cooper Lee Grocott Lee Osborne +Luis F Giron M Reznor MaDDoG Mack H +Madox Magnus Kvevlander Manuel Astudillo Marco Emparan +Mark Baffa Mark DeRidder MarthSR Martin Ansin +Matt Elder Matt Evans Matt Hargett Matt Heinrich +Matt Lichtenberg Matt McCarthy Matt Postema Matthew Pollard +Matthew Woodford MechaGG MiSTer Retro Michael Anderson +Michael Bariszlovits Michael Berger Michael C Michael Eggers +Michael Ferguson Michael Rea Michael_DKT Mike Holzinger +Mike Jegenjan Mike Olson Mike Parks Mottzilla +My War Nailbomb Narugawa Neil St Clair +NerdyNester Nic Kaiman Nick Delia Nick Gudauskas +Nico Stamp Nicolas Hurtado Niko NonstopXiaowei +Norman Wehrle Obvious Fakename OopsAllBerrys Or even +Oriez Oskar Sigvardsson PANICKED SCREECHING. Pascal Courtois +Patrick Roman Paul Paul Cunningham Paul Hoggett +Paulo M. Paweł Mandes PeFClic Pedro Santiago +Per Ole Philip Lai Philip Lawson Piafoman +Pierre-Emmanuel Martin Pontus Nyholm Rachael Netz Rachel Schaeffer +Ramon Gamaliel RandomRetro Raphael Melgar Raul3D +RayGun RetroRGB Rex Kung Rex Willer +Richard Eng Richard Murillo Richard Simpson Rick Ochoa +Riyad Twair Robert Daniel Robert Hayes Romain Dijoux +Ronald Dean Ronan Amicel Ruben Ryan +Ryan O'Malley SIDKidd64 Sam Hall Samuel Warner +Sang Hee Sascha Zupanek Schnookums Ser Erris +Shannon King Simon Osborne Spank Minister SteelRush +Stefan Krueger Stephen R Price Steve Ikeguchi Steve Lin +Steve Skrzyniarz Steve Tack Steven Hansen Steven Yedwab +Stuart Morton Sunder Raj SuperBabyHix Synbios +Syrotuck Taehyun Kim Taiki Hosoda Tales Dilli +Terse The Collector The Video TheLevelOfDetail . +Thomas Attanasio Thomas Irwin Thorias Timothy Bearup +Tobias Dossin Tom Milner Topher Campbell Travis Brown +Trifle Turboman UK Ty B VickiViperZabel +Victor Bly Victor Fontanez Will Abbott William Clemens +William Tryon Yunus Soğukkanlı Zach Marquette Zoltan Kovacs +albertprime alejandro carlos angel_killah arcadebros +benedict lindley blackwine brian burney cbab +chauviere benjamin circletheory datajerk deathr0w +deathwombat derFunkenstein gunmakuma jbrlll +jim br joshewah777 kamel rasennadja kccheng +kernelchagi keropi liphy meng po +metal natalie nonamebear pacoarcade +patrick pejic qzxcvbn retroPREZ retrod00d +rsn8887 slayer213 taal.M tonitellezb +troy coberly turbochop3300 type78 yoaarond +``` diff --git a/snapshots/jotego_jtcores_pr1169/cores/twin16/README.md b/snapshots/jotego_jtcores_pr1169/cores/twin16/README.md new file mode 100644 index 0000000000000000000000000000000000000000..58c0f6bd3c9dca0311811beaf0c3d76bc8f94818 --- /dev/null +++ b/snapshots/jotego_jtcores_pr1169/cores/twin16/README.md @@ -0,0 +1,44 @@ +# JTTWIN16 FPGA core Compatible with Konami's Twin16 hardware + +By Jose Tejada (@topapate) + +You can show your appreciation through +* [Patreon](https://patreon.com/jotego) +* [Paypal](https://paypal.me/topapate) +* [Github](https://github.com/sponsors/jotego) + +Project source code hosted at http://www.github.com/jotego/jtcores +License: GPL3, you are obligued to publish your code if you use mine + + +Yes, you always wanted to have an arcade board at home. First you couldn't get it because your parents somehow did not understand you. Then you grow up and your wife doesn't understand you either. Don't worry, JT cores are here to the rescue. + +I hope you will have as much fun with this project as I had while working on it! + +# Hardware Information + +This core is based on the official schematics for this system and the incredible reverse engineering work done by Skutis on them. It is also based on our own lab measurements of a working board. + +# Graphic Chips + +This system seems to implement many of the ideas seen in the TMNT/Aliens sprite chipset. However, instead of using two pairs of chips, one for sprites and one for tilemaps, this early implementation uses many more custom and discrete chips. + +All the information on these chips is known thanks to Skutis work. + +- Tilemap chip 0077'79 holds the scroll register values, regardless of the lower bits connecting directly to 0077'81 through external registers +- 0077'79 has a memory mapper feature so AB[12:11] will be used to drive the external RAM depending upon configuration +- Objects use two frame buffers, contrary to the line buffers seen in TMNT/Aliens +- Object chip 0077'83 parses object data during DMA, by checking only the priority byte +- Object data takes 8kB for 512 sprites x 16 bytes. Then gets parsed down to 2kB + +Comparing this chipset with TMNT/Aliens: + +- There is no hardware zoom for sprites +- There is no row/column scroll for tile maps +- There is no H/V flip for the fixed layer + +Graphic bitmaps are stored both in ROM and RAM chips. The subsidiary CPU is in charge of filling the tile RAMs. + +# Credits + +Special thanks to Skutis for all his open source research and for lending us the board. diff --git a/snapshots/jotego_jtcores_pr1169/doc/audio.md b/snapshots/jotego_jtcores_pr1169/doc/audio.md new file mode 100644 index 0000000000000000000000000000000000000000..41c5be907c6f5a06627b13c3a2fea780234505c9 --- /dev/null +++ b/snapshots/jotego_jtcores_pr1169/doc/audio.md @@ -0,0 +1,14 @@ +# Output Specifications for Audio chips + +Chip | Output (Vpp) | Rout (kOhm) | Remarks +-------------|--------------|--------------|------------- +VLM5030 | | 55 | preliminary measurements for Rout +AY-3-8910 | | | +YM3012 | | | +YM3014 | 0.5 | 81.25 | Runit=32.5kOhm one chip measured +sn76489 | | | +MSM5205 | | | +oki6295 | | | +YM2203 (PSG) | | | + +For YM3014, the output impedance depends on the exponent setting and can vary between 2 and 3.15 times Runit \ No newline at end of file diff --git a/snapshots/jotego_jtcores_pr1169/doc/precps.txt b/snapshots/jotego_jtcores_pr1169/doc/precps.txt new file mode 100644 index 0000000000000000000000000000000000000000..9b011ecdc92e94e45045fc511bdb0224fe49dde5 --- /dev/null +++ b/snapshots/jotego_jtcores_pr1169/doc/precps.txt @@ -0,0 +1,24 @@ +1942, Z80, AY, 1984 +Higemaru, Z80, AY, 1984 +Vulgus, Z80, AY, 1984 +Son Son, 6809, AY, 1984 +Exed Exes, Z80, AY, 1985 +GnG, 6809, FM, 1985 +Commando, Z80, FM, 1985 +Gun Smoke, Z80, FM, 1985 +Side Arms, Z80, FM, 1986 +Speed Rumbler, 6809, FM, 1986 +Black Tiger, Z80, FM, 1987 +1943, Z80, FM, 1987 +Avengers, Z80, FM+MSM5205, 1987 +Legendary Wings,Z80, FM+MSM5205, 1986 +Trojan, Z80, FM+MSM5205, 1986 +Section Z, Z80, FM+MSM5205, 1985 +Bionic Commando,68000, FM, 1987 +F-1 Dream, 68000, FM, 1988 +Last Duel, 68000, FM, 1988 +LED Storm, 68000, FM+MSM6295, 1989 +Street Fighter, 68000, YM2151+6205,1987 +Tiger Road, 68000, FM, 1987 + + diff --git a/snapshots/jotego_jtcores_pr1169/doc/rgb.ods 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0000000000000000000000000000000000000000..82e60d4afadf133cede3b84b2771c301a4f45c31 --- /dev/null +++ b/snapshots/jotego_jtcores_pr1242/cores/xmen/doc/lab/xmen/obj3.png @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:cfa8dab13176284f51bb23fe7b6b66f163baa69e90f6db720841f64a00a41e1f +size 93053 diff --git a/snapshots/jotego_jtcores_pr1242/modules/HUC6280/cfg/files.yaml b/snapshots/jotego_jtcores_pr1242/modules/HUC6280/cfg/files.yaml new file mode 100644 index 0000000000000000000000000000000000000000..aed7734e8534a1a46e96ed0983fdefb96209e438 --- /dev/null +++ b/snapshots/jotego_jtcores_pr1242/modules/HUC6280/cfg/files.yaml @@ -0,0 +1,13 @@ +HUC6280: + - unless: [VERILATOR] + get: + - HUC6280.vhd + - HUC6280_CPU.vhd + - HUC6280_PKG.vhd + - HUC6280_MC.vhd + - HUC6280_ALU.vhd + - HUC6280_AG.vhd + - AddSubBCD.vhd + - when: [VERILATOR] + get: + - HUC6280.v diff --git a/snapshots/jotego_jtcores_pr1242/modules/HUC6280/hdl/AddSubBCD.vhd b/snapshots/jotego_jtcores_pr1242/modules/HUC6280/hdl/AddSubBCD.vhd new file mode 100644 index 0000000000000000000000000000000000000000..c5cd7d186460d15027a5a3dc6632129698058a76 --- /dev/null +++ b/snapshots/jotego_jtcores_pr1242/modules/HUC6280/hdl/AddSubBCD.vhd @@ -0,0 +1,193 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library STD; +use IEEE.NUMERIC_STD.ALL; +library work; + +entity bit_adder is + port( + A : in std_logic; + B : in std_logic; + CI : in std_logic; + S : out std_logic; + CO : out std_logic + ); +end bit_adder; + +architecture rtl of bit_adder is + +begin + + S <= (not A and not B and CI) or + (not A and B and not CI) or + ( A and not B and not CI) or + ( A and B and CI); + + CO <= (not A and B and CI) or + ( A and not B and CI) or + ( A and B and not CI) or + ( A and B and CI); + +end rtl; + + + +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library STD; +use IEEE.NUMERIC_STD.ALL; +library work; + +entity adder4 is + port( + A : in std_logic_vector(3 downto 0); + B : in std_logic_vector(3 downto 0); + CI : in std_logic; + S : out std_logic_vector(3 downto 0); + CO : out std_logic + ); +end adder4; + +architecture rtl of adder4 is + + component bit_adder is + port( + A : in std_logic; + B : in std_logic; + CI : in std_logic; + S : out std_logic; + CO : out std_logic + ); + end component; + + signal CO0, CO1, CO2 : std_logic; + +begin + + b_add0: bit_adder port map (A(0), B(0), CI, S(0), CO0); + b_add1: bit_adder port map (A(1), B(1), CO0, S(1), CO1); + b_add2: bit_adder port map (A(2), B(2), CO1, S(2), CO2); + b_add3: bit_adder port map (A(3), B(3), CO2, S(3), CO); + +end rtl; + + +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library STD; +use IEEE.NUMERIC_STD.ALL; +library work; + +entity BCDAdder is + port( + A : in std_logic_vector(3 downto 0); + B : in std_logic_vector(3 downto 0); + CI : in std_logic; + + S : out std_logic_vector(3 downto 0); + CO : out std_logic; + VO : out std_logic; + + ADD : in std_logic; + BCD : in std_logic + ); +end BCDAdder; + +architecture rtl of BCDAdder is + + signal B2 : std_logic_vector(3 downto 0); + signal BIN_S : std_logic_vector(3 downto 0); + signal BIN_CO : std_logic; + signal BCD_B : std_logic_vector(3 downto 0); + signal BCD_CO : std_logic; + + signal CI2 : std_logic; + +begin + + B2 <= B xor (3 downto 0 => not ADD); + + bin_adder : entity work.adder4 + port map( + A => A, + B => B2, + CI => CI, + S => BIN_S, + CO => BIN_CO + ); + + BCD_CO <= (BIN_S(3) and BIN_S(2)) or (BIN_S(3) and BIN_S(1)) or (BIN_CO xor not ADD); + BCD_B <= not ADD & ((BCD_CO and BCD) xor not ADD) & ((BCD_CO and BCD) xor not ADD) & not ADD; + + CI2 <= not ADD; + bcd_corr_adder : entity work.adder4 + port map( + A => BIN_S, + B => BCD_B, + CI => CI2, + S => S + ); + + CO <= BIN_CO when BCD = '0' else BCD_CO xor not ADD; + VO <= (not (A(3) xor B2(3))) and (A(3) xor BIN_S(3)); + +end rtl; + + +library IEEE; +use IEEE.std_logic_1164.all; +use ieee.numeric_std.all; +library work; + +entity AddSubBCD is + port( + A : in std_logic_vector(7 downto 0); + B : in std_logic_vector(7 downto 0); + CI : in std_logic; + ADD : in std_logic; + BCD : in std_logic; + S : out std_logic_vector(7 downto 0); + CO : out std_logic; + VO : out std_logic + ); +end AddSubBCD; + +architecture rtl of AddSubBCD is + + signal VO1 : std_logic; + signal CO0, CO1 : std_logic; + +begin + + add0 : entity work.BCDAdder + port map ( + A => A(3 downto 0), + B => B(3 downto 0), + CI => CI, + + S => S(3 downto 0), + CO => CO0, + + ADD => ADD, + BCD => BCD + ); + + add1 : entity work.BCDAdder + port map ( + A => A(7 downto 4), + B => B(7 downto 4), + CI => CO0, + + S => S(7 downto 4), + CO => CO1, + VO => VO1, + + ADD => ADD, + BCD => BCD + ); + + + VO <= VO1; + CO <= CO1; + +end rtl; \ No newline at end of file diff --git a/snapshots/jotego_jtcores_pr1242/modules/HUC6280/hdl/HUC6280.v b/snapshots/jotego_jtcores_pr1242/modules/HUC6280/hdl/HUC6280.v new file mode 100644 index 0000000000000000000000000000000000000000..2103609a5c6221b86352d434ffbfe1b223407b34 --- /dev/null +++ b/snapshots/jotego_jtcores_pr1242/modules/HUC6280/hdl/HUC6280.v @@ -0,0 +1,10662 @@ +/* verilator lint_off UNOPTFLAT*/ +module bit_adder + (input a, + input b, + input ci, + output s, + output co); + wire n1844_o; + wire n1845_o; + wire n1846_o; + wire n1847_o; + wire n1848_o; + wire n1849_o; + wire n1850_o; + wire n1851_o; + wire n1852_o; + wire n1853_o; + wire n1854_o; + wire n1855_o; + wire n1856_o; + wire n1857_o; + wire n1858_o; + wire n1859_o; + wire n1860_o; + wire n1861_o; + wire n1862_o; + wire n1863_o; + wire n1864_o; + wire n1865_o; + wire n1866_o; + wire n1867_o; + wire n1868_o; + wire n1869_o; + wire n1870_o; + wire n1871_o; + wire n1872_o; + wire n1873_o; + wire n1874_o; + assign s = n1860_o; + assign co = n1874_o; + /* AddSubBCD.vhd:21:15 */ + assign n1844_o = ~a; + /* AddSubBCD.vhd:21:25 */ + assign n1845_o = ~b; + /* AddSubBCD.vhd:21:21 */ + assign n1846_o = n1844_o & n1845_o; + /* AddSubBCD.vhd:21:31 */ + assign n1847_o = n1846_o & ci; + /* AddSubBCD.vhd:22:20 */ + assign n1848_o = ~a; + /* AddSubBCD.vhd:22:26 */ + assign n1849_o = n1848_o & b; + /* AddSubBCD.vhd:22:40 */ + assign n1850_o = ~ci; + /* AddSubBCD.vhd:22:36 */ + assign n1851_o = n1849_o & n1850_o; + /* AddSubBCD.vhd:21:43 */ + assign n1852_o = n1847_o | n1851_o; + /* AddSubBCD.vhd:23:30 */ + assign n1853_o = ~b; + /* AddSubBCD.vhd:23:26 */ + assign n1854_o = a & n1853_o; + /* AddSubBCD.vhd:23:40 */ + assign n1855_o = ~ci; + /* AddSubBCD.vhd:23:36 */ + assign n1856_o = n1854_o & n1855_o; + /* AddSubBCD.vhd:22:48 */ + assign n1857_o = n1852_o | n1856_o; + /* AddSubBCD.vhd:24:26 */ + assign n1858_o = a & b; + /* AddSubBCD.vhd:24:36 */ + assign n1859_o = n1858_o & ci; + /* AddSubBCD.vhd:23:48 */ + assign n1860_o = n1857_o | n1859_o; + /* AddSubBCD.vhd:26:16 */ + assign n1861_o = ~a; + /* AddSubBCD.vhd:26:22 */ + assign n1862_o = n1861_o & b; + /* AddSubBCD.vhd:26:32 */ + assign n1863_o = n1862_o & ci; + /* AddSubBCD.vhd:27:36 */ + assign n1864_o = ~b; + /* AddSubBCD.vhd:27:32 */ + assign n1865_o = a & n1864_o; + /* AddSubBCD.vhd:27:42 */ + assign n1866_o = n1865_o & ci; + /* AddSubBCD.vhd:26:44 */ + assign n1867_o = n1863_o | n1866_o; + /* AddSubBCD.vhd:28:32 */ + assign n1868_o = a & b; + /* AddSubBCD.vhd:28:46 */ + assign n1869_o = ~ci; + /* AddSubBCD.vhd:28:42 */ + assign n1870_o = n1868_o & n1869_o; + /* AddSubBCD.vhd:27:54 */ + assign n1871_o = n1867_o | n1870_o; + /* AddSubBCD.vhd:29:32 */ + assign n1872_o = a & b; + /* AddSubBCD.vhd:29:42 */ + assign n1873_o = n1872_o & ci; + /* AddSubBCD.vhd:28:54 */ + assign n1874_o = n1871_o | n1873_o; +endmodule + +module adder4 + (input [3:0] a, + input [3:0] b, + input ci, + output [3:0] s, + output co); + wire co0; + wire co1; + wire co2; + wire n1809_o; + wire n1810_o; + wire b_add0_n1811; + wire b_add0_n1812; + wire b_add0_s; + wire b_add0_co; + wire n1817_o; + wire n1818_o; + wire b_add1_n1819; + wire b_add1_n1820; + wire b_add1_s; + wire b_add1_co; + wire n1825_o; + wire n1826_o; + wire b_add2_n1827; + wire b_add2_n1828; + wire b_add2_s; + wire b_add2_co; + wire n1833_o; + wire n1834_o; + wire b_add3_n1835; + wire b_add3_n1836; + wire b_add3_s; + wire b_add3_co; + wire [3:0] n1841_o; + assign s = n1841_o; + assign co = b_add3_n1836; + /* AddSubBCD.vhd:63:16 */ + assign co0 = b_add0_n1812; // (signal) + /* AddSubBCD.vhd:63:21 */ + assign co1 = b_add1_n1820; // (signal) + /* AddSubBCD.vhd:63:26 */ + assign co2 = b_add2_n1828; // (signal) + /* AddSubBCD.vhd:67:38 */ + assign n1809_o = a[0]; + /* AddSubBCD.vhd:67:44 */ + assign n1810_o = b[0]; + /* AddSubBCD.vhd:67:54 */ + assign b_add0_n1811 = b_add0_s; // (signal) + /* AddSubBCD.vhd:67:60 */ + assign b_add0_n1812 = b_add0_co; // (signal) + /* AddSubBCD.vhd:67:9 */ + bit_adder b_add0 ( + .a(n1809_o), + .b(n1810_o), + .ci(ci), + .s(b_add0_s), + .co(b_add0_co)); + /* AddSubBCD.vhd:68:38 */ + assign n1817_o = a[1]; + /* AddSubBCD.vhd:68:44 */ + assign n1818_o = b[1]; + /* AddSubBCD.vhd:68:54 */ + assign b_add1_n1819 = b_add1_s; // (signal) + /* AddSubBCD.vhd:68:60 */ + assign b_add1_n1820 = b_add1_co; // (signal) + /* AddSubBCD.vhd:68:9 */ + bit_adder b_add1 ( + .a(n1817_o), + .b(n1818_o), + .ci(co0), + .s(b_add1_s), + .co(b_add1_co)); + /* AddSubBCD.vhd:69:38 */ + assign n1825_o = a[2]; + /* AddSubBCD.vhd:69:44 */ + assign n1826_o = b[2]; + /* AddSubBCD.vhd:69:54 */ + assign b_add2_n1827 = b_add2_s; // (signal) + /* AddSubBCD.vhd:69:60 */ + assign b_add2_n1828 = b_add2_co; // (signal) + /* AddSubBCD.vhd:69:9 */ + bit_adder b_add2 ( + .a(n1825_o), + .b(n1826_o), + .ci(co1), + .s(b_add2_s), + .co(b_add2_co)); + /* AddSubBCD.vhd:70:38 */ + assign n1833_o = a[3]; + /* AddSubBCD.vhd:70:44 */ + assign n1834_o = b[3]; + /* AddSubBCD.vhd:70:54 */ + assign b_add3_n1835 = b_add3_s; // (signal) + /* AddSubBCD.vhd:70:60 */ + assign b_add3_n1836 = b_add3_co; // (signal) + /* AddSubBCD.vhd:70:9 */ + bit_adder b_add3 ( + .a(n1833_o), + .b(n1834_o), + .ci(co2), + .s(b_add3_s), + .co(b_add3_co)); + assign n1841_o = {b_add3_n1835, b_add2_n1827, b_add1_n1819, b_add0_n1811}; +endmodule + +module bcdadder + (input [3:0] a, + input [3:0] b, + input ci, + input add, + input bcd, + output [3:0] s, + output co, + output vo); + wire [3:0] b2; + wire [3:0] bin_s; + wire bin_co; + wire [3:0] bcd_b; + wire bcd_co; + wire ci2; + wire n1764_o; + wire n1765_o; + wire n1766_o; + wire n1767_o; + wire [3:0] n1768_o; + wire [3:0] n1769_o; + wire [3:0] bin_adder_s; + wire bin_adder_co; + wire n1772_o; + wire n1773_o; + wire n1774_o; + wire n1775_o; + wire n1776_o; + wire n1777_o; + wire n1778_o; + wire n1779_o; + wire n1780_o; + wire n1781_o; + wire n1782_o; + wire n1783_o; + wire n1784_o; + wire n1785_o; + wire [1:0] n1786_o; + wire n1787_o; + wire n1788_o; + wire n1789_o; + wire [2:0] n1790_o; + wire n1791_o; + wire [3:0] n1792_o; + wire n1793_o; + wire [3:0] bcd_corr_adder_s; + wire bcd_corr_adder_co; + wire n1795_o; + wire n1796_o; + wire n1797_o; + wire n1798_o; + wire n1799_o; + wire n1800_o; + wire n1801_o; + wire n1802_o; + wire n1803_o; + wire n1804_o; + wire n1805_o; + wire n1806_o; + assign s = bcd_corr_adder_s; + assign co = n1796_o; + assign vo = n1806_o; + /* AddSubBCD.vhd:98:16 */ + assign b2 = n1769_o; // (signal) + /* AddSubBCD.vhd:99:16 */ + assign bin_s = bin_adder_s; // (signal) + /* AddSubBCD.vhd:100:16 */ + assign bin_co = bin_adder_co; // (signal) + /* AddSubBCD.vhd:101:16 */ + assign bcd_b = n1792_o; // (signal) + /* AddSubBCD.vhd:102:16 */ + assign bcd_co = n1781_o; // (signal) + /* AddSubBCD.vhd:104:16 */ + assign ci2 = n1793_o; // (signal) + /* AddSubBCD.vhd:108:36 */ + assign n1764_o = ~add; + /* AddSubBCD.vhd:108:36 */ + assign n1765_o = ~add; + /* AddSubBCD.vhd:108:36 */ + assign n1766_o = ~add; + /* AddSubBCD.vhd:108:36 */ + assign n1767_o = ~add; + assign n1768_o = {n1767_o, n1766_o, n1765_o, n1764_o}; + /* AddSubBCD.vhd:108:17 */ + assign n1769_o = b ^ n1768_o; + /* AddSubBCD.vhd:110:9 */ + adder4 bin_adder ( + .a(a), + .b(b2), + .ci(ci), + .s(bin_adder_s), + .co(bin_adder_co)); + /* AddSubBCD.vhd:119:25 */ + assign n1772_o = bin_s[3]; + /* AddSubBCD.vhd:119:38 */ + assign n1773_o = bin_s[2]; + /* AddSubBCD.vhd:119:29 */ + assign n1774_o = n1772_o & n1773_o; + /* AddSubBCD.vhd:119:52 */ + assign n1775_o = bin_s[3]; + /* AddSubBCD.vhd:119:65 */ + assign n1776_o = bin_s[1]; + /* AddSubBCD.vhd:119:56 */ + assign n1777_o = n1775_o & n1776_o; + /* AddSubBCD.vhd:119:43 */ + assign n1778_o = n1774_o | n1777_o; + /* AddSubBCD.vhd:119:85 */ + assign n1779_o = ~add; + /* AddSubBCD.vhd:119:81 */ + assign n1780_o = bin_co ^ n1779_o; + /* AddSubBCD.vhd:119:70 */ + assign n1781_o = n1778_o | n1780_o; + /* AddSubBCD.vhd:120:18 */ + assign n1782_o = ~add; + /* AddSubBCD.vhd:120:37 */ + assign n1783_o = bcd_co & bcd; + /* AddSubBCD.vhd:120:50 */ + assign n1784_o = ~add; + /* AddSubBCD.vhd:120:46 */ + assign n1785_o = n1783_o ^ n1784_o; + /* AddSubBCD.vhd:120:26 */ + assign n1786_o = {n1782_o, n1785_o}; + /* AddSubBCD.vhd:120:70 */ + assign n1787_o = bcd_co & bcd; + /* AddSubBCD.vhd:120:83 */ + assign n1788_o = ~add; + /* AddSubBCD.vhd:120:79 */ + assign n1789_o = n1787_o ^ n1788_o; + /* AddSubBCD.vhd:120:59 */ + assign n1790_o = {n1786_o, n1789_o}; + /* AddSubBCD.vhd:120:94 */ + assign n1791_o = ~add; + /* AddSubBCD.vhd:120:92 */ + assign n1792_o = {n1790_o, n1791_o}; + /* AddSubBCD.vhd:122:16 */ + assign n1793_o = ~add; + /* AddSubBCD.vhd:123:9 */ + adder4 bcd_corr_adder ( + .a(bin_s), + .b(bcd_b), + .ci(ci2), + .s(bcd_corr_adder_s), + .co()); + /* AddSubBCD.vhd:131:31 */ + assign n1795_o = ~bcd; + /* AddSubBCD.vhd:131:22 */ + assign n1796_o = n1795_o ? bin_co : n1798_o; + /* AddSubBCD.vhd:131:53 */ + assign n1797_o = ~add; + /* AddSubBCD.vhd:131:49 */ + assign n1798_o = bcd_co ^ n1797_o; + /* AddSubBCD.vhd:132:22 */ + assign n1799_o = a[3]; + /* AddSubBCD.vhd:132:32 */ + assign n1800_o = b2[3]; + /* AddSubBCD.vhd:132:26 */ + assign n1801_o = n1799_o ^ n1800_o; + /* AddSubBCD.vhd:132:16 */ + assign n1802_o = ~n1801_o; + /* AddSubBCD.vhd:132:44 */ + assign n1803_o = a[3]; + /* AddSubBCD.vhd:132:57 */ + assign n1804_o = bin_s[3]; + /* AddSubBCD.vhd:132:48 */ + assign n1805_o = n1803_o ^ n1804_o; + /* AddSubBCD.vhd:132:38 */ + assign n1806_o = n1802_o & n1805_o; +endmodule + +module addsubbcd + (input [7:0] a, + input [7:0] b, + input ci, + input add, + input bcd, + output [7:0] s, + output co, + output vo); + wire vo1; + wire co0; + wire co1; + wire [3:0] add0_s; + wire add0_co; + wire add0_vo; + wire [3:0] n1751_o; + wire [3:0] n1752_o; + wire [3:0] add1_s; + wire add1_co; + wire add1_vo; + wire [3:0] n1755_o; + wire [3:0] n1756_o; + wire [7:0] n1760_o; + assign s = n1760_o; + assign co = co1; + assign vo = vo1; + /* AddSubBCD.vhd:157:16 */ + assign vo1 = add1_vo; // (signal) + /* AddSubBCD.vhd:158:16 */ + assign co0 = add0_co; // (signal) + /* AddSubBCD.vhd:158:21 */ + assign co1 = add1_co; // (signal) + /* AddSubBCD.vhd:162:9 */ + bcdadder add0 ( + .a(n1751_o), + .b(n1752_o), + .ci(ci), + .add(add), + .bcd(bcd), + .s(add0_s), + .co(add0_co), + .vo()); + /* AddSubBCD.vhd:164:23 */ + assign n1751_o = a[3:0]; + /* AddSubBCD.vhd:165:23 */ + assign n1752_o = b[3:0]; + /* AddSubBCD.vhd:175:9 */ + bcdadder add1 ( + .a(n1755_o), + .b(n1756_o), + .ci(co0), + .add(add), + .bcd(bcd), + .s(add1_s), + .co(add1_co), + .vo(add1_vo)); + /* AddSubBCD.vhd:177:23 */ + assign n1755_o = a[7:4]; + /* AddSubBCD.vhd:178:23 */ + assign n1756_o = b[7:4]; + assign n1760_o = {add1_s, add0_s}; +endmodule + +module huc6280_ag + (input clk, + input rst_n, + input ce, + input [2:0] pc_ctrl, + input [5:0] addr_ctrl, + input got_int, + input [7:0] di, + input [7:0] x, + input [7:0] y, + input [7:0] dr, + output [15:0] pc, + output [15:0] aa); + wire [7:0] aal; + wire [7:0] aah; + wire savedcarry; + wire [8:0] newaal; + wire [7:0] newaah; + wire [15:0] pcr; + wire [15:0] nextpc; + wire [15:0] newpcwithoffset; + wire n1612_o; + wire n1613_o; + wire n1614_o; + wire n1615_o; + wire n1616_o; + wire n1617_o; + wire n1618_o; + wire n1619_o; + wire [3:0] n1620_o; + wire [3:0] n1621_o; + wire [7:0] n1622_o; + wire [15:0] n1623_o; + wire [15:0] n1624_o; + wire n1628_o; + wire n1629_o; + wire [15:0] n1631_o; + wire [15:0] n1632_o; + wire n1634_o; + wire [7:0] n1635_o; + wire [15:0] n1636_o; + wire n1638_o; + wire [7:0] n1639_o; + wire [15:0] n1640_o; + wire n1642_o; + wire n1644_o; + wire [15:0] n1645_o; + wire n1647_o; + wire [5:0] n1648_o; + reg [15:0] n1649_o; + wire n1650_o; + wire [2:0] n1659_o; + wire [8:0] n1661_o; + wire n1663_o; + wire [8:0] n1665_o; + wire n1667_o; + wire [8:0] n1669_o; + wire [8:0] n1671_o; + wire n1673_o; + wire [8:0] n1675_o; + wire [8:0] n1677_o; + wire [8:0] n1678_o; + wire n1680_o; + wire [8:0] n1682_o; + wire [8:0] n1684_o; + wire [8:0] n1685_o; + wire n1687_o; + wire [8:0] n1689_o; + wire n1691_o; + wire [8:0] n1693_o; + wire [8:0] n1695_o; + wire [8:0] n1696_o; + wire n1698_o; + wire [8:0] n1700_o; + wire [6:0] n1701_o; + reg [8:0] n1702_o; + wire [2:0] n1703_o; + wire n1705_o; + wire n1707_o; + wire [7:0] n1709_o; + wire n1711_o; + wire [7:0] n1713_o; + wire [7:0] n1714_o; + wire n1716_o; + wire [3:0] n1717_o; + reg [7:0] n1718_o; + wire n1722_o; + wire [7:0] n1724_o; + wire n1725_o; + wire [15:0] n1739_o; + wire [7:0] n1740_o; + reg [7:0] n1741_q; + wire [7:0] n1742_o; + reg [7:0] n1743_q; + wire n1744_o; + reg n1745_q; + wire [15:0] n1746_o; + reg [15:0] n1747_q; + assign pc = pcr; + assign aa = n1739_o; + /* HUC6280_AG.vhd:26:16 */ + assign aal = n1741_q; // (signal) + /* HUC6280_AG.vhd:26:21 */ + assign aah = n1743_q; // (signal) + /* HUC6280_AG.vhd:27:16 */ + assign savedcarry = n1745_q; // (signal) + /* HUC6280_AG.vhd:29:16 */ + assign newaal = n1702_o; // (signal) + /* HUC6280_AG.vhd:117:46 */ + assign newaah = n1718_o; // (signal) + /* HUC6280_AG.vhd:32:16 */ + assign pcr = n1747_q; // (signal) + /* HUC6280_AG.vhd:33:16 */ + assign nextpc = n1649_o; // (signal) + /* HUC6280_AG.vhd:33:24 */ + assign newpcwithoffset = n1624_o; // (signal) + /* HUC6280_AG.vhd:37:88 */ + assign n1612_o = aal[7]; + /* HUC6280_AG.vhd:37:88 */ + assign n1613_o = aal[7]; + /* HUC6280_AG.vhd:37:88 */ + assign n1614_o = aal[7]; + /* HUC6280_AG.vhd:37:88 */ + assign n1615_o = aal[7]; + /* HUC6280_AG.vhd:37:88 */ + assign n1616_o = aal[7]; + /* HUC6280_AG.vhd:37:88 */ + assign n1617_o = aal[7]; + /* HUC6280_AG.vhd:37:88 */ + assign n1618_o = aal[7]; + /* HUC6280_AG.vhd:37:88 */ + assign n1619_o = aal[7]; + assign n1620_o = {n1619_o, n1618_o, n1617_o, n1616_o}; + assign n1621_o = {n1615_o, n1614_o, n1613_o, n1612_o}; + assign n1622_o = {n1620_o, n1621_o}; + /* HUC6280_AG.vhd:37:93 */ + assign n1623_o = {n1622_o, aal}; + /* HUC6280_AG.vhd:37:59 */ + assign n1624_o = pcr + n1623_o; + /* HUC6280_AG.vhd:42:25 */ + assign n1628_o = pc_ctrl == 3'b000; + /* HUC6280_AG.vhd:45:44 */ + assign n1629_o = ~got_int; + /* HUC6280_AG.vhd:46:82 */ + assign n1631_o = pcr + 16'b0000000000000001; + /* HUC6280_AG.vhd:45:33 */ + assign n1632_o = n1629_o ? n1631_o : pcr; + /* HUC6280_AG.vhd:44:25 */ + assign n1634_o = pc_ctrl == 3'b001; + /* HUC6280_AG.vhd:51:46 */ + assign n1635_o = pcr[15:8]; + /* HUC6280_AG.vhd:51:60 */ + assign n1636_o = {n1635_o, di}; + /* HUC6280_AG.vhd:50:25 */ + assign n1638_o = pc_ctrl == 3'b010; + /* HUC6280_AG.vhd:53:51 */ + assign n1639_o = pcr[7:0]; + /* HUC6280_AG.vhd:53:46 */ + assign n1640_o = {di, n1639_o}; + /* HUC6280_AG.vhd:52:25 */ + assign n1642_o = pc_ctrl == 3'b011; + /* HUC6280_AG.vhd:54:25 */ + assign n1644_o = pc_ctrl == 3'b100; + /* HUC6280_AG.vhd:57:47 */ + assign n1645_o = {aah, aal}; + /* HUC6280_AG.vhd:56:25 */ + assign n1647_o = pc_ctrl == 3'b110; + assign n1648_o = {n1647_o, n1644_o, n1642_o, n1638_o, n1634_o, n1628_o}; + /* HUC6280_AG.vhd:41:17 */ + always @* + case (n1648_o) + 6'b100000: n1649_o = n1645_o; + 6'b010000: n1649_o = newpcwithoffset; + 6'b001000: n1649_o = n1640_o; + 6'b000100: n1649_o = n1636_o; + 6'b000010: n1649_o = n1632_o; + 6'b000001: n1649_o = pcr; + default: n1649_o = pcr; + endcase + /* HUC6280_AG.vhd:62:26 */ + assign n1650_o = ~rst_n; + /* HUC6280_AG.vhd:73:31 */ + assign n1659_o = addr_ctrl[5:3]; + /* HUC6280_AG.vhd:75:47 */ + assign n1661_o = {1'b0, aal}; + /* HUC6280_AG.vhd:74:25 */ + assign n1663_o = n1659_o == 3'b000; + /* HUC6280_AG.vhd:77:47 */ + assign n1665_o = {1'b0, di}; + /* HUC6280_AG.vhd:76:25 */ + assign n1667_o = n1659_o == 3'b001; + /* HUC6280_AG.vhd:79:73 */ + assign n1669_o = {1'b0, aal}; + /* HUC6280_AG.vhd:79:80 */ + assign n1671_o = n1669_o + 9'b000000001; + /* HUC6280_AG.vhd:78:25 */ + assign n1673_o = n1659_o == 3'b010; + /* HUC6280_AG.vhd:81:73 */ + assign n1675_o = {1'b0, aal}; + /* HUC6280_AG.vhd:81:95 */ + assign n1677_o = {1'b0, x}; + /* HUC6280_AG.vhd:81:80 */ + assign n1678_o = n1675_o + n1677_o; + /* HUC6280_AG.vhd:80:25 */ + assign n1680_o = n1659_o == 3'b011; + /* HUC6280_AG.vhd:83:73 */ + assign n1682_o = {1'b0, aal}; + /* HUC6280_AG.vhd:83:95 */ + assign n1684_o = {1'b0, y}; + /* HUC6280_AG.vhd:83:80 */ + assign n1685_o = n1682_o + n1684_o; + /* HUC6280_AG.vhd:82:25 */ + assign n1687_o = n1659_o == 3'b100; + /* HUC6280_AG.vhd:85:47 */ + assign n1689_o = {1'b0, dr}; + /* HUC6280_AG.vhd:84:25 */ + assign n1691_o = n1659_o == 3'b101; + /* HUC6280_AG.vhd:87:73 */ + assign n1693_o = {1'b0, dr}; + /* HUC6280_AG.vhd:87:94 */ + assign n1695_o = {1'b0, y}; + /* HUC6280_AG.vhd:87:79 */ + assign n1696_o = n1693_o + n1695_o; + /* HUC6280_AG.vhd:86:25 */ + assign n1698_o = n1659_o == 3'b110; + /* HUC6280_AG.vhd:89:47 */ + assign n1700_o = {1'b0, x}; + assign n1701_o = {n1698_o, n1691_o, n1687_o, n1680_o, n1673_o, n1667_o, n1663_o}; + /* HUC6280_AG.vhd:73:17 */ + always @* + case (n1701_o) + 7'b1000000: n1702_o = n1696_o; + 7'b0100000: n1702_o = n1689_o; + 7'b0010000: n1702_o = n1685_o; + 7'b0001000: n1702_o = n1678_o; + 7'b0000100: n1702_o = n1671_o; + 7'b0000010: n1702_o = n1665_o; + 7'b0000001: n1702_o = n1661_o; + default: n1702_o = n1700_o; + endcase + /* HUC6280_AG.vhd:92:31 */ + assign n1703_o = addr_ctrl[2:0]; + /* HUC6280_AG.vhd:93:25 */ + assign n1705_o = n1703_o == 3'b000; + /* HUC6280_AG.vhd:95:25 */ + assign n1707_o = n1703_o == 3'b001; + /* HUC6280_AG.vhd:98:74 */ + assign n1709_o = aah + 8'b00000001; + /* HUC6280_AG.vhd:97:25 */ + assign n1711_o = n1703_o == 3'b010; + /* HUC6280_AG.vhd:100:86 */ + assign n1713_o = {7'b0000000, savedcarry}; + /* HUC6280_AG.vhd:100:74 */ + assign n1714_o = aah + n1713_o; + /* HUC6280_AG.vhd:99:25 */ + assign n1716_o = n1703_o == 3'b011; + assign n1717_o = {n1716_o, n1711_o, n1707_o, n1705_o}; + /* HUC6280_AG.vhd:92:17 */ + always @* + case (n1717_o) + 4'b1000: n1718_o = n1714_o; + 4'b0100: n1718_o = n1709_o; + 4'b0010: n1718_o = di; + 4'b0001: n1718_o = aah; + default: n1718_o = aah; + endcase + /* HUC6280_AG.vhd:109:26 */ + assign n1722_o = ~rst_n; + /* HUC6280_AG.vhd:115:46 */ + assign n1724_o = newaal[7:0]; + /* HUC6280_AG.vhd:116:53 */ + assign n1725_o = newaal[8]; + /* HUC6280_AG.vhd:122:19 */ + assign n1739_o = {aah, aal}; + /* HUC6280_AG.vhd:113:17 */ + assign n1740_o = ce ? n1724_o : aal; + /* HUC6280_AG.vhd:113:17 */ + always @(posedge clk or posedge n1722_o) + if (n1722_o) + n1741_q <= 8'b00000000; + else + n1741_q <= n1740_o; + /* HUC6280_AG.vhd:113:17 */ + assign n1742_o = ce ? newaah : aah; + /* HUC6280_AG.vhd:113:17 */ + always @(posedge clk or posedge n1722_o) + if (n1722_o) + n1743_q <= 8'b00000000; + else + n1743_q <= n1742_o; + /* HUC6280_AG.vhd:113:17 */ + assign n1744_o = ce ? n1725_o : savedcarry; + /* HUC6280_AG.vhd:113:17 */ + always @(posedge clk or posedge n1722_o) + if (n1722_o) + n1745_q <= 1'b0; + else + n1745_q <= n1744_o; + /* HUC6280_AG.vhd:64:17 */ + assign n1746_o = ce ? nextpc : pcr; + /* HUC6280_AG.vhd:64:17 */ + always @(posedge clk or posedge n1650_o) + if (n1650_o) + n1747_q <= 16'b0000000000000000; + else + n1747_q <= n1746_o; +endmodule + +module alu + (input clk, + input en, + input [7:0] l, + input [7:0] r, + input [2:0] ctrl_fstop, + input [2:0] ctrl_secop, + input ctrl_fc, + input bcd, + input ci, + input vi, + input ni, + output co, + output vo, + output no, + output zo, + output [7:0] res); + wire [6:0] n1470_o; + wire [7:0] intl; + wire [7:0] intr; + wire cr; + wire addin; + wire bcdin; + wire ciin; + wire savedc; + wire [7:0] adds; + wire addco; + wire addvo; + wire [7:0] result; + wire [2:0] n1478_o; + wire n1479_o; + wire [6:0] n1480_o; + wire [7:0] n1482_o; + wire n1484_o; + wire n1485_o; + wire [6:0] n1486_o; + wire [7:0] n1487_o; + wire n1489_o; + wire n1490_o; + wire [6:0] n1491_o; + wire [7:0] n1493_o; + wire n1495_o; + wire n1496_o; + wire [6:0] n1497_o; + wire [7:0] n1498_o; + wire n1500_o; + wire n1501_o; + wire n1502_o; + wire n1503_o; + wire n1504_o; + wire n1506_o; + wire n1508_o; + wire n1509_o; + wire n1511_o; + wire n1513_o; + wire [7:0] n1514_o; + reg [7:0] n1515_o; + reg [7:0] n1522_o; + reg n1523_o; + reg n1525_o; + wire n1528_o; + wire n1529_o; + wire n1530_o; + wire n1531_o; + wire n1532_o; + wire [7:0] addsub_s; + wire addsub_co; + wire addsub_vo; + wire [2:0] n1544_o; + wire [7:0] n1545_o; + wire n1547_o; + wire [7:0] n1548_o; + wire n1550_o; + wire [7:0] n1551_o; + wire n1553_o; + wire n1555_o; + wire n1557_o; + wire n1558_o; + wire n1560_o; + wire n1561_o; + wire n1563_o; + wire n1564_o; + wire n1565_o; + wire [7:0] n1566_o; + wire [7:0] n1567_o; + wire [7:0] n1568_o; + wire [7:0] n1569_o; + wire n1571_o; + wire [5:0] n1572_o; + reg n1573_o; + reg [7:0] n1574_o; + wire n1578_o; + wire [2:0] n1579_o; + wire n1580_o; + wire n1581_o; + wire n1582_o; + wire n1583_o; + wire n1584_o; + wire n1586_o; + wire n1587_o; + wire n1588_o; + wire n1590_o; + wire n1591_o; + wire n1592_o; + wire n1594_o; + wire n1595_o; + wire n1596_o; + wire n1598_o; + wire [3:0] n1599_o; + reg n1600_o; + reg n1601_o; + wire n1605_o; + wire n1606_o; + wire n1608_o; + reg n1609_q; + assign co = n1573_o; + assign vo = n1600_o; + assign no = n1601_o; + assign zo = n1606_o; + assign res = result; + /* HUC6280_MC.vhd:6978:17 */ + assign n1470_o = {ctrl_fc, ctrl_secop, ctrl_fstop}; + /* HUC6280_ALU.vhd:28:16 */ + assign intl = n1515_o; // (signal) + /* HUC6280_ALU.vhd:29:16 */ + assign intr = n1522_o; // (signal) + /* HUC6280_ALU.vhd:30:16 */ + assign cr = n1523_o; // (signal) + /* HUC6280_ALU.vhd:31:16 */ + assign addin = n1532_o; // (signal) + /* HUC6280_ALU.vhd:32:16 */ + assign bcdin = n1525_o; // (signal) + /* HUC6280_ALU.vhd:33:16 */ + assign ciin = n1530_o; // (signal) + /* HUC6280_ALU.vhd:34:16 */ + assign savedc = n1609_q; // (signal) + /* HUC6280_ALU.vhd:36:16 */ + assign adds = addsub_s; // (signal) + /* HUC6280_ALU.vhd:37:16 */ + assign addco = addsub_co; // (signal) + /* HUC6280_ALU.vhd:38:16 */ + assign addvo = addsub_vo; // (signal) + /* HUC6280_ALU.vhd:39:16 */ + assign result = n1574_o; // (signal) + /* HUC6280_ALU.vhd:47:27 */ + assign n1478_o = n1470_o[2:0]; + /* HUC6280_ALU.vhd:49:40 */ + assign n1479_o = l[7]; + /* HUC6280_ALU.vhd:50:42 */ + assign n1480_o = l[6:0]; + /* HUC6280_ALU.vhd:50:55 */ + assign n1482_o = {n1480_o, 1'b0}; + /* HUC6280_ALU.vhd:48:25 */ + assign n1484_o = n1478_o == 3'b000; + /* HUC6280_ALU.vhd:53:40 */ + assign n1485_o = l[7]; + /* HUC6280_ALU.vhd:54:42 */ + assign n1486_o = l[6:0]; + /* HUC6280_ALU.vhd:54:55 */ + assign n1487_o = {n1486_o, ci}; + /* HUC6280_ALU.vhd:52:25 */ + assign n1489_o = n1478_o == 3'b001; + /* HUC6280_ALU.vhd:57:40 */ + assign n1490_o = l[0]; + /* HUC6280_ALU.vhd:58:48 */ + assign n1491_o = l[7:1]; + /* HUC6280_ALU.vhd:58:45 */ + assign n1493_o = {1'b0, n1491_o}; + /* HUC6280_ALU.vhd:56:25 */ + assign n1495_o = n1478_o == 3'b010; + /* HUC6280_ALU.vhd:61:40 */ + assign n1496_o = l[0]; + /* HUC6280_ALU.vhd:62:47 */ + assign n1497_o = l[7:1]; + /* HUC6280_ALU.vhd:62:44 */ + assign n1498_o = {ci, n1497_o}; + /* HUC6280_ALU.vhd:60:25 */ + assign n1500_o = n1478_o == 3'b011; + /* HUC6280_ALU.vhd:67:60 */ + assign n1501_o = n1470_o[4]; + /* HUC6280_ALU.vhd:67:46 */ + assign n1502_o = bcd & n1501_o; + /* HUC6280_ALU.vhd:67:78 */ + assign n1503_o = n1470_o[3]; + /* HUC6280_ALU.vhd:67:64 */ + assign n1504_o = n1502_o & n1503_o; + /* HUC6280_ALU.vhd:64:25 */ + assign n1506_o = n1478_o == 3'b100; + /* HUC6280_ALU.vhd:68:25 */ + assign n1508_o = n1478_o == 3'b101; + /* HUC6280_ALU.vhd:74:49 */ + assign n1509_o = n1470_o[5]; + /* HUC6280_ALU.vhd:71:25 */ + assign n1511_o = n1478_o == 3'b110; + /* HUC6280_ALU.vhd:75:25 */ + assign n1513_o = n1478_o == 3'b111; + assign n1514_o = {n1513_o, n1511_o, n1508_o, n1506_o, n1500_o, n1495_o, n1489_o, n1484_o}; + /* HUC6280_ALU.vhd:47:17 */ + always @* + case (n1514_o) + 8'b10000000: n1515_o = l; + 8'b01000000: n1515_o = l; + 8'b00100000: n1515_o = l; + 8'b00010000: n1515_o = l; + 8'b00001000: n1515_o = n1498_o; + 8'b00000100: n1515_o = n1493_o; + 8'b00000010: n1515_o = n1487_o; + 8'b00000001: n1515_o = n1482_o; + default: n1515_o = intl; + endcase + /* HUC6280_ALU.vhd:47:17 */ + always @* + case (n1514_o) + 8'b10000000: n1522_o = 8'b00000000; + 8'b01000000: n1522_o = 8'b00000001; + 8'b00100000: n1522_o = r; + 8'b00010000: n1522_o = r; + 8'b00001000: n1522_o = 8'b00000000; + 8'b00000100: n1522_o = 8'b00000000; + 8'b00000010: n1522_o = 8'b00000000; + 8'b00000001: n1522_o = 8'b00000000; + default: n1522_o = intr; + endcase + /* HUC6280_ALU.vhd:47:17 */ + always @* + case (n1514_o) + 8'b10000000: n1523_o = savedc; + 8'b01000000: n1523_o = n1509_o; + 8'b00100000: n1523_o = ci; + 8'b00010000: n1523_o = ci; + 8'b00001000: n1523_o = n1496_o; + 8'b00000100: n1523_o = n1490_o; + 8'b00000010: n1523_o = n1485_o; + 8'b00000001: n1523_o = n1479_o; + default: n1523_o = ci; + endcase + /* HUC6280_ALU.vhd:47:17 */ + always @* + case (n1514_o) + 8'b10000000: n1525_o = 1'b0; + 8'b01000000: n1525_o = 1'b0; + 8'b00100000: n1525_o = 1'b0; + 8'b00010000: n1525_o = n1504_o; + 8'b00001000: n1525_o = 1'b0; + 8'b00000100: n1525_o = 1'b0; + 8'b00000010: n1525_o = 1'b0; + 8'b00000001: n1525_o = 1'b0; + default: n1525_o = 1'b0; + endcase + /* HUC6280_ALU.vhd:83:37 */ + assign n1528_o = n1470_o[3]; + /* HUC6280_ALU.vhd:83:23 */ + assign n1529_o = ~n1528_o; + /* HUC6280_ALU.vhd:83:20 */ + assign n1530_o = cr | n1529_o; + /* HUC6280_ALU.vhd:84:32 */ + assign n1531_o = n1470_o[5]; + /* HUC6280_ALU.vhd:84:18 */ + assign n1532_o = ~n1531_o; + /* HUC6280_ALU.vhd:86:9 */ + addsubbcd addsub ( + .a(intl), + .b(intr), + .ci(ciin), + .add(addin), + .bcd(bcdin), + .s(addsub_s), + .co(addsub_co), + .vo(addsub_vo)); + /* HUC6280_ALU.vhd:109:27 */ + assign n1544_o = n1470_o[5:3]; + /* HUC6280_ALU.vhd:112:48 */ + assign n1545_o = intl | intr; + /* HUC6280_ALU.vhd:110:25 */ + assign n1547_o = n1544_o == 3'b000; + /* HUC6280_ALU.vhd:115:48 */ + assign n1548_o = intl & intr; + /* HUC6280_ALU.vhd:113:25 */ + assign n1550_o = n1544_o == 3'b001; + /* HUC6280_ALU.vhd:118:48 */ + assign n1551_o = intl ^ intr; + /* HUC6280_ALU.vhd:116:25 */ + assign n1553_o = n1544_o == 3'b010; + /* HUC6280_ALU.vhd:119:25 */ + assign n1555_o = n1544_o == 3'b011; + /* HUC6280_ALU.vhd:119:36 */ + assign n1557_o = n1544_o == 3'b110; + /* HUC6280_ALU.vhd:119:36 */ + assign n1558_o = n1555_o | n1557_o; + /* HUC6280_ALU.vhd:119:44 */ + assign n1560_o = n1544_o == 3'b111; + /* HUC6280_ALU.vhd:119:44 */ + assign n1561_o = n1558_o | n1560_o; + /* HUC6280_ALU.vhd:122:25 */ + assign n1563_o = n1544_o == 3'b100; + /* HUC6280_ALU.vhd:127:41 */ + assign n1564_o = n1470_o[6]; + /* HUC6280_ALU.vhd:127:44 */ + assign n1565_o = ~n1564_o; + /* HUC6280_ALU.vhd:128:61 */ + assign n1566_o = ~intl; + /* HUC6280_ALU.vhd:128:56 */ + assign n1567_o = intr & n1566_o; + /* HUC6280_ALU.vhd:130:56 */ + assign n1568_o = intr | intl; + /* HUC6280_ALU.vhd:127:33 */ + assign n1569_o = n1565_o ? n1567_o : n1568_o; + /* HUC6280_ALU.vhd:125:25 */ + assign n1571_o = n1544_o == 3'b101; + assign n1572_o = {n1571_o, n1563_o, n1561_o, n1553_o, n1550_o, n1547_o}; + /* HUC6280_ALU.vhd:109:17 */ +/* verilator lint_off LATCH */ + always @* + case (n1572_o) + 6'b100000: n1573_o = cr; + 6'b010000: n1573_o = cr; + 6'b001000: n1573_o = addco; + 6'b000100: n1573_o = cr; + 6'b000010: n1573_o = cr; + 6'b000001: n1573_o = cr; + default: n1573_o = n1573_o; + endcase + /* HUC6280_ALU.vhd:109:17 */ + always @* + case (n1572_o) + 6'b100000: n1574_o = n1569_o; + 6'b010000: n1574_o = intl; + 6'b001000: n1574_o = adds; + 6'b000100: n1574_o = n1551_o; + 6'b000010: n1574_o = n1548_o; + 6'b000001: n1574_o = n1545_o; + default: n1574_o = result; + endcase +/* verilator lint_on LATCH */ + /* HUC6280_ALU.vhd:139:29 */ + assign n1578_o = result[7]; + /* HUC6280_ALU.vhd:140:27 */ + assign n1579_o = n1470_o[5:3]; + /* HUC6280_ALU.vhd:142:41 */ + assign n1580_o = n1470_o[6]; + /* HUC6280_ALU.vhd:143:51 */ + assign n1581_o = intr[6]; + /* HUC6280_ALU.vhd:144:51 */ + assign n1582_o = intr[7]; + /* HUC6280_ALU.vhd:142:33 */ + assign n1583_o = n1580_o ? n1581_o : vi; + /* HUC6280_ALU.vhd:142:33 */ + assign n1584_o = n1580_o ? n1582_o : n1578_o; + /* HUC6280_ALU.vhd:141:25 */ + assign n1586_o = n1579_o == 3'b001; + /* HUC6280_ALU.vhd:147:42 */ + assign n1587_o = ~bcdin; + /* HUC6280_ALU.vhd:147:33 */ + assign n1588_o = n1587_o ? addvo : vi; + /* HUC6280_ALU.vhd:146:25 */ + assign n1590_o = n1579_o == 3'b011; + /* HUC6280_ALU.vhd:151:43 */ + assign n1591_o = intr[6]; + /* HUC6280_ALU.vhd:152:43 */ + assign n1592_o = intr[7]; + /* HUC6280_ALU.vhd:150:25 */ + assign n1594_o = n1579_o == 3'b101; + /* HUC6280_ALU.vhd:154:42 */ + assign n1595_o = ~bcdin; + /* HUC6280_ALU.vhd:154:33 */ + assign n1596_o = n1595_o ? addvo : vi; + /* HUC6280_ALU.vhd:153:25 */ + assign n1598_o = n1579_o == 3'b111; + assign n1599_o = {n1598_o, n1594_o, n1590_o, n1586_o}; + /* HUC6280_ALU.vhd:140:17 */ + always @* + case (n1599_o) + 4'b1000: n1600_o = n1596_o; + 4'b0100: n1600_o = n1591_o; + 4'b0010: n1600_o = n1588_o; + 4'b0001: n1600_o = n1583_o; + default: n1600_o = vi; + endcase + /* HUC6280_ALU.vhd:140:17 */ + always @* + case (n1599_o) + 4'b1000: n1601_o = n1578_o; + 4'b0100: n1601_o = n1592_o; + 4'b0010: n1601_o = n1578_o; + 4'b0001: n1601_o = n1584_o; + default: n1601_o = n1578_o; + endcase + /* HUC6280_ALU.vhd:162:31 */ + assign n1605_o = result == 8'b00000000; + /* HUC6280_ALU.vhd:162:19 */ + assign n1606_o = n1605_o ? 1'b1 : 1'b0; + /* HUC6280_ALU.vhd:100:17 */ + assign n1608_o = en ? addco : savedc; + /* HUC6280_ALU.vhd:100:17 */ + always @(posedge clk) + n1609_q <= n1608_o; +endmodule + +module huc6280_mc + (input clk, + input rst_n, + input en, + input [7:0] ir, + input [4:0] state, + output [1:0] m_state_ctrl, + output [2:0] m_addr_bus, + output [1:0] m_load_sdlh, + output [2:0] m_load_p, + output [2:0] m_load_t, + output [5:0] m_addr_ctrl, + output [2:0] m_load_pc, + output [2:0] m_load_sp, + output [2:0] m_axy_ctrl, + output [3:0] m_alubus_ctrl, + output [3:0] m_out_bus, + output m_mem_cycle, + output [6:0] m_alu_ctrl); + wire [1:0] n1371_o; + wire [2:0] n1372_o; + wire [1:0] n1373_o; + wire [2:0] n1374_o; + wire [2:0] n1375_o; + wire [5:0] n1376_o; + wire [2:0] n1377_o; + wire [2:0] n1378_o; + wire [2:0] n1379_o; + wire [3:0] n1380_o; + wire [3:0] n1381_o; + wire n1382_o; + wire [6:0] n1383_o; + wire [41:0] mi; + wire [6:0] aluflags; + wire [4:0] n1384_o; + wire [4:0] n1387_o; + wire n1394_o; + wire [2:0] n1396_o; + wire [10:0] n1397_o; + wire n1399_o; + wire [1:0] n1400_o; + wire n1402_o; + wire [10:0] n1405_o; + wire [1:0] n1409_o; + wire n1411_o; + wire [10:0] n1414_o; + wire [1:0] n1418_o; + wire n1420_o; + wire [10:0] n1423_o; + wire [41:0] n1427_o; + wire [41:0] n1428_o; + wire [41:0] n1429_o; + wire [41:0] n1431_o; + wire [1:0] n1444_o; + wire [2:0] n1445_o; + wire [1:0] n1446_o; + wire [2:0] n1447_o; + wire [2:0] n1448_o; + wire [5:0] n1449_o; + wire [2:0] n1450_o; + wire [2:0] n1451_o; + wire [2:0] n1452_o; + wire [3:0] n1453_o; + wire [3:0] n1454_o; + wire n1455_o; + wire [15:0] n1456_o; + wire [14:0] n1457_o; + wire [10:0] n1458_o; + wire [43:0] n1459_o; + wire [41:0] n1460_o; + reg [41:0] n1461_q; + wire [6:0] n1463_data; // mem_rd + wire [41:0] n1465_data; // mem_rd + wire [41:0] n1467_data; // mem_rd + wire [41:0] n1469_data; // mem_rd + assign m_state_ctrl = n1371_o; + assign m_addr_bus = n1372_o; + assign m_load_sdlh = n1373_o; + assign m_load_p = n1374_o; + assign m_load_t = n1375_o; + assign m_addr_ctrl = n1376_o; + assign m_load_pc = n1377_o; + assign m_load_sp = n1378_o; + assign m_axy_ctrl = n1379_o; + assign m_alubus_ctrl = n1380_o; + assign m_out_bus = n1381_o; + assign m_mem_cycle = n1382_o; + assign m_alu_ctrl = n1383_o; + /* HUC6280_CPU.vhd:482:17 */ + assign n1371_o = n1459_o[1:0]; + /* HUC6280_CPU.vhd:472:9 */ + assign n1372_o = n1459_o[4:2]; + assign n1373_o = n1459_o[6:5]; + /* HUC6280_CPU.vhd:460:17 */ + assign n1374_o = n1459_o[9:7]; + /* HUC6280_CPU.vhd:460:17 */ + assign n1375_o = n1459_o[12:10]; + /* HUC6280_CPU.vhd:455:9 */ + assign n1376_o = n1459_o[18:13]; + assign n1377_o = n1459_o[21:19]; + /* HUC6280_CPU.vhd:431:17 */ + assign n1378_o = n1459_o[24:22]; + /* HUC6280_CPU.vhd:427:9 */ + assign n1379_o = n1459_o[27:25]; + assign n1380_o = n1459_o[31:28]; + assign n1381_o = n1459_o[35:32]; + /* HUC6280_CPU.vhd:419:9 */ + assign n1382_o = n1459_o[36]; + assign n1383_o = n1459_o[43:37]; + /* HUC6280_MC.vhd:6966:16 */ + assign mi = n1461_q; // (signal) + /* HUC6280_MC.vhd:6967:16 */ + assign aluflags = n1463_data; // (signal) + /* HUC6280_MC.vhd:6971:52 */ + assign n1384_o = mi[36:32]; + /* HUC6280_MC.vhd:6971:29 */ + assign n1387_o = 5'b10001 - n1384_o; + /* HUC6280_MC.vhd:6976:26 */ + assign n1394_o = ~rst_n; + /* HUC6280_MC.vhd:6980:56 */ + assign n1396_o = state[2:0]; + /* HUC6280_MC.vhd:6980:50 */ + assign n1397_o = {ir, n1396_o}; + /* HUC6280_MC.vhd:6981:42 */ + assign n1399_o = state == 5'b00000; + /* HUC6280_MC.vhd:6983:44 */ + assign n1400_o = state[4:3]; + /* HUC6280_MC.vhd:6983:57 */ + assign n1402_o = n1400_o == 2'b00; + /* HUC6280_MC.vhd:6984:54 */ + assign n1405_o = 11'b11111111111 - n1397_o; + /* HUC6280_MC.vhd:6985:44 */ + assign n1409_o = state[4:3]; + /* HUC6280_MC.vhd:6985:57 */ + assign n1411_o = n1409_o == 2'b01; + /* HUC6280_MC.vhd:6986:54 */ + assign n1414_o = 11'b11111111111 - n1397_o; + /* HUC6280_MC.vhd:6987:44 */ + assign n1418_o = state[4:3]; + /* HUC6280_MC.vhd:6987:57 */ + assign n1420_o = n1418_o == 2'b10; + /* HUC6280_MC.vhd:6988:54 */ + assign n1423_o = 11'b11111111111 - n1397_o; + /* HUC6280_MC.vhd:6987:33 */ + assign n1427_o = n1420_o ? n1469_data : mi; + /* HUC6280_MC.vhd:6985:33 */ + assign n1428_o = n1411_o ? n1467_data : n1427_o; + /* HUC6280_MC.vhd:6983:33 */ + assign n1429_o = n1402_o ? n1465_data : n1428_o; + /* HUC6280_MC.vhd:6981:33 */ + assign n1431_o = n1399_o ? 42'b100000000000000000000010000000000000000000 : n1429_o; + /* HUC6280_MC.vhd:6994:18 */ + assign n1444_o = mi[1:0]; + /* HUC6280_MC.vhd:6995:28 */ + assign n1445_o = mi[4:2]; + /* HUC6280_MC.vhd:6996:28 */ + assign n1446_o = mi[6:5]; + /* HUC6280_MC.vhd:6997:28 */ + assign n1447_o = mi[9:7]; + /* HUC6280_MC.vhd:6998:28 */ + assign n1448_o = mi[12:10]; + /* HUC6280_MC.vhd:6999:28 */ + assign n1449_o = mi[18:13]; + /* HUC6280_MC.vhd:7000:28 */ + assign n1450_o = mi[21:19]; + /* HUC6280_MC.vhd:7001:28 */ + assign n1451_o = mi[24:22]; + /* HUC6280_MC.vhd:7002:28 */ + assign n1452_o = mi[27:25]; + /* HUC6280_MC.vhd:7003:28 */ + assign n1453_o = mi[31:28]; + /* HUC6280_MC.vhd:7004:28 */ + assign n1454_o = mi[40:37]; + /* HUC6280_MC.vhd:7005:28 */ + assign n1455_o = mi[41]; + assign n1456_o = {aluflags, n1455_o, n1454_o, n1453_o}; + assign n1457_o = {n1452_o, n1451_o, n1450_o, n1449_o}; + assign n1458_o = {n1448_o, n1447_o, n1446_o, n1445_o}; + assign n1459_o = {n1456_o, n1457_o, n1458_o, n1444_o}; + /* HUC6280_MC.vhd:6978:17 */ + assign n1460_o = en ? n1431_o : mi; + /* HUC6280_MC.vhd:6978:17 */ + always @(posedge clk or posedge n1394_o) + if (n1394_o) + n1461_q <= 42'b100000000000000000000010000000000000000000; + else + n1461_q <= n1460_o; + /* HUC6280_MC.vhd:14:9 */ + reg [6:0] n1462[17:0] ; // memory + initial begin + n1462[17] = 7'b0100100; + n1462[16] = 7'b0001100; + n1462[15] = 7'b0000100; + n1462[14] = 7'b0010100; + n1462[13] = 7'b0011100; + n1462[12] = 7'b1111100; + n1462[11] = 7'b0111110; + n1462[10] = 7'b0011110; + n1462[9] = 7'b0100000; + n1462[8] = 7'b0100010; + n1462[7] = 7'b0100001; + n1462[6] = 7'b0100011; + n1462[5] = 7'b1001100; + n1462[4] = 7'b0101100; + n1462[3] = 7'b1101100; + n1462[2] = 7'b0110100; + n1462[1] = 7'b0111111; + n1462[0] = 7'b0011111; + end + assign n1463_data = n1462[n1387_o]; + /* HUC6280_MC.vhd:6971:29 */ + /* HUC6280_MC.vhd:6971:28 */ + reg [41:0] n1464[2047:0] ; // memory + initial begin + n1464[2047] = 42'b100000000000000000000010000000000000000000; + n1464[2046] = 42'b100000000000000000000010000000000000000000; + n1464[2045] = 42'b000000000000000000000000000000000000000000; + n1464[2044] = 42'b101100000000000000110000000000000000001000; + n1464[2043] = 42'b101110000000000000110000000000000000001000; + n1464[2042] = 42'b101010000000000000110000000000000000001000; + n1464[2041] = 42'b100000000000000000000100000000000100010000; + n1464[2040] = 42'b100000000000000000000110000000000000010010; + n1464[2039] = 42'b100000000000000000000010000000000000000000; + n1464[2038] = 42'b100000000000000000000010010000000000000000; + n1464[2037] = 42'b000000000000000000000000110000000000000000; + n1464[2036] = 42'b100000000000000000000000100000000000001100; + n1464[2035] = 42'b100000000000000000000001010010000000001100; + n1464[2034] = 42'b000000000000000000000000000000000000000000; + n1464[2033] = 42'b100000001000010010000000000000000010000110; + n1464[2032] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1464[2031] = 42'b100000000000000000000010000000000000000000; + n1464[2030] = 42'b100000000000110100000000000000100000000000; + n1464[2029] = 42'b000000000001011000000000000000000000000010; + n1464[2028] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1464[2027] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1464[2026] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1464[2025] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1464[2024] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1464[2023] = 42'b100000000000000000000010000000000000000000; + n1464[2022] = 42'b100000000000000000000010000000010000000000; + n1464[2021] = 42'b000000000000000000000000000000000000000000; + n1464[2020] = 42'b101000000000000000000000000000000000010110; + n1464[2019] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1464[2018] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1464[2017] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1464[2016] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1464[2015] = 42'b100000000000000000000010000000000000000000; + n1464[2014] = 42'b100000000000000000000010010000000000000000; + n1464[2013] = 42'b000000000000000000000000000000000000000000; + n1464[2012] = 42'b100000111000010000000000000000011010001100; + n1464[2011] = 42'b000000000000000000000000000000000000000000; + n1464[2010] = 42'b101000000000000000000000000000000000001110; + n1464[2009] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1464[2008] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1464[2007] = 42'b100000000000000000000010000000000000000000; + n1464[2006] = 42'b100000000000000000000010010000000000000000; + n1464[2005] = 42'b000000000000000000000000000000000000000000; + n1464[2004] = 42'b100000001000010010000000000000000010001110; + n1464[2003] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1464[2002] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1464[2001] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1464[2000] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1464[1999] = 42'b100000000000000000000010000000000000000000; + n1464[1998] = 42'b100000000000000000000010010000000000000000; + n1464[1997] = 42'b000000000000000000000000000000000000000000; + n1464[1996] = 42'b100000100000000000000000000000011010001100; + n1464[1995] = 42'b000000000000000000000000000000000000000000; + n1464[1994] = 42'b101000000000000000000000000000000000001110; + n1464[1993] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1464[1992] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1464[1991] = 42'b100000000000000000000010000000000000000000; + n1464[1990] = 42'b100000000000000000000010010000000000000000; + n1464[1989] = 42'b000000000000000000000000000000000000000000; + n1464[1988] = 42'b100000110111000000000000000000010000001100; + n1464[1987] = 42'b000000000000000000000000000000000000000000; + n1464[1986] = 42'b000000000000000000000000000000000000000000; + n1464[1985] = 42'b101000000000000000000000000000000000001110; + n1464[1984] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1464[1983] = 42'b100000000000000000000010000000000000000000; + n1464[1982] = 42'b100000000000000000000000000000000000000000; + n1464[1981] = 42'b101010000000000000110000000000000000001010; + n1464[1980] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1464[1979] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1464[1978] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1464[1977] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1464[1976] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1464[1975] = 42'b100000000000000000000010000000000000000000; + n1464[1974] = 42'b100000001000010010000010000000000010000010; + n1464[1973] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1464[1972] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1464[1971] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1464[1970] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1464[1969] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1464[1968] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1464[1967] = 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42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1464[169] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1464[168] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1464[167] = 42'b100000000000000000000010000000000000000000; + n1464[166] = 42'b000000000000000000000000000000000000000010; + n1464[165] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1464[164] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1464[163] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1464[162] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1464[161] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1464[160] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1464[159] = 42'b100000000000000000000010000000000000000000; + n1464[158] = 42'b100000000000000000000010010000000000000000; + n1464[157] = 42'b100000000000000000000010000010000000000000; + n1464[156] = 42'b000000000000000000000000000000000000000000; + n1464[155] = 42'b100000111100100000000000000000001010000110; + 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42'b100000011100000000000000000000010010000100; + n1464[138] = 42'b000000000000000000000000000000000000000000; + n1464[137] = 42'b101000000000000000000000000000000000000110; + n1464[136] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1464[135] = 42'b100000000000000000000010000000000000000000; + n1464[134] = 42'b100000000000000000000010010000000000000000; + n1464[133] = 42'b000000000000000000000000000000000000000000; + n1464[132] = 42'b000000000000000000000000000000000000000000; + n1464[131] = 42'b100000000000000000000000000000000000001100; + n1464[130] = 42'b100000000000000000000010010000000000000010; + n1464[129] = 42'b000000000000000000001000000000000000000000; + n1464[128] = 42'b000000000000000000000000000000000000000010; + n1464[127] = 42'b100000000000000000000010000000000000000000; + n1464[126] = 42'b100000000000000000000010010000000000000010; + n1464[125] = 42'b100000000000000000000000000000000000000000; + n1464[124] = 42'b000000000000000000001000000000000000000010; + n1464[123] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1464[122] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1464[121] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1464[120] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1464[119] = 42'b100000000000000000000010000000000000000000; + n1464[118] = 42'b100000000000000000000010010000000000000000; + n1464[117] = 42'b000000000000000000000000000000000000000000; + n1464[116] = 42'b100000000000000000000000100000000000001100; + n1464[115] = 42'b100000000000000000000001100010000000001100; + n1464[114] = 42'b000000000000000000000000000110000000000000; + n1464[113] = 42'b100000010100010010000000000000001010000101; + n1464[112] = 42'b000000000000000000000000000000000000000010; + n1464[111] = 42'b100000000000000000000010000000000000000000; + n1464[110] = 42'b100000000000000000000010010000000000000000; + n1464[109] = 42'b000000000000000000000000000000000000000000; + n1464[108] = 42'b100000000000000000000000100000000000001100; + n1464[107] = 42'b100000000000000000000001010010000000001100; + n1464[106] = 42'b000000000000000000000000000000000000000000; + n1464[105] = 42'b100000010100010010000000000000001010000101; + n1464[104] = 42'b000000000000000000000000000000000000000010; + n1464[103] = 42'b100000000000000000000010000000000000000000; + n1464[102] = 42'b100110000000000000110000000000000000001000; + n1464[101] = 42'b100010000000000000110000000000000000001000; + n1464[100] = 42'b100100000000000000000000000000000000001000; + n1464[99] = 42'b100000000000000100000010000000000000000000; + n1464[98] = 42'b100000000000000000000010000000000000100000; + n1464[97] = 42'b100000000000001000000010000000000000000000; + n1464[96] = 42'b100000000000000000000010000000000001000000; + n1464[95] = 42'b100000000000000000000010000000000000000000; + n1464[94] = 42'b100000000000000000000000000000001100000010; + n1464[93] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1464[92] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1464[91] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1464[90] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1464[89] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1464[88] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1464[87] = 42'b100000000000000000000010000000000000000000; + n1464[86] = 42'b100000000000000000000010010000000000000000; + n1464[85] = 42'b000000000000000000000000110000000000000000; + n1464[84] = 42'b100000010100010010000000000000001010001101; + n1464[83] = 42'b000000000000000000000000000000000000000010; + n1464[82] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1464[81] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1464[80] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1464[79] = 42'b100000000000000000000010000000000000000000; + n1464[78] = 42'b100000000000000000000010010000000000000000; + n1464[77] = 42'b000000000000000000000000110000000000000000; + n1464[76] = 42'b100000011100000000000000000000010010001100; + n1464[75] = 42'b000000000000000000000000000000000000000000; + n1464[74] = 42'b101000000000000000000000000000000000001110; + n1464[73] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1464[72] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1464[71] = 42'b100000000000000000000010000000000000000000; + n1464[70] = 42'b100000000000000000000010010000000000000000; + n1464[69] = 42'b000000000000000000000000000000000000000000; + n1464[68] = 42'b100000111011000000000000000000010000001100; + n1464[67] = 42'b000000000000000000000000000000000000000000; + n1464[66] = 42'b000000000000000000000000000000000000000000; + n1464[65] = 42'b101000000000000000000000000000000000001110; + n1464[64] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1464[63] = 42'b100000000000000000000010000000000000000000; + n1464[62] = 42'b100000000000000000000000000000001000000010; + n1464[61] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1464[60] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1464[59] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1464[58] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1464[57] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1464[56] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1464[55] = 42'b100000000000000000000010000000000000000000; + n1464[54] = 42'b100000000000000000000010010000000000000000; + n1464[53] = 42'b100000000000000000000011000010000000000000; + n1464[52] = 42'b000000000000000000000000000110000000000000; + n1464[51] = 42'b100000010100010010000000000000001010000101; + n1464[50] = 42'b000000000000000000000000000000000000000010; + n1464[49] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1464[48] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1464[47] = 42'b100000000000000000000010000000000000000000; + n1464[46] = 42'b000000000000000000000000000000000000000000; + n1464[45] = 42'b000000000000000000100000000000000000000000; + n1464[44] = 42'b100000000000000100000000000000000010001010; + n1464[43] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1464[42] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1464[41] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1464[40] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1464[39] = 42'b100000000000000000000010000000000000000000; + n1464[38] = 42'b000000000000000000000000000000000000000010; + n1464[37] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1464[36] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1464[35] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1464[34] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1464[33] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1464[32] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1464[31] = 42'b100000000000000000000010000000000000000000; + n1464[30] = 42'b000000000000000000000000000000000000000010; + n1464[29] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1464[28] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1464[27] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1464[26] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1464[25] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1464[24] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1464[23] = 42'b100000000000000000000010000000000000000000; + n1464[22] = 42'b100000000000000000000010010000000000000000; + n1464[21] = 42'b100000000000000000000010110010000000000000; + n1464[20] = 42'b000000000000000000000000000110000000000000; + n1464[19] = 42'b100000010100010010000000000000001010000101; + n1464[18] = 42'b000000000000000000000000000000000000000010; + n1464[17] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1464[16] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1464[15] = 42'b100000000000000000000010000000000000000000; + n1464[14] = 42'b100000000000000000000010010000000000000000; + n1464[13] = 42'b100000000000000000000010110010000000000000; + n1464[12] = 42'b000000000000000000000000000110000000000000; + n1464[11] = 42'b100000011100000000000000000000010010000100; + n1464[10] = 42'b000000000000000000000000000000000000000000; + n1464[9] = 42'b101000000000000000000000000000000000000110; + n1464[8] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1464[7] = 42'b100000000000000000000010000000000000000000; + n1464[6] = 42'b100000000000000000000010010000000000000000; + n1464[5] = 42'b000000000000000000000000000000000000000000; + n1464[4] = 42'b000000000000000000000000000000000000000000; + n1464[3] = 42'b100000000000000000000000000000000000001100; + n1464[2] = 42'b100000000000000000000010010000000000000010; + n1464[1] = 42'b000000000000000000001000000000000000000000; + n1464[0] = 42'b000000000000000000000000000000000000000010; + end + assign n1465_data = n1464[n1405_o]; + /* HUC6280_MC.vhd:6984:54 */ + /* HUC6280_MC.vhd:6984:53 */ + reg [41:0] n1466[2047:0] ; // memory + initial begin + n1466[2047] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[2046] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[2045] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[2044] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[2043] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[2042] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[2041] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[2040] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[2039] = 42'b100000000000000000000010010000000000000000; + n1466[2038] = 42'b000000000000000000000000110000000000000000; + n1466[2037] = 42'b100000000000000000000000100000000000001100; + n1466[2036] = 42'b100000000000000000000001010010000000001100; + n1466[2035] = 42'b000000000000000000000000000000000000000000; + n1466[2034] = 42'b100000000000000000000000000000010000000100; + n1466[2033] = 42'b000000000000000000000001110000000000000000; + n1466[2032] = 42'b100000001001010000000000000000010010001100; + n1466[2031] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[2030] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[2029] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[2028] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[2027] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[2026] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[2025] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[2024] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[2023] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[2022] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[2021] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[2020] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[2019] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[2018] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[2017] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[2016] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[2015] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[2014] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[2013] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[2012] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[2011] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[2010] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[2009] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[2008] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[2007] = 42'b100000000000000000000010010000000000000000; + n1466[2006] = 42'b000000000000000000000000000000000000000000; + n1466[2005] = 42'b100000000000000000000000000000010000001100; + n1466[2004] = 42'b000000000000000000000001110000000000000000; + n1466[2003] = 42'b100000001001010000000000000000010010001100; + n1466[2002] = 42'b101000000000000000000000000000000000001110; + n1466[2001] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[2000] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1999] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1998] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1997] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1996] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1995] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1994] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1993] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1992] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1991] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1990] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1989] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1988] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1987] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1986] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1985] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1984] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1983] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1982] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1981] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1980] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1979] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1978] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1977] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1976] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1975] = 42'b100000000000000000000010000000010000000000; + n1466[1974] = 42'b000000000000000000000001110000000000000000; + n1466[1973] = 42'b100000001001010000000000000000010010001100; + n1466[1972] = 42'b101000000000000000000000000000000000001110; + n1466[1971] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1970] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1969] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1968] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1967] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1966] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1965] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1964] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1963] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1962] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1961] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1960] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1959] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1958] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1957] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1956] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1955] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1954] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1953] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1952] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1951] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1950] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1949] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1948] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1947] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1946] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1945] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1944] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1943] = 42'b100000000000000000000010010000000000000000; + n1466[1942] = 42'b100000000000000000000010000010000000000000; + n1466[1941] = 42'b000000000000000000000000000000000000000000; + n1466[1940] = 42'b100000000000000000000000000000010000000100; + n1466[1939] = 42'b000000000000000000000001110000000000000000; + n1466[1938] = 42'b100000001001010000000000000000010010001100; + n1466[1937] = 42'b101000000000000000000000000000000000001110; + n1466[1936] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1935] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1934] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1933] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1932] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1931] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1930] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1929] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1928] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1927] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1926] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1925] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1924] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1923] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1922] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1921] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1920] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1919] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1918] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1917] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1916] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1915] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1914] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1913] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1912] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1911] = 42'b100000000000000000000010010000000000000000; + n1466[1910] = 42'b000000000000000000000000000000000000000000; + n1466[1909] = 42'b100000000000000000000000100000000000001100; + n1466[1908] = 42'b100000000000000000000001100010000000001100; + n1466[1907] = 42'b000000000000000000000000000110000000000000; + n1466[1906] = 42'b100000000000000000000000000000010000000100; + n1466[1905] = 42'b000000000000000000000001110000000000000000; + n1466[1904] = 42'b100000001001010000000000000000010010001100; + n1466[1903] = 42'b100000000000000000000010010000000000000000; + n1466[1902] = 42'b000000000000000000000000000000000000000000; + n1466[1901] = 42'b100000000000000000000000100000000000001100; + n1466[1900] = 42'b100000000000000000000001010010000000001100; + n1466[1899] = 42'b000000000000000000000000000000000000000000; + n1466[1898] = 42'b100000000000000000000000000000010000000100; + n1466[1897] = 42'b000000000000000000000001110000000000000000; + n1466[1896] = 42'b100000001001010000000000000000010010001100; + n1466[1895] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1894] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1893] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1892] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1891] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1890] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1889] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1888] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1887] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1886] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1885] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1884] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1883] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1882] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1881] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1880] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1879] = 42'b100000000000000000000010010000000000000000; + n1466[1878] = 42'b000000000000000000000000110000000000000000; + n1466[1877] = 42'b100000000000000000000000000000010000001100; + n1466[1876] = 42'b000000000000000000000001110000000000000000; + n1466[1875] = 42'b100000001001010000000000000000010010001100; + n1466[1874] = 42'b101000000000000000000000000000000000001110; + n1466[1873] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1872] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1871] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1870] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1869] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1868] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1867] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1866] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1865] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1864] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1863] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1862] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1861] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1860] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1859] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1858] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1857] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1856] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1855] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1854] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1853] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1852] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1851] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1850] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1849] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1848] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1847] = 42'b100000000000000000000010010000000000000000; + n1466[1846] = 42'b100000000000000000000011000010000000000000; + n1466[1845] = 42'b000000000000000000000000000110000000000000; + n1466[1844] = 42'b100000000000000000000000000000010000000100; + n1466[1843] = 42'b000000000000000000000001110000000000000000; + n1466[1842] = 42'b100000001001010000000000000000010010001100; + n1466[1841] = 42'b101000000000000000000000000000000000001110; + n1466[1840] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1839] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1838] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1837] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1836] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1835] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1834] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1833] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1832] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1831] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1830] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1829] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1828] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1827] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1826] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1825] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1824] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1823] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1822] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1821] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1820] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1819] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1818] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1817] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1816] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1815] = 42'b100000000000000000000010010000000000000000; + n1466[1814] = 42'b100000000000000000000010110010000000000000; + n1466[1813] = 42'b000000000000000000000000000110000000000000; + n1466[1812] = 42'b100000000000000000000000000000010000000100; + n1466[1811] = 42'b000000000000000000000001110000000000000000; + n1466[1810] = 42'b100000001001010000000000000000010010001100; + n1466[1809] = 42'b101000000000000000000000000000000000001110; + n1466[1808] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1807] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1806] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1805] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1804] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1803] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1802] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1801] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1800] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1799] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1798] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1797] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1796] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1795] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1794] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1793] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1792] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1791] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1790] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1789] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1788] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1787] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1786] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1785] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1784] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1783] = 42'b100000000000000000000010010000000000000000; + n1466[1782] = 42'b000000000000000000000000110000000000000000; + n1466[1781] = 42'b100000000000000000000000100000000000001100; + n1466[1780] = 42'b100000000000000000000001010010000000001100; + n1466[1779] = 42'b000000000000000000000000000000000000000000; + n1466[1778] = 42'b100000000000000000000000000000010000000100; + n1466[1777] = 42'b000000000000000000000001110000000000000000; + n1466[1776] = 42'b100000000101010000000000000000010010001100; + n1466[1775] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1774] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1773] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1772] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1771] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1770] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1769] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1768] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1767] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1766] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1765] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1764] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1763] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1762] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1761] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1760] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1759] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1758] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1757] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1756] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1755] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1754] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1753] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1752] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1751] = 42'b100000000000000000000010010000000000000000; + n1466[1750] = 42'b000000000000000000000000000000000000000000; + n1466[1749] = 42'b100000000000000000000000000000010000001100; + n1466[1748] = 42'b000000000000000000000001110000000000000000; + n1466[1747] = 42'b100000000101010000000000000000010010001100; + n1466[1746] = 42'b101000000000000000000000000000000000001110; + n1466[1745] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1744] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1743] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1742] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1741] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1740] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1739] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1738] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1737] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1736] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1735] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1734] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1733] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1732] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1731] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1730] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1729] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1728] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1727] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1726] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1725] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1724] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1723] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1722] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1721] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1720] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1719] = 42'b100000000000000000000010000000010000000000; + n1466[1718] = 42'b000000000000000000000001110000000000000000; + n1466[1717] = 42'b100000000101010000000000000000010010001100; + n1466[1716] = 42'b101000000000000000000000000000000000001110; + n1466[1715] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1714] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1713] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1712] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1711] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1710] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1709] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1708] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1707] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1706] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1705] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1704] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1703] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1702] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1701] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1700] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1699] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1698] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1697] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1696] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1695] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1694] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1693] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1692] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1691] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1690] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1689] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1688] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1687] = 42'b100000000000000000000010010000000000000000; + n1466[1686] = 42'b100000000000000000000010000010000000000000; + n1466[1685] = 42'b000000000000000000000000000000000000000000; + n1466[1684] = 42'b100000000000000000000000000000010000000100; + n1466[1683] = 42'b000000000000000000000001110000000000000000; + n1466[1682] = 42'b100000000101010000000000000000010010001100; + n1466[1681] = 42'b101000000000000000000000000000000000001110; + n1466[1680] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1679] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1678] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1677] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1676] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1675] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1674] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1673] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1672] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1671] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1670] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1669] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1668] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1667] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1666] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1665] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1664] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1663] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1662] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1661] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1660] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1659] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1658] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1657] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1656] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1655] = 42'b100000000000000000000010010000000000000000; + n1466[1654] = 42'b000000000000000000000000000000000000000000; + n1466[1653] = 42'b100000000000000000000000100000000000001100; + n1466[1652] = 42'b100000000000000000000001100010000000001100; + n1466[1651] = 42'b000000000000000000000000000110000000000000; + n1466[1650] = 42'b100000000000000000000000000000010000000100; + n1466[1649] = 42'b000000000000000000000001110000000000000000; + n1466[1648] = 42'b100000000101010000000000000000010010001100; + n1466[1647] = 42'b100000000000000000000010010000000000000000; + n1466[1646] = 42'b000000000000000000000000000000000000000000; + n1466[1645] = 42'b100000000000000000000000100000000000001100; + n1466[1644] = 42'b100000000000000000000001010010000000001100; + n1466[1643] = 42'b000000000000000000000000000000000000000000; + n1466[1642] = 42'b100000000000000000000000000000010000000100; + n1466[1641] = 42'b000000000000000000000001110000000000000000; + n1466[1640] = 42'b100000000101010000000000000000010010001100; + n1466[1639] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1638] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1637] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1636] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1635] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1634] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1633] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1632] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1631] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1630] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1629] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1628] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1627] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1626] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1625] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1624] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1623] = 42'b100000000000000000000010010000000000000000; + n1466[1622] = 42'b000000000000000000000000110000000000000000; + n1466[1621] = 42'b100000000000000000000000000000010000001100; + n1466[1620] = 42'b000000000000000000000001110000000000000000; + n1466[1619] = 42'b100000000101010000000000000000010010001100; + n1466[1618] = 42'b101000000000000000000000000000000000001110; + n1466[1617] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1616] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1615] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1614] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1613] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1612] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1611] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1610] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1609] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1608] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1607] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1606] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1605] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1604] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1603] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1602] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1601] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1600] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1599] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1598] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1597] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1596] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1595] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1594] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1593] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1592] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1591] = 42'b100000000000000000000010010000000000000000; + n1466[1590] = 42'b100000000000000000000011000010000000000000; + n1466[1589] = 42'b000000000000000000000000000110000000000000; + n1466[1588] = 42'b100000000000000000000000000000010000000100; + n1466[1587] = 42'b000000000000000000000001110000000000000000; + n1466[1586] = 42'b100000000101010000000000000000010010001100; + n1466[1585] = 42'b101000000000000000000000000000000000001110; + n1466[1584] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1583] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1582] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1581] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1580] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1579] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1578] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1577] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1576] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1575] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1574] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1573] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1572] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1571] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1570] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1569] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1568] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1567] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1566] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1565] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1564] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1563] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1562] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1561] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1560] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1559] = 42'b100000000000000000000010010000000000000000; + n1466[1558] = 42'b100000000000000000000010110010000000000000; + n1466[1557] = 42'b000000000000000000000000000110000000000000; + n1466[1556] = 42'b100000000000000000000000000000010000000100; + n1466[1555] = 42'b000000000000000000000001110000000000000000; + n1466[1554] = 42'b100000000101010000000000000000010010001100; + n1466[1553] = 42'b101000000000000000000000000000000000001110; + n1466[1552] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1551] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1550] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1549] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1548] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1547] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1546] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1545] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1544] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1543] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1542] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1541] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1540] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1539] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1538] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1537] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1536] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1535] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1534] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1533] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1532] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1531] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1530] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1529] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1528] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1527] = 42'b100000000000000000000010010000000000000000; + n1466[1526] = 42'b000000000000000000000000110000000000000000; + n1466[1525] = 42'b100000000000000000000000100000000000001100; + n1466[1524] = 42'b100000000000000000000001010010000000001100; + n1466[1523] = 42'b000000000000000000000000000000000000000000; + n1466[1522] = 42'b100000000000000000000000000000010000000100; + n1466[1521] = 42'b000000000000000000000001110000000000000000; + n1466[1520] = 42'b100000001101010000000000000000010010001100; + n1466[1519] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1518] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1517] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1516] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1515] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1514] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1513] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1512] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1511] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1510] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1509] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1508] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1507] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1506] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1505] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1504] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1503] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1502] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1501] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1500] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1499] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1498] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1497] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1496] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1495] = 42'b100000000000000000000010010000000000000000; + n1466[1494] = 42'b000000000000000000000000000000000000000000; + n1466[1493] = 42'b100000000000000000000000000000010000001100; + n1466[1492] = 42'b000000000000000000000001110000000000000000; + n1466[1491] = 42'b100000001101010000000000000000010010001100; + n1466[1490] = 42'b101000000000000000000000000000000000001110; + n1466[1489] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1488] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1487] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1486] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1485] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1484] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1483] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1482] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1481] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1480] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1479] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1478] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1477] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1476] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1475] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1474] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1473] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1472] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1471] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1470] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1469] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1468] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1467] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1466] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1465] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1464] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1463] = 42'b100000000000000000000010000000010000000000; + n1466[1462] = 42'b000000000000000000000001110000000000000000; + n1466[1461] = 42'b100000001101010000000000000000010010001100; + n1466[1460] = 42'b101000000000000000000000000000000000001110; + n1466[1459] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1458] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1457] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1456] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1455] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1454] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1453] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1452] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1451] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1450] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1449] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1448] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1447] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1446] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1445] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1444] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1443] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1442] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1441] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1440] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1439] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1438] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1437] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1436] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1435] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1434] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1433] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1432] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1431] = 42'b100000000000000000000010010000000000000000; + n1466[1430] = 42'b100000000000000000000010000010000000000000; + n1466[1429] = 42'b000000000000000000000000000000000000000000; + n1466[1428] = 42'b100000000000000000000000000000010000000100; + n1466[1427] = 42'b000000000000000000000001110000000000000000; + n1466[1426] = 42'b100000001101010000000000000000010010001100; + n1466[1425] = 42'b101000000000000000000000000000000000001110; + n1466[1424] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1423] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1422] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1421] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1420] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1419] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1418] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1417] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1416] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1415] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1414] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1413] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1412] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1411] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1410] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1409] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1408] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1407] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1406] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1405] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1404] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1403] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1402] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1401] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1400] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1399] = 42'b100000000000000000000010010000000000000000; + n1466[1398] = 42'b000000000000000000000000000000000000000000; + n1466[1397] = 42'b100000000000000000000000100000000000001100; + n1466[1396] = 42'b100000000000000000000001100010000000001100; + n1466[1395] = 42'b000000000000000000000000000110000000000000; + n1466[1394] = 42'b100000000000000000000000000000010000000100; + n1466[1393] = 42'b000000000000000000000001110000000000000000; + n1466[1392] = 42'b100000001101010000000000000000010010001100; + n1466[1391] = 42'b100000000000000000000010010000000000000000; + n1466[1390] = 42'b000000000000000000000000000000000000000000; + n1466[1389] = 42'b100000000000000000000000100000000000001100; + n1466[1388] = 42'b100000000000000000000001010010000000001100; + n1466[1387] = 42'b000000000000000000000000000000000000000000; + n1466[1386] = 42'b100000000000000000000000000000010000000100; + n1466[1385] = 42'b000000000000000000000001110000000000000000; + n1466[1384] = 42'b100000001101010000000000000000010010001100; + n1466[1383] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1382] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1381] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1380] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1379] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1378] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1377] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1376] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1375] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1374] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1373] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1372] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1371] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1370] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1369] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1368] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1367] = 42'b100000000000000000000010010000000000000000; + n1466[1366] = 42'b000000000000000000000000110000000000000000; + n1466[1365] = 42'b100000000000000000000000000000010000001100; + n1466[1364] = 42'b000000000000000000000001110000000000000000; + n1466[1363] = 42'b100000001101010000000000000000010010001100; + n1466[1362] = 42'b101000000000000000000000000000000000001110; + n1466[1361] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1360] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1359] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1358] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1357] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1356] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1355] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1354] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1353] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1352] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1351] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1350] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1349] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1348] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1347] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1346] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1345] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1344] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1343] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1342] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1341] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1340] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1339] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1338] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1337] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1336] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1335] = 42'b100000000000000000000010010000000000000000; + n1466[1334] = 42'b100000000000000000000011000010000000000000; + n1466[1333] = 42'b000000000000000000000000000110000000000000; + n1466[1332] = 42'b100000000000000000000000000000010000000100; + n1466[1331] = 42'b000000000000000000000001110000000000000000; + n1466[1330] = 42'b100000001101010000000000000000010010001100; + n1466[1329] = 42'b101000000000000000000000000000000000001110; + n1466[1328] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1327] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1326] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1325] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1324] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1323] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1322] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1321] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1320] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1319] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1318] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1317] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1316] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1315] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1314] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1313] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1312] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1311] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1310] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1309] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1308] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1307] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1306] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1305] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1304] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1303] = 42'b100000000000000000000010010000000000000000; + n1466[1302] = 42'b100000000000000000000010110010000000000000; + n1466[1301] = 42'b000000000000000000000000000110000000000000; + n1466[1300] = 42'b100000000000000000000000000000010000000100; + n1466[1299] = 42'b000000000000000000000001110000000000000000; + n1466[1298] = 42'b100000001101010000000000000000010010001100; + n1466[1297] = 42'b101000000000000000000000000000000000001110; + n1466[1296] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1295] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1294] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1293] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1292] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1291] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1290] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1289] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1288] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1287] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1286] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1285] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1284] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1283] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1282] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1281] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1280] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1279] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1278] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1277] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1276] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1275] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1274] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1273] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1272] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1271] = 42'b100000000000000000000010010000000000000000; + n1466[1270] = 42'b000000000000000000000000110000000000000000; + n1466[1269] = 42'b100000000000000000000000100000000000001100; + n1466[1268] = 42'b100000000000000000000001010010000000001100; + n1466[1267] = 42'b000000000000000000000000000000000000000000; + n1466[1266] = 42'b100000000000000000000000000000010000000100; + n1466[1265] = 42'b000000000000000000000001110000000000000000; + n1466[1264] = 42'b100000010001010000000000000000011010001100; + n1466[1263] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1262] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1261] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1260] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1259] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1258] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1257] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1256] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1255] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1254] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1253] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1252] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1251] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1250] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1249] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1248] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1247] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1246] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1245] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1244] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1243] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1242] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1241] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1240] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1239] = 42'b100000000000000000000010010000000000000000; + n1466[1238] = 42'b000000000000000000000000000000000000000000; + n1466[1237] = 42'b100000000000000000000000000000010000001100; + n1466[1236] = 42'b000000000000000000000001110000000000000000; + n1466[1235] = 42'b100000010001010000000000000000011010001100; + n1466[1234] = 42'b101000000000000000000000000000000000001101; + n1466[1233] = 42'b000000000000000000000000000000000000000010; + n1466[1232] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1231] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1230] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1229] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1228] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1227] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1226] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1225] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1224] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1223] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1222] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1221] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1220] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1219] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1218] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1217] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1216] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1215] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1214] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1213] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1212] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1211] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1210] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1209] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1208] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1207] = 42'b100000000000000000000010000000010000000000; + n1466[1206] = 42'b000000000000000000000001110000000000000000; + n1466[1205] = 42'b100000010001010000000000000000011010001100; + n1466[1204] = 42'b101000000000000000000000000000000000001101; + n1466[1203] = 42'b000000000000000000000000000000000000000010; + n1466[1202] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1201] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1200] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1199] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1198] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1197] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1196] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1195] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1194] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1193] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1192] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1191] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1190] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1189] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1188] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1187] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1186] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1185] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1184] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1183] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1182] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1181] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1180] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1179] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1178] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1177] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1176] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1175] = 42'b100000000000000000000010010000000000000000; + n1466[1174] = 42'b100000000000000000000010000010000000000000; + n1466[1173] = 42'b000000000000000000000000000000000000000000; + n1466[1172] = 42'b100000000000000000000000000000010000000100; + n1466[1171] = 42'b000000000000000000000001110000000000000000; + n1466[1170] = 42'b100000010001010000000000000000011010001100; + n1466[1169] = 42'b101000000000000000000000000000000000001101; + n1466[1168] = 42'b000000000000000000000000000000000000000010; + n1466[1167] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1166] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1165] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1164] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1163] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1162] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1161] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1160] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1159] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1158] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1157] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1156] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1155] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1154] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1153] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1152] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1151] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1150] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1149] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1148] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1147] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1146] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1145] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1144] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1143] = 42'b100000000000000000000010010000000000000000; + n1466[1142] = 42'b000000000000000000000000000000000000000000; + n1466[1141] = 42'b100000000000000000000000100000000000001100; + n1466[1140] = 42'b100000000000000000000001100010000000001100; + n1466[1139] = 42'b000000000000000000000000000110000000000000; + n1466[1138] = 42'b100000000000000000000000000000010000000100; + n1466[1137] = 42'b000000000000000000000001110000000000000000; + n1466[1136] = 42'b100000010001010000000000000000011010001100; + n1466[1135] = 42'b100000000000000000000010010000000000000000; + n1466[1134] = 42'b000000000000000000000000000000000000000000; + n1466[1133] = 42'b100000000000000000000000100000000000001100; + n1466[1132] = 42'b100000000000000000000001010010000000001100; + n1466[1131] = 42'b000000000000000000000000000000000000000000; + n1466[1130] = 42'b100000000000000000000000000000010000000100; + n1466[1129] = 42'b000000000000000000000001110000000000000000; + n1466[1128] = 42'b100000010001010000000000000000011010001100; + n1466[1127] = 42'b100000000000000010000010000000000000000000; + n1466[1126] = 42'b100000000000000000000010000000000001100000; + n1466[1125] = 42'b000000000000000000000000000000000000000000; + n1466[1124] = 42'b000000000000000000000000000000000000000000; + n1466[1123] = 42'b000000011000010000000000000000000000000000; + n1466[1122] = 42'b000001000010100000000000000000000000000000; + n1466[1121] = 42'b100000011100100100000000000001000000011000; + n1466[1120] = 42'b000001000110000000000000000000000000100000; + n1466[1119] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1118] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1117] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1116] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1115] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1114] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1113] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1112] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1111] = 42'b100000000000000000000010010000000000000000; + n1466[1110] = 42'b000000000000000000000000110000000000000000; + n1466[1109] = 42'b100000000000000000000000000000010000001100; + n1466[1108] = 42'b000000000000000000000001110000000000000000; + n1466[1107] = 42'b100000010001010000000000000000011010001100; + n1466[1106] = 42'b101000000000000000000000000000000000001101; + n1466[1105] = 42'b000000000000000000000000000000000000000010; + n1466[1104] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1103] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1102] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1101] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1100] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1099] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1098] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1097] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1096] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1095] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1094] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1093] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1092] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1091] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1090] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1089] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1088] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1087] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1086] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1085] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1084] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1083] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1082] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1081] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1080] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1079] = 42'b100000000000000000000010010000000000000000; + n1466[1078] = 42'b100000000000000000000011000010000000000000; + n1466[1077] = 42'b000000000000000000000000000110000000000000; + n1466[1076] = 42'b100000000000000000000000000000010000000100; + n1466[1075] = 42'b000000000000000000000001110000000000000000; + n1466[1074] = 42'b100000010001010000000000000000011010001100; + n1466[1073] = 42'b101000000000000000000000000000000000001101; + n1466[1072] = 42'b000000000000000000000000000000000000000010; + n1466[1071] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1070] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1069] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1068] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1067] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1066] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1065] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1064] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1063] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1062] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1061] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1060] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1059] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1058] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1057] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1056] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1055] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1054] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1053] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1052] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1051] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1050] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1049] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1048] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1047] = 42'b100000000000000000000010010000000000000000; + n1466[1046] = 42'b100000000000000000000010110010000000000000; + n1466[1045] = 42'b000000000000000000000000000110000000000000; + n1466[1044] = 42'b100000000000000000000000000000010000000100; + n1466[1043] = 42'b000000000000000000000001110000000000000000; + n1466[1042] = 42'b100000010001010000000000000000011010001100; + n1466[1041] = 42'b101000000000000000000000000000000000001101; + n1466[1040] = 42'b000000000000000000000000000000000000000010; + n1466[1039] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1038] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1037] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1036] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1035] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1034] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1033] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1032] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1031] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1030] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1029] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1028] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1027] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1026] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1025] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1024] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1023] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1022] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1021] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1020] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1019] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1018] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1017] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1016] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1015] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1014] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1013] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1012] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1011] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1010] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1009] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1008] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1007] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1006] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1005] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1004] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1003] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1002] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1001] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1000] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[999] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[998] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[997] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[996] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[995] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[994] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[993] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[992] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[991] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[990] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[989] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[988] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[987] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[986] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[985] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[984] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[983] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[982] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[981] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[980] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[979] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[978] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[977] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[976] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[975] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[974] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[973] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[972] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[971] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[970] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[969] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[968] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[967] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[966] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[965] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[964] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[963] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[962] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[961] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[960] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[959] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[958] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[957] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[956] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[955] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[954] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[953] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[952] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[951] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[950] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[949] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[948] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[947] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[946] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[945] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[944] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[943] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[942] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[941] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[940] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[939] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[938] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[937] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[936] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[935] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[934] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[933] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[932] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[931] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[930] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[929] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[928] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[927] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[926] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[925] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[924] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[923] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[922] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[921] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[920] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[919] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[918] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[917] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[916] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[915] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[914] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[913] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[912] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[911] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[910] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[909] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[908] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[907] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[906] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[905] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[904] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[903] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[902] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[901] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[900] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[899] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[898] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[897] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[896] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[895] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[894] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[893] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[892] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[891] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[890] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[889] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[888] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[887] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[886] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[885] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[884] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[883] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[882] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[881] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[880] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[879] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[878] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[877] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[876] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[875] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[874] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[873] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[872] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[871] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[870] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[869] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[868] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[867] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[866] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[865] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[864] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[863] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[862] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[861] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[860] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[859] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[858] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[857] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[856] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[855] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[854] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[853] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[852] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[851] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[850] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[849] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[848] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[847] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[846] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[845] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[844] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[843] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[842] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[841] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[840] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[839] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[838] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[837] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[836] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[835] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[834] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[833] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[832] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[831] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[830] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[829] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[828] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[827] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[826] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[825] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[824] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[823] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[822] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[821] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[820] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[819] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[818] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[817] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[816] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[815] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[814] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[813] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[812] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[811] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[810] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[809] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[808] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[807] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[806] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[805] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[804] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[803] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[802] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[801] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[800] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[799] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[798] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[797] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[796] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[795] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[794] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[793] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[792] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[791] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[790] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[789] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[788] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[787] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[786] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[785] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[784] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[783] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[782] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[781] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[780] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[779] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[778] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[777] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[776] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[775] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[774] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[773] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[772] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[771] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[770] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[769] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[768] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[767] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[766] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[765] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[764] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[763] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[762] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[761] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[760] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[759] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[758] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[757] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[756] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[755] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[754] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[753] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[752] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[751] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[750] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[749] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[748] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[747] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[746] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[745] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[744] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[743] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[742] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[741] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[740] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[739] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[738] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[737] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[736] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[735] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[734] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[733] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[732] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[731] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[730] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[729] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[728] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[727] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[726] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[725] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[724] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[723] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[722] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[721] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[720] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[719] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[718] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[717] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[716] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[715] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[714] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[713] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[712] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[711] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[710] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[709] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[708] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[707] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[706] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[705] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[704] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[703] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[702] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[701] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[700] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[699] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[698] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[697] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[696] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[695] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[694] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[693] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[692] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[691] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[690] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[689] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[688] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[687] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[686] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[685] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[684] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[683] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[682] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[681] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[680] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[679] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[678] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[677] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[676] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[675] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[674] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[673] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[672] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[671] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[670] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[669] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[668] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[667] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[666] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[665] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[664] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[663] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[662] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[661] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[660] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[659] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[658] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[657] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[656] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[655] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[654] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[653] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[652] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[651] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[650] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[649] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[648] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[647] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[646] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[645] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[644] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[643] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[642] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[641] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[640] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[639] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[638] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[637] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[636] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[635] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[634] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[633] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[632] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[631] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[630] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[629] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[628] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[627] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[626] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[625] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[624] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[623] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[622] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[621] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[620] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[619] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[618] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[617] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[616] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[615] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[614] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[613] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[612] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[611] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[610] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[609] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[608] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[607] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[606] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[605] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[604] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[603] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[602] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[601] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[600] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[599] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[598] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[597] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[596] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[595] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[594] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[593] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[592] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[591] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[590] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[589] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[588] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[587] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[586] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[585] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[584] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[583] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[582] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[581] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[580] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[579] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[578] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[577] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[576] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[575] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[574] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[573] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[572] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[571] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[570] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[569] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[568] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[567] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[566] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[565] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[564] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[563] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[562] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[561] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[560] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[559] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[558] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[557] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[556] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[555] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[554] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[553] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[552] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[551] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[550] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[549] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[548] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[547] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[546] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[545] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[544] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[543] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[542] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[541] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[540] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[539] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[538] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[537] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[536] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[535] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[534] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[533] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[532] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[531] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[530] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[529] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[528] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[527] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[526] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[525] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[524] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[523] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[522] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[521] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[520] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[519] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[518] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[517] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[516] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[515] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[514] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[513] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[512] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[511] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[510] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[509] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[508] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[507] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[506] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[505] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[504] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[503] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[502] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[501] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[500] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[499] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[498] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[497] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[496] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[495] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[494] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[493] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[492] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[491] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[490] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[489] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[488] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[487] = 42'b100000000000000010000010000000000000000000; + n1466[486] = 42'b100000000000000000000010000000000001100000; + n1466[485] = 42'b000000000000000000000000000000000000000000; + n1466[484] = 42'b000000000000000000000000000000000000000000; + n1466[483] = 42'b000000011000010000000000000000000000000000; + n1466[482] = 42'b000001000010100000000000000000000000000000; + n1466[481] = 42'b100000011000100100000000000001000000011000; + n1466[480] = 42'b000001000010000000000000000000000000100000; + n1466[479] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[478] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[477] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[476] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[475] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[474] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[473] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[472] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[471] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[470] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[469] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[468] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[467] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[466] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[465] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[464] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[463] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[462] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[461] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[460] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[459] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[458] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[457] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[456] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[455] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[454] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[453] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[452] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[451] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[450] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[449] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[448] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[447] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[446] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[445] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[444] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[443] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[442] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[441] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[440] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[439] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[438] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[437] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[436] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[435] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[434] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[433] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[432] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[431] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[430] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[429] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[428] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[427] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[426] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[425] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[424] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[423] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[422] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[421] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[420] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[419] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[418] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[417] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[416] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[415] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[414] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[413] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[412] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[411] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[410] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[409] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[408] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[407] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[406] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[405] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[404] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[403] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[402] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[401] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[400] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[399] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[398] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[397] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[396] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[395] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[394] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[393] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[392] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[391] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[390] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[389] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[388] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[387] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[386] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[385] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[384] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[383] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[382] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[381] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[380] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[379] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[378] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[377] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[376] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[375] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[374] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[373] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[372] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[371] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[370] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[369] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[368] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[367] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[366] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[365] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[364] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[363] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[362] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[361] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[360] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[359] = 42'b100000000000000010000010000000000000000000; + n1466[358] = 42'b100000000000000000000010000000000001100000; + n1466[357] = 42'b000000000000000000000000000000000000000000; + n1466[356] = 42'b000000000000000000000000000000000000000000; + n1466[355] = 42'b000000011000010000000000000000000000000000; + n1466[354] = 42'b000001000010100000000000000000000000000000; + n1466[353] = 42'b100000011100100100000000000001000000011000; + n1466[352] = 42'b000001000110000000000000000000000000100000; + n1466[351] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[350] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[349] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[348] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[347] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[346] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[345] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[344] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[343] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[342] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[341] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[340] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[339] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[338] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[337] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[336] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[335] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[334] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[333] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[332] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[331] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[330] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[329] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[328] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[327] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[326] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[325] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[324] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[323] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[322] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[321] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[320] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[319] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[318] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[317] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[316] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[315] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[314] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[313] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[312] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[311] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[310] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[309] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[308] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[307] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[306] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[305] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[304] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[303] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[302] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[301] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[300] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[299] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[298] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[297] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[296] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[295] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[294] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[293] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[292] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[291] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[290] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[289] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[288] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[287] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[286] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[285] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[284] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[283] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[282] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[281] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[280] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[279] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[278] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[277] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[276] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[275] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[274] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[273] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[272] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[271] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[270] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[269] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[268] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[267] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[266] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[265] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[264] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[263] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[262] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[261] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[260] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[259] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[258] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[257] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[256] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[255] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[254] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[253] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[252] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[251] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[250] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[249] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[248] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[247] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[246] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[245] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[244] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[243] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[242] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[241] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[240] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[239] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[238] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[237] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[236] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[235] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[234] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[233] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[232] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[231] = 42'b100000000000000010000010000000000000000000; + n1466[230] = 42'b100000000000000000000010000000000001100000; + n1466[229] = 42'b000000000000000000000000000000000000000000; + n1466[228] = 42'b000000000000000000000000000000000000000000; + n1466[227] = 42'b000000011000010000000000000000000000000000; + n1466[226] = 42'b000001000010100000000000000000000000000000; + n1466[225] = 42'b100000011100100100000000000001000000011000; + n1466[224] = 42'b000001000110000000000000000000000000100000; + n1466[223] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[222] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[221] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[220] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[219] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[218] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[217] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[216] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[215] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[214] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[213] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[212] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[211] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[210] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[209] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[208] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[207] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[206] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[205] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[204] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[203] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[202] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[201] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[200] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[199] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[198] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[197] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[196] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[195] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[194] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[193] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[192] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[191] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[190] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[189] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[188] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[187] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[186] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[185] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[184] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[183] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[182] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[181] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[180] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[179] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[178] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[177] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[176] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[175] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[174] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[173] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[172] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[171] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[170] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[169] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[168] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[167] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[166] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[165] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[164] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[163] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[162] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[161] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[160] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[159] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[158] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[157] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[156] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[155] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[154] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[153] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[152] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[151] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[150] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[149] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[148] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[147] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[146] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[145] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[144] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[143] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[142] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[141] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[140] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[139] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[138] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[137] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[136] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[135] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[134] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[133] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[132] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[131] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[130] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[129] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[128] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[127] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[126] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[125] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[124] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[123] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[122] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[121] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[120] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[119] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[118] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[117] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[116] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[115] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[114] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[113] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[112] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[111] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[110] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[109] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[108] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[107] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[106] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[105] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[104] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[103] = 42'b100000000000000010000010000000000000000000; + n1466[102] = 42'b100000000000000000000010000000000001100000; + n1466[101] = 42'b000000000000000000000000000000000000000000; + n1466[100] = 42'b000000000000000000000000000000000000000000; + n1466[99] = 42'b000000011000010000000000000000000000000000; + n1466[98] = 42'b000001000010100000000000000000000000000000; + n1466[97] = 42'b100000011000100100000000000001000000011000; + n1466[96] = 42'b000001000010000000000000000000000000100000; + n1466[95] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[94] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[93] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[92] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[91] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[90] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[89] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[88] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[87] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[86] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[85] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[84] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[83] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[82] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[81] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[80] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[79] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[78] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[77] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[76] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[75] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[74] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[73] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[72] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[71] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[70] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[69] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[68] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[67] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[66] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[65] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[64] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[63] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[62] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[61] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[60] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[59] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[58] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[57] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[56] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[55] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[54] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[53] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[52] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[51] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[50] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[49] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[48] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[47] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[46] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[45] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[44] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[43] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[42] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[41] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[40] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[39] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[38] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[37] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[36] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[35] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[34] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[33] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[32] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[31] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[30] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[29] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[28] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[27] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[26] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[25] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[24] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[23] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[22] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[21] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[20] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[19] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[18] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[17] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[16] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[15] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[14] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[13] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[12] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[11] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[10] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[9] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[8] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[7] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[6] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[5] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[4] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[3] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[2] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[1] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1466[0] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + end + assign n1467_data = n1466[n1414_o]; + /* HUC6280_MC.vhd:6986:54 */ + /* HUC6280_MC.vhd:6986:53 */ + reg [41:0] n1468[2047:0] ; // memory + initial begin + n1468[2047] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[2046] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[2045] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[2044] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[2043] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[2042] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[2041] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[2040] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[2039] = 42'b101000000000000000000000000000000000001110; + n1468[2038] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[2037] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[2036] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[2035] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[2034] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[2033] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[2032] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[2031] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[2030] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[2029] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[2028] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[2027] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[2026] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[2025] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[2024] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[2023] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[2022] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[2021] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[2020] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[2019] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[2018] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[2017] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[2016] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[2015] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[2014] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[2013] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[2012] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[2011] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[2010] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[2009] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[2008] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[2007] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[2006] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[2005] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[2004] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[2003] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[2002] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[2001] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[2000] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1999] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1998] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1997] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1996] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1995] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1994] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1993] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1992] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1991] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1990] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1989] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1988] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1987] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1986] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1985] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1984] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1983] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1982] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1981] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1980] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1979] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1978] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1977] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1976] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1975] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1974] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1973] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1972] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1971] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1970] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1969] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1968] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1967] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1966] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1965] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1964] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1963] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1962] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1961] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1960] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1959] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1958] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1957] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1956] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1955] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1954] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1953] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1952] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1951] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1950] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1949] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1948] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1947] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1946] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1945] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1944] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1943] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1942] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1941] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1940] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1939] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1938] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1937] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1936] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1935] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1934] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1933] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1932] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1931] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1930] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1929] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1928] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1927] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1926] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1925] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1924] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1923] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1922] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1921] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1920] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1919] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1918] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1917] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1916] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1915] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1914] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1913] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1912] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1911] = 42'b101000000000000000000000000000000000001110; + n1468[1910] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1909] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1908] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1907] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1906] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1905] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1904] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1903] = 42'b101000000000000000000000000000000000001110; + n1468[1902] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1901] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1900] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1899] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1898] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1897] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1896] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1895] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1894] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1893] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1892] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1891] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1890] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1889] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1888] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1887] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1886] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1885] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1884] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1883] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1882] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1881] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1880] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1879] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1878] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1877] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1876] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1875] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1874] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1873] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1872] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1871] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1870] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1869] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1868] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1867] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1866] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1865] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1864] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1863] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1862] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1861] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1860] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1859] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1858] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1857] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1856] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1855] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1854] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1853] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1852] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1851] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1850] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1849] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1848] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1847] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1846] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1845] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1844] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1843] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1842] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1841] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1840] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1839] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1838] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1837] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1836] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1835] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1834] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1833] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1832] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1831] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1830] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1829] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1828] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1827] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1826] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1825] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1824] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1823] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1822] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1821] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1820] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1819] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1818] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1817] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1816] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1815] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1814] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1813] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1812] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1811] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1810] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1809] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1808] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1807] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1806] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1805] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1804] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1803] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1802] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1801] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1800] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1799] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1798] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1797] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1796] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1795] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1794] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1793] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1792] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1791] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1790] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1789] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1788] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1787] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1786] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1785] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1784] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1783] = 42'b101000000000000000000000000000000000001110; + n1468[1782] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1781] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1780] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1779] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1778] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1777] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1776] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1775] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1774] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1773] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1772] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1771] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1770] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1769] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1768] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1767] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1766] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1765] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1764] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1763] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1762] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1761] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1760] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1759] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1758] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1757] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1756] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1755] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1754] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1753] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1752] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1751] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1750] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1749] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1748] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1747] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1746] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1745] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1744] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1743] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1742] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1741] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1740] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1739] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1738] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1737] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1736] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1735] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1734] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1733] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1732] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1731] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1730] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1729] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1728] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1727] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1726] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1725] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1724] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1723] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1722] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1721] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1720] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1719] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1718] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1717] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1716] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1715] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1714] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1713] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1712] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1711] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1710] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1709] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1708] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1707] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1706] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1705] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1704] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1703] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1702] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1701] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1700] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1699] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1698] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1697] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1696] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1695] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1694] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1693] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1692] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1691] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1690] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1689] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1688] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1687] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1686] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1685] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1684] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1683] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1682] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1681] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1680] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1679] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1678] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1677] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1676] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1675] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1674] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1673] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1672] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1671] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1670] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1669] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1668] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1667] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1666] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1665] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1664] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1663] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1662] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1661] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1660] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1659] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1658] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1657] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1656] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1655] = 42'b101000000000000000000000000000000000001110; + n1468[1654] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1653] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1652] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1651] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1650] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1649] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1648] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1647] = 42'b101000000000000000000000000000000000001110; + n1468[1646] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1645] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1644] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1643] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1642] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1641] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1640] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1639] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1638] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1637] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1636] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1635] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1634] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1633] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1632] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1631] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1630] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1629] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1628] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1627] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1626] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1625] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1624] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1623] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1622] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1621] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1620] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1619] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1618] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1617] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1616] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1615] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1614] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1613] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1612] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1611] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1610] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1609] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1608] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1607] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1606] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1605] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1604] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1603] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1602] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1601] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1600] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1599] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1598] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1597] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1596] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1595] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1594] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1593] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1592] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1591] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1590] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1589] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1588] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1587] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1586] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1585] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1584] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1583] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1582] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1581] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1580] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1579] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1578] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1577] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1576] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1575] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1574] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1573] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1572] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1571] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1570] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1569] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1568] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1567] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1566] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1565] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1564] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1563] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1562] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1561] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1560] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1559] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1558] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1557] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1556] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1555] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1554] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1553] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1552] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1551] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1550] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1549] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1548] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1547] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1546] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1545] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1544] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1543] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1542] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1541] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1540] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1539] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1538] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1537] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1536] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1535] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1534] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1533] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1532] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1531] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1530] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1529] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1528] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1527] = 42'b101000000000000000000000000000000000001110; + n1468[1526] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1525] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1524] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1523] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1522] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1521] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1520] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1519] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1518] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1517] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1516] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1515] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1514] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1513] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1512] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1511] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1510] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1509] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1508] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1507] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1506] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1505] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1504] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1503] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1502] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1501] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1500] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1499] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1498] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1497] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1496] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1495] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1494] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1493] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1492] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1491] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1490] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1489] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1488] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1487] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1486] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1485] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1484] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1483] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1482] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1481] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1480] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1479] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1478] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1477] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1476] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1475] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1474] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1473] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1472] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1471] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1470] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1469] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1468] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1467] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1466] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1465] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1464] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1463] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1462] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1461] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1460] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1459] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1458] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1457] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1456] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1455] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1454] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1453] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1452] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1451] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1450] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1449] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1448] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1447] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1446] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1445] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1444] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1443] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1442] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1441] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1440] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1439] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1438] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1437] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1436] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1435] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1434] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1433] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1432] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1431] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1430] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1429] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1428] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1427] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1426] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1425] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1424] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1423] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1422] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1421] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1420] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1419] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1418] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1417] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1416] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1415] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1414] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1413] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1412] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1411] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1410] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1409] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1408] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1407] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1406] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1405] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1404] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1403] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1402] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1401] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1400] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1399] = 42'b101000000000000000000000000000000000001110; + n1468[1398] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1397] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1396] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1395] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1394] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1393] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1392] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1391] = 42'b101000000000000000000000000000000000001110; + n1468[1390] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1389] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1388] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1387] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1386] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1385] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1384] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1383] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1382] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1381] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1380] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1379] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1378] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1377] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1376] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1375] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1374] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1373] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1372] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1371] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1370] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1369] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1368] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1367] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1366] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1365] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1364] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1363] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1362] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1361] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1360] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1359] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1358] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1357] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1356] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1355] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1354] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1353] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1352] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1351] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1350] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1349] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1348] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1347] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1346] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1345] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1344] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1343] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1342] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1341] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1340] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1339] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1338] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1337] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1336] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1335] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1334] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1333] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1332] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1331] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1330] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1329] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1328] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1327] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1326] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1325] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1324] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1323] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1322] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1321] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1320] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1319] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1318] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1317] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1316] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1315] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1314] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1313] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1312] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1311] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1310] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1309] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1308] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1307] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1306] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1305] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1304] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1303] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1302] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1301] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1300] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1299] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1298] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1297] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1296] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1295] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1294] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1293] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1292] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1291] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1290] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1289] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1288] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1287] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1286] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1285] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1284] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1283] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1282] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1281] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1280] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1279] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1278] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1277] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1276] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1275] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1274] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1273] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1272] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1271] = 42'b101000000000000000000000000000000000001101; + n1468[1270] = 42'b000000000000000000000000000000000000000010; + n1468[1269] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1268] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1267] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1266] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1265] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1264] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1263] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1262] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1261] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1260] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1259] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1258] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1257] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1256] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1255] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1254] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1253] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1252] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1251] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1250] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1249] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1248] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1247] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1246] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1245] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1244] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1243] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1242] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1241] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1240] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1239] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1238] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1237] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1236] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1235] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1234] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1233] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1232] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1231] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1230] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1229] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1228] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1227] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1226] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1225] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1224] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1223] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1222] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1221] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1220] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1219] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1218] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1217] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1216] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1215] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1214] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1213] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1212] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1211] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1210] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1209] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1208] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1207] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1206] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1205] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1204] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1203] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1202] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1201] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1200] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1199] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1198] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1197] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1196] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1195] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1194] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1193] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1192] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1191] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1190] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1189] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1188] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1187] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1186] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1185] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1184] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1183] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1182] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1181] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1180] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1179] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1178] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1177] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1176] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1175] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1174] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1173] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1172] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1171] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1170] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1169] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1168] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1167] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1166] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1165] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1164] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1163] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1162] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1161] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1160] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1159] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1158] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1157] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1156] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1155] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1154] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1153] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1152] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1151] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1150] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1149] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1148] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1147] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1146] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1145] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1144] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1143] = 42'b101000000000000000000000000000000000001101; + n1468[1142] = 42'b000000000000000000000000000000000000000010; + n1468[1141] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1140] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1139] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1138] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1137] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1136] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1135] = 42'b101000000000000000000000000000000000001101; + n1468[1134] = 42'b100000000000000000000000000000000000000010; + n1468[1133] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1132] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1131] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1130] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1129] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1128] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1127] = 42'b101000011100111000000000000000000000011100; + n1468[1126] = 42'b000001000110010000000000000000000001000000; + n1468[1125] = 42'b000000011000010010000000000000000000000000; + n1468[1124] = 42'b000001000010100000000000000000000001100011; + n1468[1123] = 42'b100000000000000100100000000000000000001000; + n1468[1122] = 42'b100000000000000010100000000000000000001000; + n1468[1121] = 42'b100000000000001000000000000000000000001010; + n1468[1120] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1119] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1118] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1117] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1116] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1115] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1114] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1113] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1112] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1111] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1110] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1109] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1108] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1107] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1106] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1105] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1104] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1103] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1102] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1101] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1100] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1099] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1098] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1097] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1096] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1095] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1094] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1093] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1092] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1091] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1090] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1089] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1088] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1087] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1086] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1085] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1084] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1083] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1082] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1081] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1080] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1079] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1078] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1077] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1076] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1075] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1074] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1073] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1072] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1071] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1070] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1069] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1068] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1067] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1066] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1065] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1064] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1063] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1062] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1061] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1060] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1059] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1058] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1057] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1056] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1055] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1054] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1053] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1052] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1051] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1050] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1049] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1048] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1047] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1046] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1045] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1044] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1043] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1042] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1041] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1040] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1039] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1038] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1037] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1036] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1035] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1034] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1033] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1032] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1031] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1030] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1029] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1028] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1027] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1026] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1025] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1024] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1023] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1022] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1021] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1020] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1019] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1018] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1017] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1016] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1015] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1014] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1013] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1012] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1011] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1010] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1009] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1008] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1007] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1006] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1005] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1004] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1003] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1002] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1001] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1000] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[999] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[998] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[997] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[996] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[995] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[994] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[993] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[992] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[991] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[990] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[989] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[988] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[987] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[986] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[985] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[984] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[983] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[982] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[981] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[980] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[979] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[978] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[977] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[976] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[975] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[974] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[973] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[972] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[971] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[970] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[969] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[968] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[967] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[966] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[965] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[964] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[963] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[962] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[961] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[960] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[959] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[958] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[957] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[956] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[955] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[954] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[953] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[952] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[951] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[950] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[949] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[948] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[947] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[946] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[945] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[944] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[943] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[942] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[941] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[940] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[939] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[938] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[937] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[936] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[935] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[934] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[933] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[932] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[931] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[930] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[929] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[928] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[927] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[926] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[925] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[924] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[923] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[922] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[921] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[920] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[919] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[918] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[917] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[916] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[915] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[914] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[913] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[912] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[911] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[910] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[909] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[908] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[907] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[906] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[905] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[904] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[903] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[902] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[901] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[900] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[899] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[898] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[897] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[896] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[895] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[894] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[893] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[892] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[891] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[890] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[889] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[888] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[887] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[886] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[885] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[884] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[883] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[882] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[881] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[880] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[879] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[878] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[877] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[876] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[875] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[874] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[873] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[872] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[871] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[870] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[869] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[868] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[867] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[866] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[865] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[864] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[863] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[862] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[861] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[860] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[859] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[858] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[857] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[856] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[855] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[854] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[853] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[852] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[851] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[850] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[849] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[848] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[847] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[846] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[845] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[844] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[843] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[842] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[841] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[840] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[839] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[838] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[837] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[836] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[835] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[834] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[833] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[832] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[831] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[830] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[829] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[828] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[827] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[826] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[825] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[824] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[823] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[822] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[821] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[820] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[819] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[818] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[817] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[816] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[815] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[814] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[813] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[812] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[811] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[810] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[809] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[808] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[807] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[806] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[805] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[804] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[803] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[802] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[801] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[800] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[799] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[798] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[797] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[796] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[795] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[794] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[793] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[792] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[791] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[790] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[789] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[788] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[787] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[786] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[785] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[784] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[783] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[782] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[781] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[780] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[779] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[778] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[777] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[776] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[775] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[774] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[773] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[772] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[771] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[770] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[769] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[768] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[767] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[766] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[765] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[764] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[763] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[762] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[761] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[760] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[759] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[758] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[757] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[756] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[755] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[754] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[753] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[752] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[751] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[750] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[749] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[748] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[747] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[746] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[745] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[744] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[743] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[742] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[741] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[740] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[739] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[738] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[737] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[736] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[735] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[734] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[733] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[732] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[731] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[730] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[729] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[728] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[727] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[726] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[725] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[724] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[723] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[722] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[721] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[720] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[719] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[718] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[717] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[716] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[715] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[714] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[713] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[712] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[711] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[710] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[709] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[708] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[707] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[706] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[705] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[704] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[703] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[702] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[701] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[700] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[699] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[698] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[697] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[696] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[695] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[694] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[693] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[692] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[691] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[690] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[689] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[688] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[687] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[686] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[685] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[684] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[683] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[682] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[681] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[680] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[679] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[678] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[677] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[676] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[675] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[674] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[673] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[672] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[671] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[670] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[669] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[668] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[667] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[666] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[665] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[664] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[663] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[662] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[661] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[660] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[659] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[658] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[657] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[656] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[655] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[654] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[653] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[652] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[651] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[650] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[649] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[648] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[647] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[646] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[645] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[644] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[643] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[642] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[641] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[640] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[639] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[638] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[637] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[636] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[635] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[634] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[633] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[632] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[631] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[630] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[629] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[628] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[627] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[626] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[625] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[624] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[623] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[622] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[621] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[620] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[619] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[618] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[617] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[616] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[615] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[614] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[613] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[612] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[611] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[610] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[609] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[608] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[607] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[606] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[605] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[604] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[603] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[602] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[601] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[600] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[599] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[598] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[597] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[596] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[595] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[594] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[593] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[592] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[591] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[590] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[589] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[588] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[587] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[586] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[585] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[584] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[583] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[582] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[581] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[580] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[579] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[578] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[577] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[576] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[575] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[574] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[573] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[572] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[571] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[570] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[569] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[568] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[567] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[566] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[565] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[564] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[563] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[562] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[561] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[560] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[559] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[558] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[557] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[556] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[555] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[554] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[553] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[552] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[551] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[550] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[549] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[548] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[547] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[546] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[545] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[544] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[543] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[542] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[541] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[540] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[539] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[538] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[537] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[536] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[535] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[534] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[533] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[532] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[531] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[530] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[529] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[528] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[527] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[526] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[525] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[524] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[523] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[522] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[521] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[520] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[519] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[518] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[517] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[516] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[515] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[514] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[513] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[512] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[511] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[510] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[509] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[508] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[507] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[506] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[505] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[504] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[503] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[502] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[501] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[500] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[499] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[498] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[497] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[496] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[495] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[494] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[493] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[492] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[491] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[490] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[489] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[488] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[487] = 42'b101000011000111000000000000000000000011100; + n1468[486] = 42'b000001000010010000000000000000000001000000; + n1468[485] = 42'b000000011000010010000000000000000000000000; + n1468[484] = 42'b000001000010100000000000000000000001100011; + n1468[483] = 42'b100000000000000100100000000000000000001000; + n1468[482] = 42'b100000000000000010100000000000000000001000; + n1468[481] = 42'b100000000000001000000000000000000000001010; + n1468[480] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[479] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[478] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[477] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[476] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[475] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[474] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[473] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[472] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[471] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[470] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[469] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[468] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[467] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[466] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[465] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[464] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[463] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[462] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[461] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[460] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[459] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[458] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[457] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[456] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[455] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[454] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[453] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[452] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[451] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[450] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[449] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[448] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[447] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[446] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[445] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[444] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[443] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[442] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[441] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[440] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[439] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[438] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[437] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[436] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[435] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[434] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[433] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[432] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[431] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[430] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[429] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[428] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[427] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[426] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[425] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[424] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[423] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[422] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[421] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[420] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[419] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[418] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[417] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[416] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[415] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[414] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[413] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[412] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[411] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[410] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[409] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[408] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[407] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[406] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[405] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[404] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[403] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[402] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[401] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[400] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[399] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[398] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[397] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[396] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[395] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[394] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[393] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[392] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[391] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[390] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[389] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[388] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[387] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[386] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[385] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[384] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[383] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[382] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[381] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[380] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[379] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[378] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[377] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[376] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[375] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[374] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[373] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[372] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[371] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[370] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[369] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[368] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[367] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[366] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[365] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[364] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[363] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[362] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[361] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[360] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[359] = 42'b101000000000000000000000000000000000011100; + n1468[358] = 42'b000000000000000000000000000000000000000000; + n1468[357] = 42'b000000011000010010000000000000000000000000; + n1468[356] = 42'b000001000010100000000000000000000001100011; + n1468[355] = 42'b100000000000000100100000000000000000001000; + n1468[354] = 42'b100000000000000010100000000000000000001000; + n1468[353] = 42'b100000000000001000000000000000000000001010; + n1468[352] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[351] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[350] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[349] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[348] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[347] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[346] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[345] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[344] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[343] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[342] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[341] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[340] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[339] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[338] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[337] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[336] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[335] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[334] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[333] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[332] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[331] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[330] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[329] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[328] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[327] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[326] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[325] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[324] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[323] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[322] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[321] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[320] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[319] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[318] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[317] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[316] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[315] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[314] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[313] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[312] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[311] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[310] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[309] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[308] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[307] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[306] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[305] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[304] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[303] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[302] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[301] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[300] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[299] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[298] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[297] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[296] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[295] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[294] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[293] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[292] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[291] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[290] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[289] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[288] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[287] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[286] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[285] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[284] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[283] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[282] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[281] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[280] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[279] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[278] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[277] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[276] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[275] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[274] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[273] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[272] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[271] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[270] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[269] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[268] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[267] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[266] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[265] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[264] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[263] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[262] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[261] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[260] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[259] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[258] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[257] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[256] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[255] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[254] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[253] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[252] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[251] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[250] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[249] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[248] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[247] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[246] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[245] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[244] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[243] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[242] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[241] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[240] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[239] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[238] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[237] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[236] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[235] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[234] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[233] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[232] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[231] = 42'b101000011000111000000000000000000000011100; + n1468[230] = 42'b000001000010010000000000000000000001000000; + n1468[229] = 42'b000000011000010010000000000000000000000000; + n1468[228] = 42'b000001000010100000000000000000000001100011; + n1468[227] = 42'b100000000000000100100000000000000000001000; + n1468[226] = 42'b100000000000000010100000000000000000001000; + n1468[225] = 42'b100000000000001000000000000000000000001010; + n1468[224] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[223] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[222] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[221] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[220] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[219] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[218] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[217] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[216] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[215] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[214] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[213] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[212] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[211] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[210] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[209] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[208] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[207] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[206] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[205] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[204] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[203] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[202] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[201] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[200] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[199] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[198] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[197] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[196] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[195] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[194] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[193] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[192] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[191] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[190] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[189] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[188] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[187] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[186] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[185] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[184] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[183] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[182] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[181] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[180] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[179] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[178] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[177] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[176] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[175] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[174] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[173] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[172] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[171] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[170] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[169] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[168] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[167] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[166] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[165] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[164] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[163] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[162] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[161] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[160] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[159] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[158] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[157] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[156] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[155] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[154] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[153] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[152] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[151] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[150] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[149] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[148] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[147] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[146] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[145] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[144] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[143] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[142] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[141] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[140] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[139] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[138] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[137] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[136] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[135] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[134] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[133] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[132] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[131] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[130] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[129] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[128] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[127] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[126] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[125] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[124] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[123] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[122] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[121] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[120] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[119] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[118] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[117] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[116] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[115] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[114] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[113] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[112] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[111] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[110] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[109] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[108] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[107] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[106] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[105] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[104] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[103] = 42'b101000011100111000000000000000000000011100; + n1468[102] = 42'b000001000110010000000000000000000001000000; + n1468[101] = 42'b000000011000010010000000000000000000000000; + n1468[100] = 42'b000001000010100000000000000000000001100011; + n1468[99] = 42'b100000000000000100100000000000000000001000; + n1468[98] = 42'b100000000000000010100000000000000000001000; + n1468[97] = 42'b100000000000001000000000000000000000001010; + n1468[96] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[95] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[94] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[93] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[92] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[91] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[90] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[89] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[88] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[87] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[86] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[85] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[84] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[83] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[82] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[81] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[80] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[79] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[78] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[77] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[76] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[75] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[74] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[73] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[72] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[71] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[70] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[69] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[68] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[67] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[66] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[65] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[64] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[63] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[62] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[61] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[60] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[59] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[58] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[57] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[56] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[55] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[54] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[53] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[52] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[51] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[50] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[49] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[48] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[47] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[46] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[45] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[44] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[43] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[42] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[41] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[40] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[39] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[38] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[37] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[36] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[35] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[34] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[33] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[32] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[31] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[30] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[29] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[28] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[27] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[26] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[25] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[24] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[23] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[22] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[21] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[20] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[19] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[18] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[17] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[16] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[15] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[14] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[13] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[12] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[11] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[10] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[9] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[8] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[7] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[6] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[5] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[4] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[3] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[2] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[1] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + n1468[0] = 42'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + end + assign n1469_data = n1468[n1423_o]; + /* HUC6280_MC.vhd:6988:54 */ +endmodule + +module huc6280_cpu + (input clk, + input rst_n, + input ce, + input [7:0] di, + input rdy, + input nmi_n, + input irq1_n, + input irq2_n, + input irqt_n, + input vdcnum, + output [20:0] a_out, + output [7:0] dout, + output we_n, + output mcycle, + output cs); + wire en; + wire [7:0] a; + wire [7:0] x; + wire [7:0] y; + wire [7:0] sp; + wire [7:0] p; + wire [15:0] pc; + wire [15:0] aa; + wire [7:0] t; + wire [7:0] dr; + wire [7:0] sh; + wire [7:0] dh; + wire [7:0] lh; + wire [63:0] mpr; + wire [7:0] ir; + wire [4:0] state; + wire [43:0] mc; + wire [7:0] next_ir; + wire [4:0] next_state; + wire last_cycle; + wire branch_taken; + wire mem_inst; + wire talt; + wire [15:0] addr_bus; + wire [7:0] mpr_out; + wire [7:0] mpr_last; + wire [6:0] alu_ctrl; + wire [7:0] alu_l; + wire [7:0] alu_out; + wire co; + wire vo; + wire no; + wire zo; + wire [7:0] mask; + wire got_int; + wire res_int; + wire nmi_int; + wire irq1_int; + wire irq2_int; + wire irqt_int; + wire brk_int; + wire old_nmi_n; + wire nmi_sync; + wire nmi_active; + wire n410_o; + wire n412_o; + wire [7:0] n413_o; + wire [7:0] n415_o; + wire [4:0] n418_o; + wire n420_o; + wire n422_o; + wire n423_o; + wire [2:0] n424_o; + wire n425_o; + wire n426_o; + wire n428_o; + wire n429_o; + wire n431_o; + wire n432_o; + wire n433_o; + wire n435_o; + wire n436_o; + wire n438_o; + wire n439_o; + wire n440_o; + wire n442_o; + wire n443_o; + wire n445_o; + wire n446_o; + wire n447_o; + wire n449_o; + wire n450_o; + wire n452_o; + wire [7:0] n453_o; + reg n455_o; + wire [3:0] n456_o; + wire n458_o; + wire n460_o; + wire n461_o; + wire [2:0] n462_o; + wire n466_o; + wire n467_o; + wire n470_o; + wire n472_o; + wire n473_o; + wire n478_o; + wire n480_o; + wire n481_o; + wire n483_o; + wire n484_o; + wire n486_o; + wire n487_o; + wire n489_o; + wire n490_o; + wire n492_o; + wire n493_o; + wire n495_o; + wire n496_o; + wire n498_o; + wire n499_o; + wire n501_o; + wire n502_o; + wire n504_o; + wire n505_o; + wire n507_o; + wire n508_o; + wire n510_o; + wire n511_o; + wire n513_o; + wire n514_o; + wire n516_o; + wire n517_o; + wire n519_o; + wire n520_o; + wire n522_o; + wire n523_o; + wire n525_o; + wire n526_o; + wire n528_o; + wire n529_o; + wire n531_o; + wire n532_o; + wire n534_o; + wire n535_o; + wire n537_o; + wire n538_o; + wire n540_o; + wire n541_o; + wire n543_o; + wire n544_o; + wire n546_o; + wire n547_o; + wire n549_o; + wire n550_o; + wire n552_o; + wire n553_o; + wire n555_o; + wire n556_o; + wire n558_o; + wire n559_o; + wire n561_o; + wire n562_o; + wire n564_o; + wire n565_o; + wire n567_o; + wire n568_o; + wire n570_o; + wire n571_o; + wire n573_o; + wire n574_o; + wire n576_o; + wire n577_o; + wire n579_o; + wire n580_o; + wire n582_o; + wire n583_o; + wire n584_o; + wire [1:0] n588_o; + wire n589_o; + wire n590_o; + wire n592_o; + wire n593_o; + wire n594_o; + wire n595_o; + wire [4:0] n597_o; + wire [4:0] n599_o; + wire n601_o; + wire n602_o; + wire n603_o; + wire [4:0] n605_o; + wire [4:0] n607_o; + wire n609_o; + wire [4:0] n611_o; + wire [4:0] n613_o; + wire n615_o; + wire n617_o; + wire n619_o; + wire n620_o; + wire [4:0] n622_o; + wire [4:0] n624_o; + wire n626_o; + wire [3:0] n627_o; + reg [4:0] n628_o; + wire n632_o; + wire n645_o; + wire n646_o; + wire n650_o; + wire n653_o; + wire n655_o; + wire n656_o; + wire n657_o; + wire n659_o; + wire [1:0] mcode_m_state_ctrl; + wire [2:0] mcode_m_addr_bus; + wire [1:0] mcode_m_load_sdlh; + wire [2:0] mcode_m_load_p; + wire [2:0] mcode_m_load_t; + wire [5:0] mcode_m_addr_ctrl; + wire [2:0] mcode_m_load_pc; + wire [2:0] mcode_m_load_sp; + wire [2:0] mcode_m_axy_ctrl; + wire [3:0] mcode_m_alubus_ctrl; + wire [3:0] mcode_m_out_bus; + wire mcode_m_mem_cycle; + wire [6:0] mcode_m_alu_ctrl; + wire [43:0] n665_o; + wire n671_o; + wire n673_o; + wire n675_o; + wire n676_o; + wire n677_o; + wire n679_o; + wire n681_o; + wire n683_o; + wire n684_o; + wire n685_o; + wire n686_o; + wire n687_o; + wire n688_o; + wire n689_o; + wire [4:0] n690_o; + wire [2:0] n694_o; + wire n696_o; + wire n698_o; + wire n700_o; + wire n702_o; + wire n704_o; + wire n706_o; + wire n708_o; + wire [6:0] n709_o; + reg [7:0] n718_o; + wire [3:0] n720_o; + wire n722_o; + wire n724_o; + wire n726_o; + wire n728_o; + wire n730_o; + wire n732_o; + wire n734_o; + wire n736_o; + wire n738_o; + wire n740_o; + wire n742_o; + wire [10:0] n744_o; + reg [7:0] n745_o; + wire alu_co; + wire alu_vo; + wire alu_no; + wire alu_zo; + wire [7:0] alu_res; + wire [2:0] n746_o; + wire [2:0] n747_o; + wire n748_o; + wire n749_o; + wire n750_o; + wire n751_o; + wire n752_o; + wire n760_o; + wire n762_o; + wire n764_o; + wire n766_o; + wire n768_o; + wire n769_o; + wire n770_o; + wire n783_o; + wire [2:0] n785_o; + wire n787_o; + wire n789_o; + wire n791_o; + wire n793_o; + wire [3:0] n794_o; + reg [7:0] n795_o; + wire n803_o; + wire [2:0] n805_o; + wire n807_o; + wire [7:0] n809_o; + wire n811_o; + wire [7:0] n813_o; + wire n815_o; + wire [2:0] n816_o; + reg [7:0] n817_o; + wire n825_o; + wire [2:0] n827_o; + wire n829_o; + wire n833_o; + wire n835_o; + wire [1:0] n836_o; + wire n837_o; + wire n839_o; + wire n840_o; + wire n842_o; + wire n845_o; + wire n846_o; + wire n848_o; + wire [3:0] n849_o; + wire n850_o; + reg n851_o; + wire n852_o; + reg n853_o; + wire n854_o; + reg n855_o; + wire n856_o; + reg n857_o; + wire n859_o; + wire n861_o; + wire n864_o; + wire n867_o; + wire [6:0] n868_o; + wire n869_o; + wire n870_o; + reg n871_o; + wire n872_o; + wire n873_o; + reg n874_o; + wire n875_o; + wire n876_o; + reg n877_o; + wire n878_o; + wire n879_o; + reg n880_o; + wire n881_o; + wire n882_o; + reg n883_o; + wire n884_o; + wire n885_o; + reg n886_o; + wire n887_o; + wire n888_o; + reg n889_o; + wire n890_o; + wire n891_o; + reg n892_o; + wire n894_o; + wire n896_o; + wire n897_o; + wire n899_o; + wire [7:0] n900_o; + wire n908_o; + wire [1:0] n910_o; + wire n912_o; + wire n914_o; + wire n916_o; + wire [2:0] n917_o; + reg [7:0] n918_o; + reg [7:0] n919_o; + reg [7:0] n920_o; + wire n936_o; + wire n947_o; + wire n948_o; + wire n949_o; + wire [7:0] n950_o; + wire [7:0] n951_o; + wire n952_o; + wire [7:0] n953_o; + wire [7:0] n954_o; + wire n955_o; + wire [7:0] n956_o; + wire [7:0] n957_o; + wire n958_o; + wire [7:0] n959_o; + wire [7:0] n960_o; + wire n961_o; + wire [7:0] n962_o; + wire [7:0] n963_o; + wire n964_o; + wire [7:0] n965_o; + wire [7:0] n966_o; + wire n967_o; + wire [7:0] n968_o; + wire [7:0] n969_o; + wire n970_o; + wire [7:0] n971_o; + wire [7:0] n972_o; + wire [63:0] n973_o; + wire n976_o; + wire n977_o; + wire [63:0] n980_o; + wire [7:0] n984_o; + wire n985_o; + wire [7:0] n986_o; + wire [7:0] n987_o; + wire n988_o; + wire [7:0] n989_o; + wire [7:0] n990_o; + wire n991_o; + wire [7:0] n992_o; + wire [7:0] n993_o; + wire n994_o; + wire [7:0] n995_o; + wire [7:0] n996_o; + wire n997_o; + wire [7:0] n998_o; + wire [7:0] n999_o; + wire n1000_o; + wire [7:0] n1001_o; + wire [7:0] n1002_o; + wire n1003_o; + wire [7:0] n1004_o; + wire [7:0] n1005_o; + wire n1006_o; + wire [7:0] n1007_o; + wire [3:0] n1008_o; + wire n1010_o; + wire n1012_o; + wire n1014_o; + wire n1016_o; + wire [2:0] n1017_o; + wire n1018_o; + wire [3:0] n1019_o; + wire [3:0] n1020_o; + wire [7:0] n1021_o; + wire n1023_o; + wire [7:0] n1024_o; + wire n1026_o; + wire [7:0] n1027_o; + wire n1029_o; + wire [6:0] n1031_o; + reg [7:0] n1032_o; + wire [3:0] n1035_o; + wire n1037_o; + wire n1038_o; + wire n1039_o; + wire n1042_o; + wire n1047_o; + wire [15:0] ag_pc; + wire [15:0] ag_aa; + wire [2:0] n1054_o; + wire [5:0] n1055_o; + wire n1060_o; + wire n1062_o; + wire n1063_o; + wire n1064_o; + wire n1065_o; + wire n1066_o; + wire n1067_o; + wire n1068_o; + wire n1070_o; + wire n1072_o; + wire n1084_o; + wire n1086_o; + wire n1087_o; + wire n1088_o; + wire n1089_o; + wire n1090_o; + wire n1091_o; + wire n1092_o; + wire n1093_o; + wire n1094_o; + wire n1095_o; + wire n1096_o; + wire n1097_o; + wire n1099_o; + wire n1101_o; + wire n1102_o; + wire n1103_o; + wire n1104_o; + wire n1105_o; + wire n1106_o; + wire n1107_o; + wire n1108_o; + wire n1109_o; + wire n1110_o; + wire n1111_o; + wire n1112_o; + wire n1113_o; + wire n1114_o; + wire n1122_o; + wire n1123_o; + wire n1124_o; + wire n1125_o; + wire n1126_o; + wire n1127_o; + wire n1128_o; + wire n1154_o; + wire n1155_o; + wire n1156_o; + wire n1157_o; + wire [2:0] n1161_o; + wire n1163_o; + wire n1165_o; + wire [15:0] n1167_o; + wire n1169_o; + wire [7:0] n1170_o; + wire [15:0] n1172_o; + wire n1174_o; + wire n1176_o; + wire [3:0] n1178_o; + wire n1179_o; + wire [3:0] n1181_o; + wire n1182_o; + wire [3:0] n1184_o; + wire n1185_o; + wire [3:0] n1187_o; + wire n1188_o; + wire [3:0] n1190_o; + wire n1191_o; + wire [3:0] n1193_o; + wire n1194_o; + wire [3:0] n1196_o; + wire [3:0] n1197_o; + wire [3:0] n1198_o; + wire [3:0] n1199_o; + wire [3:0] n1200_o; + wire [3:0] n1201_o; + wire [3:0] n1202_o; + wire n1204_o; + wire [11:0] n1206_o; + wire [13:0] n1208_o; + wire [1:0] n1209_o; + wire n1212_o; + wire n1215_o; + wire [1:0] n1217_o; + reg [1:0] n1218_o; + wire n1220_o; + wire [15:0] n1221_o; + wire n1223_o; + wire [15:0] n1224_o; + wire n1226_o; + wire [7:0] n1227_o; + wire [1:0] n1228_o; + wire [1:0] n1229_o; + wire [1:0] n1230_o; + wire [1:0] n1231_o; + wire [1:0] n1232_o; + wire [1:0] n1233_o; + wire [1:0] n1234_o; + wire [1:0] n1235_o; + reg [1:0] n1236_o; + wire [1:0] n1237_o; + wire [1:0] n1238_o; + wire [1:0] n1239_o; + wire [1:0] n1240_o; + wire [1:0] n1241_o; + wire [1:0] n1242_o; + wire [1:0] n1243_o; + wire [1:0] n1244_o; + wire [1:0] n1245_o; + reg [1:0] n1246_o; + wire [11:0] n1247_o; + wire [11:0] n1248_o; + wire [11:0] n1249_o; + wire [11:0] n1250_o; + wire [11:0] n1251_o; + wire [11:0] n1252_o; + wire [11:0] n1253_o; + wire [11:0] n1254_o; + reg [11:0] n1255_o; + wire [12:0] n1257_o; + wire [2:0] n1259_o; + wire n1261_o; + wire [7:0] n1262_o; + wire [2:0] n1263_o; + wire [2:0] n1266_o; + wire n1271_o; + wire [6:0] n1273_o; + wire n1275_o; + wire n1277_o; + wire n1278_o; + wire n1279_o; + wire n1281_o; + wire n1286_o; + wire [7:0] n1287_o; + reg [7:0] n1288_q; + wire [7:0] n1289_o; + reg [7:0] n1290_q; + wire [7:0] n1291_o; + reg [7:0] n1292_q; + wire [7:0] n1293_o; + reg [7:0] n1294_q; + wire [7:0] n1295_o; + reg [7:0] n1296_q; + wire [7:0] n1297_o; + reg [7:0] n1298_q; + wire [7:0] n1299_o; + reg [7:0] n1300_q; + wire [7:0] n1301_o; + reg [7:0] n1302_q; + wire [7:0] n1303_o; + reg [7:0] n1304_q; + wire [7:0] n1305_o; + reg [7:0] n1306_q; + wire [63:0] n1307_o; + reg [63:0] n1308_q; + wire [7:0] n1309_o; + reg [7:0] n1310_q; + wire [4:0] n1311_o; + reg [4:0] n1312_q; + wire n1313_o; + reg n1314_q; + wire [15:0] n1315_o; + wire n1316_o; + wire n1317_o; + wire [7:0] n1318_o; + reg [7:0] n1319_q; + wire [6:0] n1320_o; + wire n1321_o; + reg n1322_q; + wire n1323_o; + reg n1324_q; + wire n1325_o; + reg n1326_q; + wire n1327_o; + reg n1328_q; + wire n1329_o; + reg n1330_q; + wire n1331_o; + reg n1332_q; + wire n1333_o; + reg n1334_q; + wire n1335_o; + reg n1336_q; + wire n1337_o; + reg n1338_q; + wire [20:0] n1339_o; + wire n1340_o; + reg n1341_q; + wire n1342_o; + wire n1343_o; + wire n1344_o; + wire n1345_o; + wire n1346_o; + wire n1347_o; + wire n1348_o; + wire n1349_o; + wire [1:0] n1350_o; + reg n1351_o; + wire [1:0] n1352_o; + reg n1353_o; + wire n1354_o; + wire n1355_o; + wire [7:0] n1356_o; + wire [7:0] n1357_o; + wire [7:0] n1358_o; + wire [7:0] n1359_o; + wire [7:0] n1360_o; + wire [7:0] n1361_o; + wire [7:0] n1362_o; + wire [7:0] n1363_o; + wire [1:0] n1364_o; + reg [7:0] n1365_o; + wire [1:0] n1366_o; + reg [7:0] n1367_o; + wire n1368_o; + wire [7:0] n1369_o; + assign a_out = n1339_o; + assign dout = n1032_o; + assign we_n = n1042_o; + assign mcycle = n1286_o; + assign cs = n1341_q; + /* HUC6280_CPU.vhd:32:16 */ + assign en = n410_o; // (signal) + /* HUC6280_CPU.vhd:35:16 */ + assign a = n1288_q; // (signal) + /* HUC6280_CPU.vhd:36:16 */ + assign x = n1290_q; // (signal) + /* HUC6280_CPU.vhd:37:16 */ + assign y = n1292_q; // (signal) + /* HUC6280_CPU.vhd:38:16 */ + assign sp = n1294_q; // (signal) + /* HUC6280_CPU.vhd:39:16 */ + assign p = n1296_q; // (signal) + /* HUC6280_CPU.vhd:40:16 */ + assign pc = ag_pc; // (signal) + /* HUC6280_CPU.vhd:41:16 */ + assign aa = ag_aa; // (signal) + /* HUC6280_CPU.vhd:42:16 */ + assign t = n1298_q; // (signal) + /* HUC6280_CPU.vhd:43:16 */ + assign dr = n1300_q; // (signal) + /* HUC6280_CPU.vhd:44:16 */ + assign sh = n1302_q; // (signal) + /* HUC6280_CPU.vhd:45:16 */ + assign dh = n1304_q; // (signal) + /* HUC6280_CPU.vhd:46:16 */ + assign lh = n1306_q; // (signal) + /* HUC6280_CPU.vhd:47:16 */ + assign mpr = n1308_q; // (signal) + /* HUC6280_CPU.vhd:50:16 */ + assign ir = n1310_q; // (signal) + /* HUC6280_CPU.vhd:51:16 */ + assign state = n1312_q; // (signal) + /* HUC6280_CPU.vhd:52:16 */ + assign mc = n665_o; // (signal) + /* HUC6280_CPU.vhd:53:16 */ + assign next_ir = n413_o; // (signal) + /* HUC6280_CPU.vhd:54:16 */ + assign next_state = n628_o; // (signal) + /* HUC6280_CPU.vhd:55:16 */ + assign last_cycle = n646_o; // (signal) + /* HUC6280_CPU.vhd:56:16 */ + assign branch_taken = n473_o; // (signal) + /* HUC6280_CPU.vhd:57:16 */ + assign mem_inst = n584_o; // (signal) + /* HUC6280_CPU.vhd:58:16 */ + assign talt = n1314_q; // (signal) + /* HUC6280_CPU.vhd:61:16 */ + assign addr_bus = n1315_o; // (signal) + /* HUC6280_CPU.vhd:62:16 */ + assign mpr_out = n986_o; // (signal) + /* HUC6280_CPU.vhd:63:16 */ + assign mpr_last = n1319_q; // (signal) + /* HUC6280_CPU.vhd:66:16 */ + assign alu_ctrl = n1320_o; // (signal) + /* HUC6280_CPU.vhd:67:16 */ + assign alu_l = n745_o; // (signal) + /* HUC6280_CPU.vhd:68:16 */ + assign alu_out = alu_res; // (signal) + /* HUC6280_CPU.vhd:69:16 */ + assign co = alu_co; // (signal) + /* HUC6280_CPU.vhd:70:16 */ + assign vo = alu_vo; // (signal) + /* HUC6280_CPU.vhd:71:16 */ + assign no = alu_no; // (signal) + /* HUC6280_CPU.vhd:72:16 */ + assign zo = alu_zo; // (signal) + /* HUC6280_CPU.vhd:73:16 */ + assign mask = n718_o; // (signal) + /* HUC6280_CPU.vhd:76:16 */ + assign got_int = n1322_q; // (signal) + /* HUC6280_CPU.vhd:77:16 */ + assign res_int = n1324_q; // (signal) + /* HUC6280_CPU.vhd:78:16 */ + assign nmi_int = n1326_q; // (signal) + /* HUC6280_CPU.vhd:79:16 */ + assign irq1_int = n1328_q; // (signal) + /* HUC6280_CPU.vhd:80:16 */ + assign irq2_int = n1330_q; // (signal) + /* HUC6280_CPU.vhd:81:16 */ + assign irqt_int = n1332_q; // (signal) + /* HUC6280_CPU.vhd:82:16 */ + assign brk_int = n1157_o; // (signal) + /* HUC6280_CPU.vhd:83:16 */ + assign old_nmi_n = n1334_q; // (signal) + /* HUC6280_CPU.vhd:84:16 */ + assign nmi_sync = n1336_q; // (signal) + /* HUC6280_CPU.vhd:85:16 */ + assign nmi_active = n1338_q; // (signal) + /* HUC6280_CPU.vhd:89:19 */ + assign n410_o = rdy & ce; + /* HUC6280_CPU.vhd:91:35 */ + assign n412_o = state != 5'b00000; + /* HUC6280_CPU.vhd:91:23 */ + assign n413_o = n412_o ? ir : n415_o; + /* HUC6280_CPU.vhd:91:47 */ + assign n415_o = got_int ? 8'b00000000 : di; + /* HUC6280_CPU.vhd:99:22 */ + assign n418_o = ir[4:0]; + /* HUC6280_CPU.vhd:99:35 */ + assign n420_o = n418_o == 5'b10000; + /* HUC6280_CPU.vhd:99:55 */ + assign n422_o = state == 5'b00001; + /* HUC6280_CPU.vhd:99:45 */ + assign n423_o = n420_o & n422_o; + /* HUC6280_CPU.vhd:100:32 */ + assign n424_o = ir[7:5]; + /* HUC6280_CPU.vhd:101:68 */ + assign n425_o = p[7]; + /* HUC6280_CPU.vhd:101:63 */ + assign n426_o = ~n425_o; + /* HUC6280_CPU.vhd:101:33 */ + assign n428_o = n424_o == 3'b000; + /* HUC6280_CPU.vhd:102:68 */ + assign n429_o = p[7]; + /* HUC6280_CPU.vhd:102:33 */ + assign n431_o = n424_o == 3'b001; + /* HUC6280_CPU.vhd:103:68 */ + assign n432_o = p[6]; + /* HUC6280_CPU.vhd:103:63 */ + assign n433_o = ~n432_o; + /* HUC6280_CPU.vhd:103:33 */ + assign n435_o = n424_o == 3'b010; + /* HUC6280_CPU.vhd:104:68 */ + assign n436_o = p[6]; + /* HUC6280_CPU.vhd:104:33 */ + assign n438_o = n424_o == 3'b011; + /* HUC6280_CPU.vhd:105:68 */ + assign n439_o = p[0]; + /* HUC6280_CPU.vhd:105:63 */ + assign n440_o = ~n439_o; + /* HUC6280_CPU.vhd:105:33 */ + assign n442_o = n424_o == 3'b100; + /* HUC6280_CPU.vhd:106:68 */ + assign n443_o = p[0]; + /* HUC6280_CPU.vhd:106:33 */ + assign n445_o = n424_o == 3'b101; + /* HUC6280_CPU.vhd:107:68 */ + assign n446_o = p[1]; + /* HUC6280_CPU.vhd:107:63 */ + assign n447_o = ~n446_o; + /* HUC6280_CPU.vhd:107:33 */ + assign n449_o = n424_o == 3'b110; + /* HUC6280_CPU.vhd:108:68 */ + assign n450_o = p[1]; + /* HUC6280_CPU.vhd:108:33 */ + assign n452_o = n424_o == 3'b111; + assign n453_o = {n452_o, n449_o, n445_o, n442_o, n438_o, n435_o, n431_o, n428_o}; + /* HUC6280_CPU.vhd:100:25 */ + always @* + case (n453_o) + 8'b10000000: n455_o = n450_o; + 8'b01000000: n455_o = n447_o; + 8'b00100000: n455_o = n443_o; + 8'b00010000: n455_o = n440_o; + 8'b00001000: n455_o = n436_o; + 8'b00000100: n455_o = n433_o; + 8'b00000010: n455_o = n429_o; + 8'b00000001: n455_o = n426_o; + default: n455_o = 1'b0; + endcase + /* HUC6280_CPU.vhd:111:25 */ + assign n456_o = ir[3:0]; + /* HUC6280_CPU.vhd:111:38 */ + assign n458_o = n456_o == 4'b1111; + /* HUC6280_CPU.vhd:111:57 */ + assign n460_o = state == 5'b00101; + /* HUC6280_CPU.vhd:111:47 */ + assign n461_o = n458_o & n460_o; + /* HUC6280_CPU.vhd:112:53 */ + assign n462_o = ir[6:4]; + /* HUC6280_CPU.vhd:112:73 */ + assign n466_o = ir[7]; + /* HUC6280_CPU.vhd:112:69 */ + assign n467_o = n1355_o == n466_o; + /* HUC6280_CPU.vhd:112:25 */ + assign n470_o = n467_o ? 1'b1 : 1'b0; + /* HUC6280_CPU.vhd:111:17 */ + assign n472_o = n461_o ? n470_o : 1'b0; + /* HUC6280_CPU.vhd:99:17 */ + assign n473_o = n423_o ? n455_o : n472_o; + /* HUC6280_CPU.vhd:118:33 */ + assign n478_o = di == 8'b01101001; + /* HUC6280_CPU.vhd:118:47 */ + assign n480_o = di == 8'b01100101; + /* HUC6280_CPU.vhd:118:41 */ + assign n481_o = n478_o | n480_o; + /* HUC6280_CPU.vhd:118:61 */ + assign n483_o = di == 8'b01110101; + /* HUC6280_CPU.vhd:118:55 */ + assign n484_o = n481_o | n483_o; + /* HUC6280_CPU.vhd:118:75 */ + assign n486_o = di == 8'b01110010; + /* HUC6280_CPU.vhd:118:69 */ + assign n487_o = n484_o | n486_o; + /* HUC6280_CPU.vhd:118:89 */ + assign n489_o = di == 8'b01100001; + /* HUC6280_CPU.vhd:118:83 */ + assign n490_o = n487_o | n489_o; + /* HUC6280_CPU.vhd:118:103 */ + assign n492_o = di == 8'b01110001; + /* HUC6280_CPU.vhd:118:97 */ + assign n493_o = n490_o | n492_o; + /* HUC6280_CPU.vhd:118:117 */ + assign n495_o = di == 8'b01101101; + /* HUC6280_CPU.vhd:118:111 */ + assign n496_o = n493_o | n495_o; + /* HUC6280_CPU.vhd:118:131 */ + assign n498_o = di == 8'b01111101; + /* HUC6280_CPU.vhd:118:125 */ + assign n499_o = n496_o | n498_o; + /* HUC6280_CPU.vhd:118:145 */ + assign n501_o = di == 8'b01111001; + /* HUC6280_CPU.vhd:118:139 */ + assign n502_o = n499_o | n501_o; + /* HUC6280_CPU.vhd:119:68 */ + assign n504_o = di == 8'b00101001; + /* HUC6280_CPU.vhd:118:153 */ + assign n505_o = n502_o | n504_o; + /* HUC6280_CPU.vhd:119:82 */ + assign n507_o = di == 8'b00100101; + /* HUC6280_CPU.vhd:119:76 */ + assign n508_o = n505_o | n507_o; + /* HUC6280_CPU.vhd:119:96 */ + assign n510_o = di == 8'b00110101; + /* HUC6280_CPU.vhd:119:90 */ + assign n511_o = n508_o | n510_o; + /* HUC6280_CPU.vhd:119:110 */ + assign n513_o = di == 8'b00110010; + /* HUC6280_CPU.vhd:119:104 */ + assign n514_o = n511_o | n513_o; + /* HUC6280_CPU.vhd:119:124 */ + assign n516_o = di == 8'b00100001; + /* HUC6280_CPU.vhd:119:118 */ + assign n517_o = n514_o | n516_o; + /* HUC6280_CPU.vhd:119:138 */ + assign n519_o = di == 8'b00110001; + /* HUC6280_CPU.vhd:119:132 */ + assign n520_o = n517_o | n519_o; + /* HUC6280_CPU.vhd:119:152 */ + assign n522_o = di == 8'b00101101; + /* HUC6280_CPU.vhd:119:146 */ + assign n523_o = n520_o | n522_o; + /* HUC6280_CPU.vhd:119:166 */ + assign n525_o = di == 8'b00111101; + /* HUC6280_CPU.vhd:119:160 */ + assign n526_o = n523_o | n525_o; + /* HUC6280_CPU.vhd:119:180 */ + assign n528_o = di == 8'b00111001; + /* HUC6280_CPU.vhd:119:174 */ + assign n529_o = n526_o | n528_o; + /* HUC6280_CPU.vhd:120:68 */ + assign n531_o = di == 8'b00001001; + /* HUC6280_CPU.vhd:119:188 */ + assign n532_o = n529_o | n531_o; + /* HUC6280_CPU.vhd:120:82 */ + assign n534_o = di == 8'b00000101; + /* HUC6280_CPU.vhd:120:76 */ + assign n535_o = n532_o | n534_o; + /* HUC6280_CPU.vhd:120:96 */ + assign n537_o = di == 8'b00010101; + /* HUC6280_CPU.vhd:120:90 */ + assign n538_o = n535_o | n537_o; + /* HUC6280_CPU.vhd:120:110 */ + assign n540_o = di == 8'b00010010; + /* HUC6280_CPU.vhd:120:104 */ + assign n541_o = n538_o | n540_o; + /* HUC6280_CPU.vhd:120:124 */ + assign n543_o = di == 8'b00000001; + /* HUC6280_CPU.vhd:120:118 */ + assign n544_o = n541_o | n543_o; + /* HUC6280_CPU.vhd:120:138 */ + assign n546_o = di == 8'b00010001; + /* HUC6280_CPU.vhd:120:132 */ + assign n547_o = n544_o | n546_o; + /* HUC6280_CPU.vhd:120:152 */ + assign n549_o = di == 8'b00001101; + /* HUC6280_CPU.vhd:120:146 */ + assign n550_o = n547_o | n549_o; + /* HUC6280_CPU.vhd:120:166 */ + assign n552_o = di == 8'b00011101; + /* HUC6280_CPU.vhd:120:160 */ + assign n553_o = n550_o | n552_o; + /* HUC6280_CPU.vhd:120:180 */ + assign n555_o = di == 8'b00011001; + /* HUC6280_CPU.vhd:120:174 */ + assign n556_o = n553_o | n555_o; + /* HUC6280_CPU.vhd:121:68 */ + assign n558_o = di == 8'b01001001; + /* HUC6280_CPU.vhd:120:188 */ + assign n559_o = n556_o | n558_o; + /* HUC6280_CPU.vhd:121:82 */ + assign n561_o = di == 8'b01000101; + /* HUC6280_CPU.vhd:121:76 */ + assign n562_o = n559_o | n561_o; + /* HUC6280_CPU.vhd:121:96 */ + assign n564_o = di == 8'b01010101; + /* HUC6280_CPU.vhd:121:90 */ + assign n565_o = n562_o | n564_o; + /* HUC6280_CPU.vhd:121:110 */ + assign n567_o = di == 8'b01010010; + /* HUC6280_CPU.vhd:121:104 */ + assign n568_o = n565_o | n567_o; + /* HUC6280_CPU.vhd:121:124 */ + assign n570_o = di == 8'b01000001; + /* HUC6280_CPU.vhd:121:118 */ + assign n571_o = n568_o | n570_o; + /* HUC6280_CPU.vhd:121:138 */ + assign n573_o = di == 8'b01010001; + /* HUC6280_CPU.vhd:121:132 */ + assign n574_o = n571_o | n573_o; + /* HUC6280_CPU.vhd:121:152 */ + assign n576_o = di == 8'b01001101; + /* HUC6280_CPU.vhd:121:146 */ + assign n577_o = n574_o | n576_o; + /* HUC6280_CPU.vhd:121:166 */ + assign n579_o = di == 8'b01011101; + /* HUC6280_CPU.vhd:121:160 */ + assign n580_o = n577_o | n579_o; + /* HUC6280_CPU.vhd:121:180 */ + assign n582_o = di == 8'b01011001; + /* HUC6280_CPU.vhd:121:174 */ + assign n583_o = n580_o | n582_o; + /* HUC6280_CPU.vhd:118:25 */ + assign n584_o = n583_o ? 1'b1 : 1'b0; + /* HUC6280_CPU.vhd:127:25 */ + assign n588_o = mc[1:0]; + /* HUC6280_CPU.vhd:129:56 */ + assign n589_o = p[5]; + /* HUC6280_CPU.vhd:129:51 */ + assign n590_o = mem_inst & n589_o; + /* HUC6280_CPU.vhd:129:81 */ + assign n592_o = state == 5'b00000; + /* HUC6280_CPU.vhd:129:71 */ + assign n593_o = n590_o & n592_o; + /* HUC6280_CPU.vhd:129:103 */ + assign n594_o = ~got_int; + /* HUC6280_CPU.vhd:129:91 */ + assign n595_o = n593_o & n594_o; + /* HUC6280_CPU.vhd:132:61 */ + assign n597_o = state + 5'b00001; + /* HUC6280_CPU.vhd:129:33 */ + assign n599_o = n595_o ? 5'b01000 : n597_o; + /* HUC6280_CPU.vhd:128:25 */ + assign n601_o = n588_o == 2'b00; + /* HUC6280_CPU.vhd:135:37 */ + assign n602_o = p[3]; + /* HUC6280_CPU.vhd:135:46 */ + assign n603_o = ~n602_o; + /* HUC6280_CPU.vhd:138:61 */ + assign n605_o = state + 5'b00001; + /* HUC6280_CPU.vhd:135:33 */ + assign n607_o = n603_o ? 5'b00000 : n605_o; + /* HUC6280_CPU.vhd:134:25 */ + assign n609_o = n588_o == 2'b01; + /* HUC6280_CPU.vhd:142:61 */ + assign n611_o = state + 5'b00001; + /* HUC6280_CPU.vhd:141:33 */ + assign n613_o = branch_taken ? n611_o : 5'b00000; + /* HUC6280_CPU.vhd:140:25 */ + assign n615_o = n588_o == 2'b10; + /* HUC6280_CPU.vhd:147:38 */ + assign n617_o = a == 8'b00000000; + /* HUC6280_CPU.vhd:147:53 */ + assign n619_o = lh == 8'b00000000; + /* HUC6280_CPU.vhd:147:46 */ + assign n620_o = n617_o & n619_o; + /* HUC6280_CPU.vhd:148:61 */ + assign n622_o = state + 5'b00001; + /* HUC6280_CPU.vhd:147:33 */ + assign n624_o = n620_o ? n622_o : 5'b01110; + /* HUC6280_CPU.vhd:146:25 */ + assign n626_o = n588_o == 2'b11; + assign n627_o = {n626_o, n615_o, n609_o, n601_o}; + /* HUC6280_CPU.vhd:127:17 */ + always @* + case (n627_o) + 4'b1000: n628_o = n624_o; + 4'b0100: n628_o = n613_o; + 4'b0010: n628_o = n607_o; + 4'b0001: n628_o = n599_o; + default: n628_o = state; + endcase + /* HUC6280_CPU.vhd:160:26 */ + assign n632_o = ~rst_n; + /* HUC6280_CPU.vhd:171:43 */ + assign n645_o = next_state == 5'b00000; + /* HUC6280_CPU.vhd:171:27 */ + assign n646_o = n645_o ? 1'b1 : 1'b0; + /* HUC6280_CPU.vhd:175:26 */ + assign n650_o = ~rst_n; + /* HUC6280_CPU.vhd:179:42 */ + assign n653_o = state == 5'b01101; + /* HUC6280_CPU.vhd:181:45 */ + assign n655_o = state == 5'b10011; + /* HUC6280_CPU.vhd:182:49 */ + assign n656_o = ~talt; + /* HUC6280_CPU.vhd:181:33 */ + assign n657_o = n655_o ? n656_o : talt; + /* HUC6280_CPU.vhd:179:33 */ + assign n659_o = n653_o ? 1'b0 : n657_o; + /* HUC6280_CPU.vhd:188:9 */ + huc6280_mc mcode ( + .clk(clk), + .rst_n(rst_n), + .en(en), + .ir(next_ir), + .state(next_state), + .m_state_ctrl(mcode_m_state_ctrl), + .m_addr_bus(mcode_m_addr_bus), + .m_load_sdlh(mcode_m_load_sdlh), + .m_load_p(mcode_m_load_p), + .m_load_t(mcode_m_load_t), + .m_addr_ctrl(mcode_m_addr_ctrl), + .m_load_pc(mcode_m_load_pc), + .m_load_sp(mcode_m_load_sp), + .m_axy_ctrl(mcode_m_axy_ctrl), + .m_alubus_ctrl(mcode_m_alubus_ctrl), + .m_out_bus(mcode_m_out_bus), + .m_mem_cycle(mcode_m_mem_cycle), + .m_alu_ctrl(mcode_m_alu_ctrl)); + assign n665_o = {mcode_m_alu_ctrl, mcode_m_mem_cycle, mcode_m_out_bus, mcode_m_alubus_ctrl, mcode_m_axy_ctrl, mcode_m_load_sp, mcode_m_load_pc, mcode_m_addr_ctrl, mcode_m_load_t, mcode_m_load_p, mcode_m_load_sdlh, mcode_m_addr_bus, mcode_m_state_ctrl}; + /* HUC6280_CPU.vhd:201:23 */ + assign n671_o = ir == 8'b11100011; + /* HUC6280_CPU.vhd:201:42 */ + assign n673_o = state == 5'b10000; + /* HUC6280_CPU.vhd:201:56 */ + assign n675_o = state == 5'b10001; + /* HUC6280_CPU.vhd:201:47 */ + assign n676_o = n673_o | n675_o; + /* HUC6280_CPU.vhd:201:31 */ + assign n677_o = n671_o & n676_o; + /* HUC6280_CPU.vhd:203:26 */ + assign n679_o = ir == 8'b11110011; + /* HUC6280_CPU.vhd:203:45 */ + assign n681_o = state == 5'b01110; + /* HUC6280_CPU.vhd:203:59 */ + assign n683_o = state == 5'b01111; + /* HUC6280_CPU.vhd:203:50 */ + assign n684_o = n681_o | n683_o; + /* HUC6280_CPU.vhd:203:34 */ + assign n685_o = n679_o & n684_o; + assign n686_o = mc[42]; + /* HUC6280_CPU.vhd:203:17 */ + assign n687_o = n685_o ? talt : n686_o; + /* HUC6280_CPU.vhd:201:17 */ + assign n688_o = n677_o ? talt : n687_o; + assign n689_o = mc[43]; + assign n690_o = mc[41:37]; + /* HUC6280_CPU.vhd:210:24 */ + assign n694_o = ir[6:4]; + /* HUC6280_CPU.vhd:211:25 */ + assign n696_o = n694_o == 3'b000; + /* HUC6280_CPU.vhd:212:25 */ + assign n698_o = n694_o == 3'b001; + /* HUC6280_CPU.vhd:213:25 */ + assign n700_o = n694_o == 3'b010; + /* HUC6280_CPU.vhd:214:25 */ + assign n702_o = n694_o == 3'b011; + /* HUC6280_CPU.vhd:215:25 */ + assign n704_o = n694_o == 3'b100; + /* HUC6280_CPU.vhd:216:25 */ + assign n706_o = n694_o == 3'b101; + /* HUC6280_CPU.vhd:217:25 */ + assign n708_o = n694_o == 3'b110; + assign n709_o = {n708_o, n706_o, n704_o, n702_o, n700_o, n698_o, n696_o}; + /* HUC6280_CPU.vhd:210:17 */ + always @* + case (n709_o) + 7'b1000000: n718_o = 8'b01000000; + 7'b0100000: n718_o = 8'b00100000; + 7'b0010000: n718_o = 8'b00010000; + 7'b0001000: n718_o = 8'b00001000; + 7'b0000100: n718_o = 8'b00000100; + 7'b0000010: n718_o = 8'b00000010; + 7'b0000001: n718_o = 8'b00000001; + default: n718_o = 8'b10000000; + endcase + /* HUC6280_CPU.vhd:222:17 */ + assign n720_o = mc[31:28]; + /* HUC6280_CPU.vhd:223:41 */ + assign n722_o = n720_o == 4'b0000; + /* HUC6280_CPU.vhd:224:50 */ + assign n724_o = n720_o == 4'b0001; + /* HUC6280_CPU.vhd:225:50 */ + assign n726_o = n720_o == 4'b0010; + /* HUC6280_CPU.vhd:226:50 */ + assign n728_o = n720_o == 4'b0011; + /* HUC6280_CPU.vhd:227:65 */ + assign n730_o = n720_o == 4'b0100; + /* HUC6280_CPU.vhd:228:50 */ + assign n732_o = n720_o == 4'b0101; + /* HUC6280_CPU.vhd:229:50 */ + assign n734_o = n720_o == 4'b1000; + /* HUC6280_CPU.vhd:230:50 */ + assign n736_o = n720_o == 4'b1001; + /* HUC6280_CPU.vhd:231:57 */ + assign n738_o = n720_o == 4'b1010; + /* HUC6280_CPU.vhd:232:57 */ + assign n740_o = n720_o == 4'b1011; + /* HUC6280_CPU.vhd:233:50 */ + assign n742_o = n720_o == 4'b1100; + assign n744_o = {n742_o, n740_o, n738_o, n736_o, n734_o, n732_o, n730_o, n728_o, n726_o, n724_o, n722_o}; + /* HUC6280_CPU.vhd:222:9 */ + always @* + case (n744_o) + 11'b10000000000: n745_o = mask; + 11'b01000000000: n745_o = mpr_out; + 11'b00100000000: n745_o = lh; + 11'b00010000000: n745_o = dh; + 11'b00001000000: n745_o = sh; + 11'b00000100000: n745_o = t; + 11'b00000010000: n745_o = sp; + 11'b00000001000: n745_o = y; + 11'b00000000100: n745_o = x; + 11'b00000000010: n745_o = a; + 11'b00000000001: n745_o = di; + default: n745_o = 8'b00000000; + endcase + /* HUC6280_CPU.vhd:236:9 */ + alu alu ( + .clk(clk), + .en(en), + .l(alu_l), + .r(di), + .ctrl_fstop(n746_o), + .ctrl_secop(n747_o), + .ctrl_fc(n748_o), + .bcd(n749_o), + .ci(n750_o), + .vi(n751_o), + .ni(n752_o), + .co(alu_co), + .vo(alu_vo), + .no(alu_no), + .zo(alu_zo), + .res(alu_res)); + assign n746_o = alu_ctrl[2:0]; + assign n747_o = alu_ctrl[5:3]; + assign n748_o = alu_ctrl[6]; + /* HUC6280_CPU.vhd:243:37 */ + assign n749_o = p[3]; + /* HUC6280_CPU.vhd:244:37 */ + assign n750_o = p[0]; + /* HUC6280_CPU.vhd:245:37 */ + assign n751_o = p[6]; + /* HUC6280_CPU.vhd:246:37 */ + assign n752_o = p[7]; + /* HUC6280_CPU.vhd:257:26 */ + assign n760_o = ~rst_n; + /* HUC6280_CPU.vhd:263:47 */ + assign n762_o = mc[25]; + /* HUC6280_CPU.vhd:266:47 */ + assign n764_o = mc[26]; + /* HUC6280_CPU.vhd:269:47 */ + assign n766_o = mc[27]; + /* HUC6280_CPU.vhd:262:25 */ + assign n768_o = en & n762_o; + /* HUC6280_CPU.vhd:262:25 */ + assign n769_o = en & n764_o; + /* HUC6280_CPU.vhd:262:25 */ + assign n770_o = en & n766_o; + /* HUC6280_CPU.vhd:278:26 */ + assign n783_o = ~rst_n; + /* HUC6280_CPU.vhd:282:41 */ + assign n785_o = mc[12:10]; + /* HUC6280_CPU.vhd:283:41 */ + assign n787_o = n785_o == 3'b001; + /* HUC6280_CPU.vhd:284:41 */ + assign n789_o = n785_o == 3'b010; + /* HUC6280_CPU.vhd:285:41 */ + assign n791_o = n785_o == 3'b011; + /* HUC6280_CPU.vhd:286:41 */ + assign n793_o = n785_o == 3'b100; + assign n794_o = {n793_o, n791_o, n789_o, n787_o}; + /* HUC6280_CPU.vhd:282:33 */ + always @* + case (n794_o) + 4'b1000: n795_o = di; + 4'b0100: n795_o = y; + 4'b0010: n795_o = x; + 4'b0001: n795_o = alu_out; + default: n795_o = t; + endcase + /* HUC6280_CPU.vhd:295:26 */ + assign n803_o = ~rst_n; + /* HUC6280_CPU.vhd:299:41 */ + assign n805_o = mc[24:22]; + /* HUC6280_CPU.vhd:300:41 */ + assign n807_o = n805_o == 3'b001; + /* HUC6280_CPU.vhd:303:85 */ + assign n809_o = sp + 8'b00000001; + /* HUC6280_CPU.vhd:302:41 */ + assign n811_o = n805_o == 3'b010; + /* HUC6280_CPU.vhd:305:85 */ + assign n813_o = sp - 8'b00000001; + /* HUC6280_CPU.vhd:304:41 */ + assign n815_o = n805_o == 3'b011; + assign n816_o = {n815_o, n811_o, n807_o}; + /* HUC6280_CPU.vhd:299:33 */ + always @* + case (n816_o) + 3'b100: n817_o = n813_o; + 3'b010: n817_o = n809_o; + 3'b001: n817_o = alu_out; + default: n817_o = sp; + endcase + /* HUC6280_CPU.vhd:315:26 */ + assign n825_o = ~rst_n; + /* HUC6280_CPU.vhd:319:41 */ + assign n827_o = mc[9:7]; + /* HUC6280_CPU.vhd:320:41 */ + assign n829_o = n827_o == 3'b001; + /* HUC6280_CPU.vhd:323:41 */ + assign n833_o = n827_o == 3'b010; + /* HUC6280_CPU.vhd:326:41 */ + assign n835_o = n827_o == 3'b011; + /* HUC6280_CPU.vhd:329:56 */ + assign n836_o = ir[7:6]; + /* HUC6280_CPU.vhd:330:85 */ + assign n837_o = ir[5]; + /* HUC6280_CPU.vhd:330:57 */ + assign n839_o = n836_o == 2'b00; + /* HUC6280_CPU.vhd:331:85 */ + assign n840_o = ir[5]; + /* HUC6280_CPU.vhd:331:57 */ + assign n842_o = n836_o == 2'b01; + /* HUC6280_CPU.vhd:332:57 */ + assign n845_o = n836_o == 2'b10; + /* HUC6280_CPU.vhd:333:85 */ + assign n846_o = ir[5]; + /* HUC6280_CPU.vhd:333:57 */ + assign n848_o = n836_o == 2'b11; + assign n849_o = {n848_o, n845_o, n842_o, n839_o}; + assign n850_o = p[0]; + /* HUC6280_CPU.vhd:329:49 */ + always @* + case (n849_o) + 4'b1000: n851_o = n850_o; + 4'b0100: n851_o = n850_o; + 4'b0010: n851_o = n850_o; + 4'b0001: n851_o = n837_o; + default: n851_o = n850_o; + endcase + assign n852_o = p[2]; + /* HUC6280_CPU.vhd:329:49 */ + always @* + case (n849_o) + 4'b1000: n853_o = n852_o; + 4'b0100: n853_o = n852_o; + 4'b0010: n853_o = n840_o; + 4'b0001: n853_o = n852_o; + default: n853_o = n852_o; + endcase + assign n854_o = p[3]; + /* HUC6280_CPU.vhd:329:49 */ + always @* + case (n849_o) + 4'b1000: n855_o = n846_o; + 4'b0100: n855_o = n854_o; + 4'b0010: n855_o = n854_o; + 4'b0001: n855_o = n854_o; + default: n855_o = n854_o; + endcase + assign n856_o = p[6]; + /* HUC6280_CPU.vhd:329:49 */ + always @* + case (n849_o) + 4'b1000: n857_o = n856_o; + 4'b0100: n857_o = 1'b0; + 4'b0010: n857_o = n856_o; + 4'b0001: n857_o = n856_o; + default: n857_o = n856_o; + endcase + /* HUC6280_CPU.vhd:328:41 */ + assign n859_o = n827_o == 3'b100; + /* HUC6280_CPU.vhd:336:41 */ + assign n861_o = n827_o == 3'b101; + /* HUC6280_CPU.vhd:341:41 */ + assign n864_o = n827_o == 3'b110; + /* HUC6280_CPU.vhd:343:41 */ + assign n867_o = n827_o == 3'b111; + assign n868_o = {n867_o, n864_o, n861_o, n859_o, n835_o, n833_o, n829_o}; + assign n869_o = di[0]; + assign n870_o = p[0]; + /* HUC6280_CPU.vhd:319:33 */ + always @* + case (n868_o) + 7'b1000000: n871_o = n870_o; + 7'b0100000: n871_o = n870_o; + 7'b0010000: n871_o = co; + 7'b0001000: n871_o = n851_o; + 7'b0000100: n871_o = n869_o; + 7'b0000010: n871_o = n870_o; + 7'b0000001: n871_o = n870_o; + default: n871_o = n870_o; + endcase + assign n872_o = di[1]; + assign n873_o = p[1]; + /* HUC6280_CPU.vhd:319:33 */ + always @* + case (n868_o) + 7'b1000000: n874_o = n873_o; + 7'b0100000: n874_o = n873_o; + 7'b0010000: n874_o = zo; + 7'b0001000: n874_o = n873_o; + 7'b0000100: n874_o = n872_o; + 7'b0000010: n874_o = n873_o; + 7'b0000001: n874_o = zo; + default: n874_o = n873_o; + endcase + assign n875_o = di[2]; + assign n876_o = p[2]; + /* HUC6280_CPU.vhd:319:33 */ + always @* + case (n868_o) + 7'b1000000: n877_o = n876_o; + 7'b0100000: n877_o = n876_o; + 7'b0010000: n877_o = n876_o; + 7'b0001000: n877_o = n853_o; + 7'b0000100: n877_o = n875_o; + 7'b0000010: n877_o = 1'b1; + 7'b0000001: n877_o = n876_o; + default: n877_o = n876_o; + endcase + assign n878_o = di[3]; + assign n879_o = p[3]; + /* HUC6280_CPU.vhd:319:33 */ + always @* + case (n868_o) + 7'b1000000: n880_o = n879_o; + 7'b0100000: n880_o = n879_o; + 7'b0010000: n880_o = n879_o; + 7'b0001000: n880_o = n855_o; + 7'b0000100: n880_o = n878_o; + 7'b0000010: n880_o = 1'b0; + 7'b0000001: n880_o = n879_o; + default: n880_o = n879_o; + endcase + assign n881_o = di[4]; + assign n882_o = p[4]; + /* HUC6280_CPU.vhd:319:33 */ + always @* + case (n868_o) + 7'b1000000: n883_o = n882_o; + 7'b0100000: n883_o = n882_o; + 7'b0010000: n883_o = n882_o; + 7'b0001000: n883_o = n882_o; + 7'b0000100: n883_o = n881_o; + 7'b0000010: n883_o = n882_o; + 7'b0000001: n883_o = n882_o; + default: n883_o = n882_o; + endcase + assign n884_o = di[5]; + assign n885_o = p[5]; + /* HUC6280_CPU.vhd:319:33 */ + always @* + case (n868_o) + 7'b1000000: n886_o = 1'b0; + 7'b0100000: n886_o = 1'b1; + 7'b0010000: n886_o = n885_o; + 7'b0001000: n886_o = n885_o; + 7'b0000100: n886_o = n884_o; + 7'b0000010: n886_o = n885_o; + 7'b0000001: n886_o = n885_o; + default: n886_o = n885_o; + endcase + assign n887_o = di[6]; + assign n888_o = p[6]; + /* HUC6280_CPU.vhd:319:33 */ + always @* + case (n868_o) + 7'b1000000: n889_o = n888_o; + 7'b0100000: n889_o = n888_o; + 7'b0010000: n889_o = vo; + 7'b0001000: n889_o = n857_o; + 7'b0000100: n889_o = n887_o; + 7'b0000010: n889_o = n888_o; + 7'b0000001: n889_o = n888_o; + default: n889_o = n888_o; + endcase + assign n890_o = di[7]; + assign n891_o = p[7]; + /* HUC6280_CPU.vhd:319:33 */ + always @* + case (n868_o) + 7'b1000000: n892_o = n891_o; + 7'b0100000: n892_o = n891_o; + 7'b0010000: n892_o = no; + 7'b0001000: n892_o = n891_o; + 7'b0000100: n892_o = n890_o; + 7'b0000010: n892_o = n891_o; + 7'b0000001: n892_o = no; + default: n892_o = n891_o; + endcase + /* HUC6280_CPU.vhd:348:44 */ + assign n894_o = next_ir != 8'b00000000; + /* HUC6280_CPU.vhd:348:63 */ + assign n896_o = state == 5'b00000; + /* HUC6280_CPU.vhd:348:53 */ + assign n897_o = n894_o & n896_o; + /* HUC6280_CPU.vhd:348:33 */ + assign n899_o = n897_o ? 1'b0 : n886_o; + assign n900_o = {n892_o, n889_o, n899_o, n883_o, n880_o, n877_o, n874_o, n871_o}; + /* HUC6280_CPU.vhd:357:26 */ + assign n908_o = ~rst_n; + /* HUC6280_CPU.vhd:363:41 */ + assign n910_o = mc[6:5]; + /* HUC6280_CPU.vhd:364:41 */ + assign n912_o = n910_o == 2'b01; + /* HUC6280_CPU.vhd:365:41 */ + assign n914_o = n910_o == 2'b10; + /* HUC6280_CPU.vhd:366:41 */ + assign n916_o = n910_o == 2'b11; + assign n917_o = {n916_o, n914_o, n912_o}; + /* HUC6280_CPU.vhd:363:33 */ + always @* + case (n917_o) + 3'b100: n918_o = sh; + 3'b010: n918_o = sh; + 3'b001: n918_o = alu_out; + default: n918_o = sh; + endcase + /* HUC6280_CPU.vhd:363:33 */ + always @* + case (n917_o) + 3'b100: n919_o = dh; + 3'b010: n919_o = alu_out; + 3'b001: n919_o = dh; + default: n919_o = dh; + endcase + /* HUC6280_CPU.vhd:363:33 */ + always @* + case (n917_o) + 3'b100: n920_o = alu_out; + 3'b010: n920_o = lh; + 3'b001: n920_o = lh; + default: n920_o = lh; + endcase + /* HUC6280_CPU.vhd:375:26 */ + assign n936_o = ~rst_n; + /* HUC6280_CPU.vhd:386:39 */ + assign n947_o = ir == 8'b01010011; + /* HUC6280_CPU.vhd:386:47 */ + assign n948_o = n947_o & last_cycle; + /* HUC6280_CPU.vhd:388:53 */ + assign n949_o = t[0]; + assign n950_o = mpr[63:56]; + /* HUC6280_CPU.vhd:388:49 */ + assign n951_o = n949_o ? a : n950_o; + /* HUC6280_CPU.vhd:388:53 */ + assign n952_o = t[1]; + assign n953_o = mpr[55:48]; + /* HUC6280_CPU.vhd:388:49 */ + assign n954_o = n952_o ? a : n953_o; + /* HUC6280_CPU.vhd:388:53 */ + assign n955_o = t[2]; + assign n956_o = mpr[47:40]; + /* HUC6280_CPU.vhd:388:49 */ + assign n957_o = n955_o ? a : n956_o; + /* HUC6280_CPU.vhd:388:53 */ + assign n958_o = t[3]; + assign n959_o = mpr[39:32]; + /* HUC6280_CPU.vhd:388:49 */ + assign n960_o = n958_o ? a : n959_o; + /* HUC6280_CPU.vhd:388:53 */ + assign n961_o = t[4]; + assign n962_o = mpr[31:24]; + /* HUC6280_CPU.vhd:388:49 */ + assign n963_o = n961_o ? a : n962_o; + /* HUC6280_CPU.vhd:388:53 */ + assign n964_o = t[5]; + assign n965_o = mpr[23:16]; + /* HUC6280_CPU.vhd:388:49 */ + assign n966_o = n964_o ? a : n965_o; + /* HUC6280_CPU.vhd:388:53 */ + assign n967_o = t[6]; + assign n968_o = mpr[15:8]; + /* HUC6280_CPU.vhd:388:49 */ + assign n969_o = n967_o ? a : n968_o; + /* HUC6280_CPU.vhd:388:53 */ + assign n970_o = t[7]; + assign n971_o = mpr[7:0]; + /* HUC6280_CPU.vhd:388:49 */ + assign n972_o = n970_o ? a : n971_o; + assign n973_o = {n951_o, n954_o, n957_o, n960_o, n963_o, n966_o, n969_o, n972_o}; + /* HUC6280_CPU.vhd:385:25 */ + assign n976_o = en & n948_o; + /* HUC6280_CPU.vhd:385:25 */ + assign n977_o = en & n948_o; + assign n980_o = {8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000}; + /* HUC6280_CPU.vhd:398:23 */ + assign n984_o = mpr[63:56]; + /* HUC6280_CPU.vhd:398:33 */ + assign n985_o = t[0]; + /* HUC6280_CPU.vhd:398:27 */ + assign n986_o = n985_o ? n984_o : n989_o; + /* HUC6280_CPU.vhd:399:38 */ + assign n987_o = mpr[55:48]; + /* HUC6280_CPU.vhd:399:48 */ + assign n988_o = t[1]; + /* HUC6280_CPU.vhd:398:43 */ + assign n989_o = n988_o ? n987_o : n992_o; + /* HUC6280_CPU.vhd:400:38 */ + assign n990_o = mpr[47:40]; + /* HUC6280_CPU.vhd:400:48 */ + assign n991_o = t[2]; + /* HUC6280_CPU.vhd:399:58 */ + assign n992_o = n991_o ? n990_o : n995_o; + /* HUC6280_CPU.vhd:401:38 */ + assign n993_o = mpr[39:32]; + /* HUC6280_CPU.vhd:401:48 */ + assign n994_o = t[3]; + /* HUC6280_CPU.vhd:400:58 */ + assign n995_o = n994_o ? n993_o : n998_o; + /* HUC6280_CPU.vhd:402:38 */ + assign n996_o = mpr[31:24]; + /* HUC6280_CPU.vhd:402:48 */ + assign n997_o = t[4]; + /* HUC6280_CPU.vhd:401:58 */ + assign n998_o = n997_o ? n996_o : n1001_o; + /* HUC6280_CPU.vhd:403:38 */ + assign n999_o = mpr[23:16]; + /* HUC6280_CPU.vhd:403:48 */ + assign n1000_o = t[5]; + /* HUC6280_CPU.vhd:402:58 */ + assign n1001_o = n1000_o ? n999_o : n1004_o; + /* HUC6280_CPU.vhd:404:38 */ + assign n1002_o = mpr[15:8]; + /* HUC6280_CPU.vhd:404:48 */ + assign n1003_o = t[6]; + /* HUC6280_CPU.vhd:403:58 */ + assign n1004_o = n1003_o ? n1002_o : n1007_o; + /* HUC6280_CPU.vhd:405:38 */ + assign n1005_o = mpr[7:0]; + /* HUC6280_CPU.vhd:405:48 */ + assign n1006_o = t[7]; + /* HUC6280_CPU.vhd:404:58 */ + assign n1007_o = n1006_o ? n1005_o : mpr_last; + /* HUC6280_CPU.vhd:409:17 */ + assign n1008_o = mc[35:32]; + /* HUC6280_CPU.vhd:410:25 */ + assign n1010_o = n1008_o == 4'b0001; + /* HUC6280_CPU.vhd:411:35 */ + assign n1012_o = n1008_o == 4'b0010; + /* HUC6280_CPU.vhd:412:35 */ + assign n1014_o = n1008_o == 4'b0011; + /* HUC6280_CPU.vhd:413:35 */ + assign n1016_o = n1008_o == 4'b0100; + /* HUC6280_CPU.vhd:414:34 */ + assign n1017_o = p[7:5]; + /* HUC6280_CPU.vhd:414:50 */ + assign n1018_o = ~got_int; + /* HUC6280_CPU.vhd:414:47 */ + assign n1019_o = {n1017_o, n1018_o}; + /* HUC6280_CPU.vhd:414:66 */ + assign n1020_o = p[3:0]; + /* HUC6280_CPU.vhd:414:63 */ + assign n1021_o = {n1019_o, n1020_o}; + /* HUC6280_CPU.vhd:414:79 */ + assign n1023_o = n1008_o == 4'b0101; + /* HUC6280_CPU.vhd:415:35 */ + assign n1024_o = pc[15:8]; + /* HUC6280_CPU.vhd:415:49 */ + assign n1026_o = n1008_o == 4'b0110; + /* HUC6280_CPU.vhd:416:35 */ + assign n1027_o = pc[7:0]; + /* HUC6280_CPU.vhd:416:48 */ + assign n1029_o = n1008_o == 4'b0111; + assign n1031_o = {n1029_o, n1026_o, n1023_o, n1016_o, n1014_o, n1012_o, n1010_o}; + /* HUC6280_CPU.vhd:409:9 */ + always @* + case (n1031_o) + 7'b1000000: n1032_o = n1027_o; + 7'b0100000: n1032_o = n1024_o; + 7'b0010000: n1032_o = n1021_o; + 7'b0001000: n1032_o = t; + 7'b0000100: n1032_o = y; + 7'b0000010: n1032_o = x; + 7'b0000001: n1032_o = a; + default: n1032_o = 8'b00000000; + endcase + /* HUC6280_CPU.vhd:422:23 */ + assign n1035_o = mc[35:32]; + /* HUC6280_CPU.vhd:422:31 */ + assign n1037_o = n1035_o != 4'b0000; + /* HUC6280_CPU.vhd:422:53 */ + assign n1038_o = ~res_int; + /* HUC6280_CPU.vhd:422:41 */ + assign n1039_o = n1037_o & n1038_o; + /* HUC6280_CPU.vhd:422:17 */ + assign n1042_o = n1039_o ? 1'b0 : 1'b1; + /* HUC6280_CPU.vhd:429:26 */ + assign n1047_o = ~rst_n; + /* HUC6280_CPU.vhd:438:9 */ + huc6280_ag ag ( + .clk(clk), + .rst_n(rst_n), + .ce(en), + .pc_ctrl(n1054_o), + .addr_ctrl(n1055_o), + .got_int(got_int), + .di(di), + .x(x), + .y(y), + .dr(dr), + .pc(ag_pc), + .aa(ag_aa)); + /* HUC6280_CPU.vhd:443:39 */ + assign n1054_o = mc[21:19]; + /* HUC6280_CPU.vhd:444:39 */ + assign n1055_o = mc[18:13]; + /* HUC6280_CPU.vhd:457:26 */ + assign n1060_o = ~rst_n; + /* HUC6280_CPU.vhd:461:36 */ + assign n1062_o = ~res_int; + /* HUC6280_CPU.vhd:463:42 */ + assign n1063_o = ~nmi_n; + /* HUC6280_CPU.vhd:463:48 */ + assign n1064_o = n1063_o & old_nmi_n; + /* HUC6280_CPU.vhd:463:81 */ + assign n1065_o = ~nmi_sync; + /* HUC6280_CPU.vhd:463:68 */ + assign n1066_o = n1064_o & n1065_o; + /* HUC6280_CPU.vhd:465:56 */ + assign n1067_o = nmi_active & last_cycle; + /* HUC6280_CPU.vhd:465:77 */ + assign n1068_o = n1067_o & en; + /* HUC6280_CPU.vhd:465:33 */ + assign n1070_o = n1068_o ? 1'b0 : nmi_sync; + /* HUC6280_CPU.vhd:463:33 */ + assign n1072_o = n1066_o ? 1'b1 : n1070_o; + /* HUC6280_CPU.vhd:474:26 */ + assign n1084_o = ~rst_n; + /* HUC6280_CPU.vhd:483:38 */ + assign n1086_o = rdy & ce; + /* HUC6280_CPU.vhd:486:53 */ + assign n1087_o = last_cycle & en; + /* HUC6280_CPU.vhd:487:52 */ + assign n1088_o = ~got_int; + /* HUC6280_CPU.vhd:488:62 */ + assign n1089_o = ~irq1_n; + /* HUC6280_CPU.vhd:488:76 */ + assign n1090_o = ~irq2_n; + /* HUC6280_CPU.vhd:488:73 */ + assign n1091_o = n1089_o | n1090_o; + /* HUC6280_CPU.vhd:488:90 */ + assign n1092_o = ~irqt_n; + /* HUC6280_CPU.vhd:488:87 */ + assign n1093_o = n1091_o | n1092_o; + /* HUC6280_CPU.vhd:488:111 */ + assign n1094_o = p[2]; + /* HUC6280_CPU.vhd:488:106 */ + assign n1095_o = ~n1094_o; + /* HUC6280_CPU.vhd:488:102 */ + assign n1096_o = n1093_o & n1095_o; + /* HUC6280_CPU.vhd:488:121 */ + assign n1097_o = n1096_o | nmi_active; + /* HUC6280_CPU.vhd:486:33 */ + assign n1099_o = n1122_o ? 1'b0 : nmi_sync; + /* HUC6280_CPU.vhd:487:41 */ + assign n1101_o = n1088_o ? n1097_o : 1'b0; + /* HUC6280_CPU.vhd:487:41 */ + assign n1102_o = n1088_o & nmi_active; + /* HUC6280_CPU.vhd:498:53 */ + assign n1103_o = ~irq1_n; + /* HUC6280_CPU.vhd:498:73 */ + assign n1104_o = p[2]; + /* HUC6280_CPU.vhd:498:68 */ + assign n1105_o = ~n1104_o; + /* HUC6280_CPU.vhd:498:64 */ + assign n1106_o = n1103_o & n1105_o; + /* HUC6280_CPU.vhd:499:53 */ + assign n1107_o = ~irq2_n; + /* HUC6280_CPU.vhd:499:73 */ + assign n1108_o = p[2]; + /* HUC6280_CPU.vhd:499:68 */ + assign n1109_o = ~n1108_o; + /* HUC6280_CPU.vhd:499:64 */ + assign n1110_o = n1107_o & n1109_o; + /* HUC6280_CPU.vhd:500:53 */ + assign n1111_o = ~irqt_n; + /* HUC6280_CPU.vhd:500:73 */ + assign n1112_o = p[2]; + /* HUC6280_CPU.vhd:500:68 */ + assign n1113_o = ~n1112_o; + /* HUC6280_CPU.vhd:500:64 */ + assign n1114_o = n1111_o & n1113_o; + /* HUC6280_CPU.vhd:486:33 */ + assign n1122_o = n1087_o & n1102_o; + /* HUC6280_CPU.vhd:483:25 */ + assign n1123_o = n1086_o & n1087_o; + /* HUC6280_CPU.vhd:483:25 */ + assign n1124_o = n1086_o & n1087_o; + /* HUC6280_CPU.vhd:483:25 */ + assign n1125_o = n1086_o & n1087_o; + /* HUC6280_CPU.vhd:483:25 */ + assign n1126_o = n1086_o & n1087_o; + /* HUC6280_CPU.vhd:483:25 */ + assign n1127_o = n1086_o & n1087_o; + /* HUC6280_CPU.vhd:483:25 */ + assign n1128_o = n1086_o & n1087_o; + /* HUC6280_CPU.vhd:506:32 */ + assign n1154_o = ir == 8'b00000000; + /* HUC6280_CPU.vhd:506:52 */ + assign n1155_o = ~got_int; + /* HUC6280_CPU.vhd:506:40 */ + assign n1156_o = n1154_o & n1155_o; + /* HUC6280_CPU.vhd:506:24 */ + assign n1157_o = n1156_o ? 1'b1 : 1'b0; + /* HUC6280_CPU.vhd:511:25 */ + assign n1161_o = mc[4:2]; + /* HUC6280_CPU.vhd:512:25 */ + assign n1163_o = n1161_o == 3'b000; + /* HUC6280_CPU.vhd:514:25 */ + assign n1165_o = n1161_o == 3'b001; + /* HUC6280_CPU.vhd:517:51 */ + assign n1167_o = {8'b00100001, sp}; + /* HUC6280_CPU.vhd:516:25 */ + assign n1169_o = n1161_o == 3'b010; + /* HUC6280_CPU.vhd:519:55 */ + assign n1170_o = aa[7:0]; + /* HUC6280_CPU.vhd:519:51 */ + assign n1172_o = {8'b00100000, n1170_o}; + /* HUC6280_CPU.vhd:518:25 */ + assign n1174_o = n1161_o == 3'b011; + /* HUC6280_CPU.vhd:523:78 */ + assign n1176_o = state[0]; + /* HUC6280_CPU.vhd:523:71 */ + assign n1178_o = {3'b111, n1176_o}; + /* HUC6280_CPU.vhd:525:78 */ + assign n1179_o = state[0]; + /* HUC6280_CPU.vhd:525:71 */ + assign n1181_o = {3'b110, n1179_o}; + /* HUC6280_CPU.vhd:527:78 */ + assign n1182_o = state[0]; + /* HUC6280_CPU.vhd:527:71 */ + assign n1184_o = {3'b011, n1182_o}; + /* HUC6280_CPU.vhd:529:78 */ + assign n1185_o = state[0]; + /* HUC6280_CPU.vhd:529:71 */ + assign n1187_o = {3'b101, n1185_o}; + /* HUC6280_CPU.vhd:531:78 */ + assign n1188_o = state[0]; + /* HUC6280_CPU.vhd:531:71 */ + assign n1190_o = {3'b100, n1188_o}; + /* HUC6280_CPU.vhd:533:78 */ + assign n1191_o = state[0]; + /* HUC6280_CPU.vhd:533:71 */ + assign n1193_o = {3'b011, n1191_o}; + /* HUC6280_CPU.vhd:535:78 */ + assign n1194_o = state[0]; + /* HUC6280_CPU.vhd:535:71 */ + assign n1196_o = {3'b111, n1194_o}; + /* HUC6280_CPU.vhd:532:33 */ + assign n1197_o = irq2_int ? n1193_o : n1196_o; + /* HUC6280_CPU.vhd:530:33 */ + assign n1198_o = irq1_int ? n1190_o : n1197_o; + /* HUC6280_CPU.vhd:528:33 */ + assign n1199_o = irqt_int ? n1187_o : n1198_o; + /* HUC6280_CPU.vhd:526:33 */ + assign n1200_o = brk_int ? n1184_o : n1199_o; + /* HUC6280_CPU.vhd:524:33 */ + assign n1201_o = nmi_int ? n1181_o : n1200_o; + /* HUC6280_CPU.vhd:522:33 */ + assign n1202_o = res_int ? n1178_o : n1201_o; + /* HUC6280_CPU.vhd:520:25 */ + assign n1204_o = n1161_o == 3'b100; + /* HUC6280_CPU.vhd:538:72 */ + assign n1206_o = {11'b00000000000, vdcnum}; + /* HUC6280_CPU.vhd:538:81 */ + assign n1208_o = {n1206_o, 2'b00}; + /* HUC6280_CPU.vhd:539:40 */ + assign n1209_o = ir[5:4]; + /* HUC6280_CPU.vhd:540:41 */ + assign n1212_o = n1209_o == 2'b00; + /* HUC6280_CPU.vhd:541:41 */ + assign n1215_o = n1209_o == 2'b01; + assign n1217_o = {n1215_o, n1212_o}; + /* HUC6280_CPU.vhd:539:33 */ + always @* + case (n1217_o) + 2'b10: n1218_o = 2'b10; + 2'b01: n1218_o = 2'b00; + default: n1218_o = 2'b11; + endcase + /* HUC6280_CPU.vhd:537:25 */ + assign n1220_o = n1161_o == 3'b101; + /* HUC6280_CPU.vhd:545:48 */ + assign n1221_o = {sh, x}; + /* HUC6280_CPU.vhd:544:25 */ + assign n1223_o = n1161_o == 3'b110; + /* HUC6280_CPU.vhd:547:48 */ + assign n1224_o = {dh, y}; + /* HUC6280_CPU.vhd:546:25 */ + assign n1226_o = n1161_o == 3'b111; + assign n1227_o = {n1226_o, n1223_o, n1220_o, n1204_o, n1174_o, n1169_o, n1165_o, n1163_o}; + assign n1228_o = pc[1:0]; + assign n1229_o = aa[1:0]; + assign n1230_o = n1167_o[1:0]; + assign n1231_o = n1172_o[1:0]; + assign n1232_o = n1202_o[1:0]; + assign n1233_o = n1221_o[1:0]; + assign n1234_o = n1224_o[1:0]; + assign n1235_o = addr_bus[1:0]; + /* HUC6280_CPU.vhd:511:17 */ + always @* + case (n1227_o) + 8'b10000000: n1236_o = n1234_o; + 8'b01000000: n1236_o = n1233_o; + 8'b00100000: n1236_o = n1218_o; + 8'b00010000: n1236_o = n1232_o; + 8'b00001000: n1236_o = n1231_o; + 8'b00000100: n1236_o = n1230_o; + 8'b00000010: n1236_o = n1229_o; + 8'b00000001: n1236_o = n1228_o; + default: n1236_o = n1235_o; + endcase + assign n1237_o = pc[3:2]; + assign n1238_o = aa[3:2]; + assign n1239_o = n1167_o[3:2]; + assign n1240_o = n1172_o[3:2]; + assign n1241_o = n1202_o[3:2]; + assign n1242_o = n1208_o[1:0]; + assign n1243_o = n1221_o[3:2]; + assign n1244_o = n1224_o[3:2]; + assign n1245_o = addr_bus[3:2]; + /* HUC6280_CPU.vhd:511:17 */ + always @* + case (n1227_o) + 8'b10000000: n1246_o = n1244_o; + 8'b01000000: n1246_o = n1243_o; + 8'b00100000: n1246_o = n1242_o; + 8'b00010000: n1246_o = n1241_o; + 8'b00001000: n1246_o = n1240_o; + 8'b00000100: n1246_o = n1239_o; + 8'b00000010: n1246_o = n1238_o; + 8'b00000001: n1246_o = n1237_o; + default: n1246_o = n1245_o; + endcase + assign n1247_o = pc[15:4]; + assign n1248_o = aa[15:4]; + assign n1249_o = n1167_o[15:4]; + assign n1250_o = n1172_o[15:4]; + assign n1251_o = n1208_o[13:2]; + assign n1252_o = n1221_o[15:4]; + assign n1253_o = n1224_o[15:4]; + assign n1254_o = addr_bus[15:4]; + /* HUC6280_CPU.vhd:511:17 */ + always @* + case (n1227_o) + 8'b10000000: n1255_o = n1253_o; + 8'b01000000: n1255_o = n1252_o; + 8'b00100000: n1255_o = n1251_o; + 8'b00010000: n1255_o = 12'b111111111111; + 8'b00001000: n1255_o = n1250_o; + 8'b00000100: n1255_o = n1249_o; + 8'b00000010: n1255_o = n1248_o; + 8'b00000001: n1255_o = n1247_o; + default: n1255_o = n1254_o; + endcase + /* HUC6280_CPU.vhd:552:39 */ + assign n1257_o = addr_bus[12:0]; + /* HUC6280_CPU.vhd:553:46 */ + assign n1259_o = mc[4:2]; + /* HUC6280_CPU.vhd:553:55 */ + assign n1261_o = n1259_o == 3'b101; + /* HUC6280_CPU.vhd:553:38 */ + assign n1262_o = n1261_o ? 8'b11111111 : n1369_o; + /* HUC6280_CPU.vhd:553:100 */ + assign n1263_o = addr_bus[15:13]; + /* HUC6280_CPU.vhd:553:72 */ + assign n1266_o = 3'b111 - n1263_o; + /* HUC6280_CPU.vhd:557:26 */ + assign n1271_o = ~rst_n; + /* HUC6280_CPU.vhd:561:38 */ + assign n1273_o = ir[6:0]; + /* HUC6280_CPU.vhd:561:51 */ + assign n1275_o = n1273_o == 7'b1010100; + /* HUC6280_CPU.vhd:561:73 */ + assign n1277_o = state == 5'b00001; + /* HUC6280_CPU.vhd:561:63 */ + assign n1278_o = n1275_o & n1277_o; + /* HUC6280_CPU.vhd:562:49 */ + assign n1279_o = ir[7]; + /* HUC6280_CPU.vhd:560:25 */ + assign n1281_o = en & n1278_o; + /* HUC6280_CPU.vhd:568:22 */ + assign n1286_o = mc[36]; + /* HUC6280_CPU.vhd:261:17 */ + assign n1287_o = n768_o ? alu_out : a; + /* HUC6280_CPU.vhd:261:17 */ + always @(posedge clk or posedge n760_o) + if (n760_o) + n1288_q <= 8'b00000000; + else + n1288_q <= n1287_o; + /* HUC6280_CPU.vhd:261:17 */ + assign n1289_o = n769_o ? alu_out : x; + /* HUC6280_CPU.vhd:261:17 */ + always @(posedge clk or posedge n760_o) + if (n760_o) + n1290_q <= 8'b00000000; + else + n1290_q <= n1289_o; + /* HUC6280_CPU.vhd:261:17 */ + assign n1291_o = n770_o ? alu_out : y; + /* HUC6280_CPU.vhd:261:17 */ + always @(posedge clk or posedge n760_o) + if (n760_o) + n1292_q <= 8'b00000000; + else + n1292_q <= n1291_o; + /* HUC6280_CPU.vhd:297:17 */ + assign n1293_o = en ? n817_o : sp; + /* HUC6280_CPU.vhd:297:17 */ + always @(posedge clk or posedge n803_o) + if (n803_o) + n1294_q <= 8'b00000000; + else + n1294_q <= n1293_o; + /* HUC6280_CPU.vhd:317:17 */ + assign n1295_o = en ? n900_o : p; + /* HUC6280_CPU.vhd:317:17 */ + always @(posedge clk or posedge n825_o) + if (n825_o) + n1296_q <= 8'b00000100; + else + n1296_q <= n1295_o; + /* HUC6280_CPU.vhd:280:17 */ + assign n1297_o = en ? n795_o : t; + /* HUC6280_CPU.vhd:280:17 */ + always @(posedge clk or posedge n783_o) + if (n783_o) + n1298_q <= 8'b00000000; + else + n1298_q <= n1297_o; + /* HUC6280_CPU.vhd:431:17 */ + assign n1299_o = en ? di : dr; + /* HUC6280_CPU.vhd:431:17 */ + always @(posedge clk or posedge n1047_o) + if (n1047_o) + n1300_q <= 8'b00000000; + else + n1300_q <= n1299_o; + /* HUC6280_CPU.vhd:361:17 */ + assign n1301_o = en ? n918_o : sh; + /* HUC6280_CPU.vhd:361:17 */ + always @(posedge clk or posedge n908_o) + if (n908_o) + n1302_q <= 8'b00000000; + else + n1302_q <= n1301_o; + /* HUC6280_CPU.vhd:361:17 */ + assign n1303_o = en ? n919_o : dh; + /* HUC6280_CPU.vhd:361:17 */ + always @(posedge clk or posedge n908_o) + if (n908_o) + n1304_q <= 8'b00000000; + else + n1304_q <= n1303_o; + /* HUC6280_CPU.vhd:361:17 */ + assign n1305_o = en ? n920_o : lh; + /* HUC6280_CPU.vhd:361:17 */ + always @(posedge clk or posedge n908_o) + if (n908_o) + n1306_q <= 8'b00000000; + else + n1306_q <= n1305_o; + /* HUC6280_CPU.vhd:384:17 */ + assign n1307_o = n976_o ? n973_o : mpr; + /* HUC6280_CPU.vhd:384:17 */ + always @(posedge clk or posedge n936_o) + if (n936_o) + n1308_q <= n980_o; + else + n1308_q <= n1307_o; + /* HUC6280_CPU.vhd:163:17 */ + assign n1309_o = en ? next_ir : ir; + /* HUC6280_CPU.vhd:163:17 */ + always @(posedge clk or posedge n632_o) + if (n632_o) + n1310_q <= 8'b00000000; + else + n1310_q <= n1309_o; + /* HUC6280_CPU.vhd:163:17 */ + assign n1311_o = en ? next_state : state; + /* HUC6280_CPU.vhd:163:17 */ + always @(posedge clk or posedge n632_o) + if (n632_o) + n1312_q <= 5'b00000; + else + n1312_q <= n1311_o; + /* HUC6280_CPU.vhd:177:17 */ + assign n1313_o = en ? n659_o : talt; + /* HUC6280_CPU.vhd:177:17 */ + always @(posedge clk or posedge n650_o) + if (n650_o) + n1314_q <= 1'b0; + else + n1314_q <= n1313_o; + /* HUC6280_CPU.vhd:175:17 */ + assign n1315_o = {n1255_o, n1246_o, n1236_o}; + /* HUC6280_CPU.vhd:373:9 */ + assign n1316_o = ~n936_o; + /* HUC6280_CPU.vhd:373:9 */ + assign n1317_o = n977_o & n1316_o; + /* HUC6280_CPU.vhd:384:17 */ + assign n1318_o = n1317_o ? a : mpr_last; + /* HUC6280_CPU.vhd:384:17 */ + always @(posedge clk) + n1319_q <= n1318_o; + /* HUC6280_CPU.vhd:375:17 */ + assign n1320_o = {n689_o, n688_o, n690_o}; + /* HUC6280_CPU.vhd:482:17 */ + assign n1321_o = n1123_o ? n1101_o : got_int; + /* HUC6280_CPU.vhd:482:17 */ + always @(posedge clk or posedge n1084_o) + if (n1084_o) + n1322_q <= 1'b1; + else + n1322_q <= n1321_o; + /* HUC6280_CPU.vhd:482:17 */ + assign n1323_o = n1124_o ? 1'b0 : res_int; + /* HUC6280_CPU.vhd:482:17 */ + always @(posedge clk or posedge n1084_o) + if (n1084_o) + n1324_q <= 1'b1; + else + n1324_q <= n1323_o; + /* HUC6280_CPU.vhd:482:17 */ + assign n1325_o = n1125_o ? nmi_active : nmi_int; + /* HUC6280_CPU.vhd:482:17 */ + always @(posedge clk or posedge n1084_o) + if (n1084_o) + n1326_q <= 1'b0; + else + n1326_q <= n1325_o; + /* HUC6280_CPU.vhd:482:17 */ + assign n1327_o = n1126_o ? n1106_o : irq1_int; + /* HUC6280_CPU.vhd:482:17 */ + always @(posedge clk or posedge n1084_o) + if (n1084_o) + n1328_q <= 1'b0; + else + n1328_q <= n1327_o; + /* HUC6280_CPU.vhd:482:17 */ + assign n1329_o = n1127_o ? n1110_o : irq2_int; + /* HUC6280_CPU.vhd:482:17 */ + always @(posedge clk or posedge n1084_o) + if (n1084_o) + n1330_q <= 1'b0; + else + n1330_q <= n1329_o; + /* HUC6280_CPU.vhd:482:17 */ + assign n1331_o = n1128_o ? n1114_o : irqt_int; + /* HUC6280_CPU.vhd:482:17 */ + always @(posedge clk or posedge n1084_o) + if (n1084_o) + n1332_q <= 1'b0; + else + n1332_q <= n1331_o; + /* HUC6280_CPU.vhd:460:17 */ + assign n1333_o = n1062_o ? nmi_n : old_nmi_n; + /* HUC6280_CPU.vhd:460:17 */ + always @(posedge clk or posedge n1060_o) + if (n1060_o) + n1334_q <= 1'b1; + else + n1334_q <= n1333_o; + /* HUC6280_CPU.vhd:460:17 */ + assign n1335_o = n1062_o ? n1072_o : nmi_sync; + /* HUC6280_CPU.vhd:460:17 */ + always @(posedge clk or posedge n1060_o) + if (n1060_o) + n1336_q <= 1'b0; + else + n1336_q <= n1335_o; + /* HUC6280_CPU.vhd:482:17 */ + assign n1337_o = n1086_o ? n1099_o : nmi_active; + /* HUC6280_CPU.vhd:482:17 */ + always @(posedge clk or posedge n1084_o) + if (n1084_o) + n1338_q <= 1'b0; + else + n1338_q <= n1337_o; + /* HUC6280_CPU.vhd:474:17 */ + assign n1339_o = {n1262_o, n1257_o}; + /* HUC6280_CPU.vhd:559:17 */ + assign n1340_o = n1281_o ? n1279_o : n1341_q; + /* HUC6280_CPU.vhd:559:17 */ + always @(posedge clk or posedge n1271_o) + if (n1271_o) + n1341_q <= 1'b0; + else + n1341_q <= n1340_o; + /* HUC6280_CPU.vhd:451:44 */ + assign n1342_o = dr[0]; + /* HUC6280_CPU.vhd:450:44 */ + assign n1343_o = dr[1]; + /* HUC6280_CPU.vhd:251:36 */ + assign n1344_o = dr[2]; + /* HUC6280_CPU.vhd:250:36 */ + assign n1345_o = dr[3]; + /* HUC6280_CPU.vhd:249:36 */ + assign n1346_o = dr[4]; + /* HUC6280_CPU.vhd:248:28 */ + assign n1347_o = dr[5]; + /* HUC6280_CPU.vhd:247:36 */ + assign n1348_o = dr[6]; + /* HUC6280_CPU.vhd:195:44 */ + assign n1349_o = dr[7]; + /* HUC6280_CPU.vhd:112:30 */ + assign n1350_o = n462_o[1:0]; + /* HUC6280_CPU.vhd:112:30 */ + always @* + case (n1350_o) + 2'b00: n1351_o = n1342_o; + 2'b01: n1351_o = n1343_o; + 2'b10: n1351_o = n1344_o; + 2'b11: n1351_o = n1345_o; + endcase + /* HUC6280_CPU.vhd:112:30 */ + assign n1352_o = n462_o[1:0]; + /* HUC6280_CPU.vhd:112:30 */ + always @* + case (n1352_o) + 2'b00: n1353_o = n1346_o; + 2'b01: n1353_o = n1347_o; + 2'b10: n1353_o = n1348_o; + 2'b11: n1353_o = n1349_o; + endcase + /* HUC6280_CPU.vhd:112:30 */ + assign n1354_o = n462_o[2]; + /* HUC6280_CPU.vhd:112:30 */ + assign n1355_o = n1354_o ? n1353_o : n1351_o; + /* HUC6280_CPU.vhd:112:30 */ + assign n1356_o = mpr[7:0]; + /* HUC6280_CPU.vhd:112:31 */ + assign n1357_o = mpr[15:8]; + /* HUC6280_CPU.vhd:559:17 */ + assign n1358_o = mpr[23:16]; + /* HUC6280_CPU.vhd:555:9 */ + assign n1359_o = mpr[31:24]; + /* HUC6280_CPU.vhd:553:72 */ + assign n1360_o = mpr[39:32]; + assign n1361_o = mpr[47:40]; + /* HUC6280_CPU.vhd:509:9 */ + assign n1362_o = mpr[55:48]; + assign n1363_o = mpr[63:56]; + /* HUC6280_CPU.vhd:553:71 */ + assign n1364_o = n1266_o[1:0]; + /* HUC6280_CPU.vhd:553:71 */ + always @* + case (n1364_o) + 2'b00: n1365_o = n1356_o; + 2'b01: n1365_o = n1357_o; + 2'b10: n1365_o = n1358_o; + 2'b11: n1365_o = n1359_o; + endcase + /* HUC6280_CPU.vhd:553:71 */ + assign n1366_o = n1266_o[1:0]; + /* HUC6280_CPU.vhd:553:71 */ + always @* + case (n1366_o) + 2'b00: n1367_o = n1360_o; + 2'b01: n1367_o = n1361_o; + 2'b10: n1367_o = n1362_o; + 2'b11: n1367_o = n1363_o; + endcase + /* HUC6280_CPU.vhd:553:71 */ + assign n1368_o = n1266_o[2]; + /* HUC6280_CPU.vhd:553:71 */ + assign n1369_o = n1368_o ? n1367_o : n1365_o; +endmodule + +module HUC6280 + (input CLK, + input RST_N, + input WAIT_N, + input [7:0] DI, + input RDY, + input NMI_N, + input IRQ1_N, + input IRQ2_N, + input [7:0] K, + input VDCNUM, + output SX, + output [20:0] A, + output [7:0] DO, + output WR_N, + output RD_N, + output CE, + output CEK_N, + output CE7_N, + output CER_N, + output PRE_RD, + output PRE_WR, + output HSM, + output [7:0] O, + output [23:0] AUD_LDATA, + output [23:0] AUD_RDATA); + wire cpu_ce; + wire cpu_cer; + wire io_ce; + wire en; + wire [7:0] cpu_di; + wire [7:0] cpu_do; + wire [20:0] cpu_a; + wire cpu_we_n; + wire cpu_cs; + wire cpu_mcycle; + wire cpu_irq1_n; + wire cpu_irq2_n; + wire cpu_irqt_n; + wire cpu_rdy; + wire [4:0] cpu_clk_cnt; + wire [2:0] io_clk_cnt; + wire vdc_sel_old; + wire [7:0] io_buf; + wire ram_sel; + wire vdc_sel; + wire vce_sel; + wire iop_sel; + wire psg_sel; + wire tmr_sel; + wire int_sel; + wire io_sel; + wire [2:0] int_mask; + wire [9:0] tmr_pre_cnt; + wire [6:0] tmr_value; + wire [6:0] tmr_latch; + wire tmr_en; + wire tmr_reload; + wire tmr_irq; + wire tmr_irq_ack; + wire n17_o; + wire n20_o; + wire n21_o; + wire n23_o; + wire n24_o; + wire n25_o; + wire n26_o; + wire n29_o; + wire n31_o; + wire n32_o; + wire n34_o; + wire n35_o; + wire n36_o; + wire n37_o; + wire n40_o; + wire [4:0] n42_o; + wire [4:0] n44_o; + wire n46_o; + wire [4:0] n48_o; + wire n50_o; + wire n53_o; + wire [2:0] n56_o; + wire n58_o; + wire n61_o; + wire [2:0] n64_o; + wire n84_o; + wire n85_o; + wire [20:0] core_a_out; + wire [7:0] core_do; + wire core_we_n; + wire core_mcycle; + wire core_cs; + wire n91_o; + wire n92_o; + wire n93_o; + wire n94_o; + wire n95_o; + wire n96_o; + wire n97_o; + wire [5:0] n99_o; + wire n101_o; + wire n102_o; + wire [7:0] n105_o; + wire n107_o; + wire [2:0] n108_o; + wire n110_o; + wire n111_o; + wire n112_o; + wire [7:0] n115_o; + wire n117_o; + wire [2:0] n118_o; + wire n120_o; + wire n121_o; + wire n122_o; + wire n126_o; + wire n128_o; + wire n129_o; + wire n130_o; + wire n131_o; + wire n132_o; + wire n133_o; + wire n134_o; + wire n136_o; + wire n138_o; + wire n140_o; + wire n141_o; + wire n142_o; + wire n143_o; + wire n144_o; + wire n145_o; + wire n146_o; + wire n161_o; + wire n162_o; + wire n163_o; + wire n164_o; + wire n165_o; + wire n166_o; + wire n167_o; + wire n168_o; + wire [7:0] n170_o; + wire n172_o; + wire [2:0] n173_o; + wire n175_o; + wire n176_o; + wire n177_o; + wire n181_o; + wire n183_o; + wire n184_o; + wire n186_o; + wire [7:0] n192_o; + wire n194_o; + wire [2:0] n195_o; + wire n197_o; + wire n198_o; + wire n199_o; + wire n203_o; + wire n205_o; + wire n206_o; + wire [1:0] n207_o; + wire [2:0] n208_o; + wire n210_o; + wire n212_o; + wire [1:0] n213_o; + reg [2:0] n214_o; + reg n217_o; + wire [1:0] n218_o; + wire n220_o; + reg n223_o; + wire n225_o; + wire n226_o; + wire n228_o; + wire [7:0] n238_o; + wire n240_o; + wire [2:0] n241_o; + wire n243_o; + wire n244_o; + wire n245_o; + wire n249_o; + wire n251_o; + wire n252_o; + wire n253_o; + wire n254_o; + wire n255_o; + wire [6:0] n256_o; + wire n257_o; + wire n258_o; + wire n259_o; + wire n260_o; + wire [9:0] n262_o; + wire [6:0] n263_o; + wire [9:0] n264_o; + wire [6:0] n265_o; + wire n267_o; + wire [9:0] n268_o; + wire [6:0] n269_o; + wire n270_o; + wire n273_o; + wire [9:0] n275_o; + wire n277_o; + wire [6:0] n279_o; + wire n281_o; + wire n284_o; + wire n286_o; + wire [6:0] n287_o; + wire n289_o; + wire n290_o; + wire [9:0] n291_o; + wire n292_o; + wire n294_o; + wire n296_o; + wire [6:0] n297_o; + wire n298_o; + wire [6:0] n299_o; + wire n301_o; + wire [7:0] n322_o; + wire n324_o; + wire [2:0] n325_o; + wire n327_o; + wire n328_o; + wire n329_o; + wire n331_o; + wire n332_o; + wire n333_o; + wire n336_o; + wire n338_o; + wire [7:0] n339_o; + wire n341_o; + wire n349_o; + wire [1:0] n350_o; + wire [4:0] n351_o; + wire [7:0] n352_o; + wire n354_o; + wire [4:0] n355_o; + wire [5:0] n356_o; + wire n357_o; + wire [6:0] n358_o; + wire n359_o; + wire [7:0] n360_o; + wire n362_o; + wire [1:0] n363_o; + reg [7:0] n364_o; + wire n365_o; + wire [7:0] n366_o; + wire [7:0] n367_o; + wire [7:0] n368_o; + wire [7:0] n369_o; + wire [7:0] n371_o; + wire [7:0] n372_o; + reg n375_q; + reg n376_q; + reg n377_q; + reg [7:0] n378_q; + reg n379_q; + reg [4:0] n380_q; + reg [2:0] n381_q; + wire n382_o; + reg n383_q; + wire [7:0] n384_o; + reg [7:0] n385_q; + wire [2:0] n386_o; + reg [2:0] n387_q; + reg [9:0] n388_q; + reg [6:0] n389_q; + wire [6:0] n390_o; + reg [6:0] n391_q; + wire n392_o; + reg n393_q; + wire n394_o; + reg n395_q; + reg n396_q; + reg n397_q; + reg n398_q; + reg n399_q; + reg n400_q; + wire [7:0] n401_o; + reg [7:0] n402_q; + localparam [23:0] n403_o = 24'bZ; + localparam [23:0] n404_o = 24'bZ; + assign SX = n398_q; + assign A = cpu_a; + assign DO = cpu_do; + assign WR_N = n399_q; + assign RD_N = n400_q; + assign CE = n84_o; + assign CEK_N = n168_o; + assign CE7_N = n167_o; + assign CER_N = n166_o; + assign PRE_RD = n162_o; + assign PRE_WR = n165_o; + assign HSM = cpu_cs; + assign O = n402_q; + assign AUD_LDATA = n403_o; + assign AUD_RDATA = n404_o; + /* HUC6280.vhd:45:16 */ + assign cpu_ce = n375_q; // (signal) + /* HUC6280.vhd:46:16 */ + assign cpu_cer = n376_q; // (signal) + /* HUC6280.vhd:47:16 */ + assign io_ce = n377_q; // (signal) + /* HUC6280.vhd:48:16 */ + assign en = n85_o; // (signal) + /* HUC6280.vhd:50:16 */ + assign cpu_di = n378_q; // (signal) + /* HUC6280.vhd:51:16 */ + assign cpu_do = core_do; // (signal) + /* HUC6280.vhd:52:16 */ + assign cpu_a = core_a_out; // (signal) + /* HUC6280.vhd:53:16 */ + assign cpu_we_n = core_we_n; // (signal) + /* HUC6280.vhd:54:16 */ + assign cpu_cs = core_cs; // (signal) + /* HUC6280.vhd:55:16 */ + assign cpu_mcycle = core_mcycle; // (signal) + /* HUC6280.vhd:56:16 */ + assign cpu_irq1_n = n92_o; // (signal) + /* HUC6280.vhd:57:16 */ + assign cpu_irq2_n = n94_o; // (signal) + /* HUC6280.vhd:58:16 */ + assign cpu_irqt_n = n97_o; // (signal) + /* HUC6280.vhd:59:16 */ + assign cpu_rdy = n379_q; // (signal) + /* HUC6280.vhd:61:16 */ + assign cpu_clk_cnt = n380_q; // (signal) + /* HUC6280.vhd:62:16 */ + assign io_clk_cnt = n381_q; // (signal) + /* HUC6280.vhd:63:16 */ + assign vdc_sel_old = n383_q; // (signal) + /* HUC6280.vhd:66:16 */ + assign io_buf = n385_q; // (signal) + /* HUC6280.vhd:67:16 */ + assign ram_sel = n102_o; // (signal) + /* HUC6280.vhd:68:16 */ + assign vdc_sel = n112_o; // (signal) + /* HUC6280.vhd:69:16 */ + assign vce_sel = n122_o; // (signal) + /* HUC6280.vhd:70:16 */ + assign iop_sel = n177_o; // (signal) + /* HUC6280.vhd:71:16 */ + assign psg_sel = n329_o; // (signal) + /* HUC6280.vhd:72:16 */ + assign tmr_sel = n245_o; // (signal) + /* HUC6280.vhd:73:16 */ + assign int_sel = n199_o; // (signal) + /* HUC6280.vhd:74:16 */ + assign io_sel = n333_o; // (signal) + /* HUC6280.vhd:76:16 */ + assign int_mask = n387_q; // (signal) + /* HUC6280.vhd:77:16 */ + assign tmr_pre_cnt = n388_q; // (signal) + /* HUC6280.vhd:78:16 */ + assign tmr_value = n389_q; // (signal) + /* HUC6280.vhd:79:16 */ + assign tmr_latch = n391_q; // (signal) + /* HUC6280.vhd:80:16 */ + assign tmr_en = n393_q; // (signal) + /* HUC6280.vhd:81:16 */ + assign tmr_reload = n395_q; // (signal) + /* HUC6280.vhd:82:16 */ + assign tmr_irq = n396_q; // (signal) + /* HUC6280.vhd:83:16 */ + assign tmr_irq_ack = n397_q; // (signal) + /* HUC6280.vhd:90:26 */ + assign n17_o = ~RST_N; + /* HUC6280.vhd:99:41 */ + assign n20_o = cpu_clk_cnt == 5'b00010; + /* HUC6280.vhd:99:45 */ + assign n21_o = n20_o & cpu_cs; + /* HUC6280.vhd:99:79 */ + assign n23_o = cpu_clk_cnt == 5'b01011; + /* HUC6280.vhd:99:95 */ + assign n24_o = ~cpu_cs; + /* HUC6280.vhd:99:84 */ + assign n25_o = n23_o & n24_o; + /* HUC6280.vhd:99:63 */ + assign n26_o = n21_o | n25_o; + /* HUC6280.vhd:99:25 */ + assign n29_o = n26_o ? 1'b1 : 1'b0; + /* HUC6280.vhd:104:41 */ + assign n31_o = cpu_clk_cnt == 5'b00101; + /* HUC6280.vhd:104:45 */ + assign n32_o = n31_o & cpu_cs; + /* HUC6280.vhd:104:79 */ + assign n34_o = cpu_clk_cnt == 5'b10111; + /* HUC6280.vhd:104:95 */ + assign n35_o = ~cpu_cs; + /* HUC6280.vhd:104:84 */ + assign n36_o = n34_o & n35_o; + /* HUC6280.vhd:104:63 */ + assign n37_o = n32_o | n36_o; + /* HUC6280.vhd:105:33 */ + assign n40_o = WAIT_N ? 1'b1 : 1'b0; + /* HUC6280.vhd:105:33 */ + assign n42_o = WAIT_N ? 5'b00000 : cpu_clk_cnt; + /* HUC6280.vhd:110:60 */ + assign n44_o = cpu_clk_cnt + 5'b00001; + /* HUC6280.vhd:104:25 */ + assign n46_o = n37_o ? n40_o : 1'b0; + /* HUC6280.vhd:104:25 */ + assign n48_o = n37_o ? n42_o : n44_o; + /* HUC6280.vhd:114:40 */ + assign n50_o = cpu_clk_cnt == 5'b00001; + /* HUC6280.vhd:114:25 */ + assign n53_o = n50_o ? 1'b1 : 1'b0; + /* HUC6280.vhd:119:50 */ + assign n56_o = io_clk_cnt + 3'b001; + /* HUC6280.vhd:120:39 */ + assign n58_o = io_clk_cnt == 3'b101; + /* HUC6280.vhd:120:25 */ + assign n61_o = n58_o ? 1'b1 : 1'b0; + /* HUC6280.vhd:120:25 */ + assign n64_o = n58_o ? 3'b000 : n56_o; + /* HUC6280.vhd:127:22 */ + assign n84_o = cpu_ce & cpu_rdy; + /* HUC6280.vhd:129:22 */ + assign n85_o = cpu_ce & cpu_rdy; + /* HUC6280.vhd:132:9 */ + huc6280_cpu core ( + .clk(CLK), + .rst_n(RST_N), + .ce(cpu_ce), + .di(cpu_di), + .rdy(cpu_rdy), + .nmi_n(NMI_N), + .irq1_n(cpu_irq1_n), + .irq2_n(cpu_irq2_n), + .irqt_n(cpu_irqt_n), + .vdcnum(VDCNUM), + .a_out(core_a_out), + .dout(core_do), + .we_n(core_we_n), + .mcycle(core_mcycle), + .cs(core_cs)); + /* HUC6280.vhd:152:41 */ + assign n91_o = int_mask[1]; + /* HUC6280.vhd:152:30 */ + assign n92_o = IRQ1_N | n91_o; + /* HUC6280.vhd:153:41 */ + assign n93_o = int_mask[0]; + /* HUC6280.vhd:153:30 */ + assign n94_o = IRQ2_N | n93_o; + /* HUC6280.vhd:154:23 */ + assign n95_o = ~tmr_irq; + /* HUC6280.vhd:154:46 */ + assign n96_o = int_mask[2]; + /* HUC6280.vhd:154:35 */ + assign n97_o = n95_o | n96_o; + /* HUC6280.vhd:156:34 */ + assign n99_o = cpu_a[20:15]; + /* HUC6280.vhd:156:49 */ + assign n101_o = n99_o == 6'b111110; + /* HUC6280.vhd:156:24 */ + assign n102_o = n101_o ? 1'b1 : 1'b0; + /* HUC6280.vhd:157:34 */ + assign n105_o = cpu_a[20:13]; + /* HUC6280.vhd:157:49 */ + assign n107_o = n105_o == 8'b11111111; + /* HUC6280.vhd:157:66 */ + assign n108_o = cpu_a[12:10]; + /* HUC6280.vhd:157:81 */ + assign n110_o = n108_o == 3'b000; + /* HUC6280.vhd:157:57 */ + assign n111_o = n107_o & n110_o; + /* HUC6280.vhd:157:24 */ + assign n112_o = n111_o ? 1'b1 : 1'b0; + /* HUC6280.vhd:158:34 */ + assign n115_o = cpu_a[20:13]; + /* HUC6280.vhd:158:49 */ + assign n117_o = n115_o == 8'b11111111; + /* HUC6280.vhd:158:66 */ + assign n118_o = cpu_a[12:10]; + /* HUC6280.vhd:158:81 */ + assign n120_o = n118_o == 3'b001; + /* HUC6280.vhd:158:57 */ + assign n121_o = n117_o & n120_o; + /* HUC6280.vhd:158:24 */ + assign n122_o = n121_o ? 1'b1 : 1'b0; + /* HUC6280.vhd:162:26 */ + assign n126_o = ~RST_N; + /* HUC6280.vhd:171:49 */ + assign n128_o = ~cpu_we_n; + /* HUC6280.vhd:169:33 */ + assign n129_o = cpu_mcycle ? cpu_we_n : n399_q; + /* HUC6280.vhd:169:33 */ + assign n130_o = cpu_mcycle ? n128_o : n400_q; + /* HUC6280.vhd:174:56 */ + assign n131_o = vdc_sel | vce_sel; + /* HUC6280.vhd:175:51 */ + assign n132_o = vdc_sel | vce_sel; + /* HUC6280.vhd:175:85 */ + assign n133_o = ~vdc_sel_old; + /* HUC6280.vhd:175:69 */ + assign n134_o = n132_o & n133_o; + /* HUC6280.vhd:175:33 */ + assign n136_o = n134_o ? 1'b0 : cpu_rdy; + /* HUC6280.vhd:178:25 */ + assign n138_o = n141_o ? 1'b1 : n399_q; + /* HUC6280.vhd:178:25 */ + assign n140_o = n142_o ? 1'b1 : n400_q; + /* HUC6280.vhd:178:25 */ + assign n141_o = cpu_ce & cpu_rdy; + /* HUC6280.vhd:178:25 */ + assign n142_o = cpu_ce & cpu_rdy; + /* HUC6280.vhd:178:25 */ + assign n143_o = cpu_ce ? RDY : cpu_rdy; + /* HUC6280.vhd:168:25 */ + assign n144_o = cpu_cer ? n129_o : n138_o; + /* HUC6280.vhd:168:25 */ + assign n145_o = cpu_cer ? n130_o : n140_o; + /* HUC6280.vhd:168:25 */ + assign n146_o = cpu_cer ? n136_o : n143_o; + /* HUC6280.vhd:188:28 */ + assign n161_o = cpu_we_n & cpu_mcycle; + /* HUC6280.vhd:188:43 */ + assign n162_o = n161_o & RST_N; + /* HUC6280.vhd:189:19 */ + assign n163_o = ~cpu_we_n; + /* HUC6280.vhd:189:32 */ + assign n164_o = n163_o & cpu_mcycle; + /* HUC6280.vhd:189:47 */ + assign n165_o = n164_o & RST_N; + /* HUC6280.vhd:193:18 */ + assign n166_o = ~ram_sel; + /* HUC6280.vhd:194:18 */ + assign n167_o = ~vdc_sel; + /* HUC6280.vhd:195:18 */ + assign n168_o = ~vce_sel; + /* HUC6280.vhd:201:34 */ + assign n170_o = cpu_a[20:13]; + /* HUC6280.vhd:201:49 */ + assign n172_o = n170_o == 8'b11111111; + /* HUC6280.vhd:201:66 */ + assign n173_o = cpu_a[12:10]; + /* HUC6280.vhd:201:81 */ + assign n175_o = n173_o == 3'b100; + /* HUC6280.vhd:201:57 */ + assign n176_o = n172_o & n175_o; + /* HUC6280.vhd:201:24 */ + assign n177_o = n176_o ? 1'b1 : 1'b0; + /* HUC6280.vhd:204:26 */ + assign n181_o = ~RST_N; + /* HUC6280.vhd:208:63 */ + assign n183_o = ~cpu_we_n; + /* HUC6280.vhd:208:50 */ + assign n184_o = iop_sel & n183_o; + /* HUC6280.vhd:207:25 */ + assign n186_o = en & n184_o; + /* HUC6280.vhd:216:34 */ + assign n192_o = cpu_a[20:13]; + /* HUC6280.vhd:216:49 */ + assign n194_o = n192_o == 8'b11111111; + /* HUC6280.vhd:216:66 */ + assign n195_o = cpu_a[12:10]; + /* HUC6280.vhd:216:81 */ + assign n197_o = n195_o == 3'b101; + /* HUC6280.vhd:216:57 */ + assign n198_o = n194_o & n197_o; + /* HUC6280.vhd:216:24 */ + assign n199_o = n198_o ? 1'b1 : 1'b0; + /* HUC6280.vhd:219:26 */ + assign n203_o = ~RST_N; + /* HUC6280.vhd:224:42 */ + assign n205_o = int_sel & cpu_cer; + /* HUC6280.vhd:225:45 */ + assign n206_o = ~cpu_we_n; + /* HUC6280.vhd:226:51 */ + assign n207_o = cpu_a[1:0]; + /* HUC6280.vhd:228:75 */ + assign n208_o = cpu_do[2:0]; + /* HUC6280.vhd:227:49 */ + assign n210_o = n207_o == 2'b10; + /* HUC6280.vhd:229:49 */ + assign n212_o = n207_o == 2'b11; + assign n213_o = {n212_o, n210_o}; + /* HUC6280.vhd:226:41 */ + always @* + case (n213_o) + 2'b10: n214_o = int_mask; + 2'b01: n214_o = n208_o; + default: n214_o = int_mask; + endcase + /* HUC6280.vhd:226:41 */ + always @* + case (n213_o) + 2'b10: n217_o = 1'b1; + 2'b01: n217_o = 1'b0; + default: n217_o = 1'b0; + endcase + /* HUC6280.vhd:234:51 */ + assign n218_o = cpu_a[1:0]; + /* HUC6280.vhd:235:49 */ + assign n220_o = n218_o == 2'b10; + /* HUC6280.vhd:234:41 */ + always @* + case (n220_o) + 1'b1: n223_o = 1'b1; + default: n223_o = 1'b0; + endcase + /* HUC6280.vhd:225:33 */ + assign n225_o = n206_o ? n217_o : n223_o; + /* HUC6280.vhd:224:25 */ + assign n226_o = n205_o & n206_o; + /* HUC6280.vhd:224:25 */ + assign n228_o = n205_o ? n225_o : 1'b0; + /* HUC6280.vhd:246:34 */ + assign n238_o = cpu_a[20:13]; + /* HUC6280.vhd:246:49 */ + assign n240_o = n238_o == 8'b11111111; + /* HUC6280.vhd:246:66 */ + assign n241_o = cpu_a[12:10]; + /* HUC6280.vhd:246:81 */ + assign n243_o = n241_o == 3'b011; + /* HUC6280.vhd:246:57 */ + assign n244_o = n240_o & n243_o; + /* HUC6280.vhd:246:24 */ + assign n245_o = n244_o ? 1'b1 : 1'b0; + /* HUC6280.vhd:249:26 */ + assign n249_o = ~RST_N; + /* HUC6280.vhd:257:55 */ + assign n251_o = ~cpu_we_n; + /* HUC6280.vhd:257:42 */ + assign n252_o = tmr_sel & n251_o; + /* HUC6280.vhd:257:61 */ + assign n253_o = n252_o & cpu_cer; + /* HUC6280.vhd:258:41 */ + assign n254_o = cpu_a[0]; + /* HUC6280.vhd:258:45 */ + assign n255_o = ~n254_o; + /* HUC6280.vhd:260:60 */ + assign n256_o = cpu_do[6:0]; + /* HUC6280.vhd:263:57 */ + assign n257_o = cpu_do[0]; + /* HUC6280.vhd:264:51 */ + assign n258_o = ~tmr_en; + /* HUC6280.vhd:264:67 */ + assign n259_o = cpu_do[0]; + /* HUC6280.vhd:264:57 */ + assign n260_o = n258_o & n259_o; + /* HUC6280.vhd:264:41 */ + assign n262_o = n260_o ? 10'b1111111111 : tmr_pre_cnt; + /* HUC6280.vhd:264:41 */ + assign n263_o = n260_o ? tmr_latch : tmr_value; + /* HUC6280.vhd:258:33 */ + assign n264_o = n255_o ? tmr_pre_cnt : n262_o; + /* HUC6280.vhd:258:33 */ + assign n265_o = n255_o ? tmr_value : n263_o; + /* HUC6280.vhd:258:33 */ + assign n267_o = n255_o ? tmr_en : n257_o; + /* HUC6280.vhd:257:25 */ + assign n268_o = n253_o ? n264_o : tmr_pre_cnt; + /* HUC6280.vhd:257:25 */ + assign n269_o = n253_o ? n265_o : tmr_value; + /* HUC6280.vhd:257:25 */ + assign n270_o = n253_o & n255_o; + /* HUC6280.vhd:271:25 */ + assign n273_o = tmr_irq_ack ? 1'b0 : tmr_irq; + /* HUC6280.vhd:278:68 */ + assign n275_o = tmr_pre_cnt - 10'b0000000001; + /* HUC6280.vhd:279:56 */ + assign n277_o = tmr_pre_cnt == 10'b0000000000; + /* HUC6280.vhd:280:100 */ + assign n279_o = tmr_value - 7'b0000001; + /* HUC6280.vhd:281:62 */ + assign n281_o = tmr_value == 7'b0000000; + /* HUC6280.vhd:281:49 */ + assign n284_o = n281_o ? 1'b1 : 1'b0; + /* HUC6280.vhd:275:25 */ + assign n286_o = n301_o ? 1'b1 : n273_o; + /* HUC6280.vhd:277:33 */ + assign n287_o = n292_o ? n279_o : n269_o; + /* HUC6280.vhd:279:41 */ + assign n289_o = n277_o ? n284_o : 1'b0; + /* HUC6280.vhd:279:41 */ + assign n290_o = n277_o & n281_o; + /* HUC6280.vhd:275:25 */ + assign n291_o = n298_o ? n275_o : n268_o; + /* HUC6280.vhd:277:33 */ + assign n292_o = tmr_en & n277_o; + /* HUC6280.vhd:277:33 */ + assign n294_o = tmr_en ? n289_o : 1'b0; + /* HUC6280.vhd:277:33 */ + assign n296_o = tmr_en & n290_o; + /* HUC6280.vhd:288:33 */ + assign n297_o = tmr_reload ? tmr_latch : n287_o; + /* HUC6280.vhd:275:25 */ + assign n298_o = io_ce & tmr_en; + /* HUC6280.vhd:275:25 */ + assign n299_o = io_ce ? n297_o : n269_o; + /* HUC6280.vhd:275:25 */ + assign n301_o = io_ce & n296_o; + /* HUC6280.vhd:296:34 */ + assign n322_o = cpu_a[20:13]; + /* HUC6280.vhd:296:49 */ + assign n324_o = n322_o == 8'b11111111; + /* HUC6280.vhd:296:66 */ + assign n325_o = cpu_a[12:10]; + /* HUC6280.vhd:296:81 */ + assign n327_o = n325_o == 3'b010; + /* HUC6280.vhd:296:57 */ + assign n328_o = n324_o & n327_o; + /* HUC6280.vhd:296:24 */ + assign n329_o = n328_o ? 1'b1 : 1'b0; + /* HUC6280.vhd:313:27 */ + assign n331_o = iop_sel | int_sel; + /* HUC6280.vhd:313:38 */ + assign n332_o = n331_o | tmr_sel; + /* HUC6280.vhd:313:49 */ + assign n333_o = n332_o | psg_sel; + /* HUC6280.vhd:316:26 */ + assign n336_o = ~RST_N; + /* HUC6280.vhd:321:53 */ + assign n338_o = ~cpu_we_n; + /* HUC6280.vhd:321:41 */ + assign n339_o = n338_o ? cpu_do : cpu_di; + /* HUC6280.vhd:319:25 */ + assign n341_o = en & io_sel; + /* HUC6280.vhd:334:35 */ + assign n349_o = ~io_sel; + /* HUC6280.vhd:341:43 */ + assign n350_o = cpu_a[1:0]; + /* HUC6280.vhd:343:65 */ + assign n351_o = io_buf[7:3]; + /* HUC6280.vhd:343:78 */ + assign n352_o = {n351_o, int_mask}; + /* HUC6280.vhd:342:41 */ + assign n354_o = n350_o == 2'b10; + /* HUC6280.vhd:345:65 */ + assign n355_o = io_buf[7:3]; + /* HUC6280.vhd:345:78 */ + assign n356_o = {n355_o, tmr_irq}; + /* HUC6280.vhd:345:90 */ + assign n357_o = ~IRQ1_N; + /* HUC6280.vhd:345:88 */ + assign n358_o = {n356_o, n357_o}; + /* HUC6280.vhd:345:103 */ + assign n359_o = ~IRQ2_N; + /* HUC6280.vhd:345:101 */ + assign n360_o = {n358_o, n359_o}; + /* HUC6280.vhd:344:41 */ + assign n362_o = n350_o == 2'b11; + assign n363_o = {n362_o, n354_o}; + /* HUC6280.vhd:341:33 */ + always @* + case (n363_o) + 2'b10: n364_o = n360_o; + 2'b01: n364_o = n352_o; + default: n364_o = io_buf; + endcase + /* HUC6280.vhd:350:49 */ + assign n365_o = io_buf[7]; + /* HUC6280.vhd:350:53 */ + assign n366_o = {n365_o, tmr_value}; + /* HUC6280.vhd:349:25 */ + assign n367_o = tmr_sel ? n366_o : io_buf; + /* HUC6280.vhd:340:25 */ + assign n368_o = int_sel ? n364_o : n367_o; + /* HUC6280.vhd:338:25 */ + assign n369_o = iop_sel ? K : n368_o; + /* HUC6280.vhd:336:25 */ + assign n371_o = psg_sel ? 8'b00000000 : n369_o; + /* HUC6280.vhd:334:25 */ + assign n372_o = n349_o ? DI : n371_o; + /* HUC6280.vhd:97:17 */ + always @(posedge CLK or posedge n17_o) + if (n17_o) + n375_q <= 1'b0; + else + n375_q <= n46_o; + /* HUC6280.vhd:97:17 */ + always @(posedge CLK or posedge n17_o) + if (n17_o) + n376_q <= 1'b0; + else + n376_q <= n53_o; + /* HUC6280.vhd:97:17 */ + always @(posedge CLK or posedge n17_o) + if (n17_o) + n377_q <= 1'b0; + else + n377_q <= n61_o; + /* HUC6280.vhd:333:17 */ + always @(posedge CLK) + n378_q <= n372_o; + /* HUC6280.vhd:167:17 */ + always @(posedge CLK or posedge n126_o) + if (n126_o) + n379_q <= 1'b1; + else + n379_q <= n146_o; + /* HUC6280.vhd:97:17 */ + always @(posedge CLK or posedge n17_o) + if (n17_o) + n380_q <= 5'b00000; + else + n380_q <= n48_o; + /* HUC6280.vhd:97:17 */ + always @(posedge CLK or posedge n17_o) + if (n17_o) + n381_q <= 3'b000; + else + n381_q <= n64_o; + /* HUC6280.vhd:167:17 */ + assign n382_o = cpu_cer ? n131_o : vdc_sel_old; + /* HUC6280.vhd:167:17 */ + always @(posedge CLK or posedge n126_o) + if (n126_o) + n383_q <= 1'b0; + else + n383_q <= n382_o; + /* HUC6280.vhd:318:17 */ + assign n384_o = n341_o ? n339_o : io_buf; + /* HUC6280.vhd:318:17 */ + always @(posedge CLK or posedge n336_o) + if (n336_o) + n385_q <= 8'b11111111; + else + n385_q <= n384_o; + /* HUC6280.vhd:222:17 */ + assign n386_o = n226_o ? n214_o : int_mask; + /* HUC6280.vhd:222:17 */ + always @(posedge CLK or posedge n203_o) + if (n203_o) + n387_q <= 3'b000; + else + n387_q <= n386_o; + /* HUC6280.vhd:256:17 */ + always @(posedge CLK or posedge n249_o) + if (n249_o) + n388_q <= 10'b1111111111; + else + n388_q <= n291_o; + /* HUC6280.vhd:256:17 */ + always @(posedge CLK or posedge n249_o) + if (n249_o) + n389_q <= 7'b0000000; + else + n389_q <= n299_o; + /* HUC6280.vhd:256:17 */ + assign n390_o = n270_o ? n256_o : tmr_latch; + /* HUC6280.vhd:256:17 */ + always @(posedge CLK or posedge n249_o) + if (n249_o) + n391_q <= 7'b0000000; + else + n391_q <= n390_o; + /* HUC6280.vhd:256:17 */ + assign n392_o = n253_o ? n267_o : tmr_en; + /* HUC6280.vhd:256:17 */ + always @(posedge CLK or posedge n249_o) + if (n249_o) + n393_q <= 1'b0; + else + n393_q <= n392_o; + /* HUC6280.vhd:256:17 */ + assign n394_o = io_ce ? n294_o : tmr_reload; + /* HUC6280.vhd:256:17 */ + always @(posedge CLK or posedge n249_o) + if (n249_o) + n395_q <= 1'b0; + else + n395_q <= n394_o; + /* HUC6280.vhd:256:17 */ + always @(posedge CLK or posedge n249_o) + if (n249_o) + n396_q <= 1'b0; + else + n396_q <= n286_o; + /* HUC6280.vhd:222:17 */ + always @(posedge CLK or posedge n203_o) + if (n203_o) + n397_q <= 1'b0; + else + n397_q <= n228_o; + /* HUC6280.vhd:97:17 */ + always @(posedge CLK or posedge n17_o) + if (n17_o) + n398_q <= 1'b0; + else + n398_q <= n29_o; + /* HUC6280.vhd:167:17 */ + always @(posedge CLK or posedge n126_o) + if (n126_o) + n399_q <= 1'b1; + else + n399_q <= n144_o; + /* HUC6280.vhd:167:17 */ + always @(posedge CLK or posedge n126_o) + if (n126_o) + n400_q <= 1'b1; + else + n400_q <= n145_o; + /* HUC6280.vhd:206:17 */ + assign n401_o = n186_o ? cpu_do : n402_q; + /* HUC6280.vhd:206:17 */ + always @(posedge CLK or posedge n181_o) + if (n181_o) + n402_q <= 8'b00000000; + else + n402_q <= n401_o; +endmodule +/* verilator lint_on UNOPTFLAT*/ \ No newline at end of file diff --git a/snapshots/jotego_jtcores_pr1242/modules/HUC6280/hdl/HUC6280.vhd b/snapshots/jotego_jtcores_pr1242/modules/HUC6280/hdl/HUC6280.vhd new file mode 100644 index 0000000000000000000000000000000000000000..092240a3cd596bd28e1275fa56d0410c6e5ee945 --- /dev/null +++ b/snapshots/jotego_jtcores_pr1242/modules/HUC6280/hdl/HUC6280.vhd @@ -0,0 +1,358 @@ +library IEEE; +use IEEE.std_logic_1164.all; +use ieee.numeric_std.all; +library work; +use work.HUC6280_PKG.all; + +entity HUC6280 is + port( + CLK : in std_logic; + RST_N : in std_logic; + WAIT_N : in std_logic; + SX : out std_logic; + + A : out std_logic_vector(20 downto 0); + DI : in std_logic_vector(7 downto 0); + DO : out std_logic_vector(7 downto 0); + WR_N : out std_logic; + RD_N : out std_logic; + RDY : in std_logic; + NMI_N : in std_logic; + IRQ1_N : in std_logic; + IRQ2_N : in std_logic; + + CE : out std_logic; + CEK_N : out std_logic; + CE7_N : out std_logic; + CER_N : out std_logic; + PRE_RD : out std_logic; -- for MiSTer sdram/ddram read + PRE_WR : out std_logic; + + HSM : out std_logic; + + O : out std_logic_vector(7 downto 0); + K : in std_logic_vector(7 downto 0); + + VDCNUM : in std_logic; + + AUD_LDATA: out std_logic_vector(23 downto 0); + AUD_RDATA: out std_logic_vector(23 downto 0) + ); +end HUC6280; + +architecture rtl of HUC6280 is + + signal CPU_CE : std_logic; + signal CPU_CER : std_logic; + signal IO_CE : std_logic; + signal EN : std_logic; + + signal CPU_DI : std_logic_vector(7 downto 0); + signal CPU_DO : std_logic_vector(7 downto 0); + signal CPU_A : std_logic_vector(20 downto 0); + signal CPU_WE_N : std_logic; + signal CPU_CS : std_logic; + signal CPU_MCYCLE : std_logic; + signal CPU_IRQ1_N : std_logic; + signal CPU_IRQ2_N : std_logic; + signal CPU_IRQT_N : std_logic; + signal CPU_RDY : std_logic; + + signal CPU_CLK_CNT : unsigned(4 downto 0); + signal IO_CLK_CNT : unsigned(2 downto 0); + signal VDC_SEL_OLD : std_logic; + + --IO + signal IO_BUF : std_logic_vector(7 downto 0); + signal RAM_SEL : std_logic; + signal VDC_SEL : std_logic; + signal VCE_SEL : std_logic; + signal IOP_SEL : std_logic; + signal PSG_SEL : std_logic; + signal TMR_SEL : std_logic; + signal INT_SEL : std_logic; + signal IO_SEL : std_logic; + + signal INT_MASK : std_logic_vector(2 downto 0); + signal TMR_PRE_CNT : unsigned(9 downto 0); + signal TMR_VALUE : std_logic_vector(6 downto 0); + signal TMR_LATCH : std_logic_vector(6 downto 0); + signal TMR_EN : std_logic; + signal TMR_RELOAD : std_logic; + signal TMR_IRQ : std_logic; + signal TMR_IRQ_ACK : std_logic; + +begin + + + process(CLK, RST_N) + begin + if RST_N = '0' then + CPU_CLK_CNT <= (others=>'0'); + CPU_CE <= '0'; + CPU_CER <= '0'; + IO_CLK_CNT <= (others=>'0'); + IO_CE <= '0'; + SX <= '0'; + elsif rising_edge(CLK) then + CPU_CE <= '0'; + if (CPU_CLK_CNT = 2 and CPU_CS = '1') or (CPU_CLK_CNT = 11 and CPU_CS = '0') then + SX <= '1'; + else + SX <= '0'; + end if; + if (CPU_CLK_CNT = 5 and CPU_CS = '1') or (CPU_CLK_CNT = 23 and CPU_CS = '0') then + if WAIT_N = '1' then + CPU_CLK_CNT <= (others=>'0'); + CPU_CE <= '1'; + end if; + else + CPU_CLK_CNT <= CPU_CLK_CNT + 1; + end if; + + CPU_CER <= '0'; + if CPU_CLK_CNT = 1 then + CPU_CER <= '1'; + end if; + + IO_CE <= '0'; + IO_CLK_CNT <= IO_CLK_CNT + 1; + if IO_CLK_CNT = 5 then + IO_CLK_CNT <= (others=>'0'); + IO_CE <= '1'; + end if; + end if; + end process; + + CE <= CPU_CE and CPU_RDY; + + EN <= CPU_CE and CPU_RDY; + + + CORE : entity work.HUC6280_CPU + port map ( + CLK => CLK, + RST_N => RST_N, + CE => CPU_CE, + + A_OUT => CPU_A, + DI => CPU_DI, + DO => CPU_DO, + WE_N => CPU_WE_N, + RDY => CPU_RDY, + IRQ1_N => CPU_IRQ1_N, + IRQ2_N => CPU_IRQ2_N, + IRQT_N => CPU_IRQT_N, + NMI_N => NMI_N, + MCYCLE => CPU_MCYCLE, + CS => CPU_CS, + VDCNUM => VDCNUM + ); + + CPU_IRQ1_N <= IRQ1_N or INT_MASK(1); + CPU_IRQ2_N <= IRQ2_N or INT_MASK(0); + CPU_IRQT_N <= not TMR_IRQ or INT_MASK(2); + + RAM_SEL <= '1' when CPU_A(20 downto 15) = "111110" else '0'; -- RAM : Page $F8 - $FB + VDC_SEL <= '1' when CPU_A(20 downto 13) = x"FF" and CPU_A(12 downto 10) = "000" else '0'; -- VDC : $0000 - $03FF + VCE_SEL <= '1' when CPU_A(20 downto 13) = x"FF" and CPU_A(12 downto 10) = "001" else '0'; -- VCE : $0400 - $07FF + + process(CLK, RST_N) + begin + if RST_N = '0' then + WR_N <= '1'; + RD_N <= '1'; + CPU_RDY <= '1'; + VDC_SEL_OLD <= '0'; + elsif rising_edge(CLK) then + if CPU_CER = '1' then + if CPU_MCYCLE = '1' then + WR_N <= CPU_WE_N; + RD_N <= not CPU_WE_N; + end if; + + VDC_SEL_OLD <= VDC_SEL or VCE_SEL; + if (VDC_SEL = '1' or VCE_SEL = '1') and VDC_SEL_OLD = '0' then + CPU_RDY <= '0'; + end if; + elsif CPU_CE = '1' then + if CPU_RDY = '1' then + WR_N <= '1'; + RD_N <= '1'; + end if; + CPU_RDY <= RDY; + end if; + end if; + end process; + + PRE_RD <= CPU_WE_N and CPU_MCYCLE and RST_N; + PRE_WR <= not CPU_WE_N and CPU_MCYCLE and RST_N; + + A <= CPU_A; + DO <= CPU_DO; + CER_N <= not RAM_SEL; + CE7_N <= not VDC_SEL; + CEK_N <= not VCE_SEL; + HSM <= CPU_CS; + + + + --KO port + IOP_SEL <= '1' when CPU_A(20 downto 13) = x"FF" and CPU_A(12 downto 10) = "100" else '0'; -- IOP : $1000 - $13FF + process(CLK, RST_N) + begin + if RST_N = '0' then + O <= (others=>'0'); + elsif rising_edge(CLK) then + if EN = '1' then + if IOP_SEL = '1' and CPU_WE_N = '0' then + O <= CPU_DO; + end if; + end if; + end if; + end process; + + --Interrupts register + INT_SEL <= '1' when CPU_A(20 downto 13) = x"FF" and CPU_A(12 downto 10) = "101" else '0'; -- INT : $1400 - $17FF + process(CLK, RST_N) + begin + if RST_N = '0' then + INT_MASK <= (others=>'0'); + TMR_IRQ_ACK <= '0'; + elsif rising_edge(CLK) then + TMR_IRQ_ACK <= '0'; + if INT_SEL = '1' and CPU_CER = '1' then + if CPU_WE_N = '0' then + case CPU_A(1 downto 0) is + when "10" => + INT_MASK <= CPU_DO(2 downto 0); + when "11" => + TMR_IRQ_ACK <= '1'; + when others => null; + end case; + else + case CPU_A(1 downto 0) is + when "10" => + TMR_IRQ_ACK <= '1'; + when others => null; + end case; + end if; + end if; + end if; + end process; + + + -- Timer + TMR_SEL <= '1' when CPU_A(20 downto 13) = x"FF" and CPU_A(12 downto 10) = "011" else '0'; -- TMR : $0C00 - $0FFF + process( CLK, RST_N ) + begin + if RST_N = '0' then + TMR_VALUE <= (others => '0'); + TMR_PRE_CNT <= (others => '1'); + TMR_LATCH <= (others => '0'); + TMR_EN <= '0'; + TMR_RELOAD <= '0'; + TMR_IRQ <= '0'; + elsif rising_edge(CLK) then + if TMR_SEL = '1' and CPU_WE_N = '0' and CPU_CER = '1' then + if CPU_A(0) = '0' then + -- Timer latch + TMR_LATCH <= CPU_DO(6 downto 0); + else + -- Timer enable + TMR_EN <= CPU_DO(0); + if TMR_EN = '0' and CPU_DO(0) = '1' then + TMR_VALUE <= TMR_LATCH; + TMR_PRE_CNT <= (others => '1'); + end if; + end if; + end if; + + if TMR_IRQ_ACK = '1' then + TMR_IRQ <= '0'; + end if; + + if IO_CE = '1' then + TMR_RELOAD <= '0'; + if TMR_EN = '1' then + TMR_PRE_CNT <= TMR_PRE_CNT - 1; + if TMR_PRE_CNT = 0 then + TMR_VALUE <= std_logic_vector( unsigned(TMR_VALUE) - 1 ); + if TMR_VALUE = "0000000" then + TMR_RELOAD <= '1'; + TMR_IRQ <= '1'; + end if; + end if; + end if; + + if TMR_RELOAD = '1' then + TMR_VALUE <= TMR_LATCH; + end if; + end if; + end if; + end process; + + -- PSG + PSG_SEL <= '1' when CPU_A(20 downto 13) = x"FF" and CPU_A(12 downto 10) = "010" else '0'; -- PSG : $0800 - $0BFF + -- PSG unused in Robocop, I remove it so I don't have to deal + -- with the dpram module, which is mapped to an Altera primitive +-- PSG : entity work.psg port map ( +-- CLK => CLK, +-- CLKEN => IO_CE, -- 7.16 Mhz clock +-- RESET_N => RST_N, +-- +-- DI => CPU_DO, +-- A => CPU_A(3 downto 0), +-- WE => not CPU_WE_N and EN and PSG_SEL, +-- +-- DAC_LATCH=> '1', +-- LDATA => AUD_LDATA, +-- RDATA => AUD_RDATA +-- ); + + IO_SEL <= IOP_SEL or INT_SEL or TMR_SEL or PSG_SEL; + process(CLK, RST_N) + begin + if RST_N = '0' then + IO_BUF <= (others=>'1'); + elsif rising_edge(CLK) then + if EN = '1' then + if IO_SEL = '1' then + if CPU_WE_N = '0' then + IO_BUF <= CPU_DO; + else + IO_BUF <= CPU_DI; + end if; + end if; + end if; + end if; + end process; + + process(CLK) + begin + if rising_edge(CLK) then + if IO_SEL = '0' then + CPU_DI <= DI; + elsif PSG_SEL = '1' then + CPU_DI <= x"00"; + elsif IOP_SEL = '1' then + CPU_DI <= K; + elsif INT_SEL = '1' then + case CPU_A(1 downto 0) is + when "10" => + CPU_DI <= IO_BUF(7 downto 3) & INT_MASK; + when "11" => + CPU_DI <= IO_BUF(7 downto 3) & TMR_IRQ & not IRQ1_N & not IRQ2_N; + when others => + CPU_DI <= IO_BUF; + end case; + elsif TMR_SEL = '1' then + CPU_DI <= IO_BUF(7) & TMR_VALUE; + else + CPU_DI <= IO_BUF; + end if; + end if; + end process; + +end rtl; + \ No newline at end of file diff --git a/snapshots/jotego_jtcores_pr1242/modules/HUC6280/hdl/HUC6280_AG.vhd b/snapshots/jotego_jtcores_pr1242/modules/HUC6280/hdl/HUC6280_AG.vhd new file mode 100644 index 0000000000000000000000000000000000000000..58a7042f35c6b886f74860c7aeb5c5f229852cba --- /dev/null +++ b/snapshots/jotego_jtcores_pr1242/modules/HUC6280/hdl/HUC6280_AG.vhd @@ -0,0 +1,125 @@ +library IEEE; +use IEEE.std_logic_1164.all; +use ieee.numeric_std.all; +library work; + +entity HUC6280_AG is + port( + CLK : in std_logic; + RST_N : in std_logic; + CE : in std_logic; + PC_CTRL : in std_logic_vector(2 downto 0); + ADDR_CTRL : in std_logic_vector(5 downto 0); + GOT_INT : in std_logic; + DI : in std_logic_vector(7 downto 0); + X : in std_logic_vector(7 downto 0); + Y : in std_logic_vector(7 downto 0); + DR : in std_logic_vector(7 downto 0); + + PC : out std_logic_vector(15 downto 0); + AA : out std_logic_vector(15 downto 0) + ); +end HUC6280_AG; + +architecture rtl of HUC6280_AG is + + signal AAL, AAH : std_logic_vector(7 downto 0); + signal SavedCarry : std_logic; + + signal NewAAL : std_logic_vector(8 downto 0); + signal NewAAH : std_logic_vector(7 downto 0); + + signal PCr: std_logic_vector(15 downto 0); + signal NextPC, NewPCWithOffset: std_logic_vector(15 downto 0); + +begin + + NewPCWithOffset <= std_logic_vector(unsigned(PCr) + unsigned((7 downto 0 => AAL(7)) & AAL)); + + process(CLK, RST_N, PC_CTRL, PCr, DI, DR, GOT_INT, NewPCWithOffset, AAH, AAL ) + begin + case PC_CTRL is + when "000" => + NextPC <= PCr; + when "001" => + if GOT_INT = '0' then + NextPC <= std_logic_vector(unsigned(PCr) + 1); + else + NextPC <= PCr; + end if; + when "010"=> + NextPC <= PCr(15 downto 8) & DI; + when "011" => + NextPC <= DI & PCr(7 downto 0); + when "100" => + NextPC <= NewPCWithOffset; + when "110" => + NextPC <= AAH & AAL; + when others => + NextPC <= PCr; + end case; + + if RST_N = '0' then + PCr <= (others=>'0'); + elsif rising_edge(CLK) then + if CE = '1' then + PCr <= NextPC; + end if; + end if; + end process; + + process(ADDR_CTRL, AAL, AAH, X, Y, DI, DR, SavedCarry) + begin + case ADDR_CTRL(5 downto 3) is + when "000"=> + NewAAL <= "0" & AAL; + when "001"=> + NewAAL <= "0" & DI; + when "010" => + NewAAL <= std_logic_vector(unsigned("0" & AAL) + 1); + when "011" => + NewAAL <= std_logic_vector(unsigned("0" & AAL) + unsigned("0" & X)); + when "100" => + NewAAL <= std_logic_vector(unsigned("0" & AAL) + unsigned("0" & Y)); + when "101" => + NewAAL <= "0" & DR; + when "110" => + NewAAL <= std_logic_vector(unsigned("0" & DR) + unsigned("0" & Y)); + when others => + NewAAL <= "0" & X; + end case; + + case ADDR_CTRL(2 downto 0) is + when "000"=> + NewAAH <= AAH; + when "001"=> + NewAAH <= DI; + when "010" => + NewAAH <= std_logic_vector(unsigned(AAH) + 1); + when "011" => + NewAAH <= std_logic_vector(unsigned(AAH) + ("0000000"&SavedCarry)); + when others => + NewAAH <= AAH; + end case; + end process; + + + process(CLK, RST_N) + begin + if RST_N = '0' then + AAL <= (others=>'0'); + AAH <= (others=>'0'); + SavedCarry <= '0'; + elsif rising_edge(CLK) then + if CE = '1' then + AAL <= NewAAL(7 downto 0); + SavedCarry <= NewAAL(8); + AAH <= NewAAH(7 downto 0); + end if; + end if; + end process; + + AA <= AAH & AAL; + PC <= PCr; + +end rtl; \ No newline at end of file diff --git a/snapshots/jotego_jtcores_pr1242/modules/HUC6280/hdl/HUC6280_ALU.vhd b/snapshots/jotego_jtcores_pr1242/modules/HUC6280/hdl/HUC6280_ALU.vhd new file mode 100644 index 0000000000000000000000000000000000000000..957ee151f9a2b1187440e09a2da3425d9dd5114a --- /dev/null +++ b/snapshots/jotego_jtcores_pr1242/modules/HUC6280/hdl/HUC6280_ALU.vhd @@ -0,0 +1,166 @@ +library IEEE; +use IEEE.std_logic_1164.all; +use ieee.numeric_std.all; +library work; +use work.HUC6280_PKG.all; + +entity ALU is + port( + CLK : in std_logic; + EN : in std_logic; + L : in std_logic_vector(7 downto 0); + R : in std_logic_vector(7 downto 0); + CTRL : in ALUCtrl_r; + BCD : in std_logic; + CI : in std_logic; + VI : in std_logic; + NI : in std_logic; + CO : out std_logic; + VO : out std_logic; + NO : out std_logic; + ZO : out std_logic; + RES : out std_logic_vector(7 downto 0) + ); +end ALU; + +architecture rtl of ALU is + + signal IntL : std_logic_vector(7 downto 0); + signal IntR : std_logic_vector(7 downto 0); + signal CR : std_logic; + signal ADDIn : std_logic; + signal BCDIn : std_logic; + signal CIIn : std_logic; + signal SavedC : std_logic; + + signal AddS : std_logic_vector(7 downto 0); + signal AddCO : std_logic; + signal AddVO : std_logic; + signal Result : std_logic_vector(7 downto 0); + +begin + + process(CTRL, CI, L, R, BCD, SavedC) + begin + CR <= CI; + BCDIn <= '0'; + case CTRL.fstOp is + when "000" => + CR <= L(7); + IntL <= L(6 downto 0) & "0"; + IntR <= x"00"; + when "001"=> + CR <= L(7); + IntL <= L(6 downto 0) & CI; + IntR <= x"00"; + when "010" => + CR <= L(0); + IntL <= "0" & L(7 downto 1); + IntR <= x"00"; + when "011" => + CR <= L(0); + IntL <= CI & L(7 downto 1); + IntR <= x"00"; + when "100" => + IntL <= L; + IntR <= R; + BCDIn <= BCD and CTRL.secOp(1) and CTRL.secOp(0); + when "101" => + IntL <= L; + IntR <= R; + when "110" => -- INC/DEC LSB + IntL <= L; + IntR <= x"01"; + CR <= CTRL.secOp(2); + when "111" => -- INC/DEC MSB + IntL <= L; + IntR <= x"00"; + CR <= SavedC; + when others => null; + end case; + end process; + + CIIn <= CR or not CTRL.secOp(0); + ADDIn <= not CTRL.secOp(2); + + AddSub: entity work.AddSubBCD + port map ( + A => IntL, + B => IntR, + CI => CIIn, + ADD => ADDIn, + BCD => BCDIn, + S => AddS, + CO => AddCO, + VO => AddVO + ); + + process(CLK) + begin + if rising_edge(CLK) then + if EN = '1' then + SavedC <= AddCO; + end if; + end if; + end process; + + process(CTRL, CR, IntL, IntR, AddCO, AddS) + begin + case CTRL.secOp is + when "000" => + CO <= CR; + Result <= IntL or IntR; + when "001"=> + CO <= CR; + Result <= IntL and IntR; + when "010" => + CO <= CR; + Result <= IntL xor IntR; + when "011" | "110" | "111" => + CO <= AddCO; + Result <= AddS; + when "100" => + CO <= CR; + Result <= IntL; + when "101" => --TRB,TSB + CO <= CR; + if CTRL.fc = '0' then + Result <= IntR and (not IntL); + else + Result <= IntR or IntL; + end if; + when others => null; + end case; + end process; + + process(CTRL, VI, NI, IntR, Result, AddVO, BCDIn) + begin + VO <= VI; + NO <= Result(7); + case CTRL.secOp is + when "001" => --AND + if CTRL.fc = '1' then --BIT + VO <= IntR(6); + NO <= IntR(7); + end if; + when "011" => -- ADC + if BCDIn = '0' then + VO <= AddVO; + end if; + when "101" => --TRB,TSB + VO <= IntR(6); + NO <= IntR(7); + when "111" => -- SBC + if BCDIn = '0' then + VO <= AddVO; + end if; + when others => null; + end case; + end process; + + + ZO <= '1' when Result = x"00" else '0'; + + RES <= Result; + +end rtl; \ No newline at end of file diff --git a/snapshots/jotego_jtcores_pr1242/modules/HUC6280/hdl/HUC6280_CPU.vhd b/snapshots/jotego_jtcores_pr1242/modules/HUC6280/hdl/HUC6280_CPU.vhd new file mode 100644 index 0000000000000000000000000000000000000000..c25a79948ed47f4e8e126894bd403f7844246158 --- /dev/null +++ b/snapshots/jotego_jtcores_pr1242/modules/HUC6280/hdl/HUC6280_CPU.vhd @@ -0,0 +1,571 @@ +library IEEE; +use IEEE.std_logic_1164.all; +use ieee.numeric_std.all; +library work; +use work.HUC6280_PKG.all; + +entity HUC6280_CPU is + port( + CLK : in std_logic; + RST_N : in std_logic; + CE : in std_logic; + + A_OUT : out std_logic_vector(20 downto 0); + DI : in std_logic_vector(7 downto 0); + DO : out std_logic_vector(7 downto 0); + WE_N : out std_logic; + RDY : in std_logic; + NMI_N : in std_logic; + IRQ1_N : in std_logic; + IRQ2_N : in std_logic; + IRQT_N : in std_logic; + + VDCNUM : in std_logic; + + MCYCLE : out std_logic; + CS : out std_logic + ); +end HUC6280_CPU; + +architecture rtl of HUC6280_CPU is + + signal EN : std_logic; + + --Registers + signal A : std_logic_vector(7 downto 0); + signal X : std_logic_vector(7 downto 0); + signal Y : std_logic_vector(7 downto 0); + signal SP : std_logic_vector(7 downto 0); + signal P : std_logic_vector(7 downto 0); + signal PC : std_logic_vector(15 downto 0); + signal AA : std_logic_vector(15 downto 0); + signal T : std_logic_vector(7 downto 0); + signal DR : std_logic_vector(7 downto 0); + signal SH : std_logic_vector(7 downto 0); + signal DH : std_logic_vector(7 downto 0); + signal LH : std_logic_vector(7 downto 0); + signal MPR : MPR_t; + + --Instruction decoder + signal IR : std_logic_vector(7 downto 0); + signal STATE : unsigned(4 downto 0); + signal MC : MCode_r; + signal NEXT_IR : std_logic_vector(7 downto 0); + signal NEXT_STATE : unsigned(4 downto 0); + signal LAST_CYCLE : std_logic; + signal BRANCH_TAKEN : std_logic; + signal MEM_INST : std_logic; + signal TALT : std_logic; + + --Buses + signal ADDR_BUS : std_logic_vector(15 downto 0); + signal MPR_OUT : std_logic_vector(7 downto 0); + signal MPR_LAST : std_logic_vector(7 downto 0); + + --ALU + signal ALU_CTRL : ALUCtrl_r; + signal ALU_L : std_logic_vector(7 downto 0); + signal ALU_OUT : std_logic_vector(7 downto 0); + signal CO : std_logic; + signal VO : std_logic; + signal NO : std_logic; + signal ZO : std_logic; + signal MASK : std_logic_vector(7 downto 0); + + --Interrupts + signal GOT_INT : std_logic; + signal RES_INT : std_logic; + signal NMI_INT : std_logic; + signal IRQ1_INT : std_logic; + signal IRQ2_INT : std_logic; + signal IRQT_INT : std_logic; + signal BRK_INT : std_logic; + signal OLD_NMI_N : std_logic; + signal NMI_SYNC : std_logic; + signal NMI_ACTIVE : std_logic; + +begin + + EN <= RDY and CE; + + NEXT_IR <= IR when (STATE /= "00000") else + x"00" when GOT_INT = '1' else + DI; + + + process(IR, STATE, P, DR) + begin + BRANCH_TAKEN <= '0'; + if IR(4 downto 0) = "10000" and STATE = "00001" then + case IR(7 downto 5) is + when "000" => BRANCH_TAKEN <= not P(FLAG_N); -- BPL + when "001" => BRANCH_TAKEN <= P(FLAG_N); -- BMI + when "010" => BRANCH_TAKEN <= not P(FLAG_V); -- BVC + when "011" => BRANCH_TAKEN <= P(FLAG_V); -- BVS + when "100" => BRANCH_TAKEN <= not P(FLAG_C); -- BCC + when "101" => BRANCH_TAKEN <= P(FLAG_C); -- BCS + when "110" => BRANCH_TAKEN <= not P(FLAG_Z); -- BNE + when "111" => BRANCH_TAKEN <= P(FLAG_Z); -- BEQ + when others => BRANCH_TAKEN <= '0'; + end case; + elsif IR(3 downto 0) = "1111" and STATE = "00101" then + if DR(to_integer(unsigned(IR(6 downto 4)))) = IR(7) then + BRANCH_TAKEN <= '1'; + end if; + end if; + end process; + + MEM_INST <= '1' when DI = x"69" or DI = x"65" or DI = x"75" or DI = x"72" or DI = x"61" or DI = x"71" or DI = x"6D" or DI = x"7D" or DI = x"79" or + DI = x"29" or DI = x"25" or DI = x"35" or DI = x"32" or DI = x"21" or DI = x"31" or DI = x"2D" or DI = x"3D" or DI = x"39" or + DI = x"09" or DI = x"05" or DI = x"15" or DI = x"12" or DI = x"01" or DI = x"11" or DI = x"0D" or DI = x"1D" or DI = x"19" or + DI = x"49" or DI = x"45" or DI = x"55" or DI = x"52" or DI = x"41" or DI = x"51" or DI = x"4D" or DI = x"5D" or DI = x"59" + else '0'; + + + process(MC, IR, STATE, BRANCH_TAKEN, P, MEM_INST, GOT_INT, A, LH) + begin + case MC.STATE_CTRL is + when "00" => + if MEM_INST = '1' and P(FLAG_T) = '1' and STATE = "00000" and GOT_INT = '0' then + NEXT_STATE <= "01000"; + else + NEXT_STATE <= STATE + 1; + end if; + when "01" => + if P(FLAG_D) = '0' then + NEXT_STATE <= "00000"; + else + NEXT_STATE <= STATE + 1; + end if; + when "10" => + if BRANCH_TAKEN = '1' then + NEXT_STATE <= STATE + 1; + else + NEXT_STATE <= "00000"; + end if; + when "11" => + if A = x"00" and LH = x"00" then + NEXT_STATE <= STATE + 1; + else + NEXT_STATE <= "01110"; + end if; + when others => + NEXT_STATE <= STATE; + end case; + end process; + + + process(CLK, RST_N) + begin + if RST_N = '0' then + IR <= (others=>'0'); + STATE <= (others=>'0'); + elsif rising_edge(CLK) then + if EN = '1' then + IR <= NEXT_IR; + STATE <= NEXT_STATE; + end if; + end if; + end process; + + LAST_CYCLE <= '1' when NEXT_STATE = "00000" else '0'; + + process(CLK, RST_N) + begin + if RST_N = '0' then + TALT <= '0'; + elsif rising_edge(CLK) then + if EN = '1' then + if STATE = "01101" then + TALT <= '0'; + elsif STATE = "10011" then + TALT <= not TALT; + end if; + end if; + end if; + end process; + + MCODE: entity work.HUC6280_MC + port map ( + CLK => CLK, + RST_N => RST_N, + EN => EN, + IR => NEXT_IR, + STATE => NEXT_STATE, + M => MC + ); + + process(MC, IR, STATE, TALT) + begin + ALU_CTRL <= MC.ALU_CTRL; + if IR = x"E3" and (STATE = 16 or STATE = 17) then + ALU_CTRL.secOp(2) <= TALT; + elsif IR = x"F3" and (STATE = 14 or STATE = 15) then + ALU_CTRL.secOp(2) <= TALT; + end if; + end process; + + process(IR) + begin + case IR(6 downto 4) is + when "000" => MASK <= x"01"; + when "001" => MASK <= x"02"; + when "010" => MASK <= x"04"; + when "011" => MASK <= x"08"; + when "100" => MASK <= x"10"; + when "101" => MASK <= x"20"; + when "110" => MASK <= x"40"; + when others => MASK <= x"80"; + end case; + end process; + + with MC.ALUBUS_CTRL select + ALU_L <= DI when "0000", + A when "0001", + X when "0010", + Y when "0011", + SP when "0100", + T when "0101", + SH when "1000", + DH when "1001", + LH when "1010", + MPR_OUT when "1011", + MASK when "1100", + x"00" when others; + + ALU: entity work.ALU + port map ( + CLK => CLK, + EN => EN, + L => ALU_L, + R => DI, + CTRL => ALU_CTRL, + BCD => P(FLAG_D), + CI => P(FLAG_C), + VI => P(FLAG_V), + NI => P(FLAG_N), + CO => CO, + VO => VO, + NO => NO, + ZO => ZO, + RES => ALU_OUT + ); + + + process(CLK, RST_N) + begin + if RST_N = '0' then + A <= (others=>'0'); + X <= (others=>'0'); + Y <= (others=>'0'); + elsif rising_edge(CLK) then + if EN = '1' then + if MC.AXY_CTRL(0) = '1' then + A <= ALU_OUT; + end if; + if MC.AXY_CTRL(1) = '1' then + X <= ALU_OUT; + end if; + if MC.AXY_CTRL(2) = '1' then + Y <= ALU_OUT; + end if; + end if; + end if; + end process; + + process(CLK, RST_N) + begin + if RST_N = '0' then + T <= (others=>'0'); + elsif rising_edge(CLK) then + if EN = '1' then + case MC.LOAD_T is + when "001" => T <= ALU_OUT; + when "010" => T <= X; + when "011" => T <= Y; + when "100" => T <= DI; + when others => null; + end case; + end if; + end if; + end process; + + process(CLK, RST_N) + begin + if RST_N = '0' then + SP <= (others=>'0'); + elsif rising_edge(CLK) then + if EN = '1' then + case MC.LOAD_SP is + when "001" => + SP <= ALU_OUT; + when "010"=> + SP <= std_logic_vector(unsigned(SP) + 1); + when "011" => + SP <= std_logic_vector(unsigned(SP) - 1); + when others => null; + end case; + end if; + end if; + end process; + + --Status register + process(CLK, RST_N) + begin + if RST_N = '0' then + P <= "00000100"; + elsif rising_edge(CLK) then + if EN = '1' then + case MC.LOAD_P is + when "001" => -- ALU + P(FLAG_Z) <= ZO; + P(FLAG_N) <= NO; + when "010" => -- BRK/interrupts + P(FLAG_I) <= '1'; + P(FLAG_D) <= '0'; + when "011" => -- RTI/PLP + P <= DI; + when "100" => + case IR(7 downto 6) is + when "00" => P(FLAG_C) <= IR(5); -- CLC/SEC 18/38 + when "01" => P(FLAG_I) <= IR(5); -- CLI/SEI 58/78 + when "10" => P(FLAG_V) <= '0'; -- CLV B8 + when "11" => P(FLAG_D) <= IR(5); -- CLD/SED D8/F8 + when others => null; + end case; + when "101" => -- ALU + P(FLAG_C) <= CO; + P(FLAG_Z) <= ZO; + P(FLAG_V) <= VO; + P(FLAG_N) <= NO; + when "110" => -- SET + P(FLAG_T) <= '1'; + when "111" => -- clear T + P(FLAG_T) <= '0'; + when others => null; + end case; + + if NEXT_IR /= x"00" and STATE = "00000" then + P(FLAG_T) <= '0'; + end if; + end if; + end if; + end process; + + process(CLK, RST_N) + begin + if RST_N = '0' then + SH <= (others=>'0'); + DH <= (others=>'0'); + LH <= (others=>'0'); + elsif rising_edge(CLK) then + if EN = '1' then + case MC.LOAD_SDLH is + when "01" => SH <= ALU_OUT; + when "10" => DH <= ALU_OUT; + when "11" => LH <= ALU_OUT; + when others => null; + end case; + end if; + end if; + end process; + + process(CLK, RST_N) + begin + if RST_N = '0' then + MPR(0) <= (others=>'0'); + MPR(1) <= (others=>'0'); + MPR(2) <= (others=>'0'); + MPR(3) <= (others=>'0'); + MPR(4) <= (others=>'0'); + MPR(5) <= (others=>'0'); + MPR(6) <= (others=>'0'); + MPR(7) <= (others=>'0'); + elsif rising_edge(CLK) then + if EN = '1' then + if IR = x"53" and LAST_CYCLE = '1' then --TAMi + for i in 0 to 7 loop + if T(i) = '1' then + MPR(i) <= A; + end if; + end loop; + MPR_LAST <= A; + end if; + end if; + end if; + end process; + + MPR_OUT <= MPR(0) when T(0) = '1' else + MPR(1) when T(1) = '1' else + MPR(2) when T(2) = '1' else + MPR(3) when T(3) = '1' else + MPR(4) when T(4) = '1' else + MPR(5) when T(5) = '1' else + MPR(6) when T(6) = '1' else + MPR(7) when T(7) = '1' else + MPR_LAST; + + --Data bus + with MC.OUT_BUS select + DO <= A when "0001", + X when "0010", + Y when "0011", + T when "0100", + P(7 downto 5) & (not GOT_INT) & P(3 downto 0) when "0101", + PC(15 downto 8) when "0110", + PC(7 downto 0) when "0111", + x"00" when others; + + process(MC, RES_INT) + begin + WE_N <= '1'; + if MC.OUT_BUS /= "0000" and RES_INT = '0' then + WE_N <= '0'; + end if; + end process; + + process(CLK, RST_N) + begin + if RST_N = '0' then + DR <= (others=>'0'); + elsif rising_edge(CLK) then + if EN = '1' then + DR <= DI; + end if; + end if; + end process; + + AG: entity work.HUC6280_AG + port map ( + CLK => CLK, + RST_N => RST_N, + CE => EN, + PC_CTRL => MC.LOAD_PC, + ADDR_CTRL => MC.ADDR_CTRL, + GOT_INT => GOT_INT, + DI => DI, + X => X, + Y => Y, + DR => DR, + PC => PC, + AA => AA + ); + + --Interrupts + process(CLK, RST_N) + begin + if RST_N = '0' then + OLD_NMI_N <= '1'; + NMI_SYNC <= '0'; + elsif rising_edge(CLK) then + if RES_INT = '0' then + OLD_NMI_N <= NMI_N; + if NMI_N = '0' and OLD_NMI_N = '1' and NMI_SYNC = '0' then + NMI_SYNC <= '1'; + elsif NMI_ACTIVE = '1' and LAST_CYCLE = '1' and EN = '1' then + NMI_SYNC <= '0'; + end if; + end if; + end if; + end process; + + process(CLK, RST_N) + begin + if RST_N = '0' then + RES_INT <= '1'; + NMI_INT <= '0'; + IRQ1_INT <= '0'; + IRQ2_INT <= '0'; + IRQT_INT <= '0'; + GOT_INT <= '1'; + NMI_ACTIVE <= '0'; + elsif rising_edge(CLK) then + if RDY = '1' and CE = '1' then + NMI_ACTIVE <= NMI_SYNC; + + if LAST_CYCLE = '1' and EN = '1' then + if GOT_INT = '0' then + GOT_INT <= ((not IRQ1_N or not IRQ2_N or not IRQT_N) and not P(FLAG_I)) or NMI_ACTIVE; + if NMI_ACTIVE = '1' then + NMI_ACTIVE <= '0'; + end if; + else + GOT_INT <= '0'; + end if; + + RES_INT <= '0'; + NMI_INT <= NMI_ACTIVE; + IRQ1_INT <= not IRQ1_N and not P(FLAG_I); + IRQ2_INT <= not IRQ2_N and not P(FLAG_I); + IRQT_INT <= not IRQT_N and not P(FLAG_I); + end if; + end if; + end if; + end process; + + BRK_INT <= '1' when IR = x"00" and GOT_INT = '0' else '0'; + + --Address bus + process(MC, PC, AA, SP, SH, DH, X, Y, STATE, IR, RES_INT, NMI_INT, BRK_INT, IRQ1_INT, IRQ2_INT, IRQT_INT, VDCNUM) + begin + case MC.ADDR_BUS is + when "000" => + ADDR_BUS <= PC; + when "001"=> + ADDR_BUS <= AA; + when "010" => + ADDR_BUS <= x"21" & SP; + when "011" => + ADDR_BUS <= x"20" & AA(7 downto 0); + when "100" => + ADDR_BUS(15 downto 4) <= x"FFF"; + if RES_INT = '1' then + ADDR_BUS(3 downto 0) <= "111" & STATE(0); --FFFE/F + elsif NMI_INT = '1' then + ADDR_BUS(3 downto 0) <= "110" & STATE(0); --FFFC/D + elsif BRK_INT = '1' then + ADDR_BUS(3 downto 0) <= "011" & STATE(0); --FFF6/7 + elsif IRQT_INT = '1' then + ADDR_BUS(3 downto 0) <= "101" & STATE(0); --FFFA/B + elsif IRQ1_INT = '1' then + ADDR_BUS(3 downto 0) <= "100" & STATE(0); --FFF8/9 + elsif IRQ2_INT = '1' then + ADDR_BUS(3 downto 0) <= "011" & STATE(0); --FFF6/7 + else + ADDR_BUS(3 downto 0) <= "111" & STATE(0); -- + end if; + when "101"=> + ADDR_BUS(15 downto 2) <= x"00" & "000" & VDCNUM & "00"; + case IR(5 downto 4) is + when "00" => ADDR_BUS(1 downto 0) <= "00"; + when "01" => ADDR_BUS(1 downto 0) <= "10"; + when others => ADDR_BUS(1 downto 0) <= "11"; + end case; + when "110"=> + ADDR_BUS <= SH & X; + when "111"=> + ADDR_BUS <= DH & Y; + when others => null; + end case; + end process; + + A_OUT(12 downto 0) <= ADDR_BUS(12 downto 0); + A_OUT(20 downto 13) <= x"FF" when MC.ADDR_BUS = "101" else MPR(to_integer(unsigned(ADDR_BUS(15 downto 13)))); + + process(CLK, RST_N) + begin + if RST_N = '0' then + CS <= '0'; + elsif rising_edge(CLK) then + if EN = '1' then + if IR(6 downto 0) = "1010100" and STATE = "00001" then + CS <= IR(7); + end if; + end if; + end if; + end process; + + MCYCLE <= MC.MEM_CYCLE; + +end rtl; + \ No newline at end of file diff --git a/snapshots/jotego_jtcores_pr1242/modules/HUC6280/hdl/HUC6280_MC.vhd b/snapshots/jotego_jtcores_pr1242/modules/HUC6280/hdl/HUC6280_MC.vhd new file mode 100644 index 0000000000000000000000000000000000000000..cc1de3c2ae7856e001c2475d7753094fb79f1d88 --- /dev/null +++ b/snapshots/jotego_jtcores_pr1242/modules/HUC6280/hdl/HUC6280_MC.vhd @@ -0,0 +1,7009 @@ +library IEEE; +use IEEE.std_logic_1164.all; +use ieee.numeric_std.all; +library work; +use work.HUC6280_PKG.all; + +entity HUC6280_MC is + port( + CLK : in std_logic; + RST_N : in std_logic; + EN : in std_logic; + IR : in std_logic_vector(7 downto 0); + STATE : in unsigned(4 downto 0); + M : out MCode_r + ); +end HUC6280_MC; + +architecture rtl of HUC6280_MC is + + type MicroInst_t is array(0 to 256*8-1) of MicroInst_r; + constant M_TAB1: MicroInst_t := ( + --STATE ADBUS SDLH P T ADDRCTRL PC SP AXYBUS ALUBUS ALUCTRL OUT MCYC + -- 00 BRK + ("00","000","00","000","000","000000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->IR', 'PC++'] + ("00","000","00","000","000","000000","001","000","000","0000","00000","0000",'1'),-- ['PC++'] + ("00","000","00","000","000","000000","000","000","000","0000","00000","0000",'0'),-- [] + ("00","010","00","000","000","000000","000","011","000","0000","00000","0110",'1'),-- ['PCH->[21:SP]', 'SP--'] + ("00","010","00","000","000","000000","000","011","000","0000","00000","0111",'1'),-- ['PCL->[21:SP]', 'SP--'] + ("00","010","00","000","000","000000","000","011","000","0000","00000","0101",'1'),-- ['P->[21:SP]', 'SP--', '0->T] + ("00","100","00","010","000","000000","010","000","000","0000","00000","0000",'1'),-- ['[VECT+0]->PCL', '1->I', '0->D', '1->B'] + ("10","100","00","000","000","000000","011","000","000","0000","00000","0000",'1'),-- ['[VECT+1]->PCH'] + -- 01 ORA (ZP,X) + ("00","000","00","000","000","000000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->IR', 'PC++'] + ("00","000","00","000","000","001000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->AAL', 'PC++'] + ("00","000","00","000","000","011000","000","000","000","0000","00000","0000",'0'),-- ['AAL+X->AAL'] + ("00","011","00","000","000","010000","000","000","000","0000","00000","0000",'1'),-- ['[20:AAL]->DR', 'AAL+1->AAL'] + ("00","011","00","000","000","101001","000","000","000","0000","00000","0000",'1'),-- ['[20:AAL]->AAH', 'DR->AAL'] + ("00","000","00","000","000","000000","000","000","000","0000","00000","0000",'0'),-- [] + ("10","001","00","001","000","000000","000","000","001","0001","00010","0000",'1'),-- ['ALU(A,[AA])->A', 'Flags'] + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- 02 SXY + ("00","000","00","000","000","000000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->IR', 'PC++'] + ("00","000","00","000","010","000000","000","000","010","0011","00000","0000",'1'),-- ['X->T', 'Y->X'] + ("10","000","00","000","000","000000","000","000","100","0101","00000","0000",'0'),-- ['T->Y'] + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- 03 ST0 + ("00","000","00","000","000","000000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->IR', 'PC++'] + ("00","000","00","000","001","000000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->T', 'PC++'] + ("00","000","00","000","000","000000","000","000","000","0000","00000","0000",'0'),-- [] + ("10","101","00","000","000","000000","000","000","000","0000","00000","0100",'1'),-- ['T->[ST]'] + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- 04 TSB ZP + ("00","000","00","000","000","000000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->IR', 'PC++'] + ("00","000","00","000","000","001000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->AAL', 'PC++'] + ("00","000","00","000","000","000000","000","000","000","0000","00000","0000",'0'),-- [] + ("00","011","00","101","001","000000","000","000","000","0001","01110","0000",'1'),-- ['ALU(A,[20:AAL])->T', 'Flags'] + ("00","000","00","000","000","000000","000","000","000","0000","00000","0000",'0'),-- [] + ("10","011","00","000","000","000000","000","000","000","0000","00000","0100",'1'),-- ['T->[20:AAL]'] + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- 05 ORA ZP + ("00","000","00","000","000","000000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->IR', 'PC++'] + ("00","000","00","000","000","001000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->AAL', 'PC++'] + ("00","000","00","000","000","000000","000","000","000","0000","00000","0000",'0'),-- [] + ("10","011","00","001","000","000000","000","000","001","0001","00010","0000",'1'),-- ['ALU(A,[20:AAL])->A', 'Flags'] + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- 06 ASL ZP + ("00","000","00","000","000","000000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->IR', 'PC++'] + ("00","000","00","000","000","001000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->AAL', 'PC++'] + ("00","000","00","000","000","000000","000","000","000","0000","00000","0000",'0'),-- [] + ("00","011","00","101","001","000000","000","000","000","0000","01000","0000",'1'),-- ['ALU([20:AAL])->T', 'Flags'] + ("00","000","00","000","000","000000","000","000","000","0000","00000","0000",'0'),-- [] + ("10","011","00","000","000","000000","000","000","000","0000","00000","0100",'1'),-- ['T->[20:AAL]'] + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- 07 RMB0 + ("00","000","00","000","000","000000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->IR', 'PC++'] + ("00","000","00","000","000","001000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->AAL', 'PC++'] + ("00","000","00","000","000","000000","000","000","000","0000","00000","0000",'0'),-- [] + ("00","011","00","000","001","000000","000","000","000","1100","01101","0000",'1'),-- ['ALU([20:AAL])->T'] + ("00","000","00","000","000","000000","000","000","000","0000","00000","0000",'0'),-- [] + ("00","000","00","000","000","000000","000","000","000","0000","00000","0000",'0'),-- [] + ("10","011","00","000","000","000000","000","000","000","0000","00000","0100",'1'),-- ['T->[20:AAL]'] + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- 08 PHP + ("00","000","00","000","000","000000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->IR', 'PC++'] + ("00","000","00","000","000","000000","000","000","000","0000","00000","0000",'1'),-- [] + ("10","010","00","000","000","000000","000","011","000","0000","00000","0101",'1'),-- ['P->[21:SP]', 'SP--'] + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- 09 ORA IMM / IMM,(X) + ("00","000","00","000","000","000000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->IR', 'PC++'] + ("10","000","00","001","000","000000","001","000","001","0001","00010","0000",'1'),-- ['ALU(A,[PC])->A', 'PC++', 'Flags'] + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- 0A ASL A + ("00","000","00","000","000","000000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->IR', 'PC++'] + ("10","000","00","101","000","000000","000","000","001","0001","01000","0000",'1'),-- ['ALU(A)->A', 'Flags'] + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- 0B + ("00","000","00","000","000","000000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->IR', 'PC++'] + ("10","000","00","000","000","000000","000","000","000","0000","00000","0000",'0'),-- [] + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- 0C TSB ABS + ("00","000","00","000","000","000000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->IR', 'PC++'] + ("00","000","00","000","000","001000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->AAL', 'PC++'] + ("00","000","00","000","000","000001","001","000","000","0000","00000","0000",'1'),-- ['[PC]->AAH', 'PC++'] + ("00","000","00","000","000","000000","000","000","000","0000","00000","0000",'0'),-- [] + ("00","001","00","101","001","000000","000","000","000","0001","01110","0000",'1'),-- ['ALU(A,[AA])->T', 'Flags'] + ("00","000","00","000","000","000000","000","000","000","0000","00000","0000",'0'),-- [] + ("10","001","00","000","000","000000","000","000","000","0000","00000","0100",'1'),-- ['T->[AA]'] + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- 0D ORA ABS + ("00","000","00","000","000","000000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->IR', 'PC++'] + ("00","000","00","000","000","001000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->AAL', 'PC++'] + ("00","000","00","000","000","000001","001","000","000","0000","00000","0000",'1'),-- ['[PC]->AAH', 'PC++'] + ("00","000","00","000","000","000000","000","000","000","0000","00000","0000",'0'),-- [] + ("10","001","00","001","000","000000","000","000","001","0001","00010","0000",'1'),-- ['ALU(A,[AA])->A', 'Flags'] + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- 0E ASL ABS + ("00","000","00","000","000","000000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->IR', 'PC++'] + ("00","000","00","000","000","001000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->AAL', 'PC++'] + ("00","000","00","000","000","000001","001","000","000","0000","00000","0000",'1'),-- ['[PC]->AAH', 'PC++'] + ("00","000","00","000","000","000000","000","000","000","0000","00000","0000",'0'),-- [] + ("00","001","00","101","001","000000","000","000","000","0000","01000","0000",'1'),-- ['ALU([AA])->T', 'Flags'] + ("00","000","00","000","000","000000","000","000","000","0000","00000","0000",'0'),-- [] + ("10","001","00","000","000","000000","000","000","000","0000","00000","0100",'1'),-- ['T->[AA]'] + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- 0F BBR0 + ("00","000","00","000","000","000000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->IR', 'PC++'] + ("00","000","00","000","000","001000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->AAL', 'PC++'] + ("00","000","00","000","000","000000","000","000","000","0000","00000","0000",'0'),-- [] + ("00","000","00","000","000","000000","000","000","000","0000","00000","0000",'0'),-- [] + ("00","011","00","000","000","000000","000","000","000","0000","00000","0000",'1'),-- ['[20:AAL]->DR'] + ("10","000","00","000","000","001000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->AAL', 'PC++'] + ("00","000","00","000","000","000000","100","000","000","0000","00000","0000",'0'),-- ['PC+AAL->PC'] + ("10","000","00","000","000","000000","000","000","000","0000","00000","0000",'0'),-- [] + -- 10 BPL + ("00","000","00","000","000","000000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->IR', 'PC++'] + ("10","000","00","000","000","001000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->AAL', 'PC++'] + ("00","000","00","000","000","000000","000","000","000","0000","00000","0000",'1'),-- [] + ("10","000","00","000","000","000000","100","000","000","0000","00000","0000",'0'),-- ['PC+AAL->PC'] + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- 11 ORA (ZP),Y + ("00","000","00","000","000","000000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->IR', 'PC++'] + ("00","000","00","000","000","001000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->AAL', 'PC++'] + ("00","000","00","000","000","000000","000","000","000","0000","00000","0000",'0'),-- [] + ("00","011","00","000","000","010000","000","000","000","0000","00000","0000",'1'),-- ['[20:AAL]->DR', 'AAL+1->AAL'] + ("00","011","00","000","000","110001","000","000","000","0000","00000","0000",'1'),-- ['[20:AAL]->AAH', 'DR+Y->AAL'] + ("00","000","00","000","000","000011","000","000","000","0000","00000","0000",'1'),-- ['AAH+AALCarry->AAH'] + ("10","001","00","001","000","000000","000","000","001","0001","00010","0000",'1'),-- ['ALU(A,[AA])->A', 'Flags'] + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- 12 ORA (ZP) + ("00","000","00","000","000","000000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->IR', 'PC++'] + ("00","000","00","000","000","001000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->AAL', 'PC++'] + ("00","000","00","000","000","000000","000","000","000","0000","00000","0000",'0'),-- [] + ("00","011","00","000","000","010000","000","000","000","0000","00000","0000",'1'),-- ['[20:AAL]->DR', 'AAL+1->AAL'] + ("00","011","00","000","000","101001","000","000","000","0000","00000","0000",'1'),-- ['[20:AAL]->AAH', 'DR->AAL'] + ("00","000","00","000","000","000000","000","000","000","0000","00000","0000",'0'),-- [] + ("10","001","00","001","000","000000","000","000","001","0001","00010","0000",'1'),-- ['ALU(A,[AA])->A', 'Flags'] + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- 13 ST1 + ("00","000","00","000","000","000000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->IR', 'PC++'] + ("00","000","00","000","001","000000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->T', 'PC++'] + ("00","000","00","000","000","000000","000","000","000","0000","00000","0000",'0'),-- [] + ("10","101","00","000","000","000000","000","000","000","0000","00000","0100",'1'),-- ['T->[ST]'] + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- 14 TRB ZP + ("00","000","00","000","000","000000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->IR', 'PC++'] + ("00","000","00","000","000","001000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->AAL', 'PC++'] + ("00","000","00","000","000","000000","000","000","000","0000","00000","0000",'0'),-- [] + ("00","011","00","101","001","000000","000","000","000","0001","01101","0000",'1'),-- ['ALU(A,[20:AAL])->T', 'Flags'] + ("00","000","00","000","000","000000","000","000","000","0000","00000","0000",'0'),-- [] + ("10","011","00","000","000","000000","000","000","000","0000","00000","0100",'1'),-- ['T->[20:AAL]'] + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- 15 ORA ZP,X + ("00","000","00","000","000","000000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->IR', 'PC++'] + ("00","000","00","000","000","001000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->AAL', 'PC++'] + ("00","000","00","000","000","011000","000","000","000","0000","00000","0000",'0'),-- ['AAL+X->AAL'] + ("10","011","00","001","000","000000","000","000","001","0001","00010","0000",'1'),-- ['ALU(A,[20:AAL])->A', 'Flags'] + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- 16 ASL ZP,X + ("00","000","00","000","000","000000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->IR', 'PC++'] + ("00","000","00","000","000","001000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->AAL', 'PC++'] + ("00","000","00","000","000","011000","000","000","000","0000","00000","0000",'0'),-- ['AAL+X->AAL'] + ("00","011","00","101","001","000000","000","000","000","0000","01000","0000",'1'),-- ['ALU([20:AAL])->T', 'Flags'] + ("00","000","00","000","000","000000","000","000","000","0000","00000","0000",'0'),-- [] + ("10","011","00","000","000","000000","000","000","000","0000","00000","0100",'1'),-- ['T->[20:AAL]'] + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- 17 RMB1 + ("00","000","00","000","000","000000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->IR', 'PC++'] + ("00","000","00","000","000","001000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->AAL', 'PC++'] + ("00","000","00","000","000","000000","000","000","000","0000","00000","0000",'0'),-- [] + ("00","011","00","000","001","000000","000","000","000","1100","01101","0000",'1'),-- ['ALU([20:AAL])->T'] + ("00","000","00","000","000","000000","000","000","000","0000","00000","0000",'0'),-- [] + ("00","000","00","000","000","000000","000","000","000","0000","00000","0000",'0'),-- [] + ("10","011","00","000","000","000000","000","000","000","0000","00000","0100",'1'),-- ['T->[20:AAL]'] + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- 18 CLC + ("00","000","00","000","000","000000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->IR', 'PC++'] + ("10","000","00","100","000","000000","000","000","000","0000","00000","0000",'1'),-- ['Flags'] + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- 19 ORA ABS,Y + ("00","000","00","000","000","000000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->IR', 'PC++'] + ("00","000","00","000","000","001000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->AAL', 'PC++'] + ("00","000","00","000","000","100001","001","000","000","0000","00000","0000",'1'),-- ['[PC]->AAH', 'PC++', 'AAL+Y->AAL'] + ("00","000","00","000","000","000011","000","000","000","0000","00000","0000",'0'),-- ['AAH+AALCarry->AAH'] + ("10","001","00","001","000","000000","000","000","001","0001","00010","0000",'1'),-- ['ALU(A,[AA])->A', 'Flags'] + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- 1A INC A + ("00","000","00","000","000","000000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->IR', 'PC++'] + ("10","000","00","001","000","000000","000","000","001","0001","00111","0000",'1'),-- ['ALU(A)->A', 'Flags'] + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- 1B + ("00","000","00","000","000","000000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->IR', 'PC++'] + ("10","000","00","000","000","000000","000","000","000","0000","00000","0000",'0'),-- [] + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- 1C TRB ABS + ("00","000","00","000","000","000000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->IR', 'PC++'] + ("00","000","00","000","000","001000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->AAL', 'PC++'] + ("00","000","00","000","000","000001","001","000","000","0000","00000","0000",'1'),-- ['[PC]->AAH', 'PC++'] + ("00","000","00","000","000","000000","000","000","000","0000","00000","0000",'0'),-- [] + ("00","001","00","101","001","000000","000","000","000","0001","01101","0000",'1'),-- ['ALU(A,[AA])->T', 'Flags'] + ("00","000","00","000","000","000000","000","000","000","0000","00000","0000",'0'),-- [] + ("10","001","00","000","000","000000","000","000","000","0000","00000","0100",'1'),-- ['T->[AA]'] + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- 1D ORA ABS,X + ("00","000","00","000","000","000000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->IR', 'PC++'] + ("00","000","00","000","000","001000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->AAL', 'PC++'] + ("00","000","00","000","000","011001","001","000","000","0000","00000","0000",'1'),-- ['[PC]->AAH', 'PC++', 'AAL+X->AAL'] + ("00","000","00","000","000","000011","000","000","000","0000","00000","0000",'0'),-- ['AAH+AALCarry->AAH'] + ("10","001","00","001","000","000000","000","000","001","0001","00010","0000",'1'),-- ['ALU(A,[AA])->A', 'Flags'] + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- 1E ASL ABS,X + ("00","000","00","000","000","000000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->IR', 'PC++'] + ("00","000","00","000","000","001000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->AAL', 'PC++'] + ("00","000","00","000","000","011001","001","000","000","0000","00000","0000",'1'),-- ['[PC]->AAH', 'PC++', 'AAL+X->AAL'] + ("00","000","00","000","000","000011","000","000","000","0000","00000","0000",'0'),-- ['AAH+AALCarry->AAH'] + ("00","001","00","101","001","000000","000","000","000","0000","01000","0000",'1'),-- ['ALU([AA])->T', 'Flags'] + ("00","000","00","000","000","000000","000","000","000","0000","00000","0000",'0'),-- [] + ("10","001","00","000","000","000000","000","000","000","0000","00000","0100",'1'),-- ['T->[AA]'] + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- 1F BBR1 + ("00","000","00","000","000","000000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->IR', 'PC++'] + ("00","000","00","000","000","001000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->AAL', 'PC++'] + ("00","000","00","000","000","000000","000","000","000","0000","00000","0000",'0'),-- [] + ("00","000","00","000","000","000000","000","000","000","0000","00000","0000",'0'),-- [] + ("00","011","00","000","000","000000","000","000","000","0000","00000","0000",'1'),-- ['[20:AAL]->DR'] + ("10","000","00","000","000","001000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->AAL', 'PC++'] + ("00","000","00","000","000","000000","100","000","000","0000","00000","0000",'0'),-- ['PC+AAL->PC'] + ("10","000","00","000","000","000000","000","000","000","0000","00000","0000",'0'),-- [] + -- 20 JSR ABS + ("00","000","00","000","000","000000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->IR', 'PC++'] + ("00","000","00","000","000","001000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->AAL', 'PC++'] + ("00","000","00","000","000","000001","000","000","000","0000","00000","0000",'1'),-- ['[PC]->AAH'] + ("00","000","00","000","000","000000","000","000","000","0000","00000","0000",'0'),-- [] + ("00","010","00","000","000","000000","000","011","000","0000","00000","0110",'1'),-- ['PCH->[00:SP]', 'SP--'] + ("00","010","00","000","000","000000","000","011","000","0000","00000","0111",'1'),-- ['PCL->[00:SP]', 'SP--'] + ("10","000","00","000","000","000000","110","000","000","0000","00000","0000",'0'),-- ['AA->PC'] + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- 21 AND (ZP,X) + ("00","000","00","000","000","000000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->IR', 'PC++'] + ("00","000","00","000","000","001000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->AAL', 'PC++'] + ("00","000","00","000","000","011000","000","000","000","0000","00000","0000",'0'),-- ['AAL+X->AAL'] + ("00","011","00","000","000","010000","000","000","000","0000","00000","0000",'1'),-- ['[20:AAL]->DR', 'AAL+1->AAL'] + ("00","011","00","000","000","101001","000","000","000","0000","00000","0000",'1'),-- ['[20:AAL]->AAH', 'DR->AAL'] + ("00","000","00","000","000","000000","000","000","000","0000","00000","0000",'0'),-- [] + ("10","001","00","001","000","000000","000","000","001","0001","00001","0000",'1'),-- ['ALU(A,[AA])->A', 'Flags'] + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- 22 SAX + ("00","000","00","000","000","000000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->IR', 'PC++'] + ("00","000","00","000","010","000000","000","000","010","0001","00000","0000",'1'),-- ['X->T', 'A->X'] + ("10","000","00","000","000","000000","000","000","001","0101","00000","0000",'0'),-- ['T->A'] + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- 23 ST2 + ("00","000","00","000","000","000000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->IR', 'PC++'] + ("00","000","00","000","001","000000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->T', 'PC++'] + ("00","000","00","000","000","000000","000","000","000","0000","00000","0000",'0'),-- [] + ("10","101","00","000","000","000000","000","000","000","0000","00000","0100",'1'),-- ['T->[ST]'] + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- 24 BIT ZP + ("00","000","00","000","000","000000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->IR', 'PC++'] + ("00","000","00","000","000","001000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->AAL', 'PC++'] + ("00","000","00","000","000","000000","000","000","000","0000","00000","0000",'0'),-- [] + ("10","011","00","101","000","000000","000","000","000","0001","01100","0000",'1'),-- ['ALU(A,[20:AAL])', 'Flags'] + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- 25 AND ZP + ("00","000","00","000","000","000000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->IR', 'PC++'] + ("00","000","00","000","000","001000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->AAL', 'PC++'] + ("00","000","00","000","000","000000","000","000","000","0000","00000","0000",'0'),-- [] + ("10","011","00","001","000","000000","000","000","001","0001","00001","0000",'1'),-- ['ALU(A,[20:AAL])->A', 'Flags'] + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- 26 ROL ZP + ("00","000","00","000","000","000000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->IR', 'PC++'] + ("00","000","00","000","000","001000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->AAL', 'PC++'] + ("00","000","00","000","000","000000","000","000","000","0000","00000","0000",'0'),-- [] + ("00","011","00","101","001","000000","000","000","000","0000","01010","0000",'1'),-- ['ALU([20:AAL])->T', 'Flags'] + ("00","000","00","000","000","000000","000","000","000","0000","00000","0000",'0'),-- [] + ("10","011","00","000","000","000000","000","000","000","0000","00000","0100",'1'),-- ['T->[20:AAL]'] + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- 27 RMB2 + ("00","000","00","000","000","000000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->IR', 'PC++'] + ("00","000","00","000","000","001000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->AAL', 'PC++'] + ("00","000","00","000","000","000000","000","000","000","0000","00000","0000",'0'),-- [] + ("00","011","00","000","001","000000","000","000","000","1100","01101","0000",'1'),-- ['ALU([20:AAL])->T'] + ("00","000","00","000","000","000000","000","000","000","0000","00000","0000",'0'),-- [] + ("00","000","00","000","000","000000","000","000","000","0000","00000","0000",'0'),-- [] + ("10","011","00","000","000","000000","000","000","000","0000","00000","0100",'1'),-- ['T->[20:AAL]'] + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- 28 PLP + ("00","000","00","000","000","000000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->IR', 'PC++'] + ("00","000","00","000","000","000000","000","000","000","0000","00000","0000",'0'),-- [] + ("00","000","00","000","000","000000","000","010","000","0000","00000","0000",'0'),-- ['SP++'] + ("10","010","00","011","000","000000","000","000","000","0000","00000","0000",'1'),-- ['[21:SP]->P'] + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- 29 AND IMM / IMM,(X) + ("00","000","00","000","000","000000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->IR', 'PC++'] + ("10","000","00","001","000","000000","001","000","001","0001","00001","0000",'1'),-- ['ALU(A,[PC])->A', 'PC++', 'Flags'] + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- 2A ROL A + ("00","000","00","000","000","000000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->IR', 'PC++'] + ("10","000","00","101","000","000000","000","000","001","0001","01010","0000",'1'),-- ['ALU(A)->A', 'Flags'] + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- 2B + ("00","000","00","000","000","000000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->IR', 'PC++'] + ("10","000","00","000","000","000000","000","000","000","0000","00000","0000",'0'),-- [] + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- 2C BIT ABS + ("00","000","00","000","000","000000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->IR', 'PC++'] + ("00","000","00","000","000","001000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->AAL', 'PC++'] + ("00","000","00","000","000","000001","001","000","000","0000","00000","0000",'1'),-- ['[PC]->AAH', 'PC++'] + ("00","000","00","000","000","000000","000","000","000","0000","00000","0000",'0'),-- [] + ("10","001","00","101","000","000000","000","000","000","0001","01100","0000",'1'),-- ['ALU(A,[AA])', 'Flags'] + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- 2D AND ABS + ("00","000","00","000","000","000000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->IR', 'PC++'] + ("00","000","00","000","000","001000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->AAL', 'PC++'] + ("00","000","00","000","000","000001","001","000","000","0000","00000","0000",'1'),-- ['[PC]->AAH', 'PC++'] + ("00","000","00","000","000","000000","000","000","000","0000","00000","0000",'0'),-- [] + ("10","001","00","001","000","000000","000","000","001","0001","00001","0000",'1'),-- ['ALU(A,[AA])->A', 'Flags'] + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- 2E ROL ABS + ("00","000","00","000","000","000000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->IR', 'PC++'] + ("00","000","00","000","000","001000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->AAL', 'PC++'] + ("00","000","00","000","000","000001","001","000","000","0000","00000","0000",'1'),-- ['[PC]->AAH', 'PC++'] + ("00","000","00","000","000","000000","000","000","000","0000","00000","0000",'0'),-- [] + ("00","001","00","101","001","000000","000","000","000","0000","01010","0000",'1'),-- ['ALU([AA])->T', 'Flags'] + ("00","000","00","000","000","000000","000","000","000","0000","00000","0000",'0'),-- [] + ("10","001","00","000","000","000000","000","000","000","0000","00000","0100",'1'),-- ['T->[AA]'] + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- 2F BBR2 + ("00","000","00","000","000","000000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->IR', 'PC++'] + ("00","000","00","000","000","001000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->AAL', 'PC++'] + ("00","000","00","000","000","000000","000","000","000","0000","00000","0000",'0'),-- [] + ("00","000","00","000","000","000000","000","000","000","0000","00000","0000",'0'),-- [] + ("00","011","00","000","000","000000","000","000","000","0000","00000","0000",'1'),-- ['[20:AAL]->DR'] + ("10","000","00","000","000","001000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->AAL', 'PC++'] + ("00","000","00","000","000","000000","100","000","000","0000","00000","0000",'0'),-- ['PC+AAL->PC'] + ("10","000","00","000","000","000000","000","000","000","0000","00000","0000",'0'),-- [] + -- 30 BMI + ("00","000","00","000","000","000000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->IR', 'PC++'] + ("10","000","00","000","000","001000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->AAL', 'PC++'] + ("00","000","00","000","000","000000","000","000","000","0000","00000","0000",'1'),-- [] + ("10","000","00","000","000","000000","100","000","000","0000","00000","0000",'0'),-- ['PC+AAL->PC'] + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- 31 AND (ZP),Y + ("00","000","00","000","000","000000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->IR', 'PC++'] + ("00","000","00","000","000","001000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->AAL', 'PC++'] + ("00","000","00","000","000","000000","000","000","000","0000","00000","0000",'0'),-- [] + ("00","011","00","000","000","010000","000","000","000","0000","00000","0000",'1'),-- ['[20:AAL]->DR', 'AAL+1->AAL'] + ("00","011","00","000","000","110001","000","000","000","0000","00000","0000",'1'),-- ['[20:AAL]->AAH', 'DR+Y->AAL'] + ("00","000","00","000","000","000011","000","000","000","0000","00000","0000",'0'),-- ['AAH+AALCarry->AAH'] + ("10","001","00","001","000","000000","000","000","001","0001","00001","0000",'1'),-- ['ALU(A,[AA])->A', 'Flags'] + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- 32 AND (ZP) + ("00","000","00","000","000","000000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->IR', 'PC++'] + ("00","000","00","000","000","001000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->AAL', 'PC++'] + ("00","000","00","000","000","000000","000","000","000","0000","00000","0000",'0'),-- [] + ("00","011","00","000","000","010000","000","000","000","0000","00000","0000",'1'),-- ['[20:AAL]->DR', 'AAL+1->AAL'] + ("00","011","00","000","000","101001","000","000","000","0000","00000","0000",'1'),-- ['[20:AAL]->AAH', 'DR->AAL'] + ("00","000","00","000","000","000000","000","000","000","0000","00000","0000",'0'),-- [] + ("10","001","00","001","000","000000","000","000","001","0001","00001","0000",'1'),-- ['ALU(A,[AA])->A', 'Flags'] + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- 33 + ("00","000","00","000","000","000000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->IR', 'PC++'] + ("10","000","00","000","000","000000","000","000","000","0000","00000","0000",'0'),-- [] + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- 34 BIT ZP,X + ("00","000","00","000","000","000000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->IR', 'PC++'] + ("00","000","00","000","000","001000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->AAL', 'PC++'] + ("00","000","00","000","000","011000","000","000","000","0000","00000","0000",'0'),-- ['AAL+X->AAL'] + ("10","011","00","101","000","000000","000","000","000","0001","01100","0000",'1'),-- ['ALU(A,[20:AAL])', 'Flags'] + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- 35 AND ZP,X + ("00","000","00","000","000","000000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->IR', 'PC++'] + ("00","000","00","000","000","001000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->AAL', 'PC++'] + ("00","000","00","000","000","011000","000","000","000","0000","00000","0000",'0'),-- ['AAL+X->AAL'] + ("10","011","00","001","000","000000","000","000","001","0001","00001","0000",'1'),-- ['ALU(A,[20:AAL])->A', 'Flags'] + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- 36 ROL ZP,X + ("00","000","00","000","000","000000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->IR', 'PC++'] + ("00","000","00","000","000","001000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->AAL', 'PC++'] + ("00","000","00","000","000","011000","000","000","000","0000","00000","0000",'0'),-- ['AAL+X->AAL'] + ("00","011","00","101","001","000000","000","000","000","0000","01010","0000",'1'),-- ['ALU([20:AAL])->T', 'Flags'] + ("00","000","00","000","000","000000","000","000","000","0000","00000","0000",'0'),-- [] + ("10","011","00","000","000","000000","000","000","000","0000","00000","0100",'1'),-- ['T->[20:AAL]'] + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- 37 RMB3 + ("00","000","00","000","000","000000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->IR', 'PC++'] + ("00","000","00","000","000","001000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->AAL', 'PC++'] + ("00","000","00","000","000","000000","000","000","000","0000","00000","0000",'0'),-- [] + ("00","011","00","000","001","000000","000","000","000","1100","01101","0000",'1'),-- ['ALU([20:AAL])->T'] + ("00","000","00","000","000","000000","000","000","000","0000","00000","0000",'0'),-- [] + ("00","000","00","000","000","000000","000","000","000","0000","00000","0000",'0'),-- [] + ("10","011","00","000","000","000000","000","000","000","0000","00000","0100",'1'),-- ['T->[20:AAL]'] + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- 38 SEC + ("00","000","00","000","000","000000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->IR', 'PC++'] + ("10","000","00","100","000","000000","000","000","000","0000","00000","0000",'1'),-- ['Flags'] + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- 39 AND ABS,Y + ("00","000","00","000","000","000000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->IR', 'PC++'] + ("00","000","00","000","000","001000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->AAL', 'PC++'] + ("00","000","00","000","000","100001","001","000","000","0000","00000","0000",'1'),-- ['[PC]->AAH', 'PC++', 'AAL+Y->AAL'] + ("00","000","00","000","000","000011","000","000","000","0000","00000","0000",'0'),-- ['AAH+AALCarry->AAH'] + ("10","001","00","001","000","000000","000","000","001","0001","00001","0000",'1'),-- ['ALU(A,[AA])->A', 'Flags'] + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- 3A DEC A + ("00","000","00","000","000","000000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->IR', 'PC++'] + ("10","000","00","001","000","000000","000","000","001","0001","00110","0000",'1'),-- ['ALU(A)->A', 'Flags'] + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- 3B + ("00","000","00","000","000","000000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->IR', 'PC++'] + ("10","000","00","000","000","000000","000","000","000","0000","00000","0000",'0'),-- [] + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- 3C BIT ABS,X + ("00","000","00","000","000","000000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->IR', 'PC++'] + ("00","000","00","000","000","001000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->AAL', 'PC++'] + ("00","000","00","000","000","011001","001","000","000","0000","00000","0000",'1'),-- ['[PC]->AAH', 'PC++', 'AAL+X->AAL'] + ("00","000","00","000","000","000011","000","000","000","0000","00000","0000",'0'),-- ['AAH+AALCarry->AAH'] + ("10","001","00","101","000","000000","000","000","000","0001","01100","0000",'1'),-- ['ALU(A,[AA])', 'Flags'] + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- 3D AND ABS,X + ("00","000","00","000","000","000000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->IR', 'PC++'] + ("00","000","00","000","000","001000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->AAL', 'PC++'] + ("00","000","00","000","000","011001","001","000","000","0000","00000","0000",'1'),-- ['[PC]->AAH', 'PC++', 'AAL+X->AAL'] + ("00","000","00","000","000","000011","000","000","000","0000","00000","0000",'0'),-- ['AAH+AALCarry->AAH'] + ("10","001","00","001","000","000000","000","000","001","0001","00001","0000",'1'),-- ['ALU(A,[AA])->A', 'Flags'] + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- 3E ROL ABS,X + ("00","000","00","000","000","000000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->IR', 'PC++'] + ("00","000","00","000","000","001000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->AAL', 'PC++'] + ("00","000","00","000","000","011001","001","000","000","0000","00000","0000",'1'),-- ['[PC]->AAH', 'PC++', 'AAL+X->AAL'] + ("00","000","00","000","000","000011","000","000","000","0000","00000","0000",'0'),-- ['AAH+AALCarry->AAH'] + ("00","001","00","101","001","000000","000","000","000","0000","01010","0000",'1'),-- ['ALU([AA])->T', 'Flags'] + ("00","000","00","000","000","000000","000","000","000","0000","00000","0000",'0'),-- [] + ("10","001","00","000","000","000000","000","000","000","0000","00000","0100",'1'),-- ['T->[AA]'] + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- 3F BBR3 + ("00","000","00","000","000","000000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->IR', 'PC++'] + ("00","000","00","000","000","001000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->AAL', 'PC++'] + ("00","000","00","000","000","000000","000","000","000","0000","00000","0000",'0'),-- [] + ("00","000","00","000","000","000000","000","000","000","0000","00000","0000",'0'),-- [] + ("00","011","00","000","000","000000","000","000","000","0000","00000","0000",'1'),-- ['[20:AAL]->DR'] + ("10","000","00","000","000","001000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->AAL', 'PC++'] + ("00","000","00","000","000","000000","100","000","000","0000","00000","0000",'0'),-- ['PC+AAL->PC'] + ("10","000","00","000","000","000000","000","000","000","0000","00000","0000",'0'),-- [] + -- 40 RTI + ("00","000","00","000","000","000000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->IR', 'PC++'] + ("00","000","00","000","000","000000","000","000","000","0000","00000","0000",'0'),-- [] + ("00","000","00","000","000","000000","000","000","000","0000","00000","0000",'0'),-- [] + ("00","000","00","000","000","000000","000","010","000","0000","00000","0000",'0'),-- ['SP++'] + ("00","010","00","011","000","000000","000","010","000","0000","00000","0000",'1'),-- ['[21:SP]->P', 'SP++'] + ("00","010","00","000","000","000000","010","010","000","0000","00000","0000",'1'),-- ['[21:SP]->PCL', 'SP++'] + ("10","010","00","000","000","000000","011","000","000","0000","00000","0000",'1'),-- ['[21:SP]->PCH'] + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- 41 EOR (ZP,X) + ("00","000","00","000","000","000000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->IR', 'PC++'] + ("00","000","00","000","000","001000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->AAL', 'PC++'] + ("00","000","00","000","000","011000","000","000","000","0000","00000","0000",'0'),-- ['AAL+X->AAL'] + ("00","011","00","000","000","010000","000","000","000","0000","00000","0000",'1'),-- ['[20:AAL]->DR', 'AAL+1->AAL'] + ("00","011","00","000","000","101001","000","000","000","0000","00000","0000",'1'),-- ['[20:AAL]->AAH', 'DR->AAL'] + ("00","000","00","000","000","000000","000","000","000","0000","00000","0000",'0'),-- [] + ("10","001","00","001","000","000000","000","000","001","0001","00011","0000",'1'),-- ['ALU(A,[AA])->A', 'Flags'] + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- 42 SAY + ("00","000","00","000","000","000000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->IR', 'PC++'] + ("00","000","00","000","011","000000","000","000","100","0100","00000","0000",'1'),-- ['Y->T', 'A->Y'] + ("10","000","00","000","000","000000","000","000","001","0100","00000","0000",'0'),-- ['T->A'] + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- 43 TMAi + ("00","000","00","000","000","000000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->IR', 'PC++'] + ("00","000","00","000","001","000000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->T', 'PC++'] + ("00","000","00","000","000","000000","000","000","000","0000","00000","0000",'0'),-- [] + ("10","000","00","000","000","000000","000","000","001","1011","00000","0000",'0'),-- ['MPR->A'] + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- 44 BSR + ("00","000","00","000","000","000000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->IR', 'PC++'] + ("00","000","00","000","000","000000","000","000","000","0000","00000","0000",'0'),-- [] + ("00","010","00","000","000","000000","000","011","000","0000","00000","0110",'1'),-- ['PCH->[00:SP]', 'SP--'] + ("00","010","00","000","000","000000","000","011","000","0000","00000","0111",'1'),-- ['PCL->[00:SP]', 'SP--'] + ("00","000","00","000","000","001000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->AAL', 'PC++'] + ("00","000","00","000","000","000000","000","000","000","0000","00000","0000",'0'),-- [] + ("00","000","00","000","000","000000","000","000","000","0000","00000","0000",'0'),-- [] + ("10","000","00","000","000","000000","100","000","000","0000","00000","0000",'0'),-- ['PC+AAL->PC'] + -- 45 EOR ZP + ("00","000","00","000","000","000000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->IR', 'PC++'] + ("00","000","00","000","000","001000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->AAL', 'PC++'] + ("00","000","00","000","000","000000","000","000","000","0000","00000","0000",'0'),-- [] + ("10","011","00","001","000","000000","000","000","001","0001","00011","0000",'1'),-- ['ALU(A,[20:AAL])->A', 'Flags'] + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- 46 LSR ZP + ("00","000","00","000","000","000000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->IR', 'PC++'] + ("00","000","00","000","000","001000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->AAL', 'PC++'] + ("00","000","00","000","000","000000","000","000","000","0000","00000","0000",'0'),-- [] + ("00","011","00","101","001","000000","000","000","000","0000","01001","0000",'1'),-- ['ALU([20:AAL])->T', 'Flags'] + ("00","000","00","000","000","000000","000","000","000","0000","00000","0000",'0'),-- [] + ("10","011","00","000","000","000000","000","000","000","0000","00000","0100",'1'),-- ['T->[20:AAL]'] + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- 47 RMB4 + ("00","000","00","000","000","000000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->IR', 'PC++'] + ("00","000","00","000","000","001000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->AAL', 'PC++'] + ("00","000","00","000","000","000000","000","000","000","0000","00000","0000",'0'),-- [] + ("00","011","00","000","001","000000","000","000","000","1100","01101","0000",'1'),-- ['ALU([20:AAL])->T'] + ("00","000","00","000","000","000000","000","000","000","0000","00000","0000",'0'),-- [] + ("00","000","00","000","000","000000","000","000","000","0000","00000","0000",'0'),-- [] + ("10","011","00","000","000","000000","000","000","000","0000","00000","0100",'1'),-- ['T->[20:AAL]'] + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- 48 PHA + ("00","000","00","000","000","000000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->IR', 'PC++'] + ("00","000","00","000","000","000000","000","000","000","0000","00000","0000",'1'),-- [] + ("10","010","00","000","000","000000","000","011","000","0000","00000","0001",'1'),-- ['A->[21:SP]', 'SP--'] + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- 49 EOR IMM / IMM,(X) + ("00","000","00","000","000","000000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->IR', 'PC++'] + ("10","000","00","001","000","000000","001","000","001","0001","00011","0000",'1'),-- ['ALU(A,[PC])->A', 'PC++', 'Flags'] + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- 4A LSR A + ("00","000","00","000","000","000000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->IR', 'PC++'] + ("10","000","00","101","000","000000","000","000","001","0001","01001","0000",'1'),-- ['ALU(A)->A', 'Flags'] + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- 4B + ("00","000","00","000","000","000000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->IR', 'PC++'] + ("10","000","00","000","000","000000","000","000","000","0000","00000","0000",'0'),-- [] + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- 4C JMP ABS + ("00","000","00","000","000","000000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->IR', 'PC++'] + ("00","000","00","000","000","001000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->AAL', 'PC++'] + ("00","000","00","000","000","000001","000","000","000","0000","00000","0000",'1'),-- ['[PC]->AAH'] + ("10","000","00","000","000","000000","110","000","000","0000","00000","0000",'0'),-- ['AA->PC'] + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- 4D EOR ABS + ("00","000","00","000","000","000000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->IR', 'PC++'] + ("00","000","00","000","000","001000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->AAL', 'PC++'] + ("00","000","00","000","000","000001","001","000","000","0000","00000","0000",'1'),-- ['[PC]->AAH', 'PC++'] + ("00","000","00","000","000","000000","000","000","000","0000","00000","0000",'0'),-- [] + ("10","001","00","001","000","000000","000","000","001","0001","00011","0000",'1'),-- ['ALU(A,[AA])->A', 'Flags'] + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- 4E LSR ABS + ("00","000","00","000","000","000000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->IR', 'PC++'] + ("00","000","00","000","000","001000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->AAL', 'PC++'] + ("00","000","00","000","000","000001","001","000","000","0000","00000","0000",'1'),-- ['[PC]->AAH', 'PC++'] + ("00","000","00","000","000","000000","000","000","000","0000","00000","0000",'0'),-- [] + ("00","001","00","101","001","000000","000","000","000","0000","01001","0000",'1'),-- ['ALU([AA])->T', 'Flags'] + ("00","000","00","000","000","000000","000","000","000","0000","00000","0000",'0'),-- [] + ("10","001","00","000","000","000000","000","000","000","0000","00000","0100",'1'),-- ['T->[AA]'] + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- 4F BBR4 + ("00","000","00","000","000","000000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->IR', 'PC++'] + ("00","000","00","000","000","001000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->AAL', 'PC++'] + ("00","000","00","000","000","000000","000","000","000","0000","00000","0000",'0'),-- [] + ("00","000","00","000","000","000000","000","000","000","0000","00000","0000",'0'),-- [] + ("00","011","00","000","000","000000","000","000","000","0000","00000","0000",'1'),-- ['[20:AAL]->DR'] + ("10","000","00","000","000","001000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->AAL', 'PC++'] + ("00","000","00","000","000","000000","100","000","000","0000","00000","0000",'0'),-- ['PC+AAL->PC'] + ("10","000","00","000","000","000000","000","000","000","0000","00000","0000",'0'),-- [] + -- 50 BVC + ("00","000","00","000","000","000000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->IR', 'PC++'] + ("10","000","00","000","000","001000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->AAL', 'PC++'] + ("00","000","00","000","000","000000","000","000","000","0000","00000","0000",'1'),-- [] + ("10","000","00","000","000","000000","100","000","000","0000","00000","0000",'0'),-- ['PC+AAL->PC'] + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- 51 EOR (ZP),Y + ("00","000","00","000","000","000000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->IR', 'PC++'] + ("00","000","00","000","000","001000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->AAL', 'PC++'] + ("00","000","00","000","000","000000","000","000","000","0000","00000","0000",'0'),-- [] + ("00","011","00","000","000","010000","000","000","000","0000","00000","0000",'1'),-- ['[20:AAL]->DR', 'AAL+1->AAL'] + ("00","011","00","000","000","110001","000","000","000","0000","00000","0000",'1'),-- ['[20:AAL]->AAH', 'DR+Y->AAL'] + ("00","000","00","000","000","000011","000","000","000","0000","00000","0000",'0'),-- ['AAH+AALCarry->AAH'] + ("10","001","00","001","000","000000","000","000","001","0001","00011","0000",'1'),-- ['ALU(A,[AA])->A', 'Flags'] + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- 52 EOR (ZP) + ("00","000","00","000","000","000000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->IR', 'PC++'] + ("00","000","00","000","000","001000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->AAL', 'PC++'] + ("00","000","00","000","000","000000","000","000","000","0000","00000","0000",'0'),-- [] + ("00","011","00","000","000","010000","000","000","000","0000","00000","0000",'1'),-- ['[20:AAL]->DR', 'AAL+1->AAL'] + ("00","011","00","000","000","101001","000","000","000","0000","00000","0000",'1'),-- ['[20:AAL]->AAH', 'DR->AAL'] + ("00","000","00","000","000","000000","000","000","000","0000","00000","0000",'0'),-- [] + ("10","001","00","001","000","000000","000","000","001","0001","00011","0000",'1'),-- ['ALU(A,[AA])->A', 'Flags'] + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- 53 TAMi + ("00","000","00","000","000","000000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->IR', 'PC++'] + ("00","000","00","000","001","000000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->T', 'PC++'] + ("00","000","00","000","000","000000","000","000","000","0000","00000","0000",'0'),-- [] + ("00","000","00","000","000","000000","000","000","000","0000","00000","0000",'0'),-- [] + ("10","000","00","000","000","000000","000","000","000","0000","00000","0000",'0'),-- ['A->MPR'] + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- 54 CSL + ("00","000","00","000","000","000000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->IR', 'PC++'] + ("00","000","00","000","000","000000","000","000","000","0000","00000","0000",'1'),-- [] + ("10","000","00","000","000","000000","000","000","000","0000","00000","0000",'0'),-- [] + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- 55 EOR ZP,X + ("00","000","00","000","000","000000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->IR', 'PC++'] + ("00","000","00","000","000","001000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->AAL', 'PC++'] + ("00","000","00","000","000","011000","000","000","000","0000","00000","0000",'0'),-- ['AAL+X->AAL'] + ("10","011","00","001","000","000000","000","000","001","0001","00011","0000",'1'),-- ['ALU(A,[20:AAL])->A', 'Flags'] + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- 56 LSR ZP,X + ("00","000","00","000","000","000000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->IR', 'PC++'] + ("00","000","00","000","000","001000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->AAL', 'PC++'] + ("00","000","00","000","000","011000","000","000","000","0000","00000","0000",'0'),-- ['AAL+X->AAL'] + ("00","011","00","101","001","000000","000","000","000","0000","01001","0000",'1'),-- ['ALU([20:AAL])->T', 'Flags'] + ("00","000","00","000","000","000000","000","000","000","0000","00000","0000",'0'),-- [] + ("10","011","00","000","000","000000","000","000","000","0000","00000","0100",'1'),-- ['T->[20:AAL]'] + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- 57 RMB5 + ("00","000","00","000","000","000000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->IR', 'PC++'] + ("00","000","00","000","000","001000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->AAL', 'PC++'] + ("00","000","00","000","000","000000","000","000","000","0000","00000","0000",'0'),-- [] + ("00","011","00","000","001","000000","000","000","000","1100","01101","0000",'1'),-- ['ALU([20:AAL])->T'] + ("00","000","00","000","000","000000","000","000","000","0000","00000","0000",'0'),-- [] + ("00","000","00","000","000","000000","000","000","000","0000","00000","0000",'0'),-- [] + ("10","011","00","000","000","000000","000","000","000","0000","00000","0100",'1'),-- ['T->[20:AAL]'] + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- 58 CLI + ("00","000","00","000","000","000000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->IR', 'PC++'] + ("10","000","00","100","000","000000","000","000","000","0000","00000","0000",'1'),-- ['Flags'] + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- 59 EOR ABS,Y + ("00","000","00","000","000","000000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->IR', 'PC++'] + ("00","000","00","000","000","001000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->AAL', 'PC++'] + ("00","000","00","000","000","100001","001","000","000","0000","00000","0000",'1'),-- ['[PC]->AAH', 'PC++', 'AAL+Y->AAL'] + ("00","000","00","000","000","000011","000","000","000","0000","00000","0000",'0'),-- ['AAH+AALCarry->AAH'] + ("10","001","00","001","000","000000","000","000","001","0001","00011","0000",'1'),-- ['ALU(A,[AA])->A', 'Flags'] + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- 5A PHY + ("00","000","00","000","000","000000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->IR', 'PC++'] + ("00","000","00","000","000","000000","000","000","000","0000","00000","0000",'1'),-- [] + ("10","010","00","000","000","000000","000","011","000","0000","00000","0011",'1'),-- ['Y->[21:SP]', 'SP--'] + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- 5B + ("00","000","00","000","000","000000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->IR', 'PC++'] + ("10","000","00","000","000","000000","000","000","000","0000","00000","0000",'0'),-- [] + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- 5C + ("00","000","00","000","000","000000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->IR', 'PC++'] + ("10","000","00","000","000","000000","000","000","000","0000","00000","0000",'0'),-- [] + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- 5D EOR ABS,X + ("00","000","00","000","000","000000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->IR', 'PC++'] + ("00","000","00","000","000","001000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->AAL', 'PC++'] + ("00","000","00","000","000","011001","001","000","000","0000","00000","0000",'1'),-- ['[PC]->AAH', 'PC++', 'AAL+X->AAL'] + ("00","000","00","000","000","000011","000","000","000","0000","00000","0000",'0'),-- ['AAH+AALCarry->AAH'] + ("10","001","00","001","000","000000","000","000","001","0001","00011","0000",'1'),-- ['ALU(A,[AA])->A', 'Flags'] + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- 5E LSR ABS,X + ("00","000","00","000","000","000000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->IR', 'PC++'] + ("00","000","00","000","000","001000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->AAL', 'PC++'] + ("00","000","00","000","000","011001","001","000","000","0000","00000","0000",'1'),-- ['[PC]->AAH', 'PC++', 'AAL+X->AAL'] + ("00","000","00","000","000","000011","000","000","000","0000","00000","0000",'0'),-- ['AAH+AALCarry->AAH'] + ("00","001","00","101","001","000000","000","000","000","0000","01001","0000",'1'),-- ['ALU([AA])->T', 'Flags'] + ("00","000","00","000","000","000000","000","000","000","0000","00000","0000",'0'),-- [] + ("10","001","00","000","000","000000","000","000","000","0000","00000","0100",'1'),-- ['T->[AA]'] + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- 5F BBR5 + ("00","000","00","000","000","000000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->IR', 'PC++'] + ("00","000","00","000","000","001000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->AAL', 'PC++'] + ("00","000","00","000","000","000000","000","000","000","0000","00000","0000",'0'),-- [] + ("00","000","00","000","000","000000","000","000","000","0000","00000","0000",'0'),-- [] + ("00","011","00","000","000","000000","000","000","000","0000","00000","0000",'1'),-- ['[20:AAL]->DR'] + ("10","000","00","000","000","001000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->AAL', 'PC++'] + ("00","000","00","000","000","000000","100","000","000","0000","00000","0000",'0'),-- ['PC+AAL->PC'] + ("10","000","00","000","000","000000","000","000","000","0000","00000","0000",'0'),-- [] + -- 60 RTS + ("00","000","00","000","000","000000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->IR', 'PC++'] + ("00","000","00","000","000","000000","000","000","000","0000","00000","0000",'0'),-- [] + ("00","000","00","000","000","000000","000","000","000","0000","00000","0000",'0'),-- [] + ("00","000","00","000","000","000000","000","010","000","0000","00000","0000",'0'),-- ['SP++'] + ("00","010","00","000","000","000000","010","010","000","0000","00000","0000",'1'),-- ['[21:SP]->PCL', 'SP++'] + ("00","010","00","000","000","000000","011","000","000","0000","00000","0000",'1'),-- ['[21:SP]->PCH'] + ("10","000","00","000","000","000000","001","000","000","0000","00000","0000",'0'),-- ['PC++'] + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- 61 ADC (ZP,X) + ("00","000","00","000","000","000000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->IR', 'PC++'] + ("00","000","00","000","000","001000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->AAL', 'PC++'] + ("00","000","00","000","000","011000","000","000","000","0000","00000","0000",'0'),-- ['AAL+X->AAL'] + ("00","011","00","000","000","010000","000","000","000","0000","00000","0000",'1'),-- ['[20:AAL]->DR', 'AAL+1->AAL'] + ("00","011","00","000","000","101001","000","000","000","0000","00000","0000",'1'),-- ['[20:AAL]->AAH', 'DR->AAL'] + ("00","000","00","000","000","000000","000","000","000","0000","00000","0000",'0'),-- [] + ("01","001","00","101","000","000000","000","000","001","0001","00100","0000",'1'),-- ['ALU(A,[AA])->A', 'Flags'] + ("10","000","00","000","000","000000","000","000","000","0000","00000","0000",'1'),-- [] + -- 62 CLA + ("00","000","00","000","000","000000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->IR', 'PC++'] + ("10","000","00","000","000","000000","000","000","001","1111","00000","0000",'1'),-- ['0->A'] + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- 63 + ("00","000","00","000","000","000000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->IR', 'PC++'] + ("10","000","00","000","000","000000","000","000","000","0000","00000","0000",'0'),-- [] + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- 64 STZ ZP + ("00","000","00","000","000","000000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->IR', 'PC++'] + ("00","000","00","000","000","001000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->AAL', 'PC++'] + ("00","000","00","000","000","000000","000","000","000","0000","00000","0000",'0'),-- [] + ("10","011","00","000","000","000000","000","000","000","0000","00000","1111",'1'),-- ['0->[20:AAL]'] + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- 65 ADC ZP + ("00","000","00","000","000","000000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->IR', 'PC++'] + ("00","000","00","000","000","001000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->AAL', 'PC++'] + ("00","000","00","000","000","000000","000","000","000","0000","00000","0000",'0'),-- [] + ("01","011","00","101","000","000000","000","000","001","0001","00100","0000",'1'),-- ['ALU(A,[20:AAL])->A', 'Flags'] + ("10","000","00","000","000","000000","000","000","000","0000","00000","0000",'0'),-- [] + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- 66 ROR ZP + ("00","000","00","000","000","000000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->IR', 'PC++'] + ("00","000","00","000","000","001000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->AAL', 'PC++'] + ("00","000","00","000","000","000000","000","000","000","0000","00000","0000",'0'),-- [] + ("00","011","00","101","001","000000","000","000","000","0000","01011","0000",'1'),-- ['ALU([20:AAL])->T', 'Flags'] + ("00","000","00","000","000","000000","000","000","000","0000","00000","0000",'0'),-- [] + ("10","011","00","000","000","000000","000","000","000","0000","00000","0100",'1'),-- ['T->[20:AAL]'] + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- 67 RMB6 + ("00","000","00","000","000","000000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->IR', 'PC++'] + ("00","000","00","000","000","001000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->AAL', 'PC++'] + ("00","000","00","000","000","000000","000","000","000","0000","00000","0000",'0'),-- [] + ("00","011","00","000","001","000000","000","000","000","1100","01101","0000",'1'),-- ['ALU([20:AAL])->T'] + ("00","000","00","000","000","000000","000","000","000","0000","00000","0000",'0'),-- [] + ("00","000","00","000","000","000000","000","000","000","0000","00000","0000",'0'),-- [] + ("10","011","00","000","000","000000","000","000","000","0000","00000","0100",'1'),-- ['T->[20:AAL]'] + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- 68 PLA + ("00","000","00","000","000","000000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->IR', 'PC++'] + ("00","000","00","000","000","000000","000","000","000","0000","00000","0000",'0'),-- [] + ("00","000","00","000","000","000000","000","010","000","0000","00000","0000",'0'),-- ['SP++'] + ("10","010","00","001","000","000000","000","000","001","0000","00000","0000",'1'),-- ['ALU([21:SP])->A'] + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- 69 ADC IMM / IMM,(X) + ("00","000","00","000","000","000000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->IR', 'PC++'] + ("01","000","00","101","000","000000","001","000","001","0001","00100","0000",'1'),-- ['ALU(A,[PC])->A', 'PC++', 'Flags'] + ("10","000","00","000","000","000000","000","000","000","0000","00000","0000",'0'),-- [] + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- 6A ROR A + ("00","000","00","000","000","000000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->IR', 'PC++'] + ("10","000","00","101","000","000000","000","000","001","0001","01011","0000",'1'),-- ['ALU(A)->A', 'Flags'] + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- 6B + ("00","000","00","000","000","000000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->IR', 'PC++'] + ("10","000","00","000","000","000000","000","000","000","0000","00000","0000",'0'),-- [] + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- 6C JMP (ABS) + ("00","000","00","000","000","000000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->IR', 'PC++'] + ("00","000","00","000","000","001000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->AAL', 'PC++'] + ("00","000","00","000","000","000001","001","000","000","0000","00000","0000",'1'),-- ['[PC]->AAH', 'PC++'] + ("00","000","00","000","000","000000","000","000","000","0000","00000","0000",'0'),-- [] + ("00","001","00","000","000","010000","010","000","000","0000","00000","0000",'1'),-- ['[AA]->PCL', 'AAL+1->AAL'] + ("00","000","00","000","000","000011","000","000","000","0000","00000","0000",'0'),-- ['AAH+AALCarry->AAH'] + ("10","001","00","000","000","000000","011","000","000","0000","00000","0000",'1'),-- ['[AA]->PCH'] + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- 6D ADC ABS + ("00","000","00","000","000","000000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->IR', 'PC++'] + ("00","000","00","000","000","001000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->AAL', 'PC++'] + ("00","000","00","000","000","000001","001","000","000","0000","00000","0000",'1'),-- ['[PC]->AAH', 'PC++'] + ("00","000","00","000","000","000000","000","000","000","0000","00000","0000",'0'),-- [] + ("01","001","00","101","000","000000","000","000","001","0001","00100","0000",'1'),-- ['ALU(A,[AA])->A', 'Flags'] + ("10","000","00","000","000","000000","000","000","000","0000","00000","0000",'0'),-- [] + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- 6E ROR ABS + ("00","000","00","000","000","000000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->IR', 'PC++'] + ("00","000","00","000","000","001000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->AAL', 'PC++'] + ("00","000","00","000","000","000001","001","000","000","0000","00000","0000",'1'),-- ['[PC]->AAH', 'PC++'] + ("00","000","00","000","000","000000","000","000","000","0000","00000","0000",'0'),-- [] + ("00","001","00","101","001","000000","000","000","000","0000","01011","0000",'1'),-- ['ALU([AA])->T', 'Flags'] + ("00","000","00","000","000","000000","000","000","000","0000","00000","0000",'0'),-- [] + ("10","001","00","000","000","000000","000","000","000","0000","00000","0100",'1'),-- ['T->[AA]'] + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- 6F BBR6 + ("00","000","00","000","000","000000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->IR', 'PC++'] + ("00","000","00","000","000","001000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->AAL', 'PC++'] + ("00","000","00","000","000","000000","000","000","000","0000","00000","0000",'0'),-- [] + ("00","000","00","000","000","000000","000","000","000","0000","00000","0000",'0'),-- [] + ("00","011","00","000","000","000000","000","000","000","0000","00000","0000",'1'),-- ['[20:AAL]->DR'] + ("10","000","00","000","000","001000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->AAL', 'PC++'] + ("00","000","00","000","000","000000","100","000","000","0000","00000","0000",'0'),-- ['PC+AAL->PC'] + ("10","000","00","000","000","000000","000","000","000","0000","00000","0000",'0'),-- [] + -- 70 BVS + ("00","000","00","000","000","000000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->IR', 'PC++'] + ("10","000","00","000","000","001000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->AAL', 'PC++'] + ("00","000","00","000","000","000000","000","000","000","0000","00000","0000",'1'),-- [] + ("10","000","00","000","000","000000","100","000","000","0000","00000","0000",'0'),-- ['PC+AAL->PC'] + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- 71 ADC (ZP),Y + ("00","000","00","000","000","000000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->IR', 'PC++'] + ("00","000","00","000","000","001000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->AAL', 'PC++'] + ("00","000","00","000","000","000000","000","000","000","0000","00000","0000",'0'),-- [] + ("00","011","00","000","000","010000","000","000","000","0000","00000","0000",'1'),-- ['[20:AAL]->DR', 'AAL+1->AAL'] + ("00","011","00","000","000","110001","000","000","000","0000","00000","0000",'1'),-- ['[20:AAL]->AAH', 'DR+Y->AAL'] + ("00","000","00","000","000","000011","000","000","000","0000","00000","0000",'0'),-- ['AAH+AALCarry->AAH'] + ("01","001","00","101","000","000000","000","000","001","0001","00100","0000",'1'),-- ['ALU(A,[AA])->A', 'Flags'] + ("10","000","00","000","000","000000","000","000","000","0000","00000","0000",'0'),-- [] + -- 72 ADC (ZP) + ("00","000","00","000","000","000000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->IR', 'PC++'] + ("00","000","00","000","000","001000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->AAL', 'PC++'] + ("00","000","00","000","000","000000","000","000","000","0000","00000","0000",'0'),-- [] + ("00","011","00","000","000","010000","000","000","000","0000","00000","0000",'1'),-- ['[20:AAL]->DR', 'AAL+1->AAL'] + ("00","011","00","000","000","101001","000","000","000","0000","00000","0000",'1'),-- ['[20:AAL]->AAH', 'DR->AAL'] + ("00","000","00","000","000","000000","000","000","000","0000","00000","0000",'0'),-- [] + ("01","001","00","101","000","000000","000","000","001","0001","00100","0000",'1'),-- ['ALU(A,[AA])->A', 'Flags'] + ("10","000","00","000","000","000000","000","000","000","0000","00000","0000",'0'),-- [] + -- 73 TII + ("00","000","00","000","000","000000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->IR', 'PC++'] + ("00","010","00","000","000","000000","000","011","000","0000","00000","0011",'1'),-- ['Y->[21:SP]', 'SP--'] + ("00","010","00","000","000","000000","000","011","000","0000","00000","0001",'1'),-- ['A->[21:SP]', 'SP--'] + ("00","010","00","000","000","000000","000","000","000","0000","00000","0010",'1'),-- ['X->[21:SP]'] + ("00","000","00","000","000","000000","001","000","010","0000","00000","0000",'1'),-- ['[PC]->X', 'PC++'] + ("00","000","01","000","000","000000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->SH', 'PC++'] + ("00","000","00","000","000","000000","001","000","100","0000","00000","0000",'1'),-- ['[PC]->Y', 'PC++'] + ("00","000","10","000","000","000000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->DH', 'PC++'] + -- 74 STZ ZP,X + ("00","000","00","000","000","000000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->IR', 'PC++'] + ("00","000","00","000","000","001000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->AAL', 'PC++'] + ("00","000","00","000","000","011000","000","000","000","0000","00000","0000",'0'),-- ['AAL+X->AAL'] + ("10","011","00","000","000","000000","000","000","000","0000","00000","1111",'1'),-- ['0->[20:AAL]'] + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- 75 ADC ZP,X + ("00","000","00","000","000","000000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->IR', 'PC++'] + ("00","000","00","000","000","001000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->AAL', 'PC++'] + ("00","000","00","000","000","011000","000","000","000","0000","00000","0000",'0'),-- ['AAL+X->AAL'] + ("01","011","00","101","000","000000","000","000","001","0001","00100","0000",'1'),-- ['ALU(A,[20:AAL])->A', 'Flags'] + ("10","000","00","000","000","000000","000","000","000","0000","00000","0000",'0'),-- [] + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- 76 ROR ZP,X + ("00","000","00","000","000","000000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->IR', 'PC++'] + ("00","000","00","000","000","001000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->AAL', 'PC++'] + ("00","000","00","000","000","011000","000","000","000","0000","00000","0000",'0'),-- ['AAL+X->AAL'] + ("00","011","00","101","001","000000","000","000","000","0000","01011","0000",'1'),-- ['ALU([20:AAL])->T', 'Flags'] + ("00","000","00","000","000","000000","000","000","000","0000","00000","0000",'0'),-- [] + ("10","011","00","000","000","000000","000","000","000","0000","00000","0100",'1'),-- ['T->[20:AAL]'] + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- 77 RMB7 + ("00","000","00","000","000","000000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->IR', 'PC++'] + ("00","000","00","000","000","001000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->AAL', 'PC++'] + ("00","000","00","000","000","000000","000","000","000","0000","00000","0000",'0'),-- [] + ("00","011","00","000","001","000000","000","000","000","1100","01101","0000",'1'),-- ['ALU([20:AAL])->T'] + ("00","000","00","000","000","000000","000","000","000","0000","00000","0000",'0'),-- [] + ("00","000","00","000","000","000000","000","000","000","0000","00000","0000",'0'),-- [] + ("10","011","00","000","000","000000","000","000","000","0000","00000","0100",'1'),-- ['T->[20:AAL]'] + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- 78 SEI + ("00","000","00","000","000","000000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->IR', 'PC++'] + ("10","000","00","100","000","000000","000","000","000","0000","00000","0000",'1'),-- ['Flags'] + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- 79 ADC ABS,Y/ABS,Y,(X) + ("00","000","00","000","000","000000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->IR', 'PC++'] + ("00","000","00","000","000","001000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->AAL', 'PC++'] + ("00","000","00","000","000","100001","001","000","000","0000","00000","0000",'1'),-- ['[PC]->AAH', 'PC++', 'AAL+Y->AAL'] + ("00","000","00","000","000","000011","000","000","000","0000","00000","0000",'0'),-- ['AAH+AALCarry->AAH'] + ("01","001","00","101","000","000000","000","000","001","0001","00100","0000",'1'),-- ['ALU(A,[AA])->A', 'Flags'] + ("10","000","00","000","000","000000","000","000","000","0000","00000","0000",'0'),-- [] + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- 7A PLY + ("00","000","00","000","000","000000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->IR', 'PC++'] + ("00","000","00","000","000","000000","000","000","000","0000","00000","0000",'0'),-- [] + ("00","000","00","000","000","000000","000","010","000","0000","00000","0000",'0'),-- ['SP++'] + ("10","010","00","001","000","000000","000","000","100","0000","00000","0000",'1'),-- ['ALU([21:SP])->Y'] + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- 7B + ("00","000","00","000","000","000000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->IR', 'PC++'] + ("10","000","00","000","000","000000","000","000","000","0000","00000","0000",'0'),-- [] + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- 7C JMP (ABS,X) + ("00","000","00","000","000","000000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->IR', 'PC++'] + ("00","000","00","000","000","001000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->AAL', 'PC++'] + ("00","000","00","000","000","011001","001","000","000","0000","00000","0000",'1'),-- ['[PC]->AAH', 'PC++', 'AAL+X->AAL'] + ("00","000","00","000","000","000011","000","000","000","0000","00000","0000",'0'),-- ['AAH+AALCarry->AAH'] + ("00","001","00","000","000","010000","010","000","000","0000","00000","0000",'1'),-- ['[AA]->PCL', 'AAL+1->AAL'] + ("00","000","00","000","000","000011","000","000","000","0000","00000","0000",'0'),-- ['AAH+AALCarry->AAH'] + ("10","001","00","000","000","000000","011","000","000","0000","00000","0000",'1'),-- ['[AA]->PCH'] + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- 7D ADC ABS,X + ("00","000","00","000","000","000000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->IR', 'PC++'] + ("00","000","00","000","000","001000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->AAL', 'PC++'] + ("00","000","00","000","000","011001","001","000","000","0000","00000","0000",'1'),-- ['[PC]->AAH', 'PC++', 'AAL+X->AAL'] + ("00","000","00","000","000","000011","000","000","000","0000","00000","0000",'0'),-- ['AAH+AALCarry->AAH'] + ("01","001","00","101","000","000000","000","000","001","0001","00100","0000",'1'),-- ['ALU(A,[AA])->A', 'Flags'] + ("10","000","00","000","000","000000","000","000","000","0000","00000","0000",'0'),-- [] + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- 7E ROR ABS,X + ("00","000","00","000","000","000000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->IR', 'PC++'] + ("00","000","00","000","000","001000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->AAL', 'PC++'] + ("00","000","00","000","000","011001","001","000","000","0000","00000","0000",'1'),-- ['[PC]->AAH', 'PC++', 'AAL+X->AAL'] + ("00","000","00","000","000","000011","000","000","000","0000","00000","0000",'0'),-- ['AAH+AALCarry->AAH'] + ("00","001","00","101","001","000000","000","000","000","0000","01011","0000",'1'),-- ['ALU([AA])->T', 'Flags'] + ("00","000","00","000","000","000000","000","000","000","0000","00000","0000",'0'),-- [] + ("10","001","00","000","000","000000","000","000","000","0000","00000","0100",'1'),-- ['T->[AA]'] + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- 7F BBR7 + ("00","000","00","000","000","000000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->IR', 'PC++'] + ("00","000","00","000","000","001000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->AAL', 'PC++'] + ("00","000","00","000","000","000000","000","000","000","0000","00000","0000",'0'),-- [] + ("00","000","00","000","000","000000","000","000","000","0000","00000","0000",'0'),-- [] + ("00","011","00","000","000","000000","000","000","000","0000","00000","0000",'1'),-- ['[20:AAL]->DR'] + ("10","000","00","000","000","001000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->AAL', 'PC++'] + ("00","000","00","000","000","000000","100","000","000","0000","00000","0000",'1'),-- ['PC+AAL->PC'] + ("10","000","00","000","000","000000","000","000","000","0000","00000","0000",'0'),-- [] + -- 80 BRA + ("00","000","00","000","000","000000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->IR', 'PC++'] + ("00","000","00","000","000","001000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->AAL', 'PC++'] + ("00","000","00","000","000","000000","000","000","000","0000","00000","0000",'0'),-- [] + ("10","000","00","000","000","000000","100","000","000","0000","00000","0000",'0'),-- ['PC+AAL->PC'] + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- 81 STA (ZP,X) + ("00","000","00","000","000","000000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->IR', 'PC++'] + ("00","000","00","000","000","001000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->AAL', 'PC++'] + ("00","000","00","000","000","011000","000","000","000","0000","00000","0000",'0'),-- ['AAL+X->AAL'] + ("00","011","00","000","000","010000","000","000","000","0000","00000","0000",'1'),-- ['[20:AAL]->DR', 'AAL+1->AAL'] + ("00","011","00","000","000","101001","000","000","000","0000","00000","0000",'1'),-- ['[20:AAL]->AAH', 'DR->AAL'] + ("00","000","00","000","000","000000","000","000","000","0000","00000","0000",'0'),-- [] + ("10","001","00","000","000","000000","000","000","000","0000","00000","0001",'1'),-- ['A->[AA]'] + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- 82 CLX + ("00","000","00","000","000","000000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->IR', 'PC++'] + ("10","000","00","000","000","000000","000","000","010","1111","00000","0000",'1'),-- ['0->X'] + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- 83 TST IMM,ZP + ("00","000","00","000","000","000000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->IR', 'PC++'] + ("00","000","00","000","001","000000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->T', 'PC++'] + ("00","000","00","000","000","001000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->AAL', 'PC++'] + ("00","000","00","000","000","000000","000","000","000","0000","00000","0000",'0'),-- [] + ("00","000","00","000","000","000000","000","000","000","0000","00000","0000",'0'),-- [] + ("00","000","00","000","000","000000","000","000","000","0000","00000","0000",'0'),-- [] + ("10","011","00","101","000","000000","000","000","000","0101","01100","0000",'1'),-- ['ALU(T,[20:AAL])', 'Flags'] + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- 84 STY ZP + ("00","000","00","000","000","000000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->IR', 'PC++'] + ("00","000","00","000","000","001000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->AAL', 'PC++'] + ("00","000","00","000","000","000000","000","000","000","0000","00000","0000",'0'),-- [] + ("10","011","00","000","000","000000","000","000","000","0000","00000","0011",'1'),-- ['Y->[20:AAL]'] + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- 85 STA ZP + ("00","000","00","000","000","000000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->IR', 'PC++'] + ("00","000","00","000","000","001000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->AAL', 'PC++'] + ("00","000","00","000","000","000000","000","000","000","0000","00000","0000",'0'),-- [] + ("10","011","00","000","000","000000","000","000","000","0000","00000","0001",'1'),-- ['A->[20:AAL]'] + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- 86 STX ZP + ("00","000","00","000","000","000000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->IR', 'PC++'] + ("00","000","00","000","000","001000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->AAL', 'PC++'] + ("00","000","00","000","000","000000","000","000","000","0000","00000","0000",'0'),-- [] + ("10","011","00","000","000","000000","000","000","000","0000","00000","0010",'1'),-- ['X->[20:AAL]'] + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- 87 SMB0 + ("00","000","00","000","000","000000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->IR', 'PC++'] + ("00","000","00","000","000","001000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->AAL', 'PC++'] + ("00","000","00","000","000","000000","000","000","000","0000","00000","0000",'0'),-- [] + ("00","011","00","000","001","000000","000","000","000","1100","01110","0000",'1'),-- ['ALU([20:AAL])->T'] + ("00","000","00","000","000","000000","000","000","000","0000","00000","0000",'0'),-- [] + ("00","000","00","000","000","000000","000","000","000","0000","00000","0000",'0'),-- [] + ("10","011","00","000","000","000000","000","000","000","0000","00000","0100",'1'),-- ['T->[20:AAL]'] + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- 88 DEY + ("00","000","00","000","000","000000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->IR', 'PC++'] + ("10","000","00","001","000","000000","000","000","100","0011","00110","0000",'1'),-- ['ALU(Y)->Y', 'Flags'] + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- 89 BIT IMM + ("00","000","00","000","000","000000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->IR', 'PC++'] + ("10","000","00","101","000","000000","001","000","000","0001","01100","0000",'1'),-- ['ALU(A,[PC])', 'PC++', 'Flags'] + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- 8A TXA + ("00","000","00","000","000","000000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->IR', 'PC++'] + ("10","000","00","001","000","000000","000","000","001","0010","00000","0000",'1'),-- ['ALU(X)->A'] + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- 8B + ("00","000","00","000","000","000000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->IR', 'PC++'] + ("10","000","00","000","000","000000","000","000","000","0000","00000","0000",'0'),-- [] + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- 8C STY ABS + ("00","000","00","000","000","000000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->IR', 'PC++'] + ("00","000","00","000","000","001000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->AAL', 'PC++'] + ("00","000","00","000","000","000001","001","000","000","0000","00000","0000",'1'),-- ['[PC]->AAH', 'PC++'] + ("00","000","00","000","000","000000","000","000","000","0000","00000","0000",'0'),-- [] + ("10","001","00","000","000","000000","000","000","000","0000","00000","0011",'1'),-- ['Y->[AA]'] + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- 8D STA ABS + ("00","000","00","000","000","000000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->IR', 'PC++'] + ("00","000","00","000","000","001000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->AAL', 'PC++'] + ("00","000","00","000","000","000001","001","000","000","0000","00000","0000",'1'),-- ['[PC]->AAH', 'PC++'] + ("00","000","00","000","000","000000","000","000","000","0000","00000","0000",'0'),-- [] + ("10","001","00","000","000","000000","000","000","000","0000","00000","0001",'1'),-- ['A->[AA]'] + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- 8E STX ABS + ("00","000","00","000","000","000000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->IR', 'PC++'] + ("00","000","00","000","000","001000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->AAL', 'PC++'] + ("00","000","00","000","000","000001","001","000","000","0000","00000","0000",'1'),-- ['[PC]->AAH', 'PC++'] + ("00","000","00","000","000","000000","000","000","000","0000","00000","0000",'0'),-- [] + ("10","001","00","000","000","000000","000","000","000","0000","00000","0010",'1'),-- ['X->[AA]'] + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- 8F BBS0 + ("00","000","00","000","000","000000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->IR', 'PC++'] + ("00","000","00","000","000","001000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->AAL', 'PC++'] + ("00","000","00","000","000","000000","000","000","000","0000","00000","0000",'0'),-- [] + ("00","000","00","000","000","000000","000","000","000","0000","00000","0000",'0'),-- [] + ("00","011","00","000","000","000000","000","000","000","0000","00000","0000",'1'),-- ['[20:AAL]->DR'] + ("10","000","00","000","000","001000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->AAL', 'PC++'] + ("00","000","00","000","000","000000","100","000","000","0000","00000","0000",'0'),-- ['PC+AAL->PC'] + ("10","000","00","000","000","000000","000","000","000","0000","00000","0000",'0'),-- [] + -- 90 BCC + ("00","000","00","000","000","000000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->IR', 'PC++'] + ("10","000","00","000","000","001000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->AAL', 'PC++'] + ("00","000","00","000","000","000000","000","000","000","0000","00000","0000",'1'),-- [] + ("10","000","00","000","000","000000","100","000","000","0000","00000","0000",'0'),-- ['PC+AAL->PC'] + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- 91 STA (ZP),Y + ("00","000","00","000","000","000000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->IR', 'PC++'] + ("00","000","00","000","000","001000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->AAL', 'PC++'] + ("00","000","00","000","000","000000","000","000","000","0000","00000","0000",'0'),-- [] + ("00","011","00","000","000","010000","000","000","000","0000","00000","0000",'1'),-- ['[20:AAL]->DR', 'AAL+1->AAL'] + ("00","011","00","000","000","110001","000","000","000","0000","00000","0000",'1'),-- ['[20:AAL]->AAH', 'DR+Y->AAL'] + ("00","000","00","000","000","000011","000","000","000","0000","00000","0000",'0'),-- ['AAH+AALCarry->AAH'] + ("10","001","00","000","000","000000","000","000","000","0000","00000","0001",'1'),-- ['A->[AA]'] + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- 92 STA (ZP) + ("00","000","00","000","000","000000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->IR', 'PC++'] + ("00","000","00","000","000","001000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->AAL', 'PC++'] + ("00","000","00","000","000","000000","000","000","000","0000","00000","0000",'0'),-- [] + ("00","011","00","000","000","010000","000","000","000","0000","00000","0000",'1'),-- ['[20:AAL]->DR', 'AAL+1->AAL'] + ("00","011","00","000","000","101001","000","000","000","0000","00000","0000",'1'),-- ['[20:AAL]->AAH', 'DR->AAL'] + ("00","000","00","000","000","000000","000","000","000","0000","00000","0000",'0'),-- [] + ("10","001","00","000","000","000000","000","000","000","0000","00000","0001",'1'),-- ['A->[AA]'] + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- 93 TST IMM,ABS + ("00","000","00","000","000","000000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->IR', 'PC++'] + ("00","000","00","000","001","000000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->T', 'PC++'] + ("00","000","00","000","000","001000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->AAL', 'PC++'] + ("00","000","00","000","000","000001","001","000","000","0000","00000","0000",'1'),-- ['[PC]->AAH', 'PC++'] + ("00","000","00","000","000","000000","000","000","000","0000","00000","0000",'0'),-- [] + ("00","000","00","000","000","000000","000","000","000","0000","00000","0000",'0'),-- [] + ("00","000","00","000","000","000000","000","000","000","0000","00000","0000",'0'),-- [] + ("10","001","00","101","000","000000","000","000","000","0101","01100","0000",'1'),-- ['ALU(T,[AA])', 'Flags'] + -- 94 STY ZP, X + ("00","000","00","000","000","000000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->IR', 'PC++'] + ("00","000","00","000","000","001000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->AAL', 'PC++'] + ("00","000","00","000","000","011000","000","000","000","0000","00000","0000",'0'),-- ['AAL+X->AAL'] + ("10","011","00","000","000","000000","000","000","000","0000","00000","0011",'1'),-- ['Y->[20:AAL]'] + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- 95 STA ZP,X + ("00","000","00","000","000","000000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->IR', 'PC++'] + ("00","000","00","000","000","001000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->AAL', 'PC++'] + ("00","000","00","000","000","011000","000","000","000","0000","00000","0000",'0'),-- ['AAL+X->AAL'] + ("10","011","00","000","000","000000","000","000","000","0000","00000","0001",'1'),-- ['A->[20:AAL]'] + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- 96 STX ZP,Y + ("00","000","00","000","000","000000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->IR', 'PC++'] + ("00","000","00","000","000","001000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->AAL', 'PC++'] + ("00","000","00","000","000","100000","000","000","000","0000","00000","0000",'0'),-- ['AAL+Y->AAL'] + ("10","011","00","000","000","000000","000","000","000","0000","00000","0010",'1'),-- ['X->[20:AAL]'] + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- 97 SMB1 + ("00","000","00","000","000","000000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->IR', 'PC++'] + ("00","000","00","000","000","001000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->AAL', 'PC++'] + ("00","000","00","000","000","000000","000","000","000","0000","00000","0000",'0'),-- [] + ("00","011","00","000","001","000000","000","000","000","1100","01110","0000",'1'),-- ['ALU([20:AAL])->T'] + ("00","000","00","000","000","000000","000","000","000","0000","00000","0000",'0'),-- [] + ("00","000","00","000","000","000000","000","000","000","0000","00000","0000",'0'),-- [] + ("10","011","00","000","000","000000","000","000","000","0000","00000","0100",'1'),-- ['T->[20:AAL]'] + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- 98 TYA + ("00","000","00","000","000","000000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->IR', 'PC++'] + ("10","000","00","001","000","000000","000","000","001","0011","00000","0000",'1'),-- ['ALU(Y)->A'] + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- 99 STA ABS,Y + ("00","000","00","000","000","000000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->IR', 'PC++'] + ("00","000","00","000","000","001000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->AAL', 'PC++'] + ("00","000","00","000","000","100001","001","000","000","0000","00000","0000",'1'),-- ['[PC]->AAH', 'PC++', 'AAL+Y->AAL'] + ("00","000","00","000","000","000011","000","000","000","0000","00000","0000",'0'),-- ['AAH+AALCarry->AAH'] + ("10","001","00","000","000","000000","000","000","000","0000","00000","0001",'1'),-- ['A->[AA]'] + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- 9A TXS + ("00","000","00","000","000","000000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->IR', 'PC++'] + ("10","000","00","000","000","000000","000","001","000","0010","00000","0000",'1'),-- ['X->SP'] + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- 9B + ("00","000","00","000","000","000000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->IR', 'PC++'] + ("10","000","00","000","000","000000","000","000","000","0000","00000","0000",'0'),-- [] + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- 9C STZ ABS + ("00","000","00","000","000","000000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->IR', 'PC++'] + ("00","000","00","000","000","001000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->AAL', 'PC++'] + ("00","000","00","000","000","000001","001","000","000","0000","00000","0000",'1'),-- ['[PC]->AAH', 'PC++'] + ("00","000","00","000","000","000000","000","000","000","0000","00000","0000",'0'),-- [] + ("10","001","00","000","000","000000","000","000","000","0000","00000","1111",'1'),-- ['0->[AA]'] + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- 9D STA ABS,X + ("00","000","00","000","000","000000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->IR', 'PC++'] + ("00","000","00","000","000","001000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->AAL', 'PC++'] + ("00","000","00","000","000","011001","001","000","000","0000","00000","0000",'1'),-- ['[PC]->AAH', 'PC++', 'AAL+X->AAL'] + ("00","000","00","000","000","000011","000","000","000","0000","00000","0000",'0'),-- ['AAH+AALCarry->AAH'] + ("10","001","00","000","000","000000","000","000","000","0000","00000","0001",'1'),-- ['A->[AA]'] + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- 9E STZ ABS,X + ("00","000","00","000","000","000000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->IR', 'PC++'] + ("00","000","00","000","000","001000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->AAL', 'PC++'] + ("00","000","00","000","000","011001","001","000","000","0000","00000","0000",'1'),-- ['[PC]->AAH', 'PC++', 'AAL+X->AAL'] + ("00","000","00","000","000","000011","000","000","000","0000","00000","0000",'0'),-- ['AAH+AALCarry->AAH'] + ("10","001","00","000","000","000000","000","000","000","0000","00000","1111",'1'),-- ['0->[AA]'] + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- 9F BBS1 + ("00","000","00","000","000","000000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->IR', 'PC++'] + ("00","000","00","000","000","001000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->AAL', 'PC++'] + ("00","000","00","000","000","000000","000","000","000","0000","00000","0000",'0'),-- [] + ("00","000","00","000","000","000000","000","000","000","0000","00000","0000",'0'),-- [] + ("00","011","00","000","000","000000","000","000","000","0000","00000","0000",'1'),-- ['[20:AAL]->DR'] + ("10","000","00","000","000","001000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->AAL', 'PC++'] + ("00","000","00","000","000","000000","100","000","000","0000","00000","0000",'0'),-- ['PC+AAL->PC'] + ("10","000","00","000","000","000000","000","000","000","0000","00000","0000",'0'),-- [] + -- A0 LDY IMM + ("00","000","00","000","000","000000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->IR', 'PC++'] + ("10","000","00","001","000","000000","001","000","100","0000","00000","0000",'1'),-- ['ALU([PC])->Y', 'PC++', 'Flags'] + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- A1 LDA (ZP,X) + ("00","000","00","000","000","000000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->IR', 'PC++'] + ("00","000","00","000","000","001000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->AAL', 'PC++'] + ("00","000","00","000","000","011000","000","000","000","0000","00000","0000",'0'),-- ['AAL+X->AAL'] + ("00","011","00","000","000","010000","000","000","000","0000","00000","0000",'1'),-- ['[20:AAL]->DR', 'AAL+1->AAL'] + ("00","011","00","000","000","101001","000","000","000","0000","00000","0000",'1'),-- ['[20:AAL]->AAH', 'DR->AAL'] + ("00","000","00","000","000","000000","000","000","000","0000","00000","0000",'0'),-- [] + ("10","001","00","001","000","000000","000","000","001","0000","00000","0000",'1'),-- ['ALU([AA])->A', 'Flags'] + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- A2 LDX IMM + ("00","000","00","000","000","000000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->IR', 'PC++'] + ("10","000","00","001","000","000000","001","000","010","0000","00000","0000",'1'),-- ['ALU([PC])->X', 'PC++', 'Flags'] + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- A3 TST IMM,ZP,X + ("00","000","00","000","000","000000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->IR', 'PC++'] + ("00","000","00","000","001","000000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->T', 'PC++'] + ("00","000","00","000","000","001000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->AAL', 'PC++'] + ("00","000","00","000","000","011000","000","000","000","0000","00000","0000",'0'),-- ['AAL+X->AAL'] + ("00","000","00","000","000","000000","000","000","000","0000","00000","0000",'0'),-- [] + ("00","000","00","000","000","000000","000","000","000","0000","00000","0000",'0'),-- [] + ("10","011","00","101","000","000000","000","000","000","0101","01100","0000",'1'),-- ['ALU(T,[20:AAL])', 'Flags'] + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- A4 LDY ZP + ("00","000","00","000","000","000000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->IR', 'PC++'] + ("00","000","00","000","000","001000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->AAL', 'PC++'] + ("00","000","00","000","000","000000","000","000","000","0000","00000","0000",'0'),-- [] + ("10","011","00","001","000","000000","000","000","100","0000","00000","0000",'1'),-- ['ALU([20:AAL])->Y', 'Flags'] + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- A5 LDA ZP + ("00","000","00","000","000","000000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->IR', 'PC++'] + ("00","000","00","000","000","001000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->AAL', 'PC++'] + ("00","000","00","000","000","000000","000","000","000","0000","00000","0000",'0'),-- [] + ("10","011","00","001","000","000000","000","000","001","0000","00000","0000",'1'),-- ['ALU([20:AAL])->A', 'Flags'] + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- A6 LDX ZP + ("00","000","00","000","000","000000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->IR', 'PC++'] + ("00","000","00","000","000","001000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->AAL', 'PC++'] + ("00","000","00","000","000","000000","000","000","000","0000","00000","0000",'0'),-- [] + ("10","011","00","001","000","000000","000","000","010","0000","00000","0000",'1'),-- ['ALU([20:AAL])->X', 'Flags'] + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- A7 SMB2 + ("00","000","00","000","000","000000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->IR', 'PC++'] + ("00","000","00","000","000","001000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->AAL', 'PC++'] + ("00","000","00","000","000","000000","000","000","000","0000","00000","0000",'0'),-- [] + ("00","011","00","000","001","000000","000","000","000","1100","01110","0000",'1'),-- ['ALU([20:AAL])->T'] + ("00","000","00","000","000","000000","000","000","000","0000","00000","0000",'0'),-- [] + ("00","000","00","000","000","000000","000","000","000","0000","00000","0000",'0'),-- [] + ("10","011","00","000","000","000000","000","000","000","0000","00000","0100",'1'),-- ['T->[20:AAL]'] + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- A8 TAY + ("00","000","00","000","000","000000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->IR', 'PC++'] + ("10","000","00","001","000","000000","000","000","100","0001","00000","0000",'1'),-- ['ALU(A)->Y', 'Flags'] + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- A9 LDA IMM + ("00","000","00","000","000","000000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->IR', 'PC++'] + ("10","000","00","001","000","000000","001","000","001","0000","00000","0000",'1'),-- ['ALU([PC])->A', 'PC++', 'Flags'] + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- AA TAX + ("00","000","00","000","000","000000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->IR', 'PC++'] + ("10","000","00","001","000","000000","000","000","010","0001","00000","0000",'1'),-- ['ALU(A)->X', 'Flags'] + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- AB + ("00","000","00","000","000","000000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->IR', 'PC++'] + ("10","000","00","000","000","000000","000","000","000","0000","00000","0000",'0'),-- [] + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- AC LDY ABS + ("00","000","00","000","000","000000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->IR', 'PC++'] + ("00","000","00","000","000","001000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->AAL', 'PC++'] + ("00","000","00","000","000","000001","001","000","000","0000","00000","0000",'1'),-- ['[PC]->AAH', 'PC++'] + ("00","000","00","000","000","000000","000","000","000","0000","00000","0000",'0'),-- [] + ("10","001","00","001","000","000000","000","000","100","0000","00000","0000",'1'),-- ['ALU([AA])->Y', 'Flags'] + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- AD LDA ABS + ("00","000","00","000","000","000000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->IR', 'PC++'] + ("00","000","00","000","000","001000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->AAL', 'PC++'] + ("00","000","00","000","000","000001","001","000","000","0000","00000","0000",'1'),-- ['[PC]->AAH', 'PC++'] + ("00","000","00","000","000","000000","000","000","000","0000","00000","0000",'0'),-- [] + ("10","001","00","001","000","000000","000","000","001","0000","00000","0000",'1'),-- ['ALU([AA])->A', 'Flags'] + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- AE LDX ABS + ("00","000","00","000","000","000000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->IR', 'PC++'] + ("00","000","00","000","000","001000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->AAL', 'PC++'] + ("00","000","00","000","000","000001","001","000","000","0000","00000","0000",'1'),-- ['[PC]->AAH', 'PC++'] + ("00","000","00","000","000","000000","000","000","000","0000","00000","0000",'0'),-- [] + ("10","001","00","001","000","000000","000","000","010","0000","00000","0000",'1'),-- ['ALU([AA])->X', 'Flags'] + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- AF BBS2 + ("00","000","00","000","000","000000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->IR', 'PC++'] + ("00","000","00","000","000","001000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->AAL', 'PC++'] + ("00","000","00","000","000","000000","000","000","000","0000","00000","0000",'0'),-- [] + ("00","000","00","000","000","000000","000","000","000","0000","00000","0000",'0'),-- [] + ("00","011","00","000","000","000000","000","000","000","0000","00000","0000",'1'),-- ['[20:AAL]->DR'] + ("10","000","00","000","000","001000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->AAL', 'PC++'] + ("00","000","00","000","000","000000","100","000","000","0000","00000","0000",'0'),-- ['PC+AAL->PC'] + ("10","000","00","000","000","000000","000","000","000","0000","00000","0000",'0'),-- [] + -- B0 BCS + ("00","000","00","000","000","000000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->IR', 'PC++'] + ("10","000","00","000","000","001000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->AAL', 'PC++'] + ("00","000","00","000","000","000000","000","000","000","0000","00000","0000",'1'),-- [] + ("10","000","00","000","000","000000","100","000","000","0000","00000","0000",'0'),-- ['PC+AAL->PC'] + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- B1 LDA (ZP),Y + ("00","000","00","000","000","000000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->IR', 'PC++'] + ("00","000","00","000","000","001000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->AAL', 'PC++'] + ("00","000","00","000","000","000000","000","000","000","0000","00000","0000",'0'),-- [] + ("00","011","00","000","000","010000","000","000","000","0000","00000","0000",'1'),-- ['[20:AAL]->DR', 'AAL+1->AAL'] + ("00","011","00","000","000","110001","000","000","000","0000","00000","0000",'1'),-- ['[20:AAL]->AAH', 'DR+Y->AAL'] + ("00","000","00","000","000","000011","000","000","000","0000","00000","0000",'0'),-- ['AAH+AALCarry->AAH'] + ("10","001","00","001","000","000000","000","000","001","0000","00000","0000",'1'),-- ['ALU([AA])->A', 'Flags'] + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- B2 LDA (ZP) + ("00","000","00","000","000","000000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->IR', 'PC++'] + ("00","000","00","000","000","001000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->AAL', 'PC++'] + ("00","000","00","000","000","000000","000","000","000","0000","00000","0000",'0'),-- [] + ("00","011","00","000","000","010000","000","000","000","0000","00000","0000",'1'),-- ['[20:AAL]->DR', 'AAL+1->AAL'] + ("00","011","00","000","000","101001","000","000","000","0000","00000","0000",'1'),-- ['[20:AAL]->AAH', 'DR->AAL'] + ("00","000","00","000","000","000000","000","000","000","0000","00000","0000",'0'),-- [] + ("10","001","00","001","000","000000","000","000","001","0000","00000","0000",'1'),-- ['ALU([AA])->A', 'Flags'] + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- B3 TST IMM,ABS,X + ("00","000","00","000","000","000000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->IR', 'PC++'] + ("00","000","00","000","001","000000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->T', 'PC++'] + ("00","000","00","000","000","001000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->AAL', 'PC++'] + ("00","000","00","000","000","011001","001","000","000","0000","00000","0000",'1'),-- ['[PC]->AAH', 'PC++', 'AAL+X->AAL'] + ("00","000","00","000","000","000011","000","000","000","0000","00000","0000",'0'),-- ['AAH+AALCarry->AAH'] + ("00","000","00","000","000","000000","000","000","000","0000","00000","0000",'0'),-- [] + ("00","000","00","000","000","000000","000","000","000","0000","00000","0000",'0'),-- [] + ("10","001","00","101","000","000000","000","000","000","0101","01100","0000",'1'),-- ['ALU(T,[AA])', 'Flags'] + -- B4 LDY ZP, X + ("00","000","00","000","000","000000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->IR', 'PC++'] + ("00","000","00","000","000","001000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->AAL', 'PC++'] + ("00","000","00","000","000","011000","000","000","000","0000","00000","0000",'0'),-- ['AAL+X->AAL'] + ("10","011","00","001","000","000000","000","000","100","0000","00000","0000",'1'),-- ['ALU([20:AAL])->Y', 'Flags'] + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- B5 LDA ZP, X + ("00","000","00","000","000","000000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->IR', 'PC++'] + ("00","000","00","000","000","001000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->AAL', 'PC++'] + ("00","000","00","000","000","011000","000","000","000","0000","00000","0000",'0'),-- ['AAL+X->AAL'] + ("10","011","00","001","000","000000","000","000","001","0000","00000","0000",'1'),-- ['ALU([20:AAL])->A', 'Flags'] + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- B6 LDX ZP, Y + ("00","000","00","000","000","000000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->IR', 'PC++'] + ("00","000","00","000","000","001000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->AAL', 'PC++'] + ("00","000","00","000","000","100000","000","000","000","0000","00000","0000",'0'),-- ['AAL+Y->AAL'] + ("10","011","00","001","000","000000","000","000","010","0000","00000","0000",'1'),-- ['ALU([20:AAL])->X', 'Flags'] + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- B7 SMB3 + ("00","000","00","000","000","000000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->IR', 'PC++'] + ("00","000","00","000","000","001000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->AAL', 'PC++'] + ("00","000","00","000","000","000000","000","000","000","0000","00000","0000",'0'),-- [] + ("00","011","00","000","001","000000","000","000","000","1100","01110","0000",'1'),-- ['ALU([20:AAL])->T'] + ("00","000","00","000","000","000000","000","000","000","0000","00000","0000",'0'),-- [] + ("00","000","00","000","000","000000","000","000","000","0000","00000","0000",'0'),-- [] + ("10","011","00","000","000","000000","000","000","000","0000","00000","0100",'1'),-- ['T->[20:AAL]'] + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- B8 CLV + ("00","000","00","000","000","000000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->IR', 'PC++'] + ("10","000","00","100","000","000000","000","000","000","0000","00000","0000",'1'),-- ['Flags'] + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- B9 LDA ABS,Y + ("00","000","00","000","000","000000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->IR', 'PC++'] + ("00","000","00","000","000","001000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->AAL', 'PC++'] + ("00","000","00","000","000","100001","001","000","000","0000","00000","0000",'1'),-- ['[PC]->AAH', 'PC++', 'AAL+Y->AAL'] + ("00","000","00","000","000","000011","000","000","000","0000","00000","0000",'0'),-- ['AAH+AALCarry->AAH'] + ("10","001","00","001","000","000000","000","000","001","0000","00000","0000",'1'),-- ['ALU([AA])->A', 'Flags'] + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- BA TSX + ("00","000","00","000","000","000000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->IR', 'PC++'] + ("10","000","00","001","000","000000","000","000","010","0100","00000","0000",'1'),-- ['ALU(SP)->X'] + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- BB + ("00","000","00","000","000","000000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->IR', 'PC++'] + ("10","000","00","000","000","000000","000","000","000","0000","00000","0000",'0'),-- [] + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- BC LDY ABS,X + ("00","000","00","000","000","000000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->IR', 'PC++'] + ("00","000","00","000","000","001000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->AAL', 'PC++'] + ("00","000","00","000","000","011001","001","000","000","0000","00000","0000",'1'),-- ['[PC]->AAH', 'PC++', 'AAL+X/Y->AAL'] + ("00","000","00","000","000","000011","000","000","000","0000","00000","0000",'0'),-- ['AAH+AALCarry->AAH'] + ("10","001","00","001","000","000000","000","000","100","0000","00000","0000",'1'),-- ['ALU([AA])->Y', 'Flags'] + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- BD LDA ABS,X + ("00","000","00","000","000","000000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->IR', 'PC++'] + ("00","000","00","000","000","001000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->AAL', 'PC++'] + ("00","000","00","000","000","011001","001","000","000","0000","00000","0000",'1'),-- ['[PC]->AAH', 'PC++', 'AAL+X->AAL'] + ("00","000","00","000","000","000011","000","000","000","0000","00000","0000",'0'),-- ['AAH+AALCarry->AAH'] + ("10","001","00","001","000","000000","000","000","001","0000","00000","0000",'1'),-- ['ALU([AA])->A', 'Flags'] + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- BE LDX ABS,Y + ("00","000","00","000","000","000000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->IR', 'PC++'] + ("00","000","00","000","000","001000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->AAL', 'PC++'] + ("00","000","00","000","000","100001","001","000","000","0000","00000","0000",'1'),-- ['[PC]->AAH', 'PC++', 'AAL+X/Y->AAL'] + ("00","000","00","000","000","000011","000","000","000","0000","00000","0000",'0'),-- ['AAH+AALCarry->AAH'] + ("10","001","00","001","000","000000","000","000","010","0000","00000","0000",'1'),-- ['ALU([AA])->X', 'Flags'] + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- BF BBS3 + ("00","000","00","000","000","000000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->IR', 'PC++'] + ("00","000","00","000","000","001000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->AAL', 'PC++'] + ("00","000","00","000","000","000000","000","000","000","0000","00000","0000",'0'),-- [] + ("00","000","00","000","000","000000","000","000","000","0000","00000","0000",'0'),-- [] + ("00","011","00","000","000","000000","000","000","000","0000","00000","0000",'1'),-- ['[20:AAL]->DR'] + ("10","000","00","000","000","001000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->AAL', 'PC++'] + ("00","000","00","000","000","000000","100","000","000","0000","00000","0000",'0'),-- ['PC+AAL->PC'] + ("10","000","00","000","000","000000","000","000","000","0000","00000","0000",'0'),-- [] + -- C0 CPY IMM + ("00","000","00","000","000","000000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->IR', 'PC++'] + ("10","000","00","101","000","000000","001","000","000","0011","01111","0000",'1'),-- ['ALU(Y,[PC])', 'PC++', 'Flags'] + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- C1 CMP (ZP,X) + ("00","000","00","000","000","000000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->IR', 'PC++'] + ("00","000","00","000","000","001000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->AAL', 'PC++'] + ("00","000","00","000","000","011000","000","000","000","0000","00000","0000",'0'),-- ['AAL+X->AAL'] + ("00","011","00","000","000","010000","000","000","000","0000","00000","0000",'1'),-- ['[20:AAL]->DR', 'AAL+1->AAL'] + ("00","011","00","000","000","101001","000","000","000","0000","00000","0000",'1'),-- ['[20:AAL]->AAH', 'DR->AAL'] + ("00","000","00","000","000","000000","000","000","000","0000","00000","0000",'0'),-- [] + ("10","001","00","101","000","000000","000","000","000","0001","01111","0000",'1'),-- ['ALU(A,[AA])', 'Flags'] + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- C2 CLY + ("00","000","00","000","000","000000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->IR', 'PC++'] + ("10","000","00","000","000","000000","000","000","100","1111","00000","0000",'1'),-- ['0->Y'] + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- C3 TDD + ("00","000","00","000","000","000000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->IR', 'PC++'] + ("00","010","00","000","000","000000","000","011","000","0000","00000","0011",'1'),-- ['Y->[21:SP]', 'SP--'] + ("00","010","00","000","000","000000","000","011","000","0000","00000","0001",'1'),-- ['A->[21:SP]', 'SP--'] + ("00","010","00","000","000","000000","000","000","000","0000","00000","0010",'1'),-- ['X->[21:SP]'] + ("00","000","00","000","000","000000","001","000","010","0000","00000","0000",'1'),-- ['[PC]->X', 'PC++'] + ("00","000","01","000","000","000000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->SH', 'PC++'] + ("00","000","00","000","000","000000","001","000","100","0000","00000","0000",'1'),-- ['[PC]->Y', 'PC++'] + ("00","000","10","000","000","000000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->DH', 'PC++'] + -- C4 CPY ZP + ("00","000","00","000","000","000000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->IR', 'PC++'] + ("00","000","00","000","000","001000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->AAL', 'PC++'] + ("00","000","00","000","000","000000","000","000","000","0000","00000","0000",'0'),-- [] + ("10","011","00","101","000","000000","000","000","000","0011","01111","0000",'1'),-- ['ALU(Y,[20:AAL])', 'Flags'] + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- C5 CMP ZP + ("00","000","00","000","000","000000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->IR', 'PC++'] + ("00","000","00","000","000","001000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->AAL', 'PC++'] + ("00","000","00","000","000","000000","000","000","000","0000","00000","0000",'0'),-- [] + ("10","011","00","101","000","000000","000","000","000","0001","01111","0000",'1'),-- ['ALU(A,[20:AAL])', 'Flags'] + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- C6 DEC ZP + ("00","000","00","000","000","000000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->IR', 'PC++'] + ("00","000","00","000","000","001000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->AAL', 'PC++'] + ("00","000","00","000","000","000000","000","000","000","0000","00000","0000",'0'),-- [] + ("00","011","00","001","001","000000","000","000","000","0000","00110","0000",'1'),-- ['ALU([20:AAL])->T', 'Flags'] + ("00","000","00","000","000","000000","000","000","000","0000","00000","0000",'0'),-- [] + ("10","011","00","000","000","000000","000","000","000","0000","00000","0100",'1'),-- ['T->[20:AAL]'] + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- C7 SMB4 + ("00","000","00","000","000","000000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->IR', 'PC++'] + ("00","000","00","000","000","001000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->AAL', 'PC++'] + ("00","000","00","000","000","000000","000","000","000","0000","00000","0000",'0'),-- [] + ("00","011","00","000","001","000000","000","000","000","1100","01110","0000",'1'),-- ['ALU([20:AAL])->T'] + ("00","000","00","000","000","000000","000","000","000","0000","00000","0000",'0'),-- [] + ("00","000","00","000","000","000000","000","000","000","0000","00000","0000",'0'),-- [] + ("10","011","00","000","000","000000","000","000","000","0000","00000","0100",'1'),-- ['T->[20:AAL]'] + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- C8 INY + ("00","000","00","000","000","000000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->IR', 'PC++'] + ("10","000","00","001","000","000000","000","000","100","0011","00111","0000",'1'),-- ['ALU(Y)->Y', 'Flags'] + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- C9 CMP IMM + ("00","000","00","000","000","000000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->IR', 'PC++'] + ("10","000","00","101","000","000000","001","000","000","0001","01111","0000",'1'),-- ['ALU(A,[PC])', 'PC++', 'Flags'] + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- CA DEX + ("00","000","00","000","000","000000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->IR', 'PC++'] + ("10","000","00","001","000","000000","000","000","010","0010","00110","0000",'1'),-- ['ALU(X)->X', 'Flags'] + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- CB + ("00","000","00","000","000","000000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->IR', 'PC++'] + ("10","000","00","000","000","000000","000","000","000","0000","00000","0000",'0'),-- [] + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- CC CPY ABS + ("00","000","00","000","000","000000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->IR', 'PC++'] + ("00","000","00","000","000","001000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->AAL', 'PC++'] + ("00","000","00","000","000","000001","001","000","000","0000","00000","0000",'1'),-- ['[PC]->AAH', 'PC++'] + ("00","000","00","000","000","000000","000","000","000","0000","00000","0000",'0'),-- [] + ("10","001","00","101","000","000000","000","000","000","0011","01111","0000",'1'),-- ['ALU(Y,[AA])', 'Flags'] + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- CD CMP ABS + ("00","000","00","000","000","000000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->IR', 'PC++'] + ("00","000","00","000","000","001000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->AAL', 'PC++'] + ("00","000","00","000","000","000001","001","000","000","0000","00000","0000",'1'),-- ['[PC]->AAH', 'PC++'] + ("00","000","00","000","000","000000","000","000","000","0000","00000","0000",'0'),-- [] + ("10","001","00","101","000","000000","000","000","000","0001","01111","0000",'1'),-- ['ALU(A,[AA])', 'Flags'] + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- CE DEC ABS + ("00","000","00","000","000","000000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->IR', 'PC++'] + ("00","000","00","000","000","001000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->AAL', 'PC++'] + ("00","000","00","000","000","000001","001","000","000","0000","00000","0000",'1'),-- ['[PC]->AAH', 'PC++'] + ("00","000","00","000","000","000000","000","000","000","0000","00000","0000",'0'),-- [] + ("00","001","00","001","001","000000","000","000","000","0000","00110","0000",'1'),-- ['ALU([AA])->T', 'Flags'] + ("00","000","00","000","000","000000","000","000","000","0000","00000","0000",'0'),-- [] + ("10","001","00","000","000","000000","000","000","000","0000","00000","0100",'1'),-- ['T->[AA]'] + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- CF BBS4 + ("00","000","00","000","000","000000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->IR', 'PC++'] + ("00","000","00","000","000","001000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->AAL', 'PC++'] + ("00","000","00","000","000","000000","000","000","000","0000","00000","0000",'0'),-- [] + ("00","000","00","000","000","000000","000","000","000","0000","00000","0000",'0'),-- [] + ("00","011","00","000","000","000000","000","000","000","0000","00000","0000",'1'),-- ['[20:AAL]->DR'] + ("10","000","00","000","000","001000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->AAL', 'PC++'] + ("00","000","00","000","000","000000","100","000","000","0000","00000","0000",'0'),-- ['PC+AAL->PC'] + ("10","000","00","000","000","000000","000","000","000","0000","00000","0000",'0'),-- [] + -- D0 BNE + ("00","000","00","000","000","000000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->IR', 'PC++'] + ("10","000","00","000","000","001000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->AAL', 'PC++'] + ("00","000","00","000","000","000000","000","000","000","0000","00000","0000",'0'),-- [] + ("10","000","00","000","000","000000","100","000","000","0000","00000","0000",'0'),-- ['PC+AAL->PC'] + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- D1 CMP (ZP),Y + ("00","000","00","000","000","000000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->IR', 'PC++'] + ("00","000","00","000","000","001000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->AAL', 'PC++'] + ("00","000","00","000","000","000000","000","000","000","0000","00000","0000",'0'),-- [] + ("00","011","00","000","000","010000","000","000","000","0000","00000","0000",'1'),-- ['[20:AAL]->DR', 'AAL+1->AAL'] + ("00","011","00","000","000","110001","000","000","000","0000","00000","0000",'1'),-- ['[20:AAL]->AAH', 'DR+Y->AAL'] + ("00","000","00","000","000","000011","000","000","000","0000","00000","0000",'0'),-- ['AAH+AALCarry->AAH'] + ("10","001","00","101","000","000000","000","000","000","0001","01111","0000",'1'),-- ['ALU(A,[AA])', 'Flags'] + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- D2 CMP (ZP) + ("00","000","00","000","000","000000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->IR', 'PC++'] + ("00","000","00","000","000","001000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->AAL', 'PC++'] + ("00","000","00","000","000","000000","000","000","000","0000","00000","0000",'0'),-- [] + ("00","011","00","000","000","010000","000","000","000","0000","00000","0000",'1'),-- ['[20:AAL]->DR', 'AAL+1->AAL'] + ("00","011","00","000","000","101001","000","000","000","0000","00000","0000",'1'),-- ['[20:AAL]->AAH', 'DR->AAL'] + ("00","000","00","000","000","000000","000","000","000","0000","00000","0000",'0'),-- [] + ("10","001","00","101","000","000000","000","000","000","0001","01111","0000",'1'),-- ['ALU(A,[AA])', 'Flags'] + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- D3 TIN + ("00","000","00","000","000","000000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->IR', 'PC++'] + ("00","010","00","000","000","000000","000","011","000","0000","00000","0011",'1'),-- ['Y->[21:SP]', 'SP--'] + ("00","010","00","000","000","000000","000","011","000","0000","00000","0001",'1'),-- ['A->[21:SP]', 'SP--'] + ("00","010","00","000","000","000000","000","000","000","0000","00000","0010",'1'),-- ['X->[21:SP]'] + ("00","000","00","000","000","000000","001","000","010","0000","00000","0000",'1'),-- ['[PC]->X', 'PC++'] + ("00","000","01","000","000","000000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->SH', 'PC++'] + ("00","000","00","000","000","000000","001","000","100","0000","00000","0000",'1'),-- ['[PC]->Y', 'PC++'] + ("00","000","10","000","000","000000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->DH', 'PC++'] + -- D4 CSH + ("00","000","00","000","000","000000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->IR', 'PC++'] + ("00","000","00","000","000","000000","000","000","000","0000","00000","0000",'1'),-- [] + ("10","000","00","000","000","000000","000","000","000","0000","00000","0000",'0'),-- [] + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- D5 CMP ZP,X + ("00","000","00","000","000","000000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->IR', 'PC++'] + ("00","000","00","000","000","001000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->AAL', 'PC++'] + ("00","000","00","000","000","011000","000","000","000","0000","00000","0000",'0'),-- ['AAL+X->AAL'] + ("10","011","00","101","000","000000","000","000","000","0001","01111","0000",'1'),-- ['ALU(A,[20:AAL])', 'Flags'] + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- D6 DEC ZP,X + ("00","000","00","000","000","000000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->IR', 'PC++'] + ("00","000","00","000","000","001000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->AAL', 'PC++'] + ("00","000","00","000","000","011000","000","000","000","0000","00000","0000",'0'),-- ['AAL+X->AAL'] + ("00","011","00","001","001","000000","000","000","000","0000","00110","0000",'1'),-- ['ALU([20:AAL])->T', 'Flags'] + ("00","000","00","000","000","000000","000","000","000","0000","00000","0000",'0'),-- [] + ("10","011","00","000","000","000000","000","000","000","0000","00000","0100",'1'),-- ['T->[20:AAL]'] + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- D7 SMB5 + ("00","000","00","000","000","000000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->IR', 'PC++'] + ("00","000","00","000","000","001000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->AAL', 'PC++'] + ("00","000","00","000","000","000000","000","000","000","0000","00000","0000",'0'),-- [] + ("00","011","00","000","001","000000","000","000","000","1100","01110","0000",'1'),-- ['ALU([20:AAL])->T'] + ("00","000","00","000","000","000000","000","000","000","0000","00000","0000",'0'),-- [] + ("00","000","00","000","000","000000","000","000","000","0000","00000","0000",'0'),-- [] + ("10","011","00","000","000","000000","000","000","000","0000","00000","0100",'1'),-- ['T->[20:AAL]'] + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- D8 CLD + ("00","000","00","000","000","000000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->IR', 'PC++'] + ("10","000","00","100","000","000000","000","000","000","0000","00000","0000",'1'),-- ['Flags'] + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- D9 CMP ABS,Y + ("00","000","00","000","000","000000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->IR', 'PC++'] + ("00","000","00","000","000","001000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->AAL', 'PC++'] + ("00","000","00","000","000","100001","001","000","000","0000","00000","0000",'1'),-- ['[PC]->AAH', 'PC++', 'AAL+Y->AAL'] + ("00","000","00","000","000","000011","000","000","000","0000","00000","0000",'0'),-- ['AAH+AALCarry->AAH'] + ("10","001","00","101","000","000000","000","000","000","0001","01111","0000",'1'),-- ['ALU(A,[AA])', 'Flags'] + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- DA PHX + ("00","000","00","000","000","000000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->IR', 'PC++'] + ("00","000","00","000","000","000000","000","000","000","0000","00000","0000",'1'),-- [] + ("10","010","00","000","000","000000","000","011","000","0000","00000","0010",'1'),-- ['X->[21:SP]', 'SP--'] + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- DB + ("00","000","00","000","000","000000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->IR', 'PC++'] + ("10","000","00","000","000","000000","000","000","000","0000","00000","0000",'0'),-- [] + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- DC + ("00","000","00","000","000","000000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->IR', 'PC++'] + ("10","000","00","000","000","000000","000","000","000","0000","00000","0000",'0'),-- [] + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- DD CMP ABS,X + ("00","000","00","000","000","000000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->IR', 'PC++'] + ("00","000","00","000","000","001000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->AAL', 'PC++'] + ("00","000","00","000","000","011001","001","000","000","0000","00000","0000",'1'),-- ['[PC]->AAH', 'PC++', 'AAL+X->AAL'] + ("00","000","00","000","000","000011","000","000","000","0000","00000","0000",'0'),-- ['AAH+AALCarry->AAH'] + ("10","001","00","101","000","000000","000","000","000","0001","01111","0000",'1'),-- ['ALU(A,[AA])', 'Flags'] + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- DE DEC ABS,X + ("00","000","00","000","000","000000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->IR', 'PC++'] + ("00","000","00","000","000","001000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->AAL', 'PC++'] + ("00","000","00","000","000","011001","001","000","000","0000","00000","0000",'1'),-- ['[PC]->AAH', 'PC++', 'AAL+X->AAL'] + ("00","000","00","000","000","000011","000","000","000","0000","00000","0000",'0'),-- ['AAH+AALCarry->AAH'] + ("00","001","00","001","001","000000","000","000","000","0000","00110","0000",'1'),-- ['ALU([AA])->T', 'Flags'] + ("00","000","00","000","000","000000","000","000","000","0000","00000","0000",'0'),-- [] + ("10","001","00","000","000","000000","000","000","000","0000","00000","0100",'1'),-- ['T->[AA]'] + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- DF BBS5 + ("00","000","00","000","000","000000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->IR', 'PC++'] + ("00","000","00","000","000","001000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->AAL', 'PC++'] + ("00","000","00","000","000","000000","000","000","000","0000","00000","0000",'0'),-- [] + ("00","000","00","000","000","000000","000","000","000","0000","00000","0000",'0'),-- [] + ("00","011","00","000","000","000000","000","000","000","0000","00000","0000",'1'),-- ['[20:AAL]->DR'] + ("10","000","00","000","000","001000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->AAL', 'PC++'] + ("00","000","00","000","000","000000","100","000","000","0000","00000","0000",'0'),-- ['PC+AAL->PC'] + ("10","000","00","000","000","000000","000","000","000","0000","00000","0000",'0'),-- [] + -- E0 CPX IMM + ("00","000","00","000","000","000000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->IR', 'PC++'] + ("10","000","00","101","000","000000","001","000","000","0010","01111","0000",'1'),-- ['ALU(X,[PC])', 'PC++', 'Flags'] + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- E1 SBC (ZP,X) + ("00","000","00","000","000","000000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->IR', 'PC++'] + ("00","000","00","000","000","001000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->AAL', 'PC++'] + ("00","000","00","000","000","011000","000","000","000","0000","00000","0000",'0'),-- ['AAL+X->AAL'] + ("00","011","00","000","000","010000","000","000","000","0000","00000","0000",'1'),-- ['[20:AAL]->DR', 'AAL+1->AAL'] + ("00","011","00","000","000","101001","000","000","000","0000","00000","0000",'1'),-- ['[20:AAL]->AAH', 'DR->AAL'] + ("00","000","00","000","000","000000","000","000","000","0000","00000","0000",'0'),-- [] + ("01","001","00","101","000","000000","000","000","001","0001","00101","0000",'1'),-- ['ALU(A,[AA])->A', 'Flags'] + ("10","000","00","000","000","000000","000","000","000","0000","00000","0000",'0'),-- [] + -- E2 + ("00","000","00","000","000","000000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->IR', 'PC++'] + ("10","000","00","000","000","000000","000","000","000","0000","00000","0000",'0'),-- [] + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- E3 TIA + ("00","000","00","000","000","000000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->IR', 'PC++'] + ("00","010","00","000","000","000000","000","011","000","0000","00000","0011",'1'),-- ['Y->[21:SP]', 'SP--'] + ("00","010","00","000","000","000000","000","011","000","0000","00000","0001",'1'),-- ['A->[21:SP]', 'SP--'] + ("00","010","00","000","000","000000","000","000","000","0000","00000","0010",'1'),-- ['X->[21:SP]'] + ("00","000","00","000","000","000000","001","000","010","0000","00000","0000",'1'),-- ['[PC]->X', 'PC++'] + ("00","000","01","000","000","000000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->SH', 'PC++'] + ("00","000","00","000","000","000000","001","000","100","0000","00000","0000",'1'),-- ['[PC]->Y', 'PC++'] + ("00","000","10","000","000","000000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->DH', 'PC++'] + -- E4 CPX ZP + ("00","000","00","000","000","000000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->IR', 'PC++'] + ("00","000","00","000","000","001000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->AAL', 'PC++'] + ("00","000","00","000","000","000000","000","000","000","0000","00000","0000",'0'),-- [] + ("10","011","00","101","000","000000","000","000","000","0010","01111","0000",'1'),-- ['ALU(X,[20:AAL])', 'Flags'] + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- E5 SBC ZP + ("00","000","00","000","000","000000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->IR', 'PC++'] + ("00","000","00","000","000","001000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->AAL', 'PC++'] + ("00","000","00","000","000","000000","000","000","000","0000","00000","0000",'0'),-- [] + ("01","011","00","101","000","000000","000","000","001","0001","00101","0000",'1'),-- ['ALU(A,[20:AAL])->A', 'Flags'] + ("10","000","00","000","000","000000","000","000","000","0000","00000","0000",'0'),-- [] + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- E6 INC ZP + ("00","000","00","000","000","000000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->IR', 'PC++'] + ("00","000","00","000","000","001000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->AAL', 'PC++'] + ("00","000","00","000","000","000000","000","000","000","0000","00000","0000",'0'),-- [] + ("00","011","00","001","001","000000","000","000","000","0000","00111","0000",'1'),-- ['ALU([20:AAL])->T', 'Flags'] + ("00","000","00","000","000","000000","000","000","000","0000","00000","0000",'0'),-- [] + ("10","011","00","000","000","000000","000","000","000","0000","00000","0100",'1'),-- ['T->[20:AAL]'] + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- E7 SMB6 + ("00","000","00","000","000","000000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->IR', 'PC++'] + ("00","000","00","000","000","001000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->AAL', 'PC++'] + ("00","000","00","000","000","000000","000","000","000","0000","00000","0000",'0'),-- [] + ("00","011","00","000","001","000000","000","000","000","1100","01110","0000",'1'),-- ['ALU([20:AAL])->T'] + ("00","000","00","000","000","000000","000","000","000","0000","00000","0000",'0'),-- [] + ("00","000","00","000","000","000000","000","000","000","0000","00000","0000",'0'),-- [] + ("10","011","00","000","000","000000","000","000","000","0000","00000","0100",'1'),-- ['T->[20:AAL]'] + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- E8 INX + ("00","000","00","000","000","000000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->IR', 'PC++'] + ("10","000","00","001","000","000000","000","000","010","0010","00111","0000",'1'),-- ['ALU(X)->X', 'Flags'] + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- E9 SBC IMM + ("00","000","00","000","000","000000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->IR', 'PC++'] + ("01","000","00","101","000","000000","001","000","001","0001","00101","0000",'1'),-- ['ALU(A,[PC])->A', 'PC++', 'Flags'] + ("10","000","00","000","000","000000","000","000","000","0000","00000","0000",'0'),-- [] + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- EA NOP + ("00","000","00","000","000","000000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->IR', 'PC++'] + ("10","000","00","000","000","000000","000","000","000","0000","00000","0000",'1'),-- [] + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- EB + ("00","000","00","000","000","000000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->IR', 'PC++'] + ("10","000","00","000","000","000000","000","000","000","0000","00000","0000",'0'),-- [] + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- EC CPX ABS + ("00","000","00","000","000","000000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->IR', 'PC++'] + ("00","000","00","000","000","001000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->AAL', 'PC++'] + ("00","000","00","000","000","000001","001","000","000","0000","00000","0000",'1'),-- ['[PC]->AAH', 'PC++'] + ("00","000","00","000","000","000000","000","000","000","0000","00000","0000",'0'),-- [] + ("10","001","00","101","000","000000","000","000","000","0010","01111","0000",'1'),-- ['ALU(X,[AA])', 'Flags'] + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- ED SBC ABS + ("00","000","00","000","000","000000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->IR', 'PC++'] + ("00","000","00","000","000","001000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->AAL', 'PC++'] + ("00","000","00","000","000","000001","001","000","000","0000","00000","0000",'1'),-- ['[PC]->AAH', 'PC++'] + ("00","000","00","000","000","000000","000","000","000","0000","00000","0000",'0'),-- [] + ("10","001","00","101","000","000000","000","000","001","0001","00101","0000",'1'),-- ['ALU(A,[AA])->A', 'Flags'] + ("10","000","00","000","000","000000","000","000","000","0000","00000","0000",'0'),-- [] + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- EE INC ABS + ("00","000","00","000","000","000000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->IR', 'PC++'] + ("00","000","00","000","000","001000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->AAL', 'PC++'] + ("00","000","00","000","000","000001","001","000","000","0000","00000","0000",'1'),-- ['[PC]->AAH', 'PC++'] + ("00","000","00","000","000","000000","000","000","000","0000","00000","0000",'0'),-- [] + ("00","001","00","001","001","000000","000","000","000","0000","00111","0000",'1'),-- ['ALU([AA])->T', 'Flags'] + ("00","000","00","000","000","000000","000","000","000","0000","00000","0000",'0'),-- [] + ("10","001","00","000","000","000000","000","000","000","0000","00000","0100",'1'),-- ['T->[AA]'] + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- EF BBS6 + ("00","000","00","000","000","000000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->IR', 'PC++'] + ("00","000","00","000","000","001000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->AAL', 'PC++'] + ("00","000","00","000","000","000000","000","000","000","0000","00000","0000",'0'),-- [] + ("00","000","00","000","000","000000","000","000","000","0000","00000","0000",'0'),-- [] + ("00","011","00","000","000","000000","000","000","000","0000","00000","0000",'1'),-- ['[20:AAL]->DR'] + ("10","000","00","000","000","001000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->AAL', 'PC++'] + ("00","000","00","000","000","000000","100","000","000","0000","00000","0000",'0'),-- ['PC+AAL->PC'] + ("10","000","00","000","000","000000","000","000","000","0000","00000","0000",'0'),-- [] + -- F0 BEQ + ("00","000","00","000","000","000000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->IR', 'PC++'] + ("10","000","00","000","000","001000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->AAL', 'PC++'] + ("00","000","00","000","000","000000","000","000","000","0000","00000","0000",'1'),-- [] + ("10","000","00","000","000","000000","100","000","000","0000","00000","0000",'0'),-- ['PC+AAL->PC'] + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- F1 SBC (ZP),Y + ("00","000","00","000","000","000000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->IR', 'PC++'] + ("00","000","00","000","000","001000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->AAL', 'PC++'] + ("00","000","00","000","000","000000","000","000","000","0000","00000","0000",'0'),-- [] + ("00","011","00","000","000","010000","000","000","000","0000","00000","0000",'1'),-- ['[20:AAL]->DR', 'AAL+1->AAL'] + ("00","011","00","000","000","110001","000","000","000","0000","00000","0000",'1'),-- ['[20:AAL]->AAH', 'DR+Y->AAL'] + ("00","000","00","000","000","000011","000","000","000","0000","00000","0000",'0'),-- ['AAH+AALCarry->AAH'] + ("01","001","00","101","000","000000","000","000","001","0001","00101","0000",'1'),-- ['ALU(A,[AA])->A', 'Flags'] + ("10","000","00","000","000","000000","000","000","000","0000","00000","0000",'0'),-- [] + -- F2 SBC (ZP) + ("00","000","00","000","000","000000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->IR', 'PC++'] + ("00","000","00","000","000","001000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->AAL', 'PC++'] + ("00","000","00","000","000","000000","000","000","000","0000","00000","0000",'0'),-- [] + ("00","011","00","000","000","010000","000","000","000","0000","00000","0000",'1'),-- ['[20:AAL]->DR', 'AAL+1->AAL'] + ("00","011","00","000","000","101001","000","000","000","0000","00000","0000",'1'),-- ['[20:AAL]->AAH', 'DR->AAL'] + ("00","000","00","000","000","000000","000","000","000","0000","00000","0000",'0'),-- [] + ("01","001","00","101","000","000000","000","000","001","0001","00101","0000",'1'),-- ['ALU(A,[AA])->A', 'Flags'] + ("10","000","00","000","000","000000","000","000","000","0000","00000","0000",'0'),-- [] + -- F3 TAI + ("00","000","00","000","000","000000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->IR', 'PC++'] + ("00","010","00","000","000","000000","000","011","000","0000","00000","0011",'1'),-- ['Y->[21:SP]', 'SP--'] + ("00","010","00","000","000","000000","000","011","000","0000","00000","0001",'1'),-- ['A->[21:SP]', 'SP--'] + ("00","010","00","000","000","000000","000","000","000","0000","00000","0010",'1'),-- ['X->[21:SP]'] + ("00","000","00","000","000","000000","001","000","010","0000","00000","0000",'1'),-- ['[PC]->X', 'PC++'] + ("00","000","01","000","000","000000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->SH', 'PC++'] + ("00","000","00","000","000","000000","001","000","100","0000","00000","0000",'1'),-- ['[PC]->Y', 'PC++'] + ("00","000","10","000","000","000000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->DH', 'PC++'] + -- F4 SET + ("00","000","00","000","000","000000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->IR', 'PC++'] + ("10","000","00","110","000","000000","000","000","000","0000","00000","0000",'1'),-- ['Flags'] + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- F5 SBC ZP,X + ("00","000","00","000","000","000000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->IR', 'PC++'] + ("00","000","00","000","000","001000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->AAL', 'PC++'] + ("00","000","00","000","000","011000","000","000","000","0000","00000","0000",'0'),-- ['AAL+X->AAL'] + ("01","011","00","101","000","000000","000","000","001","0001","00101","0000",'1'),-- ['ALU(A,[20:AAL])->A', 'Flags'] + ("10","000","00","000","000","000000","000","000","000","0000","00000","0000",'0'),-- [] + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- F6 INC ZP,X + ("00","000","00","000","000","000000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->IR', 'PC++'] + ("00","000","00","000","000","001000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->AAL', 'PC++'] + ("00","000","00","000","000","011000","000","000","000","0000","00000","0000",'0'),-- ['AAL+X->AAL'] + ("00","011","00","001","001","000000","000","000","000","0000","00111","0000",'1'),-- ['ALU([20:AAL])->T', 'Flags'] + ("00","000","00","000","000","000000","000","000","000","0000","00000","0000",'0'),-- [] + ("10","011","00","000","000","000000","000","000","000","0000","00000","0100",'1'),-- ['T->[20:AAL]'] + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- F7 SMB7 + ("00","000","00","000","000","000000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->IR', 'PC++'] + ("00","000","00","000","000","001000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->AAL', 'PC++'] + ("00","000","00","000","000","000000","000","000","000","0000","00000","0000",'0'),-- [] + ("00","011","00","000","001","000000","000","000","000","1100","01110","0000",'1'),-- ['ALU([20:AAL])->T'] + ("00","000","00","000","000","000000","000","000","000","0000","00000","0000",'0'),-- [] + ("00","000","00","000","000","000000","000","000","000","0000","00000","0000",'0'),-- [] + ("10","011","00","000","000","000000","000","000","000","0000","00000","0100",'1'),-- ['T->[20:AAL]'] + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- F8 SED + ("00","000","00","000","000","000000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->IR', 'PC++'] + ("10","000","00","100","000","000000","000","000","000","0000","00000","0000",'1'),-- ['Flags'] + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- F9 SBC ABS,Y + ("00","000","00","000","000","000000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->IR', 'PC++'] + ("00","000","00","000","000","001000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->AAL', 'PC++'] + ("00","000","00","000","000","100001","001","000","000","0000","00000","0000",'1'),-- ['[PC]->AAH', 'PC++', 'AAL+Y->AAL'] + ("00","000","00","000","000","000011","000","000","000","0000","00000","0000",'0'),-- ['AAH+AALCarry->AAH'] + ("01","001","00","101","000","000000","000","000","001","0001","00101","0000",'1'),-- ['ALU(A,[AA])->A', 'Flags'] + ("10","000","00","000","000","000000","000","000","000","0000","00000","0000",'0'),-- [] + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- FA PLX + ("00","000","00","000","000","000000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->IR', 'PC++'] + ("00","000","00","000","000","000000","000","000","000","0000","00000","0000",'0'),-- [] + ("00","000","00","000","000","000000","000","010","000","0000","00000","0000",'0'),-- ['SP++'] + ("10","010","00","001","000","000000","000","000","010","0000","00000","0000",'1'),-- ['ALU([21:SP])->X'] + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- FB + ("00","000","00","000","000","000000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->IR', 'PC++'] + ("10","000","00","000","000","000000","000","000","000","0000","00000","0000",'0'),-- [] + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- FC + ("00","000","00","000","000","000000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->IR', 'PC++'] + ("10","000","00","000","000","000000","000","000","000","0000","00000","0000",'0'),-- [] + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- FD SBC ABS,X + ("00","000","00","000","000","000000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->IR', 'PC++'] + ("00","000","00","000","000","001000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->AAL', 'PC++'] + ("00","000","00","000","000","011001","001","000","000","0000","00000","0000",'1'),-- ['[PC]->AAH', 'PC++', 'AAL+X->AAL'] + ("00","000","00","000","000","000011","000","000","000","0000","00000","0000",'0'),-- ['AAH+AALCarry->AAH'] + ("01","001","00","101","000","000000","000","000","001","0001","00101","0000",'1'),-- ['ALU(A,[AA])->A', 'Flags'] + ("10","000","00","000","000","000000","000","000","000","0000","00000","0000",'0'),-- [] + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- FE INC ABS,X + ("00","000","00","000","000","000000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->IR', 'PC++'] + ("00","000","00","000","000","001000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->AAL', 'PC++'] + ("00","000","00","000","000","011001","001","000","000","0000","00000","0000",'1'),-- ['[PC]->AAH', 'PC++', 'AAL+X->AAL'] + ("00","000","00","000","000","000011","000","000","000","0000","00000","0000",'0'),-- ['AAH+AALCarry->AAH'] + ("00","001","00","001","001","000000","000","000","000","0000","00111","0000",'1'),-- ['ALU([AA])->T', 'Flags'] + ("00","000","00","000","000","000000","000","000","000","0000","00000","0000",'0'),-- [] + ("10","001","00","000","000","000000","000","000","000","0000","00000","0100",'1'),-- ['T->[AA]'] + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- FF BBS7 + ("00","000","00","000","000","000000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->IR', 'PC++'] + ("00","000","00","000","000","001000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->AAL', 'PC++'] + ("00","000","00","000","000","000000","000","000","000","0000","00000","0000",'0'),-- [] + ("00","000","00","000","000","000000","000","000","000","0000","00000","0000",'0'),-- [] + ("00","011","00","000","000","000000","000","000","000","0000","00000","0000",'1'),-- ['[20:AAL]->DR'] + ("10","000","00","000","000","001000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->AAL', 'PC++'] + ("00","000","00","000","000","000000","100","000","000","0000","00000","0000",'0'),-- ['PC+AAL->PC'] + ("10","000","00","000","000","000000","000","000","000","0000","00000","0000",'0') -- [] + ); + + constant M_TAB2: MicroInst_t := ( + -- 00 BRK + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- 01 ORA (ZP,X) + ("00","000","00","000","000","001000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->AAL', 'PC++'] + ("00","000","00","000","000","011000","000","000","000","0000","00000","0000",'0'),-- ['AAL+X->AAL'] + ("00","011","00","000","000","010000","000","000","000","0000","00000","0000",'1'),-- ['[20:AAL]->DR', 'AAL+1->AAL'] + ("00","011","00","000","000","101001","000","000","000","0000","00000","0000",'1'),-- ['[20:AAL]->AAH', 'DR->AAL'] + ("00","000","00","000","000","000000","000","000","000","0000","00000","0000",'0'),-- [] + ("00","001","00","000","001","000000","000","000","000","0000","00000","0000",'1'),-- ['[AA]->T'] + ("00","000","00","000","000","111000","000","000","000","0000","00000","0000",'0'),-- ['X->AAL'] + ("00","011","00","001","001","000000","000","000","000","0101","00010","0000",'1'),-- ['ALU(T,[20:AAL])->T', 'Flags'] + -- 02 SXY + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- 03 ST0 + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- 04 TSB ZP + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- 05 ORA ZP + ("00","000","00","000","000","001000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->AAL', 'PC++'] + ("00","000","00","000","000","000000","000","000","000","0000","00000","0000",'0'),-- [] + ("00","011","00","000","001","000000","000","000","000","0000","00000","0000",'1'),-- ['[20:AAL]->T'] + ("00","000","00","000","000","111000","000","000","000","0000","00000","0000",'0'),-- ['X->AAL'] + ("00","011","00","001","001","000000","000","000","000","0101","00010","0000",'1'),-- ['ALU(T,[20:AAL])->T', 'Flags'] + ("10","011","00","000","000","000000","000","000","000","0000","00000","0100",'1'),-- ['T->[20:AAL]'] + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- 06 ASL ZP + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- 07 RMB0 + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- 08 PHP + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- 09 ORA IMM / IMM,(X) + ("00","000","00","000","001","000000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->T', 'PC++'] + ("00","000","00","000","000","111000","000","000","000","0000","00000","0000",'0'),-- ['X->AAL'] + ("00","011","00","001","001","000000","000","000","000","0101","00010","0000",'1'),-- ['ALU(T,[20:AAL])->T', 'Flags'] + ("10","011","00","000","000","000000","000","000","000","0000","00000","0100",'1'),-- ['T->[20:AAL]'] + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- 0A ASL A + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- 0B + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- 0C TSB ABS + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- 0D ORA ABS + ("00","000","00","000","000","001000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->AAL', 'PC++'] + ("00","000","00","000","000","000001","001","000","000","0000","00000","0000",'1'),-- ['[PC]->AAH', 'PC++'] + ("00","000","00","000","000","000000","000","000","000","0000","00000","0000",'0'),-- [] + ("00","001","00","000","001","000000","000","000","000","0000","00000","0000",'1'),-- ['ALU(A,[AA])->A'] + ("00","000","00","000","000","111000","000","000","000","0000","00000","0000",'0'),-- ['X->AAL'] + ("00","011","00","001","001","000000","000","000","000","0101","00010","0000",'1'),-- ['ALU(T,[20:AAL])->T', 'Flags'] + ("10","011","00","000","000","000000","000","000","000","0000","00000","0100",'1'),-- ['T->[20:AAL]'] + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- 0E ASL ABS + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- 0F BBR0 + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- 10 BPL + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- 11 ORA (ZP),Y + ("00","000","00","000","000","001000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->AAL', 'PC++'] + ("00","000","00","000","000","000000","000","000","000","0000","00000","0000",'0'),-- [] + ("00","011","00","000","000","010000","000","000","000","0000","00000","0000",'1'),-- ['[20:AAL]->DR', 'AAL+1->AAL'] + ("00","011","00","000","000","110001","000","000","000","0000","00000","0000",'1'),-- ['[20:AAL]->AAH', 'DR+Y->AAL'] + ("00","000","00","000","000","000011","000","000","000","0000","00000","0000",'0'),-- ['AAH+AALCarry->AAH'] + ("00","001","00","000","001","000000","000","000","000","0000","00000","0000",'1'),-- ['ALU(A,[AA])->A'] + ("00","000","00","000","000","111000","000","000","000","0000","00000","0000",'0'),-- ['X->AAL'] + ("00","011","00","001","001","000000","000","000","000","0101","00010","0000",'1'),-- ['ALU(T,[20:AAL])->T', 'Flags'] + -- 12 ORA (ZP) + ("00","000","00","000","000","001000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->AAL', 'PC++'] + ("00","000","00","000","000","000000","000","000","000","0000","00000","0000",'0'),-- [] + ("00","011","00","000","000","010000","000","000","000","0000","00000","0000",'1'),-- ['[20:AAL]->DR', 'AAL+1->AAL'] + ("00","011","00","000","000","101001","000","000","000","0000","00000","0000",'1'),-- ['[20:AAL]->AAH', 'DR->AAL'] + ("00","000","00","000","000","000000","000","000","000","0000","00000","0000",'0'),-- [] + ("00","001","00","000","001","000000","000","000","000","0000","00000","0000",'1'),-- ['ALU(A,[AA])->A'] + ("00","000","00","000","000","111000","000","000","000","0000","00000","0000",'0'),-- ['X->AAL'] + ("00","011","00","001","001","000000","000","000","000","0101","00010","0000",'1'),-- ['ALU(T,[20:AAL])->T', 'Flags'] + -- 13 ST1 + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- 14 TRB ZP + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- 15 ORA ZP,X + ("00","000","00","000","000","001000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->AAL', 'PC++'] + ("00","000","00","000","000","011000","000","000","000","0000","00000","0000",'0'),-- ['AAL+X->AAL'] + ("00","011","00","000","001","000000","000","000","000","0000","00000","0000",'1'),-- ['ALU(A,[20:AAL])->A'] + ("00","000","00","000","000","111000","000","000","000","0000","00000","0000",'0'),-- ['X->AAL'] + ("00","011","00","001","001","000000","000","000","000","0101","00010","0000",'1'),-- ['ALU(T,[20:AAL])->T', 'Flags'] + ("10","011","00","000","000","000000","000","000","000","0000","00000","0100",'1'),-- ['T->[20:AAL]'] + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- 16 ASL ZP,X + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- 17 RMB1 + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- 18 CLC + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- 19 ORA ABS,Y + ("00","000","00","000","000","001000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->AAL', 'PC++'] + ("00","000","00","000","000","100001","001","000","000","0000","00000","0000",'1'),-- ['[PC]->AAH', 'PC++', 'AAL+Y->AAL'] + ("00","000","00","000","000","000011","000","000","000","0000","00000","0000",'0'),-- ['AAH+AALCarry->AAH'] + ("00","001","00","000","001","000000","000","000","000","0000","00000","0000",'1'),-- ['ALU(A,[AA])->A'] + ("00","000","00","000","000","111000","000","000","000","0000","00000","0000",'0'),-- ['X->AAL'] + ("00","011","00","001","001","000000","000","000","000","0101","00010","0000",'1'),-- ['ALU(T,[20:AAL])->T', 'Flags'] + ("10","011","00","000","000","000000","000","000","000","0000","00000","0100",'1'),-- ['T->[20:AAL]'] + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- 1A INC A + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- 1B + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- 1C TRB ABS + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- 1D ORA ABS,X + ("00","000","00","000","000","001000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->AAL', 'PC++'] + ("00","000","00","000","000","011001","001","000","000","0000","00000","0000",'1'),-- ['[PC]->AAH', 'PC++', 'AAL+X->AAL'] + ("00","000","00","000","000","000011","000","000","000","0000","00000","0000",'0'),-- ['AAH+AALCarry->AAH'] + ("00","001","00","000","001","000000","000","000","000","0000","00000","0000",'1'),-- ['ALU(A,[AA])->A'] + ("00","000","00","000","000","111000","000","000","000","0000","00000","0000",'0'),-- ['X->AAL'] + ("00","011","00","001","001","000000","000","000","000","0101","00010","0000",'1'),-- ['ALU(T,[20:AAL])->T', 'Flags'] + ("10","011","00","000","000","000000","000","000","000","0000","00000","0100",'1'),-- ['T->[20:AAL]'] + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- 1E ASL ABS,X + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- 1F BBR1 + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- 20 JSR ABS + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- 21 AND (ZP,X) + ("00","000","00","000","000","001000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->AAL', 'PC++'] + ("00","000","00","000","000","011000","000","000","000","0000","00000","0000",'0'),-- ['AAL+X->AAL'] + ("00","011","00","000","000","010000","000","000","000","0000","00000","0000",'1'),-- ['[20:AAL]->DR', 'AAL+1->AAL'] + ("00","011","00","000","000","101001","000","000","000","0000","00000","0000",'1'),-- ['[20:AAL]->AAH', 'DR->AAL'] + ("00","000","00","000","000","000000","000","000","000","0000","00000","0000",'0'),-- [] + ("00","001","00","000","001","000000","000","000","000","0000","00000","0000",'1'),-- ['ALU(A,[AA])->A'] + ("00","000","00","000","000","111000","000","000","000","0000","00000","0000",'0'),-- ['X->AAL'] + ("00","011","00","001","001","000000","000","000","000","0101","00001","0000",'1'),-- ['ALU(T,[20:AAL])->T', 'Flags'] + -- 22 SAX + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- 23 ST2 + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- 24 BIT ZP + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- 25 AND ZP + ("00","000","00","000","000","001000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->AAL', 'PC++'] + ("00","000","00","000","000","000000","000","000","000","0000","00000","0000",'0'),-- [] + ("00","011","00","000","001","000000","000","000","000","0000","00000","0000",'1'),-- ['ALU(A,[20:AAL])->A'] + ("00","000","00","000","000","111000","000","000","000","0000","00000","0000",'0'),-- ['X->AAL'] + ("00","011","00","001","001","000000","000","000","000","0101","00001","0000",'1'),-- ['ALU(T,[20:AAL])->T', 'Flags'] + ("10","011","00","000","000","000000","000","000","000","0000","00000","0100",'1'),-- ['T->[20:AAL]'] + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- 26 ROL ZP + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- 27 RMB2 + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- 28 PLP + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- 29 AND IMM / IMM,(X) + ("00","000","00","000","001","000000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->T', 'PC++'] + ("00","000","00","000","000","111000","000","000","000","0000","00000","0000",'0'),-- ['X->AAL'] + ("00","011","00","001","001","000000","000","000","000","0101","00001","0000",'1'),-- ['ALU(T,[20:AAL])->T'] + ("10","011","00","000","000","000000","000","000","000","0000","00000","0100",'1'),-- ['T->[20:AAL]'] + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- 2A ROL A + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- 2B + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- 2C BIT ABS + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- 2D AND ABS + ("00","000","00","000","000","001000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->AAL', 'PC++'] + ("00","000","00","000","000","000001","001","000","000","0000","00000","0000",'1'),-- ['[PC]->AAH', 'PC++'] + ("00","000","00","000","000","000000","000","000","000","0000","00000","0000",'0'),-- [] + ("00","001","00","000","001","000000","000","000","000","0000","00000","0000",'1'),-- ['ALU(A,[AA])->A'] + ("00","000","00","000","000","111000","000","000","000","0000","00000","0000",'0'),-- ['X->AAL'] + ("00","011","00","001","001","000000","000","000","000","0101","00001","0000",'1'),-- ['ALU(T,[20:AAL])->T', 'Flags'] + ("10","011","00","000","000","000000","000","000","000","0000","00000","0100",'1'),-- ['T->[20:AAL]'] + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- 2E ROL ABS + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- 2F BBR2 + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- 30 BMI + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- 31 AND (ZP),Y + ("00","000","00","000","000","001000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->AAL', 'PC++'] + ("00","000","00","000","000","000000","000","000","000","0000","00000","0000",'0'),-- [] + ("00","011","00","000","000","010000","000","000","000","0000","00000","0000",'1'),-- ['[20:AAL]->DR', 'AAL+1->AAL'] + ("00","011","00","000","000","110001","000","000","000","0000","00000","0000",'1'),-- ['[20:AAL]->AAH', 'DR+Y->AAL'] + ("00","000","00","000","000","000011","000","000","000","0000","00000","0000",'0'),-- ['AAH+AALCarry->AAH'] + ("00","001","00","000","001","000000","000","000","000","0000","00000","0000",'1'),-- ['ALU(A,[AA])->A'] + ("00","000","00","000","000","111000","000","000","000","0000","00000","0000",'0'),-- ['X->AAL'] + ("00","011","00","001","001","000000","000","000","000","0101","00001","0000",'1'),-- ['ALU(T,[20:AAL])->T', 'Flags'] + -- 32 AND (ZP) + ("00","000","00","000","000","001000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->AAL', 'PC++'] + ("00","000","00","000","000","000000","000","000","000","0000","00000","0000",'0'),-- [] + ("00","011","00","000","000","010000","000","000","000","0000","00000","0000",'1'),-- ['[20:AAL]->DR', 'AAL+1->AAL'] + ("00","011","00","000","000","101001","000","000","000","0000","00000","0000",'1'),-- ['[20:AAL]->AAH', 'DR->AAL'] + ("00","000","00","000","000","000000","000","000","000","0000","00000","0000",'0'),-- [] + ("00","001","00","000","001","000000","000","000","000","0000","00000","0000",'1'),-- ['ALU(A,[AA])->A'] + ("00","000","00","000","000","111000","000","000","000","0000","00000","0000",'0'),-- ['X->AAL'] + ("00","011","00","001","001","000000","000","000","000","0101","00001","0000",'1'),-- ['ALU(T,[20:AAL])->T', 'Flags'] + -- 33 + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- 34 BIT ZP,X + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- 35 AND ZP,X + ("00","000","00","000","000","001000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->AAL', 'PC++'] + ("00","000","00","000","000","011000","000","000","000","0000","00000","0000",'0'),-- ['AAL+X->AAL'] + ("00","011","00","000","001","000000","000","000","000","0000","00000","0000",'1'),-- ['ALU(A,[20:AAL])->A'] + ("00","000","00","000","000","111000","000","000","000","0000","00000","0000",'0'),-- ['X->AAL'] + ("00","011","00","001","001","000000","000","000","000","0101","00001","0000",'1'),-- ['ALU(T,[20:AAL])->T', 'Flags'] + ("10","011","00","000","000","000000","000","000","000","0000","00000","0100",'1'),-- ['T->[20:AAL]'] + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- 36 ROL ZP,X + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- 37 RMB3 + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- 38 SEC + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- 39 AND ABS,Y + ("00","000","00","000","000","001000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->AAL', 'PC++'] + ("00","000","00","000","000","100001","001","000","000","0000","00000","0000",'1'),-- ['[PC]->AAH', 'PC++', 'AAL+Y->AAL'] + ("00","000","00","000","000","000011","000","000","000","0000","00000","0000",'0'),-- ['AAH+AALCarry->AAH'] + ("00","001","00","000","001","000000","000","000","000","0000","00000","0000",'1'),-- ['ALU(A,[AA])->A'] + ("00","000","00","000","000","111000","000","000","000","0000","00000","0000",'0'),-- ['X->AAL'] + ("00","011","00","001","001","000000","000","000","000","0101","00001","0000",'1'),-- ['ALU(T,[20:AAL])->T', 'Flags'] + ("10","011","00","000","000","000000","000","000","000","0000","00000","0100",'1'),-- ['T->[20:AAL]'] + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- 3A DEC A + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- 3B + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- 3C BIT ABS,X + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- 3D AND ABS,X + ("00","000","00","000","000","001000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->AAL', 'PC++'] + ("00","000","00","000","000","011001","001","000","000","0000","00000","0000",'1'),-- ['[PC]->AAH', 'PC++', 'AAL+X->AAL'] + ("00","000","00","000","000","000011","000","000","000","0000","00000","0000",'0'),-- ['AAH+AALCarry->AAH'] + ("00","001","00","000","001","000000","000","000","000","0000","00000","0000",'1'),-- ['ALU(A,[AA])->A'] + ("00","000","00","000","000","111000","000","000","000","0000","00000","0000",'0'),-- ['X->AAL'] + ("00","011","00","001","001","000000","000","000","000","0101","00001","0000",'1'),-- ['ALU(T,[20:AAL])->T', 'Flags'] + ("10","011","00","000","000","000000","000","000","000","0000","00000","0100",'1'),-- ['T->[20:AAL]'] + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- 3E ROL ABS,X + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- 3F BBR3 + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- 40 RTI + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- 41 EOR (ZP,X) + ("00","000","00","000","000","001000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->AAL', 'PC++'] + ("00","000","00","000","000","011000","000","000","000","0000","00000","0000",'0'),-- ['AAL+X->AAL'] + ("00","011","00","000","000","010000","000","000","000","0000","00000","0000",'1'),-- ['[20:AAL]->DR', 'AAL+1->AAL'] + ("00","011","00","000","000","101001","000","000","000","0000","00000","0000",'1'),-- ['[20:AAL]->AAH', 'DR->AAL'] + ("00","000","00","000","000","000000","000","000","000","0000","00000","0000",'0'),-- [] + ("00","001","00","000","001","000000","000","000","000","0000","00000","0000",'1'),-- ['ALU(A,[AA])->T'] + ("00","000","00","000","000","111000","000","000","000","0000","00000","0000",'0'),-- ['X->AAL'] + ("00","011","00","001","001","000000","000","000","000","0101","00011","0000",'1'),-- ['ALU(T,[20:AAL])->T', 'Flags'] + -- 42 SAY + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- 43 TMAi + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- 44 BSR + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- 45 EOR ZP + ("00","000","00","000","000","001000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->AAL', 'PC++'] + ("00","000","00","000","000","000000","000","000","000","0000","00000","0000",'0'),-- [] + ("00","011","00","000","001","000000","000","000","000","0000","00000","0000",'1'),-- ['ALU(A,[20:AAL])->T'] + ("00","000","00","000","000","111000","000","000","000","0000","00000","0000",'0'),-- ['X->AAL'] + ("00","011","00","001","001","000000","000","000","000","0101","00011","0000",'1'),-- ['ALU(T,[20:AAL])->T', 'Flags'] + ("10","011","00","000","000","000000","000","000","000","0000","00000","0100",'1'),-- ['T->[20:AAL]'] + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- 46 LSR ZP + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- 47 RMB4 + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- 48 PHA + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- 49 EOR IMM / IMM,(X) + ("00","000","00","000","001","000000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->T', 'PC++'] + ("00","000","00","000","000","111000","000","000","000","0000","00000","0000",'0'),-- ['X->AAL'] + ("00","011","00","001","001","000000","000","000","000","0101","00011","0000",'1'),-- ['ALU(T,[20:AAL])->T'] + ("10","011","00","000","000","000000","000","000","000","0000","00000","0100",'1'),-- ['T->[20:AAL]'] + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- 4A LSR A + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- 4B + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- 4C JMP ABS + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- 4D EOR ABS + ("00","000","00","000","000","001000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->AAL', 'PC++'] + ("00","000","00","000","000","000001","001","000","000","0000","00000","0000",'1'),-- ['[PC]->AAH', 'PC++'] + ("00","000","00","000","000","000000","000","000","000","0000","00000","0000",'0'),-- [] + ("00","001","00","000","001","000000","000","000","000","0000","00000","0000",'1'),-- ['[AA]->T'] + ("00","000","00","000","000","111000","000","000","000","0000","00000","0000",'0'),-- ['X->AAL'] + ("00","011","00","001","001","000000","000","000","000","0101","00011","0000",'1'),-- ['ALU(T,[20:AAL])->T', 'Flags'] + ("10","011","00","000","000","000000","000","000","000","0000","00000","0100",'1'),-- ['T->[20:AAL]'] + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- 4E LSR ABS + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- 4F BBR4 + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- 50 BVC + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- 51 EOR (ZP),Y + ("00","000","00","000","000","001000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->AAL', 'PC++'] + ("00","000","00","000","000","000000","000","000","000","0000","00000","0000",'0'),-- [] + ("00","011","00","000","000","010000","000","000","000","0000","00000","0000",'1'),-- ['[20:AAL]->DR', 'AAL+1->AAL'] + ("00","011","00","000","000","110001","000","000","000","0000","00000","0000",'1'),-- ['[20:AAL]->AAH', 'DR+Y->AAL'] + ("00","000","00","000","000","000011","000","000","000","0000","00000","0000",'0'),-- ['AAH+AALCarry->AAH'] + ("00","001","00","000","001","000000","000","000","000","0000","00000","0000",'1'),-- ['[AA]->T'] + ("00","000","00","000","000","111000","000","000","000","0000","00000","0000",'0'),-- ['X->AAL'] + ("00","011","00","001","001","000000","000","000","000","0101","00011","0000",'1'),-- ['ALU(T,[20:AAL])->T', 'Flags'] + -- 52 EOR (ZP) + ("00","000","00","000","000","001000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->AAL', 'PC++'] + ("00","000","00","000","000","000000","000","000","000","0000","00000","0000",'0'),-- [] + ("00","011","00","000","000","010000","000","000","000","0000","00000","0000",'1'),-- ['[20:AAL]->DR', 'AAL+1->AAL'] + ("00","011","00","000","000","101001","000","000","000","0000","00000","0000",'1'),-- ['[20:AAL]->AAH', 'DR->AAL'] + ("00","000","00","000","000","000000","000","000","000","0000","00000","0000",'0'),-- [] + ("00","001","00","000","001","000000","000","000","000","0000","00000","0000",'1'),-- ['[AA]->T'] + ("00","000","00","000","000","111000","000","000","000","0000","00000","0000",'0'),-- ['X->AAL'] + ("00","011","00","001","001","000000","000","000","000","0101","00011","0000",'1'),-- ['ALU(T,[20:AAL])->T', 'Flags'] + -- 53 TAMi + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- 54 CSL + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- 55 EOR ZP,X + ("00","000","00","000","000","001000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->AAL', 'PC++'] + ("00","000","00","000","000","011000","000","000","000","0000","00000","0000",'0'),-- ['AAL+X->AAL'] + ("00","011","00","000","001","000000","000","000","000","0000","00000","0000",'1'),-- ['[20:AAL]->T'] + ("00","000","00","000","000","111000","000","000","000","0000","00000","0000",'0'),-- ['X->AAL'] + ("00","011","00","001","001","000000","000","000","000","0101","00011","0000",'1'),-- ['ALU(T,[20:AAL])->T', 'Flags'] + ("10","011","00","000","000","000000","000","000","000","0000","00000","0100",'1'),-- ['T->[20:AAL]'] + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- 56 LSR ZP,X + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- 57 RMB5 + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- 58 CLI + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- 59 EOR ABS,Y + ("00","000","00","000","000","001000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->AAL', 'PC++'] + ("00","000","00","000","000","100001","001","000","000","0000","00000","0000",'1'),-- ['[PC]->AAH', 'PC++', 'AAL+Y->AAL'] + ("00","000","00","000","000","000011","000","000","000","0000","00000","0000",'0'),-- ['AAH+AALCarry->AAH'] + ("00","001","00","000","001","000000","000","000","000","0000","00000","0000",'1'),-- ['[AA]->T'] + ("00","000","00","000","000","111000","000","000","000","0000","00000","0000",'0'),-- ['X->AAL'] + ("00","011","00","001","001","000000","000","000","000","0101","00011","0000",'1'),-- ['ALU(T,[20:AAL])->T', 'Flags'] + ("10","011","00","000","000","000000","000","000","000","0000","00000","0100",'1'),-- ['T->[20:AAL]'] + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- 5A PHY + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- 5B + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- 5C + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- 5D EOR ABS,X + ("00","000","00","000","000","001000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->AAL', 'PC++'] + ("00","000","00","000","000","011001","001","000","000","0000","00000","0000",'1'),-- ['[PC]->AAH', 'PC++', 'AAL+X->AAL'] + ("00","000","00","000","000","000011","000","000","000","0000","00000","0000",'0'),-- ['AAH+AALCarry->AAH'] + ("00","001","00","000","001","000000","000","000","000","0000","00000","0000",'1'),-- ['[AA]->T'] + ("00","000","00","000","000","111000","000","000","000","0000","00000","0000",'0'),-- ['X->AAL'] + ("00","011","00","001","001","000000","000","000","000","0101","00011","0000",'1'),-- ['ALU(T,[20:AAL])->T', 'Flags'] + ("10","011","00","000","000","000000","000","000","000","0000","00000","0100",'1'),-- ['T->[20:AAL]'] + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- 5E LSR ABS,X + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- 5F BBR5 + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- 60 RTS + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- 61 ADC (ZP,X) + ("00","000","00","000","000","001000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->AAL', 'PC++'] + ("00","000","00","000","000","011000","000","000","000","0000","00000","0000",'0'),-- ['AAL+X->AAL'] + ("00","011","00","000","000","010000","000","000","000","0000","00000","0000",'1'),-- ['[20:AAL]->DR', 'AAL+1->AAL'] + ("00","011","00","000","000","101001","000","000","000","0000","00000","0000",'1'),-- ['[20:AAL]->AAH', 'DR->AAL'] + ("00","000","00","000","000","000000","000","000","000","0000","00000","0000",'0'),-- [] + ("00","001","00","000","001","000000","000","000","000","0000","00000","0000",'1'),-- ['[AA]->T'] + ("00","000","00","000","000","111000","000","000","000","0000","00000","0000",'0'),-- ['X->AAL'] + ("00","011","00","101","001","000000","000","000","000","0101","00100","0000",'1'),-- ['ALU(T,[20:AAL])->T', 'Flags'] + -- 62 CLA + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- 63 + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- 64 STZ ZP + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- 65 ADC ZP + ("00","000","00","000","000","001000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->AAL', 'PC++'] + ("00","000","00","000","000","000000","000","000","000","0000","00000","0000",'0'),-- [] + ("00","011","00","000","001","000000","000","000","000","0000","00000","0000",'1'),-- ['[20:AAL]->T'] + ("00","000","00","000","000","111000","000","000","000","0000","00000","0000",'0'),-- ['X->AAL'] + ("00","011","00","101","001","000000","000","000","000","0101","00100","0000",'1'),-- ['ALU(T,[20:AAL])->T', 'Flags'] + ("01","011","00","000","000","000000","000","000","000","0000","00000","0100",'1'),-- ['T->[20:AAL]'] + ("10","000","00","000","000","000000","000","000","000","0000","00000","0000",'0'),-- [] + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- 66 ROR ZP + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- 67 RMB6 + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- 68 PLA + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- 69 ADC IMM / IMM,(X) + ("00","000","00","000","001","000000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->T', 'PC++'] + ("00","000","00","000","000","111000","000","000","000","0000","00000","0000",'0'),-- ['X->AAL'] + ("00","011","00","101","001","000000","000","000","000","0101","00100","0000",'1'),-- ['ALU(T,[20:AAL])->T', 'Flags'] + ("01","011","00","000","000","000000","000","000","000","0000","00000","0100",'1'),-- ['T->[20:AAL]'] + ("10","000","00","000","000","000000","000","000","000","0000","00000","0000",'0'),-- [] + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- 6A ROR A + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- 6B + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- 6C JMP (ABS) + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- 6D ADC ABS + ("00","000","00","000","000","001000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->AAL', 'PC++'] + ("00","000","00","000","000","000001","001","000","000","0000","00000","0000",'1'),-- ['[PC]->AAH', 'PC++'] + ("00","000","00","000","000","000000","000","000","000","0000","00000","0000",'0'),-- [] + ("00","001","00","000","001","000000","000","000","000","0000","00000","0000",'1'),-- ['[AA]->T'] + ("00","000","00","000","000","111000","000","000","000","0000","00000","0000",'0'),-- ['X->AAL'] + ("00","011","00","101","001","000000","000","000","000","0101","00100","0000",'1'),-- ['ALU(T,[20:AAL])->T', 'Flags'] + ("01","011","00","000","000","000000","000","000","000","0000","00000","0100",'1'),-- ['T->[20:AAL]'] + ("10","000","00","000","000","000000","000","000","000","0000","00000","0000",'0'),-- [] + -- 6E ROR ABS + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- 6F BBR6 + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- 70 BVS + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- 71 ADC (ZP),Y + ("00","000","00","000","000","001000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->AAL', 'PC++'] + ("00","000","00","000","000","000000","000","000","000","0000","00000","0000",'0'),-- [] + ("00","011","00","000","000","010000","000","000","000","0000","00000","0000",'1'),-- ['[20:AAL]->DR', 'AAL+1->AAL'] + ("00","011","00","000","000","110001","000","000","000","0000","00000","0000",'1'),-- ['[20:AAL]->AAH', 'DR+Y->AAL'] + ("00","000","00","000","000","000011","000","000","000","0000","00000","0000",'0'),-- ['AAH+AALCarry->AAH'] + ("00","001","00","000","001","000000","000","000","000","0000","00000","0000",'1'),-- ['[AA]->T'] + ("00","000","00","000","000","111000","000","000","000","0000","00000","0000",'0'),-- ['X->AAL'] + ("00","011","00","101","001","000000","000","000","000","0101","00100","0000",'1'),-- ['ALU(T,[20:AAL])->T', 'Flags'] + -- 72 ADC (ZP) + ("00","000","00","000","000","001000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->AAL', 'PC++'] + ("00","000","00","000","000","000000","000","000","000","0000","00000","0000",'0'),-- [] + ("00","011","00","000","000","010000","000","000","000","0000","00000","0000",'1'),-- ['[20:AAL]->DR', 'AAL+1->AAL'] + ("00","011","00","000","000","101001","000","000","000","0000","00000","0000",'1'),-- ['[20:AAL]->AAH', 'DR->AAL'] + ("00","000","00","000","000","000000","000","000","000","0000","00000","0000",'0'),-- [] + ("00","001","00","000","001","000000","000","000","000","0000","00000","0000",'1'),-- ['[AA]->T'] + ("00","000","00","000","000","111000","000","000","000","0000","00000","0000",'0'),-- ['X->AAL'] + ("00","011","00","101","001","000000","000","000","000","0101","00100","0000",'1'),-- ['ALU(T,[20:AAL])->T', 'Flags'] + -- 73 TII + ("00","000","00","000","000","000000","001","000","001","0000","00000","0000",'1'),-- ['[PC]->A', 'PC++'] + ("00","000","11","000","000","000000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->LH', 'PC++'] + ("00","000","00","000","000","000000","000","000","000","0000","00000","0000",'0'),-- [] + ("00","000","00","000","000","000000","000","000","000","0000","00000","0000",'0'),-- [] + ("00","000","00","000","000","000000","000","000","000","0001","00110","0000",'0'),-- ['ALU(A+/-1)->A'] + ("00","000","00","000","000","000000","000","000","000","1010","10000","0000",'0'),-- ['ALU(LH+/-C)->LH'] + ("00","110","00","000","100","000000","000","000","010","0010","00111","0000",'1'),-- ['[SH:X]->T', 'ALU(X+/-1)->X'] + ("00","000","01","000","000","000000","000","000","000","1000","10001","0000",'0'),-- ['ALU(SH+/-C)->SH'] + -- 74 STZ ZP,X + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- 75 ADC ZP,X + ("00","000","00","000","000","001000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->AAL', 'PC++'] + ("00","000","00","000","000","011000","000","000","000","0000","00000","0000",'0'),-- ['AAL+X->AAL'] + ("00","011","00","000","001","000000","000","000","000","0000","00000","0000",'1'),-- ['[20:AAL]->T'] + ("00","000","00","000","000","111000","000","000","000","0000","00000","0000",'0'),-- ['X->AAL'] + ("00","011","00","101","001","000000","000","000","000","0101","00100","0000",'1'),-- ['ALU(T,[20:AAL])->T', 'Flags'] + ("01","011","00","000","000","000000","000","000","000","0000","00000","0100",'1'),-- ['T->[20:AAL]'] + ("10","000","00","000","000","000000","000","000","000","0000","00000","0000",'0'),-- [] + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- 76 ROR ZP,X + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- 77 RMB7 + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- 78 SEI + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- 79 ADC ABS,Y/ABS,Y,(X) + ("00","000","00","000","000","001000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->AAL', 'PC++'] + ("00","000","00","000","000","100001","001","000","000","0000","00000","0000",'1'),-- ['[PC]->AAH', 'PC++', 'AAL+Y->AAL'] + ("00","000","00","000","000","000011","000","000","000","0000","00000","0000",'0'),-- ['AAH+AALCarry->AAH'] + ("00","001","00","000","001","000000","000","000","000","0000","00000","0000",'1'),-- ['[AA]->T'] + ("00","000","00","000","000","111000","000","000","000","0000","00000","0000",'0'),-- ['X->AAL'] + ("00","011","00","101","001","000000","000","000","000","0101","00100","0000",'1'),-- ['ALU(T,[20:AAL])->T', 'Flags'] + ("01","011","00","000","000","000000","000","000","000","0000","00000","0100",'1'),-- ['T->[20:AAL]'] + ("10","000","00","000","000","000000","000","000","000","0000","00000","0000",'0'),-- [] + -- 7A PLY + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- 7B + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- 7C JMP (ABS,X) + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- 7D ADC ABS,X + ("00","000","00","000","000","001000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->AAL', 'PC++'] + ("00","000","00","000","000","011001","001","000","000","0000","00000","0000",'1'),-- ['[PC]->AAH', 'PC++', 'AAL+X->AAL'] + ("00","000","00","000","000","000011","000","000","000","0000","00000","0000",'0'),-- ['AAH+AALCarry->AAH'] + ("00","001","00","000","001","000000","000","000","000","0000","00000","0000",'1'),-- ['[AA]->T'] + ("00","000","00","000","000","111000","000","000","000","0000","00000","0000",'0'),-- ['X->AAL'] + ("00","011","00","101","001","000000","000","000","000","0101","00100","0000",'1'),-- ['ALU(T,[20:AAL])->T', 'Flags'] + ("01","011","00","000","000","000000","000","000","000","0000","00000","0100",'1'),-- ['T->[20:AAL]'] + ("10","000","00","000","000","000000","000","000","000","0000","00000","0000",'0'),-- [] + -- 7E ROR ABS,X + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- 7F BBR7 + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- 80 BRA + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- 81 STA (ZP,X) + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- 82 CLX + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- 83 TST IMM,ZP + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- 84 STY ZP + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- 85 STA ZP + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- 86 STX ZP + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- 87 SMB0 + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- 88 DEY + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- 89 BIT IMM + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- 8A TXA + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- 8B + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- 8C STY ABS + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- 8D STA ABS + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- 8E STX ABS + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- 8F BBS0 + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- 90 BCC + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- 91 STA (ZP),Y + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- 92 STA (ZP) + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- 93 TST IMM,ABS + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- 94 STY ZP, X + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- 95 STA ZP,X + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- 96 STX ZP,Y + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- 97 SMB1 + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- 98 TYA + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- 99 STA ABS,Y + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- 9A TXS + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- 9B + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- 9C STZ ABS + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- 9D STA ABS,X + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- 9E STZ ABS,X + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- 9F BBS1 + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- A0 LDY IMM + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- A1 LDA (ZP,X) + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- A2 LDX IMM + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- A3 TST IMM,ZP,X + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- A4 LDY ZP + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- A5 LDA ZP + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- A6 LDX ZP + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- A7 SMB2 + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- A8 TAY + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- A9 LDA IMM + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- AA TAX + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- AB + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- AC LDY ABS + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- AD LDA ABS + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- AE LDX ABS + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- AF BBS2 + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- B0 BCS + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- B1 LDA (ZP),Y + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- B2 LDA (ZP) + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- B3 TST IMM,ABS,X + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- B4 LDY ZP, X + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- B5 LDA ZP, X + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- B6 LDX ZP, Y + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- B7 SMB3 + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- B8 CLV + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- B9 LDA ABS,Y + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- BA TSX + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- BB + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- BC LDY ABS,X + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- BD LDA ABS,X + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- BE LDX ABS,Y + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- BF BBS3 + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- C0 CPY IMM + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- C1 CMP (ZP,X) + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- C2 CLY + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- C3 TDD + ("00","000","00","000","000","000000","001","000","001","0000","00000","0000",'1'),-- ['[PC]->A', 'PC++'] + ("00","000","11","000","000","000000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->LH', 'PC++'] + ("00","000","00","000","000","000000","000","000","000","0000","00000","0000",'0'),-- [] + ("00","000","00","000","000","000000","000","000","000","0000","00000","0000",'0'),-- [] + ("00","000","00","000","000","000000","000","000","000","0001","00110","0000",'0'),-- ['ALU(A+/-1)->A'] + ("00","000","00","000","000","000000","000","000","000","1010","10000","0000",'0'),-- ['ALU(LH+/-C)->LH'] + ("00","110","00","000","100","000000","000","000","010","0010","00110","0000",'1'),-- ['[SH:X]->T', 'ALU(X+/-1)->X'] + ("00","000","01","000","000","000000","000","000","000","1000","10000","0000",'0'),-- ['ALU(SH+/-C)->SH'] + -- C4 CPY ZP + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- C5 CMP ZP + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- C6 DEC ZP + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- C7 SMB4 + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- C8 INY + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- C9 CMP IMM + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- CA DEX + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- CB + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- CC CPY ABS + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- CD CMP ABS + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- CE DEC ABS + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- CF BBS4 + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- D0 BNE + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- D1 CMP (ZP),Y + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- D2 CMP (ZP) + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- D3 TIN + ("00","000","00","000","000","000000","001","000","001","0000","00000","0000",'1'),-- ['[PC]->A', 'PC++'] + ("00","000","11","000","000","000000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->LH', 'PC++'] + ("00","000","00","000","000","000000","000","000","000","0000","00000","0000",'0'),-- [] + ("00","000","00","000","000","000000","000","000","000","0000","00000","0000",'0'),-- [] + ("00","000","00","000","000","000000","000","000","000","0001","00110","0000",'0'),-- ['ALU(A+/-1)->A'] + ("00","000","00","000","000","000000","000","000","000","1010","10000","0000",'0'),-- ['ALU(LH+/-C)->LH'] + ("00","110","00","000","100","000000","000","000","010","0010","00111","0000",'1'),-- ['[SH:X]->T', 'ALU(X+/-1)->X'] + ("00","000","01","000","000","000000","000","000","000","1000","10001","0000",'0'),-- ['ALU(SH+/-C)->SH'] + -- D4 CSH + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- D5 CMP ZP,X + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- D6 DEC ZP,X + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- D7 SMB5 + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- D8 CLD + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- D9 CMP ABS,Y + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- DA PHX + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- DB + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- DC + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- DD CMP ABS,X + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- DE DEC ABS,X + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- DF BBS5 + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- E0 CPX IMM + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- E1 SBC (ZP,X) + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- E2 + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- E3 TIA + ("00","000","00","000","000","000000","001","000","001","0000","00000","0000",'1'),-- ['[PC]->A', 'PC++'] + ("00","000","11","000","000","000000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->LH', 'PC++'] + ("00","000","00","000","000","000000","000","000","000","0000","00000","0000",'0'),-- [] + ("00","000","00","000","000","000000","000","000","000","0000","00000","0000",'0'),-- [] + ("00","000","00","000","000","000000","000","000","000","0001","00110","0000",'0'),-- ['ALU(A+/-1)->A'] + ("00","000","00","000","000","000000","000","000","000","1010","10000","0000",'0'),-- ['ALU(LH+/-C)->LH'] + ("00","110","00","000","100","000000","000","000","010","0010","00111","0000",'1'),-- ['[SH:X]->T', 'ALU(X+/-1)->X'] + ("00","000","01","000","000","000000","000","000","000","1000","10001","0000",'0'),-- ['ALU(SH+/-C)->SH'] + -- E4 CPX ZP + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- E5 SBC ZP + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- E6 INC ZP + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- E7 SMB6 + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- E8 INX + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- E9 SBC IMM + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- EA NOP + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- EB + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- EC CPX ABS + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- ED SBC ABS + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- EE INC ABS + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- EF BBS6 + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- F0 BEQ + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- F1 SBC (ZP),Y + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- F2 SBC (ZP) + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- F3 TAI + ("00","000","00","000","000","000000","001","000","001","0000","00000","0000",'1'),-- ['[PC]->A', 'PC++'] + ("00","000","11","000","000","000000","001","000","000","0000","00000","0000",'1'),-- ['[PC]->LH', 'PC++'] + ("00","000","00","000","000","000000","000","000","000","0000","00000","0000",'0'),-- [] + ("00","000","00","000","000","000000","000","000","000","0000","00000","0000",'0'),-- [] + ("00","000","00","000","000","000000","000","000","000","0001","00110","0000",'0'),-- ['ALU(A+/-1)->A'] + ("00","000","00","000","000","000000","000","000","000","1010","10000","0000",'0'),-- ['ALU(LH+/-C)->LH'] + ("00","110","00","000","100","000000","000","000","010","0010","00110","0000",'1'),-- ['[SH:X]->T', 'ALU(X+/-1)->X'] + ("00","000","01","000","000","000000","000","000","000","1000","10000","0000",'0'),-- ['ALU(SH+/-C)->SH'] + -- F4 SET + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- F5 SBC ZP,X + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- F6 INC ZP,X + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- F7 SMB7 + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- F8 SED + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- F9 SBC ABS,Y + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- FA PLX + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- FB + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- FC + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- FD SBC ABS,X + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- FE INC ABS,X + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- FF BBS7 + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X') + ); + + constant M_TAB3: MicroInst_t := ( + -- 00 BRK + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- 01 ORA (ZP,X) + ("10","011","00","000","000","000000","000","000","000","0000","00000","0100",'1'),-- ['T->[20:AAL]'] + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- 02 SXY + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- 03 ST0 + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- 04 TSB ZP + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- 05 ORA ZP + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- 06 ASL ZP + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- 07 RMB0 + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- 08 PHP + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- 09 ORA IMM / IMM,(X) + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- 0A ASL A + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- 0B + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- 0C TSB ABS + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- 0D ORA ABS + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- 0E ASL ABS + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- 0F BBR0 + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- 10 BPL + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- 11 ORA (ZP),Y + ("10","011","00","000","000","000000","000","000","000","0000","00000","0100",'1'),-- ['T->[20:AAL]'] + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- 12 ORA (ZP) + ("10","011","00","000","000","000000","000","000","000","0000","00000","0100",'1'),-- ['T->[20:AAL]'] + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- 13 ST1 + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- 14 TRB ZP + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- 15 ORA ZP,X + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- 16 ASL ZP,X + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- 17 RMB1 + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- 18 CLC + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- 19 ORA ABS,Y + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- 1A INC A + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- 1B + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- 1C TRB ABS + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- 1D ORA ABS,X + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- 1E ASL ABS,X + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- 1F BBR1 + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- 20 JSR ABS + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- 21 AND (ZP,X) + ("10","011","00","000","000","000000","000","000","000","0000","00000","0100",'1'),-- ['T->[20:AAL]'] + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- 22 SAX + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- 23 ST2 + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- 24 BIT ZP + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- 25 AND ZP + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- 26 ROL ZP + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- 27 RMB2 + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- 28 PLP + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- 29 AND IMM / IMM,(X) + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- 2A ROL A + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- 2B + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- 2C BIT ABS + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- 2D AND ABS + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- 2E ROL ABS + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- 2F BBR2 + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- 30 BMI + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- 31 AND (ZP),Y + ("10","011","00","000","000","000000","000","000","000","0000","00000","0100",'1'),-- ['T->[20:AAL]'] + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- 32 AND (ZP) + ("10","011","00","000","000","000000","000","000","000","0000","00000","0100",'1'),-- ['T->[20:AAL]'] + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- 33 + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- 34 BIT ZP,X + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- 35 AND ZP,X + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- 36 ROL ZP,X + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- 37 RMB3 + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- 38 SEC + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- 39 AND ABS,Y + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- 3A DEC A + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- 3B + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- 3C BIT ABS,X + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- 3D AND ABS,X + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- 3E ROL ABS,X + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- 3F BBR3 + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- 40 RTI + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- 41 EOR (ZP,X) + ("10","011","00","000","000","000000","000","000","000","0000","00000","0100",'1'),-- ['T->[20:AAL]'] + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- 42 SAY + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- 43 TMAi + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- 44 BSR + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- 45 EOR ZP + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- 46 LSR ZP + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- 47 RMB4 + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- 48 PHA + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- 49 EOR IMM / IMM,(X) + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- 4A LSR A + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- 4B + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- 4C JMP ABS + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- 4D EOR ABS + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- 4E LSR ABS + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- 4F BBR4 + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- 50 BVC + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- 51 EOR (ZP),Y + ("10","011","00","000","000","000000","000","000","000","0000","00000","0100",'1'),-- ['T->[20:AAL]'] + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- 52 EOR (ZP) + ("10","011","00","000","000","000000","000","000","000","0000","00000","0100",'1'),-- ['T->[20:AAL]'] + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- 53 TAMi + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- 54 CSL + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- 55 EOR ZP,X + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- 56 LSR ZP,X + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- 57 RMB5 + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- 58 CLI + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- 59 EOR ABS,Y + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- 5A PHY + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- 5B + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- 5C + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- 5D EOR ABS,X + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- 5E LSR ABS,X + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- 5F BBR5 + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- 60 RTS + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- 61 ADC (ZP,X) + ("01","011","00","000","000","000000","000","000","000","0000","00000","0100",'1'),-- ['T->[20:AAL]'] + ("10","000","00","000","000","000000","000","000","000","0000","00000","0000",'0'),-- [] + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- 62 CLA + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- 63 + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- 64 STZ ZP + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- 65 ADC ZP + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- 66 ROR ZP + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- 67 RMB6 + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- 68 PLA + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- 69 ADC IMM / IMM,(X) + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- 6A ROR A + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- 6B + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- 6C JMP (ABS) + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- 6D ADC ABS + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- 6E ROR ABS + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- 6F BBR6 + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- 70 BVS + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- 71 ADC (ZP),Y + ("01","011","00","000","000","000000","000","000","000","0000","00000","0100",'1'),-- ['T->[20:AAL]'] + ("10","000","00","000","000","000000","000","000","000","0000","00000","0000",'0'),-- [] + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- 72 ADC (ZP) + ("01","011","00","000","000","000000","000","000","000","0000","00000","0100",'1'),-- ['T->[20:AAL]'] + ("10","000","00","000","000","000000","000","000","000","0000","00000","0000",'1'),-- [] + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- 73 TII + ("00","111","00","000","000","000000","000","000","100","0011","00111","0100",'1'),-- ['T->[DH:Y]', 'ALU(Y+/-1)->Y'] + ("00","000","10","000","000","000000","000","000","000","1001","10001","0000",'0'),-- ['ALU(DH+/-C)->DH'] + ("00","000","00","000","000","000000","000","000","001","0001","00110","0000",'0'),-- ['ALU(A+/-1)->A'] + ("11","000","11","000","000","000000","000","000","000","1010","10000","0000",'0'),-- ['ALU(LH+/-C)->LH'] + ("00","010","00","000","000","000000","000","010","010","0000","00000","0000",'1'),-- ['ALU([21:SP])->X', 'SP++'] + ("00","010","00","000","000","000000","000","010","001","0000","00000","0000",'1'),-- ['ALU([21:SP])->A', 'SP++'] + ("10","010","00","000","000","000000","000","000","100","0000","00000","0000",'1'),-- ['ALU([21:SP])->Y'] + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- 74 STZ ZP,X + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- 75 ADC ZP,X + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- 76 ROR ZP,X + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- 77 RMB7 + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- 78 SEI + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- 79 ADC ABS,Y/ABS,Y,(X) + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- 7A PLY + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- 7B + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- 7C JMP (ABS,X) + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- 7D ADC ABS,X + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- 7E ROR ABS,X + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- 7F BBR7 + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- 80 BRA + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- 81 STA (ZP,X) + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- 82 CLX + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- 83 TST IMM,ZP + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- 84 STY ZP + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- 85 STA ZP + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- 86 STX ZP + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- 87 SMB0 + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- 88 DEY + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- 89 BIT IMM + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- 8A TXA + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- 8B + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- 8C STY ABS + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- 8D STA ABS + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- 8E STX ABS + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- 8F BBS0 + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- 90 BCC + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- 91 STA (ZP),Y + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- 92 STA (ZP) + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- 93 TST IMM,ABS + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- 94 STY ZP, X + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- 95 STA ZP,X + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- 96 STX ZP,Y + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- 97 SMB1 + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- 98 TYA + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- 99 STA ABS,Y + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- 9A TXS + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- 9B + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- 9C STZ ABS + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- 9D STA ABS,X + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- 9E STZ ABS,X + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- 9F BBS1 + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- A0 LDY IMM + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- A1 LDA (ZP,X) + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- A2 LDX IMM + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- A3 TST IMM,ZP,X + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- A4 LDY ZP + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- A5 LDA ZP + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- A6 LDX ZP + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- A7 SMB2 + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- A8 TAY + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- A9 LDA IMM + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- AA TAX + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- AB + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- AC LDY ABS + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- AD LDA ABS + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- AE LDX ABS + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- AF BBS2 + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- B0 BCS + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- B1 LDA (ZP),Y + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- B2 LDA (ZP) + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- B3 TST IMM,ABS,X + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- B4 LDY ZP, X + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- B5 LDA ZP, X + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- B6 LDX ZP, Y + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- B7 SMB3 + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- B8 CLV + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- B9 LDA ABS,Y + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- BA TSX + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- BB + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- BC LDY ABS,X + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- BD LDA ABS,X + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- BE LDX ABS,Y + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- BF BBS3 + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- C0 CPY IMM + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- C1 CMP (ZP,X) + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- C2 CLY + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- C3 TDD + ("00","111","00","000","000","000000","000","000","100","0011","00110","0100",'1'),-- ['T->[DH:Y]', 'ALU(Y+/-1)->Y'] + ("00","000","10","000","000","000000","000","000","000","1001","10000","0000",'0'),-- ['ALU(DH+/-C)->DH'] + ("00","000","00","000","000","000000","000","000","001","0001","00110","0000",'0'),-- ['ALU(A+/-1)->A'] + ("11","000","11","000","000","000000","000","000","000","1010","10000","0000",'0'),-- ['ALU(LH+/-C)->LH'] + ("00","010","00","000","000","000000","000","010","010","0000","00000","0000",'1'),-- ['ALU([21:SP])->X', 'SP++'] + ("00","010","00","000","000","000000","000","010","001","0000","00000","0000",'1'),-- ['ALU([21:SP])->A', 'SP++'] + ("10","010","00","000","000","000000","000","000","100","0000","00000","0000",'1'),-- ['ALU([21:SP])->Y'] + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- C4 CPY ZP + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- C5 CMP ZP + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- C6 DEC ZP + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- C7 SMB4 + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- C8 INY + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- C9 CMP IMM + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- CA DEX + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- CB + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- CC CPY ABS + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- CD CMP ABS + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- CE DEC ABS + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- CF BBS4 + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- D0 BNE + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- D1 CMP (ZP),Y + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- D2 CMP (ZP) + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- D3 TIN + ("00","111","00","000","000","000000","000","000","000","0000","00000","0100",'1'),-- ['T->[DH:Y]'] + ("00","000","00","000","000","000000","000","000","000","0000","00000","0000",'0'),-- [] + ("00","000","00","000","000","000000","000","000","001","0001","00110","0000",'0'),-- ['ALU(A+/-1)->A'] + ("11","000","11","000","000","000000","000","000","000","1010","10000","0000",'0'),-- ['ALU(LH+/-C)->LH'] + ("00","010","00","000","000","000000","000","010","010","0000","00000","0000",'1'),-- ['ALU([21:SP])->X', 'SP++'] + ("00","010","00","000","000","000000","000","010","001","0000","00000","0000",'1'),-- ['ALU([21:SP])->A', 'SP++'] + ("10","010","00","000","000","000000","000","000","100","0000","00000","0000",'1'),-- ['ALU([21:SP])->Y'] + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- D4 CSH + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- D5 CMP ZP,X + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- D6 DEC ZP,X + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- D7 SMB5 + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- D8 CLD + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- D9 CMP ABS,Y + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- DA PHX + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- DB + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- DC + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- DD CMP ABS,X + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- DE DEC ABS,X + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- DF BBS5 + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- E0 CPX IMM + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- E1 SBC (ZP,X) + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- E2 + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- E3 TIA + ("00","111","00","000","000","000000","000","000","100","0011","00110","0100",'1'),-- ['T->[DH:Y]', 'ALU(Y+/-1)->Y'] + ("00","000","10","000","000","000000","000","000","000","1001","10000","0000",'0'),-- ['ALU(DH+/-C)->DH'] + ("00","000","00","000","000","000000","000","000","001","0001","00110","0000",'0'),-- ['ALU(A+/-1)->A'] + ("11","000","11","000","000","000000","000","000","000","1010","10000","0000",'0'),-- ['ALU(LH+/-C)->LH'] + ("00","010","00","000","000","000000","000","010","010","0000","00000","0000",'1'),-- ['ALU([21:SP])->X', 'SP++'] + ("00","010","00","000","000","000000","000","010","001","0000","00000","0000",'1'),-- ['ALU([21:SP])->A', 'SP++'] + ("10","010","00","000","000","000000","000","000","100","0000","00000","0000",'1'),-- ['ALU([21:SP])->Y'] + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- E4 CPX ZP + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- E5 SBC ZP + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- E6 INC ZP + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- E7 SMB6 + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- E8 INX + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- E9 SBC IMM + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- EA NOP + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- EB + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- EC CPX ABS + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- ED SBC ABS + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- EE INC ABS + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- EF BBS6 + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- F0 BEQ + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- F1 SBC (ZP),Y + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- F2 SBC (ZP) + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- F3 TAI + ("00","111","00","000","000","000000","000","000","100","0011","00111","0100",'1'),-- ['T->[DH:Y]', 'ALU(Y+/-1)->Y'] + ("00","000","10","000","000","000000","000","000","000","1001","10001","0000",'0'),-- ['ALU(DH+/-C)->DH'] + ("00","000","00","000","000","000000","000","000","001","0001","00110","0000",'0'),-- ['ALU(A+/-1)->A'] + ("11","000","11","000","000","000000","000","000","000","1010","10000","0000",'0'),-- ['ALU(LH+/-C)->LH'] + ("00","010","00","000","000","000000","000","010","010","0000","00000","0000",'1'),-- ['ALU([21:SP])->X', 'SP++'] + ("00","010","00","000","000","000000","000","010","001","0000","00000","0000",'1'),-- ['ALU([21:SP])->A', 'SP++'] + ("10","010","00","000","000","000000","000","000","100","0000","00000","0000",'1'),-- ['ALU([21:SP])->Y'] + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- F4 SET + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- F5 SBC ZP,X + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- F6 INC ZP,X + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- F7 SMB7 + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- F8 SED + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- F9 SBC ABS,Y + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- FA PLX + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- FB + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- FC + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- FD SBC ABS,X + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- FE INC ABS,X + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + -- FF BBS7 + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X'), + ("XX","XXX","XX","XXX","XXX","XXXXXX","XXX","XXX","XXX","XXXX","XXXXX","XXXX",'X') + ); + + type ALUCtrl_t is array(0 to 17) of ALUCtrl_r; + constant ALU_TAB: ALUCtrl_t := ( + ("100","100",'0'),-- 00000 LOAD + ("100","001",'0'),-- 00001 AND + ("100","000",'0'),-- 00010 ORA + ("100","010",'0'),-- 00011 EOR + ("100","011",'0'),-- 00100 ADC + ("100","111",'1'),-- 00101 SBC + ("110","111",'0'),-- 00110 DEC + ("110","011",'0'),-- 00111 INC + ("000","100",'0'),-- 01000 ASL + ("010","100",'0'),-- 01001 LSR + ("001","100",'0'),-- 01010 ROL + ("011","100",'0'),-- 01011 ROR + ("100","001",'1'),-- 01100 BIT + ("100","101",'0'),-- 01101 TRB + ("100","101",'1'),-- 01110 TSB + ("100","110",'0'),-- 01111 CMP + ("111","111",'0'),-- 10000 DEC16 + ("111","011",'0') -- 10001 INC16 + ); + + + signal MI : MicroInst_r; + signal ALUFlags : ALUCtrl_r; + +begin + + ALUFlags <= ALU_TAB(to_integer(unsigned(MI.ALUCtrl))); + + process(CLK, RST_N) + variable N : unsigned(10 downto 0); + begin + if RST_N = '0' then + MI <= ("00","000","00","000","000","000000","001","000","000","0000","00000","0000",'1'); + elsif rising_edge(CLK) then + if EN = '1' then + N := unsigned(IR)&STATE(2 downto 0); + if STATE = "00000" then + MI <= ("00","000","00","000","000","000000","001","000","000","0000","00000","0000",'1'); + elsif STATE(4 downto 3) = "00" then + MI <= M_TAB1(to_integer(N)); + elsif STATE(4 downto 3) = "01" then + MI <= M_TAB2(to_integer(N)); + elsif STATE(4 downto 3) = "10" then + MI <= M_TAB3(to_integer(N)); + end if; + end if; + end if; + end process; + + M <= (MI.STATE_CTRL, + MI.ADDR_BUS, + MI.LOAD_SDLH, + MI.LOAD_P, + MI.LOAD_T, + MI.ADDR_CTRL, + MI.LOAD_PC, + MI.LOAD_SP, + MI.AXY_CTRL, + MI.ALUBUS_CTRL, + MI.OUT_BUS, + MI.MEM_CYCLE, + ALUFlags); + + +end rtl; \ No newline at end of file diff --git a/snapshots/jotego_jtcores_pr1242/modules/HUC6280/hdl/HUC6280_PKG.vhd b/snapshots/jotego_jtcores_pr1242/modules/HUC6280/hdl/HUC6280_PKG.vhd new file mode 100644 index 0000000000000000000000000000000000000000..088881922263c4360d0e72b386029143f7a14bf3 --- /dev/null +++ b/snapshots/jotego_jtcores_pr1242/modules/HUC6280/hdl/HUC6280_PKG.vhd @@ -0,0 +1,61 @@ +library IEEE; +use IEEE.std_logic_1164.all; +use ieee.numeric_std.all; + +package HUC6280_PKG is + + type MicroInst_r is record + STATE_CTRL : std_logic_vector(1 downto 0); + ADDR_BUS : std_logic_vector(2 downto 0); + LOAD_SDLH : std_logic_vector(1 downto 0); + LOAD_P : std_logic_vector(2 downto 0); + LOAD_T : std_logic_vector(2 downto 0); + ADDR_CTRL : std_logic_vector(5 downto 0); + LOAD_PC : std_logic_vector(2 downto 0); + LOAD_SP : std_logic_vector(2 downto 0); + AXY_CTRL : std_logic_vector(2 downto 0); + ALUBUS_CTRL : std_logic_vector(3 downto 0); + ALUCtrl : std_logic_vector(4 downto 0); + OUT_BUS : std_logic_vector(3 downto 0); + MEM_CYCLE : std_logic; + end record; + + type ALUCtrl_r is record + fstOp : std_logic_vector(2 downto 0); + secOp : std_logic_vector(2 downto 0); + fc : std_logic; + end record; + + type MCode_r is record + STATE_CTRL : std_logic_vector(1 downto 0); + ADDR_BUS : std_logic_vector(2 downto 0); + LOAD_SDLH : std_logic_vector(1 downto 0); + LOAD_P : std_logic_vector(2 downto 0); + LOAD_T : std_logic_vector(2 downto 0); + ADDR_CTRL : std_logic_vector(5 downto 0); + LOAD_PC : std_logic_vector(2 downto 0); + LOAD_SP : std_logic_vector(2 downto 0); + AXY_CTRL : std_logic_vector(2 downto 0); + ALUBUS_CTRL : std_logic_vector(3 downto 0); + OUT_BUS : std_logic_vector(3 downto 0); + MEM_CYCLE : std_logic; + ALU_CTRL : ALUCtrl_r; + end record; + + constant FLAG_C : integer := 0; + constant FLAG_Z : integer := 1; + constant FLAG_I : integer := 2; + constant FLAG_D : integer := 3; + constant FLAG_B : integer := 4; + constant FLAG_T : integer := 5; + constant FLAG_V : integer := 6; + constant FLAG_N : integer := 7; + + type MPR_t is array(0 to 7) of std_logic_vector(7 downto 0); + +end HUC6280_PKG; + +package body HUC6280_PKG is + + +end package body HUC6280_PKG; diff --git a/snapshots/jotego_jtcores_pr1242/modules/jt007232/cfg/files.yaml b/snapshots/jotego_jtcores_pr1242/modules/jt007232/cfg/files.yaml new file mode 100644 index 0000000000000000000000000000000000000000..31384ff9c8f1134a2bd13d13b15f23147ad41044 --- /dev/null +++ b/snapshots/jotego_jtcores_pr1242/modules/jt007232/cfg/files.yaml @@ -0,0 +1,3 @@ +jt007232: + - get: + - "*.v" \ No newline at end of file diff --git a/snapshots/jotego_jtcores_pr1242/modules/jt007232/doc/k007232.cpp b/snapshots/jotego_jtcores_pr1242/modules/jt007232/doc/k007232.cpp new file mode 100644 index 0000000000000000000000000000000000000000..9b4bc9e4b1655100568e2b630fb1759b9fb112b5 --- /dev/null +++ b/snapshots/jotego_jtcores_pr1242/modules/jt007232/doc/k007232.cpp @@ -0,0 +1,290 @@ +// license:BSD-3-Clause +// copyright-holders:Nicola Salmoria,Hiromitsu Shioya +/*********************************************************/ +/* Konami PCM controller */ +/*********************************************************/ + +/* + Changelog, Hiromitsu Shioya 02/05/2002 + fixed start address decode timing. (sample loop bug.) + + Changelog, Mish, August 1999: + Removed interface support for different memory regions per channel. + Removed interface support for differing channel volume. + + Added bankswitching. + Added support for multiple chips. + + (NB: Should different memory regions per channel be needed, the bankswitching function can set this up). + + Chanelog, Nicola, August 1999: + Added Support for the k007232_VOL() macro. + Added external port callback, and functions to set the volume of the channels +*/ + + +#include "emu.h" +#include "k007232.h" +#include "wavwrite.h" +#include + +#define K007232_LOG_PCM (0) + +DEFINE_DEVICE_TYPE(K007232, k007232_device, "k007232", "K007232 PCM Controller") + +k007232_device::k007232_device(const machine_config &mconfig, const char *tag, device_t *owner, u32 clock) + : device_t(mconfig, K007232, tag, owner, clock) + , device_sound_interface(mconfig, *this) + , device_memory_interface(mconfig, *this) + , m_data_config("data", ENDIANNESS_LITTLE, 8, 17) // 17 bit address, 8 bit data, can be bankswitched per each voices + , m_rom(*this, DEVICE_SELF) + , m_pcmlimit(~0) + , m_bank(0) + , m_stream(nullptr) + , m_port_write_handler(*this) +{ + std::fill(std::begin(m_wreg), std::end(m_wreg), 0); +} + +//------------------------------------------------- +// device_start - device-specific startup +//------------------------------------------------- + +void k007232_device::device_start() +{ + // assumes it can make an address mask with m_rom.length() - 1 + assert (!m_rom.found() || !(m_rom.length() & (m_rom.length() - 1))); + + m_pcmlimit = 1 << 17; + // default mapping (bankswitched ROM) + if (m_rom.found() && !has_configured_map(0)) + { + if (m_rom.bytes() > 0x20000) + space(0).install_read_handler(0x00000, std::min(0x1ffff, m_rom.bytes() - 1), read8sm_delegate(*this, FUNC(k007232_device::read_rom_default))); + else + { + space(0).install_rom(0x00000, m_rom.length() - 1, m_rom.target()); + m_pcmlimit = m_rom.bytes(); + } + } + space(0).cache(m_cache); + + /* Set up the chips */ + m_port_write_handler.resolve_safe(); + + for (int i = 0; i < KDAC_A_PCM_MAX; i++) + { + m_channel[i].addr = 0; + m_channel[i].start = 0; + m_channel[i].counter = 0x1000; + m_channel[i].step = 0; + m_channel[i].play = 0; + m_channel[i].bank = 0; + } + m_channel[0].vol[0] = 255; /* channel A output to output A */ + m_channel[0].vol[1] = 0; + m_channel[1].vol[0] = 0; + m_channel[1].vol[1] = 255; /* channel B output to output B */ + + for (auto & elem : m_wreg) + elem = 0; + + m_stream = stream_alloc(0, 2, clock()/128); + + save_item(STRUCT_MEMBER(m_channel, vol)); + save_item(STRUCT_MEMBER(m_channel, addr)); + save_item(STRUCT_MEMBER(m_channel, counter)); + save_item(STRUCT_MEMBER(m_channel, start)); + save_item(STRUCT_MEMBER(m_channel, step)); + save_item(STRUCT_MEMBER(m_channel, bank)); + save_item(STRUCT_MEMBER(m_channel, play)); + save_item(NAME(m_wreg)); +} + +//------------------------------------------------- +// device_clock_changed - called if the clock +// changes +//------------------------------------------------- + +void k007232_device::device_clock_changed() +{ + m_stream->set_sample_rate(clock()/128); +} + +//------------------------------------------------- +// memory_space_config - return a description of +// any address spaces owned by this device +//------------------------------------------------- + +device_memory_interface::space_config_vector k007232_device::memory_space_config() const +{ + return space_config_vector{ std::make_pair(0, &m_data_config) }; +} + +/************************************************/ +/* Konami PCM write register */ +/************************************************/ + +void k007232_device::write(offs_t offset, u8 data) +{ + m_stream->update(); + + m_wreg[offset] = data; // standard data write + + if (offset == 12) + { + // external port, usually volume control + m_port_write_handler(0, data); + } + else if (offset == 13) + { + // loop flag, handled by standard data write + } + else + { + channel_t *channel = &m_channel[(offset >= 6 ? 1 : 0)]; + int reg_index = (offset >= 6 ? 6 : 0); + if (offset >= 6) + offset -= 6; + + switch (offset) + { + case 0: // address step, LSB + case 1: // address step, MSB + channel->step = (BIT(m_wreg[reg_index + 1], 0, 4) << 8) | m_wreg[reg_index]; + // TODO: Bit 4-5 is frequency divider, but not implemented now + break; + case 2: + case 3: + case 4: + // working data for start address + channel->start = (BIT(m_wreg[reg_index + 4], 0) << 16) | (m_wreg[reg_index + 3] << 8) | m_wreg[reg_index + 2]; + break; + case 5: // start address + if (channel->start < m_pcmlimit) + { + channel->play = true; + channel->addr = channel->start; + channel->counter = 0x1000; + } + break; + } + } +} + +/************************************************/ +/* Konami PCM read register */ +/************************************************/ + +u8 k007232_device::read(offs_t offset) +{ + if (offset == 5 || offset == 11) + { + channel_t *channel = &m_channel[(offset == 11) ? 1 : 0]; + + if (channel->start < m_pcmlimit) + { + channel->play = true; + channel->addr = channel->start; + channel->counter = 0x1000; + } + } + return 0; +} + +/*****************************************************************************/ + +void k007232_device::set_volume(int channel, int vol_a, int vol_b) +{ + m_channel[channel].vol[0] = vol_a; + m_channel[channel].vol[1] = vol_b; +} + +void k007232_device::set_bank(int chan_a_bank, int chan_b_bank) +{ + m_channel[0].bank = chan_a_bank << 17; + m_channel[1].bank = chan_b_bank << 17; +} + +/*****************************************************************************/ + + +//------------------------------------------------- +// sound_stream_update - handle a stream update +//------------------------------------------------- + +void k007232_device::sound_stream_update(sound_stream &stream, std::vector const &inputs, std::vector &outputs) +{ + if (K007232_LOG_PCM) + { + for (int i = 0; i < KDAC_A_PCM_MAX; i++) + { + channel_t *channel = &m_channel[i]; + if (channel->play) + { + char filebuf[256]; + snprintf(filebuf, 256, "pcm%08x.wav", channel->start); + util::wav_file_ptr file = util::wav_open(filebuf, stream.sample_rate(), 1); + if (file) + { + u32 addr = channel->start; + while (!BIT(read_sample(i, addr), 7) && addr < m_pcmlimit) + { + int16_t out = ((read_sample(i, addr) & 0x7f) - 0x40) << 7; + util::wav_add_data_16(*file, &out, 1); + addr++; + } + } + } + } + } + + for (int j = 0; j < outputs[0].samples(); j++) + { + s32 lsum = 0, rsum = 0; + for (int i = 0; i < KDAC_A_PCM_MAX; i++) + { + channel_t *channel = &m_channel[i]; + if (channel->play) + { + /**** PCM setup ****/ + int vol_a = channel->vol[0] * 2; + int vol_b = channel->vol[1] * 2; + + u32 addr = channel->addr & 0x1ffff; + while (channel->counter <= channel->step) // result : clock / (4 * (4096 - frequency)) + { + if (BIT(read_sample(i, addr++), 7) || addr >= m_pcmlimit) + { + // end of sample + if (BIT(m_wreg[13], i)) + { + /* loop to the beginning */ + addr = channel->start; + } + else + { + /* stop sample */ + channel->play = false; + break; + } + } + channel->counter += (0x1000 - channel->step); + } + channel->addr = addr; + + if (!channel->play) + break; + + channel->counter -= 32; + + int out = (read_sample(i, addr) & 0x7f) - 0x40; + + lsum += out * vol_a; + rsum += out * vol_b; + } + } + outputs[0].put_int(j, lsum, 32768); + outputs[1].put_int(j, rsum, 32768); + } +} diff --git a/snapshots/jotego_jtcores_pr1242/modules/jt007232/hdl/jt007232.v b/snapshots/jotego_jtcores_pr1242/modules/jt007232/hdl/jt007232.v new file mode 100644 index 0000000000000000000000000000000000000000..6acc8b6b7df2b1488d1b20c6d280c796fb9cfcf6 --- /dev/null +++ b/snapshots/jotego_jtcores_pr1242/modules/jt007232/hdl/jt007232.v @@ -0,0 +1,237 @@ +/* This file is part of JTCORES. + JTCORES program is free software: you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation, either version 3 of the License, or + (at your option) any later version. + + JTCORES program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with JTCORES. If not, see . + + Author: Jose Tejada Gomez. Twitter: @topapate + Version: 1.0 + Date: 24-8-2021 */ + +// RAM-write operation is not implemented +// 2-channel PCM. The two channels connect to the same +// external ROM. The connections are separated for convenience +// in this implementation + +// This chip seems to be usually hooked to a rough resistor DAC for +// channel volume. The DAC is made of four resistors which are not linear +// 24k, 40k, 100k, 200k (instead of 25, 50, 100, 200). This creates a small +// lineary error. Converting the DAC gain to an 8-bit number: +// Code Real Ideal Error +// 0 0 0 0 +// 1 16 17 -1 +// 2 31 34 -3 +// 3 47 51 -4 +// 4 78 68 10 +// 5 94 85 9 +// 6 109 102 7 +// 7 125 119 6 +// 8 130 136 -6 +// 9 146 153 -7 +// 10 161 170 -9 +// 11 177 187 -10 +// 12 208 204 4 +// 13 224 221 3 +// 14 239 238 1 +// 15 255 255 0 +// This is specially bad in the code 7 to 8 transition +// I am not modelling this effect as the music probably sounds better +// using the linear model rather than the *authentic* one +// It is also used with a proper R2R ladder in some games, like Haunted Castle +// so the response is linear for those ones + +module jt007232( + input rst, + input clk, + input cen, + input [ 3:0] addr, + // RAM ports not implemented + // input nrcs, + // input nrd, + input dacs, // active high + input wr_n, // not a pin on the original + input [ 7:0] din, + // output cen_2m,// equivalent to ck2m pin -- not implemented + output reg cen_q, // equivalent to NE pin + output reg cen_e, // equivalent to NQ pin + // output [ 7:0] dout, + input swap_gains, // makes ^ with REG12A below + + // External memory - the original chip + // only had one bus + output [16:0] roma_addr, + input [ 7:0] roma_dout, + output roma_cs, + input roma_ok, + + output [16:0] romb_addr, + input [ 7:0] romb_dout, + output romb_cs, + input romb_ok, + // sound output - scaled by register 12 + output signed [10:0] snda, + output signed [10:0] sndb, + output signed [10:0] snd, + // debug + input [ 7:0] debug_bus, + output reg [ 7:0] st_dout +); + +parameter REG12A=1, // location of CHA gain, the gain device is external to the + // chip. There is normally an 8-bit latch attached. It holds + // the value at mmr[12], which isn't internal but just sets + // the SLEV pin when set. + // MX5000 uses the upper nibble for channel A, but + // aliens uses the lower. + INVA0 =0, // invert A0? The real chip did, we don't by default + NOGAIN=0; // Set to 1 to output the raw channel sign-extended to 11 bits + // in order to apply gain externally. See use case in ajax + +reg [7:0] mmr[0:13]; // Not all bits are used + +wire signed [ 6:0] rawa, rawb; +// Channel A control +wire [11:0] cha_pres = { mmr[1][3:0], mmr[0] }; +wire [16:0] cha_addr = { mmr[4][0], mmr[3], mmr[2] }; +wire [ 1:0] cha_presel = mmr[1][5:4]; +reg cha_play, cha_load; +wire peak; +wire cha_loop = mmr[13][0]; + +// Channel B control +wire [11:0] chb_pres = { mmr[7][3:0], mmr[6] }; +wire [16:0] chb_addr = { mmr[10][0], mmr[9], mmr[8] }; +wire [ 1:0] chb_presel = mmr[7][5:4]; +reg chb_play, chb_load; +wire chb_loop = mmr[13][1]; + +wire [3:0] addrj = INVA0==1 ? (addr^4'b1) : addr; // addr LSB may be inverted + +jt007232_gain #(.REG12A(REG12A),.NOGAIN(NOGAIN)) u_gain( + .clk ( clk ), + .reg12 ( mmr[12] ), + .swap_gains ( swap_gains ), + .rawa ( rawa ), + .rawb ( rawb ), + .snda ( snda ), + .sndb ( sndb ) +); + +jtframe_limsum #(.WI(11),.K(2)) u_limsum( + .rst ( rst ), + .clk ( clk ), + .cen ( 1'b1 ), + .en ( 2'b11 ), + .parts ( {snda, sndb } ), + .sum ( snd ), + .peak ( peak ) +); + +always @(posedge clk, posedge rst) begin + if( rst ) begin + mmr[ 0] <= 0; mmr[ 1] <= 0; mmr[ 2] <= 0; mmr[ 3] <= 0; + mmr[ 4] <= 0; mmr[ 5] <= 0; mmr[ 6] <= 0; mmr[ 7] <= 0; + mmr[ 8] <= 0; mmr[ 9] <= 0; mmr[10] <= 0; mmr[11] <= 0; + mmr[12] <= 0; mmr[13] <= 0; + cha_play <= 0; + chb_play <= 0; + st_dout <= 0; + end else begin + cha_load <= 0; + chb_load <= 0; + if( dacs && !wr_n ) begin + mmr[ addrj ] <= din; + cha_load <= addrj==0 || addrj==1; + chb_load <= addrj==6 || addrj==7; + end + cha_play <= dacs && addrj==5; + chb_play <= dacs && addrj==11; + st_dout <= mmr[debug_bus[3:0]]; + end +end + +// E/Q clocks, these are M6809 clocks, E and Q operate at 1/4 of clk +// E is 90º ahead of Q +// Here, I only generate two clock enable signals in opposite phases +// RAM access is done originally when E is low +// Here, RAM access is done when E is high + +reg [1:0] cen_cnt; + +always @(posedge clk, posedge rst) begin + if( rst ) begin + cen_e <= 0; + cen_q <= 0; + cen_cnt <= 0; + end else begin + if(cen) cen_cnt <= cen_cnt+1'd1; + cen_e <= cen && cen_cnt==3; + cen_q <= cen && cen_cnt==1; + end +end + +// reg [7:0] div_cnt; +// reg cen_div; +// +// always @(posedge clk, posedge rst) begin +// if( rst ) begin +// div_cnt <= 0; +// cen_div <= 0; +// end else begin +// if( cen ) div_cnt <= div_cnt + 1'd1; +// cen_div <= cen && (&div_cnt); +// end +// end + +// it looks like the clock isn't q/2 but q +// contrary to Furrtek's RE + +jt007232_channel u_cha( + .rst ( rst ), + .clk ( clk ), + .cen_q ( cen_q ), + // control from MMR + .rom_start ( cha_addr ), + .pre0 ( cha_pres ), + .pre_sel ( cha_presel), + .loop ( cha_loop ), + .play ( cha_play ), + .load ( cha_load ), + + .rom_addr ( roma_addr ), + .rom_cs ( roma_cs ), + .rom_ok ( roma_ok ), + .rom_dout ( roma_dout ), + .snd ( rawa ) +); + +jt007232_channel u_chb( + .rst ( rst ), + .clk ( clk ), + .cen_q ( cen_q ), + // control from MMR + .rom_start ( chb_addr ), + .pre0 ( chb_pres ), + .pre_sel ( chb_presel), + .loop ( chb_loop ), + .play ( chb_play ), + .load ( chb_load ), + + .rom_addr ( romb_addr ), + .rom_cs ( romb_cs ), + .rom_ok ( romb_ok ), + .rom_dout ( romb_dout ), + .snd ( rawb ) +); + + +endmodule + diff --git a/snapshots/jotego_jtcores_pr1242/modules/jt007232/hdl/jt007232_channel.v b/snapshots/jotego_jtcores_pr1242/modules/jt007232/hdl/jt007232_channel.v new file mode 100644 index 0000000000000000000000000000000000000000..ed9aab1a198f611680d780cba0e8cdfbcc2be4e2 --- /dev/null +++ b/snapshots/jotego_jtcores_pr1242/modules/jt007232/hdl/jt007232_channel.v @@ -0,0 +1,98 @@ +/* This file is part of JTCORES. + JTCORES program is free software: you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation, either version 3 of the License, or + (at your option) any later version. + + JTCORES program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with JTCORES. If not, see . + + Author: Jose Tejada Gomez. Twitter: @topapate + Version: 1.0 + Date: 24-8-2021 */ + +// playback is delayed by one sample to ease the ROM interface +module jt007232_channel( + input rst, + input clk, + input cen_q, + // control from MMR + input [16:0] rom_start, + input [11:0] pre0, + input [ 1:0] pre_sel, + input loop, + input play, + input load, + + output reg [16:0] rom_addr, + output rom_cs, + input rom_ok, + input [ 7:0] rom_dout, + output reg signed [6:0] snd +); + +parameter [6:0] OFFSET='h40; + +reg [11:0] cnt; +wire over; +reg busy, playl; + +// counter length is set by an MMR +assign over = pre_sel[0] ? (&cnt[7:0]) : (pre_sel[1] ? (&cnt[11:8]) : (&cnt)); +assign rom_cs = busy; + +always @(posedge clk, posedge rst) begin + if( rst ) begin + cnt <= 0; + busy <= 0; + snd <= 0; + rom_addr <= 0; + end else begin + playl <= play; + if( cen_q ) begin + if( over ) begin + cnt <= pre0; + if( busy ) begin + if( pre_sel[1] ) begin + rom_addr[ 3: 0] <= rom_addr[ 3: 0] + 1'd1; + rom_addr[ 7: 4] <= rom_addr[ 7: 4] + 1'd1; + rom_addr[11: 8] <= rom_addr[11: 8] + 1'd1; + rom_addr[16:12] <= rom_addr[16:12] + 1'd1; + end else begin + rom_addr <= rom_addr + 1'd1; + end + snd <= rom_dout[6:0]-OFFSET; + if( rom_dout[7] ) begin + if( loop ) + rom_addr <= rom_start; + else + busy <= 0; + end + end + end else begin + if( pre_sel[1] ) begin + cnt[ 7:0] <= cnt[ 7:0]+1'd1; + cnt[11:8] <= cnt[11:8]+1'd1; + end else begin + cnt <= cnt + 1'd1; + end + end + end + if( play && !playl ) begin + busy <= 1; + rom_addr <= rom_start; + end + if( load ) begin + cnt <= pre0; + end + if(!busy) snd <= 0; + end +end + + +endmodule \ No newline at end of file diff --git a/snapshots/jotego_jtcores_pr1242/modules/jt007232/hdl/jt007232_gain.v b/snapshots/jotego_jtcores_pr1242/modules/jt007232/hdl/jt007232_gain.v new file mode 100644 index 0000000000000000000000000000000000000000..5b5f6eb026f3ee3bba5788c31ccb77c8fabe8cb5 --- /dev/null +++ b/snapshots/jotego_jtcores_pr1242/modules/jt007232/hdl/jt007232_gain.v @@ -0,0 +1,43 @@ +/* This file is part of JTCORES. + JTCORES program is free software: you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation, either version 3 of the License, or + (at your option) any later version. + + JTCORES program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with JTCORES. If not, see . + + Author: Jose Tejada Gomez. Twitter: @topapate + Version: 1.0 + Date: 24-8-2021 */ + +module jt007232_gain( + input clk, + input swap_gains, // makes ^ with REG12A below + input [ 7:0] reg12, + input signed [ 6:0] rawa, rawb, + output reg signed [10:0] snda, sndb +); + +parameter REG12A=1, NOGAIN=0; + +wire signed [ 4:0] cha_gain = {1'b0, (REG12A[0]^swap_gains) ? reg12[7:4] : reg12[3:0] }; +wire signed [ 4:0] chb_gain = {1'b0, ~(REG12A[0]^swap_gains) ? reg12[7:4] : reg12[3:0] }; +reg signed [11:0] mula, mulb; + +always @(posedge clk) begin + if(NOGAIN==1) begin + snda <= {{4{rawa[6]}},rawa}; + sndb <= {{4{rawb[6]}},rawb}; + end else begin + snda <= rawa * cha_gain; + sndb <= rawb * chb_gain; + end +end + +endmodule \ No newline at end of file diff --git a/snapshots/jotego_jtcores_pr1242/modules/jt007232/ver/channel/.simunit b/snapshots/jotego_jtcores_pr1242/modules/jt007232/ver/channel/.simunit new file mode 100644 index 0000000000000000000000000000000000000000..e69de29bb2d1d6434b8b29ae775ad8c2e48c5391 diff --git a/snapshots/jotego_jtcores_pr1242/modules/jt007232/ver/channel/gather.f b/snapshots/jotego_jtcores_pr1242/modules/jt007232/ver/channel/gather.f new file mode 100644 index 0000000000000000000000000000000000000000..a5c166ad4a310b3c38271c5d812f6fcfd5d03d6c --- /dev/null +++ b/snapshots/jotego_jtcores_pr1242/modules/jt007232/ver/channel/gather.f @@ -0,0 +1 @@ +../../hdl/jt007232_channel.v diff --git a/snapshots/jotego_jtcores_pr1242/modules/jt007232/ver/channel/test.v b/snapshots/jotego_jtcores_pr1242/modules/jt007232/ver/channel/test.v new file mode 100644 index 0000000000000000000000000000000000000000..9239bf6cd9bfbc27d5a2c0cb082691947a83c2b0 --- /dev/null +++ b/snapshots/jotego_jtcores_pr1242/modules/jt007232/ver/channel/test.v @@ -0,0 +1,68 @@ +module test; + +localparam W=7; //8 +localparam OFF=64; + +reg clk, rst; +reg [7:0] dout; +reg play; +wire signed [W-1:0] snd_out; + +/* +initial begin + $dumpfile("test.lxt"); + $dumpvars; + $dumpon; + #10000000 $finish; +end +*/ + +initial begin + clk=0; + forever #10 clk=~clk; +end + +integer snd_in=0,exp; + +initial begin + rst = 1; + play = 0; + dout=0; + repeat (20) @(posedge clk); + rst = 0; + @(posedge clk) + play = 1; + for(snd_in=0;snd_in<128;snd_in=snd_in+1) begin + dout=snd_in[7:0]; + repeat (2) @(posedge clk); + exp = snd_in - OFF; + @(posedge clk); + if( {{32-W{snd_out[W-1]}},snd_out}!=exp) begin + $display("Bad signed value at rom_dout %d",dout); + $display("output vs expected: %d <> %d",snd_out,exp); + $display("FAIL"); + $finish; + end + end + $display("PASS"); + $finish; +end + +jt007232_channel uut( + .rst ( rst ), + .clk ( clk ), + .cen_q ( 1'b1 ), + .rom_start ( 17'h0 ), + .pre0 ( 12'hFFF ), + .pre_sel ( 2'b0 ), + .loop ( 1'b1 ), + .play ( play ), + .load ( 1'b1 ), + .rom_addr ( ), + .rom_cs ( ), + .rom_ok ( 1'b1 ), + .rom_dout ( dout ), + .snd ( snd_out ) +); + +endmodule \ No newline at end of file diff --git a/snapshots/jotego_jtcores_pr1242/modules/jt007232/ver/gain/.simunit b/snapshots/jotego_jtcores_pr1242/modules/jt007232/ver/gain/.simunit new file mode 100644 index 0000000000000000000000000000000000000000..e69de29bb2d1d6434b8b29ae775ad8c2e48c5391 diff --git a/snapshots/jotego_jtcores_pr1242/modules/jt007232/ver/gain/gather.f b/snapshots/jotego_jtcores_pr1242/modules/jt007232/ver/gain/gather.f new file mode 100644 index 0000000000000000000000000000000000000000..80a8b487531eb5d4e8eceb45fc1fd14f9f97c9ce --- /dev/null +++ b/snapshots/jotego_jtcores_pr1242/modules/jt007232/ver/gain/gather.f @@ -0,0 +1 @@ +../../hdl/jt007232_gain.v diff --git a/snapshots/jotego_jtcores_pr1242/modules/jt007232/ver/gain/test.v b/snapshots/jotego_jtcores_pr1242/modules/jt007232/ver/gain/test.v new file mode 100644 index 0000000000000000000000000000000000000000..5a535d3e44210f058312227ee5af2d6bb6a2708f --- /dev/null +++ b/snapshots/jotego_jtcores_pr1242/modules/jt007232/ver/gain/test.v @@ -0,0 +1,64 @@ +module test; + +localparam W=11; + +reg clk; +reg signed [6:0] rawa, rawb; +reg [7:0] reg12; +wire signed [W-1:0] snda, sndb; + +initial begin + clk=0; + forever #10 clk=~clk; +end + +integer gain=0,expa,expb, gaina, gainb; + +initial begin + reg12=0; + rawa=0; + rawb=0; + repeat (20) @(posedge clk); + + rawa=127; + rawb=-128; + for(gain=0;gain<256;gain=gain+1) begin + reg12=gain[7:0]; + repeat (2) @(posedge clk); + gaina = {1'b0,reg12[7:4]}; + gainb = {1'b0,reg12[3:0]}; + @(posedge clk); + expa = rawa*gaina; + expb = rawb*gainb; + @(posedge clk); + if(snda!=$signed(expa[W-1:0]) || sndb!=$signed(expb[W-1:0])) begin + $display("Bad value at gain %d/%d",reg12[3:0],reg12[7:4]); + $display("channel a: %d <> %d",snda,expa); + $display("channel b: %d <> %d",sndb,expb); + $display("FAIL"); + $finish; + end + if( expa[30:W-1]!={32-W{expa[31]}} || expb[30:W-1]!={32-W{expb[31]}}) begin + $display("Bad sign at gain %d/%d",reg12[3:0],reg12[7:4]); + $display("channel a: %d <> %d",snda,expa); + $display("channel b: %d <> %d",sndb,expb); + $display("FAIL"); + $finish; + end + end + $display("PASS"); + $finish; +end + + +jt007232_gain uut( + .clk ( clk ), + .reg12 ( reg12 ), + .swap_gains ( 1'b0 ), + .rawa ( rawa ), + .rawb ( rawb ), + .snda ( snda ), + .sndb ( sndb ) +); + +endmodule \ No newline at end of file diff --git a/snapshots/jotego_jtcores_pr1242/modules/jt5232/cfg/files.yaml b/snapshots/jotego_jtcores_pr1242/modules/jt5232/cfg/files.yaml new file mode 100644 index 0000000000000000000000000000000000000000..1f66445b3913614545ff34114524a2f233b1e66b --- /dev/null +++ b/snapshots/jotego_jtcores_pr1242/modules/jt5232/cfg/files.yaml @@ -0,0 +1,3 @@ +jt5232: + - get: + - "*.v" diff --git a/snapshots/jotego_jtcores_pr1242/modules/jt5232/doc/msm5232.cpp b/snapshots/jotego_jtcores_pr1242/modules/jt5232/doc/msm5232.cpp new file mode 100644 index 0000000000000000000000000000000000000000..3761e442ae7027721e428acc408ab7ceffa35e89 --- /dev/null +++ b/snapshots/jotego_jtcores_pr1242/modules/jt5232/doc/msm5232.cpp @@ -0,0 +1,781 @@ +// license:GPL-2.0+ +// copyright-holders:Jarek Burczynski, Hiromitsu Shioya +#include "emu.h" +#include "msm5232.h" + +#define CLOCK_RATE_DIVIDER 16 + +/* + OKI MSM5232RS + 8 channel tone generator +*/ + +DEFINE_DEVICE_TYPE(MSM5232, msm5232_device, "msm5232", "MSM5232") + +msm5232_device::msm5232_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock) + : device_t(mconfig, MSM5232, tag, owner, clock) + , device_sound_interface(mconfig, *this) + , m_stream(nullptr) + , m_noise_cnt(0), m_noise_step(0), m_noise_rng(0), m_noise_clocks(0), m_UpdateStep(0), m_control1(0), m_control2(0), m_gate(0), m_chip_clock(0), m_rate(0) + , m_gate_handler_cb(*this) +{ +} + +//------------------------------------------------- +// device_start - device-specific startup +//------------------------------------------------- + +void msm5232_device::device_start() +{ + int rate = clock()/CLOCK_RATE_DIVIDER; + int voicenum; + + init(clock(), rate); + + m_stream = stream_alloc(0, 11, rate); + + /* register with the save state system */ + save_item(NAME(m_EN_out16)); + save_item(NAME(m_EN_out8)); + save_item(NAME(m_EN_out4)); + save_item(NAME(m_EN_out2)); + save_item(NAME(m_noise_cnt)); + save_item(NAME(m_noise_rng)); + save_item(NAME(m_noise_clocks)); + save_item(NAME(m_control1)); + save_item(NAME(m_control2)); + save_item(NAME(m_gate)); + save_item(NAME(m_chip_clock)); + save_item(NAME(m_rate)); + + /* register voice-specific data for save states */ + for (voicenum = 0; voicenum < 8; voicenum++) + { + VOICE *voice = &m_voi[voicenum]; + + save_item(NAME(voice->mode), voicenum); + save_item(NAME(voice->TG_count_period), voicenum); + save_item(NAME(voice->TG_cnt), voicenum); + save_item(NAME(voice->TG_out16), voicenum); + save_item(NAME(voice->TG_out8), voicenum); + save_item(NAME(voice->TG_out4), voicenum); + save_item(NAME(voice->TG_out2), voicenum); + save_item(NAME(voice->egvol), voicenum); + save_item(NAME(voice->eg_sect), voicenum); + save_item(NAME(voice->counter), voicenum); + save_item(NAME(voice->eg), voicenum); + save_item(NAME(voice->eg_arm), voicenum); + save_item(NAME(voice->ar_rate), voicenum); + save_item(NAME(voice->dr_rate), voicenum); + save_item(NAME(voice->pitch), voicenum); + save_item(NAME(voice->GF), voicenum); + } +} + +//------------------------------------------------- +// device_reset - device-specific reset +//------------------------------------------------- + +void msm5232_device::device_reset() +{ + for (int i=0; i<8; i++) + { + write(i, 0x80); + write(i, 0x00); + } + m_noise_cnt = 0; + m_noise_rng = 1; + m_noise_clocks = 0; + + m_control1 = 0; + m_EN_out16[0] = 0; + m_EN_out8[0] = 0; + m_EN_out4[0] = 0; + m_EN_out2[0] = 0; + + m_control2 = 0; + m_EN_out16[1] = 0; + m_EN_out8[1] = 0; + m_EN_out4[1] = 0; + m_EN_out2[1] = 0; + + gate_update(); +} + +//------------------------------------------------- +// device_stop - device-specific stop +//------------------------------------------------- + +void msm5232_device::device_stop() +{ +#ifdef SAVE_SAMPLE + fclose(sample[8]); +#endif +#ifdef SAVE_SEPARATE_CHANNELS + fclose(sample[0]); + fclose(sample[1]); + fclose(sample[2]); + fclose(sample[3]); + fclose(sample[4]); + fclose(sample[5]); + fclose(sample[6]); + fclose(sample[7]); +#endif +} + +void msm5232_device::set_capacitors(double cap1, double cap2, double cap3, double cap4, double cap5, double cap6, double cap7, double cap8) +{ + m_external_capacitance[0] = cap1; + m_external_capacitance[1] = cap2; + m_external_capacitance[2] = cap3; + m_external_capacitance[3] = cap4; + m_external_capacitance[4] = cap5; + m_external_capacitance[5] = cap6; + m_external_capacitance[6] = cap7; + m_external_capacitance[7] = cap8; +} + +// Default chip clock is 2119040 Hz +// At this clock chip generates exactly 440.0 Hz signal on 8' output when pitch data=0x21 + + +// ROM table to convert from pitch data into data for programmable counter and binary counter +// Chip has 88x12bits ROM (addressing (in hex) from 0x00 to 0x57) +#define ROM(counter,bindiv) (counter|(bindiv<<9)) + +static const uint16_t MSM5232_ROM[88]={ +/* higher values are Programmable Counter data (9 bits) */ +/* lesser values are Binary Counter shift data (3 bits) */ + +/* 0 */ ROM (506, 7), + +/* 1 */ ROM (478, 7),/* 2 */ ROM (451, 7),/* 3 */ ROM (426, 7),/* 4 */ ROM (402, 7), +/* 5 */ ROM (379, 7),/* 6 */ ROM (358, 7),/* 7 */ ROM (338, 7),/* 8 */ ROM (319, 7), +/* 9 */ ROM (301, 7),/* A */ ROM (284, 7),/* B */ ROM (268, 7),/* C */ ROM (253, 7), + +/* D */ ROM (478, 6),/* E */ ROM (451, 6),/* F */ ROM (426, 6),/*10 */ ROM (402, 6), +/*11 */ ROM (379, 6),/*12 */ ROM (358, 6),/*13 */ ROM (338, 6),/*14 */ ROM (319, 6), +/*15 */ ROM (301, 6),/*16 */ ROM (284, 6),/*17 */ ROM (268, 6),/*18 */ ROM (253, 6), + +/*19 */ ROM (478, 5),/*1A */ ROM (451, 5),/*1B */ ROM (426, 5),/*1C */ ROM (402, 5), +/*1D */ ROM (379, 5),/*1E */ ROM (358, 5),/*1F */ ROM (338, 5),/*20 */ ROM (319, 5), +/*21 */ ROM (301, 5),/*22 */ ROM (284, 5),/*23 */ ROM (268, 5),/*24 */ ROM (253, 5), + +/*25 */ ROM (478, 4),/*26 */ ROM (451, 4),/*27 */ ROM (426, 4),/*28 */ ROM (402, 4), +/*29 */ ROM (379, 4),/*2A */ ROM (358, 4),/*2B */ ROM (338, 4),/*2C */ ROM (319, 4), +/*2D */ ROM (301, 4),/*2E */ ROM (284, 4),/*2F */ ROM (268, 4),/*30 */ ROM (253, 4), + +/*31 */ ROM (478, 3),/*32 */ ROM (451, 3),/*33 */ ROM (426, 3),/*34 */ ROM (402, 3), +/*35 */ ROM (379, 3),/*36 */ ROM (358, 3),/*37 */ ROM (338, 3),/*38 */ ROM (319, 3), +/*39 */ ROM (301, 3),/*3A */ ROM (284, 3),/*3B */ ROM (268, 3),/*3C */ ROM (253, 3), + +/*3D */ ROM (478, 2),/*3E */ ROM (451, 2),/*3F */ ROM (426, 2),/*40 */ ROM (402, 2), +/*41 */ ROM (379, 2),/*42 */ ROM (358, 2),/*43 */ ROM (338, 2),/*44 */ ROM (319, 2), +/*45 */ ROM (301, 2),/*46 */ ROM (284, 2),/*47 */ ROM (268, 2),/*48 */ ROM (253, 2), + +/*49 */ ROM (478, 1),/*4A */ ROM (451, 1),/*4B */ ROM (426, 1),/*4C */ ROM (402, 1), +/*4D */ ROM (379, 1),/*4E */ ROM (358, 1),/*4F */ ROM (338, 1),/*50 */ ROM (319, 1), +/*51 */ ROM (301, 1),/*52 */ ROM (284, 1),/*53 */ ROM (268, 1),/*54 */ ROM (253, 1), + +/*55 */ ROM (253, 1),/*56 */ ROM (253, 1), + +/*57 */ ROM (13, 7) +}; +#undef ROM + + +#define STEP_SH (16) /* step calculations accuracy */ + + +/* save output as raw 16-bit sample */ +/* #define SAVE_SAMPLE */ +/* #define SAVE_SEPARATE_CHANNELS */ +#if defined SAVE_SAMPLE || defined SAVE_SEPARATE_CHANNELS +static FILE *sample[9]; +#endif + + + +/* + * Resistance values are guesswork, default capacitance is mentioned in the datasheets + * + * Two errors in the datasheet, one probable, one certain + * - it mentions 0.39uF caps, but most boards have 1uF caps and expect datasheet timings + * + * - the 330ms timing of decay2 has been measured to be 250ms (which + * also matches the duty cycle information for the rest of the table) + * + * In both cases it ends up with smaller resistor values, which are + * easier to do on-die. + * + * The timings are for a 90% charge/discharge of the external + * capacitor through three possible resistors, one for attack, two for + * decay. + * + * Expected timings are 2ms, 40ms and 250ms respectively with a 1uF + * capacitor. + * + * exp(-t/(r*c)) = (100% - 90%) => r = -r/(log(0.1)*c) + * + * 2ms -> 870 ohms + * 40ms -> 17400 ohms + * 250ms -> 101000 ohms + */ + + +static constexpr double R51 = 870; // attack resistance +static constexpr double R52 = 17400; // decay 1 resistance +static constexpr double R53 = 101000; // decay 2 resistance + + +void msm5232_device::init_tables() +{ + // sample rate = chip clock !!! But : + // highest possible frequency is chipclock/13/16 (pitch data=0x57) + // at 2MHz : 2000000/13/16 = 9615 Hz + + m_UpdateStep = int(double(1 << STEP_SH) * double(m_rate) / double(m_chip_clock)); + //logerror("clock=%i Hz rate=%i Hz, UpdateStep=%i\n", m_chip_clock, m_rate, m_UpdateStep); + + double const scale = double(m_chip_clock) / double(m_rate); + m_noise_step = ((1 << STEP_SH) / 128.0) * scale; // step of the rng reg in 16.16 format + //logerror("noise step=%8x\n", m_noise_step); + + for (int i = 0; i < 8; i++) + { + double const clockscale = double(m_chip_clock) / 2119040.0; + int const rcp_duty_cycle = 1 << ((i & 4) ? (i & ~2) : i); // bit 1 is ignored if bit 2 is set + m_ar_tbl[i] = (rcp_duty_cycle / clockscale) * R51; + } + + for (int i = 0; i < 8; i++) + { + double const clockscale = double(m_chip_clock) / 2119040.0; + int const rcp_duty_cycle = 1 << ((i & 4) ? (i & ~2) : i); // bit 1 is ignored if bit 2 is set + m_dr_tbl[i] = (rcp_duty_cycle / clockscale) * R52; + m_dr_tbl[i + 8] = (rcp_duty_cycle / clockscale) * R53; + } + + +#ifdef SAVE_SAMPLE + sample[8]=fopen("sampsum.pcm","wb"); +#endif +#ifdef SAVE_SEPARATE_CHANNELS + sample[0]=fopen("samp0.pcm","wb"); + sample[1]=fopen("samp1.pcm","wb"); + sample[2]=fopen("samp2.pcm","wb"); + sample[3]=fopen("samp3.pcm","wb"); + sample[4]=fopen("samp4.pcm","wb"); + sample[5]=fopen("samp5.pcm","wb"); + sample[6]=fopen("samp6.pcm","wb"); + sample[7]=fopen("samp7.pcm","wb"); +#endif +} + + +void msm5232_device::init_voice(int i) +{ + m_voi[i].ar_rate= m_ar_tbl[0] * m_external_capacitance[i]; + m_voi[i].dr_rate= m_dr_tbl[0] * m_external_capacitance[i]; + m_voi[i].rr_rate= m_dr_tbl[0] * m_external_capacitance[i]; /* this is constant value */ + m_voi[i].eg_sect= -1; + m_voi[i].eg = 0.0; + m_voi[i].eg_arm = 0; + m_voi[i].pitch = -1.0; +} + + +void msm5232_device::gate_update() +{ + int new_state = (m_control2 & 0x20) ? m_voi[7].GF : 0; + + if (m_gate != new_state) + { + m_gate = new_state; + m_gate_handler_cb(new_state); + } +} + +void msm5232_device::init(int clock, int rate) +{ + int j; + + m_chip_clock = clock; + m_rate = rate ? rate : 44100; /* avoid division by 0 */ + + init_tables(); + + for (j=0; j<8; j++) + { + memset(&m_voi[j],0,sizeof(VOICE)); + init_voice(j); + } +} + + +void msm5232_device::write(offs_t offset, uint8_t data) +{ + if (offset > 0x0d) + return; + + m_stream->update (); + + if (offset < 0x08) /* pitch */ + { + int ch = offset&7; + + m_voi[ch].GF = ((data&0x80)>>7); + if (ch == 7) + gate_update(); + + if(data&0x80) + { + if(data >= 0xd8) + { + /*if ((data&0x7f) != 0x5f) logerror("MSM5232: WRONG PITCH CODE = %2x\n",data&0x7f);*/ + m_voi[ch].mode = 1; /* noise mode */ + m_voi[ch].eg_sect = 0; /* Key On */ + } + else + { + if ( m_voi[ch].pitch != (data&0x7f) ) + { + int n; + uint16_t pg; + + m_voi[ch].pitch = data&0x7f; + + pg = MSM5232_ROM[ data&0x7f ]; + + m_voi[ch].TG_count_period = (pg & 0x1ff) * m_UpdateStep / 2; + + n = (pg>>9) & 7; /* n = bit number for 16' output */ + m_voi[ch].TG_out16 = 1<0)? n-1: 0; + m_voi[ch].TG_out8 = 1<0)? n-1: 0; + m_voi[ch].TG_out4 = 1<0)? n-1: 0; + m_voi[ch].TG_out2 = 1< go to release */ + else /* arm = 1 */ + m_voi[ch].eg_sect = 1; /* Key Off -> go to decay */ + } + } + else + { + int i; + switch(offset) + { + case 0x08: /* group1 attack */ + for (i=0; i<4; i++) + m_voi[i].ar_rate = m_ar_tbl[data&0x7] * m_external_capacitance[i]; + break; + + case 0x09: /* group2 attack */ + for (i=0; i<4; i++) + m_voi[i+4].ar_rate = m_ar_tbl[data&0x7] * m_external_capacitance[i+4]; + break; + + case 0x0a: /* group1 decay */ + for (i=0; i<4; i++) + m_voi[i].dr_rate = m_dr_tbl[data&0xf] * m_external_capacitance[i]; + break; + + case 0x0b: /* group2 decay */ + for (i=0; i<4; i++) + m_voi[i+4].dr_rate = m_dr_tbl[data&0xf] * m_external_capacitance[i+4]; + break; + + case 0x0c: /* group1 control */ + + /*if (m_control1 != data) + logerror("msm5232: control1 ctrl=%x OE=%x\n", data&0xf0, data&0x0f);*/ + + /*if (data & 0x10) + popmessage("msm5232: control1 ctrl=%2x\n", data);*/ + + m_control1 = data; + + for (i=0; i<4; i++) + { + if ( (data&0x10) && (m_voi[i].eg_sect == 1) ) + m_voi[i].eg_sect = 0; + m_voi[i].eg_arm = data&0x10; + } + + m_EN_out16[0] = (data&1) ? ~0:0; + m_EN_out8[0] = (data&2) ? ~0:0; + m_EN_out4[0] = (data&4) ? ~0:0; + m_EN_out2[0] = (data&8) ? ~0:0; + + break; + + case 0x0d: /* group2 control */ + + /*if (m_control2 != data) + logerror("msm5232: control2 ctrl=%x OE=%x\n", data&0xf0, data&0x0f);*/ + + /*if (data & 0x10) + popmessage("msm5232: control2 ctrl=%2x\n", data);*/ + + m_control2 = data; + gate_update(); + + for (i=0; i<4; i++) + { + if ( (data&0x10) && (m_voi[i+4].eg_sect == 1) ) + m_voi[i+4].eg_sect = 0; + m_voi[i+4].eg_arm = data&0x10; + } + + m_EN_out16[1] = (data&1) ? ~0:0; + m_EN_out8[1] = (data&2) ? ~0:0; + m_EN_out4[1] = (data&4) ? ~0:0; + m_EN_out2[1] = (data&8) ? ~0:0; + + break; + } + } +} + + + +#define VMIN 0 +#define VMAX 32768 + + +void msm5232_device::EG_voices_advance() +{ + VOICE *voi = &m_voi[0]; + int samplerate = m_rate; + int i; + + i = 8; + do + { + switch(voi->eg_sect) + { + case 0: /* attack */ + + /* capacitor charge */ + if (voi->eg < VMAX) + { + voi->counter -= (int)((VMAX - voi->eg) / voi->ar_rate); + if ( voi->counter <= 0 ) + { + int n = -voi->counter / samplerate + 1; + voi->counter += n * samplerate; + if ( (voi->eg += n) > VMAX ) + voi->eg = VMAX; + } + } + + /* when ARM=0, EG switches to decay as soon as cap is charged to VT (EG inversion voltage; about 80% of MAX) */ + if (!voi->eg_arm) + { + if(voi->eg >= VMAX * 80/100 ) + { + voi->eg_sect = 1; + } + } + else + /* ARM=1 */ + { + /* when ARM=1, EG stays at maximum until key off */ + } + + voi->egvol = voi->eg / 16; /*32768/16 = 2048 max*/ + + break; + + case 1: /* decay */ + + /* capacitor discharge */ + if (voi->eg > VMIN) + { + voi->counter -= (int)((voi->eg - VMIN) / voi->dr_rate); + if ( voi->counter <= 0 ) + { + int n = -voi->counter / samplerate + 1; + voi->counter += n * samplerate; + if ( (voi->eg -= n) < VMIN ) + voi->eg = VMIN; + } + } + else /* voi->eg <= VMIN */ + { + voi->eg_sect =-1; + } + + voi->egvol = voi->eg / 16; /*32768/16 = 2048 max*/ + + break; + + case 2: /* release */ + + /* capacitor discharge */ + if (voi->eg > VMIN) + { + voi->counter -= (int)((voi->eg - VMIN) / voi->rr_rate); + if ( voi->counter <= 0 ) + { + int n = -voi->counter / samplerate + 1; + voi->counter += n * samplerate; + if ( (voi->eg -= n) < VMIN ) + voi->eg = VMIN; + } + } + else /* voi->eg <= VMIN */ + { + voi->eg_sect =-1; + } + + voi->egvol = voi->eg / 16; /*32768/16 = 2048 max*/ + + break; + + default: + break; + } + + voi++; + i--; + } while (i>0); + +} + +static int o2,o4,o8,o16,solo8,solo16; + +void msm5232_device::TG_group_advance(int groupidx) +{ + VOICE *voi = &m_voi[groupidx*4]; + int i; + + o2 = o4 = o8 = o16 = solo8 = solo16 = 0; + + i=4; + do + { + int out2, out4, out8, out16; + + out2 = out4 = out8 = out16 = 0; + + if (voi->mode==0) /* generate square tone */ + { + int left = 1<TG_cnt&voi->TG_out16) out16+=voi->TG_count; + if (voi->TG_cnt&voi->TG_out8) out8 +=voi->TG_count; + if (voi->TG_cnt&voi->TG_out4) out4 +=voi->TG_count; + if (voi->TG_cnt&voi->TG_out2) out2 +=voi->TG_count; + + voi->TG_count -= nextevent; + + while (voi->TG_count <= 0) + { + voi->TG_count += voi->TG_count_period; + voi->TG_cnt++; + if (voi->TG_cnt&voi->TG_out16) out16+=voi->TG_count_period; + if (voi->TG_cnt&voi->TG_out8 ) out8 +=voi->TG_count_period; + if (voi->TG_cnt&voi->TG_out4 ) out4 +=voi->TG_count_period; + if (voi->TG_cnt&voi->TG_out2 ) out2 +=voi->TG_count_period; + + if (voi->TG_count > 0) + break; + + voi->TG_count += voi->TG_count_period; + voi->TG_cnt++; + if (voi->TG_cnt&voi->TG_out16) out16+=voi->TG_count_period; + if (voi->TG_cnt&voi->TG_out8 ) out8 +=voi->TG_count_period; + if (voi->TG_cnt&voi->TG_out4 ) out4 +=voi->TG_count_period; + if (voi->TG_cnt&voi->TG_out2 ) out2 +=voi->TG_count_period; + } + if (voi->TG_cnt&voi->TG_out16) out16-=voi->TG_count; + if (voi->TG_cnt&voi->TG_out8 ) out8 -=voi->TG_count; + if (voi->TG_cnt&voi->TG_out4 ) out4 -=voi->TG_count; + if (voi->TG_cnt&voi->TG_out2 ) out2 -=voi->TG_count; + + left -=nextevent; + + }while (left>0); + } + else /* generate noise */ + { + if (m_noise_clocks&8) out16+=(1<egvol) >> STEP_SH; + o8 += ( (out8 -(1<<(STEP_SH-1))) * voi->egvol) >> STEP_SH; + o4 += ( (out4 -(1<<(STEP_SH-1))) * voi->egvol) >> STEP_SH; + o2 += ( (out2 -(1<<(STEP_SH-1))) * voi->egvol) >> STEP_SH; + + if (i == 1 && groupidx == 1) + { + solo16 += ( (out16-(1<<(STEP_SH-1))) << 11) >> STEP_SH; + solo8 += ( (out8 -(1<<(STEP_SH-1))) << 11) >> STEP_SH; + } + + voi++; + i--; + }while (i>0); + + /* cut off disabled output lines */ + o16 &= m_EN_out16[groupidx]; + o8 &= m_EN_out8 [groupidx]; + o4 &= m_EN_out4 [groupidx]; + o2 &= m_EN_out2 [groupidx]; +} + + +/* macro saves feet data to mono file */ +#ifdef SAVE_SEPARATE_CHANNELS + #define SAVE_SINGLE_CHANNEL(j,val) \ + { signed int pom= val; \ + if (pom > 32767) pom = 32767; else if (pom < -32768) pom = -32768; \ + fputc((unsigned short)pom&0xff,sample[j]); \ + fputc(((unsigned short)pom>>8)&0xff,sample[j]); } +#else + #define SAVE_SINGLE_CHANNEL(j,val) +#endif + +/* first macro saves all 8 feet outputs to mixed (mono) file */ +/* second macro saves one group into left and the other in right channel */ +#if 1 /*MONO*/ + #ifdef SAVE_SAMPLE + #define SAVE_ALL_CHANNELS \ + { signed int pom = buf1[i] + buf2[i]; \ + fputc((unsigned short)pom&0xff,sample[8]); \ + fputc(((unsigned short)pom>>8)&0xff,sample[8]); \ + } + #else + #define SAVE_ALL_CHANNELS + #endif +#else /*STEREO*/ + #ifdef SAVE_SAMPLE + #define SAVE_ALL_CHANNELS \ + { signed int pom = buf1[i]; \ + fputc((unsigned short)pom&0xff,sample[8]); \ + fputc(((unsigned short)pom>>8)&0xff,sample[8]); \ + pom = buf2[i]; \ + fputc((unsigned short)pom&0xff,sample[8]); \ + fputc(((unsigned short)pom>>8)&0xff,sample[8]); \ + } + #else + #define SAVE_ALL_CHANNELS + #endif +#endif + + +/* MAME Interface */ +void msm5232_device::device_post_load() +{ + init_tables(); +} + +void msm5232_device::set_clock(int clock) +{ + if (m_chip_clock != clock) + { + m_stream->update (); + m_chip_clock = clock; + m_rate = clock/CLOCK_RATE_DIVIDER; + init_tables(); + m_stream->set_sample_rate(m_rate); + } +} + + +//------------------------------------------------- +// sound_stream_update - handle a stream update +//------------------------------------------------- + +void msm5232_device::sound_stream_update(sound_stream &stream, std::vector const &inputs, std::vector &outputs) +{ + auto &buf1 = outputs[0]; + auto &buf2 = outputs[1]; + auto &buf3 = outputs[2]; + auto &buf4 = outputs[3]; + auto &buf5 = outputs[4]; + auto &buf6 = outputs[5]; + auto &buf7 = outputs[6]; + auto &buf8 = outputs[7]; + auto &bufsolo1 = outputs[8]; + auto &bufsolo2 = outputs[9]; + auto &bufnoise = outputs[10]; + int i; + + for (i=0; i> STEP_SH; + m_noise_cnt &= ((1< 0) + { + int tmp = m_noise_rng & (1<<16); /* store current level */ + + if (m_noise_rng&1) + m_noise_rng ^= 0x24000; + m_noise_rng>>=1; + + if ( (m_noise_rng & (1<<16)) != tmp ) /* level change detect */ + m_noise_clocks++; + + cnt--; + } + } + + bufnoise.put(i, (m_noise_rng & (1<<16)) ? 1.0 : 0.0); + } +} diff --git a/snapshots/jotego_jtcores_pr1242/modules/jt5232/hdl/jt5232.v b/snapshots/jotego_jtcores_pr1242/modules/jt5232/hdl/jt5232.v new file mode 100644 index 0000000000000000000000000000000000000000..b473dc39543cceb10d78f7ad8c6d6c6a7b6289ea --- /dev/null +++ b/snapshots/jotego_jtcores_pr1242/modules/jt5232/hdl/jt5232.v @@ -0,0 +1,166 @@ +/* This file is part of JTCORES. + JTCORES program is free software: you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation, either version 3 of the License, or + (at your option) any later version. + + JTCORES program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with JTCORES. If not, see . + + Author: Jose Tejada Gomez. Twitter: @topapate + Version: 1.0 + Date: 6-12-2024 */ + +// the ' means feet in an organ pipe length +// output 2' = 4*f +// output 4' = 2*f +// output 8' is the base pitch = f +// output 16' = f/2 + +// items not implemented (yet) +// - solo output +// - gate output +// - solo mode bit +// - noise +module jt5232( + input rst, + input clk, + input cen1, + input cen2, + input [7:0] din, + input [3:0] addr, + input we, + output [14:0] snd1, + output [14:0] snd2, + // debug information + output reg clip=0, + output reg no_used // noise used flag. Noise is not currently implemented +); + +// TG configuration +reg [ 8:0] step[0:7]; +wire [ 8:0] pgcnt; +wire [ 2:0] pgbit; +reg [ 2:0] pitch_sel; +reg [ 2:0] bsel[0:7]; +reg [ 6:0] pitch; +reg [ 7:0] gf, kon, noise; +reg [ 2:0] attack[0:1]; +reg [ 3:0] decay[0:1]; +reg [ 3:0] oen[0:1]; // 2' 4' 8' 16' output enable +reg sf; // solo flag (group 2 only) +reg [ 1:0] ege, // envelope generator enable + arm; // attack-release mode +wire no_en; // noise enable +// sound +wire [12*8-1:0] eg; +wire [ 3*8-1:0] organ; +// clip detection +wire clip_raw; +reg clip_l; +reg [3:0] clip_cnt; + +// clock divider +reg [6:0] div3=0; // A divider for each group +reg [4:0] duty=0; +reg cen256=0; + +`ifdef SIMULATION +reg [3:0] al; +reg [7:0] dl; +always_latch begin + if(we) begin al=addr; dl=din; end +end +`endif + +always @(posedge clk) begin + clip_l <= clip_raw; + if(!clip_l && clip_raw) begin clip<=1; clip_cnt<=0; end + if(cen256 && clip) {clip,clip_cnt}<={1'd0,clip_cnt}+5'd1; +end + +always @(posedge clk) begin + {cen256,div3} <= {1'b0,div3}+7'd1; + duty <= duty+{4'd0,cen256}; +end + +// CPU interface +always @(posedge clk) begin + no_used <= |noise; +end + +always @(posedge clk) begin + if(rst) begin + gf <= 0; + attack[0] <= 0; attack[1] <= 0; + decay [0] <= 0; decay [1] <= 0; + oen [0] <= 0; oen [1] <= 0; + pitch <= 0; pitch_sel <= 0; + step[0] <= 0; step[1] <= 0; step[2] <= 0; step[3] <= 0; + step[4] <= 0; step[5] <= 0; step[6] <= 0; step[7] <= 0; + bsel[0] <= 0; bsel[1] <= 0; bsel[2] <= 0; bsel[3] <= 0; + bsel[4] <= 0; bsel[5] <= 0; bsel[6] <= 0; bsel[7] <= 0; + {sf,ege,arm} <= 0; + end else begin + kon <= 0; + if(we) casez(addr) + 4'b0???: begin + if(din[7]) {pitch_sel, pitch} <= {addr[2:0],din[6:0]}; + gf[addr[2:0]] <= din[7]; + kon[addr[2:0]] <= din[7]; + end + 8, 9: attack[addr[0]] <= din[2:0]; + 10,11: decay [addr[0]] <= din[3:0]; + 12: { ege[0],arm[0],oen[0]} <= din[5:0]; + 13: {sf,ege[1],arm[1],oen[1]} <= din[6:0]; + default:; + endcase + {step[pitch_sel],bsel[pitch_sel],noise[pitch_sel]}<={pgcnt,pgbit,no_en}; + end +end + +// envelope generators +jt5232_eg u_eg0(rst,clk,cen256,duty,gf[0],kon[0],ege[0],arm[0],attack[0],decay[0],eg[0*12+:12]); +jt5232_eg u_eg1(rst,clk,cen256,duty,gf[1],kon[1],ege[0],arm[0],attack[0],decay[0],eg[1*12+:12]); +jt5232_eg u_eg2(rst,clk,cen256,duty,gf[2],kon[2],ege[0],arm[0],attack[0],decay[0],eg[2*12+:12]); +jt5232_eg u_eg3(rst,clk,cen256,duty,gf[3],kon[3],ege[0],arm[0],attack[0],decay[0],eg[3*12+:12]); +jt5232_eg u_eg4(rst,clk,cen256,duty,gf[4],kon[4],ege[1],arm[1],attack[1],decay[1],eg[4*12+:12]); +jt5232_eg u_eg5(rst,clk,cen256,duty,gf[5],kon[5],ege[1],arm[1],attack[1],decay[1],eg[5*12+:12]); +jt5232_eg u_eg6(rst,clk,cen256,duty,gf[6],kon[6],ege[1],arm[1],attack[1],decay[1],eg[6*12+:12]); +jt5232_eg u_eg7(rst,clk,cen256,duty,gf[7],kon[7],ege[1],arm[1],attack[1],decay[1],eg[7*12+:12]); +// tone generators +// group 1 +jt5232_tg u_tg0( rst, clk, cen1, step[0], bsel[0], oen[0], organ[0*3+:3] ); +jt5232_tg u_tg1( rst, clk, cen1, step[1], bsel[1], oen[0], organ[1*3+:3] ); +jt5232_tg u_tg2( rst, clk, cen1, step[2], bsel[2], oen[0], organ[2*3+:3] ); +jt5232_tg u_tg3( rst, clk, cen1, step[3], bsel[3], oen[0], organ[3*3+:3] ); +// group 2 +jt5232_tg u_tg4( rst, clk, cen2, step[4], bsel[4], oen[1], organ[4*3+:3] ); +jt5232_tg u_tg5( rst, clk, cen2, step[5], bsel[5], oen[1], organ[5*3+:3] ); +jt5232_tg u_tg6( rst, clk, cen2, step[6], bsel[6], oen[1], organ[6*3+:3] ); +jt5232_tg u_tg7( rst, clk, cen2, step[7], bsel[7], oen[1], organ[7*3+:3] ); +// accumulator +jt5232_acc u_acc( + .clk ( clk ), + .cen ( cen256 ), + .eg ( eg ), + .organ ( organ ), + .snd1 ( snd1 ), + .snd2 ( snd2 ), + .clip ( clip_raw ) +); + +jt5232_rom u_rom( + .clk ( clk ), + .addr ( pitch ), + .pgcnt( pgcnt ), + .bsel ( pgbit ), + .noise( no_en ) +); + +endmodule \ No newline at end of file diff --git a/snapshots/jotego_jtcores_pr1242/modules/jt5232/hdl/jt5232.vh b/snapshots/jotego_jtcores_pr1242/modules/jt5232/hdl/jt5232.vh new file mode 100644 index 0000000000000000000000000000000000000000..06f95000241e99de1bbbea73969e1419bd913e94 --- /dev/null +++ b/snapshots/jotego_jtcores_pr1242/modules/jt5232/hdl/jt5232.vh @@ -0,0 +1,10 @@ +// common definitions used on tests +localparam TW=16; // tone output bit width + +// registers +localparam ATIME1=8, + ATIME2=9, + DTIME1=10, + DTIME2=11, + GCTL1 =12, + GCTL2 =13; \ No newline at end of file diff --git a/snapshots/jotego_jtcores_pr1242/modules/jt5232/hdl/jt5232_acc.v b/snapshots/jotego_jtcores_pr1242/modules/jt5232/hdl/jt5232_acc.v new file mode 100644 index 0000000000000000000000000000000000000000..93f2912f445a74930a517eeb401ae6225888d5a5 --- /dev/null +++ b/snapshots/jotego_jtcores_pr1242/modules/jt5232/hdl/jt5232_acc.v @@ -0,0 +1,53 @@ +/* This file is part of JTCORES. + JTCORES program is free software: you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation, either version 3 of the License, or + (at your option) any later version. + + JTCORES program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with JTCORES. If not, see . + + Author: Jose Tejada Gomez. Twitter: @topapate + Version: 1.0 + Date: 6-12-2024 */ + +module jt5232_acc( + input clk, + input cen, + input [12*8-1:0] eg, + input [ 3*8-1:0] organ, + output [ 14:0] snd1, snd2, + output reg clip +); + +integer i; +reg [14:0] mul[0:7]; +reg [15:0] acc0,acc1,acc2,acc3; +reg [16:0] acc4,acc5; + +function [14:0] clipsnd(input [16:0] s); + clipsnd = s[16:15]!=0 ? ~15'h0 : s[14:0]; +endfunction + +assign snd1=clipsnd(acc4); +assign snd2=clipsnd(acc5); + +always @(posedge clk) begin + clip <= |{acc4[16:14],acc5[16:14]}; // these are expected to always be zero + for(i=0;i<8;i=i+1) mul[i]<=eg[12*i+:12]*organ[3*i+:3]; + acc0 <= {1'b0,mul[0]}+{1'b0,mul[1]}; + acc1 <= {1'b0,mul[2]}+{1'b0,mul[3]}; + acc2 <= {1'b0,mul[4]}+{1'b0,mul[5]}; + acc3 <= {1'b0,mul[7]}+{1'b0,mul[7]}; + if(cen) begin + acc4 <= {1'b0,acc0}+{1'b0,acc1}; + acc5 <= {1'b0,acc2}+{1'b0,acc3}; + end +end + +endmodule \ No newline at end of file diff --git a/snapshots/jotego_jtcores_pr1242/modules/jt5232/hdl/jt5232_eg.v b/snapshots/jotego_jtcores_pr1242/modules/jt5232/hdl/jt5232_eg.v new file mode 100644 index 0000000000000000000000000000000000000000..ae27ad2a6e6a9a4304e4ee903edfbc2d7ba87436 --- /dev/null +++ b/snapshots/jotego_jtcores_pr1242/modules/jt5232/hdl/jt5232_eg.v @@ -0,0 +1,136 @@ +/* This file is part of JTCORES. + JTCORES program is free software: you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation, either version 3 of the License, or + (at your option) any later version. + + JTCORES program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with JTCORES. If not, see . + + Author: Jose Tejada Gomez. Twitter: @topapate + Version: 1.0 + Date: 6-12-2024 */ + +// envelope generator + +module jt5232_eg( + input rst, + input clk, + input cen256, // 1 in 256 clk's + input [ 4:0] duty, // divide cen256 following atime and dtime + input gf, + input kon, + input en, + input arm, // attack-release mode + input [ 2:0] atime, // attack time configuration + input [ 3:0] dtime, // decay time configuration + output [11:0] env +); + +// resistor values from MAME +localparam real CLK=`JTFRAME_MCLK/256, + CAP=1e-6, + RA = 870, // attack resistor + R2 = 5800, // release/damping + R1 = 37000; // decay +`ifdef SIMULATION +/* verilator lint_off REALCVT */ +localparam real DA=1.0-$pow(2.71828,-1.0/(CLK*CAP*RA)), + D1=1.0-$pow(2.71828,-1.0/(CLK*CAP*R1)), + D2=1.0-$pow(2.71828,-1.0/(CLK*CAP*R2)), + P9=0.9; +localparam [EW-1:0] DAB=DA*(48'd1<P9B && !arm ) attack<=0; + end else begin + sel <= ((!arm && dtime[3]) && gf) ? DECAY : RELEASE; + eg <= egfall; + end + end + if(eg==0) eg <= 1; + end +end + +endmodule \ No newline at end of file diff --git a/snapshots/jotego_jtcores_pr1242/modules/jt5232/hdl/jt5232_rom.v b/snapshots/jotego_jtcores_pr1242/modules/jt5232/hdl/jt5232_rom.v new file mode 100644 index 0000000000000000000000000000000000000000..094abf3e7f6e1bcd8f94a79a35919c7a2b3b972d --- /dev/null +++ b/snapshots/jotego_jtcores_pr1242/modules/jt5232/hdl/jt5232_rom.v @@ -0,0 +1,131 @@ +/* This file is part of JTCORES. + JTCORES program is free software: you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation, either version 3 of the License, or + (at your option) any later version. + + JTCORES program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with JTCORES. If not, see . + + Author: Jose Tejada Gomez. Twitter: @topapate + Version: 1.0 + Date: 6-12-2024 */ + +// Matches documentation table 1 + +module jt5232_rom( + input clk, + input [6:0] addr, + output [8:0] pgcnt, // programmable counter + output [2:0] bsel, // binary counter shift data + output reg noise +); + +reg [11:0] rom; + +assign {pgcnt,bsel}=rom; + +always @(posedge clk) begin + noise <= 0; + case(addr) + 7'h00: rom <= { 9'd506, 3'd7}; + 7'h01: rom <= { 9'd478, 3'd7}; + 7'h02: rom <= { 9'd451, 3'd7}; + 7'h03: rom <= { 9'd426, 3'd7}; + 7'h04: rom <= { 9'd402, 3'd7}; + 7'h05: rom <= { 9'd379, 3'd7}; + 7'h06: rom <= { 9'd358, 3'd7}; + 7'h07: rom <= { 9'd338, 3'd7}; + 7'h08: rom <= { 9'd319, 3'd7}; + 7'h09: rom <= { 9'd301, 3'd7}; + 7'h0A: rom <= { 9'd284, 3'd7}; + 7'h0B: rom <= { 9'd268, 3'd7}; + 7'h0C: rom <= { 9'd253, 3'd7}; + 7'h0D: rom <= { 9'd478, 3'd6}; + 7'h0E: rom <= { 9'd451, 3'd6}; + 7'h0F: rom <= { 9'd426, 3'd6}; + 7'h10: rom <= { 9'd402, 3'd6}; + 7'h11: rom <= { 9'd379, 3'd6}; + 7'h12: rom <= { 9'd358, 3'd6}; + 7'h13: rom <= { 9'd338, 3'd6}; + 7'h14: rom <= { 9'd319, 3'd6}; + 7'h15: rom <= { 9'd301, 3'd6}; + 7'h16: rom <= { 9'd284, 3'd6}; + 7'h17: rom <= { 9'd268, 3'd6}; + 7'h18: rom <= { 9'd253, 3'd6}; + 7'h19: rom <= { 9'd478, 3'd5}; + 7'h1A: rom <= { 9'd451, 3'd5}; + 7'h1B: rom <= { 9'd426, 3'd5}; + 7'h1C: rom <= { 9'd402, 3'd5}; + 7'h1D: rom <= { 9'd379, 3'd5}; + 7'h1E: rom <= { 9'd358, 3'd5}; + 7'h1F: rom <= { 9'd338, 3'd5}; + 7'h20: rom <= { 9'd319, 3'd5}; + 7'h21: rom <= { 9'd301, 3'd5}; + 7'h22: rom <= { 9'd284, 3'd5}; + 7'h23: rom <= { 9'd268, 3'd5}; + 7'h24: rom <= { 9'd253, 3'd5}; + 7'h25: rom <= { 9'd478, 3'd4}; + 7'h26: rom <= { 9'd451, 3'd4}; + 7'h27: rom <= { 9'd426, 3'd4}; + 7'h28: rom <= { 9'd402, 3'd4}; + 7'h29: rom <= { 9'd379, 3'd4}; + 7'h2A: rom <= { 9'd358, 3'd4}; + 7'h2B: rom <= { 9'd338, 3'd4}; + 7'h2C: rom <= { 9'd319, 3'd4}; + 7'h2D: rom <= { 9'd301, 3'd4}; + 7'h2E: rom <= { 9'd284, 3'd4}; + 7'h2F: rom <= { 9'd268, 3'd4}; + 7'h30: rom <= { 9'd253, 3'd4}; + 7'h31: rom <= { 9'd478, 3'd3}; + 7'h32: rom <= { 9'd451, 3'd3}; + 7'h33: rom <= { 9'd426, 3'd3}; + 7'h34: rom <= { 9'd402, 3'd3}; + 7'h35: rom <= { 9'd379, 3'd3}; + 7'h36: rom <= { 9'd358, 3'd3}; + 7'h37: rom <= { 9'd338, 3'd3}; + 7'h38: rom <= { 9'd319, 3'd3}; + 7'h39: rom <= { 9'd301, 3'd3}; + 7'h3A: rom <= { 9'd284, 3'd3}; + 7'h3B: rom <= { 9'd268, 3'd3}; + 7'h3C: rom <= { 9'd253, 3'd3}; + 7'h3D: rom <= { 9'd478, 3'd2}; + 7'h3E: rom <= { 9'd451, 3'd2}; + 7'h3F: rom <= { 9'd426, 3'd2}; + 7'h40: rom <= { 9'd402, 3'd2}; + 7'h41: rom <= { 9'd379, 3'd2}; + 7'h42: rom <= { 9'd358, 3'd2}; + 7'h43: rom <= { 9'd338, 3'd2}; + 7'h44: rom <= { 9'd319, 3'd2}; + 7'h45: rom <= { 9'd301, 3'd2}; + 7'h46: rom <= { 9'd284, 3'd2}; + 7'h47: rom <= { 9'd268, 3'd2}; + 7'h48: rom <= { 9'd253, 3'd2}; + 7'h49: rom <= { 9'd478, 3'd1}; + 7'h4A: rom <= { 9'd451, 3'd1}; + 7'h4B: rom <= { 9'd426, 3'd1}; + 7'h4C: rom <= { 9'd402, 3'd1}; + 7'h4D: rom <= { 9'd379, 3'd1}; + 7'h4E: rom <= { 9'd358, 3'd1}; + 7'h4F: rom <= { 9'd338, 3'd1}; + 7'h50: rom <= { 9'd319, 3'd1}; + 7'h51: rom <= { 9'd301, 3'd1}; + 7'h52: rom <= { 9'd284, 3'd1}; + 7'h53: rom <= { 9'd268, 3'd1}; + 7'h54: rom <= { 9'd253, 3'd1}; + 7'h55: rom <= { 9'd253, 3'd1}; + 7'h56: rom <= { 9'd253, 3'd1}; + 7'h57: rom <= { 9'd013, 3'd7}; + // noise generator according to data sheet is pitch data $7F + // but MAME uses any value above $58 + default: begin noise <= 1; rom <= { 9'd000, 3'd3}; end + // default: rom <= 0; + endcase +end + +endmodule \ No newline at end of file diff --git a/snapshots/jotego_jtcores_pr1242/modules/jt5232/hdl/jt5232_tg.v b/snapshots/jotego_jtcores_pr1242/modules/jt5232/hdl/jt5232_tg.v new file mode 100644 index 0000000000000000000000000000000000000000..12e782d2559c8434a43ea560f4069a86c8b9199c --- /dev/null +++ b/snapshots/jotego_jtcores_pr1242/modules/jt5232/hdl/jt5232_tg.v @@ -0,0 +1,68 @@ +/* This file is part of JTCORES. + JTCORES program is free software: you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation, either version 3 of the License, or + (at your option) any later version. + + JTCORES program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with JTCORES. If not, see . + + Author: Jose Tejada Gomez. Twitter: @topapate + Version: 1.0 + Date: 6-12-2024 */ + +// the ' means feet in an organ pipe length +// output 2' = 4*f +// output 4' = 2*f +// output 8' is the base pitch = f +// output 16' = f/2 + +module jt5232_tg( + input rst, + input clk, + input cen, + input [ 8:0] step, + input [ 2:0] bsel, // bit selection + input [ 3:0] pipe_en, + output reg [ 2:0] organ +); + +reg [ 8:0] cnt=0; +wire [ 8:0] nxc; +reg [ 3:0] pipes=0; +reg [ 7:0] h=0; // harmonics +wire [ 7:0] hnx; +reg hl; +wire over, over2; + +assign over = cnt==step; +assign over2 = cnt==(step>>1); +assign hnx = h+8'd1; + +always @(posedge clk) if(cen) begin + cnt <= over ? 9'd0 : cnt+9'd1; + // counts twice, at the middle and at the end + if(over2 && !hl) begin hl<=1; h <= hnx; end + if(over ) begin hl<=0; h <= hnx; end + case(bsel) + 1: pipes <= {h[0],h[0],h[0],h[1]}; + 2: pipes <= {h[0],h[0],h[1],h[2]}; + 3: pipes <= {h[0],h[1],h[2],h[3]}; + 4: pipes <= {h[1],h[2],h[3],h[4]}; + 5: pipes <= {h[2],h[3],h[4],h[5]}; + 6: pipes <= {h[3],h[4],h[5],h[6]}; + 7: pipes <= {h[4],h[5],h[6],h[7]}; + endcase + if(!pipe_en[0]) pipes[0] <= 0; + if(!pipe_en[1]) pipes[1] <= 0; + if(!pipe_en[2]) pipes[2] <= 0; + if(!pipe_en[3]) pipes[3] <= 0; + organ <= {2'd0,pipes[0]}+{2'd0,pipes[1]}+{2'd0,pipes[2]}+{2'd0,pipes[3]}; +end + +endmodule \ No newline at end of file diff --git a/snapshots/jotego_jtcores_pr1242/modules/jt5232/ver/.gitignore b/snapshots/jotego_jtcores_pr1242/modules/jt5232/ver/.gitignore new file mode 100644 index 0000000000000000000000000000000000000000..83d415ddd5a27aeace71d0378751f152ae94da18 --- /dev/null +++ b/snapshots/jotego_jtcores_pr1242/modules/jt5232/ver/.gitignore @@ -0,0 +1,2 @@ +sim* + diff --git a/snapshots/jotego_jtcores_pr1242/modules/jt5232/ver/eg/sim.sh b/snapshots/jotego_jtcores_pr1242/modules/jt5232/ver/eg/sim.sh new file mode 100644 index 0000000000000000000000000000000000000000..a0f0aa5746972aab03cf8dbaad3ecd5991e118af --- /dev/null +++ b/snapshots/jotego_jtcores_pr1242/modules/jt5232/ver/eg/sim.sh @@ -0,0 +1,3 @@ +#!/bin/bash +iverilog -g2012 ../../hdl/*.v test.v -o sim -DSIMULATION -DJTFRAME_MCLK=48000000 && sim -lxt +rm -f sim diff --git a/snapshots/jotego_jtcores_pr1242/modules/jt5232/ver/eg/test.v b/snapshots/jotego_jtcores_pr1242/modules/jt5232/ver/eg/test.v new file mode 100644 index 0000000000000000000000000000000000000000..ae024fbfa7c2d22c2854a57c1ef19250df9000b4 --- /dev/null +++ b/snapshots/jotego_jtcores_pr1242/modules/jt5232/ver/eg/test.v @@ -0,0 +1,94 @@ +`timescale 1ns / 1ps + +module test; + +`include "../../hdl/jt5232.vh" + +reg clk=0, we, rst, clk_ref=0; +wire cen1, cen2; +wire [TW-1:0] tone_a, tone_b; +reg [ 1:0] div=0; +reg [ 7:0] din; +reg [ 3:0] addr; + +assign cen1 = clk & div[0]; +assign cen2 = clk && div==1; + +initial forever #10.416 clk =~clk; // 48 MHz + + +always @(posedge clk) begin + div <= div+2'd1; +end + +integer fsel; +wire fsignal = uut.u_tg0.pipes[fsel]; + +initial begin + we=0; din=0; addr=0; + // reset + rst=1; + repeat(20) @(negedge clk); + @(negedge uut.cen256); + rst=0; + repeat(20) @(negedge clk); + // enable harmonics and EG + addr=12; din=8'h2f; we=1; @(negedge clk); + we=0; @(negedge clk); + // program 440 Hz signal + // Try fast ON/OFF + @(negedge clk); + addr=0; din=8'hA1; we=1; @(negedge clk); + we=0; @(negedge clk); + repeat(200) @(negedge uut.cen256); + @(negedge clk); + addr=0; din=8'h21; we=1; @(negedge clk); + we=0; @(negedge clk); + repeat(2_000) @(negedge uut.cen256); + @(negedge clk); + addr=0; din=8'hA1; we=1; @(negedge clk); + we=0; @(negedge clk); + repeat(4000) @(negedge uut.cen256); + // release + @(negedge clk); + addr=0; din=8'h21; we=1; @(negedge clk); + we=0; @(negedge clk); + repeat(20_000) @(negedge uut.cen256); + // + // try ARM=1 + @(negedge clk); + addr=12; din=8'h30; we=1; @(negedge clk); + we=0; @(negedge clk); + @(negedge clk); + addr=0; din=8'hA1; we=1; @(negedge clk); + we=0; @(negedge clk); + repeat(20_000) @(negedge uut.cen256); + @(negedge clk); // key off + addr=0; din=8'h21; we=1; @(negedge clk); + we=0; @(negedge clk); + repeat(20_000) @(negedge uut.cen256); + $display("PASS"); + $finish; +end + +jt5232 uut( + .rst ( rst ), + .clk ( clk ), + .cen1 ( cen1 ), + .cen2 ( cen2 ), + .din ( din ), + .addr ( addr ), + .we ( we ), + .snd1 ( tone_a ), + .snd2 ( tone_b ) +); + +initial begin + $dumpfile("test.lxt"); + $dumpvars; + $dumpon; + #400_000_000; + $fatal(1,"Time over\nFAIL"); // fallback +end + +endmodule diff --git a/snapshots/jotego_jtcores_pr1242/modules/jt5232/ver/eg_attack/sim.sh b/snapshots/jotego_jtcores_pr1242/modules/jt5232/ver/eg_attack/sim.sh new file mode 100644 index 0000000000000000000000000000000000000000..a0f0aa5746972aab03cf8dbaad3ecd5991e118af --- /dev/null +++ b/snapshots/jotego_jtcores_pr1242/modules/jt5232/ver/eg_attack/sim.sh @@ -0,0 +1,3 @@ +#!/bin/bash +iverilog -g2012 ../../hdl/*.v test.v -o sim -DSIMULATION -DJTFRAME_MCLK=48000000 && sim -lxt +rm -f sim diff --git a/snapshots/jotego_jtcores_pr1242/modules/jt5232/ver/eg_attack/test.v b/snapshots/jotego_jtcores_pr1242/modules/jt5232/ver/eg_attack/test.v new file mode 100644 index 0000000000000000000000000000000000000000..b8dc407939f4a83ea19e300b7dac4b9cf2e31a4b --- /dev/null +++ b/snapshots/jotego_jtcores_pr1242/modules/jt5232/ver/eg_attack/test.v @@ -0,0 +1,106 @@ +`timescale 1ns / 1ps + +module test; + +`include "../../hdl/jt5232.vh" + +reg clk=0, we, rst, clk_ref=0; +wire cen1, cen2; +wire [TW-1:0] tone_a, tone_b; +reg [ 1:0] div=0; +reg [ 7:0] din; +reg [ 3:0] addr; +reg [ 3:0] atime=0; +reg loop=0; +real t0,t1; +wire [ 11:0] eg; + +assign cen1 = clk & div[0]; +assign cen2 = clk && div==1; +assign eg = uut.eg[0+:12]; + +initial forever #10.416 clk =~clk; // 48 MHz + +always @(posedge clk) begin + div <= div+2'd1; +end + +integer fsel; +wire fsignal = uut.u_tg0.pipes[fsel]; + +task check_time; + input real tdiff; + input real exp; +begin + assert(exp*0.9<(tdiff/1e6)&&exp*1.1>(tdiff/1e6)) else + $fatal(1,"attack time not met. %.0f ms expected, got %.0f ms",exp,tdiff/1e6); +end +endtask + +task meas_attack; +begin + we=0; din=0; addr=0; + // reset + rst=1; + repeat(20) @(negedge clk); + @(negedge uut.cen256); + rst=0; + repeat(20) @(negedge clk); + // enable harmonics and EG, sustained mode + addr=GCTL1; din=8'h3f; we=1; @(negedge clk); + we=0; @(negedge clk); + // set attack time + addr=ATIME1; din={5'd0,atime[2:0]}; we=1; @(negedge clk); + we=0; @(negedge clk); + // program 440 Hz signal + @(negedge clk); + addr=0; din=8'hA1; we=1; @(negedge clk); + we=0; @(negedge clk); + t0 = $time; + loop = 1; + for(;loop;) begin + @(negedge uut.cen256); + if(eg>=3685) begin + t1=$time; + loop=0; + end + end + $display("Attack time: $%d -> %.0f ms",atime[2:0],(t1-t0)/1e6); + case(atime[2:0]) + 0: check_time(t1-t0,2); + 1: check_time(t1-t0,4); + 2: check_time(t1-t0,8); + 3: check_time(t1-t0,16); + 3'b1?0: check_time(t1-t0,32); + 3'b1?1: check_time(t1-t0,64); + endcase +end +endtask + +initial begin + for(atime = 0; atime<8;atime=atime+1) meas_attack; + $display("PASS"); + $finish; +end + +jt5232 uut( + .rst ( rst ), + .clk ( clk ), + .cen1 ( cen1 ), + .cen2 ( cen2 ), + .din ( din ), + .addr ( addr ), + .we ( we ), + .snd1 ( tone_a ), + .snd2 ( tone_b ) +); + +initial begin + $dumpfile("test.lxt"); + $dumpvars; + $dumpon; + #500_000_000; + $fatal(1,"Time over\nFAIL"); // fallback +end + +endmodule diff --git a/snapshots/jotego_jtcores_pr1242/modules/jt5232/ver/eg_decay/fast.sh b/snapshots/jotego_jtcores_pr1242/modules/jt5232/ver/eg_decay/fast.sh new file mode 100644 index 0000000000000000000000000000000000000000..ef264c0b3541d086a52f05f871847b59c06682bf --- /dev/null +++ b/snapshots/jotego_jtcores_pr1242/modules/jt5232/ver/eg_decay/fast.sh @@ -0,0 +1,7 @@ +#!/bin/bash -e +for i in 1 2 8 9;do + iverilog -g2012 ../../hdl/*.v test.v -o sim$i -DSINGLE=$i -DSIMULATION -DJTFRAME_MCLK=48000000 + nice sim$i & +done +wait +rm -f sim* diff --git a/snapshots/jotego_jtcores_pr1242/modules/jt5232/ver/eg_decay/parallel.sh b/snapshots/jotego_jtcores_pr1242/modules/jt5232/ver/eg_decay/parallel.sh new file mode 100644 index 0000000000000000000000000000000000000000..0f4069f355be82c887b6479116c4268d7a34575f --- /dev/null +++ b/snapshots/jotego_jtcores_pr1242/modules/jt5232/ver/eg_decay/parallel.sh @@ -0,0 +1,7 @@ +#!/bin/bash -e +for i in {0..15};do + iverilog -g2012 ../../hdl/*.v test.v -o sim$i -DSINGLE=$i -DSIMULATION -DJTFRAME_MCLK=48000000 + nice sim$i & +done +wait +rm -f sim* diff --git a/snapshots/jotego_jtcores_pr1242/modules/jt5232/ver/eg_decay/test.v b/snapshots/jotego_jtcores_pr1242/modules/jt5232/ver/eg_decay/test.v new file mode 100644 index 0000000000000000000000000000000000000000..ea51b7580f6f485b95cf2c4adc1148e3a91f1492 --- /dev/null +++ b/snapshots/jotego_jtcores_pr1242/modules/jt5232/ver/eg_decay/test.v @@ -0,0 +1,135 @@ +`timescale 1ns / 1ps + +module test; + +`include "../../hdl/jt5232.vh" + +reg clk=0, we, rst, clk_ref=0; +wire cen1, cen2; +wire [TW-1:0] tone_a, tone_b; +reg [ 1:0] div=0; +reg [ 7:0] din; +reg [ 3:0] addr; +reg [ 4:0] dtime=0; +reg loop=0; +real t0,t1; +wire [ 11:0] eg; +reg [ 11:0] eg_l; + +assign cen1 = clk & div[0]; +assign cen2 = clk && div==1; +assign eg = uut.eg[0+:12]; + +initial forever #10.416 clk =~clk; // 48 MHz + +always @(posedge clk) begin + div <= div+2'd1; +end + +integer fsel; +wire fsignal = uut.u_tg0.pipes[fsel]; + +task check_time; + input real tdiff; + input real exp; +begin + assert(exp*0.9<(tdiff/1e6)&&exp*1.1>(tdiff/1e6)) else + $fatal(1,"attack time not met. %.0f ms expected, got %.0f ms",exp,tdiff/1e6); +end +endtask + +task meas_decay; +begin + we=0; din=0; addr=0; + // reset + rst=1; + repeat(20) @(negedge clk); + @(negedge uut.cen256); + rst=0; + repeat(20) @(negedge clk); + // enable harmonics and EG, decay mode + addr=GCTL1; din=8'h2f; we=1; @(negedge clk); + we=0; @(negedge clk); + // set decay time + addr=DTIME1; din={5'd0,dtime[3:0]}; we=1; @(negedge clk); + we=0; @(negedge clk); + // program 440 Hz signal + @(negedge clk); + addr=0; din=8'hA1; we=1; @(negedge clk); + we=0; @(negedge clk); + // wait for attack phase to finish + loop = 1; + for(;loop;) begin + eg_l = eg; + @(negedge uut.cen256); + if(eg %.0f ms",dtime[3:0],(t1-t0)/1e6); + case(dtime[3:0]) + 4'd0: check_time(t1-t0,40); + 4'd1: check_time(t1-t0,80); + 4'd2: check_time(t1-t0,160); + 4'd3: check_time(t1-t0,320); + 4'b01?0: check_time(t1-t0,640); + 4'b01?1: check_time(t1-t0,1300); + 4'd8: check_time(t1-t0,250); + 4'd9: check_time(t1-t0,500); + 4'd10: check_time(t1-t0,1000); + 4'd11: check_time(t1-t0,2000); + 4'b11?0: check_time(t1-t0,4000); + 4'b11?1: check_time(t1-t0,8000); + endcase +end +endtask + +initial begin +`ifdef SINGLE + dtime=`SINGLE; + meas_decay; +`else + $display("Simulating all 16 cases"); + for(dtime = 0; dtime<16;dtime=dtime+1) meas_decay; +`endif + $display("PASS"); + $finish; +end + +jt5232 uut( + .rst ( rst ), + .clk ( clk ), + .cen1 ( cen1 ), + .cen2 ( cen2 ), + .din ( din ), + .addr ( addr ), + .we ( we ), + .snd1 ( tone_a ), + .snd2 ( tone_b ) +); + +initial begin +`ifdef KEEP + $dumpfile("test.lxt"); + $dumpvars; + $dumpon; +`endif +`ifdef SINGLE + #8_500_000_000; // 8.5s +`else + #33_000_000_000; // 33 s +`endif + $fatal(1,"Time over\nFAIL"); // fallback +end + +endmodule diff --git a/snapshots/jotego_jtcores_pr1242/modules/jt5232/ver/sim.sh b/snapshots/jotego_jtcores_pr1242/modules/jt5232/ver/sim.sh new file mode 100644 index 0000000000000000000000000000000000000000..a0f0aa5746972aab03cf8dbaad3ecd5991e118af --- /dev/null +++ b/snapshots/jotego_jtcores_pr1242/modules/jt5232/ver/sim.sh @@ -0,0 +1,3 @@ +#!/bin/bash +iverilog -g2012 ../../hdl/*.v test.v -o sim -DSIMULATION -DJTFRAME_MCLK=48000000 && sim -lxt +rm -f sim diff --git a/snapshots/jotego_jtcores_pr1242/modules/jt5232/ver/tones/sim.sh b/snapshots/jotego_jtcores_pr1242/modules/jt5232/ver/tones/sim.sh new file mode 100644 index 0000000000000000000000000000000000000000..a0f0aa5746972aab03cf8dbaad3ecd5991e118af --- /dev/null +++ b/snapshots/jotego_jtcores_pr1242/modules/jt5232/ver/tones/sim.sh @@ -0,0 +1,3 @@ +#!/bin/bash +iverilog -g2012 ../../hdl/*.v test.v -o sim -DSIMULATION -DJTFRAME_MCLK=48000000 && sim -lxt +rm -f sim diff --git a/snapshots/jotego_jtcores_pr1242/modules/jt5232/ver/tones/test.v b/snapshots/jotego_jtcores_pr1242/modules/jt5232/ver/tones/test.v new file mode 100644 index 0000000000000000000000000000000000000000..06ef290e47f7db3c36285564940fd4a8d536f7cb --- /dev/null +++ b/snapshots/jotego_jtcores_pr1242/modules/jt5232/ver/tones/test.v @@ -0,0 +1,97 @@ +`timescale 1ns / 1ps + +module test; + +`include "../../hdl/jt5232.vh" + +reg clk=0, we, rst, clk_ref=0; +wire cen1, cen2; +wire [TW-1:0] tone_a, tone_b; +reg [ 1:0] div=0; +reg [ 7:0] din; +reg [ 3:0] addr; + +assign cen1 = clk & div[0]; // 2119040 Hz +assign cen2 = clk && div==1; // 2119040/2 Hz + +initial forever #117.978 clk =~clk; // 2*2119040 Hz + + +always @(posedge clk) begin + div <= div+2'd1; +end + +integer fsel; +wire fsignal = uut.u_tg0.pipes[fsel]; + +task check_freq(input integer sel, input real freq); + real t0,t1,fo; + begin + fsel=sel; + repeat(2) @(posedge fsignal); + t0=$time; + repeat(10) @(posedge fsignal); + t1=$time; + fo=10.0/(t1-t0)*1e9; + assert(fo>freq*0.9 && fo %.0f Hz (should be %.0f)",fsel,fo,freq); + end +endtask + +initial begin + we=0; din=0; addr=0; + // reset + rst=1; + repeat(20) @(negedge clk); + rst=0; + repeat(20) @(negedge clk); + // program 440 Hz signal + addr=0; din=8'h21|8'h80; we=1; @(negedge clk); + we=0; @(negedge clk); + // repeat(20) assert(uut.u_tg0.harmonics==0) else $fatal(1,"harmonics should be zero at %t",$time); + // enable harmonics + addr=12; din=8'hf; we=1; @(negedge clk); + we=0; @(negedge clk); + repeat(20) @(negedge clk); + // check the frequency for each harmonic output + $display("440Hz test"); + check_freq(1,440*1); + check_freq(0,440/2); + check_freq(2,440*2); + check_freq(3,440*4); + // program 261.74 Hz + @(negedge clk); + addr=0; din=8'h19|8'h80; we=1; @(negedge clk); + we=0; @(negedge clk); + repeat(20) @(negedge clk); + // check the frequency for each harmonic output + $display("277Hz test"); + check_freq(1,277*1); + check_freq(0,277/2); + check_freq(3,277*4); + check_freq(2,277*2); + $display("PASS"); + $finish; +end + +jt5232 uut( + .rst ( rst ), + .clk ( clk ), + .cen1 ( cen1 ), + .cen2 ( cen2 ), + .din ( din ), + .addr ( addr ), + .we ( we ), + .snd1 ( tone_a ), + .snd2 ( tone_b ) +); + +initial begin + $dumpfile("test.lxt"); + $dumpvars; + $dumpon; + #600_000_000; + $fatal(1,"Time over\nFAIL"); // fallback +end + +endmodule diff --git a/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cheat/jtframe_cheat.v b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cheat/jtframe_cheat.v new file mode 100644 index 0000000000000000000000000000000000000000..c39f141833c581147c4eacc9888652a3fcbce4d2 --- /dev/null +++ b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cheat/jtframe_cheat.v @@ -0,0 +1,391 @@ +/* This file is part of JTFRAME. + JTFRAME program is free software: you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation, either version 3 of the License, or + (at your option) any later version. + + JTFRAME program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with JTFRAME. If not, see . + + Author: Jose Tejada Gomez. Twitter: @topapate + Version: 1.0 + Date: 1-6-2021 */ + +module jtframe_cheat #(parameter AW=22)( + input rst, + input clk_rom, + input clk_pico, // always 48 MHz + + input LVBL, + input [31:0] status, + + // From/to game + input [AW-1:0] game_addr, + input game_rd, + input game_wr, + input [ 15:0] game_din, + input [ 1:0] game_din_m, + output reg game_ack, + output reg game_dst, + output reg game_rdy, + + // From/to SDRAM bank 0 + output reg [AW-1:0] ba0_addr, + output reg ba0_rd, + output reg ba0_wr, + input ba0_ack, + input ba0_dst, + input ba0_rdy, + output reg [ 15:0] ba0_din, + output reg [ 1:0] ba0_din_m, + input [ 15:0] data_read, + + // control + input [31:0] flags, + input [ 7:0] joy1, + input [15:0] joyana_l1, + input [15:0] joyana_r1, + + input [ 7:0] joy2, + input [15:0] joyana_l2, + input [15:0] joyana_r2, + + output reg led, + input [31:0] timestamp, + input pause_in, + output pause_out, + input locked, + + // Communication with game module + output reg [7:0] st_addr, + input [7:0] st_dout, + input [7:0] debug_bus, + + // Video RAM + output reg [9:0] vram_addr, + output reg [7:0] vram_dout, + input [7:0] vram_din, + output reg vram_we, + output reg [2:0] vram_ctrl, + + // UART + input uart_rx, // Define JTFRAME_UART for OSD options to show + output uart_tx, + + // PBlaze Program + input prog_en, // resets the address counter + input prog_wr, // strobe for new data + input [7:0] prog_addr, // only 8 bits are needed regardless of actual length + input [7:0] prog_data +); + +localparam CHEATW=10; // 12=>9kB (8 BRAM) + // 10=>2.25kB (2 BRAM), 9=>1.12kB (1 BRAM) + +localparam [31:0] BUILDTIME = `JTFRAME_TIMESTAMP; // Build time + +// UART works at 57.6 kbps for 48MHz, 115.2 for 96MHz +localparam [4:0] UART_DIV=29; + +wire clk = clk_pico; + +// Instruction ROM +wire [11:0] iaddr; +wire [17:0] idata; + +// Ports +wire [ 7:0] pout, paddr; +reg [ 7:0] pin=0; +wire pwr, kwr, prd; + +// interrupts +reg irq=0, LVBL_last; +wire iack; + +// uptime +reg [ 5:0] frame_cnt=0; +reg [23:0] sec_cnt=0; // count up to 194 days +wire [31:0] cur_time = timestamp + {8'd0, sec_cnt}; + +// UART +wire [ 7:0] uart_dout; +reg uart_clr; +wire uart_wr, uart_busy, uart_rdy, uart_error; + +reg [ 3:0] watchdog; +reg prst=0; + +assign pause_out = pause_in; +// UART +assign uart_wr = pwr && paddr==8'h34; + +always @(posedge clk) begin + prst <= watchdog[3] | rst; +end + +`ifdef JTFRAME_EXPIRATION + localparam [31:0] EXPIRATION = `JTFRAME_EXPIRATION; + reg expired; + + always @(posedge clk) expired = cur_time > EXPIRATION; +`else + wire expired=0; +`endif + +always @(posedge clk) begin + LVBL_last <= LVBL; + if( !LVBL && LVBL_last ) begin + if( frame_cnt==59 ) begin + frame_cnt <= 0; + sec_cnt <= sec_cnt + 1'd1; + end else begin + frame_cnt <= frame_cnt+1; + end + end +end + +always @(posedge clk) begin + if( prst ) begin + irq <= 0; + end else begin + if( !LVBL && LVBL_last ) + irq <= 1; + else if( iack ) irq <= 0; + end +end + +// Ports +reg [ 7:0] ports[0:5]; +reg [ 7:0] sdram_lsb, sdram_msb; +wire [23:0] blaze_sdram_addr; +wire [15:0] blaze_sdram_din; +wire [ 1:0] blaze_sdram_din_m; + +// SDRAM +reg sdram_busy=0, pico_busy=0, owner=0, sdram_req=0, sdram_req_wr=0; + +assign blaze_sdram_addr = { ports[2], ports[1], ports[0] }; +assign blaze_sdram_din = { ports[4], ports[3] }; +assign blaze_sdram_din_m = ports[5][1:0]; + +// VRAM +always @(posedge clk) begin + if( prst ) begin + vram_we <= 0; + vram_ctrl <= 0; + end else begin + vram_we <= 0; + if( (pwr|kwr) && paddr[7:3]==5'b0000_1 ) begin + case( paddr[2:0] ) + 0: vram_addr[4:0] <= pout[4:0]; + 1: vram_addr[9:5] <= pout[4:0]; + 2: { vram_we, vram_dout } <= { 1'b1, 1'b1, pout[6:0] }; + 3: vram_ctrl <= pout[2:0]; + endcase + end + end +end + +always @(posedge clk) begin + if( (pwr|kwr) && paddr<=5 ) begin + ports[ paddr[2:0] ] <= pout; + end + // Game status + if( (pwr|kwr) && paddr==8'hc ) begin + st_addr <= pout; + end + // watchdog + if( !LVBL && LVBL_last ) begin + watchdog <= watchdog+1'd1; + end + if( (pwr && paddr[7:6]==2'b01) || prst ) + watchdog <= 0; + // led + if( prst ) + led <= 0; + else if( (pwr|kwr) && paddr==6 ) + led <= pout[0]; +end + +reg [7:0] timemux; + +always @(*) begin + case( paddr[7:0] ) + 8'h20: timemux = timestamp[ 7: 0]; + 8'h21: timemux = timestamp[15: 8]; + 8'h22: timemux = timestamp[23:16]; + 8'h23: timemux = timestamp[31:24]; + 8'h24: timemux = BUILDTIME[ 7: 0]; + 8'h25: timemux = BUILDTIME[15: 8]; + 8'h26: timemux = BUILDTIME[23:16]; + 8'h27: timemux = BUILDTIME[31:24]; + 8'h28: timemux = cur_time[ 7: 0]; + 8'h29: timemux = cur_time[15: 8]; + 8'h2a: timemux = cur_time[23:16]; + 8'h2b: timemux = cur_time[31:24]; + 8'h2c: timemux = {2'd0, frame_cnt }; + default: timemux = 0; + endcase +end + +always @(posedge clk) begin + if(prst) begin + pin <= 0; + uart_clr <= 0; + end else begin + uart_clr <= 0; + if(prd) begin + casez( paddr[7:0] ) + 0,1,2,3,4,5: + pin <= ports[ paddr[2:0] ]; + 6: pin <= sdram_lsb; + 7: pin <= sdram_msb; + // VRAM or status + 8'h0a: pin <= vram_din; + 8'h0d: pin <= st_dout; + 8'h0f: pin <= debug_bus; + + // Flags + 8'h10: pin <= flags[ 7: 0]; + 8'h11: pin <= flags[15: 8]; + 8'h12: pin <= flags[23:16]; + 8'h13: pin <= flags[31:24]; + + // Board status + 8'h14: pin <= status[ 7: 0]; + 8'h15: pin <= status[15: 8]; + 8'h16: pin <= status[23:16]; + 8'h17: pin <= status[31:24]; + + // Joystick + 8'h18: pin <= joy1; + 8'h1a: pin <= joyana_l1[ 7:0]; + 8'h1b: pin <= joyana_l1[15:8]; + 8'h1c: pin <= joyana_r1[ 7:0]; + 8'h1d: pin <= joyana_r1[15:8]; + 8'h48: pin <= joy2; + 8'h4a: pin <= joyana_l2[ 7:0]; + 8'h4b: pin <= joyana_l2[15:8]; + 8'h4c: pin <= joyana_r2[ 7:0]; + 8'h4d: pin <= joyana_r2[15:8]; + + + 8'h2?: pin <= timemux; // Time + // UART + 8'h34: begin + pin <= uart_dout; + uart_clr <= 1; + end + 8'h35: pin <= { 3'b0, uart_error, 2'b0, uart_busy, uart_rdy }; + 8'h80: pin <= { owner, pico_busy, LVBL, 3'b0, expired, locked }; // 8'hc0 means that the SDRAM data is ready + default: pin <= 0; + endcase + end + end +end + + +// SDRAM signals must use clk_rom +always @(posedge clk_rom) begin + if( ba0_dst && owner ) begin + {sdram_msb, sdram_lsb} <= data_read; + end + if( pwr && paddr[7] && !locked ) begin + sdram_req <= 1; + sdram_req_wr <= paddr[6]; + end + if( ba0_ack && owner ) begin + sdram_req <= 0; + end +end + +// SDRAM arbitrer +always @(posedge clk_rom) begin + if( ba0_rdy ) begin + sdram_busy <= 0; + if( owner ) pico_busy <= 0; + end + if( !sdram_busy ) begin + if( game_rd || game_wr ) begin + sdram_busy <= 1; + owner <= 0; + end else if( sdram_req ) begin + sdram_busy <= 1; + owner <= 1; + pico_busy <= 1; + end + end +end + +always @(*) begin + ba0_addr = owner ? blaze_sdram_addr : game_addr; + ba0_rd = owner ? (sdram_req & ~sdram_req_wr) : game_rd; + ba0_wr = owner ? (sdram_req & sdram_req_wr) : game_wr; + ba0_din = owner ? blaze_sdram_din : game_din; + ba0_din_m = owner ? blaze_sdram_din_m : game_din_m; + game_dst = ~owner & ba0_dst; + game_rdy = ~owner & ba0_rdy; + game_ack = ~owner & ba0_ack; +end + +// PicoBlaze compatible module + +pauloBlaze u_blaze( + .clk ( clk ), + .reset ( prst ), + .sleep ( 1'b0 ), + + .address ( iaddr ), + .instruction ( idata ), + .bram_enable ( ), + + .in_port ( pin ), + .out_port ( pout ), + .port_id ( paddr ), + .write_strobe ( pwr ), + .k_write_strobe ( kwr ), + .read_strobe ( prd ), + + //.interrupt ( irq ), + .interrupt ( 1'b0 ), // The interrupt in pauloBlaze is buggy + .interrupt_ack ( iack ) +); + +jtframe_uart #( + .CLK_DIVIDER( UART_DIV ) +) u_uart( + .rst ( rst ), + .clk ( clk ), + // serial wires + .uart_rx ( uart_rx ), + .uart_tx ( uart_tx ), // serial signal to transmit. High when idle + // Rx interface + .rx_data ( uart_dout ), + .rx_error ( uart_error), + .rx_rdy ( uart_rdy ), + .rx_clr ( uart_clr ), // clear the rx_rdy flag + // Tx interface + .tx_busy ( uart_busy ), + .tx_data ( pout ), + .tx_wr ( uart_wr ) // write strobe +); + +jtframe_cheat_rom #(.AW(CHEATW)) u_rom( + .rst ( rst ), + .clk_rom ( clk_rom ), + .clk_pico ( clk_pico ), + .iaddr ( iaddr[CHEATW-1:0] ), + .idata ( idata ), + // PBlaze Program + .prog_addr ( prog_addr ), + .prog_en ( prog_en ), // resets the address counter + .prog_wr ( prog_wr ), // strobe for new data + .prog_data ( prog_data ) +); + +endmodule diff --git a/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cheat/jtframe_cheat_rom.v b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cheat/jtframe_cheat_rom.v new file mode 100644 index 0000000000000000000000000000000000000000..9c31202d1fb7682f592bcfab1fb124e0f1728ba1 --- /dev/null +++ b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cheat/jtframe_cheat_rom.v @@ -0,0 +1,126 @@ +/* This file is part of JTFRAME. + JTFRAME program is free software: you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation, either version 3 of the License, or + (at your option) any later version. + + JTFRAME program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with JTFRAME. If not, see . + + Author: Jose Tejada Gomez. Twitter: @topapate + Version: 1.0 + Date: 1-6-2021 */ + +module jtframe_cheat_rom #(parameter AW=10)( + input rst, + input clk_rom, + input clk_pico, + input [AW-1:0] iaddr, + output [17:0] idata, + // PBlaze Program + input prog_en, // resets the address counter + input prog_wr, // strobe for new data + input [7:0] prog_addr, + input [7:0] prog_data +); + +// 8 to 18 bit conversion +reg [15:0] prog_fifo; +reg last_en, prog_post; +reg [17:0] prog_word; +reg word_we; +reg [ 3:0] word_cnt; +reg [AW-1:0] prom_addr; +wire [17:0] iraw; +reg irom_ok=0; // reset only at FPGA programming + +// If the ROM has not been loaded, it outputs 0 +assign idata = irom_ok ? iraw : 18'd0; + +`ifdef JTFRAME_CHEAT_SCRAMBLE + reg [7:0] new_data; + reg [7:0] mask; + localparam [15:0] SCRAMBLE = `JTFRAME_CHEAT_SCRAMBLE; + + initial $display("scramble!"); + + always @(*) begin + new_data = prog_data; + mask = prog_addr[7:0] ^ SCRAMBLE[7:0]; + if( mask[0] ) new_data[1:0] = {new_data[0], new_data[1]}; + if( mask[1] ) new_data[3:2] = {new_data[2], new_data[3]}; + if( mask[2] ) new_data[5:4] = {new_data[4], new_data[5]}; + if( mask[3] ) new_data[7:6] = {new_data[6], new_data[7]}; + new_data = new_data ^ SCRAMBLE[15:8]; + if( mask[4] ) new_data[1:0] = {new_data[0], new_data[1]}; + if( mask[5] ) new_data[3:2] = {new_data[2], new_data[3]}; + if( mask[6] ) new_data[5:4] = {new_data[4], new_data[5]}; + if( mask[7] ) new_data[7:6] = {new_data[6], new_data[7]}; + end +`else + wire [7:0] new_data = prog_data; +`endif + +always @(posedge clk_rom) begin + last_en <= prog_en; + if(word_we) irom_ok <= 1; + if( prog_en & ~last_en ) begin + word_cnt <= 0; + prog_post <= 0; + prom_addr <= 0; + prog_word <= 0; + end else begin + if( prog_wr & prog_en ) begin + prog_fifo <= { new_data, prog_fifo[15:8] }; + word_cnt <= word_cnt[3] ? 4'd0 : word_cnt + 4'd1; + case( word_cnt ) + 2: begin + word_we <= 1; + prog_word <= { new_data[1:0], prog_fifo }; + end + 4: begin + word_we <= 1; + prog_word <= { new_data[3:0], prog_fifo[15:2] }; + end + 6: begin + word_we <= 1; + prog_word <= { new_data[5:0], prog_fifo[15:4] }; + end + 8: begin + word_we <= 1; + prog_word <= { new_data[7:0], prog_fifo[15:6] }; + end + default: word_we <= 0; + endcase + end else begin + word_we <= 0; + end + if( word_we ) prom_addr <= prom_addr+1'd1; + end +end + +jtframe_dual_ram #( + .DW ( 18 ), + .AW ( AW ) + //.SIMHEXFILE("cheat.hex") +) u_irom( + .clk0 ( clk_rom ), + .clk1 ( clk_pico ), + // Port 0 + .data0 ( prog_word ), + .addr0 ( prom_addr ), + .we0 ( word_we ), + .q0 ( ), + // Port 1 + .data1 ( ), + .addr1 ( iaddr[AW-1:0] ), + .we1 ( 1'b0 ), + .q1 ( iraw ) +); + +endmodule diff --git a/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/clocking/jtframe_cen24.v b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/clocking/jtframe_cen24.v new file mode 100644 index 0000000000000000000000000000000000000000..c73c37090986bc51f64812ec36740c8b066acf59 --- /dev/null +++ b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/clocking/jtframe_cen24.v @@ -0,0 +1,64 @@ +/* This file is part of JTFRAME. + JTFRAME program is free software: you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation, either version 3 of the License, or + (at your option) any later version. + + JTFRAME program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with JTFRAME. If not, see . + + Author: Jose Tejada Gomez. Twitter: @topapate + Version: 1.0 + Date: 6-12-2019 */ + +// Input clock must be 24 MHz +// Generates various clock enable signals + +module jtframe_cen24( + input clk, // 24 MHz + output reg cen12, + output cen8, + output reg cen6, + output reg cen4, + output reg cen3, + output reg cen3q, // 1/4 advanced with respect to cen3 + output reg cen1p5, + // 180 shifted signals + output reg cen12b, + output reg cen6b, + output reg cen3b, + output reg cen3qb, + output reg cen1p5b +); + +reg [3:0] cencnt =4'd0; +reg [2:0] cencnt3=3'd0; +reg [2:0] cencnt8=3'd1; + +assign cen8 = cencnt8[2]; + +always @(posedge clk) begin + cencnt <= cencnt+4'd1; + cencnt3 <= cencnt3==3'd5 ? 3'd0 : (cencnt3+3'd1); + cencnt8 <= { cencnt8[1:0], cencnt8[2] }; +end + +always @(posedge clk) begin + cen12 <= cencnt[0] == 1'd0; + cen12b <= cencnt[0] == 1'd1; + cen4 <= cencnt3 == 3'd0; + cen6 <= cencnt[1:0] == 2'd0; + cen6b <= cencnt[1:0] == 2'd2; + cen3 <= cencnt[2:0] == 3'd0; + cen3b <= cencnt[2:0] == 3'h4; + cen3q <= cencnt[2:0] == 3'b110; + cen3qb <= cencnt[2:0] == 3'b010; + cen1p5 <= cencnt[3:0] == 4'd0; + cen1p5b<= cencnt[3:0] == 4'b1000; +end +endmodule diff --git a/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/clocking/jtframe_cen48.v b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/clocking/jtframe_cen48.v new file mode 100644 index 0000000000000000000000000000000000000000..7118cea585f0c80a301651559a3cb1176322762d --- /dev/null +++ b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/clocking/jtframe_cen48.v @@ -0,0 +1,164 @@ +/* This file is part of JTFRAME. + JTFRAME program is free software: you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation, either version 3 of the License, or + (at your option) any later version. + + JTFRAME program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with JTFRAME. If not, see . + + Author: Jose Tejada Gomez. Twitter: @topapate + Version: 1.0 + Date: 6-12-2019 */ + +// Input clock must be 48 MHz +// Generates various clock enable signals + +module jtframe_cen48( + input clk, // 48 MHz + output reg cen12, + output reg cen16, + output reg cen8, + output reg cen6, + output reg cen4, + output reg cen4_12, // cen4 based on cen12 + output reg cen3, + output reg cen3q, // 1/4 advanced with respect to cen3 + output reg cen1p5, + // 180 shifted signals + output reg cen16b, + output reg cen12b, + output reg cen6b, + output reg cen3b, + output reg cen3qb, + output reg cen1p5b +); + +reg [4:0] cencnt=5'd0; +reg [2:0] cencnt6=3'd0; +reg cencnt12=1'd0; +reg [2:0] cencnt4_12=3'd1; + +always @(posedge clk) begin + cencnt <= cencnt+5'd1; + cencnt6 <= cencnt6==3'd5 ? 3'd0 : (cencnt6+3'd1); + cencnt12<= cencnt12 ^^ (cencnt6==3'd5); +end + +always @(posedge clk) begin + cen12 <= cencnt[1:0] == 2'd0; + cen12b <= cencnt[1:0] == 2'd2; + if(cencnt[1:0]==2'b0) cencnt4_12 <= { cencnt4_12[1:0], cencnt4_12[2]}; + cen4_12 <= cencnt[1:0]==2'd0 && cencnt4_12[2]; + cen16 <= cencnt6 == 3'd0 || cencnt6 == 3'd3; + cen16b <= cencnt6 == 3'd2 || cencnt6 == 3'd5; + cen8 <= cencnt6 == 3'd0; + cen4 <= cencnt6 == 3'd0 && cencnt12; + cen6 <= cencnt[2:0] == 3'd0; + cen6b <= cencnt[2:0] == 3'd4; + cen3 <= cencnt[3:0] == 4'd0; + cen3b <= cencnt[3:0] == 4'h8; + cen3q <= cencnt[3:0] == 4'b1100; + cen3qb <= cencnt[3:0] == 4'b0100; + cen1p5 <= cencnt[4:0] == 5'd0; + cen1p5b<= cencnt[4:0] == 5'h10; +end +endmodule + +//////////////////////////////////////////////////////////////////// +// Generates a 3.57 MHz clock enable signal for a 48MHz/24MHz clock + +module jtframe_cen3p57( + input clk, // 48 MHz + output cen_3p57, + output cen_1p78 +); + parameter CLK24=0; + + localparam [15:0] STEP = +`ifdef JTFRAME_PLL6144 + 16'd1048; +`elsif JTFRAME_PLL6293 + 16'd35; +`elsif JTFRAME_PLL6671 + 16'd105; +`else + 16'd3758; // 6MHz PLL +`endif + + localparam [15:0] LIM = +`ifdef JTFRAME_PLL6144 + 16'd14391; +`elsif JTFRAME_PLL6293 + 16'd492; +`elsif JTFRAME_PLL6671 + 16'd1566; +`else + 16'd50393; +`endif + + jtframe_frac_cen #(.W(2),.WC(16)) u_frac( + .clk ( clk ), + .n ( STEP<= 7'd124 ) begin + cencnt <= 7'd0; + cen_p384 <= 1'b1; + end +end +endmodule + +//////////////////////////////////////////////////////////////////// +// 10MHz clock enable +module jtframe_cen10( + input clk, // 48MHz only + output reg cen10, + // 180 shifted signals + output reg cen10b +); + +reg [2:0] cencnt=3'd0; +reg [2:0] muxcnt=3'd0; +reg [2:0] next=3'd4, nextb=3'd2; + +always @(*) begin + next = muxcnt[2] ? 3'd3 : 3'd4; + nextb= muxcnt[2] ? 3'd1 : 3'd2; +end + +always @(posedge clk) begin + cencnt <= cencnt+3'd1; + cen10 <= cencnt == next; + cen10b <= cencnt == nextb; + if( cencnt==next ) begin + cencnt <= 3'd0; + muxcnt <= muxcnt[2] ? 3'd1 : muxcnt + 3'b1; + end +end +endmodule + diff --git a/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/clocking/jtframe_cen96.v b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/clocking/jtframe_cen96.v new file mode 100644 index 0000000000000000000000000000000000000000..9fc209e848b7fdbef5aea5e05b42ba0a803ed182 --- /dev/null +++ b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/clocking/jtframe_cen96.v @@ -0,0 +1,46 @@ +/* This file is part of JTFRAME. + JTFRAME program is free software: you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation, either version 3 of the License, or + (at your option) any later version. + + JTFRAME program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with JTFRAME. If not, see . + + Author: Jose Tejada Gomez. Twitter: @topapate + Version: 1.0 + Date: 6-12-2019 */ + +// Input clock must be 96 MHz +// Generates various clock enable signals + +module jtframe_cen96( + input clk, // 96 MHz + output reg cen16, + output reg cen8, + output reg cen12, + output reg cen6, + output reg cen6b +); + +reg [3:0] cencnt12 = 4'd0; +reg [3:0] cencnt16 = 4'd0; + +always @(posedge clk) begin + cencnt12 <= cencnt12==4'd11 ? 4'd0 : cencnt12+4'd1; + cencnt16 <= cencnt16 + 1'd1; +end + +always @(posedge clk) begin + cen16 <= cencnt12 == 4'd0 || cencnt12 == 4'd6; + cen8 <= cencnt12 == 4'd0; + cen12 <= cencnt16 == 4'd0 || cencnt16 == 4'd8; + cen6 <= cencnt16 == 4'd0; + cen6b <= cencnt16 == 4'd8; +end +endmodule diff --git a/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/clocking/jtframe_cencross_strobe.v b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/clocking/jtframe_cencross_strobe.v new file mode 100644 index 0000000000000000000000000000000000000000..b34fd89f8f01c391e4130552752ed0e07f3f5b68 --- /dev/null +++ b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/clocking/jtframe_cencross_strobe.v @@ -0,0 +1,53 @@ +/* This file is part of JTFRAME. + JTFRAME program is free software: you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation, either version 3 of the License, or + (at your option) any later version. + + JTFRAME program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with JTFRAME. If not, see . + + Author: Jose Tejada Gomez. Twitter: @topapate + Version: 1.0 + Date: 31-10-2019 */ + +// Converts an input strobe (stin) defined in some clock gating domain +// to a strobe in the specified cen input domain +// both clock-enable signals belong to the same clock domain + +module jtframe_cencross_strobe( + input rst, + (* direct_enable *) input cen, + input clk, + input stin, + output reg stout +); + +reg last, st_latch; +wire st_edge = stin && !last; + +always @(posedge clk, posedge rst) begin + if(rst) begin + last <= 1'b0; + st_latch <= 1'b0; + end else begin + last <= stin; + if( st_edge ) st_latch <= 1'b1; + if( stout ) st_latch <= 1'b0; + end +end + +always @(posedge clk, posedge rst) begin + if(rst) begin + stout <= 1'b0; + end else if(cen) begin + stout <= st_latch | st_edge; + end +end + +endmodule \ No newline at end of file diff --git a/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/clocking/jtframe_cendiv.v b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/clocking/jtframe_cendiv.v new file mode 100644 index 0000000000000000000000000000000000000000..34677ce86bc4faa4849541c252f70dc482f35413 --- /dev/null +++ b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/clocking/jtframe_cendiv.v @@ -0,0 +1,43 @@ +/* This file is part of JTFRAME. + JTFRAME program is free software: you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation, either version 3 of the License, or + (at your option) any later version. + + JTFRAME program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with JTFRAME. If not, see . + + Author: Jose Tejada Gomez. Twitter: @topapate + Version: 1.0 + Date: 15-4-2021 */ + +// Divides a clock enable signal frequency by an integer + +module jtframe_cendiv #( parameter + MDIV = 2 +)( + input clk, + input cen_in, + output reg cen_div, // Divided but not alligned with the original + output cen_da // Divided and alligned +); + +localparam CW = $clog2(MDIV); + +reg [CW-1:0] cnt=0; +reg z; + +assign cen_da = cen_in & z; + +always @(posedge clk) begin + if( cen_in ) cnt <= cnt==(MDIV[CW-1:0]-1) ? {CW{1'b0}} : cnt+1'd1; + z <= cnt==0; + cen_div <= cen_da; +end + +endmodule \ No newline at end of file diff --git a/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/clocking/jtframe_crossclk_cen.v b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/clocking/jtframe_crossclk_cen.v new file mode 100644 index 0000000000000000000000000000000000000000..2a358b96dbdd11b0d218374628b62eb8701378c9 --- /dev/null +++ b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/clocking/jtframe_crossclk_cen.v @@ -0,0 +1,49 @@ +/* This file is part of JTFRAME. + JTFRAME program is free software: you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation, either version 3 of the License, or + (at your option) any later version. + + JTFRAME program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with JTFRAME. If not, see . + + Author: Jose Tejada Gomez. Twitter: @topapate + Version: 1.0 + Date: 14-11-2021 */ + +// Converts a clock enable (cen) signal in the fast domain +// to a cen in the slow domain +// The effective cen frequency cannot be greater than 0.5*clk_out + +module jtframe_crossclk_cen( + input clk_in, // fast clock + input cen_in, + input clk_out, // slow clock + output reg cen_out +); + +reg flag; + +initial begin + flag = 0; + cen_out = 0; +end + +always @(posedge clk_in) begin + if( cen_in ) flag <= 1; + if( cen_out ) flag <= 0; +end + +reg flag_l; + +always @(posedge clk_out) begin + flag_l <= flag; + cen_out <= flag && !flag_l; +end + +endmodule \ No newline at end of file diff --git a/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/clocking/jtframe_crossclk_strobe.v b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/clocking/jtframe_crossclk_strobe.v new file mode 100644 index 0000000000000000000000000000000000000000..4d9b1a249f49aae4c9a6c1b2d542ab2f70c8b09c --- /dev/null +++ b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/clocking/jtframe_crossclk_strobe.v @@ -0,0 +1,69 @@ +/* This file is part of JTFRAME. + JTFRAME program is free software: you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation, either version 3 of the License, or + (at your option) any later version. + + JTFRAME program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with JTFRAME. If not, see . + + Author: Jose Tejada Gomez. Twitter: @topapate + Version: 1.0 + Date: 12-8-2022 */ + +// Converts an active-high strobe in one clock domain to +// a strobe in a different clock domain +// +// There is a max frequency for the strobe transfer, depending +// on the ratio of the two clocks and the synchronizer stages +// +// An optional DLY parameter will shift the output strobe a +// number of clock cycles + +module jtframe_crossclk_strobe( + input clk_in, + input clk_out, + input stin, + output stout +); + +parameter DLY=0; + +reg [1:0] sclr=0; +reg [2:0] sset=0; +reg set=0, pre_out=0; +wire clr; + +assign clr = sset[1]; + +always @(posedge clk_in) begin + sclr <= { sclr[0], clr }; + if( stin ) set <= 1; + if( sclr[1] ) set <= 0; +end + +always @(posedge clk_out) begin + sset <= { sset[1:0], set }; + pre_out <= sset[2:1]==2'b01; +end + +generate + if (DLY==0) begin + assign stout = pre_out; + end else begin + reg [DLY-1:0] dly; + assign stout = dly[DLY-1]; + + always @(posedge clk_out) begin + dly <= dly<<1; + dly[0] <= pre_out; + end + end +endgenerate + +endmodule \ No newline at end of file diff --git a/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/clocking/jtframe_frac_cen.v b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/clocking/jtframe_frac_cen.v new file mode 100644 index 0000000000000000000000000000000000000000..de1ed28c6aeadad573fa9814e21bb6234314acac --- /dev/null +++ b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/clocking/jtframe_frac_cen.v @@ -0,0 +1,88 @@ +/* This file is part of JTFRAME. + JTFRAME program is free software: you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation, either version 3 of the License, or + (at your option) any later version. + + JTFRAME program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with JTFRAME. If not, see . + + Author: Jose Tejada Gomez. Twitter: @topapate + Version: 1.0 + Date: 6-12-2019 */ + +/////////////////////////////////////////////////////////////////////////// +// Fractional clock enable signal +// W refers to the number of divided down cen signals available +// each one is divided by 2 + +/* verilator tracing_off */ + +module jtframe_frac_cen #(parameter W=2,WC=10)( + input clk, + input [WC-1:0] n, // numerator + input [WC-1:0] m, // denominator + output reg [W-1:0] cen, + output reg [W-1:0] cenb // 180 shifted +); + +wire [WC:0] step={1'b0,n}, + lim ={1'b0,m}, + absmax = lim+step; + +reg [WC:0] cencnt=0, + next, next2; + +always @(*) begin + next = cencnt+step; + next2 = next-lim; +end + +reg half = 0; +wire over = next>=lim; +wire halfway = next >= (lim>>1) && !half; + +reg [W-1:0] edgecnt = 0; +wire [W-1:0] next_edgecnt = edgecnt + 1'd1; +wire [W-1:0] toggle = next_edgecnt & ~edgecnt; + +reg [W-1:0] edgecnt_b = 0; +wire [W-1:0] next_edgecnt_b = edgecnt_b + 1'd1; +wire [W-1:0] toggle_b = next_edgecnt_b & ~edgecnt_b; + +`ifdef SIMULATION +initial begin + if( n>(m>>1) ) $display("WARNING: %m will generate cen signals high for 2 cycles in a row"); +end +`endif + +always @(posedge clk) begin + cen <= 0; + cenb <= 0; + + if( cencnt >= absmax ) begin + // something went wrong: restart + cencnt <= 0; + end else + if( halfway ) begin + half <= 1'b1; + edgecnt_b <= next_edgecnt_b; + cenb <= { toggle_b[W-2:0], 1'b1 }; + end + if( over ) begin + cencnt <= next2; + half <= 1'b0; + edgecnt <= next_edgecnt; + cen <= { toggle[W-2:0], 1'b1 }; + end else begin + cencnt <= next; + end +end + + +endmodule \ No newline at end of file diff --git a/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/clocking/jtframe_freqinfo.v b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/clocking/jtframe_freqinfo.v new file mode 100644 index 0000000000000000000000000000000000000000..ae3f8b7b6b44319b0607a668cdb6c31683fdc0aa --- /dev/null +++ b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/clocking/jtframe_freqinfo.v @@ -0,0 +1,86 @@ +/* This file is part of JTFRAME. + JTFRAME program is free software: you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation, either version 3 of the License, or + (at your option) any later version. + + JTFRAME program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with JTFRAME. If not, see . + + Author: Jose Tejada Gomez. Twitter: @topapate + Version: 1.0 + Date: 16-4-2022 */ + +module jtframe_freqinfo #(parameter + KHZ = 1, // set to 1 to output kHz, set to 0 to output Hz + MFREQ = `JTFRAME_MCLK/1000, // clk input frequency in kHz + DIGITS = 4 // count up to 9999 kHz, change to 5 for 10MHz and above +)( + input rst, + input clk, + input pulse, + output reg [DIGITS*4-1:0] fave, // average cpu_cen frequency in kHz (BCD encoding) + output reg [DIGITS*4-1:0] fworst // worst case registered (BCD) +); + +localparam BW=$clog2(MFREQ-1); + +wire cnt_event; +wire cen, ms; +reg [BW-1:0] freq_cnt; +wire [DIGITS*4-1:0] fout_cnt; +reg pulse_l; + +assign ms = freq_cnt == MFREQ[BW-1:0]-1'd1; + +generate + if( KHZ==1 ) + assign cen = 1; + else begin + // counts a full second + // This is useful when the input signal is below 1kHz + reg [9:0] div; + assign cen = div==999; + always @(posedge clk, posedge rst) begin + if( rst ) begin + div <= 0; + end else begin + div <= cen ? 10'd0 : div+10'd1; + end + end + end +endgenerate + +// Frequency reporting +assign cnt_event = pulse & ~pulse_l; + +always @(posedge clk, posedge rst) begin + if( rst ) begin + freq_cnt <= 0; + fworst <= {DIGITS*4{1'b1}}; + fave <= 0; + end else begin + pulse_l <= pulse; + if( cen ) freq_cnt <= freq_cnt + 1'd1; + if( ms ) begin // updated every 1ms + freq_cnt <= 0; + fave <= fout_cnt; + if( fworst > fout_cnt ) fworst <= fout_cnt; + end + end +end + +jtframe_bcd_cnt #(.DIGITS(DIGITS),.WRAP(0)) u_bcd( + .rst ( rst ), + .clk ( clk ), + .clr ( ms ), + .up ( cnt_event ), + .cnt ( fout_cnt ) +); + +endmodule \ No newline at end of file diff --git a/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/clocking/jtframe_gated_cen.v b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/clocking/jtframe_gated_cen.v new file mode 100644 index 0000000000000000000000000000000000000000..77c69198769b3f4291979819d50da70537ae20d9 --- /dev/null +++ b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/clocking/jtframe_gated_cen.v @@ -0,0 +1,100 @@ +/* This file is part of JTFRAME. + JTFRAME program is free software: you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation, either version 3 of the License, or + (at your option) any later version. + + JTFRAME program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with JTFRAME. If not, see . + + Author: Jose Tejada Gomez. Twitter: @topapate + Version: 1.0 + Date: 6-12-2019 */ + +/////////////////////////////////////////////////////////////////////////// +// Fractional clock enable signal +// W refers to the number of divided down cen signals available +// each one is divided by 2 +// generation is halted while busy input is high, and lost +// cycles are recovered once busy goes low + +/* verilator tracing_on */ + +module jtframe_gated_cen #( parameter + W = 2, + MFREQ = `ifdef JTFRAME_MCLK `JTFRAME_MCLK/1000 `else 48000 `endif, + NUM = 1, + DEN = 8, + CW = $clog2(DEN+NUM*2)+4 +)( + input rst, + input clk, + input busy, + output reg [W-1:0] cen, + + output [ 15:0] fave, fworst // average cpu_cen frequency in kHz +); + +localparam NUM2 = NUM<<1, + DIGITS = (MFREQ*NUM)/DEN>9999 ? 5 : 4; + +wire over; +wire [ CW:0] cencnt_nx, sum; +reg [CW-1:0] cencnt=0; +reg [ W-1:0] toggle=0, toggle_l=0; +wire [DIGITS*4-1:0] full_ave, full_worst; +wire cnt_en = !busy || rst; +integer i; + +assign over = cencnt > DEN[CW-1:0]-NUM2[CW-1:0]; +assign cencnt_nx = {1'b0,cencnt}+NUM2[CW:0] - ((over && cnt_en) ? DEN[CW:0] : {CW+1{1'b0}}); +assign fave = full_ave[ DIGITS*4-1-:16]; +assign fworst = full_worst[DIGITS*4-1-:16]; + +always @(posedge clk) begin + cencnt <= cencnt_nx[CW] ? {CW{1'b1}} : cencnt_nx[CW-1:0]; + if( over && cnt_en ) begin + toggle <= toggle + 1'd1; + toggle_l <= toggle; + cen <= ~toggle & toggle_l; + end else begin + cen <= 0; + end +end + +`ifdef SIMULATION +reg bad=0, rst2=1, busy2=0; +reg [2:0] badcnt=0; + +always @(posedge clk) begin + if( cen[0] ) rst2<=rst; + busy2 <= busy; + if( !rst2 && busy2 && cen!=0 ) begin + $display("%m cen active while busy was high. Is busy dependent on a different clock domain?"); + bad<=1; + end + if(bad) begin + badcnt <= badcnt+1; + if( &badcnt ) $finish; + end + if( rst ) begin + badcnt <= 0; + bad <= 0; + end +end +`endif + +jtframe_freqinfo #(.MFREQ( MFREQ ),.DIGITS(DIGITS)) u_info( + .rst ( rst ), + .clk ( clk ), + .pulse ( cen[0] ), + .fave ( full_ave ), // average cpu_cen frequency in kHz + .fworst ( full_worst) +); + +endmodule \ No newline at end of file diff --git a/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/clocking/jtframe_int_cen.v b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/clocking/jtframe_int_cen.v new file mode 100644 index 0000000000000000000000000000000000000000..d0a44cb0dde38076b48457863296987a6fd3688f --- /dev/null +++ b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/clocking/jtframe_int_cen.v @@ -0,0 +1,31 @@ +/* This file is part of JTFRAME. + JTFRAME program is free software: you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation, either version 3 of the License, or + (at your option) any later version. + + JTFRAME program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with JTFRAME. If not, see . + + Author: Rafael Eduardo Paiva Feener. Copyright: Miki Saito + Version: 1.0 + Date: 21-02-2025 */ + +module jtframe_int_cen#(parameter CKW=3)( + input clk, + output reg cen +); + +reg [CKW-1:0] cnt=0; + +always @(posedge clk) begin + cnt <= cnt + 1'b1; + cen <= &cnt; +end + +endmodule \ No newline at end of file diff --git a/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/clocking/jtframe_pxlcen.v b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/clocking/jtframe_pxlcen.v new file mode 100644 index 0000000000000000000000000000000000000000..fb3ac8d0e9cc50ba569da5dd622dfdfcbebe36fb --- /dev/null +++ b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/clocking/jtframe_pxlcen.v @@ -0,0 +1,48 @@ +/* This file is part of JTFRAME. + JTFRAME program is free software: you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation, either version 3 of the License, or + (at your option) any later version. + + JTFRAME program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with JTFRAME. If not, see . + + Author: Jose Tejada Gomez. Twitter: @topapate + Version: 1.0 + Date: 6-12-2022 */ + +`ifdef JTFRAME_PXLCLK +module jtframe_pxlcen( + input clk, + output pxl_cen, + output pxl2_cen +); + + localparam PXLCLK = `JTFRAME_PXLCLK, + CLK = `ifdef JTFRAME_SDRAM96 96 `else 48 `endif, + M = (PXLCLK==12 ? 2 : PXLCLK==8 ? 3 : 4) << (CLK==96 ? 1:0); + + initial begin + if( PXLCLK!=8 && PXLCLK!=6 ) begin + $display("JTFRAME_PXLCLK is set to %d. But that value isn't supported yet.",PXLCLK); + $finish; + end else begin + $display("jtframe_pxlcen: using %0d as clock divider", M[3:0]); + end + end + + jtframe_frac_cen #(.WC(4),.W(2)) u_cen( + .clk ( clk ), // 48 or 96 MHz + .n ( 4'd1 ), + .m (M[3:0]), + .cen ( { pxl_cen, pxl2_cen } ), + .cenb ( ) + ); + +endmodule +`endif diff --git a/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/clocking/jtframe_rst_sync.v b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/clocking/jtframe_rst_sync.v new file mode 100644 index 0000000000000000000000000000000000000000..ddd3c645b8c6e47babd47f192aad8ea37548a4ff --- /dev/null +++ b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/clocking/jtframe_rst_sync.v @@ -0,0 +1,36 @@ +/* This file is part of JTFRAME. + JTFRAME program is free software: you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation, either version 3 of the License, or + (at your option) any later version. + + JTFRAME program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with JTFRAME. If not, see . + + Author: Jose Tejada Gomez. Twitter: @topapate + Version: 1.0 + Date: 6-9-2021 */ + +// Reference: +// https://www.intel.com/content/www/us/en/programmable/quartushelp/15.1/index.htm#verify/da/comp_file_rules_reset_synch.htm + +module jtframe_rst_sync( + input rst, + input clk, + output rst_sync +); + +reg [1:0] s; + +assign rst_sync = s[1]; + +always @(posedge clk) begin + s <= { s[0], rst }; +end + +endmodule \ No newline at end of file diff --git a/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/clocking/jtframe_rtc.v b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/clocking/jtframe_rtc.v new file mode 100644 index 0000000000000000000000000000000000000000..4b7e5d63158c279ac037b86ffa0f793e2d4ee913 --- /dev/null +++ b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/clocking/jtframe_rtc.v @@ -0,0 +1,84 @@ +/* This file is part of JTFRAME. + JTFRAME program is free software: you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation, either version 3 of the License, or + (at your option) any later version. + + JTFRAME program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with JTFRAME. If not, see . + + Author: Jose Tejada Gomez. Twitter: @topapate + Version: 1.0 + Date: 22-6-2023 */ + +module jtframe_rtc( + input rst, + input clk, + input cen, // 1024 Hz clock enable + input [7:0] din, + input [2:0] we, // overwrite hour, min, sec + output reg [7:0] sec, min, hour, // BCD + // IOCTL dump + input [1:0] ioctl_addr, + input [7:0] ioctl_dout, + output reg [7:0] ioctl_din, + input ioctl_wr +); + +reg [9:0] cnt; + +always @(posedge clk, posedge rst) begin + if( rst ) begin + { hour, min, sec } <= `ifndef JTFRAME_SIM_RTC 0 `else `JTFRAME_SIM_RTC `endif; + cnt <= 0; + end else begin + if( cen ) begin + cnt <= cnt+10'd1; + if( cnt==0 ) begin + sec[3:0] <= sec[3:0]+4'd1; + if( sec[3:0]==9 ) begin // 9 seconds + sec[3:0] <= 0; + sec[7:4] <= sec[7:4]+4'd1; + if( sec[7:4]==5 ) begin // 59 seconds + sec[7:4] <= 0; + min[3:0] <= min[3:0]+4'd1; + if( min[3:0]==9 ) begin // 9 minutes + min[3:0] <= 0; + min[7:4] <= min[7:4]+4'd1; + if( min[7:4]==5 ) begin // 59 minutes + min[7:4] <= 0; + hour[3:0] <= hour[3:0]+4'd1; + if( hour[3:0]==9 || hour==8'h23 ) begin // 9 or 23 hours + hour[3:0] <= 0; + hour[7:4] <= hour==8'h23 ? 4'd0 : hour[7:4]+4'd1; + end + end + end + end + end + end + end + if( we[0] ) sec <= din; + if( we[1] ) min <= din; + if( we[2] ) hour <= din; + if( ioctl_wr ) case(ioctl_addr) + 0: sec <= ioctl_dout; + 1: min <= ioctl_dout; + 2: hour <= ioctl_dout; + default:; + endcase + case( ioctl_addr ) + 0: ioctl_din <= sec; + 1: ioctl_din <= min; + 2: ioctl_din <= hour; + 3: ioctl_din <= 0; + endcase + end +end + +endmodule \ No newline at end of file diff --git a/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/clocking/jtframe_sync.v b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/clocking/jtframe_sync.v new file mode 100644 index 0000000000000000000000000000000000000000..b02f5d80874fcd4d1dd994839fcca22bd89a31d5 --- /dev/null +++ b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/clocking/jtframe_sync.v @@ -0,0 +1,91 @@ +/* This file is part of JTFRAME. + JTFRAME program is free software: you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation, either version 3 of the License, or + (at your option) any later version. + + JTFRAME program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with JTFRAME. If not, see . + + Author: Jose Tejada Gomez. Twitter: @topapate + Version: 1.0 + Date: 6-9-2021 */ + +// Enable the LATCHIN parameter if the raw input comes +// from combinational logic + +module jtframe_sync #( parameter + W=1, // input signal bit width + LATCHIN=0, // latch the input signal with the input clock + SW =2, // Number of synchronizing stages + AND=0 // Adds one more bit to the shift register and + // the output only goes high if the last two bits + // were high. +)( + input clk_in, + input clk_out, + input [W-1:0] raw, + output [W-1:0] sync +); + +localparam EW = SW + AND[0]; + +`ifdef SIMULATION +initial begin + if( SW<2 ) begin $display("%m SW cannot be less than 2"); $finish; end +end +`endif + +reg [W-1:0] latched; +wire [W-1:0] eff; + +always @(posedge clk_in) latched <= raw; +assign eff = LATCHIN ? latched : raw; + +generate + genvar i; + for( i=0; i + Copyright (C) + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with this library; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +Also add information on how to contact you by electronic and paper mail. + +You should also get your employer (if you work as a programmer) or your +school, if any, to sign a "copyright disclaimer" for the library, if +necessary. Here is a sample; alter the names: + + Yoyodyne, Inc., hereby disclaims all copyright interest in the + library `Frob' (a library for tweaking knobs) written by James Random Hacker. + + , 1 April 1990 + Ty Coon, President of Vice + +That's all there is to it! + + + + diff --git a/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/8051/addsub_core_.vhd b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/8051/addsub_core_.vhd new file mode 100644 index 0000000000000000000000000000000000000000..dbf682130a89c56f107724b6c4d7dd18f8aa3cec --- /dev/null +++ b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/8051/addsub_core_.vhd @@ -0,0 +1,90 @@ +------------------------------------------------------------------------------- +-- -- +-- X X XXXXXX XXXXXX XXXXXX XXXXXX X -- +-- XX XX X X X X X X X XX -- +-- X X X X X X X X X X X X -- +-- X X X X X X X X X X X X -- +-- X X X X XXXXXX X X XXXXXX X -- +-- X X X X X X X X X -- +-- X X X X X X X X X -- +-- X X X X X X X X X X -- +-- X X XXXXXX XXXXXX XXXXXX XXXXXX X -- +-- -- +-- -- +-- O R E G A N O S Y S T E M S -- +-- -- +-- Design & Consulting -- +-- -- +------------------------------------------------------------------------------- +-- -- +-- Web: http://www.oregano.at/ -- +-- -- +-- Contact: mc8051@oregano.at -- +-- -- +------------------------------------------------------------------------------- +-- -- +-- MC8051 - VHDL 8051 Microcontroller IP Core -- +-- Copyright (C) 2001 OREGANO SYSTEMS -- +-- -- +-- This library is free software; you can redistribute it and/or -- +-- modify it under the terms of the GNU Lesser General Public -- +-- License as published by the Free Software Foundation; either -- +-- version 2.1 of the License, or (at your option) any later version. -- +-- -- +-- This library is distributed in the hope that it will be useful, -- +-- but WITHOUT ANY WARRANTY; without even the implied warranty of -- +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -- +-- Lesser General Public License for more details. -- +-- -- +-- Full details of the license can be found in the file LGPL.TXT. -- +-- -- +-- You should have received a copy of the GNU Lesser General Public -- +-- License along with this library; if not, write to the Free Software -- +-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -- +-- -- +------------------------------------------------------------------------------- +-- +-- +-- Author: Roland Hller +-- +-- Filename: addsub_core_.vhd +-- +-- Date of Creation: Mon Aug 9 12:14:48 1999 +-- +-- Version: $Revision: 1.5 $ +-- +-- Date of Latest Version: $Date: 2002-01-07 12:17:44 $ +-- +-- +-- Description: Adder/Subtractor with carry/borrow, arbitrary data +-- width, overflow, and nibble carry for decimal +-- adjustment. +-- +-- +-- +-- +------------------------------------------------------------------------------- +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.std_logic_arith.all; + +library work; +use work.mc8051_p.all; + +-----------------------------ENTITY DECLARATION-------------------------------- + +entity addsub_core is + + generic (DWIDTH : integer := 16); -- Data width of the ALU + + port (opa_i : in std_logic_vector(DWIDTH-1 downto 0); + opb_i : in std_logic_vector(DWIDTH-1 downto 0); + addsub_i : in std_logic; + cy_i : in std_logic; + + cy_o : out std_logic_vector((DWIDTH-1)/4 downto 0); + ov_o : out std_logic; + rslt_o : out std_logic_vector(DWIDTH-1 downto 0)); + +end addsub_core; + diff --git a/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/8051/addsub_core_struc.vhd b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/8051/addsub_core_struc.vhd new file mode 100644 index 0000000000000000000000000000000000000000..0e5cc57f962d52044683278f9b76477d6fae8197 --- /dev/null +++ b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/8051/addsub_core_struc.vhd @@ -0,0 +1,116 @@ +------------------------------------------------------------------------------- +-- -- +-- X X XXXXXX XXXXXX XXXXXX XXXXXX X -- +-- XX XX X X X X X X X XX -- +-- X X X X X X X X X X X X -- +-- X X X X X X X X X X X X -- +-- X X X X XXXXXX X X XXXXXX X -- +-- X X X X X X X X X -- +-- X X X X X X X X X -- +-- X X X X X X X X X X -- +-- X X XXXXXX XXXXXX XXXXXX XXXXXX X -- +-- -- +-- -- +-- O R E G A N O S Y S T E M S -- +-- -- +-- Design & Consulting -- +-- -- +------------------------------------------------------------------------------- +-- -- +-- Web: http://www.oregano.at/ -- +-- -- +-- Contact: mc8051@oregano.at -- +-- -- +------------------------------------------------------------------------------- +-- -- +-- MC8051 - VHDL 8051 Microcontroller IP Core -- +-- Copyright (C) 2001 OREGANO SYSTEMS -- +-- -- +-- This library is free software; you can redistribute it and/or -- +-- modify it under the terms of the GNU Lesser General Public -- +-- License as published by the Free Software Foundation; either -- +-- version 2.1 of the License, or (at your option) any later version. -- +-- -- +-- This library is distributed in the hope that it will be useful, -- +-- but WITHOUT ANY WARRANTY; without even the implied warranty of -- +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -- +-- Lesser General Public License for more details. -- +-- -- +-- Full details of the license can be found in the file LGPL.TXT. -- +-- -- +-- You should have received a copy of the GNU Lesser General Public -- +-- License along with this library; if not, write to the Free Software -- +-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -- +-- -- +------------------------------------------------------------------------------- +-- +-- +-- Author: Roland Hller +-- +-- Filename: addsub_core_struc.vhd +-- +-- Date of Creation: Mon Aug 9 12:14:48 1999 +-- +-- Version: $Revision: 1.4 $ +-- +-- Date of Latest Version: $Date: 2002-01-07 12:17:44 $ +-- +-- +-- Description: Adder/Subtractor with carry/borrow, arbitrary data +-- width, overflow, and nibble carry for decimal +-- adjustment. +-- +-- +-- +-- +------------------------------------------------------------------------------- +architecture struc of addsub_core is + + type t_cy is array (1 to (DWIDTH/4)+1) of std_logic_vector(0 downto 0); + + signal s_cy : t_cy; + +begin -- architecture structural + + gen_smorequ_four : if (DWIDTH > 0 and DWIDTH <= 4) generate + addsub_ovcy_1 : addsub_ovcy + generic map (DWIDTH => DWIDTH) + port map (opa_i => opa_i, + opb_i => opb_i, + addsub_i => addsub_i, + cy_i => cy_i, + cy_o => cy_o(0), + ov_o => ov_o, + rslt_o => rslt_o); + end generate gen_smorequ_four; + + s_cy(1)(0) <= cy_i; + + gen_greater_four : if (DWIDTH > 4) generate + gen_addsub: for i in 1 to DWIDTH generate + gen_nibble_addsub: if (i mod 4 = 0) and i <= ((DWIDTH-1)/4)*4 generate + i_addsub_cy: addsub_cy + generic map (DWIDTH => 4) + port map (opa_i => opa_i(i-1 downto i-4), + opb_i => opb_i(i-1 downto i-4), + addsub_i => addsub_i, + cy_i => s_cy(i/4)(0), + cy_o => s_cy((i+4)/4)(0), + rslt_o => rslt_o(i-1 downto i-4)); + cy_o(i/4-1) <= s_cy((i+4)/4)(0); + end generate gen_nibble_addsub; + gen_last_addsub: if (i = ((DWIDTH-1)/4)*4+1) generate + i_addsub_ovcy: addsub_ovcy + generic map (DWIDTH => DWIDTH-((DWIDTH-1)/4)*4) + port map (opa_i => opa_i(DWIDTH-1 downto i-1), + opb_i => opb_i(DWIDTH-1 downto i-1), + addsub_i => addsub_i, + cy_i => s_cy((DWIDTH-1)/4+1)(0), + cy_o => cy_o((DWIDTH-1)/4), + ov_o => ov_o, + rslt_o => rslt_o(DWIDTH-1 downto i-1)); + end generate gen_last_addsub; + end generate gen_addsub; + end generate gen_greater_four; + +end struc; diff --git a/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/8051/addsub_core_struc_cfg.vhd b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/8051/addsub_core_struc_cfg.vhd new file mode 100644 index 0000000000000000000000000000000000000000..2c26e73625261efdcedbc949e17ec328cf8c61f2 --- /dev/null +++ b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/8051/addsub_core_struc_cfg.vhd @@ -0,0 +1,89 @@ +------------------------------------------------------------------------------- +-- -- +-- X X XXXXXX XXXXXX XXXXXX XXXXXX X -- +-- XX XX X X X X X X X XX -- +-- X X X X X X X X X X X X -- +-- X X X X X X X X X X X X -- +-- X X X X XXXXXX X X XXXXXX X -- +-- X X X X X X X X X -- +-- X X X X X X X X X -- +-- X X X X X X X X X X -- +-- X X XXXXXX XXXXXX XXXXXX XXXXXX X -- +-- -- +-- -- +-- O R E G A N O S Y S T E M S -- +-- -- +-- Design & Consulting -- +-- -- +------------------------------------------------------------------------------- +-- -- +-- Web: http://www.oregano.at/ -- +-- -- +-- Contact: mc8051@oregano.at -- +-- -- +------------------------------------------------------------------------------- +-- -- +-- MC8051 - VHDL 8051 Microcontroller IP Core -- +-- Copyright (C) 2001 OREGANO SYSTEMS -- +-- -- +-- This library is free software; you can redistribute it and/or -- +-- modify it under the terms of the GNU Lesser General Public -- +-- License as published by the Free Software Foundation; either -- +-- version 2.1 of the License, or (at your option) any later version. -- +-- -- +-- This library is distributed in the hope that it will be useful, -- +-- but WITHOUT ANY WARRANTY; without even the implied warranty of -- +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -- +-- Lesser General Public License for more details. -- +-- -- +-- Full details of the license can be found in the file LGPL.TXT. -- +-- -- +-- You should have received a copy of the GNU Lesser General Public -- +-- License along with this library; if not, write to the Free Software -- +-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -- +-- -- +------------------------------------------------------------------------------- +-- +-- +-- Author: Roland Hller +-- +-- Filename: addsub_core_struc_cfg.vhd +-- +-- Date of Creation: Mon Aug 9 12:14:48 1999 +-- +-- Version: $Revision: 1.4 $ +-- +-- Date of Latest Version: $Date: 2002-01-07 12:17:44 $ +-- +-- +-- Description: Adder/Subtractor with carry/borrow, arbitrary data +-- width, overflow, and nibble carry for decimal +-- adjustment. +-- +-- +-- +-- +------------------------------------------------------------------------------- +configuration addsub_core_struc_cfg of addsub_core is + for struc + for gen_smorequ_four + for addsub_ovcy_1 : addsub_ovcy + use configuration work.addsub_ovcy_rtl_cfg; + end for; + end for; + for gen_greater_four + for gen_addsub + for gen_nibble_addsub + for all : addsub_cy + use configuration work.addsub_cy_rtl_cfg; + end for; + end for; + for gen_last_addsub + for all : addsub_ovcy + use configuration work.addsub_ovcy_rtl_cfg; + end for; + end for; + end for; + end for; + end for; +end addsub_core_struc_cfg; diff --git a/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/8051/addsub_cy_.vhd b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/8051/addsub_cy_.vhd new file mode 100644 index 0000000000000000000000000000000000000000..507fd45962dec1e40faeca3d07aacc3c7eeba479 --- /dev/null +++ b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/8051/addsub_cy_.vhd @@ -0,0 +1,84 @@ +------------------------------------------------------------------------------- +-- -- +-- X X XXXXXX XXXXXX XXXXXX XXXXXX X -- +-- XX XX X X X X X X X XX -- +-- X X X X X X X X X X X X -- +-- X X X X X X X X X X X X -- +-- X X X X XXXXXX X X XXXXXX X -- +-- X X X X X X X X X -- +-- X X X X X X X X X -- +-- X X X X X X X X X X -- +-- X X XXXXXX XXXXXX XXXXXX XXXXXX X -- +-- -- +-- -- +-- O R E G A N O S Y S T E M S -- +-- -- +-- Design & Consulting -- +-- -- +------------------------------------------------------------------------------- +-- -- +-- Web: http://www.oregano.at/ -- +-- -- +-- Contact: mc8051@oregano.at -- +-- -- +------------------------------------------------------------------------------- +-- -- +-- MC8051 - VHDL 8051 Microcontroller IP Core -- +-- Copyright (C) 2001 OREGANO SYSTEMS -- +-- -- +-- This library is free software; you can redistribute it and/or -- +-- modify it under the terms of the GNU Lesser General Public -- +-- License as published by the Free Software Foundation; either -- +-- version 2.1 of the License, or (at your option) any later version. -- +-- -- +-- This library is distributed in the hope that it will be useful, -- +-- but WITHOUT ANY WARRANTY; without even the implied warranty of -- +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -- +-- Lesser General Public License for more details. -- +-- -- +-- Full details of the license can be found in the file LGPL.TXT. -- +-- -- +-- You should have received a copy of the GNU Lesser General Public -- +-- License along with this library; if not, write to the Free Software -- +-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -- +-- -- +------------------------------------------------------------------------------- +-- +-- +-- Author: Roland Hller +-- +-- Filename: addsub_cy_.vhd +-- +-- Date of Creation: Mon Aug 9 12:14:48 1999 +-- +-- Version: $Revision: 1.4 $ +-- +-- Date of Latest Version: $Date: 2002-01-07 12:17:44 $ +-- +-- +-- Description: Adder/Subtractor with carry/borrow and arbitrary +-- data width. +-- +-- +-- +-- +------------------------------------------------------------------------------- +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.std_logic_arith.all; + +-----------------------------ENTITY DECLARATION-------------------------------- + +entity addsub_cy is + + generic (DWIDTH : integer := 4); + + port (opa_i : in std_logic_vector(DWIDTH-1 downto 0); -- Operand A + opb_i : in std_logic_vector(DWIDTH-1 downto 0); -- Operand B + addsub_i : in std_logic; -- Add or subtract command + cy_i : in std_logic; -- Carry input + cy_o : out std_logic; -- Carry/borrow bit + rslt_o : out std_logic_vector(DWIDTH-1 downto 0)); -- Result + +end addsub_cy; + diff --git a/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/8051/addsub_cy_rtl.vhd b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/8051/addsub_cy_rtl.vhd new file mode 100644 index 0000000000000000000000000000000000000000..dbbf8ea61619a3f409edc32c2a43ae3b974550db --- /dev/null +++ b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/8051/addsub_cy_rtl.vhd @@ -0,0 +1,94 @@ +------------------------------------------------------------------------------- +-- -- +-- X X XXXXXX XXXXXX XXXXXX XXXXXX X -- +-- XX XX X X X X X X X XX -- +-- X X X X X X X X X X X X -- +-- X X X X X X X X X X X X -- +-- X X X X XXXXXX X X XXXXXX X -- +-- X X X X X X X X X -- +-- X X X X X X X X X -- +-- X X X X X X X X X X -- +-- X X XXXXXX XXXXXX XXXXXX XXXXXX X -- +-- -- +-- -- +-- O R E G A N O S Y S T E M S -- +-- -- +-- Design & Consulting -- +-- -- +------------------------------------------------------------------------------- +-- -- +-- Web: http://www.oregano.at/ -- +-- -- +-- Contact: mc8051@oregano.at -- +-- -- +------------------------------------------------------------------------------- +-- -- +-- MC8051 - VHDL 8051 Microcontroller IP Core -- +-- Copyright (C) 2001 OREGANO SYSTEMS -- +-- -- +-- This library is free software; you can redistribute it and/or -- +-- modify it under the terms of the GNU Lesser General Public -- +-- License as published by the Free Software Foundation; either -- +-- version 2.1 of the License, or (at your option) any later version. -- +-- -- +-- This library is distributed in the hope that it will be useful, -- +-- but WITHOUT ANY WARRANTY; without even the implied warranty of -- +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -- +-- Lesser General Public License for more details. -- +-- -- +-- Full details of the license can be found in the file LGPL.TXT. -- +-- -- +-- You should have received a copy of the GNU Lesser General Public -- +-- License along with this library; if not, write to the Free Software -- +-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -- +-- -- +------------------------------------------------------------------------------- +-- +-- +-- Author: Roland Hller +-- +-- Filename: addsub_cy_rtl.vhd +-- +-- Date of Creation: Mon Aug 9 12:14:48 1999 +-- +-- Version: $Revision: 1.4 $ +-- +-- Date of Latest Version: $Date: 2002-01-07 12:17:44 $ +-- +-- +-- Description: Adder/Subtractor with carry/borrow and arbitrary +-- data width. +-- +-- +-- +-- +------------------------------------------------------------------------------- +architecture rtl of addsub_cy is + +begin + + -- purpose: Simple adder/subtractor with carry/borrow + -- type : combinational + -- inputs : opa_i, opb_i, addsub_i + -- outputs: cy_o, rslt_o + p_addsub: process (opa_i, opb_i, addsub_i, cy_i) + variable v_a : unsigned(DWIDTH downto 0); + variable v_b : unsigned(DWIDTH downto 0); + variable v_result : std_logic_vector(DWIDTH+1 downto 0); + begin -- process p_addsub + v_a(DWIDTH downto 1) := unsigned(opa_i); + v_b(DWIDTH downto 1) := unsigned(opb_i); + if addsub_i = '1' then + v_a(0) := '1'; + v_b(0) := cy_i; + v_result := conv_unsigned(v_a,DWIDTH+2) + v_b; + else + v_a(0) := '0'; + v_b(0) := cy_i; + v_result := conv_unsigned(v_a,DWIDTH+2) - v_b; + end if; + cy_o <= v_result(DWIDTH+1); + rslt_o <= v_result(DWIDTH downto 1); + end process p_addsub; + +end rtl; diff --git a/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/8051/addsub_cy_rtl_cfg.vhd b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/8051/addsub_cy_rtl_cfg.vhd new file mode 100644 index 0000000000000000000000000000000000000000..6dd200b6a0ccea20b5f3bae49085121d3237803e --- /dev/null +++ b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/8051/addsub_cy_rtl_cfg.vhd @@ -0,0 +1,72 @@ +------------------------------------------------------------------------------- +-- -- +-- X X XXXXXX XXXXXX XXXXXX XXXXXX X -- +-- XX XX X X X X X X X XX -- +-- X X X X X X X X X X X X -- +-- X X X X X X X X X X X X -- +-- X X X X XXXXXX X X XXXXXX X -- +-- X X X X X X X X X -- +-- X X X X X X X X X -- +-- X X X X X X X X X X -- +-- X X XXXXXX XXXXXX XXXXXX XXXXXX X -- +-- -- +-- -- +-- O R E G A N O S Y S T E M S -- +-- -- +-- Design & Consulting -- +-- -- +------------------------------------------------------------------------------- +-- -- +-- Web: http://www.oregano.at/ -- +-- -- +-- Contact: mc8051@oregano.at -- +-- -- +------------------------------------------------------------------------------- +-- -- +-- MC8051 - VHDL 8051 Microcontroller IP Core -- +-- Copyright (C) 2001 OREGANO SYSTEMS -- +-- -- +-- This library is free software; you can redistribute it and/or -- +-- modify it under the terms of the GNU Lesser General Public -- +-- License as published by the Free Software Foundation; either -- +-- version 2.1 of the License, or (at your option) any later version. -- +-- -- +-- This library is distributed in the hope that it will be useful, -- +-- but WITHOUT ANY WARRANTY; without even the implied warranty of -- +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -- +-- Lesser General Public License for more details. -- +-- -- +-- Full details of the license can be found in the file LGPL.TXT. -- +-- -- +-- You should have received a copy of the GNU Lesser General Public -- +-- License along with this library; if not, write to the Free Software -- +-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -- +-- -- +------------------------------------------------------------------------------- +-- +-- +-- Author: Roland Hller +-- +-- Filename: addsub_cy_rtl_cfg.vhd +-- +-- Date of Creation: Mon Aug 9 12:14:48 1999 +-- +-- Version: $Revision: 1.4 $ +-- +-- Date of Latest Version: $Date: 2002-01-07 12:17:44 $ +-- +-- +-- Description: Adder/Subtractor with carry/borrow and arbitrary +-- data width. +-- +-- +-- +-- +------------------------------------------------------------------------------- +configuration addsub_cy_rtl_cfg of addsub_cy is + + for rtl + + end for; + +end addsub_cy_rtl_cfg; diff --git a/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/8051/addsub_ovcy_.vhd b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/8051/addsub_ovcy_.vhd new file mode 100644 index 0000000000000000000000000000000000000000..8b9d0314aee5bcedb2fc918827b1074c2e9bb94a --- /dev/null +++ b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/8051/addsub_ovcy_.vhd @@ -0,0 +1,85 @@ +------------------------------------------------------------------------------- +-- -- +-- X X XXXXXX XXXXXX XXXXXX XXXXXX X -- +-- XX XX X X X X X X X XX -- +-- X X X X X X X X X X X X -- +-- X X X X X X X X X X X X -- +-- X X X X XXXXXX X X XXXXXX X -- +-- X X X X X X X X X -- +-- X X X X X X X X X -- +-- X X X X X X X X X X -- +-- X X XXXXXX XXXXXX XXXXXX XXXXXX X -- +-- -- +-- -- +-- O R E G A N O S Y S T E M S -- +-- -- +-- Design & Consulting -- +-- -- +------------------------------------------------------------------------------- +-- -- +-- Web: http://www.oregano.at/ -- +-- -- +-- Contact: mc8051@oregano.at -- +-- -- +------------------------------------------------------------------------------- +-- -- +-- MC8051 - VHDL 8051 Microcontroller IP Core -- +-- Copyright (C) 2001 OREGANO SYSTEMS -- +-- -- +-- This library is free software; you can redistribute it and/or -- +-- modify it under the terms of the GNU Lesser General Public -- +-- License as published by the Free Software Foundation; either -- +-- version 2.1 of the License, or (at your option) any later version. -- +-- -- +-- This library is distributed in the hope that it will be useful, -- +-- but WITHOUT ANY WARRANTY; without even the implied warranty of -- +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -- +-- Lesser General Public License for more details. -- +-- -- +-- Full details of the license can be found in the file LGPL.TXT. -- +-- -- +-- You should have received a copy of the GNU Lesser General Public -- +-- License along with this library; if not, write to the Free Software -- +-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -- +-- -- +------------------------------------------------------------------------------- +-- +-- +-- Author: Roland Hller +-- +-- Filename: addsub_ovcy_.vhd +-- +-- Date of Creation: Mon Aug 9 12:14:48 1999 +-- +-- Version: $Revision: 1.4 $ +-- +-- Date of Latest Version: $Date: 2002-01-07 12:17:44 $ +-- +-- +-- Description: Adder/Subtractor with carry/borrow and arbitrary data +-- width and overflow flag. +-- +-- +-- +-- +------------------------------------------------------------------------------- +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.std_logic_arith.all; + +-----------------------------ENTITY DECLARATION-------------------------------- + +entity addsub_ovcy is + + generic (DWIDTH : integer := 4); + + port (opa_i : in std_logic_vector(DWIDTH-1 downto 0); -- Operand A + opb_i : in std_logic_vector(DWIDTH-1 downto 0); -- Operand B + addsub_i : in std_logic; -- Add or subtract command + cy_i : in std_logic; -- Carry input + cy_o : out std_logic; -- Carry/borrow bit + ov_o : out std_logic; -- Overflow flag + rslt_o : out std_logic_vector(DWIDTH-1 downto 0)); -- Result + +end addsub_ovcy; + diff --git a/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/8051/addsub_ovcy_rtl.vhd b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/8051/addsub_ovcy_rtl.vhd new file mode 100644 index 0000000000000000000000000000000000000000..48740003dae233f643e985f458e43672bc60a69f --- /dev/null +++ b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/8051/addsub_ovcy_rtl.vhd @@ -0,0 +1,138 @@ +------------------------------------------------------------------------------- +-- -- +-- X X XXXXXX XXXXXX XXXXXX XXXXXX X -- +-- XX XX X X X X X X X XX -- +-- X X X X X X X X X X X X -- +-- X X X X X X X X X X X X -- +-- X X X X XXXXXX X X XXXXXX X -- +-- X X X X X X X X X -- +-- X X X X X X X X X -- +-- X X X X X X X X X X -- +-- X X XXXXXX XXXXXX XXXXXX XXXXXX X -- +-- -- +-- -- +-- O R E G A N O S Y S T E M S -- +-- -- +-- Design & Consulting -- +-- -- +------------------------------------------------------------------------------- +-- -- +-- Web: http://www.oregano.at/ -- +-- -- +-- Contact: mc8051@oregano.at -- +-- -- +------------------------------------------------------------------------------- +-- -- +-- MC8051 - VHDL 8051 Microcontroller IP Core -- +-- Copyright (C) 2001 OREGANO SYSTEMS -- +-- -- +-- This library is free software; you can redistribute it and/or -- +-- modify it under the terms of the GNU Lesser General Public -- +-- License as published by the Free Software Foundation; either -- +-- version 2.1 of the License, or (at your option) any later version. -- +-- -- +-- This library is distributed in the hope that it will be useful, -- +-- but WITHOUT ANY WARRANTY; without even the implied warranty of -- +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -- +-- Lesser General Public License for more details. -- +-- -- +-- Full details of the license can be found in the file LGPL.TXT. -- +-- -- +-- You should have received a copy of the GNU Lesser General Public -- +-- License along with this library; if not, write to the Free Software -- +-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -- +-- -- +------------------------------------------------------------------------------- +-- +-- +-- Author: Roland Hller +-- +-- Filename: addsub_ovcy_rtl.vhd +-- +-- Date of Creation: Mon Aug 9 12:14:48 1999 +-- +-- Version: $Revision: 1.4 $ +-- +-- Date of Latest Version: $Date: 2002-01-07 12:17:44 $ +-- +-- +-- Description: Adder/Subtractor with carry/borrow and arbitrary data +-- width and overflow flag. +-- +-- +-- +-- +------------------------------------------------------------------------------- +architecture rtl of addsub_ovcy is + +begin + + gen_equal_one: if (DWIDTH = 1) generate + -- purpose: Simple adder/subtractor with carry/borrow and overflow + -- type : combinational + -- inputs : opa_i, opb_i, addsub_i, cy_i + -- outputs: cy_o, rslt_o + p_addsub_ov: process (opa_i, opb_i, addsub_i, cy_i) + variable v_la : unsigned(1 downto 0); + variable v_lb : unsigned(1 downto 0); + variable v_lresult : std_logic_vector(2 downto 0); + begin -- process p_addsub + v_la(1) := opa_i(DWIDTH-1); + v_lb(1) := opb_i(DWIDTH-1); + if addsub_i = '1' then + v_la(0) := '1'; + v_lb(0) := cy_i; + v_lresult := conv_unsigned(v_la,3) + unsigned(v_lb); + else + v_la(0) := '0'; + v_lb(0) := cy_i; + v_lresult := conv_unsigned(v_la,3) - unsigned(v_lb); + end if; + cy_o <= v_lresult(2); + ov_o <= (cy_i and not(v_lresult(2))) or + (v_lresult(2) and not(cy_i)); + rslt_o(DWIDTH-1) <= v_lresult(1); + end process p_addsub_ov; + end generate gen_equal_one; + + gen_greater_one: if (DWIDTH > 1) generate + -- purpose: Simple adder/subtractor with carry/borrow and overflow + -- type : combinational + -- inputs : opa_i, opb_i, addsub_i, cy_i + -- outputs: cy_o, rslt_o + p_addsub_ov: process (opa_i, opb_i, addsub_i, cy_i) + variable v_a : unsigned(DWIDTH-1 downto 0); + variable v_b : unsigned(DWIDTH-1 downto 0); + variable v_result : std_logic_vector(DWIDTH downto 0); + variable v_la : unsigned(1 downto 0); + variable v_lb : unsigned(1 downto 0); + variable v_lresult : std_logic_vector(2 downto 0); + begin -- process p_addsub + v_a(DWIDTH-1 downto 1) := unsigned(opa_i(DWIDTH-2 downto 0)); + v_b(DWIDTH-1 downto 1) := unsigned(opb_i(DWIDTH-2 downto 0)); + v_la(1) := opa_i(DWIDTH-1); + v_lb(1) := opb_i(DWIDTH-1); + if addsub_i = '1' then + v_a(0) := '1'; + v_b(0) := cy_i; + v_result := conv_unsigned(v_a,DWIDTH+1) + unsigned(v_b); + v_la(0) := '1'; + v_lb(0) := v_result(DWIDTH); + v_lresult := conv_unsigned(v_la,3) + unsigned(v_lb); + else + v_a(0) := '0'; + v_b(0) := cy_i; + v_result := conv_unsigned(v_a,DWIDTH+1) - unsigned(v_b); + v_la(0) := '0'; + v_lb(0) := v_result(DWIDTH); + v_lresult := conv_unsigned(v_la,3) - unsigned(v_lb); + end if; + cy_o <= v_lresult(2); + ov_o <= (v_result(DWIDTH) and not(v_lresult(2))) or + (v_lresult(2) and not(v_result(DWIDTH))); + rslt_o(DWIDTH-2 downto 0) <= v_result(DWIDTH-1 downto 1); + rslt_o(DWIDTH-1) <= v_lresult(1); + end process p_addsub_ov; + end generate gen_greater_one; + +end rtl; diff --git a/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/8051/addsub_ovcy_rtl_cfg.vhd b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/8051/addsub_ovcy_rtl_cfg.vhd new file mode 100644 index 0000000000000000000000000000000000000000..b38433ae21c83eb364b77e87ad1deda656437d6d --- /dev/null +++ b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/8051/addsub_ovcy_rtl_cfg.vhd @@ -0,0 +1,72 @@ +------------------------------------------------------------------------------- +-- -- +-- X X XXXXXX XXXXXX XXXXXX XXXXXX X -- +-- XX XX X X X X X X X XX -- +-- X X X X X X X X X X X X -- +-- X X X X X X X X X X X X -- +-- X X X X XXXXXX X X XXXXXX X -- +-- X X X X X X X X X -- +-- X X X X X X X X X -- +-- X X X X X X X X X X -- +-- X X XXXXXX XXXXXX XXXXXX XXXXXX X -- +-- -- +-- -- +-- O R E G A N O S Y S T E M S -- +-- -- +-- Design & Consulting -- +-- -- +------------------------------------------------------------------------------- +-- -- +-- Web: http://www.oregano.at/ -- +-- -- +-- Contact: mc8051@oregano.at -- +-- -- +------------------------------------------------------------------------------- +-- -- +-- MC8051 - VHDL 8051 Microcontroller IP Core -- +-- Copyright (C) 2001 OREGANO SYSTEMS -- +-- -- +-- This library is free software; you can redistribute it and/or -- +-- modify it under the terms of the GNU Lesser General Public -- +-- License as published by the Free Software Foundation; either -- +-- version 2.1 of the License, or (at your option) any later version. -- +-- -- +-- This library is distributed in the hope that it will be useful, -- +-- but WITHOUT ANY WARRANTY; without even the implied warranty of -- +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -- +-- Lesser General Public License for more details. -- +-- -- +-- Full details of the license can be found in the file LGPL.TXT. -- +-- -- +-- You should have received a copy of the GNU Lesser General Public -- +-- License along with this library; if not, write to the Free Software -- +-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -- +-- -- +------------------------------------------------------------------------------- +-- +-- +-- Author: Roland Hller +-- +-- Filename: addsub_ovcy_rtl_cfg.vhd +-- +-- Date of Creation: Mon Aug 9 12:14:48 1999 +-- +-- Version: $Revision: 1.4 $ +-- +-- Date of Latest Version: $Date: 2002-01-07 12:17:44 $ +-- +-- +-- Description: Adder/Subtractor with carry/borrow and arbitrary data +-- width and overflow flag. +-- +-- +-- +-- +------------------------------------------------------------------------------- +configuration addsub_ovcy_rtl_cfg of addsub_ovcy is + + for rtl + + end for; + +end addsub_ovcy_rtl_cfg; diff --git a/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/8051/alucore_.vhd b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/8051/alucore_.vhd new file mode 100644 index 0000000000000000000000000000000000000000..68b5a34747424e2daa837dd454188f0763d6f650 --- /dev/null +++ b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/8051/alucore_.vhd @@ -0,0 +1,92 @@ +------------------------------------------------------------------------------- +-- -- +-- X X XXXXXX XXXXXX XXXXXX XXXXXX X -- +-- XX XX X X X X X X X XX -- +-- X X X X X X X X X X X X -- +-- X X X X X X X X X X X X -- +-- X X X X XXXXXX X X XXXXXX X -- +-- X X X X X X X X X -- +-- X X X X X X X X X -- +-- X X X X X X X X X X -- +-- X X XXXXXX XXXXXX XXXXXX XXXXXX X -- +-- -- +-- -- +-- O R E G A N O S Y S T E M S -- +-- -- +-- Design & Consulting -- +-- -- +------------------------------------------------------------------------------- +-- -- +-- Web: http://www.oregano.at/ -- +-- -- +-- Contact: mc8051@oregano.at -- +-- -- +------------------------------------------------------------------------------- +-- -- +-- MC8051 - VHDL 8051 Microcontroller IP Core -- +-- Copyright (C) 2001 OREGANO SYSTEMS -- +-- -- +-- This library is free software; you can redistribute it and/or -- +-- modify it under the terms of the GNU Lesser General Public -- +-- License as published by the Free Software Foundation; either -- +-- version 2.1 of the License, or (at your option) any later version. -- +-- -- +-- This library is distributed in the hope that it will be useful, -- +-- but WITHOUT ANY WARRANTY; without even the implied warranty of -- +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -- +-- Lesser General Public License for more details. -- +-- -- +-- Full details of the license can be found in the file LGPL.TXT. -- +-- -- +-- You should have received a copy of the GNU Lesser General Public -- +-- License along with this library; if not, write to the Free Software -- +-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -- +-- -- +------------------------------------------------------------------------------- +-- +-- +-- Author: Roland Hller +-- +-- Filename: alucore_.vhd +-- +-- Date of Creation: Mon Aug 9 12:14:48 1999 +-- +-- Version: $Revision: 1.4 $ +-- +-- Date of Latest Version: $Date: 2002-01-07 12:17:44 $ +-- +-- +-- Description: This unit performs simple logical operations. +-- +-- +-- +-- +------------------------------------------------------------------------------- +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.std_logic_arith.all; +library work; +use work.mc8051_p.all; + +-----------------------------ENTITY DECLARATION-------------------------------- + +entity alucore is + + generic (DWIDTH : integer := 8); -- Data width of the ALU + + port (op_a_i : in std_logic_vector(DWIDTH-1 downto 0); + op_b_i : in std_logic_vector(DWIDTH-1 downto 0); + alu_cmd_i : in std_logic_vector(3 downto 0); + cy_i : in std_logic_vector((DWIDTH-1)/4 downto 0); + cy_o : out std_logic_vector((DWIDTH-1)/4 downto 0); + result_o : out std_logic_vector(DWIDTH-1 downto 0)); + +end alucore; + +-- op_a_i....... operand A +-- op_b_i....... operand B +-- alu_cmd_i.... command for the ALU core +-- cy_i......... carry flags (MSB is CY, rest is AC) + +-- cy_o......... resulting carry out (MSB is CY, rest is AC) +-- result_o..... result diff --git a/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/8051/alucore_rtl.vhd b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/8051/alucore_rtl.vhd new file mode 100644 index 0000000000000000000000000000000000000000..1ff5dc851fbd2c9b471a7f056bf11fe14f3bdfe2 --- /dev/null +++ b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/8051/alucore_rtl.vhd @@ -0,0 +1,161 @@ +------------------------------------------------------------------------------- +-- -- +-- X X XXXXXX XXXXXX XXXXXX XXXXXX X -- +-- XX XX X X X X X X X XX -- +-- X X X X X X X X X X X X -- +-- X X X X X X X X X X X X -- +-- X X X X XXXXXX X X XXXXXX X -- +-- X X X X X X X X X -- +-- X X X X X X X X X -- +-- X X X X X X X X X X -- +-- X X XXXXXX XXXXXX XXXXXX XXXXXX X -- +-- -- +-- -- +-- O R E G A N O S Y S T E M S -- +-- -- +-- Design & Consulting -- +-- -- +------------------------------------------------------------------------------- +-- -- +-- Web: http://www.oregano.at/ -- +-- -- +-- Contact: mc8051@oregano.at -- +-- -- +------------------------------------------------------------------------------- +-- -- +-- MC8051 - VHDL 8051 Microcontroller IP Core -- +-- Copyright (C) 2001 OREGANO SYSTEMS -- +-- -- +-- This library is free software; you can redistribute it and/or -- +-- modify it under the terms of the GNU Lesser General Public -- +-- License as published by the Free Software Foundation; either -- +-- version 2.1 of the License, or (at your option) any later version. -- +-- -- +-- This library is distributed in the hope that it will be useful, -- +-- but WITHOUT ANY WARRANTY; without even the implied warranty of -- +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -- +-- Lesser General Public License for more details. -- +-- -- +-- Full details of the license can be found in the file LGPL.TXT. -- +-- -- +-- You should have received a copy of the GNU Lesser General Public -- +-- License along with this library; if not, write to the Free Software -- +-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -- +-- -- +------------------------------------------------------------------------------- +-- +-- +-- Author: Roland Hller +-- +-- Filename: alucore_rtl.vhd +-- +-- Date of Creation: Mon Aug 9 12:14:48 1999 +-- +-- Version: $Revision: 1.5 $ +-- +-- Date of Latest Version: $Date: 2002-01-07 12:17:44 $ +-- +-- +-- Description: This unit performs simple logical operations. +-- +-- +-- +-- +------------------------------------------------------------------------------- +architecture rtl of alucore is + + constant LAND : std_logic_vector(3 downto 0) := "0011"; + constant LOR : std_logic_vector(3 downto 0) := "0101"; + constant LXOR : std_logic_vector(3 downto 0) := "0110"; + constant RL : std_logic_vector(3 downto 0) := "0111"; + constant RLC : std_logic_vector(3 downto 0) := "1000"; + constant RR : std_logic_vector(3 downto 0) := "1001"; + constant RRC : std_logic_vector(3 downto 0) := "1010"; + constant COMP : std_logic_vector(3 downto 0) := "1011"; + constant INV : std_logic_vector(3 downto 0) := "1100"; + +begin -- architecture structural + + p_alu: process (alu_cmd_i, op_a_i, op_b_i, cy_i) + + begin + + case alu_cmd_i is +------------------------------------------------------------------------------- + when LAND => -- op_a_i and op_b_i + result_o <= op_a_i and op_b_i; + cy_o <= cy_i; +------------------------------------------------------------------------------- + when LOR => -- op_a_i or op_b_i + result_o <= op_a_i or op_b_i; + cy_o <= cy_i; +------------------------------------------------------------------------------- + when LXOR => -- op_a_i xor op_b_i + result_o <= op_a_i xor op_b_i; + cy_o <= cy_i; +------------------------------------------------------------------------------- + when RL => -- rotate left op_a_i + if DWIDTH > 1 then + result_o(DWIDTH-1 downto 1) <= op_a_i(DWIDTH-2 downto 0); + result_o(0) <= op_a_i(DWIDTH-1); + else + result_o <= op_a_i; + end if; + cy_o <= cy_i; +------------------------------------------------------------------------------- + when RLC => -- rotate left op_a_i with CY + if DWIDTH > 1 then + result_o(DWIDTH-1 downto 1) <= op_a_i(DWIDTH-2 downto 0); + result_o(0) <= cy_i((DWIDTH-1)/4); + else + result_o(0) <= cy_i((DWIDTH-1)/4); + end if; + cy_o <= cy_i; + cy_o((DWIDTH-1)/4) <= op_a_i(DWIDTH-1); +------------------------------------------------------------------------------- + when RR => -- rotate right op_a_i + if DWIDTH > 1 then + result_o(DWIDTH-2 downto 0) <= op_a_i(DWIDTH-1 downto 1); + result_o(DWIDTH-1) <= op_a_i(0); + else + result_o <= op_a_i; + end if; + cy_o <= cy_i; +------------------------------------------------------------------------------- + when RRC => -- rotate right op_a_i with CY + if DWIDTH > 1 then + result_o(DWIDTH-2 downto 0) <= op_a_i(DWIDTH-1 downto 1); + result_o(DWIDTH-1) <= cy_i((DWIDTH-1)/4); + else + result_o(0) <= cy_i((DWIDTH-1)/4); + end if; + cy_o <= cy_i; + cy_o((DWIDTH-1)/4) <= op_a_i(0); +------------------------------------------------------------------------------- + when COMP => -- Compare op_a_i with op_b_i + if op_a_i = op_b_i then + result_o <= (others => '0'); + else + result_o <= (others => '1'); + end if; + cy_o <= cy_i; + if op_a_i < op_b_i then + cy_o((DWIDTH-1)/4) <= '1'; + else + cy_o((DWIDTH-1)/4) <= '0'; + end if; +------------------------------------------------------------------------------- + when INV => -- invert op_a_i + result_o <= not(op_a_i); + cy_o <= cy_i; +------------------------------------------------------------------------------- + when others => -- turn unit off + result_o <= (others => '0'); + cy_o <= (others => '0'); +------------------------------------------------------------------------------- + end case; + + end process p_alu; + +end rtl; + diff --git a/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/8051/alucore_rtl_cfg.vhd b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/8051/alucore_rtl_cfg.vhd new file mode 100644 index 0000000000000000000000000000000000000000..3dfff35e90a2290005f5a3888e456f25ebce1883 --- /dev/null +++ b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/8051/alucore_rtl_cfg.vhd @@ -0,0 +1,71 @@ +------------------------------------------------------------------------------- +-- -- +-- X X XXXXXX XXXXXX XXXXXX XXXXXX X -- +-- XX XX X X X X X X X XX -- +-- X X X X X X X X X X X X -- +-- X X X X X X X X X X X X -- +-- X X X X XXXXXX X X XXXXXX X -- +-- X X X X X X X X X -- +-- X X X X X X X X X -- +-- X X X X X X X X X X -- +-- X X XXXXXX XXXXXX XXXXXX XXXXXX X -- +-- -- +-- -- +-- O R E G A N O S Y S T E M S -- +-- -- +-- Design & Consulting -- +-- -- +------------------------------------------------------------------------------- +-- -- +-- Web: http://www.oregano.at/ -- +-- -- +-- Contact: mc8051@oregano.at -- +-- -- +------------------------------------------------------------------------------- +-- -- +-- MC8051 - VHDL 8051 Microcontroller IP Core -- +-- Copyright (C) 2001 OREGANO SYSTEMS -- +-- -- +-- This library is free software; you can redistribute it and/or -- +-- modify it under the terms of the GNU Lesser General Public -- +-- License as published by the Free Software Foundation; either -- +-- version 2.1 of the License, or (at your option) any later version. -- +-- -- +-- This library is distributed in the hope that it will be useful, -- +-- but WITHOUT ANY WARRANTY; without even the implied warranty of -- +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -- +-- Lesser General Public License for more details. -- +-- -- +-- Full details of the license can be found in the file LGPL.TXT. -- +-- -- +-- You should have received a copy of the GNU Lesser General Public -- +-- License along with this library; if not, write to the Free Software -- +-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -- +-- -- +------------------------------------------------------------------------------- +-- +-- +-- Author: Roland Hller +-- +-- Filename: alucore_rtl_cfg.vhd +-- +-- Date of Creation: Mon Aug 9 12:14:48 1999 +-- +-- Version: $Revision: 1.4 $ +-- +-- Date of Latest Version: $Date: 2002-01-07 12:17:44 $ +-- +-- +-- Description: This unit performs simple logical operations. +-- +-- +-- +-- +------------------------------------------------------------------------------- +configuration alucore_rtl_cfg of alucore is + + for rtl + + end for; + +end alucore_rtl_cfg; diff --git a/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/8051/alumux_.vhd b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/8051/alumux_.vhd new file mode 100644 index 0000000000000000000000000000000000000000..5f5742f2da018be7e0490ea43ac9309ca580a8a5 --- /dev/null +++ b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/8051/alumux_.vhd @@ -0,0 +1,124 @@ +------------------------------------------------------------------------------- +-- -- +-- X X XXXXXX XXXXXX XXXXXX XXXXXX X -- +-- XX XX X X X X X X X XX -- +-- X X X X X X X X X X X X -- +-- X X X X X X X X X X X X -- +-- X X X X XXXXXX X X XXXXXX X -- +-- X X X X X X X X X -- +-- X X X X X X X X X -- +-- X X X X X X X X X X -- +-- X X XXXXXX XXXXXX XXXXXX XXXXXX X -- +-- -- +-- -- +-- O R E G A N O S Y S T E M S -- +-- -- +-- Design & Consulting -- +-- -- +------------------------------------------------------------------------------- +-- -- +-- Web: http://www.oregano.at/ -- +-- -- +-- Contact: mc8051@oregano.at -- +-- -- +------------------------------------------------------------------------------- +-- -- +-- MC8051 - VHDL 8051 Microcontroller IP Core -- +-- Copyright (C) 2001 OREGANO SYSTEMS -- +-- -- +-- This library is free software; you can redistribute it and/or -- +-- modify it under the terms of the GNU Lesser General Public -- +-- License as published by the Free Software Foundation; either -- +-- version 2.1 of the License, or (at your option) any later version. -- +-- -- +-- This library is distributed in the hope that it will be useful, -- +-- but WITHOUT ANY WARRANTY; without even the implied warranty of -- +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -- +-- Lesser General Public License for more details. -- +-- -- +-- Full details of the license can be found in the file LGPL.TXT. -- +-- -- +-- You should have received a copy of the GNU Lesser General Public -- +-- License along with this library; if not, write to the Free Software -- +-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -- +-- -- +------------------------------------------------------------------------------- +-- +-- +-- Author: Roland Hller +-- +-- Filename: alumux_.vhd +-- +-- Date of Creation: Mon Aug 9 12:14:48 1999 +-- +-- Version: $Revision: 1.6 $ +-- +-- Date of Latest Version: $Date: 2002-01-07 12:17:44 $ +-- +-- +-- Description: Select data path according to the actual command. +-- +-- +-- +-- +------------------------------------------------------------------------------- +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.std_logic_arith.all; +library work; +use work.mc8051_p.all; + +-----------------------------ENTITY DECLARATION-------------------------------- + + +entity alumux is + + generic (DWIDTH : integer := 8); -- Data width of the ALU + + port ( + -- inputs from control unit + rom_data_i : in std_logic_vector(DWIDTH-1 downto 0); + ram_data_i : in std_logic_vector(DWIDTH-1 downto 0); + acc_i : in std_logic_vector(DWIDTH-1 downto 0); + cmd_i : in std_logic_vector(5 downto 0); + cy_i : in std_logic_vector((DWIDTH-1)/4 downto 0); + ov_i : in std_logic; + -- outputs to control unit + cy_o : out std_logic_vector((DWIDTH-1)/4 downto 0); + ov_o : out std_logic; + result_a_o : out std_logic_vector(DWIDTH-1 downto 0); + result_b_o : out std_logic_vector(DWIDTH-1 downto 0); + -- inputs from alu core + result_i : in std_logic_vector(DWIDTH-1 downto 0); + new_cy_i : in std_logic_vector((DWIDTH-1)/4 downto 0); + -- inputs from addsub unit + addsub_rslt_i : in std_logic_vector(DWIDTH-1 downto 0); + addsub_cy_i : in std_logic_vector((DWIDTH-1)/4 downto 0); + addsub_ov_i : in std_logic; + -- outputs to alu core + op_a_o : out std_logic_vector(DWIDTH-1 downto 0); + op_b_o : out std_logic_vector(DWIDTH-1 downto 0); + alu_cmd_o : out std_logic_vector(3 downto 0); + -- outputs to addsub unit + opa_o : out std_logic_vector(DWIDTH-1 downto 0); + opb_o : out std_logic_vector(DWIDTH-1 downto 0); + addsub_o : out std_logic; + addsub_cy_o : out std_logic; + -- outputs to divider unit + dvdnd_o : out std_logic_vector(DWIDTH-1 downto 0); + dvsor_o : out std_logic_vector(DWIDTH-1 downto 0); + -- inputs from divider + qutnt_i : in std_logic_vector(DWIDTH-1 downto 0); + rmndr_i : in std_logic_vector(DWIDTH-1 downto 0); + -- outputs to multiplier + mltplcnd_o : out std_logic_vector(DWIDTH-1 downto 0); + mltplctr_o : out std_logic_vector(DWIDTH-1 downto 0); + -- inputs from multiplier + product_i : in std_logic_vector((DWIDTH*2)-1 downto 0); + -- outputs to decimal adjustement + dcml_data_o : out std_logic_vector(DWIDTH-1 downto 0); + -- inputs from decimal adjustement + dcml_data_i : in std_logic_vector(DWIDTH-1 downto 0); + dcml_cy_i : in std_logic); + +end alumux; diff --git a/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/8051/alumux_rtl.vhd b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/8051/alumux_rtl.vhd new file mode 100644 index 0000000000000000000000000000000000000000..ab698847f04d199b4df8e642965e3a010fed12bf --- /dev/null +++ b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/8051/alumux_rtl.vhd @@ -0,0 +1,432 @@ +------------------------------------------------------------------------------- +-- -- +-- X X XXXXXX XXXXXX XXXXXX XXXXXX X -- +-- XX XX X X X X X X X XX -- +-- X X X X X X X X X X X X -- +-- X X X X X X X X X X X X -- +-- X X X X XXXXXX X X XXXXXX X -- +-- X X X X X X X X X -- +-- X X X X X X X X X -- +-- X X X X X X X X X X -- +-- X X XXXXXX XXXXXX XXXXXX XXXXXX X -- +-- -- +-- -- +-- O R E G A N O S Y S T E M S -- +-- -- +-- Design & Consulting -- +-- -- +------------------------------------------------------------------------------- +-- -- +-- Web: http://www.oregano.at/ -- +-- -- +-- Contact: mc8051@oregano.at -- +-- -- +------------------------------------------------------------------------------- +-- -- +-- MC8051 - VHDL 8051 Microcontroller IP Core -- +-- Copyright (C) 2001 OREGANO SYSTEMS -- +-- -- +-- This library is free software; you can redistribute it and/or -- +-- modify it under the terms of the GNU Lesser General Public -- +-- License as published by the Free Software Foundation; either -- +-- version 2.1 of the License, or (at your option) any later version. -- +-- -- +-- This library is distributed in the hope that it will be useful, -- +-- but WITHOUT ANY WARRANTY; without even the implied warranty of -- +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -- +-- Lesser General Public License for more details. -- +-- -- +-- Full details of the license can be found in the file LGPL.TXT. -- +-- -- +-- You should have received a copy of the GNU Lesser General Public -- +-- License along with this library; if not, write to the Free Software -- +-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -- +-- -- +------------------------------------------------------------------------------- +-- +-- +-- Author: Roland Hller +-- +-- Filename: alumux_rtl.vhd +-- +-- Date of Creation: Mon Aug 9 12:14:48 1999 +-- +-- Version: $Revision: 1.6 $ +-- +-- Date of Latest Version: $Date: 2002-01-07 12:17:44 $ +-- +-- +-- Description: Select data path according to the actual command. +-- +-- +-- +-- +------------------------------------------------------------------------------- +architecture rtl of alumux is + + constant DA : std_logic_vector(5 downto 0) := "100000"; + constant ADD_ACC_RAM : std_logic_vector(5 downto 0) := "100001"; + constant ADD_ACC_ROM : std_logic_vector(5 downto 0) := "100010"; + constant ADDC_ACC_RAM : std_logic_vector(5 downto 0) := "100011"; + constant ADDC_ACC_ROM : std_logic_vector(5 downto 0) := "100100"; + constant AND_ACC_RAM : std_logic_vector(5 downto 0) := "100101"; + constant AND_ACC_ROM : std_logic_vector(5 downto 0) := "100110"; + constant AND_RAM_ROM : std_logic_vector(5 downto 0) := "100111"; + constant SUB_ACC_RAM : std_logic_vector(5 downto 0) := "101000"; + constant SUB_ACC_ROM : std_logic_vector(5 downto 0) := "101001"; + constant MUL_ACC_RAM : std_logic_vector(5 downto 0) := "101010"; + constant DIV_ACC_RAM : std_logic_vector(5 downto 0) := "101011"; + constant OR_RAM_ACC : std_logic_vector(5 downto 0) := "101100"; + constant OR_ROM_ACC : std_logic_vector(5 downto 0) := "101101"; + constant OR_ROM_RAM : std_logic_vector(5 downto 0) := "101110"; + constant XOR_RAM_ACC : std_logic_vector(5 downto 0) := "101111"; + constant XOR_ROM_ACC : std_logic_vector(5 downto 0) := "110000"; + constant XOR_ROM_RAM : std_logic_vector(5 downto 0) := "110001"; + constant RL_ACC : std_logic_vector(5 downto 0) := "110010"; + constant RLC_ACC : std_logic_vector(5 downto 0) := "110011"; + constant RR_ACC : std_logic_vector(5 downto 0) := "110100"; + constant RRC_ACC : std_logic_vector(5 downto 0) := "110101"; + constant INV_ACC : std_logic_vector(5 downto 0) := "110110"; + constant INV_RAM : std_logic_vector(5 downto 0) := "110111"; + constant DEC_ACC : std_logic_vector(5 downto 0) := "111000"; + constant DEC_RAM : std_logic_vector(5 downto 0) := "111001"; + constant COMP_RAM_ACC : std_logic_vector(5 downto 0) := "111010"; + constant COMP_ROM_ACC : std_logic_vector(5 downto 0) := "111011"; + constant COMP_ROM_RAM : std_logic_vector(5 downto 0) := "111100"; + constant INC_ACC : std_logic_vector(5 downto 0) := "111110"; + constant INC_RAM : std_logic_vector(5 downto 0) := "111111"; + + constant NOP : std_logic_vector(3 downto 0) := "0000"; + constant LAND : std_logic_vector(3 downto 0) := "0011"; + constant LOR : std_logic_vector(3 downto 0) := "0101"; + constant LXOR : std_logic_vector(3 downto 0) := "0110"; + constant RL : std_logic_vector(3 downto 0) := "0111"; + constant RLC : std_logic_vector(3 downto 0) := "1000"; + constant RR : std_logic_vector(3 downto 0) := "1001"; + constant RRC : std_logic_vector(3 downto 0) := "1010"; + constant COMP : std_logic_vector(3 downto 0) := "1011"; + constant INV : std_logic_vector(3 downto 0) := "1100"; + +begin + + -- Multiplex the input data and generate the command for the alu core. + p_alucore_mux : process (rom_data_i, + ram_data_i, + acc_i, + cmd_i) + begin + case cmd_i is + when AND_ACC_RAM => + alu_cmd_o <= LAND; + op_a_o <= acc_i; + op_b_o <= ram_data_i; + when AND_ACC_ROM => + alu_cmd_o <= LAND; + op_a_o <= acc_i; + op_b_o <= rom_data_i; + when AND_RAM_ROM => + alu_cmd_o <= LAND; + op_a_o <= ram_data_i; + op_b_o <= rom_data_i; + when OR_RAM_ACC => + alu_cmd_o <= LOR; + op_a_o <= acc_i; + op_b_o <= ram_data_i; + when OR_ROM_ACC => + alu_cmd_o <= LOR; + op_a_o <= acc_i; + op_b_o <= rom_data_i; + when OR_ROM_RAM => + alu_cmd_o <= LOR; + op_a_o <= rom_data_i; + op_b_o <= ram_data_i; + when XOR_RAM_ACC => + alu_cmd_o <= LXOR; + op_a_o <= acc_i; + op_b_o <= ram_data_i; + when XOR_ROM_ACC => + alu_cmd_o <= LXOR; + op_a_o <= acc_i; + op_b_o <= rom_data_i; + when XOR_ROM_RAM => + alu_cmd_o <= LXOR; + op_a_o <= rom_data_i; + op_b_o <= ram_data_i; + when RL_ACC => + alu_cmd_o <= RL; + op_a_o <= acc_i; + op_b_o <= ( others => '0' ); + when RLC_ACC => + alu_cmd_o <= RLC; + op_a_o <= acc_i; + op_b_o <= ( others => '0' ); + when RR_ACC => + alu_cmd_o <= RR; + op_a_o <= acc_i; + op_b_o <= ( others => '0' ); + when RRC_ACC => + alu_cmd_o <= RRC; + op_a_o <= acc_i; + op_b_o <= ( others => '0' ); + when INV_ACC => + alu_cmd_o <= INV; + op_a_o <= acc_i; + op_b_o <= ( others => '0' ); + when INV_RAM => + alu_cmd_o <= INV; + op_a_o <= ram_data_i; + op_b_o <= ( others => '0' ); + when COMP_RAM_ACC => + alu_cmd_o <= COMP; + op_a_o <= acc_i; + op_b_o <= ram_data_i; + when COMP_ROM_ACC => + alu_cmd_o <= COMP; + op_a_o <= acc_i; + op_b_o <= rom_data_i; + when COMP_ROM_RAM => + alu_cmd_o <= COMP; + op_a_o <= ram_data_i; + op_b_o <= rom_data_i; + when others => + alu_cmd_o <= NOP; + op_a_o <= ( others => '0' ); + op_b_o <= ( others => '0' ); + end case; + end process p_alucore_mux; + + -- Multiplex the input data for all the functions not included in the + -- alu core. + p_ext_mux : process (ram_data_i, + rom_data_i, + acc_i, + cy_i, + cmd_i) + begin + case cmd_i is + when DA => + dcml_data_o <= acc_i; + mltplcnd_o <= ( others => '0' ); + mltplctr_o <= ( others => '0' ); + dvdnd_o <= ( others => '0' ); + dvsor_o <= ( others => '0' ); + addsub_o <= '0'; + addsub_cy_o <= '0'; + opa_o <= ( others => '0' ); + opb_o <= ( others => '0' ); + when DIV_ACC_RAM => + dcml_data_o <= ( others => '0' ); + mltplcnd_o <= ( others => '0' ); + mltplctr_o <= ( others => '0' ); + dvdnd_o <= acc_i; + dvsor_o <= ram_data_i; + addsub_o <= '0'; + addsub_cy_o <= '0'; + opa_o <= ( others => '0' ); + opb_o <= ( others => '0' ); + when MUL_ACC_RAM => + dcml_data_o <= ( others => '0' ); + mltplcnd_o <= acc_i; + mltplctr_o <= ram_data_i; + dvdnd_o <= ( others => '0' ); + dvsor_o <= ( others => '0' ); + addsub_o <= '0'; + addsub_cy_o <= '0'; + opa_o <= ( others => '0' ); + opb_o <= ( others => '0' ); + when INC_ACC => + dcml_data_o <= ( others => '0' ); + mltplcnd_o <= ( others => '0' ); + mltplctr_o <= ( others => '0' ); + dvdnd_o <= ( others => '0' ); + dvsor_o <= ( others => '0' ); + addsub_o <= '1'; + addsub_cy_o <= '0'; + opa_o <= acc_i; + opb_o <= std_logic_vector(conv_unsigned(1, DWIDTH)); + when INC_RAM => + dcml_data_o <= ( others => '0' ); + mltplcnd_o <= ( others => '0' ); + mltplctr_o <= ( others => '0' ); + dvdnd_o <= ( others => '0' ); + dvsor_o <= ( others => '0' ); + addsub_o <= '1'; + addsub_cy_o <= '0'; + opa_o <= ram_data_i; + opb_o <= std_logic_vector(conv_unsigned(1, DWIDTH)); + when DEC_ACC => + dcml_data_o <= ( others => '0' ); + mltplcnd_o <= ( others => '0' ); + mltplctr_o <= ( others => '0' ); + dvdnd_o <= ( others => '0' ); + dvsor_o <= ( others => '0' ); + addsub_o <= '0'; + addsub_cy_o <= '0'; + opa_o <= acc_i; + opb_o <= std_logic_vector(conv_unsigned(1, DWIDTH)); + when DEC_RAM => + dcml_data_o <= ( others => '0' ); + mltplcnd_o <= ( others => '0' ); + mltplctr_o <= ( others => '0' ); + dvdnd_o <= ( others => '0' ); + dvsor_o <= ( others => '0' ); + addsub_o <= '0'; + addsub_cy_o <= '0'; + opa_o <= ram_data_i; + opb_o <= std_logic_vector(conv_unsigned(1, DWIDTH)); + when SUB_ACC_RAM => + dcml_data_o <= ( others => '0' ); + mltplcnd_o <= ( others => '0' ); + mltplctr_o <= ( others => '0' ); + dvdnd_o <= ( others => '0' ); + dvsor_o <= ( others => '0' ); + addsub_o <= '0'; + addsub_cy_o <= cy_i((DWIDTH-1)/4); + opa_o <= acc_i; + opb_o <= ram_data_i; + when SUB_ACC_ROM => + dcml_data_o <= ( others => '0' ); + mltplcnd_o <= ( others => '0' ); + mltplctr_o <= ( others => '0' ); + dvdnd_o <= ( others => '0' ); + dvsor_o <= ( others => '0' ); + addsub_o <= '0'; + addsub_cy_o <= cy_i((DWIDTH-1)/4); + opa_o <= acc_i; + opb_o <= rom_data_i; + when ADD_ACC_RAM => + dcml_data_o <= ( others => '0' ); + mltplcnd_o <= ( others => '0' ); + mltplctr_o <= ( others => '0' ); + dvdnd_o <= ( others => '0' ); + dvsor_o <= ( others => '0' ); + addsub_o <= '1'; + addsub_cy_o <= '0'; + opa_o <= acc_i; + opb_o <= ram_data_i; + when ADD_ACC_ROM => + dcml_data_o <= ( others => '0' ); + mltplcnd_o <= ( others => '0' ); + mltplctr_o <= ( others => '0' ); + dvdnd_o <= ( others => '0' ); + dvsor_o <= ( others => '0' ); + addsub_o <= '1'; + addsub_cy_o <= '0'; + opa_o <= acc_i; + opb_o <= rom_data_i; + when ADDC_ACC_RAM => + dcml_data_o <= ( others => '0' ); + mltplcnd_o <= ( others => '0' ); + mltplctr_o <= ( others => '0' ); + dvdnd_o <= ( others => '0' ); + dvsor_o <= ( others => '0' ); + addsub_o <= '1'; + addsub_cy_o <= cy_i((DWIDTH-1)/4); + opa_o <= acc_i; + opb_o <= ram_data_i; + when ADDC_ACC_ROM => + dcml_data_o <= ( others => '0' ); + mltplcnd_o <= ( others => '0' ); + mltplctr_o <= ( others => '0' ); + dvdnd_o <= ( others => '0' ); + dvsor_o <= ( others => '0' ); + addsub_o <= '1'; + addsub_cy_o <= cy_i((DWIDTH-1)/4); + opa_o <= acc_i; + opb_o <= rom_data_i; + when others => + dcml_data_o <= ( others => '0' ); + mltplcnd_o <= ( others => '0' ); + mltplctr_o <= ( others => '0' ); + dvdnd_o <= ( others => '0' ); + dvsor_o <= ( others => '0' ); + addsub_o <= '0'; + addsub_cy_o <= '0'; + opa_o <= ( others => '0' ); + opb_o <= ( others => '0' ); + end case; + end process p_ext_mux; + + -- Multiplex the results for all the units contributing to the ALU. + p_rslt_mux : process (ram_data_i, + cy_i, + ov_i, + product_i, + qutnt_i, + rmndr_i, + result_i, + new_cy_i, + addsub_rslt_i, + addsub_cy_i, + addsub_ov_i, + dcml_data_i, + dcml_cy_i, + cmd_i) + begin + case cmd_i is + when DA => + if (C_IMPL_DA /= 0) then + result_a_o <= dcml_data_i; + result_b_o <= ( others => '0' ); + cy_o <= cy_i; + cy_o((DWIDTH-1)/4) <= dcml_cy_i; + ov_o <= ov_i; + else + result_a_o <= ( others => '0' ); + result_b_o <= ( others => '0' ); + cy_o <= conv_std_logic_vector(0,(DWIDTH-1)/4+1); + ov_o <= '0'; + end if; + when DIV_ACC_RAM => + if (C_IMPL_DIV /= 0) then + result_a_o <= qutnt_i; + result_b_o <= rmndr_i; + cy_o <= conv_std_logic_vector(0,(DWIDTH-1)/4+1); + if ram_data_i = conv_std_logic_vector(0,DWIDTH) then + ov_o <= '1'; + else + ov_o <= '0'; + end if; + else + result_a_o <= ( others => '0' ); + result_b_o <= ( others => '0' ); + cy_o <= conv_std_logic_vector(0,(DWIDTH-1)/4+1); + ov_o <= '0'; + end if; + when MUL_ACC_RAM => + if (C_IMPL_MUL /= 0) then + result_a_o <= product_i(DWIDTH-1 downto 0); + result_b_o <= product_i(DWIDTH*2-1 downto DWIDTH); + cy_o <= conv_std_logic_vector(0,(DWIDTH-1)/4+1); + if product_i(DWIDTH*2-1 downto DWIDTH) + = conv_std_logic_vector(0, DWIDTH) then + ov_o <= '0'; + else + ov_o <= '1'; + end if; + else + result_a_o <= ( others => '0' ); + result_b_o <= ( others => '0' ); + cy_o <= conv_std_logic_vector(0,(DWIDTH-1)/4+1); + ov_o <= '0'; + end if; + when SUB_ACC_RAM | SUB_ACC_ROM | ADD_ACC_RAM | ADD_ACC_ROM | + ADDC_ACC_RAM | ADDC_ACC_ROM => + result_a_o <= addsub_rslt_i; + result_b_o <= ( others => '0' ); + cy_o <= addsub_cy_i; + ov_o <= addsub_ov_i; + when INC_ACC | INC_RAM | DEC_ACC | DEC_RAM => + result_a_o <= addsub_rslt_i; + result_b_o <= ( others => '0' ); + cy_o <= cy_i; + ov_o <= addsub_ov_i; + when others => + result_a_o <= result_i; + result_b_o <= ( others => '0' ); + cy_o <= new_cy_i; + ov_o <= ov_i; + end case; + end process p_rslt_mux; + +end rtl; diff --git a/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/8051/alumux_rtl_cfg.vhd b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/8051/alumux_rtl_cfg.vhd new file mode 100644 index 0000000000000000000000000000000000000000..a09557bb4b9e9f5883a1122528d473d2947d94c0 --- /dev/null +++ b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/8051/alumux_rtl_cfg.vhd @@ -0,0 +1,68 @@ +------------------------------------------------------------------------------- +-- -- +-- X X XXXXXX XXXXXX XXXXXX XXXXXX X -- +-- XX XX X X X X X X X XX -- +-- X X X X X X X X X X X X -- +-- X X X X X X X X X X X X -- +-- X X X X XXXXXX X X XXXXXX X -- +-- X X X X X X X X X -- +-- X X X X X X X X X -- +-- X X X X X X X X X X -- +-- X X XXXXXX XXXXXX XXXXXX XXXXXX X -- +-- -- +-- -- +-- O R E G A N O S Y S T E M S -- +-- -- +-- Design & Consulting -- +-- -- +------------------------------------------------------------------------------- +-- -- +-- Web: http://www.oregano.at/ -- +-- -- +-- Contact: mc8051@oregano.at -- +-- -- +------------------------------------------------------------------------------- +-- -- +-- MC8051 - VHDL 8051 Microcontroller IP Core -- +-- Copyright (C) 2001 OREGANO SYSTEMS -- +-- -- +-- This library is free software; you can redistribute it and/or -- +-- modify it under the terms of the GNU Lesser General Public -- +-- License as published by the Free Software Foundation; either -- +-- version 2.1 of the License, or (at your option) any later version. -- +-- -- +-- This library is distributed in the hope that it will be useful, -- +-- but WITHOUT ANY WARRANTY; without even the implied warranty of -- +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -- +-- Lesser General Public License for more details. -- +-- -- +-- Full details of the license can be found in the file LGPL.TXT. -- +-- -- +-- You should have received a copy of the GNU Lesser General Public -- +-- License along with this library; if not, write to the Free Software -- +-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -- +-- -- +------------------------------------------------------------------------------- +-- +-- +-- Author: Roland Hller +-- +-- Filename: alumux_rtl_cfg.vhd +-- +-- Date of Creation: Mon Aug 9 12:14:48 1999 +-- +-- Version: $Revision: 1.4 $ +-- +-- Date of Latest Version: $Date: 2002-01-07 12:17:44 $ +-- +-- +-- Description: Select data path according to the actual command. +-- +-- +-- +-- +------------------------------------------------------------------------------- +configuration alumux_rtl_cfg of alumux is + for rtl + end for; +end alumux_rtl_cfg; diff --git a/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/8051/comb_divider_.vhd b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/8051/comb_divider_.vhd new file mode 100644 index 0000000000000000000000000000000000000000..1161c81e037c07d248e654d41b82a6e255d29559 --- /dev/null +++ b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/8051/comb_divider_.vhd @@ -0,0 +1,82 @@ +------------------------------------------------------------------------------- +-- -- +-- X X XXXXXX XXXXXX XXXXXX XXXXXX X -- +-- XX XX X X X X X X X XX -- +-- X X X X X X X X X X X X -- +-- X X X X X X X X X X X X -- +-- X X X X XXXXXX X X XXXXXX X -- +-- X X X X X X X X X -- +-- X X X X X X X X X -- +-- X X X X X X X X X X -- +-- X X XXXXXX XXXXXX XXXXXX XXXXXX X -- +-- -- +-- -- +-- O R E G A N O S Y S T E M S -- +-- -- +-- Design & Consulting -- +-- -- +------------------------------------------------------------------------------- +-- -- +-- Web: http://www.oregano.at/ -- +-- -- +-- Contact: mc8051@oregano.at -- +-- -- +------------------------------------------------------------------------------- +-- -- +-- MC8051 - VHDL 8051 Microcontroller IP Core -- +-- Copyright (C) 2001 OREGANO SYSTEMS -- +-- -- +-- This library is free software; you can redistribute it and/or -- +-- modify it under the terms of the GNU Lesser General Public -- +-- License as published by the Free Software Foundation; either -- +-- version 2.1 of the License, or (at your option) any later version. -- +-- -- +-- This library is distributed in the hope that it will be useful, -- +-- but WITHOUT ANY WARRANTY; without even the implied warranty of -- +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -- +-- Lesser General Public License for more details. -- +-- -- +-- Full details of the license can be found in the file LGPL.TXT. -- +-- -- +-- You should have received a copy of the GNU Lesser General Public -- +-- License along with this library; if not, write to the Free Software -- +-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -- +-- -- +------------------------------------------------------------------------------- +-- +-- +-- Author: Roland Hller +-- +-- Filename: comb_divider_.vhd +-- +-- Date of Creation: Mon Aug 9 12:14:48 1999 +-- +-- Version: $Revision: 1.4 $ +-- +-- Date of Latest Version: $Date: 2002-01-07 12:17:44 $ +-- +-- +-- Description: Divider with parameteriseable data width. Realised +-- using combinational logic only. +-- +-- +-- +-- +------------------------------------------------------------------------------- +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.std_logic_arith.all; + +-----------------------------ENTITY DECLARATION-------------------------------- + +entity comb_divider is + + generic (DWIDTH : integer := 8); + + port (dvdnd_i : in std_logic_vector(DWIDTH-1 downto 0); -- Dividend + dvsor_i : in std_logic_vector(DWIDTH-1 downto 0); -- Divisor + qutnt_o : out std_logic_vector(DWIDTH-1 downto 0); -- Quotient + rmndr_o : out std_logic_vector(DWIDTH-1 downto 0)); -- Remainder + +end comb_divider; + diff --git a/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/8051/comb_divider_rtl.vhd b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/8051/comb_divider_rtl.vhd new file mode 100644 index 0000000000000000000000000000000000000000..6ca5044a69eacb84dea688eb6e5cdcf44d967373 --- /dev/null +++ b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/8051/comb_divider_rtl.vhd @@ -0,0 +1,114 @@ +------------------------------------------------------------------------------- +-- -- +-- X X XXXXXX XXXXXX XXXXXX XXXXXX X -- +-- XX XX X X X X X X X XX -- +-- X X X X X X X X X X X X -- +-- X X X X X X X X X X X X -- +-- X X X X XXXXXX X X XXXXXX X -- +-- X X X X X X X X X -- +-- X X X X X X X X X -- +-- X X X X X X X X X X -- +-- X X XXXXXX XXXXXX XXXXXX XXXXXX X -- +-- -- +-- -- +-- O R E G A N O S Y S T E M S -- +-- -- +-- Design & Consulting -- +-- -- +------------------------------------------------------------------------------- +-- -- +-- Web: http://www.oregano.at/ -- +-- -- +-- Contact: mc8051@oregano.at -- +-- -- +------------------------------------------------------------------------------- +-- -- +-- MC8051 - VHDL 8051 Microcontroller IP Core -- +-- Copyright (C) 2001 OREGANO SYSTEMS -- +-- -- +-- This library is free software; you can redistribute it and/or -- +-- modify it under the terms of the GNU Lesser General Public -- +-- License as published by the Free Software Foundation; either -- +-- version 2.1 of the License, or (at your option) any later version. -- +-- -- +-- This library is distributed in the hope that it will be useful, -- +-- but WITHOUT ANY WARRANTY; without even the implied warranty of -- +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -- +-- Lesser General Public License for more details. -- +-- -- +-- Full details of the license can be found in the file LGPL.TXT. -- +-- -- +-- You should have received a copy of the GNU Lesser General Public -- +-- License along with this library; if not, write to the Free Software -- +-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -- +-- -- +------------------------------------------------------------------------------- +-- +-- +-- Author: Roland Hller +-- +-- Filename: comb_divider_rtl.vhd +-- +-- Date of Creation: Mon Aug 9 12:14:48 1999 +-- +-- Version: $Revision: 1.4 $ +-- +-- Date of Latest Version: $Date: 2002-01-07 12:17:44 $ +-- +-- +-- Description: Divider with parameteriseable data width. Realised +-- using combinational logic only. +-- +-- +-- +-- +------------------------------------------------------------------------------- +architecture rtl of comb_divider is + +begin -- rtl + + -- purpose: Divide dvdnd_i through dvsor_i and deliver the result to qutnt_o + -- and the remainder to rmndr_o. + -- type : combinational + -- inputs : dvdnd_i, dvsor_i + -- outputs: qutnt_o, rmndr_o + p_divide: process (dvdnd_i, dvsor_i) + + variable v_actl_dvdnd : unsigned(DWIDTH-1 downto 0); + variable v_dffrnc : unsigned(DWIDTH-1 downto 0); + variable v_qutnt : unsigned(DWIDTH-1 downto 0); + + begin -- process p_divide + + v_actl_dvdnd := unsigned(dvdnd_i); + + for i in DWIDTH-1 downto 0 loop + -- If the divisor can be subtracted from this part of the dividend, then + -- the corresponding bit of the quotient has to be 1, otherwise 0. + if conv_std_logic_vector(v_actl_dvdnd(DWIDTH-1 downto i),DWIDTH) >= + dvsor_i then + -- Divisor can be subtracted + v_qutnt(i) := '1'; + v_dffrnc := conv_unsigned(v_actl_dvdnd(DWIDTH-1 downto i),DWIDTH) + - unsigned(dvsor_i); + -- As long as this is not the last step of calculation, shift the + -- intermediate result. + if i /= 0 then + v_actl_dvdnd(DWIDTH-1 downto i) := v_dffrnc(DWIDTH-1-i downto 0); + v_actl_dvdnd(i-1) := dvdnd_i(i-1); + end if; + else + -- Divisor is greater than this part of the dividend. + v_qutnt(i) := '0'; + v_dffrnc := conv_unsigned(v_actl_dvdnd(DWIDTH-1 downto i),DWIDTH); + end if; + end loop; -- i + + rmndr_o <= std_logic_vector(v_dffrnc); + qutnt_o <= std_logic_vector(v_qutnt); + + end process p_divide; + +end rtl; + + diff --git a/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/8051/comb_divider_rtl_cfg.vhd b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/8051/comb_divider_rtl_cfg.vhd new file mode 100644 index 0000000000000000000000000000000000000000..ddec90a11549576429ac37c7eedf6b15dcc35034 --- /dev/null +++ b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/8051/comb_divider_rtl_cfg.vhd @@ -0,0 +1,72 @@ +------------------------------------------------------------------------------- +-- -- +-- X X XXXXXX XXXXXX XXXXXX XXXXXX X -- +-- XX XX X X X X X X X XX -- +-- X X X X X X X X X X X X -- +-- X X X X X X X X X X X X -- +-- X X X X XXXXXX X X XXXXXX X -- +-- X X X X X X X X X -- +-- X X X X X X X X X -- +-- X X X X X X X X X X -- +-- X X XXXXXX XXXXXX XXXXXX XXXXXX X -- +-- -- +-- -- +-- O R E G A N O S Y S T E M S -- +-- -- +-- Design & Consulting -- +-- -- +------------------------------------------------------------------------------- +-- -- +-- Web: http://www.oregano.at/ -- +-- -- +-- Contact: mc8051@oregano.at -- +-- -- +------------------------------------------------------------------------------- +-- -- +-- MC8051 - VHDL 8051 Microcontroller IP Core -- +-- Copyright (C) 2001 OREGANO SYSTEMS -- +-- -- +-- This library is free software; you can redistribute it and/or -- +-- modify it under the terms of the GNU Lesser General Public -- +-- License as published by the Free Software Foundation; either -- +-- version 2.1 of the License, or (at your option) any later version. -- +-- -- +-- This library is distributed in the hope that it will be useful, -- +-- but WITHOUT ANY WARRANTY; without even the implied warranty of -- +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -- +-- Lesser General Public License for more details. -- +-- -- +-- Full details of the license can be found in the file LGPL.TXT. -- +-- -- +-- You should have received a copy of the GNU Lesser General Public -- +-- License along with this library; if not, write to the Free Software -- +-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -- +-- -- +------------------------------------------------------------------------------- +-- +-- +-- Author: Roland Hller +-- +-- Filename: comb_divider_rtl_cfg.vhd +-- +-- Date of Creation: Mon Aug 9 12:14:48 1999 +-- +-- Version: $Revision: 1.4 $ +-- +-- Date of Latest Version: $Date: 2002-01-07 12:17:44 $ +-- +-- +-- Description: Divider with parameteriseable data width. Realised +-- using combinational logic only. +-- +-- +-- +-- +------------------------------------------------------------------------------- +configuration comb_divider_rtl_cfg of comb_divider is + + for rtl + + end for; + +end comb_divider_rtl_cfg; diff --git a/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/8051/comb_mltplr_.vhd b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/8051/comb_mltplr_.vhd new file mode 100644 index 0000000000000000000000000000000000000000..d0c620c45a6bc249c21ab9dc092c4e016af5ecaf --- /dev/null +++ b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/8051/comb_mltplr_.vhd @@ -0,0 +1,81 @@ +------------------------------------------------------------------------------- +-- -- +-- X X XXXXXX XXXXXX XXXXXX XXXXXX X -- +-- XX XX X X X X X X X XX -- +-- X X X X X X X X X X X X -- +-- X X X X X X X X X X X X -- +-- X X X X XXXXXX X X XXXXXX X -- +-- X X X X X X X X X -- +-- X X X X X X X X X -- +-- X X X X X X X X X X -- +-- X X XXXXXX XXXXXX XXXXXX XXXXXX X -- +-- -- +-- -- +-- O R E G A N O S Y S T E M S -- +-- -- +-- Design & Consulting -- +-- -- +------------------------------------------------------------------------------- +-- -- +-- Web: http://www.oregano.at/ -- +-- -- +-- Contact: mc8051@oregano.at -- +-- -- +------------------------------------------------------------------------------- +-- -- +-- MC8051 - VHDL 8051 Microcontroller IP Core -- +-- Copyright (C) 2001 OREGANO SYSTEMS -- +-- -- +-- This library is free software; you can redistribute it and/or -- +-- modify it under the terms of the GNU Lesser General Public -- +-- License as published by the Free Software Foundation; either -- +-- version 2.1 of the License, or (at your option) any later version. -- +-- -- +-- This library is distributed in the hope that it will be useful, -- +-- but WITHOUT ANY WARRANTY; without even the implied warranty of -- +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -- +-- Lesser General Public License for more details. -- +-- -- +-- Full details of the license can be found in the file LGPL.TXT. -- +-- -- +-- You should have received a copy of the GNU Lesser General Public -- +-- License along with this library; if not, write to the Free Software -- +-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -- +-- -- +------------------------------------------------------------------------------- +-- +-- +-- Author: Roland Hller +-- +-- Filename: comb_mltplr_.vhd +-- +-- Date of Creation: Mon Aug 9 12:14:48 1999 +-- +-- Version: $Revision: 1.4 $ +-- +-- Date of Latest Version: $Date: 2002-01-07 12:17:44 $ +-- +-- +-- Description: Multiplier with parameteriseable data width. Realised +-- using combinational logic only. +-- +-- +-- +-- +------------------------------------------------------------------------------- +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.std_logic_arith.all; + +-----------------------------ENTITY DECLARATION-------------------------------- + +entity comb_mltplr is + + generic (DWIDTH : integer := 8); + + port (mltplcnd_i : in std_logic_vector(DWIDTH-1 downto 0); -- Multiplicand + mltplctr_i : in std_logic_vector(DWIDTH-1 downto 0); -- Multiplicator + product_o : out std_logic_vector((DWIDTH*2)-1 downto 0)); -- Product + +end comb_mltplr; + diff --git a/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/8051/comb_mltplr_rtl.vhd b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/8051/comb_mltplr_rtl.vhd new file mode 100644 index 0000000000000000000000000000000000000000..8e7e52677c31e63b12db67de9e7538f7541f1e65 --- /dev/null +++ b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/8051/comb_mltplr_rtl.vhd @@ -0,0 +1,88 @@ +------------------------------------------------------------------------------- +-- -- +-- X X XXXXXX XXXXXX XXXXXX XXXXXX X -- +-- XX XX X X X X X X X XX -- +-- X X X X X X X X X X X X -- +-- X X X X X X X X X X X X -- +-- X X X X XXXXXX X X XXXXXX X -- +-- X X X X X X X X X -- +-- X X X X X X X X X -- +-- X X X X X X X X X X -- +-- X X XXXXXX XXXXXX XXXXXX XXXXXX X -- +-- -- +-- -- +-- O R E G A N O S Y S T E M S -- +-- -- +-- Design & Consulting -- +-- -- +------------------------------------------------------------------------------- +-- -- +-- Web: http://www.oregano.at/ -- +-- -- +-- Contact: mc8051@oregano.at -- +-- -- +------------------------------------------------------------------------------- +-- -- +-- MC8051 - VHDL 8051 Microcontroller IP Core -- +-- Copyright (C) 2001 OREGANO SYSTEMS -- +-- -- +-- This library is free software; you can redistribute it and/or -- +-- modify it under the terms of the GNU Lesser General Public -- +-- License as published by the Free Software Foundation; either -- +-- version 2.1 of the License, or (at your option) any later version. -- +-- -- +-- This library is distributed in the hope that it will be useful, -- +-- but WITHOUT ANY WARRANTY; without even the implied warranty of -- +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -- +-- Lesser General Public License for more details. -- +-- -- +-- Full details of the license can be found in the file LGPL.TXT. -- +-- -- +-- You should have received a copy of the GNU Lesser General Public -- +-- License along with this library; if not, write to the Free Software -- +-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -- +-- -- +------------------------------------------------------------------------------- +-- +-- +-- Author: Roland Hller +-- +-- Filename: comb_mltplr_rtl.vhd +-- +-- Date of Creation: Mon Aug 9 12:14:48 1999 +-- +-- Version: $Revision: 1.4 $ +-- +-- Date of Latest Version: $Date: 2002-01-07 12:17:44 $ +-- +-- +-- Description: Multiplier with parameteriseable data width. Realised +-- using combinational logic only. +-- +-- +-- +-- +------------------------------------------------------------------------------- +architecture rtl of comb_mltplr is + +begin -- rtl + + -- purpose: Multiply the multiplicand with the multiplicator. + -- type : combinational + -- inputs : dvdnd_i, dvsor_i + -- outputs: product_o + p_mltply: process (mltplctr_i, mltplcnd_i) + + variable v_product : unsigned(DWIDTH*2-1 downto 0); + + begin -- process p_divide + + v_product := conv_unsigned(unsigned(mltplctr_i) + * unsigned(mltplcnd_i),DWIDTH*2); + product_o <= std_logic_vector(v_product); + + end process p_mltply; + +end rtl; + + diff --git a/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/8051/comb_mltplr_rtl_cfg.vhd b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/8051/comb_mltplr_rtl_cfg.vhd new file mode 100644 index 0000000000000000000000000000000000000000..3878fc28c756d8f6abd9d76a3bcb6206bb300552 --- /dev/null +++ b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/8051/comb_mltplr_rtl_cfg.vhd @@ -0,0 +1,72 @@ +------------------------------------------------------------------------------- +-- -- +-- X X XXXXXX XXXXXX XXXXXX XXXXXX X -- +-- XX XX X X X X X X X XX -- +-- X X X X X X X X X X X X -- +-- X X X X X X X X X X X X -- +-- X X X X XXXXXX X X XXXXXX X -- +-- X X X X X X X X X -- +-- X X X X X X X X X -- +-- X X X X X X X X X X -- +-- X X XXXXXX XXXXXX XXXXXX XXXXXX X -- +-- -- +-- -- +-- O R E G A N O S Y S T E M S -- +-- -- +-- Design & Consulting -- +-- -- +------------------------------------------------------------------------------- +-- -- +-- Web: http://www.oregano.at/ -- +-- -- +-- Contact: mc8051@oregano.at -- +-- -- +------------------------------------------------------------------------------- +-- -- +-- MC8051 - VHDL 8051 Microcontroller IP Core -- +-- Copyright (C) 2001 OREGANO SYSTEMS -- +-- -- +-- This library is free software; you can redistribute it and/or -- +-- modify it under the terms of the GNU Lesser General Public -- +-- License as published by the Free Software Foundation; either -- +-- version 2.1 of the License, or (at your option) any later version. -- +-- -- +-- This library is distributed in the hope that it will be useful, -- +-- but WITHOUT ANY WARRANTY; without even the implied warranty of -- +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -- +-- Lesser General Public License for more details. -- +-- -- +-- Full details of the license can be found in the file LGPL.TXT. -- +-- -- +-- You should have received a copy of the GNU Lesser General Public -- +-- License along with this library; if not, write to the Free Software -- +-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -- +-- -- +------------------------------------------------------------------------------- +-- +-- +-- Author: Roland Hller +-- +-- Filename: comb_mltplr_rtl_cfg.vhd +-- +-- Date of Creation: Mon Aug 9 12:14:48 1999 +-- +-- Version: $Revision: 1.4 $ +-- +-- Date of Latest Version: $Date: 2002-01-07 12:17:44 $ +-- +-- +-- Description: Multiplier with parameteriseable data width. Realised +-- using combinational logic only. +-- +-- +-- +-- +------------------------------------------------------------------------------- +configuration comb_mltplr_rtl_cfg of comb_mltplr is + + for rtl + + end for; + +end comb_mltplr_rtl_cfg; diff --git a/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/8051/control_fsm_.vhd b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/8051/control_fsm_.vhd new file mode 100644 index 0000000000000000000000000000000000000000..5afac977b77791650c3d2e8a81870a80308ef3b7 --- /dev/null +++ b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/8051/control_fsm_.vhd @@ -0,0 +1,124 @@ +------------------------------------------------------------------------------- +-- -- +-- X X XXXXXX XXXXXX XXXXXX XXXXXX X -- +-- XX XX X X X X X X X XX -- +-- X X X X X X X X X X X X -- +-- X X X X X X X X X X X X -- +-- X X X X XXXXXX X X XXXXXX X -- +-- X X X X X X X X X -- +-- X X X X X X X X X -- +-- X X X X X X X X X X -- +-- X X XXXXXX XXXXXX XXXXXX XXXXXX X -- +-- -- +-- -- +-- O R E G A N O S Y S T E M S -- +-- -- +-- Design & Consulting -- +-- -- +------------------------------------------------------------------------------- +-- -- +-- Web: http://www.oregano.at/ -- +-- -- +-- Contact: mc8051@oregano.at -- +-- -- +------------------------------------------------------------------------------- +-- -- +-- MC8051 - VHDL 8051 Microcontroller IP Core -- +-- Copyright (C) 2001 OREGANO SYSTEMS -- +-- -- +-- This library is free software; you can redistribute it and/or -- +-- modify it under the terms of the GNU Lesser General Public -- +-- License as published by the Free Software Foundation; either -- +-- version 2.1 of the License, or (at your option) any later version. -- +-- -- +-- This library is distributed in the hope that it will be useful, -- +-- but WITHOUT ANY WARRANTY; without even the implied warranty of -- +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -- +-- Lesser General Public License for more details. -- +-- -- +-- Full details of the license can be found in the file LGPL.TXT. -- +-- -- +-- You should have received a copy of the GNU Lesser General Public -- +-- License along with this library; if not, write to the Free Software -- +-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -- +-- -- +------------------------------------------------------------------------------- +-- +-- +-- Author: Helmut Mayrhofer +-- +-- Filename: control_fsm_.vhd +-- +-- Date of Creation: Mon Aug 9 12:14:48 1999 +-- +-- Version: $Revision: 1.6 $ +-- +-- Date of Latest Version: $Date: 2006-09-07 09:57:24 $ +-- +-- +-- Description: Decode instruction and execute it. Pure combinational +-- descripton of the finite state machine. +-- +-- +-- +-- +------------------------------------------------------------------------------- +library IEEE; +library work; +use IEEE.std_logic_1164.all; +use IEEE.std_logic_arith.all; +use work.mc8051_p.all; + + +------------------------ ENTITY DECLARATION ------------------------- +entity control_fsm is + + port (state_i : in t_state; -- actual state + help_i : in std_logic_vector (7 downto 0); -- general help-reg + bit_data_i : in std_logic; -- bitdata from regs + aludata_i : in std_logic_vector (7 downto 0); -- ALU result + command_i : in std_logic_vector (7 downto 0); -- actual command + inthigh_i : in std_logic; -- high priority int is running + intlow_i : in std_logic; -- low priority int is running + intpre_i : in std_logic; -- an interrupt must start + intpre2_i : in std_logic; -- prepare for interrupt + intblock_i : in std_logic; -- interrupt delay at RETI, IE, IP + ti_i : in std_logic; + ri_i : in std_logic; + ie0_i : in std_logic; + ie1_i : in std_logic; + tf0_i : in std_logic; + tf1_i : in std_logic; + acc : in std_logic_vector(7 downto 0); + psw : in std_logic_vector(7 downto 0); + ie : in std_logic_vector(7 downto 0); + ip : in std_logic_vector(7 downto 0); + + alu_cmd_o : out std_logic_vector (5 downto 0); -- ALU code + pc_inc_en_o : out std_logic_vector (3 downto 0); + nextstate_o : out t_state; -- enable signal for state + adr_mux_o : out std_logic_vector (3 downto 0); + adrx_mux_o : out std_logic_vector (1 downto 0); + wrx_mux_o : out std_logic; + data_mux_o : out std_logic_vector (3 downto 0); + bdata_mux_o : out std_logic_vector (3 downto 0); + regs_wr_en_o : out std_logic_vector (2 downto 0); + help_en_o : out std_logic_vector (3 downto 0); + help16_en_o : out std_logic_vector (1 downto 0); + helpb_en_o : out std_logic; + inthigh_en_o : out std_logic; + intlow_en_o : out std_logic; + intpre2_en_o : out std_logic; + inthigh_d_o : out std_logic; + intlow_d_o : out std_logic; + intpre2_d_o : out std_logic; + ext0isr_d_o : out std_logic; + ext1isr_d_o : out std_logic; + ext0isrh_d_o : out std_logic; + ext1isrh_d_o : out std_logic; + ext0isr_en_o : out std_logic; + ext1isr_en_o : out std_logic; + ext0isrh_en_o : out std_logic; + ext1isrh_en_o : out std_logic); + +end control_fsm; diff --git a/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/8051/control_fsm_rtl.vhd b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/8051/control_fsm_rtl.vhd new file mode 100644 index 0000000000000000000000000000000000000000..698d30bb109e8dc491d6c1819b6abb509d8ae056 --- /dev/null +++ b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/8051/control_fsm_rtl.vhd @@ -0,0 +1,2171 @@ +------------------------------------------------------------------------------- +-- -- +-- X X XXXXXX XXXXXX XXXXXX XXXXXX X -- +-- XX XX X X X X X X X XX -- +-- X X X X X X X X X X X X -- +-- X X X X X X X X X X X X -- +-- X X X X XXXXXX X X XXXXXX X -- +-- X X X X X X X X X -- +-- X X X X X X X X X -- +-- X X X X X X X X X X -- +-- X X XXXXXX XXXXXX XXXXXX XXXXXX X -- +-- -- +-- -- +-- O R E G A N O S Y S T E M S -- +-- -- +-- Design & Consulting -- +-- -- +------------------------------------------------------------------------------- +-- -- +-- Web: http://www.oregano.at/ -- +-- -- +-- Contact: mc8051@oregano.at -- +-- -- +------------------------------------------------------------------------------- +-- -- +-- MC8051 - VHDL 8051 Microcontroller IP Core -- +-- Copyright (C) 2001 OREGANO SYSTEMS -- +-- -- +-- This library is free software; you can redistribute it and/or -- +-- modify it under the terms of the GNU Lesser General Public -- +-- License as published by the Free Software Foundation; either -- +-- version 2.1 of the License, or (at your option) any later version. -- +-- -- +-- This library is distributed in the hope that it will be useful, -- +-- but WITHOUT ANY WARRANTY; without even the implied warranty of -- +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -- +-- Lesser General Public License for more details. -- +-- -- +-- Full details of the license can be found in the file LGPL.TXT. -- +-- -- +-- You should have received a copy of the GNU Lesser General Public -- +-- License along with this library; if not, write to the Free Software -- +-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -- +-- -- +------------------------------------------------------------------------------- +-- +-- +-- Author: Helmut Mayrhofer +-- +-- Filename: control_fsm_rtl.vhd +-- +-- Date of Creation: Mon Aug 9 12:14:48 1999 +-- +-- Version: $Revision: 1.10 $ +-- +-- Date of Latest Version: $Date: 2010-03-24 10:20:48 $ +-- +-- +-- Description: Decode instruction and execute it. Pure combinational +-- descripton of the finite state machine. +-- +-- +-- +-- +------------------------------------------------------------------------------- +architecture rtl of control_fsm is + + alias CY : std_logic is psw(7); -- carry + alias AC : std_logic is psw(6); -- auxilary carry + alias OV : std_logic is psw(2); -- overflow flag + alias EA: std_logic is ie(7); -- enable interupts + alias ES: std_logic is ie(4); -- enable serial interupt + alias ET1: std_logic is ie(3); -- enable timer 1 interupt + alias EX1: std_logic is ie(2); -- enable external 1 interupt + alias ET0: std_logic is ie(1); -- enable timer 0 interupt + alias EX0: std_logic is ie(0); -- enable external 0 interupt + alias PS0: std_logic is ip(4); -- priority of serial interupt + alias PT1: std_logic is ip(3); -- priority of timer1 interupt + alias PX1: std_logic is ip(2); -- priority of ext1 interupt + alias PT0: std_logic is ip(1); -- priority of timer0 interupt + alias PX0: std_logic is ip(0); -- priority of ext0 interupt + + signal state: t_state; -- actual state + signal s_nextstate: t_state; -- enable signal for state + signal s_instr_category : t_instr_category; -- predecoded insturction + + signal s_help: unsigned (7 downto 0); -- general help-register + + signal s_bit_data : std_logic; -- bitdata from MUX + signal s_intpre: std_logic; -- an interrupt must start + signal s_intpre2: std_logic; -- prepare for interrupt + signal s_inthigh: std_logic; -- high priority int is running + signal s_intlow: std_logic; -- low priority int is running + + signal s_tf1 : std_logic; -- Timer1-Overflowflag + signal s_tf0 : std_logic; -- Timer0-Overflowflag + signal s_ie1 : std_logic; -- ExtINT1-Flag + signal s_ie0 : std_logic; -- ExtINT0-Flag + + signal s_ri : std_logic; -- serial receive-ready + signal s_ti : std_logic; -- serial transmit-ready + + signal s_command: std_logic_vector (7 downto 0); -- actual command + + signal s_pc_inc_en : std_logic_vector (3 downto 0); -- pc control + signal s_regs_wr_en : std_logic_vector (2 downto 0); -- write control + signal s_data_mux : std_logic_vector (3 downto 0); -- data control + signal s_bdata_mux : std_logic_vector (3 downto 0); -- bitdata control + signal s_adr_mux : std_logic_vector (3 downto 0); -- adress control + signal s_adrx_mux : std_logic_vector (1 downto 0); -- ext. adress control + signal s_wrx_mux : std_logic; -- ext. write control + signal s_help_en : std_logic_vector (3 downto 0); -- helpreg control + signal s_help16_en : std_logic_vector (1 downto 0); -- help16 control + signal s_helpb_en : std_logic; -- helpbit control + signal s_intpre2_d : std_logic; -- intput of intpre2 + signal s_intpre2_en : std_logic; -- control + signal s_intlow_d : std_logic; -- input of intlow + signal s_intlow_en : std_logic; -- control + signal s_inthigh_d : std_logic; -- input of inthigh + signal s_inthigh_en : std_logic; -- control + signal s_ext0isr_d : std_logic; -- ext int 0 ISR running if set + signal s_ext1isr_d : std_logic; -- ext int 1 ISR running if set + signal s_ext0isrh_d : std_logic; -- ext int 0 ISR has high priority if 1 + signal s_ext1isrh_d : std_logic; -- ext int 1 ISR has high priority if 1 + signal s_ext0isr_en : std_logic; + signal s_ext1isr_en : std_logic; + signal s_ext0isrh_en : std_logic; + signal s_ext1isrh_en : std_logic; + +begin + + -- some simple signal-assignments for outputs + + pc_inc_en_o <= s_pc_inc_en; + nextstate_o <= s_nextstate; + adr_mux_o <= s_adr_mux; + adrx_mux_o <= s_adrx_mux; + wrx_mux_o <= s_wrx_mux; + data_mux_o <= s_data_mux; + bdata_mux_o <= s_bdata_mux; + regs_wr_en_o <= s_regs_wr_en; + help_en_o <= s_help_en; + help16_en_o <= s_help16_en; + helpb_en_o <= s_helpb_en; + inthigh_en_o <= s_inthigh_en; + intlow_en_o <= s_intlow_en; + intpre2_en_o <= s_intpre2_en; + inthigh_d_o <= s_inthigh_d; + intlow_d_o <= s_intlow_d; + intpre2_d_o <= s_intpre2_d; + ext0isr_d_o <= s_ext0isr_d; + ext1isr_d_o <= s_ext1isr_d; + ext0isrh_d_o <= s_ext0isrh_d; + ext1isrh_d_o <= s_ext1isrh_d; + ext0isr_en_o <= s_ext0isr_en; + ext1isr_en_o <= s_ext1isr_en; + ext0isrh_en_o <= s_ext0isrh_en; + ext1isrh_en_o <= s_ext1isrh_en; + + -- some simple signal assignments from intputs + + state <= state_i; + s_help <= unsigned(help_i); + s_bit_data <= bit_data_i; + s_command <= command_i; + s_inthigh <= inthigh_i; + s_intlow <= intlow_i; + s_intpre <= intpre_i; + s_intpre2 <= intpre2_i; + s_ti <= ti_i; + s_ri <= ri_i; + s_ie0 <= ie0_i; + s_ie1 <= ie1_i; + s_tf0 <= tf0_i; + s_tf1 <= tf1_i; + + -- predecode instruction + s_instr_category <= + IC_ACALL when s_command(4 downto 0) = ACALL else + IC_ADD_A_RR when s_command(7 downto 3) = ADD_A_RR else + IC_ADD_A_D when s_command = ADD_A_D else + IC_ADD_A_ATRI when s_command(7 downto 1) = ADD_A_ATRI else + IC_ADD_A_DATA when s_command = ADD_A_DATA else + IC_ADDC_A_RR when s_command(7 downto 3) = ADDC_A_RR else + IC_ADDC_A_D when s_command = ADDC_A_D else + IC_ADDC_A_ATRI when s_command(7 downto 1) = ADDC_A_ATRI else + IC_ADDC_A_DATA when s_command = ADDC_A_DATA else + IC_AJMP when s_command(4 downto 0) = AJMP else + IC_ANL_A_RR when s_command(7 downto 3) = ANL_A_RR else + IC_ANL_A_D when s_command = ANL_A_D else + IC_ANL_A_ATRI when s_command(7 downto 1) = ANL_A_ATRI else + IC_ANL_A_DATA when s_command = ANL_A_DATA else + IC_ANL_D_A when s_command = ANL_D_A else + IC_ANL_D_DATA when s_command = ANL_D_DATA else + IC_ANL_C_BIT when s_command = ANL_C_BIT else + IC_ANL_C_NBIT when s_command = ANL_C_NBIT else + IC_CJNE_A_D when s_command = CJNE_A_D else + IC_CJNE_A_DATA when s_command = CJNE_A_DATA else + IC_CJNE_RR_DATA when s_command(7 downto 3) = CJNE_RR_DATA else + IC_CJNE_ATRI_DATA when s_command(7 downto 1) = CJNE_ATRI_DATA else + IC_CLR_A when s_command = CLR_A else + IC_CLR_C when s_command = CLR_C else + IC_CLR_BIT when s_command = CLR_BIT else + IC_CPL_A when s_command = CPL_A else + IC_CPL_C when s_command = CPL_C else + IC_CPL_BIT when s_command = CPL_BIT else + IC_DA_A when s_command = DA_A else + IC_DEC_A when s_command = DEC_A else + IC_DEC_RR when s_command(7 downto 3) = DEC_RR else + IC_DEC_D when s_command = DEC_D else + IC_DEC_ATRI when s_command(7 downto 1) = DEC_ATRI else + IC_DIV_AB when s_command = DIV_AB else + IC_DJNZ_RR when s_command(7 downto 3) = DJNZ_RR else + IC_DJNZ_D when s_command = DJNZ_D else + IC_INC_A when s_command = INC_A else + IC_INC_RR when s_command(7 downto 3) = INC_RR else + IC_INC_D when s_command = INC_D else + IC_INC_ATRI when s_command(7 downto 1) = INC_ATRI else + IC_INC_DPTR when s_command = INC_DPTR else + IC_JB when s_command = JB else + IC_JBC when s_command = JBC else + IC_JC when s_command = JC else + IC_JMP_A_DPTR when s_command = JMP_A_DPTR else + IC_JNB when s_command = JNB else + IC_JNC when s_command = JNC else + IC_JNZ when s_command = JNZ else + IC_JZ when s_command = JZ else + IC_LCALL when s_command = LCALL else + IC_LJMP when s_command = LJMP else + IC_MOV_A_RR when s_command(7 downto 3) = MOV_A_RR else + IC_MOV_A_D when s_command = MOV_A_D else + IC_MOV_A_ATRI when s_command(7 downto 1) = MOV_A_ATRI else + IC_MOV_A_DATA when s_command = MOV_A_DATA else + IC_MOV_RR_A when s_command(7 downto 3) = MOV_RR_A else + IC_MOV_RR_D when s_command(7 downto 3) = MOV_RR_D else + IC_MOV_RR_DATA when s_command(7 downto 3) = MOV_RR_DATA else + IC_MOV_D_A when s_command = MOV_D_A else + IC_MOV_D_RR when s_command(7 downto 3) = MOV_D_RR else + IC_MOV_D_D when s_command = MOV_D_D else + IC_MOV_D_ATRI when s_command(7 downto 1) = MOV_D_ATRI else + IC_MOV_D_DATA when s_command = MOV_D_DATA else + IC_MOV_ATRI_A when s_command(7 downto 1) = MOV_ATRI_A else + IC_MOV_ATRI_D when s_command(7 downto 1) = MOV_ATRI_D else + IC_MOV_ATRI_DATA when s_command(7 downto 1) = MOV_ATRI_DATA else + IC_MOVC_A_ATDPTR when s_command = MOVC_A_ATDPTR else + IC_MOVC_A_ATPC when s_command = MOVC_A_ATPC else + IC_MOVX_A_ATRI when s_command(7 downto 1) = MOVX_A_ATRI else + IC_MOVX_A_ATDPTR when s_command = MOVX_A_ATDPTR else + IC_MOVX_ATRI_A when s_command(7 downto 1) = MOVX_ATRI_A else + IC_MOVX_ATDPTR_A when s_command = MOVX_ATDPTR_A else + IC_MOV_C_BIT when s_command = MOV_C_BIT else + IC_MOV_BIT_C when s_command = MOV_BIT_C else + IC_MOV_DPTR_DATA when s_command = MOV_DPTR_DATA else + IC_MUL_AB when s_command = MUL_AB else + IC_NOP when s_command = NOP else + IC_ORL_A_RR when s_command(7 downto 3) = ORL_A_RR else + IC_ORL_A_D when s_command = ORL_A_D else + IC_ORL_A_ATRI when s_command(7 downto 1) = ORL_A_ATRI else + IC_ORL_A_DATA when s_command = ORL_A_DATA else + IC_ORL_D_A when s_command = ORL_D_A else + IC_ORL_D_DATA when s_command = ORL_D_DATA else + IC_ORL_C_BIT when s_command = ORL_C_BIT else + IC_ORL_C_NBIT when s_command = ORL_C_NBIT else + IC_POP when s_command = POP else + IC_PUSH when s_command = PUSH else + IC_RET when s_command = RET else + IC_RETI when s_command = RETI else + IC_RL_A when s_command = RL_A else + IC_RLC_A when s_command = RLC_A else + IC_RR_A when s_command = RR_A else + IC_RRC_A when s_command = RRC_A else + IC_SETB_C when s_command = SETB_C else + IC_SETB_BIT when s_command = SETB_BIT else + IC_SJMP when s_command = SJMP else + IC_SUBB_A_RR when s_command(7 downto 3) = SUBB_A_RR else + IC_SUBB_A_D when s_command = SUBB_A_D else + IC_SUBB_A_ATRI when s_command(7 downto 1) = SUBB_A_ATRI else + IC_SUBB_A_DATA when s_command = SUBB_A_DATA else + IC_SWAP_A when s_command = SWAP_A else + IC_XCH_A_RR when s_command(7 downto 3) = XCH_A_RR else + IC_XCH_A_D when s_command = XCH_A_D else + IC_XCH_A_ATRI when s_command(7 downto 1) = XCH_A_ATRI else + IC_XCHD_A_ATRI when s_command(7 downto 1) = XCHD_A_ATRI else + IC_XRL_A_RR when s_command(7 downto 3) = XRL_A_RR else + IC_XRL_A_D when s_command = XRL_A_D else + IC_XRL_A_ATRI when s_command(7 downto 1) = XRL_A_ATRI else + IC_XRL_A_DATA when s_command = XRL_A_DATA else + IC_XRL_D_A when s_command = XRL_D_A else + IC_XRL_D_DATA when s_command = XRL_D_DATA else + IC_NOP; + +------------------------------------------------------------------------------ +-- purpose: main-process to control the mcu +-- includes the interupt-handling and the state machine +-- inputs: state,s_help,s_ti,s_ri,s_ie0,s_ie1,s_tf0,s_tf1, +-- s_bit_data,aludata_i,s_command,s_inthigh, +-- s_intlow,acc,psw,s_intpre,s_intpre2,ie,ip +-- outputs: pc_inc_en_o,s_nextstate_o,adr_mux_o,data_mux_o,bdata_mux_o +-- regs_wr_en_o,help_en_o,help16_en_o,helpb_en_o,inthigh_en_o +-- intlow_en_o,intpre2_en_o,inthigh_d_o,intlow_d_o,intpre2_d_o +------------------------------------------------------------------------------ + + p_state: process (state,s_help,s_ti,s_ri,s_ie0,s_ie1,s_tf0,s_tf1, + s_bit_data,aludata_i,s_instr_category,s_inthigh, + s_intlow,acc,psw,s_intpre,s_intpre2,ie,ip,intblock_i) + begin + s_data_mux <= "0000"; -- default values + s_adr_mux <= "0000"; + s_bdata_mux <= "0000"; + alu_cmd_o <= OFF; + s_regs_wr_en <= "000"; + s_help_en <= "0000"; + s_help16_en <= "00"; + s_helpb_en <= '0'; + s_pc_inc_en <= "0000"; + s_inthigh_en <= '0'; + s_intlow_en <= '0'; + s_intpre2_en <= '0'; + s_inthigh_d <= '0'; + s_intlow_d <= '0'; + s_intpre2_d <= '0'; + s_adrx_mux <= "00"; + s_wrx_mux <= '0'; + s_nextstate <= FETCH; + s_ext0isr_d <= '0'; + s_ext1isr_d <= '0'; + s_ext0isrh_d <= '0'; + s_ext1isrh_d <= '0'; + s_ext0isr_en <= '0'; + s_ext1isr_en <= '0'; + s_ext0isrh_en <= '0'; + s_ext1isrh_en <= '0'; + + if state=STARTUP then + -- Power up wait cycle + NULL; + else + -- begin of starting the interrupt procedure + -- saving the old adress + if intblock_i = '0' and s_instr_category /= IC_RETI and -- fixes bug when + -- a higher priority interrupt occurred during the RETI of a lower priority one + -- by wickerwaka https://github.com/MiSTer-devel/Arcade-IremM72_MiSTer/commit/2218dc0 + ((s_intpre='1' and state=FETCH) or s_intpre2='1') then + if state=FETCH then + s_intpre2_en <= '1'; + s_intpre2_d <= '1'; + s_regs_wr_en <= "001"; -- increment stackpointer + s_nextstate <= EXEC1; + elsif state=EXEC1 then + if (PX0 and EX0 and s_ie0)='1' then -- external interrupt 0 + s_help_en <= "0101"; -- interruptvector 0003h + s_inthigh_d <= '1'; + s_inthigh_en <= '1'; + s_adr_mux <= "0001"; + s_regs_wr_en <= "110"; -- reset IE0 + s_ext0isrh_d <= '1'; + s_ext0isrh_en <= '1'; + elsif (PT0 and ET0 and s_tf0)='1' then -- timer interrupt 0 + s_help_en <= "0110"; -- interruptvector 000Bh + s_inthigh_d <= '1'; + s_inthigh_en <= '1'; + s_adr_mux <= "0010"; + s_regs_wr_en <= "110"; -- reset TF0 + elsif (PX1 and EX1 and s_ie1)='1' then -- external interrupt 1 + s_help_en <= "0111"; -- interruptvector 0013h + s_inthigh_d <= '1'; + s_inthigh_en <= '1'; + s_adr_mux <= "0011"; + s_regs_wr_en <= "110"; -- reset IE1 + s_ext1isrh_d <= '1'; + s_ext1isrh_en <= '1'; + elsif (PT1 and ET1 and s_tf1)='1' then -- timer interrupt 1 + s_help_en <= "1000"; -- interruptvector 001Bh + s_inthigh_d <= '1'; + s_inthigh_en <= '1'; + s_adr_mux <= "0100"; + s_regs_wr_en <= "110"; -- reset TF1 + elsif (PS0 and ES and (s_ri or s_ti))='1' then -- serial interrupt 0 + s_help_en <= "1001"; -- interruptvector 0023h + s_inthigh_d <= '1'; + s_inthigh_en <= '1'; + elsif (EX0 and s_ie0)='1' then -- external interrupt 0 low priority + s_help_en <= "0101"; -- interruptvector 0003h + s_intlow_d <= '1'; + s_intlow_en <= '1'; + s_adr_mux <= "0001"; + s_regs_wr_en <= "110"; -- reset IE0 + s_ext0isr_d <= '1'; + s_ext0isr_en <= '1'; + elsif (ET0 and s_tf0)='1' then -- timer interrupt 0 low priority + s_help_en <= "0110"; -- interruptvector 000Bh + s_intlow_d <= '1'; + s_intlow_en <= '1'; + s_adr_mux <= "0010"; + s_regs_wr_en <= "110"; -- reset TF0 + elsif (EX1 and s_ie1)='1' then -- external interrupt 1 low priority + s_help_en <= "0111"; -- interruptvector 0013h + s_intlow_d <= '1'; + s_intlow_en <= '1'; + s_adr_mux <= "0011"; + s_regs_wr_en <= "110"; -- reset IE1 + s_ext1isr_d <= '1'; + s_ext1isr_en <= '1'; + elsif (ET1 and s_tf1)='1' then -- timer interrupt 1 low priority + s_help_en <= "1000"; -- interruptvector 001Bh + s_intlow_d <= '1'; + s_intlow_en <= '1'; + s_adr_mux <= "0100"; + s_regs_wr_en <= "110"; -- reset TF1 + elsif (ES and (s_ri or s_ti))='1' then -- serial int 0 low priority + s_help_en <= "1001"; -- interruptvector 0023h + s_intlow_d <= '1'; + s_intlow_en <= '1'; + else + NULL; + end if; + s_nextstate <= EXEC2; + elsif state=EXEC2 then + s_adr_mux <= "0101"; + s_data_mux <= "0001"; -- data = pc(7 downto 0) + s_regs_wr_en <= "101"; -- write one byte and increment SP + s_nextstate <= EXEC3; + elsif state=EXEC3 then + s_intpre2_d <= '0'; + s_intpre2_en <= '1'; + s_adr_mux <= "0101"; + s_data_mux <= "0010"; -- data = pc(15 downto 8) + s_regs_wr_en <= "100"; -- write one byte + s_pc_inc_en <= "0011"; -- load program counter + s_nextstate <= FETCH; + else + s_nextstate <= FETCH; + end if; + + -- end of starting interrupt procedure + + else + + case s_instr_category is + + --------------------------------------------------------------------- + + when IC_ACALL => -- ACALL addr11 + if state=FETCH then + s_adr_mux <= "1111"; -- adress = sp + 1 + s_data_mux <= "1110"; -- data = (pc+2)(7 downto 0) + s_regs_wr_en <= "101"; -- write one byte and increment SP + s_help16_en <= "10"; -- s_help16 = pc+2 + s_pc_inc_en <= "0001"; -- increment program-counter + s_nextstate <= EXEC1; + elsif state=EXEC1 then + s_adr_mux <= "1111"; -- adress = sp + 1 + s_data_mux <= "1101"; -- data = s_help16(15 downto 8) + s_regs_wr_en <= "101"; -- write one byte and increment SP + s_pc_inc_en <= "0100"; -- load PC with 11 bits (2k block) + s_nextstate <= FETCH; + end if; + + --------------------------------------------------------------------- + + when IC_ADD_A_RR => -- ADD A,Rr + if state=FETCH then + s_adr_mux <= "0110"; -- adress = RR-adress + s_nextstate <= EXEC1; + elsif state=EXEC1 then + alu_cmd_o <= ADD_ACC_RAM; -- addition command (ACC + RAM_DATA) + s_data_mux <= "0011"; -- data = aludata_i + s_regs_wr_en <= "011"; -- write ACC and CY,OV,AC + s_pc_inc_en <= "0001"; -- increment program-counter + s_nextstate <= FETCH; + end if; + + --------------------------------------------------------------------- + + when IC_ADD_A_D => -- ADD A, direct + if state=FETCH then + s_pc_inc_en <= "0001"; -- increment program-counter + s_nextstate <= EXEC1; + elsif state=EXEC1 then + s_adr_mux <= "1000"; -- adress = rom_data_i + s_nextstate <= EXEC2; + elsif state=EXEC2 then + alu_cmd_o <= ADD_ACC_RAM; -- addition command (ACC + RAM_DATA) + s_data_mux <= "0011"; -- data = aludata_i + s_regs_wr_en <= "011"; -- write ACC and CY,OV,AC + s_pc_inc_en <= "0001"; -- increment program-counter + s_nextstate <= FETCH; + end if; + + --------------------------------------------------------------------- + + when IC_ADD_A_ATRI => -- ADD A,@Ri + if state=FETCH then + s_adr_mux <= "0111"; -- address = Ri-register + s_nextstate <= EXEC1; + elsif state=EXEC1 then + alu_cmd_o <= ADD_ACC_RAM; -- addition command (ACC + RAM_DATA) + s_data_mux <= "0011"; -- data = aludata_i + s_regs_wr_en <= "011"; -- write ACC and CY,OV,AC + s_pc_inc_en <= "0001"; -- increment program-counter + s_nextstate <= FETCH; + end if; + + --------------------------------------------------------------------- + + when IC_ADD_A_DATA => -- ADD A, DATA + if state=FETCH then + s_pc_inc_en <= "0001"; -- increment program-counter + s_nextstate <= EXEC1; + elsif state=EXEC1 then + alu_cmd_o <= ADD_ACC_ROM; -- addition command (ACC + ROM_DATA_I) + s_data_mux <= "0011"; -- data = aludata_i + s_regs_wr_en <= "011"; -- write ACC and CY,OV,AC + s_pc_inc_en <= "0001"; -- increment program-counter + s_nextstate <= FETCH; + end if; + + --------------------------------------------------------------------- + + when IC_ADDC_A_RR => -- ADDC A,Rr + if state=FETCH then + s_adr_mux <= "0110"; -- adress = RR-adress + s_nextstate <= EXEC1; + elsif state=EXEC1 then + alu_cmd_o <= ADDC_ACC_RAM; -- addition command (ACC+RAM_DATA+CY) + s_data_mux <= "0011"; -- data = aludata_i + s_regs_wr_en <= "011"; -- write ACC and CY,OV,AC + s_pc_inc_en <= "0001"; -- increment program-counter + s_nextstate <= FETCH; + end if; + + --------------------------------------------------------------------- + + when IC_ADDC_A_D => -- ADDC A, direct + if state=FETCH then + s_pc_inc_en <= "0001"; -- increment program-counter + s_nextstate <= EXEC1; + elsif state=EXEC1 then + s_adr_mux <= "1000"; -- adress = rom_data_i + s_nextstate <= EXEC2; + elsif state=EXEC2 then + alu_cmd_o <= ADDC_ACC_RAM; -- addition command (ACC+RAM_DATA+CY) + s_data_mux <= "0011"; -- data = aludata_i + s_regs_wr_en <= "011"; -- write ACC and CY,OV,AC + s_pc_inc_en <= "0001"; -- increment program-counter + s_nextstate <= FETCH; + end if; + + --------------------------------------------------------------------- + + when IC_ADDC_A_ATRI => -- ADDC A,@Ri + if state=FETCH then + s_adr_mux <= "0111"; -- address = Ri-register + s_nextstate <= EXEC1; + elsif state=EXEC1 then + alu_cmd_o <= ADDC_ACC_RAM; -- addition command (ACC+RAM_DATA+CY) + s_data_mux <= "0011"; -- data = aludata_i + s_regs_wr_en <= "011"; -- write ACC and CY,OV,AC + s_pc_inc_en <= "0001"; -- increment program-counter + s_nextstate <= FETCH; + end if; + + --------------------------------------------------------------------- + + when IC_ADDC_A_DATA => -- ADDC A, data + if state=FETCH then + s_pc_inc_en <= "0001"; -- increment program-counter + s_nextstate <= EXEC1; + elsif state=EXEC1 then + alu_cmd_o <= ADDC_ACC_ROM;-- addition command (ACC+ROM_DATA_I+CY) + s_data_mux <= "0011"; -- data = aludata_i + s_regs_wr_en <= "011"; -- write ACC and CY,OV,AC + s_pc_inc_en <= "0001"; -- increment program-counter + s_nextstate <= FETCH; + end if; + + --------------------------------------------------------------------- + + when IC_AJMP => -- AJMP addr11 + if state=FETCH then + s_help16_en <= "10"; -- s_help16 = pc+2 + s_pc_inc_en <= "0001"; -- increment program-counter + s_nextstate <= EXEC1; + elsif state=EXEC1 then + s_pc_inc_en <= "0100"; -- load PC with 11 bits (2k block) + s_nextstate <= FETCH; + end if; + + --------------------------------------------------------------------- + + when IC_ANL_A_RR => -- ANL A,Rr + if state=FETCH then + s_adr_mux <= "0110"; -- adress = RR-adress + s_nextstate <= EXEC1; + elsif state=EXEC1 then + alu_cmd_o <= AND_ACC_RAM; -- AND command (ACC ^ RAM_DATA) + s_data_mux <= "0011"; -- data = aludata_i + s_regs_wr_en <= "010"; -- write ACC + s_pc_inc_en <= "0001"; -- increment program-counter + s_nextstate <= FETCH; + end if; + + --------------------------------------------------------------------- + + when IC_ANL_A_D => -- ANL A, direct + if state=FETCH then + s_pc_inc_en <= "0001"; -- increment program-counter + s_nextstate <= EXEC1; + elsif state=EXEC1 then + s_adr_mux <= "1000"; -- address = rom_data_i + s_nextstate <= EXEC2; + elsif state=EXEC2 then + alu_cmd_o <= AND_ACC_RAM; -- AND command (ACC ^ RAM_DATA) + s_data_mux <= "0011"; -- data = aludata_i + s_regs_wr_en <= "010"; -- write ACC + s_pc_inc_en <= "0001"; -- increment program-counter + s_nextstate <= FETCH; + end if; + + --------------------------------------------------------------------- + + when IC_ANL_A_ATRI => -- ANL A,ATRi + if state=FETCH then + s_adr_mux <= "0111"; -- address = Ri-register + s_nextstate <= EXEC1; + elsif state=EXEC1 then + alu_cmd_o <= AND_ACC_RAM; -- AND command (ACC ^ RAM_DATA) + s_data_mux <= "0011"; -- data = aludata_i + s_regs_wr_en <= "010"; -- write ACC + s_pc_inc_en <= "0001"; -- increment program-counter + s_nextstate <= FETCH; + end if; + + --------------------------------------------------------------------- + when IC_ANL_A_DATA => -- ANL A, data + if state=FETCH then + s_pc_inc_en <= "0001"; -- increment program-counter + s_nextstate <= EXEC1; + elsif state=EXEC1 then + alu_cmd_o <= AND_ACC_ROM; -- AND command (ACC ^ ROM_DATA_I) + s_data_mux <= "0011"; -- data = aludata_i + s_regs_wr_en <= "010"; -- write ACC + s_pc_inc_en <= "0001"; -- increment program-counter + s_nextstate <= FETCH; + end if; + + --------------------------------------------------------------------- + + when IC_ANL_D_A => -- ANL direct, A + if state=FETCH then + s_pc_inc_en <= "0001"; -- increment program-counter + s_nextstate <= EXEC1; + elsif state=EXEC1 then + s_adr_mux <= "1000"; -- adress = rom_data_i + s_nextstate <= EXEC2; + elsif state=EXEC2 then + alu_cmd_o <= AND_ACC_RAM; -- AND command (ACC ^ RAM_DATA) + s_adr_mux <= "1000"; -- adress = rom_data_i + s_data_mux <= "0011"; -- data = aludata_i + s_regs_wr_en <= "100"; -- write one byte + s_pc_inc_en <= "0001"; -- increment program-counter + s_nextstate <= FETCH; + end if; + + --------------------------------------------------------------------- + + when IC_ANL_D_DATA => -- ANL direct, DATA + if state=FETCH then + s_pc_inc_en <= "0001"; -- increment program-counter + s_nextstate <= EXEC1; + elsif state=EXEC1 then + s_help_en <= "0001"; -- help = rom_data_i + s_adr_mux <= "1000"; -- adress = rom_data_i + s_pc_inc_en <= "0001"; -- increment program-counter + s_nextstate <= EXEC2; + elsif state=EXEC2 then + alu_cmd_o <= AND_RAM_ROM; -- AND command (ROM_DATA_I ^ RAM_DATA) + s_adr_mux <= "1010"; -- adress = help + s_data_mux <= "0011"; -- data = aludata_i + s_regs_wr_en <= "100"; -- write one byte + s_pc_inc_en <= "0001"; -- increment program-counter + s_nextstate <= FETCH; + end if; + + --------------------------------------------------------------------- + + when IC_ANL_C_BIT => -- ANL C, bit + if state=FETCH then + s_pc_inc_en <= "0001"; -- increment program-counter + s_nextstate <= EXEC1; + elsif state=EXEC1 then + s_adr_mux <= "1000"; -- adress = rom_data_i + s_nextstate <= EXEC2; + elsif state=EXEC2 then + s_bdata_mux <= "0001"; -- bdata = s_bit_data and cy + s_regs_wr_en <= "110"; -- write one bit (automatic CY-address) + s_pc_inc_en <= "0001"; -- increment program-counter + s_nextstate <= FETCH; + end if; + + --------------------------------------------------------------------- + + when IC_ANL_C_NBIT => -- ANL C, /bit + if state=FETCH then + s_pc_inc_en <= "0001"; -- increment program-counter + s_nextstate <= EXEC1; + elsif state=EXEC1 then + s_adr_mux <= "1000"; -- adress = rom_data_i + s_nextstate <= EXEC2; + elsif state=EXEC2 then + s_bdata_mux <= "0010"; -- bdata = not (s_bit_data and cy) + s_regs_wr_en <= "110"; -- write one bit (automatic CY-address) + s_pc_inc_en <= "0001"; -- increment program-counter + s_nextstate <= FETCH; + end if; + + --------------------------------------------------------------------- + + when IC_CJNE_A_D => -- CJNE A, direct, rel + if state=FETCH then + s_pc_inc_en <= "0001"; -- increment program-counter + s_nextstate <= EXEC1; + elsif state=EXEC1 then + s_adr_mux <= "1000"; -- address = rom_data_i + s_pc_inc_en <= "0001"; -- increment program-counter + s_nextstate <= EXEC2; + elsif state=EXEC2 then + alu_cmd_o <= COMP_RAM_ACC; -- Compare RAM_DATA/ACC operation + if unsigned(aludata_i) /= 0 then + s_adr_mux <= "1011"; -- adress of CY + s_bdata_mux <= "0011"; -- bdata = cby_i + s_regs_wr_en <= "110"; -- write one bit + s_pc_inc_en <= "0010"; -- add relativ adress to PC + else + s_adr_mux <= "1011"; -- adress of CY (CV: changed V1.5 according to specification: clear carry) + s_bdata_mux <= "0000"; -- bdata = 0 + s_regs_wr_en <= "110"; -- write one bit + s_pc_inc_en <= "0001"; -- increment program-counter + end if; + s_nextstate <= FETCH; + end if; + + --------------------------------------------------------------------- + + when IC_CJNE_A_DATA => -- CJNE A, #data, rel + if state=FETCH then + s_pc_inc_en <= "0001"; -- increment program-counter + s_nextstate <= EXEC1; + elsif state=EXEC1 then + alu_cmd_o <= COMP_ROM_ACC; -- Compare ROM_DATA_I/ACC operation + s_help_en <= "0010"; + s_helpb_en <= '1'; -- save new_cy_i + s_pc_inc_en <= "0001"; -- increment program-counter + s_nextstate <= EXEC2; + elsif state=EXEC2 then + if s_help /= 0 then + s_adr_mux <= "1011"; -- adress of CY + s_bdata_mux <= "0100"; -- bdata = s_helpb + s_regs_wr_en <= "110"; -- write one bit + s_pc_inc_en <= "0010"; -- add relativ adress to PC + else + s_adr_mux <= "1011"; -- adress of CY (CV: changed V1.5 according to specification: clear carry) + s_bdata_mux <= "0000"; -- bdata = 0 + s_regs_wr_en <= "110"; -- write one bit + s_pc_inc_en <= "0001"; -- increment program-counter + end if; + s_nextstate <= FETCH; + end if; + + --------------------------------------------------------------------- + + when IC_CJNE_RR_DATA => -- CJNE RR, #data, rel + if state=FETCH then + s_adr_mux <= "0110"; -- address = rr-address + s_pc_inc_en <= "0001"; -- increment program-counter + s_nextstate <= EXEC1; + elsif state=EXEC1 then + alu_cmd_o <= COMP_ROM_RAM;-- Compare ROM_DATA_I/RAM_DATA operat. + s_help_en <= "0010"; -- save aludata_i + s_helpb_en <= '1'; -- save new_cy_i + s_pc_inc_en <= "0001"; -- increment program-counter + s_nextstate <= EXEC2; + elsif state=EXEC2 then + if s_help /= 0 then + s_adr_mux <= "1011"; -- adress of CY + s_bdata_mux <= "0100"; -- bdata = s_helpb + s_regs_wr_en <= "110"; -- write one bit + s_pc_inc_en <= "0010"; -- add relativ adress to PC + else + s_adr_mux <= "1011"; -- adress of CY (CV: changed V1.5 according to specification: clear carry) + s_bdata_mux <= "0000"; -- bdata = 0 + s_regs_wr_en <= "110"; -- write one bit + s_pc_inc_en <= "0001"; -- increment program-counter + end if; + s_nextstate <= FETCH; + end if; + + --------------------------------------------------------------------- + + when IC_CJNE_ATRI_DATA => -- CJNE @Ri, #data, rel + if state=FETCH then + s_adr_mux <= "0111"; -- address = Ri-register + s_pc_inc_en <= "0001"; -- increment program-counter + s_nextstate <= EXEC1; + elsif state=EXEC1 then + alu_cmd_o <= COMP_ROM_RAM; -- Compare ROM_/RAM_DATA operation + s_help_en <= "0010"; -- save aludata_i + s_helpb_en <= '1'; -- save new_cy_i + s_pc_inc_en <= "0001"; -- increment program-counter + s_nextstate <= EXEC2; + elsif state=EXEC2 then + if s_help /= 0 then + s_adr_mux <= "1011"; -- adress of CY + s_bdata_mux <= "0100"; -- bdata = s_helpb + s_regs_wr_en <= "110"; -- write one bit + s_pc_inc_en <= "0010"; -- add relativ adress to PC + else + s_adr_mux <= "1011"; -- adress of CY (CV: changed V1.5 according to specification: clear carry) + s_bdata_mux <= "0000"; -- bdata = 0 + s_regs_wr_en <= "110"; -- write one bit + s_pc_inc_en <= "0001"; -- increment program-counter + end if; + s_nextstate <= FETCH; + end if; + + --------------------------------------------------------------------- + + when IC_CLR_A => -- CLR A + s_data_mux <= "0000"; -- data = 0 + s_regs_wr_en <= "010"; -- write ACC + s_pc_inc_en <= "0001"; -- increment program-counter + s_nextstate <= FETCH; + + --------------------------------------------------------------------- + + when IC_CLR_C => -- CLR C + s_adr_mux <= "1011"; -- adress of CY + s_bdata_mux <= "0000"; -- bdata = 0 + s_regs_wr_en <= "110"; -- write one bit + s_pc_inc_en <= "0001"; -- increment program-counter + s_nextstate <= FETCH; + + --------------------------------------------------------------------- + + when IC_CLR_BIT => -- CLR bit + if state=FETCH then + s_pc_inc_en <= "0001"; -- increment program-counter + s_nextstate <= EXEC1; + elsif state=EXEC1 then + s_adr_mux <= "1000"; -- address = rom_data_i + s_bdata_mux <= "0000"; -- bdata = 0 + s_regs_wr_en <= "110"; -- write one bit + s_pc_inc_en <= "0001"; -- increment program-counter + s_nextstate <= FETCH; + end if; + + --------------------------------------------------------------------- + + when IC_CPL_A => -- CPL A + alu_cmd_o <= INV_ACC; -- complement operation + s_data_mux <= "0011"; -- data = aludata_i + s_regs_wr_en <= "010"; -- write ACC + s_pc_inc_en <= "0001"; -- increment program-counter + s_nextstate <= FETCH; + + --------------------------------------------------------------------- + + when IC_CPL_C => -- CPL C + s_adr_mux <= "1011"; -- adress of CY + s_bdata_mux <= "0101"; -- bdata = not cy + s_regs_wr_en <= "110"; -- write one bit + s_pc_inc_en <= "0001"; -- increment program-counter + s_nextstate <= FETCH; + + --------------------------------------------------------------------- + + when IC_CPL_BIT => -- CPL bit + if state=FETCH then + s_pc_inc_en <= "0001"; -- increment program-counter + s_nextstate <= EXEC1; + elsif state=EXEC1 then + s_adr_mux <= "1000"; -- bit adress + s_nextstate <= EXEC2; + elsif state=EXEC2 then + s_adr_mux <= "1000"; -- bit adress + s_bdata_mux <= "0110"; -- bdata = not s_bit_data + s_regs_wr_en <= "110"; -- write one bit + s_pc_inc_en <= "0001"; -- increment program-counter + s_nextstate <= FETCH; + else + s_nextstate <= FETCH; + end if; + + --------------------------------------------------------------------- + + when IC_DA_A => -- DA A + alu_cmd_o <= DA; -- DA operation + s_data_mux <= "0011"; -- data = aludata_i + s_regs_wr_en <= "111"; -- write ACC and CY (special operation) + s_pc_inc_en <= "0001"; -- increment program-counter + s_nextstate <= FETCH; + + --------------------------------------------------------------------- + + when IC_DEC_A => -- DEC A + alu_cmd_o <= DEC_ACC; -- decrement operation + s_data_mux <= "0011"; -- data = aludata_i + s_regs_wr_en <= "010"; -- write ACC + s_pc_inc_en <= "0001"; -- increment program-counter + s_nextstate <= FETCH; + + --------------------------------------------------------------------- + + when IC_DEC_RR => -- DEC Rr + if state=FETCH then + s_adr_mux <= "0110"; -- address = rr-address + s_nextstate <= EXEC1; + elsif state=EXEC1 then + alu_cmd_o <= DEC_RAM; -- decrement operation + s_adr_mux <= "0110"; -- address = rr-address + s_data_mux <= "0011"; -- data = aludata_i + s_regs_wr_en <= "100"; -- write one byte + s_pc_inc_en <= "0001"; -- increment program-counter + s_nextstate <= FETCH; + end if; + + --------------------------------------------------------------------- + + when IC_DEC_D => -- DEC direct + if state=FETCH then + s_pc_inc_en <= "0001"; -- increment program-counter + s_nextstate <= EXEC1; + elsif state=EXEC1 then + s_adr_mux <= "1000"; -- address = rom_data_i + s_nextstate <= EXEC2; + elsif state=EXEC2 then + s_adr_mux <= "1000"; -- address = rom_data_i + s_data_mux <= "0011"; -- data = aludata_i + s_regs_wr_en <= "100"; -- write one byte + alu_cmd_o <= DEC_RAM; -- decrement operation + s_pc_inc_en <= "0001"; -- increment program-counter + s_nextstate <= FETCH; + end if; + + --------------------------------------------------------------------- + + when IC_DEC_ATRI => -- DEC @Ri + if state=FETCH then + s_adr_mux <= "0111"; -- address = Ri-register + s_nextstate <= EXEC1; + elsif state=EXEC1 then + alu_cmd_o <= DEC_RAM; -- decrement operation + s_adr_mux <= "0111"; -- address = ri-address + s_data_mux <= "0011"; -- data = aludata_i + s_regs_wr_en <= "100"; -- write one byte + s_pc_inc_en <= "0001"; -- increment program-counter + s_nextstate <= FETCH; + end if; + + --------------------------------------------------------------------- + + when IC_DIV_AB => -- DIV AB + if state=FETCH then + s_adr_mux <= "1100"; -- adress of B register + alu_cmd_o <= DIV_ACC_RAM; -- divison operation + s_nextstate <= EXEC1; + elsif state=EXEC1 then + s_data_mux <= "0011"; -- data = aludata_i + s_adr_mux <= "1100"; -- adress of B register + alu_cmd_o <= DIV_ACC_RAM; -- divison operation + s_nextstate <= EXEC2; + elsif state=EXEC2 then + s_data_mux <= "0011"; -- data = aludata_i + s_adr_mux <= "1100"; -- adress of B register + s_regs_wr_en <= "111"; -- write ACC,B,OV,CY(special operation) + alu_cmd_o <= DIV_ACC_RAM; -- divison operation + s_pc_inc_en <= "0001"; -- increment program-counter + s_nextstate <= FETCH; + end if; + + --------------------------------------------------------------------- + + when IC_DJNZ_RR => -- DJNZ Rr, rel + if state=FETCH then + s_adr_mux <= "0110"; -- address = rr-address + s_help_en <= "0100"; -- save Rr-adress + s_pc_inc_en <= "0001"; -- increment program-counter + s_nextstate <= EXEC1; + elsif state=EXEC1 then + alu_cmd_o <= DEC_RAM; -- decrement operation + if unsigned(aludata_i) /= 0 then + s_adr_mux <= "1010"; -- address = rr-address + s_data_mux <= "0011"; -- data = aludata_i + s_regs_wr_en <= "100"; -- write one byte + s_pc_inc_en <= "0010"; -- add relativ adress to PC + else + s_adr_mux <= "1010"; -- address = rr-address + s_data_mux <= "0011"; -- data = aludata_i + s_regs_wr_en <= "100"; -- write one byte + s_pc_inc_en <= "0001"; -- increment program-counter + end if; + s_nextstate <= FETCH; + end if; + + --------------------------------------------------------------------- + + when IC_DJNZ_D => -- DJNZ direct, rel + if state=FETCH then + s_pc_inc_en <= "0001"; -- increment program-counter + s_nextstate <= EXEC1; + elsif state=EXEC1 then + s_help_en <= "0001"; -- save address + s_adr_mux <= "1000"; -- address = rom_data + s_pc_inc_en <= "0001"; -- increment program-counter + s_nextstate <= EXEC2; + elsif state=EXEC2 then + alu_cmd_o <= DEC_RAM; -- decrement operation + if unsigned(aludata_i) /= 0 then + s_adr_mux <= "1010"; -- address = help + s_data_mux <= "0011"; -- data = aludata_i + s_regs_wr_en <= "100"; -- write one byte + s_pc_inc_en <= "0010"; -- add relativ adress to PC + else + s_adr_mux <= "1010"; -- address = help + s_data_mux <= "0011"; -- data = aludata_i + s_regs_wr_en <= "100"; -- write one byte + s_pc_inc_en <= "0001"; -- increment program-counter + end if; + s_nextstate <= FETCH; + end if; + + --------------------------------------------------------------------- + + when IC_INC_A => -- INC A + alu_cmd_o <= INC_ACC; -- increment operation + s_data_mux <= "0011"; -- data = aludata_i + s_regs_wr_en <= "010"; -- write ACC + s_pc_inc_en <= "0001"; -- increment program-counter + s_nextstate <= FETCH; + + --------------------------------------------------------------------- + + when IC_INC_RR => -- INC Rr + if state=FETCH then + s_adr_mux <= "0110"; -- address = rr-address + s_nextstate <= EXEC1; + elsif state=EXEC1 then + alu_cmd_o <= INC_RAM; -- increment operation + s_adr_mux <= "0110"; -- address = rr-address + s_data_mux <= "0011"; -- data = aludata_i + s_regs_wr_en <= "100"; -- write one byte + s_pc_inc_en <= "0001"; -- increment program-counter + s_nextstate <= FETCH; + end if; + + --------------------------------------------------------------------- + + when IC_INC_D => -- INC direct + if state=FETCH then + s_pc_inc_en <= "0001"; -- increment program-counter + s_nextstate <= EXEC1; + elsif state=EXEC1 then + s_adr_mux <= "1000"; -- address = rom_data_i + s_nextstate <= EXEC2; + elsif state=EXEC2 then + alu_cmd_o <= INC_RAM; -- increment operation + s_adr_mux <= "1000"; -- address = rom_data_i + s_data_mux <= "0011"; -- data = aludata_i + s_regs_wr_en <= "100"; -- write one byte + s_pc_inc_en <= "0001"; -- increment program-counter + s_nextstate <= FETCH; + end if; + + --------------------------------------------------------------------- + + when IC_INC_ATRI => -- INC @Ri + if state=FETCH then + s_adr_mux <= "0111"; -- address = Ri-register + s_nextstate <= EXEC1; + elsif state=EXEC1 then + alu_cmd_o <= INC_RAM; -- increment operation + s_adr_mux <= "0111"; -- address = Ri-register + s_data_mux <= "0011"; -- data = aludata_i + s_regs_wr_en <= "100"; -- write one byte + s_pc_inc_en <= "0001"; -- increment program-counter + s_nextstate <= FETCH; + end if; + + --------------------------------------------------------------------- + + when IC_INC_DPTR => -- INC DPTR + if state=FETCH then + s_adr_mux <= "1101"; -- adress of DPL + s_nextstate <= EXEC1; + elsif state=EXEC1 then + alu_cmd_o <= INC_RAM; -- increment operation + s_help_en <= "0010"; -- help = aludata_i + s_adr_mux <= "1101"; -- adress of DPL + s_data_mux <= "0011"; -- data = aludata_i + s_regs_wr_en <= "100"; -- write one byte + s_nextstate <= EXEC2; + elsif state=EXEC2 then + s_adr_mux <= "1110"; -- adress of DPH + s_nextstate <= EXEC3; + elsif state=EXEC3 then + if s_help=conv_unsigned(0,8) then + alu_cmd_o <= INC_RAM; -- increment operation + s_adr_mux <= "1110"; -- adress of DPH + s_data_mux <= "0011"; -- data = aludata_i + s_regs_wr_en <= "100"; -- write one byte + else + end if; + s_pc_inc_en <= "0001"; -- increment program-counter + s_nextstate <= FETCH; + end if; + + --------------------------------------------------------------------- + + when IC_JB => -- JB bit, rel + if state=FETCH then + s_pc_inc_en <= "0001"; -- increment program-counter + s_nextstate <= EXEC1; + elsif state=EXEC1 then + s_adr_mux <= "1000"; -- bit adress = rom_data_i + s_pc_inc_en <= "0001"; -- increment program-counter + s_nextstate <= EXEC2; + elsif state=EXEC2 then + if s_bit_data = '1' then + s_pc_inc_en <= "0010"; -- add relativ adress to PC + else + s_pc_inc_en <= "0001"; -- increment program-counter + end if; + s_nextstate <= FETCH; + end if; + + --------------------------------------------------------------------- + + when IC_JBC => -- JBC bit, rel + if state=FETCH then + s_pc_inc_en <= "0001"; -- increment program-counter + s_nextstate <= EXEC1; + elsif state=EXEC1 then + s_adr_mux <= "1000"; -- bit adress = rom_data_i + s_help_en <= "0001"; -- s_help = rom_data_i + s_pc_inc_en <= "0001"; -- increment program-counter + s_nextstate <= EXEC2; + elsif state=EXEC2 then + s_adr_mux <= "1010"; -- s_adr = s_help + s_bdata_mux <= "0000"; -- s_bdata = 0 + s_regs_wr_en <= "110"; -- write one bit + if s_bit_data = '1' then + s_pc_inc_en <= "0010"; -- add relativ adress to PC + else + s_pc_inc_en <= "0001"; -- increment program-counter + end if; + s_nextstate <= FETCH; + end if; + + --------------------------------------------------------------------- + + when IC_JC => -- JC rel + if state=FETCH then + s_pc_inc_en <= "0001"; -- increment program-counter + s_nextstate <= EXEC1; + elsif state=EXEC1 then + if cy = '1' then + s_pc_inc_en <= "0010"; -- add relativ adress to PC + else + s_pc_inc_en <= "0001"; -- increment program-counter + end if; + s_nextstate <= FETCH; + end if; + + --------------------------------------------------------------------- + + when IC_JMP_A_DPTR => -- JMP @A+DPTR + s_pc_inc_en <= "0101"; -- PC = ACC + DPTR + s_nextstate <= FETCH; + + --------------------------------------------------------------------- + + when IC_JNB => -- JNB bit, rel + if state=FETCH then + s_pc_inc_en <= "0001"; -- increment program-counter + s_nextstate <= EXEC1; + elsif state=EXEC1 then + s_adr_mux <= "1000"; -- bit adress = rom_data_i + s_pc_inc_en <= "0001"; -- increment program-counter + s_nextstate <= EXEC2; + elsif state=EXEC2 then + if s_bit_data = '0' then + s_pc_inc_en <= "0010"; -- add relativ adress to PC + else + s_pc_inc_en <= "0001"; -- increment program-counter + end if; + s_nextstate <= FETCH; + end if; + + --------------------------------------------------------------------- + + when IC_JNC => -- JNC rel + if state=FETCH then + s_pc_inc_en <= "0001"; -- increment program-counter + s_nextstate <= EXEC1; + elsif state=EXEC1 then + if cy = '0' then + s_pc_inc_en <= "0010"; -- add relativ adress to PC + else + s_pc_inc_en <= "0001"; -- increment program-counter + end if; + s_nextstate <= FETCH; + end if; + + --------------------------------------------------------------------- + + when IC_JNZ => -- JNZ rel + if state=FETCH then + s_pc_inc_en <= "0001"; -- increment program-counter + s_nextstate <= EXEC1; + elsif state=EXEC1 then + if unsigned(acc) /= conv_unsigned(0,8) then + s_pc_inc_en <= "0010"; -- add relativ adress to PC + else + s_pc_inc_en <= "0001"; -- increment program-counter + end if; + s_nextstate <= FETCH; + end if; + + --------------------------------------------------------------------- + + when IC_JZ => -- JZ rel + if state=FETCH then + s_pc_inc_en <= "0001"; -- increment program-counter + s_nextstate <= EXEC1; + elsif state=EXEC1 then + if unsigned(acc) = conv_unsigned(0,8) then + s_pc_inc_en <= "0010"; -- add relativ adress to PC + else + s_pc_inc_en <= "0001"; -- increment program-counter + end if; + s_nextstate <= FETCH; + end if; + + --------------------------------------------------------------------- + + when IC_LCALL => -- LCALL addr16 + if state=FETCH then + s_regs_wr_en <= "001"; -- increment stackpointer + s_help16_en <= "01"; -- s_help16 <= pc + 3 + s_pc_inc_en <= "0001"; -- increment program-counter + s_nextstate <= EXEC1; + elsif state=EXEC1 then + s_help_en <= "0001"; -- help <= rom_data_i + s_data_mux <= "1100"; -- data <= help16(7 downto 0) + s_adr_mux <= "0101"; -- s_adr <= sp + s_regs_wr_en <= "101"; -- write one byte and increment SP + s_pc_inc_en <= "0001"; -- increment program-counter + s_nextstate <= EXEC2; + elsif state=EXEC2 then + s_data_mux <= "1101"; -- data = help16(15 downto 8) + s_adr_mux <= "0101"; -- s_adr <= sp + s_regs_wr_en <= "100"; -- write one byte + s_pc_inc_en <= "0111"; -- load program counter + s_nextstate <= FETCH; + end if; + + --------------------------------------------------------------------- + + when IC_LJMP => -- LJMP addr16 + if state=FETCH then + s_pc_inc_en <= "0001"; -- increment program-counter + s_nextstate <= EXEC1; + elsif state=EXEC1 then + s_help_en <= "0001"; -- help = rom_data_i + s_pc_inc_en <= "0001"; -- increment program-counter + s_nextstate <= EXEC2; + elsif state=EXEC2 then + s_pc_inc_en <= "0111"; -- load program-counter + s_nextstate <= FETCH; + end if; + + --------------------------------------------------------------------- + + when IC_MOV_A_RR => -- MOV A,Rr + if state=FETCH then + s_adr_mux <= "0110"; -- address = rr-address + s_nextstate <= EXEC1; + elsif state=EXEC1 then + s_data_mux <= "0100"; -- data = s_reg_data + s_regs_wr_en <= "010"; -- write ACC + s_pc_inc_en <= "0001"; -- increment program-counter + s_nextstate <= FETCH; + end if; + + --------------------------------------------------------------------- + when IC_MOV_A_D => -- MOV A, direct + if state=FETCH then + s_pc_inc_en <= "0001"; -- increment program-counter + s_nextstate <= EXEC1; + elsif state=EXEC1 then + s_adr_mux <= "1000"; -- address = rom_data_i + s_nextstate <= EXEC2; + elsif state=EXEC2 then + s_data_mux <= "0100"; -- data = s_reg_data + s_regs_wr_en <= "010"; -- write ACC + s_pc_inc_en <= "0001"; -- increment program-counter + s_nextstate <= FETCH; + end if; + + --------------------------------------------------------------------- + + when IC_MOV_A_ATRI => -- MOV A,@Ri + if state=FETCH then + s_adr_mux <= "0111"; -- address = Ri-register + s_nextstate <= EXEC1; + elsif state=EXEC1 then + s_data_mux <= "0100"; -- data = s_reg_data + s_regs_wr_en <= "010"; -- write ACC + s_pc_inc_en <= "0001"; -- increment program-counter + s_nextstate <= FETCH; + end if; + + --------------------------------------------------------------------- + + when IC_MOV_A_DATA => -- MOV A, #DATA + if state=FETCH then + s_pc_inc_en <= "0001"; -- increment program-counter + s_nextstate <= EXEC1; + elsif state=EXEC1 then + s_data_mux <= "0101"; -- data = rom_data_i + s_regs_wr_en <= "010"; -- write ACC + s_pc_inc_en <= "0001"; -- increment program-counter + s_nextstate <= FETCH; + end if; + + --------------------------------------------------------------------- + + when IC_MOV_RR_A => -- MOV Rr,A + s_adr_mux <= "0110"; -- address = rr-address + s_data_mux <= "0110"; -- data = ACC + s_regs_wr_en <= "100"; -- write one byte + s_pc_inc_en <= "0001"; -- increment program-counter + s_nextstate <= FETCH; + + --------------------------------------------------------------------- + + when IC_MOV_RR_D => -- MOV Rr, direct + if state=FETCH then + s_help_en <= "0100"; -- save Rr-adress in help + s_pc_inc_en <= "0001"; -- increment program-counter + s_nextstate <= EXEC1; + elsif state=EXEC1 then + s_adr_mux <= "1000"; -- address = rom_data_i + s_nextstate <= EXEC2; + elsif state=EXEC2 then + s_adr_mux <= "1010"; -- address = help + s_data_mux <= "0100"; -- data = s_reg_data + s_regs_wr_en <= "100"; -- write one byte + s_pc_inc_en <= "0001"; -- do nothing with program counter + s_nextstate <= FETCH; + end if; + + --------------------------------------------------------------------- + + when IC_MOV_RR_DATA => -- MOV Rr,#data + if state=FETCH then + s_help_en <= "0100"; -- save Rr-adress in help + s_pc_inc_en <= "0001"; -- increment program-counter + s_nextstate <= EXEC1; + elsif state=EXEC1 then + s_adr_mux <= "1010"; -- address = help + s_data_mux <= "0101"; -- data = rom_data_i + s_regs_wr_en <= "100"; -- write one byte + s_pc_inc_en <= "0001"; -- do nothing with program counter + s_nextstate <= FETCH; + end if; + + --------------------------------------------------------------------- + + when IC_MOV_D_A => -- MOV direct, A + if state=FETCH then + s_pc_inc_en <= "0001"; -- increment program-counter + s_nextstate <= EXEC1; + elsif state=EXEC1 then + s_adr_mux <= "1000"; -- address = rom_data_i + s_data_mux <= "0110"; -- data = ACC + s_regs_wr_en <= "100"; -- write one byte + s_pc_inc_en <= "0001"; -- increment program-counter + s_nextstate <= FETCH; + end if; + + ------------------------------------------------------------------- + + when IC_MOV_D_RR => -- MOV direct, Rr + if state=FETCH then + s_adr_mux <= "0110"; -- address = rr-address + s_pc_inc_en <= "0001"; -- increment program-counter + s_nextstate <= EXEC1; + elsif state=EXEC1 then + s_adr_mux <= "1000"; -- address = rom_data_i + s_data_mux <= "0100"; -- data = s_reg_data + s_regs_wr_en <= "100"; -- write one byte + s_pc_inc_en <= "0001"; -- do nothing with program counter + s_nextstate <= FETCH; + end if; + + --------------------------------------------------------------------- + + when IC_MOV_D_D => -- MOV direct, direct + if state=FETCH then + s_pc_inc_en <= "0001"; -- increment program-counter + s_nextstate <= EXEC1; + elsif state=EXEC1 then + s_adr_mux <= "1000"; -- address = rom_data_i + s_pc_inc_en <= "0001"; -- increment program-counter + s_nextstate <= EXEC2; + elsif state=EXEC2 then + s_adr_mux <= "1000"; -- address = rom_data_i + s_data_mux <= "0100"; -- data = s_reg_data + s_regs_wr_en <= "100"; -- write one byte + s_pc_inc_en <= "0001"; -- increment program-counter + s_nextstate <= FETCH; + end if; + + --------------------------------------------------------------------- + + when IC_MOV_D_ATRI => -- MOV direct ,@Ri + if state=FETCH then + s_adr_mux <= "0111"; -- address = Ri-register + s_pc_inc_en <= "0001"; -- increment program-counter + s_nextstate <= EXEC1; + elsif state=EXEC1 then + s_adr_mux <= "1000"; -- address = rom_data_i + s_data_mux <= "0100"; -- data = s_reg_data + s_regs_wr_en <= "100"; -- write one byte + s_pc_inc_en <= "0001"; -- increment program-counter + s_nextstate <= FETCH; + end if; + + --------------------------------------------------------------------- + + when IC_MOV_D_DATA => -- MOV direct, #data + if state=FETCH then + s_pc_inc_en <= "0001"; -- increment program-counter + s_nextstate <= EXEC1; + elsif state=EXEC1 then + s_help_en <= "0001"; -- save direct adress + s_pc_inc_en <= "0001"; -- increment program-counter + s_nextstate <= EXEC2; + elsif state=EXEC2 then + s_adr_mux <= "1010"; -- address = help + s_data_mux <= "0101"; -- data = rom_data_i + s_regs_wr_en <= "100"; -- write one byte + s_pc_inc_en <= "0001"; -- increment program-counter + s_nextstate <= FETCH; + end if; + + --------------------------------------------------------------------- + + when IC_MOV_ATRI_A => -- MOV @Ri,A + s_adr_mux <= "0111"; -- address = Ri-register + s_data_mux <= "0110"; -- data = ACC + s_regs_wr_en <= "100"; -- write one byte + s_pc_inc_en <= "0001"; -- increment program-counter + s_nextstate <= FETCH; + + --------------------------------------------------------------------- + + when IC_MOV_ATRI_D => -- MOV @Ri, direct + if state=FETCH then + s_pc_inc_en <= "0001"; -- increment program-counter + s_nextstate <= EXEC1; + elsif state=EXEC1 then + s_adr_mux <= "1000"; -- address = rom_data_i + s_nextstate <= EXEC2; + elsif state=EXEC2 then + s_adr_mux <= "0111"; -- address = Ri-register + s_data_mux <= "0100"; -- data = s_reg_data + s_regs_wr_en <= "100"; -- write one byte + s_pc_inc_en <= "0001"; -- increment program-counter + s_nextstate <= FETCH; + end if; + + --------------------------------------------------------------------- + + when IC_MOV_ATRI_DATA => -- MOV @Ri,#data + if state=FETCH then + s_pc_inc_en <= "0001"; -- increment program-counter + s_nextstate <= EXEC1; + elsif state=EXEC1 then + s_adr_mux <= "0111"; -- address = Ri-register + s_data_mux <= "0101"; -- data = rom_data_i + s_regs_wr_en <= "100"; -- write one byte + s_pc_inc_en <= "0001"; -- increment program-counter + s_nextstate <= FETCH; + end if; + + --------------------------------------------------------------------- + + when IC_MOVC_A_ATDPTR => -- MOVC A, @A+DPTR + if state=FETCH then + s_help16_en <= "11"; -- save PC+1 in help16 + s_pc_inc_en <= "0101"; -- PC = A+DPTR + s_nextstate <= EXEC1; + elsif state=EXEC1 then + s_data_mux <= "0101"; -- data = rom_data_i + s_regs_wr_en <= "010"; -- write ACC + s_pc_inc_en <= "0110"; -- PC = help16 + s_nextstate <= FETCH; + end if; + + --------------------------------------------------------------------- + + when IC_MOVC_A_ATPC => -- MOVC A, @A+PC + if state=FETCH then + s_help16_en <= "11"; -- save PC+1 in help16 + s_pc_inc_en <= "1001"; -- PC = A+PC+1 + s_nextstate <= EXEC1; + elsif state=EXEC1 then + s_data_mux <= "0101"; -- data = rom_data_i + s_regs_wr_en <= "010"; -- write ACC + s_pc_inc_en <= "0110"; -- PC = help16 + s_nextstate <= FETCH; + end if; + + --------------------------------------------------------------------- + + when IC_MOVX_A_ATRI => -- MOVX A, @RI + if state=FETCH then + s_adrx_mux <= "10"; -- external adress = Ri + s_nextstate <= EXEC1; + elsif state=EXEC1 then + s_data_mux <= "1111"; -- data = datax_i + s_regs_wr_en <= "010"; -- write ACC + s_pc_inc_en <= "0001"; -- increment program-counter + s_nextstate <= FETCH; + end if; + + --------------------------------------------------------------------- + + when IC_MOVX_A_ATDPTR => -- MOVX A, @DPTR + if state=FETCH then + s_adrx_mux <= "01"; -- external adress = DPTR + s_nextstate <= EXEC1; + elsif state=EXEC1 then + s_data_mux <= "1111"; -- data = datax_i + s_regs_wr_en <= "010"; -- write ACC + s_pc_inc_en <= "0001"; -- increment program-counter + s_nextstate <= FETCH; + end if; + + --------------------------------------------------------------------- + + when IC_MOVX_ATRI_A => -- MOVX @RI, A + s_adrx_mux <= "10"; -- external adress = Ri + s_wrx_mux <= '1'; + s_pc_inc_en <= "0001"; -- increment program-counter + s_nextstate <= FETCH; + + --------------------------------------------------------------------- + + when IC_MOVX_ATDPTR_A => -- MOVX @DPTR, A + s_adrx_mux <= "01"; -- external adress = DPTR + s_wrx_mux <= '1'; + s_pc_inc_en <= "0001"; -- increment program-counter + s_nextstate <= FETCH; + + --------------------------------------------------------------------- + + when IC_MOV_C_BIT => -- MOV C, bit + if state=FETCH then + s_pc_inc_en <= "0001"; -- increment program-counter + s_nextstate <= EXEC1; + elsif state=EXEC1 then + s_adr_mux <= "1000"; -- address = rom_data_i + s_nextstate <= EXEC2; + elsif state=EXEC2 then + s_bdata_mux <= "0111"; -- bdata = s_bit_data + s_regs_wr_en <= "110"; -- write one bit (automatic CY-address) + s_pc_inc_en <= "0001"; -- increment program-counter + s_nextstate <= FETCH; + end if; + + --------------------------------------------------------------------- + + when IC_MOV_BIT_C => -- MOV bit,C + if state=FETCH then + s_pc_inc_en <= "0001"; -- increment program-counter + s_nextstate <= EXEC1; + elsif state=EXEC1 then + s_adr_mux <= "1000"; -- address = rom_data_i + s_bdata_mux <= "1000"; -- bdata = cy + s_regs_wr_en <= "110"; -- write one bit + s_pc_inc_en <= "0001"; -- increment program-counter + s_nextstate <= FETCH; + end if; + + --------------------------------------------------------------------- + + when IC_MOV_DPTR_DATA => -- MOV DPTR, #data16 + if state=FETCH then + s_pc_inc_en <= "0001"; -- increment program-counter + s_nextstate <= EXEC1; + elsif state=EXEC1 then + s_adr_mux <= "1110"; -- adress of DPH + s_data_mux <= "0101"; -- data = rom_data_i + s_regs_wr_en <= "100"; -- write one byte + s_pc_inc_en <= "0001"; -- increment program-counter + s_nextstate <= EXEC2; + elsif state=EXEC2 then + s_adr_mux <= "1101"; -- adress of DPL + s_data_mux <= "0101"; -- data = rom_data_i + s_regs_wr_en <= "100"; -- write one byte + s_pc_inc_en <= "0001"; -- increment program-counter + s_nextstate <= FETCH; + end if; + + --------------------------------------------------------------------- + + when IC_MUL_AB => -- MUL AB + if state=FETCH then + s_adr_mux <= "1100"; -- adress of B register + alu_cmd_o <= MUL_ACC_RAM; -- divison operation + s_nextstate <= EXEC1; + elsif state=EXEC1 then + s_data_mux <= "0011"; -- data = aludata_i + s_adr_mux <= "1100"; -- adress of B register + alu_cmd_o <= MUL_ACC_RAM; -- divison operation + s_nextstate <= EXEC2; + elsif state=EXEC2 then + s_data_mux <= "0011"; -- data = aludata_i + s_adr_mux <= "1100"; -- adress of B register + s_regs_wr_en <= "111"; -- write ACC,B,OV,CY (special operation) + alu_cmd_o <= MUL_ACC_RAM; -- divison operation + s_pc_inc_en <= "0001"; -- increment program-counter + s_nextstate <= FETCH; + end if; + + --------------------------------------------------------------------- + + when IC_NOP => -- NOP + s_pc_inc_en <= "0001"; -- increment program-counter + s_nextstate <= FETCH; + + --------------------------------------------------------------------- + + when IC_ORL_A_RR => -- ORL A,Rr + if state=FETCH then + s_adr_mux <= "0110"; -- address = rr-address + s_nextstate <= EXEC1; + elsif state=EXEC1 then + alu_cmd_o <= OR_RAM_ACC; -- OR command (ACC v RAM_DATA) + s_data_mux <= "0011"; -- data = aludata_i + s_regs_wr_en <= "010"; -- write ACC + s_pc_inc_en <= "0001"; -- increment program-counter + s_nextstate <= FETCH; + end if; + + --------------------------------------------------------------------- + when IC_ORL_A_D => -- ORL A, direct + if state=FETCH then + s_pc_inc_en <= "0001"; -- increment program-counter + s_nextstate <= EXEC1; + elsif state=EXEC1 then + s_adr_mux <= "1000"; -- address = rom_data_i + s_nextstate <= EXEC2; + elsif state=EXEC2 then + alu_cmd_o <= OR_RAM_ACC; -- OR command (ACC v RAM_DATA) + s_data_mux <= "0011"; -- data = aludata_i + s_regs_wr_en <= "010"; -- write ACC + s_pc_inc_en <= "0001"; -- increment program-counter + s_nextstate <= FETCH; + end if; + + --------------------------------------------------------------------- + when IC_ORL_A_ATRI => -- ORL A,@Ri + if state=FETCH then + s_adr_mux <= "0111"; -- address = Ri-register + s_nextstate <= EXEC1; + elsif state=EXEC1 then + alu_cmd_o <= OR_RAM_ACC; -- OR command (ACC v RAM_DATA) + s_data_mux <= "0011"; -- data = aludata_i + s_regs_wr_en <= "010"; -- write ACC + s_pc_inc_en <= "0001"; -- increment program-counter + s_nextstate <= FETCH; + end if; + + --------------------------------------------------------------------- + when IC_ORL_A_DATA => -- ORL A, data + if state=FETCH then + s_pc_inc_en <= "0001"; -- increment program-counter + s_nextstate <= EXEC1; + elsif state=EXEC1 then + alu_cmd_o <= OR_ROM_ACC; -- OR command (ACC v ROM_DATA_I) + s_data_mux <= "0011"; -- data = aludata_i + s_regs_wr_en <= "010"; -- write ACC + s_pc_inc_en <= "0001"; -- increment program-counter + s_nextstate <= FETCH; + end if; + + --------------------------------------------------------------------- + when IC_ORL_D_A => -- ORL direct, A + if state=FETCH then + s_pc_inc_en <= "0001"; -- increment program-counter + s_nextstate <= EXEC1; + elsif state=EXEC1 then + s_adr_mux <= "1000"; -- address = rom_data_i + s_nextstate <= EXEC2; + elsif state=EXEC2 then + alu_cmd_o <= OR_RAM_ACC; -- OR command (ACC v RAM_DATA) + s_adr_mux <= "1000"; -- address = rom_data_i + s_data_mux <= "0011"; -- data = aludata_i + s_regs_wr_en <= "100"; -- write one byte + s_pc_inc_en <= "0001"; -- increment program-counter + s_nextstate <= FETCH; + end if; + + --------------------------------------------------------------------- + + when IC_ORL_D_DATA => -- ORL direct, DATA + if state=FETCH then + s_pc_inc_en <= "0001"; -- increment program-counter + s_nextstate <= EXEC1; + elsif state=EXEC1 then + s_help_en <= "0001"; -- save rom_data_i + s_adr_mux <= "1000"; + s_pc_inc_en <= "0001"; -- increment program-counter + s_nextstate <= EXEC2; + elsif state=EXEC2 then + alu_cmd_o <= OR_ROM_RAM; -- OR command (ROM_DATA_I v RAM_DATA) + s_adr_mux <= "1010"; -- address = help + s_data_mux <= "0011"; -- data = aludata_i + s_regs_wr_en <= "100"; -- write one byte + s_pc_inc_en <= "0001"; -- increment program-counter + s_nextstate <= FETCH; + end if; + + --------------------------------------------------------------------- + + when IC_ORL_C_BIT => -- ORL C, bit + if state=FETCH then + s_pc_inc_en <= "0001"; -- increment program-counter + s_nextstate <= EXEC1; + elsif state=EXEC1 then + s_adr_mux <= "1000"; -- address = rom_data_i + s_nextstate <= EXEC2; + elsif state=EXEC2 then + s_bdata_mux <= "1001"; -- bdata = s_bit_data or cy + s_regs_wr_en <= "110"; -- write one bit (autmatically CY) + s_pc_inc_en <= "0001"; -- increment program-counter + s_nextstate <= FETCH; + end if; + + --------------------------------------------------------------------- + + when IC_ORL_C_NBIT => -- ORL C, /bit + if state=FETCH then + s_pc_inc_en <= "0001"; -- increment program-counter + s_nextstate <= EXEC1; + elsif state=EXEC1 then + s_adr_mux <= "1000"; -- address = rom_data_i + s_nextstate <= EXEC2; + elsif state=EXEC2 then + s_bdata_mux <= "1010"; -- bdata = not (s_bit_data or cy) + s_regs_wr_en <= "110"; -- write one bit (autmatically CY) + s_pc_inc_en <= "0001"; -- increment program-counter + s_nextstate <= FETCH; + end if; + + --------------------------------------------------------------------- + + when IC_POP => -- POP direct + if state=FETCH then + s_adr_mux <= "0101"; -- address = SP + s_pc_inc_en <= "0001"; -- increment program-counter + s_nextstate <= EXEC1; + elsif state=EXEC1 then + s_adr_mux <= "1000"; -- address = rom_data_i + s_data_mux <= "0100"; -- data = s_reg_data + s_regs_wr_en <= "101"; -- write one byte and decrement SP + s_pc_inc_en <= "0001"; -- increment program-counter + s_nextstate <= FETCH; + end if; + + --------------------------------------------------------------------- + + when IC_PUSH => -- PUSH direct + if state=FETCH then + s_regs_wr_en <= "001"; -- increment SP + s_pc_inc_en <= "0001"; -- increment program-counter + s_nextstate <= EXEC1; + elsif state=EXEC1 then + s_adr_mux <= "1000"; -- address = rom_data_i + s_nextstate <= EXEC2; + elsif state=EXEC2 then + s_adr_mux <= "0101"; -- address = SP + s_data_mux <= "0100"; -- data = s_reg_data + s_regs_wr_en <= "100"; -- write one byte + s_pc_inc_en <= "0001"; -- increment program-counter + s_nextstate <= FETCH; + end if; + + --------------------------------------------------------------------- + + when IC_RET => -- RET + if state=FETCH then + s_adr_mux <= "0101"; -- adress = SP + s_regs_wr_en <= "001"; -- decrement stackpointer + s_nextstate <= EXEC1; + elsif state=EXEC1 then + s_help_en <= "0011"; -- save data for PC-high + s_adr_mux <= "0101"; -- adress = SP + s_nextstate <= EXEC2; + elsif state=EXEC2 then + s_regs_wr_en <= "001"; -- decrement stackpointer + s_pc_inc_en <= "1000"; -- reload program-counter + s_nextstate <= FETCH; + end if; + + --------------------------------------------------------------------- + + when IC_RETI => -- RETI + if state=FETCH then + s_adr_mux <= "0101"; -- adress = SP + s_regs_wr_en <= "001"; -- decrement stackpointer + s_nextstate <= EXEC1; + elsif state=EXEC1 then + s_help_en <= "0011"; -- save data for PC-high + s_adr_mux <= "0101"; + s_nextstate <= EXEC2; + elsif state=EXEC2 then + if s_inthigh='1' then -- an high priority interrupt is ending + s_inthigh_en <= '1'; + s_inthigh_d <= '0'; + s_ext0isrh_d <= '0'; + s_ext0isrh_en <= '1'; + s_ext1isrh_d <= '0'; + s_ext1isrh_en <= '1'; + elsif s_intlow='1' then -- an low priority interrupt is ending + s_intlow_en <= '1'; + s_intlow_d <= '0'; + s_ext0isr_d <= '0'; + s_ext0isr_en <= '1'; + s_ext1isr_d <= '0'; + s_ext1isr_en <= '1'; + else -- no interrupt was started + NULL; -- => normal RET command + end if; + s_regs_wr_en <= "001"; -- decrement stackpointer + s_pc_inc_en <= "1000"; -- reload program-counter + s_nextstate <= FETCH; + end if; + + --------------------------------------------------------------------- + + when IC_RL_A => -- RL A + alu_cmd_o <= RL_ACC; -- rotate ACC left + s_data_mux <= "0011"; -- data = aludata_i + s_regs_wr_en <= "010"; -- write ACC + s_pc_inc_en <= "0001"; -- increment program-counter + s_nextstate <= FETCH; + + --------------------------------------------------------------------- + + when IC_RLC_A => -- RLC A + alu_cmd_o <= RLC_ACC; -- rotate ACC with CY left + s_data_mux <= "0011"; -- data = aludata_i + s_regs_wr_en <= "111"; -- write ACC and CY (special operation) + s_pc_inc_en <= "0001"; -- increment program-counter + s_nextstate <= FETCH; + + --------------------------------------------------------------------- + + when IC_RR_A => -- RR A + alu_cmd_o <= RR_ACC; -- rotate ACC right + s_data_mux <= "0011"; -- data = aludata_i + s_regs_wr_en <= "010"; -- write ACC + s_pc_inc_en <= "0001"; -- increment program-counter + s_nextstate <= FETCH; + + --------------------------------------------------------------------- + + when IC_RRC_A => -- RRC A + alu_cmd_o <= RRC_ACC; -- rotate ACC with CY right + s_data_mux <= "0011"; -- data = aludata_i + s_regs_wr_en <= "111"; -- write ACC and CY (special operation) + s_pc_inc_en <= "0001"; -- increment program-counter + s_nextstate <= FETCH; + + --------------------------------------------------------------------- + + when IC_SETB_C => -- SETB C + s_adr_mux <= "1011"; -- adress of CY + s_bdata_mux <= "1011"; -- bdata = 1 + s_regs_wr_en <= "110"; -- write one bit + s_pc_inc_en <= "0001"; -- increment program-counter + s_nextstate <= FETCH; + + --------------------------------------------------------------------- + + when IC_SETB_BIT => -- SETB bit + if state=FETCH then + s_pc_inc_en <= "0001"; -- increment program-counter + s_nextstate <= EXEC1; + elsif state=EXEC1 then + s_adr_mux <= "1000"; -- byte adress + s_bdata_mux <= "1011"; -- bdata = 1 + s_regs_wr_en <= "110"; -- write one bit + s_pc_inc_en <= "0001"; -- increment program-counter + s_nextstate <= FETCH; + end if; + + --------------------------------------------------------------------- + + when IC_SJMP => -- SJMP rel + if state=FETCH then + s_pc_inc_en <= "0001"; -- increment program-counter + s_nextstate <= EXEC1; + elsif state=EXEC1 then + s_pc_inc_en <= "0010"; -- load program-counter + s_nextstate <= FETCH; + end if; + + --------------------------------------------------------------------- + + when IC_SUBB_A_RR => -- SUBB A,Rr + if state=FETCH then + s_adr_mux <= "0110"; -- address = rr-address + s_nextstate <= EXEC1; + elsif state=EXEC1 then + alu_cmd_o <= SUB_ACC_RAM; -- subtraction command (ACC - RAM_DATA) + s_data_mux <= "0011"; -- data = aludata_i + s_regs_wr_en <= "011"; -- write ACC and CY,OV,AC + s_pc_inc_en <= "0001"; -- increment program-counter + s_nextstate <= FETCH; + end if; + + --------------------------------------------------------------------- + when IC_SUBB_A_D => -- SUBB A, direct + if state=FETCH then + s_pc_inc_en <= "0001"; -- increment program-counter + s_nextstate <= EXEC1; + elsif state=EXEC1 then + s_adr_mux <= "1000"; -- address = rom_data_i + s_nextstate <= EXEC2; + elsif state=EXEC2 then + alu_cmd_o <= SUB_ACC_RAM; -- subtraction command (ACC - RAM_DATA) + s_data_mux <= "0011"; -- data = aludata_i + s_regs_wr_en <= "011"; -- write ACC and CY,OV,AC + s_pc_inc_en <= "0001"; -- increment program-counter + s_nextstate <= FETCH; + end if; + + --------------------------------------------------------------------- + when IC_SUBB_A_ATRI => -- SUBB A,@Ri + if state=FETCH then + s_adr_mux <= "0111"; -- address = Ri-register + s_nextstate <= EXEC1; + elsif state=EXEC1 then + alu_cmd_o <= SUB_ACC_RAM; -- subtraction command (ACC - RAM_DATA) + s_data_mux <= "0011"; -- data = aludata_i + s_regs_wr_en <= "011"; -- write ACC and CY,OV,AC + s_pc_inc_en <= "0001"; -- increment program-counter + s_nextstate <= FETCH; + end if; + + --------------------------------------------------------------------- + + when IC_SUBB_A_DATA => -- SUBB A, DATA + if state=FETCH then + s_pc_inc_en <= "0001"; -- increment program-counter + s_nextstate <= EXEC1; + elsif state=EXEC1 then + s_data_mux <= "0011"; -- data = aludata_i + s_regs_wr_en <= "011"; -- write ACC and CY,OV,AC + alu_cmd_o <= SUB_ACC_ROM; -- subtraction command (ACC-ROM_DATA_I) + s_pc_inc_en <= "0001"; -- increment program-counter + s_nextstate <= FETCH; + end if; + + --------------------------------------------------------------------- + + when IC_SWAP_A => -- SWAP A + s_data_mux <= "0111"; -- data = acc(3 downto 0) acc(7 downto 4) + s_regs_wr_en <= "010"; -- write ACC + s_pc_inc_en <= "0001"; -- increment program-counter + s_nextstate <= FETCH; + + --------------------------------------------------------------------- + + when IC_XCH_A_RR => -- XCH A,Rr + if state=FETCH then + s_adr_mux <= "0110"; -- address = rr-address + s_nextstate <= EXEC1; + elsif state=EXEC1 then + s_adr_mux <= "0110"; -- address = rr-address + s_help_en <= "0011"; -- help = s_reg_data + s_data_mux <= "0110"; -- data = ACC + s_regs_wr_en <= "100"; -- write ACC + s_nextstate <= EXEC2; + elsif state=EXEC2 then + s_data_mux <= "1000"; -- data = help + s_regs_wr_en <= "010"; -- write ACC + s_pc_inc_en <= "0001"; -- increment program-counter + s_nextstate <= FETCH; + end if; + + --------------------------------------------------------------------- + + when IC_XCH_A_D => -- XCH A, direct + if state=FETCH then + s_pc_inc_en <= "0001"; -- increment program-counter + s_nextstate <= EXEC1; + elsif state=EXEC1 then + s_adr_mux <= "1000"; -- address = rom_data_i + s_nextstate <= EXEC2; + elsif state=EXEC2 then + s_adr_mux <= "1000"; -- address = rom_data_i + s_help_en <= "0011"; -- help = s_reg_data + s_data_mux <= "0110"; -- data = ACC + s_regs_wr_en <= "100"; -- write one byte + s_nextstate <= EXEC3; + elsif state=EXEC3 then + s_data_mux <= "1000"; -- data = help; + s_regs_wr_en <= "010"; -- write ACC + s_pc_inc_en <= "0001"; -- increment program-counter + s_nextstate <= FETCH; + end if; + + --------------------------------------------------------------------- + + when IC_XCH_A_ATRI => -- XCH A,@Ri + if state=FETCH then + s_adr_mux <= "0111"; -- address = Ri-register + s_nextstate <= EXEC1; + elsif state=EXEC1 then + s_adr_mux <= "0111"; -- address = Ri-register + s_help_en <= "0011"; -- help = s_reg_data + s_data_mux <= "0110"; -- data = ACC + s_regs_wr_en <= "100"; -- write one byte + s_nextstate <= EXEC2; + elsif state=EXEC2 then + s_data_mux <= "1000"; -- data = help; + s_regs_wr_en <= "010"; -- write ACC + s_pc_inc_en <= "0001"; -- increment program-counter + s_nextstate <= FETCH; + end if; + + --------------------------------------------------------------------- + + when IC_XCHD_A_ATRI => -- XCHD A,@Ri + if state=FETCH then + s_adr_mux <= "0111"; -- address = Ri-register + s_help_en <= "1010"; -- s_help = acc + s_nextstate <= EXEC1; + elsif state=EXEC1 then + s_adr_mux <= "0111"; -- address = Ri-register + s_data_mux <= "1010"; -- data = acc(7..4) & s_reg_data(3..0) + s_regs_wr_en <= "010"; -- write ACC + s_nextstate <= EXEC2; + elsif state=EXEC2 then + s_adr_mux <= "0111"; -- address = Ri-register + s_data_mux <= "1001"; -- data = s_reg_data(7..4) & s_help(3..0) + s_regs_wr_en <= "100"; -- write one byte + s_pc_inc_en <= "0001"; -- increment program-counter + s_nextstate <= FETCH; + end if; + + --------------------------------------------------------------------- + + when IC_XRL_A_RR => -- XRL A,Rr + if state=FETCH then + s_adr_mux <= "0110"; -- address = rr-address + s_nextstate <= EXEC1; + elsif state=EXEC1 then + alu_cmd_o <= XOR_RAM_ACC; -- XOR command (ACC v RAM_DATA) + s_data_mux <= "0011"; -- data = aludata_i + s_regs_wr_en <= "010"; -- write ACC + s_pc_inc_en <= "0001"; -- increment program-counter + s_nextstate <= FETCH; + end if; + + --------------------------------------------------------------------- + when IC_XRL_A_D => -- XRL A, direct + if state=FETCH then + s_pc_inc_en <= "0001"; -- increment program-counter + s_nextstate <= EXEC1; + elsif state=EXEC1 then + s_adr_mux <= "1000"; + s_nextstate <= EXEC2; + elsif state=EXEC2 then + alu_cmd_o <= XOR_RAM_ACC; -- XOR command (ACC v RAM_DATA) + s_data_mux <= "0011"; -- data = aludata_i + s_regs_wr_en <= "010"; -- write ACC + s_pc_inc_en <= "0001"; -- increment program-counter + s_nextstate <= FETCH; + end if; + + --------------------------------------------------------------------- + when IC_XRL_A_ATRI => -- XRL A,@Ri + if state=FETCH then + s_adr_mux <= "0111"; -- address = Ri-register + s_nextstate <= EXEC1; + elsif state=EXEC1 then + alu_cmd_o <= XOR_RAM_ACC; -- XOR command (ACC v RAM_DATA) + s_data_mux <= "0011"; -- data = aludata_i + s_regs_wr_en <= "010"; -- write ACC + s_pc_inc_en <= "0001"; -- increment program-counter + s_nextstate <= FETCH; + end if; + + --------------------------------------------------------------------- + when IC_XRL_A_DATA => -- XRL A, data + if state=FETCH then + s_pc_inc_en <= "0001"; -- increment program-counter + s_nextstate <= EXEC1; + elsif state=EXEC1 then + s_data_mux <= "0011"; -- data = aludata_i + s_regs_wr_en <= "010"; -- write ACC + alu_cmd_o <= XOR_ROM_ACC; -- XOR command (ACC v ROM_DATA_I) + s_pc_inc_en <= "0001"; -- increment program-counter + s_nextstate <= FETCH; + end if; + + --------------------------------------------------------------------- + when IC_XRL_D_A => -- XRL direct, A + if state=FETCH then + s_pc_inc_en <= "0001"; -- increment program-counter + s_nextstate <= EXEC1; + elsif state=EXEC1 then + s_adr_mux <= "1000"; + s_nextstate <= EXEC2; + elsif state=EXEC2 then + s_adr_mux <= "1000"; + s_data_mux <= "0011"; -- data = aludata_i + s_regs_wr_en <= "100"; -- write one byte + alu_cmd_o <= XOR_RAM_ACC; -- XOR command (ACC v RAM_DATA) + s_pc_inc_en <= "0001"; -- increment program-counter + s_nextstate <= FETCH; + end if; + + --------------------------------------------------------------------- + + when IC_XRL_D_DATA => -- XRL direct, DATA + if state=FETCH then + s_pc_inc_en <= "0001"; -- increment program-counter + s_nextstate <= EXEC1; + elsif state=EXEC1 then + s_help_en <= "0001"; + s_adr_mux <= "1000"; + s_pc_inc_en <= "0001"; -- increment program-counter + s_nextstate <= EXEC2; + elsif state=EXEC2 then + s_adr_mux <= "1010"; + s_data_mux <= "0011"; -- data = aludata_i + alu_cmd_o <= XOR_ROM_RAM; -- XOR command (ROM_DATA_I v RAM_DATA) + s_regs_wr_en <= "100"; -- write one byte + s_pc_inc_en <= "0001"; -- increment program-counter + s_nextstate <= FETCH; + end if; + + --------------------------------------------------------------------- + + when others => + s_nextstate <= FETCH; + end case; + end if; + end if; + end process p_state; + +end rtl; diff --git a/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/8051/control_fsm_rtl_cfg.vhd b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/8051/control_fsm_rtl_cfg.vhd new file mode 100644 index 0000000000000000000000000000000000000000..1115d26c5f95cbe3a5fbbf053dee5c5bc7ca0a94 --- /dev/null +++ b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/8051/control_fsm_rtl_cfg.vhd @@ -0,0 +1,69 @@ +------------------------------------------------------------------------------- +-- -- +-- X X XXXXXX XXXXXX XXXXXX XXXXXX X -- +-- XX XX X X X X X X X XX -- +-- X X X X X X X X X X X X -- +-- X X X X X X X X X X X X -- +-- X X X X XXXXXX X X XXXXXX X -- +-- X X X X X X X X X -- +-- X X X X X X X X X -- +-- X X X X X X X X X X -- +-- X X XXXXXX XXXXXX XXXXXX XXXXXX X -- +-- -- +-- -- +-- O R E G A N O S Y S T E M S -- +-- -- +-- Design & Consulting -- +-- -- +------------------------------------------------------------------------------- +-- -- +-- Web: http://www.oregano.at/ -- +-- -- +-- Contact: mc8051@oregano.at -- +-- -- +------------------------------------------------------------------------------- +-- -- +-- MC8051 - VHDL 8051 Microcontroller IP Core -- +-- Copyright (C) 2001 OREGANO SYSTEMS -- +-- -- +-- This library is free software; you can redistribute it and/or -- +-- modify it under the terms of the GNU Lesser General Public -- +-- License as published by the Free Software Foundation; either -- +-- version 2.1 of the License, or (at your option) any later version. -- +-- -- +-- This library is distributed in the hope that it will be useful, -- +-- but WITHOUT ANY WARRANTY; without even the implied warranty of -- +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -- +-- Lesser General Public License for more details. -- +-- -- +-- Full details of the license can be found in the file LGPL.TXT. -- +-- -- +-- You should have received a copy of the GNU Lesser General Public -- +-- License along with this library; if not, write to the Free Software -- +-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -- +-- -- +------------------------------------------------------------------------------- +-- +-- +-- Author: Helmut Mayrhofer +-- +-- Filename: control_fsm_rtl_cfg.vhd +-- +-- Date of Creation: Mon Aug 9 12:14:48 1999 +-- +-- Version: $Revision: 1.4 $ +-- +-- Date of Latest Version: $Date: 2002-01-07 12:17:44 $ +-- +-- +-- Description: Decode instruction and execute it. Pure combinational +-- descripton of the finite state machine. +-- +-- +-- +-- +------------------------------------------------------------------------------- +configuration control_fsm_rtl_cfg of control_fsm is + for rtl + end for; +end control_fsm_rtl_cfg; diff --git a/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/8051/control_mem_.vhd b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/8051/control_mem_.vhd new file mode 100644 index 0000000000000000000000000000000000000000..465e625220cf798fec7654b603585de4f5228cd3 --- /dev/null +++ b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/8051/control_mem_.vhd @@ -0,0 +1,206 @@ +------------------------------------------------------------------------------- +-- -- +-- X X XXXXXX XXXXXX XXXXXX XXXXXX X -- +-- XX XX X X X X X X X XX -- +-- X X X X X X X X X X X X -- +-- X X X X X X X X X X X X -- +-- X X X X XXXXXX X X XXXXXX X -- +-- X X X X X X X X X -- +-- X X X X X X X X X -- +-- X X X X X X X X X X -- +-- X X XXXXXX XXXXXX XXXXXX XXXXXX X -- +-- -- +-- -- +-- O R E G A N O S Y S T E M S -- +-- -- +-- Design & Consulting -- +-- -- +------------------------------------------------------------------------------- +-- -- +-- Web: http://www.oregano.at/ -- +-- -- +-- Contact: mc8051@oregano.at -- +-- -- +------------------------------------------------------------------------------- +-- -- +-- MC8051 - VHDL 8051 Microcontroller IP Core -- +-- Copyright (C) 2001 OREGANO SYSTEMS -- +-- -- +-- This library is free software; you can redistribute it and/or -- +-- modify it under the terms of the GNU Lesser General Public -- +-- License as published by the Free Software Foundation; either -- +-- version 2.1 of the License, or (at your option) any later version. -- +-- -- +-- This library is distributed in the hope that it will be useful, -- +-- but WITHOUT ANY WARRANTY; without even the implied warranty of -- +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -- +-- Lesser General Public License for more details. -- +-- -- +-- Full details of the license can be found in the file LGPL.TXT. -- +-- -- +-- You should have received a copy of the GNU Lesser General Public -- +-- License along with this library; if not, write to the Free Software -- +-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -- +-- -- +------------------------------------------------------------------------------- +-- +-- +-- Author: Helmut Mayrhofer +-- +-- Filename: control_mem_.vhd +-- +-- Date of Creation: Mon Aug 9 12:14:48 1999 +-- +-- Version: $Revision: 1.6 $ +-- +-- Date of Latest Version: $Date: 2006-09-07 09:59:09 $ +-- +-- +-- Description: Describe all sequential funcitonality like read from +-- special function registers, observe interrupt sources, +-- write to special function registers, and read or write +-- to the bit addressable memory area. +-- +-- +-- +-- +------------------------------------------------------------------------------- +library IEEE; +library work; +use IEEE.std_logic_1164.all; +use IEEE.std_logic_arith.all; +use work.mc8051_p.all; + + +entity control_mem is + + port (pc_o : out std_logic_vector(15 downto 0); -- Programmcounter = + -- ROM-adress + rom_data_i : in std_logic_vector(7 downto 0); -- data input from ROM + ram_data_o : out std_logic_vector(7 downto 0); -- data output to + -- internal RAM + ram_data_i : in std_logic_vector(7 downto 0); -- data input from + -- internal RAM + ram_adr_o : out std_logic_vector(6 downto 0); -- internal RAM-adress + reg_data_o : out std_logic_vector(7 downto 0); -- data for ALU + ram_wr_o : out std_logic; -- read (0) / write (1) + -- internal RAM + cy_o : out std_logic_vector(1 downto 0); -- Carry Flag + ov_o : out std_logic; -- Overflow Flag + ram_en_o : out std_logic; -- RAM-block enable + aludata_i : in std_logic_vector (7 downto 0); -- ALU result + aludatb_i : in std_logic_vector (7 downto 0); -- 2nd ALU result + acc_o : out std_logic_vector (7 downto 0); -- ACC register + new_cy_i : in std_logic_vector(1 downto 0); -- CY result of ALU + new_ov_i : in std_logic; -- OV result of ALU + reset : in std_logic; -- reset signal + clk : in std_logic; -- clock signal + cen : in std_logic; -- clock enable + int0_i : in std_logic_vector(C_IMPL_N_EXT-1 downto 0); -- ext.Int + int1_i : in std_logic_vector(C_IMPL_N_EXT-1 downto 0); -- ext.Int + + p0_i : in std_logic_vector(7 downto 0); -- IO-port0 + p1_i : in std_logic_vector(7 downto 0); -- IO-port1 + p2_i : in std_logic_vector(7 downto 0); -- IO-port2 + p3_i : in std_logic_vector(7 downto 0); -- IO-port3 + + p0_o : out std_logic_vector(7 downto 0); -- IO-port0 + p1_o : out std_logic_vector(7 downto 0); -- IO-port1 + p2_o : out std_logic_vector(7 downto 0); -- IO-port2 + p3_o : out std_logic_vector(7 downto 0); -- IO-port3 + + -- Signals to and from the SIUs + + -- "1" starts serial transmission in SIU + all_trans_o : out std_logic_vector(C_IMPL_N_SIU-1 downto 0); + -- RI,SM0,SM1,SM2,REN,TB8 + all_scon_o : out std_logic_vector(6*C_IMPL_N_SIU-1 downto 0); + -- data buffer for SIU + all_sbuf_o : out std_logic_vector(8*C_IMPL_N_SIU-1 downto 0); + -- baud rate for SIU in PCON + all_smod_o : out std_logic_vector(C_IMPL_N_SIU-1 downto 0); + -- RB8, TI, RI of SIU + all_scon_i : in std_logic_vector(3*C_IMPL_N_SIU-1 downto 0); + -- int. data buffer of SIU + all_sbuf_i : in std_logic_vector(8*C_IMPL_N_SIU-1 downto 0); + + -- signals to and from the timer/counters + + -- timer run flag0 of T/C + all_tcon_tr0_o : out std_logic_vector(C_IMPL_N_TMR-1 downto 0); + -- timer run flag1 of T/C + all_tcon_tr1_o : out std_logic_vector(C_IMPL_N_TMR-1 downto 0); + -- TMOD for T/C + all_tmod_o : out std_logic_vector(8*C_IMPL_N_TMR-1 downto 0); + -- user reload value for T/C + all_reload_o : out std_logic_vector(8*C_IMPL_N_TMR-1 downto 0); + -- reload enable for T/C + all_wt_o : out std_logic_vector(2*C_IMPL_N_TMR-1 downto 0); + -- reload target for T/C + all_wt_en_o : out std_logic_vector(C_IMPL_N_TMR-1 downto 0); + -- timer OF flag0 of T/C + all_tf0_i : in std_logic_vector(C_IMPL_N_TMR-1 downto 0); + -- timer OF flag1 of T/C + all_tf1_i : in std_logic_vector(C_IMPL_N_TMR-1 downto 0); + -- count value of T/C + all_tl0_i : in std_logic_vector(8*C_IMPL_N_TMR-1 downto 0); + -- count value of T/C + all_tl1_i : in std_logic_vector(8*C_IMPL_N_TMR-1 downto 0); + -- count value of T/C + all_th0_i : in std_logic_vector(8*C_IMPL_N_TMR-1 downto 0); + -- count value of T/C + all_th1_i : in std_logic_vector(8*C_IMPL_N_TMR-1 downto 0); + + -- signals from/to the state-machine + + state_o : out t_state; -- actual state + help_o : out std_logic_vector(7 downto 0); -- general help-reg + bit_data_o : out std_logic; -- bitdata from regs + command_o : out std_logic_vector (7 downto 0); -- actual command + inthigh_o : out std_logic; -- high priority int is running + intlow_o : out std_logic; -- low priority int is running + intpre_o : out std_logic; -- an interrupt must start + intpre2_o : out std_logic; -- prepare for interrupt + intblock_o : out std_logic; -- interrupt delay at RETI, IE, IP + ti_o : out std_logic; + ri_o : out std_logic; + ie0_o : out std_logic; + ie1_o : out std_logic; + tf0_o : out std_logic; + tf1_o : out std_logic; + psw_o : out std_logic_vector(7 downto 0); + ie_o : out std_logic_vector(7 downto 0); + ip_o : out std_logic_vector(7 downto 0); + adrx_o : out std_logic_vector(15 downto 0); -- ext. RAM + datax_o : out std_logic_vector(7 downto 0); -- ext. RAM + wrx_o : out std_logic; -- ext. RAM + memx_o : out std_logic; + + datax_i : in std_logic_vector(7 downto 0); -- ext. RAM + pc_inc_en_i : in std_logic_vector (3 downto 0); + nextstate_i : in t_state; -- enable signal for state + adr_mux_i : in std_logic_vector (3 downto 0); + adrx_mux_i : in std_logic_vector (1 downto 0); + wrx_mux_i : in std_logic; + data_mux_i : in std_logic_vector (3 downto 0); + bdata_mux_i : in std_logic_vector (3 downto 0); + regs_wr_en_i : in std_logic_vector (2 downto 0); + help_en_i : in std_logic_vector (3 downto 0); + help16_en_i : in std_logic_vector (1 downto 0); + helpb_en_i : in std_logic; + inthigh_en_i : in std_logic; + intlow_en_i : in std_logic; + intpre2_en_i : in std_logic; + inthigh_d_i : in std_logic; + intlow_d_i : in std_logic; + intpre2_d_i : in std_logic; + ext0isr_d_i : in std_logic; + ext1isr_d_i : in std_logic; + ext0isrh_d_i : in std_logic; + ext1isrh_d_i : in std_logic; + ext0isr_en_i : in std_logic; + ext1isr_en_i : in std_logic; + ext0isrh_en_i : in std_logic; + ext1isrh_en_i : in std_logic); + +end control_mem; diff --git a/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/8051/control_mem_rtl.vhd b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/8051/control_mem_rtl.vhd new file mode 100644 index 0000000000000000000000000000000000000000..15169a363f95dcabfec65bedded46e2ab49eb50e --- /dev/null +++ b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/8051/control_mem_rtl.vhd @@ -0,0 +1,1148 @@ +------------------------------------------------------------------------------- +-- -- +-- X X XXXXXX XXXXXX XXXXXX XXXXXX X -- +-- XX XX X X X X X X X XX -- +-- X X X X X X X X X X X X -- +-- X X X X X X X X X X X X -- +-- X X X X XXXXXX X X XXXXXX X -- +-- X X X X X X X X X -- +-- X X X X X X X X X -- +-- X X X X X X X X X X -- +-- X X XXXXXX XXXXXX XXXXXX XXXXXX X -- +-- -- +-- -- +-- O R E G A N O S Y S T E M S -- +-- -- +-- Design & Consulting -- +-- -- +------------------------------------------------------------------------------- +-- -- +-- Web: http://www.oregano.at/ -- +-- -- +-- Contact: mc8051@oregano.at -- +-- -- +------------------------------------------------------------------------------- +-- -- +-- MC8051 - VHDL 8051 Microcontroller IP Core -- +-- Copyright (C) 2001 OREGANO SYSTEMS -- +-- -- +-- This library is free software; you can redistribute it and/or -- +-- modify it under the terms of the GNU Lesser General Public -- +-- License as published by the Free Software Foundation; either -- +-- version 2.1 of the License, or (at your option) any later version. -- +-- -- +-- This library is distributed in the hope that it will be useful, -- +-- but WITHOUT ANY WARRANTY; without even the implied warranty of -- +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -- +-- Lesser General Public License for more details. -- +-- -- +-- Full details of the license can be found in the file LGPL.TXT. -- +-- -- +-- You should have received a copy of the GNU Lesser General Public -- +-- License along with this library; if not, write to the Free Software -- +-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -- +-- -- +------------------------------------------------------------------------------- +-- +-- +-- Author: Helmut Mayrhofer +-- +-- Filename: control_mem_rtl.vhd +-- +-- Date of Creation: Mon Aug 9 12:14:48 1999 +-- +-- Version: $Revision: 1.11 $ +-- +-- Date of Latest Version: $Date: 2010-03-24 10:20:48 $ +-- +-- +-- Description: Describe all sequential funcitonality like read from +-- special function registers, observe interrupt sources, +-- write to special function registers, and read or write +-- to the bit addressable memory area. +-- +-- +-- +-- +------------------------------------------------------------------------------- +architecture rtl of control_mem is + + + type t_gprbit is array (15 downto 0) of unsigned(7 downto 0); + subtype muxint is integer range C_IMPL_N_TMR-1 downto 0; + + signal s_help: unsigned (7 downto 0); -- general help-register + signal s_help16: unsigned (15 downto 0); -- 16 bit help-register + signal s_helpb : std_logic; -- general help-bit + signal s_ir: unsigned (7 downto 0); -- reg for saving the command + signal gprbit: t_gprbit; -- bitadressable general purpose RAM + signal s_r0_b0: unsigned (7 downto 0); -- Register R0 / Bank 0 + signal s_r1_b0: unsigned (7 downto 0); -- Register R1 / Bank 0 + signal s_r0_b1: unsigned (7 downto 0); -- Register R0 / Bank 1 + signal s_r1_b1: unsigned (7 downto 0); -- Register R1 / Bank 1 + signal s_r0_b2: unsigned (7 downto 0); -- Register R0 / Bank 2 + signal s_r1_b2: unsigned (7 downto 0); -- Register R1 / Bank 2 + signal s_r0_b3: unsigned (7 downto 0); -- Register R0 / Bank 3 + signal s_r1_b3: unsigned (7 downto 0); -- Register R1 / Bank 3 + signal s_reg_data: unsigned (7 downto 0); -- equals reg_data_o + Signal state: t_state; -- actual state + signal s_command: std_logic_vector (7 downto 0); + + signal s_pc_inc_en : std_logic_vector (3 downto 0); + signal s_regs_wr_en : std_logic_vector (2 downto 0); + signal s_data_mux : std_logic_vector (3 downto 0); + signal s_bdata_mux : std_logic_vector (3 downto 0); + signal s_adr_mux : std_logic_vector (3 downto 0); + signal s_adrx_mux : std_logic_vector (1 downto 0); + signal s_help_en : std_logic_vector (3 downto 0); + signal s_help16_en : std_logic_vector (1 downto 0); + signal s_helpb_en : std_logic; + signal s_intpre2_d : std_logic; + signal s_intpre2_en: std_logic; + signal s_intlow_d : std_logic; + signal s_intlow_en : std_logic; + signal s_inthigh_d : std_logic; + signal s_inthigh_en: std_logic; + signal s_ext0isr_d : std_logic; + signal s_ext0isrh_d : std_logic; + signal s_ext1isr_d : std_logic; + signal s_ext1isrh_d : std_logic; + + signal s_nextstate : t_state; -- enable signal for state + + signal s_bit_data : std_logic; + signal s_intpre: std_logic; -- an interrupt must start + signal s_intpre2: std_logic; -- prepare for interrupt + signal s_inthigh: std_logic; -- high priority int is running + signal s_intlow: std_logic; -- low priority int is running + signal s_intblock: std_logic; -- interrupt delay at RETI, IE, IP + signal s_intblock_o: std_logic; -- CK, CV: intblock_o signal for internal use + + signal s_int0_edge : t_ext_l; + signal s_int1_edge : t_ext_l; + + signal s_tf0_edge : t_tmr_l; + signal s_tf1_edge : t_tmr_l; + signal s_ri_edge : t_siu_l; + signal s_ti_edge : t_siu_l; + signal s_smodreg : t_siu_l; + signal s_tl0 : t_tmr_us; + signal s_tl1 : t_tmr_us; + signal s_th0 : t_tmr_us; + signal s_th1 : t_tmr_us; + signal s_sbufi : t_siu_us; + signal s_reload : t_tmr_us; + signal s_wt : t_tmr_us2; + + signal s_tf1 : std_logic; + signal s_tf0 : std_logic; + signal s_ie1 : std_logic; + signal s_ie0 : std_logic; + + signal s_ri : std_logic; + signal s_ti : std_logic; + signal s_rb8 : std_logic; + signal s_tb8 : std_logic; + signal s_ren : std_logic; + signal s_sm2 : std_logic; + signal s_sm1 : std_logic; + signal s_sm0 : std_logic; + signal s_smod : std_logic; + + signal s_int0_h1 : t_ext_l; -- help-bit for edge detection + signal s_int0_h2 : t_ext_l; + signal s_int0_h3 : t_ext_l; + signal s_int1_h1 : t_ext_l; + signal s_int1_h2 : t_ext_l; + signal s_int1_h3 : t_ext_l; + + signal s_tf0_h1,s_tf0_h2 : t_tmr_l; + signal s_tf1_h1,s_tf1_h2 : t_tmr_l; + signal s_ri_h1,s_ri_h2 : t_siu_l; + signal s_ti_h1,s_ti_h2 : t_siu_l; + + signal s_tsel : muxint; + signal s_ssel : muxint; + + signal s_p : std_logic; + + signal s_p0 : std_logic_vector(7 downto 0); + signal s_p1 : std_logic_vector(7 downto 0); + signal s_p2 : std_logic_vector(7 downto 0); + signal s_p3 : std_logic_vector(7 downto 0); + + signal pc: unsigned(15 downto 0); -- program counter register + signal pc_comb: unsigned(15 downto 0); -- program counter + signal pc_plus1: unsigned(15 downto 0); -- program counter + 1 + signal pc_plus2: unsigned(15 downto 0); -- program counter + 2 + + signal s_data : unsigned(7 downto 0); + signal s_adr : unsigned(7 downto 0); + signal s_preadr : unsigned(7 downto 0); + signal s_bdata : std_logic; + signal s_rr_adr : unsigned (7 downto 0); + signal s_ri_adr : std_logic_vector (7 downto 0); + signal s_ri_data : unsigned (7 downto 0); + + -- 8051 standard special-function-register (SFR) + + signal p0: unsigned(7 downto 0); + signal sp: unsigned(7 downto 0); + signal dpl: unsigned(7 downto 0); + signal dph: unsigned(7 downto 0); + signal pcon: unsigned(3 downto 0); + signal tcon: t_tmr_lv; + signal tmod: t_tmr_us; + signal p1: unsigned(7 downto 0); + signal scon: t_siu_lv; + signal sbuf: t_siu_us; + signal p2: unsigned(7 downto 0); + signal ie: std_logic_vector(7 downto 0); + signal p3: unsigned(7 downto 0); + signal ip: std_logic_vector(7 downto 0); + signal psw: std_logic_vector(7 downto 0); + signal acc: unsigned(7 downto 0); + signal b: unsigned(7 downto 0); + + -- 8051 extended special-function-register + + signal tsel: unsigned(7 downto 0); -- select a Timer-Unit + signal ssel: unsigned(7 downto 0); -- select a SIU-Unit + + alias CY : std_logic is psw(7); + alias AC : std_logic is psw(6); + alias OV : std_logic is psw(2); + alias EA: std_logic is ie(7); + alias ES: std_logic is ie(4); + alias ET1: std_logic is ie(3); + alias EX1: std_logic is ie(2); + alias ET0: std_logic is ie(1); + alias EX0: std_logic is ie(0); + alias PS0: std_logic is ip(4); + alias PT1: std_logic is ip(3); + alias PX1: std_logic is ip(2); + alias PT0: std_logic is ip(1); + alias PX0: std_logic is ip(0); + +begin + + -- some simple assignments + + pc_o <= std_logic_vector(pc_comb); + pc_plus1 <= pc + conv_unsigned(1,1); + pc_plus2 <= pc + conv_unsigned(2,2); + ram_adr_o <= std_logic_vector(s_adr(6 downto 0)); + reg_data_o <= std_logic_vector(s_reg_data); + ram_data_o <= std_logic_vector(s_data); + acc_o <= std_logic_vector(acc); + cy_o(1) <= cy; + ov_o <= ov; + cy_o(0) <= ac; + + ie_o <= ie; + ip_o <= ip; + psw_o <= psw; + state_o <= state; + command_o <= s_command; + ri_o <= s_ri; + ti_o <= s_ti; + help_o <= std_logic_vector(s_help); + bit_data_o <= s_bit_data; + intpre_o <= s_intpre; + intpre2_o <= s_intpre2; + inthigh_o <= s_inthigh; + intlow_o <= s_intlow; + tf1_o <= s_tf1; + tf0_o <= s_tf0; + ie1_o <= s_ie1; + ie0_o <= s_ie0; + + s_pc_inc_en <= pc_inc_en_i; + s_nextstate <= nextstate_i; + s_adr_mux <= adr_mux_i; + s_adrx_mux <= adrx_mux_i; + s_data_mux <= data_mux_i; + s_bdata_mux <= bdata_mux_i; + s_regs_wr_en <= regs_wr_en_i; + s_help_en <= help_en_i; + s_help16_en <= help16_en_i; + s_helpb_en <= helpb_en_i; + s_inthigh_en <= inthigh_en_i; + s_intlow_en <= intlow_en_i; + s_intpre2_en <= intpre2_en_i; + s_inthigh_d <= inthigh_d_i; + s_intlow_d <= intlow_d_i; + s_intpre2_d <= intpre2_d_i; + intblock_o <= s_intblock_o; -- CK, CV: assignment of intblock_o output + + s_tsel <= conv_integer(tsel) when tsel < C_IMPL_N_TMR + else conv_integer(0); -- selected timer unit is (not) implemented + s_ssel <= conv_integer(ssel) when ssel < C_IMPL_N_SIU + else conv_integer(0); -- selected siu unit is (not) implemented + + for_tmr: + for i in 0 to C_IMPL_N_TMR-1 generate + all_tcon_tr0_o(i) <= tcon(i)(4); + all_tcon_tr1_o(i) <= tcon(i)(6); + all_tmod_o((i*8)+7 downto i*8) <= std_logic_vector(tmod(i)); + s_tl0(i) <= unsigned(all_tl0_i((i*8)+7 downto i*8)); + s_tl1(i) <= unsigned(all_tl1_i((i*8)+7 downto i*8)); + s_th0(i) <= unsigned(all_th0_i((i*8)+7 downto i*8)); + s_th1(i) <= unsigned(all_th1_i((i*8)+7 downto i*8)); + all_reload_o((i*8)+7 downto i*8) <= std_logic_vector(s_reload(i)); + all_wt_o((i*2)+1 downto i*2) <= std_logic_vector(s_wt(i)); + end generate for_tmr; + + s_tf1 <= tcon(s_tsel)(7); + s_tf0 <= tcon(s_tsel)(5); + s_ie1 <= tcon(s_tsel)(3); + s_ie0 <= tcon(s_tsel)(1); + + for_siu: + for i in 0 to C_IMPL_N_SIU-1 generate + all_scon_o((6*i)+5) <= scon(i)(0); -- RI + all_scon_o((6*i)+4) <= scon(i)(7); -- SM0 + all_scon_o((6*i)+3) <= scon(i)(6); -- SM1 + all_scon_o((6*i)+2) <= scon(i)(5); -- SM2 + all_scon_o((6*i)+1) <= scon(i)(4); -- REN + all_scon_o(6*i) <= scon(i)(3); -- TB8 + all_smod_o(i) <= s_smodreg(i); -- SMOD + all_sbuf_o((8*i)+7 downto 8*i) <= std_logic_vector(sbuf(i)); + s_sbufi(i) <= unsigned(all_sbuf_i((i*8)+7 downto i*8)); + end generate for_siu; + + s_sm0 <= scon(s_ssel)(7); + s_sm1 <= scon(s_ssel)(6); + s_sm2 <= scon(s_ssel)(5); + s_ren <= scon(s_ssel)(4); + s_tb8 <= scon(s_ssel)(3); + s_rb8 <= all_scon_i((s_ssel*3)+2); + s_ti <= scon(s_ssel)(1); + s_ri <= scon(s_ssel)(0); + s_smod<= s_smodreg(s_ssel); + + p0_o <= std_logic_vector(p0); + p1_o <= std_logic_vector(p1); + p2_o <= std_logic_vector(p2); + p3_o <= std_logic_vector(p3); + + s_p <= acc(7) xor acc(6) xor acc(5) xor acc(4) xor + acc(3) xor acc(2) xor acc(1) xor acc(0); + -- P should be set, if the count + -- of 1 in the acc is even + + s_command <= rom_data_i when state=FETCH + else conv_std_logic_vector(s_ir,8); + + s_rr_adr <= unsigned((psw and "00011000") or (rom_data_i + and "00000111")); -- calculate registerdirect-adress + + s_ri_adr <= ((psw and "00011000") or (s_command(7 downto 0) and "00000001")); + + datax_o <= std_logic_vector(acc); + wrx_o <= wrx_mux_i; + + -- This logic ensures that a pending interrupt is not serviced if + -- a) RETI instruction is in progress, + -- b) any write to IE or IP register is in progress. + + --s_intblock <= --'1' when (std_logic_vector(s_ir) = RETI) or -- RETI in progress -- CK,CV: new logic for s_intblock inserted + + --(s_regs_wr_en = "100" and -- \ + -- (conv_integer(s_adr) = 16#B8# or -- | write to + -- conv_integer(s_adr) = 16#A8#) and -- | IE or IP + -- s_intpre2 = '0') or -- / + --(s_regs_wr_en = "110" and -- \ + -- (s_adr(7 downto 3) = conv_unsigned(21,5) or -- | bit access + -- s_adr(7 downto 3) = conv_unsigned(23,5)) and -- | to IE v IP + -- s_intpre2 = '0') else '0'; -- / + +-- s_intblock <= '1' when (std_logic_vector(s_command) = RETI) +-- else '0' when (s_nextstate = FETCH and (std_logic_vector(s_command) /= RETI)) +-- else s_intblock_o; + + process(s_command, s_regs_wr_en, s_adr, s_intpre2, s_intblock_o, s_nextstate) + + begin + + if (std_logic_vector(s_command) = RETI) -- ensure single instruction execution after RETI command + or + (s_regs_wr_en = "100" and -- register access to IP or I + (conv_integer(s_adr) = 16#B8# or conv_integer(s_adr) = 16#A8#) and + s_intpre2 = '0') + or + (s_regs_wr_en = "110" and -- bitr access to IE or IP + (s_adr(7 downto 3) = conv_unsigned(21,5) or s_adr(7 downto 3) = conv_unsigned(23,5)) and + s_intpre2 = '0') + then s_intblock <= '1'; + + elsif (s_nextstate = FETCH and (std_logic_vector(s_command) /= RETI)) + then s_intblock <= '0'; + + else s_intblock <= s_intblock_o; + + end if; + end process; -- CK,CV: end of logic insertion + + +------------------------------------------------------------------------------ +-- purpose: process to read SFR, bitadressable or normal RAM +-- inputs: s_adr,s_preadr,sp,dpl,dph,pcon,tcon,tmod,all_tl0_i, +-- all_tl1_i,all_th0_i,all_th1_i,s_p0,s_p1,all_scon_i,all_sbuf_i, +-- s_p2,ie,s_p3,ip,psw,acc,b,gprbit,ram_data_i +-- outputs: s_reg_data, s_bit_data +------------------------------------------------------------------------------ + + p_readram : process (s_preadr,s_p0,sp,dpl,dph,pcon,tcon,tmod,s_p1,scon,s_p2, + ie,s_p3,ip,psw,acc,b,gprbit,ram_data_i,s_r0_b0,s_r1_b0, + s_r0_b1,s_r1_b1,s_r0_b2,s_r1_b2,s_r0_b3,s_r1_b3, + s_smod,s_sm0,s_sm1,s_sm2,s_ren,s_tb8,s_rb8,s_ti,s_ri, + s_sbufi,s_th1,s_th0,s_ssel,s_tsel,s_tl1,s_tl0, + ssel,tsel) + begin + if s_preadr(7)='1' then + case conv_integer(s_preadr) is -- read one byte of a SFR + when 16#80# => s_reg_data <= unsigned(s_p0); + when 16#81# => s_reg_data <= sp; + when 16#82# => s_reg_data <= dpl; + when 16#83# => s_reg_data <= dph; + when 16#87# => + s_reg_data(7) <= s_smod; + s_reg_data(6 downto 4) <= "000"; + s_reg_data(3 downto 0) <= pcon; + when 16#88# => s_reg_data <= unsigned(tcon(s_tsel)); + when 16#89# => s_reg_data <= unsigned(tmod(s_tsel)); + when 16#8A# => s_reg_data <= s_tl0(s_tsel); + when 16#8B# => s_reg_data <= s_tl1(s_tsel); + when 16#8C# => s_reg_data <= s_th0(s_tsel); + when 16#8D# => s_reg_data <= s_th1(s_tsel); + when 16#8E# => s_reg_data <= tsel; + when 16#90# => s_reg_data <= unsigned(s_p1); + when 16#98# => + s_reg_data(0) <= s_ri; -- from SCON register + s_reg_data(1) <= s_ti; -- from SCON register + s_reg_data(2) <= s_rb8; -- read extern input!!! + s_reg_data(3) <= s_tb8; + s_reg_data(4) <= s_ren; + s_reg_data(5) <= s_sm2; + s_reg_data(6) <= s_sm1; + s_reg_data(7) <= s_sm0; + when 16#99# => s_reg_data <= s_sbufi(s_ssel); + when 16#9A# => s_reg_data <= ssel; + when 16#A0# => s_reg_data <= unsigned(s_p2); + when 16#A8# => s_reg_data <= unsigned(ie); + when 16#B0# => s_reg_data <= unsigned(s_p3); + when 16#B8# => s_reg_data <= unsigned(ip); + when 16#D0# => s_reg_data <= unsigned(psw); + when 16#E0# => s_reg_data <= acc; + when 16#F0# => s_reg_data <= b; + when others => s_reg_data <= conv_unsigned(0,8); + end case; + -- read one byte to bitadressable GPR + elsif conv_std_logic_vector(s_preadr(7 downto 4),4)="0010" then + s_reg_data <= gprbit(conv_integer(s_preadr(3 downto 0))); + + elsif conv_std_logic_vector(s_preadr,8)="00000000" then + s_reg_data <= s_r0_b0; -- read R0 / Bank 0 + elsif conv_std_logic_vector(s_preadr,8)="00000001" then + s_reg_data <= s_r1_b0; -- read R1 / Bank 0 + elsif conv_std_logic_vector(s_preadr,8)="00001000" then + s_reg_data <= s_r0_b1; -- read R0 / Bank 1 + elsif conv_std_logic_vector(s_preadr,8)="00001001" then + s_reg_data <= s_r1_b1; -- read R1 / Bank 1 + elsif conv_std_logic_vector(s_preadr,8)="00010000" then + s_reg_data <= s_r0_b2; -- read R0 / Bank 2 + elsif conv_std_logic_vector(s_preadr,8)="00010001" then + s_reg_data <= s_r1_b2; -- read R1 / Bank 2 + elsif conv_std_logic_vector(s_preadr,8)="00011000" then + s_reg_data <= s_r0_b3; -- read R0 / Bank 3 + elsif conv_std_logic_vector(s_preadr,8)="00011001" then + s_reg_data <= s_r1_b3; -- read R1 / Bank 3 + + else -- read on general purpose RAM + s_reg_data <= unsigned(ram_data_i); + end if; + + if s_preadr(7)='1' then + case s_preadr(6 downto 3) is -- read only one bit from a SFR + when "0000" => s_bit_data <= s_p0(conv_integer(s_preadr(2 downto 0))); + when "0001" => + s_bit_data <= tcon(s_tsel)(conv_integer(s_preadr(2 downto 0))); + when "0010" => s_bit_data <= s_p1(conv_integer(s_preadr(2 downto 0))); + when "0011" => + if conv_integer(s_preadr(2 downto 0))=2 then + s_bit_data <= s_rb8; + else + s_bit_data <= scon(s_ssel)(conv_integer(s_preadr(2 downto 0))); + end if; + when "0100" => s_bit_data <= s_p2(conv_integer(s_preadr(2 downto 0))); + when "0101" => s_bit_data <= ie(conv_integer(s_preadr(2 downto 0))); + when "0110" => s_bit_data <= s_p3(conv_integer(s_preadr(2 downto 0))); + when "0111" => s_bit_data <= ip(conv_integer(s_preadr(2 downto 0))); + when "1010" => s_bit_data <= psw(conv_integer(s_preadr(2 downto 0))); + when "1100" => s_bit_data <= acc(conv_integer(s_preadr(2 downto 0))); + when "1110" => s_bit_data <= b(conv_integer(s_preadr(2 downto 0))); + when others => s_bit_data <= '0'; + end case; + else -- read one bit from bitadressable GP + s_bit_data <= gprbit(conv_integer(s_preadr(6 downto 3))) + (conv_integer(s_preadr(2 downto 0))); + end if; + end process p_readram; + +------------------------------------------------------------------------------ +-- detect the rising/falling edge of interupt-sources +------------------------------------------------------------------------------ + +for_intext_edge: + for i in 0 to C_IMPL_N_EXT-1 generate + -- falling edge of int0_i + s_int0_edge(i) <= not s_int0_h2(i) and s_int0_h3(i); + -- falling edge of int1_i + s_int1_edge(i) <= not s_int1_h2(i) and s_int1_h3(i); + end generate for_intext_edge; + +for_tf_edge: + for i in 0 to C_IMPL_N_TMR-1 generate + -- on rising edge of tf0_i + s_tf0_edge(i) <= s_tf0_h1(i) and not s_tf0_h2(i); + -- on rising edge of tf1_i + s_tf1_edge(i) <= s_tf1_h1(i) and not s_tf1_h2(i); + end generate for_tf_edge; + +for_siu_edge: + for i in 0 to C_IMPL_N_SIU-1 generate + -- on rising edge of RI + s_ri_edge(i) <= s_ri_h1(i) and not s_ri_h2(i); + -- on rising edge of TI + s_ti_edge(i) <= s_ti_h1(i) and not s_ti_h2(i); + end generate for_siu_edge; + + +------------------------------------------------------------------------------ +-- purpose: write some help-regs for detecting the falling/rising edge +-- of interupt-sources +-- inputs: clk,reset,int0_i,int1_i,all_tf0_i,all_tf1_i,all_scon_i, +-- s_tf0_h1,s_tf1_h1,s_ri_h1,s_ti_h1 +-- outputs: s_int0_h1,s_int0_h2,s_int0_h3,s_int1_h1,s_int1_h2,s_int1_h3, +-- s_tf0_h1,s_tf0_h2 +-- s_tf1_h1,s_tf1_h2,s_ri_h1,s_ri_h2,s_ti_h1,s_ti_h2 +------------------------------------------------------------------------------ + + iep: process (clk,cen,reset) + + begin -- process iep + + -- activities triggered by asynchronous reset + if reset = '1' then + s_int0_h1 <= (others => '1'); + s_int0_h2 <= (others => '1'); + s_int0_h3 <= (others => '1'); + s_int1_h1 <= (others => '1'); + s_int1_h2 <= (others => '1'); + s_int1_h3 <= (others => '1'); + s_tf0_h1 <= (others => '0'); + s_tf0_h2 <= (others => '0'); + s_tf1_h1 <= (others => '0'); + s_tf1_h2 <= (others => '0'); + s_ri_h1 <= (others => '0'); + s_ri_h2 <= (others => '0'); + s_ti_h1 <= (others => '0'); + s_ti_h2 <= (others => '0'); + s_intblock_o <= '0'; -- CK, CV: changed s_inblock_o to s_intblock_o for internal use + -- activities triggered by rising edge of clock + elsif clk'event and clk = '1' and cen = '1' then + s_intblock_o <= s_intblock; -- CK, CV: changed s_inblock_o to s_intblock_o for internal use + for i in 0 to C_IMPL_N_EXT-1 loop + s_int0_h1(i) <= int0_i(i); -- external INT0 + s_int0_h2(i) <= s_int0_h1(i); + s_int0_h3(i) <= s_int0_h2(i); + s_int1_h1(i) <= int1_i(i); -- external INT1 + s_int1_h2(i) <= s_int1_h1(i); + s_int1_h3(i) <= s_int1_h2(i); + end loop; + for i in 0 to C_IMPL_N_TMR-1 loop + s_tf0_h1(i) <= all_tf0_i(i); -- TF0 flags + s_tf0_h2(i) <= s_tf0_h1(i); + s_tf1_h1(i) <= all_tf1_i(i); -- TF1 flags + s_tf1_h2(i) <= s_tf1_h1(i); + -- all_xxx is a std_logic_vector, s_xxx is a array of std_logic !!! + end loop; + for i in 0 to C_IMPL_N_SIU-1 loop + s_ri_h1(i) <= all_scon_i(i*3); -- RI flag + s_ri_h2(i) <= s_ri_h1(i); + s_ti_h1(i) <= all_scon_i((i*3)+1); -- TI flag + s_ti_h2(i) <= s_ti_h1(i); + -- all_xxx is a std_logic_vector, s_xxx is a array of std_logic !!! + end loop; + end if; + end process iep; + +------------------------------------------------------------------------------ +-- purpose: check the interupt-sources and start an interupt if necessary +-- inputs: ie,ip,scon,tcon,s_inthigh,s_intlow,s_ti,s_ri,s_ie0, +-- s_ie1,s_tf0,s_tf1 +-- outputs: s_intpre +------------------------------------------------------------------------------ + + intpre : process (ie,ip,scon,tcon,s_inthigh,s_intlow,s_ti,s_ri,s_ie0, + s_ie1,s_tf0,s_tf1) + begin + if (EA='1' and (EX0='1' or ET0='1' or EX1='1' or ET1='1' or ES='1')) then + if s_inthigh='1' then -- interrupt with high priority is running + s_intpre <= '0'; + elsif s_intlow='1' then -- interrupt with low priority is running + if ((PX0 and EX0 and s_ie0) or + (PT0 and ET0 and s_tf0) or + (PX1 and EX1 and s_ie1) or + (PT1 and ET1 and s_tf1) or + (PS0 and ES and (s_ri or s_ti)))='1' then + s_intpre <= '1'; -- a second interrupt must start + else + s_intpre <= '0'; + end if; + else -- no interrupt is running + if ((EX0 and s_ie0) or + (ET0 and s_tf0) or + (EX1 and s_ie1) or + (ET1 and s_tf1) or + (ES and (s_ri or s_ti)))='1' then + s_intpre <= '1'; -- an interrupt must start + else + s_intpre <= '0'; + end if; + end if; + else -- no interrupt must be carried out + s_intpre <= '0'; + end if; + end process intpre; + +------------------------------------------------------------------------------ +-- purpose: this are the main-multiplexer for reading and writing regs +-- inputs: s_data_mux,pc,aludata_i,s_reg_data,rom_data_i,acc, +-- s_bdata_mux,s_bit_data,psw,new_cy_i,s_helpb,sp,s_rr_adr, +-- s_ri_data,s_help,s_adr_mux,s_adr,s_regs_wr_en,pc_plus2, +-- s_help16,s_ri_adr,s_r0_b0,s_r1_b0,s_r0_b1,s_r1_b1, +-- s_r0_b2,s_r1_b2,s_r0_b3,s_r1_b3 +-- outputs: s_data,s_bdata,s_adr,s_ri_data,ram_wr_o +------------------------------------------------------------------------------ + + p_multiplexer : process (s_data_mux,pc,aludata_i,s_reg_data,rom_data_i,acc, + s_bdata_mux,s_bit_data,psw,new_cy_i,s_helpb,sp,s_rr_adr, + s_ri_data,s_help,s_adr_mux,s_adr,s_regs_wr_en,pc_plus2, + s_help16,s_ri_adr,s_r0_b0,s_r1_b0,s_r0_b1,s_r1_b1, + s_r0_b2,s_r1_b2,s_r0_b3,s_r1_b3,s_adrx_mux,dph,dpl, + datax_i) + begin + case s_data_mux is + when "0000" => s_data <= conv_unsigned(0,8); + when "0001" => s_data <= pc(7 downto 0); + when "0010" => s_data <= pc(15 downto 8); + when "0011" => s_data <= unsigned(aludata_i); + when "0100" => s_data <= s_reg_data; + when "0101" => s_data <= unsigned(rom_data_i); + when "0110" => s_data <= acc; + when "0111" => + s_data(7 downto 4) <= acc(3 downto 0); + s_data(3 downto 0) <= acc(7 downto 4); + when "1000" => s_data <= s_help; + when "1001" => + s_data(7 downto 4) <= s_reg_data(7 downto 4); + s_data(3 downto 0) <= s_help(3 downto 0); + when "1010" => + s_data(7 downto 4) <= acc(7 downto 4); + s_data(3 downto 0) <= s_reg_data(3 downto 0); + when "1100" => s_data <= s_help16(7 downto 0); + when "1101" => s_data <= s_help16(15 downto 8); + when "1110" => s_data <= pc_plus2(7 downto 0); + when "1111" => s_data <= unsigned(datax_i); + when others => s_data <= conv_unsigned(0,8); + end case; + + case s_bdata_mux is + when "0000" => s_bdata <= '0'; + when "0001" => s_bdata <= s_bit_data and cy; + when "0010" => s_bdata <= not(s_bit_data) and cy; + when "0011" => s_bdata <= new_cy_i(1); + when "0100" => s_bdata <= s_helpb; + when "0101" => s_bdata <= not cy; + when "0110" => s_bdata <= not s_bit_data; + when "0111" => s_bdata <= s_bit_data; + when "1000" => s_bdata <= cy; + when "1001" => s_bdata <= s_bit_data or cy; + when "1010" => s_bdata <= not(s_bit_data) or cy; + when "1011" => s_bdata <= '1'; + when others => s_bdata <= '0'; + end case; + + case s_adr_mux is + when "0000" => s_adr <= conv_unsigned(0,8); + when "0001" => s_adr <= conv_unsigned(16#89#,8); + when "0010" => s_adr <= conv_unsigned(16#8D#,8); + when "0011" => s_adr <= conv_unsigned(16#8B#,8); + when "0100" => s_adr <= conv_unsigned(16#8F#,8); + when "0101" => s_adr <= sp; + when "0110" => s_adr <= s_rr_adr; + when "0111" => s_adr <= s_ri_data; + when "1000" => s_adr <= unsigned(rom_data_i); + when "1001" => s_adr <= s_reg_data; + when "1010" => s_adr <= s_help ; + when "1011" => s_adr <= conv_unsigned(16#D7#,8); + when "1100" => s_adr <= conv_unsigned(16#F0#,8); + when "1101" => s_adr <= conv_unsigned(16#82#,8); + when "1110" => s_adr <= conv_unsigned(16#83#,8); + when "1111" => s_adr <= sp + conv_unsigned(1,1); + when others => s_adr <= conv_unsigned(0,8); + end case; + + case s_adrx_mux is + --when "00" => adrx_o <= (others => '0'); + when "01" => + adrx_o(15 downto 8) <= std_logic_vector(dph); + adrx_o(7 downto 0) <= std_logic_vector(dpl); + memx_o <= '1'; + when "10" => + adrx_o(15 downto 8) <= (others => '0'); + adrx_o(7 downto 0) <= std_logic_vector(s_ri_data); + memx_o <= '1'; + when others => adrx_o <= (others => '0'); memx_o <= '0'; + end case; + + case s_ri_adr is + when "00000000" => s_ri_data <= s_r0_b0; + when "00000001" => s_ri_data <= s_r1_b0; + when "00001000" => s_ri_data <= s_r0_b1; + when "00001001" => s_ri_data <= s_r1_b1; + when "00010000" => s_ri_data <= s_r0_b2; + when "00010001" => s_ri_data <= s_r1_b2; + when "00011000" => s_ri_data <= s_r0_b3; + when "00011001" => s_ri_data <= s_r1_b3; + when others => s_ri_data <= conv_unsigned(0,8); + end case; + + if ((s_regs_wr_en="100") or (s_regs_wr_en="101")) then -- write one byte + if ((s_adr(7)='1') or -- SFR + (conv_std_logic_vector(s_adr(7 downto 4),4)="0010") -- bitadressable + or ((std_logic_vector(s_adr) AND "11100110") = "00000000")) -- R0,R1 + then + ram_wr_o <= '0'; + else + ram_wr_o <= '1'; -- to RAM-block + end if; + else + ram_wr_o <= '0'; + end if; + end process p_multiplexer; + +------------------------------------------------------------------------------ +-- purpose: writes internal registers, on which the user have no +-- direct access +-- inputs: reset,clk,s_nextstate,state,s_help_en, +-- rom_data_i,aludata_i,s_reg_data,s_rr_adr,new_cy_i +-- outputs: state,s_ir,s_help,s_help16,s_helpb,s_intpre2,s_intlow, +-- s_inthigh,s_preadr +------------------------------------------------------------------------------ + + p_wr_internal_reg : process (reset,cen,clk) + begin + if reset='1' then + state <= STARTUP; + s_ir <= conv_unsigned(0,8); + s_help <= conv_unsigned(0,8); + s_help16 <= conv_unsigned(0,16); + s_helpb <= '0'; + s_intpre2 <= '0'; + s_intlow <= '0'; + s_inthigh <= '0'; + s_preadr <= conv_unsigned(0,8); + pc <= conv_unsigned(0,16); + s_p0 <= "11111111"; + s_p1 <= "11111111"; + s_p2 <= "11111111"; + s_p3 <= "11111111"; + s_ext0isr_d <= '0'; + s_ext0isrh_d <= '0'; + s_ext1isr_d <= '0'; + s_ext1isrh_d <= '0'; + else + if Rising_Edge(clk) and cen='1' then + + state <= s_nextstate; -- update current state + + if state=FETCH then + s_ir <= unsigned(rom_data_i); -- save OP-Code in IR + end if; + + case s_help_en is + when "0000" => NULL; + when "0001" => s_help <= unsigned(rom_data_i); + when "0010" => s_help <= unsigned(aludata_i); + when "0011" => s_help <= s_reg_data; + when "0100" => s_help <= s_rr_adr; + when "0101" => s_help <= conv_unsigned(16#03#,8); + when "0110" => s_help <= conv_unsigned(16#0B#,8); + when "0111" => s_help <= conv_unsigned(16#13#,8); + when "1000" => s_help <= conv_unsigned(16#1B#,8); + when "1001" => s_help <= conv_unsigned(16#23#,8); + when "1010" => s_help <= acc; + when others => NULL; + end case; + + case s_help16_en is + when "00" => NULL; + when "01" => s_help16 <= pc + conv_unsigned(3,2); + when "10" => s_help16 <= pc_plus2; + when "11" => s_help16 <= pc_plus1; + when others => NULL; + end case; + + case s_helpb_en is + when '0' => NULL; + when '1' => s_helpb <= new_cy_i(1); + when others => NULL; + end case; + + if s_intpre2_en='1' then -- help-reg for s_intpre + s_intpre2 <= s_intpre2_d; + else + NULL; + end if; + + if s_intlow_en='1' then + s_intlow <= s_intlow_d; + else + NULL; + end if; + + if s_inthigh_en='1' then + s_inthigh <= s_inthigh_d; + else + NULL; + end if; + + if ext0isr_en_i = '1' then + s_ext0isr_d <= ext0isr_d_i; + end if; + if ext1isr_en_i = '1' then + s_ext1isr_d <= ext1isr_d_i; + end if; + if ext0isrh_en_i = '1' then + s_ext0isrh_d <= ext0isrh_d_i; + end if; + if ext1isrh_en_i = '1' then + s_ext1isrh_d <= ext1isrh_d_i; + end if; + + s_preadr <= s_adr; + + pc <= pc_comb; -- write pc-register + + s_p0 <= p0_i; + s_p1 <= p1_i; + s_p2 <= p2_i; + s_p3 <= p3_i; + + end if; + end if; + end process p_wr_internal_reg; + +------------------------------------------------------------------------------ +-- purpose: calculate the next PC-adress +-- inputs: s_pc_inc_en,pc_plus1,rom_data_i,s_intpre2,s_help,s_command, +-- s_help16,s_ir,dph,dpl,acc,s_reg_data,pc +-- outputs: pc_comb +------------------------------------------------------------------------------ + + p_pc : process (s_pc_inc_en,pc_plus1,rom_data_i,s_help, + s_help16,s_ir,dph,dpl,acc,s_reg_data,pc) + variable v_dptr: unsigned(15 downto 0); + begin + v_dptr(15 downto 8) := dph; + v_dptr(7 downto 0) := dpl; + case s_pc_inc_en is + when "0001" => -- increment PC + pc_comb <= pc_plus1; + when "0010" => -- for relativ jumps and calls + pc_comb <= conv_unsigned(pc_plus1 + signed(rom_data_i),16); + when "0011" => -- load interrupt vectoradress + pc_comb(15 downto 8) <= conv_unsigned(0,8); + pc_comb(7 downto 0) <= s_help; + when "0100" => -- ACALL and AJMP + pc_comb(15 downto 11) <= s_help16(15 downto 11); + pc_comb(10 downto 8) <= s_ir(7 downto 5); + pc_comb(7 downto 0) <= unsigned(rom_data_i); + when "0101" => -- JMP_A_DPTR, MOVC_A_ATDPTR + pc_comb <= v_dptr + conv_unsigned(acc,8); + when "0110" => -- MOVC + pc_comb <= s_help16; + when "0111" => -- LJMP, LCALL + pc_comb(15 downto 8) <= s_help; + pc_comb(7 downto 0) <= unsigned(rom_data_i); + when "1000" => -- RET, RETI + pc_comb(15 downto 8) <= s_help; + pc_comb(7 downto 0) <= s_reg_data; + when "1001" => -- MOVC_A_ATPC + pc_comb <= pc_plus1 + conv_unsigned(acc,8); + when others => pc_comb <= pc; + end case; + end process p_pc; + +------------------------------------------------------------------------------ +-- purpose: write RAM, SFR or bitadressable Registers +-- inputs: reset,clk +-- outputs: SFR, gprbit +------------------------------------------------------------------------------ + + p_write_ram : process (reset,clk,cen) + begin + if reset='1' then + ram_en_o <= '0'; + gprbit(0) <= conv_unsigned(0,8); + gprbit(1) <= conv_unsigned(0,8); + gprbit(2) <= conv_unsigned(0,8); + gprbit(3) <= conv_unsigned(0,8); + gprbit(4) <= conv_unsigned(0,8); + gprbit(5) <= conv_unsigned(0,8); + gprbit(6) <= conv_unsigned(0,8); + gprbit(7) <= conv_unsigned(0,8); + gprbit(8) <= conv_unsigned(0,8); + gprbit(9) <= conv_unsigned(0,8); + gprbit(10) <= conv_unsigned(0,8); + gprbit(11) <= conv_unsigned(0,8); + gprbit(12) <= conv_unsigned(0,8); + gprbit(13) <= conv_unsigned(0,8); + gprbit(14) <= conv_unsigned(0,8); + gprbit(15) <= conv_unsigned(0,8); + s_r0_b0 <= conv_unsigned(0,8); + s_r1_b0 <= conv_unsigned(0,8); + s_r0_b1 <= conv_unsigned(0,8); + s_r1_b1 <= conv_unsigned(0,8); + s_r0_b2 <= conv_unsigned(0,8); + s_r1_b2 <= conv_unsigned(0,8); + s_r0_b3 <= conv_unsigned(0,8); + s_r1_b3 <= conv_unsigned(0,8); + p0 <= conv_unsigned(255,8); + sp <= conv_unsigned(7,8); + dpl <= conv_unsigned(0,8); + dph <= conv_unsigned(0,8); + pcon <= conv_unsigned(0,4); + tcon <= (others => (others => '0')); + tmod <= (others => (others => '0')); + tsel <= conv_unsigned(0,8); + p1 <= conv_unsigned(255,8); + scon <= (others => (others => '0')); + s_smodreg <= (others => '0'); + sbuf <= (others => (others => '0')); + ssel <= conv_unsigned(0,8); + p2 <= conv_unsigned(255,8); + ie <= conv_std_logic_vector(0,8); + p3 <= conv_unsigned(255,8); + ip <= conv_std_logic_vector(0,8); + psw <= conv_std_logic_vector(0,8); + acc <= conv_unsigned(0,8); + b <= conv_unsigned(0,8); + s_reload <= (others => (others => '0')); + all_wt_en_o <= (others => '0'); + s_wt <= (others => (others => '0')); + all_trans_o <= (others => '0'); + else + ram_en_o <= '1'; + + if Rising_Edge(clk) and cen='1' then + all_wt_en_o <= ( others => '0' ); -- default values + all_trans_o <= ( others => '0' ); + psw(0) <= s_p; + for i in 0 to C_IMPL_N_TMR-1 loop + tcon(i)(3) <= tcon(i)(3) or ((tcon(i)(2) and s_int1_edge(i)) or + ((not tcon(i)(2) and not s_int1_h2(i)) and + not(s_ext1isr_d or s_ext1isrh_d))); + tcon(i)(1) <= tcon(i)(1) or ((tcon(i)(0) and s_int0_edge(i)) or + ((not tcon(i)(0) and not s_int0_h2(i)) and + not(s_ext0isr_d or s_ext0isrh_d))); + tcon(i)(5) <= tcon(i)(5) or s_tf0_edge(i); + tcon(i)(7) <= tcon(i)(7) or s_tf1_edge(i); + end loop; + -- update TF1, TF0 and IE1, IE0 in dependance on the IT flags + for i in 0 to C_IMPL_N_SIU-1 loop + scon(i)(0) <= scon(i)(0) or s_ri_edge(i); + scon(i)(1) <= scon(i)(1) or s_ti_edge(i); + end loop; + + case s_regs_wr_en is + when "001" => -- inc or dec SP + + if (s_intblock='0' and s_intpre='1' and state=FETCH) or s_intpre2='1' then + sp <= sp + conv_unsigned(1,1); + else + case s_command is + when RET | RETI => + sp <= sp - conv_unsigned(1,1); + when others => + sp <= sp + conv_unsigned(1,1); + end case; + end if; + when "010" => -- write to ACC + acc <= s_data; + when "011" => -- write to ACC and PSW + acc <= s_data; + psw(7) <= new_cy_i(1); + psw(6) <= new_cy_i(0); + psw(2) <= new_ov_i; + when "100" | "101" => + case s_regs_wr_en is -- sp register + when "100" => + if conv_integer(s_adr) = 16#81# then + sp <= s_data; + end if; + when "101" => + if (s_intblock='0' and s_intpre='1' and state=FETCH) or s_intpre2='1' then + sp <= sp + conv_unsigned(1,1); + else + if s_command = POP then + if (conv_integer(s_adr) = 16#81#) then + sp <= s_data; + else + sp <= sp - conv_unsigned(1, 1); + end if; + else + sp <= sp + conv_unsigned(1, 1); + end if; + end if; + when others => NULL; + end case; + + if s_adr(7)='1' then + case conv_integer(s_adr) is -- write one byte of a SFR + when 16#80# => p0 <= s_data; + when 16#82# => dpl <= s_data; + when 16#83# => dph <= s_data; + when 16#87# => + pcon <= s_data(3 downto 0); + s_smodreg(s_ssel) <= s_data(7); + when 16#88# => tcon(s_tsel) <= std_logic_vector(s_data); + when 16#89# => tmod(s_tsel) <= s_data; + when 16#8A# => + s_reload(s_tsel) <= s_data; -- tl0 + s_wt(s_tsel) <= "00"; + all_wt_en_o(s_tsel) <= '1'; + when 16#8B# => + s_reload(s_tsel) <= s_data; -- tl1 + s_wt(s_tsel) <= "01"; + all_wt_en_o(s_tsel) <= '1'; + when 16#8C# => + s_reload(s_tsel) <= s_data; -- th0 + s_wt(s_tsel) <= "10"; + all_wt_en_o(s_tsel) <= '1'; + when 16#8D# => + s_reload(s_tsel) <= s_data; -- th1 + s_wt(s_tsel) <= "11"; + all_wt_en_o(s_tsel) <= '1'; + when 16#8E# => tsel <= s_data; + when 16#90# => p1 <= s_data; + when 16#98# => scon(s_ssel) <= std_logic_vector(s_data); + when 16#99# => + sbuf(s_ssel) <= s_data; + all_trans_o(s_ssel) <= '1'; + when 16#9A# => ssel <= s_data; + when 16#A0# => p2 <= s_data; + when 16#A8# => ie <= conv_std_logic_vector(s_data,8); + when 16#B0# => p3 <= s_data; + when 16#B8# => ip <= conv_std_logic_vector(s_data,8); + when 16#D0# => + psw(7 downto 1) <= conv_std_logic_vector(s_data(7 downto 1),7); + when 16#E0# => acc <= s_data; + when 16#F0# => b <= s_data; + when others => NULL; + end case; + -- write one byte to bitadressable GPR + elsif conv_std_logic_vector(s_adr(7 downto 4),4)="0010" then + gprbit(conv_integer(s_adr(3 downto 0))) <= s_data; + elsif conv_std_logic_vector(s_adr,8)="00000000" then + s_r0_b0 <= s_data; -- write R0 / Bank 0 + elsif conv_std_logic_vector(s_adr,8)="00000001" then + s_r1_b0 <= s_data; -- write R1 / Bank 0 + elsif conv_std_logic_vector(s_adr,8)="00001000" then + s_r0_b1 <= s_data; -- write R0 / Bank 1 + elsif conv_std_logic_vector(s_adr,8)="00001001" then + s_r1_b1 <= s_data; -- write R1 / Bank 1 + elsif conv_std_logic_vector(s_adr,8)="00010000" then + s_r0_b2 <= s_data; -- write R0 / Bank 2 + elsif conv_std_logic_vector(s_adr,8)="00010001" then + s_r1_b2 <= s_data; -- write R1 / Bank 2 + elsif conv_std_logic_vector(s_adr,8)="00011000" then + s_r0_b3 <= s_data; -- write R0 / Bank 3 + elsif conv_std_logic_vector(s_adr,8)="00011001" then + s_r1_b3 <= s_data; -- write R1 / Bank 3 + else -- write on general purpose RAM + NULL; + end if; + when "110" => + if (s_intblock='0' and s_intpre='1' and state=FETCH) or s_intpre2='1' or + (s_command /= ANL_C_BIT and + s_command /= ANL_C_NBIT and + s_command /= MOV_C_BIT and + s_command /= ORL_C_BIT and + s_command /= ORL_C_NBIT) then + if s_adr(7)='1' then + case s_adr(6 downto 3) is -- write only one bit of an SFR + when "0000" => + p0(conv_integer(s_adr(2 downto 0))) <= s_bdata; + when "0001" => + tcon(s_tsel)(conv_integer(s_adr(2 downto 0))) <= s_bdata; + when "0010" => + p1(conv_integer(s_adr(2 downto 0))) <= s_bdata; + when "0011" => + scon(s_ssel)(conv_integer(s_adr(2 downto 0))) <= s_bdata; + when "0100" => + p2(conv_integer(s_adr(2 downto 0))) <= s_bdata; + when "0101" => + ie(conv_integer(s_adr(2 downto 0))) <= s_bdata; + when "0110" => + p3(conv_integer(s_adr(2 downto 0))) <= s_bdata; + when "0111" => + ip(conv_integer(s_adr(2 downto 0))) <= s_bdata; + when "1010" => + case s_adr(2 downto 0) is + when "000" => NULL; + when "001" => psw(1) <= s_bdata; + when "010" => psw(2) <= s_bdata; + when "011" => psw(3) <= s_bdata; + when "100" => psw(4) <= s_bdata; + when "101" => psw(5) <= s_bdata; + when "110" => psw(6) <= s_bdata; + when "111" => psw(7) <= s_bdata; + when others => NULL; + end case; + when "1100" => + acc(conv_integer(s_adr(2 downto 0))) <= s_bdata; + when "1110" => + b(conv_integer(s_adr(2 downto 0))) <= s_bdata; + when others => NULL; + end case; + else -- write one bit to bitadressable GP + gprbit(conv_integer(s_adr(6 downto 3))) + (conv_integer(s_adr(2 downto 0))) <= s_bdata; + end if; + else + psw(7) <= s_bdata; -- write CY + end if; + when "111" => + case s_command is + when DA_A | RLC_A | RRC_A => -- write ACC, CY + acc <= s_data; + psw(7) <= new_cy_i(1); + when DIV_AB | MUL_AB => -- write ACC, B, CY, OV + acc <= s_data; + b <= unsigned(aludatb_i); + psw(7) <= '0'; + psw(2) <= new_ov_i; + when others => NULL; + end case; + when others => NULL; + end case; + end if; + end if; + end process p_write_ram; + +end rtl; + diff --git a/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/8051/control_mem_rtl_cfg.vhd b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/8051/control_mem_rtl_cfg.vhd new file mode 100644 index 0000000000000000000000000000000000000000..f00fb8a2062da9466e40c0ed54b1b345ed444774 --- /dev/null +++ b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/8051/control_mem_rtl_cfg.vhd @@ -0,0 +1,71 @@ +------------------------------------------------------------------------------- +-- -- +-- X X XXXXXX XXXXXX XXXXXX XXXXXX X -- +-- XX XX X X X X X X X XX -- +-- X X X X X X X X X X X X -- +-- X X X X X X X X X X X X -- +-- X X X X XXXXXX X X XXXXXX X -- +-- X X X X X X X X X -- +-- X X X X X X X X X -- +-- X X X X X X X X X X -- +-- X X XXXXXX XXXXXX XXXXXX XXXXXX X -- +-- -- +-- -- +-- O R E G A N O S Y S T E M S -- +-- -- +-- Design & Consulting -- +-- -- +------------------------------------------------------------------------------- +-- -- +-- Web: http://www.oregano.at/ -- +-- -- +-- Contact: mc8051@oregano.at -- +-- -- +------------------------------------------------------------------------------- +-- -- +-- MC8051 - VHDL 8051 Microcontroller IP Core -- +-- Copyright (C) 2001 OREGANO SYSTEMS -- +-- -- +-- This library is free software; you can redistribute it and/or -- +-- modify it under the terms of the GNU Lesser General Public -- +-- License as published by the Free Software Foundation; either -- +-- version 2.1 of the License, or (at your option) any later version. -- +-- -- +-- This library is distributed in the hope that it will be useful, -- +-- but WITHOUT ANY WARRANTY; without even the implied warranty of -- +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -- +-- Lesser General Public License for more details. -- +-- -- +-- Full details of the license can be found in the file LGPL.TXT. -- +-- -- +-- You should have received a copy of the GNU Lesser General Public -- +-- License along with this library; if not, write to the Free Software -- +-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -- +-- -- +------------------------------------------------------------------------------- +-- +-- +-- Author: Helmut Mayrhofer +-- +-- Filename: control_mem_rtl_cfg.vhd +-- +-- Date of Creation: Mon Aug 9 12:14:48 1999 +-- +-- Version: $Revision: 1.4 $ +-- +-- Date of Latest Version: $Date: 2002-01-07 12:17:44 $ +-- +-- +-- Description: Describe all sequential funcitonality like read from +-- special function registers, observe interrupt sources, +-- write to special function registers, and read or write +-- to the bit addressable memory area. +-- +-- +-- +-- +------------------------------------------------------------------------------- +configuration control_mem_rtl_cfg of control_mem is + for rtl + end for; +end control_mem_rtl_cfg; \ No newline at end of file diff --git a/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/8051/dcml_adjust_.vhd b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/8051/dcml_adjust_.vhd new file mode 100644 index 0000000000000000000000000000000000000000..8e86e7dff4a77dd0aaeb55228aee269254fba6b3 --- /dev/null +++ b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/8051/dcml_adjust_.vhd @@ -0,0 +1,89 @@ +------------------------------------------------------------------------------- +-- -- +-- X X XXXXXX XXXXXX XXXXXX XXXXXX X -- +-- XX XX X X X X X X X XX -- +-- X X X X X X X X X X X X -- +-- X X X X X X X X X X X X -- +-- X X X X XXXXXX X X XXXXXX X -- +-- X X X X X X X X X -- +-- X X X X X X X X X -- +-- X X X X X X X X X X -- +-- X X XXXXXX XXXXXX XXXXXX XXXXXX X -- +-- -- +-- -- +-- O R E G A N O S Y S T E M S -- +-- -- +-- Design & Consulting -- +-- -- +------------------------------------------------------------------------------- +-- -- +-- Web: http://www.oregano.at/ -- +-- -- +-- Contact: mc8051@oregano.at -- +-- -- +------------------------------------------------------------------------------- +-- -- +-- MC8051 - VHDL 8051 Microcontroller IP Core -- +-- Copyright (C) 2001 OREGANO SYSTEMS -- +-- -- +-- This library is free software; you can redistribute it and/or -- +-- modify it under the terms of the GNU Lesser General Public -- +-- License as published by the Free Software Foundation; either -- +-- version 2.1 of the License, or (at your option) any later version. -- +-- -- +-- This library is distributed in the hope that it will be useful, -- +-- but WITHOUT ANY WARRANTY; without even the implied warranty of -- +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -- +-- Lesser General Public License for more details. -- +-- -- +-- Full details of the license can be found in the file LGPL.TXT. -- +-- -- +-- You should have received a copy of the GNU Lesser General Public -- +-- License along with this library; if not, write to the Free Software -- +-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -- +-- -- +------------------------------------------------------------------------------- +-- +-- +-- Author: Roland Hller +-- +-- Filename: dcml_adjust_.vhd +-- +-- Date of Creation: Mon Aug 9 12:14:48 1999 +-- +-- Version: $Revision: 1.4 $ +-- +-- Date of Latest Version: $Date: 2002-01-07 12:17:44 $ +-- +-- +-- Description: Combinational design to calculate the decimal +-- representation (BCD) of a data bus. +-- +-- +-- +-- +------------------------------------------------------------------------------- +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.std_logic_arith.all; + +-----------------------------ENTITY DECLARATION-------------------------------- + +entity dcml_adjust is + + generic (DWIDTH : integer := 12); + + port (data_i : in std_logic_vector(DWIDTH-1 downto 0); + cy_i : in std_logic_vector((DWIDTH-1)/4 downto 0); + data_o : out std_logic_vector(DWIDTH-1 downto 0); + cy_o : out std_logic); + + ----------------------------------------------------------------------------- + -- data_i .......... Data bus + -- cy_i ............ Carry flags (one for each nibble) + -- data_o .......... Adjusted data bus + -- cy_o ............ New overall carry flag + ----------------------------------------------------------------------------- + +end dcml_adjust; + diff --git a/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/8051/dcml_adjust_rtl.vhd b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/8051/dcml_adjust_rtl.vhd new file mode 100644 index 0000000000000000000000000000000000000000..fa27c30a0a2bc72df211dddaa352b370d01e5889 --- /dev/null +++ b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/8051/dcml_adjust_rtl.vhd @@ -0,0 +1,142 @@ +------------------------------------------------------------------------------- +-- -- +-- X X XXXXXX XXXXXX XXXXXX XXXXXX X -- +-- XX XX X X X X X X X XX -- +-- X X X X X X X X X X X X -- +-- X X X X X X X X X X X X -- +-- X X X X XXXXXX X X XXXXXX X -- +-- X X X X X X X X X -- +-- X X X X X X X X X -- +-- X X X X X X X X X X -- +-- X X XXXXXX XXXXXX XXXXXX XXXXXX X -- +-- -- +-- -- +-- O R E G A N O S Y S T E M S -- +-- -- +-- Design & Consulting -- +-- -- +------------------------------------------------------------------------------- +-- -- +-- Web: http://www.oregano.at/ -- +-- -- +-- Contact: mc8051@oregano.at -- +-- -- +------------------------------------------------------------------------------- +-- -- +-- MC8051 - VHDL 8051 Microcontroller IP Core -- +-- Copyright (C) 2001 OREGANO SYSTEMS -- +-- -- +-- This library is free software; you can redistribute it and/or -- +-- modify it under the terms of the GNU Lesser General Public -- +-- License as published by the Free Software Foundation; either -- +-- version 2.1 of the License, or (at your option) any later version. -- +-- -- +-- This library is distributed in the hope that it will be useful, -- +-- but WITHOUT ANY WARRANTY; without even the implied warranty of -- +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -- +-- Lesser General Public License for more details. -- +-- -- +-- Full details of the license can be found in the file LGPL.TXT. -- +-- -- +-- You should have received a copy of the GNU Lesser General Public -- +-- License along with this library; if not, write to the Free Software -- +-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -- +-- -- +------------------------------------------------------------------------------- +-- +-- +-- Author: Roland Hller +-- +-- Filename: dcml_adjust_rtl.vhd +-- +-- Date of Creation: Mon Aug 9 12:14:48 1999 +-- +-- Version: $Revision: 1.4 $ +-- +-- Date of Latest Version: $Date: 2002-01-07 12:17:44 $ +-- +-- +-- Description: Combinational design to calculate the decimal +-- representation (BCD) of a data bus. +-- +-- +-- +-- +------------------------------------------------------------------------------- +architecture rtl of dcml_adjust is + +begin -- rtl + + p_calc_adjst: process (data_i, cy_i) + + variable v_cy : std_logic_vector((DWIDTH-1)/4 downto 0); + variable v_nxtcy : std_logic; + variable v_tmpda : unsigned(DWIDTH downto 0); + variable v_tmpda1 : unsigned(4 downto 0); + variable v_compvl : unsigned(3 downto 0); + + begin -- process p_calc_adjst + v_tmpda(DWIDTH-1 downto 0) := unsigned(data_i); + v_tmpda(DWIDTH) := '0'; + v_cy := cy_i; + v_nxtcy := '0'; + for i in 0 to (DWIDTH-1)/4 loop + if DWIDTH-i*4 <= 4 then + -- Calculate the decimal adjustment of the last nibble/rest of bits + v_compvl := conv_unsigned(0,4); + v_compvl(DWIDTH-1-i*4 downto 0) := v_tmpda(DWIDTH-1 downto i*4); + if (v_cy(i) = '1') or (v_compvl > conv_unsigned(9,4)) then + if DWIDTH-i*4 > 2 then + v_tmpda(DWIDTH downto i*4) := v_tmpda(DWIDTH-1 downto i*4) + + conv_unsigned(6,v_tmpda(DWIDTH downto i*4)'LENGTH); + else + v_tmpda(DWIDTH downto i*4) := v_tmpda(DWIDTH-1 downto i*4) + + conv_unsigned(2,v_tmpda(DWIDTH downto i*4)'LENGTH); + end if; + end if; + -- An already set intermediate carry flag must not be lost. + v_cy(i) := v_tmpda(DWIDTH) or v_cy(i); + else + -- Calculate the decimal adjustment of all nibbles, but the last one. + v_compvl := v_tmpda(i*4+3 downto i*4); + v_tmpda1 := conv_unsigned(0,5); + if (v_cy(i) = '1') or (v_compvl > conv_unsigned(9,4)) then + for j in i to (DWIDTH-1)/4 loop + if DWIDTH-1 > j*4+3 then + -- Calculate all subsequent nibbles from the actual position up + -- to the one before the last. + if j=i then + v_tmpda1 := v_tmpda(j*4+3 downto j*4) + + conv_unsigned(6,5); + v_nxtcy := v_tmpda1(4); + v_tmpda(j*4+3 downto j*4) := v_tmpda1(3 downto 0); + else + v_tmpda1 := v_tmpda(j*4+3 downto j*4) + + conv_unsigned(v_nxtcy,5); + v_nxtcy := v_tmpda1(4); + v_tmpda(j*4+3 downto j*4) := v_tmpda1(3 downto 0); + end if; + -- An already set intermediate carry flag must not be lost. + v_cy(j) := v_tmpda1(4) or v_cy(j); + else + -- Calculate the last nibble. + if j=i then + v_tmpda(DWIDTH downto j*4) := v_tmpda(DWIDTH-1 downto j*4) + + conv_unsigned(6,v_tmpda(DWIDTH downto j*4)'LENGTH); + else + v_tmpda(DWIDTH downto j*4) := v_tmpda(DWIDTH-1 downto j*4) + + conv_unsigned(v_nxtcy,v_tmpda(DWIDTH downto j*4)'LENGTH); + end if; + -- An already set intermediate carry flag must not be lost. + v_cy(j) := v_tmpda(DWIDTH) or v_cy(j); + end if; + end loop; -- j + end if; + end if; + end loop; -- i + -- Generate outputs + cy_o <= v_cy(v_cy'HIGH); + data_o <= std_logic_vector(v_tmpda(DWIDTH-1 downto 0)); + end process p_calc_adjst; + +end rtl; diff --git a/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/8051/dcml_adjust_rtl_cfg.vhd b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/8051/dcml_adjust_rtl_cfg.vhd new file mode 100644 index 0000000000000000000000000000000000000000..593261e9aa66bf4a63273f2df0f535e548928ede --- /dev/null +++ b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/8051/dcml_adjust_rtl_cfg.vhd @@ -0,0 +1,72 @@ +------------------------------------------------------------------------------- +-- -- +-- X X XXXXXX XXXXXX XXXXXX XXXXXX X -- +-- XX XX X X X X X X X XX -- +-- X X X X X X X X X X X X -- +-- X X X X X X X X X X X X -- +-- X X X X XXXXXX X X XXXXXX X -- +-- X X X X X X X X X -- +-- X X X X X X X X X -- +-- X X X X X X X X X X -- +-- X X XXXXXX XXXXXX XXXXXX XXXXXX X -- +-- -- +-- -- +-- O R E G A N O S Y S T E M S -- +-- -- +-- Design & Consulting -- +-- -- +------------------------------------------------------------------------------- +-- -- +-- Web: http://www.oregano.at/ -- +-- -- +-- Contact: mc8051@oregano.at -- +-- -- +------------------------------------------------------------------------------- +-- -- +-- MC8051 - VHDL 8051 Microcontroller IP Core -- +-- Copyright (C) 2001 OREGANO SYSTEMS -- +-- -- +-- This library is free software; you can redistribute it and/or -- +-- modify it under the terms of the GNU Lesser General Public -- +-- License as published by the Free Software Foundation; either -- +-- version 2.1 of the License, or (at your option) any later version. -- +-- -- +-- This library is distributed in the hope that it will be useful, -- +-- but WITHOUT ANY WARRANTY; without even the implied warranty of -- +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -- +-- Lesser General Public License for more details. -- +-- -- +-- Full details of the license can be found in the file LGPL.TXT. -- +-- -- +-- You should have received a copy of the GNU Lesser General Public -- +-- License along with this library; if not, write to the Free Software -- +-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -- +-- -- +------------------------------------------------------------------------------- +-- +-- +-- Author: Roland Hller +-- +-- Filename: dcml_adjust_rtl_cfg.vhd +-- +-- Date of Creation: Mon Aug 9 12:14:48 1999 +-- +-- Version: $Revision: 1.4 $ +-- +-- Date of Latest Version: $Date: 2002-01-07 12:17:44 $ +-- +-- +-- Description: Combinational design to calculate the decimal +-- representation (BCD) of a data bus. +-- +-- +-- +-- +------------------------------------------------------------------------------- +configuration dcml_adjust_rtl_cfg of dcml_adjust is + + for rtl + + end for; + +end dcml_adjust_rtl_cfg; diff --git a/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/8051/mc8051_alu_.vhd b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/8051/mc8051_alu_.vhd new file mode 100644 index 0000000000000000000000000000000000000000..660dc051878eec5e0dfbd591481d6265c60f4e32 --- /dev/null +++ b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/8051/mc8051_alu_.vhd @@ -0,0 +1,103 @@ +------------------------------------------------------------------------------- +-- -- +-- X X XXXXXX XXXXXX XXXXXX XXXXXX X -- +-- XX XX X X X X X X X XX -- +-- X X X X X X X X X X X X -- +-- X X X X X X X X X X X X -- +-- X X X X XXXXXX X X XXXXXX X -- +-- X X X X X X X X X -- +-- X X X X X X X X X -- +-- X X X X X X X X X X -- +-- X X XXXXXX XXXXXX XXXXXX XXXXXX X -- +-- -- +-- -- +-- O R E G A N O S Y S T E M S -- +-- -- +-- Design & Consulting -- +-- -- +------------------------------------------------------------------------------- +-- -- +-- Web: http://www.oregano.at/ -- +-- -- +-- Contact: mc8051@oregano.at -- +-- -- +------------------------------------------------------------------------------- +-- -- +-- MC8051 - VHDL 8051 Microcontroller IP Core -- +-- Copyright (C) 2001 OREGANO SYSTEMS -- +-- -- +-- This library is free software; you can redistribute it and/or -- +-- modify it under the terms of the GNU Lesser General Public -- +-- License as published by the Free Software Foundation; either -- +-- version 2.1 of the License, or (at your option) any later version. -- +-- -- +-- This library is distributed in the hope that it will be useful, -- +-- but WITHOUT ANY WARRANTY; without even the implied warranty of -- +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -- +-- Lesser General Public License for more details. -- +-- -- +-- Full details of the license can be found in the file LGPL.TXT. -- +-- -- +-- You should have received a copy of the GNU Lesser General Public -- +-- License along with this library; if not, write to the Free Software -- +-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -- +-- -- +------------------------------------------------------------------------------- +-- +-- +-- Author: Roland Hller +-- +-- Filename: mc8051_alu_.vhd +-- +-- Date of Creation: Mon Aug 9 12:14:48 1999 +-- +-- Version: $Revision: 1.7 $ +-- +-- Date of Latest Version: $Date: 2002-01-07 12:17:44 $ +-- +-- +-- Description: Connects the units alumux, alucore, addsub_core, +-- comb_mltplr, comb_divider, and dcml_adjust together. +-- The whole design is made up of combinational logic. +-- +-- +-- +-- +------------------------------------------------------------------------------- +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.std_logic_arith.all; +library work; +use work.mc8051_p.all; + +-----------------------------ENTITY DECLARATION-------------------------------- + +entity mc8051_alu is + + generic (DWIDTH : integer := 8); -- Data width of the ALU + + port (rom_data_i : in std_logic_vector(DWIDTH-1 downto 0); + ram_data_i : in std_logic_vector(DWIDTH-1 downto 0); + acc_i : in std_logic_vector(DWIDTH-1 downto 0); + cmd_i : in std_logic_vector(5 downto 0); + cy_i : in std_logic_vector((DWIDTH-1)/4 downto 0); + ov_i : in std_logic; + + new_cy_o : out std_logic_vector((DWIDTH-1)/4 downto 0); + new_ov_o : out std_logic; + result_a_o : out std_logic_vector(DWIDTH-1 downto 0); + result_b_o : out std_logic_vector(DWIDTH-1 downto 0)); + +end mc8051_alu; +--Inputs: +-- rom_data_i...... data input from ROM +-- ram_data_i...... data input from RAM +-- acc_i........... the contents of the accumulator register +-- cmd_i........... command from the control unit +-- cy_i............ CY-Flags of the SFR +-- ov_i............ OV-Flag of the SFR +--Outputs: +-- new_cy_o........ new CY-Flags for SFR +-- new_ov_o........ new OV-Flag for SFR +-- result_a_o...... result +-- result_b_o...... result diff --git a/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/8051/mc8051_alu_struc.vhd b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/8051/mc8051_alu_struc.vhd new file mode 100644 index 0000000000000000000000000000000000000000..25555dab637d602b3c8cb3c6dbf41d6bc7bf2645 --- /dev/null +++ b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/8051/mc8051_alu_struc.vhd @@ -0,0 +1,197 @@ +------------------------------------------------------------------------------- +-- -- +-- X X XXXXXX XXXXXX XXXXXX XXXXXX X -- +-- XX XX X X X X X X X XX -- +-- X X X X X X X X X X X X -- +-- X X X X X X X X X X X X -- +-- X X X X XXXXXX X X XXXXXX X -- +-- X X X X X X X X X -- +-- X X X X X X X X X -- +-- X X X X X X X X X X -- +-- X X XXXXXX XXXXXX XXXXXX XXXXXX X -- +-- -- +-- -- +-- O R E G A N O S Y S T E M S -- +-- -- +-- Design & Consulting -- +-- -- +------------------------------------------------------------------------------- +-- -- +-- Web: http://www.oregano.at/ -- +-- -- +-- Contact: mc8051@oregano.at -- +-- -- +------------------------------------------------------------------------------- +-- -- +-- MC8051 - VHDL 8051 Microcontroller IP Core -- +-- Copyright (C) 2001 OREGANO SYSTEMS -- +-- -- +-- This library is free software; you can redistribute it and/or -- +-- modify it under the terms of the GNU Lesser General Public -- +-- License as published by the Free Software Foundation; either -- +-- version 2.1 of the License, or (at your option) any later version. -- +-- -- +-- This library is distributed in the hope that it will be useful, -- +-- but WITHOUT ANY WARRANTY; without even the implied warranty of -- +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -- +-- Lesser General Public License for more details. -- +-- -- +-- Full details of the license can be found in the file LGPL.TXT. -- +-- -- +-- You should have received a copy of the GNU Lesser General Public -- +-- License along with this library; if not, write to the Free Software -- +-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -- +-- -- +------------------------------------------------------------------------------- +-- +-- +-- Author: Roland Hller +-- +-- Filename: mc8051_alu_struc.vhd +-- +-- Date of Creation: Mon Aug 9 12:14:48 1999 +-- +-- Version: $Revision: 1.9 $ +-- +-- Date of Latest Version: $Date: 2006-09-07 10:02:11 $ +-- +-- +-- Description: Connects the units alumux, alucore, addsub_core, +-- comb_mltplr, comb_divider, and dcml_adjust together. +-- The whole design is made up of combinational logic. +-- +-- +-- +-- +------------------------------------------------------------------------------- +architecture struc of mc8051_alu is + + signal s_alu_result : std_logic_vector(DWIDTH-1 downto 0); + signal s_alu_new_cy : std_logic_vector((DWIDTH-1)/4 downto 0); + signal s_alu_op_a : std_logic_vector(DWIDTH-1 downto 0); + signal s_alu_op_b : std_logic_vector(DWIDTH-1 downto 0); + signal s_alu_cmd : std_logic_vector(3 downto 0); + signal s_dvdnd : std_logic_vector(DWIDTH-1 downto 0); + signal s_dvsor : std_logic_vector(DWIDTH-1 downto 0); + signal s_qutnt : std_logic_vector(DWIDTH-1 downto 0); + signal s_rmndr : std_logic_vector(DWIDTH-1 downto 0); + signal s_mltplcnd : std_logic_vector(DWIDTH-1 downto 0); + signal s_mltplctr : std_logic_vector(DWIDTH-1 downto 0); + signal s_product : std_logic_vector((DWIDTH*2)-1 downto 0); + signal s_dcml_data : std_logic_vector(DWIDTH-1 downto 0); + signal s_dcml_rslt : std_logic_vector(DWIDTH-1 downto 0); + signal s_dcml_cy : std_logic; + signal s_addsub_rslt : std_logic_vector(DWIDTH-1 downto 0); + signal s_addsub_newcy : std_logic_vector((DWIDTH-1)/4 downto 0); + signal s_addsub_ov : std_logic; + signal s_addsub_cy : std_logic; + signal s_addsub : std_logic; + signal s_addsub_opa : std_logic_vector(DWIDTH-1 downto 0); + signal s_addsub_opb : std_logic_vector(DWIDTH-1 downto 0); + +begin -- architecture structural + + i_alumux : alumux + generic map ( + DWIDTH => DWIDTH) + port map ( + -- Primary I/Os of the ALU unit. + rom_data_i => rom_data_i, + ram_data_i => ram_data_i, + acc_i => acc_i, + cmd_i => cmd_i, + cy_i => cy_i, + ov_i => ov_i, + cy_o => new_cy_o, + ov_o => new_ov_o, + result_a_o => result_a_o, + result_b_o => result_b_o, + -- I/Os connecting the submodules. + result_i => s_alu_result, + new_cy_i => s_alu_new_cy, + addsub_rslt_i => s_addsub_rslt, + addsub_cy_i => s_addsub_newcy, + addsub_ov_i => s_addsub_ov, + op_a_o => s_alu_op_a, + op_b_o => s_alu_op_b, + alu_cmd_o => s_alu_cmd, + opa_o => s_addsub_opa, + opb_o => s_addsub_opb, + addsub_o => s_addsub, + addsub_cy_o => s_addsub_cy, + dvdnd_o => s_dvdnd, + dvsor_o => s_dvsor, + qutnt_i => s_qutnt, + rmndr_i => s_rmndr, + mltplcnd_o => s_mltplcnd, + mltplctr_o => s_mltplctr, + product_i => s_product, + dcml_data_o => s_dcml_data, + dcml_data_i => s_dcml_rslt, + dcml_cy_i => s_dcml_cy); + + i_alucore : alucore + generic map ( + DWIDTH => DWIDTH) + port map ( + op_a_i => s_alu_op_a, + op_b_i => s_alu_op_b, + alu_cmd_i => s_alu_cmd, + cy_i => cy_i, + cy_o => s_alu_new_cy, + result_o => s_alu_result); + + i_addsub_core : addsub_core + generic map (DWIDTH => DWIDTH) + port map (opa_i => s_addsub_opa, + opb_i => s_addsub_opb, + addsub_i => s_addsub, + cy_i => s_addsub_cy, + cy_o => s_addsub_newcy, + ov_o => s_addsub_ov, + rslt_o => s_addsub_rslt); + + gen_multiplier1 : if C_IMPL_MUL = 1 generate + i_comb_mltplr : comb_mltplr + generic map ( + DWIDTH => DWIDTH) + port map ( + mltplcnd_i => s_mltplcnd, + mltplctr_i => s_mltplctr, + product_o => s_product); + end generate gen_multiplier1; + gen_multiplier0 : if C_IMPL_MUL /= 1 generate + s_product <= (others => '0'); + end generate gen_multiplier0; + + gen_divider1 : if C_IMPL_DIV = 1 generate + i_comb_divider : comb_divider + generic map ( + DWIDTH => DWIDTH) + port map ( + dvdnd_i => s_dvdnd, + dvsor_i => s_dvsor, + qutnt_o => s_qutnt, + rmndr_o => s_rmndr); + end generate gen_divider1; + gen_divider0 : if C_IMPL_DIV /= 1 generate + s_qutnt <= (others => '0'); + s_rmndr <= (others => '0'); + end generate gen_divider0; + + gen_dcml_adj1 : if C_IMPL_DA = 1 generate + i_dcml_adjust : dcml_adjust + generic map ( + DWIDTH => DWIDTH) + port map ( + data_i => s_dcml_data, + cy_i => cy_i, + data_o => s_dcml_rslt, + cy_o => s_dcml_cy); + end generate gen_dcml_adj1; + gen_dcml_adj0 : if C_IMPL_DA /= 1 generate + s_dcml_rslt <= (others => '0'); + s_dcml_cy <= '0'; + end generate gen_dcml_adj0; + +end struc; diff --git a/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/8051/mc8051_alu_struc_cfg.vhd b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/8051/mc8051_alu_struc_cfg.vhd new file mode 100644 index 0000000000000000000000000000000000000000..8866437d8fccf0a149fd485ea22ce99c310a8284 --- /dev/null +++ b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/8051/mc8051_alu_struc_cfg.vhd @@ -0,0 +1,96 @@ +------------------------------------------------------------------------------- +-- -- +-- X X XXXXXX XXXXXX XXXXXX XXXXXX X -- +-- XX XX X X X X X X X XX -- +-- X X X X X X X X X X X X -- +-- X X X X X X X X X X X X -- +-- X X X X XXXXXX X X XXXXXX X -- +-- X X X X X X X X X -- +-- X X X X X X X X X -- +-- X X X X X X X X X X -- +-- X X XXXXXX XXXXXX XXXXXX XXXXXX X -- +-- -- +-- -- +-- O R E G A N O S Y S T E M S -- +-- -- +-- Design & Consulting -- +-- -- +------------------------------------------------------------------------------- +-- -- +-- Web: http://www.oregano.at/ -- +-- -- +-- Contact: mc8051@oregano.at -- +-- -- +------------------------------------------------------------------------------- +-- -- +-- MC8051 - VHDL 8051 Microcontroller IP Core -- +-- Copyright (C) 2001 OREGANO SYSTEMS -- +-- -- +-- This library is free software; you can redistribute it and/or -- +-- modify it under the terms of the GNU Lesser General Public -- +-- License as published by the Free Software Foundation; either -- +-- version 2.1 of the License, or (at your option) any later version. -- +-- -- +-- This library is distributed in the hope that it will be useful, -- +-- but WITHOUT ANY WARRANTY; without even the implied warranty of -- +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -- +-- Lesser General Public License for more details. -- +-- -- +-- Full details of the license can be found in the file LGPL.TXT. -- +-- -- +-- You should have received a copy of the GNU Lesser General Public -- +-- License along with this library; if not, write to the Free Software -- +-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -- +-- -- +------------------------------------------------------------------------------- +-- +-- +-- Author: Roland Hller +-- +-- Filename: mc8051_alu_struc_cfg.vhd +-- +-- Date of Creation: Mon Aug 9 12:14:48 1999 +-- +-- Version: $Revision: 1.6 $ +-- +-- Date of Latest Version: $Date: 2006-09-07 10:02:31 $ +-- +-- +-- Description: Connects the units alumux, alucore, addsub_core, +-- comb_mltplr, comb_divider, and dcml_adjust together. +-- The whole design is made up of combinational logic. +-- +-- +-- +-- +------------------------------------------------------------------------------- +configuration mc8051_alu_struc_cfg of mc8051_alu is + + for struc + for i_alumux : alumux + use configuration work.alumux_rtl_cfg; + end for; + for i_alucore : alucore + use configuration work.alucore_rtl_cfg; + end for; + for i_addsub_core : addsub_core + use configuration work.addsub_core_struc_cfg; + end for; + for gen_multiplier1 + for all : comb_mltplr + use configuration work.comb_mltplr_rtl_cfg; + end for; + end for; + for gen_divider1 + for all : comb_divider + use configuration work.comb_divider_rtl_cfg; + end for; + end for; + for gen_dcml_adj1 + for all : dcml_adjust + use configuration work.dcml_adjust_rtl_cfg; + end for; + end for; + end for; + +end mc8051_alu_struc_cfg; diff --git a/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/8051/mc8051_control_.vhd b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/8051/mc8051_control_.vhd new file mode 100644 index 0000000000000000000000000000000000000000..98060c7837beb7db8f01fd9ea9a56b891bda2c6e --- /dev/null +++ b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/8051/mc8051_control_.vhd @@ -0,0 +1,144 @@ +------------------------------------------------------------------------------- +-- -- +-- X X XXXXXX XXXXXX XXXXXX XXXXXX X -- +-- XX XX X X X X X X X XX -- +-- X X X X X X X X X X X X -- +-- X X X X X X X X X X X X -- +-- X X X X XXXXXX X X XXXXXX X -- +-- X X X X X X X X X -- +-- X X X X X X X X X -- +-- X X X X X X X X X X -- +-- X X XXXXXX XXXXXX XXXXXX XXXXXX X -- +-- -- +-- -- +-- O R E G A N O S Y S T E M S -- +-- -- +-- Design & Consulting -- +-- -- +------------------------------------------------------------------------------- +-- -- +-- Web: http://www.oregano.at/ -- +-- -- +-- Contact: mc8051@oregano.at -- +-- -- +------------------------------------------------------------------------------- +-- -- +-- MC8051 - VHDL 8051 Microcontroller IP Core -- +-- Copyright (C) 2001 OREGANO SYSTEMS -- +-- -- +-- This library is free software; you can redistribute it and/or -- +-- modify it under the terms of the GNU Lesser General Public -- +-- License as published by the Free Software Foundation; either -- +-- version 2.1 of the License, or (at your option) any later version. -- +-- -- +-- This library is distributed in the hope that it will be useful, -- +-- but WITHOUT ANY WARRANTY; without even the implied warranty of -- +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -- +-- Lesser General Public License for more details. -- +-- -- +-- Full details of the license can be found in the file LGPL.TXT. -- +-- -- +-- You should have received a copy of the GNU Lesser General Public -- +-- License along with this library; if not, write to the Free Software -- +-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -- +-- -- +------------------------------------------------------------------------------- +-- +-- +-- Author: Helmut Mayrhofer +-- +-- Filename: mc8051_control_.vhd +-- +-- Date of Creation: Mon Aug 9 12:14:48 1999 +-- +-- Version: $Revision: 1.7 $ +-- +-- Date of Latest Version: $Date: 2002-01-07 12:17:45 $ +-- +-- +-- Description: Connects the units control_fsm and control_mem. This +-- unit manages the whole microcontroller core. +-- +-- +-- +-- +------------------------------------------------------------------------------- +library IEEE; +library work; +use IEEE.std_logic_1164.all; +use IEEE.std_logic_arith.all; +use work.mc8051_p.all; + + +------------------------ ENTITY DECLARATION ------------------------- +entity mc8051_control is + + port (pc_o : out std_logic_vector(15 downto 0); -- Programmcounter = + -- ROM-adress + rom_data_i : in std_logic_vector(7 downto 0); -- data input from ROM + ram_data_o : out std_logic_vector(7 downto 0); -- data output to + -- internal RAM + ram_data_i : in std_logic_vector(7 downto 0); -- data input from + -- internal RAM + ram_adr_o : out std_logic_vector(6 downto 0); -- internal RAM-adress + reg_data_o : out std_logic_vector(7 downto 0); -- data for ALU + ram_wr_o : out std_logic; -- read (0) / write (1) + -- internal RAM + cy_o : out std_logic_vector(1 downto 0); -- Carry Flag + ov_o : out std_logic; -- Overflow Flag + ram_en_o : out std_logic; -- RAM-block enable + alu_cmd_o : out std_logic_vector (5 downto 0); -- ALU operationscode + aludata_i : in std_logic_vector (7 downto 0); -- ALU result + aludatb_i : in std_logic_vector (7 downto 0); -- 2nd ALU result + acc_o : out std_logic_vector (7 downto 0); -- ACC register + new_cy_i : in std_logic_vector(1 downto 0); -- CY result of ALU + new_ov_i : in std_logic; -- OV result of ALU + reset : in std_logic; -- reset signal + clk : in std_logic; -- clock signal + cen : in std_logic; -- clock enable signal + int0_i : in std_logic_vector(C_IMPL_N_EXT-1 downto 0); -- ext.Int + int1_i : in std_logic_vector(C_IMPL_N_EXT-1 downto 0); -- ext.Int + + datax_i : in std_logic_vector (7 downto 0); -- ext. RAM + datax_o : out std_logic_vector (7 downto 0); -- ext. RAM + adrx_o : out std_logic_vector (15 downto 0); -- ext. RAM + wrx_o : out std_logic; -- ext. RAM + memx_o : out std_logic; -- ext. RAM + + p0_i : in std_logic_vector(7 downto 0); -- IO-port0 + p1_i : in std_logic_vector(7 downto 0); -- IO-port1 + p2_i : in std_logic_vector(7 downto 0); -- IO-port2 + p3_i : in std_logic_vector(7 downto 0); -- IO-port3 + + p0_o : out std_logic_vector(7 downto 0); -- IO-port0 + p1_o : out std_logic_vector(7 downto 0); -- IO-port1 + p2_o : out std_logic_vector(7 downto 0); -- IO-port2 + p3_o : out std_logic_vector(7 downto 0); -- IO-port3 + + -- Signals to and from the SIUs + + all_trans_o : out std_logic_vector(C_IMPL_N_SIU-1 downto 0); + all_scon_o : out std_logic_vector(6*C_IMPL_N_SIU-1 downto 0); + all_sbuf_o : out std_logic_vector(8*C_IMPL_N_SIU-1 downto 0); + all_smod_o : out std_logic_vector(C_IMPL_N_SIU-1 downto 0); + all_scon_i : in std_logic_vector(3*C_IMPL_N_SIU-1 downto 0); + all_sbuf_i : in std_logic_vector(8*C_IMPL_N_SIU-1 downto 0); + + -- signals to and from the timer/counters + + all_tcon_tr0_o : out std_logic_vector(C_IMPL_N_TMR-1 downto 0); + all_tcon_tr1_o : out std_logic_vector(C_IMPL_N_TMR-1 downto 0); + all_tmod_o : out std_logic_vector(8*C_IMPL_N_TMR-1 downto 0); + all_reload_o : out std_logic_vector(8*C_IMPL_N_TMR-1 downto 0); + all_wt_o : out std_logic_vector(2*C_IMPL_N_TMR-1 downto 0); + all_wt_en_o : out std_logic_vector(C_IMPL_N_TMR-1 downto 0); + + all_tf0_i : in std_logic_vector(C_IMPL_N_TMR-1 downto 0); + all_tf1_i : in std_logic_vector(C_IMPL_N_TMR-1 downto 0); + all_tl0_i : in std_logic_vector(8*C_IMPL_N_TMR-1 downto 0); + all_tl1_i : in std_logic_vector(8*C_IMPL_N_TMR-1 downto 0); + all_th0_i : in std_logic_vector(8*C_IMPL_N_TMR-1 downto 0); + all_th1_i : in std_logic_vector(8*C_IMPL_N_TMR-1 downto 0)); + +end mc8051_control; + diff --git a/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/8051/mc8051_control_struc.vhd b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/8051/mc8051_control_struc.vhd new file mode 100644 index 0000000000000000000000000000000000000000..16c3f57c6d42e3d46e5748826a996d1e9edca44f --- /dev/null +++ b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/8051/mc8051_control_struc.vhd @@ -0,0 +1,269 @@ +------------------------------------------------------------------------------- +-- -- +-- X X XXXXXX XXXXXX XXXXXX XXXXXX X -- +-- XX XX X X X X X X X XX -- +-- X X X X X X X X X X X X -- +-- X X X X X X X X X X X X -- +-- X X X X XXXXXX X X XXXXXX X -- +-- X X X X X X X X X -- +-- X X X X X X X X X -- +-- X X X X X X X X X X -- +-- X X XXXXXX XXXXXX XXXXXX XXXXXX X -- +-- -- +-- -- +-- O R E G A N O S Y S T E M S -- +-- -- +-- Design & Consulting -- +-- -- +------------------------------------------------------------------------------- +-- -- +-- Web: http://www.oregano.at/ -- +-- -- +-- Contact: mc8051@oregano.at -- +-- -- +------------------------------------------------------------------------------- +-- -- +-- MC8051 - VHDL 8051 Microcontroller IP Core -- +-- Copyright (C) 2001 OREGANO SYSTEMS -- +-- -- +-- This library is free software; you can redistribute it and/or -- +-- modify it under the terms of the GNU Lesser General Public -- +-- License as published by the Free Software Foundation; either -- +-- version 2.1 of the License, or (at your option) any later version. -- +-- -- +-- This library is distributed in the hope that it will be useful, -- +-- but WITHOUT ANY WARRANTY; without even the implied warranty of -- +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -- +-- Lesser General Public License for more details. -- +-- -- +-- Full details of the license can be found in the file LGPL.TXT. -- +-- -- +-- You should have received a copy of the GNU Lesser General Public -- +-- License along with this library; if not, write to the Free Software -- +-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -- +-- -- +------------------------------------------------------------------------------- +-- +-- +-- Author: Helmut Mayrhofer +-- +-- Filename: mc8051_control_struc.vhd +-- +-- Date of Creation: Mon Aug 9 12:14:48 1999 +-- +-- Version: $Revision: 1.7 $ +-- +-- Date of Latest Version: $Date: 2006-09-07 10:03:45 $ +-- +-- +-- Description: Connects the units control_fsm and control_mem. This +-- unit manages the whole microcontroller core. +-- +-- +-- +-- +------------------------------------------------------------------------------- +architecture struc of mc8051_control is + + -- signals connecting the fsm and the mem unit + + signal s_pc_inc_en : std_logic_vector (3 downto 0); + signal s_regs_wr_en : std_logic_vector (2 downto 0); + signal s_data_mux : std_logic_vector (3 downto 0); + signal s_bdata_mux : std_logic_vector (3 downto 0); + signal s_adr_mux : std_logic_vector (3 downto 0); + signal s_adrx_mux : std_logic_vector (1 downto 0); + signal s_wrx_mux : std_logic; + signal s_help_en : std_logic_vector (3 downto 0); + signal s_help16_en : std_logic_vector (1 downto 0); + signal s_helpb_en : std_logic; + signal s_intpre2_d : std_logic; + signal s_intpre2_en : std_logic; + signal s_intlow_d : std_logic; + signal s_intlow_en : std_logic; + signal s_inthigh_d : std_logic; + signal s_inthigh_en : std_logic; + signal s_nextstate : t_state; -- enable signal for state + signal state : t_state; -- actual state + signal s_command : std_logic_vector (7 downto 0); + signal s_help : std_logic_vector(7 downto 0); -- general help-register + signal s_bit_data : std_logic; + signal s_intpre : std_logic; -- an interrupt must start + signal s_intpre2 : std_logic; -- prepare for interrupt + signal s_inthigh : std_logic; -- high priority int is running + signal s_intlow : std_logic; -- low priority int is running + signal s_intblock : std_logic; -- interrupt delay at RETI, IE, IP + signal s_ri : std_logic; + signal s_ti : std_logic; + signal s_tf1 : std_logic; + signal s_tf0 : std_logic; + signal s_ie1 : std_logic; + signal s_ie0 : std_logic; + signal ie : std_logic_vector(7 downto 0); + signal ip : std_logic_vector(7 downto 0); + signal psw : std_logic_vector(7 downto 0); + signal acc : std_logic_vector(7 downto 0); + signal s_ext0isr_d : std_logic; + signal s_ext1isr_d : std_logic; + signal s_ext0isrh_d : std_logic; + signal s_ext1isrh_d : std_logic; + signal s_ext0isr_en : std_logic; + signal s_ext1isr_en : std_logic; + signal s_ext0isrh_en : std_logic; + signal s_ext1isrh_en : std_logic; + + + +begin -- architecture structural + + acc_o <= acc; + + i_control_fsm : control_fsm + port map(state_i => state, + help_i => s_help, + bit_data_i => s_bit_data, + aludata_i => aludata_i, + command_i => s_command, + inthigh_i => s_inthigh, + intlow_i => s_intlow, + intpre_i => s_intpre, + intpre2_i => s_intpre2, + intblock_i => s_intblock, + ti_i => s_ti, + ri_i => s_ri, + ie0_i => s_ie0, + ie1_i => s_ie1, + tf0_i => s_tf0, + tf1_i => s_tf1, + acc => acc, + psw => psw, + ie => ie, + ip => ip, + + alu_cmd_o => alu_cmd_o, + pc_inc_en_o => s_pc_inc_en, + nextstate_o => s_nextstate, + adr_mux_o => s_adr_mux, + adrx_mux_o => s_adrx_mux, + wrx_mux_o => s_wrx_mux, + data_mux_o => s_data_mux, + bdata_mux_o => s_bdata_mux, + regs_wr_en_o => s_regs_wr_en, + help_en_o => s_help_en, + help16_en_o => s_help16_en, + helpb_en_o => s_helpb_en, + inthigh_en_o => s_inthigh_en, + intlow_en_o => s_intlow_en, + intpre2_en_o => s_intpre2_en, + inthigh_d_o => s_inthigh_d, + intlow_d_o => s_intlow_d, + intpre2_d_o => s_intpre2_d, + ext0isr_d_o => s_ext0isr_d , + ext1isr_d_o => s_ext1isr_d , + ext0isrh_d_o => s_ext0isrh_d , + ext1isrh_d_o => s_ext1isrh_d , + ext0isr_en_o => s_ext0isr_en , + ext1isr_en_o => s_ext1isr_en , + ext0isrh_en_o => s_ext0isrh_en, + ext1isrh_en_o => s_ext1isrh_en); + + + i_control_mem : control_mem + port map(pc_o => pc_o, + rom_data_i => rom_data_i, + ram_data_o => ram_data_o, + ram_data_i => ram_data_i, + ram_adr_o => ram_adr_o, + reg_data_o => reg_data_o, + ram_wr_o => ram_wr_o, + cy_o => cy_o, + ov_o => ov_o, + ram_en_o => ram_en_o, + aludata_i => aludata_i, + aludatb_i => aludatb_i, + acc_o => acc, + new_cy_i => new_cy_i, + new_ov_i => new_ov_i, + reset => reset, + clk => clk, + cen => cen, + int0_i => int0_i, + int1_i => int1_i, + p0_i => p0_i, + p1_i => p1_i, + p2_i => p2_i, + p3_i => p3_i, + p0_o => p0_o, + p1_o => p1_o, + p2_o => p2_o, + p3_o => p3_o, + all_trans_o => all_trans_o, + all_scon_o => all_scon_o, + all_sbuf_o => all_sbuf_o, + all_smod_o => all_smod_o, + all_scon_i => all_scon_i, + all_sbuf_i => all_sbuf_i, + all_tcon_tr0_o => all_tcon_tr0_o, + all_tcon_tr1_o => all_tcon_tr1_o, + all_tmod_o => all_tmod_o, + all_reload_o => all_reload_o, + all_wt_o => all_wt_o, + all_wt_en_o => all_wt_en_o, + all_tf0_i => all_tf0_i, + all_tf1_i => all_tf1_i, + all_tl0_i => all_tl0_i, + all_tl1_i => all_tl1_i, + all_th0_i => all_th0_i, + all_th1_i => all_th1_i, + + state_o => state, + help_o => s_help, + bit_data_o => s_bit_data, + command_o => s_command, + inthigh_o => s_inthigh, + intlow_o => s_intlow, + intpre_o => s_intpre, + intpre2_o => s_intpre2, + intblock_o => s_intblock, + ti_o => s_ti, + ri_o => s_ri, + ie0_o => s_ie0, + ie1_o => s_ie1, + tf0_o => s_tf0, + tf1_o => s_tf1, + psw_o => psw, + ie_o => ie, + ip_o => ip, + adrx_o => adrx_o, + datax_o => datax_o, + wrx_o => wrx_o, + memx_o => memx_o, + + datax_i => datax_i, + pc_inc_en_i => s_pc_inc_en, + nextstate_i => s_nextstate, + adr_mux_i => s_adr_mux, + adrx_mux_i => s_adrx_mux, + wrx_mux_i => s_wrx_mux, + data_mux_i => s_data_mux, + bdata_mux_i => s_bdata_mux, + regs_wr_en_i => s_regs_wr_en, + help_en_i => s_help_en, + help16_en_i => s_help16_en, + helpb_en_i => s_helpb_en, + inthigh_en_i => s_inthigh_en, + intlow_en_i => s_intlow_en, + intpre2_en_i => s_intpre2_en, + inthigh_d_i => s_inthigh_d, + intlow_d_i => s_intlow_d, + intpre2_d_i => s_intpre2_d, + ext0isr_d_i => s_ext0isr_d , + ext1isr_d_i => s_ext1isr_d , + ext0isrh_d_i => s_ext0isrh_d , + ext1isrh_d_i => s_ext1isrh_d , + ext0isr_en_i => s_ext0isr_en , + ext1isr_en_i => s_ext1isr_en , + ext0isrh_en_i => s_ext0isrh_en, + ext1isrh_en_i => s_ext1isrh_en); + +end struc; diff --git a/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/8051/mc8051_control_struc_cfg.vhd b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/8051/mc8051_control_struc_cfg.vhd new file mode 100644 index 0000000000000000000000000000000000000000..b46fe74822f004d7fe497701c5a00021406c294e --- /dev/null +++ b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/8051/mc8051_control_struc_cfg.vhd @@ -0,0 +1,75 @@ +------------------------------------------------------------------------------- +-- -- +-- X X XXXXXX XXXXXX XXXXXX XXXXXX X -- +-- XX XX X X X X X X X XX -- +-- X X X X X X X X X X X X -- +-- X X X X X X X X X X X X -- +-- X X X X XXXXXX X X XXXXXX X -- +-- X X X X X X X X X -- +-- X X X X X X X X X -- +-- X X X X X X X X X X -- +-- X X XXXXXX XXXXXX XXXXXX XXXXXX X -- +-- -- +-- -- +-- O R E G A N O S Y S T E M S -- +-- -- +-- Design & Consulting -- +-- -- +------------------------------------------------------------------------------- +-- -- +-- Web: http://www.oregano.at/ -- +-- -- +-- Contact: mc8051@oregano.at -- +-- -- +------------------------------------------------------------------------------- +-- -- +-- MC8051 - VHDL 8051 Microcontroller IP Core -- +-- Copyright (C) 2001 OREGANO SYSTEMS -- +-- -- +-- This library is free software; you can redistribute it and/or -- +-- modify it under the terms of the GNU Lesser General Public -- +-- License as published by the Free Software Foundation; either -- +-- version 2.1 of the License, or (at your option) any later version. -- +-- -- +-- This library is distributed in the hope that it will be useful, -- +-- but WITHOUT ANY WARRANTY; without even the implied warranty of -- +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -- +-- Lesser General Public License for more details. -- +-- -- +-- Full details of the license can be found in the file LGPL.TXT. -- +-- -- +-- You should have received a copy of the GNU Lesser General Public -- +-- License along with this library; if not, write to the Free Software -- +-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -- +-- -- +------------------------------------------------------------------------------- +-- +-- +-- Author: Helmut Mayrhofer +-- +-- Filename: mc8051_control_struc_cfg.vhd +-- +-- Date of Creation: Mon Aug 9 12:14:48 1999 +-- +-- Version: $Revision: 1.4 $ +-- +-- Date of Latest Version: $Date: 2002-01-07 12:17:45 $ +-- +-- +-- Description: Connects the units control_fsm and control_mem. This +-- unit manages the whole microcontroller core. +-- +-- +-- +-- +------------------------------------------------------------------------------- +configuration mc8051_control_struc_cfg of mc8051_control is + for struc + for i_control_fsm : control_fsm + use configuration work.control_fsm_rtl_cfg; + end for; + for i_control_mem : control_mem + use configuration work.control_mem_rtl_cfg; + end for; + end for; +end mc8051_control_struc_cfg; diff --git a/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/8051/mc8051_core_.vhd b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/8051/mc8051_core_.vhd new file mode 100644 index 0000000000000000000000000000000000000000..32b92c9af7a8e623423d049af67bc4d2095ea850 --- /dev/null +++ b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/8051/mc8051_core_.vhd @@ -0,0 +1,122 @@ +------------------------------------------------------------------------------- +-- -- +-- X X XXXXXX XXXXXX XXXXXX XXXXXX X -- +-- XX XX X X X X X X X XX -- +-- X X X X X X X X X X X X -- +-- X X X X X X X X X X X X -- +-- X X X X XXXXXX X X XXXXXX X -- +-- X X X X X X X X X -- +-- X X X X X X X X X -- +-- X X X X X X X X X X -- +-- X X XXXXXX XXXXXX XXXXXX XXXXXX X -- +-- -- +-- -- +-- O R E G A N O S Y S T E M S -- +-- -- +-- Design & Consulting -- +-- -- +------------------------------------------------------------------------------- +-- -- +-- Web: http://www.oregano.at/ -- +-- -- +-- Contact: mc8051@oregano.at -- +-- -- +------------------------------------------------------------------------------- +-- -- +-- MC8051 - VHDL 8051 Microcontroller IP Core -- +-- Copyright (C) 2001 OREGANO SYSTEMS -- +-- -- +-- This library is free software; you can redistribute it and/or -- +-- modify it under the terms of the GNU Lesser General Public -- +-- License as published by the Free Software Foundation; either -- +-- version 2.1 of the License, or (at your option) any later version. -- +-- -- +-- This library is distributed in the hope that it will be useful, -- +-- but WITHOUT ANY WARRANTY; without even the implied warranty of -- +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -- +-- Lesser General Public License for more details. -- +-- -- +-- Full details of the license can be found in the file LGPL.TXT. -- +-- -- +-- You should have received a copy of the GNU Lesser General Public -- +-- License along with this library; if not, write to the Free Software -- +-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -- +-- -- +------------------------------------------------------------------------------- +-- +-- +-- Author: Helmut Mayrhofer +-- +-- Filename: mc8051_core_.vhd +-- +-- Date of Creation: Mon Aug 9 12:14:48 1999 +-- +-- Version: $Revision: 1.8 $ +-- +-- Date of Latest Version: $Date: 2002-01-07 12:17:45 $ +-- +-- +-- Description: Connect the mc8051_control and mc8051_alu modules. +-- Generate and connect a certain number of mc8051_tmrctr +-- and mc8051_siu units. +-- +-- +-- +-- +------------------------------------------------------------------------------- +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.std_logic_arith.all; +library work; +use work.mc8051_p.all; + +-----------------------------ENTITY DECLARATION-------------------------------- + +entity mc8051_core is + + port (clk : in std_logic; -- system clock + cen : in std_logic; -- system clock enable + reset : in std_logic; -- system reset + rom_data_i : in std_logic_vector(7 downto 0); -- data input from ROM + ram_data_i : in std_logic_vector(7 downto 0); -- data input from + -- internal RAM + int0_i : in std_logic_vector(C_IMPL_N_EXT-1 downto 0); -- ext.Int + int1_i : in std_logic_vector(C_IMPL_N_EXT-1 downto 0); -- ext.Int + -- counter input 0 for T/C + all_t0_i : in std_logic_vector(C_IMPL_N_TMR-1 downto 0); + -- counter input 1 for T/C + all_t1_i : in std_logic_vector(C_IMPL_N_TMR-1 downto 0); + -- serial input for SIU + all_rxd_i : in std_logic_vector(C_IMPL_N_SIU-1 downto 0); + p0_i : in std_logic_vector(7 downto 0); -- IO-port0 input + p1_i : in std_logic_vector(7 downto 0); -- IO-port1 input + p2_i : in std_logic_vector(7 downto 0); -- IO-port2 input + p3_i : in std_logic_vector(7 downto 0); -- IO-port3 input + + p0_o : out std_logic_vector(7 downto 0); -- IO-port0 output + p1_o : out std_logic_vector(7 downto 0); -- IO-port1 output + p2_o : out std_logic_vector(7 downto 0); -- IO-port2 output + p3_o : out std_logic_vector(7 downto 0); -- IO-port3 output + -- M0 serial output for SIU + all_rxd_o : out std_logic_vector(C_IMPL_N_SIU-1 downto 0); + -- serial output for SIU + all_txd_o : out std_logic_vector(C_IMPL_N_SIU-1 downto 0); + -- rxd direction signal + all_rxdwr_o : out std_logic_vector(C_IMPL_N_SIU-1 downto 0); + + rom_adr_o : out std_logic_vector(15 downto 0); -- Programmcounter = + -- ROM-adress + ram_data_o : out std_logic_vector(7 downto 0); -- data output to + -- internal RAM + ram_adr_o : out std_logic_vector(6 downto 0); -- internal RAM-address + ram_wr_o : out std_logic; -- read (0) / write (1) + ram_en_o : out std_logic; -- RAM-block enable + + datax_i : in std_logic_vector (7 downto 0); -- ext. RAM data input + datax_o : out std_logic_vector (7 downto 0); -- ext. RAM data output + adrx_o : out std_logic_vector (15 downto 0); -- ext. RAM address + memx_o : out std_logic; -- ext. RAM access + wrx_o : out std_logic); -- ext. RAM write enable + +end mc8051_core; + diff --git a/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/8051/mc8051_core_struc.vhd b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/8051/mc8051_core_struc.vhd new file mode 100644 index 0000000000000000000000000000000000000000..47bb3ec7c20fc0195c87bfc975168a55e78af258 --- /dev/null +++ b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/8051/mc8051_core_struc.vhd @@ -0,0 +1,224 @@ +------------------------------------------------------------------------------- +-- -- +-- X X XXXXXX XXXXXX XXXXXX XXXXXX X -- +-- XX XX X X X X X X X XX -- +-- X X X X X X X X X X X X -- +-- X X X X X X X X X X X X -- +-- X X X X XXXXXX X X XXXXXX X -- +-- X X X X X X X X X -- +-- X X X X X X X X X -- +-- X X X X X X X X X X -- +-- X X XXXXXX XXXXXX XXXXXX XXXXXX X -- +-- -- +-- -- +-- O R E G A N O S Y S T E M S -- +-- -- +-- Design & Consulting -- +-- -- +------------------------------------------------------------------------------- +-- -- +-- Web: http://www.oregano.at/ -- +-- -- +-- Contact: mc8051@oregano.at -- +-- -- +------------------------------------------------------------------------------- +-- -- +-- MC8051 - VHDL 8051 Microcontroller IP Core -- +-- Copyright (C) 2001 OREGANO SYSTEMS -- +-- -- +-- This library is free software; you can redistribute it and/or -- +-- modify it under the terms of the GNU Lesser General Public -- +-- License as published by the Free Software Foundation; either -- +-- version 2.1 of the License, or (at your option) any later version. -- +-- -- +-- This library is distributed in the hope that it will be useful, -- +-- but WITHOUT ANY WARRANTY; without even the implied warranty of -- +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -- +-- Lesser General Public License for more details. -- +-- -- +-- Full details of the license can be found in the file LGPL.TXT. -- +-- -- +-- You should have received a copy of the GNU Lesser General Public -- +-- License along with this library; if not, write to the Free Software -- +-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -- +-- -- +------------------------------------------------------------------------------- +-- +-- +-- Author: Helmut Mayrhofer +-- +-- Filename: mc8051_core_struc.vhd +-- +-- Date of Creation: Mon Aug 9 12:14:48 1999 +-- +-- Version: $Revision: 1.9 $ +-- +-- Date of Latest Version: $Date: 2002-01-07 12:17:45 $ +-- +-- +-- Description: Connect the mc8051_control and mc8051_alu modules. +-- Generate and connect a certain number of mc8051_tmrctr +-- and mc8051_siu units. +-- +-- +-- +-- +------------------------------------------------------------------------------- +architecture struc of mc8051_core is + + -- signals connecting the control unit with the rest + + signal s_reg_data: std_logic_vector(7 downto 0); -- data for ALU + signal s_cy : std_logic_vector(1 downto 0); -- Carry Flag + signal s_ov : std_logic; -- Overflow Flag + signal s_alu_cmd: std_logic_vector (5 downto 0); -- ALU operationscode + signal s_alu_data0: std_logic_vector (7 downto 0); -- ALU result + signal s_alu_data1: std_logic_vector (7 downto 0); -- 2nd ALU result + signal s_acc: std_logic_vector (7 downto 0); -- ACC register + signal s_cyb: std_logic_vector (1 downto 0); -- CY result of ALU + signal s_ovb: std_logic; -- OV result of ALU + signal s_reset: std_logic; -- reset signal + signal s_clk: std_logic; -- clock signal + + -- signals to and from the SIUs + + signal s_all_trans : std_logic_vector(C_IMPL_N_SIU-1 downto 0); + signal s_all_scon : std_logic_vector(6*C_IMPL_N_SIU-1 downto 0); + signal s_all_sbuf : std_logic_vector(8*C_IMPL_N_SIU-1 downto 0); + signal s_all_smod : std_logic_vector(C_IMPL_N_SIU-1 downto 0); + signal s_all_scon_out : std_logic_vector(3*C_IMPL_N_SIU-1 downto 0); + signal s_all_sbuf_out : std_logic_vector(8*C_IMPL_N_SIU-1 downto 0); + + -- signals to and from the timer/counters + + signal s_all_tcon_tr0 : std_logic_vector(C_IMPL_N_TMR-1 downto 0); + signal s_all_tcon_tr1 : std_logic_vector(C_IMPL_N_TMR-1 downto 0); + signal s_all_tmod : std_logic_vector(8*C_IMPL_N_TMR-1 downto 0); + signal s_all_reload : std_logic_vector(8*C_IMPL_N_TMR-1 downto 0); + signal s_all_wt : std_logic_vector(2*C_IMPL_N_TMR-1 downto 0); + signal s_all_wt_en : std_logic_vector(C_IMPL_N_TMR-1 downto 0); + signal s_all_tf0 : std_logic_vector(C_IMPL_N_TMR-1 downto 0); + signal s_all_tf1 : std_logic_vector(C_IMPL_N_TMR-1 downto 0); + signal s_all_tl0 : std_logic_vector(8*C_IMPL_N_TMR-1 downto 0); + signal s_all_th0 : std_logic_vector(8*C_IMPL_N_TMR-1 downto 0); + signal s_all_tl1 : std_logic_vector(8*C_IMPL_N_TMR-1 downto 0); + signal s_all_th1 : std_logic_vector(8*C_IMPL_N_TMR-1 downto 0); + +begin -- architecture structural + + i_mc8051_control : mc8051_control + port map(pc_o => rom_adr_o, + rom_data_i => rom_data_i, + ram_data_o => ram_data_o, + ram_data_i => ram_data_i, + ram_adr_o => ram_adr_o, + reg_data_o => s_reg_data, + ram_wr_o => ram_wr_o, + cy_o => s_cy, + ov_o => s_ov, + ram_en_o => ram_en_o, + alu_cmd_o => s_alu_cmd, + aludata_i => s_alu_data0, + aludatb_i => s_alu_data1, + acc_o => s_acc, + new_cy_i => s_cyb, + new_ov_i => s_ovb, + reset => reset, + clk => clk, + cen => cen, + int0_i => int0_i, + int1_i => int1_i, + p0_i => p0_i, + p1_i => p1_i, + p2_i => p2_i, + p3_i => p3_i, + p0_o => p0_o, + p1_o => p1_o, + p2_o => p2_o, + p3_o => p3_o, + all_trans_o => s_all_trans, + all_scon_o => s_all_scon, + all_sbuf_o => s_all_sbuf, + all_smod_o => s_all_smod, + all_scon_i => s_all_scon_out, + all_sbuf_i => s_all_sbuf_out, + all_tcon_tr0_o => s_all_tcon_tr0, + all_tcon_tr1_o => s_all_tcon_tr1, + all_tmod_o => s_all_tmod, + all_reload_o => s_all_reload, + all_wt_o => s_all_wt, + all_wt_en_o => s_all_wt_en, + all_tf0_i => s_all_tf0, + all_tf1_i => s_all_tf1, + all_tl0_i => s_all_tl0, + all_tl1_i => s_all_tl1, + all_th0_i => s_all_th0, + all_th1_i => s_all_th1, + adrx_o => adrx_o, + datax_o => datax_o, + wrx_o => wrx_o, + memx_o => memx_o, + datax_i => datax_i); + + + i_mc8051_alu : mc8051_alu + generic map (DWIDTH => 8) + port map(rom_data_i => rom_data_i, -- inputs to mc8051_alu + ram_data_i => s_reg_data, + acc_i => s_acc, + cmd_i => s_alu_cmd, + cy_i => s_cy, + ov_i => s_ov, + + result_a_o => s_alu_data0, -- outputs of mc8051_alu + result_b_o => s_alu_data1, + new_cy_o => s_cyb, + new_ov_o => s_ovb); + + + gen_mc8051_siu : for i in c_impl_n_siu-1 downto 0 generate + i_mc8051_siu : mc8051_siu + port map (clk => clk, -- SIUs inputs + cen => cen, + reset => reset, + tf_i => s_all_tf1(i), + trans_i => s_all_trans(i), + rxd_i => all_rxd_i(i), + scon_i => s_all_scon((6*i)+5 downto i*6), + sbuf_i => s_all_sbuf((8*i)+7 downto i*8), + smod_i => s_all_smod(i), + -- SIUs outputs + sbuf_o => s_all_sbuf_out((8*i)+7 downto i*8), + scon_o => s_all_scon_out((3*i)+2 downto i*3), + rxdwr_o => all_rxdwr_o(i), + rxd_o => all_rxd_o(i), + txd_o => all_txd_o(i)); + end generate; + + + gen_mc8051_tmrctr : for i in c_impl_n_tmr-1 downto 0 generate + i_mc8051_tmrctr : mc8051_tmrctr + port map (clk => clk, -- tmr_ctr inputs + cen => cen, + reset => reset, + int0_i => int0_i(i), + int1_i => int1_i(i), + t0_i => all_t0_i(i), + t1_i => all_t1_i(i), + tmod_i => s_all_tmod((8*i)+7 downto i*8), + tcon_tr0_i => s_all_tcon_tr0(i), + tcon_tr1_i => s_all_tcon_tr1(i), + reload_i => s_all_reload((8*i)+7 downto i*8), + wt_en_i => s_all_wt_en(i), + wt_i => s_all_wt((2*i)+1 downto i*2), + -- tmr_ctr outputs + th0_o => s_all_th0((8*i)+7 downto i*8), + tl0_o => s_all_tl0((8*i)+7 downto i*8), + th1_o => s_all_th1((8*i)+7 downto i*8), + tl1_o => s_all_tl1((8*i)+7 downto i*8), + tf0_o => s_all_tf0(i), + tf1_o => s_all_tf1(i)); + end generate; + + +end struc; diff --git a/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/8051/mc8051_core_struc_cfg.vhd b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/8051/mc8051_core_struc_cfg.vhd new file mode 100644 index 0000000000000000000000000000000000000000..6d528fabb431a89fcdcaaf5862a303aeaabbee29 --- /dev/null +++ b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/8051/mc8051_core_struc_cfg.vhd @@ -0,0 +1,86 @@ +------------------------------------------------------------------------------- +-- -- +-- X X XXXXXX XXXXXX XXXXXX XXXXXX X -- +-- XX XX X X X X X X X XX -- +-- X X X X X X X X X X X X -- +-- X X X X X X X X X X X X -- +-- X X X X XXXXXX X X XXXXXX X -- +-- X X X X X X X X X -- +-- X X X X X X X X X -- +-- X X X X X X X X X X -- +-- X X XXXXXX XXXXXX XXXXXX XXXXXX X -- +-- -- +-- -- +-- O R E G A N O S Y S T E M S -- +-- -- +-- Design & Consulting -- +-- -- +------------------------------------------------------------------------------- +-- -- +-- Web: http://www.oregano.at/ -- +-- -- +-- Contact: mc8051@oregano.at -- +-- -- +------------------------------------------------------------------------------- +-- -- +-- MC8051 - VHDL 8051 Microcontroller IP Core -- +-- Copyright (C) 2001 OREGANO SYSTEMS -- +-- -- +-- This library is free software; you can redistribute it and/or -- +-- modify it under the terms of the GNU Lesser General Public -- +-- License as published by the Free Software Foundation; either -- +-- version 2.1 of the License, or (at your option) any later version. -- +-- -- +-- This library is distributed in the hope that it will be useful, -- +-- but WITHOUT ANY WARRANTY; without even the implied warranty of -- +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -- +-- Lesser General Public License for more details. -- +-- -- +-- Full details of the license can be found in the file LGPL.TXT. -- +-- -- +-- You should have received a copy of the GNU Lesser General Public -- +-- License along with this library; if not, write to the Free Software -- +-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -- +-- -- +------------------------------------------------------------------------------- +-- +-- +-- Author: Helmut Mayrhofer +-- +-- Filename: mc8051_core_struc_cfg.vhd +-- +-- Date of Creation: Mon Aug 9 12:14:48 1999 +-- +-- Version: $Revision: 1.6 $ +-- +-- Date of Latest Version: $Date: 2002-01-07 12:17:45 $ +-- +-- +-- Description: Connect the mc8051_control and mc8051_alu modules. +-- Generate and connect a certain number of mc8051_tmrctr +-- and mc8051_siu units. +-- +-- +-- +-- +------------------------------------------------------------------------------- +configuration mc8051_core_struc_cfg of mc8051_core is + for struc + for i_mc8051_control : mc8051_control + use configuration work.mc8051_control_struc_cfg; + end for; + for i_mc8051_alu : mc8051_alu + use configuration work.mc8051_alu_struc_cfg; + end for; + for gen_mc8051_siu + for all : mc8051_siu + use configuration work.mc8051_siu_rtl_cfg; + end for; + end for; + for gen_mc8051_tmrctr + for all : mc8051_tmrctr + use configuration work.mc8051_tmrctr_rtl_cfg; + end for; + end for; + end for; +end mc8051_core_struc_cfg; diff --git a/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/8051/mc8051_p.vhd b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/8051/mc8051_p.vhd new file mode 100644 index 0000000000000000000000000000000000000000..5739de814dc913e72937a53178a9a38cc24d892f --- /dev/null +++ b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/8051/mc8051_p.vhd @@ -0,0 +1,864 @@ +------------------------------------------------------------------------------- +-- -- +-- X X XXXXXX XXXXXX XXXXXX XXXXXX X -- +-- XX XX X X X X X X X XX -- +-- X X X X X X X X X X X X -- +-- X X X X X X X X X X X X -- +-- X X X X XXXXXX X X XXXXXX X -- +-- X X X X X X X X X -- +-- X X X X X X X X X -- +-- X X X X X X X X X X -- +-- X X XXXXXX XXXXXX XXXXXX XXXXXX X -- +-- -- +-- -- +-- O R E G A N O S Y S T E M S -- +-- -- +-- Design & Consulting -- +-- -- +------------------------------------------------------------------------------- +-- -- +-- Web: http://www.oregano.at/ -- +-- -- +-- Contact: mc8051@oregano.at -- +-- -- +------------------------------------------------------------------------------- +-- -- +-- MC8051 - VHDL 8051 Microcontroller IP Core -- +-- Copyright (C) 2001 OREGANO SYSTEMS -- +-- -- +-- This library is free software; you can redistribute it and/or -- +-- modify it under the terms of the GNU Lesser General Public -- +-- License as published by the Free Software Foundation; either -- +-- version 2.1 of the License, or (at your option) any later version. -- +-- -- +-- This library is distributed in the hope that it will be useful, -- +-- but WITHOUT ANY WARRANTY; without even the implied warranty of -- +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -- +-- Lesser General Public License for more details. -- +-- -- +-- Full details of the license can be found in the file LGPL.TXT. -- +-- -- +-- You should have received a copy of the GNU Lesser General Public -- +-- License along with this library; if not, write to the Free Software -- +-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -- +-- -- +------------------------------------------------------------------------------- +-- +-- +-- Author: Roland Hller +-- +-- Filename: mc8051_p.vhd +-- +-- Date of Creation: Mon Aug 9 12:14:48 1999 +-- +-- Version: $Revision: 1.16 $ +-- +-- Date of Latest Version: $Date: 2006-09-07 10:29:29 $ +-- +-- +-- Description: Collection of constants, types, and components. +-- +-- +-- +-- +------------------------------------------------------------------------------- +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.std_logic_arith.all; + +package mc8051_p is + + ----------------------------------------------------------------------------- + -- Set data width of mc8051_alu (no other than 8 supported at the moment!) + -- Default: 8 + constant C_DWIDTH : integer := 8; + ----------------------------------------------------------------------------- + + ----------------------------------------------------------------------------- + -- Select whether to implement (1) or skip (0) the multiplier + -- Default: 1 + constant C_IMPL_MUL : integer := 1; + ----------------------------------------------------------------------------- + + ----------------------------------------------------------------------------- + -- Select whether to implement (1) or skip (0) the divider + -- Default: 1 + constant C_IMPL_DIV : integer := 1; + ----------------------------------------------------------------------------- + + ----------------------------------------------------------------------------- + -- Select whether to implement (1) or skip (0) the decimal adjustment command + -- Default: 1 + constant C_IMPL_DA : integer := 1; + ----------------------------------------------------------------------------- + + ----------------------------------------------------------------------------- + -- Select how many timer/counter units should be implemented + -- Default: 1 + constant C_IMPL_N_TMR : integer := 1; + ----------------------------------------------------------------------------- + + ----------------------------------------------------------------------------- + -- Select how many serial interface units should be implemented + -- Default: C_IMPL_N_TMR ---(DO NOT CHANGE!)--- + constant C_IMPL_N_SIU : integer := C_IMPL_N_TMR; + ----------------------------------------------------------------------------- + + ----------------------------------------------------------------------------- + -- Select how many external interrupt-inputs should be implemented + -- Default: C_IMPL_N_TMR ---(DO NOT CHANGE!)--- + constant C_IMPL_N_EXT : integer := C_IMPL_N_TMR; + ----------------------------------------------------------------------------- + + constant OFF : std_logic_vector(5 downto 0) := "000000"; + constant DA : std_logic_vector(5 downto 0) := "100000"; + constant ADD_ACC_RAM : std_logic_vector(5 downto 0) := "100001"; + constant ADD_ACC_ROM : std_logic_vector(5 downto 0) := "100010"; + constant ADDC_ACC_RAM : std_logic_vector(5 downto 0) := "100011"; + constant ADDC_ACC_ROM : std_logic_vector(5 downto 0) := "100100"; + constant AND_ACC_RAM : std_logic_vector(5 downto 0) := "100101"; + constant AND_ACC_ROM : std_logic_vector(5 downto 0) := "100110"; + constant AND_RAM_ROM : std_logic_vector(5 downto 0) := "100111"; + constant SUB_ACC_RAM : std_logic_vector(5 downto 0) := "101000"; + constant SUB_ACC_ROM : std_logic_vector(5 downto 0) := "101001"; + constant MUL_ACC_RAM : std_logic_vector(5 downto 0) := "101010"; + constant DIV_ACC_RAM : std_logic_vector(5 downto 0) := "101011"; + constant OR_RAM_ACC : std_logic_vector(5 downto 0) := "101100"; + constant OR_ROM_ACC : std_logic_vector(5 downto 0) := "101101"; + constant OR_ROM_RAM : std_logic_vector(5 downto 0) := "101110"; + constant XOR_RAM_ACC : std_logic_vector(5 downto 0) := "101111"; + constant XOR_ROM_ACC : std_logic_vector(5 downto 0) := "110000"; + constant XOR_ROM_RAM : std_logic_vector(5 downto 0) := "110001"; + constant RL_ACC : std_logic_vector(5 downto 0) := "110010"; + constant RLC_ACC : std_logic_vector(5 downto 0) := "110011"; + constant RR_ACC : std_logic_vector(5 downto 0) := "110100"; + constant RRC_ACC : std_logic_vector(5 downto 0) := "110101"; + constant INV_ACC : std_logic_vector(5 downto 0) := "110110"; + constant INV_RAM : std_logic_vector(5 downto 0) := "110111"; + constant DEC_ACC : std_logic_vector(5 downto 0) := "111000"; + constant DEC_RAM : std_logic_vector(5 downto 0) := "111001"; + constant COMP_RAM_ACC : std_logic_vector(5 downto 0) := "111010"; + constant COMP_ROM_ACC : std_logic_vector(5 downto 0) := "111011"; + constant COMP_ROM_RAM : std_logic_vector(5 downto 0) := "111100"; + constant INC_ACC : std_logic_vector(5 downto 0) := "111110"; + constant INC_RAM : std_logic_vector(5 downto 0) := "111111"; + + constant ACALL : std_logic_vector(4 downto 0) := "10001"; + constant ADD_A_RR : std_logic_vector(4 downto 0) := "00101"; + constant ADD_A_D : std_logic_vector(7 downto 0) := "00100101"; + constant ADD_A_ATRI : std_logic_vector(6 downto 0) := "0010011"; + constant ADD_A_DATA : std_logic_vector(7 downto 0) := "00100100"; + constant ADDC_A_RR : std_logic_vector(4 downto 0) := "00111"; + constant ADDC_A_D : std_logic_vector(7 downto 0) := "00110101"; + constant ADDC_A_ATRI : std_logic_vector(6 downto 0) := "0011011"; + constant ADDC_A_DATA : std_logic_vector(7 downto 0) := "00110100"; + constant AJMP : std_logic_vector(4 downto 0) := "00001"; + constant ANL_A_RR : std_logic_vector(4 downto 0) := "01011"; + constant ANL_A_D : std_logic_vector(7 downto 0) := "01010101"; + constant ANL_A_ATRI : std_logic_vector(6 downto 0) := "0101011"; + constant ANL_A_DATA : std_logic_vector(7 downto 0) := "01010100"; + constant ANL_D_A : std_logic_vector(7 downto 0) := "01010010"; + constant ANL_D_DATA : std_logic_vector(7 downto 0) := "01010011"; + constant ANL_C_BIT : std_logic_vector(7 downto 0) := "10000010"; + constant ANL_C_NBIT : std_logic_vector(7 downto 0) := "10110000"; + constant CJNE_A_D : std_logic_vector(7 downto 0) := "10110101"; + constant CJNE_A_DATA : std_logic_vector(7 downto 0) := "10110100"; + constant CJNE_RR_DATA : std_logic_vector(4 downto 0) := "10111"; + constant CJNE_ATRI_DATA: std_logic_vector(6 downto 0) := "1011011" ; + constant CLR_A : std_logic_vector(7 downto 0) := "11100100"; + constant CLR_C : std_logic_vector(7 downto 0) := "11000011"; + constant CLR_BIT : std_logic_vector(7 downto 0) := "11000010"; + constant CPL_A : std_logic_vector(7 downto 0) := "11110100"; + constant CPL_C : std_logic_vector(7 downto 0) := "10110011"; + constant CPL_BIT : std_logic_vector(7 downto 0) := "10110010"; + constant DA_A : std_logic_vector(7 downto 0) := "11010100"; + constant DEC_A : std_logic_vector(7 downto 0) := "00010100"; + constant DEC_RR : std_logic_vector(4 downto 0) := "00011"; + constant DEC_D : std_logic_vector(7 downto 0) := "00010101"; + constant DEC_ATRI : std_logic_vector(6 downto 0) := "0001011"; + constant DIV_AB : std_logic_vector(7 downto 0) := "10000100"; + constant DJNZ_RR : std_logic_vector(4 downto 0) := "11011"; + constant DJNZ_D : std_logic_vector(7 downto 0) := "11010101"; + constant INC_A : std_logic_vector(7 downto 0) := "00000100"; + constant INC_RR : std_logic_vector(4 downto 0) := "00001"; + constant INC_D : std_logic_vector(7 downto 0) := "00000101"; + constant INC_ATRI : std_logic_vector(6 downto 0) := "0000011"; + constant INC_DPTR : std_logic_vector(7 downto 0) := "10100011"; + constant JB : std_logic_vector(7 downto 0) := "00100000"; + constant JBC : std_logic_vector(7 downto 0) := "00010000"; + constant JC : std_logic_vector(7 downto 0) := "01000000"; + constant JMP_A_DPTR : std_logic_vector(7 downto 0) := "01110011"; + constant JNB : std_logic_vector(7 downto 0) := "00110000"; + constant JNC : std_logic_vector(7 downto 0) := "01010000"; + constant JNZ : std_logic_vector(7 downto 0) := "01110000"; + constant JZ : std_logic_vector(7 downto 0) := "01100000"; + constant LCALL : std_logic_vector(7 downto 0) := "00010010"; + constant LJMP : std_logic_vector(7 downto 0) := "00000010"; + constant MOV_A_RR : std_logic_vector(4 downto 0) := "11101"; + constant MOV_A_D : std_logic_vector(7 downto 0) := "11100101"; + constant MOV_A_ATRI : std_logic_vector(6 downto 0) := "1110011"; + constant MOV_A_DATA : std_logic_vector(7 downto 0) := "01110100"; + constant MOV_RR_A : std_logic_vector(4 downto 0) := "11111"; + constant MOV_RR_D : std_logic_vector(4 downto 0) := "10101"; + constant MOV_RR_DATA : std_logic_vector(4 downto 0) := "01111"; + constant MOV_D_A : std_logic_vector(7 downto 0) := "11110101"; + constant MOV_D_RR : std_logic_vector(4 downto 0) := "10001"; + constant MOV_D_D : std_logic_vector(7 downto 0) := "10000101"; + constant MOV_D_ATRI : std_logic_vector(6 downto 0) := "1000011"; + constant MOV_D_DATA : std_logic_vector(7 downto 0) := "01110101"; + constant MOV_ATRI_A : std_logic_vector(6 downto 0) := "1111011"; + constant MOV_ATRI_D : std_logic_vector(6 downto 0) := "1010011"; + constant MOV_ATRI_DATA : std_logic_vector(6 downto 0) := "0111011"; + constant MOVC_A_ATDPTR : std_logic_vector(7 downto 0) := "10010011"; + constant MOVC_A_ATPC : std_logic_vector(7 downto 0) := "10000011"; + constant MOVX_A_ATRI : std_logic_vector(6 downto 0) := "1110001"; + constant MOVX_A_ATDPTR : std_logic_vector(7 downto 0) := "11100000"; + constant MOVX_ATRI_A : std_logic_vector(6 downto 0) := "1111001"; + constant MOVX_ATDPTR_A : std_logic_vector(7 downto 0) := "11110000"; + constant MOV_C_BIT : std_logic_vector(7 downto 0) := "10100010"; + constant MOV_BIT_C : std_logic_vector(7 downto 0) := "10010010"; + constant MOV_DPTR_DATA : std_logic_vector(7 downto 0) := "10010000"; + constant MUL_AB : std_logic_vector(7 downto 0) := "10100100"; + constant NOP : std_logic_vector(7 downto 0) := "00000000"; + constant ORL_A_RR : std_logic_vector(4 downto 0) := "01001"; + constant ORL_A_D : std_logic_vector(7 downto 0) := "01000101"; + constant ORL_A_ATRI : std_logic_vector(6 downto 0) := "0100011"; + constant ORL_A_DATA : std_logic_vector(7 downto 0) := "01000100"; + constant ORL_D_A : std_logic_vector(7 downto 0) := "01000010"; + constant ORL_D_DATA : std_logic_vector(7 downto 0) := "01000011"; + constant ORL_C_BIT : std_logic_vector(7 downto 0) := "01110010"; + constant ORL_C_NBIT : std_logic_vector(7 downto 0) := "10100000"; + constant POP : std_logic_vector(7 downto 0) := "11010000"; + constant PUSH : std_logic_vector(7 downto 0) := "11000000"; + constant RET : std_logic_vector(7 downto 0) := "00100010"; + constant RETI : std_logic_vector(7 downto 0) := "00110010"; + constant RL_A : std_logic_vector(7 downto 0) := "00100011"; + constant RLC_A : std_logic_vector(7 downto 0) := "00110011"; + constant RR_A : std_logic_vector(7 downto 0) := "00000011"; + constant RRC_A : std_logic_vector(7 downto 0) := "00010011"; + constant SETB_C : std_logic_vector(7 downto 0) := "11010011"; + constant SETB_BIT : std_logic_vector(7 downto 0) := "11010010"; + constant SJMP : std_logic_vector(7 downto 0) := "10000000"; + constant SUBB_A_RR : std_logic_vector(4 downto 0) := "10011"; + constant SUBB_A_D : std_logic_vector(7 downto 0) := "10010101"; + constant SUBB_A_ATRI : std_logic_vector(6 downto 0) := "1001011"; + constant SUBB_A_DATA : std_logic_vector(7 downto 0) := "10010100"; + constant SWAP_A : std_logic_vector(7 downto 0) := "11000100"; + constant XCH_A_RR : std_logic_vector(4 downto 0) := "11001"; + constant XCH_A_D : std_logic_vector(7 downto 0) := "11000101"; + constant XCH_A_ATRI : std_logic_vector(6 downto 0) := "1100011"; + constant XCHD_A_ATRI : std_logic_vector(6 downto 0) := "1101011"; + constant XRL_A_RR : std_logic_vector(4 downto 0) := "01101"; + constant XRL_A_D : std_logic_vector(7 downto 0) := "01100101"; + constant XRL_A_ATRI : std_logic_vector(6 downto 0) := "0110011"; + constant XRL_A_DATA : std_logic_vector(7 downto 0) := "01100100"; + constant XRL_D_A : std_logic_vector(7 downto 0) := "01100010"; + constant XRL_D_DATA : std_logic_vector(7 downto 0) := "01100011"; + + + type t_state is (STARTUP, + FETCH, + EXEC1, + EXEC2, + EXEC3); + + type t_instr_category is (IC_ACALL, + IC_ADD_A_RR, + IC_ADD_A_D, + IC_ADD_A_ATRI, + IC_ADD_A_DATA, + IC_ADDC_A_RR, + IC_ADDC_A_D, + IC_ADDC_A_ATRI, + IC_ADDC_A_DATA, + IC_AJMP, + IC_ANL_A_RR, + IC_ANL_A_D, + IC_ANL_A_ATRI, + IC_ANL_A_DATA, + IC_ANL_D_A, + IC_ANL_D_DATA, + IC_ANL_C_BIT, + IC_ANL_C_NBIT, + IC_CJNE_A_D, + IC_CJNE_A_DATA, + IC_CJNE_RR_DATA, + IC_CJNE_ATRI_DATA, + IC_CLR_A, + IC_CLR_C, + IC_CLR_BIT, + IC_CPL_A, + IC_CPL_C, + IC_CPL_BIT, + IC_DA_A, + IC_DEC_A, + IC_DEC_RR, + IC_DEC_D, + IC_DEC_ATRI, + IC_DIV_AB, + IC_DJNZ_RR, + IC_DJNZ_D, + IC_INC_A, + IC_INC_RR, + IC_INC_D, + IC_INC_ATRI, + IC_INC_DPTR, + IC_JB, + IC_JBC, + IC_JC, + IC_JMP_A_DPTR, + IC_JNB, + IC_JNC, + IC_JNZ, + IC_JZ, + IC_LCALL, + IC_LJMP, + IC_MOV_A_RR, + IC_MOV_A_D, + IC_MOV_A_ATRI, + IC_MOV_A_DATA, + IC_MOV_RR_A, + IC_MOV_RR_D, + IC_MOV_RR_DATA, + IC_MOV_D_A, + IC_MOV_D_RR, + IC_MOV_D_D, + IC_MOV_D_ATRI, + IC_MOV_D_DATA, + IC_MOV_ATRI_A, + IC_MOV_ATRI_D, + IC_MOV_ATRI_DATA, + IC_MOVC_A_ATDPTR, + IC_MOVC_A_ATPC, + IC_MOVX_A_ATRI, + IC_MOVX_A_ATDPTR, + IC_MOVX_ATRI_A, + IC_MOVX_ATDPTR_A, + IC_MOV_C_BIT, + IC_MOV_BIT_C, + IC_MOV_DPTR_DATA, + IC_MUL_AB, + IC_NOP, + IC_ORL_A_RR, + IC_ORL_A_D, + IC_ORL_A_ATRI, + IC_ORL_A_DATA, + IC_ORL_D_A, + IC_ORL_D_DATA, + IC_ORL_C_BIT, + IC_ORL_C_NBIT, + IC_POP, + IC_PUSH, + IC_RET, + IC_RETI, + IC_RL_A, + IC_RLC_A, + IC_RR_A, + IC_RRC_A, + IC_SETB_C, + IC_SETB_BIT, + IC_SJMP, + IC_SUBB_A_RR, + IC_SUBB_A_D, + IC_SUBB_A_ATRI, + IC_SUBB_A_DATA, + IC_SWAP_A, + IC_XCH_A_RR, + IC_XCH_A_D, + IC_XCH_A_ATRI, + IC_XCHD_A_ATRI, + IC_XRL_A_RR, + IC_XRL_A_D, + IC_XRL_A_ATRI, + IC_XRL_A_DATA, + IC_XRL_D_A, + IC_XRL_D_DATA); + + type t_tmr_lv is array(C_IMPL_N_TMR-1 downto 0) of + std_logic_vector(7 downto 0); + + type t_tmr_us is array(C_IMPL_N_TMR-1 downto 0) of unsigned(7 downto 0); + + type t_tmr_us2 is array(C_IMPL_N_TMR-1 downto 0) of unsigned(1 downto 0); + + type t_tmr_l is array(C_IMPL_N_TMR-1 downto 0) of std_logic; + + type t_siu_lv is array(C_IMPL_N_SIU-1 downto 0) of + std_logic_vector(7 downto 0); + + type t_siu_us is array(C_IMPL_N_SIU-1 downto 0) of unsigned(7 downto 0); + + type t_siu_l is array(C_IMPL_N_SIU-1 downto 0) of std_logic; + + type t_ext_l is array(C_IMPL_N_EXT-1 downto 0) of std_logic; + + + component addsub_cy + generic (DWIDTH : integer); + port (opa_i : in std_logic_vector(DWIDTH-1 downto 0); + opb_i : in std_logic_vector(DWIDTH-1 downto 0); + addsub_i : in std_logic; + cy_i : in std_logic; + cy_o : out std_logic; + rslt_o : out std_logic_vector(DWIDTH-1 downto 0)); + end component; + + component addsub_ovcy + generic (DWIDTH : integer); + port (opa_i : in std_logic_vector(DWIDTH-1 downto 0); + opb_i : in std_logic_vector(DWIDTH-1 downto 0); + addsub_i : in std_logic; + cy_i : in std_logic; + cy_o : out std_logic; + ov_o : out std_logic; + rslt_o : out std_logic_vector(DWIDTH-1 downto 0)); + end component; + + component addsub_core + generic (DWIDTH : integer); + port (opa_i : in std_logic_vector(DWIDTH-1 downto 0); + opb_i : in std_logic_vector(DWIDTH-1 downto 0); + addsub_i : in std_logic; + cy_i : in std_logic; + cy_o : out std_logic_vector((DWIDTH-1)/4 downto 0); + ov_o : out std_logic; + rslt_o : out std_logic_vector(DWIDTH-1 downto 0)); + end component; + + component alucore + generic (DWIDTH : integer); + port (op_a_i : in std_logic_vector(DWIDTH-1 downto 0); + op_b_i : in std_logic_vector(DWIDTH-1 downto 0); + alu_cmd_i : in std_logic_vector(3 downto 0); + cy_i : in std_logic_vector((DWIDTH-1)/4 downto 0); + cy_o : out std_logic_vector((DWIDTH-1)/4 downto 0); + result_o : out std_logic_vector(DWIDTH-1 downto 0)); + end component; + + component comb_divider + generic ( + DWIDTH : integer); + port ( + dvdnd_i : in std_logic_vector(DWIDTH-1 downto 0); + dvsor_i : in std_logic_vector(DWIDTH-1 downto 0); + qutnt_o : out std_logic_vector(DWIDTH-1 downto 0); + rmndr_o : out std_logic_vector(DWIDTH-1 downto 0)); + end component; + + component comb_mltplr + generic ( + DWIDTH : integer); + port ( + mltplcnd_i : in std_logic_vector(DWIDTH-1 downto 0); + mltplctr_i : in std_logic_vector(DWIDTH-1 downto 0); + product_o : out std_logic_vector((DWIDTH*2)-1 downto 0)); + end component; + + component dcml_adjust + generic ( + DWIDTH : integer); + port ( + data_i : in std_logic_vector(DWIDTH-1 downto 0); + cy_i : in std_logic_vector((DWIDTH-1)/4 downto 0); + data_o : out std_logic_vector(DWIDTH-1 downto 0); + cy_o : out std_logic); + end component; + + component alumux + generic (DWIDTH : integer); + port (rom_data_i : in std_logic_vector(DWIDTH-1 downto 0); + ram_data_i : in std_logic_vector(DWIDTH-1 downto 0); + acc_i : in std_logic_vector(DWIDTH-1 downto 0); + cmd_i : in std_logic_vector(5 downto 0); + cy_i : in std_logic_vector((DWIDTH-1)/4 downto 0); + ov_i : in std_logic; + cy_o : out std_logic_vector((DWIDTH-1)/4 downto 0); + ov_o : out std_logic; + result_a_o : out std_logic_vector(DWIDTH-1 downto 0); + result_b_o : out std_logic_vector(DWIDTH-1 downto 0); + result_i : in std_logic_vector(DWIDTH-1 downto 0); + new_cy_i : in std_logic_vector((DWIDTH-1)/4 downto 0); + addsub_rslt_i : in std_logic_vector(DWIDTH-1 downto 0); + addsub_cy_i : in std_logic_vector((DWIDTH-1)/4 downto 0); + addsub_ov_i : in std_logic; + op_a_o : out std_logic_vector(DWIDTH-1 downto 0); + op_b_o : out std_logic_vector(DWIDTH-1 downto 0); + alu_cmd_o : out std_logic_vector(3 downto 0); + opa_o : out std_logic_vector(DWIDTH-1 downto 0); + opb_o : out std_logic_vector(DWIDTH-1 downto 0); + addsub_o : out std_logic; + addsub_cy_o : out std_logic; + dvdnd_o : out std_logic_vector(DWIDTH-1 downto 0); + dvsor_o : out std_logic_vector(DWIDTH-1 downto 0); + qutnt_i : in std_logic_vector(DWIDTH-1 downto 0); + rmndr_i : in std_logic_vector(DWIDTH-1 downto 0); + mltplcnd_o : out std_logic_vector(DWIDTH-1 downto 0); + mltplctr_o : out std_logic_vector(DWIDTH-1 downto 0); + product_i : in std_logic_vector((DWIDTH*2)-1 downto 0); + dcml_data_o : out std_logic_vector(DWIDTH-1 downto 0); + dcml_data_i : in std_logic_vector(DWIDTH-1 downto 0); + dcml_cy_i : in std_logic); + end component; + + component mc8051_alu + generic ( + DWIDTH : integer); + port ( + rom_data_i : in std_logic_vector(DWIDTH-1 downto 0); + ram_data_i : in std_logic_vector(DWIDTH-1 downto 0); + acc_i : in std_logic_vector(DWIDTH-1 downto 0); + cmd_i : in std_logic_vector(5 downto 0); + cy_i : in std_logic_vector((DWIDTH-1)/4 downto 0); + ov_i : in std_logic; + new_cy_o : out std_logic_vector((DWIDTH-1)/4 downto 0); + new_ov_o : out std_logic; + result_a_o : out std_logic_vector(DWIDTH-1 downto 0); + result_b_o : out std_logic_vector(DWIDTH-1 downto 0)); + end component; + + component mc8051_siu + port (clk : in std_logic; + cen : in std_logic; + reset : in std_logic; + tf_i : in std_logic; + trans_i : in std_logic; + rxd_i : in std_logic; + scon_i : in std_logic_vector(5 downto 0); + sbuf_i : in std_logic_vector(7 downto 0); + smod_i : in std_logic; + sbuf_o : out std_logic_vector(7 downto 0); + scon_o : out std_logic_vector(2 downto 0); + rxdwr_o : out std_logic; + rxd_o : out std_logic; + txd_o : out std_logic); + end component; + + + component mc8051_tmrctr + port (clk : in std_logic; + cen : in std_logic; + reset : in std_logic; + int0_i : in std_logic; + int1_i : in std_logic; + t0_i : in std_logic; + t1_i : in std_logic; + tmod_i : in std_logic_vector(7 downto 0); + tcon_tr0_i : in std_logic; + tcon_tr1_i : in std_logic; + reload_i : in std_logic_vector(7 downto 0); + wt_en_i : in std_logic; + wt_i : in std_logic_vector(1 downto 0); + th0_o : out std_logic_vector(7 downto 0); + tl0_o : out std_logic_vector(7 downto 0); + th1_o : out std_logic_vector(7 downto 0); + tl1_o : out std_logic_vector(7 downto 0); + tf0_o : out std_logic; + tf1_o : out std_logic); + end component; + + + component control_fsm + port ( state_i : in t_state; -- actual state + help_i : in std_logic_vector (7 downto 0); -- general help-reg + bit_data_i : in std_logic; -- bitdata from regs + aludata_i : in std_logic_vector (7 downto 0); -- ALU result + command_i : in std_logic_vector (7 downto 0); -- actual command + inthigh_i : in std_logic; -- high priority int is running + intlow_i : in std_logic; -- low priority int is running + intpre_i : in std_logic; -- an interrupt must start + intpre2_i : in std_logic; -- prepare for interrupt + intblock_i : in std_logic; -- interrupt delay at RETI, IE, IP + ti_i : in std_logic; + ri_i : in std_logic; + ie0_i : in std_logic; + ie1_i : in std_logic; + tf0_i : in std_logic; + tf1_i : in std_logic; + acc : in std_logic_vector(7 downto 0); + psw : in std_logic_vector(7 downto 0); + ie : in std_logic_vector(7 downto 0); + ip : in std_logic_vector(7 downto 0); + + alu_cmd_o : out std_logic_vector (5 downto 0); -- ALU code + pc_inc_en_o : out std_logic_vector (3 downto 0); + nextstate_o : out t_state; + adr_mux_o : out std_logic_vector (3 downto 0); + adrx_mux_o : out std_logic_vector (1 downto 0); + wrx_mux_o : out std_logic; + data_mux_o : out std_logic_vector (3 downto 0); + bdata_mux_o : out std_logic_vector (3 downto 0); + regs_wr_en_o : out std_logic_vector (2 downto 0); + help_en_o : out std_logic_vector (3 downto 0); + help16_en_o : out std_logic_vector (1 downto 0); + helpb_en_o : out std_logic; + inthigh_en_o : out std_logic; + intlow_en_o : out std_logic; + intpre2_en_o : out std_logic; + inthigh_d_o : out std_logic; + intlow_d_o : out std_logic; + intpre2_d_o : out std_logic; + ext0isr_d_o : out std_logic; + ext1isr_d_o : out std_logic; + ext0isrh_d_o : out std_logic; + ext1isrh_d_o : out std_logic; + ext0isr_en_o : out std_logic; + ext1isr_en_o : out std_logic; + ext0isrh_en_o : out std_logic; + ext1isrh_en_o : out std_logic); + + end component; + + component control_mem + port (pc_o : out std_logic_vector(15 downto 0); + rom_data_i : in std_logic_vector(7 downto 0); + ram_data_o : out std_logic_vector(7 downto 0); + ram_data_i : in std_logic_vector(7 downto 0); + ram_adr_o : out std_logic_vector(6 downto 0); + reg_data_o : out std_logic_vector(7 downto 0); + ram_wr_o : out std_logic; + cy_o : out std_logic_vector(1 downto 0); + ov_o : out std_logic; + ram_en_o : out std_logic; + aludata_i : in std_logic_vector (7 downto 0); + aludatb_i : in std_logic_vector (7 downto 0); + acc_o : out std_logic_vector (7 downto 0); + new_cy_i : in std_logic_vector(1 downto 0); + new_ov_i : in std_logic; + reset : in std_logic; + clk : in std_logic; + cen : in std_logic; + int0_i : in std_logic_vector(C_IMPL_N_EXT-1 downto 0); + int1_i : in std_logic_vector(C_IMPL_N_EXT-1 downto 0); + p0_i : in std_logic_vector(7 downto 0); + p1_i : in std_logic_vector(7 downto 0); + p2_i : in std_logic_vector(7 downto 0); + p3_i : in std_logic_vector(7 downto 0); + p0_o : out std_logic_vector(7 downto 0); + p1_o : out std_logic_vector(7 downto 0); + p2_o : out std_logic_vector(7 downto 0); + p3_o : out std_logic_vector(7 downto 0); + all_trans_o : out std_logic_vector(C_IMPL_N_SIU-1 downto 0); + all_scon_o : out std_logic_vector(6*C_IMPL_N_SIU-1 downto 0); + all_sbuf_o : out std_logic_vector(8*C_IMPL_N_SIU-1 downto 0); + all_smod_o : out std_logic_vector(C_IMPL_N_SIU-1 downto 0); + all_scon_i : in std_logic_vector(3*C_IMPL_N_SIU-1 downto 0); + all_sbuf_i : in std_logic_vector(8*C_IMPL_N_SIU-1 downto 0); + all_tcon_tr0_o : out std_logic_vector(C_IMPL_N_TMR-1 downto 0); + all_tcon_tr1_o : out std_logic_vector(C_IMPL_N_TMR-1 downto 0); + all_tmod_o : out std_logic_vector(8*C_IMPL_N_TMR-1 downto 0); + all_reload_o : out std_logic_vector(8*C_IMPL_N_TMR-1 downto 0); + all_wt_o : out std_logic_vector(2*C_IMPL_N_TMR-1 downto 0); + all_wt_en_o : out std_logic_vector(C_IMPL_N_TMR-1 downto 0); + all_tf0_i : in std_logic_vector(C_IMPL_N_TMR-1 downto 0); + all_tf1_i : in std_logic_vector(C_IMPL_N_TMR-1 downto 0); + all_tl0_i : in std_logic_vector(8*C_IMPL_N_TMR-1 downto 0); + all_tl1_i : in std_logic_vector(8*C_IMPL_N_TMR-1 downto 0); + all_th0_i : in std_logic_vector(8*C_IMPL_N_TMR-1 downto 0); + all_th1_i : in std_logic_vector(8*C_IMPL_N_TMR-1 downto 0); + state_o : out t_state; + help_o : out std_logic_vector(7 downto 0); + bit_data_o : out std_logic; + command_o : out std_logic_vector (7 downto 0); + inthigh_o : out std_logic; + intlow_o : out std_logic; + intpre_o : out std_logic; + intpre2_o : out std_logic; + intblock_o : out std_logic; + ti_o : out std_logic; + ri_o : out std_logic; + ie0_o : out std_logic; + ie1_o : out std_logic; + tf0_o : out std_logic; + tf1_o : out std_logic; + psw_o : out std_logic_vector(7 downto 0); + ie_o : out std_logic_vector(7 downto 0); + ip_o : out std_logic_vector(7 downto 0); + adrx_o : out std_logic_vector(15 downto 0); + datax_o : out std_logic_vector(7 downto 0); + memx_o : out std_logic; + wrx_o : out std_logic; + datax_i : in std_logic_vector(7 downto 0); + pc_inc_en_i : in std_logic_vector (3 downto 0); + nextstate_i : in t_state; + adr_mux_i : in std_logic_vector (3 downto 0); + adrx_mux_i : in std_logic_vector (1 downto 0); + wrx_mux_i : in std_logic; + data_mux_i : in std_logic_vector (3 downto 0); + bdata_mux_i : in std_logic_vector (3 downto 0); + regs_wr_en_i : in std_logic_vector (2 downto 0); + help_en_i : in std_logic_vector (3 downto 0); + help16_en_i : in std_logic_vector (1 downto 0); + helpb_en_i : in std_logic; + inthigh_en_i : in std_logic; + intlow_en_i : in std_logic; + intpre2_en_i : in std_logic; + inthigh_d_i : in std_logic; + intlow_d_i : in std_logic; + intpre2_d_i : in std_logic; + ext0isr_d_i : in std_logic; + ext1isr_d_i : in std_logic; + ext0isrh_d_i : in std_logic; + ext1isrh_d_i : in std_logic; + ext0isr_en_i : in std_logic; + ext1isr_en_i : in std_logic; + ext0isrh_en_i : in std_logic; + ext1isrh_en_i : in std_logic); + + end component; + + component mc8051_control + port (pc_o : out std_logic_vector(15 downto 0); + rom_data_i : in std_logic_vector(7 downto 0); + ram_data_o : out std_logic_vector(7 downto 0); + ram_data_i : in std_logic_vector(7 downto 0); + ram_adr_o : out std_logic_vector(6 downto 0); + reg_data_o : out std_logic_vector(7 downto 0); + ram_wr_o : out std_logic; + cy_o : out std_logic_vector(1 downto 0); + ov_o : out std_logic; + ram_en_o : out std_logic; + alu_cmd_o : out std_logic_vector (5 downto 0); + aludata_i : in std_logic_vector (7 downto 0); + aludatb_i : in std_logic_vector (7 downto 0); + acc_o : out std_logic_vector (7 downto 0); + new_cy_i : in std_logic_vector(1 downto 0); + new_ov_i : in std_logic; + reset : in std_logic; + clk : in std_logic; + cen : in std_logic; + int0_i : in std_logic_vector(C_IMPL_N_EXT-1 downto 0); + int1_i : in std_logic_vector(C_IMPL_N_EXT-1 downto 0); + datax_i : in std_logic_vector (7 downto 0); + datax_o : out std_logic_vector (7 downto 0); + adrx_o : out std_logic_vector (15 downto 0); + memx_o : out std_logic; + wrx_o : out std_logic; + p0_i : in std_logic_vector(7 downto 0); + p1_i : in std_logic_vector(7 downto 0); + p2_i : in std_logic_vector(7 downto 0); + p3_i : in std_logic_vector(7 downto 0); + p0_o : out std_logic_vector(7 downto 0); + p1_o : out std_logic_vector(7 downto 0); + p2_o : out std_logic_vector(7 downto 0); + p3_o : out std_logic_vector(7 downto 0); + all_trans_o : out std_logic_vector(C_IMPL_N_SIU-1 downto 0); + all_scon_o : out std_logic_vector(6*C_IMPL_N_SIU-1 downto 0); + all_sbuf_o : out std_logic_vector(8*C_IMPL_N_SIU-1 downto 0); + all_smod_o : out std_logic_vector(C_IMPL_N_SIU-1 downto 0); + all_scon_i : in std_logic_vector(3*C_IMPL_N_SIU-1 downto 0); + all_sbuf_i : in std_logic_vector(8*C_IMPL_N_SIU-1 downto 0); + all_tcon_tr0_o : out std_logic_vector(C_IMPL_N_TMR-1 downto 0); + all_tcon_tr1_o : out std_logic_vector(C_IMPL_N_TMR-1 downto 0); + all_tmod_o : out std_logic_vector(8*C_IMPL_N_TMR-1 downto 0); + all_reload_o : out std_logic_vector(8*C_IMPL_N_TMR-1 downto 0); + all_wt_o : out std_logic_vector(2*C_IMPL_N_TMR-1 downto 0); + all_wt_en_o : out std_logic_vector(C_IMPL_N_TMR-1 downto 0); + all_tf0_i : in std_logic_vector(C_IMPL_N_TMR-1 downto 0); + all_tf1_i : in std_logic_vector(C_IMPL_N_TMR-1 downto 0); + all_tl0_i : in std_logic_vector(8*C_IMPL_N_TMR-1 downto 0); + all_tl1_i : in std_logic_vector(8*C_IMPL_N_TMR-1 downto 0); + all_th0_i : in std_logic_vector(8*C_IMPL_N_TMR-1 downto 0); + all_th1_i : in std_logic_vector(8*C_IMPL_N_TMR-1 downto 0)); + + end component; + + + component mc8051_core + port (clk : in std_logic; + cen : in std_logic; + reset : in std_logic; + rom_data_i : in std_logic_vector(7 downto 0); + ram_data_i : in std_logic_vector(7 downto 0); + int0_i : in std_logic_vector(C_IMPL_N_EXT-1 downto 0); + int1_i : in std_logic_vector(C_IMPL_N_EXT-1 downto 0); + all_t0_i : in std_logic_vector(C_IMPL_N_TMR-1 downto 0); + all_t1_i : in std_logic_vector(C_IMPL_N_TMR-1 downto 0); + all_rxd_i : in std_logic_vector(C_IMPL_N_SIU-1 downto 0); + p0_i : in std_logic_vector(7 downto 0); + p1_i : in std_logic_vector(7 downto 0); + p2_i : in std_logic_vector(7 downto 0); + p3_i : in std_logic_vector(7 downto 0); + p0_o : out std_logic_vector(7 downto 0); + p1_o : out std_logic_vector(7 downto 0); + p2_o : out std_logic_vector(7 downto 0); + p3_o : out std_logic_vector(7 downto 0); + all_rxd_o : out std_logic_vector(C_IMPL_N_SIU-1 downto 0); + all_txd_o : out std_logic_vector(C_IMPL_N_SIU-1 downto 0); + all_rxdwr_o : out std_logic_vector(C_IMPL_N_SIU-1 downto 0); + rom_adr_o : out std_logic_vector(15 downto 0); + ram_data_o : out std_logic_vector(7 downto 0); + ram_adr_o : out std_logic_vector(6 downto 0); + ram_wr_o : out std_logic; + ram_en_o : out std_logic; + datax_i : in std_logic_vector (7 downto 0); + datax_o : out std_logic_vector (7 downto 0); + adrx_o : out std_logic_vector (15 downto 0); + memx_o : out std_logic; + wrx_o : out std_logic); + + end component; + + + component mc8051_top + port (clk : in std_logic; + cen : in std_logic; + reset : in std_logic; + int0_i : in std_logic_vector(C_IMPL_N_EXT-1 downto 0); + int1_i : in std_logic_vector(C_IMPL_N_EXT-1 downto 0); + all_t0_i : in std_logic_vector(C_IMPL_N_TMR-1 downto 0); + all_t1_i : in std_logic_vector(C_IMPL_N_TMR-1 downto 0); + all_rxd_i : in std_logic_vector(C_IMPL_N_SIU-1 downto 0); + p0_i : in std_logic_vector(7 downto 0); + p1_i : in std_logic_vector(7 downto 0); + p2_i : in std_logic_vector(7 downto 0); + p3_i : in std_logic_vector(7 downto 0); + p0_o : out std_logic_vector(7 downto 0); + p1_o : out std_logic_vector(7 downto 0); + p2_o : out std_logic_vector(7 downto 0); + p3_o : out std_logic_vector(7 downto 0); + all_rxd_o : out std_logic_vector(C_IMPL_N_SIU-1 downto 0); + all_txd_o : out std_logic_vector(C_IMPL_N_SIU-1 downto 0); + all_rxdwr_o : out std_logic_vector(C_IMPL_N_SIU-1 downto 0)); + + end component; + + ----------------------------------------------------------------------------- + -- START: Component declarations for simulation models + ----------------------------------------------------------------------------- + component mc8051_ram + port (clk : in std_logic; + cen : in std_logic; + reset : in std_logic; + ram_data_i : in std_logic_vector(7 downto 0); + ram_data_o : out std_logic_vector(7 downto 0); + ram_adr_i : in std_logic_vector(6 downto 0); + ram_wr_i : in std_logic; + ram_en_i : in std_logic); + + end component; + + component mc8051_ramx + port (clk : in std_logic; + cen : in std_logic; + reset : in std_logic; + ram_data_i : in std_logic_vector(7 downto 0); + ram_data_o : out std_logic_vector(7 downto 0); + ram_adr_i : in std_logic_vector(15 downto 0); + ram_wr_i : in std_logic); + + end component; + + component mc8051_rom + port (clk : in std_logic; + cen : in std_logic; + reset : in std_logic; + rom_data_o : out std_logic_vector(7 downto 0); + rom_adr_i : in std_logic_vector(15 downto 0)); + + end component; + ----------------------------------------------------------------------------- + -- END: Component declarations for simulation models + ----------------------------------------------------------------------------- + + +end mc8051_p; diff --git a/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/8051/mc8051_siu_.vhd b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/8051/mc8051_siu_.vhd new file mode 100644 index 0000000000000000000000000000000000000000..2967fd83d79f892b11baa914e73b22eb141c8216 --- /dev/null +++ b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/8051/mc8051_siu_.vhd @@ -0,0 +1,92 @@ +------------------------------------------------------------------------------- +-- -- +-- X X XXXXXX XXXXXX XXXXXX XXXXXX X -- +-- XX XX X X X X X X X XX -- +-- X X X X X X X X X X X X -- +-- X X X X X X X X X X X X -- +-- X X X X XXXXXX X X XXXXXX X -- +-- X X X X X X X X X -- +-- X X X X X X X X X -- +-- X X X X X X X X X X -- +-- X X XXXXXX XXXXXX XXXXXX XXXXXX X -- +-- -- +-- -- +-- O R E G A N O S Y S T E M S -- +-- -- +-- Design & Consulting -- +-- -- +------------------------------------------------------------------------------- +-- -- +-- Web: http://www.oregano.at/ -- +-- -- +-- Contact: mc8051@oregano.at -- +-- -- +------------------------------------------------------------------------------- +-- -- +-- MC8051 - VHDL 8051 Microcontroller IP Core -- +-- Copyright (C) 2001 OREGANO SYSTEMS -- +-- -- +-- This library is free software; you can redistribute it and/or -- +-- modify it under the terms of the GNU Lesser General Public -- +-- License as published by the Free Software Foundation; either -- +-- version 2.1 of the License, or (at your option) any later version. -- +-- -- +-- This library is distributed in the hope that it will be useful, -- +-- but WITHOUT ANY WARRANTY; without even the implied warranty of -- +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -- +-- Lesser General Public License for more details. -- +-- -- +-- Full details of the license can be found in the file LGPL.TXT. -- +-- -- +-- You should have received a copy of the GNU Lesser General Public -- +-- License along with this library; if not, write to the Free Software -- +-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -- +-- -- +------------------------------------------------------------------------------- +-- +-- +-- Author: Roland Hller +-- +-- Filename: mc8051_siu_.vhd +-- +-- Date of Creation: Mon Aug 9 12:14:48 1999 +-- +-- Version: $Revision: 1.5 $ +-- +-- Date of Latest Version: $Date: 2002-01-07 12:17:45 $ +-- +-- +-- Description: Serial interface unit for the mc8051 microcontroller. +-- +-- +-- +-- +------------------------------------------------------------------------------- +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.std_logic_arith.all; + +-----------------------------ENTITY DECLARATION-------------------------------- + +entity mc8051_siu is + + port (clk : in std_logic; --< system clock + cen : in std_logic; --< system clock enable + reset : in std_logic; --< system reset + tf_i : in std_logic; --< timer1 overflow flag + trans_i : in std_logic; --< 1 activates transm. + rxd_i : in std_logic; --< serial data input + scon_i : in std_logic_vector(5 downto 0); --< from SFR register + --< bits 7 to 3 + sbuf_i : in std_logic_vector(7 downto 0); --< data for transm. + smod_i : in std_logic; --< low(0)/high baudrate + + sbuf_o : out std_logic_vector(7 downto 0); --< received data + scon_o : out std_logic_vector(2 downto 0); --< to SFR register + --< bits 0 to 2 + rxdwr_o : out std_logic; --< rxd direction signal + rxd_o : out std_logic; --< mode0 data output + txd_o : out std_logic); --< serial data output + +end mc8051_siu; + diff --git a/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/8051/mc8051_siu_rtl.vhd b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/8051/mc8051_siu_rtl.vhd new file mode 100644 index 0000000000000000000000000000000000000000..b3a9282f1279b06ed079c45c427cb31568981a4a --- /dev/null +++ b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/8051/mc8051_siu_rtl.vhd @@ -0,0 +1,1202 @@ +------------------------------------------------------------------------------- +-- -- +-- X X XXXXXX XXXXXX XXXXXX XXXXXX X -- +-- XX XX X X X X X X X XX -- +-- X X X X X X X X X X X X -- +-- X X X X X X X X X X X X -- +-- X X X X XXXXXX X X XXXXXX X -- +-- X X X X X X X X X -- +-- X X X X X X X X X -- +-- X X X X X X X X X X -- +-- X X XXXXXX XXXXXX XXXXXX XXXXXX X -- +-- -- +-- -- +-- O R E G A N O S Y S T E M S -- +-- -- +-- Design & Consulting -- +-- -- +------------------------------------------------------------------------------- +-- -- +-- Web: http://www.oregano.at/ -- +-- -- +-- Contact: mc8051@oregano.at -- +-- -- +------------------------------------------------------------------------------- +-- -- +-- MC8051 - VHDL 8051 Microcontroller IP Core -- +-- Copyright (C) 2001 OREGANO SYSTEMS -- +-- -- +-- This library is free software; you can redistribute it and/or -- +-- modify it under the terms of the GNU Lesser General Public -- +-- License as published by the Free Software Foundation; either -- +-- version 2.1 of the License, or (at your option) any later version. -- +-- -- +-- This library is distributed in the hope that it will be useful, -- +-- but WITHOUT ANY WARRANTY; without even the implied warranty of -- +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -- +-- Lesser General Public License for more details. -- +-- -- +-- Full details of the license can be found in the file LGPL.TXT. -- +-- -- +-- You should have received a copy of the GNU Lesser General Public -- +-- License along with this library; if not, write to the Free Software -- +-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -- +-- -- +------------------------------------------------------------------------------- +-- +-- +-- Author: Roland Hller +-- +-- Filename: mc8051_siu_rtl.vhd +-- +-- Date of Creation: Mon Aug 9 12:14:48 1999 +-- +-- Version: $Revision: 1.10 $ +-- +-- Date of Latest Version: $Date: 2010-03-24 10:20:48 $ +-- +-- +-- Description: Serial interface unit for the mc8051 microcontroller. +-- +-- +-- +-- +------------------------------------------------------------------------------- +architecture rtl of mc8051_siu is + + signal s_rxpre_count : unsigned(5 downto 0); -- Receive prescaler + signal s_txpre_count : unsigned(5 downto 0); -- Transmit prescaler + signal s_m0_shift_en : std_logic; -- masks out every twelfth + -- rising edge of clk + signal s_m2_rxshift_en : std_logic; -- mode 2 shift enable + signal s_m13_rxshift_en : std_logic; -- mode 1 and 3 shift enable + signal s_m2_txshift_en : std_logic; -- mode 2 shift enable + signal s_m13_txshift_en : std_logic; -- mode 1 and 3 shift enable + signal s_ff0 : std_logic; -- flipflop for edge dedection + signal s_ff1 : std_logic; -- flipflop for edge dedection + signal s_tf : std_logic; -- synchronised timer flag + signal s_mode : unsigned(1 downto 0); -- mode + signal s_sm2 : std_logic; -- multi processor comm. bit + signal s_detect : std_logic; -- indicates start of recept. + signal s_ren : std_logic; -- receive enable + signal s_rxd_val : std_logic; -- received data bit + signal s_txdm0 : std_logic; -- shift clock for m0 + signal s_ri : std_logic; -- external receive interrupt + signal s_trans : std_logic; -- enable transmission + signal s_recv_done : std_logic; -- receive interrupt + signal s_tran_done : std_logic; -- transmit interrupt + signal s_rb8 : std_logic; -- 8th data bit + signal s_tb8 : std_logic; -- 8th data bit + signal s_recv_state : unsigned(3 downto 0); -- state reg. of receive unit + signal s_tran_state : unsigned(3 downto 0); -- state reg. of transmit unit + signal s_rxd_ff0 : std_logic; -- sample flip-flop + signal s_rxd_ff1 : std_logic; -- sample flip-flop + signal s_rxd_ff2 : std_logic; -- sample flip-flop + signal s_det_ff0 : std_logic; -- rec. detect flip-flop + signal s_det_ff1 : std_logic; -- rec. detect flip-flop + signal s_tran_sh : unsigned(10 downto 0); -- transmission shift register + signal s_recv_sh : unsigned(7 downto 0); -- reception shift register + signal s_recv_buf : unsigned(7 downto 0); -- reception buffer register + signal s_rxm13_ff0 : std_logic; -- generates an enable singal + signal s_rxm13_ff1 : std_logic; -- generates an enable singal + signal s_txm13_ff0 : std_logic; -- generates an enable singal + signal s_txm13_ff1 : std_logic; -- generates an enable singal + +begin -- architecture rtl + + s_mode(1) <= scon_i(4); -- defines the 4 operating modes + s_mode(0) <= scon_i(3); + s_ren <= scon_i(1); -- receive enable + s_sm2 <= scon_i(2); -- 1 time or half time baud rate + s_tb8 <= scon_i(0); -- 9th data bit for transmission + s_ri <= scon_i(5); -- the receive interrupt bit of the + -- control unit + sbuf_o <= std_logic_vector(s_recv_buf); -- the receive buffer output + scon_o(0) <= s_recv_done; -- set when reception is completed + scon_o(1) <= s_tran_done; -- set when transmission is completed + scon_o(2) <= s_rb8; -- 9th data bit of reception + +------------------------------------------------------------------------------- + -- The two flip flops are updated every rising clock edge of clk. + -- If a rising edge + -- on the port tf_i is dedected the signal s_tf is set to 1 for one period. + -- + -- The transmission start signal s_trans is generated and held high till + -- the statemachine has been launched with its first shift. + -- + -- The shift clock for mode0 is generated. It toggles with the half + -- s_m0_shift_en rate. + + s_tf <= '1' when (s_ff0 = '1' and s_ff1 = '0') else '0'; + + p_sample_tf: process (clk, cen, reset) + + begin + + if reset = '1' then + s_ff0 <= '0'; + s_ff1 <= '0'; + s_trans <= '0'; + else + if clk'event and clk = '1' and cen='1' then + s_ff0 <= tf_i; + s_ff1 <= s_ff0; + + if trans_i = '1' then + s_trans <= '1'; + else + case s_mode is + when ("00") => + if s_m0_shift_en = '1' then + s_trans <= '0'; + end if; + when ("01") => + if s_m13_txshift_en = '1' then + s_trans <= '0'; + end if; + when ("10") => + if s_m2_txshift_en = '1' then + s_trans <= '0'; + end if; + when others => + if s_m13_txshift_en = '1' then + s_trans <= '0'; + end if; + end case; + end if; + end if; + end if; + + end process p_sample_tf; + + +------------------------------------------------------------------------------- + -- The register s_rxpre_count is driven with the system clock clk. So a + -- good enable signal (which is stable when clk has its rising edge) can be + -- derived to mask out every pulse of clk needed. + -- s_m0_shift_en activates every twelfth clock cycle + -- s_m2_shift_en activates baud rates of 1/32 or 1/64 the clock frequenzy + -- depending on signal smod_i + -- s_m13_shift_en activates baud rates depending on timer/counter1 flag + + s_m0_shift_en <= '1' when s_txpre_count(3 downto 0) = conv_unsigned(11,5) + else '0'; + + s_m2_rxshift_en <= '1' when (s_rxpre_count(4 downto 0) = conv_unsigned(31,5) + and smod_i = '1') or + (s_rxpre_count = conv_unsigned(63,6) + and smod_i = '0') + else '0'; + s_m13_rxshift_en <= '1' when s_rxm13_ff0 = '1' and s_rxm13_ff1 = '0' + else '0'; + + s_m2_txshift_en <= '1' when (s_txpre_count(4 downto 0) = conv_unsigned(31,5) + and smod_i = '1') or + (s_txpre_count = conv_unsigned(63,6) + and smod_i = '0') + else '0'; + s_m13_txshift_en <= '1' when s_txm13_ff0 = '1' and s_txm13_ff1 = '0' + else '0'; + + p_divide_clk: process (clk, cen, reset) + + begin + + if reset = '1' then + s_rxpre_count <= conv_unsigned(0,6); + s_txpre_count <= conv_unsigned(0,6); + s_rxm13_ff0 <= '0'; + s_rxm13_ff1 <= '0'; + s_txm13_ff0 <= '0'; + s_txm13_ff1 <= '0'; + else + if clk'event and clk='1' and cen='1' then + + s_rxm13_ff1 <= s_rxm13_ff0; + s_txm13_ff1 <= s_txm13_ff0; + + if trans_i = '1' then + s_txpre_count <= conv_unsigned(0,6); + else + if s_mode=conv_unsigned(0,2) then + s_txpre_count <= s_txpre_count + conv_unsigned(1,1); + if s_txpre_count = conv_unsigned(11,6) then + s_txpre_count <= conv_unsigned(0,6); + end if; + elsif s_mode=conv_unsigned(2,2) then + s_txpre_count <= s_txpre_count + conv_unsigned(1,1); + else + if s_tf = '1' then + s_txpre_count <= s_txpre_count + conv_unsigned(1,1); + end if; + end if; + end if; + + if s_detect = '1' then + s_rxpre_count <= conv_unsigned(0,6); + else + if s_mode=conv_unsigned(0,2) then + s_rxpre_count <= s_rxpre_count + conv_unsigned(1,1); + if s_rxpre_count = conv_unsigned(11,6) then + s_rxpre_count <= conv_unsigned(0,6); + end if; + elsif s_mode=conv_unsigned(2,2) then + s_rxpre_count <= s_rxpre_count + conv_unsigned(1,1); + else + if s_tf = '1' then + s_rxpre_count <= s_rxpre_count + conv_unsigned(1,1); + end if; + end if; + end if; + + if smod_i = '1' then + if s_rxpre_count(3 downto 0) = conv_unsigned(15,4) then + s_rxm13_ff0 <= '1'; + else + s_rxm13_ff0 <= '0'; + end if; + else + if s_rxpre_count(4 downto 0) = conv_unsigned(31,5) then + s_rxm13_ff0 <= '1'; + else + s_rxm13_ff0 <= '0'; + end if; + end if; + + if smod_i = '1' then + if s_txpre_count(3 downto 0) = conv_unsigned(15,4) then + s_txm13_ff0 <= '1'; + else + s_txm13_ff0 <= '0'; + end if; + else + if s_txpre_count(4 downto 0) = conv_unsigned(31,5) then + s_txm13_ff0 <= '1'; + else + s_txm13_ff0 <= '0'; + end if; + end if; + + end if; + end if; + + end process p_divide_clk; + +------------------------------------------------------------------------------- + -- This section samples the serial input for data detection, that is a + -- 1-to-0 transition at rxd in state "0000". + -- In all other states this unit reads the data bits depending on the baud + -- rate. In mode0 this section is not active. + + s_detect <= '1' when s_det_ff0 = '0' and s_det_ff1 = '1' else '0'; + s_rxd_val <= '1' when (s_rxd_ff0 = '1' and s_rxd_ff1 = '1') or + (s_rxd_ff0 = '1' and s_rxd_ff2 = '1') or + (s_rxd_ff1 = '1' and s_rxd_ff2 = '1') else '0'; + + p_sample_rx: process (clk, cen, reset) + begin + if reset = '1' then + s_rxd_ff0 <= '0'; + s_rxd_ff1 <= '0'; + s_rxd_ff2 <= '0'; + s_det_ff0 <= '0'; + s_det_ff1 <= '0'; + else + if clk'event and clk='1' and cen='1' then + if s_recv_state = conv_unsigned(0,4) then -- state "0000" means + if s_ren = '1' then -- to listen for a 1 to 0 + case s_mode is -- transition + when ("01") | ("11") => + if smod_i = '1' then + if s_tf = '1' then + s_det_ff0 <= rxd_i; + s_det_ff1 <= s_det_ff0; + end if; + else + if s_rxpre_count(0) = '1' then + s_det_ff0 <= rxd_i; + s_det_ff1 <= s_det_ff0; + end if; + end if; + when ("10") => + if smod_i = '1' then + if s_rxpre_count(0) = '1' then + s_det_ff0 <= rxd_i; + s_det_ff1 <= s_det_ff0; + end if; + else + if s_rxpre_count(1) = '1' then + s_det_ff0 <= rxd_i; + s_det_ff1 <= s_det_ff0; + end if; + end if; + when others => + null; + end case; + else + s_det_ff0 <= '0'; + s_det_ff1 <= '0'; + end if; + else -- in all other states + s_det_ff0 <= '0'; + s_det_ff1 <= '0'; + if s_ren = '1' then -- sample for data bits + case s_mode is + when ("01") | ("11") => + if smod_i = '1' then + if s_rxpre_count(3 downto 0) = conv_unsigned(7,4) or + s_rxpre_count(3 downto 0) = conv_unsigned(8,4) or + s_rxpre_count(3 downto 0) = conv_unsigned(9,4) then + s_rxd_ff0 <= rxd_i; + s_rxd_ff1 <= s_rxd_ff0; + s_rxd_ff2 <= s_rxd_ff1; + end if; + else + if s_rxpre_count(4 downto 0) = conv_unsigned(14,5) or + s_rxpre_count(4 downto 0) = conv_unsigned(16,5) or + s_rxpre_count(4 downto 0) = conv_unsigned(18,5) then + s_rxd_ff0 <= rxd_i; + s_rxd_ff1 <= s_rxd_ff0; + s_rxd_ff2 <= s_rxd_ff1; + end if; + end if; + when ("10") => + if smod_i = '1' then + if s_rxpre_count(4 downto 0) = conv_unsigned(14,5) or + s_rxpre_count(4 downto 0) = conv_unsigned(16,5) or + s_rxpre_count(4 downto 0) = conv_unsigned(18,5) then + s_rxd_ff0 <= rxd_i; + s_rxd_ff1 <= s_rxd_ff0; + s_rxd_ff2 <= s_rxd_ff1; + end if; + else + if s_rxpre_count(5 downto 0) = conv_unsigned(28,6) or + s_rxpre_count(5 downto 0) = conv_unsigned(32,6) or + s_rxpre_count(5 downto 0) = conv_unsigned(36,6) then + s_rxd_ff0 <= rxd_i; + s_rxd_ff1 <= s_rxd_ff0; + s_rxd_ff2 <= s_rxd_ff1; + end if; + end if; + when others => + null; + end case; + end if; + end if; + end if; + end if; + + end process p_sample_rx; + + +------------------------------------------------------------------------------- +--*************************** TRANSMIT **************************************** +-- This is the finit state machine for the transmit shift register +------------------------------------------------------------------------------- + + txd_o <= s_txdm0; + + p_transmit : process (clk, cen, reset) + + variable v_txstep : std_logic_vector(1 downto 0); + + begin + + if reset = '1' then + s_tran_state <= conv_unsigned(0, 4); + s_tran_sh <= conv_unsigned(0, 11); + s_tran_done <= '0'; + + s_txdm0 <= '1'; + rxd_o <= '1'; + rxdwr_o <= '0'; + else + if clk'event and clk = '1' and cen='1' then + + -- Set default behavior + v_txstep := "00"; + + case s_mode is +------------------------------------------------------------------------------- +-- MODE 0 +------------------------------------------------------------------------------- + when ("00") => + + if s_tran_state = conv_unsigned(1, 4) or + s_tran_state = conv_unsigned(2, 4) or + s_tran_state = conv_unsigned(3, 4) or + s_tran_state = conv_unsigned(4, 4) or + s_tran_state = conv_unsigned(5, 4) or + s_tran_state = conv_unsigned(6, 4) or + s_tran_state = conv_unsigned(7, 4) or + s_tran_state = conv_unsigned(8, 4) or + s_recv_state = conv_unsigned(1, 4) or + s_recv_state = conv_unsigned(2, 4) or + s_recv_state = conv_unsigned(3, 4) or + s_recv_state = conv_unsigned(4, 4) or + s_recv_state = conv_unsigned(5, 4) or + s_recv_state = conv_unsigned(6, 4) or + s_recv_state = conv_unsigned(7, 4) or + s_recv_state = conv_unsigned(8, 4) then + if s_txpre_count(3 downto 0) = conv_unsigned(14, 4) or + s_txpre_count(3 downto 0) = conv_unsigned(6, 4) then + s_txdm0 <= not(s_txdm0); + end if; + else + s_txdm0 <= '1'; + end if; + + if s_m0_shift_en = '1' then + case s_tran_state is + when ("0001") => -- D1 + s_tran_sh(10) <= '1'; + s_tran_sh(9 downto 0) <= s_tran_sh(10 downto 1); + v_txstep := "01"; + rxd_o <= s_tran_sh(1); + rxdwr_o <= '1'; + when ("0010") => -- D2 + s_tran_sh(10) <= '1'; + s_tran_sh(9 downto 0) <= s_tran_sh(10 downto 1); + v_txstep := "01"; + rxd_o <= s_tran_sh(1); + rxdwr_o <= '1'; + when ("0011") => -- D3 + s_tran_sh(10) <= '1'; + s_tran_sh(9 downto 0) <= s_tran_sh(10 downto 1); + v_txstep := "01"; + rxd_o <= s_tran_sh(1); + rxdwr_o <= '1'; + when ("0100") => -- D4 + s_tran_sh(10) <= '1'; + s_tran_sh(9 downto 0) <= s_tran_sh(10 downto 1); + v_txstep := "01"; + rxd_o <= s_tran_sh(1); + rxdwr_o <= '1'; + when ("0101") => -- D5 + s_tran_sh(10) <= '1'; + s_tran_sh(9 downto 0) <= s_tran_sh(10 downto 1); + v_txstep := "01"; + rxd_o <= s_tran_sh(1); + rxdwr_o <= '1'; + when ("0110") => -- D6 + s_tran_sh(10) <= '1'; + s_tran_sh(9 downto 0) <= s_tran_sh(10 downto 1); + v_txstep := "01"; + rxd_o <= s_tran_sh(1); + rxdwr_o <= '1'; + when ("0111") => -- D7 + s_tran_sh(10) <= '1'; + s_tran_sh(9 downto 0) <= s_tran_sh(10 downto 1); + v_txstep := "01"; + rxd_o <= s_tran_sh(1); + rxdwr_o <= '1'; + when ("1000") => -- D8, STOP BIT + s_tran_sh(10) <= '1'; + s_tran_sh(9 downto 0) <= s_tran_sh(10 downto 1); + s_tran_done <= '1'; + v_txstep := "10"; + rxd_o <= s_tran_sh(1); + rxdwr_o <= '1'; + when others => -- D0 + -- commence transmission if conditions are met + rxdwr_o <= '0'; + if s_trans = '1' then + s_tran_sh(10 downto 8) <= conv_unsigned(7, 3); + s_tran_sh(7 downto 0) <= unsigned(sbuf_i); + v_txstep := "01"; + s_tran_done <= '0'; + rxd_o <= sbuf_i(0); + rxdwr_o <= '1'; + end if; + end case; + end if; +------------------------------------------------------------------------------- +-- MODE 1 +------------------------------------------------------------------------------- + when ("01") => + rxdwr_o <= '0'; + rxd_o <= '0'; + case s_tran_state is + when ("0001") => -- D1 + if s_m13_txshift_en = '1' then + s_tran_sh(10) <= '1'; + s_tran_sh(9 downto 0) <= s_tran_sh(10 downto 1); + v_txstep := "01"; + s_txdm0 <= s_tran_sh(1); + end if; + when ("0010") => -- D2 + if s_m13_txshift_en = '1' then + s_tran_sh(10) <= '1'; + s_tran_sh(9 downto 0) <= s_tran_sh(10 downto 1); + v_txstep := "01"; + s_txdm0 <= s_tran_sh(1); + end if; + when ("0011") => -- D3 + if s_m13_txshift_en = '1' then + s_tran_sh(10) <= '1'; + s_tran_sh(9 downto 0) <= s_tran_sh(10 downto 1); + v_txstep := "01"; + s_txdm0 <= s_tran_sh(1); + end if; + when ("0100") => -- D4 + if s_m13_txshift_en = '1' then + s_tran_sh(10) <= '1'; + s_tran_sh(9 downto 0) <= s_tran_sh(10 downto 1); + v_txstep := "01"; + s_txdm0 <= s_tran_sh(1); + end if; + when ("0101") => -- D5 + if s_m13_txshift_en = '1' then + s_tran_sh(10) <= '1'; + s_tran_sh(9 downto 0) <= s_tran_sh(10 downto 1); + v_txstep := "01"; + s_txdm0 <= s_tran_sh(1); + end if; + when ("0110") => -- D6 + if s_m13_txshift_en = '1' then + s_tran_sh(10) <= '1'; + s_tran_sh(9 downto 0) <= s_tran_sh(10 downto 1); + v_txstep := "01"; + s_txdm0 <= s_tran_sh(1); + end if; + when ("0111") => -- D7 + if s_m13_txshift_en = '1' then + s_tran_sh(10) <= '1'; + s_tran_sh(9 downto 0) <= s_tran_sh(10 downto 1); + v_txstep := "01"; + s_txdm0 <= s_tran_sh(1); + end if; + when ("1000") => -- D8 + if s_m13_txshift_en = '1' then + s_tran_sh(10) <= '1'; + s_tran_sh(9 downto 0) <= s_tran_sh(10 downto 1); + v_txstep := "01"; + s_txdm0 <= s_tran_sh(1); + end if; + when ("1001") => -- D9, set done bit + if s_m13_txshift_en = '1' then + s_tran_sh(10) <= '1'; + s_tran_sh(9 downto 0) <= s_tran_sh(10 downto 1); + s_tran_done <= '1'; + v_txstep := "10"; + s_txdm0 <= s_tran_sh(1); + end if; + when others => -- D0 + -- commence transmission if conditions are met + s_txdm0 <= '1'; + if s_m13_txshift_en = '1' then + if s_trans = '1' then + s_tran_sh(10 downto 9) <= conv_unsigned(3, 2); + s_tran_sh(8 downto 1) <= unsigned(sbuf_i); + s_tran_sh(0) <= '0'; + v_txstep := "01"; + s_tran_done <= '0'; + s_txdm0 <= '0'; + end if; + end if; + end case; +------------------------------------------------------------------------------- +-- MODE 2 +------------------------------------------------------------------------------- + when ("10") => + rxdwr_o <= '0'; + rxd_o <= '0'; + case s_tran_state is + when ("0001") => -- D1 + if s_m2_txshift_en = '1' then + s_tran_sh(10) <= '1'; + s_tran_sh(9 downto 0) <= s_tran_sh(10 downto 1); + v_txstep := "01"; + s_txdm0 <= s_tran_sh(1); + end if; + when ("0010") => -- D2 + if s_m2_txshift_en = '1' then + s_tran_sh(10) <= '1'; + s_tran_sh(9 downto 0) <= s_tran_sh(10 downto 1); + v_txstep := "01"; + s_txdm0 <= s_tran_sh(1); + end if; + when ("0011") => -- D3 + if s_m2_txshift_en = '1' then + s_tran_sh(10) <= '1'; + s_tran_sh(9 downto 0) <= s_tran_sh(10 downto 1); + v_txstep := "01"; + s_txdm0 <= s_tran_sh(1); + end if; + when ("0100") => -- D4 + if s_m2_txshift_en = '1' then + s_tran_sh(10) <= '1'; + s_tran_sh(9 downto 0) <= s_tran_sh(10 downto 1); + v_txstep := "01"; + s_txdm0 <= s_tran_sh(1); + end if; + when ("0101") => -- D5 + if s_m2_txshift_en = '1' then + s_tran_sh(10) <= '1'; + s_tran_sh(9 downto 0) <= s_tran_sh(10 downto 1); + v_txstep := "01"; + s_txdm0 <= s_tran_sh(1); + end if; + when ("0110") => -- D6 + if s_m2_txshift_en = '1' then + s_tran_sh(10) <= '1'; + s_tran_sh(9 downto 0) <= s_tran_sh(10 downto 1); + v_txstep := "01"; + s_txdm0 <= s_tran_sh(1); + end if; + when ("0111") => -- D7 + if s_m2_txshift_en = '1' then + s_tran_sh(10) <= '1'; + s_tran_sh(9 downto 0) <= s_tran_sh(10 downto 1); + v_txstep := "01"; + s_txdm0 <= s_tran_sh(1); + end if; + when ("1000") => -- D8 + if s_m2_txshift_en = '1' then + s_tran_sh(10) <= '1'; + s_tran_sh(9 downto 0) <= s_tran_sh(10 downto 1); + v_txstep := "01"; + s_txdm0 <= s_tran_sh(1); + end if; + when ("1001") => -- D9 + if s_m2_txshift_en = '1' then + s_tran_sh(10) <= '1'; + s_tran_sh(9 downto 0) <= s_tran_sh(10 downto 1); + v_txstep := "01"; + s_txdm0 <= s_tran_sh(1); + end if; + when ("1010") => -- D10, set done bit + if s_m2_txshift_en = '1' then + s_tran_sh(10) <= '1'; + s_tran_sh(9 downto 0) <= s_tran_sh(10 downto 1); + s_tran_done <= '1'; + v_txstep := "10"; + s_txdm0 <= s_tran_sh(1); + end if; + when others => -- D0 + -- commence transmission if conditions are met + s_txdm0 <= '1'; + if s_m2_txshift_en = '1' then + if s_trans = '1' then + s_tran_sh(10) <= '1'; + s_tran_sh(9) <= s_tb8; + s_tran_sh(8 downto 1) <= unsigned(sbuf_i); + s_tran_sh(0) <= '0'; + v_txstep := "01"; + s_tran_done <= '0'; + s_txdm0 <= '0'; + end if; + end if; + end case; +------------------------------------------------------------------------------- +-- MODE 3 +------------------------------------------------------------------------------- + when ("11") => + rxd_o <= '0'; + rxdwr_o <= '0'; + case s_tran_state is + when ("0001") => -- D1 + if s_m13_txshift_en = '1' then + s_tran_sh(10) <= '1'; + s_tran_sh(9 downto 0) <= s_tran_sh(10 downto 1); + v_txstep := "01"; + s_txdm0 <= s_tran_sh(1); + end if; + when ("0010") => -- D2 + if s_m13_txshift_en = '1' then + s_tran_sh(10) <= '1'; + s_tran_sh(9 downto 0) <= s_tran_sh(10 downto 1); + v_txstep := "01"; + s_txdm0 <= s_tran_sh(1); + end if; + when ("0011") => -- D3 + if s_m13_txshift_en = '1' then + s_tran_sh(10) <= '1'; + s_tran_sh(9 downto 0) <= s_tran_sh(10 downto 1); + v_txstep := "01"; + s_txdm0 <= s_tran_sh(1); + end if; + when ("0100") => -- D4 + if s_m13_txshift_en = '1' then + s_tran_sh(10) <= '1'; + s_tran_sh(9 downto 0) <= s_tran_sh(10 downto 1); + v_txstep := "01"; + s_txdm0 <= s_tran_sh(1); + end if; + when ("0101") => -- D5 + if s_m13_txshift_en = '1' then + s_tran_sh(10) <= '1'; + s_tran_sh(9 downto 0) <= s_tran_sh(10 downto 1); + v_txstep := "01"; + s_txdm0 <= s_tran_sh(1); + end if; + when ("0110") => -- D6 + if s_m13_txshift_en = '1' then + s_tran_sh(10) <= '1'; + s_tran_sh(9 downto 0) <= s_tran_sh(10 downto 1); + v_txstep := "01"; + s_txdm0 <= s_tran_sh(1); + end if; + when ("0111") => -- D7 + if s_m13_txshift_en = '1' then + s_tran_sh(10) <= '1'; + s_tran_sh(9 downto 0) <= s_tran_sh(10 downto 1); + v_txstep := "01"; + s_txdm0 <= s_tran_sh(1); + end if; + when ("1000") => -- D8 + if s_m13_txshift_en = '1' then + s_tran_sh(10) <= '1'; + s_tran_sh(9 downto 0) <= s_tran_sh(10 downto 1); + v_txstep := "01"; + s_txdm0 <= s_tran_sh(1); + end if; + when ("1001") => -- D9 + if s_m13_txshift_en = '1' then + s_tran_sh(10) <= '1'; + s_tran_sh(9 downto 0) <= s_tran_sh(10 downto 1); + v_txstep := "01"; + s_txdm0 <= s_tran_sh(1); + end if; + when ("1010") => -- D10, set done bit + if s_m13_txshift_en = '1' then + s_tran_sh(10) <= '1'; + s_tran_sh(9 downto 0) <= s_tran_sh(10 downto 1); + s_tran_done <= '1'; + v_txstep := "10"; + s_txdm0 <= s_tran_sh(1); + end if; + when others => -- D0 + -- commence transmission if conditions are met + s_txdm0 <= '1'; + if s_m13_txshift_en = '1' then + if s_trans = '1' then + s_tran_sh(10) <= '1'; + s_tran_sh(9) <= s_tb8; + s_tran_sh(8 downto 1) <= unsigned(sbuf_i); + s_tran_sh(0) <= '0'; + s_tran_done <= '0'; + v_txstep := "01"; + s_txdm0 <= '0'; + end if; + end if; + end case; +------------------------------------------------------------------------------- + when others => + null; + end case; + + case v_txstep is + when "01" => + s_tran_state <= s_tran_state + conv_unsigned(1, 1); + when "10" => + s_tran_state <= conv_unsigned(0, 4); + when others => + null; + end case; + + end if; + end if; + end process p_transmit; + +------------------------------------------------------------------------------- +--**************************** RECEIVE **************************************** +-- This is the finit state machine for the receive shift register +------------------------------------------------------------------------------- + + p_receive: process (clk, cen, reset) + variable v_rxstep : std_logic_vector(1 downto 0); + + begin + + if reset = '1' then + s_recv_state <= conv_unsigned(0,4); + s_recv_sh <= conv_unsigned(0,8); + s_recv_buf <= conv_unsigned(0,8); + s_recv_done <= '0'; + s_rb8 <= '0'; + else + if clk'event and clk = '1' and cen='1' then + +------------------------------------------------------------------------------- +-- MODE 0 +------------------------------------------------------------------------------- + v_rxstep := "00"; + case s_mode is + when ("00") => + case s_recv_state is + when ("0000") => -- D0 + -- commence reception if conditions are met + if s_ren = '1' and s_ri = '0' then + if s_m0_shift_en = '1' then + v_rxstep := "01"; + s_recv_done <= '0'; + end if; + end if; + when ("0001") => -- D1 + if s_m0_shift_en = '1' then + s_recv_sh(7) <= rxd_i; + s_recv_sh(6 downto 0) <= s_recv_sh(7 downto 1); + v_rxstep := "01"; + end if; + when ("0010") => -- D2 + if s_m0_shift_en = '1' then + s_recv_sh(7) <= rxd_i; + s_recv_sh(6 downto 0) <= s_recv_sh(7 downto 1); + v_rxstep := "01"; + end if; + when ("0011") => -- D3 + if s_m0_shift_en = '1' then + s_recv_sh(7) <= rxd_i; + s_recv_sh(6 downto 0) <= s_recv_sh(7 downto 1); + v_rxstep := "01"; + end if; + when ("0100") => -- D4 + if s_m0_shift_en = '1' then + s_recv_sh(7) <= rxd_i; + s_recv_sh(6 downto 0) <= s_recv_sh(7 downto 1); + v_rxstep := "01"; + end if; + when ("0101") => -- D5 + if s_m0_shift_en = '1' then + s_recv_sh(7) <= rxd_i; + s_recv_sh(6 downto 0) <= s_recv_sh(7 downto 1); + v_rxstep := "01"; + end if; + when ("0110") => -- D6 + if s_m0_shift_en = '1' then + s_recv_sh(7) <= rxd_i; + s_recv_sh(6 downto 0) <= s_recv_sh(7 downto 1); + v_rxstep := "01"; + end if; + when ("0111") => -- D6 + if s_m0_shift_en = '1' then + s_recv_sh(7) <= rxd_i; + s_recv_sh(6 downto 0) <= s_recv_sh(7 downto 1); + v_rxstep := "01"; + end if; + when ("1000") => -- D7, set bits and store data + if s_m0_shift_en = '1' then + s_recv_sh(7) <= rxd_i; + s_recv_sh(6 downto 0) <= s_recv_sh(7 downto 1); + s_recv_done <= '1'; + s_recv_buf(7) <= rxd_i; + s_recv_buf(6 downto 0) <= s_recv_sh(7 downto 1); + v_rxstep := "10"; + end if; + when others => + v_rxstep := "10"; + end case; + +------------------------------------------------------------------------------- +-- MODE 1 +------------------------------------------------------------------------------- + when ("01") => + case s_recv_state is + when ("0000") => -- synchronise reception + if s_ren = '1' and s_detect = '1' then + v_rxstep := "01"; + s_recv_sh <= conv_unsigned(0,8); + s_recv_done <= '0'; + end if; + when ("0001") => -- D0 = START BIT + if s_detect = '0' then + if s_rxd_val = '0' then + if s_m13_rxshift_en = '1' then + s_recv_sh(7) <= s_rxd_val; + s_recv_sh(6 downto 0) <= s_recv_sh(7 downto 1); + v_rxstep := "01"; + end if; + else -- reject false start bits + if s_m13_rxshift_en = '1' then + v_rxstep := "10"; + end if; + end if; + end if; + when ("0010") => -- D1 + if s_m13_rxshift_en = '1' then + s_recv_sh(7) <= s_rxd_val; + s_recv_sh(6 downto 0) <= s_recv_sh(7 downto 1); + v_rxstep := "01"; + end if; + when ("0011") => -- D2 + if s_m13_rxshift_en = '1' then + s_recv_sh(7) <= s_rxd_val; + s_recv_sh(6 downto 0) <= s_recv_sh(7 downto 1); + v_rxstep := "01"; + end if; + when ("0100") => -- D3 + if s_m13_rxshift_en = '1' then + s_recv_sh(7) <= s_rxd_val; + s_recv_sh(6 downto 0) <= s_recv_sh(7 downto 1); + v_rxstep := "01"; + end if; + when ("0101") => -- D4 + if s_m13_rxshift_en = '1' then + s_recv_sh(7) <= s_rxd_val; + s_recv_sh(6 downto 0) <= s_recv_sh(7 downto 1); + v_rxstep := "01"; + end if; + when ("0110") => -- D5 + if s_m13_rxshift_en = '1' then + s_recv_sh(7) <= s_rxd_val; + s_recv_sh(6 downto 0) <= s_recv_sh(7 downto 1); + v_rxstep := "01"; + end if; + when ("0111") => -- D6 + if s_m13_rxshift_en = '1' then + s_recv_sh(7) <= s_rxd_val; + s_recv_sh(6 downto 0) <= s_recv_sh(7 downto 1); + v_rxstep := "01"; + end if; + when ("1000") => -- D7 + if s_m13_rxshift_en = '1' then + s_recv_sh(7) <= s_rxd_val; + s_recv_sh(6 downto 0) <= s_recv_sh(7 downto 1); + v_rxstep := "01"; + end if; + when ("1001") => -- D8 + if s_m13_rxshift_en = '1' then + s_recv_sh(7) <= s_rxd_val; + s_recv_sh(6 downto 0) <= s_recv_sh(7 downto 1); + v_rxstep := "01"; + end if; + when ("1010") => -- D9 = STOP BIT + -- store data and set interrupt bit if conditions are met. + if (s_ri = '0' and s_sm2 = '0') or + (s_ri = '0' and s_rxd_val = '1') then + --if s_m13_rxshift_en = '1' then + if s_rxpre_count(3 downto 0) = conv_unsigned(10,4) then -- CK, CV: changed to enter state 0 after one stopbit + s_recv_sh(7) <= s_rxd_val; + s_recv_sh(6 downto 0) <= s_recv_sh(7 downto 1); + v_rxstep := "10"; + s_recv_done <= '1'; + s_rb8 <= s_rxd_val; + s_recv_buf <= s_recv_sh(7 downto 0); + end if; + -- forget data and recommence listening for a start bit + else + if s_m13_rxshift_en = '1' then + v_rxstep := "10"; + end if; + end if; + when others => + v_rxstep := "10"; + end case; + +------------------------------------------------------------------------------- +-- MODE 2 +------------------------------------------------------------------------------- + when ("10") => + case s_recv_state is + when ("0000") => -- synchronise reception + if s_ren = '1' and s_detect = '1' then + v_rxstep := "01"; + s_recv_sh <= conv_unsigned(0,8); + s_recv_done <= '0'; + end if; + when ("0001") => -- D0 = START BIT + if s_rxd_val = '0' then + if s_m2_rxshift_en = '1' then + s_recv_sh(7) <= s_rxd_val; + s_recv_sh(6 downto 0) <= s_recv_sh(7 downto 1); + v_rxstep := "01"; + end if; + else -- reject false start bits + if s_m2_rxshift_en = '1' then + v_rxstep := "10"; + end if; + end if; + when ("0010") => -- D1 + if s_m2_rxshift_en = '1' then + s_recv_sh(7) <= s_rxd_val; + s_recv_sh(6 downto 0) <= s_recv_sh(7 downto 1); + v_rxstep := "01"; + end if; + when ("0011") => -- D2 + if s_m2_rxshift_en = '1' then + s_recv_sh(7) <= s_rxd_val; + s_recv_sh(6 downto 0) <= s_recv_sh(7 downto 1); + v_rxstep := "01"; + end if; + when ("0100") => -- D3 + if s_m2_rxshift_en = '1' then + s_recv_sh(7) <= s_rxd_val; + s_recv_sh(6 downto 0) <= s_recv_sh(7 downto 1); + v_rxstep := "01"; + end if; + when ("0101") => -- D4 + if s_m2_rxshift_en = '1' then + s_recv_sh(7) <= s_rxd_val; + s_recv_sh(6 downto 0) <= s_recv_sh(7 downto 1); + v_rxstep := "01"; + end if; + when ("0110") => -- D5 + if s_m2_rxshift_en = '1' then + s_recv_sh(7) <= s_rxd_val; + s_recv_sh(6 downto 0) <= s_recv_sh(7 downto 1); + v_rxstep := "01"; + end if; + when ("0111") => -- D6 + if s_m2_rxshift_en = '1' then + s_recv_sh(7) <= s_rxd_val; + s_recv_sh(6 downto 0) <= s_recv_sh(7 downto 1); + v_rxstep := "01"; + end if; + when ("1000") => -- D7 + if s_m2_rxshift_en = '1' then + s_recv_sh(7) <= s_rxd_val; + s_recv_sh(6 downto 0) <= s_recv_sh(7 downto 1); + v_rxstep := "01"; + end if; + when ("1001") => -- D8 + if s_m2_rxshift_en = '1' then + s_recv_sh(7) <= s_rxd_val; + s_recv_sh(6 downto 0) <= s_recv_sh(7 downto 1); + v_rxstep := "01"; + end if; + when ("1010") => -- D9 + -- store data and set interrupt bit if conditions are met. + if (s_ri = '0' and s_sm2 = '0') or + (s_ri = '0' and s_rxd_val = '1') then + if s_m2_rxshift_en = '1' then + s_recv_sh(7) <= s_rxd_val; + s_recv_sh(6 downto 0) <= s_recv_sh(7 downto 1); + s_recv_done <= '1'; + s_rb8 <= s_rxd_val; + s_recv_buf <= s_recv_sh(7 downto 0); + end if; + end if; + -- forget data + if s_m2_rxshift_en = '1' then + v_rxstep := "01"; + end if; + when ("1011") => -- D10 STOP BIT + -- recommence listening for a start bit + if s_m2_rxshift_en = '1' then + -- s_recv_state <= conv_unsigned(0,4); + v_rxstep := "10"; + end if; + when others => + -- s_recv_state <= conv_unsigned(0,4); + v_rxstep := "10"; + end case; + +------------------------------------------------------------------------------- +-- MODE 3 +------------------------------------------------------------------------------- + when ("11") => + case s_recv_state is + when ("0000") => -- synchronise reception + if s_ren = '1' and s_detect = '1' then + v_rxstep := "01"; + s_recv_sh <= conv_unsigned(0,8); + s_recv_done <= '0'; + end if; + when ("0001") => -- D0 = START BIT + if s_detect = '0' then + if s_rxd_val = '0' then + if s_m13_rxshift_en = '1' then + s_recv_sh(7) <= s_rxd_val; + s_recv_sh(6 downto 0) <= s_recv_sh(7 downto 1); + v_rxstep := "01"; + end if; + else -- reject false start bits + if s_m13_rxshift_en = '1' then + v_rxstep := "10"; + end if; + end if; + end if; + when ("0010") => -- D1 + if s_m13_rxshift_en = '1' then + s_recv_sh(7) <= s_rxd_val; + s_recv_sh(6 downto 0) <= s_recv_sh(7 downto 1); + v_rxstep := "01"; + end if; + when ("0011") => -- D2 + if s_m13_rxshift_en = '1' then + s_recv_sh(7) <= s_rxd_val; + s_recv_sh(6 downto 0) <= s_recv_sh(7 downto 1); + v_rxstep := "01"; + end if; + when ("0100") => -- D3 + if s_m13_rxshift_en = '1' then + s_recv_sh(7) <= s_rxd_val; + s_recv_sh(6 downto 0) <= s_recv_sh(7 downto 1); + v_rxstep := "01"; + end if; + when ("0101") => -- D4 + if s_m13_rxshift_en = '1' then + s_recv_sh(7) <= s_rxd_val; + s_recv_sh(6 downto 0) <= s_recv_sh(7 downto 1); + v_rxstep := "01"; + end if; + when ("0110") => -- D5 + if s_m13_rxshift_en = '1' then + s_recv_sh(7) <= s_rxd_val; + s_recv_sh(6 downto 0) <= s_recv_sh(7 downto 1); + v_rxstep := "01"; + end if; + when ("0111") => -- D6 + if s_m13_rxshift_en = '1' then + s_recv_sh(7) <= s_rxd_val; + s_recv_sh(6 downto 0) <= s_recv_sh(7 downto 1); + v_rxstep := "01"; + end if; + when ("1000") => -- D7 + if s_m13_rxshift_en = '1' then + s_recv_sh(7) <= s_rxd_val; + s_recv_sh(6 downto 0) <= s_recv_sh(7 downto 1); + v_rxstep := "01"; + end if; + when ("1001") => -- D8 + if s_m13_rxshift_en = '1' then + s_recv_sh(7) <= s_rxd_val; + s_recv_sh(6 downto 0) <= s_recv_sh(7 downto 1); + v_rxstep := "01"; + end if; + when ("1010") => -- D9 + -- store data and set interrupt bit if conditions are met. + if (s_ri = '0' and s_sm2 = '0') or + (s_ri = '0' and s_rxd_val = '1') then + if s_m13_rxshift_en = '1' then + s_recv_sh(7) <= s_rxd_val; + s_recv_sh(6 downto 0) <= s_recv_sh(7 downto 1); + s_recv_done <= '1'; + s_rb8 <= s_rxd_val; + s_recv_buf <= s_recv_sh(7 downto 0); + end if; + end if; + -- forget data + if s_m13_rxshift_en = '1' then + v_rxstep := "01"; + end if; + when ("1011") => -- D10 STOP BIT + -- recommence listening for a start bit + if s_m13_rxshift_en = '1' then + v_rxstep := "10"; + end if; + when others => + v_rxstep := "10"; + end case; + when others => + null; + end case; + + case v_rxstep is + when "01" => + s_recv_state <= s_recv_state + conv_unsigned(1,1); + when "10" => + s_recv_state <= conv_unsigned(0,4); + when others => + null; + end case; + + end if; + end if; + + + end process p_receive; + + +end rtl; diff --git a/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/8051/mc8051_siu_rtl_cfg.vhd b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/8051/mc8051_siu_rtl_cfg.vhd new file mode 100644 index 0000000000000000000000000000000000000000..4f8b1def758e6c97a1df8b32d5a419eceb95e16b --- /dev/null +++ b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/8051/mc8051_siu_rtl_cfg.vhd @@ -0,0 +1,71 @@ +------------------------------------------------------------------------------- +-- -- +-- X X XXXXXX XXXXXX XXXXXX XXXXXX X -- +-- XX XX X X X X X X X XX -- +-- X X X X X X X X X X X X -- +-- X X X X X X X X X X X X -- +-- X X X X XXXXXX X X XXXXXX X -- +-- X X X X X X X X X -- +-- X X X X X X X X X -- +-- X X X X X X X X X X -- +-- X X XXXXXX XXXXXX XXXXXX XXXXXX X -- +-- -- +-- -- +-- O R E G A N O S Y S T E M S -- +-- -- +-- Design & Consulting -- +-- -- +------------------------------------------------------------------------------- +-- -- +-- Web: http://www.oregano.at/ -- +-- -- +-- Contact: mc8051@oregano.at -- +-- -- +------------------------------------------------------------------------------- +-- -- +-- MC8051 - VHDL 8051 Microcontroller IP Core -- +-- Copyright (C) 2001 OREGANO SYSTEMS -- +-- -- +-- This library is free software; you can redistribute it and/or -- +-- modify it under the terms of the GNU Lesser General Public -- +-- License as published by the Free Software Foundation; either -- +-- version 2.1 of the License, or (at your option) any later version. -- +-- -- +-- This library is distributed in the hope that it will be useful, -- +-- but WITHOUT ANY WARRANTY; without even the implied warranty of -- +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -- +-- Lesser General Public License for more details. -- +-- -- +-- Full details of the license can be found in the file LGPL.TXT. -- +-- -- +-- You should have received a copy of the GNU Lesser General Public -- +-- License along with this library; if not, write to the Free Software -- +-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -- +-- -- +------------------------------------------------------------------------------- +-- +-- +-- Author: Roland Hller +-- +-- Filename: mc8051_siu_rtl_cfg.vhd +-- +-- Date of Creation: Mon Aug 9 12:14:48 1999 +-- +-- Version: $Revision: 1.4 $ +-- +-- Date of Latest Version: $Date: 2002-01-07 12:17:45 $ +-- +-- +-- Description: Serial interface unit for the mc8051 microcontroller. +-- +-- +-- +-- +------------------------------------------------------------------------------- +configuration mc8051_siu_rtl_cfg of mc8051_siu is + + for rtl + + end for; + +end mc8051_siu_rtl_cfg; diff --git a/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/8051/mc8051_tmrctr_.vhd b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/8051/mc8051_tmrctr_.vhd new file mode 100644 index 0000000000000000000000000000000000000000..7f3b94af07712ff4b203b68ac00c9bbd00380374 --- /dev/null +++ b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/8051/mc8051_tmrctr_.vhd @@ -0,0 +1,96 @@ +------------------------------------------------------------------------------- +-- -- +-- X X XXXXXX XXXXXX XXXXXX XXXXXX X -- +-- XX XX X X X X X X X XX -- +-- X X X X X X X X X X X X -- +-- X X X X X X X X X X X X -- +-- X X X X XXXXXX X X XXXXXX X -- +-- X X X X X X X X X -- +-- X X X X X X X X X -- +-- X X X X X X X X X X -- +-- X X XXXXXX XXXXXX XXXXXX XXXXXX X -- +-- -- +-- -- +-- O R E G A N O S Y S T E M S -- +-- -- +-- Design & Consulting -- +-- -- +------------------------------------------------------------------------------- +-- -- +-- Web: http://www.oregano.at/ -- +-- -- +-- Contact: mc8051@oregano.at -- +-- -- +------------------------------------------------------------------------------- +-- -- +-- MC8051 - VHDL 8051 Microcontroller IP Core -- +-- Copyright (C) 2001 OREGANO SYSTEMS -- +-- -- +-- This library is free software; you can redistribute it and/or -- +-- modify it under the terms of the GNU Lesser General Public -- +-- License as published by the Free Software Foundation; either -- +-- version 2.1 of the License, or (at your option) any later version. -- +-- -- +-- This library is distributed in the hope that it will be useful, -- +-- but WITHOUT ANY WARRANTY; without even the implied warranty of -- +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -- +-- Lesser General Public License for more details. -- +-- -- +-- Full details of the license can be found in the file LGPL.TXT. -- +-- -- +-- You should have received a copy of the GNU Lesser General Public -- +-- License along with this library; if not, write to the Free Software -- +-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -- +-- -- +------------------------------------------------------------------------------- +-- +-- +-- Author: Roland Hller +-- +-- Filename: mc8051_tmrctr_.vhd +-- +-- Date of Creation: Mon Aug 9 12:14:48 1999 +-- +-- Version: $Revision: 1.4 $ +-- +-- Date of Latest Version: $Date: 2002-01-07 12:17:45 $ +-- +-- +-- Description: Timer/Counter unit of the mc8051 microcontroller. +-- +-- +-- +-- +------------------------------------------------------------------------------- +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.std_logic_arith.all; + +-----------------------------ENTITY DECLARATION-------------------------------- + +entity mc8051_tmrctr is + + port (clk : in std_logic; --< system clock + cen : in std_logic; --< system clock enable + reset : in std_logic; --< system reset + int0_i : in std_logic; --< interrupt 0 + int1_i : in std_logic; --< interrupt 1 + t0_i : in std_logic; --< external clock for + -- timer/counter0 + t1_i : in std_logic; --< external clock for + -- timer/counter1 + tmod_i : in std_logic_vector(7 downto 0); --< from SFR register + tcon_tr0_i : in std_logic; --< timer run 0 + tcon_tr1_i : in std_logic; --< timer run 1 + reload_i : in std_logic_vector(7 downto 0); --< to load counter + wt_en_i : in std_logic; --< indicates reload + wt_i : in std_logic_vector(1 downto 0); --< reload which reg. + th0_o : out std_logic_vector(7 downto 0); --< contents of th0 + tl0_o : out std_logic_vector(7 downto 0); --< contents of tl0 + th1_o : out std_logic_vector(7 downto 0); --< contents of th1 + tl1_o : out std_logic_vector(7 downto 0); --< contents of tl1 + tf0_o : out std_logic; --< interrupt flag 0 + tf1_o : out std_logic); --< interrupt flag 1 + +end mc8051_tmrctr; + diff --git a/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/8051/mc8051_tmrctr_rtl.vhd b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/8051/mc8051_tmrctr_rtl.vhd new file mode 100644 index 0000000000000000000000000000000000000000..43ed380b92175145bee2f61576d60cdf186b86ee --- /dev/null +++ b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/8051/mc8051_tmrctr_rtl.vhd @@ -0,0 +1,766 @@ +------------------------------------------------------------------------------- +-- -- +-- X X XXXXXX XXXXXX XXXXXX XXXXXX X -- +-- XX XX X X X X X X X XX -- +-- X X X X X X X X X X X X -- +-- X X X X X X X X X X X X -- +-- X X X X XXXXXX X X XXXXXX X -- +-- X X X X X X X X X -- +-- X X X X X X X X X -- +-- X X X X X X X X X X -- +-- X X XXXXXX XXXXXX XXXXXX XXXXXX X -- +-- -- +-- -- +-- O R E G A N O S Y S T E M S -- +-- -- +-- Design & Consulting -- +-- -- +------------------------------------------------------------------------------- +-- -- +-- Web: http://www.oregano.at/ -- +-- -- +-- Contact: mc8051@oregano.at -- +-- -- +------------------------------------------------------------------------------- +-- -- +-- MC8051 - VHDL 8051 Microcontroller IP Core -- +-- Copyright (C) 2001 OREGANO SYSTEMS -- +-- -- +-- This library is free software; you can redistribute it and/or -- +-- modify it under the terms of the GNU Lesser General Public -- +-- License as published by the Free Software Foundation; either -- +-- version 2.1 of the License, or (at your option) any later version. -- +-- -- +-- This library is distributed in the hope that it will be useful, -- +-- but WITHOUT ANY WARRANTY; without even the implied warranty of -- +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -- +-- Lesser General Public License for more details. -- +-- -- +-- Full details of the license can be found in the file LGPL.TXT. -- +-- -- +-- You should have received a copy of the GNU Lesser General Public -- +-- License along with this library; if not, write to the Free Software -- +-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -- +-- -- +------------------------------------------------------------------------------- +-- +-- +-- Author: Roland Hller +-- +-- Filename: mc8051_tmrctr_rtl.vhd +-- +-- Date of Creation: Mon Aug 9 12:14:48 1999 +-- +-- Version: $Revision: 1.9 $ +-- +-- Date of Latest Version: $Date: 2006-09-07 09:43:21 $ +-- +-- +-- Description: Timer/Counter unit of the mc8051 microcontroller. +-- +-- +-- +-- +------------------------------------------------------------------------------- +architecture rtl of mc8051_tmrctr is + + signal s_pre_count : unsigned(3 downto 0); -- these two signals provide + signal s_count_enable : std_logic; -- a clock enable signal which + -- masks out every twelfth + -- rising edge of clk + + signal s_count0 : unsigned(15 downto 0); -- count for tmr/ctr0 + signal s_countl0 : unsigned(7 downto 0); -- count register for tmr/ctr0 + signal s_counth0 : unsigned(7 downto 0); -- count register for tmr/ctr0 + signal s_count1 : unsigned(15 downto 0); -- count for tmr/ctr1 + signal s_countl1 : unsigned(7 downto 0); -- count register for tmr/ctr1 + signal s_counth1 : unsigned(7 downto 0); -- count register for tmr/ctr1 + signal s_gate0 : std_logic; -- gate bit for tmr/ctr 0 + signal s_gate1 : std_logic; -- gate bit for tmr/ctr 1 + signal s_c_t0 : std_logic; -- tmr/ctr 0 is timer if 0 + signal s_c_t1 : std_logic; -- tmr/ctr 1 is timer if 0 + signal s_tmr_ctr0_en : std_logic; -- starts tmr/ctr 0 if 1 + signal s_tmr_ctr1_en : std_logic; -- starts tmr/ctr 1 if 1 + signal s_mode0 : unsigned(1 downto 0); -- mode of tmr/ctr 0 + signal s_mode1 : unsigned(1 downto 0); -- mode of tmr/ctr 1 + signal s_tf0 : std_logic; -- overflow flag of tmr/ctr 0 + signal s_tf1 : std_logic; -- overflow flag of tmr/ctr 1 + signal s_t0ff0 : std_logic; -- flipflop for edge dedection + signal s_t0ff1 : std_logic; -- flipflop for edge dedection + signal s_t0ff2 : std_logic; -- flipflop for edge dedection + signal s_t1ff0 : std_logic; -- flipflop for edge dedection + signal s_t1ff1 : std_logic; -- flipflop for edge dedection + signal s_t1ff2 : std_logic; -- flipflop for edge dedection + signal s_ext_edge0 : std_logic; -- 1 if external edge dedected + signal s_ext_edge1 : std_logic; -- 1 if external edge dedected + signal s_int0_sync : std_logic_vector(1 downto 0); -- sync int0 input + signal s_int1_sync : std_logic_vector(1 downto 0); -- sync int1 input + + +begin -- architecture rtl + + -- The names of the following signals make the code more readable. + s_gate0 <= tmod_i(3); + s_c_t0 <= tmod_i(2); + s_mode0(1) <= tmod_i(1); + s_mode0(0) <= tmod_i(0); + + s_gate1 <= tmod_i(7); + s_c_t1 <= tmod_i(6); + s_mode1(1) <= tmod_i(5); + s_mode1(0) <= tmod_i(4); + + -- These two signals start the corresponding timer/counter if they are 1. + s_tmr_ctr0_en <= tcon_tr0_i and (not(s_gate0) or s_int0_sync(1)); + s_tmr_ctr1_en <= (not(s_gate1) or s_int1_sync(1)) when + s_mode0 = conv_unsigned(3,2) else + tcon_tr1_i and (not(s_gate1) or s_int1_sync(1)); + + -- The outputs of this unit are the two timer overflow flags, which are read + -- by the control unit and the two 16 bit count registers to enable read + -- access. + tf0_o <= s_tf0; + tf1_o <= s_tf1; + th0_o <= std_logic_vector(s_count0(15 downto 8)); + tl0_o <= std_logic_vector(s_count0(7 downto 0)); + th1_o <= std_logic_vector(s_count1(15 downto 8)); + tl1_o <= std_logic_vector(s_count1(7 downto 0)); + +------------------------------------------------------------------------------- + -- The register s_pre_count is driven with the system clock. So a + -- good enable signal (which is stable when clk has its rising edge) can be + -- derived to mask out every twelfth pulse of clk. Also synchronize the + -- interrupt inputs here. + + s_count_enable <= '1' when s_pre_count = conv_unsigned(11,4) else '0'; + + p_divide_clk: process (clk, cen, reset) + + begin + + if reset = '1' then + s_pre_count <= conv_unsigned(0,4); + s_int0_sync <= "00"; + s_int1_sync <= "00"; + else + if clk'event and clk='1' and cen='1' then + s_pre_count <= s_pre_count + conv_unsigned(1,1); + if s_pre_count = conv_unsigned(11,4) then + s_pre_count <= conv_unsigned(0,4); + end if; + s_int0_sync(0) <= int0_i; + s_int0_sync(1) <= s_int0_sync(0); + s_int1_sync(0) <= int1_i; + s_int1_sync(1) <= s_int1_sync(0); + end if; + end if; + + end process p_divide_clk; + +------------------------------------------------------------------------------- + -- The two flip flops are updated every second clock period. + -- If a falling edge + -- on the port t0_i is dedected the signal s_ext_edge0 is set to 1 and with + -- the next rising edge of clk the counter0 is incremented. + -- The same function is realised for counter1. + s_ext_edge0 <= '1' when (s_t0ff1 = '0' and s_t0ff2 = '1') else '0'; + + p_sample_t0: process (clk, cen, reset) + + begin + + if reset = '1' then + s_t0ff0 <= '0'; + s_t0ff1 <= '0'; + s_t0ff2 <= '0'; + else + + if clk'event and clk = '1' and cen='1' then + if s_pre_count = conv_unsigned(6,3) then + if s_c_t0 = '1' then + s_t0ff0 <= t0_i; + s_t0ff1 <= s_t0ff0; + s_t0ff2 <= s_t0ff1; + end if; + end if; + end if; + end if; + + end process p_sample_t0; + + s_ext_edge1 <= '1' when (s_t1ff1 = '0' and s_t1ff2 = '1') else '0'; + + p_sample_t1: process (clk, cen, reset) + + begin + + if reset = '1' then + s_t1ff0 <= '0'; + s_t1ff1 <= '0'; + s_t1ff2 <= '0'; + else + if clk'event and clk = '1' and cen='1' then + if s_pre_count = conv_unsigned(6,3) then + if s_c_t1 = '1' then + s_t1ff0 <= t1_i; + s_t1ff1 <= s_t1ff0; + s_t1ff2 <= s_t1ff1; + end if; + end if; + end if; + end if; + + end process p_sample_t1; + +------------------------------------------------------------------------------ +--+++++++++++++++++++++ TIMER / COUNTER 0 ++++++++++++++++++++++++++++++-- +------------------------------------------------------------------------------ +-- This is timer/counter0. It is built around the 16 bit count register +-- s_count0 and realises its four operating modes +------------------------------------------------------------------------------ + s_count0(15 downto 8) <= s_counth0; + s_count0(7 downto 0) <= s_countl0; + s_count1(15 downto 8) <= s_counth1; + s_count1(7 downto 0) <= s_countl1; + + p_tmr_ctr: process (clk, cen, reset) + + begin + + if reset = '1' then -- perform asynchronous reset + + s_countl0 <= conv_unsigned(0,8); + s_counth0 <= conv_unsigned(0,8); + s_countl1 <= conv_unsigned(0,8); + s_counth1 <= conv_unsigned(0,8); + s_tf1 <= '0'; + s_tf0 <= '0'; + + else + + if clk'event and clk = '1' and cen='1' then + s_tf1 <= '0'; + s_tf0 <= '0'; + +------------------------------------------------------------------------------- +-- operating mode 0 (13 bit timer/counter) +------------------------------------------------------------------------------- + case s_mode0 is + when "00" => + + -- This section generates the timer/counter overflow flag0 + if s_tmr_ctr0_en = '1' then + if s_count_enable = '1' then + if s_c_t0 = '0' or (s_ext_edge0 = '1' and s_c_t0 = '1') then + if s_count0 = conv_unsigned(65311,16) then + s_tf0 <= '1'; + else + s_tf0 <= '0'; + end if; + end if; + end if; + end if; + + -- This section generates the low byte register of tmr/ctr0 + if wt_i = "00" and wt_en_i = '1' then + s_countl0 <= unsigned(reload_i); + else + if s_tmr_ctr0_en = '1' then + if s_count_enable = '1' then + if s_c_t0 = '0' then + if s_countl0 = conv_unsigned(31,8) then + s_countl0 <= conv_unsigned(0,8); + else + s_countl0 <= s_countl0 + conv_unsigned(1,1); + end if; + else + if s_ext_edge0 = '1' then + if s_countl0 = conv_unsigned(31,8) then + s_countl0 <= conv_unsigned(0,8); + else + s_countl0 <= s_countl0 + conv_unsigned(1,1); + end if; + end if; + end if; + end if; + end if; + end if; + + -- This section generates the high byte register of tmr/ctr0 + if wt_i = "10" and wt_en_i = '1' then + s_counth0 <= unsigned(reload_i); + else + if s_tmr_ctr0_en = '1' then + if s_count_enable = '1' then + if s_c_t0 = '0' then + if s_count0 = conv_unsigned(65311,16) then + s_counth0 <= conv_unsigned(0,8); + else + if s_countl0 = conv_unsigned(31,8) then + s_counth0 <= s_counth0 + conv_unsigned(1,1); + end if; + end if; + else + if s_ext_edge0 = '1' then + if s_count0 = conv_unsigned(65311,16) then + s_counth0 <= conv_unsigned(0,8); + else + if s_countl0 = conv_unsigned(31,8) then + s_counth0 <= s_counth0 + conv_unsigned(1,1); + end if; + end if; + end if; + end if; + end if; + end if; + end if; +------------------------------------------------------------------------------- +-- operating mode 1 (16 bit timer/counter) +------------------------------------------------------------------------------- + + when "01" => + + -- This section generates the timer/counter overflow flag0 + if s_tmr_ctr0_en = '1' then + if s_count_enable = '1' then + if s_c_t0 = '0' or (s_ext_edge0 = '1' and s_c_t0 = '1') then + if s_count0 = conv_unsigned(65535,16) then + s_tf0 <= '1'; + else + s_tf0 <= '0'; + end if; + end if; + end if; + end if; + + -- This section generates the low byte register of tmr/ctr0 + if wt_i = "00" and wt_en_i = '1' then + s_countl0 <= unsigned(reload_i); + else + if s_tmr_ctr0_en = '1' then + if s_count_enable = '1' then + if s_c_t0 = '0' then + if s_count0 = conv_unsigned(65535,16) then + s_countl0 <= conv_unsigned(0,8); + else + s_countl0 <= s_countl0 + conv_unsigned(1,1); + end if; + else + if s_ext_edge0 = '1' then + if s_count0 = conv_unsigned(65535,16) then + s_countl0 <= conv_unsigned(0,8); + else + s_countl0 <= s_countl0 + conv_unsigned(1,1); + end if; + end if; + end if; + end if; + end if; + end if; + + -- This section generates the high byte register of tmr/ctr0 + if wt_i = "10" and wt_en_i = '1' then + s_counth0 <= unsigned(reload_i); + else + if s_tmr_ctr0_en = '1' then + if s_count_enable = '1' then + if s_c_t0 = '0' then + if s_count0 = conv_unsigned(65535,16) then + s_counth0 <= conv_unsigned(0,8); + else + if s_countl0 = conv_unsigned(255,8) then + s_counth0 <= s_counth0 + conv_unsigned(1,1); + end if; + end if; + else + if s_ext_edge0 = '1' then + if s_count0 = conv_unsigned(65535,16) then + s_counth0 <= conv_unsigned(0,8); + else + if s_countl0 = conv_unsigned(255,8) then + s_counth0 <= s_counth0 + conv_unsigned(1,1); + end if; + end if; + end if; + end if; + end if; + end if; + end if; + + +------------------------------------------------------------------------------- +-- operating mode 2 (8 bit timer/counter, autoreloaded from high byte register) +------------------------------------------------------------------------------- + + when "10" => + + -- This section generates the timer/counter overflow flag0 + if s_tmr_ctr0_en = '1' then + if s_count_enable = '1' then + if s_c_t0 = '0' or (s_ext_edge0 = '1' and s_c_t0 = '1') then + if s_count0(7 downto 0) = conv_unsigned(255,16) then + s_tf0 <= '1'; + else + s_tf0 <= '0'; + end if; + end if; + end if; + end if; + + -- This section generates the low byte register of tmr/ctr0 + if wt_i = "00" and wt_en_i = '1' then + s_countl0 <= unsigned(reload_i); + else + if s_tmr_ctr0_en = '1' then + if s_count_enable = '1' then + if s_c_t0 = '0' then + if s_countl0 = conv_unsigned(255,8) then + s_countl0 <= s_counth0; + else + s_countl0 <= s_countl0 + conv_unsigned(1,1); + end if; + else + if s_ext_edge0 = '1' then + if s_countl0 = conv_unsigned(255,8) then + s_countl0 <= s_counth0; + else + s_countl0 <= s_countl0 + conv_unsigned(1,1); + end if; + end if; + end if; + end if; + end if; + end if; + + -- This section generates the high byte register of tmr/ctr0 + if wt_i = "10" and wt_en_i = '1' then + s_counth0 <= unsigned(reload_i); + end if; + +------------------------------------------------------------------------------- +-- operating mode 3 (One 8 bit timer/counter and one 8 bit timer) +------------------------------------------------------------------------------- + + when "11" => + + -- This section generates the timer/counter overflow flag0 + if s_tmr_ctr0_en = '1' then + if s_count_enable = '1' then + if s_c_t0 = '0' or (s_ext_edge0 = '1' and s_c_t0 = '1') then + if s_count0(7 downto 0) = conv_unsigned(255,16) then + s_tf0 <= '1'; + else + s_tf0 <= '0'; + end if; + end if; + end if; + end if; + + -- This section generates the low byte register of tmr/ctr0 + if wt_i = "00" and wt_en_i = '1' then + s_countl0 <= unsigned(reload_i); + else + if s_tmr_ctr0_en = '1' then + if s_count_enable = '1' then + if s_c_t0 = '0' then + if s_countl0 = conv_unsigned(255,8) then + s_countl0 <= conv_unsigned(0,8); + else + s_countl0 <= s_countl0 + conv_unsigned(1,1); + end if; + else + if s_ext_edge0 = '1' then + if s_countl0 = conv_unsigned(255,8) then + s_countl0 <= conv_unsigned(0,8); + else + s_countl0 <= s_countl0 + conv_unsigned(1,1); + end if; + end if; + end if; + end if; + end if; + end if; + + -- This section generates the timer/counter overflow flag1 + if tcon_tr1_i = '1' then + if s_count_enable = '1' then + if s_count0(15 downto 8) = conv_unsigned(255,8) then + s_tf1 <= '1'; + else + s_tf1 <= '0'; + end if; + end if; + end if; + + -- This section generates the high byte register of tmr/ctr0 + if wt_i = "10" and wt_en_i = '1' then + s_counth0 <= unsigned(reload_i); + else + if tcon_tr1_i = '1' then + if s_count_enable = '1' then + if s_counth0 = conv_unsigned(255,8) then + s_counth0 <= conv_unsigned(0,8); + else + s_counth0 <= s_counth0 + conv_unsigned(1,1); + end if; + end if; + end if; + end if; + + when others => null; + end case; + +------------------------------------------------------------------------------ +--+++++++++++++++++ END OF TIMER / COUNTER 0 +++++++++++++++++++++++++++-- +------------------------------------------------------------------------------ + + +------------------------------------------------------------------------------ +--+++++++++++++++++++++ TIMER / COUNTER 1 ++++++++++++++++++++++++++++++-- +------------------------------------------------------------------------------ +-- This is timer/counter1. It is built around the 16 bit count register +-- s_count1 and realises its four operating modes +------------------------------------------------------------------------------ + +------------------------------------------------------------------------------- +-- operating mode 0 (13 bit timer/counter) +------------------------------------------------------------------------------- + case s_mode1 is + when "00" => + + -- This section generates the timer/counter overflow flag1 + if s_tmr_ctr1_en = '1' then + if s_count_enable = '1' then + if s_mode0 = conv_unsigned(1,2) or + s_mode0 = conv_unsigned(0,2) or + s_mode0 = conv_unsigned(2,2) then + if s_c_t1 = '0' or (s_ext_edge1 = '1' and s_c_t1 = '1') then + if s_count1 = conv_unsigned(65311,16) then + s_tf1 <= '1'; + else + s_tf1 <= '0'; + end if; + end if; + else + null; + end if; + end if; + end if; + + -- This section generates the low byte register of tmr/ctr1 + if wt_i = "01" and wt_en_i = '1' then + s_countl1 <= unsigned(reload_i); + else + if s_tmr_ctr1_en = '1' then + if s_count_enable = '1' then + if s_c_t1 = '0' then + if s_countl1 = conv_unsigned(31,8) then + s_countl1 <= conv_unsigned(0,8); + else + s_countl1 <= s_countl1 + conv_unsigned(1,1); + end if; + else + if s_ext_edge1 = '1' then + if s_countl1 = conv_unsigned(31,8) then + s_countl1 <= conv_unsigned(0,8); + else + s_countl1 <= s_countl1 + conv_unsigned(1,1); + end if; + end if; + end if; + end if; + end if; + end if; + + -- This section generates the high byte register of tmr/ctr1 + if wt_i = "11" and wt_en_i = '1' then + s_counth1 <= unsigned(reload_i); + else + if s_tmr_ctr1_en = '1' then + if s_count_enable = '1' then + if s_c_t1 = '0' then + if s_count1 = conv_unsigned(65311,16) then + s_counth1 <= conv_unsigned(0,8); + else + if s_countl1 = conv_unsigned(31,8) then + s_counth1 <= s_counth1 + conv_unsigned(1,1); + end if; + end if; + else + if s_ext_edge1 = '1' then + if s_count1 = conv_unsigned(65311,16) then + s_counth1 <= conv_unsigned(0,8); + else + if s_countl1 = conv_unsigned(31,8) then + s_counth1 <= s_counth1 + conv_unsigned(1,1); + end if; + end if; + end if; + end if; + end if; + end if; + end if; +------------------------------------------------------------------------------- +-- operating mode 1 (16 bit timer/counter) +------------------------------------------------------------------------------- + + when "01" => + + -- This section generates the timer/counter overflow flag1 + if s_tmr_ctr1_en = '1' then + if s_count_enable = '1' then + if s_mode0 = conv_unsigned(1,2) or + s_mode0 = conv_unsigned(0,2) or + s_mode0 = conv_unsigned(2,2) then + if s_c_t1 = '0' or (s_ext_edge1 = '1' and s_c_t1 = '1') then + if s_count1 = conv_unsigned(65535,16) then + s_tf1 <= '1'; + else + s_tf1 <= '0'; + end if; + end if; + else + null; + end if; + end if; + end if; + + -- This section generates the low byte register of tmr/ctr1 + if wt_i = "01" and wt_en_i = '1' then + s_countl1 <= unsigned(reload_i); + else + if s_tmr_ctr1_en = '1' then + if s_count_enable = '1' then + if s_c_t1 = '0' then + if s_count1 = conv_unsigned(65535,16) then + s_countl1 <= conv_unsigned(0,8); + else + s_countl1 <= s_countl1 + conv_unsigned(1,1); + end if; + else + if s_ext_edge1 = '1' then + if s_count1 = conv_unsigned(65535,16) then + s_countl1 <= conv_unsigned(0,8); + else + s_countl1 <= s_countl1 + conv_unsigned(1,1); + end if; + end if; + end if; + end if; + end if; + end if; + + -- This section generates the high byte register of tmr/ctr1 + if wt_i = "11" and wt_en_i = '1' then + s_counth1 <= unsigned(reload_i); + else + if s_tmr_ctr1_en = '1' then + if s_count_enable = '1' then + if s_c_t1 = '0' then + if s_count1 = conv_unsigned(65535,16) then + s_counth1 <= conv_unsigned(0,8); + else + if s_countl1 = conv_unsigned(255,8) then + s_counth1 <= s_counth1 + conv_unsigned(1,1); + end if; + end if; + else + if s_ext_edge1 = '1' then + if s_count1 = conv_unsigned(65535,16) then + s_counth1 <= conv_unsigned(0,8); + else + if s_countl1 = conv_unsigned(255,8) then + s_counth1 <= s_counth1 + conv_unsigned(1,1); + end if; + end if; + end if; + end if; + end if; + end if; + end if; + +------------------------------------------------------------------------------- +-- operating mode 2 (8 bit timer/counter, auto reloaded) +------------------------------------------------------------------------------- + + when "10" => + + -- This section generates the timer/counter overflow flag1 + if s_tmr_ctr1_en = '1' then + if s_count_enable = '1' then + if s_mode0 = conv_unsigned(1,2) or + s_mode0 = conv_unsigned(0,2) or + s_mode0 = conv_unsigned(2,2) then + if s_c_t1 = '0' or (s_ext_edge1 = '1' and s_c_t1 = '1') then + if s_count1(7 downto 0) = conv_unsigned(255,16) then + s_tf1 <= '1'; + else + s_tf1 <= '0'; + end if; + end if; + else + null; + end if; + end if; + end if; + + -- This section generates the low byte register of tmr/ctr1 + if wt_i = "01" and wt_en_i = '1' then + s_countl1 <= unsigned(reload_i); + else + if s_tmr_ctr1_en = '1' then + if s_count_enable = '1' then + if s_c_t1 = '0' then + if s_countl1 = conv_unsigned(255,8) then + s_countl1 <= s_counth1; + else + s_countl1 <= s_countl1 + conv_unsigned(1,1); + end if; + else + if s_ext_edge1 = '1' then + if s_countl1 = conv_unsigned(255,8) then + s_countl1 <= s_counth1; + else + s_countl1 <= s_countl1 + conv_unsigned(1,1); + end if; + end if; + end if; + end if; + end if; + end if; + + -- This section generates the high byte register of tmr/ctr1 + if wt_i = "11" and wt_en_i = '1' then + s_counth1 <= unsigned(reload_i); + end if; + +------------------------------------------------------------------------------- +-- operating mode 3 (One 8 bit timer/counter and one 8 bit timer) +------------------------------------------------------------------------------- + + when "11" => + + -- This section generates the low byte register of tmr/ctr1 + if wt_i = "01" and wt_en_i = '1' then + s_countl1 <= unsigned(reload_i); + end if; + + -- This section generates the high byte register of tmr/ctr1 + if wt_i = "11" and wt_en_i = '1' then + s_counth1 <= unsigned(reload_i); + end if; + + when others => null; + end case; +------------------------------------------------------------------------------ +--+++++++++++++++++ END OF TIMER / COUNTER 1 +++++++++++++++++++++++++++-- +------------------------------------------------------------------------------ + + end if; + end if; + + end process p_tmr_ctr; + + +end rtl; + diff --git a/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/8051/mc8051_tmrctr_rtl_cfg.vhd b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/8051/mc8051_tmrctr_rtl_cfg.vhd new file mode 100644 index 0000000000000000000000000000000000000000..2c3d84271f433c282cedf56fc421c18d11b99693 --- /dev/null +++ b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/8051/mc8051_tmrctr_rtl_cfg.vhd @@ -0,0 +1,71 @@ +------------------------------------------------------------------------------- +-- -- +-- X X XXXXXX XXXXXX XXXXXX XXXXXX X -- +-- XX XX X X X X X X X XX -- +-- X X X X X X X X X X X X -- +-- X X X X X X X X X X X X -- +-- X X X X XXXXXX X X XXXXXX X -- +-- X X X X X X X X X -- +-- X X X X X X X X X -- +-- X X X X X X X X X X -- +-- X X XXXXXX XXXXXX XXXXXX XXXXXX X -- +-- -- +-- -- +-- O R E G A N O S Y S T E M S -- +-- -- +-- Design & Consulting -- +-- -- +------------------------------------------------------------------------------- +-- -- +-- Web: http://www.oregano.at/ -- +-- -- +-- Contact: mc8051@oregano.at -- +-- -- +------------------------------------------------------------------------------- +-- -- +-- MC8051 - VHDL 8051 Microcontroller IP Core -- +-- Copyright (C) 2001 OREGANO SYSTEMS -- +-- -- +-- This library is free software; you can redistribute it and/or -- +-- modify it under the terms of the GNU Lesser General Public -- +-- License as published by the Free Software Foundation; either -- +-- version 2.1 of the License, or (at your option) any later version. -- +-- -- +-- This library is distributed in the hope that it will be useful, -- +-- but WITHOUT ANY WARRANTY; without even the implied warranty of -- +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -- +-- Lesser General Public License for more details. -- +-- -- +-- Full details of the license can be found in the file LGPL.TXT. -- +-- -- +-- You should have received a copy of the GNU Lesser General Public -- +-- License along with this library; if not, write to the Free Software -- +-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -- +-- -- +------------------------------------------------------------------------------- +-- +-- +-- Author: Roland Hller +-- +-- Filename: mc8051_tmrctr_rtl_cfg.vhd +-- +-- Date of Creation: Mon Aug 9 12:14:48 1999 +-- +-- Version: $Revision: 1.4 $ +-- +-- Date of Latest Version: $Date: 2002-01-07 12:17:45 $ +-- +-- +-- Description: Timer/Counter unit of the mc8051 microcontroller. +-- +-- +-- +-- +------------------------------------------------------------------------------- +configuration mc8051_tmrctr_rtl_cfg of mc8051_tmrctr is + + for rtl + + end for; + +end mc8051_tmrctr_rtl_cfg; diff --git a/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/j68/cpu_j68.v b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/j68/cpu_j68.v new file mode 100644 index 0000000000000000000000000000000000000000..81a51fbabb82668387ff65ec7dbcdf21dfff01c4 --- /dev/null +++ b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/j68/cpu_j68.v @@ -0,0 +1,744 @@ +// Copyright 2011-2018 Frederic Requin +// +// The J68 core: +// ------------- +// Simple re-implementation of the MC68000 CPU +// The core has the following characteristics: +// - Tested on a Cyclone III (90 MHz) and a Stratix II (180 MHz) +// - from 1500 (~70 MHz) to 1900 LEs (~90 MHz) on Cyclone III +// - 2048 x 20-bit microcode ROM +// - 256 x 28-bit decode ROM +// - 2 x block RAM for the data and instruction stacks +// - stack based CPU with forth-like microcode +// - not cycle-exact : needs a frequency ~3 x higher +// - all 68000 instructions are implemented +// - almost all 68000 exceptions are implemented (only bus error missing) +// - only auto-vector interrupts supported + +module cpu_j68 +( + // Clock and reset + input rst, // CPU reset + input clk, // CPU clock + /* direct_enable = 1 */ input clk_ena, // CPU clock enable + // Bus interface + output rd_ena, // Read strobe + output wr_ena, // Write strobe + input data_ack, // Data acknowledge + output [1:0] byte_ena, // Byte enable + output [31:0] address, // Address bus + input [15:0] rd_data, // Data bus in + output [15:0] wr_data, // Data bus out + // 68000 control + output [2:0] fc, // Function code + input [2:0] ipl_n, // Interrupt level + // 68000 debug + output [3:0] dbg_reg_addr, // Register address + output [3:0] dbg_reg_wren, // Register write enable + output [15:0] dbg_reg_data, // Register write data + output [15:0] dbg_sr_reg, // Status register + output [31:0] dbg_pc_reg, // Program counter + output [31:0] dbg_usp_reg, // User stack pointer + output [31:0] dbg_ssp_reg, // Supervisor stack pointer + output [31:0] dbg_vbr_reg, // Vector base register + output [31:0] dbg_cycles, // Cycles counter + output dbg_ifetch, // Instruction fetch + output [2:0] dbg_irq_lvl // Interrupt level +); + parameter USE_CLK_ENA = 0; + + // ALU operations + localparam [4:0] + ALU_ADD = 5'b00000, + ALU_ADDC = 5'b00001, + ALU_SUB = 5'b00010, + ALU_SUBC = 5'b00011, + ALU_AND = 5'b00100, + ALU_BAND = 5'b10100, + ALU_OR = 5'b00101, + ALU_BOR = 5'b10101, + ALU_XOR = 5'b00110, + ALU_BXOR = 5'b10110, + ALU_NOT = 5'b00111, + ALU_BNOT = 5'b10111, + ALU_SHL = 5'b01000, + ALU_SHR = 5'b01100, + ALU_DIV = 5'b01110, + ALU_MUL = 5'b01111; + + // ALU inputs + localparam [1:0] + A_ADD_ZERO = 2'b00, + A_ADD_T = 2'b10, + A_ADD_NOT_T = 2'b11, + B_ADD_ZERO = 2'b00, + B_ADD_N = 2'b10, + B_ADD_NOT_N = 2'b11, + A_LOG_ZERO = 2'b00, + A_LOG_IMM = 2'b01, + A_LOG_T = 2'b10, + A_LOG_RAM = 2'b11, + B_LOG_ZERO = 2'b00, + B_LOG_IO = 2'b01, + B_LOG_N = 2'b10, + B_LOG_NOT_N = 2'b11; + + reg r_rst_dly; // Delayed reset signal + + wire [19:0] w_inst_in; // Internal RAM instruction read + wire w_ram_rd; // Internal RAM read + reg r_ram_rd; // Internal RAM read (delayed) + wire w_ram_wr; // Internal RAM write + wire [1:0] w_ram_bena; // Internal RAM byte enable + wire [10:0] w_ram_addr; // Internal RAM address + wire [15:0] w_ram_din; // Internal RAM data write + wire [15:0] w_ram_dout; // Internal RAM data read + wire w_ram_rdy; // RAM data ready + + wire w_reg_wr; // CPU register write + wire [1:0] w_reg_bena; // CPU register byte enable + wire [10:0] w_reg_addr; // CPU register address + + reg [11:0] w_alu_c; // ALU control (wire) + reg [10:0] w_flg_c; // Flags control (wire) + reg [3:0] w_cin_c; // Carry in control (wire) + + reg [3:0] r_ds_ptr; // Data stack pointer (reg) + reg [3:0] w_ds_nxt; // Next data stack pointer (wire) + wire [3:0] w_ds_inc; // Data stack pointer increment (wire) + reg [15:0] r_ds[0:15]; // Data stack (regs) + reg [15:0] r_ds_T; // Data stack output T (reg) + wire [15:0] w_ds_N; // Data stack output N (wire) + wire [31:0] w_ds_R; // Data stack input : ALU result (wire) + reg w_ds_wr; // Data stack write enable (wire) + + wire w_ifetch; // Fetch next instruction + wire [10:0] w_pc_inc; // PC value incremented by 1 (wire) + reg [10:0] r_pc_reg; // PC register (reg) + reg [10:0] w_pc_nxt; // Next PC value (wire) + wire [10:0] w_pc_loop; // PC value for loop (wire) + + reg [3:0] r_rs_ptr; // Return stack pointer (reg) + reg [3:0] w_rs_nxt; // Next return stack pointer (wire) + reg [10:0] r_rs[0:15]; // Return stack (regs) + wire [10:0] w_rs_q; // Return stack output (wire) + reg [10:0] w_rs_d; // Return stack input (wire) + reg w_rs_wr; // Return stack write enable (wire) + reg w_rs_rd; // Return stack read enable (wire) + + // Micro-instruction decode + wire w_io_op = (w_inst_in[19:17] == 3'b100) ? 1'b1 : 1'b0; + wire w_reg_op = (w_inst_in[19:17] == 3'b101) ? 1'b1 : 1'b0; + wire w_t_mode = (w_inst_in[15:12] == 4'b1111) ? 1'b1 : 1'b0; + wire w_branch; + wire [3:0] w_loop_cnt; + wire w_loop; + wire w_skip; + + // ALU <-> Flags + wire [31:0] w_res; + wire [3:0] w_alu; + wire [1:0] w_size; + wire [4:0] w_c_flg; + wire [5:0] w_v_flg; + wire [10:0] w_sr; + wire [4:0] w_ccr; + wire w_c_in; + wire w_z_flg; + wire w_g_flg; + + // Memory access + wire w_io_rd; // I/O register read + wire w_io_wr; // I/O register write + wire w_io_ext; // External memory access + wire w_io_rdy; // I/O data ready + wire w_io_end; // End of I/O cycle + wire [15:0] w_io_din; // I/O data input + wire [10:0] w_io_flg_c; // Flag control (for SR write) + + // M68k instruction decoder + wire [15:0] w_insw; // Instruction word + wire [15:0] w_extw; // Extension word + wire [15:0] w_ea1b; // Effective address #1 bitfield + + // Debug + reg [31:0] r_usp_reg; + reg [31:0] r_ssp_reg; + reg [31:0] r_cycles; + reg r_go_super; + reg [2:0] r_irq_lvl; + wire w_super_st; + + // Delayed reset + always@(posedge clk) begin : RESET_DLY + if (clk_ena) r_rst_dly <= rst; + end + + // RAM access + assign w_ram_rd = w_reg_op & w_inst_in[7] & ~w_ram_rdy; + assign w_ram_addr = w_reg_addr; + assign w_ram_bena = w_reg_bena & { w_reg_wr, w_reg_wr }; + assign w_ram_din = r_ds_T; + assign w_ram_rdy = (w_reg_op & w_inst_in[6]) | r_ram_rd; + + always@(posedge clk) begin : RAM_READ + if (clk_ena) r_ram_rd <= w_ram_rd; + end + + // Debug + assign dbg_reg_addr = (w_reg_wr) ? w_reg_addr[4:1] : 4'b0000; + assign dbg_reg_wren[3] = w_reg_wr & w_reg_addr[5] & w_reg_addr[0] & w_reg_bena[1]; + assign dbg_reg_wren[2] = w_reg_wr & w_reg_addr[5] & w_reg_addr[0] & w_reg_bena[0]; + assign dbg_reg_wren[1] = w_reg_wr & w_reg_addr[5] & ~w_reg_addr[0] & w_reg_bena[1]; + assign dbg_reg_wren[0] = w_reg_wr & w_reg_addr[5] & ~w_reg_addr[0] & w_reg_bena[0]; + assign dbg_reg_data = (w_reg_wr) ? r_ds_T : 16'h0000; + assign dbg_sr_reg = { (w_sr & 11'b1010_0111_000) , w_ccr}; + assign dbg_usp_reg = r_usp_reg; + assign dbg_ssp_reg = r_ssp_reg; + assign dbg_vbr_reg = 32'h00000000; + assign dbg_cycles = r_cycles; + assign dbg_irq_lvl = r_irq_lvl; + assign w_super_st = w_sr[8] | r_go_super; + + always @(posedge rst or posedge clk) begin : CPU_DEBUG + + if (rst) begin + r_usp_reg <= 32'd0; + r_ssp_reg <= 32'd0; + r_cycles <= 32'd0; + r_go_super <= 1'b0; + r_irq_lvl <= 3'd0; + end + else if (clk_ena) begin + // Stack pointers access + if (w_reg_wr) begin + // USP low word + if ((w_reg_addr[5:0] == 6'b011100) || + ((w_reg_addr[5:0] == 6'b111110) && (!w_super_st))) begin + r_usp_reg[15:0] <= r_ds_T; + end + // USP high word + if ((w_reg_addr[5:0] == 6'b011101) || + ((w_reg_addr[5:0] == 6'b111111) && (!w_super_st))) begin + r_usp_reg[31:16] <= r_ds_T; + end + // SSP low word + if ((w_reg_addr[5:0] == 6'b011110) || + ((w_reg_addr[5:0] == 6'b111110) && (w_super_st))) begin + r_ssp_reg[15:0] <= r_ds_T; + end + // SSP high word + if ((w_reg_addr[5:0] == 6'b011111) || + ((w_reg_addr[5:0] == 6'b111111) && (w_super_st))) begin + r_ssp_reg[31:16] <= r_ds_T; + end + end + + // Number of cycles + r_cycles <= r_cycles + 32'd1; + + if (USE_CLK_ENA == 1) begin + // We will enter supervisor state + if (w_sr[8]) begin + r_go_super <= 1'b0; + end + else if ((r_pc_reg >= 11'h014) && (r_pc_reg <= 11'h044)) begin + r_go_super <= 1'b1; + end + + // Interrupt acknowledge + if (r_pc_reg == 11'h016) begin + r_irq_lvl <= ~ipl_n; + end + // Interrupt clear + else if (ipl_n == 3'b111) begin + r_irq_lvl <= 3'd0; + end + end + else begin + // We will enter supervisor state + if (w_sr[8]) begin + r_go_super <= 1'b0; + end + else if ((r_pc_reg >= 11'h015) && (r_pc_reg <= 11'h045)) begin + r_go_super <= 1'b1; + end + + // Interrupt acknowledge + if (r_pc_reg == 11'h017) begin + r_irq_lvl <= ~ipl_n; + end + // Interrupt clear + else if (ipl_n == 3'b111) begin + r_irq_lvl <= 3'd0; + end + end + end + end + + // I/O access + assign w_io_wr = ~w_inst_in[8] & w_inst_in[6] & w_io_op; + assign w_io_rd = ~w_inst_in[8] & w_inst_in[7] & w_io_op & ~w_io_rdy; + assign w_io_ext = w_inst_in[8] & w_io_op & ~w_io_rdy; + assign w_io_end = w_io_rdy | w_io_wr; + + + // PC calculation + assign w_pc_inc = r_pc_reg + 11'd1; + + always @(*) begin : PC_CALC + + if (rst) begin + w_pc_nxt = 11'h000; + end + else begin + case (w_inst_in[19:17]) + // LOOP instruction + 3'b000 : begin + if (w_skip) begin + // Null loop count + w_pc_nxt = w_inst_in[10:0]; + end + else begin + // First instruction of the loop + w_pc_nxt = w_pc_inc; + end + end + // JUMP/CALL instruction + 3'b001 : begin + if (w_branch) begin + // Branch taken + w_pc_nxt = w_inst_in[10:0] | (r_ds_T[10:0] & {11{w_t_mode}}); + end + else begin + // Branch not taken + w_pc_nxt = w_pc_inc; + end + end + // Rest of instruction + default : begin + if (w_inst_in[16]) begin + // With RTS + w_pc_nxt = w_rs_q; + end + else begin + if (w_loop) begin + // Jump to start of loop + w_pc_nxt = w_pc_loop; + end + else begin + // Following instruction + w_pc_nxt = w_pc_inc; + end + end + end + endcase + end + end + + assign w_ifetch = ((w_io_end | w_ram_rdy | (~w_io_op & ~w_reg_op) | r_rst_dly) & ~rst); + + always @(posedge rst or posedge clk) begin : PC_REG + + if (rst) begin + r_pc_reg <= 11'h7FF; + end + else if (clk_ena) begin + if (w_ifetch) r_pc_reg <= w_pc_nxt; + end + end + + + // Return stack pointer calculation + always @(*) begin : RS_PTR_CALC + + if (w_inst_in[19:17] == 3'b001) begin + if (w_inst_in[16]) begin + // "JUMP" instruction + w_rs_nxt = r_rs_ptr; + w_rs_d = r_pc_reg; + w_rs_wr = 1'b0; + w_rs_rd = 1'b0; + end + else begin + // "CALL" instruction + w_rs_nxt = r_rs_ptr - 4'd1; + w_rs_d = w_pc_inc; + w_rs_wr = 1'b1; + w_rs_rd = 1'b0; + end + end + else begin + if ((w_inst_in[16]) && (w_ifetch)) begin + // Embedded "RTS" + w_rs_nxt = r_rs_ptr + 4'd1; + w_rs_d = r_pc_reg; + w_rs_wr = 1'b0; + w_rs_rd = 1'b1; + end + else begin + // No "RTS" + w_rs_nxt = r_rs_ptr; + w_rs_d = r_pc_reg; + w_rs_wr = 1'b0; + w_rs_rd = 1'b0; + end + end + end + + // Return stack + always @(posedge rst or posedge clk) begin : RS_PTR_REG + + if (rst) begin + r_rs_ptr <= 4'd0; + end + else if (clk_ena) begin + // Latch the return stack pointer + r_rs_ptr <= w_rs_nxt; + if (w_rs_wr) r_rs[w_rs_nxt] <= w_rs_d; + end + end + // Return stack output value + assign w_rs_q = r_rs[r_rs_ptr]; + + assign w_ds_inc = {{3{w_inst_in[13]}}, w_inst_in[12]}; + + // ALU parameters and data stack update + always@(*) begin : ALU_DS_PTR_CALC + + case(w_inst_in[19:17]) + // LOOP + 3'b000 : begin + // Generate a "DROP" or a "NOP" + w_alu_c[11:10] = 2'b01; // Operand size + w_alu_c[9] = 1'b0; // CCR update + w_alu_c[8:4] = ALU_OR; // ALU operation + // Data stack update if "LOOP T" + if (w_inst_in[11]) begin + // DROP + w_alu_c[3:2] = A_LOG_ZERO; // A = 0x0000 + w_alu_c[1:0] = B_LOG_N; // B = Next on stack + w_ds_nxt = r_ds_ptr - 4'd1; + end + else begin + // NOP + w_alu_c[3:2] = A_LOG_T; // A = Top of stack + w_alu_c[1:0] = B_LOG_ZERO; // B = 0x0000 + w_ds_nxt = r_ds_ptr; + end + w_ds_wr = 1'b0; + end + // CALL, JUMP + 3'b001 : begin + // Generate a "DROP" or a "NOP" + w_alu_c[11:10] = 2'b01; // Operand size + w_alu_c[9] = 1'b0; // CCR update + w_alu_c[8:4] = ALU_OR; // ALU operation + // Data stack update if "JUMP (T)" or "CALL (T)" + if (w_t_mode) begin + // DROP + w_alu_c[3:2] = A_LOG_ZERO; // A = 0x0000 + w_alu_c[1:0] = B_LOG_N; // B = Next on stack + w_ds_nxt = r_ds_ptr - 4'd1; + end + else begin + // NOP + w_alu_c[3:2] = A_LOG_T; // A = Top of stack + w_alu_c[1:0] = B_LOG_ZERO; // B = 0x0000 + w_ds_nxt = r_ds_ptr; + end + w_ds_wr = 1'b0; + end + // LIT + 3'b010 : begin + w_alu_c[11:10] = 2'b01; // Operand size + w_alu_c[9] = 1'b0; // CCR update + w_alu_c[8:4] = ALU_OR; // ALU operation + w_alu_c[3:2] = A_LOG_IMM; // A = Immediate value + w_alu_c[1:0] = B_LOG_ZERO; // B = 0x0000 + // Data stack update + w_ds_nxt = r_ds_ptr + 4'd1; + w_ds_wr = 1'b1; + end + // FLAG + 3'b011 : begin + // Generate a "NOP" + w_alu_c[11:10] = 2'b01; // Operand size + w_alu_c[9] = 1'b0; // CCR update + w_alu_c[8:4] = ALU_OR; // ALU operation + w_alu_c[3:2] = A_LOG_T; // A = Top of stack + w_alu_c[1:0] = B_LOG_ZERO; // B = 0x0000 + // No data stack update + w_ds_nxt = r_ds_ptr; + w_ds_wr = 1'b0; + end + // I/O reg. access + 3'b100 : begin + w_alu_c[11:10] = 2'b01; // Operand size + w_alu_c[9] = w_inst_in[9]; // CCR update + w_alu_c[8:4] = ALU_OR; // ALU operation + if (w_inst_in[7]) begin + if (w_ds_inc[0]) begin + // I/O register load + w_alu_c[3:2] = A_LOG_ZERO; // A = 0x0000 + w_alu_c[1:0] = B_LOG_IO; // B = I/O data + end + else begin + // I/O register fetch + w_alu_c[3:2] = A_LOG_T; // A = Top of stack + w_alu_c[1:0] = B_LOG_ZERO; // B = 0x0000 + end + end + else begin + if (w_ds_inc[0]) begin + // I/O register store + w_alu_c[3:2] = A_LOG_ZERO; // A = 0x0000 + w_alu_c[1:0] = B_LOG_N; // B = Next on stack + end + else begin + // I/O register write + w_alu_c[3:2] = A_LOG_T; // A = Top of stack + w_alu_c[1:0] = B_LOG_ZERO; // B = 0x0000 + end + end + // Data stack update + w_ds_nxt = r_ds_ptr + w_ds_inc; + w_ds_wr = w_inst_in[14]; + end + // M68k reg. access + 3'b101 : begin + w_alu_c[11:10] = 2'b01; // Operand size + w_alu_c[9] = w_inst_in[9]; // CCR update + w_alu_c[8:4] = ALU_OR; // ALU operation + if (w_inst_in[7]) begin + // M68k register load + w_alu_c[3:2] = A_LOG_RAM; // A = RAM data + w_alu_c[1:0] = B_LOG_ZERO; // B = 0x0000 + end + else begin + if (w_ds_inc[0]) begin + // M68k register store + w_alu_c[3:2] = A_LOG_ZERO; // A = 0x0000 + w_alu_c[1:0] = B_LOG_N; // B = Next on stack + end + else begin + // M68k register write + w_alu_c[3:2] = A_LOG_T; // A = Top of stack + w_alu_c[1:0] = B_LOG_ZERO; // B = 0x0000 + end + end + // Data stack update + w_ds_nxt = r_ds_ptr + w_ds_inc; + w_ds_wr = w_inst_in[14]; + end + // ALU operation + 3'b110 : begin + w_alu_c[11:10] = w_inst_in[11:10]; // Operand size + w_alu_c[9] = w_inst_in[9]; // CCR update + w_alu_c[8:4] = w_inst_in[8:4]; // ALU operation + w_alu_c[3:2] = w_inst_in[3:2]; // A source + w_alu_c[1:0] = w_inst_in[1:0]; // B source + // Data stack update + w_ds_nxt = r_ds_ptr + w_ds_inc; + w_ds_wr = w_inst_in[14]; + end + default : begin + // Generate a "NOP" + w_alu_c[11:10] = 2'b01; // Operand size + w_alu_c[9] = 1'b0; // CCR update + w_alu_c[8:4] = ALU_OR; // ALU operation + w_alu_c[3:2] = A_LOG_T; // A = Top of stack + w_alu_c[1:0] = B_LOG_ZERO; // B = 0x0000 + // No data stack update + w_ds_nxt = r_ds_ptr; + w_ds_wr = 1'b0; + end + endcase + end + + // Data stack + always @(posedge rst or posedge clk) begin : DS_PTR_REG + + if (rst) begin + r_ds_ptr <= 4'd0; + r_ds_T <= 16'h0000; + end + else if (clk_ena) begin + if ((w_io_end) || (w_ram_rdy) || (!(w_io_op | w_reg_op))) begin + // Latch the data stack pointer + r_ds_ptr <= w_ds_nxt; + // Latch the data stack value T + r_ds_T <= w_ds_R[15:0]; + // Latch the data stack value N + if (w_ds_wr) r_ds[w_ds_nxt] <= w_ds_R[31:16]; + end + end + end + // Data stack output value #1 (N) + assign w_ds_N = r_ds[r_ds_ptr]; + + + // Flags control + always@(*) begin : FLAGS_CTRL + + if (w_inst_in[19:17] == 3'b011) begin + // Update flags + w_flg_c = w_inst_in[10:0]; + w_cin_c = w_inst_in[14:11]; + end + else begin + // Keep flags + w_flg_c = w_io_flg_c; + w_cin_c = 4'b0000; + end + end + + + // 16/32-bit ALU + j68_alu U_alu + ( + .rst (rst), + .clk (clk), + .clk_ena (clk_ena), + .size (w_alu_c[11:10]), + .cc_upd (w_alu_c[9]), + .alu_c (w_alu_c[8:4]), + .a_ctl (w_alu_c[3:2]), + .b_ctl (w_alu_c[1:0]), + .c_in (w_c_in), + .v_in (w_ccr[1]), + .a_src (r_ds_T), + .b_src (w_ds_N), + .ram_in (w_ram_dout), + .io_in (w_io_din), + .imm_in (w_inst_in[15:0]), + .result (w_ds_R), + .c_flg (w_c_flg), + .v_flg (w_v_flg[4:0]), + .l_res (w_res), + .l_alu (w_alu), + .l_size (w_size) + ); + + + // Flags update + j68_flags U_flags + ( + .rst (rst), + .clk (clk), + .clk_ena (clk_ena), + .c_flg (w_c_flg), + .v_flg (w_v_flg), + .l_res (w_res), + .l_alu (w_alu), + .l_size (w_size), + .a_src (r_ds_T), + .b_src (w_ds_N), + .flg_c (w_flg_c), + .cin_c (w_cin_c), + .cc_out (w_ccr), + .c_in (w_c_in), + .z_flg (w_z_flg), + .g_flg (w_g_flg) + ); + + + // Conditional Jump/Call + j68_test U_test + ( + .inst_in (w_inst_in), + .flg_in ({w_g_flg, w_res[15], w_z_flg, w_c_flg[1]}), + .sr_in ({w_sr, w_ccr}), + .a_src (r_ds_T), + .ea1b (w_ea1b), + .extw (w_extw), + .branch (w_branch) + ); + + + // Hardware loop + j68_loop U_loop + ( + .rst (rst), + .clk (clk), + .clk_ena (clk_ena), + .inst_in (w_inst_in), + .i_fetch (w_ifetch), + .a_src (r_ds_T[5:0]), + .pc_in (w_pc_nxt), + .pc_out (w_pc_loop), + .branch (w_loop), + .skip (w_skip), + .lcount (w_loop_cnt) + ); + + + // Bus interface + j68_mem_io + #( + .USE_CLK_ENA (USE_CLK_ENA) + ) + U_mem_io + ( + .rst (rst), + .clk (clk), + .clk_ena (clk_ena), + .rd_ena (rd_ena), + .wr_ena (wr_ena), + .data_ack (data_ack), + .byte_ena (byte_ena), + .address (address), + .rd_data (rd_data), + .wr_data (wr_data), + .fc (fc), + .ipl_n (ipl_n), + .io_rd (w_io_rd), + .io_wr (w_io_wr), + .io_ext (w_io_ext), + .io_reg (w_reg_op), + .io_rdy (w_io_rdy), + .io_din (w_io_din), + .io_dout (r_ds_T), + .inst_in (w_inst_in), + .cc_upd (w_alu_c[9]), + .alu_op (w_alu_c[7:4]), + .a_src (r_ds_T), + .b_src (w_ds_N), + .v_flg (w_v_flg[5]), + .insw (w_insw), + .extw (w_extw), + .ea1b (w_ea1b), + .ccr_in (w_ccr), + .sr_out (w_sr), + .flg_c (w_io_flg_c), + .loop_cnt (w_loop_cnt), + .reg_addr (w_reg_addr[5:0]), + .reg_wr (w_reg_wr), + .reg_bena (w_reg_bena), + .dbg_pc (dbg_pc_reg), + .dbg_if (dbg_ifetch) + ); + assign w_reg_addr[10:6] = 5'b11111; + + // Microcode ROM : 2048 x 20-bit + j68_dpram_2048x20 + #( + .RAM_INIT_FILE ((USE_CLK_ENA) ? "j68_ram_c.mem" : "j68_ram.mem") + ) + U_j68_dpram_2048x20 + ( + // Reset and clock + .clock (clk), + .clocken (clk_ena), + // Port A : micro-instruction fetch + .rden_a (w_ifetch), + .address_a (w_pc_nxt), + .q_a (w_inst_in), + // Port B : m68k registers read/write + .wren_b (w_ram_bena), + .address_b (w_ram_addr), + .data_b (w_ram_din), + .q_b (w_ram_dout) + ); + +endmodule diff --git a/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/j68/j68_addsub_32.v b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/j68/j68_addsub_32.v new file mode 100644 index 0000000000000000000000000000000000000000..445906a1015b6f1c84caea64a04708332ec30c47 --- /dev/null +++ b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/j68/j68_addsub_32.v @@ -0,0 +1,70 @@ +// Copyright 2011-2018 Frederic Requin +// +// This file is part of the MCC216 project +// +// The J68 core: +// ------------- +// Simple re-implementation of the MC68000 CPU +// The core has the following characteristics: +// - Tested on a Cyclone III (90 MHz) and a Stratix II (180 MHz) +// - from 1500 (~70 MHz) to 1900 LEs (~90 MHz) on Cyclone III +// - 2048 x 20-bit microcode ROM +// - 256 x 28-bit decode ROM +// - 2 x block RAM for the data and instruction stacks +// - stack based CPU with forth-like microcode +// - not cycle-exact : needs a frequency ~3 x higher +// - all 68000 instructions are implemented +// - almost all 68000 exceptions are implemented (only bus error missing) +// - only auto-vector interrupts supported + +module j68_addsub_32 +( + input add_sub, + input [31:0] dataa, + input [31:0] datab, + output cout, + output [31:0] result +); + +//`ifdef verilator3 + + // Testbench + wire [32:0] w_result; + + assign w_result = (add_sub) ? { 1'b0, dataa } + { 1'b0, datab } + : { 1'b0, dataa } - { 1'b0, datab }; + + assign cout = ~w_result[32]; + assign result = w_result[31:0]; +/* +`else + + // Synthesis + lpm_add_sub + #( + .lpm_direction ("UNUSED"), + .lpm_hint ("ONE_INPUT_IS_CONSTANT=NO,CIN_USED=NO"), + .lpm_representation ("UNSIGNED"), + .lpm_type ("LPM_ADD_SUB"), + .lpm_width (32) + ) + lpm_add_sub_32 + ( + .add_sub (add_sub), + .dataa (dataa), + .datab (datab), + .cout (cout), + .result (result) + // synopsys translate_off + , + .aclr (), + .cin (), + .clken (), + .clock (), + .overflow () + // synopsys translate_on + ); + +`endif +*/ +endmodule diff --git a/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/j68/j68_alu.v b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/j68/j68_alu.v new file mode 100644 index 0000000000000000000000000000000000000000..f3e86287627acdbd59d1bf7d47687309eb275f6c --- /dev/null +++ b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/j68/j68_alu.v @@ -0,0 +1,282 @@ +// Copyright 2011-2018 Frederic Requin +// +// This file is part of the MCC216 project +// +// The J68 core: +// ------------- +// Simple re-implementation of the MC68000 CPU +// The core has the following characteristics: +// - Tested on a Cyclone III (90 MHz) and a Stratix II (180 MHz) +// - from 1500 (~70 MHz) to 1900 LEs (~90 MHz) on Cyclone III +// - 2048 x 20-bit microcode ROM +// - 256 x 28-bit decode ROM +// - 2 x block RAM for the data and instruction stacks +// - stack based CPU with forth-like microcode +// - not cycle-exact : needs a frequency ~3 x higher +// - all 68000 instructions are implemented +// - almost all 68000 exceptions are implemented (only bus error missing) +// - only auto-vector interrupts supported + +module j68_alu +( + // Clock and reset + input rst, // CPU reset + input clk, // CPU clock + /* direct_enable = 1 */ input clk_ena, // CPU clock enable + // Control signals + input cc_upd, // Condition codes update + input [1:0] size, // Operand size (00 = byte, 01 = word, 1x = long) + input [4:0] alu_c, // ALU control + input [1:0] a_ctl, // A source control + input [1:0] b_ctl, // B source control + // Operands + input c_in, // Carry in + input v_in, // Overflow in + input [15:0] a_src, // A source + input [15:0] b_src, // B source + input [15:0] ram_in, // RAM read + input [15:0] io_in, // I/O read + input [15:0] imm_in, // Immediate + // Result + output [31:0] result, // ALU result + // Flags + output [4:0] c_flg, // Partial C/X flags + output [4:0] v_flg, // Partial V flag + output [31:0] l_res, // Latched result for N & Z flags + output [3:0] l_alu, // Latched ALU control + output [1:0] l_size // Latched operand size +); + + reg [15:0] w_a_log; // Operand A for logic + reg [15:0] w_a_add; // Operand A for adder + reg w_a_lsb; // Operand A lsb + + reg [15:0] w_b_log; // Operand B for logic + reg [15:0] w_b_add; // Operand B for adder + reg w_b_lsb; // Operand B lsb + + wire [17:0] w_add_r; // Adder result + reg [15:0] w_log_r; // Logical result + reg [31:0] w_lsh_r; // Left shifter result + reg [31:0] w_rsh_r; // Right shifter result + + wire [4:0] w_c_flg; // Carry flags + wire [4:0] w_v_flg; // Overflow flags + + reg [31:0] w_result; // ALU result + + reg [4:0] r_c_flg; // Partial C/X flags + reg [4:0] r_v_flg; // Partial V flag + reg [31:0] r_l_res; // Latched result for N & Z flags + reg [3:0] r_l_alu; // Latched ALU control + reg [1:0] r_l_size; // Latched operand size + + // A source for Adder (1 LUT level) + always @(*) begin : ADDER_A_SRC + + case (a_ctl) + 2'b00 : w_a_add = 16'h0000; + 2'b01 : w_a_add = 16'hFFFF; + 2'b10 : w_a_add = a_src; + 2'b11 : w_a_add = ~a_src; + endcase + end + + // B source for Adder (1 LUT level) + always @(*) begin : ADDER_B_SRC + + case (b_ctl) + 2'b00 : w_b_add = 16'h0000; + 2'b01 : w_b_add = 16'hFFFF; + 2'b10 : w_b_add = b_src; + 2'b11 : w_b_add = ~b_src; + endcase + end + + // A source for Logic (1 LUT level) + always @(*) begin : LOGIC_A_SRC + + case (a_ctl) + 2'b00 : w_a_log = 16'h0000; + 2'b01 : w_a_log = imm_in; // Immediate value through OR + 2'b10 : w_a_log = a_src; + 2'b11 : w_a_log = ram_in; // RAM read through OR + endcase + end + + // B source for Logic (2 LUT levels) + always @(*) begin : LOGIC_B_SRC + + if (alu_c[4]) begin + // Mask generation for BTST, BCHG, BCLR, BSET + case ({b_src[4]&(size[1]|size[0]), b_src[3]&(size[1]|size[0]), b_src[2:0]}) + 5'b00000 : w_b_log = 16'b0000000000000001 & {16{~size[1]}} ^ {16{b_ctl[0]}}; + 5'b00001 : w_b_log = 16'b0000000000000010 & {16{~size[1]}} ^ {16{b_ctl[0]}}; + 5'b00010 : w_b_log = 16'b0000000000000100 & {16{~size[1]}} ^ {16{b_ctl[0]}}; + 5'b00011 : w_b_log = 16'b0000000000001000 & {16{~size[1]}} ^ {16{b_ctl[0]}}; + 5'b00100 : w_b_log = 16'b0000000000010000 & {16{~size[1]}} ^ {16{b_ctl[0]}}; + 5'b00101 : w_b_log = 16'b0000000000100000 & {16{~size[1]}} ^ {16{b_ctl[0]}}; + 5'b00110 : w_b_log = 16'b0000000001000000 & {16{~size[1]}} ^ {16{b_ctl[0]}}; + 5'b00111 : w_b_log = 16'b0000000010000000 & {16{~size[1]}} ^ {16{b_ctl[0]}}; + 5'b01000 : w_b_log = 16'b0000000100000000 & {16{~size[1]}} ^ {16{b_ctl[0]}}; + 5'b01001 : w_b_log = 16'b0000001000000000 & {16{~size[1]}} ^ {16{b_ctl[0]}}; + 5'b01010 : w_b_log = 16'b0000010000000000 & {16{~size[1]}} ^ {16{b_ctl[0]}}; + 5'b01011 : w_b_log = 16'b0000100000000000 & {16{~size[1]}} ^ {16{b_ctl[0]}}; + 5'b01100 : w_b_log = 16'b0001000000000000 & {16{~size[1]}} ^ {16{b_ctl[0]}}; + 5'b01101 : w_b_log = 16'b0010000000000000 & {16{~size[1]}} ^ {16{b_ctl[0]}}; + 5'b01110 : w_b_log = 16'b0100000000000000 & {16{~size[1]}} ^ {16{b_ctl[0]}}; + 5'b01111 : w_b_log = 16'b1000000000000000 & {16{~size[1]}} ^ {16{b_ctl[0]}}; + 5'b10000 : w_b_log = 16'b0000000000000001 & {16{~size[0]}} ^ {16{b_ctl[0]}}; + 5'b10001 : w_b_log = 16'b0000000000000010 & {16{~size[0]}} ^ {16{b_ctl[0]}}; + 5'b10010 : w_b_log = 16'b0000000000000100 & {16{~size[0]}} ^ {16{b_ctl[0]}}; + 5'b10011 : w_b_log = 16'b0000000000001000 & {16{~size[0]}} ^ {16{b_ctl[0]}}; + 5'b10100 : w_b_log = 16'b0000000000010000 & {16{~size[0]}} ^ {16{b_ctl[0]}}; + 5'b10101 : w_b_log = 16'b0000000000100000 & {16{~size[0]}} ^ {16{b_ctl[0]}}; + 5'b10110 : w_b_log = 16'b0000000001000000 & {16{~size[0]}} ^ {16{b_ctl[0]}}; + 5'b10111 : w_b_log = 16'b0000000010000000 & {16{~size[0]}} ^ {16{b_ctl[0]}}; + 5'b11000 : w_b_log = 16'b0000000100000000 & {16{~size[0]}} ^ {16{b_ctl[0]}}; + 5'b11001 : w_b_log = 16'b0000001000000000 & {16{~size[0]}} ^ {16{b_ctl[0]}}; + 5'b11010 : w_b_log = 16'b0000010000000000 & {16{~size[0]}} ^ {16{b_ctl[0]}}; + 5'b11011 : w_b_log = 16'b0000100000000000 & {16{~size[0]}} ^ {16{b_ctl[0]}}; + 5'b11100 : w_b_log = 16'b0001000000000000 & {16{~size[0]}} ^ {16{b_ctl[0]}}; + 5'b11101 : w_b_log = 16'b0010000000000000 & {16{~size[0]}} ^ {16{b_ctl[0]}}; + 5'b11110 : w_b_log = 16'b0100000000000000 & {16{~size[0]}} ^ {16{b_ctl[0]}}; + 5'b11111 : w_b_log = 16'b1000000000000000 & {16{~size[0]}} ^ {16{b_ctl[0]}}; + endcase + end + else begin + case (b_ctl) + 2'b00 : w_b_log = 16'h0000; + 2'b01 : w_b_log = io_in; // I/O read through OR + 2'b10 : w_b_log = b_src; + 2'b11 : w_b_log = ~b_src; + endcase + end + end + + // Carry input (1 LUT level) + always @(*) begin : CARRY_IN + case (alu_c[1:0]) + 2'b00 : begin // For: R = A + B + w_a_lsb = 1'b0; + w_b_lsb = 1'b0; + end + 2'b01 : begin // For: R = A + B + Carry + w_a_lsb = c_in; + w_b_lsb = c_in; + end + 2'b10 : begin // For: R = A - B + w_a_lsb = 1'b1; + w_b_lsb = 1'b1; + end + 2'b11 : begin // For: R = B - A - Borrow + w_a_lsb = ~c_in; + w_b_lsb = ~c_in; + end + endcase + end + + // Adder (1 LUT level + carry chain) + assign w_add_r = {1'b0, w_a_add, w_a_lsb} + {1'b0, w_b_add, w_b_lsb}; + + // Logical operations (2 LUT levels) + always @(*) begin : LOGIC_OP + + case (alu_c[1:0]) + 2'b00 : w_log_r[7:0] = w_a_log[7:0] & w_b_log[7:0]; // AND.B + 2'b01 : w_log_r[7:0] = w_a_log[7:0] | w_b_log[7:0]; // OR.B + 2'b10 : w_log_r[7:0] = w_a_log[7:0] ^ w_b_log[7:0]; // XOR.B + 2'b11 : w_log_r[7:0] = ~w_a_log[7:0]; // NOT.B + endcase + if (size == 2'b00) begin + w_log_r[15:8] = w_a_log[15:8]; + end + else begin + case (alu_c[1:0]) + 2'b00 : w_log_r[15:8] = w_a_log[15:8] & w_b_log[15:8]; // AND.W + 2'b01 : w_log_r[15:8] = w_a_log[15:8] | w_b_log[15:8]; // OR.W + 2'b10 : w_log_r[15:8] = w_a_log[15:8] ^ w_b_log[15:8]; // XOR.W + 2'b11 : w_log_r[15:8] = ~w_a_log[15:8]; // NOT.W + endcase + end + end + + // Left shifter (1 LUT level) + always @(*) begin : LEFT_SHIFT + case (size) + 2'b00 : w_lsh_r = { b_src[15:0], a_src[15:8], a_src[6:0], c_in }; // Byte + 2'b01 : w_lsh_r = { b_src[15:0], a_src[14:0], c_in }; // Word + default : w_lsh_r = { b_src[14:0], a_src[15:0], c_in }; // Long + endcase + end + + // Right shifter (1 LUT level) + always @(*) begin : RIGHT_SHIFT + case (size) + 2'b00 : w_rsh_r = { b_src[15:0], a_src[15:8], c_in, a_src[7:1] }; // Byte + 2'b01 : w_rsh_r = { b_src[15:0], c_in, a_src[15:1] }; // Word + default : w_rsh_r = { c_in, b_src[15:0], a_src[15:1] }; // Long + endcase + end + + // Final MUX (2 LUTs level) + always @(*) begin : ALU_MUX + case (alu_c[3:2]) + 2'b00 : w_result = { a_src, w_add_r[16:1] }; // Adder + 2'b01 : w_result = { a_src, w_log_r }; // Logic + 2'b10 : w_result = w_lsh_r; // Left shift + 2'b11 : w_result = w_rsh_r; // Right shift + endcase + end + assign result = w_result; + + // Partial carry flags from adder + assign w_c_flg[0] = w_add_r[9] ^ w_a_add[8] + ^ w_b_add[8] ^ alu_c[1]; // Byte + assign w_c_flg[1] = w_add_r[17] ^ alu_c[1]; // Word + // Partial carry flags from shifter + assign w_c_flg[2] = (a_src[0] & alu_c[2]) + | (a_src[7] & ~alu_c[2]); // Byte + assign w_c_flg[3] = (a_src[0] & alu_c[2]) + | (a_src[15] & ~alu_c[2]); // Word + assign w_c_flg[4] = (a_src[0] & alu_c[2]) + | (b_src[15] & ~alu_c[2]); // Long + // Partial overflow flags from adder + assign w_v_flg[0] = w_add_r[9] ^ w_add_r[8] + ^ w_a_add[8] ^ w_a_add[7] + ^ w_b_add[8] ^ w_b_add[7]; // Byte + assign w_v_flg[1] = w_add_r[17] ^ w_add_r[16] + ^ w_a_add[15] ^ w_b_add[15]; // Word + // Partial overflow flags from shifter + assign w_v_flg[2] = v_in | (a_src[7] ^ a_src[6]); // Byte + assign w_v_flg[3] = v_in | (a_src[15] ^ a_src[14]); // Word + assign w_v_flg[4] = v_in | (b_src[15] ^ b_src[14]); // Long + + // Latch partial flags and result + always@(posedge rst or posedge clk) begin : ALU_REGS + + if (rst) begin + r_c_flg <= 5'b00000; + r_v_flg <= 5'b00000; + r_l_res <= 32'h00000000; + r_l_alu <= 4'b0000; + r_l_size <= 2'b00; + end + else if (clk_ena) begin + if (cc_upd) begin + r_c_flg <= w_c_flg; + r_v_flg <= w_v_flg; + r_l_res <= result; + r_l_alu <= alu_c[3:0]; + r_l_size <= size; + end + end + end + + assign c_flg = r_c_flg; + assign v_flg = r_v_flg; + assign l_res = r_l_res; + assign l_alu = r_l_alu; + assign l_size = r_l_size; + +endmodule diff --git a/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/j68/j68_dec.mem b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/j68/j68_dec.mem new file mode 100644 index 0000000000000000000000000000000000000000..f00620316fe8edf1d3b2f1c0821d6158f815184c --- /dev/null +++ b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/j68/j68_dec.mem @@ -0,0 +1,256 @@ +001000000011000000000000111000000000 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+001001010010000000000000011100000000 diff --git a/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/j68/j68_decode.v b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/j68/j68_decode.v new file mode 100644 index 0000000000000000000000000000000000000000..58100d653ef2022a284bd55fe8e5d0d38443c474 --- /dev/null +++ b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/j68/j68_decode.v @@ -0,0 +1,503 @@ +// Copyright 2011-2018 Frederic Requin +// +// This file is part of the MCC216 project +// +// The J68 core: +// ------------- +// Simple re-implementation of the MC68000 CPU +// The core has the following characteristics: +// - Tested on a Cyclone III (90 MHz) and a Stratix II (180 MHz) +// - from 1500 (~70 MHz) to 1900 LEs (~90 MHz) on Cyclone III +// - 2048 x 20-bit microcode ROM +// - 256 x 28-bit decode ROM +// - 2 x block RAM for the data and instruction stacks +// - stack based CPU with forth-like microcode +// - not cycle-exact : needs a frequency ~3 x higher +// - all 68000 instructions are implemented +// - almost all 68000 exceptions are implemented (only bus error missing) +// - only auto-vector interrupts supported + +module j68_decode +( + input rst, + input clk, + input clk_ena, + input ins_rdy, + input [15:0] instr, + input ext_rdy, + input [15:0] ext_wd, + input imm_rdy, + input [15:0] imm_wd, + input user_mode, + input [3:0] ccr_in, + output [11:0] dec_jmp, + output [3:0] ea1_jmp, + output [3:0] ea2_jmp, + output reg [15:0] imm_val, + output [15:0] ea1_bit, + output reg cc_jmp, + output ext_inst, + output bit_inst, + output vld_inst +); + parameter USE_CLK_ENA = 0; + + // Trap routines addresses + localparam [11:0] OP_PRIVILEDGED = (USE_CLK_ENA) ? 12'h038 : 12'h039; + localparam [11:0] OP_ILLEGAL = (USE_CLK_ENA) ? 12'h03A : 12'h03B; + + // $FE00 - $FEFF : Instruction decoder jump table + // $FF00 - $FF1F : Empty + // $FF20 - $FF2F : EA1 read BYTE jump table + // $FF30 - $FF3F : EA1 read WORD jump table + // $FF40 - $FF4F : EA1 read LONG jump table + // $FF50 - $FF5F : EA1 calculation jump table + // $FF60 - $FF6F : EA1 write BYTE jump table + // $FF70 - $FF7F : EA1 write WORD jump table + // $FF80 - $FF8F : EA1 write LONG jump table + // $FF90 - $FF9F : EA2 write BYTE jump table + // $FFA0 - $FFAF : EA2 write WORD jump table + // $FFB0 - $FFBF : EA2 write LONG jump table + // $FFC0 - $FFCF : Bit masks + // $FFD0 - $FFD5 : Empty + // $FFD6 - $FFD7 : VBR + // $FFD8 - $FFD9 : TMP1 + // $FFDA - $FFDB : TMP2 + // $FFDC - $FFDD : USP + // $FFDE - $FFDF : SSP + // $FFE0 - $FFEF : Data registers (D0 - D7) + // $FFF0 - $FFFF : Address registers (A0 - A7) + + + // +---------------------+-------+----------------+------------------+ + // | Index | | | | + // | Decimal | Binary | Group | Description | Op-code | + // +----------+----------+-------+----------------+------------------+ + // | 0..63 | 00xxxxxx | 4 | miscellaneous | 0100111001xxxxxx | + // | 64..95 | 010xxxxx | 0 | immediate | 0000xxx0xx------ | + // | 96..127 | 011xxxxx | 4 | one operand | 0100xxx0xx------ | + // | 128..143 | 1000xxxx | E | shift byte reg | 1110---x00xxx--- | + // | 144..159 | 1001xxxx | E | shift word reg | 1110---x01xxx--- | + // | 160..175 | 1010xxxx | E | shift long reg | 1110---x10xxx--- | + // | 177 | 10110001 | 1 | MOVE.B | 0001------------ | + // | 178 | 10110010 | 2 | MOVE.L | 0010------------ | + // | 179 | 10110011 | 3 | MOVE.W | 0011------------ | + // | 182 | 10110110 | 6 | Bcc | 0110------------ | + // | 183 | 10110111 | 7 | MOVEQ | 0111------------ | + // | 186 | 10111010 | A | Line A | 1010------------ | + // | 191 | 10111111 | F | Line F | 1111------------ | + // | 192..199 | 11000xxx | 8 | OR/DIVx | 1000---xxx------ | + // | 200..207 | 11001xxx | 9 | SUB | 1001---xxx------ | + // | 208..215 | 11010xxx | 5 | ADDQ/SUBQ | 0101---xxx------ | + // | 216..223 | 11011xxx | B | CMP/EOR | 1011---xxx------ | + // | 224..231 | 11100xxx | C | AND/MULx | 1100---xxx------ | + // | 232..239 | 11101xxx | D | ADD | 1101---xxx------ | + // | 240..247 | 11110xxx | E | shift memory | 1110---011xxx--- | + // | 248..251 | 111110xx | 0 | bit operation | 0000---1xx------ | + // | 252..255 | 111111xx | 4 | two operands | 0100---1xx------ | + // +----------+----------+-------+----------------+------------------+ + + // Instructions groups + wire [15:0] w_grp_p0; + + // Effective address bitfields + wire [15:0] w_ea1b_p0; // EA #1 + reg [15:0] r_ea1b_p1; + wire [9:0] w_ea2b_p0; // EA #2 + + // Jump table indexes + wire [3:0] w_ea1_jmp_p0; // EA #1 + reg [3:0] r_ea1_jmp_p1; + //reg [3:0] r_ea1_jmp_p2; + wire [3:0] w_ea2_jmp_p0; // EA #2 + reg [3:0] r_ea2_jmp_p1; + //reg [3:0] r_ea2_jmp_p2; + + // Instructions sub-groups + wire w_g0_immed_p0; + wire w_g0_bitimm_p0; + wire w_g0_bitop_p0; + wire w_g4_misc_p0; + wire w_g4_oneop_p0; + wire w_g4_twoop_p0; + wire w_g5_addsub_p0; + wire w_g6_bsr_p0; + wire w_gE_shmem_p0; + wire w_gE_shreg_p0; + + // NEGX, ADDX, SUBX, NBCD, ABCD, SBCD + wire w_g4_nbcd_p0; + wire w_g8_sbcd_p0; + wire w_gC_abcd_p0; + wire w_g4_negx_p0; + wire w_g9_subx_p0; + wire w_gD_addx_p0; + + // Pre-decode + wire w_ill_ins_p0; // Illegal instruction + reg r_ill_ins_p1; + wire w_prv_ins_p0; // Priviledged instruction + reg r_prv_ins_p1; + wire w_ext_ins_p0; // Special Z flag treatment + reg r_ext_ins_p1; + //reg r_ext_ins_p2; + wire w_bit_ins_p0; // Bit manipulation instructions + reg r_bit_ins_p1; + //reg r_bit_ins_p2; + reg w_vld_ins_p1; // Valid instruction + reg r_vld_ins_p2; + + // Call address + wire w_call1_ena_p0; // Jump table call #1 enable + wire w_call2_ena_p0; // Jump table call #2 enable + reg [1:0] r_call_en_p1; + reg [11:0] r_call_p2; + + // Indexes + wire [5:0] w_idx6_5_0_p0; // 5..0 + wire [5:0] w_idx5_B_6_p0; // 11..9, 7..6 + wire [5:0] w_idx4_8_3_p0; // 8, 5..3 + wire [5:0] w_idx4_F_C_p0; // 15..12 + wire [5:0] w_idx3_8_6_p0; // 8..6 + wire [5:0] w_idx3_A_8_p0; // 10..8 + wire [5:0] w_idx2_7_6_p0; // 7..6 + + // Decoder ROM + wire [7:0] w_addr_p0; // Decoder ROM address + wire [35:0] w_data_p1; // Decoder ROM data + reg [15:0] w_ea1m_p1; // Effective address #1 mask + reg [5:0] w_incr_p1; // Call address increment + reg [11:0] w_call_p1; // Call address + + // Immediate values + wire [15:0] w_imm3_i; // For ADDQ, SUBQ, Shift reg + wire [15:0] w_imm4_i; // For TRAP + wire [15:0] w_imm8_i; // For MOVEQ, Bcc.B + wire [15:0] w_imm5_e; // For BTST, BCHG, BCLR, BSET + wire [15:0] w_imm8_e; // For d8(An, Rn), d8(PC, Rn) + + // Instructions groups decode + assign w_grp_p0[0] = (instr[15:12] == 4'b0000) ? 1'b1 : 1'b0; // Immed + assign w_grp_p0[1] = (instr[15:12] == 4'b0001) ? 1'b1 : 1'b0; // MOVE.B + assign w_grp_p0[2] = (instr[15:12] == 4'b0010) ? 1'b1 : 1'b0; // MOVE.L + assign w_grp_p0[3] = (instr[15:12] == 4'b0011) ? 1'b1 : 1'b0; // MOVE.W + assign w_grp_p0[4] = (instr[15:12] == 4'b0100) ? 1'b1 : 1'b0; // Misc + assign w_grp_p0[5] = (instr[15:12] == 4'b0101) ? 1'b1 : 1'b0; // ADDQ, SUBQ + assign w_grp_p0[6] = (instr[15:12] == 4'b0110) ? 1'b1 : 1'b0; // Bcc + assign w_grp_p0[7] = (instr[15:12] == 4'b0111) ? 1'b1 : 1'b0; // MOVEQ + assign w_grp_p0[8] = (instr[15:12] == 4'b1000) ? 1'b1 : 1'b0; // OR, DIV + assign w_grp_p0[9] = (instr[15:12] == 4'b1001) ? 1'b1 : 1'b0; // SUB + assign w_grp_p0[10] = (instr[15:12] == 4'b1010) ? 1'b1 : 1'b0; // Line A + assign w_grp_p0[11] = (instr[15:12] == 4'b1011) ? 1'b1 : 1'b0; // CMP, EOR + assign w_grp_p0[12] = (instr[15:12] == 4'b1100) ? 1'b1 : 1'b0; // AND, MUL + assign w_grp_p0[13] = (instr[15:12] == 4'b1101) ? 1'b1 : 1'b0; // ADD + assign w_grp_p0[14] = (instr[15:12] == 4'b1110) ? 1'b1 : 1'b0; // Shift + assign w_grp_p0[15] = (instr[15:12] == 4'b1111) ? 1'b1 : 1'b0; // Line F + + // Effective addresses #1 bitfield + assign w_ea1b_p0[15] = (instr[5:0] == 6'b111111) ? 1'b1 : 1'b0; // ??? + assign w_ea1b_p0[14] = (instr[5:0] == 6'b111110) ? 1'b1 : 1'b0; // ??? + assign w_ea1b_p0[13] = (instr[5:0] == 6'b111101) ? 1'b1 : 1'b0; // ??? + assign w_ea1b_p0[12] = (instr[5:0] == 6'b111100) ? 1'b1 : 1'b0; // #imm, CCR/SR + assign w_ea1b_p0[11] = (instr[5:0] == 6'b111011) ? 1'b1 : 1'b0; // d8(PC,Rn) + assign w_ea1b_p0[10] = (instr[5:0] == 6'b111010) ? 1'b1 : 1'b0; // d16(PC) + assign w_ea1b_p0[9] = (instr[5:0] == 6'b111001) ? 1'b1 : 1'b0; // xxxxxxxx.L + assign w_ea1b_p0[8] = (instr[5:0] == 6'b111000) ? 1'b1 : 1'b0; // xxxx.W + assign w_ea1b_p0[7] = (instr[5:4] == 2'b00) ? 1'b1 : 1'b0; // Bcc.W + assign w_ea1b_p0[6] = (instr[5:3] == 3'b110) ? 1'b1 : 1'b0; // d8(An,Rn) + assign w_ea1b_p0[5] = (instr[5:3] == 3'b101) ? 1'b1 : 1'b0; // d16(An) + assign w_ea1b_p0[4] = (instr[5:3] == 3'b100) ? 1'b1 : 1'b0; // -(An) + assign w_ea1b_p0[3] = (instr[5:3] == 3'b011) ? 1'b1 : 1'b0; // (An)+ + assign w_ea1b_p0[2] = (instr[5:3] == 3'b010) ? 1'b1 : 1'b0; // (An) + assign w_ea1b_p0[1] = (instr[5:3] == 3'b001) ? 1'b1 : 1'b0; // An + assign w_ea1b_p0[0] = (instr[5:3] == 3'b000) ? 1'b1 : 1'b0; // Dn + + // Effective addresses #2 bitfield + assign w_ea2b_p0[9] = (instr[8:6] == 3'b111) + && (instr[11:10] != 2'b00) ? 1'b1 : 1'b0; // ??? + assign w_ea2b_p0[8] = (instr[11:6] == 6'b001111) ? 1'b1 : 1'b0; // xxxxxxxx.L + assign w_ea2b_p0[7] = (instr[11:6] == 6'b000111) ? 1'b1 : 1'b0; // xxxx.W + assign w_ea2b_p0[6] = (instr[8:6] == 3'b110) ? 1'b1 : 1'b0; // d8(An,Rn) + assign w_ea2b_p0[5] = (instr[8:6] == 3'b101) ? 1'b1 : 1'b0; // d16(An) + assign w_ea2b_p0[4] = (instr[8:6] == 3'b100) ? 1'b1 : 1'b0; // -(An) + assign w_ea2b_p0[3] = (instr[8:6] == 3'b011) ? 1'b1 : 1'b0; // (An)+ + assign w_ea2b_p0[2] = (instr[8:6] == 3'b010) ? 1'b1 : 1'b0; // (An) + assign w_ea2b_p0[1] = (instr[8:6] == 3'b001) ? 1'b1 : 1'b0; // An + assign w_ea2b_p0[0] = (instr[8:6] == 3'b000) ? 1'b1 : 1'b0; // Dn + + // Effective addresses indexes (6-bit EA field -> 4-bit index) + assign w_ea1_jmp_p0[3] = (instr[5:3] == 3'b111) ? 1'b1 : 1'b0; + assign w_ea1_jmp_p0[2:0] = (instr[5:3] == 3'b111) ? instr[2:0] : instr[5:3]; + assign w_ea2_jmp_p0[3] = (instr[8:6] == 3'b111) ? 1'b1 : 1'b0; + assign w_ea2_jmp_p0[2:0] = (instr[8:6] == 3'b111) ? instr[11:9] : instr[8:6]; + + // Instructions sub-groups decode + assign w_g0_immed_p0 = w_grp_p0[0] & ~instr[8]; + assign w_g0_bitimm_p0 = (instr[15:8] == 8'b0000_1000) ? 1'b1 : 1'b0; + assign w_g0_bitop_p0 = w_grp_p0[0] & instr[8]; + assign w_g4_misc_p0 = (instr[15:6] == 10'b0100_111_001) ? 1'b1 : 1'b0; + assign w_g4_oneop_p0 = w_grp_p0[4] & ~instr[8] & ~w_g4_misc_p0; + assign w_g4_twoop_p0 = w_grp_p0[4] & instr[8]; + assign w_g5_addsub_p0 = w_grp_p0[5] & ~(instr[7] & instr[6]); + assign w_g6_bsr_p0 = (instr[11:8] == 4'b0001) ? 1'b1 : 1'b0; + assign w_gE_shmem_p0 = w_grp_p0[14] & instr[7] & instr[6]; + assign w_gE_shreg_p0 = w_grp_p0[14] & ~(instr[7] & instr[6]); + + // Special Z flag treatment for NBCD, SBCD, ABCD, NEGX, SUB, ADDX + assign w_g4_nbcd_p0 = (w_grp_p0[4]) && (instr[11:6] == 6'b100000) ? 1'b1 : 1'b0; + assign w_g8_sbcd_p0 = (w_grp_p0[8]) && (instr[8:4] == 5'b10000) ? 1'b1 : 1'b0; + assign w_gC_abcd_p0 = (w_grp_p0[12]) && (instr[8:4] == 5'b10000) ? 1'b1 : 1'b0; + assign w_g4_negx_p0 = (w_grp_p0[4]) && (instr[11:8] == 4'b0000) ? 1'b1 : 1'b0; + assign w_g9_subx_p0 = (w_grp_p0[9]) && ((instr[8:4] == 5'b10000) || + (instr[8:4] == 5'b10100) || + (instr[8:4] == 5'b11000)) ? 1'b1 : 1'b0; + assign w_gD_addx_p0 = (w_grp_p0[13]) && ((instr[8:4] == 5'b10000) || + (instr[8:4] == 5'b10100) || + (instr[8:4] == 5'b11000)) ? 1'b1 : 1'b0; + assign w_ext_ins_p0 = w_g4_negx_p0 | w_g9_subx_p0 | w_gD_addx_p0 + | w_g4_nbcd_p0 | w_g8_sbcd_p0 | w_gC_abcd_p0; + + // Bit manipulation instructions + assign w_bit_ins_p0 = w_g0_bitop_p0 | w_g0_bitimm_p0; + + // Illegal instruction pre-decode (not present in the jump table) + assign w_ill_ins_p0 = (w_grp_p0[1] & w_ea2b_p0[1]) // MOVE.B An, + | (w_grp_p0[1] & w_ea2b_p0[9]) // MOVE.B ,??? + | (w_grp_p0[2] & w_ea2b_p0[9]) // MOVE.L ,??? + | (w_grp_p0[3] & w_ea2b_p0[9]) // MOVE.W ,??? + | (w_grp_p0[7] & instr[8]) // Coldfire's MVS/MVZ instr. + | (w_grp_p0[14] & instr[11] & instr[7] & instr[6]); // Empty slots in shift instr. + // Priviledged instruction pre-decode + assign w_prv_ins_p0 = ((w_grp_p0[0]) && (instr[6]) && (w_ea1b_p0[12])) // Log. immed SR + || ((w_g4_misc_p0) && ((instr[5:4] == 2'b10) || // MOVE USP + (instr[5:0] == 6'b110000) || // RESET + (instr[6:1] == 6'b11001))) // STOP, RTE + || ((w_grp_p0[4]) && (instr[11:6] == 6'b011011)) // MOVE ,SR + ? user_mode : 1'b0; + + // Jump table call #1 enable + assign w_call1_ena_p0 = (w_grp_p0[0] & w_ea1b_p0[0]) // Bit op. reg + | (w_grp_p0[2] & w_ea2b_p0[1]) // MOVEA.L + | (w_grp_p0[3] & w_ea2b_p0[1]) // MOVEA.W + | (w_grp_p0[4] & ~w_g4_misc_p0 & w_ea1b_p0[0]) // SWAP, EXT + | (w_grp_p0[6] & w_g6_bsr_p0) // BSR + | (w_grp_p0[8] & w_ea1b_p0[0]) // SBCD reg + | (w_grp_p0[9] & w_ea1b_p0[0]) // SUBX reg + | (w_grp_p0[12] & w_ea1b_p0[0]) // ABCD reg, EXG + | (w_grp_p0[13] & w_ea1b_p0[0]); // ADDX reg + // Jump table call #2 enable + assign w_call2_ena_p0 = (w_grp_p0[0] & ~instr[8] & w_ea1b_p0[12]) // Log op. SR + | (w_grp_p0[0] & instr[8] & w_ea1b_p0[1]) // MOVEP + | (w_grp_p0[4] & ~w_g4_misc_p0 & w_ea1b_p0[3]) // MOVEM (An)+ + | (w_grp_p0[4] & ~w_g4_misc_p0 & w_ea1b_p0[4]) // MOVEM ,-(An) + | (w_grp_p0[5] & w_ea1b_p0[1]) // ADDQA, SUBQA, DBcc + | (w_grp_p0[8] & w_ea1b_p0[1]) // SBCD mem + | (w_grp_p0[9] & w_ea1b_p0[1]) // SUBX mem + | (w_grp_p0[11] & w_ea1b_p0[1]) // CMPM + | (w_grp_p0[12] & w_ea1b_p0[1]) // ABCD mem, EXG + | (w_grp_p0[13] & w_ea1b_p0[1]); // ADDX mem + + // 6-bit indexes calculations + assign w_idx6_5_0_p0 = (w_g4_misc_p0) + ? instr[5:0] + : 6'b000000; + assign w_idx5_B_6_p0 = (w_g0_immed_p0 | w_g4_oneop_p0) + ? { instr[14], instr[11:9], instr[7:6] } + : 6'b000000; + assign w_idx4_8_3_p0 = (w_gE_shreg_p0) + ? { instr[7:6], instr[8], instr[5:3] } + : 6'b000000; + assign w_idx4_F_C_p0 = (w_grp_p0[1] | w_grp_p0[2] | w_grp_p0[3] | w_grp_p0[6] | w_grp_p0[7] | w_grp_p0[10] | w_grp_p0[15]) + ? { 2'b11, instr[15:12] } + : 6'b000000; + assign w_idx3_8_6_p0 = (w_grp_p0[5] | w_grp_p0[8] | w_grp_p0[9] | w_grp_p0[11] | w_grp_p0[12] | w_grp_p0[13]) + ? { instr[14] ^ ~instr[15], instr[13] ^ ~instr[15], instr[12] ^ ~instr[15], instr[8:6] } + : 6'b000000; + assign w_idx3_A_8_p0 = (w_gE_shmem_p0) + ? { 3'b110, instr[10:8] } + : 6'b000000; + assign w_idx2_7_6_p0 = (w_g0_bitop_p0 | w_g4_twoop_p0) + ? { 3'b111, instr[14], instr[7:6] } + : 6'b000000; + + // 256-entry table index (16-bit instr. -> 8-bit index) + assign w_addr_p0[7] = ((instr[12] | instr[13]) & ~instr[15]) // Groups #1,2,3,5,6,7 + | instr[15] | w_g0_bitop_p0 | w_g4_twoop_p0; // Groups #8-15 + assign w_addr_p0[6] = w_grp_p0[5] | w_grp_p0[8] | w_grp_p0[9] + | w_grp_p0[11] | w_grp_p0[12] | w_grp_p0[13] + | w_g0_immed_p0 | w_g0_bitop_p0 | w_g4_oneop_p0 + | w_g4_twoop_p0 | w_gE_shmem_p0; + assign w_addr_p0[5:0] = w_idx6_5_0_p0 | w_idx5_B_6_p0 | w_idx4_8_3_p0 + | w_idx4_F_C_p0 | w_idx3_8_6_p0 | w_idx3_A_8_p0 + | w_idx2_7_6_p0; + + // Jump table ROM + j68_decode_rom + #( + .USE_CLK_ENA (USE_CLK_ENA) + ) + U_decode_rom + ( + .clock (clk), + .address (w_addr_p0), + .q (w_data_p1) + ); + + always@(*) begin + + // EA #1 mask + case (w_data_p1[11:8]) + 4'b0000 : w_ea1m_p1 = 16'b000_00000_00000000; // $0000 + 4'b0001 : w_ea1m_p1 = 16'b000_00011_01110101; // $01F5 + 4'b0010 : w_ea1m_p1 = 16'b000_00011_01111100; // $01FC + 4'b0011 : w_ea1m_p1 = 16'b000_00011_01111101; // $01FD + 4'b0100 : w_ea1m_p1 = 16'b000_00011_01111110; // $01FE + 4'b0101 : w_ea1m_p1 = 16'b000_00011_01111111; // $01FF + 4'b0110 : w_ea1m_p1 = 16'b000_01111_01001101; // $07CD + 4'b0111 : w_ea1m_p1 = 16'b000_01111_01100100; // $07E4 + 4'b1000 : w_ea1m_p1 = 16'b000_01111_01100101; // $07E5 + 4'b1001 : w_ea1m_p1 = 16'b000_01111_01101100; // $07EC + 4'b1010 : w_ea1m_p1 = 16'b000_01111_01111101; // $07FD + 4'b1011 : w_ea1m_p1 = 16'b000_10011_01111101; // $09FD + 4'b1100 : w_ea1m_p1 = 16'b000_11111_01111101; // $0FFD + 4'b1101 : w_ea1m_p1 = 16'b000_11111_01111111; // $0FFF + default : w_ea1m_p1 = 16'b111_11111_01111111; // $7FFF + endcase + // Call address increment + w_incr_p1 = (w_data_p1[23:18] & {6{r_call_en_p1[0]}}) + | (w_data_p1[17:12] & {6{r_call_en_p1[1]}}); + // Call address + if (((w_ea1m_p1 & r_ea1b_p1) == 16'h0000) || (r_ill_ins_p1)) begin + // Illegal instruction + w_call_p1 = OP_ILLEGAL; + w_vld_ins_p1 = 1'b0; + end + else if (r_prv_ins_p1) begin + // Priviledge violation + w_call_p1 = OP_PRIVILEDGED; + w_vld_ins_p1 = 1'b1; + end + else begin + // Valid instruction + w_call_p1 = w_data_p1[35:24] + { 6'b000000, w_incr_p1 }; + w_vld_ins_p1 = 1'b1; + end + end + + // Latch the indexes and bitfields + always @(posedge rst or posedge clk) begin : DECODE_P1_P2 + + if (rst) begin + r_ea1_jmp_p1 <= 4'b0000; + r_ea2_jmp_p1 <= 4'b0000; + r_ill_ins_p1 <= 1'b0; + r_prv_ins_p1 <= 1'b0; + r_ext_ins_p1 <= 1'b0; + r_bit_ins_p1 <= 1'b0; + r_call_en_p1 <= 2'b00; + r_ea1b_p1 <= 16'b0000000_00000000; + + //r_ext_ins_p2 <= 1'b0; + //r_bit_ins_p2 <= 1'b0; + r_vld_ins_p2 <= 1'b0; + //r_ea1_jmp_p2 <= 4'b0000; + //r_ea2_jmp_p2 <= 4'b0000; + r_call_p2 <= 12'h000; + end + else if (clk_ena) begin + // Cycle #1 + r_ea1_jmp_p1 <= w_ea1_jmp_p0; + r_ea2_jmp_p1 <= w_ea2_jmp_p0; + r_ill_ins_p1 <= w_ill_ins_p0; + r_prv_ins_p1 <= w_prv_ins_p0; + r_ext_ins_p1 <= w_ext_ins_p0; + r_bit_ins_p1 <= w_bit_ins_p0; + r_call_en_p1 <= { w_call2_ena_p0, w_call1_ena_p0 }; + r_ea1b_p1 <= w_ea1b_p0; + // Cycle #2 + //r_ext_ins_p2 <= r_ext_ins_p1; + //r_bit_ins_p2 <= r_bit_ins_p1; + r_vld_ins_p2 <= w_vld_ins_p1; + //r_ea1_jmp_p2 <= r_ea1_jmp_p1; + //r_ea2_jmp_p2 <= r_ea2_jmp_p1; + r_call_p2 <= w_call_p1; + end + end + + assign vld_inst = r_vld_ins_p2; + assign ext_inst = r_ext_ins_p1; + assign bit_inst = r_bit_ins_p1; + assign dec_jmp = r_call_p2; + assign ea1_jmp = r_ea1_jmp_p1; + assign ea2_jmp = r_ea2_jmp_p1; + assign ea1_bit = r_ea1b_p1; + + // Immediate values from instruction word + // For ADDQ, SUBQ and shift immediate + assign w_imm3_i[15:4] = 12'h000; + assign w_imm3_i[3] = (instr[11:9] == 3'b000) ? (w_g5_addsub_p0 | (w_gE_shreg_p0 & ~instr[5])) : 1'b0; + assign w_imm3_i[2:0] = (w_g5_addsub_p0 | (w_gE_shreg_p0 & ~instr[5])) ? instr[11:9] : 3'b000; + // For TRAP #x : xxx0 - xxxF -> 0080 - 00BC + assign w_imm4_i[15:8] = 8'h00; + assign w_imm4_i[7:0] = (w_g4_misc_p0) ? {2'b10, instr[3:0], 2'b00} : 8'h00; + // For MOVEQ and Bcc.B + assign w_imm8_i[15:8] = (w_grp_p0[6] | (w_grp_p0[7] & ~instr[8])) ? {8{instr[7]}} : 8'h00; + assign w_imm8_i[7:0] = (w_grp_p0[6] | (w_grp_p0[7] & ~instr[8])) ? instr[7:0] : 8'h00; + + // Immediate values from extension word + // For BTST, BCHG, BCLR and BSET + assign w_imm5_e[15:5] = 11'b0; + assign w_imm5_e[4:0] = ext_wd[4:0]; + // For d8(An,Rn) and d8(PC,Rn) + assign w_imm8_e[15:8] = {8{ext_wd[7]}}; + assign w_imm8_e[7:0] = ext_wd[7:0]; + + // Latch the immediate values + always @(posedge rst or posedge clk) begin : IMMED_VAL + + if (rst) begin + imm_val <= 16'h0000; + end + else if (clk_ena) begin + if (ins_rdy) imm_val <= w_imm3_i | w_imm4_i | w_imm8_i; + if (ext_rdy) begin + if (w_g0_bitimm_p0) begin + imm_val <= w_imm5_e; + end + else begin + imm_val <= w_imm8_e; + end + end + if (imm_rdy) imm_val <= imm_wd; + end + end + + // Jump flag from condition codes + always @(posedge rst or posedge clk) begin : CC_JUMP_FLAG + + if (rst) begin + cc_jmp <= 1'b0; + end + else if (clk_ena) begin + case (instr[11:8]) + 4'b0000 : cc_jmp <= 1'b1; // T + 4'b0001 : cc_jmp <= 1'b0; // F + 4'b0010 : cc_jmp <= ~(ccr_in[0] | ccr_in[2]); // HI + 4'b0011 : cc_jmp <= ccr_in[0] | ccr_in[2]; // LS + 4'b0100 : cc_jmp <= ~ ccr_in[0]; // CC + 4'b0101 : cc_jmp <= ccr_in[0]; // CS + 4'b0110 : cc_jmp <= ~ ccr_in[2]; // NE + 4'b0111 : cc_jmp <= ccr_in[2]; // EQ + 4'b1000 : cc_jmp <= ~ ccr_in[1]; // VC + 4'b1001 : cc_jmp <= ccr_in[1]; // VS + 4'b1010 : cc_jmp <= ~ ccr_in[3]; // PL + 4'b1011 : cc_jmp <= ccr_in[3]; // MI + 4'b1100 : cc_jmp <= ~(ccr_in[1] ^ ccr_in[3]); // GE + 4'b1101 : cc_jmp <= ccr_in[1] ^ ccr_in[3]; // LT + 4'b1110 : cc_jmp <= ~((ccr_in[1] ^ ccr_in[3]) | ccr_in[2]); // GT + 4'b1111 : cc_jmp <= (ccr_in[1] ^ ccr_in[3]) | ccr_in[2]; // LE + endcase + end + end + +endmodule diff --git a/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/j68/j68_decode_rom.v b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/j68/j68_decode_rom.v new file mode 100644 index 0000000000000000000000000000000000000000..f3a9203bb7fe62bcb27b4ee465bb7b26eb4202b4 --- /dev/null +++ b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/j68/j68_decode_rom.v @@ -0,0 +1,45 @@ +// Copyright 2011-2018 Frederic Requin +// +// This file is part of the MCC216 project +// +// The J68 core: +// ------------- +// Simple re-implementation of the MC68000 CPU +// The core has the following characteristics: +// - Tested on a Cyclone III (90 MHz) and a Stratix II (180 MHz) +// - from 1500 (~70 MHz) to 1900 LEs (~90 MHz) on Cyclone III +// - 2048 x 20-bit microcode ROM +// - 256 x 28-bit decode ROM +// - 2 x block RAM for the data and instruction stacks +// - stack based CPU with forth-like microcode +// - not cycle-exact : needs a frequency ~3 x higher +// - all 68000 instructions are implemented +// - almost all 68000 exceptions are implemented (only bus error missing) +// - only auto-vector interrupts supported + +module j68_decode_rom +( + input clock, + input [7:0] address, + output [35:0] q +); + parameter USE_CLK_ENA = 0; + + // Testbench + reg [35:0] r_mem_blk [0:255]; + reg [35:0] r_q; + + initial begin + if (USE_CLK_ENA) + $readmemb("j68_dec_c.mem", r_mem_blk); + else + $readmemb("j68_dec.mem", r_mem_blk); + end + + always@(posedge clock) begin : READ_PORT + r_q <= r_mem_blk[address]; + end + + assign q = r_q; + +endmodule diff --git a/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/j68/j68_dpram_2048x20.v b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/j68/j68_dpram_2048x20.v new file mode 100644 index 0000000000000000000000000000000000000000..d0325f0e11916f8630f40bb82bcedf268c339eab --- /dev/null +++ b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/j68/j68_dpram_2048x20.v @@ -0,0 +1,66 @@ +// Copyright 2011-2018 Frederic Requin +// +// This file is part of the MCC216 project +// +// The J68 core: +// ------------- +// Simple re-implementation of the MC68000 CPU +// The core has the following characteristics: +// - Tested on a Cyclone III (90 MHz) and a Stratix II (180 MHz) +// - from 1500 (~70 MHz) to 1900 LEs (~90 MHz) on Cyclone III +// - 2048 x 20-bit microcode ROM +// - 256 x 28-bit decode ROM +// - 2 x block RAM for the data and instruction stacks +// - stack based CPU with forth-like microcode +// - not cycle-exact : needs a frequency ~3 x higher +// - all 68000 instructions are implemented +// - almost all 68000 exceptions are implemented (only bus error missing) +// - only auto-vector interrupts supported + +// Testbench +module j68_dpram_2048x20 +( + // Clock + input clock, + input clocken, + // Port A : micro-instruction fetch + input rden_a, + input [10:0] address_a, + output reg [19:0] q_a, + // Port B : m68k registers read/write + input [1:0] wren_b, + input [10:0] address_b, + input [15:0] data_b, + output reg [15:0] q_b +); + parameter RAM_INIT_FILE = "j68_ram.mem"; + + // Inferred block RAM + reg [19:0] r_mem_blk [0:2047]; + + initial begin + $readmemb(RAM_INIT_FILE, r_mem_blk); + end + + // Port A (read only) + always@(posedge clock) begin : PORT_A + if (rden_a & clocken) begin + q_a <= r_mem_blk[address_a]; + end + end + + // Port B (read/write) + always@(posedge clock) begin : PORT_B + + if (clocken) begin + q_b <= r_mem_blk[address_b][15:0]; + if (wren_b[0]) begin + r_mem_blk[address_b][7:0] <= data_b[7:0]; + end + if (wren_b[1]) begin + r_mem_blk[address_b][15:8] <= data_b[15:8]; + end + end + end + +endmodule diff --git a/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/j68/j68_flags.v b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/j68/j68_flags.v new file mode 100644 index 0000000000000000000000000000000000000000..2660113de39dcbbdbd14b32d21724e68fa8011f9 --- /dev/null +++ b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/j68/j68_flags.v @@ -0,0 +1,264 @@ +// Copyright 2011-2018 Frederic Requin +// +// This file is part of the MCC216 project +// +// The J68 core: +// ------------- +// Simple re-implementation of the MC68000 CPU +// The core has the following characteristics: +// - Tested on a Cyclone III (90 MHz) and a Stratix II (180 MHz) +// - from 1500 (~70 MHz) to 1900 LEs (~90 MHz) on Cyclone III +// - 2048 x 20-bit microcode ROM +// - 256 x 28-bit decode ROM +// - 2 x block RAM for the data and instruction stacks +// - stack based CPU with forth-like microcode +// - not cycle-exact : needs a frequency ~3 x higher +// - all 68000 instructions are implemented +// - almost all 68000 exceptions are implemented (only bus error missing) +// - only auto-vector interrupts supported + +module j68_flags +( + // Clock and reset + input rst, // CPU reset + input clk, // CPU clock + /* direct_enable = 1 */ input clk_ena, // CPU clock enable + // Flags input + input [4:0] c_flg, // Partial C/X flags + input [5:0] v_flg, // Partial V flags + input [31:0] l_res, // Latched result for N & Z flags + input [3:0] l_alu, // Latched ALU control + input [1:0] l_size, // Latched operand size + // Operand input + input [15:0] a_src, // A operand + input [15:0] b_src, // B operand + // Flags control + input [10:0] flg_c, // Flags output control + input [3:0] cin_c, // Carry in control + // Flags output + output [4:0] cc_out, // XNZVC 68000 flags + output c_in, // Carry in for ALU + output z_flg, // Zero flag for test block + output g_flg // Greater than flag for test block +); + reg w_c_flg; + reg w_v_flg; + reg w_z_flg; + reg w_n_flg; + wire [2:0] w_zero; + + reg r_z_flg; + reg [4:0] r_cc_out; + reg r_c_in; + + // C/X flag computation + always@(*) begin : C_X_FLAG + + case (l_alu[3:2]) + // Adder + 2'b00 : begin + if (l_size == 2'b00) begin + w_c_flg = c_flg[0]; // Byte + end + else begin + w_c_flg = c_flg[1]; // Word & Long + end + end + // Logic + 2'b01 : begin + w_c_flg = 1'b0; + end + // Shifter + default : begin + case (l_size) + 2'b00 : w_c_flg = c_flg[2]; // Byte + 2'b01 : w_c_flg = c_flg[3]; // Word + default : w_c_flg = c_flg[4]; // Long + endcase + end + endcase + end + + // V flag computation + always@(l_alu or l_size or v_flg) begin : V_FLAG + + case (l_alu[3:2]) + // Adder + 2'b00 : begin + if (l_size == 2'b00) begin + w_v_flg = v_flg[0]; // Byte + end + else begin + w_v_flg = v_flg[1]; // Word & Long + end + end + // Left shifter (ASL case) + 2'b10 : begin + case (l_size) + 2'b00 : w_v_flg = v_flg[2]; // Byte + 2'b01 : w_v_flg = v_flg[3]; // Word + default : w_v_flg = v_flg[4]; // Long + endcase + end + // Right shifter (DIVU/DIVS case) + 2'b11 : begin + w_v_flg = v_flg[5] & l_alu[1]; + end + // Logic : no overflow + default : begin + w_v_flg = 1'b0; + end + endcase + end + + // Z flag computation + assign w_zero[0] = (l_res[7:0] == 8'h00) ? 1'b1 : 1'b0; + assign w_zero[1] = (l_res[15:8] == 8'h00) ? 1'b1 : 1'b0; + assign w_zero[2] = (l_res[31:16] == 16'h0000) ? 1'b1 : 1'b0; + always@(*) begin : Z_FLAG + + if (l_alu[3]) begin + // Shifter + case (l_size) + 2'b00 : w_z_flg = w_zero[0]; // Byte + 2'b01 : w_z_flg = w_zero[0] & w_zero[1]; // Word + default : w_z_flg = w_zero[0] & w_zero[1] & w_zero[2]; // Long + endcase + end + else begin + // Adder & Logic + case (l_size) + 2'b00 : w_z_flg = w_zero[0]; // Byte + 2'b01 : w_z_flg = w_zero[0] & w_zero[1]; // Word + default : w_z_flg = w_zero[0] & w_zero[1] & r_z_flg; // Long + endcase + end + end + + // N flag computation + always@(*) begin : N_FLAG + + if (l_alu[3]) begin + // Shifter + case (l_size) + 2'b00 : w_n_flg = l_res[7]; // Byte + 2'b01 : w_n_flg = l_res[15]; // Word + default : w_n_flg = l_res[31]; // Long + endcase + end + else begin + // Adder & Logic + case (l_size) + 2'b00 : w_n_flg = l_res[7]; // Byte + 2'b01 : w_n_flg = l_res[15]; // Word + default : w_n_flg = l_res[15]; // Long + endcase + end + end + + // Flag output control + // 00 : keep (-) + // 01 : update (*) + // 10 : clear (0) + // 11 : set (1) + // 100 : update, clear only (.) + always@(posedge rst or posedge clk) begin : CCR_OUTPUT + + if (rst) begin + r_cc_out <= 5'b00100; + r_z_flg <= 1'b0; + end + else if (clk_ena) begin + // C flag update + case (flg_c[1:0]) + 2'b00 : r_cc_out[0] <= r_cc_out[0]; + 2'b01 : r_cc_out[0] <= w_c_flg; + 2'b10 : r_cc_out[0] <= 1'b0; + 2'b11 : r_cc_out[0] <= 1'b1; + endcase + // V flag update + case (flg_c[3:2]) + 2'b00 : r_cc_out[1] <= r_cc_out[1]; + 2'b01 : r_cc_out[1] <= w_v_flg; + 2'b10 : r_cc_out[1] <= 1'b0; + 2'b11 : r_cc_out[1] <= 1'b1; + endcase + // Z flag update + case (flg_c[6:4]) + 3'b000 : r_cc_out[2] <= r_cc_out[2]; + 3'b001 : r_cc_out[2] <= w_z_flg; + 3'b010 : r_cc_out[2] <= 1'b0; + 3'b011 : r_cc_out[2] <= 1'b1; + 3'b100 : r_cc_out[2] <= r_cc_out[2]; + 3'b101 : r_cc_out[2] <= w_z_flg & r_cc_out[2]; + 3'b110 : r_cc_out[2] <= 1'b0; + 3'b111 : r_cc_out[2] <= 1'b1; + endcase + // N flag update + case (flg_c[8:7]) + 2'b00 : r_cc_out[3] <= r_cc_out[3]; + 2'b01 : r_cc_out[3] <= w_n_flg; + 2'b10 : r_cc_out[3] <= 1'b0; + 2'b11 : r_cc_out[3] <= 1'b1; + endcase + // X flag update + case (flg_c[10:9]) + 2'b00 : r_cc_out[4] <= r_cc_out[4]; + 2'b01 : r_cc_out[4] <= w_c_flg; + 2'b10 : r_cc_out[4] <= 1'b0; + 2'b11 : r_cc_out[4] <= 1'b1; + endcase + if ((!l_alu[3]) && (l_size == 2'b01)) begin + r_z_flg <= w_zero[0] & w_zero[1]; + end + end + end + assign cc_out = r_cc_out; + // Zero flag from word result + assign z_flg = w_zero[0] & w_zero[1]; + // Greater than from adder : not((V xor N) or Z) + assign g_flg = ~((v_flg[1] ^ l_res[15]) | (w_zero[0] & w_zero[1])); + + // Carry input control + // 0000 : keep : KEEP + // 0001 : 0 : CLR + // 0010 : c_flg[1] : C_ADD + // 0011 : w_c_flg : C_FLG + // 0100 : X flag : X_SR + // 0101 : result[7] : N_B + // 0110 : result[15] : N_W + // 0111 : N flag : N_SR + // 1000 : a_src[0] : T0 + // 1001 : a_src[7] : T7 + // 1010 : a_src[15] : T15 + // 1100 : b_src[0] : N0 + // 1101 : b_src[7] : N7 + // 1110 : b_src[15] : N15 + always@(posedge rst or posedge clk) begin : CARRY_INPUT + + if (rst) begin + r_c_in <= 1'b0; + end + else if (clk_ena) begin + case (cin_c) + 4'b0000 : r_c_in <= r_c_in; // Keep flag + 4'b0001 : r_c_in <= 1'b0; // For ASL, LSL, LSR + 4'b0010 : r_c_in <= c_flg[1]; // For ADD.L, SUB.L + 4'b0011 : r_c_in <= w_c_flg; // For ADDX, SUBX, ROXL, ROXR + 4'b0100 : r_c_in <= r_cc_out[4]; // X flag + 4'b0101 : r_c_in <= l_res[7]; // For EXT.W + 4'b0110 : r_c_in <= l_res[15]; // For EXT.L + 4'b0111 : r_c_in <= r_cc_out[3]; // N flag + 4'b1000 : r_c_in <= a_src[0]; // For ROR + 4'b1001 : r_c_in <= a_src[7]; // For ASR.B, ROL.B + 4'b1010 : r_c_in <= a_src[15]; // For ASR.W, ROL.W + 4'b1100 : r_c_in <= b_src[0]; // For ROR.B, ROR.W + 4'b1101 : r_c_in <= b_src[7]; // For ASR.B, ROL.B + 4'b1110 : r_c_in <= b_src[15]; // For ASR.W, ASR.L, ROL.W, ROL.L + default : r_c_in <= 1'b0; + endcase + end + end + assign c_in = r_c_in; + +endmodule diff --git a/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/j68/j68_loop.v b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/j68/j68_loop.v new file mode 100644 index 0000000000000000000000000000000000000000..512feda511640109ed9e653ecc3a0b5bbb55aaee --- /dev/null +++ b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/j68/j68_loop.v @@ -0,0 +1,110 @@ +// Copyright 2011-2018 Frederic Requin +// +// This file is part of the MCC216 project +// +// The J68 core: +// ------------- +// Simple re-implementation of the MC68000 CPU +// The core has the following characteristics: +// - Tested on a Cyclone III (90 MHz) and a Stratix II (180 MHz) +// - from 1500 (~70 MHz) to 1900 LEs (~90 MHz) on Cyclone III +// - 2048 x 20-bit microcode ROM +// - 256 x 28-bit decode ROM +// - 2 x block RAM for the data and instruction stacks +// - stack based CPU with forth-like microcode +// - not cycle-exact : needs a frequency ~3 x higher +// - all 68000 instructions are implemented +// - almost all 68000 exceptions are implemented (only bus error missing) +// - only auto-vector interrupts supported + +module j68_loop +( + // Clock and reset + input rst, // CPU reset + input clk, // CPU clock + /* direct_enable = 1 */ input clk_ena, // CPU clock enable + // Loop control + input [19:0] inst_in, + input i_fetch, // Instruction fetch + input [5:0] a_src, // A source + input [10:0] pc_in, // PC input + output [10:0] pc_out, // PC output + output branch, // Loop taken + output skip, // Loop skipped + output [3:0] lcount // Loop count for MOVEM +); + + reg [10:0] r_loop_st; // Loop start PC + reg [10:0] r_loop_end; // Loop end PC + reg [5:0] r_loop_cnt; // Loop count + reg r_loop_ena; // Loop enable + reg r_branch; // Loop taken + reg [3:0] r_lcount; // Loop count for MOVEM + + always @(posedge rst or posedge clk) begin : HW_LOOP + + if (rst) begin + r_loop_st = 11'd0; + r_loop_end = 11'd0; + r_loop_cnt = 6'd0; + r_loop_ena = 1'b0; + r_branch <= 1'b0; + r_lcount <= 4'd0; + end + else if (clk_ena) begin + // "LOOP" instruction is executed + if (inst_in[19:17] == 3'b000) begin + // Store current PC (start of loop) + r_loop_st = pc_in; + // Store address field (end of loop) + r_loop_end = inst_in[10:0]; + if (inst_in[11]) begin + // "LOOPT" + r_loop_cnt = a_src[5:0] - 6'd1; + // Skipped if T = 0 + r_loop_ena = ~skip; + end + else begin + // "LOOP16" + r_loop_cnt = 6'd15; + // Always executed + r_loop_ena = 1'b1; + end + end + // Loop count for MOVEM + r_lcount <= r_loop_cnt[3:0]; + + if (r_loop_ena) begin + if (i_fetch) begin + // End of loop reached + if (r_loop_end == pc_in) begin + if (r_loop_cnt == 6'd0) begin + // Loop count = 0 : exit loop + r_branch <= 1'b0; + r_loop_ena = 1'b0; + end + else begin + // Loop count > 0 : go on + r_branch <= 1'b1; + r_loop_cnt = r_loop_cnt - 6'd1; + end + end + else begin + r_branch <= 1'b0; + end + end + end + else begin + r_branch <= 1'b0; + end + end + end + + assign branch = r_branch; + assign lcount = r_lcount; + // Loop start PC value + assign pc_out = r_loop_st; + // Loop skipped when T is null and "LOOPT" instruction + assign skip = (a_src[5:0] == 6'd0) ? inst_in[11] : 1'b0; + +endmodule diff --git a/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/j68/j68_mem_io.v b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/j68/j68_mem_io.v new file mode 100644 index 0000000000000000000000000000000000000000..6dcbbf1bbdb5a0b91e487edbeca34e791497c996 --- /dev/null +++ b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/j68/j68_mem_io.v @@ -0,0 +1,603 @@ +// Copyright 2011-2018 Frederic Requin +// +// This file is part of the MCC216 project +// +// The J68 core: +// ------------- +// Simple re-implementation of the MC68000 CPU +// The core has the following characteristics: +// - Tested on a Cyclone III (90 MHz) and a Stratix II (180 MHz) +// - from 1500 (~70 MHz) to 1900 LEs (~90 MHz) on Cyclone III +// - 2048 x 20-bit microcode ROM +// - 256 x 28-bit decode ROM +// - 2 x block RAM for the data and instruction stacks +// - stack based CPU with forth-like microcode +// - not cycle-exact : needs a frequency ~3 x higher +// - all 68000 instructions are implemented +// - almost all 68000 exceptions are implemented (only bus error missing) +// - only auto-vector interrupts supported + +module j68_mem_io +( + // Clock and reset + input rst, // CPU reset + input clk, // CPU clock + /* direct_enable = 1 */ input clk_ena, // CPU clock enable + // Outside bus interface + output rd_ena, // Read strobe + output wr_ena, // Write strobe + input data_ack, // Data acknowledge + output [1:0] byte_ena, // Byte enable + output [31:0] address, // Address bus + input [15:0] rd_data, // Data bus in + output [15:0] wr_data, // Data bus out + // 68000 control + output [2:0] fc, // Function code + input [2:0] ipl_n, // Interrupt level + // I/O bus + input io_rd, // I/O read strobe from J68 micro-core + input io_wr, // I/O write strobe from J68 micro-core + input io_ext, // External memory access + input io_reg, // Read/write to CPU register + output io_rdy, // Data ready to J68 micro-core + output [15:0] io_din, // Data to J68 micro-core + input [15:0] io_dout, // Data from J68 micro-core + input [19:0] inst_in, // Microcode word + // ALU interface (MUL/DIV) + input cc_upd, // Condition codes update + input [3:0] alu_op, // ALU operation + input [15:0] a_src, // A source + input [15:0] b_src, // B source + output v_flg, // V flag from divide + // Decoder data + output [15:0] insw, // Instruction word + output [15:0] extw, // Extension word + output [15:0] ea1b, // EA #1 bitfield + // Status register + input [4:0] ccr_in, // XNZVC 68000 flags + output [10:0] sr_out, // Status register + output [10:0] flg_c, // Flag output control + // Register access + input [3:0] loop_cnt, // Loop count for MOVEM + output reg [5:0] reg_addr, // Register address + output reg reg_wr, // Register write enable + output reg [1:0] reg_bena, // Register byte enable + // Debug + output [31:0] dbg_pc, // Program counter + output dbg_if // Instruction fetch +); + parameter USE_CLK_ENA = 0; + + reg [15:1] r_vec_addr; // Vector address (reg) + reg [31:0] r_pc_addr; // Program counter (reg) + reg [31:0] r_ea1_addr; // Effective address #1 (reg) + reg [31:0] r_ea2_addr; // Effective address #2 (reg) + reg r_v_flg; // Overflow flag from divide + reg [10:0] r_flg_c; // Flag output control + reg [7:0] r_cpu_sr; // Status register high byte (reg) + wire [2:0] w_int_nr; // Interrupt number (wire) + wire w_cc_jump; // Condition code jump flag (wire) + wire [31:0] w_vec_addr; // Vector address (wire) + + reg [15:0] r_md_lsh; // MUL/DIV left shifter (reg) + reg [31:0] r_md_acc; // MUL/DIV accumulator (reg) + wire [31:0] w_md_val; // Multiplier/Divisor (wire) + wire [31:0] w_md_res; // MUL/DIV partial result (wire) + wire w_borrow; // Subtract borrow + + reg r_io_rdy; // Data ready to J68 micro-core + reg [15:0] r_io_din; // Data to J68 micro-core + reg [15:0] r_ins_word; // Instruction word + wire w_ins_rdy; // Instruction word ready + reg [15:0] r_ext_word; // Extension word + wire w_ext_rdy; // Extension word ready + reg [15:0] r_imm_word; // Immediate word + wire w_imm_rdy; // Immediate word ready + wire [15:0] w_imm_val; // Immediate value + wire [11:0] w_dec_jump; // Decoder call address + wire [3:0] w_ea1_jump; // EA #1 jump table index + wire [3:0] w_ea2_jump; // EA #2 jump table index + + reg r_io_ext; // Delayed io_ext + reg [31:0] r_address; // Address bus + reg [2:0] r_fc; // Function code + reg r_mem_rd; // Memory read (reg) + reg r_rd_ena; // Read strobe + reg r_mem_wr; // Memory write (reg) + reg r_wr_ena; // Write strobe + reg [1:0] r_byte_ena; // Byte enable + reg [15:0] r_wr_data; // Data bus out + reg r_mem_err; // Address error during data access (reg) + reg [31:0] r_err_addr; // Address that caused an address error (reg) + reg [15:0] r_err_inst; // Opcode executed during an address error (reg) + reg [4:0] r_err_cpu; // CPU state during an address error (reg) + reg [31:0] w_mem_addr; // Memory address (wire) + reg [2:0] w_mem_inc; // Memory address increment (wire) + wire w_sp_inc; // Memory increment for stack access (wire) + wire [3:0] w_loop_cnt; // Loop count for MOVEM + reg [1:0] r_ctr; + + assign dbg_pc = r_pc_addr; + + assign w_sp_inc = ((r_ins_word[2:0] == 3'b111) && (inst_in[1:0] == 2'b00)) // EA1 with A7 + || ((r_ins_word[11:9] == 3'b111) && (inst_in[1:0] == 2'b01)) // EA2 with A7 + ? 1'b1 : 1'b0; + + // Address MUX and increment + always@(*) begin : MEM_ADDR_MUX + case (inst_in[1:0]) // addr field + 2'b00 : w_mem_addr = r_ea1_addr; // Read/write EA1 data + 2'b01 : w_mem_addr = r_ea2_addr; // Read/write EA2 data + 2'b10 : w_mem_addr = r_pc_addr; // Fetch instruction + 2'b11 : w_mem_addr = w_vec_addr; // Fetch vector + endcase + case ({inst_in[10]|inst_in[11], inst_in[3:2]}) // size & incr fields + // No increment, byte + 3'b000 : w_mem_inc = 3'b000; + // Post increment, word (stack) / byte + 3'b001 : w_mem_inc = (w_sp_inc) ? 3'b010 : 3'b001; + // Pre decrement, word (stack) / byte + 3'b010 : w_mem_inc = (w_sp_inc) ? 3'b110 : 3'b111; + // Pre increment, word (stack) / byte + 3'b011 : w_mem_inc = (w_sp_inc) ? 3'b010 : 3'b001; + // No increment, word + 3'b100 : w_mem_inc = 3'b000; + // Post increment, word + 3'b101 : w_mem_inc = 3'b010; + // Pre decrement, word + 3'b110 : w_mem_inc = 3'b110; + // Pre increment, word + 3'b111 : w_mem_inc = 3'b010; + endcase + end + assign w_vec_addr = { 8'b0, r_vec_addr[15:10], 8'b0, r_vec_addr[9:1], 1'b0 }; + + // Registers read + always@(posedge rst or posedge clk) begin : REG_READ + + if (rst) begin + r_ins_word <= 16'h0000; + r_ext_word <= 16'h0000; + r_imm_word <= 16'h0000; + r_io_din <= 16'h0000; + r_io_rdy <= 1'b0; + r_ctr <= 2'b00; + end + else if (clk_ena) begin + if (io_rd) begin + case (inst_in[3:0]) + // Effective address #1 + 4'b0000 : r_io_din <= r_ea1_addr[15:0]; + 4'b0001 : r_io_din <= r_ea1_addr[31:16]; + // Effective address #2 + 4'b0010 : r_io_din <= r_ea2_addr[15:0]; + 4'b0011 : r_io_din <= r_ea2_addr[31:16]; + // Program + 4'b0100 : r_io_din <= r_pc_addr[15:0]; + 4'b0101 : r_io_din <= r_pc_addr[31:16]; + // Vectors + 4'b0110 : + begin + r_io_din <= { 5'b00000, r_vec_addr[4:2], 8'h00 }; + r_ctr <= 2'b00; + end + // CPU state + 4'b0111 : + begin + case (r_ctr) + 2'b00 : r_io_din <= r_err_inst; + 2'b01 : r_io_din <= r_err_addr[15:0]; + 2'b10 : r_io_din <= r_err_addr[31:16]; + 2'b11 : r_io_din <= {11'b0, r_err_cpu }; + endcase + r_ctr <= r_ctr + 2'd1; + end + // Immediate value + 4'b1000 : r_io_din <= w_imm_val; + // MUL/DIV left shifter + 4'b1001 : r_io_din <= r_md_lsh; + // MUL/DIV accumulator + 4'b1010 : r_io_din <= r_md_acc[15:0]; + 4'b1011 : r_io_din <= r_md_acc[31:16]; + // Jump table indexes + 4'b1100 : r_io_din <= { 4'd0, w_dec_jump }; + 4'b1101 : r_io_din <= { 12'd0, w_ea1_jump }; + 4'b1110 : r_io_din <= { 12'd0, w_ea2_jump }; + // Status register : T-S--III---XNZVC + 4'b1111 : r_io_din <= { r_cpu_sr[7], 1'b0, r_cpu_sr[5], 2'b00, r_cpu_sr[2:0], 3'b000, ccr_in }; + default : r_io_din <= 16'h0000; + endcase + end + else if ((r_mem_rd) && (data_ack)) begin + // Memory read + case ({ inst_in[11:10], address[0] }) + // Byte, even addr. : --- use + 3'b000 : r_io_din <= { rd_data[7:0], rd_data[15:8] }; + // Byte, odd addr. : --- use + 3'b001 : r_io_din <= { rd_data[15:8], rd_data[7:0] }; + // Word, even addr. : use use + 3'b010 : r_io_din <= { rd_data[15:8], rd_data[7:0] }; + // Word, odd addr. : !! exception !! + 3'b011 : r_io_din <= { rd_data[15:8], rd_data[7:0] }; + // LSB, even addr. : --- use + 3'b100 : r_io_din <= { 8'b0000_0000, rd_data[15:8] }; + // LSB, odd addr. : --- use + 3'b101 : r_io_din <= { 8'b0000_0000, rd_data[7:0] }; + // MSB, even addr. : use --- + 3'b110 : r_io_din <= { rd_data[15:8], 8'b0000_0000 }; + // MSB, odd addr. : use --- + 3'b111 : r_io_din <= { rd_data[7:0], 8'b0000_0000 }; + endcase + // Instruction fetch + if (inst_in[1:0] == 2'b10) begin + case (inst_in[3:2]) + 2'b00 : r_ins_word <= rd_data; // Fetching instruction + 2'b01 : r_ext_word <= rd_data; // Fetching extension word + default : r_imm_word <= rd_data; // Fetching immediate data + endcase + end + end + else begin + r_io_din <= 16'h0000; + end + // Ready signal for register read, memory read and write + r_io_rdy <= io_rd | (r_mem_rd & data_ack) | (r_mem_wr & data_ack) | r_mem_err; + end + end + + assign io_rdy = r_io_rdy; + assign io_din = r_io_din; + + // Status bits for the test module : T-SaeIII--b + assign sr_out[10] = r_cpu_sr[7]; // Trace + assign sr_out[9] = 1'b0; // Not used + assign sr_out[8] = r_cpu_sr[5]; // Supervisor + assign sr_out[7] = r_cpu_sr[4]|r_mem_err; // Address error (internal) + assign sr_out[6] = r_cpu_sr[3]|r_cpu_sr[4]|r_mem_err; // Exception (internal) + assign sr_out[5:3] = r_cpu_sr[2:0]; // Interrupt level + assign sr_out[2:1] = 2'b00; // Not used + assign sr_out[0] = w_cc_jump; // Branch flag + + // Registers writes + always@(posedge rst or posedge clk) begin : REG_WRITE + + if (rst) begin + r_vec_addr <= 15'd0; + r_pc_addr <= 32'd0; + r_ea1_addr <= 32'd0; + r_ea2_addr <= 32'd0; + r_md_lsh <= 16'd0; + r_md_acc <= 32'd0; + r_v_flg <= 1'b0; + r_cpu_sr <= 8'b00100111; + r_flg_c <= 11'b00_00_000_00_00; + end + else if (clk_ena) begin + if (io_wr) begin + case (inst_in[3:0]) + // Effective address #1 (and #2 for RMW cycles) + 4'b0000 : begin + r_ea1_addr[15:0] <= io_dout; + r_ea2_addr[15:0] <= io_dout; + end + 4'b0001 : begin + r_ea1_addr[31:16] <= io_dout; + r_ea2_addr[31:16] <= io_dout; + end + // Effective address #2 + 4'b0010 : r_ea2_addr[15:0] <= io_dout; + 4'b0011 : r_ea2_addr[31:16] <= io_dout; + // Program + 4'b0100 : r_pc_addr[15:0] <= io_dout; + 4'b0101 : r_pc_addr[31:16] <= io_dout; + // Vectors + 4'b0110 : begin + r_vec_addr <= io_dout[15:1]; + r_cpu_sr[4] <= 1'b0; // Clear address error + end + 4'b0111 : ; // No VBR on 68000, vector address is 9-bit long ! + // MUL/DIV left shifer + 4'b1001 : r_md_lsh <= io_dout; + // MUL/DIV accumulator + 4'b1010 : r_md_acc[15:0] <= io_dout; + 4'b1011 : r_md_acc[31:16] <= io_dout; + // Status register + 4'b1111 : begin + // MSB (word write) + if (inst_in[10]) begin + r_cpu_sr[7] <= io_dout[15]; // Trace + r_cpu_sr[6] <= 1'b0; + r_cpu_sr[5] <= io_dout[13]; // Supervisor + r_cpu_sr[2:0] <= io_dout[10:8]; // Interrupt mask + end + // LSB + r_flg_c[10] <= 1'b1; + r_flg_c[9] <= io_dout[4]; // Extend flag + r_flg_c[8] <= 1'b1; + r_flg_c[7] <= io_dout[3]; // Negative flag + r_flg_c[6] <= 1'b0; + r_flg_c[5] <= 1'b1; + r_flg_c[4] <= io_dout[2]; // Zero flag + r_flg_c[3] <= 1'b1; + r_flg_c[2] <= io_dout[1]; // Overflow flag + r_flg_c[1] <= 1'b1; + r_flg_c[0] <= io_dout[0]; // Carry flag + end + default : ; + endcase + end + else begin + r_flg_c <= 11'b00_00_000_00_00; + + // Memory control + if ((io_ext) && (!r_io_ext)) begin + // Auto-increment/decrement + case (inst_in[1:0]) // addr field + 2'b00 : r_ea1_addr <= r_ea1_addr + { {29{w_mem_inc[2]}}, w_mem_inc }; + 2'b01 : r_ea2_addr <= r_ea2_addr + { {29{w_mem_inc[2]}}, w_mem_inc }; + 2'b10 : r_pc_addr <= r_pc_addr + 32'd2; + 2'b11 : r_vec_addr[9:1] <= r_vec_addr[9:1] + 9'd1; + endcase + end + + // Multiply/divide step (right shift special) + if (alu_op[3:1] == 3'b111) begin + // Accumulator + if ((alu_op[0]) || (w_borrow)) begin + r_md_acc <= w_md_res; + end + // Left shifter + r_md_lsh <= { r_md_lsh[14:0], w_borrow }; + // V flag + if (cc_upd) r_v_flg <= r_md_lsh[15]; + end + + // Interrupts management + if (((w_int_nr > r_cpu_sr[2:0]) || (w_int_nr == 3'd7)) && (w_int_nr >= r_vec_addr[4:2]) && (r_vec_addr[9:5] == 5'b00011)) begin + r_cpu_sr[3] <= 1'b1; + r_vec_addr[9:1] <= { 5'b00011, w_int_nr, 1'b0 }; + end + else begin + r_cpu_sr[3] <= r_cpu_sr[4] | r_cpu_sr[7]; // Address error or trace mode + end + + // Latch address error flag + if (r_mem_err) r_cpu_sr[4] <= 1'b1; + end + end + end + + assign v_flg = r_v_flg; + assign flg_c = r_flg_c; + + // Interrupt number + assign w_int_nr = ~ipl_n; + + // Multiply/divide step + assign w_md_val = (r_md_lsh[15]) || (!alu_op[0]) ? { b_src, a_src } : 32'd0; + j68_addsub_32 U_addsub + ( + .add_sub (alu_op[0]), + .dataa (r_md_acc), + .datab (w_md_val), + .cout (w_borrow), + .result (w_md_res) + ); + + // Debug : instruction fetch signal + assign dbg_if = (inst_in[3:0] == 4'b0010) ? io_ext & ~r_io_ext : 1'b0; + + // Memory access + always@(posedge rst or posedge clk) begin : MEM_READ_WRITE + + if (rst) begin + r_io_ext <= 1'b0; + r_address <= 32'd0; + r_fc <= 3'b100; + r_mem_rd <= 1'b0; + r_rd_ena <= 1'b0; + r_mem_wr <= 1'b0; + r_wr_ena <= 1'b0; + r_byte_ena <= 2'b00; + r_mem_err <= 1'b0; + r_err_addr <= 32'd0; + r_err_inst <= 16'h0000; + r_err_cpu <= 5'b00000; + r_wr_data <= 16'h0000; + end + else if (clk_ena) begin + // Delayed io_ext + r_io_ext <= io_ext; + // Memory address and data output + if ((io_ext) && (!r_io_ext) && ((!inst_in[3]) || (inst_in[1]))) begin + // No or Post increment + r_address <= w_mem_addr; + // Function code + r_fc[2] <= r_cpu_sr[5]; // 0 : User, 1 : Supervisor + case (inst_in[1:0]) + 2'b00 : r_fc[1:0] <= 2'b01; // EA1 : data + 2'b01 : r_fc[1:0] <= 2'b01; // EA2 : data + 2'b10 : r_fc[1:0] <= 2'b10; // PC : program + 2'b11 : r_fc[1:0] <= 2'b11; // Vector : CPU + endcase + // Memory write + case ({ inst_in[11:10], w_mem_addr[0] }) + // Byte, even addr. : --- use + 3'b000 : r_wr_data <= { io_dout[7:0], io_dout[15:8] }; + // Byte, odd addr. : --- use + 3'b001 : r_wr_data <= { io_dout[15:8], io_dout[7:0] }; + // Word, even addr. : use use + 3'b010 : r_wr_data <= { io_dout[15:8], io_dout[7:0] }; + // Word, odd addr. : !! exception !! + 3'b011 : r_wr_data <= { io_dout[15:8], io_dout[7:0] }; + // LSB, even addr. : use --- + 3'b100 : r_wr_data <= { io_dout[7:0], io_dout[15:8] }; + // LSB, odd addr. : --- use + 3'b101 : r_wr_data <= { io_dout[15:8], io_dout[7:0] }; + // MSB, even addr. : use --- + 3'b110 : r_wr_data <= { io_dout[15:8], io_dout[7:0] }; + // MSB, odd addr. : --- use + 3'b111 : r_wr_data <= { io_dout[7:0], io_dout[15:8] }; + endcase + end + else if ((r_io_ext) && (inst_in[3]) && (!inst_in[1])) begin + // Pre decrement/increment + r_address <= w_mem_addr; + // Function code + r_fc[2] <= r_cpu_sr[5]; // 0 : User, 1 : Supervisor + case (inst_in[1:0]) + 2'b00 : r_fc[1:0] <= 2'b01; // EA1 : data + 2'b01 : r_fc[1:0] <= 2'b01; // EA2 : data + 2'b10 : r_fc[1:0] <= 2'b10; // PC : program + 2'b11 : r_fc[1:0] <= 2'b11; // Vector : CPU + endcase + // Memory write + case ({ inst_in[11:10], w_mem_addr[0] }) + // Byte, even addr. : --- use + 3'b000 : r_wr_data <= { io_dout[7:0], io_dout[15:8] }; + // Byte, odd addr. : --- use + 3'b001 : r_wr_data <= { io_dout[15:8], io_dout[7:0] }; + // Word, even addr. : use use + 3'b010 : r_wr_data <= { io_dout[15:8], io_dout[7:0] }; + // Word, odd addr. : !! exception !! + 3'b011 : r_wr_data <= { io_dout[15:8], io_dout[7:0] }; + // LSB, even addr. : use --- + 3'b100 : r_wr_data <= { io_dout[7:0], io_dout[15:8] }; + // LSB, odd addr. : --- use + 3'b101 : r_wr_data <= { io_dout[15:8], io_dout[7:0] }; + // MSB, even addr. : use --- + 3'b110 : r_wr_data <= { io_dout[15:8], io_dout[7:0] }; + // MSB, odd addr. : --- use + 3'b111 : r_wr_data <= { io_dout[7:0], io_dout[15:8] }; + endcase + end + + // Read, write and byte strobes + if ((io_ext) && (!r_io_ext)) begin + r_mem_rd <= inst_in[7]; + r_mem_wr <= inst_in[6]; + case ({ inst_in[11:10], w_mem_addr[0] }) + 3'b000 : r_byte_ena <= { ~(inst_in[3] & ~inst_in[1]), (inst_in[3] & ~inst_in[1]) }; + 3'b001 : r_byte_ena <= { (inst_in[3] & ~inst_in[1]), ~(inst_in[3] & ~inst_in[1]) }; + 3'b010 : r_byte_ena <= 2'b11; + 3'b011 : // Word access at odd address !! + begin + r_byte_ena <= 2'b00; // No read/write + r_mem_err <= 1'b1; // Address error + r_err_addr <= w_mem_addr; // Keep EA value + r_err_inst <= r_ins_word; // Keep opcode + case (inst_in[1:0]) + 2'b00 : r_err_cpu[1:0] <= 2'b01; // EA1 : data + 2'b01 : r_err_cpu[1:0] <= 2'b01; // EA2 : data + 2'b10 : r_err_cpu[1:0] <= 2'b10; // PC : program + 2'b11 : r_err_cpu[1:0] <= 2'b11; // Vector : CPU + endcase + r_err_cpu[2] <= r_cpu_sr[5]; // 0 : User, 1 : Supervisor + r_err_cpu[3] <= 1'b0; // Instruction identified + r_err_cpu[4] <= inst_in[7]; // 0 : Write, 1 : Read + end + 3'b100 : r_byte_ena <= 2'b10; + 3'b101 : r_byte_ena <= 2'b01; + 3'b110 : r_byte_ena <= 2'b10; + 3'b111 : r_byte_ena <= 2'b01; + endcase + end + + // Keep PC value for address error exception + if ((io_wr) && (inst_in[3:1] == 3'b010)) begin + if (inst_in[0]) + r_err_addr[31:16] <= io_dout; + else + r_err_addr[15:0] <= io_dout; + // Address error if odd address on PC + if ((!inst_in[0]) && (io_dout[0])) begin + r_mem_err <= 1'b1; // Address error + r_err_inst <= r_ins_word; // Keep opcode + r_err_cpu <= { 2'b10, r_cpu_sr[5], 2'b10 }; + end + end + + // End of memory cycle : acknowledge or error + if ((data_ack) || (r_mem_err)) begin + r_mem_rd <= 1'b0; + r_rd_ena <= 1'b0; + r_mem_wr <= 1'b0; + r_wr_ena <= 1'b0; + r_byte_ena <= 2'b00; + r_mem_err <= 1'b0; + r_fc <= { r_cpu_sr[5], 2'b00 }; // No access + end + else begin + r_rd_ena <= (inst_in[7] & (~inst_in[3] | inst_in[1]) & io_ext) | r_mem_rd; + r_wr_ena <= (inst_in[6] & (~inst_in[3] | inst_in[1]) & io_ext) | r_mem_wr; + end + end + end + + // Outside bus interface + assign fc = r_fc; + assign rd_ena = r_rd_ena; + assign wr_ena = r_wr_ena; + assign byte_ena = r_byte_ena; + assign address = r_address; + assign wr_data = r_wr_data; + + // Instruction decoder + assign w_ins_rdy = (inst_in[3:0] == 4'b0010) ? (r_io_rdy & r_io_ext) : 1'b0; + assign w_ext_rdy = (inst_in[3:0] == 4'b0110) ? (r_io_rdy & r_io_ext) : 1'b0; + assign w_imm_rdy = (inst_in[3:0] == 4'b1010) ? (r_io_rdy & r_io_ext) : 1'b0; + + j68_decode + #( + .USE_CLK_ENA (USE_CLK_ENA) + ) + U_decode + ( + .rst (rst), + .clk (clk), + .clk_ena (1'b1), + .ins_rdy (w_ins_rdy), + .instr (r_ins_word), + .ext_rdy (w_ext_rdy), + .ext_wd (r_ext_word), + .imm_rdy (w_imm_rdy), + .imm_wd (r_imm_word), + .user_mode (~r_cpu_sr[5]), + .ccr_in (ccr_in[3:0]), + .dec_jmp (w_dec_jump), + .ea1_jmp (w_ea1_jump), + .ea2_jmp (w_ea2_jump), + .imm_val (w_imm_val), + .ea1_bit (ea1b), + .cc_jmp (w_cc_jump), + .ext_inst (), + .bit_inst (), + .vld_inst () + ); + assign insw = r_ins_word; + assign extw = r_ext_word; + + // Registers access + assign w_loop_cnt = ea1b[4] ? loop_cnt : ~loop_cnt; + always@(*) begin : REG_ADDR + + case (inst_in[3:0]) + 4'b0000 : reg_addr = { 2'b10, r_ins_word[2:0], inst_in[8] }; // D[EA1] + 4'b0001 : reg_addr = { 2'b11, r_ins_word[2:0], inst_in[8] }; // A[EA1] + 4'b0010 : reg_addr = { 1'b1, r_ins_word[3:0], inst_in[8] }; // R[EA1] + 4'b0011 : reg_addr = { 5'b11111, inst_in[8] }; // A7 + 4'b0100 : reg_addr = { 2'b10, r_ins_word[11:9], inst_in[8] }; // D[EA2] + 4'b0101 : reg_addr = { 2'b11, r_ins_word[11:9], inst_in[8] }; // A[EA2] + 4'b0110 : reg_addr = { 1'b1, r_ins_word[6], r_ins_word[11:9], inst_in[8] }; // R[EA2] + 4'b0111 : reg_addr = { 1'b1, w_loop_cnt, inst_in[8] }; // R[CNT] + 4'b1000 : reg_addr = { 2'b10, r_ext_word[14:12], inst_in[8] }; // D[EXT] + 4'b1001 : reg_addr = { 2'b11, r_ext_word[14:12], inst_in[8] }; // A[EXT] + 4'b1010 : reg_addr = { 1'b1, r_ext_word[15:12], inst_in[8] }; // R[EXT] + default : reg_addr = { 2'b01, inst_in[2:0], inst_in[8] }; // VBR, TMP1, TMP2, USP, SSP + endcase + reg_wr = inst_in[6] & io_reg; + reg_bena[0] = io_reg; + reg_bena[1] = inst_in[10] & io_reg; + end + +endmodule diff --git a/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/j68/j68_ram_c.mem b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/j68/j68_ram_c.mem new file mode 100644 index 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b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/j68/j68_test.v @@ -0,0 +1,55 @@ +// Copyright 2011-2018 Frederic Requin +// +// This file is part of the MCC216 project +// +// The J68 core: +// ------------- +// Simple re-implementation of the MC68000 CPU +// The core has the following characteristics: +// - Tested on a Cyclone III (90 MHz) and a Stratix II (180 MHz) +// - from 1500 (~70 MHz) to 1900 LEs (~90 MHz) on Cyclone III +// - 2048 x 20-bit microcode ROM +// - 256 x 28-bit decode ROM +// - 2 x block RAM for the data and instruction stacks +// - stack based CPU with forth-like microcode +// - not cycle-exact : needs a frequency ~3 x higher +// - all 68000 instructions are implemented +// - almost all 68000 exceptions are implemented (only bus error missing) +// - only auto-vector interrupts supported + +module j68_test +( + // Micro-instruction word + input [19:0] inst_in, + // Operand input + input [3:0] flg_in, // Partial flags + input [15:0] sr_in, // Status register + input [15:0] a_src, // A operand + input [15:0] ea1b, // EA #1 bitfield + input [15:0] extw, // Extension word + // Test output + output reg branch // Branch taken +); + + always@(*) begin : BRANCH_FLAG + + case (inst_in[15:12]) + 4'b0000 : branch = inst_in[11] ^ sr_in[12]; // Address error + 4'b0001 : branch = inst_in[11] ^ flg_in[1]; // Z_FLG : Partial zero (for CHK, Bcc and DBcc) + 4'b0010 : branch = inst_in[11] ^ flg_in[2]; // N_FLG : Partial negative (for MULS, DIVS, ABCD and SBCD) + 4'b0011 : branch = inst_in[11] ^ flg_in[3]; // G_FLG : Greater than (for CHK) + 4'b0100 : branch = inst_in[11] ^ a_src[0]; // T[0] (for MOVEM) + 4'b0101 : branch = inst_in[11] ^ ea1b[4]; // (An)+ addressing + 4'b0110 : branch = inst_in[11] ^ ea1b[7]; // Dn/An addressing + 4'b0111 : branch = inst_in[11] ^ extw[11]; // Long/Word for d8(An,Rn) + 4'b1000 : branch = inst_in[11] ^ sr_in[1]; // V flag + 4'b1001 : branch = inst_in[11] ^ sr_in[3]; // N flag + 4'b1010 : branch = inst_in[11] ^ sr_in[5]; // Branch flag (for DBcc and Bcc) + 4'b1011 : branch = inst_in[11] ^ sr_in[11]; // Interrupt flag + 4'b1100 : branch = inst_in[11] ^ sr_in[13]; // Supervisor flag + 4'b1101 : branch = inst_in[11] ^ sr_in[15]; // Trace flag + default : branch = 1'b1; // Always + endcase + end + +endmodule diff --git a/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/j68/jtframe_j68.v b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/j68/jtframe_j68.v new file mode 100644 index 0000000000000000000000000000000000000000..f3f3587e938b498da2c8c7c7c23f5d568cec6ea3 --- /dev/null +++ b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/j68/jtframe_j68.v @@ -0,0 +1,119 @@ +/* This file is part of JTFRAME. + JTFRAME program is free software: you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation, either version 3 of the License, or + (at your option) any later version. + + JTFRAME program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with JTFRAME. If not, see . + + Author: Jose Tejada Gomez. Twitter: @topapate + Version: 1.0 + Date: 30-5-2021 */ + +module jtframe_j68( + input clk, + input rst, + + input HALTn, + + output [23:1] eab, + output reg ASn, + output LDSn, + output UDSn, + output eRWn, + input DTACKn, + + // Data bus + input [15:0] iEdb, + output [15:0] oEdb, + + // Bus sharing + input BRn, + input BGACKn, + output reg BGn=1, + + // interrupts + input IPL0n, + input IPL1n, + input IPL2n, + + // state + output FC0, + output FC1, + output FC2 +); + +reg cen=0; + +wire [1:0] byte_ena; // Byte enable +wire [31:0] address; // Address bus +wire [2:0] fc, // Function code + ipl_n; // Interrupt level +wire data_ack, rd_ena, wr_ena; + +assign {FC2,FC1,FC0} = fc; +assign ipl_n = { IPL2n, IPL1n, IPL0n }; +assign {UDSn,LDSn} = ~byte_ena; +assign data_ack = ~DTACKn; +assign eRWn = ~wr_ena; +assign eab = address[23:1]; + +always @(posedge clk) begin + // During memory access (ASn low), we need to introduce some + // idle cycles (cen at 50%) for J68 to work well with the external glue logic + cen <= rst | ((~cen | ASn) & HALTn & BGn); + if( ASn && !BRn ) BGn <= 0; + if( BRn ) BGn <= 1; +end + +always @(posedge clk) begin + if( rst ) + ASn <= 1; + else begin + if( rd_ena | wr_ena ) + ASn <= 0; + else if( data_ack ) + ASn <= 1; + end +end + + +cpu_j68 #(.USE_CLK_ENA(1)) u_j68 +( + // Clock and reset + .rst ( rst ), + .clk ( clk ), + .clk_ena ( cen ), // CPU clock enable + // Bus interface + .rd_ena ( rd_ena ), // Read strobe + .wr_ena ( wr_ena ), // Write strobe + .data_ack ( data_ack ), // Data acknowledge + .byte_ena ( byte_ena ), // Byte enable + .address ( address ), // Address bus + .rd_data ( iEdb ), // Data bus in + .wr_data ( oEdb ), // Data bus out + // 68000 control + .fc ( fc ), // Function code + .ipl_n ( ipl_n ), // Interrupt level + + // 68000 debug - unused + .dbg_reg_addr (), // Register address + .dbg_reg_wren (), // Register write enable + .dbg_reg_data (), // Register write data + .dbg_sr_reg (), // Status register + .dbg_pc_reg (), // Program counter + .dbg_usp_reg (), // User stack pointer + .dbg_ssp_reg (), // Supervisor stack pointer + .dbg_vbr_reg (), // Vector base register + .dbg_cycles (), // Cycles counter + .dbg_ifetch (), // Instruction fetch + .dbg_irq_lvl () // Interrupt level +); + +endmodule \ No newline at end of file diff --git a/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/mc6502/LICENSE b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/mc6502/LICENSE new file mode 100644 index 0000000000000000000000000000000000000000..fa6fc7c937796788842e593c99f6737d8eb792ec --- /dev/null +++ b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/mc6502/LICENSE @@ -0,0 +1,28 @@ +Copyright (c) 2014, Takashi Toyoshima +All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + +* Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + +* Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + +* Neither the name of mc6502 nor the names of its + contributors may be used to endorse or promote products derived from + this software without specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + diff --git a/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/mc6502/MC6502.v b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/mc6502/MC6502.v new file mode 100644 index 0000000000000000000000000000000000000000..8507d67b507d0b0ae85e1ce425f9db822b53267d --- /dev/null +++ b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/mc6502/MC6502.v @@ -0,0 +1,340 @@ +// Copyright (c) 2014 Takashi Toyoshima . +// All rights reserved. Use of this source code is governed by a BSD-style +// license that can be found in the LICENSE file. + +// Modifications by Jose Tejada 2021 +// * Remove high-Z port +// * Remove clk1 clk2 outputs +// * Added clock enable signal + +module MC6502( + clk, + cen, + rstn, + i_rdy, + i_irqn, + i_nmin, + i_db, + o_db, + + o_sync, + o_rw, + o_ab); + input clk; + input cen; + input rstn; + input i_rdy; + input i_irqn; + input i_nmin; + input [ 7:0] i_db; + output [ 7:0] o_db; + output o_sync; + output o_rw; + output [15:0] o_ab; + + // InterruptLogic <=> MemoryController + wire [ 7:0] w_mc2il_data; + wire w_mc2il_brk; + wire [15:0] w_il2mc_addr; + wire w_il2mc_read; + wire w_il2mc_write; + wire [ 7:0] w_il2mc_data; + + // InterruptLogic <=> RegisterFile + wire [ 7:0] w_rf2il_s; + wire [ 7:0] w_rf2il_psr; + wire [15:0] w_rf2il_pc; + wire w_il2rf_set_i; + wire w_il2rf_set_b; + wire [ 7:0] w_il2rf_data; + wire w_il2rf_set_pcl; + wire w_il2rf_set_pch; + wire w_il2rf_pushed; + + // RegisterFile <=> MemoryController + wire [15:0] w_rf2mc_pc; + wire [ 7:0] w_rf2mc_a; + wire [ 7:0] w_rf2mc_x; + wire [ 7:0] w_rf2mc_y; + wire [ 7:0] w_rf2mc_s; + wire [ 7:0] w_rf2mc_psr; + wire w_mc2rf_fetched; + wire w_mc2rf_pushed; + wire w_mc2rf_pull; + wire [15:0] w_mc2rf_pc; + wire w_mc2rf_set_pc; + wire [ 7:0] w_mc2rf_psr; + wire w_mc2rf_set_psr; + + // InstructionDecode <=> MemoryController + wire [ 7:0] w_mc2id_data; + wire w_mc2id_valid; + wire w_id2mc_fetch; + wire w_id2mc_sync; + wire w_id2mc_operand; + wire [ 2:0] w_id2mc_mode; + wire w_id2mc_modex; + wire [ 1:0] w_id2mc_reg; + wire w_id2mc_store; + wire w_id2mc_push; + wire w_id2mc_pop; + wire w_id2mc_p_reg; + wire w_id2mc_jump; + + // InstructionDecode <=> ExecutionController + wire w_id2ec_reset_c; + wire w_id2ec_set_c; + wire w_id2ec_reset_i; + wire w_id2ec_set_i; + wire w_id2ec_reset_v; + wire w_id2ec_reset_d; + wire w_id2ec_set_d; + wire w_id2ec_load; + wire w_id2ec_ops; + wire w_id2ec_branch; + wire [ 4:0] w_id2ec_opcode; + wire [ 7:0] w_id2ec_data; + wire [ 1:0] w_id2ec_reg; + wire w_ec2id_done; + + // ExecutionController <=> RegisterFile + wire [ 7:0] w_rf2ec_pcl; + wire [ 7:0] w_rf2ec_pch; + wire [ 7:0] w_rf2ec_a; + wire [ 7:0] w_rf2ec_x; + wire [ 7:0] w_rf2ec_y; + wire w_rf2ec_c; + wire w_rf2ec_d; + wire w_rf2ec_n; + wire w_rf2ec_v; + wire w_rf2ec_z; + wire w_ec2rf_c; + wire w_ec2rf_set_c; + wire w_ec2rf_i; + wire w_ec2rf_set_i; + wire w_ec2rf_v; + wire w_ec2rf_set_v; + wire w_ec2rf_d; + wire w_ec2rf_set_d; + wire w_ec2rf_n; + wire w_ec2rf_set_n; + wire w_ec2rf_z; + wire w_ec2rf_set_z; + wire [ 7:0] w_ec2rf_data; + wire w_ec2rf_set_a; + wire w_ec2rf_set_x; + wire w_ec2rf_set_y; + wire w_ec2rf_set_s; + wire w_ec2rf_set_pcl; + wire w_ec2rf_set_pch; + + // ExecutionController <=> MemoryController + wire [ 7:0] w_ec2mc_data; + wire w_ec2mc_store; + + MC6502MemoryController mc( + .clk (clk ), + .cen (cen ), + .rstn (rstn ), + .i_rdy (i_rdy ), + .i_db (i_db ), + .o_db (o_db ), + .o_ab (o_ab ), + .o_rw (o_rw ), + .o_sync (o_sync ), + .il2mc_addr (w_il2mc_addr ), + .il2mc_read (w_il2mc_read ), + .il2mc_write (w_il2mc_write ), + .il2mc_data (w_il2mc_data ), + .mc2il_data (w_mc2il_data ), + .mc2il_brk (w_mc2il_brk ), + .rf2mc_pc (w_rf2mc_pc ), + .rf2mc_a (w_rf2mc_a ), + .rf2mc_x (w_rf2mc_x ), + .rf2mc_y (w_rf2mc_y ), + .rf2mc_s (w_rf2mc_s ), + .rf2mc_psr (w_rf2mc_psr ), + .mc2rf_fetched(w_mc2rf_fetched), + .mc2rf_pushed (w_mc2rf_pushed ), + .mc2rf_pull (w_mc2rf_pull ), + .mc2rf_pc (w_mc2rf_pc ), + .mc2rf_set_pc (w_mc2rf_set_pc ), + .mc2rf_psr (w_mc2rf_psr ), + .mc2rf_set_psr(w_mc2rf_set_psr), + .id2mc_fetch (w_id2mc_fetch ), + .id2mc_sync (w_id2mc_sync ), + .id2mc_operand(w_id2mc_operand), + .id2mc_mode (w_id2mc_mode ), + .id2mc_modex (w_id2mc_modex ), + .id2mc_reg (w_id2mc_reg ), + .id2mc_store (w_id2mc_store ), + .id2mc_push (w_id2mc_push ), + .id2mc_pop (w_id2mc_pop ), + .id2mc_p_reg (w_id2mc_p_reg ), + .id2mc_jump (w_id2mc_jump ), + .mc2id_data (w_mc2id_data ), + .mc2id_valid (w_mc2id_valid ), + .ec2mc_data (w_ec2mc_data ), + .ec2mc_store (w_ec2mc_store )); + + MC6502InterruptLogic il( + .clk (clk ), + .cen (cen ), + .rstn (rstn ), + .i_irqn (i_irqn ), + .i_nmin (i_nmin ), + .mc2il_data (w_mc2il_data ), + .mc2il_brk (w_mc2il_brk ), + .il2mc_addr (w_il2mc_addr ), + .il2mc_read (w_il2mc_read ), + .il2mc_write (w_il2mc_write ), + .il2mc_data (w_il2mc_data ), + .rf2il_s (w_rf2il_s ), + .rf2il_psr (w_rf2il_psr ), + .rf2il_pc (w_rf2il_pc ), + .il2rf_set_i (w_il2rf_set_i ), + .il2rf_set_b (w_il2rf_set_b ), + .il2rf_data (w_il2rf_data ), + .il2rf_set_pcl(w_il2rf_set_pcl), + .il2rf_set_pch(w_il2rf_set_pch), + .il2rf_pushed (w_il2rf_pushed )); + + MC6502RegisterFile rf( + .clk (clk ), + .cen (cen ), + .rstn (rstn ), + .il2rf_set_i (w_il2rf_set_i ), + .il2rf_set_b (w_il2rf_set_b ), + .il2rf_data (w_il2rf_data ), + .il2rf_set_pcl(w_il2rf_set_pcl), + .il2rf_set_pch(w_il2rf_set_pch), + .il2rf_pushed (w_il2rf_pushed ), + .rf2il_s (w_rf2il_s ), + .rf2il_psr (w_rf2il_psr ), + .rf2il_pc (w_rf2il_pc ), + .mc2rf_fetched(w_mc2rf_fetched), + .mc2rf_pushed (w_mc2rf_pushed ), + .mc2rf_pull (w_mc2rf_pull ), + .mc2rf_pc (w_mc2rf_pc ), + .mc2rf_set_pc (w_mc2rf_set_pc ), + .mc2rf_psr (w_mc2rf_psr ), + .mc2rf_set_psr(w_mc2rf_set_psr), + .rf2mc_pc (w_rf2mc_pc ), + .rf2mc_a (w_rf2mc_a ), + .rf2mc_x (w_rf2mc_x ), + .rf2mc_y (w_rf2mc_y ), + .rf2mc_s (w_rf2mc_s ), + .rf2mc_psr (w_rf2mc_psr ), + .ec2rf_c (w_ec2rf_c ), + .ec2rf_set_c (w_ec2rf_set_c ), + .ec2rf_i (w_ec2rf_i ), + .ec2rf_set_i (w_ec2rf_set_i ), + .ec2rf_v (w_ec2rf_v ), + .ec2rf_set_v (w_ec2rf_set_v ), + .ec2rf_d (w_ec2rf_d ), + .ec2rf_set_d (w_ec2rf_set_d ), + .ec2rf_n (w_ec2rf_n ), + .ec2rf_set_n (w_ec2rf_set_n ), + .ec2rf_z (w_ec2rf_z ), + .ec2rf_set_z (w_ec2rf_set_z ), + .ec2rf_data (w_ec2rf_data ), + .ec2rf_set_a (w_ec2rf_set_a ), + .ec2rf_set_x (w_ec2rf_set_x ), + .ec2rf_set_y (w_ec2rf_set_y ), + .ec2rf_set_s (w_ec2rf_set_s ), + .ec2rf_set_pcl(w_ec2rf_set_pcl), + .ec2rf_set_pch(w_ec2rf_set_pch), + .rf2ec_pcl (w_rf2ec_pcl ), + .rf2ec_pch (w_rf2ec_pch ), + .rf2ec_a (w_rf2ec_a ), + .rf2ec_x (w_rf2ec_x ), + .rf2ec_y (w_rf2ec_y ), + .rf2ec_c (w_rf2ec_c ), + .rf2ec_d (w_rf2ec_d ), + .rf2ec_n (w_rf2ec_n ), + .rf2ec_v (w_rf2ec_v ), + .rf2ec_z (w_rf2ec_z )); + + MC6502InstructionDecode id( + .clk (clk ), + .cen (cen ), + .rstn (rstn ), + .mc2id_data (w_mc2id_data ), + .mc2id_valid (w_mc2id_valid ), + .id2mc_fetch (w_id2mc_fetch ), + .id2mc_sync (w_id2mc_sync ), + .id2mc_operand(w_id2mc_operand), + .id2mc_mode (w_id2mc_mode ), + .id2mc_modex (w_id2mc_modex ), + .id2mc_reg (w_id2mc_reg ), + .id2mc_store (w_id2mc_store ), + .id2mc_push (w_id2mc_push ), + .id2mc_pop (w_id2mc_pop ), + .id2mc_p_reg (w_id2mc_p_reg ), + .id2mc_jump (w_id2mc_jump ), + .id2ec_reset_c(w_id2ec_reset_c), + .id2ec_set_c (w_id2ec_set_c ), + .id2ec_reset_i(w_id2ec_reset_i), + .id2ec_set_i (w_id2ec_set_i ), + .id2ec_reset_v(w_id2ec_reset_v), + .id2ec_reset_d(w_id2ec_reset_d), + .id2ec_set_d (w_id2ec_set_d ), + .id2ec_load (w_id2ec_load ), + .id2ec_ops (w_id2ec_ops ), + .id2ec_branch (w_id2ec_branch ), + .id2ec_opcode (w_id2ec_opcode ), + .id2ec_data (w_id2ec_data ), + .id2ec_reg (w_id2ec_reg ), + .ec2id_done (w_ec2id_done )); + + MC6502ExecutionController ec( + .clk (clk ), + .cen (cen ), + .rstn (rstn ), + .id2ec_reset_c(w_id2ec_reset_c), + .id2ec_set_c (w_id2ec_set_c ), + .id2ec_reset_i(w_id2ec_reset_i), + .id2ec_set_i (w_id2ec_set_i ), + .id2ec_reset_v(w_id2ec_reset_v), + .id2ec_reset_d(w_id2ec_reset_d), + .id2ec_set_d (w_id2ec_set_d ), + .id2ec_load (w_id2ec_load ), + .id2ec_ops (w_id2ec_ops ), + .id2ec_branch (w_id2ec_branch ), + .id2ec_opcode (w_id2ec_opcode ), + .id2ec_data (w_id2ec_data ), + .id2ec_reg (w_id2ec_reg ), + .ec2id_done (w_ec2id_done ), + .rf2ec_pcl (w_rf2ec_pcl ), + .rf2ec_pch (w_rf2ec_pch ), + .rf2ec_a (w_rf2ec_a ), + .rf2ec_x (w_rf2ec_x ), + .rf2ec_y (w_rf2ec_y ), + .rf2ec_c (w_rf2ec_c ), + .rf2ec_d (w_rf2ec_d ), + .rf2ec_n (w_rf2ec_n ), + .rf2ec_v (w_rf2ec_v ), + .rf2ec_z (w_rf2ec_z ), + .ec2rf_c (w_ec2rf_c ), + .ec2rf_set_c (w_ec2rf_set_c ), + .ec2rf_i (w_ec2rf_i ), + .ec2rf_set_i (w_ec2rf_set_i ), + .ec2rf_v (w_ec2rf_v ), + .ec2rf_set_v (w_ec2rf_set_v ), + .ec2rf_d (w_ec2rf_d ), + .ec2rf_set_d (w_ec2rf_set_d ), + .ec2rf_n (w_ec2rf_n ), + .ec2rf_set_n (w_ec2rf_set_n ), + .ec2rf_z (w_ec2rf_z ), + .ec2rf_set_z (w_ec2rf_set_z ), + .ec2rf_data (w_ec2rf_data ), + .ec2rf_set_a (w_ec2rf_set_a ), + .ec2rf_set_x (w_ec2rf_set_x ), + .ec2rf_set_y (w_ec2rf_set_y ), + .ec2rf_set_s (w_ec2rf_set_s ), + .ec2rf_set_pcl(w_ec2rf_set_pcl), + .ec2rf_set_pch(w_ec2rf_set_pch), + .ec2mc_data (w_ec2mc_data ), + .ec2mc_store (w_ec2mc_store )); + +endmodule // MC6502 diff --git a/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/mc6502/MC6502Accumulator.v b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/mc6502/MC6502Accumulator.v new file mode 100644 index 0000000000000000000000000000000000000000..33daec89d8c570fd19e729104812c614cc537bde --- /dev/null +++ b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/mc6502/MC6502Accumulator.v @@ -0,0 +1,53 @@ +// Copyright (c) 2014 Takashi Toyoshima . +// All rights reserved. Use of this source code is governed by a BSD-style +// license that can be found in the LICENSE file. + +module MC6502Accumulator( + i_a, + i_m, + i_c, + i_d, + i_s, + o_a, + o_n, + o_z, + o_c, + o_v); + input [7:0] i_a; + input [7:0] i_m; + input i_c; + input i_d; + input i_s; + output [7:0] o_a; + output o_n; + output o_z; + output o_c; + output o_v; + + wire [7:0] w_m; + wire [4:0] w_bsum_lo; + wire [4:0] w_dsum_lo; + wire [4:0] w_bsum_hi; + wire [4:0] w_dsum_hi; + wire [4:0] w_sum_low; + wire [4:0] w_sum_high; + wire w_dover_lo; + wire w_carry; + wire [3:0] w_fix; + + assign w_m = i_s ? ~i_m : i_m; + assign w_fix = i_s ? 4'ha : 4'h6; + assign w_bsum_lo = i_a[3:0] + w_m[3:0] + { 3'b000, i_c }; + assign w_dover_lo = w_bsum_lo > 5'h9; + assign w_dsum_lo = w_dover_lo ? (w_bsum_lo + w_fix) : w_bsum_lo; + assign w_sum_low = i_d ? w_dsum_lo : w_bsum_lo; + assign w_carry = i_d ? w_dover_lo ^ i_s : w_sum_low[4]; + assign w_bsum_hi = i_a[7:4] + w_m[7:4] + { 3'b000, w_carry }; + assign w_dsum_hi = (w_bsum_hi[3:0] < 4'ha) ? w_bsum_hi : (w_bsum_hi + w_fix); + assign w_sum_high = i_d ? w_dsum_hi : w_bsum_hi; + assign o_a = { w_sum_high[3:0], w_sum_low[3:0] }; + assign o_n = o_a[7]; + assign o_z = o_a == 8'h00; + assign o_c = w_sum_high[4]; + assign o_v = (!(i_a[7] ^ w_m[7]) & (i_a[7] ^ o_a[7])); +endmodule // MC6502Accumulator diff --git a/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/mc6502/MC6502Common.vh b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/mc6502/MC6502Common.vh new file mode 100644 index 0000000000000000000000000000000000000000..c22a803a79b2d8a8e20954cd1662b23422e3158f --- /dev/null +++ b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/mc6502/MC6502Common.vh @@ -0,0 +1,84 @@ +// Copyright (c) 2014 Takashi Toyoshima . +// All rights reserved. Use of this source code is governed by a BSD-style +// license that can be found in the LICENSE file. + +localparam MODE_INDEXED_INDIRECT = 3'b000; +localparam MODE_ZERO_PAGE = 3'b001; +localparam MODE_IMMEDIATE = 3'b010; +localparam MODE_ABSOLUTE = 3'b011; +localparam MODE_INDIRECT_INDEX = 3'b100; +localparam MODE_ZERO_PAGE_INDEX_X = 3'b101; +localparam MODE_ABSOLUTE_INDEXED_Y = 3'b110; +localparam MODE_ABSOLUTE_INDEXED_X = 3'b111; + +localparam MODEX_IMMEDIATE = 3'b000; +localparam MODEX_ZERO_PAGE = 3'b001; +localparam MODEX_REGISTER = 3'b010; +localparam MODEX_ABSOLUTE = 3'b011; +localparam MODEX_ABSOLUTE_PC = 3'b011; +localparam MODEX_INDIRECT_PC = 3'b100; +localparam MODEX_ZERO_PAGE_INDEX_Y = 3'b101; +localparam MODEX_ABSOLUTE_INDEXED_Y = 3'b111; + +localparam REG_A = 2'b00; +localparam REG_X = 2'b01; +localparam REG_Y = 2'b10; +localparam REG_S = 2'b11; + +localparam P_REG_A = 1'b0; +localparam P_REG_PSR = 1'b1; + +// xxx1_0000 +localparam OP_BPL = 3'b000; +localparam OP_BMI = 3'b001; +localparam OP_BVC = 3'b010; +localparam OP_BVS = 3'b011; +localparam OP_BCC = 3'b100; +localparam OP_BCS = 3'b101; +localparam OP_BNE = 3'b110; +localparam OP_BEQ = 3'b111; + +// xxx0_0000 +localparam OP_BRK = 3'b000; +localparam OP_JSR = 3'b001; +localparam OP_RTI = 3'b010; +localparam OP_RTS = 3'b011; + +// xxx0_1000 [11] +localparam OP_PHP = 3'b000; +localparam OP_PLP = 3'b001; +localparam OP_PHA = 3'b010; +localparam OP_PLA = 3'b011; +localparam OP_DEY = 3'b100; +localparam OP_TAY = 3'b101; +localparam OP_INY = 3'b110; +localparam OP_INX = 3'b111; + +// xxxy_yy01 [01] +localparam OP_ORA = 3'b000; +localparam OP_AND = 3'b001; +localparam OP_EOR = 3'b010; +localparam OP_ADC = 3'b011; +localparam OP_STA = 3'b100; +localparam OP_LDA = 3'b101; +localparam OP_CMP = 3'b110; +localparam OP_SBC = 3'b111; + +// xxxy_yy10 [10] +localparam OP_ASL = 3'b000; +localparam OP_ROL = 3'b001; +localparam OP_LSR = 3'b010; +localparam OP_ROR = 3'b011; +localparam OP_STX = 3'b100; +localparam OP_LDX = 3'b101; +localparam OP_DEC = 3'b110; +localparam OP_INC = 3'b111; + +// xxxy_yy00 [00] +localparam OP_BIT = 3'b001; +localparam OP_JMP_ABS = 3'b010; +localparam OP_JMP_IND = 3'b011; +localparam OP_STY = 3'b100; +localparam OP_LDY = 3'b101; +localparam OP_CPY = 3'b110; +localparam OP_CPX = 3'b111; diff --git a/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/mc6502/MC6502ExecutionController.v b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/mc6502/MC6502ExecutionController.v new file mode 100644 index 0000000000000000000000000000000000000000..a090a4ab7543ea011399b4c0bfa3967f950501a3 --- /dev/null +++ b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/mc6502/MC6502ExecutionController.v @@ -0,0 +1,348 @@ +// Copyright (c) 2014 Takashi Toyoshima . +// All rights reserved. Use of this source code is governed by a BSD-style +// license that can be found in the LICENSE file. + +module MC6502ExecutionController( + clk, + cen, + rstn, + // InstructionDecode interfaces + id2ec_reset_c, + id2ec_set_c, + id2ec_reset_i, + id2ec_set_i, + id2ec_reset_v, + id2ec_reset_d, + id2ec_set_d, + id2ec_load, + id2ec_ops, + id2ec_branch, + id2ec_opcode, + id2ec_data, + id2ec_reg, + ec2id_done, + // RegisterFile interfaces + rf2ec_pcl, + rf2ec_pch, + rf2ec_a, + rf2ec_x, + rf2ec_y, + rf2ec_c, + rf2ec_d, + rf2ec_n, + rf2ec_v, + rf2ec_z, + ec2rf_c, + ec2rf_set_c, + ec2rf_i, + ec2rf_set_i, + ec2rf_v, + ec2rf_set_v, + ec2rf_d, + ec2rf_set_d, + ec2rf_n, + ec2rf_set_n, + ec2rf_z, + ec2rf_set_z, + ec2rf_data, + ec2rf_set_a, + ec2rf_set_x, + ec2rf_set_y, + ec2rf_set_s, + ec2rf_set_pcl, + ec2rf_set_pch, + // MemoryController interfaces + ec2mc_data, + ec2mc_store); + input clk; + input cen; + input rstn; + + input id2ec_reset_c; + input id2ec_set_c; + input id2ec_reset_i; + input id2ec_set_i; + input id2ec_reset_v; + input id2ec_reset_d; + input id2ec_set_d; + input id2ec_load; + input id2ec_ops; + input id2ec_branch; + input [4:0] id2ec_opcode; + input [7:0] id2ec_data; + input [1:0] id2ec_reg; + output ec2id_done; + + input [7:0] rf2ec_pcl; + input [7:0] rf2ec_pch; + input [7:0] rf2ec_a; + input [7:0] rf2ec_x; + input [7:0] rf2ec_y; + input rf2ec_c; + input rf2ec_d; + input rf2ec_n; + input rf2ec_v; + input rf2ec_z; + output ec2rf_c; + output ec2rf_set_c; + output ec2rf_i; + output ec2rf_set_i; + output ec2rf_v; + output ec2rf_set_v; + output ec2rf_d; + output ec2rf_set_d; + output ec2rf_n; + output ec2rf_set_n; + output ec2rf_z; + output ec2rf_set_z; + output [7:0] ec2rf_data; + output ec2rf_set_a; + output ec2rf_set_x; + output ec2rf_set_y; + output ec2rf_set_s; + output ec2rf_set_pcl; + output ec2rf_set_pch; + + output [7:0] ec2mc_data; + output ec2mc_store; + + reg r_done; + reg r_branch; + reg r_shift; + reg r_inc; + reg [7:0] r_data; + reg [1:0] r_m2m_cnt; + + wire w_update_flag; + + wire [2:0] w_opcode; + wire w_opx_10; + wire w_opx_11; + wire w_opx_01; + wire w_opx_00; + + wire [7:0] w_ora; + wire [7:0] w_and; + wire [7:0] w_eor; + + wire w_use_alu; + wire w_ops_set_nz; + wire w_shift_set_cnz; + wire w_cmp; + wire w_sbc; + wire w_inc; + wire w_dec; + wire w_shift_rotate; + wire w_shift_right; + wire w_shift_a; + wire w_shift; + wire w_dexy; + wire w_indexy; + wire w_bit; + wire w_plp; + + wire w_m2m_done; + + wire [7:0] w_alu_in_a; + wire [7:0] w_alu_in_b; + wire [7:0] w_alu_out; + wire w_alu_cin; + wire w_alu_sbc; + wire w_alu_n; + wire w_alu_z; + wire w_alu_c; + wire w_alu_v; + + wire [7:0] w_shift_in; + wire [7:0] w_shift_out; + wire w_shift_n; + wire w_shift_z; + wire w_shift_c; + + wire [7:0] w_bit_out; + wire w_bit_n; + wire w_bit_z; + wire w_bit_v; + wire w_bit_set_nzv; + + wire w_taken; + wire w_b_carry; + wire w_b_inc; + wire w_b_dec; + + `include "MC6502Common.vh" + + assign ec2id_done = r_done | r_branch | id2ec_load | w_m2m_done | + (id2ec_ops & !w_opx_10) | + (id2ec_branch & !w_b_carry); + + assign ec2rf_c = w_plp ? id2ec_data[0] : + w_use_alu ? w_alu_c : + w_shift_set_cnz ? w_shift_c : id2ec_set_c; + assign ec2rf_set_c = w_plp | w_use_alu | w_shift_set_cnz | + id2ec_set_c | id2ec_reset_c; + assign ec2rf_i = w_plp ? id2ec_data[2] : id2ec_set_i; + assign ec2rf_set_i = w_plp | id2ec_set_i | id2ec_reset_i; + assign ec2rf_v = w_plp ? id2ec_data[6] : + w_use_alu ? w_alu_v : + w_bit_set_nzv ? w_bit_v : 1'b0; + assign ec2rf_set_v = w_plp | id2ec_reset_v | w_bit_set_nzv | + (w_use_alu & (w_opcode != OP_CMP)); + assign ec2rf_d = w_plp ? id2ec_data[3] : id2ec_set_d; + assign ec2rf_set_d = w_plp | id2ec_set_d | id2ec_reset_d; + assign ec2rf_n = w_plp ? id2ec_data[7] : + w_shift_set_cnz ? w_shift_n : + w_bit_set_nzv ? w_bit_n : + (w_use_alu | w_m2m_done) ? w_alu_n : ec2rf_data[7]; + assign ec2rf_set_n = w_plp | w_use_alu | w_m2m_done | w_ops_set_nz; + assign ec2rf_z = w_plp ? id2ec_data[1] : + w_shift_set_cnz ? w_shift_z : + w_bit_set_nzv ? w_bit_z : + (w_use_alu | w_m2m_done) ? w_alu_z : + (ec2rf_data == 8'h00); + assign ec2rf_set_z = w_plp | w_use_alu | w_m2m_done | w_ops_set_nz; + assign ec2rf_data = (w_use_alu | w_taken | r_branch) ? w_alu_out : + ((w_inc | w_dec) & id2ec_load) ? w_alu_out : + w_shift_a ? w_shift_out : + (id2ec_ops & w_opx_10) ? id2ec_data : + !id2ec_ops ? id2ec_data : + (w_opcode == OP_ORA) ? w_ora : + (w_opcode == OP_AND) ? w_and : + (w_opcode == OP_EOR) ? w_eor : + (w_opcode == OP_LDA) ? id2ec_data : 8'hxx; + assign ec2rf_set_a = (id2ec_load & (id2ec_reg == REG_A)) | + (id2ec_ops & w_opx_01 & ((w_opcode == OP_ORA) | + (w_opcode == OP_AND) | + (w_opcode == OP_EOR) | + (w_opcode == OP_ADC) | + (w_opcode == OP_SBC))); + assign ec2rf_set_x = id2ec_load & (id2ec_reg == REG_X); + assign ec2rf_set_y = id2ec_load & (id2ec_reg == REG_Y); + assign ec2rf_set_s = id2ec_load & (id2ec_reg == REG_S); + assign ec2rf_set_pcl = w_taken; + assign ec2rf_set_pch = r_branch; + + assign ec2mc_data = r_shift ? w_shift_out : w_alu_out; + assign ec2mc_store = w_m2m_done; + + assign w_update_flag = id2ec_reset_c | id2ec_set_c | id2ec_reset_i | + id2ec_set_i | id2ec_reset_v | id2ec_reset_d | + id2ec_set_d; + + assign w_opcode = id2ec_opcode[2:0]; + assign w_opx_10 = id2ec_opcode[4:3] == 2'b10; + assign w_opx_11 = id2ec_opcode[4:3] == 2'b11; + assign w_opx_01 = id2ec_opcode[4:3] == 2'b01; + assign w_opx_00 = id2ec_opcode[4:3] == 2'b00; + + assign w_ora = rf2ec_a | id2ec_data; + assign w_and = rf2ec_a & id2ec_data; + assign w_eor = rf2ec_a ^ id2ec_data; + + assign w_use_alu = id2ec_ops & w_opx_01 & ((w_opcode == OP_ADC) | + (w_opcode == OP_SBC) | + (w_opcode == OP_CMP)); + assign w_ops_set_nz = (id2ec_ops & w_opx_01 & (w_opcode != OP_STA)) | + w_bit_set_nzv | w_indexy; + assign w_shift_set_cnz = w_shift_a | (r_shift & w_m2m_done); + assign w_cmp = id2ec_ops & w_opx_01 & (w_opcode == OP_CMP); + assign w_sbc = id2ec_ops & w_opx_01 & (w_opcode == OP_SBC); + assign w_inc = id2ec_ops & w_opx_10 & (w_opcode == OP_INC); + assign w_dec = id2ec_ops & w_opx_10 & (w_opcode == OP_DEC); + assign w_shift_rotate = (w_opcode == OP_ROL) | (w_opcode == OP_ROR); + assign w_shift_right = (w_opcode == OP_LSR) | (w_opcode == OP_ROR); + assign w_shift_a = w_shift & id2ec_load; + assign w_shift = id2ec_ops & w_opx_10 & ((w_opcode == OP_ASL) | + (w_opcode == OP_ROL) | + (w_opcode == OP_LSR) | + (w_opcode == OP_ROR)); + assign w_dexy = w_dec & id2ec_load & (id2ec_reg != REG_A); + assign w_indexy = (w_inc | w_dec) & id2ec_load & (id2ec_reg != REG_A); + assign w_bit = w_opx_00 & (w_opcode == OP_BIT); + assign w_plp = id2ec_ops & w_opx_11 & (w_opcode == OP_PLP); + + assign w_m2m_done = r_m2m_cnt == 2'b01; + + assign w_alu_in_a = id2ec_branch ? rf2ec_pcl : + r_branch ? rf2ec_pch : + w_indexy ? id2ec_data : + r_m2m_cnt[0] ? r_data : + (id2ec_reg == REG_X) ? rf2ec_x : + (id2ec_reg == REG_Y) ? rf2ec_y : rf2ec_a; + assign w_alu_in_b = r_branch ? 8'h00 : + r_m2m_cnt[0] ? 8'h00 : + w_indexy ? 8'h00 : id2ec_data; + assign w_alu_cin = r_branch ? r_inc : + r_m2m_cnt[0] ? r_inc : + (rf2ec_c | w_cmp | id2ec_branch | w_inc); + assign w_alu_sbc = ((r_branch | (r_m2m_cnt != 2'b00)) & !r_inc) | + (w_dec & id2ec_load) | w_sbc | w_cmp; + + assign w_shift_in = r_m2m_cnt[0] ? r_data : id2ec_data; + + assign w_taken = !id2ec_branch ? 1'b0 : + (w_opcode == OP_BPL) ? !rf2ec_n : + (w_opcode == OP_BMI) ? rf2ec_n : + (w_opcode == OP_BVC) ? !rf2ec_v : + (w_opcode == OP_BVS) ? rf2ec_v : + (w_opcode == OP_BCC) ? !rf2ec_c : + (w_opcode == OP_BCS) ? rf2ec_c : + (w_opcode == OP_BNE) ? !rf2ec_z : rf2ec_z; + assign w_b_inc = !id2ec_data[7] & w_alu_c; + assign w_b_dec = id2ec_data[7] & !w_alu_c; + assign w_b_carry = w_taken & id2ec_branch & (w_b_inc | w_b_dec); + + assign w_bit_out = id2ec_data & rf2ec_a; + assign w_bit_set_nzv = id2ec_ops & w_bit; + assign w_bit_z = w_bit_out == 8'h00; + assign w_bit_n = w_bit_out[7]; + assign w_bit_v = w_bit_out[0]; + + always @ (posedge clk or negedge rstn) begin + if (!rstn) begin + r_done <= 1'b0; + r_branch <= 1'b0; + r_shift <= 1'b0; + r_inc <= 1'b0; + r_data <= 0; + r_m2m_cnt <= 2'b00; + end else if(cen) begin + r_done <= w_update_flag; + r_branch <= w_b_carry; + if (id2ec_ops) begin + r_shift <= w_shift; + end + if (r_m2m_cnt == 2'b00) begin + r_inc <= w_b_inc | w_inc; + end + if ((w_inc | w_dec | w_shift) & !id2ec_load) begin + r_data <= id2ec_data; + r_m2m_cnt <= 2'b11; + end else if (r_m2m_cnt != 2'b00) begin + r_m2m_cnt <= { 1'b0, r_m2m_cnt[1] }; + end + end + end + + MC6502Accumulator alu( + .i_a (w_alu_in_a ), + .i_m (w_alu_in_b ), + .i_c (w_alu_cin ), + .i_d (rf2ec_d ), + .i_s (w_alu_sbc ), + .o_a (w_alu_out ), + .o_n (w_alu_n ), + .o_z (w_alu_z ), + .o_c (w_alu_c ), + .o_v (w_alu_v )); + + MC6502Shifter shifter( + .i_data (w_shift_in ), + .i_rotate(w_shift_rotate), + .i_right (w_shift_right ), + .i_c (rf2ec_c ), + .o_data (w_shift_out ), + .o_n (w_shift_n ), + .o_z (w_shift_z ), + .o_c (w_shift_c )); +endmodule // MC6502InstructionDecode diff --git a/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/mc6502/MC6502InstructionDecode.v b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/mc6502/MC6502InstructionDecode.v new file mode 100644 index 0000000000000000000000000000000000000000..f3dd3f8604d36e20831106dc6ca08e503746fdd4 --- /dev/null +++ b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/mc6502/MC6502InstructionDecode.v @@ -0,0 +1,356 @@ +// Copyright (c) 2014 Takashi Toyoshima . +// All rights reserved. Use of this source code is governed by a BSD-style +// license that can be found in the LICENSE file. + +module MC6502InstructionDecode( + clk, + cen, + rstn, + // MemoryController interfaces + mc2id_data, + mc2id_valid, + id2mc_fetch, + id2mc_sync, + id2mc_operand, + id2mc_modex, + id2mc_mode, + id2mc_reg, + id2mc_store, + id2mc_push, + id2mc_pop, + id2mc_p_reg, + id2mc_jump, + // ExecutionController interfaces + ec2id_done, + id2ec_reset_c, + id2ec_set_c, + id2ec_reset_i, + id2ec_set_i, + id2ec_reset_v, + id2ec_reset_d, + id2ec_set_d, + id2ec_load, + id2ec_ops, + id2ec_branch, + id2ec_opcode, + id2ec_data, + id2ec_reg); + input clk; + input cen; + input rstn; + input [ 7:0] mc2id_data; + input mc2id_valid; + output id2mc_fetch; + output id2mc_sync; + output id2mc_operand; + output id2mc_modex; + output [ 2:0] id2mc_mode; + output [ 1:0] id2mc_reg; + output id2mc_store; + output id2mc_push; + output id2mc_pop; + output id2mc_p_reg; + output id2mc_jump; + + input ec2id_done; + output id2ec_reset_c; + output id2ec_set_c; + output id2ec_reset_i; + output id2ec_set_i; + output id2ec_reset_v; + output id2ec_reset_d; + output id2ec_set_d; + output id2ec_load; + output id2ec_ops; + output id2ec_branch; + output [ 4:0] id2ec_opcode; + output [ 7:0] id2ec_data; + output [ 1:0] id2ec_reg; + + reg r_sync; + reg r_load; + reg r_ops; + reg r_branch; + reg r_set_reg; + reg [ 1:0] r_reg; + reg [ 2:0] r_opcode; + reg [ 1:0] r_opx; + + wire [ 2:0] w_opcode; + wire [ 2:0] w_modified_opcode; + wire [ 2:0] w_addressing; + + wire w_fetch_valid; + wire w_operand_valid; + + wire w_unknown_instruction; + wire w_xxxx_xx00; + wire w_xxxx_xx01; + wire w_xxxx_xx10; + wire w_xxxx_1x00; + wire w_xxxx_0000; + wire w_xxxx_1000; + wire w_xxx0_0000; + wire w_xxx0_1000; + wire w_xxx0_1100; + wire w_xxx1_0000; + wire w_xxx1_1000; + wire w_10xx_xxxx; + + // Standard addressing mode (---X_XX--) + wire w_indexed_indirect; // (Indirect, X) + wire w_zero_page; // Zero Page + wire w_immediate; // Immediate + wire w_absolute; // Absolute + wire w_indirect_index; // (Indirect), Y + wire w_zero_page_index; // Zero Page, X + wire w_absolute_indexed_y; // Absolute, Y + wire w_absolute_indexed_x; // Absolute, X + + wire w_modex_immediate; + wire w_modex_register; + + wire w_ldx_code; + wire w_ldy_code; + wire w_inc_code; + wire w_dec_code; + wire w_shift_code; + wire w_bit_code; + wire w_stx_code; + wire w_sty_code; + wire w_cpx_code; + wire w_cpy_code; + + wire w_tya; + wire w_tay; + wire w_lda; + wire w_ldx; + wire w_ldy; + wire w_sta; + wire w_stx; + wire w_sty; + wire w_t; + wire w_b; + wire w_ops; + wire w_inc; + wire w_dec; + wire w_inx; + wire w_iny; + wire w_dex; + wire w_dey; + wire w_inxy; + wire w_dexy; + wire w_index; + wire w_indey; + wire w_indexy; + wire w_shift; + wire w_bit; + wire w_cpx; + wire w_cpy; + wire w_pla; + wire w_plp; + wire w_jmp_ind; + wire w_jmp; + wire w_j; + wire w_jsr; + wire w_call; + wire w_return; + wire w_interrupt; + + wire w_request_reg; + wire [ 1:0] w_from_reg; + wire [ 1:0] w_to_reg; + + wire w_valid_ld_mode; + wire w_valid_inc_mode; + wire w_valid_shift_mode; + wire w_valid_bit_mode; + wire w_valid_stx_mode; + wire w_valid_sty_mode; + wire w_valid_cp_mode; + + `include "MC6502Common.vh" + + assign id2mc_sync = r_sync; + assign id2mc_fetch = r_sync; + assign id2mc_operand = w_ldx | w_ldy | w_request_reg | w_ops | w_b | + w_inc | w_dec | w_shift | w_bit | w_stx | + w_sty | w_cpx | w_cpy | id2mc_push | + id2mc_pop | id2mc_jump; + assign id2mc_mode = w_request_reg ? MODEX_REGISTER : + w_b ? MODE_IMMEDIATE : + w_jmp_ind ? MODEX_INDIRECT_PC : + w_jsr ? MODEX_ABSOLUTE_PC : + w_addressing; + assign id2mc_modex = w_request_reg | w_ldx | w_cpx | w_cpy | + w_jmp | (w_j & w_return) | + (w_ldy & w_modex_immediate) | + (w_shift & w_modex_register) | + (w_stx & w_zero_page_index); + assign id2mc_reg = w_from_reg; + assign id2mc_store = w_sta | w_stx | w_sty; + assign id2mc_push = (w_xxx0_1000 & ((w_opcode == OP_PHP) | + (w_opcode == OP_PHA))) | + (w_j & w_call); + assign id2mc_pop = (w_xxx0_1000 & ((w_opcode == OP_PLP) | + (w_opcode == OP_PLA))) | + (w_j & w_return); + assign id2mc_p_reg = (w_xxx0_1000 & ((w_opcode == OP_PHP) | + (w_opcode == OP_PLP))) | + (w_j & w_interrupt); + assign id2mc_jump = w_jmp | w_j; + + assign id2ec_reset_c = w_xxx1_1000 & (w_opcode == 3'b000); + assign id2ec_set_c = w_xxx1_1000 & (w_opcode == 3'b001); + assign id2ec_reset_i = w_xxx1_1000 & (w_opcode == 3'b010); + assign id2ec_set_i = w_xxx1_1000 & (w_opcode == 3'b011); + assign id2ec_reset_v = w_xxx1_1000 & (w_opcode == 3'b101); + assign id2ec_reset_d = w_xxx1_1000 & (w_opcode == 3'b110); + assign id2ec_set_d = w_xxx1_1000 & (w_opcode == 3'b111); + assign id2ec_data = mc2id_data; + assign id2ec_load = w_operand_valid & (r_load | w_lda); + assign id2ec_ops = r_ops & w_operand_valid; + assign id2ec_branch = r_branch & w_operand_valid; + assign id2ec_opcode = { r_opx, r_opcode }; + assign id2ec_reg = r_reg; + + assign w_opcode = mc2id_data[7:5]; + assign w_modified_opcode = w_inxy ? OP_INC : + w_dexy ? OP_DEC : + (w_stx | w_sty) ? OP_STA : + (w_cpx | w_cpy) ? OP_CMP : + w_pla ? OP_LDA : w_opcode; + assign w_addressing = mc2id_data[4:2]; + + assign w_fetch_valid = mc2id_valid & r_sync; + assign w_operand_valid = mc2id_valid & !r_sync; + + assign w_xxxx_xx00 = w_fetch_valid & (mc2id_data[1:0] == 2'b00); + assign w_xxxx_xx01 = w_fetch_valid & (mc2id_data[1:0] == 2'b01); + assign w_xxxx_xx10 = w_fetch_valid & (mc2id_data[1:0] == 2'b10); + assign w_xxxx_1x00 = w_xxxx_xx00 & mc2id_data[3]; + assign w_xxxx_0000 = w_xxxx_xx00 & (mc2id_data[3:2] == 2'b00); + assign w_xxxx_1000 = w_xxxx_1x00 & !mc2id_data[2]; + assign w_xxx0_1000 = w_xxxx_1000 & !mc2id_data[4]; + assign w_xxx0_1100 = w_xxxx_1x00 & !mc2id_data[4] & mc2id_data[2]; + assign w_xxx0_0000 = w_xxxx_0000 & !mc2id_data[4]; + assign w_xxx1_0000 = w_xxxx_0000 & mc2id_data[4]; + assign w_xxx1_1000 = w_xxxx_1000 & mc2id_data[4]; + assign w_10xx_xxxx = w_fetch_valid & (mc2id_data[7:6] == 2'b10); + + assign w_indexed_indirect = w_addressing == MODE_INDEXED_INDIRECT; + assign w_zero_page = w_addressing == MODE_ZERO_PAGE; + assign w_immediate = w_addressing == MODE_IMMEDIATE; + assign w_absolute = w_addressing == MODE_ABSOLUTE; + assign w_indirect_index = w_addressing == MODE_INDIRECT_INDEX; + assign w_zero_page_index = w_addressing == MODE_ZERO_PAGE_INDEX_X; + assign w_absolute_indexed_y = w_addressing == MODE_ABSOLUTE_INDEXED_Y; + assign w_absolute_indexed_x = w_addressing == MODE_ABSOLUTE_INDEXED_X; + + assign w_modex_immediate = w_addressing == MODEX_IMMEDIATE; + assign w_modex_register = w_addressing == MODEX_REGISTER; + + assign w_unknown_instruction = w_fetch_valid & !id2mc_operand & !w_xxx1_1000; + + assign w_valid_ld_mode = w_modex_immediate | w_zero_page | w_absolute | + w_zero_page_index | w_absolute_indexed_x; + assign w_valid_inc_mode = w_zero_page | w_zero_page_index | + w_absolute | w_absolute_indexed_x; + assign w_valid_shift_mode = w_valid_inc_mode | w_modex_register; + assign w_valid_bit_mode = w_zero_page | w_absolute; + assign w_valid_stx_mode = w_zero_page | w_absolute | w_zero_page_index; + assign w_valid_sty_mode = w_zero_page | w_absolute | w_zero_page_index; + assign w_valid_cp_mode = w_modex_immediate | w_zero_page | w_absolute; + + assign w_ldx_code = w_xxxx_xx10 & (w_opcode == OP_LDX); + assign w_ldy_code = w_xxxx_xx00 & (w_opcode == OP_LDY); + assign w_inc_code = w_xxxx_xx10 & (w_opcode == OP_INC); + assign w_dec_code = w_xxxx_xx10 & (w_opcode == OP_DEC); + assign w_shift_code = w_xxxx_xx10 & ((w_opcode == OP_ASL) | + (w_opcode == OP_ROL) | + (w_opcode == OP_LSR) | + (w_opcode == OP_ROR)); + assign w_bit_code = w_xxxx_xx00 & (w_opcode == OP_BIT); + assign w_stx_code = w_xxxx_xx10 & (w_opcode == OP_STX); + assign w_sty_code = w_xxxx_xx00 & (w_opcode == OP_STY); + assign w_cpx_code = w_xxxx_xx00 & (w_opcode == OP_CPX); + assign w_cpy_code = w_xxxx_xx00 & (w_opcode == OP_CPY); + assign w_ldx = w_ldx_code & w_valid_ld_mode; + assign w_ldy = w_ldy_code & w_valid_ld_mode; + assign w_tya = w_xxx1_1000 & (w_opcode == 3'b100); + assign w_tay = w_xxx0_1000 & (w_opcode == OP_TAY); + assign w_lda = r_ops & (r_opx == 2'b01) & + (r_opcode == OP_LDA); + assign w_t = w_tya | w_tay | + (w_10xx_xxxx & (mc2id_data[3:0] == 4'b1010)); + assign w_b = w_xxx1_0000; + assign w_ops = w_xxxx_xx01; + assign w_inc = w_inc_code & w_valid_inc_mode; + assign w_dec = w_dec_code & w_valid_inc_mode; + assign w_shift = w_shift_code & w_valid_shift_mode; + assign w_bit = w_bit_code & w_valid_bit_mode; + assign w_sta = w_ops & (w_opcode == OP_STA) & !w_immediate; + assign w_stx = w_stx_code & w_valid_stx_mode; + assign w_sty = w_sty_code & w_valid_sty_mode; + assign w_inx = w_xxx0_1000 & (w_opcode == OP_INX); + assign w_iny = w_xxx0_1000 & (w_opcode == OP_INY); + assign w_dex = w_inc_code & w_immediate; + assign w_dey = w_xxx0_1000 & (w_opcode == OP_DEY); + assign w_inxy = w_inx | w_iny; + assign w_dexy = w_dex | w_dey; + assign w_index = w_inx | w_dex; + assign w_indey = w_iny | w_dey; + assign w_indexy = w_inx | w_iny | w_dex | w_dey; + assign w_cpx = w_cpx_code & w_valid_cp_mode; + assign w_cpy = w_cpy_code & w_valid_cp_mode; + assign w_pla = w_xxx0_1000 & (w_opcode == OP_PLA); + assign w_plp = w_xxx0_1000 & (w_opcode == OP_PLP); + assign w_jmp_ind = w_xxx0_1100 & (w_opcode == OP_JMP_IND); + assign w_jmp = w_xxx0_1100 & ((w_opcode == OP_JMP_ABS) | + (w_opcode == OP_JMP_IND)); + assign w_j = w_xxx0_0000 & !mc2id_data[7]; + assign w_jsr = w_xxx0_0000 & (w_opcode == OP_JSR); + assign w_call = (w_opcode == OP_BRK) | (w_opcode == OP_JSR); + assign w_return = (w_opcode == OP_RTI) | (w_opcode == OP_RTS); + assign w_interrupt = (w_opcode == OP_BRK) | (w_opcode == OP_RTI); + + assign w_request_reg = w_t | w_indexy; + assign w_from_reg = (w_tya | w_indey | w_sty) ? REG_Y : + (w_tay | w_shift | w_sta) ? REG_A : + (!mc2id_data[5] | w_index | w_stx) ? REG_X : + mc2id_data[4] ? REG_S : REG_A; + assign w_to_reg = w_tya ? REG_A : + (w_tay | w_indey) ? REG_Y : + (mc2id_data[5] | w_index) ? REG_X : + mc2id_data[4] ? REG_S : REG_A; + + always @ (posedge clk or negedge rstn) begin + if (!rstn) begin + r_sync <= 1'b1; + r_load <= 1'b0; + r_ops <= 1'b0; + r_branch <= 1'b0; + r_reg <= 2'b00; + r_opcode <= 3'b000; + r_opx <= 2'b00; + end else if(cen) begin + r_sync <= ec2id_done | (r_sync & !mc2id_valid); + if (w_fetch_valid) begin + r_load <= w_ldx | w_ldy | w_t | w_indexy | + (w_shift & w_modex_register); + r_ops <= w_ops | w_inc | w_dec | w_shift | w_indexy | w_bit | + w_stx | w_sty | w_cpx | w_cpy | id2mc_push | id2mc_pop | + id2mc_jump; + r_branch <= w_b; + r_reg <= (w_ldx | w_cpx) ? REG_X : + (w_ldy | w_cpy) ? REG_Y : + w_request_reg ? w_to_reg : REG_A; + r_opcode <= w_modified_opcode; + r_opx <= w_indexy ? 2'b10 : + w_plp ? 2'b11 : + (w_stx | w_sty | w_cpx | w_cpy | w_pla) ? 2'b01 : + mc2id_data[1:0]; + end + end + end +endmodule // MC6502InstructionDecode diff --git a/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/mc6502/MC6502InterruptLogic.v b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/mc6502/MC6502InterruptLogic.v new file mode 100644 index 0000000000000000000000000000000000000000..f3b26e0c99968ac050dc5b92d751aea1d8a4a9fe --- /dev/null +++ b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/mc6502/MC6502InterruptLogic.v @@ -0,0 +1,139 @@ +// Copyright (c) 2014 Takashi Toyoshima . +// All rights reserved. Use of this source code is governed by a BSD-style +// license that can be found in the LICENSE file. + +// TODO: NMI and IRQ handling is not correct. It should push PC and PSR to +// stack, and follow timing constraint. It must be realized by collaboration +// with the core sequencer. +module MC6502InterruptLogic( + clk, + cen, + rstn, + i_irqn, + i_nmin, + // MemoryController interfaces. + mc2il_data, + mc2il_brk, + il2mc_addr, + il2mc_read, + il2mc_write, + il2mc_data, + // RegisterFile interfaces. + rf2il_s, + rf2il_psr, + rf2il_pc, + il2rf_set_i, + il2rf_set_b, + il2rf_data, + il2rf_set_pcl, + il2rf_set_pch, + il2rf_pushed); + input clk; + input cen; + input rstn; + input i_irqn; + input i_nmin; + + input [ 7:0] mc2il_data; + input mc2il_brk; + output [15:0] il2mc_addr; + output il2mc_read; + output il2mc_write; + output [ 7:0] il2mc_data; + + input [ 7:0] rf2il_s; + input [ 7:0] rf2il_psr; + input [15:0] rf2il_pc; + output il2rf_set_i; + output il2rf_set_b; + output [ 7:0] il2rf_data; + output il2rf_set_pcl; + output il2rf_set_pch; + output il2rf_pushed; + + reg [ 1:0] r_res_state; + reg [ 1:0] r_int_state; + reg [ 1:0] r_vector; + + wire w_read_pcl; + wire w_read_pch; + + localparam VECTOR_NMI = 2'b01; + localparam VECTOR_RES = 2'b10; + localparam VECTOR_IRQ = 2'b11; + localparam VECTOR_BRK = 2'b11; + + localparam S_RES_IDLE = 2'b00; + localparam S_RES_LOAD_PCL = 2'b01; + localparam S_RES_LOAD_PCH = 2'b11; + + localparam S_INT_IDLE = 2'b00; + localparam S_INT_PUSH_PCL = 2'b01; + localparam S_INT_PUSH_PSR = 2'b10; + + assign il2mc_addr = il2mc_write ? { 8'h01, rf2il_s } : + { 12'hfff, 1'b1, r_vector, w_read_pch }; + assign il2mc_read = w_read_pcl | w_read_pch; + assign il2mc_write = mc2il_brk | (r_int_state == S_INT_PUSH_PCL) | + (r_int_state == S_INT_PUSH_PSR); + assign il2mc_data = mc2il_brk ? rf2il_pc[15:8] : + (r_int_state == S_INT_PUSH_PCL) ? rf2il_pc[7:0] : + (r_int_state == S_INT_PUSH_PSR) ? rf2il_psr : + 8'hxx; + assign il2rf_set_i = (r_int_state == S_INT_PUSH_PSR) | !i_irqn | !i_nmin; + assign il2rf_set_b = r_int_state == S_INT_PUSH_PSR; + assign il2rf_data = mc2il_data; + assign il2rf_set_pcl = w_read_pcl; + assign il2rf_set_pch = w_read_pch; + assign il2rf_pushed = il2mc_write; + + assign w_read_pcl = r_res_state == S_RES_LOAD_PCL; + assign w_read_pch = r_res_state == S_RES_LOAD_PCH; + + always @ (posedge clk or negedge rstn) begin + if (!rstn) begin + r_res_state <= S_RES_LOAD_PCL; + r_vector <= VECTOR_RES; + end else if(cen) begin + case (r_res_state) + S_RES_IDLE: begin + if (!i_irqn | (r_int_state == S_INT_PUSH_PSR)) begin + r_res_state <= S_RES_LOAD_PCL; + r_vector <= VECTOR_IRQ; + end else if (!i_nmin) begin + r_res_state <= S_RES_LOAD_PCL; + r_vector <= VECTOR_NMI; + end + end + S_RES_LOAD_PCL: begin + r_res_state <= S_RES_LOAD_PCH; + end + S_RES_LOAD_PCH: begin + r_res_state <= S_RES_IDLE; + end + default:; + endcase // r_res_state + end + end // always @ (posedge clk or negedge rstn) + + always @ (posedge clk or negedge rstn) begin + if (!rstn) begin + r_int_state <= S_INT_IDLE; + end else if(cen) begin + case (r_int_state) + S_INT_IDLE: begin + if (mc2il_brk) begin + r_int_state <= S_INT_PUSH_PCL; + end + end + S_INT_PUSH_PCL: begin + r_int_state <= S_INT_PUSH_PSR; + end + S_INT_PUSH_PSR: begin + r_int_state <= S_INT_IDLE; + end + default:; + endcase // r_int_state + end + end // always @ (posedge clk or negedge rstn) +endmodule // MC6502InterruptLogic diff --git a/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/mc6502/MC6502MemoryController.v b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/mc6502/MC6502MemoryController.v new file mode 100644 index 0000000000000000000000000000000000000000..b4575d853b846f9c2e386236c42c3089033af039 --- /dev/null +++ b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/mc6502/MC6502MemoryController.v @@ -0,0 +1,373 @@ +// Copyright (c) 2014 Takashi Toyoshima . +// All rights reserved. Use of this source code is governed by a BSD-style +// license that can be found in the LICENSE file. + +module MC6502MemoryController( + clk, + cen, + rstn, + i_rdy, + i_db, + o_db, + o_ab, + o_rw, + o_sync, + // InterruptLogic interfaces + il2mc_addr, + il2mc_read, + il2mc_write, + il2mc_data, + mc2il_data, + mc2il_brk, + // RegisterFile interfaces + rf2mc_pc, + rf2mc_a, + rf2mc_x, + rf2mc_y, + rf2mc_s, + rf2mc_psr, + mc2rf_fetched, + mc2rf_pushed, + mc2rf_pull, + mc2rf_pc, + mc2rf_set_pc, + mc2rf_psr, + mc2rf_set_psr, + // InstructionDecode interfaces + id2mc_fetch, + id2mc_sync, + id2mc_operand, + id2mc_modex, + id2mc_mode, + id2mc_reg, + id2mc_store, + id2mc_push, + id2mc_pop, + id2mc_p_reg, + id2mc_jump, + mc2id_data, + mc2id_valid, + // ExecutionController interfaces + ec2mc_data, + ec2mc_store); + input clk; + input cen; + input rstn; + input i_rdy; + input [ 7:0] i_db; + output [ 7:0] o_db; + output [15:0] o_ab; + output o_rw; + output o_sync; + + input [15:0] il2mc_addr; + input il2mc_read; + input il2mc_write; + input [ 7:0] il2mc_data; + output [ 7:0] mc2il_data; + output mc2il_brk; + + input [15:0] rf2mc_pc; + input [ 7:0] rf2mc_a; + input [ 7:0] rf2mc_x; + input [ 7:0] rf2mc_y; + input [ 7:0] rf2mc_s; + input [ 7:0] rf2mc_psr; + output mc2rf_fetched; + output mc2rf_pushed; + output mc2rf_pull; + output [15:0] mc2rf_pc; + output mc2rf_set_pc; + output [ 7:0] mc2rf_psr; + output mc2rf_set_psr; + + input id2mc_fetch; + input id2mc_sync; + input id2mc_operand; + input [ 2:0] id2mc_mode; + input id2mc_modex; + input [ 1:0] id2mc_reg; + input id2mc_store; + input id2mc_push; + input id2mc_pop; + input id2mc_p_reg; + input id2mc_jump; + output [ 7:0] mc2id_data; + output mc2id_valid; + + input [ 7:0] ec2mc_data; + input ec2mc_store; + + reg [ 2:0] r_operand; + reg r_modex; + reg [ 2:0] r_mode; + reg [15:0] r_data; + reg [ 1:0] r_reg; + reg r_carry; + reg r_store; + reg r_push; + reg r_pop; + reg r_jump; + + wire w_adder_valid; + wire [ 8:0] w_adder_sum; + wire [ 7:0] w_adder_in_a; + wire [ 7:0] w_adder_in_b; + + wire w_write; + wire w_push_cycle; + wire w_pop_cycle; + wire w_il_active; + wire [15:0] w_il_addr; + wire w_id_active; + wire [15:0] w_id_addr; + wire w_1t_mode; + wire w_2t_mode; + wire w_3t_mode; + wire w_4t_mode; + wire w_5t_mode; + wire w_6t_mode; + wire w_fetch_opcode; + wire w_fetch_next; + wire w_register; + wire w_immediate; + wire w_absolute; + wire w_absolute_pc; + wire w_indirect_pc; + wire w_abs_idx; + wire w_abs_idx_x; + wire w_abs_idx_y; + wire w_zero_page; + wire w_zero_idx; + wire w_zero_idx_x; + wire w_zero_idx_y; + wire w_indirect; + wire w_indirect_x; + wire w_indirect_y; + wire [15:0] w_immediate_addr; + wire [15:0] w_absolute_addr; + wire [15:0] w_abs_idx_addr; + wire [15:0] w_zero_page_addr; + wire [15:0] w_zero_idx_addr; + wire [15:0] w_indirect_addr; + wire [15:0] w_idx_ind_addr; + wire [15:0] w_ind_idx_addr; + wire w_abs_idx_add; + wire w_zero_idx_add; + wire w_idx_ind_add; + wire w_ind_idx_add; + wire [ 7:0] w_register_data; + wire [ 7:0] w_jsr_data; + wire w_jmp; + wire w_jsr; + wire w_brk; + wire w_rts; + wire w_rti; + + `include "MC6502Common.vh" + + assign o_db = ec2mc_store ? ec2mc_data : + il2mc_write ? il2mc_data : + (r_push & r_jump) ? w_jsr_data : + (r_reg == REG_A) ? rf2mc_a : + (r_reg == REG_Y) ? rf2mc_y : + (r_push & !r_jump) ? rf2mc_psr : rf2mc_x; + assign o_ab = w_il_active ? w_il_addr : + ec2mc_store ? r_data : + w_push_cycle ? { 8'h01, rf2mc_s } : + w_pop_cycle ? { 8'h01, rf2mc_s } : w_id_addr; + assign o_rw = !w_write; + assign o_sync = w_id_active & id2mc_sync; + + assign mc2il_data = il2mc_read ? i_db : 8'hxx; + assign mc2il_brk = w_brk & (r_operand == 3'b101); + + assign mc2rf_fetched = w_fetch_opcode | w_fetch_next; + assign mc2rf_pushed = w_push_cycle; + assign mc2rf_pull = ((w_rts | w_rti) & ((r_operand == 3'b101) | + (r_operand == 3'b100))) | + (!w_rts & r_pop & (r_operand == 3'b011)); + assign mc2rf_pc = (w_jsr | w_rts | w_rti) ? r_data : + { i_db, r_data[15:8] }; + assign mc2rf_set_pc = (w_jmp & ((r_operand == 3'b001) | + ((r_operand == 3'b11) & w_indirect_pc))) | + ((w_jsr | w_rti)& (r_operand == 3'b001)) | + (w_rts & (r_operand == 3'b010)); + assign mc2rf_psr = mc2rf_set_psr ? i_db : 8'hxx; + assign mc2rf_set_psr = w_rti & (r_operand == 3'b100); + + assign mc2id_data = (!mc2id_valid | w_write) ? 8'hxx : + (!w_fetch_opcode & w_register) ? w_register_data : + i_db; + assign mc2id_valid = w_fetch_opcode | (r_operand == 3'b001); + + assign w_write = (r_store & (r_operand == 3'b001)) | + ec2mc_store | w_push_cycle | il2mc_write; + assign w_push_cycle = (r_push & !r_jump & (r_operand == 3'b010)) | + (w_jsr & ((r_operand == 3'b011) | + (r_operand == 3'b010))); + assign w_pop_cycle = r_pop & ((!r_jump & ((r_operand == 3'b010) | + (r_operand == 3'b001))) | + (r_jump & ((r_operand == 3'b100) | + (r_operand == 3'b011))) | + (w_rti & (r_operand == 3'b010))); + assign w_il_active = il2mc_read | il2mc_write; + assign w_il_addr = il2mc_addr; + + assign w_id_active = !w_il_active; + assign w_id_addr = (r_operand == 3'b000) ? rf2mc_pc : + w_immediate ? w_immediate_addr : + w_absolute ? w_absolute_addr : + w_abs_idx ? w_abs_idx_addr : + w_zero_page ? w_zero_page_addr : + w_zero_idx ? w_zero_idx_addr : + w_indirect ? w_indirect_addr : rf2mc_pc; + + assign w_1t_mode = !id2mc_push & !id2mc_pop & + ((id2mc_modex & (id2mc_mode == MODEX_IMMEDIATE)) | + (!id2mc_modex & (id2mc_mode == MODE_IMMEDIATE)) | + (id2mc_modex & (id2mc_mode == MODEX_REGISTER))); + assign w_2t_mode = (id2mc_mode == MODE_ZERO_PAGE) | + ((id2mc_mode == MODEX_ABSOLUTE_PC) & id2mc_jump & + !id2mc_push) | + (id2mc_push & !id2mc_jump); + assign w_3t_mode = ((id2mc_mode == MODE_ABSOLUTE) & !id2mc_jump) | + (id2mc_pop & !id2mc_jump) | + (id2mc_mode == MODE_ZERO_PAGE_INDEX_X) | + (id2mc_mode == MODE_ABSOLUTE_INDEXED_X) | + (id2mc_mode == MODE_ABSOLUTE_INDEXED_Y); + assign w_4t_mode = id2mc_mode == MODE_INDIRECT_INDEX; + assign w_5t_mode = !id2mc_jump & !id2mc_modex & + (id2mc_mode == MODE_INDEXED_INDIRECT) | + (id2mc_jump & id2mc_push & !id2mc_p_reg) | + (id2mc_jump & id2mc_pop); + assign w_6t_mode = (id2mc_jump & id2mc_push & id2mc_p_reg); + assign w_register = r_modex & (r_mode == MODEX_REGISTER); + assign w_immediate = (r_modex & (r_mode == MODEX_IMMEDIATE)) | + (!r_modex & (r_mode == MODE_IMMEDIATE)); + assign w_absolute = (r_mode == MODEX_ABSOLUTE) & !r_jump; + assign w_absolute_pc = (r_mode == MODEX_ABSOLUTE_PC) & + (w_jmp | (r_jump & r_push)); + assign w_indirect_pc = (r_mode == MODEX_INDIRECT_PC) & w_jmp; + assign w_abs_idx = (r_mode == MODE_ABSOLUTE_INDEXED_X) | + (r_mode == MODE_ABSOLUTE_INDEXED_Y); + assign w_abs_idx_x = !r_modex && (r_mode == MODE_ABSOLUTE_INDEXED_X); + assign w_abs_idx_y = w_abs_idx & !w_abs_idx_x; + assign w_zero_page = r_mode == MODEX_ZERO_PAGE; + assign w_zero_idx = r_mode == MODE_ZERO_PAGE_INDEX_X; + assign w_zero_idx_x = !r_modex & w_zero_idx; + assign w_zero_idx_y = r_modex & w_zero_idx; + assign w_indirect = !r_modex & ((r_mode == MODE_INDEXED_INDIRECT) | + (r_mode == MODE_INDIRECT_INDEX)); + assign w_indirect_x = !r_modex & (r_mode == MODE_INDEXED_INDIRECT); + assign w_indirect_y = !r_modex & (r_mode == MODE_INDIRECT_INDEX); + assign w_immediate_addr = rf2mc_pc; + assign w_absolute_addr = (r_operand != 3'b001) ? rf2mc_pc : r_data; + assign w_abs_idx_addr = ((r_operand == 3'b010) && r_carry) ? r_data : + (r_operand == 3'b001) ? r_data : rf2mc_pc; + assign w_zero_page_addr = (r_operand == 3'b010) ? rf2mc_pc : + { 8'h00, r_data[15:8] }; + assign w_zero_idx_addr = (r_operand == 3'b010) ? { 8'h00, r_data[15:8] } : + (r_operand == 3'b001) ? { 8'h00, r_data[7:0] } : + rf2mc_pc; + assign w_idx_ind_addr = (r_operand == 3'b100) ? { 8'h00, r_data[15:8] } : + (r_operand == 3'b011) ? { 8'h00, r_data[7:0] } : + (r_operand == 3'b010) ? { 8'h00, r_data[7:0] } : + (r_operand == 3'b001) ? { 8'h00, r_data[7:0] } : + rf2mc_pc; + assign w_ind_idx_addr = (r_operand == 3'b011) ? { 8'h00, r_data[15:8] } : + (r_operand == 3'b010) ? { 8'h00, r_data[7:0] } : + (r_operand == 3'b001) ? r_data : rf2mc_pc; + assign w_indirect_addr = w_indirect_x ? w_idx_ind_addr : w_ind_idx_addr; + assign w_abs_idx_add = w_abs_idx & (r_operand == 3'b010); + assign w_zero_idx_add = w_zero_idx & (r_operand == 3'b010); + assign w_idx_ind_add = w_indirect_x & ((r_operand == 3'b100) | + (r_operand == 3'b011)); + assign w_ind_idx_add = w_indirect_y & ((r_operand == 3'b011) | + (r_operand == 3'b010)); + assign w_fetch_opcode = w_id_active & id2mc_fetch & i_rdy; + assign w_fetch_next = ((w_absolute | w_abs_idx) & (r_operand == 3'b011)) | + (w_jmp & (r_operand == 3'b010)) | + (w_indirect_pc & (r_operand == 3'b100)) | + (w_absolute_pc & (r_operand == 3'b010)) | + (!w_register & !r_jump & !r_push & !r_pop & + (r_operand == 3'b001)) | + (w_brk & (r_operand == 3'b110)) | + (w_jsr & (r_operand == 3'b101)) | + (w_rts & (r_operand == 3'b001)); + + assign w_adder_in_a = (w_idx_ind_add & (r_operand == 3'b011)) ? + r_data[7:0] : + w_adder_valid ? r_data[15:8] : 8'h00; + assign w_adder_in_b = !w_adder_valid ? 8'h00 : + r_carry ? 8'h01 : + (w_idx_ind_add & (r_operand == 3'b011)) ? 8'h01 : + (w_ind_idx_add & (r_operand == 3'b011)) ? 8'h01 : + (w_abs_idx_x | w_zero_idx_x | w_indirect_x) ? + rf2mc_x : rf2mc_y; + assign w_adder_sum = w_adder_in_a + w_adder_in_b; + assign w_adder_valid = (w_abs_idx_add | w_zero_idx_add | w_idx_ind_add | + w_ind_idx_add); + + assign w_register_data = (r_reg == REG_A) ? rf2mc_a : + (r_reg == REG_X) ? rf2mc_x : + (r_reg == REG_Y) ? rf2mc_y : rf2mc_s; + + assign w_jsr_data = (r_operand == 3'b011) ? rf2mc_pc[15:8] : + rf2mc_pc[7:0]; + assign w_jmp = r_jump & !r_push & !r_pop; + assign w_jsr = r_jump & r_push & !r_reg[0]; + assign w_brk = r_jump & r_push & r_reg[0]; + assign w_rts = r_jump & r_pop & !r_reg[0]; + assign w_rti = r_jump & r_pop & r_reg[0]; + + always @ (posedge clk or negedge rstn) begin + if (!rstn) begin + r_operand <= 3'b000; + r_modex <= 1'b0; + r_mode <= 3'b000; + r_data <= 16'h00; + r_reg <= 2'b00; + r_carry <= 1'b0; + r_store <= 1'b0; + r_push <= 1'b0; + r_pop <= 1'b0; + r_jump <= 1'b0; + end else if(cen) begin + if (id2mc_operand) begin + r_operand <= w_1t_mode ? 3'b001 : + w_2t_mode ? 3'b010 : + w_3t_mode ? 3'b011 : + w_4t_mode ? 3'b100 : + w_5t_mode ? 3'b101 : + w_6t_mode ? 3'b110 : 3'bxxx; + r_modex <= id2mc_modex; + r_mode <= id2mc_mode; + r_reg <= (id2mc_push | id2mc_pop) ? { 1'b0, id2mc_p_reg } : id2mc_reg; + r_store <= id2mc_store; + r_push <= id2mc_push; + r_pop <= id2mc_pop; + r_jump <= id2mc_jump; + end else if (r_operand != 3'b000) begin + if ((w_abs_idx | w_indirect_y) & w_adder_sum[8] & !r_carry) begin + r_carry <= 1'b1; + end else begin + r_operand <= r_operand - 3'b001; + r_carry <= 1'b0; + end + if (r_carry) begin + r_data <= { w_adder_sum[7:0], r_data[7:0] }; + end else if (w_adder_valid) begin + r_data <= { i_db, w_adder_sum[7:0] }; + end else if (w_jsr & ((r_operand == 3'b011) | + (r_operand == 3'b010))) begin + r_data <= r_data; + end else if (r_operand == 3'b001) begin + r_data <= o_ab; + end else begin + r_data <= { i_db, r_data[15:8] }; + end + end + end + end +endmodule // MC6502MemoryController diff --git a/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/mc6502/MC6502ProcessorStatusRegister.v b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/mc6502/MC6502ProcessorStatusRegister.v new file mode 100644 index 0000000000000000000000000000000000000000..84c61fb45abcc6ef441e30694c3eba21ba5bdb66 --- /dev/null +++ b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/mc6502/MC6502ProcessorStatusRegister.v @@ -0,0 +1,87 @@ +// Copyright (c) 2014 Takashi Toyoshima . +// All rights reserved. Use of this source code is governed by a BSD-style +// license that can be found in the LICENSE file. + +module MC6502ProcessorStatusRegister( + clk, + cen, + rstn, + i_c, + i_set_c, + i_i, + i_set_i, + i_v, + i_set_v, + i_d, + i_set_d, + i_n, + i_set_n, + i_z, + i_set_z, + i_b, + i_set_b, + o_psr); + + input clk; + input cen; + input rstn; + input i_c; + input i_set_c; + input i_i; + input i_set_i; + input i_v; + input i_set_v; + input i_d; + input i_set_d; + input i_n; + input i_set_n; + input i_z; + input i_set_z; + input i_b; + input i_set_b; + output [7:0] o_psr; + + reg r_n; + reg r_v; + reg r_b; + reg r_d; + reg r_i; + reg r_z; + reg r_c; + + assign o_psr = { r_n, r_v, 1'b1, r_b, r_d, r_i, r_z, r_c }; + + always @ (posedge clk or negedge rstn) begin + if (!rstn) begin + r_n <= 1'b0; + r_v <= 1'b0; + r_b <= 1'b0; + r_d <= 1'b0; + r_i <= 1'b0; + r_z <= 1'b0; + r_c <= 1'b0; + end else if(cen) begin + if (i_set_c) begin + r_c <= i_c; + end + if (i_set_i) begin + r_i <= i_i; + end + if (i_set_v) begin + r_v <= i_v; + end + if (i_set_d) begin + r_d <= i_d; + end + if (i_set_n) begin + r_n <= i_n; + end + if (i_set_z) begin + r_z <= i_z; + end + if (i_set_b) begin + r_b <= i_b; + end + end + end +endmodule // MC6502ProcessorStatusRegister diff --git a/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/mc6502/MC6502RegisterFile.v b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/mc6502/MC6502RegisterFile.v new file mode 100644 index 0000000000000000000000000000000000000000..53127447ff212c54ea640e8f463bdff61d9e280b --- /dev/null +++ b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/mc6502/MC6502RegisterFile.v @@ -0,0 +1,254 @@ +// Copyright (c) 2014 Takashi Toyoshima . +// All rights reserved. Use of this source code is governed by a BSD-style +// license that can be found in the LICENSE file. + +module MC6502RegisterFile( + clk, + cen, + rstn, + // InterruptLogic interfaces + il2rf_set_i, + il2rf_set_b, + il2rf_data, + il2rf_set_pcl, + il2rf_set_pch, + il2rf_pushed, + rf2il_s, + rf2il_psr, + rf2il_pc, + // RegisterFile interfaces + mc2rf_fetched, + mc2rf_pushed, + mc2rf_pull, + mc2rf_pc, + mc2rf_set_pc, + mc2rf_psr, + mc2rf_set_psr, + rf2mc_pc, + rf2mc_a, + rf2mc_x, + rf2mc_y, + rf2mc_s, + rf2mc_psr, + // ExecutionController interfaces + ec2rf_c, + ec2rf_set_c, + ec2rf_i, + ec2rf_set_i, + ec2rf_v, + ec2rf_set_v, + ec2rf_d, + ec2rf_set_d, + ec2rf_n, + ec2rf_set_n, + ec2rf_z, + ec2rf_set_z, + ec2rf_data, + ec2rf_set_a, + ec2rf_set_x, + ec2rf_set_y, + ec2rf_set_s, + ec2rf_set_pcl, + ec2rf_set_pch, + rf2ec_pcl, + rf2ec_pch, + rf2ec_a, + rf2ec_x, + rf2ec_y, + rf2ec_c, + rf2ec_d, + rf2ec_n, + rf2ec_v, + rf2ec_z); + input clk; + input cen; + input rstn; + + input il2rf_set_i; + input il2rf_set_b; + input [ 7:0] il2rf_data; + input il2rf_set_pcl; + input il2rf_set_pch; + input il2rf_pushed; + output [ 7:0] rf2il_s; + output [ 7:0] rf2il_psr; + output [15:0] rf2il_pc; + + input mc2rf_fetched; + input mc2rf_pushed; + input mc2rf_pull; + input [15:0] mc2rf_pc; + input mc2rf_set_pc; + input [ 7:0] mc2rf_psr; + input mc2rf_set_psr; + output [15:0] rf2mc_pc; + output [ 7:0] rf2mc_a; + output [ 7:0] rf2mc_x; + output [ 7:0] rf2mc_y; + output [ 7:0] rf2mc_s; + output [ 7:0] rf2mc_psr; + + input ec2rf_c; + input ec2rf_set_c; + input ec2rf_i; + input ec2rf_set_i; + input ec2rf_v; + input ec2rf_set_v; + input ec2rf_d; + input ec2rf_set_d; + input ec2rf_n; + input ec2rf_set_n; + input ec2rf_z; + input ec2rf_set_z; + input [ 7:0] ec2rf_data; + input ec2rf_set_a; + input ec2rf_set_x; + input ec2rf_set_y; + input ec2rf_set_s; + input ec2rf_set_pcl; + input ec2rf_set_pch; + output [ 7:0] rf2ec_pcl; + output [ 7:0] rf2ec_pch; + output [ 7:0] rf2ec_a; + output [ 7:0] rf2ec_x; + output [ 7:0] rf2ec_y; + output rf2ec_c; + output rf2ec_d; + output rf2ec_n; + output rf2ec_v; + output rf2ec_z; + + reg [ 7:0] r_pcl; + reg [ 7:0] r_pch; + reg [ 7:0] r_a; + reg [ 7:0] r_x; + reg [ 7:0] r_y; + reg [ 7:0] r_sp; + + wire w_load_pc; + wire [15:0] w_next_pc; + wire [ 7:0] w_psr; + + wire w_c; + wire w_i; + wire w_v; + wire w_d; + wire w_n; + wire w_z; + wire w_b; + wire w_set_c; + wire w_set_i; + wire w_set_v; + wire w_set_d; + wire w_set_n; + wire w_set_z; + wire w_set_b; + + assign rf2il_s = r_sp; + assign rf2il_psr = w_psr; + assign rf2il_pc = { r_pch, r_pcl }; + + assign rf2mc_pc = { r_pch, r_pcl }; + assign rf2mc_a = r_a; + assign rf2mc_x = r_x; + assign rf2mc_y = r_y; + assign rf2mc_s = r_sp; + assign rf2mc_psr = w_psr; + assign rf2ec_pcl = r_pcl; + assign rf2ec_pch = r_pch; + assign rf2ec_a = r_a; + assign rf2ec_x = r_x; + assign rf2ec_y = r_y; + assign rf2ec_c = w_psr[0]; + assign rf2ec_d = w_psr[3]; + assign rf2ec_n = w_psr[7]; + assign rf2ec_v = w_psr[6]; + assign rf2ec_z = w_psr[1]; + + assign w_load_pc = il2rf_set_pcl | il2rf_set_pch | + ec2rf_set_pcl | ec2rf_set_pch; + assign w_next_pc = { r_pch, r_pcl } + 16'h0001; + + assign w_c = ec2rf_set_c ? ec2rf_c : mc2rf_psr[0]; + assign w_set_c = ec2rf_set_c | mc2rf_set_psr; + assign w_i = ec2rf_set_i ? ec2rf_i : il2rf_set_i ? 1'b1 : mc2rf_psr[2]; + assign w_set_i = ec2rf_set_i | mc2rf_set_psr | il2rf_set_i; + assign w_v = ec2rf_set_v ? ec2rf_v : mc2rf_psr[6]; + assign w_set_v = ec2rf_set_v | mc2rf_set_psr; + assign w_d = ec2rf_set_d ? ec2rf_d : mc2rf_psr[3]; + assign w_set_d = ec2rf_set_d | mc2rf_set_psr; + assign w_n = ec2rf_set_n ? ec2rf_n : mc2rf_psr[7]; + assign w_set_n = ec2rf_set_n | mc2rf_set_psr; + assign w_z = ec2rf_set_z ? ec2rf_z : mc2rf_psr[1]; + assign w_set_z = ec2rf_set_z | mc2rf_set_psr; + assign w_b = il2rf_set_b ? 1'b1 : mc2rf_psr[4]; + assign w_set_b = mc2rf_set_psr | il2rf_set_b; + + always @ (posedge clk or negedge rstn) begin + if (!rstn) begin + r_pcl <= 8'h00; + r_pch <= 8'h00; + r_a <= 8'h00; + r_x <= 8'h00; + r_y <= 8'h00; + r_sp <= 8'h00; + end else if(cen) begin + if (w_load_pc) begin + if (il2rf_set_pcl) begin + r_pcl <= il2rf_data; + end else if (ec2rf_set_pcl) begin + r_pcl <= ec2rf_data; + end + if (il2rf_set_pch) begin + r_pch <= il2rf_data; + end else if (ec2rf_set_pch) begin + r_pch <= ec2rf_data; + end + end else begin + if (mc2rf_fetched) begin + r_pch <= w_next_pc[15:8]; + r_pcl <= w_next_pc[ 7:0]; + end else if (mc2rf_set_pc) begin + r_pch <= mc2rf_pc[15:8]; + r_pcl <= mc2rf_pc[ 7:0]; + end + end // else (w_load_pc) + if (ec2rf_set_a) begin + r_a <= ec2rf_data; + end + if (ec2rf_set_x) begin + r_x <= ec2rf_data; + end + if (ec2rf_set_y) begin + r_y <= ec2rf_data; + end + if (ec2rf_set_s) begin + r_sp <= ec2rf_data; + end else if (mc2rf_pushed | il2rf_pushed) begin + r_sp <= r_sp - 8'h01; + end else if (mc2rf_pull) begin + r_sp <= r_sp + 8'h01; + end + end + end // always @ (posedge clk or negedge rstn) + + MC6502ProcessorStatusRegister ps( + .clk (clk ), + .cen (cen ), + .rstn (rstn ), + .i_c (w_c ), + .i_set_c(w_set_c), + .i_i (w_i ), + .i_set_i(w_set_i), + .i_v (w_v ), + .i_set_v(w_set_v), + .i_d (w_d ), + .i_set_d(w_set_d), + .i_n (w_n ), + .i_set_n(w_set_n), + .i_z (w_z ), + .i_set_z(w_set_z), + .i_b (w_b ), + .i_set_b(w_set_b), + .o_psr (w_psr )); +endmodule // MC6502RegisterFile diff --git a/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/mc6502/MC6502Shifter.v b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/mc6502/MC6502Shifter.v new file mode 100644 index 0000000000000000000000000000000000000000..c84e3f4bda79a075f7b3dcbdef7d4655166bcdad --- /dev/null +++ b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/mc6502/MC6502Shifter.v @@ -0,0 +1,33 @@ +// Copyright (c) 2014 Takashi Toyoshima . +// All rights reserved. Use of this source code is governed by a BSD-style +// license that can be found in the LICENSE file. + +module MC6502Shifter( + i_data, + i_rotate, + i_right, + i_c, + o_data, + o_n, + o_z, + o_c); + input [7:0] i_data; + input i_rotate; + input i_right; + input i_c; + output [7:0] o_data; + output o_n; + output o_z; + output o_c; + + wire [8:0] w_to_left; + wire [8:0] w_to_right; + + assign o_data = i_right ? w_to_right[8:1] : w_to_left[7:0]; + assign o_n = o_data[7]; + assign o_z = o_data == 8'h00; + assign o_c = i_right ? w_to_right[0] : w_to_left[8]; + + assign w_to_left = { i_data, i_rotate ? i_c : 1'b0 }; + assign w_to_right = { i_rotate ? i_c : 1'b0, i_data }; +endmodule // MC6502Shifter diff --git a/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/mc6502/mc6502.f b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/mc6502/mc6502.f new file mode 100644 index 0000000000000000000000000000000000000000..bc1db253871b1bb7547f7b5030ec13a789ef0e57 --- /dev/null +++ b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/mc6502/mc6502.f @@ -0,0 +1,9 @@ +MC6502Accumulator.v +MC6502ExecutionController.v +MC6502InstructionDecode.v +MC6502InterruptLogic.v +MC6502MemoryController.v +MC6502ProcessorStatusRegister.v +MC6502RegisterFile.v +MC6502Shifter.v +MC6502.v diff --git a/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/mc6502/mc6502.qip b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/mc6502/mc6502.qip new file mode 100644 index 0000000000000000000000000000000000000000..43c1024da5091b612c4c5014e99938d22d83bdb0 --- /dev/null +++ b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/mc6502/mc6502.qip @@ -0,0 +1,9 @@ +set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) MC6502Accumulator.v ] +set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) MC6502ExecutionController.v ] +set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) MC6502InstructionDecode.v ] +set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) MC6502InterruptLogic.v ] +set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) MC6502MemoryController.v ] +set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) MC6502ProcessorStatusRegister.v ] +set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) MC6502RegisterFile.v ] +set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) MC6502Shifter.v ] +set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) MC6502.v ] diff --git a/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/pauloblaze/LICENSE b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/pauloblaze/LICENSE new file mode 100644 index 0000000000000000000000000000000000000000..95fd4e70a42126bed2b938c8a2f4187b469b64d9 --- /dev/null +++ b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/pauloblaze/LICENSE @@ -0,0 +1,190 @@ + Apache License + Version 2.0, January 2004 + http://www.apache.org/licenses/ + +TERMS AND CONDITIONS FOR USE, REPRODUCTION, AND DISTRIBUTION + +1. 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However, in accepting such obligations, You may act only + on Your own behalf and on Your sole responsibility, not on behalf + of any other Contributor, and only if You agree to indemnify, + defend, and hold each Contributor harmless for any liability + incurred by, or claims asserted against, such Contributor by reason + of your accepting any such warranty or additional liability. + +END OF TERMS AND CONDITIONS + +Copyright [2016] [Paul Genssler] + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. diff --git a/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/pauloblaze/alu.vhd b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/pauloblaze/alu.vhd new file mode 100644 index 0000000000000000000000000000000000000000..b49ef384f895667e87a16c6bfd1aa52d21a1f480 --- /dev/null +++ b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/pauloblaze/alu.vhd @@ -0,0 +1,289 @@ +-- EMACS settings: -*- tab-width: 4; indent-tabs-mode: t -*- +-- vim: tabstop=4:shiftwidth=4:noexpandtab +-- kate: tab-width 4; replace-tabs off; indent-width 4; +-- +-- ============================================================================= +-- Authors: Paul Genssler +-- +-- Description: +-- ------------------------------------ +-- TODO +-- +-- License: +-- ============================================================================= +-- Copyright 2007-2015 Paul Genssler - Dresden, Germany +-- +-- Licensed under the Apache License, Version 2.0 (the "License"); +-- you may not use this file except in compliance with the License. +-- You may obtain a copy of the License at +-- +-- http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Unless required by applicable law or agreed to in writing, software +-- distributed under the License is distributed on an "AS is" BASIS, +-- WITHOUT WARRANTIES or CONDITIONS of ANY KIND, either express or implied. +-- See the License for the specific language governing permissions and +-- limitations under the License. +-- ============================================================================= + +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use IEEE.NUMERIC_STD.all; +use work.op_codes.all; + +entity pauloALU is + generic ( + debug : boolean := false; + hwbuild : unsigned(7 downto 0) := X"41" + ); + port ( + clk : in STD_LOGIC; + clk2 : in STD_LOGIC; + reset : in STD_LOGIC; + sleep_int : in STD_LOGIC; + opcode : in unsigned (5 downto 0); + opB : in unsigned (7 downto 0); + preserve_flags : in std_logic; + restore_flags : in std_logic; + carry : out STD_LOGIC; + zero : out STD_LOGIC; + + reg_value : out unsigned (7 downto 0); + reg_we : out std_logic; + reg_reg0 : in unsigned (7 downto 0); + reg_reg1 : in unsigned (7 downto 0) + ); +end pauloALU; + +architecture Behavioral of pauloALU is + + + signal result : unsigned(7 downto 0); + signal res_valid : std_logic; -- result should be written to register + + signal inter_flank : std_logic; + signal carry_c : std_logic; + signal carry_o : std_logic; + signal carry_i : std_logic; -- saved during interrupt + signal zero_i : std_logic; -- same + signal zero_c : std_logic; + signal zero_o : std_logic; + + -- signal debug_opA_value : unsigned(7 downto 0); + -- signal debug_opB_value : unsigned(7 downto 0); + +begin + + process (clk) + begin + if rising_edge(clk) then + reg_value <= result; + reg_we <= not clk2 and res_valid and not sleep_int; + end if; + end process; + + carry <= carry_o; + zero <= zero_o; + + op : process (reset, opcode, opB, carry_o, zero_o, reg_reg0, reg_reg1, clk2) + variable opB_value : unsigned(7 downto 0); + variable opA_value : unsigned(7 downto 0); + variable result_v : unsigned(8 downto 0); + variable parity_v : std_logic; + variable padding : std_logic; + variable tmp : std_logic; + begin + opA_value := reg_reg0; + if (opcode (0) = '0') then -- LSB 0 = op_x sx, sy + opB_value := reg_reg1; + else -- LSB 1 = op_x sx, kk + opB_value := opB; + end if; + + if (debug) then + padding := '0'; --looks better during simulation + -- debug_opA_value <= opA_value; + -- debug_opB_value <= opB_value; + else + padding := '-'; + end if; + res_valid <= '0'; + carry_c <= carry_o; + zero_c <= zero_o; + result_v := (others => padding); + parity_v := '0'; + + if (reset = '0') then + case opcode is + --register loading + when OP_LOAD_SX_SY | OP_LOAD_SX_KK | OP_LOADRETURN_SX_KK => + result_v := padding & opB_value; + res_valid <= '1'; + when OP_STAR_SX_SY => + --Logical + when OP_AND_SX_SY | OP_AND_SX_KK => + result_v := padding & (opA_value and opB_value); + res_valid <= '1'; + if (result_v(7 downto 0) = "00000000") then + zero_c <= '1'; + else + zero_c <= '0'; + end if; + carry_c <= '0'; + when OP_OR_SX_SY | OP_OR_SX_KK => + result_v := padding & (opA_value or opB_value); + res_valid <= '1'; + if (result_v(7 downto 0) = "00000000") then + zero_c <= '1'; + else + zero_c <= '0'; + end if; + carry_c <= '0'; + when OP_XOR_SX_SY | OP_XOR_SX_KK => + result_v := padding & (opA_value xor opB_value); + res_valid <= '1'; + if (result_v(7 downto 0) = "00000000") then + zero_c <= '1'; + else + zero_c <= '0'; + end if; + carry_c <= '0'; + --Arithmetic + when OP_ADD_SX_SY | OP_ADD_SX_KK | OP_SUB_SX_SY | OP_SUB_SX_KK | + OP_ADDCY_SX_SY | OP_ADDCY_SX_KK | OP_SUBCY_SX_SY | OP_SUBCY_SX_KK => + if (opcode(3) = '0') then + result_v := ('0' & opA_value) + ('0' & opB_value) + ("" & (carry_o and opCode(1))); + else + result_v := ('0' & opA_value) - ('0' & opB_value) - ("" & (carry_o and opCode(1))); + end if; + + if (result_v(7 downto 0) = "00000000") then + if (opcode = OP_ADDCY_SX_SY or opcode = OP_ADDCY_SX_KK or opcode = OP_SUBCY_SX_SY or opcode = OP_SUBCY_SX_KK) then + zero_c <= zero_o; + else + zero_c <= '1'; + end if; + else + zero_c <= '0'; + end if; + carry_c <= result_v(8); + res_valid <= '1'; + --Test and Compare + when OP_TEST_SX_SY | OP_TEST_SX_KK | OP_TESTCY_SX_SY | OP_TESTCY_SX_KK => + result_v := (padding & (opA_value and opB_value)); + -- opCode(1) == 0 : TEST + -- opCode(1) == 1 : TESTCY + if (result_v(7 downto 0) = "00000000") then + if (opCode(1) = '0') then + zero_c <= '1'; + else + zero_c <= zero_o; + end if; + else + zero_c <= '0'; + end if; + + for i in 0 to 7 loop + parity_v := parity_v xor result_v(i); + end loop; + if (opCode(1) = '0') then + -- TEST + carry_c <= parity_v; + else + -- TESTCY + carry_c <= parity_v xor carry_o; + end if; + when OP_COMPARE_SX_SY | OP_COMPARE_SX_KK | OP_COMPARECY_SX_SY | OP_COMPARECY_SX_KK => + -- opCode(1) == 0 : COMPARE + -- opCode(1) == 1 : COMPARECY + -- mask carry with it + result_v := ('0' & opA_value) - ('0' & opB_value) - ("" & (opCode(1) and carry_o)); + + if (result_v(7 downto 0) = "00000000") then + if (opCode(1) = '0') then + zero_c <= '1'; + else + zero_c <= zero_o; + end if; + else + zero_c <= '0'; + end if; + + carry_c <= result_v(8); + --Shift and Rotate ... and hwbuild OP_HWBUILD_SX + when OP_SL0_SX => + if (opB(7) = '1') then -- hw build op + result_v := padding & hwbuild; + res_valid <= '1'; + carry_c <= '1'; + if (result_v(7 downto 0) = "00000000") then + zero_c <= '1'; + else + zero_c <= '0'; + end if; + else + -- shift and rotate + case opB(2 downto 0) is + when "110" | "111" => + tmp := opB(0); + when "010" => -- RL + tmp := opA_value(7); + when "100" => -- RR + tmp := opA_value(0); + when "000" => + tmp := carry_o; + when others => + tmp := '0'; + end case; + + if (opB(3) = '1') then + result_v := opA_value(0) & tmp & opA_value(7 downto 1); + else -- concat the carry value into the result and shift + result_v := opA_value(7) & opA_value(6 downto 0) & tmp; + end if; + + carry_c <= result_v(8); + if (result_v(7 downto 0) = "00000000") then + zero_c <= '1'; + else + zero_c <= '0'; + end if; + res_valid <= '1'; + end if; + when others => + result_v := (others => padding); + end case; + end if; + result <= result_v(7 downto 0); + end process; + + flags : process (clk) begin + if (rising_edge(clk)) then + if (reset = '1') then + carry_o <= '0'; + zero_o <= '0'; + carry_i <= '0'; + zero_i <= '0'; + else + if (preserve_flags = '1') then + -- preserve flags + carry_i <= carry_o; + zero_i <= zero_o; + end if; + if (restore_flags = '1') then + -- restore flags + carry_o <= carry_i; + zero_o <= zero_i; + elsif (clk2 = '1') then + carry_o <= carry_c; + zero_o <= zero_c; + else + carry_o <= carry_o; + zero_o <= zero_o; + end if; + end if; + end if; + end process flags; + +end Behavioral; + diff --git a/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/pauloblaze/decoder.vhd b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/pauloblaze/decoder.vhd new file mode 100644 index 0000000000000000000000000000000000000000..d4d827a291b2506d98d32e61df2d36b15d79efdc --- /dev/null +++ b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/pauloblaze/decoder.vhd @@ -0,0 +1,370 @@ +-- EMACS settings: -*- tab-width: 4; indent-tabs-mode: t -*- +-- vim: tabstop=4:shiftwidth=4:noexpandtab +-- kate: tab-width 4; replace-tabs off; indent-width 4; +-- +-- ============================================================================= +-- Authors: Paul Genssler +-- +-- Description: +-- ------------------------------------ +-- TODO +-- +-- License: +-- ============================================================================= +-- Copyright 2007-2015 Paul Genssler - Dresden, Germany +-- +-- Licensed under the Apache License, Version 2.0 (the "License"); +-- you may not use this file except in compliance with the License. +-- You may obtain a copy of the License at +-- +-- http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Unless required by applicable law or agreed to in writing, software +-- distributed under the License is distributed on an "AS is" BASIS, +-- WITHOUT WARRANTIES or CONDITIONS of ANY KIND, either express or implied. +-- See the License for the specific language governing permissions and +-- limitations under the License. +-- ============================================================================= + +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.NUMERIC_STD.ALL; +use work.op_codes.all; + +entity decoder is + generic ( + interrupt_vector : unsigned(11 downto 0) := X"3FF" + ); + Port ( + clk : in STD_LOGIC; + clk2 : in STD_LOGIC; + reset : in STD_LOGIC; + reset_int : out STD_LOGIC; + reset_bram_en : out STD_LOGIC; + rst_req : in std_logic; + sleep : in STD_LOGIC; + sleep_int : out STD_LOGIC; + bram_pause : out STD_LOGIC; + clk2_reset : out STD_LOGIC; + interrupt : in STD_LOGIC; + interrupt_ack : out STD_LOGIC; + instruction : in unsigned (17 downto 0); + opCode : out unsigned (5 downto 0); + opA : out unsigned (3 downto 0); + opB : out unsigned (7 downto 0); + reg0 : in unsigned (7 downto 0); + reg1 : in unsigned (7 downto 0); + carry : in STD_LOGIC; + zero : in STD_LOGIC; + call : out STD_LOGIC; + ret : out std_logic; + inter_j : out std_logic; + preserve_flags : out std_logic; + restore_flags : out std_logic; + jump : out STD_LOGIC; + jmp_addr : out unsigned (11 downto 0); + io_op_in : out std_logic; + io_op_out : out std_logic; + io_op_out_pp : out std_logic; + io_kk_en : out std_logic; + io_kk_port : out unsigned (3 downto 0); + io_kk_data : out unsigned (7 downto 0); + reg_address : out unsigned (7 downto 0); + reg_select : out std_logic; + reg_star : out std_logic; + spm_addr_ss : out unsigned (7 downto 0); + spm_ss : out std_logic; -- 0: spm_addr = reg1, 1: spm_addr = spm_addr_ss + spm_we : out std_logic; + spm_rd : out std_logic + ); +end decoder; + +architecture Behavioral of decoder is + + signal clk2_reset_sleep : std_logic; + signal clk2_reset_reset : std_logic; + signal reset_int_o : std_logic; + signal reset_r : std_logic; + signal reg_select_o : std_logic; + signal reg_select_i : std_logic; + signal opCode_o : unsigned (5 downto 0); + signal fetch : std_logic; + signal store : std_logic; + signal inter_en : std_logic; + signal inter_j_o : std_logic; + signal inter_block_regs : std_logic; + signal preserve_flags_o : std_logic; + signal restore_flags_o : std_logic; + signal instr_used : unsigned (17 downto 0); + signal sleep_int_o : std_logic; + signal reg_sel_save : std_logic; + signal sxy_addr : std_logic; + + signal bram_pause_sleep : std_logic; + signal bram_pause_reset : std_logic; + + type sleep_state_t is (awake, sleeping, dawn, sunrise); + signal sleep_state : sleep_state_t; + + type interrupt_state_t is (none, detected, inter_ack, interrupting, int_end); + signal inter_state : interrupt_state_t; + signal inter_state_nxt : interrupt_state_t; + + type reset_state_t is (none, detected, finishing, holding, bram_en); + signal reset_state : reset_state_t; + signal reset_state_nxt : reset_state_t; + +begin + reset_int <= reset_int_o; + clk2_reset <= clk2_reset_sleep or clk2_reset_reset; + bram_pause <= bram_pause_sleep or bram_pause_reset; + + opCode <= opCode_o; + opCode_o <= instr_used(17 downto 12); + opA <= instr_used(11 downto 8); + opB <= instr_used(7 downto 0); + jmp_addr <= instr_used(11 downto 0) when sxy_addr = '0' else reg0(3 downto 0) & reg1; + + reg_address <= instr_used(11 downto 4); + reg_select <= reg_select_o; + + spm_addr_ss <= instr_used(7 downto 0); + spm_ss <= opCode_o(0); + spm_rd <= fetch; + + io_op_out_pp <= instr_used(12); -- constant value (pp) or register as data on the output + io_kk_data <= instr_used(11 downto 4); + io_kk_port <= instr_used(3 downto 0); + + sleep_int <= sleep_int_o or inter_block_regs; + inter_j <= inter_j_o; + + restore_flags <= restore_flags_o; + + decompose : process (instr_used, reset_int_o, zero, carry, opCode_o) + begin + jump <= '0'; + sxy_addr <= '0'; + call <= '0'; + ret <= '0'; + io_op_in <= '0'; + io_op_out <= '0'; + io_kk_en <= '0'; + fetch <= '0'; + store <= '0'; + + if (reset_int_o = '0') then + case opCode_o is + when OP_JUMP_AAA => + jump <= '1'; + when OP_JUMP_SX_SY => + jump <= '1'; + sxy_addr <= '1'; + when OP_JUMP_Z_AAA | OP_JUMP_NZ_AAA => + jump <= zero xor instr_used(14); -- inst(14) == opCode_o(2): 0 -> Z; 1 -> NZ + when OP_JUMP_C_AAA | OP_JUMP_NC_AAA => + jump <= carry xor instr_used(14); -- inst(14) == opCode_o(2): 0 -> C; 1 -> NC + when OP_CALL_AAA => + call <= '1'; + when OP_CALL_SX_SY => + call <= '1'; + sxy_addr <= '1'; + when OP_CALL_Z_AAA | OP_CALL_NZ_AAA => + call <= zero xor instr_used(14); -- inst(14) == opCode_o(2): 0 -> Z; 1 -> NZ + when OP_CALL_C_AAA | OP_CALL_NC_AAA => + call <= carry xor instr_used(14); -- inst(14) == opCode_o(2): 0 -> C; 1 -> NC + when OP_RETURN | OP_RETURNI_DISABLE | OP_LOADRETURN_SX_KK => + ret <= '1'; + when OP_RETURN_Z | OP_RETURN_NZ => + ret <= zero xor instr_used(14); -- inst(14) == opCode_o(2): 0 -> Z; 1 -> NZ + when OP_RETURN_C | OP_RETURN_NC => + ret <= carry xor instr_used(14); -- inst(14) == opCode_o(2): 0 -> C; 1 -> NC + when OP_INPUT_SX_SY | OP_INPUT_SX_PP => + io_op_in <= '1'; + when OP_OUTPUT_SX_SY | OP_OUTPUT_SX_PP => + io_op_out <= '1'; + when OP_OUTPUTK_KK_P => + io_kk_en <= '1'; + when OP_FETCH_SX_SY | OP_FETCH_SX_SS => +-- spm_rd <= '1'; + fetch <= '1'; + when OP_STORE_SX_SY | OP_STORE_SX_SS => +-- spm_we <= '1'; + store <= '1'; + when others => + + end case; + end if; + end process decompose; + + reg_proc : process (clk) begin + if (rising_edge(clk)) then + if (reset_int_o = '1') then + reg_select_o <= '0'; + reg_sel_save <= '0'; + else + reg_star <= '0'; + spm_we <= store and not clk2; + + if (preserve_flags_o = '1') then + reg_sel_save <= reg_select_o; + elsif (restore_flags_o = '1') then + reg_select_o <= reg_sel_save; + elsif (opCode_o = OP_REGBANK_A) then + reg_select_o <= instr_used(0); + elsif (opCode_o = OP_STAR_SX_SY) then + reg_select_o <= not reg_select_o; + reg_star <= '1'; + end if; + end if; + end if; + end process reg_proc; + + inter_en_p : process (clk) begin + if (rising_edge(clk)) then + if (reset_int_o = '1') then + inter_en <= '0'; + else + if (opCode_o = OP_ENABLE_INTERRUPT or opCode_o = OP_RETURNI_ENABLE) then + inter_en <= instr_used(0); -- bit 0 contains set/erase + else + inter_en <= inter_en; + end if; + end if; + end if; + end process inter_en_p; + + inter_state_com_p : process (inter_state, instruction, interrupt, inter_en, clk2, opCode_o) begin + inter_state_nxt <= inter_state; + instr_used <= instruction; + preserve_flags_o <= '0'; + inter_j_o <= '0'; + interrupt_ack <= '0'; + inter_block_regs <= '0'; + restore_flags_o <= '0'; + + case (inter_state) is + when none => + if (interrupt = '1') then + inter_state_nxt <= detected; + end if; + when detected => + if (inter_en = '1' and clk2 = '0') then + inter_block_regs <= '1'; + inter_state_nxt <= inter_ack; + end if; + when inter_ack => + instr_used <= (others => '0'); + preserve_flags_o <= '1'; + interrupt_ack <= '1'; + inter_block_regs <= '1'; + inter_j_o <= '1'; + inter_state_nxt <= interrupting; + when interrupting => + if (opCode_o = OP_RETURNI_ENABLE and clk2 = '1') then + inter_state_nxt <= int_end; + restore_flags_o <= '1'; + end if; + when int_end => + inter_state_nxt <= none; + end case; + end process inter_state_com_p; + + inter_state_clk_p : process (clk) begin + if (rising_edge(clk)) then + if (reset_int_o = '1') then + inter_state <= none; + else + if (sleep = '0') then + inter_state <= inter_state_nxt; + preserve_flags <= preserve_flags_o; + end if; + end if; + end if; + end process inter_state_clk_p; + + + sleep_sm : process (clk) begin + if (rising_edge(clk)) then + if (reset_int_o = '1') then + sleep_state <= awake; + bram_pause_sleep <= '0'; + sleep_int_o <= '0'; + clk2_reset_sleep <= '0'; + else + bram_pause_sleep <= '0'; + sleep_int_o <= '0'; + clk2_reset_sleep <= '0'; + case sleep_state is + when awake => + if (sleep = '1') then + sleep_state <= sleeping; + end if; + when sleeping => + bram_pause_sleep <= '1'; + sleep_int_o <= '1'; + if (sleep = '0') then + clk2_reset_sleep <= '1'; + sleep_int_o <= '0'; + sleep_state <= dawn; + + if (clk2 = '1') then + bram_pause_sleep <= '0'; + end if; + end if; + when dawn => + sleep_state <= sunrise; + when sunrise => + sleep_int_o <= '1'; + if (clk2 = '1') then + sleep_int_o <= '0'; + sleep_state <= awake; + end if; + end case; + end if; + end if; + end process sleep_sm; + + + rst_state_com_p : process (reset, rst_req, reset_state) begin + reset_state_nxt <= reset_state; + reset_int_o <= '0'; + bram_pause_reset <= '0'; + reset_bram_en <= '0'; + clk2_reset_reset <= '0'; + case (reset_state) is + when none => + if (reset = '1') then + reset_state_nxt <= detected; + elsif (rst_req = '1') then + reset_state_nxt <= holding; + end if; + when detected => + bram_pause_reset <= '1'; + reset_int_o <= '1'; + if (reset = '0') then + reset_state_nxt <= finishing; + end if; + when finishing => + bram_pause_reset <= '1'; + reset_int_o <= '1'; + reset_state_nxt <= holding; + when holding => + bram_pause_reset <= '1'; + reset_int_o <= '1'; + clk2_reset_reset <= '1'; + reset_state_nxt <= bram_en; + when bram_en => + reset_int_o <= '1'; + reset_bram_en <= '1'; + reset_state_nxt <= none; + end case; + end process rst_state_com_p; + + rst_state_clk_p : process (clk) begin + if (rising_edge(clk)) then + reset_state <= reset_state_nxt; + end if; + end process rst_state_clk_p; + +end Behavioral; diff --git a/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/pauloblaze/io_module.vhd b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/pauloblaze/io_module.vhd new file mode 100644 index 0000000000000000000000000000000000000000..57d168251f8581fd779fb847afdb584a366a98a9 --- /dev/null +++ b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/pauloblaze/io_module.vhd @@ -0,0 +1,106 @@ +-- EMACS settings: -*- tab-width: 4; indent-tabs-mode: t -*- +-- vim: tabstop=4:shiftwidth=4:noexpandtab +-- kate: tab-width 4; replace-tabs off; indent-width 4; +-- +-- ============================================================================= +-- Authors: Paul Genssler +-- +-- Description: +-- ------------------------------------ +-- TODO +-- +-- License: +-- ============================================================================= +-- Copyright 2007-2015 Paul Genssler - Dresden, Germany +-- +-- Licensed under the Apache License, Version 2.0 (the "License"); +-- you may not use this file except in compliance with the License. +-- You may obtain a copy of the License at +-- +-- http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Unless required by applicable law or agreed to in writing, software +-- distributed under the License is distributed on an "AS is" BASIS, +-- WITHOUT WARRANTIES or CONDITIONS of ANY KIND, either express or implied. +-- See the License for the specific language governing permissions and +-- limitations under the License. +-- ============================================================================= + +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.NUMERIC_STD.ALL; +use work.op_codes.all; + +entity io_module is + Port ( + clk : in STD_LOGIC; + clk2 : in STD_LOGIC; + reset : in std_logic; + reg_value : out unsigned (7 downto 0); + reg_we : out std_logic; + reg_reg0 : in unsigned (7 downto 0); + reg_reg1 : in unsigned (7 downto 0); + out_data : in unsigned (7 downto 0); + io_op_in : in std_logic; + io_op_out : in std_logic; + io_op_out_pp : in std_logic; + io_kk_en : in std_logic; + io_kk_port : in unsigned (3 downto 0); + io_kk_data : in unsigned (7 downto 0); + -- actual i/o module ports + in_port : in unsigned (7 downto 0); + port_id : out unsigned (7 downto 0); + out_port : out unsigned (7 downto 0); + read_strobe : out STD_LOGIC; + write_strobe : out STD_LOGIC; + k_write_strobe : out STD_LOGIC + ); +end io_module; + +architecture Behavioral of io_module is + + signal strobe_o : std_logic; + +begin + + reg_value <= in_port; + read_strobe <= io_op_in and not clk2; + write_strobe <= io_op_out and strobe_o and clk2; + k_write_strobe <= io_kk_en and strobe_o and clk2; + reg_we <= io_op_in and clk2; + + out_proc : process (reset, out_data, reg_reg0, reg_reg1, io_kk_en, io_kk_port, io_kk_data, io_op_out_pp) begin + if (reset = '1') then + port_id <= (others => '0'); + out_port <= (others => '0'); + else + if (io_kk_en = '1') then + port_id <= x"0" & io_kk_port; + out_port <= io_kk_data; + else + out_port <= reg_reg0; + if (io_op_out_pp = '1') then -- intermediate value pp + port_id <= out_data; + else + port_id <= reg_reg1; + end if; + end if; + end if; + end process out_proc; + + process (clk) begin + if (rising_edge(clk)) then + if (reset = '1') then + strobe_o <= '0'; + else + if ((io_op_in or io_op_out or io_kk_en) = '1') then + strobe_o <= '1'; + else + strobe_o <= '0'; + end if; + end if; + end if; + end process; + +end Behavioral; + diff --git a/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/pauloblaze/op_codes.vhd b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/pauloblaze/op_codes.vhd new file mode 100644 index 0000000000000000000000000000000000000000..51dd6258cca904a269c3f6a40f63a74e0b4dcaf1 --- /dev/null +++ b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/pauloblaze/op_codes.vhd @@ -0,0 +1,122 @@ +-- EMACS settings: -*- tab-width: 4; indent-tabs-mode: t -*- +-- vim: tabstop=4:shiftwidth=4:noexpandtab +-- kate: tab-width 4; replace-tabs off; indent-width 4; +-- +-- ============================================================================= +-- Authors: Paul Genssler +-- +-- Description: +-- ------------------------------------ +-- TODO +-- +-- License: +-- ============================================================================= +-- Copyright 2007-2015 Paul Genssler - Dresden, Germany +-- +-- Licensed under the Apache License, Version 2.0 (the "License"); +-- you may not use this file except in compliance with the License. +-- You may obtain a copy of the License at +-- +-- http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Unless required by applicable law or agreed to in writing, software +-- distributed under the License is distributed on an "AS is" BASIS, +-- WITHOUT WARRANTIES or CONDITIONS of ANY KIND, either express or implied. +-- See the License for the specific language governing permissions and +-- limitations under the License. +-- ============================================================================= + + +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use IEEE.NUMERIC_STD.ALL; + +package op_codes is + +constant OP_LOAD_SX_SY : unsigned(5 downto 0) := "000000"; +constant OP_LOAD_SX_KK : unsigned(5 downto 0) := "000001"; +constant OP_STAR_SX_SY : unsigned(5 downto 0) := "010110"; + +constant OP_AND_SX_SY : unsigned(5 downto 0) := "000010"; +constant OP_AND_SX_KK : unsigned(5 downto 0) := "000011"; +constant OP_OR_SX_SY : unsigned(5 downto 0) := "000100"; +constant OP_OR_SX_KK : unsigned(5 downto 0) := "000101"; +constant OP_XOR_SX_SY : unsigned(5 downto 0) := "000110"; +constant OP_XOR_SX_KK : unsigned(5 downto 0) := "000111"; + +constant OP_ADD_SX_SY : unsigned(5 downto 0) := "010000"; +constant OP_ADD_SX_KK : unsigned(5 downto 0) := "010001"; +constant OP_ADDCY_SX_SY : unsigned(5 downto 0) := "010010"; +constant OP_ADDCY_SX_KK : unsigned(5 downto 0) := "010011"; +constant OP_SUB_SX_SY : unsigned(5 downto 0) := "011000"; +constant OP_SUB_SX_KK : unsigned(5 downto 0) := "011001"; +constant OP_SUBCY_SX_SY : unsigned(5 downto 0) := "011010"; +constant OP_SUBCY_SX_KK : unsigned(5 downto 0) := "011011"; + +constant OP_TEST_SX_SY : unsigned(5 downto 0) := "001100"; +constant OP_TEST_SX_KK : unsigned(5 downto 0) := "001101"; +constant OP_TESTCY_SX_SY : unsigned(5 downto 0) := "001110"; +constant OP_TESTCY_SX_KK : unsigned(5 downto 0) := "001111"; +constant OP_COMPARE_SX_SY : unsigned(5 downto 0) := "011100"; +constant OP_COMPARE_SX_KK : unsigned(5 downto 0) := "011101"; +constant OP_COMPARECY_SX_SY : unsigned(5 downto 0) := "011110"; +constant OP_COMPARECY_SX_KK : unsigned(5 downto 0) := "011111"; + +constant OP_SL0_SX : unsigned(5 downto 0) := "010100"; +constant OP_SL1_SX : unsigned(5 downto 0) := "010100"; +constant OP_SLX_SX : unsigned(5 downto 0) := "010100"; +constant OP_SLA_SX : unsigned(5 downto 0) := "010100"; +constant OP_RL_SX : unsigned(5 downto 0) := "010100"; +constant OP_SR0_SX : unsigned(5 downto 0) := "010100"; +constant OP_SR1_SX : unsigned(5 downto 0) := "010100"; +constant OP_SRX_SX : unsigned(5 downto 0) := "010100"; +constant OP_SRA_SX : unsigned(5 downto 0) := "010100"; +constant OP_RR_SX : unsigned(5 downto 0) := "010100"; + +constant OP_REGBANK_A : unsigned(5 downto 0) := "110111"; +constant OP_REGBANK_B : unsigned(5 downto 0) := "110111"; + +constant OP_INPUT_SX_SY : unsigned(5 downto 0) := "001000"; +constant OP_INPUT_SX_PP : unsigned(5 downto 0) := "001001"; +constant OP_OUTPUT_SX_SY : unsigned(5 downto 0) := "101100"; +constant OP_OUTPUT_SX_PP : unsigned(5 downto 0) := "101101"; +constant OP_OUTPUTK_KK_P : unsigned(5 downto 0) := "101011"; + + +constant OP_STORE_SX_SY : unsigned(5 downto 0) := "101110"; +constant OP_STORE_SX_SS : unsigned(5 downto 0) := "101111"; +constant OP_FETCH_SX_SY : unsigned(5 downto 0) := "001010"; +constant OP_FETCH_SX_SS : unsigned(5 downto 0) := "001011"; + +constant OP_DISABLE_INTERRUPT : unsigned(5 downto 0) := "101000"; +constant OP_ENABLE_INTERRUPT : unsigned(5 downto 0) := "101000"; +constant OP_RETURNI_DISABLE : unsigned(5 downto 0) := "101001"; +constant OP_RETURNI_ENABLE : unsigned(5 downto 0) := "101001"; + +constant OP_JUMP_AAA : unsigned(5 downto 0) := "100010"; +constant OP_JUMP_Z_AAA : unsigned(5 downto 0) := "110010"; +constant OP_JUMP_NZ_AAA : unsigned(5 downto 0) := "110110"; +constant OP_JUMP_C_AAA : unsigned(5 downto 0) := "111010"; +constant OP_JUMP_NC_AAA : unsigned(5 downto 0) := "111110"; +constant OP_JUMP_SX_SY : unsigned(5 downto 0) := "100110"; + +constant OP_CALL_AAA : unsigned(5 downto 0) := "100000"; +constant OP_CALL_Z_AAA : unsigned(5 downto 0) := "110000"; +constant OP_CALL_NZ_AAA : unsigned(5 downto 0) := "110100"; +constant OP_CALL_C_AAA : unsigned(5 downto 0) := "111000"; +constant OP_CALL_NC_AAA : unsigned(5 downto 0) := "111100"; +constant OP_CALL_SX_SY : unsigned(5 downto 0) := "100100"; +constant OP_RETURN : unsigned(5 downto 0) := "100101"; +constant OP_RETURN_Z : unsigned(5 downto 0) := "110001"; +constant OP_RETURN_NZ : unsigned(5 downto 0) := "110101"; +constant OP_RETURN_C : unsigned(5 downto 0) := "111001"; +constant OP_RETURN_NC : unsigned(5 downto 0) := "111101"; +constant OP_LOADRETURN_SX_KK : unsigned(5 downto 0) := "100001"; + +constant OP_HWBUILD_SX : unsigned(5 downto 0) := "010100"; + +end op_codes; + +package body op_codes is + +end op_codes; diff --git a/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/pauloblaze/pauloBlaze.vhd b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/pauloblaze/pauloBlaze.vhd new file mode 100644 index 0000000000000000000000000000000000000000..1d12a0e34fe4fe3a77f26131c183a0f318d0353e --- /dev/null +++ b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/pauloblaze/pauloBlaze.vhd @@ -0,0 +1,281 @@ +-- EMACS settings: -*- tab-width: 4; indent-tabs-mode: t -*- +-- vim: tabstop=4:shiftwidth=4:noexpandtab +-- kate: tab-width 4; replace-tabs off; indent-width 4; +-- +-- ============================================================================= +-- Authors: Paul Genssler +-- +-- Description: +-- ------------------------------------ +-- TODO +-- +-- License: +-- ============================================================================= +-- Copyright 2007-2015 Paul Genssler - Dresden, Germany +-- +-- Licensed under the Apache License, Version 2.0 (the "License"); +-- you may not use this file except in compliance with the License. +-- You may obtain a copy of the License at +-- +-- http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Unless required by applicable law or agreed to in writing, software +-- distributed under the License is distributed on an "AS is" BASIS, +-- WITHOUT WARRANTIES or CONDITIONS of ANY KIND, either express or implied. +-- See the License for the specific language governing permissions and +-- limitations under the License. +-- ============================================================================= + +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use IEEE.NUMERIC_STD.all; + +entity pauloBlaze is + generic ( + debug : boolean := false; + hwbuild : unsigned(7 downto 0) := X"00"; + interrupt_vector : unsigned(11 downto 0) := X"3FF"; + scratch_pad_memory_size : integer := 64; + stack_depth : positive := 30 + ); + port ( + -- control + clk : in std_logic; + reset : in std_logic; + sleep : in std_logic; + -- instruction memory + address : out std_logic_vector(11 downto 0); + instruction : in std_logic_vector(17 downto 0); + bram_enable : out std_logic; + -- i/o ports + in_port : in std_logic_vector(7 downto 0); + out_port : out std_logic_vector(7 downto 0); + port_id : out std_logic_vector(7 downto 0); + write_strobe : out std_logic; + k_write_strobe : out std_logic; + read_strobe : out std_logic; + -- interrupts + interrupt : in std_logic; + interrupt_ack : out std_logic + ); +end pauloBlaze; +architecture Behavioral of pauloBlaze is + + signal clk2 : std_logic := '1'; -- high during 2nd clk cycle + + -- used for converting from slv to my internal unsigned + signal address_u : unsigned(11 downto 0); + signal instruction_u : unsigned(17 downto 0); + signal in_port_u : unsigned(7 downto 0); + signal out_port_u : unsigned(7 downto 0); + signal port_id_u : unsigned(7 downto 0); + + -- signals alu in + signal opcode : unsigned(5 downto 0); + signal opA : unsigned(3 downto 0); + signal opB : unsigned(7 downto 0); + -- signals alu out + signal carry : STD_LOGIC; + signal zero : STD_LOGIC; + + -- signals pc in + signal rst_req : STD_LOGIC; + signal ret : STD_LOGIC; + signal call : STD_LOGIC; + signal jump : STD_LOGIC; + signal jmp_addr : unsigned (11 downto 0); + + -- signals decoder + signal reset_int : std_logic; + signal reset_bram_en : std_logic; + signal io_op_in : std_logic; + signal io_op_out : std_logic; + signal io_op_out_pp : std_logic; + signal io_kk_en : std_logic; + signal io_kk_port : unsigned (3 downto 0); + signal io_kk_data : unsigned (7 downto 0); + signal spm_addr_ss : unsigned (7 downto 0); + signal spm_ss : std_logic; + signal spm_we : std_logic; + signal spm_rd : std_logic; + signal inter_j : std_logic; + signal sleep_int : std_logic; + signal bram_pause : std_logic; + signal clk2_reset : std_logic; + signal preserve_flags : std_logic; + signal restore_flags : std_logic; + + -- general register file signals + signal reg_select : std_logic; + signal reg_star : std_logic; + signal reg_reg0 : unsigned (7 downto 0); + signal reg_reg1 : unsigned (7 downto 0); + signal reg_address : unsigned (7 downto 0); + signal reg_value : unsigned (7 downto 0); + signal reg_we : std_logic; + -- signals register file from alu + signal reg_value_a : unsigned (7 downto 0); + signal reg_we_a : std_logic; + -- signals register file from io + signal reg_value_io : unsigned (7 downto 0); + signal reg_we_io : std_logic; + + +begin + bram_enable <= clk2 and not bram_pause when reset_int = '0' else reset_bram_en; + -- in case of a reset there is a state where reset_bram_en will be high for one clk cycle, just before + -- the internal reset will be deasserted + + clk2_gen : process (clk) begin + if (rising_edge(clk)) then + if (clk2_reset = '1') then + clk2 <= '1'; + else + clk2 <= not clk2; + end if; + end if; + end process clk2_gen; + + address <= std_logic_vector(address_u); + instruction_u <= unsigned(instruction); + in_port_u <= unsigned(in_port); + out_port <= std_logic_vector(out_port_u); + port_id <= std_logic_vector(port_id_u); + + pc : entity work.program_counter + generic map( + interrupt_vector => interrupt_vector, + stack_depth => stack_depth + ) + port map( + clk => clk, + reset => reset_int, + rst_req => rst_req, + bram_pause => bram_pause, + call => call, + ret => ret, + inter_j => inter_j, + jump => jump, + jmp_addr => jmp_addr, + address => address_u + ); + + -- alu + alu_inst : entity work.pauloALU + generic map( + hwbuild => hwbuild, + debug => debug + ) + port map( + clk => clk, + clk2 => clk2, + reset => reset_int, + sleep_int => sleep_int, + opcode => opcode, + -- opA => opA, + opB => opB, + preserve_flags => preserve_flags, + restore_flags => restore_flags, + carry => carry, + zero => zero, + reg_value => reg_value_a, + reg_we => reg_we_a, + reg_reg0 => reg_reg0, + reg_reg1 => reg_reg1 + ); + + decoder_inst : entity work.decoder + generic map( + interrupt_vector => interrupt_vector + ) + port map( + clk => clk, + clk2 => clk2, + reset => reset, + reset_int => reset_int, + reset_bram_en => reset_bram_en, + rst_req => rst_req, + sleep => sleep, + sleep_int => sleep_int, + bram_pause => bram_pause, + clk2_reset => clk2_reset, + interrupt => interrupt, + interrupt_ack => interrupt_ack, + instruction => instruction_u, + opcode => opcode, + opA => opA, + opB => opB, + reg0 => reg_reg0, + reg1 => reg_reg1, + carry => carry, + zero => zero, + call => call, + ret => ret, + inter_j => inter_j, + preserve_flags => preserve_flags, + restore_flags => restore_flags, + jmp_addr => jmp_addr, + jump => jump, + io_op_in => io_op_in, + io_op_out => io_op_out, + io_op_out_pp => io_op_out_pp, + io_kk_en => io_kk_en, + io_kk_port => io_kk_port, + io_kk_data => io_kk_data, + reg_address => reg_address, + reg_select => reg_select, + reg_star => reg_star, + spm_addr_ss => spm_addr_ss, + spm_ss => spm_ss, + spm_we => spm_we, + spm_rd => spm_rd + ); + + reg_value <= reg_value_io when (io_op_in or io_op_out) = '1' else reg_value_a when reg_we_a = '1' else reg_reg0; + reg_we <= reg_we_io or reg_we_a or reg_star or spm_rd; + + register_file : entity work.reg_file + generic map( + scratch_pad_memory_size => scratch_pad_memory_size + ) + port map( + clk => clk, + reg_address => reg_address, + reg_select => reg_select, + reg_star => reg_star, + value => reg_value, + write_en => reg_we, + reg0 => reg_reg0, + reg1 => reg_reg1, + spm_addr_ss => spm_addr_ss, + spm_ss => spm_ss, + spm_we => spm_we, + spm_rd => spm_rd + ); + + io_inst : entity work.io_module + port map( + clk => clk, + clk2 => clk2, + reset => reset_int, + reg_value => reg_value_io, + reg_we => reg_we_io, + reg_reg0 => reg_reg0, + reg_reg1 => reg_reg1, + out_data => opB, + io_op_in => io_op_in, + io_op_out => io_op_out, + io_op_out_pp => io_op_out_pp, + io_kk_en => io_kk_en, + io_kk_port => io_kk_port, + io_kk_data => io_kk_data, + -- actual i/o module ports + in_port => in_port_u, + port_id => port_id_u, + out_port => out_port_u, + read_strobe => read_strobe, + write_strobe => write_strobe, + k_write_strobe => k_write_strobe + ); + +end Behavioral; diff --git a/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/pauloblaze/pauloblaze.f b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/pauloblaze/pauloblaze.f new file mode 100644 index 0000000000000000000000000000000000000000..2c8a1ad2fac1e203391ca0ea248fa9ef0e30257d --- /dev/null +++ b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/pauloblaze/pauloblaze.f @@ -0,0 +1,7 @@ +op_codes.vhd +program_counter.vhd +alu.vhd +decoder.vhd +io_module.vhd +pauloBlaze.vhd +regFile.vhd diff --git a/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/pauloblaze/program_counter.vhd b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/pauloblaze/program_counter.vhd new file mode 100644 index 0000000000000000000000000000000000000000..b1084682711f642aaff73c5531d407d842866dff --- /dev/null +++ b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/pauloblaze/program_counter.vhd @@ -0,0 +1,142 @@ +-- EMACS settings: -*- tab-width: 4; indent-tabs-mode: t -*- +-- vim: tabstop=4:shiftwidth=4:noexpandtab +-- kate: tab-width 4; replace-tabs off; indent-width 4; +-- +-- ============================================================================= +-- Authors: Paul Genssler +-- +-- Description: +-- ------------------------------------ +-- TODO +-- +-- License: +-- ============================================================================= +-- Copyright 2007-2015 Paul Genssler - Dresden, Germany +-- +-- Licensed under the Apache License, Version 2.0 (the "License"); +-- you may not use this file except in compliance with the License. +-- You may obtain a copy of the License at +-- +-- http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Unless required by applicable law or agreed to in writing, software +-- distributed under the License is distributed on an "AS is" BASIS, +-- WITHOUT WARRANTIES or CONDITIONS of ANY KIND, either express or implied. +-- See the License for the specific language governing permissions and +-- limitations under the License. +-- ============================================================================= + +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.NUMERIC_STD.ALL; + +entity program_counter is + generic ( + interrupt_vector : unsigned(11 downto 0) := X"3FF"; + stack_depth : positive := 30 + ); + Port ( + clk : in STD_LOGIC; + reset : in STD_LOGIC; + rst_req : out std_logic; + bram_pause : in STD_LOGIC; + call : in STD_LOGIC; + ret : in std_logic; + inter_j : in std_logic; + jump : in STD_LOGIC; + jmp_addr : in unsigned (11 downto 0); + address : out unsigned (11 downto 0)); +end program_counter; + +architecture Behavioral of program_counter is + + -- Logarithms: log*ceil* + -- From PoC-Library https://github.com/VLSI-EDA/PoC + -- ========================================================================== + function log2ceil(arg : positive) return natural is + variable tmp : positive := 1; + variable log : natural := 0; + begin + if arg = 1 then return 0; end if; + while arg > tmp loop + tmp := tmp * 2; + log := log + 1; + end loop; + return log; + end function; + + type stack_t is array (stack_depth-1 downto 0) of unsigned(11 downto 0); + signal stack : stack_t := (others => (others => '0')); + signal pointer : unsigned (log2ceil(stack_depth+1)-1 downto 0); + signal counter : unsigned (12 downto 0); + signal jmp_int : std_logic; + signal jmp_done : std_logic; + signal addr_o : unsigned (11 downto 0); + +begin + + jmp_int <= jump or call or inter_j; + address <= interrupt_vector when inter_j = '1' else addr_o ; + + clken : process (clk) + variable p : unsigned(pointer'left+1 downto 0); + variable addr_next : unsigned (11 downto 0); + begin + if (rising_edge(clk)) then + if (reset = '1') then + counter <= x"001" & '0'; + addr_o <= (others => '0'); + jmp_done <= '0'; + pointer <= (others => '0'); + rst_req <= '0'; + else + if (bram_pause = '1') then + -- counter <= addr_o & '1'; + jmp_done <= jmp_done; + -- addr_o <= counter(12 downto 1); + elsif (ret = '1' and jmp_done <= '0') then + p := ('0' & pointer) - 1; + if (p = (p'range => '1')) then + rst_req <= '1'; + else + pointer <= p(pointer'range); + addr_next := stack(to_integer(p)); + counter <= addr_next & '1'; + addr_o <= addr_next; + jmp_done <= '1'; + end if; + elsif (inter_j = '1') then + p := ('0' & pointer) + 1; + if (p > stack_depth) then + rst_req <= '1'; + else + stack(to_integer(pointer)) <= addr_o-1; + pointer <= p(pointer'range); + counter <= (interrupt_vector & '1') + ("" & '1'); + addr_o <= interrupt_vector; + jmp_done <= '1'; + end if; + elsif (jmp_int = '1' and jmp_done <= '0') then + if (call = '1') then + p := ('0' & pointer) +1; + if (p > stack_depth) then + rst_req <= '1'; + else + stack(to_integer(pointer)) <= addr_o+1; + pointer <= p(pointer'range); + end if; + end if; + counter <= jmp_addr & '1'; + addr_o <= jmp_addr; + jmp_done <= '1'; + else + jmp_done <= '0'; + counter <= counter + 1; + addr_o <= counter(12 downto 1); + end if; + end if; + end if; + end process clken; + +end Behavioral; + diff --git a/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/pauloblaze/regFile.vhd b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/pauloblaze/regFile.vhd new file mode 100644 index 0000000000000000000000000000000000000000..31500fde437803368503cc5de0561ece422b2511 --- /dev/null +++ b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/pauloblaze/regFile.vhd @@ -0,0 +1,127 @@ +-- EMACS settings: -*- tab-width: 4; indent-tabs-mode: t -*- +-- vim: tabstop=4:shiftwidth=4:noexpandtab +-- kate: tab-width 4; replace-tabs off; indent-width 4; +-- +-- ============================================================================= +-- Authors: Paul Genssler +-- +-- Description: +-- ------------------------------------ +-- TODO +-- +-- License: +-- ============================================================================= +-- Copyright 2007-2015 Paul Genssler - Dresden, Germany +-- +-- Licensed under the Apache License, Version 2.0 (the "License"); +-- you may not use this file except in compliance with the License. +-- You may obtain a copy of the License at +-- +-- http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Unless required by applicable law or agreed to in writing, software +-- distributed under the License is distributed on an "AS is" BASIS, +-- WITHOUT WARRANTIES or CONDITIONS of ANY KIND, either express or implied. +-- See the License for the specific language governing permissions and +-- limitations under the License. +-- ============================================================================= + +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.NUMERIC_STD.ALL; + +library work; +use work.op_codes.all; + +entity reg_file is + generic ( + debug : boolean := false; + scratch_pad_memory_size : integer := 64 + ); + port ( + clk : in std_logic; + value : in unsigned (7 downto 0); + write_en : in std_logic; + reg0 : out unsigned (7 downto 0); + reg1 : out unsigned (7 downto 0); + reg_address : in unsigned (7 downto 0); + reg_select : in std_logic; + reg_star : in std_logic; + spm_addr_ss : in unsigned (7 downto 0); + spm_ss : in std_logic; -- 0: spm_addr = reg1, 1: spm_addr = spm_addr_ss + spm_we : in std_logic; + spm_rd : in std_logic + ); +end reg_file; + +architecture Behavioral of reg_file is + + -- Logarithms: log*ceil* + -- From PoC-Library https://github.com/VLSI-EDA/PoC + -- ========================================================================== + function log2ceil(arg : positive) return natural is + variable tmp : positive := 1; + variable log : natural := 0; + begin + if arg = 1 then return 0; end if; + while arg > tmp loop + tmp := tmp * 2; + log := log + 1; + end loop; + return log; + end function; + + type reg_file_t is array (31 downto 0) of unsigned(7 downto 0); + signal reg : reg_file_t := (others=>(others=>'0')); + + type scratchpad_t is array(integer range <>) of unsigned(7 downto 0); + signal scratchpad : scratchpad_t((scratch_pad_memory_size-1) downto 0) := (others=>(others=>'0')); + + constant spm_addr_width : integer := log2ceil(scratch_pad_memory_size); -- address failsafes into a truncated one + signal spm_addr : unsigned ( spm_addr_width-1 downto 0); + + signal spm_read : unsigned (7 downto 0); + + signal reg0_buf : unsigned ( 7 downto 0); + signal reg0_o : unsigned ( 7 downto 0); + + signal reg1_buf : unsigned ( 7 downto 0); + signal reg1_o : unsigned ( 7 downto 0); + signal reg_wr_data : unsigned ( 7 downto 0); +begin + + reg0 <= reg0_o; + reg1 <= reg1_o; + reg_wr_data <= spm_read when spm_rd = '1' else value when reg_star = '0' else reg1_buf; + + spm_addr <= spm_addr_ss(spm_addr_width -1 downto 0) when spm_ss = '1' else reg1_buf(spm_addr_width -1 downto 0); + + spm_read <= scratchpad(to_integer(spm_addr)); + reg0_o <= reg(to_integer(reg_select & reg_address(7 downto 4))); + reg1_o <= reg(to_integer(reg_select & reg_address(3 downto 0))); + + write_reg : process (clk) begin + if rising_edge(clk) then + if (write_en = '1') then + reg(to_integer(reg_select & reg_address(7 downto 4))) <= reg_wr_data; + end if; + end if; + end process write_reg; + + write_spm : process (clk) begin + if rising_edge(clk) then + if (spm_we = '1') then + scratchpad(to_integer(spm_addr)) <= reg0_buf; + end if; + end if; + end process write_spm; + + buf_reg0_p : process (clk) begin + if rising_edge(clk) then + reg0_buf <= reg0_o; + reg1_buf <= reg1_o; + end if; + end process buf_reg0_p; + +end Behavioral; + diff --git a/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/t48/alu-c.vhd b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/t48/alu-c.vhd new file mode 100644 index 0000000000000000000000000000000000000000..4cfa70a97e04164e56ecfb4d9661023b8df14f4b --- /dev/null +++ b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/t48/alu-c.vhd @@ -0,0 +1,19 @@ +------------------------------------------------------------------------------- +-- +-- The Arithmetic Logic Unit (ALU). +-- It contains the ALU core plus the Accumulator and the Temp Reg. +-- +-- $Id: alu-c.vhd 295 2009-04-01 19:32:48Z arniml $ +-- +-- Copyright (c) 2004, Arnim Laeuger (arniml@opencores.org) +-- +-- All rights reserved +-- +------------------------------------------------------------------------------- + +configuration t48_alu_rtl_c0 of t48_alu is + + for rtl + end for; + +end t48_alu_rtl_c0; diff --git a/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/t48/alu.vhd b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/t48/alu.vhd new file mode 100644 index 0000000000000000000000000000000000000000..7bf8c4cbf0296358501b7cc4ce0ca12991726c2d --- /dev/null +++ b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/t48/alu.vhd @@ -0,0 +1,415 @@ +------------------------------------------------------------------------------- +-- +-- The Arithmetic Logic Unit (ALU). +-- It contains the ALU core plus the Accumulator and the Temp Reg. +-- +-- $Id: alu.vhd 295 2009-04-01 19:32:48Z arniml $ +-- +-- Copyright (c) 2004, Arnim Laeuger (arniml@opencores.org) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.opencores.org/cvsweb.shtml/t48/ +-- +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; + +use work.t48_pack.word_t; +use work.t48_alu_pack.alu_op_t; + +entity t48_alu is + + port ( + -- Global Interface ------------------------------------------------------- + clk_i : in std_logic; + res_i : in std_logic; + en_clk_i : in boolean; + -- T48 Bus Interface ------------------------------------------------------ + data_i : in word_t; + data_o : out word_t; + write_accu_i : in boolean; + write_shadow_i : in boolean; + write_temp_reg_i : in boolean; + read_alu_i : in boolean; + -- Decoder Interface ------------------------------------------------------ + carry_i : in std_logic; + carry_o : out std_logic; + aux_carry_o : out std_logic; + alu_op_i : in alu_op_t; + use_carry_i : in boolean; + da_high_i : in boolean; + da_overflow_o : out boolean; + accu_low_i : in boolean; + p06_temp_reg_i : in boolean; + p60_temp_reg_i : in boolean + ); + +end t48_alu; + + +library ieee; +use ieee.numeric_std.all; + +use work.t48_pack.clk_active_c; +use work.t48_pack.res_active_c; +use work.t48_pack.bus_idle_level_c; +use work.t48_pack.nibble_t; +use work.t48_alu_pack.all; + +-- pragma translate_off +use work.t48_tb_pack.tb_accu_s; +-- pragma translate_on + +architecture rtl of t48_alu is + + -- the Accumulator and Temp Reg + signal accumulator_q, + accu_shadow_q, + temp_req_q : word_t; + -- inputs to the ALU core + signal in_a_s, + in_b_s : word_t; + -- output of the ALU core + signal data_s : word_t; + + signal add_result_s : alu_operand_t; + +begin + + ----------------------------------------------------------------------------- + -- Process working_regs + -- + -- Purpose: + -- Implements the working registers: + -- + Accumulator + -- + Temp Reg + -- + working_regs: process (res_i, clk_i) + begin + if res_i = res_active_c then + accumulator_q <= (others => '0'); + accu_shadow_q <= (others => '0'); + temp_req_q <= (others => '0'); + + elsif clk_i'event and clk_i = clk_active_c then + if en_clk_i then + + if write_accu_i then + if accu_low_i then + accumulator_q(nibble_t'range) <= data_i(nibble_t'range); + else + accumulator_q <= data_i; + end if; + end if; + + if write_shadow_i then + -- write shadow directly from t48 data bus + accu_shadow_q <= data_i; + else + -- default: update shadow Accumulator from real Accumulator + accu_shadow_q <= accumulator_q; + end if; + + if p06_temp_reg_i then + -- low nibble of DA sequence + temp_req_q <= "00000110"; + elsif p60_temp_reg_i then + -- high nibble of DA sequence + temp_req_q <= "01100000"; + elsif write_temp_reg_i then + -- normal load from T48 bus + temp_req_q <= data_i; + end if; + + end if; + + end if; + + end process working_regs; + -- + ----------------------------------------------------------------------------- + + + ----------------------------------------------------------------------------- + -- Build the inputs to the ALU core. + -- Input A: + -- Unary operators use only Input A. + -- Is always fed from the shadow Accumulator. + -- Assumption: It never happens that the Accumulator is written and then + -- read for an ALU operation in the next cycle. + -- Its contents can thus be staged through the shadow Accu. + -- Input B: + -- Is always fed from the Temp Reg. + ----------------------------------------------------------------------------- + in_a_s <= accu_shadow_q; + in_b_s <= temp_req_q; + + + ----------------------------------------------------------------------------- + -- Process alu_core + -- + -- Purpose: + -- Implements the ALU core. + -- All operations defined in alu_op_t are handled here. + -- + alu_core: process (in_a_s, + in_b_s, + alu_op_i, + carry_i, + use_carry_i, + add_result_s) + + begin + -- default assigments + data_s <= (others => '0'); + carry_o <= '0'; + + case alu_op_i is + -- Operation: AND ------------------------------------------------------- + when ALU_AND => + data_s <= in_a_s and in_b_s; + + -- Operation: OR -------------------------------------------------------- + when ALU_OR => + data_s <= in_a_s or in_b_s; + + -- Operation: XOR ------------------------------------------------------- + when ALU_XOR => + data_s <= in_a_s xor in_b_s; + + -- Operation: Add ------------------------------------------------------- + when ALU_ADD => + data_s <= add_result_s(data_s'range); + carry_o <= add_result_s(add_result_s'high); + + -- Operation: CPL ------------------------------------------------------- + when ALU_CPL => + data_s <= not in_a_s; + + -- Operation: CLR ------------------------------------------------------- + when ALU_CLR => + data_s <= (others => '0'); + + -- Operation: RL -------------------------------------------------------- + when ALU_RL => + data_s(7 downto 1) <= in_a_s(6 downto 0); + carry_o <= in_a_s(7); + + if use_carry_i then + data_s(0) <= carry_i; + else + data_s(0) <= in_a_s(7); + end if; + + -- Operation: RR -------------------------------------------------------- + when ALU_RR => + data_s(6 downto 0) <= in_a_s(7 downto 1); + carry_o <= in_a_s(0); + + if use_carry_i then + data_s(7) <= carry_i; + else + data_s(7) <= in_a_s(0); + end if; + + -- Operation: Swap ------------------------------------------------------ + when ALU_SWAP => + data_s(3 downto 0) <= in_a_s(7 downto 4); + data_s(7 downto 4) <= in_a_s(3 downto 0); + + -- Operation: DEC ------------------------------------------------------- + when ALU_DEC => + data_s <= add_result_s(data_s'range); + + -- Operation: INC ------------------------------------------------------- + when ALU_INC => + data_s <= add_result_s(data_s'range); + + -- Operation CONCAT ----------------------------------------------------- + when ALU_CONCAT => + data_s <= in_b_s(7 downto 4) & in_a_s(3 downto 0); + + -- Operation: NOP ------------------------------------------------------- + when ALU_NOP => + data_s <= in_a_s; + + when others => + -- pragma translate_off + assert false + report "Unknown ALU operation selected!" + severity error; + -- pragma translate_on + + end case; + + end process alu_core; + -- + ----------------------------------------------------------------------------- + + + ----------------------------------------------------------------------------- + -- Process adder + -- + -- Purpose: + -- Implements the adder used by several instructions. + -- This way of modelling the adder forces resource sharing of: + -- * ADD + -- * INC + -- * DEC + -- + adder: process (in_a_s, + in_b_s, + alu_op_i, + carry_i, + use_carry_i) + + variable add_a_v, add_b_v : alu_operand_t; + variable c_v : alu_operand_t; + variable result_v : UNSIGNED(alu_operand_t'range); + variable aux_c_v : std_logic_vector(1 downto 0); + + begin + -- Carry Selection -------------------------------------------------------- + c_v := (others => '0'); + if use_carry_i and carry_i = '1' then + c_v(0) := '1'; + end if; + + -- Operand Selection ------------------------------------------------------ + -- defaults for ADD + add_a_v := '0' & in_a_s; + add_b_v := '0' & in_b_s; + + case alu_op_i is + when ALU_INC => + add_b_v := (others => '0'); + add_b_v(0) := '1'; + when ALU_DEC => + add_b_v := (others => '1'); + when others => + null; + end case; + + -- The Adder -------------------------------------------------------------- + result_v := UNSIGNED(add_a_v) + + UNSIGNED(add_b_v) + + UNSIGNED(c_v); + + add_result_s <= std_logic_vector(result_v); + + -- Auxiliary Carry -------------------------------------------------------- + aux_c_v := in_a_s(4) & in_b_s(4); + + aux_carry_o <= '0'; + case aux_c_v is + when "00" | "11" => + if result_v(4) = '1' then + aux_carry_o <= '1'; + end if; + + when "01" | "10" => + if result_v(4) = '0' then + aux_carry_o <= '1'; + end if; + + when others => + null; + + end case; + + end process adder; + -- + ----------------------------------------------------------------------------- + + + ----------------------------------------------------------------------------- + -- Process da_overflow + -- + -- Purpose: + -- Detect overflow situation during DA sequence. + -- + da_overflow: process (accu_shadow_q, + da_high_i) + + variable da_nibble_v : nibble_t; + + function da_overflow_f(data : in nibble_t) return boolean is + variable overflow_v : boolean; + begin + case data is + when "1010" | + "1011" | + "1100" | + "1101" | + "1110" | + "1111" => + overflow_v := true; + when others => + overflow_v := false; + end case; + + return(overflow_v); + end; + + begin + if da_high_i then + da_nibble_v := accu_shadow_q(7 downto 4); + else + da_nibble_v := accu_shadow_q(3 downto 0); + end if; + + da_overflow_o <= da_overflow_f(da_nibble_v); + + end process da_overflow; + -- + ----------------------------------------------------------------------------- + + + -- pragma translate_off + ----------------------------------------------------------------------------- + -- Testbench support. + ----------------------------------------------------------------------------- + tb_accu_s <= accumulator_q; + -- pragma translate_on + + ----------------------------------------------------------------------------- + -- Output Multiplexer. + ----------------------------------------------------------------------------- + data_o <= data_s + when read_alu_i else + (others => bus_idle_level_c); + +end rtl; diff --git a/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/t48/alu_pack-p.vhd b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/t48/alu_pack-p.vhd new file mode 100644 index 0000000000000000000000000000000000000000..7794cd4c492f97de73435dd07ad33f20d4ebb81c --- /dev/null +++ b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/t48/alu_pack-p.vhd @@ -0,0 +1,35 @@ +------------------------------------------------------------------------------- +-- +-- $Id: alu_pack-p.vhd 295 2009-04-01 19:32:48Z arniml $ +-- +-- Copyright (c) 2004, Arnim Laeuger (arniml@opencores.org) +-- +-- All rights reserved +-- +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; + +use work.t48_pack.word_width_c; + +package t48_alu_pack is + + ----------------------------------------------------------------------------- + -- The ALU operations + ----------------------------------------------------------------------------- + type alu_op_t is (ALU_AND, ALU_OR, ALU_XOR, + ALU_CPL, ALU_CLR, + ALU_RL, ALU_RR, + ALU_SWAP, + ALU_DEC, ALU_INC, + ALU_ADD, + ALU_CONCAT, + ALU_NOP); + + ----------------------------------------------------------------------------- + -- The dedicated ALU arithmetic types. + ----------------------------------------------------------------------------- + subtype alu_operand_t is std_logic_vector(word_width_c downto 0); + +end t48_alu_pack; diff --git a/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/t48/bus_mux-c.vhd b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/t48/bus_mux-c.vhd new file mode 100644 index 0000000000000000000000000000000000000000..66209210881fecbf4fefa895bab89e2553de00e0 --- /dev/null +++ b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/t48/bus_mux-c.vhd @@ -0,0 +1,19 @@ +------------------------------------------------------------------------------- +-- +-- The T48 Bus Connector. +-- Multiplexes all drivers of the T48 bus. +-- +-- $Id: bus_mux-c.vhd 295 2009-04-01 19:32:48Z arniml $ +-- +-- Copyright (c) 2004, Arnim Laeuger (arniml@opencores.org) +-- +-- All rights reserved +-- +------------------------------------------------------------------------------- + +configuration t48_bus_mux_rtl_c0 of t48_bus_mux is + + for rtl + end for; + +end t48_bus_mux_rtl_c0; diff --git a/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/t48/bus_mux.vhd b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/t48/bus_mux.vhd new file mode 100644 index 0000000000000000000000000000000000000000..2d1da4b3ffd3a53231c289ad10daa4f11e167847 --- /dev/null +++ b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/t48/bus_mux.vhd @@ -0,0 +1,100 @@ +------------------------------------------------------------------------------- +-- +-- The T48 Bus Connector. +-- Multiplexes all drivers of the T48 bus. +-- +-- $Id: bus_mux.vhd 295 2009-04-01 19:32:48Z arniml $ +-- +-- Copyright (c) 2004, Arnim Laeuger (arniml@opencores.org) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.opencores.org/cvsweb.shtml/t48/ +-- +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; + +use work.t48_pack.word_t; + +entity t48_bus_mux is + + port ( + alu_data_i : in word_t; + bus_data_i : in word_t; + dec_data_i : in word_t; + dm_data_i : in word_t; + pm_data_i : in word_t; + p1_data_i : in word_t; + p2_data_i : in word_t; + psw_data_i : in word_t; + tim_data_i : in word_t; + data_o : out word_t + ); + +end t48_bus_mux; + + +use work.t48_pack.bus_idle_level_c; + +architecture rtl of t48_bus_mux is + +begin + + or_tree: if bus_idle_level_c = '0' generate + data_o <= alu_data_i or + bus_data_i or + dec_data_i or + dm_data_i or + pm_data_i or + p1_data_i or + p2_data_i or + psw_data_i or + tim_data_i; + end generate; + + and_tree: if bus_idle_level_c = '1' generate + data_o <= alu_data_i and + bus_data_i and + dec_data_i and + dm_data_i and + pm_data_i and + p1_data_i and + p2_data_i and + psw_data_i and + tim_data_i; + end generate; + +end rtl; diff --git a/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/t48/clock_ctrl-c.vhd b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/t48/clock_ctrl-c.vhd new file mode 100644 index 0000000000000000000000000000000000000000..a061baa09c5ea7f4a4f739b988fcc228282aed6e --- /dev/null +++ b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/t48/clock_ctrl-c.vhd @@ -0,0 +1,14 @@ +------------------------------------------------------------------------------- +-- +-- $Id: clock_ctrl-c.vhd 295 2009-04-01 19:32:48Z arniml $ +-- +-- The clock control unit. +-- +------------------------------------------------------------------------------- + +configuration t48_clock_ctrl_rtl_c0 of t48_clock_ctrl is + + for rtl + end for; + +end t48_clock_ctrl_rtl_c0; diff --git a/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/t48/clock_ctrl.vhd b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/t48/clock_ctrl.vhd new file mode 100644 index 0000000000000000000000000000000000000000..e6d0ef7a3f3564190425fd0d927c08b6a650d1d8 --- /dev/null +++ b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/t48/clock_ctrl.vhd @@ -0,0 +1,397 @@ +------------------------------------------------------------------------------- +-- +-- The Clock Control unit. +-- Clock States and Machine Cycles are generated here. +-- +-- $Id: clock_ctrl.vhd 295 2009-04-01 19:32:48Z arniml $ +-- +-- Copyright (c) 2004, 2005, Arnim Laeuger (arniml@opencores.org) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.opencores.org/cvsweb.shtml/t48/ +-- +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; + +use work.t48_pack.all; + +entity t48_clock_ctrl is + + generic ( + -- divide XTAL1 by 3 to derive Clock States + xtal_div_3_g : integer := 1 + ); + + port ( + clk_i : in std_logic; + xtal_i : in std_logic; + xtal_en_i : in boolean; + res_i : in std_logic; + en_clk_i : in boolean; + xtal3_o : out boolean; + t0_o : out std_logic; + multi_cycle_i : in boolean; + assert_psen_i : in boolean; + assert_prog_i : in boolean; + assert_rd_i : in boolean; + assert_wr_i : in boolean; + mstate_o : out mstate_t; + second_cycle_o : out boolean; + ale_o : out boolean; + psen_o : out boolean; + prog_o : out boolean; + rd_o : out boolean; + wr_o : out boolean + ); + +end t48_clock_ctrl; + + +library ieee; +use ieee.numeric_std.all; + +architecture rtl of t48_clock_ctrl is + + -- The three XTAL1 cycles. + signal xtal_q : unsigned(1 downto 0); + signal xtal1_s, + xtal2_s, + xtal3_s : boolean; + signal x1_s, + x2_s, + x3_s : std_logic; + + signal t0_q : std_logic; + + + -- The five clock states. + signal mstate_q : mstate_t; + + signal ale_q : boolean; + signal psen_q : boolean; + signal prog_q : boolean; + signal rd_q : boolean; + signal wr_q : boolean; + + + -- The Machine Cycle marker. + signal second_cycle_q : boolean; + signal multi_cycle_q : boolean; + +begin + + ----------------------------------------------------------------------------- + -- Verify the generics + ----------------------------------------------------------------------------- + + -- pragma translate_off + + -- XTAL1 divide by 3 -------------------------------------------------------- + assert (xtal_div_3_g = 1) or (xtal_div_3_g = 0) + report "xtal_div_3_g must be either 1 or 0!" + severity failure; + + -- pragma translate_on + + + ----------------------------------------------------------------------------- + -- Divide XTAL1 by 3 to derive Clock States. + ----------------------------------------------------------------------------- + use_xtal_div: if xtal_div_3_g = 1 generate + xtal: process (res_i, xtal_i) + begin + if res_i = res_active_c then + xtal_q <= TO_UNSIGNED(0, 2); + t0_q <= '0'; + + elsif xtal_i'event and xtal_i = clk_active_c then + if xtal_en_i then + if xtal_q < 2 then + xtal_q <= xtal_q + 1; + else + xtal_q <= TO_UNSIGNED(0, 2); + end if; + + if xtal3_s then + t0_q <= '1'; + else + t0_q <= '0'; + end if; + + end if; + + end if; + end process xtal; + + x1_s <= '1' + when xtal_q = 0 and xtal_en_i else + '0'; + x2_s <= '1' + when xtal_q = 1 and xtal_en_i else + '0'; + x3_s <= '1' + when xtal_q = 2 and xtal_en_i else + '0'; + t0_o <= t0_q; + + end generate; + + ----------------------------------------------------------------------------- + -- XTAL1 is used directly for Clock States. + ----------------------------------------------------------------------------- + no_xtal_div: if xtal_div_3_g = 0 generate + xtal_q <= TO_UNSIGNED(0, 2); + + x1_s <= '1' + when xtal_en_i else + '0'; + x2_s <= '1' + when xtal_en_i else + '0'; + x3_s <= '1' + when xtal_en_i else + '0'; + t0_o <= xtal_i; + + end generate; + + -- And finally the boolean flags -------------------------------------------- + xtal1_s <= to_boolean(x1_s); + xtal2_s <= to_boolean(x2_s); + xtal3_s <= to_boolean(x3_s); + + + ----------------------------------------------------------------------------- + -- Process external_signal + -- + -- Purpose: + -- Control signals ALE, PSEN, PROG and RD/WR are generated here. + -- + external_signals: process (res_i, xtal_i) + begin + if res_i = res_active_c then + ale_q <= false; + psen_q <= false; + prog_q <= false; + rd_q <= false; + wr_q <= false; + + elsif xtal_i'event and xtal_i = clk_active_c then + + case mstate_q is + when MSTATE5 => + -- RD, WR are set at the end of XTAL2 of first machine cycle + if xtal2_s and not second_cycle_q then + if assert_rd_i then + rd_q <= true; + end if; + if assert_wr_i then + wr_q <= true; + end if; + end if; + + when MSTATE1 => + if xtal3_s then + psen_q <= false; + end if; + + when MSTATE2 => + if xtal3_s then + -- RD, WR are removed at the end of XTAL3 of second machine cycle + rd_q <= false; + wr_q <= false; + -- so is PROG + prog_q <= false; + end if; + + when MSTATE3 => + -- ALE is set at the end of XTAL3 of every machine cycle + if xtal3_s then + ale_q <= true; + end if; + + when MSTATE4 => + if xtal3_s then + -- PSEN is set at the end of XTAL3 + if assert_psen_i then + psen_q <= true; + end if; + + end if; + + -- PROG is set at the end of XTAL3 + if xtal3_s and + multi_cycle_q and not second_cycle_q and assert_prog_i then + prog_q <= true; + end if; + + -- ALE is removed at the end of XTAL2 of every machine cycle + if xtal2_s then + ale_q <= false; + end if; + + when others => + -- recover when states are out of sync + ale_q <= false; + psen_q <= false; + prog_q <= false; + rd_q <= false; + wr_q <= false; + + end case; + + end if; + + end process external_signals; + -- + ----------------------------------------------------------------------------- + + + ----------------------------------------------------------------------------- + -- Process states + -- + -- Purpose: + -- The Clock State controller. + -- + states: process (res_i, clk_i) + begin + if res_i = res_active_c then + -- Reset machine state to MSTATE3 + -- This allows a proper instruction fetch for the first real instruction + -- after reset. + -- The MSTATE3 is part of a virtual NOP that has no MSTATE1 and MSTATE2. + mstate_q <= MSTATE3; + + elsif clk_i'event and clk_i = clk_active_c then + if en_clk_i then + + case mstate_q is + when MSTATE5 => + mstate_q <= MSTATE1; + + when MSTATE1 => + mstate_q <= MSTATE2; + + when MSTATE2 => + mstate_q <= MSTATE3; + + when MSTATE3 => + mstate_q <= MSTATE4; + + when MSTATE4 => + mstate_q <= MSTATE5; + + when others => + -- recover when states are out of sync + mstate_q <= MSTATE1; + + -- pragma translate_off + assert false + report "Encoding of Clock States failed!" + severity error; + -- pragma translate_on + + end case; + + end if; + + end if; + + end process states; + -- + ----------------------------------------------------------------------------- + + + ----------------------------------------------------------------------------- + -- Process machine_cycle + -- + -- Purpose: + -- Keep track of machine cycles. + -- Basically, this means to differ between first and second cycle. + -- + machine_cycle: process (res_i, clk_i) + variable state2_v, state5_v : boolean; + begin + if res_i = res_active_c then + multi_cycle_q <= false; + second_cycle_q <= false; + + elsif clk_i'event and clk_i = clk_active_c then + if en_clk_i then + + state2_v := mstate_q = MSTATE2; + state5_v := mstate_q = MSTATE5; + + -- multi cycle information is delivered in State 2 from the decoder + if state2_v and multi_cycle_i then + multi_cycle_q <= true; + end if; + + -- mark second machine cycle + if multi_cycle_q and state5_v then + second_cycle_q <= true; + end if; + + -- reset at end of second machine cycle + if state5_v and + (multi_cycle_q and second_cycle_q) then + multi_cycle_q <= false; + second_cycle_q <= false; + end if; + + end if; + + end if; + + end process machine_cycle; + -- + ----------------------------------------------------------------------------- + + + ----------------------------------------------------------------------------- + -- Output assignments + ----------------------------------------------------------------------------- + xtal3_o <= xtal3_s; + mstate_o <= mstate_q; + second_cycle_o <= second_cycle_q; + ale_o <= ale_q; + psen_o <= psen_q; + prog_o <= prog_q; + rd_o <= rd_q; + wr_o <= wr_q; + +end rtl; diff --git a/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/t48/cond_branch-c.vhd b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/t48/cond_branch-c.vhd new file mode 100644 index 0000000000000000000000000000000000000000..fd9e7d6b72db7961d6b543293e7a1d0613b627a4 --- /dev/null +++ b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/t48/cond_branch-c.vhd @@ -0,0 +1,19 @@ +------------------------------------------------------------------------------- +-- +-- The Conditional Branch Logic unit. +-- Decisions whether to take a jump or not are made here. +-- +-- $Id: cond_branch-c.vhd 295 2009-04-01 19:32:48Z arniml $ +-- +-- Copyright (c) 2004, Arnim Laeuger (arniml@opencores.org) +-- +-- All rights reserved +-- +------------------------------------------------------------------------------- + +configuration t48_cond_branch_rtl_c0 of t48_cond_branch is + + for rtl + end for; + +end t48_cond_branch_rtl_c0; diff --git a/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/t48/cond_branch.vhd b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/t48/cond_branch.vhd new file mode 100644 index 0000000000000000000000000000000000000000..93325e11abe94d76baa3444ae1f535d544f2bd0c --- /dev/null +++ b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/t48/cond_branch.vhd @@ -0,0 +1,212 @@ +------------------------------------------------------------------------------- +-- +-- The Conditional Branch Logic unit. +-- Decisions whether to take a jump or not are made here. +-- +-- $Id: cond_branch.vhd 303 2022-12-16 19:56:46Z arniml $ +-- +-- Copyright (c) 2004, Arnim Laeuger (arniml@opencores.org) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.opencores.org/cvsweb.shtml/t48/ +-- +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; + +use work.t48_pack.word_t; + +use work.t48_cond_branch_pack.all; + +entity t48_cond_branch is + + port ( + -- Global Interface ------------------------------------------------------- + clk_i : in std_logic; + res_i : in std_logic; + en_clk_i : in boolean; + -- Decoder Interface ------------------------------------------------------ + compute_take_i : in boolean; + branch_cond_i : in branch_conditions_t; + take_branch_o : out boolean; + accu_i : in word_t; + t0_i : in std_logic; + t1_i : in std_logic; + int_n_i : in std_logic; + f0_i : in std_logic; + f1_i : in std_logic; + tf_i : in std_logic; + carry_i : in std_logic; + ibf_i : in std_logic := '0'; -- UPI41 + obf_i : in std_logic := '0'; -- UPI41 + comp_value_i : in comp_value_t + ); + +end t48_cond_branch; + + +library ieee; +use ieee.numeric_std.all; + +use work.t48_pack.res_active_c; +use work.t48_pack.clk_active_c; + +architecture rtl of t48_cond_branch is + + -- marker for branch taken + signal take_branch_s, + take_branch_q : boolean; + +begin + + ----------------------------------------------------------------------------- + -- Process decide_take + -- + -- Purpose: + -- Decides whether a branch has to be taken or not. + -- + decide_take: process (accu_i, + branch_cond_i, + t0_i, t1_i, + int_n_i, + f0_i, f1_i, + tf_i, + carry_i, + ibf_i, obf_i, + comp_value_i) + variable or_v : std_logic; + begin + -- default assignment + take_branch_s <= false; + or_v := '0'; + + case branch_cond_i is + -- Branch On: Accumulator Bit ------------------------------------------- + when COND_ON_BIT => + if accu_i(TO_INTEGER(UNSIGNED(comp_value_i))) = '1' then + take_branch_s <= true; + end if; + + -- Branch On: Accumulator Zero ------------------------------------------ + when COND_Z => + for i in accu_i'range loop + or_v := or_v or accu_i(i); + end loop; + take_branch_s <= or_v = not comp_value_i(0); + + -- Branch On: Carry ----------------------------------------------------- + when COND_C => + take_branch_s <= carry_i = comp_value_i(0); + + -- Branch On: Flag 0 ---------------------------------------------------- + when COND_F0 => + take_branch_s <= f0_i = '1'; + + -- Branch On: Flag 1 ---------------------------------------------------- + when COND_F1 => + take_branch_s <= f1_i = '1'; + + -- Branch On: Interrupt ------------------------------------------------- + when COND_INT => + take_branch_s <= int_n_i = '0'; + + -- Branch On: Test 0 ---------------------------------------------------- + when COND_T0 => + take_branch_s <= t0_i = comp_value_i(0); + + -- Branch On: Test 1 ---------------------------------------------------- + when COND_T1 => + take_branch_s <= t1_i = comp_value_i(0); + + -- Branch On: Timer Flag ------------------------------------------------ + when COND_TF => + take_branch_s <= tf_i = '1'; + + -- Branch On: IBF not set - UPI41 --------------------------------------- + when COND_NIBF => + take_branch_s <= ibf_i = '0'; + + -- Branch On: OBF set - UPI41 ------------------------------------------- + when COND_OBF => + take_branch_s <= obf_i = '1'; + + when others => + -- pragma translate_off + assert false + report "Unknown branch condition specified!" + severity error; + -- pragma translate_on + + end case; + + end process decide_take; + -- + ----------------------------------------------------------------------------- + + + ----------------------------------------------------------------------------- + -- Process reg + -- + -- Purpose: + -- Implement the marker register. + -- + reg: process (res_i, clk_i) + begin + if res_i = res_active_c then + take_branch_q <= false; + + elsif clk_i'event and clk_i = clk_active_c then + if en_clk_i then + + if compute_take_i then + take_branch_q <= take_branch_s; + end if; + + end if; + + end if; + + end process reg; + -- + ----------------------------------------------------------------------------- + + + ----------------------------------------------------------------------------- + -- Output Mapping. + ----------------------------------------------------------------------------- + take_branch_o <= take_branch_q; + +end rtl; diff --git a/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/t48/cond_branch_pack-p.vhd b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/t48/cond_branch_pack-p.vhd new file mode 100644 index 0000000000000000000000000000000000000000..bd52fa493c05ee9b665758899114f672eb140c8c --- /dev/null +++ b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/t48/cond_branch_pack-p.vhd @@ -0,0 +1,31 @@ +------------------------------------------------------------------------------- +-- +-- $Id: cond_branch_pack-p.vhd 303 2022-12-16 19:56:46Z arniml $ +-- +-- Copyright (c) 2004, Arnim Laeuger (arniml@opencores.org) +-- +-- All rights reserved +-- +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; + +package t48_cond_branch_pack is + + ----------------------------------------------------------------------------- + -- The branch conditions. + ----------------------------------------------------------------------------- + type branch_conditions_t is (COND_ON_BIT, COND_Z, + COND_C, + COND_F0, COND_F1, + COND_INT, + COND_T0, COND_T1, + COND_TF, + -- UPI41 + COND_NIBF, + COND_OBF); + + subtype comp_value_t is std_logic_vector(2 downto 0); + +end t48_cond_branch_pack; diff --git a/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/t48/db_bus-c.vhd b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/t48/db_bus-c.vhd new file mode 100644 index 0000000000000000000000000000000000000000..b47532bfd99720b79737615edd97416d631e57b1 --- /dev/null +++ b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/t48/db_bus-c.vhd @@ -0,0 +1,19 @@ +------------------------------------------------------------------------------- +-- +-- The BUS unit. +-- Implements the BUS port logic. +-- +-- $Id: db_bus-c.vhd 295 2009-04-01 19:32:48Z arniml $ +-- +-- Copyright (c) 2004, Arnim Laeuger (arniml@opencores.org) +-- +-- All rights reserved +-- +------------------------------------------------------------------------------- + +configuration t48_db_bus_rtl_c0 of t48_db_bus is + + for rtl + end for; + +end t48_db_bus_rtl_c0; diff --git a/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/t48/db_bus.vhd b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/t48/db_bus.vhd new file mode 100644 index 0000000000000000000000000000000000000000..746df29dd8d293ebedfb1510a89ab45f81c49ed3 --- /dev/null +++ b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/t48/db_bus.vhd @@ -0,0 +1,146 @@ +------------------------------------------------------------------------------- +-- +-- The BUS unit. +-- Implements the BUS port logic. +-- +-- $Id: db_bus.vhd 295 2009-04-01 19:32:48Z arniml $ +-- +-- Copyright (c) 2004, Arnim Laeuger (arniml@opencores.org) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.opencores.org/cvsweb.shtml/t48/ +-- +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; + +use work.t48_pack.word_t; + +entity t48_db_bus is + + port ( + -- Global Interface ------------------------------------------------------- + clk_i : in std_logic; + res_i : in std_logic; + en_clk_i : in boolean; + ea_i : in std_logic; + -- T48 Bus Interface ------------------------------------------------------ + data_i : in word_t; + data_o : out word_t; + write_bus_i : in boolean; + read_bus_i : in boolean; + -- BUS Interface ---------------------------------------------------------- + output_pcl_i : in boolean; + bidir_bus_i : in boolean; + pcl_i : in word_t; + db_i : in word_t; + db_o : out word_t; + db_dir_o : out std_logic + ); + +end t48_db_bus; + + +use work.t48_pack.clk_active_c; +use work.t48_pack.res_active_c; +use work.t48_pack.bus_idle_level_c; +use work.t48_pack.to_stdLogic; + +architecture rtl of t48_db_bus is + + -- the BUS output register + signal bus_q : word_t; + + -- BUS direction marker + signal db_dir_q, + db_dir_qq : std_logic; + +begin + + ----------------------------------------------------------------------------- + -- Process bus_regs + -- + -- Purpose: + -- Implements the BUS output register. + -- + bus_regs: process (res_i, clk_i) + begin + if res_i = res_active_c then + bus_q <= (others => '0'); + db_dir_q <= '0'; + db_dir_qq <= '0'; + + elsif clk_i'event and clk_i = clk_active_c then + if en_clk_i then + if write_bus_i then + db_dir_qq <= '1'; + else + -- extend bus direction by one machine cycle + db_dir_qq <= db_dir_q; + end if; + + if write_bus_i then + bus_q <= data_i; + + db_dir_q <= '1'; + + elsif ea_i = '1' or bidir_bus_i then + db_dir_q <= '0'; + + end if; + + end if; + + end if; + + end process bus_regs; + -- + ----------------------------------------------------------------------------- + + + ----------------------------------------------------------------------------- + -- Output Mapping. + ----------------------------------------------------------------------------- + db_o <= pcl_i + when output_pcl_i else + bus_q; + db_dir_o <= db_dir_qq or + to_stdLogic(output_pcl_i); + data_o <= (others => bus_idle_level_c) + when not read_bus_i else + db_i; + +end rtl; diff --git a/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/t48/decoder-c.vhd b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/t48/decoder-c.vhd new file mode 100644 index 0000000000000000000000000000000000000000..4ad089d033eedaae98d0b922de3d3d853580fd22 --- /dev/null +++ b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/t48/decoder-c.vhd @@ -0,0 +1,24 @@ +------------------------------------------------------------------------------- +-- +-- The Decoder unit. +-- It decodes the instruction opcodes and executes them. +-- +-- $Id: decoder-c.vhd 295 2009-04-01 19:32:48Z arniml $ +-- +-- Copyright (c) 2004, Arnim Laeuger (arniml@opencores.org) +-- +-- All rights reserved +-- +------------------------------------------------------------------------------- + +configuration t48_decoder_rtl_c0 of t48_decoder is + + for rtl + + for int_b: t48_int + use configuration work.t48_int_rtl_c0; + end for; + + end for; + +end t48_decoder_rtl_c0; diff --git a/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/t48/decoder.vhd b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/t48/decoder.vhd new file mode 100644 index 0000000000000000000000000000000000000000..9ffcef71cf297f62de58ffbdbdabd44ce386ef86 --- /dev/null +++ b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/t48/decoder.vhd @@ -0,0 +1,2123 @@ +------------------------------------------------------------------------------- +-- +-- The Decoder unit. +-- It decodes the instruction opcodes and executes them. +-- +-- $Id: decoder.vhd 304 2022-12-17 20:54:18Z arniml $ +-- +-- Copyright (c) 2004, Arnim Laeuger (arniml@opencores.org) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.opencores.org/cvsweb.shtml/t48/ +-- +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; + +use work.t48_pack.word_t; +use work.t48_pack.mstate_t; +use work.t48_alu_pack.alu_op_t; +use work.t48_cond_branch_pack.all; +use work.t48_dmem_ctrl_pack.all; +use work.t48_pmem_ctrl_pack.all; + +entity t48_decoder is + + generic ( + -- store mnemonic in flip-flops (registered-out) + register_mnemonic_g : integer := 1; + is_upi_g : integer := 0; + is_upi_type_a_g : integer := 0 + ); + + port ( + -- Global Interface ------------------------------------------------------- + clk_i : in std_logic; + res_i : in std_logic; + en_clk_i : in boolean; + xtal_i : in std_logic; + xtal_en_i : in boolean; + ea_i : in std_logic; + ale_i : in boolean; + int_n_i : in std_logic; + t0_dir_o : out std_logic; + -- T48 Bus Interface ------------------------------------------------------ + data_i : in word_t; + data_o : out word_t; + alu_write_accu_o : out boolean; + alu_write_shadow_o : out boolean; + alu_write_temp_reg_o : out boolean; + alu_read_alu_o : out boolean; + bus_write_bus_o : out boolean; + bus_read_bus_o : out boolean; + bus_set_f1_i : in boolean := false; -- UPI41 + bus_clear_f1_i : in boolean := false; -- UPI41 + bus_ibf_int_o : out boolean; -- UPI41 + bus_en_dma_o : out boolean; -- UPI41A + bus_en_flags_o : out boolean; -- UPI41A + bus_write_sts_o : out boolean; -- UPI41A + dm_write_dmem_addr_o : out boolean; + dm_write_dmem_o : out boolean; + dm_read_dmem_o : out boolean; + p1_write_p1_o : out boolean; + p1_read_p1_o : out boolean; + p2_write_p2_o : out boolean; + p2_write_exp_o : out boolean; + p2_read_p2_o : out boolean; + p2_read_exp_o : out boolean; + pm_write_pcl_o : out boolean; + pm_read_pcl_o : out boolean; + pm_write_pch_o : out boolean; + pm_read_pch_o : out boolean; + pm_read_pmem_o : out boolean; + psw_read_psw_o : out boolean; + psw_read_sp_o : out boolean; + psw_write_psw_o : out boolean; + psw_write_sp_o : out boolean; + -- ALU Interface ---------------------------------------------------------- + alu_carry_i : in std_logic; + alu_op_o : out alu_op_t; + alu_use_carry_o : out boolean; + alu_da_high_o : out boolean; + alu_accu_low_o : out boolean; + alu_p06_temp_reg_o : out boolean; + alu_p60_temp_reg_o : out boolean; + alu_da_overflow_i : in boolean; + -- BUS Interface ---------------------------------------------------------- + bus_output_pcl_o : out boolean; + bus_bidir_bus_o : out boolean; + -- Clock Controller Interface --------------------------------------------- + clk_multi_cycle_o : out boolean; + clk_assert_psen_o : out boolean; + clk_assert_prog_o : out boolean; + clk_assert_rd_o : out boolean; + clk_assert_wr_o : out boolean; + clk_mstate_i : in mstate_t; + clk_second_cycle_i : in boolean; + -- Conditional Branch Logic Interface ------------------------------------- + cnd_compute_take_o : out boolean; + cnd_branch_cond_o : out branch_conditions_t; + cnd_take_branch_i : in boolean; + cnd_comp_value_o : out comp_value_t; + cnd_f1_o : out std_logic; + cnd_tf_o : out std_logic; + -- Data Memory Controller Interface --------------------------------------- + dm_addr_type_o : out dmem_addr_ident_t; + -- Port 1 Interface ------------------------------------------------------- + p1_read_reg_o : out boolean; + -- Port 2 Interface ------------------------------------------------------- + p2_read_reg_o : out boolean; + p2_output_pch_o : out boolean; + -- Program Memory Controller Interface ------------------------------------ + pm_inc_pc_o : out boolean; + pm_write_pmem_addr_o : out boolean; + pm_addr_type_o : out pmem_addr_ident_t; + -- Program Status Word Interface ------------------------------------------ + psw_special_data_o : out std_logic; + psw_carry_i : in std_logic; + psw_aux_carry_i : in std_logic; + psw_f0_i : in std_logic; + psw_inc_stackp_o : out boolean; + psw_dec_stackp_o : out boolean; + psw_write_carry_o : out boolean; + psw_write_aux_carry_o : out boolean; + psw_write_f0_o : out boolean; + psw_write_bs_o : out boolean; + -- Timer Interface -------------------------------------------------------- + tim_read_timer_o : out boolean; + tim_write_timer_o : out boolean; + tim_start_t_o : out boolean; + tim_start_cnt_o : out boolean; + tim_stop_tcnt_o : out boolean; + tim_overflow_i : in boolean + ); + +end t48_decoder; + + +use work.t48_pack.all; +use work.t48_alu_pack.all; +use work.t48_decoder_pack.all; + +use work.t48_comp_pack.t48_int; + +-- pragma translate_off +use work.t48_tb_pack.tb_istrobe_s; +-- pragma translate_on + +architecture rtl of t48_decoder is + + -- Enable fixing a bug of Quartus II 4.0 + constant enable_quartus_bugfix_c : boolean := true; + + -- Opcode Decoder + signal opc_multi_cycle_s : boolean; + signal opc_read_bus_s : boolean; + signal opc_inj_int_s : boolean; + signal opc_opcode_q : word_t; + signal opc_mnemonic_s : mnemonic_t; + signal last_cycle_s : boolean; + + -- state translators + signal assert_psen_s : boolean; + + -- branch taken handshake + signal branch_taken_s, + branch_taken_q : boolean; + signal pm_inc_pc_s : boolean; + signal pm_write_pmem_addr_s : boolean; + -- additional signal to increment PC during CALL + signal add_inc_pc_s : boolean; + -- addtional signal to set PC during RET(R) + signal add_write_pmem_addr_s : boolean; + + -- Flag 1 + signal clear_f1_s, + cpl_f1_s : boolean; + signal f1_q : std_logic; + -- memory bank select + signal clear_mb_s, + set_mb_s : boolean; + signal mb_q : std_logic; + + -- T0 direction selection + signal ent0_clk_s : boolean; + signal t0_dir_q : std_logic; + + signal data_s : word_t; + signal read_dec_s : boolean; + + signal tf_s : std_logic; + + signal bus_read_bus_s : boolean; + signal add_read_bus_s : boolean; + + signal dm_write_dmem_s : boolean; + + signal p2_output_exp_s : boolean; + + signal movx_first_cycle_s : boolean; + + -- interrupt handling + signal jtf_executed_s : boolean; + signal en_tcnti_s : boolean; + signal dis_tcnti_s : boolean; + signal en_i_s : boolean; + signal dis_i_s : boolean; + signal tim_int_s : boolean; + signal retr_executed_s : boolean; + signal int_executed_s : boolean; + signal int_pending_s : boolean; + signal int_in_progress_s : boolean; + + -- the mnemonic + signal mnemonic_rec_s : mnemonic_rec_t; + signal mnemonic_q : mnemonic_t; + + -- pragma translate_off + signal istrobe_res_q : std_logic; + signal istrobe_q : std_logic; + signal injected_int_q : std_logic; + -- pragma translate_on + +begin + + -- pragma translate_off + + -- Register Mnemonic -------------------------------------------------------- + assert (register_mnemonic_g = 1) or (register_mnemonic_g = 0) + report "register_mnemonic_g must be either 1 or 0!" + severity failure; + + -- UPI41 configuration ------------------------------------------------------ + assert (is_upi_g = 0) or (is_upi_g = 1) + report "is_upi_g must be either 1 or 0!" + severity failure; + -- + assert (is_upi_type_a_g = 0) or (is_upi_type_a_g = 1) + report "is_upi_type_a_g must be either 1 or 0!" + severity failure; + + -- pragma translate_on + + + ----------------------------------------------------------------------------- + -- Opcode Decoder + -- + gen_mcs48: if is_upi_g = 0 generate + mnemonic_rec_s <= decode_mcs48_opcode_f (opcode => opc_opcode_q); + end generate; + gen_upi41: if is_upi_g = 1 and is_upi_type_a_g = 0 generate + mnemonic_rec_s <= decode_upi41_opcode_f (opcode => opc_opcode_q); + end generate; + gen_upi41a: if is_upi_g = 1 and is_upi_type_a_g = 1 generate + mnemonic_rec_s <= decode_upi41a_opcode_f(opcode => opc_opcode_q); + end generate; + -- + ----------------------------------------------------------------------------- + + + ----------------------------------------------------------------------------- + -- Process opc_regs + -- + -- Purpose: + -- Implements the opcode and mnemonic registers. + -- + opc_regs: process (res_i, clk_i) + begin + if res_i = res_active_c then + opc_opcode_q <= (others => '0'); -- NOP + mnemonic_q <= MN_NOP; + + elsif clk_i'event and clk_i = clk_active_c then + if en_clk_i then + + if opc_read_bus_s then + opc_opcode_q <= data_i; + elsif opc_inj_int_s then + opc_opcode_q <= "00010100"; + else + mnemonic_q <= mnemonic_rec_s.mnemonic; + end if; + + end if; + + end if; + + end process opc_regs; + -- + opc_multi_cycle_s <= mnemonic_rec_s.multi_cycle; + opc_mnemonic_s <= mnemonic_q + when register_mnemonic_g = 1 else + mnemonic_rec_s.mnemonic; + -- + ----------------------------------------------------------------------------- + + + ----------------------------------------------------------------------------- + -- Interrupt Controller. + ----------------------------------------------------------------------------- + int_b : t48_int + port map ( + clk_i => clk_i, + res_i => res_i, + en_clk_i => en_clk_i, + xtal_i => xtal_i, + xtal_en_i => xtal_en_i, + clk_mstate_i => clk_mstate_i, + jtf_executed_i => jtf_executed_s, + tim_overflow_i => tim_overflow_i, + tf_o => tf_s, + en_tcnti_i => en_tcnti_s, + dis_tcnti_i => dis_tcnti_s, + int_n_i => int_n_i, + ale_i => ale_i, + last_cycle_i => last_cycle_s, + en_i_i => en_i_s, + dis_i_i => dis_i_s, + ext_int_o => open, + tim_int_o => tim_int_s, + retr_executed_i => retr_executed_s, + int_executed_i => int_executed_s, + int_pending_o => int_pending_s, + int_in_progress_o => int_in_progress_s + ); + + last_cycle_s <= not opc_multi_cycle_s or + (opc_multi_cycle_s and clk_second_cycle_i); + + ----------------------------------------------------------------------------- + -- Process machine_cycle + -- + -- Purpose: + -- Generates the control signals that are basically needed for the + -- handling of a machine cycle. + -- + machine_cycle: process (clk_mstate_i, + clk_second_cycle_i, + last_cycle_s, + ea_i, + assert_psen_s, + branch_taken_q, + int_pending_s, + p2_output_exp_s, + movx_first_cycle_s) + + variable need_address_v : boolean; + + begin + -- default assignments + clk_assert_psen_o <= false; + pm_inc_pc_s <= false; + pm_write_pmem_addr_s <= false; + pm_read_pmem_o <= false; + bus_output_pcl_o <= false; + p2_output_pch_o <= false; + opc_read_bus_s <= false; + opc_inj_int_s <= false; + bus_read_bus_s <= false; + + need_address_v := not clk_second_cycle_i or + (clk_second_cycle_i and assert_psen_s); + + case clk_mstate_i is + when MSTATE1 => + if need_address_v then + if ea_i = '0' then + if not int_pending_s then + pm_read_pmem_o <= true; + end if; + + else + if not int_pending_s then + bus_read_bus_s <= true; + end if; + p2_output_pch_o <= true; + end if; + + end if; + + if not clk_second_cycle_i then + if not int_pending_s then + opc_read_bus_s <= true; + else + opc_inj_int_s <= true; -- inject interrupt call + end if; + end if; + + when MSTATE2 => + if need_address_v and not branch_taken_q and + not int_pending_s then + pm_inc_pc_s <= true; + end if; + + when MSTATE3 => + if need_address_v then + -- Theory of operation: + -- Program Memory address is updated at end of State 3 (or end of + -- State 2 in case of a RET). Address information is thus available + -- latest with State 4. + -- This is the time where we need information about access target + -- (internal or external = EA). EA information needs to be stable + -- until end of State 1. + pm_write_pmem_addr_s <= true; + end if; + + when MSTATE4 => + if ea_i = '1' and + ((not clk_second_cycle_i and assert_psen_s) + or last_cycle_s) then + clk_assert_psen_o <= true; + p2_output_pch_o <= true; + bus_output_pcl_o <= true; + end if; + + when MSTATE5 => + if ea_i = '1' and + (need_address_v or last_cycle_s) and + -- Suppress output of PCH when either + -- a) expander port is driven on P2, has priority + not p2_output_exp_s and + -- b) first cycle of MOVX, don't disturb external access + not movx_first_cycle_s then + p2_output_pch_o <= true; + end if; + + when others => + -- pragma translate_off + assert false + report "Unkown machine state!" + severity error; + -- pragma translate_on + + end case; + + end process machine_cycle; + -- + ----------------------------------------------------------------------------- + + + ----------------------------------------------------------------------------- + -- Process decode + -- + -- Purpose: + -- Indentifies each single instruction and steps through the related + -- execution sequence. + -- + decode: process (alu_carry_i, + psw_aux_carry_i, + alu_da_overflow_i, + clk_mstate_i, + clk_second_cycle_i, + cnd_take_branch_i, + opc_opcode_q, + opc_mnemonic_s, + psw_carry_i, + psw_f0_i, + f1_q, + mb_q, + tim_int_s, + int_pending_s, + int_in_progress_s) + + procedure address_indirect_3_f is + begin + -- apply dmem address from selected register for indirect mode + if opc_opcode_q(3) = '0' or enable_quartus_bugfix_c then + dm_read_dmem_o <= true; + dm_write_dmem_addr_o <= true; + dm_addr_type_o <= DM_PLAIN; + end if; + end; + + procedure and_or_xor_add_4_f is + begin + -- write dmem contents to Temp Reg + dm_read_dmem_o <= true; + alu_write_temp_reg_o <= true; + end; + + procedure and_or_xor_add_5_f (alu_op : alu_op_t) is + begin + -- perform ALU operation and store in Accumulator + alu_op_o <= alu_op; + alu_read_alu_o <= true; + alu_write_accu_o <= true; + end; + + procedure cond_jump_c2_m1_f is + begin + -- store address in Program Counter low byte if branch has to + -- be taken +-- if clk_mstate_i = MSTATE1 and cnd_take_branch_i then + pm_write_pcl_o <= true; + branch_taken_s <= true; +-- end if; + end; + + -- intermediate value of the Program Memory Bank Flag + variable mb_v : std_logic; + + begin + -- default assignments + data_s <= (others => '-'); + read_dec_s <= false; + branch_taken_s <= false; + clear_f1_s <= false; + cpl_f1_s <= false; + clear_mb_s <= false; + set_mb_s <= false; + add_inc_pc_s <= false; + assert_psen_s <= false; + alu_write_accu_o <= false; + alu_write_shadow_o <= false; + alu_write_temp_reg_o <= false; + alu_p06_temp_reg_o <= false; + alu_p60_temp_reg_o <= false; + alu_read_alu_o <= false; + bus_write_bus_o <= false; + bus_bidir_bus_o <= false; + bus_ibf_int_o <= false; -- UPI41 + bus_en_dma_o <= false; -- UPI41A + bus_en_flags_o <= false; -- UPI41A + bus_write_sts_o <= false; -- UPI41A + dm_write_dmem_addr_o <= false; + dm_write_dmem_s <= false; + dm_read_dmem_o <= false; + pm_write_pcl_o <= false; + pm_read_pcl_o <= false; + pm_write_pch_o <= false; + pm_read_pch_o <= false; + pm_addr_type_o <= PM_PC; + psw_read_psw_o <= false; + psw_read_sp_o <= false; + psw_write_psw_o <= false; + psw_write_sp_o <= false; + alu_op_o <= ALU_NOP; + alu_use_carry_o <= false; + alu_da_high_o <= false; + alu_accu_low_o <= false; + clk_assert_prog_o <= false; + clk_assert_rd_o <= false; + clk_assert_wr_o <= false; + cnd_branch_cond_o <= COND_ON_BIT; + cnd_compute_take_o <= false; + cnd_comp_value_o <= opc_opcode_q(7 downto 5); + dm_addr_type_o <= DM_REG; + tim_read_timer_o <= false; + tim_write_timer_o <= false; + tim_start_t_o <= false; + tim_start_cnt_o <= false; + tim_stop_tcnt_o <= false; + p1_write_p1_o <= false; + p1_read_p1_o <= false; + p1_read_reg_o <= false; + p2_write_p2_o <= false; + p2_write_exp_o <= false; + p2_read_p2_o <= false; + p2_read_reg_o <= false; + p2_read_exp_o <= false; + p2_output_exp_s <= false; + psw_special_data_o <= '0'; + psw_inc_stackp_o <= false; + psw_dec_stackp_o <= false; + psw_write_carry_o <= false; + psw_write_aux_carry_o <= false; + psw_write_f0_o <= false; + psw_write_bs_o <= false; + jtf_executed_s <= false; + en_tcnti_s <= false; + dis_tcnti_s <= false; + en_i_s <= false; + dis_i_s <= false; + retr_executed_s <= false; + int_executed_s <= false; + add_write_pmem_addr_s <= false; + ent0_clk_s <= false; + add_read_bus_s <= false; + movx_first_cycle_s <= false; + + -- the Program Memory Bank Flag is held low when interrupts are in progress + -- according to the MCS-48 User's Manual + if int_in_progress_s then + mb_v := '0'; + else + mb_v := mb_q; + end if; + + -- prepare potential register indirect address mode + if not clk_second_cycle_i and clk_mstate_i = MSTATE2 then + data_s <= (others => '0'); + if opc_opcode_q(3) = '1' then + data_s(2 downto 0) <= opc_opcode_q(2 downto 0); + else + data_s(2 downto 0) <= "00" & opc_opcode_q(0); + end if; + + read_dec_s <= true; + dm_write_dmem_addr_o <= true; + dm_addr_type_o <= DM_REG; + end if; + + case opc_mnemonic_s is + + -- Mnemonic ADD --------------------------------------------------------- + when MN_ADD => + case clk_mstate_i is + -- read RAM once for indirect address mode + when MSTATE3 => + if not enable_quartus_bugfix_c or + opc_opcode_q(3) = '0' then + address_indirect_3_f; + end if; + + -- store data from RAM to Temp Reg + when MSTATE4 => + and_or_xor_add_4_f; + + -- perform ADD and store in Accumulator + when MSTATE5 => + and_or_xor_add_5_f(alu_op => ALU_ADD); + + if opc_opcode_q(4) = '1' then + alu_use_carry_o <= true; + end if; + + psw_special_data_o <= alu_carry_i; + psw_write_carry_o <= true; + psw_write_aux_carry_o <= true; + + when others => + null; + + end case; + + -- Mnemonic ADD_A_DATA -------------------------------------------------- + when MN_ADD_A_DATA => + assert_psen_s <= true; + + if clk_second_cycle_i then + case clk_mstate_i is + -- write Temp Reg when contents of Program Memory is on bus + when MSTATE1 => + alu_write_temp_reg_o <= true; + + -- perform ADD and store in Accumulator + when MSTATE3 => + and_or_xor_add_5_f(alu_op => ALU_ADD); + + if opc_opcode_q(4) = '1' then + alu_use_carry_o <= true; + end if; + + psw_special_data_o <= alu_carry_i; + psw_write_carry_o <= true; + psw_write_aux_carry_o <= true; + + when others => + null; + + end case; + + end if; + + -- Mnemonic ANL --------------------------------------------------------- + when MN_ANL => + case clk_mstate_i is + -- read RAM once for indirect address mode + when MSTATE3 => + if not enable_quartus_bugfix_c or + opc_opcode_q(3) = '0' then + address_indirect_3_f; + end if; + + -- store data from RAM to Temp Reg + when MSTATE4 => + and_or_xor_add_4_f; + + -- perform AND and store in Accumulator + when MSTATE5 => + and_or_xor_add_5_f(alu_op => ALU_AND); + + when others => + null; + + end case; + + -- Mnemonic ANL_A_DATA -------------------------------------------------- + when MN_ANL_A_DATA => + assert_psen_s <= true; + + if clk_second_cycle_i then + case clk_mstate_i is + -- write Temp Reg when contents of Program Memory is on bus + when MSTATE1 => + alu_write_temp_reg_o <= true; + + -- perform AND and store in Accumulator + when MSTATE3 => + and_or_xor_add_5_f(alu_op => ALU_AND); + + when others => + null; + + end case; + + end if; + + -- Mnemonic ANL_EXT ----------------------------------------------------- + when MN_ANL_EXT => + assert_psen_s <= true; + + if not clk_second_cycle_i then + -- read port to Temp Reg + if clk_mstate_i = MSTATE5 then + if opc_opcode_q(1 downto 0) = "00" then + add_read_bus_s <= true; + elsif opc_opcode_q(1) = '0' then + p1_read_p1_o <= true; + p1_read_reg_o <= true; + else + p2_read_p2_o <= true; + p2_read_reg_o <= true; + end if; + + alu_write_temp_reg_o <= true; + end if; + + else + case clk_mstate_i is + -- write shadow Accumulator when contents of Program Memory is + -- on bus + when MSTATE1 => + alu_write_shadow_o <= true; + + -- loop shadow Accumulator through ALU to prevent update from + -- real Accumulator + when MSTATE2 => + alu_read_alu_o <= true; + alu_write_shadow_o <= true; + + -- write result of AND operation back to port + when MSTATE3 => + alu_op_o <= ALU_AND; + alu_read_alu_o <= true; + + if opc_opcode_q(1 downto 0) = "00" then + bus_write_bus_o <= true; + elsif opc_opcode_q(1) = '0' then + p1_write_p1_o <= true; + else + p2_write_p2_o <= true; + end if; + + when others => + null; + + end case; + + end if; + + -- Mnemonic CALL -------------------------------------------------------- + when MN_CALL => + assert_psen_s <= true; + + if not clk_second_cycle_i then + case clk_mstate_i is + -- read Stack Pointer and address Data Memory for low byte + -- also increment Program Counter to point to next instruction + when MSTATE3 => + psw_read_sp_o <= true; + dm_write_dmem_addr_o <= true; + dm_addr_type_o <= DM_STACK; + + -- only increment PC if this is not an injected CALL + -- injected CALLS are not located in Program Memory, + -- the PC points already to the instruction to be executed + -- after the interrupt + if not int_pending_s then + add_inc_pc_s <= true; + end if; + + -- store Program Counter low byte on stack + when MSTATE4 => + pm_read_pcl_o <= true; + dm_write_dmem_s <= true; + + -- store Program Counter high byte and PSW on stack + -- increment Stack pointer + when MSTATE5 => + psw_read_psw_o <= true; + pm_read_pch_o <= true; + dm_write_dmem_addr_o <= true; + dm_addr_type_o <= DM_STACK_HIGH; + dm_write_dmem_s <= true; + psw_inc_stackp_o <= true; + + when others => + null; + + end case; + + else + case clk_mstate_i is + -- store address in Program Counter low byte + when MSTATE1 => + pm_write_pcl_o <= true; + branch_taken_s <= true; + if int_pending_s then + -- apply low part of vector address manually + data_s <= (others => '0'); + data_s(1 downto 0) <= "11"; + if tim_int_s then + data_s(2) <= '1'; + else + bus_ibf_int_o <= true; -- UPI41 + end if; + read_dec_s <= true; + end if; + + when MSTATE2 => + pm_write_pch_o <= true; + read_dec_s <= true; + if not int_pending_s then + -- store high part of target address in Program Counter + data_s <= "0000" & mb_v & opc_opcode_q(7 downto 5); + else + -- apply high part of vector address manually + data_s <= (others => '0'); + int_executed_s <= true; + end if; + + when others => + null; + + end case; + + end if; + + -- Mnemonic CLR_A ------------------------------------------------------- + when MN_CLR_A => + -- write CLR output of ALU to Accumulator + if clk_mstate_i = MSTATE3 then + alu_op_o <= ALU_CLR; + alu_read_alu_o <= true; + alu_write_accu_o <= true; + end if; + + -- Mnemonic CLR_C ------------------------------------------------------- + when MN_CLR_C => + -- store 0 to Carry + if clk_mstate_i = MSTATE3 then + psw_special_data_o <= '0'; + psw_write_carry_o <= true; + end if; + + -- Mnemonic CLR_F ------------------------------------------------------- + when MN_CLR_F => + -- store 0 to selected flag + if clk_mstate_i = MSTATE3 then + if opc_opcode_q(5) = '0' then + psw_special_data_o <= '0'; + psw_write_f0_o <= true; + else + clear_f1_s <= true; + end if; + + end if; + + -- Mnemonic CPL_A ------------------------------------------------------- + when MN_CPL_A => + -- write CPL output of ALU to Accumulator + if clk_mstate_i = MSTATE3 then + alu_op_o <= ALU_CPL; + alu_read_alu_o <= true; + alu_write_accu_o <= true; + end if; + + -- Mnemnonic CPL_C ------------------------------------------------------ + when MN_CPL_C => + -- write inverse of Carry to PSW + if clk_mstate_i = MSTATE3 then + psw_special_data_o <= not psw_carry_i; + psw_write_carry_o <= true; + end if; + + -- Mnemonic CPL_F ------------------------------------------------------- + when MN_CPL_f => + -- write inverse of selected flag back to flag + if clk_mstate_i = MSTATE3 then + if opc_opcode_q(5) = '0' then + psw_special_data_o <= not psw_f0_i; + psw_write_f0_o <= true; + else + cpl_f1_s <= true; + end if; + + end if; + + -- Mnemonic DA ---------------------------------------------------------- + when MN_DA => + alu_op_o <= ALU_ADD; + + case clk_mstate_i is + -- Step 1: Preload Temp Reg with 0x06 + when MSTATE3 => + alu_p06_temp_reg_o <= true; + + -- Step 2: Check Auxiliary Carry and overflow on low nibble + -- Add 0x06 to shadow Accumulator if one is true + when MSTATE4 => + if psw_aux_carry_i = '1' or alu_da_overflow_i then + alu_read_alu_o <= true; + alu_write_shadow_o <= true; + end if; + + -- preload Temp Reg with 0x60 + alu_p60_temp_reg_o <= true; + + -- Step 3: Check overflow on high nibble + -- Add 0x60 to shadow Accumulator if true and store result + -- in Accumulator and PSW (only Carry) + when MSTATE5 => + alu_da_high_o <= true; + + if alu_da_overflow_i then + psw_special_data_o <= alu_carry_i; + else + alu_op_o <= ALU_NOP; + psw_special_data_o <= '0'; + end if; + alu_read_alu_o <= true; + alu_write_accu_o <= true; + psw_write_carry_o <= true; + + when others => + null; + + end case; + + -- Mnemonic DEC --------------------------------------------------------- + when MN_DEC => + case clk_mstate_i is + when MSTATE4 => + -- DEC Rr: store data from RAM to shadow Accumulator + if opc_opcode_q(6) = '1' then + dm_read_dmem_o <= true; + alu_write_shadow_o <= true; + end if; + + when MSTATE5 => + alu_op_o <= ALU_DEC; + alu_read_alu_o <= true; + + if opc_opcode_q(6) = '0' then + -- write DEC of Accumulator to Accumulator + alu_write_accu_o <= true; + else + -- store DEC of shadow Accumulator back to dmem + dm_write_dmem_s <= true; + end if; + + when others => + null; + + end case; + + -- Mnemonic DIS_EN_I ---------------------------------------------------- + when MN_DIS_EN_I => + if clk_mstate_i = MSTATE3 then + if opc_opcode_q(4) = '1' then + dis_i_s <= true; + else + en_i_s <= true; + end if; + end if; + + -- Mnemonic DIS_EN_TCNTI ------------------------------------------------ + when MN_DIS_EN_TCNTI => + if clk_mstate_i = MSTATE3 then + if opc_opcode_q(4) = '1' then + dis_tcnti_s <= true; + else + en_tcnti_s <= true; + end if; + end if; + + -- Mnemonic DJNZ -------------------------------------------------------- + when MN_DJNZ => + assert_psen_s <= true; + + if not clk_second_cycle_i then + case clk_mstate_i is + -- store data from RAM to shadow Accumulator + when MSTATE4 => + dm_read_dmem_o <= true; + alu_write_shadow_o <= true; + + -- write DEC result of shadow Accumulator back to dmem and + -- conditional branch logic + when MSTATE5 => + alu_op_o <= ALU_DEC; + alu_read_alu_o <= true; + dm_write_dmem_s <= true; + + cnd_compute_take_o <= true; + cnd_branch_cond_o <= COND_Z; + cnd_comp_value_o(0) <= '0'; + + when others => + null; + + end case; + + else + -- store address in Program Counter low byte if branch has to + -- be taken + if clk_mstate_i = MSTATE1 and cnd_take_branch_i then + cond_jump_c2_m1_f; + end if; + + end if; + + -- Mnemonic EN_DMA_FLAGS - UPI41A --------------------------------------- + when MN_EN_DMA_FLAGS => + if clk_mstate_i = MSTATE4 then + if opc_opcode_q(4) = '0' then + bus_en_dma_o <= true; + else + bus_en_flags_o <= true; + end if; + end if; + + -- Mnemonic ENT0_CLK ---------------------------------------------------- + when MN_ENT0_CLK => + if clk_mstate_i = MSTATE3 then + ent0_clk_s <= true; + end if; + + -- Mnemonic IN ---------------------------------------------------------- + when MN_IN => + -- read Port and store in Accumulator + if clk_second_cycle_i and clk_mstate_i = MSTATE2 then + alu_write_accu_o <= true; + + if opc_opcode_q(1) = '0' then + p1_read_p1_o <= true; + else + p2_read_p2_o <= true; + end if; + end if; + + -- Mnemonic IN_DBB - UPI41 ---------------------------------------------- + when MN_IN_DBB => + -- read BUS and store in Accumulator + if clk_mstate_i = MSTATE4 then + alu_write_accu_o <= true; + + add_read_bus_s <= true; + end if; + + -- Mnemonic INS --------------------------------------------------------- + when MN_INS => + clk_assert_rd_o <= true; + + -- read BUS and store in Accumulator + if clk_second_cycle_i and clk_mstate_i = MSTATE2 then + alu_write_accu_o <= true; + + add_read_bus_s <= true; + end if; + + -- Mnemonic INC --------------------------------------------------------- + when MN_INC => + case clk_mstate_i is + -- read RAM once for indirect address mode + when MSTATE3 => + if not enable_quartus_bugfix_c or + opc_opcode_q(3) = '0' then + address_indirect_3_f; + end if; + + when MSTATE4 => + -- INC Rr; INC @ Rr: store data from RAM to shadow Accumulator + if opc_opcode_q(3 downto 2) /= "01" then + dm_read_dmem_o <= true; + alu_write_shadow_o <= true; + end if; + + when MSTATE5 => + alu_op_o <= ALU_INC; + alu_read_alu_o <= true; + + if opc_opcode_q(3 downto 2) = "01" then + -- write INC output of ALU to Accumulator + alu_write_accu_o <= true; + else + -- store INC of shadow Accumulator back to dmem + dm_write_dmem_s <= true; + end if; + + when others => + null; + + end case; + + -- Mnemonic JBB --------------------------------------------------------- + when MN_JBB => + assert_psen_s <= true; + cnd_branch_cond_o <= COND_ON_BIT; + + if not clk_second_cycle_i then + -- read Accumulator and start branch calculation + if clk_mstate_i = MSTATE3 then + alu_read_alu_o <= true; + cnd_compute_take_o <= true; + -- cnd_comp_value_o is ok by default assignment + end if; + + else + -- store address in Program Counter low byte if branch has to + -- be taken + if clk_mstate_i = MSTATE1 and cnd_take_branch_i then + cond_jump_c2_m1_f; + end if; + + end if; + + -- Mnemonic JC ---------------------------------------------------------- + when MN_JC => + assert_psen_s <= true; + cnd_branch_cond_o <= COND_C; + + if not clk_second_cycle_i then + -- start branch calculation + if clk_mstate_i = MSTATE3 then + cnd_compute_take_o <= true; + cnd_comp_value_o(0) <= opc_opcode_q(4); + end if; + + else + -- store address in Program Counter low byte if branch has to + -- be taken + if clk_mstate_i = MSTATE1 and cnd_take_branch_i then + cond_jump_c2_m1_f; + end if; + + end if; + + -- Mnemonic JF ---------------------------------------------------------- + when MN_JF => + assert_psen_s <= true; + + if not clk_second_cycle_i then + -- start branch calculation + if clk_mstate_i = MSTATE3 then + cnd_compute_take_o <= true; + if opc_opcode_q(7) = '1' then + -- JF0 + cnd_branch_cond_o <= COND_F0; + else + -- JF1 + cnd_branch_cond_o <= COND_F1; + end if; + + end if; + + else + -- store address in Program Counter low byte if branch has to + -- be taken + if clk_mstate_i = MSTATE1 and cnd_take_branch_i then + cond_jump_c2_m1_f; + end if; + + end if; + + + -- Mnemonic JMP --------------------------------------------------------- + when MN_JMP => + assert_psen_s <= true; + + if clk_second_cycle_i then + case clk_mstate_i is + -- store address in Program Counter low byte + when MSTATE1 => + pm_write_pcl_o <= true; + branch_taken_s <= true; + + -- store high part of target address in Program Counter + when MSTATE2 => + data_s <= "0000" & mb_v & opc_opcode_q(7 downto 5); + read_dec_s <= true; + pm_write_pch_o <= true; + + when others => + null; + + end case; + + end if; + + -- Mnemonic JMPP -------------------------------------------------------- + when MN_JMPP => + assert_psen_s <= true; + + if not clk_second_cycle_i then + -- write Accumulator to Program Memory address + -- (skip page offset update from Program Counter) + if clk_mstate_i = MSTATE3 then + alu_read_alu_o <= true; + pm_addr_type_o <= PM_PAGE; + end if; + + else + if clk_mstate_i = MSTATE1 then + -- store address in Program Counter low byte + pm_write_pcl_o <= true; + branch_taken_s <= true; + end if; + + end if; + + -- Mnemonic JNI --------------------------------------------------------- + when MN_JNI => + assert_psen_s <= true; + cnd_branch_cond_o <= COND_INT; + + if not clk_second_cycle_i then + -- start branch calculation + if clk_mstate_i = MSTATE3 then + cnd_compute_take_o <= true; + end if; + + else + -- store address in Program Counter low byte if branch has to + -- be taken + if clk_mstate_i = MSTATE1 and cnd_take_branch_i then + cond_jump_c2_m1_f; + end if; + + end if; + + -- Mnemonic JNIBF - UPI41 ----------------------------------------------- + when MN_JNIBF => + assert_psen_s <= true; + cnd_branch_cond_o <= COND_NIBF; + + if not clk_second_cycle_i then + -- start branch calculation + if clk_mstate_i = MSTATE3 then + cnd_compute_take_o <= true; + end if; + + else + -- store address in Program Counter low byte if branch has to + -- be taken + if clk_mstate_i = MSTATE1 and cnd_take_branch_i then + cond_jump_c2_m1_f; + end if; + + end if; + + -- Mnemonic JOBF - UPI41 ------------------------------------------------ + when MN_JOBF => + assert_psen_s <= true; + cnd_branch_cond_o <= COND_OBF; + + if not clk_second_cycle_i then + -- start branch calculation + if clk_mstate_i = MSTATE3 then + cnd_compute_take_o <= true; + end if; + + else + -- store address in Program Counter low byte if branch has to + -- be taken + if clk_mstate_i = MSTATE1 and cnd_take_branch_i then + cond_jump_c2_m1_f; + end if; + + end if; + + -- Mnemonic JT ---------------------------------------------------------- + when MN_JT => + assert_psen_s <= true; + if opc_opcode_q(6) = '0' then + cnd_branch_cond_o <= COND_T0; + else + cnd_branch_cond_o <= COND_T1; + end if; + + if not clk_second_cycle_i then + -- start branch calculation + if clk_mstate_i = MSTATE3 then + cnd_compute_take_o <= true; + cnd_comp_value_o(0) <= opc_opcode_q(4); + end if; + + else + -- store address in Program Counter low byte if branch has to + -- be taken + if clk_mstate_i = MSTATE1 and cnd_take_branch_i then + cond_jump_c2_m1_f; + end if; + + end if; + + -- Mnemonic JTF --------------------------------------------------------- + when MN_JTF => + assert_psen_s <= true; + cnd_branch_cond_o <= COND_TF; + + if not clk_second_cycle_i then + -- start branch calculation + if clk_mstate_i = MSTATE3 then + cnd_compute_take_o <= true; + jtf_executed_s <= true; + end if; + + else + -- store address in Program Counter low byte if branch has to + -- be taken + if clk_mstate_i = MSTATE1 and cnd_take_branch_i then + cond_jump_c2_m1_f; + end if; + + end if; + + -- Mnemonic JZ ---------------------------------------------------------- + when MN_JZ => + assert_psen_s <= true; + cnd_branch_cond_o <= COND_Z; + + if not clk_second_cycle_i then + -- read Accumulator and start branch calculation + if clk_mstate_i = MSTATE3 then + alu_read_alu_o <= true; + cnd_compute_take_o <= true; + cnd_comp_value_o(0) <= opc_opcode_q(6); + end if; + + else + -- store address in Program Counter low byte if branch has to + -- be taken + if clk_mstate_i = MSTATE1 and cnd_take_branch_i then + cond_jump_c2_m1_f; + end if; + + end if; + + -- Mnemonic MOV_A_DATA -------------------------------------------------- + when MN_MOV_A_DATA => + assert_psen_s <= true; + + -- Write Accumulator when contents of Program Memory is on bus + -- during machine state 1 of second cycle. + if clk_second_cycle_i and clk_mstate_i = MSTATE1 then + alu_write_accu_o <= true; + end if; + + -- Mnemonic MOV_A_RR ---------------------------------------------------- + when MN_MOV_A_RR => + case clk_mstate_i is + -- read RAM once for indirect address mode + when MSTATE3 => + if not enable_quartus_bugfix_c or + opc_opcode_q(3) = '0' then + address_indirect_3_f; + end if; + + -- read data from RAM and store in Accumulator + when MSTATE4 => + and_or_xor_add_4_f; + alu_write_accu_o <= true; + + when others => + null; + + end case; + + -- Mnemonic MOV_A_PSW --------------------------------------------------- + when MN_MOV_A_PSW => + if clk_mstate_i = MSTATE3 then + psw_read_psw_o <= true; + psw_read_sp_o <= true; + alu_write_accu_o <= true; + end if; + + -- Mnemoniv MOV_PSW_A --------------------------------------------------- + when MN_MOV_PSW_A => + if clk_mstate_i = MSTATE3 then + alu_read_alu_o <= true; + psw_write_psw_o <= true; + psw_write_sp_o <= true; + end if; + + -- Mnemonic MOV_RR ------------------------------------------------------ + when MN_MOV_RR => + case clk_mstate_i is + -- read RAM once for indirect address mode + when MSTATE3 => + if not enable_quartus_bugfix_c or + opc_opcode_q(3) = '0' then + address_indirect_3_f; + end if; + + -- write Accumulator to dmem + when MSTATE5 => + alu_read_alu_o <= true; + dm_write_dmem_s <= true; + + when others => + null; + + end case; + + -- Mnemonic MOV_RR_DATA ------------------------------------------------- + when MN_MOV_RR_DATA => + assert_psen_s <= true; + + -- read RAM once for indirect address mode + if not clk_second_cycle_i and clk_mstate_i = MSTATE3 then + if not enable_quartus_bugfix_c or + opc_opcode_q(3) = '0' then + address_indirect_3_f; + end if; + end if; + + -- Write Data Memory when contents of Program Memory is on bus + -- during machine state 1 of second cycle. + if clk_second_cycle_i and clk_mstate_i = MSTATE1 then + dm_write_dmem_s <= true; + end if; + + -- Mnemonic MOV_STS - UPI41A -------------------------------------------- + when MN_MOV_STS => + -- read Accumulator and store in STS register + if clk_mstate_i = MSTATE4 then + alu_read_alu_o <= true; + + bus_write_sts_o <= true; + end if; + + -- Mnemonic MOV_T ------------------------------------------------------- + when MN_MOV_T => + if clk_mstate_i = MSTATE3 then + if opc_opcode_q(5) = '1' then + alu_read_alu_o <= true; -- MOV T, A + tim_write_timer_o <= true; + else + tim_read_timer_o <= true; -- MOV A, T + alu_write_accu_o <= true; + end if; + end if; + + -- Mnemonic OUTD_PP_A --------------------------------------------------- + when MN_OUTD_PP_A => + clk_assert_prog_o <= true; + + if not clk_second_cycle_i then + case clk_mstate_i is + -- propagate expander port number to Port 2 + when MSTATE3 => + + data_s(7 downto 4) <= (others => '0'); + data_s(1 downto 0) <= opc_opcode_q(1 downto 0); + -- decide which 8243 command to use + case opc_opcode_q(7 downto 4) is + when "1001" => + data_s(3 downto 2) <= "11"; -- ANLD command + when "1000" => + data_s(3 downto 2) <= "10"; -- ORLD command + when "0011" => + data_s(3 downto 2) <= "01"; -- MOVD command + when others => + null; + end case; + + read_dec_s <= true; + p2_write_exp_o <= true; + + -- output expander port number on Port 2 while active edge of PROG + -- write Accumulator to expander port + when MSTATE4 => + p2_output_exp_s <= true; + + alu_read_alu_o <= true; + p2_write_exp_o <= true; + + when MSTATE5 => + p2_output_exp_s <= true; + + when others => + null; + + end case; + + else + -- hold expander port until inactive edge of PROG + if clk_mstate_i = MSTATE1 or clk_mstate_i = MSTATE2 then + p2_output_exp_s <= true; + end if; + + end if; + + -- Mnemonic MOVD_A_PP --------------------------------------------------- + when MN_MOVD_A_PP => + clk_assert_prog_o <= true; + + if not clk_second_cycle_i then + case clk_mstate_i is + -- propagate expander port number to Port 2 + when MSTATE3 => + data_s <= "0000" & + "00" & -- 8243 command: read + opc_opcode_q(1 downto 0); + read_dec_s <= true; + p2_write_exp_o <= true; + + -- output expander port number on Port 2 while active edge of PROG + -- write 1's to expander port to set lower nibble of Port 2 to input + when MSTATE4 => + p2_output_exp_s <= true; + + data_s(nibble_t'range) <= (others => '1'); + read_dec_s <= true; + p2_write_exp_o <= true; + + when MSTATE5 => + p2_output_exp_s <= true; + + when others => + null; + + end case; + + else + case clk_mstate_i is + -- hold expander port until inactive edge of PROG + when MSTATE1 => + p2_output_exp_s <= true; + + -- hold expander port until inactive edge of PROG + -- write Accumulator with nibble of expander port + when MSTATE2 => + p2_read_p2_o <= true; + p2_output_exp_s <= true; + p2_read_exp_o <= true; + alu_write_accu_o <= true; + + when others => + null; + + end case; + + end if; + + -- Mnemonic MOVP -------------------------------------------------------- + when MN_MOVP => + assert_psen_s <= true; + + if not clk_second_cycle_i then + -- write Accumulator to Program Memory address + -- (skip page offset update from Program Counter) + if clk_mstate_i = MSTATE3 then + alu_read_alu_o <= true; + if opc_opcode_q(6) = '0' then + pm_addr_type_o <= PM_PAGE; + else + pm_addr_type_o <= PM_PAGE3; + end if; + end if; + + else + if clk_mstate_i = MSTATE1 then + -- store data from Program Memory in Accumulator + alu_write_accu_o <= true; + -- trick & treat to prevent additional PC increment + -- our branch target is the previously incremented PC! + branch_taken_s <= true; + end if; + + end if; + + -- Mnemonic MOVX -------------------------------------------------------- + when MN_MOVX => + bus_bidir_bus_o <= true; + + if opc_opcode_q(4) = '0' then + clk_assert_rd_o <= true; + else + clk_assert_wr_o <= true; + end if; + + if not clk_second_cycle_i then + movx_first_cycle_s <= true; + case clk_mstate_i is + -- read dmem and put contents on BUS as external address + when MSTATE3 => + dm_read_dmem_o <= true; + bus_write_bus_o <= true; + + -- store contents of Accumulator to BUS + when MSTATE5 => + if opc_opcode_q(4) = '1' then + alu_read_alu_o <= true; + bus_write_bus_o <= true; + end if; + + when others => + null; + end case; + + else + if clk_mstate_i = MSTATE2 then + if opc_opcode_q(4) = '0' then + -- store contents of BUS in Accumulator + add_read_bus_s <= true; + alu_write_accu_o <= true; + else + -- store contents of Accumulator to BUS + -- to this to keep bus in output direction + alu_read_alu_o <= true; + bus_write_bus_o <= true; + end if; + end if; + + end if; + + -- Mnemonic NOP --------------------------------------------------------- + when MN_NOP => + -- nothing to do + + -- Mnemonic ORL --------------------------------------------------------- + when MN_ORL => + case clk_mstate_i is + -- read RAM once for indirect address mode + when MSTATE3 => + if not enable_quartus_bugfix_c or + opc_opcode_q(3) = '0' then + address_indirect_3_f; + end if; + + -- store data from RAM to Temp Reg + when MSTATE4 => + and_or_xor_add_4_f; + + -- perform OR and store in Accumulator + when MSTATE5 => + and_or_xor_add_5_f(alu_op => ALU_OR); + + when others => + null; + + end case; + + -- Mnemonic ORL_A_DATA -------------------------------------------------- + when MN_ORL_A_DATA => + assert_psen_s <= true; + + if clk_second_cycle_i then + case clk_mstate_i is + -- write Temp Reg when contents of Program Memory is on bus + when MSTATE1 => + alu_write_temp_reg_o <= true; + + -- perform OR and store in Accumulator + when MSTATE3 => + and_or_xor_add_5_f(alu_op => ALU_OR); + + when others => + null; + + end case; + + end if; + + -- Mnemonic ORL_EXT ----------------------------------------------------- + when MN_ORL_EXT => + assert_psen_s <= true; + + if not clk_second_cycle_i then + -- read port to Temp Reg + if clk_mstate_i = MSTATE5 then + if opc_opcode_q(1 downto 0) = "00" then + add_read_bus_s <= true; + elsif opc_opcode_q(1) = '0' then + p1_read_p1_o <= true; + p1_read_reg_o <= true; + else + p2_read_p2_o <= true; + p2_read_reg_o <= true; + end if; + + alu_write_temp_reg_o <= true; + end if; + + else + case clk_mstate_i is + -- write shadow Accumulator when contents of Program Memory is + -- on bus + when MSTATE1 => + alu_write_shadow_o <= true; + + -- loop shadow Accumulator through ALU to prevent update from + -- real Accumulator + when MSTATE2 => + alu_read_alu_o <= true; + alu_write_shadow_o <= true; + + -- write result of OR operation back to port + when MSTATE3 => + alu_op_o <= ALU_OR; + alu_read_alu_o <= true; + + if opc_opcode_q(1 downto 0) = "00" then + bus_write_bus_o <= true; + elsif opc_opcode_q(1) = '0' then + p1_write_p1_o <= true; + else + p2_write_p2_o <= true; + end if; + + when others => + null; + + end case; + + end if; + + -- Mnemonic OUT_DBB - UPI41 --------------------------------------------- + when MN_OUT_DBB => + -- read Accumulator and store in BUS output register + if clk_mstate_i = MSTATE4 then + alu_read_alu_o <= true; + + bus_write_bus_o <= true; + end if; + + -- Mnemonic OUTL_EXT ---------------------------------------------------- + when MN_OUTL_EXT => + if opc_opcode_q(4) = '0' then + clk_assert_wr_o <= true; + end if; + + -- read Accumulator and store in Port/BUS output register + if not clk_second_cycle_i and clk_mstate_i = MSTATE4 then + alu_read_alu_o <= true; + + if opc_opcode_q(4) = '1' then + if opc_opcode_q(1) = '0' then + p1_write_p1_o <= true; + else + p2_write_p2_o <= true; + end if; + + else + bus_write_bus_o <= true; + + end if; + + end if; + + -- Mnemonic RET --------------------------------------------------------- + when MN_RET => + if not clk_second_cycle_i then + case clk_mstate_i is + -- decrement Stack Pointer + when MSTATE3 => + psw_dec_stackp_o <= true; + + -- read Stack Pointer and address Data Memory for low byte + when MSTATE4 => + psw_read_sp_o <= true; + dm_write_dmem_addr_o <= true; + dm_addr_type_o <= DM_STACK; + + -- read Data Memory and store to Program Counter low + -- prepare address to Data memory for high byte + when MSTATE5 => + dm_read_dmem_o <= true; + pm_write_pcl_o <= true; + dm_write_dmem_addr_o <= true; + dm_addr_type_o <= DM_STACK_HIGH; + + when others => + null; + + end case; + + else + case clk_mstate_i is + -- read Data Memory and store to Program Counter high and PSW + when MSTATE1 => + dm_read_dmem_o <= true; + pm_write_pch_o <= true; + if opc_opcode_q(4) = '1' then + psw_write_psw_o <= true; + retr_executed_s <= true; + end if; + + when MSTATE2 => + add_write_pmem_addr_s <= true; + + when others => + null; + + end case; + + end if; + + -- Mnemonic RL ---------------------------------------------------------- + when MN_RL => + if clk_mstate_i = MSTATE3 then + alu_op_o <= ALU_RL; + alu_read_alu_o <= true; + alu_write_accu_o <= true; + + if opc_opcode_q(4) = '1' then + psw_special_data_o <= alu_carry_i; + psw_write_carry_o <= true; + alu_use_carry_o <= true; + end if; + end if; + + -- Mnemonic RR ---------------------------------------------------------- + when MN_RR => + if clk_mstate_i = MSTATE3 then + alu_op_o <= ALU_RR; + alu_read_alu_o <= true; + alu_write_accu_o <= true; + + if opc_opcode_q(4) = '0' then + psw_special_data_o <= alu_carry_i; + psw_write_carry_o <= true; + alu_use_carry_o <= true; + end if; + end if; + + -- Mnemonic SEL_MB ------------------------------------------------------ + when MN_SEL_MB => + if clk_mstate_i = MSTATE3 then + if opc_opcode_q(4) = '1' then + set_mb_s <= true; + else + clear_mb_s <= true; + end if; + end if; + + -- Mnemonic SEL_RB ------------------------------------------------------ + when MN_SEL_RB => + if clk_mstate_i = MSTATE3 then + psw_special_data_o <= opc_opcode_q(4); + psw_write_bs_o <= true; + end if; + + -- Mnemonic STOP_TCNT --------------------------------------------------- + when MN_STOP_TCNT => + if clk_mstate_i = MSTATE3 then + tim_stop_tcnt_o <= true; + end if; + + -- Mnemonic STRT -------------------------------------------------------- + when MN_STRT => + if clk_mstate_i = MSTATE3 then + if opc_opcode_q(4) = '1' then + tim_start_t_o <= true; + else + tim_start_cnt_o <= true; + end if; + end if; + + -- Mnemonic SWAP -------------------------------------------------------- + when MN_SWAP => + alu_op_o <= ALU_SWAP; + + if clk_mstate_i = MSTATE3 then + alu_read_alu_o <= true; + alu_write_accu_o <= true; + end if; + + -- Mnemonic XCH --------------------------------------------------------- + when MN_XCH => + case clk_mstate_i is + -- read RAM once for indirect address mode + when MSTATE3 => + if not enable_quartus_bugfix_c or + opc_opcode_q(3) = '0' then + address_indirect_3_f; + end if; + + -- store data from RAM in Accumulator and Temp Reg + -- Accumulator is already shadowed! + when MSTATE4 => + dm_read_dmem_o <= true; + alu_write_accu_o <= true; + alu_write_temp_reg_o <= true; + if opc_opcode_q(4) = '1' then + -- XCHD + -- only write lower nibble of Accumulator + alu_accu_low_o <= true; + end if; + + -- store data from shadow (previous) Accumulator to dmem + when MSTATE5 => + dm_write_dmem_s <= true; + alu_read_alu_o <= true; + if opc_opcode_q(4) = '1' then + -- XCHD + -- concatenate shadow Accumulator and Temp Reg + alu_op_o <= ALU_CONCAT; + end if; + + when others => + null; + + end case; + + -- Mnemonic XRL --------------------------------------------------------- + when MN_XRL => + case clk_mstate_i is + -- read RAM once for indirect address mode + when MSTATE3 => + if not enable_quartus_bugfix_c or + opc_opcode_q(3) = '0' then + address_indirect_3_f; + end if; + + -- store data from RAM to Temp Reg + when MSTATE4 => + and_or_xor_add_4_f; + + -- perform XOR and store in Accumulator + when MSTATE5 => + and_or_xor_add_5_f(alu_op => ALU_XOR); + + when others => + null; + + end case; + + -- Mnemonic XRL_A_DATA -------------------------------------------------- + when MN_XRL_A_DATA => + assert_psen_s <= true; + + if clk_second_cycle_i then + case clk_mstate_i is + -- write Temp Reg when contents of Program Memory is on bus + when MSTATE1 => + alu_write_temp_reg_o <= true; + + -- perform XOR and store in Accumulator + when MSTATE3 => + and_or_xor_add_5_f(alu_op => ALU_XOR); + + when others => + null; + + end case; + + end if; + + -- Unimplemented mnemonic ----------------------------------------------- + when others => + -- this will behave like a NOP + + -- pragma translate_off + assert false + report "Mnemonic not yet implemented." + severity warning; + -- pragma translate_on + + end case; + + end process decode; + -- + ----------------------------------------------------------------------------- + + + ----------------------------------------------------------------------------- + -- Process regs + -- + -- Purpose: + -- Implements the various registes. + -- + regs: process (res_i, clk_i) + begin + if res_i = res_active_c then + branch_taken_q <= false; + f1_q <= '0'; + mb_q <= '0'; + t0_dir_q <= '0'; + -- pragma translate_off + istrobe_res_q <= '1'; + istrobe_q <= '0'; + injected_int_q <= '0'; + -- pragma translate_on + + elsif clk_i'event and clk_i = clk_active_c then + -- UPI41 master access + if bus_set_f1_i then + f1_q <= '1'; + elsif bus_clear_f1_i then + f1_q <= '0'; + end if; + + if en_clk_i then + + -- branch taken flag + if branch_taken_s then + branch_taken_q <= true; + elsif clk_mstate_i = MSTATE5 then + -- release flag when new instruction starts + branch_taken_q <= false; + end if; + + -- Flag 1 + if clear_f1_s then + f1_q <= '0'; + elsif cpl_f1_s then + f1_q <= not f1_q; + end if; + + -- Memory Bank select + if clear_mb_s then + mb_q <= '0'; + elsif set_mb_s then + mb_q <= '1'; + end if; + + -- T0 direction selection + if ent0_clk_s then + t0_dir_q <= '1'; + end if; + + -- pragma translate_off + -- Marker for injected instruction ------------------------------------ + if opc_inj_int_s then + injected_int_q <= '1'; + elsif clk_mstate_i = MSTATE5 and last_cycle_s then + injected_int_q <= '0'; + end if; + + -- Remove istrobe after reset suppression ----------------------------- + if clk_mstate_i = MSTATE5 and last_cycle_s then + istrobe_res_q <= '0'; + end if; + -- pragma translate_on + + end if; + + -- pragma translate_off + -- Instruction Strobe --------------------------------------------------- + if clk_mstate_i = MSTATE5 and last_cycle_s and + injected_int_q = '0' then + if istrobe_res_q = '0' then + istrobe_q <= '1'; + end if; + else + istrobe_q <= '0'; + end if; + -- pragma translate_on + + end if; + + end process regs; + -- + ----------------------------------------------------------------------------- + + -- pragma translate_off + -- assign to global signal for testbench + tb_istrobe_s <= istrobe_q; + -- pragma translate_on + + + ----------------------------------------------------------------------------- + -- Output Mapping. + ----------------------------------------------------------------------------- + clk_multi_cycle_o <= opc_multi_cycle_s; + cnd_f1_o <= f1_q; + cnd_tf_o <= tf_s; + data_o <= data_s + when read_dec_s else + (others => bus_idle_level_c); + dm_write_dmem_o <= dm_write_dmem_s and en_clk_i; + pm_inc_pc_o <= pm_inc_pc_s or add_inc_pc_s; + pm_write_pmem_addr_o <= pm_write_pmem_addr_s or add_write_pmem_addr_s; + t0_dir_o <= t0_dir_q; + bus_read_bus_o <= bus_read_bus_s or add_read_bus_s; + +end rtl; diff --git a/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/t48/decoder_pack-p.vhd b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/t48/decoder_pack-p.vhd new file mode 100644 index 0000000000000000000000000000000000000000..250b135582e11851caed2266d057738b99c615f1 --- /dev/null +++ b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/t48/decoder_pack-p.vhd @@ -0,0 +1,576 @@ +------------------------------------------------------------------------------- +-- +-- $Id: decoder_pack-p.vhd 303 2022-12-16 19:56:46Z arniml $ +-- +-- Copyright (c) 2004, Arnim Laeuger (arniml@opencores.org) +-- +-- All rights reserved +-- +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; + +use work.t48_pack.word_t; + +package t48_decoder_pack is + + ----------------------------------------------------------------------------- + -- The Mnemonics. + ----------------------------------------------------------------------------- + type mnemonic_t is (MN_INVALID, + MN_ADD, + MN_ADD_A_DATA, + MN_ANL, + MN_ANL_A_DATA, + MN_ANL_EXT, + MN_CALL, + MN_CLR_A, + MN_CLR_C, + MN_CLR_F, + MN_CPL_A, + MN_CPL_C, + MN_CPL_F, + MN_DA, + MN_DEC, + MN_DIS_EN_I, + MN_DIS_EN_TCNTI, + MN_DJNZ, + MN_ENT0_CLK, + MN_IN, + MN_INC, + MN_INS, + MN_JBB, + MN_JC, + MN_JF, + MN_JMP, + MN_JMPP, + MN_JNI, + MN_JT, + MN_JTF, + MN_JZ, + MN_MOV_A_DATA, + MN_MOV_A_PSW, + MN_MOV_A_RR, + MN_MOV_PSW_A, + MN_MOV_RR, + MN_MOV_RR_DATA, + MN_MOV_T, + MN_MOVD_A_PP, + MN_MOVP, + MN_MOVX, + MN_NOP, + MN_ORL, + MN_ORL_A_DATA, + MN_ORL_EXT, + MN_OUTD_PP_A, + MN_OUTL_EXT, + MN_RET, + MN_RL, + MN_RR, + MN_SEL_MB, + MN_SEL_RB, + MN_STOP_TCNT, + MN_STRT, + MN_SWAP, + MN_XCH, + MN_XRL, + MN_XRL_A_DATA, + -- UPI41 opcodes + MN_IN_DBB, + MN_OUT_DBB, + MN_JNIBF, + MN_JOBF, + -- UPI41A opcodes + MN_EN_DMA_FLAGS, + MN_MOV_STS + ); + + type mnemonic_rec_t is + record + mnemonic : mnemonic_t; + multi_cycle : boolean; + end record; + + function decode_mcs48_opcode_f(opcode : in word_t) return + mnemonic_rec_t; + + function decode_upi41_opcode_f(opcode : in word_t) return + mnemonic_rec_t; + + function decode_upi41a_opcode_f(opcode : in word_t) return + mnemonic_rec_t; + +end t48_decoder_pack; + + +package body t48_decoder_pack is + + ----------------------------------------------------------------------------- + -- Common opcodes of MCS-48 and UPI-41/UPI-41A + -- + function decode_common_opcode_f(opcode : in word_t) return + mnemonic_rec_t is + variable mnemonic_v : mnemonic_t; + variable multi_cycle_v : boolean; + variable result_v : mnemonic_rec_t; + begin + -- default assignment + multi_cycle_v := false; + + case opcode is + -- Mnemonic ADD --------------------------------------------------------- + when "01101000" | "01101001" | "01101010" | "01101011" | -- ADD A, Rr + "01101100" | "01101101" | "01101110" | "01101111" | -- + "01100000" | "01100001" | -- ADD A, @ Rr + "01111000" | "01111001" | "01111010" | "01111011" | -- ADDC A, Rr + "01111100" | "01111101" | "01111110" | "01111111" | -- + "01110000" | "01110001" => -- ADDC A, @ Rr + mnemonic_v := MN_ADD; + + -- Mnemonic ADD_A_DATA -------------------------------------------------- + when "00000011" | -- ADD A, data + "00010011" => -- ADDC A, data + mnemonic_v := MN_ADD_A_DATA; + multi_cycle_v := true; + + -- Mnemonic ANL --------------------------------------------------------- + when "01011000" | "01011001" | "01011010" | "01011011" | -- ANL A, Rr + "01011100" | "01011101" | "01011110" | "01011111" | -- + "01010000" | "01010001" => -- ANL A, @ Rr + mnemonic_v := MN_ANL; + + -- Mnemonic ANL_A_DATA -------------------------------------------------- + when "01010011" => -- ANL A, data + mnemonic_v := MN_ANL_A_DATA; + multi_cycle_v := true; + + -- Mnemonic CALL -------------------------------------------------------- + when "00010100" | "00110100" | "01010100" | "01110100" | -- CALL addr + "10010100" | "10110100" | "11010100" | "11110100" => -- + mnemonic_v := MN_CALL; + multi_cycle_v := true; + + -- Mnemonic CLR_A ------------------------------------------------------- + when "00100111" => -- CLR A + mnemonic_v := MN_CLR_A; + + -- Mnemonic CLR_C ------------------------------------------------------- + when "10010111" => -- CLR C + mnemonic_v := MN_CLR_C; + + -- Mnemonic CLR_F ------------------------------------------------------- + when "10000101" | -- CLR F0 + "10100101" => + mnemonic_v := MN_CLR_F; + + -- Mnemonic CPL_A ------------------------------------------------------- + when "00110111" => -- CPL A + mnemonic_v := MN_CPL_A; + + -- Mnemonic CPL_C ------------------------------------------------------- + when "10100111" => -- CPL C + mnemonic_v := MN_CPL_C; + + -- Mnemonic CPL_F ------------------------------------------------------- + when "10010101" | -- CPL F0 + "10110101" => -- CPL F1 + mnemonic_v := MN_CPL_F; + + -- Mnemonic DA ---------------------------------------------------------- + when "01010111" => -- DA D + mnemonic_v := MN_DA; + + -- Mnemonic DEC --------------------------------------------------------- + when "11001000" | "11001001" | "11001010" | "11001011" | -- DEC Rr + "11001100" | "11001101" | "11001110" | "11001111" | -- + "00000111" => -- DEC A + mnemonic_v := MN_DEC; + + -- Mnemonic DIS_EN_I ---------------------------------------------------- + when "00010101" | -- DIS I + "00000101" => -- EN I + mnemonic_v := MN_DIS_EN_I; + + -- Mnemonic DIS_EN_TCNTI ------------------------------------------------ + when "00110101" | -- DIS TCNTI + "00100101" => -- EN TCNTI + mnemonic_v := MN_DIS_EN_TCNTI; + + -- Mnemonic DJNZ -------------------------------------------------------- + when "11101000" | "11101001" | "11101010" | "11101011" | -- DJNZ Rr, addr + "11101100" | "11101101" | "11101110" | "11101111" => -- + mnemonic_v := MN_DJNZ; + multi_cycle_v := true; + + -- Mnemonic IN ---------------------------------------------------------- + when "00001001" | "00001010" => -- IN A, Pp + mnemonic_v := MN_IN; + multi_cycle_v := true; + + -- Mnemonic INC --------------------------------------------------------- + when "00010111" | -- INC A + "00011000" | "00011001" | "00011010" | "00011011" | -- INC Rr + "00011100" | "00011101" | "00011110" | "00011111" | -- + "00010000" | "00010001" => -- INC @ Rr + mnemonic_v := MN_INC; + + -- Mnemonic JBB --------------------------------------------------------- + when "00010010" | "00110010" | "01010010" | "01110010" | -- JBb addr + "10010010" | "10110010" | "11010010" | "11110010" => -- + mnemonic_v := MN_JBB; + multi_cycle_v := true; + + -- Mnemonic JC ---------------------------------------------------------- + when "11110110" | -- JC addr + "11100110" => -- JNC addr + mnemonic_v := MN_JC; + multi_cycle_v := true; + + -- Mnemonic JF ---------------------------------------------------------- + when "10110110" | -- JF0 addr + "01110110" => -- JF1 addr + mnemonic_v := MN_JF; + multi_cycle_v := true; + + -- Mnemonic JMP --------------------------------------------------------- + when "00000100" | "00100100" | "01000100" | "01100100" | -- JMP addr + "10000100" | "10100100" | "11000100" | "11100100" => -- + mnemonic_v := MN_JMP; + multi_cycle_v := true; + + -- Mnemonic JMPP -------------------------------------------------------- + when "10110011" => -- JMPP @ A + mnemonic_v := MN_JMPP; + multi_cycle_v := true; + + -- Mnemonic JT ---------------------------------------------------------- + when "00100110" | -- JNT0 addr + "01000110" | -- JNT1 addr + "00110110" | -- JT0 addr + "01010110" => -- JT1 addr + mnemonic_v := MN_JT; + multi_cycle_v := true; + + -- Mnemonic JTF --------------------------------------------------------- + when "00010110" => -- JTF addr + mnemonic_v := MN_JTF; + multi_cycle_v := true; + + -- Mnemonic JZ ---------------------------------------------------------- + when "10010110" | -- JNZ addr + "11000110" => -- JZ addr + mnemonic_v := MN_JZ; + multi_cycle_v := true; + + -- Mnemonic MOV_A_DATA -------------------------------------------------- + when "00100011" => -- MOV A, data + mnemonic_v := MN_MOV_A_DATA; + multi_cycle_v := true; + + -- Mnemonic MOV_A_PSW --------------------------------------------------- + when "11000111" => -- MOV A, PSW + mnemonic_v := MN_MOV_A_PSW; + + -- Mnemonic MOV_A_RR ---------------------------------------------------- + when "11111000" | "11111001" | "11111010" | "11111011" | -- MOV A, Rr + "11111100" | "11111101" | "11111110" | "11111111" | -- + "11110000" | "11110001" => -- MOV A, @ Rr + mnemonic_v := MN_MOV_A_RR; + + -- Mnemonic MOV_PSW_A --------------------------------------------------- + when "11010111" => -- MOV PSW, A + mnemonic_v := MN_MOV_PSW_A; + + -- Mnemonic MOV_RR ------------------------------------------------------ + when "10101000" | "10101001" | "10101010" | "10101011" | -- MOV Rr, A + "10101100" | "10101101" | "10101110" | "10101111" | -- + "10100000" | "10100001" => -- MOV @ Rr, A + mnemonic_v := MN_MOV_RR; + + -- Mnemonic MOV_RR_DATA ------------------------------------------------- + when "10111000" | "10111001" | "10111010" | "10111011" | -- MOV Rr, data + "10111100" | "10111101" | "10111110" | "10111111" | -- + "10110000" | "10110001" => -- MOV @ Rr, data + mnemonic_v := MN_MOV_RR_DATA; + multi_cycle_v := true; + + -- Mnemonic MOV_T ------------------------------------------------------- + when "01100010" | -- MOV T, A + "01000010" => -- MOV A, T + mnemonic_v := MN_MOV_T; + + -- Mnemonic MOVD_A_PP --------------------------------------------------- + when "00001100" | "00001101" | "00001110" | "00001111" => -- MOVD A, Pp + mnemonic_v := MN_MOVD_A_PP; + multi_cycle_v := true; + + -- Mnemonic MOVP -------------------------------------------------------- + when "10100011" | -- MOVP A, @ A + "11100011" => -- MOVP3 A, @ A + mnemonic_v := MN_MOVP; + multi_cycle_v := true; + + -- Mnemonic NOP --------------------------------------------------------- + when "00000000" => -- NOP + mnemonic_v := MN_NOP; + + -- Mnemonic ORL --------------------------------------------------------- + when "01001000" | "01001001" | "01001010" | "01001011" | -- ORL A, Rr + "01001100" | "01001101" | "01001110" | "01001111" | -- + "01000000" | "01000001" => -- ORL A, @ Rr + mnemonic_v := MN_ORL; + + -- Mnemonic ORL_A_DATA -------------------------------------------------- + when "01000011" => -- ORL A, data + mnemonic_v := MN_ORL_A_DATA; + multi_cycle_v := true; + + -- Mnemonic OUTD_PP_A --------------------------------------------------- + when "00111100" | "00111101" | "00111110" | "00111111" | -- MOVD Pp, A + "10011100" | "10011101" | "10011110" | "10011111" | -- ANLD PP, A + "10001100" | "10001101" | "10001110" | "10001111" => -- ORLD Pp, A + mnemonic_v := MN_OUTD_PP_A; + multi_cycle_v := true; + + -- Mnemonic RET --------------------------------------------------------- + when "10000011" | -- RET + "10010011" => -- RETR + mnemonic_v := MN_RET; + multi_cycle_v := true; + + -- Mnemonic RL ---------------------------------------------------------- + when "11100111" | -- RL A + "11110111" => -- RLC A + mnemonic_v := MN_RL; + + -- Mnemonic RR ---------------------------------------------------------- + when "01110111" | -- RR A + "01100111" => -- RRC A + mnemonic_v := MN_RR; + + -- Mnemonic SEL_RB ------------------------------------------------------ + when "11000101" | -- SEL RB0 + "11010101" => -- SEL RB1 + mnemonic_v := MN_SEL_RB; + + -- Mnemonic STOP_TCNT --------------------------------------------------- + when "01100101" => -- STOP TCNT + mnemonic_v := MN_STOP_TCNT; + + -- Mnemonic START ------------------------------------------------------- + when "01000101" | -- STRT CNT + "01010101" => -- STRT T + mnemonic_v := MN_STRT; + + -- Mnemonic SWAP -------------------------------------------------------- + when "01000111" => -- SWAP A + mnemonic_v := MN_SWAP; + + -- Mnemonic XCH --------------------------------------------------------- + when "00101000" | "00101001" | "00101010" | "00101011" | -- XCH A, Rr + "00101100" | "00101101" | "00101110" | "00101111" | -- + "00100000" | "00100001" | -- XCH A, @ Rr + "00110000" | "00110001" => -- XCHD A, @ Rr + mnemonic_v := MN_XCH; + + -- Mnemonic XRL --------------------------------------------------------- + when "11011000" | "11011001" | "11011010" | "11011011" | -- XRL A, Rr + "11011100" | "11011101" | "11011110" | "11011111" | -- + "11010000" | "11010001" => -- XRL A, @ Rr + mnemonic_v := MN_XRL; + + -- Mnemonic XRL_A_DATA -------------------------------------------------- + when "11010011" => -- XRL A, data + mnemonic_v := MN_XRL_A_DATA; + multi_cycle_v := true; + + when others => + mnemonic_v := MN_NOP; + -- pragma translate_off + assert false + report "Unknown opcode." + severity warning; + -- pragma translate_on + + end case; + + result_v.mnemonic := mnemonic_v; + result_v.multi_cycle := multi_cycle_v; + + return result_v; + end; + + + ----------------------------------------------------------------------------- + -- Specific MCS-48 opcodes + -- + function decode_mcs48_opcode_f(opcode : in word_t) return + mnemonic_rec_t is + variable mnemonic_v : mnemonic_t; + variable multi_cycle_v : boolean; + variable result_v : mnemonic_rec_t; + begin + -- default assignment + multi_cycle_v := false; + + case opcode is + -- Mnemonic ANL_EXT ----------------------------------------------------- + when "10011000" | -- ANL BUS, data + "10011001" | "10011010" => -- ANL PP, data + mnemonic_v := MN_ANL_EXT; + multi_cycle_v := true; + + -- Mnemonic ENT0_CLK ---------------------------------------------------- + when "01110101" => -- ENT0 CLK + mnemonic_v := MN_ENT0_CLK; + + -- Mnemonic INS --------------------------------------------------------- + when "00001000" => -- INS A, BUS + mnemonic_v := MN_INS; + multi_cycle_v := true; + + -- Mnemonic JNI --------------------------------------------------------- + when "10000110" => -- JNI addr + mnemonic_v := MN_JNI; + multi_cycle_v := true; + + -- Mnemonic MOVX -------------------------------------------------------- + when "10000000" | "10000001" | -- MOVX A, @ Rr + "10010000" | "10010001" => -- MOVX @ Rr, A + mnemonic_v := MN_MOVX; + multi_cycle_v := true; + + -- Mnemonic ORL_EXT ----------------------------------------------------- + when "10001000" | -- ORL BUS, data + "10001001" | "10001010" => -- ORL Pp, data + mnemonic_v := MN_ORL_EXT; + multi_cycle_v := true; + + -- Mnemonic OUTL_EXT ---------------------------------------------------- + when "00111001" | "00111010" | -- OUTL Pp, A + "00000010" => -- OUTL BUS, A + mnemonic_v := MN_OUTL_EXT; + multi_cycle_v := true; + + -- Mnemonic SEL_MB ------------------------------------------------------ + when "11100101" | -- SEL MB0 + "11110101" => -- SEL MB1 + mnemonic_v := MN_SEL_MB; + + when others => + mnemonic_v := MN_INVALID; + + end case; + + if mnemonic_v = MN_INVALID then + result_v := decode_common_opcode_f(opcode); + else + result_v.mnemonic := mnemonic_v; + result_v.multi_cycle := multi_cycle_v; + end if; + + return result_v; + end; + + + ----------------------------------------------------------------------------- + -- Specific UPI-41 opcodes + -- + function decode_upi41_opcode_f(opcode : in word_t) return + mnemonic_rec_t is + variable mnemonic_v : mnemonic_t; + variable multi_cycle_v : boolean; + variable result_v : mnemonic_rec_t; + begin + -- default assignment + multi_cycle_v := false; + + case opcode is + -- Mnemonic ANL_EXT ----------------------------------------------------- + when "10011001" | "10011010" => -- ANL PP, data + mnemonic_v := MN_ANL_EXT; + multi_cycle_v := true; + + -- Mnemonic IN_DBB ------------------------------------------------------ + when "00100010" => -- IN A, DBB + mnemonic_v := MN_IN_DBB; + + -- Mnemonic JNIBF ------------------------------------------------------- + when "11010110" => -- JNIBF addr + mnemonic_v := MN_JNIBF; + multi_cycle_v := true; + + -- Mnemonic JOBF -------------------------------------------------------- + when "10000110" => -- JOBF addr + mnemonic_v := MN_JOBF; + multi_cycle_v := true; + + -- Mnemonic ORL_EXT ----------------------------------------------------- + when "10001001" | "10001010" => -- ORL Pp, data + mnemonic_v := MN_ORL_EXT; + multi_cycle_v := true; + + -- Mnemonic OUT_DBB ----------------------------------------------------- + when "00000010" => -- OUT DBB, A + mnemonic_v := MN_OUT_DBB; + + -- Mnemonic OUTL_EXT ---------------------------------------------------- + when "00111001" | "00111010" => -- OUTL Pp, A + mnemonic_v := MN_OUTL_EXT; + multi_cycle_v := true; + + when others => + mnemonic_v := MN_INVALID; + + end case; + + if mnemonic_v = MN_INVALID then + result_v := decode_common_opcode_f(opcode); + else + result_v.mnemonic := mnemonic_v; + result_v.multi_cycle := multi_cycle_v; + end if; + + return result_v; + end; + + + ----------------------------------------------------------------------------- + -- Specific UPI-41A opcodes + -- + function decode_upi41a_opcode_f(opcode : in word_t) return + mnemonic_rec_t is + variable mnemonic_v : mnemonic_t; + variable multi_cycle_v : boolean; + variable result_v : mnemonic_rec_t; + begin + -- default assignment + multi_cycle_v := false; + + case opcode is + -- Mnemonic EN_DMA_FLAGS ------------------------------------------------ + when "11100101" | -- EN DMA + "11110101" => -- EN FLAGS + mnemonic_v := MN_EN_DMA_FLAGS; + + -- Mnemonic MOV_STS ----------------------------------------------------- + when "10010000" => -- MOV STS, A + mnemonic_v := MN_MOV_STS; + + when others => + mnemonic_v := MN_INVALID; + + end case; + + if mnemonic_v = MN_INVALID then + result_v := decode_upi41_opcode_f(opcode); + else + result_v.mnemonic := mnemonic_v; + result_v.multi_cycle := multi_cycle_v; + end if; + + return result_v; + end; + +end t48_decoder_pack; diff --git a/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/t48/dmem_ctrl-c.vhd b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/t48/dmem_ctrl-c.vhd new file mode 100644 index 0000000000000000000000000000000000000000..98535433dd7665b36d56ab38f0f8e13334d6bb5a --- /dev/null +++ b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/t48/dmem_ctrl-c.vhd @@ -0,0 +1,19 @@ +------------------------------------------------------------------------------- +-- +-- The Data Memory control unit. +-- All accesses to the Data Memory are managed here. +-- +-- $Id: dmem_ctrl-c.vhd 295 2009-04-01 19:32:48Z arniml $ +-- +-- Copyright (c) 2004, Arnim Laeuger (arniml@opencores.org) +-- +-- All rights reserved +-- +------------------------------------------------------------------------------- + +configuration t48_dmem_ctrl_rtl_c0 of t48_dmem_ctrl is + + for rtl + end for; + +end t48_dmem_ctrl_rtl_c0; diff --git a/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/t48/dmem_ctrl.vhd b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/t48/dmem_ctrl.vhd new file mode 100644 index 0000000000000000000000000000000000000000..e682de44a2c445b46ec931f53b6dc16d6f5c445e --- /dev/null +++ b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/t48/dmem_ctrl.vhd @@ -0,0 +1,202 @@ +------------------------------------------------------------------------------- +-- +-- The Data Memory control unit. +-- All accesses to the Data Memory are managed here. +-- +-- $Id: dmem_ctrl.vhd 295 2009-04-01 19:32:48Z arniml $ +-- +-- Copyright (c) 2004, Arnim Laeuger (arniml@opencores.org) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.opencores.org/cvsweb.shtml/t48/ +-- +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; + +use work.t48_pack.dmem_addr_t; +use work.t48_pack.word_t; +use work.t48_dmem_ctrl_pack.dmem_addr_ident_t; + +entity t48_dmem_ctrl is + + port ( + -- Global Interface ------------------------------------------------------- + clk_i : in std_logic; + res_i : in std_logic; + en_clk_i : in boolean; + -- Control Interface ------------------------------------------------------ + data_i : in word_t; + write_dmem_addr_i : in boolean; + write_dmem_i : in boolean; + read_dmem_i : in boolean; + addr_type_i : in dmem_addr_ident_t; + bank_select_i : in std_logic; + data_o : out word_t; + -- Data Memory Interface -------------------------------------------------- + dmem_data_i : in word_t; + dmem_addr_o : out dmem_addr_t; + dmem_we_o : out std_logic; + dmem_data_o : out word_t + ); + +end t48_dmem_ctrl; + + +library ieee; +use ieee.numeric_std.all; + +use work.t48_pack.clk_active_c; +use work.t48_pack.res_active_c; +use work.t48_pack.bus_idle_level_c; +use work.t48_pack.to_stdLogic; + +use work.t48_dmem_ctrl_pack.all; + +architecture rtl of t48_dmem_ctrl is + + signal dmem_addr_s, + dmem_addr_q : dmem_addr_t; +begin + + ----------------------------------------------------------------------------- + -- Process addr_decode + -- + -- Purpose: + -- Decode/multiplex the address information for the Data Memory. + -- + addr_decode: process (data_i, + addr_type_i, + bank_select_i, + dmem_addr_q) + variable stack_addr_v : unsigned(5 downto 0); + begin + -- default assignment + dmem_addr_s <= dmem_addr_q; + stack_addr_v := (others => '0'); + + case addr_type_i is + when DM_PLAIN => + dmem_addr_s <= data_i; + + when DM_REG => + dmem_addr_s <= (others => '0'); + dmem_addr_s(2 downto 0) <= data_i(2 downto 0); + -- implement bank switching + if bank_select_i = '1' then + -- dmem address 24 - 31: access proper set + dmem_addr_s(4 downto 3) <= "11"; + end if; + + when DM_STACK => + -- build address from stack pointer + stack_addr_v(3 downto 1) := unsigned(data_i(2 downto 0)); + -- dmem address 8 - 23 + stack_addr_v := stack_addr_v + 8; + + dmem_addr_s <= (others => '0'); + dmem_addr_s(5 downto 0) <= std_logic_vector(stack_addr_v); + + when DM_STACK_HIGH => + dmem_addr_s(0) <= '1'; + + when others => + -- do nothing + + -- pragma translate_off + assert false + report "Unknown address type identification for Data Memory controller!" + severity error; + -- pragma translate_on + + end case; + + end process addr_decode; + -- + ----------------------------------------------------------------------------- + + + ----------------------------------------------------------------------------- + -- Process dmem_addr_reg + -- + -- Purpose: + -- Implements the Data Memory Address Register. + -- This register is required to hold the address during a write operation + -- as we cannot hold the address in the input register of the + -- synchronous RAM (no clock suppression/gating). + -- + -- NOTE: May be obsoleted by clock enable feature of generic RTL RAM. + -- + dmem_addr_reg: process (res_i, clk_i) + begin + if res_i = res_active_c then + dmem_addr_q <= (others => '0'); + + elsif clk_i'event and clk_i = clk_active_c then + if en_clk_i then + + if write_dmem_addr_i then + dmem_addr_q <= dmem_addr_s; + end if; + + end if; + + end if; + + end process dmem_addr_reg; + -- + ----------------------------------------------------------------------------- + + + ----------------------------------------------------------------------------- + -- Output mapping. + ----------------------------------------------------------------------------- + dmem_addr_o <= dmem_addr_s + when write_dmem_addr_i and en_clk_i else + dmem_addr_q; + + -- data from bus is fed through + dmem_data_o <= data_i; + + -- data to bus is enabled upon read request + data_o <= dmem_data_i + when read_dmem_i else + (others => bus_idle_level_c); + + -- write enable to Data Memory is fed through + dmem_we_o <= to_stdLogic(write_dmem_i); + +end rtl; diff --git a/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/t48/dmem_ctrl_pack-p.vhd b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/t48/dmem_ctrl_pack-p.vhd new file mode 100644 index 0000000000000000000000000000000000000000..64f04b15503e274a251c8ef944e2dbe1f106319d --- /dev/null +++ b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/t48/dmem_ctrl_pack-p.vhd @@ -0,0 +1,21 @@ +------------------------------------------------------------------------------- +-- +-- $Id: dmem_ctrl_pack-p.vhd 295 2009-04-01 19:32:48Z arniml $ +-- +-- Copyright (c) 2004, Arnim Laeuger (arniml@opencores.org) +-- +-- All rights reserved +-- +------------------------------------------------------------------------------- + +package t48_dmem_ctrl_pack is + + ----------------------------------------------------------------------------- + -- Address Type Identifier + ----------------------------------------------------------------------------- + type dmem_addr_ident_t is (DM_PLAIN, + DM_REG, + DM_STACK, + DM_STACK_HIGH); + +end t48_dmem_ctrl_pack; diff --git a/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/t48/int-c.vhd b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/t48/int-c.vhd new file mode 100644 index 0000000000000000000000000000000000000000..d6e707ca84aaaf68657f5537c3b9c34a9ec0708a --- /dev/null +++ b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/t48/int-c.vhd @@ -0,0 +1,17 @@ +------------------------------------------------------------------------------- +-- +-- The Interrupt Controller. +-- It collects the interrupt sources and notifies the decoder. +-- +-- $Id: int-c.vhd 295 2009-04-01 19:32:48Z arniml $ +-- +-- All rights reserved +-- +------------------------------------------------------------------------------- + +configuration t48_int_rtl_c0 of t48_int is + + for rtl + end for; + +end t48_int_rtl_c0; diff --git a/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/t48/int.vhd b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/t48/int.vhd new file mode 100644 index 0000000000000000000000000000000000000000..3b180892e3292da477ed6b3664aefe9534ef2b84 --- /dev/null +++ b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/t48/int.vhd @@ -0,0 +1,253 @@ +------------------------------------------------------------------------------- +-- +-- The Interrupt Controller. +-- It collects the interrupt sources and notifies the decoder. +-- +-- $Id: int.vhd 295 2009-04-01 19:32:48Z arniml $ +-- +-- Copyright (c) 2004, Arnim Laeuger (arniml@opencores.org) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.opencores.org/cvsweb.shtml/t48/ +-- +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; + +use work.t48_pack.mstate_t; + +entity t48_int is + + port ( + clk_i : in std_logic; + res_i : in std_logic; + en_clk_i : in boolean; + xtal_i : in std_logic; + xtal_en_i : in boolean; + clk_mstate_i : in mstate_t; + jtf_executed_i : in boolean; + tim_overflow_i : in boolean; + tf_o : out std_logic; + en_tcnti_i : in boolean; + dis_tcnti_i : in boolean; + int_n_i : in std_logic; + ale_i : in boolean; + last_cycle_i : in boolean; + en_i_i : in boolean; + dis_i_i : in boolean; + ext_int_o : out boolean; + tim_int_o : out boolean; + retr_executed_i : in boolean; + int_executed_i : in boolean; + int_pending_o : out boolean; + int_in_progress_o : out boolean + ); + +end t48_int; + + +use work.t48_pack.all; + +architecture rtl of t48_int is + + constant tim_int_c : std_logic := '0'; + constant ext_int_c : std_logic := '1'; + + type int_state_t is (IDLE, PENDING, INT); + + signal int_state_s, + int_state_q : int_state_t; + + signal timer_flag_q : boolean; + signal timer_overflow_q : boolean; + signal timer_int_enable_q : boolean; + signal int_q : boolean; + signal int_enable_q : boolean; + signal ale_q : boolean; + signal int_type_q : std_logic; + signal int_in_progress_q : boolean; + +begin + + ----------------------------------------------------------------------------- + -- Process nstate + -- + -- Purpose: + -- Determines the next state of the Interrupt controller FSM. + -- + nstate: process (int_state_q, + int_type_q, + int_in_progress_q, + int_executed_i, + retr_executed_i, + clk_mstate_i, + last_cycle_i) + begin + int_state_s <= int_state_q; + + case int_state_q is + when IDLE => + if int_in_progress_q and + last_cycle_i and clk_mstate_i = MSTATE5 then + int_state_s <= PENDING; + end if; + + when PENDING => + if int_executed_i then + int_state_s <= INT; + end if; + + when INT => + if retr_executed_i then + int_state_s <= IDLE; + end if; + + when others => + int_state_s <= IDLE; + + end case; + + end process nstate; + -- + ----------------------------------------------------------------------------- + + + ----------------------------------------------------------------------------- + -- Process regs + -- + -- Purpose: + -- Implement the various registers. + -- They are designed according Figure "Interrupt Logic" of + -- "The Single Component MCS-48 System". + -- + regs: process (res_i, clk_i) + begin + if res_i = res_active_c then + timer_flag_q <= false; + timer_overflow_q <= false; + timer_int_enable_q <= false; + int_enable_q <= false; + int_type_q <= '0'; + int_state_q <= IDLE; + int_in_progress_q <= false; + + elsif clk_i'event and clk_i = clk_active_c then + if en_clk_i then + + int_state_q <= int_state_s; + + if jtf_executed_i then + timer_flag_q <= false; + elsif tim_overflow_i then + timer_flag_q <= true; + end if; + + if (int_type_q = tim_int_c and int_executed_i) or + not timer_int_enable_q then + timer_overflow_q <= false; + elsif tim_overflow_i then + timer_overflow_q <= true; + end if; + + if dis_tcnti_i then + timer_int_enable_q <= false; + elsif en_tcnti_i then + timer_int_enable_q <= true; + end if; + + if dis_i_i then + int_enable_q <= false; + elsif en_i_i then + int_enable_q <= true; + end if; + + if retr_executed_i then + int_in_progress_q <= false; + elsif (int_q and int_enable_q) or + timer_overflow_q then + int_in_progress_q <= true; + if not int_in_progress_q then + int_type_q <= to_stdLogic(int_q and int_enable_q); + end if; + end if; + + end if; + + end if; + + end process regs; + -- + ----------------------------------------------------------------------------- + + + ----------------------------------------------------------------------------- + -- Process xtal_regs + -- + -- Purpose: + -- Implements the sequential registers clocked with XTAL. + -- + xtal_regs: process (res_i, xtal_i) + begin + if res_i = res_active_c then + int_q <= false; + ale_q <= false; + + elsif xtal_i'event and xtal_i = clk_active_c then + if xtal_en_i then + ale_q <= ale_i; + + if last_cycle_i and + ale_q and not ale_i then + int_q <= not to_boolean(int_n_i); + end if; + + end if; + end if; + end process xtal_regs; + -- + ----------------------------------------------------------------------------- + + + ----------------------------------------------------------------------------- + -- Output Mapping. + ----------------------------------------------------------------------------- + tf_o <= to_stdLogic(timer_flag_q); + ext_int_o <= int_type_q = ext_int_c; + tim_int_o <= int_type_q = tim_int_c; + int_pending_o <= int_state_q = PENDING; + int_in_progress_o <= int_in_progress_q and int_state_q /= IDLE; + +end rtl; diff --git a/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/t48/p1-c.vhd b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/t48/p1-c.vhd new file mode 100644 index 0000000000000000000000000000000000000000..67617a5b2ebe1239a8b5727a97e9487f4a9cb232 --- /dev/null +++ b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/t48/p1-c.vhd @@ -0,0 +1,17 @@ +------------------------------------------------------------------------------- +-- +-- The Port 1 unit. +-- Implements the Port 1 logic. +-- +-- $Id: p1-c.vhd 295 2009-04-01 19:32:48Z arniml $ +-- +-- All rights reserved +-- +------------------------------------------------------------------------------- + +configuration t48_p1_rtl_c0 of t48_p1 is + + for rtl + end for; + +end t48_p1_rtl_c0; diff --git a/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/t48/p1.vhd b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/t48/p1.vhd new file mode 100644 index 0000000000000000000000000000000000000000..a5fdb050dd008d5455728bee75fa410b2dbc3c0b --- /dev/null +++ b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/t48/p1.vhd @@ -0,0 +1,151 @@ +------------------------------------------------------------------------------- +-- +-- The Port 1 unit. +-- Implements the Port 1 logic. +-- +-- $Id: p1.vhd 295 2009-04-01 19:32:48Z arniml $ +-- +-- Copyright (c) 2004, Arnim Laeuger (arniml@opencores.org) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.opencores.org/cvsweb.shtml/t48/ +-- +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; + +use work.t48_pack.word_t; + +entity t48_p1 is + + port ( + -- Global Interface ------------------------------------------------------- + clk_i : in std_logic; + res_i : in std_logic; + en_clk_i : in boolean; + -- T48 Bus Interface ------------------------------------------------------ + data_i : in word_t; + data_o : out word_t; + write_p1_i : in boolean; + read_p1_i : in boolean; + read_reg_i : in boolean; + -- Port 1 Interface ------------------------------------------------------- + p1_i : in word_t; + p1_o : out word_t; + p1_low_imp_o : out std_logic + ); + +end t48_p1; + + +use work.t48_pack.clk_active_c; +use work.t48_pack.res_active_c; +use work.t48_pack.bus_idle_level_c; + +architecture rtl of t48_p1 is + + -- the port output register + signal p1_q : word_t; + + -- the low impedance marker + signal low_imp_q : std_logic; + +begin + + ----------------------------------------------------------------------------- + -- Process p1_reg + -- + -- Purpose: + -- Implements the port output register. + -- + p1_reg: process (res_i, clk_i) + begin + if res_i = res_active_c then + p1_q <= (others => '1'); + low_imp_q <= '0'; + + elsif clk_i'event and clk_i = clk_active_c then + if en_clk_i then + + if write_p1_i then + p1_q <= data_i; + low_imp_q <= '1'; + else + low_imp_q <= '0'; + end if; + + end if; + + end if; + + end process p1_reg; + -- + ----------------------------------------------------------------------------- + + + ----------------------------------------------------------------------------- + -- Process p1_data + -- + -- Purpose: + -- Generates the T48 bus data. + -- + p1_data: process (read_p1_i, + p1_i, + read_reg_i, + p1_q) + begin + data_o <= (others => bus_idle_level_c); + + if read_p1_i then + if read_reg_i then + data_o <= p1_q; + else + data_o <= p1_i; + end if; + end if; + + end process p1_data; + -- + ----------------------------------------------------------------------------- + + + ----------------------------------------------------------------------------- + -- Output Mapping. + ----------------------------------------------------------------------------- + p1_o <= p1_q; + p1_low_imp_o <= low_imp_q; + +end rtl; diff --git a/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/t48/p2-c.vhd b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/t48/p2-c.vhd new file mode 100644 index 0000000000000000000000000000000000000000..afce43651b05a61bec33bd2a3f0759a84b10ae35 --- /dev/null +++ b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/t48/p2-c.vhd @@ -0,0 +1,17 @@ +------------------------------------------------------------------------------- +-- +-- The Port 2 unit. +-- Implements the Port 2 logic. +-- +-- $Id: p2-c.vhd 295 2009-04-01 19:32:48Z arniml $ +-- +-- All rights reserved +-- +------------------------------------------------------------------------------- + +configuration t48_p2_rtl_c0 of t48_p2 is + + for rtl + end for; + +end t48_p2_rtl_c0; diff --git a/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/t48/p2.vhd b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/t48/p2.vhd new file mode 100644 index 0000000000000000000000000000000000000000..db942602d0d5715b27c335f57d0e29ff8f69cfec --- /dev/null +++ b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/t48/p2.vhd @@ -0,0 +1,238 @@ +------------------------------------------------------------------------------- +-- +-- The Port 2 unit. +-- Implements the Port 2 logic. +-- +-- $Id: p2.vhd 295 2009-04-01 19:32:48Z arniml $ +-- +-- Copyright (c) 2004, Arnim Laeuger (arniml@opencores.org) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.opencores.org/cvsweb.shtml/t48/ +-- +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; + +use work.t48_pack.word_t; +use work.t48_pack.nibble_t; + +entity t48_p2 is + + port ( + -- Global Interface ------------------------------------------------------- + clk_i : in std_logic; + res_i : in std_logic; + en_clk_i : in boolean; + xtal_i : in std_logic; + xtal_en_i : in boolean; + -- T48 Bus Interface ------------------------------------------------------ + data_i : in word_t; + data_o : out word_t; + write_p2_i : in boolean; + write_exp_i : in boolean; + read_p2_i : in boolean; + read_reg_i : in boolean; + read_exp_i : in boolean; + -- Port 2 Interface ------------------------------------------------------- + output_pch_i : in boolean; + pch_i : in nibble_t; + p2_i : in word_t; + p2_o : out word_t; + p2l_low_imp_o : out std_logic; + p2h_low_imp_o : out std_logic + ); + +end t48_p2; + + +use work.t48_pack.clk_active_c; +use work.t48_pack.res_active_c; +use work.t48_pack.bus_idle_level_c; + +architecture rtl of t48_p2 is + + -- the port output register + signal p2_q : word_t; + + -- the low impedance markers + signal l_low_imp_q, + h_low_imp_q : std_logic; + + signal en_clk_q : boolean; + signal l_low_imp_del_q, + h_low_imp_del_q : std_logic; + signal output_pch_q : boolean; + +begin + + ----------------------------------------------------------------------------- + -- Process p2_regs + -- + -- Purpose: + -- Implements the port output and expander registers. + -- + p2_regs: process (res_i, clk_i) + begin + if res_i = res_active_c then + p2_q <= (others => '1'); + l_low_imp_q <= '0'; + h_low_imp_q <= '0'; + + elsif clk_i'event and clk_i = clk_active_c then + if en_clk_i then + -- default: reset low impedance marker + l_low_imp_q <= '0'; + h_low_imp_q <= '0'; + + if write_p2_i then + -- write whole P2 + p2_q <= data_i; + l_low_imp_q <= '1'; + h_low_imp_q <= '1'; + + elsif write_exp_i then + -- write lower nibble of P2 + p2_q(nibble_t'range) <= data_i(nibble_t'range); + l_low_imp_q <= '1'; + + end if; + + end if; + + end if; + + end process p2_regs; + -- + ----------------------------------------------------------------------------- + + + ----------------------------------------------------------------------------- + -- Process p2_port + -- + -- Purpose: + -- Generates the output byte vector for Port 2. + -- It is a synchronous process clocked with XTAL. This ensures that + -- P2 data and low impedance markers are free of glitches and stabilize + -- during the same clock/machine state. + -- On the other hand, P2 is delayed by 1 XTAL cycle. + -- + p2_port: process (res_i, xtal_i) + begin + if res_i = res_active_c then + p2_o <= (others => '1'); + l_low_imp_del_q <= '0'; + h_low_imp_del_q <= '0'; + output_pch_q <= false; + en_clk_q <= false; + + elsif xtal_i'event and xtal_i = clk_active_c then + if xtal_en_i then + -- delay clock enable by one XTAL period + en_clk_q <= en_clk_i; + + p2_o <= p2_q; + output_pch_q <= output_pch_i; + + if output_pch_i then + p2_o(nibble_t'range) <= pch_i; + end if; + + -- generate low impedance trigger for one XTAL clock period after + -- global clock enable when + -- a) switching to or from PCH + -- b) l_low_imp_q is active + if en_clk_q and + ((output_pch_q xor output_pch_i) or + l_low_imp_q = '1') then + l_low_imp_del_q <= '1'; + else + l_low_imp_del_q <= '0'; + end if; + + -- generate low impedance trigger for on XTAL clock period after + -- global clock enable when + -- h_low_imp_q is active + if en_clk_q and + h_low_imp_q = '1' then + h_low_imp_del_q <= '1'; + else + h_low_imp_del_q <= '0'; + end if; + + end if; + end if; + end process p2_port; + -- + ----------------------------------------------------------------------------- + + + ----------------------------------------------------------------------------- + -- Process p2_data + -- + -- Purpose: + -- Generates the T48 bus data. + -- + p2_data: process (read_p2_i, + p2_i, + read_reg_i, + p2_q, + read_exp_i) + begin + data_o <= (others => bus_idle_level_c); + + if read_p2_i then + if read_reg_i then + data_o <= p2_q; + elsif read_exp_i then + data_o <= "0000" & p2_i(nibble_t'range); + else + data_o <= p2_i; + end if; + end if; + + end process p2_data; + -- + ----------------------------------------------------------------------------- + + + ----------------------------------------------------------------------------- + -- Output Mapping. + ----------------------------------------------------------------------------- + p2l_low_imp_o <= l_low_imp_del_q; + p2h_low_imp_o <= h_low_imp_del_q; + +end rtl; diff --git a/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/t48/pmem_ctrl-c.vhd b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/t48/pmem_ctrl-c.vhd new file mode 100644 index 0000000000000000000000000000000000000000..06c9b981001e1da36a474f63d17126c48756b070 --- /dev/null +++ b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/t48/pmem_ctrl-c.vhd @@ -0,0 +1,17 @@ +------------------------------------------------------------------------------- +-- +-- The Program Memory control unit. +-- All operations related to the Program Memory are managed here. +-- +-- $Id: pmem_ctrl-c.vhd 295 2009-04-01 19:32:48Z arniml $ +-- +-- All rights reserved +-- +------------------------------------------------------------------------------- + +configuration t48_pmem_ctrl_rtl_c0 of t48_pmem_ctrl is + + for rtl + end for; + +end t48_pmem_ctrl_rtl_c0; diff --git a/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/t48/pmem_ctrl.vhd b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/t48/pmem_ctrl.vhd new file mode 100644 index 0000000000000000000000000000000000000000..183668fa7378c7d2c95d084576f8f9a84e417278 --- /dev/null +++ b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/t48/pmem_ctrl.vhd @@ -0,0 +1,222 @@ +------------------------------------------------------------------------------- +-- +-- The Program Memory control unit. +-- All operations related to the Program Memory are managed here. +-- +-- $Id: pmem_ctrl.vhd 295 2009-04-01 19:32:48Z arniml $ +-- +-- Copyright (c) 2004, Arnim Laeuger (arniml@opencores.org) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.opencores.org/cvsweb.shtml/t48/ +-- +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; + +use work.t48_pack.pmem_addr_t; +use work.t48_pack.word_t; +use work.t48_pmem_ctrl_pack.pmem_addr_ident_t; + +entity t48_pmem_ctrl is + + port ( + -- Global Interface ------------------------------------------------------- + clk_i : in std_logic; + res_i : in std_logic; + en_clk_i : in boolean; + -- T48 Bus Interface ------------------------------------------------------ + data_i : in word_t; + data_o : out word_t; + write_pcl_i : in boolean; + read_pcl_i : in boolean; + write_pch_i : in boolean; + read_pch_i : in boolean; + inc_pc_i : in boolean; + write_pmem_addr_i : in boolean; + addr_type_i : in pmem_addr_ident_t; + read_pmem_i : in boolean; + -- Porgram Memroy Interface ----------------------------------------------- + pmem_addr_o : out pmem_addr_t; + pmem_data_i : in word_t + ); + +end t48_pmem_ctrl; + + +library ieee; +use ieee.numeric_std.all; + +use work.t48_pmem_ctrl_pack.all; +use work.t48_pack.res_active_c; +use work.t48_pack.clk_active_c; +use work.t48_pack.bus_idle_level_c; +use work.t48_pack.pmem_addr_width_c; +use work.t48_pack.dmem_addr_width_c; +use work.t48_pack.page_t; + +architecture rtl of t48_pmem_ctrl is + + -- implemented counter width of Program Counter + -- the upper bit is only altered by JMP, CALL and RET(R) + subtype pc_count_range_t is natural range pmem_addr_width_c-2 downto 0; + + -- the Program Counter + signal program_counter_q : unsigned(pmem_addr_t'range); + + + -- the Program Memory address + signal pmem_addr_s, + pmem_addr_q : std_logic_vector(pmem_addr_t'range); + +begin + + ----------------------------------------------------------------------------- + -- Process program_counter + -- + -- Purpose: + -- Implements the Program Counter. + -- + program_counter: process (res_i, clk_i) + begin + if res_i = res_active_c then + program_counter_q <= (others => '0'); + pmem_addr_q <= (others => '0'); + + elsif clk_i'event and clk_i = clk_active_c then + if en_clk_i then + + -- parallel load mode + if write_pcl_i then + program_counter_q(data_i'range) <= UNSIGNED(data_i); + elsif write_pch_i then + program_counter_q(pmem_addr_width_c-1 downto data_i'high+1) <= + UNSIGNED(data_i(pmem_addr_width_c - dmem_addr_width_c - 1 downto 0)); + elsif inc_pc_i then + -- increment mode + -- the MSB is not modified by linear increments + -- it can only be altered by JMP, CALL or RET(R) + program_counter_q(pc_count_range_t) <= + program_counter_q(pc_count_range_t) + 1; + end if; + + -- set pmem address + if write_pmem_addr_i then + pmem_addr_q <= pmem_addr_s; + end if; + + end if; + + end if; + + end process program_counter; + -- + ----------------------------------------------------------------------------- + + + ----------------------------------------------------------------------------- + -- Process pmem_addr + -- + -- Purpose: + -- Multiplex the Program Memory address. + -- + pmem_addr: process (program_counter_q, + addr_type_i, + pmem_addr_q, + data_i) + begin + -- default assignment + pmem_addr_s <= STD_LOGIC_VECTOR(program_counter_q); + + case addr_type_i is + when PM_PC => + -- default is ok + null; + + when PM_PAGE => + pmem_addr_s(word_t'range) <= data_i; + -- take page address from program counter + -- => important for JMPP, MOVP! + -- they must wrap to next page when at FF! + + when PM_PAGE3 => + pmem_addr_s(word_t'range) <= data_i; + -- page address is explicitely specified + pmem_addr_s(page_t'range) <= "0011"; + + when others => + null; + + end case; + + end process pmem_addr; + -- + ----------------------------------------------------------------------------- + + + ----------------------------------------------------------------------------- + -- Process data_output + -- + -- Purpose: + -- Multiplex the data bus output. + -- + data_output: process (read_pmem_i, + read_pcl_i, + read_pch_i, + pmem_data_i, + program_counter_q) + begin + data_o <= (others => bus_idle_level_c); + + if read_pmem_i then + data_o <= pmem_data_i; + elsif read_pcl_i then + data_o <= STD_LOGIC_VECTOR(program_counter_q(data_o'range)); + elsif read_pch_i then + data_o(3 downto 0) <= STD_LOGIC_VECTOR(program_counter_q(pmem_addr_width_c-1 downto data_o'high+1)); + end if; + + end process data_output; + -- + ----------------------------------------------------------------------------- + + + ----------------------------------------------------------------------------- + -- Output Mapping. + ----------------------------------------------------------------------------- + pmem_addr_o <= pmem_addr_q; + +end rtl; diff --git a/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/t48/pmem_ctrl_pack-p.vhd b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/t48/pmem_ctrl_pack-p.vhd new file mode 100644 index 0000000000000000000000000000000000000000..202c51b2df8958bf73b868852f3c353d14498b21 --- /dev/null +++ b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/t48/pmem_ctrl_pack-p.vhd @@ -0,0 +1,20 @@ +------------------------------------------------------------------------------- +-- +-- $Id: pmem_ctrl_pack-p.vhd 295 2009-04-01 19:32:48Z arniml $ +-- +-- Copyright (c) 2004, Arnim Laeuger (arniml@opencores.org) +-- +-- All rights reserved +-- +------------------------------------------------------------------------------- + +package t48_pmem_ctrl_pack is + + ----------------------------------------------------------------------------- + -- Address Type Identifier + ----------------------------------------------------------------------------- + type pmem_addr_ident_t is (PM_PC, + PM_PAGE, + PM_PAGE3); + +end t48_pmem_ctrl_pack; diff --git a/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/t48/psw-c.vhd b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/t48/psw-c.vhd new file mode 100644 index 0000000000000000000000000000000000000000..bf62f497a3c4e54a70fdc4d28f6f5b0daffc47a2 --- /dev/null +++ b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/t48/psw-c.vhd @@ -0,0 +1,17 @@ +------------------------------------------------------------------------------- +-- +-- The Program Status Word (PSW). +-- Implements the PSW with its special bits. +-- +-- $Id: psw-c.vhd 295 2009-04-01 19:32:48Z arniml $ +-- +-- All rights reserved +-- +------------------------------------------------------------------------------- + +configuration t48_psw_rtl_c0 of t48_psw is + + for rtl + end for; + +end t48_psw_rtl_c0; diff --git a/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/t48/psw.vhd b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/t48/psw.vhd new file mode 100644 index 0000000000000000000000000000000000000000..7eea9d6104a46f67e4cdd5bfaccc548f24cbc944 --- /dev/null +++ b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/t48/psw.vhd @@ -0,0 +1,212 @@ +------------------------------------------------------------------------------- +-- +-- The Program Status Word (PSW). +-- Implements the PSW with its special bits. +-- +-- $Id: psw.vhd 295 2009-04-01 19:32:48Z arniml $ +-- +-- Copyright (c) 2004, Arnim Laeuger (arniml@opencores.org) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.opencores.org/cvsweb.shtml/t48/ +-- +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; + +use work.t48_pack.word_t; + +entity t48_psw is + + port ( + -- Global Interface ------------------------------------------------------- + clk_i : in std_logic; + res_i : in std_logic; + en_clk_i : in boolean; + -- T48 Bus Interface ------------------------------------------------------ + data_i : in word_t; + data_o : out word_t; + read_psw_i : in boolean; + read_sp_i : in boolean; + write_psw_i : in boolean; + write_sp_i : in boolean; + -- Decoder Interface ------------------------------------------------------ + special_data_i : in std_logic; + inc_stackp_i : in boolean; + dec_stackp_i : in boolean; + write_carry_i : in boolean; + write_aux_carry_i : in boolean; + write_f0_i : in boolean; + write_bs_i : in boolean; + carry_o : out std_logic; + aux_carry_i : in std_logic; + aux_carry_o : out std_logic; + f0_o : out std_logic; + bs_o : out std_logic + ); + +end t48_psw; + + +library ieee; +use ieee.numeric_std.all; + +use work.t48_pack.clk_active_c; +use work.t48_pack.res_active_c; +use work.t48_pack.bus_idle_level_c; +use work.t48_pack.nibble_t; + +architecture rtl of t48_psw is + + -- special bit positions in PSW + constant carry_c : natural := 3; + constant aux_carry_c : natural := 2; + constant f0_c : natural := 1; + constant bs_c : natural := 0; + + -- the PSW register + signal psw_q : nibble_t; + -- the Stack Pointer + signal sp_q : unsigned(2 downto 0); + + -- pragma translate_off + signal psw_s : word_t; + -- pragma translate_on + +begin + + ----------------------------------------------------------------------------- + -- Process psw_reg + -- + -- Purpose: + -- Implements the PSW register. + -- + psw_reg: process (res_i, clk_i) + begin + if res_i = res_active_c then + psw_q <= (others => '0'); + sp_q <= (others => '0'); + + elsif clk_i'event and clk_i = clk_active_c then + if en_clk_i then + + -- T48 bus access + if write_psw_i then + psw_q <= data_i(7 downto 4); + end if; + if write_sp_i then + sp_q <= unsigned(data_i(2 downto 0)); + end if; + + -- increment Stack Pointer + if inc_stackp_i then + sp_q <= sp_q + 1; + end if; + -- decrement Stack Pointer + if dec_stackp_i then + sp_q <= sp_q - 1; + end if; + + -- access to special bits + if write_carry_i then + psw_q(carry_c) <= special_data_i; + end if; + -- + if write_aux_carry_i then + psw_q(aux_carry_c) <= aux_carry_i; + end if; + -- + if write_f0_i then + psw_q(f0_c) <= special_data_i; + end if; + -- + if write_bs_i then + psw_q(bs_c) <= special_data_i; + end if; + + end if; + + end if; + + end process psw_reg; + -- + ----------------------------------------------------------------------------- + + + ----------------------------------------------------------------------------- + -- Process data_out + -- + -- Purpose: + -- Output multiplexer for T48 Data Bus. + -- + data_out: process (read_psw_i, + read_sp_i, + psw_q, + sp_q) + begin + data_o <= (others => bus_idle_level_c); + + if read_psw_i then + data_o(7 downto 4) <= psw_q; + end if; + + if read_sp_i then + data_o(3 downto 0) <= '1' & std_logic_vector(sp_q); + end if; + + end process data_out; + -- + ----------------------------------------------------------------------------- + + + -- pragma translate_off + tb: process (psw_q, sp_q) + begin + psw_s(7 downto 4) <= psw_q; + psw_s(3) <= '1'; + psw_s(2 downto 0) <= std_logic_vector(sp_q); + end process tb; + -- pragma translate_on + + ----------------------------------------------------------------------------- + -- Output mapping. + ----------------------------------------------------------------------------- + carry_o <= psw_q(carry_c); + aux_carry_o <= psw_q(aux_carry_c); + f0_o <= psw_q(f0_c); + bs_o <= psw_q(bs_c); + +end rtl; diff --git a/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/t48/system/generic_ram_ena-c.vhd b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/t48/system/generic_ram_ena-c.vhd new file mode 100644 index 0000000000000000000000000000000000000000..b1b13f0ce9bcae37ad77399709c477ed07848712 --- /dev/null +++ b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/t48/system/generic_ram_ena-c.vhd @@ -0,0 +1,18 @@ +------------------------------------------------------------------------------- +-- +-- Parametrizable, generic RAM with enable. +-- +-- $Id: generic_ram_ena-c.vhd 295 2009-04-01 19:32:48Z arniml $ +-- +-- Copyright (c) 2006, Arnim Laeuger (arniml@opencores.org) +-- +-- All rights reserved +-- +------------------------------------------------------------------------------- + +configuration generic_ram_ena_rtl_c0 of generic_ram_ena is + + for rtl + end for; + +end generic_ram_ena_rtl_c0; diff --git a/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/t48/system/generic_ram_ena.vhd b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/t48/system/generic_ram_ena.vhd new file mode 100644 index 0000000000000000000000000000000000000000..f3772aea190075585003258b865a44b32e259c62 --- /dev/null +++ b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/t48/system/generic_ram_ena.vhd @@ -0,0 +1,100 @@ +------------------------------------------------------------------------------- +-- +-- Parametrizable, generic RAM with enable. +-- +-- $Id: generic_ram_ena.vhd 295 2009-04-01 19:32:48Z arniml $ +-- +-- Copyright (c) 2006 Arnim Laeuger (arniml@opencores.org) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.opencores.org/cvsweb.shtml/t48/ +-- +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; + +entity generic_ram_ena is + + generic ( + addr_width_g : integer := 10; + data_width_g : integer := 8 + ); + port ( + clk_i : in std_logic; + a_i : in std_logic_vector(addr_width_g-1 downto 0); + we_i : in std_logic; + ena_i : in std_logic; + d_i : in std_logic_vector(data_width_g-1 downto 0); + d_o : out std_logic_vector(data_width_g-1 downto 0) + ); + +end generic_ram_ena; + + +library ieee; +use ieee.numeric_std.all; + +architecture rtl of generic_ram_ena is + + type mem_t is array (natural range 0 to 2**addr_width_g-1) of + std_logic_vector(d_i'range); + signal mem_q : mem_t + -- pragma translate_off + := (others => (others => '0')) + -- pragma translate_on + ; + signal a_q : std_logic_vector(a_i'range); + +begin + + mem: process (clk_i) + begin + + if clk_i'event and clk_i = '1' then + if ena_i = '1' then + if we_i = '1' then + mem_q(to_integer(unsigned(a_i))) <= d_i; + end if; + + a_q <= a_i; + end if; + + end if; + end process mem; + + d_o <= mem_q(to_integer(unsigned(a_q))); + +end rtl; diff --git a/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/t48/system/lpm_ram_dq.vhd b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/t48/system/lpm_ram_dq.vhd new file mode 100644 index 0000000000000000000000000000000000000000..8b2a30b4eb64d1f1c3ad49331ec9307e9782738f --- /dev/null +++ b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/t48/system/lpm_ram_dq.vhd @@ -0,0 +1,439 @@ +-------------------------------------------------------------------------- +-- This VHDL file was developed by Altera Corporation. It may be +-- freely copied and/or distributed at no cost. Any persons using this +-- file for any purpose do so at their own risk, and are responsible for +-- the results of such use. Altera Corporation does not guarantee that +-- this file is complete, correct, or fit for any particular purpose. +-- NO WARRANTY OF ANY KIND IS EXPRESSED OR IMPLIED. This notice must +-- accompany any copy of this file. +-- +-------------------------------------------------------------------------- +-- LPM Synthesizable Models (Support string type generic) +-------------------------------------------------------------------------- +-- Version 2.0 (lpm 220) Date 01/04/00 +-- +-- 1. Fixed LPM_RAM_DQ, LPM_RAM_DP, LPM_RAM_IO and LPM_ROM to correctly +-- read in values from LPM_FILE (*.hex) when the DATA width is greater +-- than 16 bits. +-- 2. Explicit sign conversions are added to standard logic vector +-- comparisons in LPM_RAM_DQ, LPM_RAM_DP, LPM_RAM_IO, LPM_ROM, and +-- LPM_COMPARE. +-- 3. LPM_FIFO_DC is rewritten to have correct outputs. +-- 4. LPM_FIFO outputs zeros when nothing has been read from it, and +-- outputs LPM_NUMWORDS mod exp(2, LPM_WIDTHU) when it is full. +-- 5. Fixed LPM_DIVIDE to divide correctly. +-------------------------------------------------------------------------- +-- Version 1.9 (lpm 220) Date 11/30/99 +-- +-- 1. Fixed UNUSED file not found problem and initialization problem +-- with LPM_RAM_DP, LPM_RAM_DQ, and LPM_RAM_IO. +-- 2. Fixed LPM_MULT when SUM port is not used. +-- 3. Fixed LPM_FIFO_DC to enable read when rdclock and wrclock rise +-- at the same time. +-- 4. Fixed LPM_COUNTER comparison problem when signed library is loaded +-- and counter is incrementing. +-- 5. Got rid of "Illegal Character" error message at time = 0 ns when +-- simulating LPM_COUNTER. +-------------------------------------------------------------------------- +-- Version 1.8 (lpm 220) Date 10/25/99 +-- +-- 1. Some LPM_PVALUE implementations were missing, and now implemented. +-- 2. Fixed LPM_COUNTER to count correctly without conversion overflow, +-- that is, when LPM_MODULUS = 2 ** LPM_WIDTH. +-- 3. Fixed LPM_RAM_DP sync process sensitivity list to detect wraddress +-- changes. +-------------------------------------------------------------------------- +-- Version 1.7 (lpm 220) Date 07/13/99 +-- +-- Changed LPM_RAM_IO so that it can be used to simulate both MP2 and +-- Quartus behaviour and LPM220-compliant behaviour. +-------------------------------------------------------------------------- +-- Version 1.6 (lpm 220) Date 06/15/99 +-- +-- 1. Fixed LPM_ADD_SUB sign extension problem and subtraction bug. +-- 2. Fixed LPM_COUNTER to use LPM_MODULUS value. +-- 3. Added CIN and COUT port, and discarded EQ port in LPM_COUNTER to +-- comply with the specfication. +-- 4. Included LPM_RAM_DP, LPM_RAM_DQ, LPM_RAM_IO, LPM_ROM, LPM_FIFO, and +-- LPM_FIFO_DC; they are all initialized to 0's. +-------------------------------------------------------------------------- +-- Version 1.5 (lpm 220) Date 05/10/99 +-- +-- Changed LPM_MODULUS from string type to integer. +-------------------------------------------------------------------------- +-- Version 1.4 (lpm 220) Date 02/05/99 +-- +-- 1. Added LPM_DIVIDE module. +-- 2. Added CLKEN port to LPM_MUX, LPM_DECODE, LPM_ADD_SUB, LPM_MULT +-- and LPM_COMPARE +-- 3. Replaced the constants holding string with the actual string. +-------------------------------------------------------------------------- +-- Version 1.3 Date 07/30/96 +-- +-- Modification History +-- +-- 1. Changed the DEFAULT value to "UNUSED" for LPM_SVALUE, LPM_AVALUE, +-- LPM_MODULUS, and LPM_NUMWORDS, LPM_HINT,LPM_STRENGTH, LPM_DIRECTION, +-- and LPM_PVALUE +-- +-- 2. Added the two dimentional port components (AND, OR, XOR, and MUX). +-------------------------------------------------------------------------- +-- Excluded Functions: +-- +-- LPM_FSM and LPM_TTABLE +-- +-------------------------------------------------------------------------- +-- Assumptions: +-- +-- 1. All ports and signal types are std_logic or std_logic_vector +-- from IEEE 1164 package. +-- 2. Synopsys std_logic_arith, std_logic_unsigned, and std_logic_signed +-- package are assumed to be accessible from IEEE library. +-- 3. lpm_component_package must be accessible from library work. +-- 4. The default value of LPM_SVALUE, LPM_AVALUE, LPM_MODULUS, LPM_HINT, +-- LPM_NUMWORDS, LPM_STRENGTH, LPM_DIRECTION, and LPM_PVALUE is +-- string "UNUSED". +-------------------------------------------------------------------------- + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; +--use IEEE.std_logic_unsigned.all; +use std.textio.all; + +entity LPM_RAM_DQ is + generic (LPM_WIDTH : positive; + LPM_WIDTHAD : positive; + LPM_NUMWORDS : natural := 0; + LPM_INDATA : string := "REGISTERED"; + LPM_ADDRESS_CONTROL: string := "REGISTERED"; + LPM_OUTDATA : string := "REGISTERED"; + LPM_FILE : string := "UNUSED"; + LPM_TYPE : string := "LPM_RAM_DQ"; + LPM_HINT : string := "UNUSED"); + port (DATA : in std_logic_vector(LPM_WIDTH-1 downto 0); + ADDRESS : in std_logic_vector(LPM_WIDTHAD-1 downto 0); + INCLOCK : in std_logic := '0'; + OUTCLOCK : in std_logic := '0'; + WE : in std_logic; + Q : out std_logic_vector(LPM_WIDTH-1 downto 0)); + + function int_to_str( value : integer ) return string is + variable ivalue,index : integer; + variable digit : integer; + variable line_no: string(8 downto 1) := " "; + begin + ivalue := value; + index := 1; + while (ivalue > 0) loop + digit := ivalue MOD 10; + ivalue := ivalue/10; + case digit is + when 0 => + line_no(index) := '0'; + when 1 => + line_no(index) := '1'; + when 2 => + line_no(index) := '2'; + when 3 => + line_no(index) := '3'; + when 4 => + line_no(index) := '4'; + when 5 => + line_no(index) := '5'; + when 6 => + line_no(index) := '6'; + when 7 => + line_no(index) := '7'; + when 8 => + line_no(index) := '8'; + when 9 => + line_no(index) := '9'; + when others => + ASSERT FALSE + REPORT "Illegal number!" + SEVERITY ERROR; + end case; + index := index + 1; + end loop; + return line_no; + end; + + function hex_str_to_int( str : string ) return integer is + variable len : integer := str'length; + variable ivalue : integer := 0; + variable digit : integer; + begin + for i in len downto 1 loop + case str(i) is + when '0' => + digit := 0; + when '1' => + digit := 1; + when '2' => + digit := 2; + when '3' => + digit := 3; + when '4' => + digit := 4; + when '5' => + digit := 5; + when '6' => + digit := 6; + when '7' => + digit := 7; + when '8' => + digit := 8; + when '9' => + digit := 9; + when 'A' => + digit := 10; + when 'a' => + digit := 10; + when 'B' => + digit := 11; + when 'b' => + digit := 11; + when 'C' => + digit := 12; + when 'c' => + digit := 12; + when 'D' => + digit := 13; + when 'd' => + digit := 13; + when 'E' => + digit := 14; + when 'e' => + digit := 14; + when 'F' => + digit := 15; + when 'f' => + digit := 15; + when others => + ASSERT FALSE + REPORT "Illegal character "& str(i) & "in Intel Hex File! " + SEVERITY ERROR; + end case; + ivalue := ivalue * 16 + digit; + end loop; + return ivalue; + end; + + procedure Shrink_line(L : inout LINE; pos : in integer) is + subtype nstring is string(1 to pos); + variable stmp : nstring; + begin + if pos >= 1 then + read(l, stmp); + end if; + end; + +end LPM_RAM_DQ; + +architecture LPM_SYN of lpm_ram_dq is + +--type lpm_memory is array(lpm_numwords-1 downto 0) of std_logic_vector(lpm_width-1 downto 0); +type lpm_memory is array(integer range (2**lpm_widthad)-1 downto 0) of std_logic_vector(lpm_width-1 downto 0); + +signal data_tmp, data_reg : std_logic_vector(lpm_width-1 downto 0); +signal q_tmp, q_reg : std_logic_vector(lpm_width-1 downto 0) := (others => '0'); +signal address_tmp, address_reg : std_logic_vector(lpm_widthad-1 downto 0); +signal we_tmp, we_reg : std_logic; + +begin + + sync: process(data, data_reg, address, address_reg, + we, we_reg, q_tmp, q_reg) + begin + if (lpm_address_control = "REGISTERED") then + address_tmp <= address_reg; + we_tmp <= we_reg; + else + address_tmp <= address; + we_tmp <= we; + end if; + if (lpm_indata = "REGISTERED") then + data_tmp <= data_reg; + else + data_tmp <= data; + end if; + if (lpm_outdata = "REGISTERED") then + q <= q_reg; + else + q <= q_tmp; + end if; + end process; + + input_reg: process (inclock) + begin + if inclock'event and inclock = '1' then + data_reg <= data; + address_reg <= address; + we_reg <= we; + end if; + end process; + + output_reg: process (outclock) + begin + if outclock'event and outclock = '1' then + q_reg <= q_tmp; + end if; + end process; + + memory: process(data_tmp, we_tmp, address_tmp) + variable mem_data : lpm_memory; + variable mem_data_tmp : integer := 0; + variable mem_init: boolean := false; + variable i,j,k,lineno: integer := 0; + variable buf: line ; + variable booval: boolean ; + FILE unused_file: TEXT IS OUT "UNUSED"; + FILE mem_data_file: TEXT IS IN LPM_FILE; + variable base, byte, rec_type, datain, addr, checksum: string(2 downto 1); + variable startadd: string(4 downto 1); + variable ibase: integer := 0; + variable ibyte: integer := 0; + variable istartadd: integer := 0; + variable check_sum_vec, check_sum_vec_tmp: unsigned(7 downto 0); + begin + -- INITIALIZE -- + if NOT(mem_init) then + -- INITIALIZE TO 0 -- + for i in mem_data'LOW to mem_data'HIGH loop + mem_data(i) := (OTHERS => '0'); + end loop; + + if (LPM_FILE = "UNUSED") then + ASSERT FALSE + REPORT "Initialization file not found!" + SEVERITY WARNING; + else + WHILE NOT ENDFILE(mem_data_file) loop + booval := true; + READLINE(mem_data_file, buf); + lineno := lineno + 1; + check_sum_vec := (OTHERS => '0'); + if (buf(buf'LOW) = ':') then + i := 1; + shrink_line(buf, i); + READ(L=>buf, VALUE=>byte, good=>booval); + if not (booval) then + ASSERT FALSE + REPORT "[Line "& int_to_str(lineno) & "]:Illegal Intel Hex Format!" + SEVERITY ERROR; + end if; + ibyte := hex_str_to_int(byte); + check_sum_vec := unsigned(check_sum_vec) + to_unsigned(ibyte, check_sum_vec'length); + READ(L=>buf, VALUE=>startadd, good=>booval); + if not (booval) then + ASSERT FALSE + REPORT "[Line "& int_to_str(lineno) & "]:Illegal Intel Hex Format! " + SEVERITY ERROR; + end if; + istartadd := hex_str_to_int(startadd); + addr(2) := startadd(4); + addr(1) := startadd(3); + check_sum_vec := unsigned(check_sum_vec) + to_unsigned(hex_str_to_int(addr), check_sum_vec'length); + addr(2) := startadd(2); + addr(1) := startadd(1); + check_sum_vec := unsigned(check_sum_vec) + to_unsigned(hex_str_to_int(addr), check_sum_vec'length); + READ(L=>buf, VALUE=>rec_type, good=>booval); + if not (booval) then + ASSERT FALSE + REPORT "[Line "& int_to_str(lineno) & "]:Illegal Intel Hex Format! " + SEVERITY ERROR; + end if; + check_sum_vec := unsigned(check_sum_vec) + to_unsigned(hex_str_to_int(rec_type), check_sum_vec'length); + else + ASSERT FALSE + REPORT "[Line "& int_to_str(lineno) & "]:Illegal Intel Hex Format! " + SEVERITY ERROR; + end if; + case rec_type is + when "00"=> -- Data record + i := 0; + k := lpm_width / 8; + if ((lpm_width MOD 8) /= 0) then + k := k + 1; + end if; + -- k = no. of bytes per CAM entry. + while (i < ibyte) loop + mem_data_tmp := 0; + for j in 1 to k loop + READ(L=>buf, VALUE=>datain,good=>booval); -- read in data a byte (2 hex chars) at a time. + if not (booval) then + ASSERT FALSE + REPORT "[Line "& int_to_str(lineno) & "]:Illegal Intel Hex Format! " + SEVERITY ERROR; + end if; + check_sum_vec := unsigned(check_sum_vec) + to_unsigned(hex_str_to_int(datain), check_sum_vec'length); + mem_data_tmp := mem_data_tmp * 256 + hex_str_to_int(datain); + end loop; + i := i + k; + mem_data(ibase + istartadd) := STD_LOGIC_VECTOR(to_unsigned(mem_data_tmp, lpm_width)); + istartadd := istartadd + 1; + end loop; + when "01"=> + exit; + when "02"=> + ibase := 0; + if (ibyte /= 2) then + ASSERT FALSE + REPORT "[Line "& int_to_str(lineno) & "]:Illegal Intel Hex Format for record type 02! " + SEVERITY ERROR; + end if; + for i in 0 to (ibyte-1) loop + READ(L=>buf, VALUE=>base,good=>booval); + ibase := ibase * 256 + hex_str_to_int(base); + if not (booval) then + ASSERT FALSE + REPORT "[Line "& int_to_str(lineno) & "]:Illegal Intel Hex Format! " + SEVERITY ERROR; + end if; + check_sum_vec := unsigned(check_sum_vec) + to_unsigned(hex_str_to_int(base), check_sum_vec'length); + end loop; + ibase := ibase * 16; + when OTHERS => + ASSERT FALSE + REPORT "[Line "& int_to_str(lineno) & "]:Illegal record type in Intel Hex File! " + SEVERITY ERROR; + end case; + READ(L=>buf, VALUE=>checksum,good=>booval); + if not (booval) then + ASSERT FALSE + REPORT "[Line "& int_to_str(lineno) & "]:Checksum is missing! " + SEVERITY ERROR; + end if; + + check_sum_vec := unsigned(not (check_sum_vec)) + 1 ; + check_sum_vec_tmp := to_unsigned(hex_str_to_int(checksum), check_sum_vec_tmp'length); + + if (unsigned(check_sum_vec) /= unsigned(check_sum_vec_tmp)) then + ASSERT FALSE + REPORT "[Line "& int_to_str(lineno) & "]:Incorrect checksum!" + SEVERITY ERROR; + end if; + end loop; + end if; + mem_init := TRUE; + end if; + + -- MEMORY FUNCTION -- + if we_tmp = '1' then + mem_data (to_integer(unsigned(address_tmp))) := data_tmp; + end if; + q_tmp <= mem_data(to_integer(unsigned(address_tmp))); + end process; + +end LPM_SYN; + + +-- pragma translate_off +configuration lpm_ram_dq_c0 of lpm_ram_dq is + + for lpm_syn + end for; + +end lpm_ram_dq_c0; +-- pragma translate_on diff --git a/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/t48/system/lpm_rom.vhd b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/t48/system/lpm_rom.vhd new file mode 100644 index 0000000000000000000000000000000000000000..b9450d6b10fefc85c5f85dda50d03ed6bf9ae3e7 --- /dev/null +++ b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/t48/system/lpm_rom.vhd @@ -0,0 +1,437 @@ +-------------------------------------------------------------------------- +-- This VHDL file was developed by Altera Corporation. It may be +-- freely copied and/or distributed at no cost. Any persons using this +-- file for any purpose do so at their own risk, and are responsible for +-- the results of such use. Altera Corporation does not guarantee that +-- this file is complete, correct, or fit for any particular purpose. +-- NO WARRANTY OF ANY KIND IS EXPRESSED OR IMPLIED. This notice must +-- accompany any copy of this file. +-- +-------------------------------------------------------------------------- +-- LPM Synthesizable Models (Support string type generic) +-------------------------------------------------------------------------- +-- Version 2.0 (lpm 220) Date 01/04/00 +-- +-- 1. Fixed LPM_RAM_DQ, LPM_RAM_DP, LPM_RAM_IO and LPM_ROM to correctly +-- read in values from LPM_FILE (*.hex) when the DATA width is greater +-- than 16 bits. +-- 2. Explicit sign conversions are added to standard logic vector +-- comparisons in LPM_RAM_DQ, LPM_RAM_DP, LPM_RAM_IO, LPM_ROM, and +-- LPM_COMPARE. +-- 3. LPM_FIFO_DC is rewritten to have correct outputs. +-- 4. LPM_FIFO outputs zeros when nothing has been read from it, and +-- outputs LPM_NUMWORDS mod exp(2, LPM_WIDTHU) when it is full. +-- 5. Fixed LPM_DIVIDE to divide correctly. +-------------------------------------------------------------------------- +-- Version 1.9 (lpm 220) Date 11/30/99 +-- +-- 1. Fixed UNUSED file not found problem and initialization problem +-- with LPM_RAM_DP, LPM_RAM_DQ, and LPM_RAM_IO. +-- 2. Fixed LPM_MULT when SUM port is not used. +-- 3. Fixed LPM_FIFO_DC to enable read when rdclock and wrclock rise +-- at the same time. +-- 4. Fixed LPM_COUNTER comparison problem when signed library is loaded +-- and counter is incrementing. +-- 5. Got rid of "Illegal Character" error message at time = 0 ns when +-- simulating LPM_COUNTER. +-------------------------------------------------------------------------- +-- Version 1.8 (lpm 220) Date 10/25/99 +-- +-- 1. Some LPM_PVALUE implementations were missing, and now implemented. +-- 2. Fixed LPM_COUNTER to count correctly without conversion overflow, +-- that is, when LPM_MODULUS = 2 ** LPM_WIDTH. +-- 3. Fixed LPM_RAM_DP sync process sensitivity list to detect wraddress +-- changes. +-------------------------------------------------------------------------- +-- Version 1.7 (lpm 220) Date 07/13/99 +-- +-- Changed LPM_RAM_IO so that it can be used to simulate both MP2 and +-- Quartus behaviour and LPM220-compliant behaviour. +-------------------------------------------------------------------------- +-- Version 1.6 (lpm 220) Date 06/15/99 +-- +-- 1. Fixed LPM_ADD_SUB sign extension problem and subtraction bug. +-- 2. Fixed LPM_COUNTER to use LPM_MODULUS value. +-- 3. Added CIN and COUT port, and discarded EQ port in LPM_COUNTER to +-- comply with the specfication. +-- 4. Included LPM_RAM_DP, LPM_RAM_DQ, LPM_RAM_IO, LPM_ROM, LPM_FIFO, and +-- LPM_FIFO_DC; they are all initialized to 0's. +-------------------------------------------------------------------------- +-- Version 1.5 (lpm 220) Date 05/10/99 +-- +-- Changed LPM_MODULUS from string type to integer. +-------------------------------------------------------------------------- +-- Version 1.4 (lpm 220) Date 02/05/99 +-- +-- 1. Added LPM_DIVIDE module. +-- 2. Added CLKEN port to LPM_MUX, LPM_DECODE, LPM_ADD_SUB, LPM_MULT +-- and LPM_COMPARE +-- 3. Replaced the constants holding string with the actual string. +-------------------------------------------------------------------------- +-- Version 1.3 Date 07/30/96 +-- +-- Modification History +-- +-- 1. Changed the DEFAULT value to "UNUSED" for LPM_SVALUE, LPM_AVALUE, +-- LPM_MODULUS, and LPM_NUMWORDS, LPM_HINT,LPM_STRENGTH, LPM_DIRECTION, +-- and LPM_PVALUE +-- +-- 2. Added the two dimentional port components (AND, OR, XOR, and MUX). +-------------------------------------------------------------------------- +-- Excluded Functions: +-- +-- LPM_FSM and LPM_TTABLE +-- +-------------------------------------------------------------------------- +-- Assumptions: +-- +-- 1. All ports and signal types are std_logic or std_logic_vector +-- from IEEE 1164 package. +-- 2. Synopsys std_logic_arith, std_logic_unsigned, and std_logic_signed +-- package are assumed to be accessible from IEEE library. +-- 3. lpm_component_package must be accessible from library work. +-- 4. The default value of LPM_SVALUE, LPM_AVALUE, LPM_MODULUS, LPM_HINT, +-- LPM_NUMWORDS, LPM_STRENGTH, LPM_DIRECTION, and LPM_PVALUE is +-- string "UNUSED". +-------------------------------------------------------------------------- + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; +--use work.LPM_COMPONENTS.all; +use std.textio.all; + +entity LPM_ROM is + generic (LPM_WIDTH : positive; + LPM_WIDTHAD : positive; + LPM_NUMWORDS : natural := 0; + LPM_ADDRESS_CONTROL : string := "REGISTERED"; + LPM_OUTDATA : string := "REGISTERED"; + LPM_FILE : string; + LPM_TYPE : string := "LPM_ROM"; + LPM_HINT : string := "UNUSED"); + port (ADDRESS : in STD_LOGIC_VECTOR(LPM_WIDTHAD-1 downto 0); + INCLOCK : in STD_LOGIC := '0'; + OUTCLOCK : in STD_LOGIC := '0'; + MEMENAB : in STD_LOGIC := '1'; + Q : out STD_LOGIC_VECTOR(LPM_WIDTH-1 downto 0)); + + function int_to_str( value : integer ) return string is + variable ivalue,index : integer; + variable digit : integer; + variable line_no: string(8 downto 1) := " "; + begin + ivalue := value; + index := 1; + while (ivalue > 0 ) loop + digit := ivalue MOD 10; + ivalue := ivalue/10; + case digit is + when 0 => + line_no(index) := '0'; + when 1 => + line_no(index) := '1'; + when 2 => + line_no(index) := '2'; + when 3 => + line_no(index) := '3'; + when 4 => + line_no(index) := '4'; + when 5 => + line_no(index) := '5'; + when 6 => + line_no(index) := '6'; + when 7 => + line_no(index) := '7'; + when 8 => + line_no(index) := '8'; + when 9 => + line_no(index) := '9'; + when others => + ASSERT FALSE + REPORT "Illegal number!" + SEVERITY ERROR; + end case; + index := index + 1; + end loop; + return line_no; + end; + + function hex_str_to_int( str : string ) return integer is + variable len : integer := str'length; + variable ivalue : integer := 0; + variable digit : integer; + begin + for i in len downto 1 loop + case str(i) is + when '0' => + digit := 0; + when '1' => + digit := 1; + when '2' => + digit := 2; + when '3' => + digit := 3; + when '4' => + digit := 4; + when '5' => + digit := 5; + when '6' => + digit := 6; + when '7' => + digit := 7; + when '8' => + digit := 8; + when '9' => + digit := 9; + when 'A' => + digit := 10; + when 'a' => + digit := 10; + when 'B' => + digit := 11; + when 'b' => + digit := 11; + when 'C' => + digit := 12; + when 'c' => + digit := 12; + when 'D' => + digit := 13; + when 'd' => + digit := 13; + when 'E' => + digit := 14; + when 'e' => + digit := 14; + when 'F' => + digit := 15; + when 'f' => + digit := 15; + when others => + ASSERT FALSE + REPORT "Illegal character "& str(i) & "in Intel Hex File! " + SEVERITY ERROR; + end case; + ivalue := ivalue * 16 + digit; + end loop; + return ivalue; + end; + + procedure Shrink_line(L : inout LINE; pos : in integer) is + subtype nstring is string(1 to pos); + variable stmp : nstring; + begin + if pos >= 1 then + read(l, stmp); + end if; + end; + +end LPM_ROM; + +architecture LPM_SYN of lpm_rom is + +--type lpm_memory is array(lpm_numwords-1 downto 0) of std_logic_vector(lpm_width-1 downto 0); +type lpm_memory is array(integer range (2**lpm_widthad)-1 downto 0) of std_logic_vector(lpm_width-1 downto 0); + +signal q2, q_tmp, q_reg : std_logic_vector(lpm_width-1 downto 0); +signal address_tmp, address_reg : std_logic_vector(lpm_widthad-1 downto 0); + +begin + + enable_mem: process(memenab, q2) + begin + if (memenab = '1') then + q <= q2; + else + q <= (OTHERS => 'Z'); + end if; + end process; + + sync: process(address, address_reg, q_tmp, q_reg) + begin + if (lpm_address_control = "REGISTERED") then + address_tmp <= address_reg; + else + address_tmp <= address; + end if; + if (lpm_outdata = "REGISTERED") then + q2 <= q_reg; + else + q2 <= q_tmp; + end if; + end process; + + input_reg: process (inclock) + begin + if inclock'event and inclock = '1' then + address_reg <= address; + end if; + end process; + + output_reg: process (outclock) + begin + if outclock'event and outclock = '1' then + q_reg <= q_tmp; + end if; + end process; + + memory: process(memenab, address_tmp) + variable mem_data : lpm_memory; + variable mem_data_tmp : integer := 0; + variable mem_init: boolean := false; + variable i, j, k, lineno : integer := 0; + variable buf: line ; + variable booval: boolean ; + FILE mem_data_file: TEXT IS IN LPM_FILE; + variable base, byte, rec_type, datain, addr, checksum: string(2 downto 1); + variable startadd: string(4 downto 1); + variable ibase: integer := 0; + variable ibyte: integer := 0; + variable istartadd: integer := 0; + variable check_sum_vec, check_sum_vec_tmp: unsigned(7 downto 0); + begin + -- INITIALIZE -- + if NOT(mem_init) then + -- INITIALIZE TO 0 -- + for i in mem_data'LOW to mem_data'HIGH loop + mem_data(i) := (OTHERS => '0'); + end loop; + + if (LPM_FILE = "UNUSED") then + ASSERT FALSE + REPORT "Initialization file not found!" + SEVERITY ERROR; + else + WHILE NOT ENDFILE(mem_data_file) loop + booval := true; + READLINE(mem_data_file, buf); + lineno := lineno + 1; + check_sum_vec := (OTHERS => '0'); + if (buf(buf'LOW) = ':') then + i := 1; + shrink_line(buf, i); + READ(L=>buf, VALUE=>byte, good=>booval); + if not (booval) then + ASSERT FALSE + REPORT "[Line "& int_to_str(lineno) & "]:Illegal Intel Hex Format!" + SEVERITY ERROR; + end if; + ibyte := hex_str_to_int(byte); + check_sum_vec := unsigned(check_sum_vec) + to_unsigned(ibyte, 8); + READ(L=>buf, VALUE=>startadd, good=>booval); + if not (booval) then + ASSERT FALSE + REPORT "[Line "& int_to_str(lineno) & "]:Illegal Intel Hex Format! " + SEVERITY ERROR; + end if; + istartadd := hex_str_to_int(startadd); + addr(2) := startadd(4); + addr(1) := startadd(3); + check_sum_vec := unsigned(check_sum_vec) + to_unsigned(hex_str_to_int(addr), check_sum_vec'length); + addr(2) := startadd(2); + addr(1) := startadd(1); + check_sum_vec := unsigned(check_sum_vec) + to_unsigned(hex_str_to_int(addr), check_sum_vec'length); + READ(L=>buf, VALUE=>rec_type, good=>booval); + if not (booval) then + ASSERT FALSE + REPORT "[Line "& int_to_str(lineno) & "]:Illegal Intel Hex Format! " + SEVERITY ERROR; + end if; + check_sum_vec := unsigned(check_sum_vec) + to_unsigned(hex_str_to_int(rec_type), check_sum_vec'length); + else + ASSERT FALSE + REPORT "[Line "& int_to_str(lineno) & "]:Illegal Intel Hex Format! " + SEVERITY ERROR; + end if; + case rec_type is + when "00"=> -- Data record + i := 0; + k := lpm_width / 8; + if ((lpm_width MOD 8) /= 0) then + k := k + 1; + end if; + -- k = no. of bytes per CAM entry. + while (i < ibyte) loop + mem_data_tmp := 0; + for j in 1 to k loop + READ(L=>buf, VALUE=>datain,good=>booval); -- read in data a byte (2 hex chars) at a time. + if not (booval) then + ASSERT FALSE + REPORT "[Line "& int_to_str(lineno) & "]:Illegal Intel Hex Format! " + SEVERITY ERROR; + end if; + check_sum_vec := unsigned(check_sum_vec) + to_unsigned(hex_str_to_int(datain), check_sum_vec'length); + mem_data_tmp := mem_data_tmp * 256 + hex_str_to_int(datain); + end loop; + i := i + k; + mem_data(ibase + istartadd) := STD_LOGIC_VECTOR(to_unsigned(mem_data_tmp, lpm_width)); + istartadd := istartadd + 1; + end loop; + when "01"=> + exit; + when "02"=> + ibase := 0; + if (ibyte /= 2) then + ASSERT FALSE + REPORT "[Line "& int_to_str(lineno) & "]:Illegal Intel Hex Format for record type 02! " + SEVERITY ERROR; + end if; + for i in 0 to (ibyte-1) loop + READ(L=>buf, VALUE=>base,good=>booval); + ibase := ibase * 256 + hex_str_to_int(base); + if not (booval) then + ASSERT FALSE + REPORT "[Line "& int_to_str(lineno) & "]:Illegal Intel Hex Format! " + SEVERITY ERROR; + end if; + check_sum_vec := unsigned(check_sum_vec) + to_unsigned(hex_str_to_int(base), check_sum_vec'length); + end loop; + ibase := ibase * 16; + when OTHERS => + ASSERT FALSE + REPORT "[Line "& int_to_str(lineno) & "]:Illegal record type in Intel Hex File! " + SEVERITY ERROR; + end case; + READ(L=>buf, VALUE=>checksum,good=>booval); + if not (booval) then + ASSERT FALSE + REPORT "[Line "& int_to_str(lineno) & "]:Checksum is missing! " + SEVERITY ERROR; + end if; + + check_sum_vec := unsigned(not (check_sum_vec)) + 1 ; + check_sum_vec_tmp := to_unsigned(hex_str_to_int(checksum),8); + + if (unsigned(check_sum_vec) /= unsigned(check_sum_vec_tmp)) then + ASSERT FALSE + REPORT "[Line "& int_to_str(lineno) & "]:Incorrect checksum!" + SEVERITY ERROR; + end if; + end loop; + end if; + mem_init := TRUE; + end if; + + -- MEMORY FUNCTION -- + --if memenab = '1' then + q_tmp <= mem_data(to_integer(UNSIGNED(address_tmp))); + --else + -- q_tmp <= (OTHERS => 'Z'); + --end if; + end process; + +end LPM_SYN; + + +--------------------------------------------------------------------------- + + +-- pragma translate_off +configuration lpm_rom_c0 of lpm_rom is + + for lpm_syn + end for; + +end lpm_rom_c0; +-- pragma translate_on diff --git a/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/t48/system/t48_rom-e.vhd b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/t48/system/t48_rom-e.vhd new file mode 100644 index 0000000000000000000000000000000000000000..359159e2f79bea6c6e11cd65a1b9c48c6f7fd751 --- /dev/null +++ b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/t48/system/t48_rom-e.vhd @@ -0,0 +1,57 @@ +------------------------------------------------------------------------------- +-- +-- T8x48 ROM +-- +-- $Id: t48_rom-e.vhd 295 2009-04-01 19:32:48Z arniml $ +-- +-- Copyright (c) 2006 Arnim Laeuger (arniml@opencores.org) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.opencores.org/cvsweb.shtml/t48/ +-- +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; + +entity t48_rom is + + port ( + clk_i : in std_logic; + rom_addr_i : in std_logic_vector(9 downto 0); + rom_data_o : out std_logic_vector(7 downto 0) + ); + +end t48_rom; diff --git a/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/t48/system/t48_rom-struct-a.vhd b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/t48/system/t48_rom-struct-a.vhd new file mode 100644 index 0000000000000000000000000000000000000000..b75eddf321ed5eff5ae99d04610b14373ba64e80 --- /dev/null +++ b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/t48/system/t48_rom-struct-a.vhd @@ -0,0 +1,65 @@ +------------------------------------------------------------------------------- +-- +-- T8x48 ROM +-- +-- $Id: t48_rom-struct-a.vhd 295 2009-04-01 19:32:48Z arniml $ +-- +-- Copyright (c) 2006 Arnim Laeuger (arniml@opencores.org) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.opencores.org/cvsweb.shtml/t48/ +-- +------------------------------------------------------------------------------- + +architecture struct of t48_rom is + + component rom_t48 + port( + Clk : in std_logic; + A : in std_logic_vector(9 downto 0); + D : out std_logic_vector(7 downto 0) + ); + end component; + +begin + + rom_b : rom_t48 + port map ( + Clk => clk_i, + A => rom_addr_i, + D => rom_data_o + ); + +end struct; diff --git a/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/t48/system/t48_rom-struct-c.vhd b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/t48/system/t48_rom-struct-c.vhd new file mode 100644 index 0000000000000000000000000000000000000000..c492056ebcdf316f90c2254445eb305da5c58a17 --- /dev/null +++ b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/t48/system/t48_rom-struct-c.vhd @@ -0,0 +1,23 @@ +------------------------------------------------------------------------------- +-- +-- T8x48 ROM +-- +-- $Id: t48_rom-struct-c.vhd 295 2009-04-01 19:32:48Z arniml $ +-- +-- Copyright (c) 2006, Arnim Laeuger (arniml@opencores.org) +-- +-- All rights reserved +-- +------------------------------------------------------------------------------- + +configuration t48_rom_struct_c0 of t48_rom is + + for struct + + for rom_b: rom_t48 + use configuration work.rom_t48_rtl_c0; + end for; + + end for; + +end t48_rom_struct_c0; diff --git a/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/t48/system/t48_system_comp_pack-p.vhd b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/t48/system/t48_system_comp_pack-p.vhd new file mode 100644 index 0000000000000000000000000000000000000000..e36c7a90d281e05d0c36ac0ff0d5cf90e2f47c50 --- /dev/null +++ b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/t48/system/t48_system_comp_pack-p.vhd @@ -0,0 +1,321 @@ +------------------------------------------------------------------------------- +-- +-- $Id: t48_system_comp_pack-p.vhd 311 2022-12-19 20:58:04Z arniml $ +-- +-- Copyright (c) 2004, Arnim Laeuger (arniml@opencores.org) +-- +-- All rights reserved +-- +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; + +package t48_system_comp_pack is + + component t48_wb_master + port ( + xtal_i : in std_logic; + res_i : in std_logic; + en_clk_o : out std_logic; + ale_i : in std_logic; + rd_n_i : in std_logic; + wr_n_i : in std_logic; + adr_i : in std_logic; + db_bus_i : in std_logic_vector( 7 downto 0); + db_bus_o : out std_logic_vector( 7 downto 0); + wb_cyc_o : out std_logic; + wb_stb_o : out std_logic; + wb_we_o : out std_logic; + wb_adr_o : out std_logic_vector(23 downto 0); + wb_ack_i : in std_logic; + wb_dat_i : in std_logic_vector( 7 downto 0); + wb_dat_o : out std_logic_vector( 7 downto 0) + ); + end component; + + component t8048_notri + generic ( + gate_port_input_g : integer := 1 + ); + + port ( + xtal_i : in std_logic; + xtal_en_i : in std_logic; + reset_n_i : in std_logic; + t0_i : in std_logic; + t0_o : out std_logic; + t0_dir_o : out std_logic; + int_n_i : in std_logic; + ea_i : in std_logic; + rd_n_o : out std_logic; + psen_n_o : out std_logic; + wr_n_o : out std_logic; + ale_o : out std_logic; + db_i : in std_logic_vector( 7 downto 0); + db_o : out std_logic_vector( 7 downto 0); + db_dir_o : out std_logic; + t1_i : in std_logic; + p2_i : in std_logic_vector( 7 downto 0); + p2_o : out std_logic_vector( 7 downto 0); + p2l_low_imp_o : out std_logic; + p2h_low_imp_o : out std_logic; + p1_i : in std_logic_vector( 7 downto 0); + p1_o : out std_logic_vector( 7 downto 0); + p1_low_imp_o : out std_logic; + prog_n_o : out std_logic + ); + end component; + + component t8039_notri + generic ( + gate_port_input_g : integer := 1 + ); + + port ( + xtal_i : in std_logic; + xtal_en_i : in std_logic; + reset_n_i : in std_logic; + t0_i : in std_logic; + t0_o : out std_logic; + t0_dir_o : out std_logic; + int_n_i : in std_logic; + ea_i : in std_logic; + rd_n_o : out std_logic; + psen_n_o : out std_logic; + wr_n_o : out std_logic; + ale_o : out std_logic; + db_i : in std_logic_vector( 7 downto 0); + db_o : out std_logic_vector( 7 downto 0); + db_dir_o : out std_logic; + t1_i : in std_logic; + p2_i : in std_logic_vector( 7 downto 0); + p2_o : out std_logic_vector( 7 downto 0); + p2l_low_imp_o : out std_logic; + p2h_low_imp_o : out std_logic; + p1_i : in std_logic_vector( 7 downto 0); + p1_o : out std_logic_vector( 7 downto 0); + p1_low_imp_o : out std_logic; + prog_n_o : out std_logic + ); + end component; + + component t8050_wb + generic ( + gate_port_input_g : integer := 1 + ); + + port ( + xtal_i : in std_logic; + reset_n_i : in std_logic; + t0_i : in std_logic; + t0_o : out std_logic; + t0_dir_o : out std_logic; + int_n_i : in std_logic; + ea_i : in std_logic; + rd_n_o : out std_logic; + psen_n_o : out std_logic; + wr_n_o : out std_logic; + ale_o : out std_logic; + t1_i : in std_logic; + p2_i : in std_logic_vector( 7 downto 0); + p2_o : out std_logic_vector( 7 downto 0); + p2l_low_imp_o : out std_logic; + p2h_low_imp_o : out std_logic; + p1_i : in std_logic_vector( 7 downto 0); + p1_o : out std_logic_vector( 7 downto 0); + p1_low_imp_o : out std_logic; + prog_n_o : out std_logic; + wb_cyc_o : out std_logic; + wb_stb_o : out std_logic; + wb_we_o : out std_logic; + wb_adr_o : out std_logic_vector(23 downto 0); + wb_ack_i : in std_logic; + wb_dat_i : in std_logic_vector( 7 downto 0); + wb_dat_o : out std_logic_vector( 7 downto 0) + ); + end component; + + component t8048 + port ( + xtal_i : in std_logic; + reset_n_i : in std_logic; + t0_b : inout std_logic; + int_n_i : in std_logic; + ea_i : in std_logic; + rd_n_o : out std_logic; + psen_n_o : out std_logic; + wr_n_o : out std_logic; + ale_o : out std_logic; + db_b : inout std_logic_vector( 7 downto 0); + t1_i : in std_logic; + p2_b : inout std_logic_vector( 7 downto 0); + p1_b : inout std_logic_vector( 7 downto 0); + prog_n_o : out std_logic + ); + end component; + + component t8039 + port ( + xtal_i : in std_logic; + reset_n_i : in std_logic; + t0_b : inout std_logic; + int_n_i : in std_logic; + ea_i : in std_logic; + rd_n_o : out std_logic; + psen_n_o : out std_logic; + wr_n_o : out std_logic; + ale_o : out std_logic; + db_b : inout std_logic_vector( 7 downto 0); + t1_i : in std_logic; + p2_b : inout std_logic_vector( 7 downto 0); + p1_b : inout std_logic_vector( 7 downto 0); + prog_n_o : out std_logic + ); + end component; + + component t8041_notri + generic ( + gate_port_input_g : integer := 1 + ); + + port ( + xtal_i : in std_logic; + xtal_en_i : in std_logic; + reset_n_i : in std_logic; + t0_i : in std_logic; + cs_n_i : in std_logic; + rd_n_i : in std_logic; + a0_i : in std_logic; + wr_n_i : in std_logic; + sync_o : out std_logic; + db_i : in std_logic_vector( 7 downto 0); + db_o : out std_logic_vector( 7 downto 0); + db_dir_o : out std_logic; + t1_i : in std_logic; + p2_i : in std_logic_vector( 7 downto 0); + p2_o : out std_logic_vector( 7 downto 0); + p2l_low_imp_o : out std_logic; + p2h_low_imp_o : out std_logic; + p1_i : in std_logic_vector( 7 downto 0); + p1_o : out std_logic_vector( 7 downto 0); + p1_low_imp_o : out std_logic; + prog_n_o : out std_logic + ); + end component; + + component t8041 + port ( + xtal_i : in std_logic; + reset_n_i : in std_logic; + t0_i : in std_logic; + cs_n_i : in std_logic; + rd_n_i : in std_logic; + a0_i : in std_logic; + wr_n_i : in std_logic; + sync_o : out std_logic; + db_b : inout std_logic_vector( 7 downto 0); + t1_i : in std_logic; + p2_b : inout std_logic_vector( 7 downto 0); + p1_b : inout std_logic_vector( 7 downto 0); + prog_n_o : out std_logic + ); + end component; + + component t8041a_notri + generic ( + gate_port_input_g : integer := 1 + ); + + port ( + xtal_i : in std_logic; + xtal_en_i : in std_logic; + reset_n_i : in std_logic; + t0_i : in std_logic; + cs_n_i : in std_logic; + rd_n_i : in std_logic; + a0_i : in std_logic; + wr_n_i : in std_logic; + sync_o : out std_logic; + db_i : in std_logic_vector( 7 downto 0); + db_o : out std_logic_vector( 7 downto 0); + db_dir_o : out std_logic; + t1_i : in std_logic; + p2_i : in std_logic_vector( 7 downto 0); + p2_o : out std_logic_vector( 7 downto 0); + p2l_low_imp_o : out std_logic; + p2h_low_imp_o : out std_logic; + p1_i : in std_logic_vector( 7 downto 0); + p1_o : out std_logic_vector( 7 downto 0); + p1_low_imp_o : out std_logic; + prog_n_o : out std_logic + ); + end component; + + component t8041a + port ( + xtal_i : in std_logic; + reset_n_i : in std_logic; + t0_i : in std_logic; + cs_n_i : in std_logic; + rd_n_i : in std_logic; + a0_i : in std_logic; + wr_n_i : in std_logic; + sync_o : out std_logic; + db_b : inout std_logic_vector( 7 downto 0); + t1_i : in std_logic; + p2_b : inout std_logic_vector( 7 downto 0); + p1_b : inout std_logic_vector( 7 downto 0); + prog_n_o : out std_logic + ); + end component; + + component t8042ah_notri + generic ( + gate_port_input_g : integer := 1 + ); + + port ( + xtal_i : in std_logic; + xtal_en_i : in std_logic; + reset_n_i : in std_logic; + t0_i : in std_logic; + cs_n_i : in std_logic; + rd_n_i : in std_logic; + a0_i : in std_logic; + wr_n_i : in std_logic; + sync_o : out std_logic; + db_i : in std_logic_vector( 7 downto 0); + db_o : out std_logic_vector( 7 downto 0); + db_dir_o : out std_logic; + t1_i : in std_logic; + p2_i : in std_logic_vector( 7 downto 0); + p2_o : out std_logic_vector( 7 downto 0); + p2l_low_imp_o : out std_logic; + p2h_low_imp_o : out std_logic; + p1_i : in std_logic_vector( 7 downto 0); + p1_o : out std_logic_vector( 7 downto 0); + p1_low_imp_o : out std_logic; + prog_n_o : out std_logic + ); + end component; + + component t8042ah + port ( + xtal_i : in std_logic; + reset_n_i : in std_logic; + t0_i : in std_logic; + cs_n_i : in std_logic; + rd_n_i : in std_logic; + a0_i : in std_logic; + wr_n_i : in std_logic; + sync_o : out std_logic; + db_b : inout std_logic_vector( 7 downto 0); + t1_i : in std_logic; + p2_b : inout std_logic_vector( 7 downto 0); + p1_b : inout std_logic_vector( 7 downto 0); + prog_n_o : out std_logic + ); + end component; + +end t48_system_comp_pack; diff --git a/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/t48/system/t49_rom-e.vhd b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/t48/system/t49_rom-e.vhd new file mode 100644 index 0000000000000000000000000000000000000000..7a8f6f5825746ad70a5b0f65bb4cdcf4fe50563a --- /dev/null +++ b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/t48/system/t49_rom-e.vhd @@ -0,0 +1,57 @@ +------------------------------------------------------------------------------- +-- +-- T8x49 ROM +-- +-- $Id: t49_rom-e.vhd 295 2009-04-01 19:32:48Z arniml $ +-- +-- Copyright (c) 2006 Arnim Laeuger (arniml@opencores.org) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.opencores.org/cvsweb.shtml/t48/ +-- +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; + +entity t49_rom is + + port ( + clk_i : in std_logic; + rom_addr_i : in std_logic_vector(10 downto 0); + rom_data_o : out std_logic_vector( 7 downto 0) + ); + +end t49_rom; diff --git a/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/t48/system/t49_rom-struct-a.vhd b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/t48/system/t49_rom-struct-a.vhd new file mode 100644 index 0000000000000000000000000000000000000000..25b6cd53fa4e988a27f46b86b514869bc491fae6 --- /dev/null +++ b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/t48/system/t49_rom-struct-a.vhd @@ -0,0 +1,65 @@ +------------------------------------------------------------------------------- +-- +-- T8x49 ROM +-- +-- $Id: t49_rom-struct-a.vhd 295 2009-04-01 19:32:48Z arniml $ +-- +-- Copyright (c) 2006 Arnim Laeuger (arniml@opencores.org) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.opencores.org/cvsweb.shtml/t48/ +-- +------------------------------------------------------------------------------- + +architecture struct of t49_rom is + + component rom_t49 + port( + Clk : in std_logic; + A : in std_logic_vector(10 downto 0); + D : out std_logic_vector( 7 downto 0) + ); + end component; + +begin + + rom_b : rom_t49 + port map ( + Clk => clk_i, + A => rom_addr_i, + D => rom_data_o + ); + +end struct; diff --git a/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/t48/system/t49_rom-struct-c.vhd b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/t48/system/t49_rom-struct-c.vhd new file mode 100644 index 0000000000000000000000000000000000000000..e70e28c83d19fdc3cfff470443c84f631a764078 --- /dev/null +++ b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/t48/system/t49_rom-struct-c.vhd @@ -0,0 +1,23 @@ +------------------------------------------------------------------------------- +-- +-- T8x49 ROM +-- +-- $Id: t49_rom-struct-c.vhd 295 2009-04-01 19:32:48Z arniml $ +-- +-- Copyright (c) 2006, Arnim Laeuger (arniml@opencores.org) +-- +-- All rights reserved +-- +------------------------------------------------------------------------------- + +configuration t49_rom_struct_c0 of t49_rom is + + for struct + + for rom_b: rom_t49 + use configuration work.rom_t49_rtl_c0; + end for; + + end for; + +end t49_rom_struct_c0; diff --git a/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/t48/system/t8039-c.vhd b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/t48/system/t8039-c.vhd new file mode 100644 index 0000000000000000000000000000000000000000..9fcd7bffa4e74d2d8d639f356ba4b3a46b86e820 --- /dev/null +++ b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/t48/system/t8039-c.vhd @@ -0,0 +1,23 @@ +------------------------------------------------------------------------------- +-- +-- T8039 Microcontroller System +-- +-- $Id: t8039-c.vhd 295 2009-04-01 19:32:48Z arniml $ +-- +-- Copyright (c) 2004, Arnim Laeuger (arniml@opencores.org) +-- +-- All rights reserved +-- +------------------------------------------------------------------------------- + +configuration t8039_struct_c0 of t8039 is + + for struct + + for t8039_notri_b : t8039_notri + use configuration work.t8039_notri_struct_c0; + end for; + + end for; + +end t8039_struct_c0; diff --git a/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/t48/system/t8039.vhd b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/t48/system/t8039.vhd new file mode 100644 index 0000000000000000000000000000000000000000..eef0fc9887ec756f9ae834a3c22b96b0ba02ce38 --- /dev/null +++ b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/t48/system/t8039.vhd @@ -0,0 +1,182 @@ +------------------------------------------------------------------------------- +-- +-- T8039 Microcontroller System +-- +-- $Id: t8039.vhd 295 2009-04-01 19:32:48Z arniml $ +-- +-- Copyright (c) 2004, Arnim Laeuger (arniml@opencores.org) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.opencores.org/cvsweb.shtml/t48/ +-- +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; + +entity t8039 is + + port ( + xtal_i : in std_logic; + reset_n_i : in std_logic; + t0_b : inout std_logic; + int_n_i : in std_logic; + ea_i : in std_logic; + rd_n_o : out std_logic; + psen_n_o : out std_logic; + wr_n_o : out std_logic; + ale_o : out std_logic; + db_b : inout std_logic_vector( 7 downto 0); + t1_i : in std_logic; + p2_b : inout std_logic_vector( 7 downto 0); + p1_b : inout std_logic_vector( 7 downto 0); + prog_n_o : out std_logic + ); + +end t8039; + + +use work.t48_system_comp_pack.t8039_notri; + +architecture struct of t8039 is + + signal t0_s : std_logic; + signal t0_dir_s : std_logic; + signal db_s : std_logic_vector( 7 downto 0); + signal db_dir_s : std_logic; + signal p2_s : std_logic_vector( 7 downto 0); + signal p2l_low_imp_s : std_logic; + signal p2h_low_imp_s : std_logic; + signal p1_s : std_logic_vector( 7 downto 0); + signal p1_low_imp_s : std_logic; + + signal vdd_s : std_logic; + +begin + + vdd_s <= '1'; + + t8039_notri_b : t8039_notri + generic map ( + -- we don't need explicit gating of input ports + -- this is done implicitely by the bidirectional pads + gate_port_input_g => 0 + ) + + port map ( + xtal_i => xtal_i, + xtal_en_i => vdd_s, + reset_n_i => reset_n_i, + t0_i => t0_b, + t0_o => t0_s, + t0_dir_o => t0_dir_s, + int_n_i => int_n_i, + ea_i => ea_i, + rd_n_o => rd_n_o, + psen_n_o => psen_n_o, + wr_n_o => wr_n_o, + ale_o => ale_o, + db_i => db_b, + db_o => db_s, + db_dir_o => db_dir_s, + t1_i => t1_i, + p2_i => p2_b, + p2_o => p2_s, + p2l_low_imp_o => p2l_low_imp_s, + p2h_low_imp_o => p2h_low_imp_s, + p1_i => p1_b, + p1_o => p1_s, + p1_low_imp_o => p1_low_imp_s, + prog_n_o => prog_n_o + ); + + ----------------------------------------------------------------------------- + -- Process bidirs + -- + -- Purpose: + -- Assign bidirectional signals. + -- + bidirs: process (t0_b, t0_s, t0_dir_s, + db_b, db_s, db_dir_s, + p1_b, p1_s, p1_low_imp_s, + p2_b, p2_s, p2l_low_imp_s, p2h_low_imp_s) + + function port_bidir_f(port_value : in std_logic_vector; + low_imp : in std_logic) return std_logic_vector is + variable result_v : std_logic_vector(port_value'range); + begin + for idx in port_value'high downto port_value'low loop + if low_imp = '1' then + result_v(idx) := port_value(idx); + elsif port_value(idx) = '0' then + result_v(idx) := '0'; + else + result_v(idx) := 'Z'; + end if; + end loop; + + return result_v; + end; + + begin + -- Test 0 ----------------------------------------------------------------- + if t0_dir_s = '1' then + t0_b <= t0_s; + else + t0_b <= 'Z'; + end if; + + -- Data Bus --------------------------------------------------------------- + if db_dir_s = '1' then + db_b <= db_s; + else + db_b <= (others => 'Z'); + end if; + + -- Port 1 ----------------------------------------------------------------- + p1_b <= port_bidir_f(port_value => p1_s, + low_imp => p1_low_imp_s); + + -- Port 2 ----------------------------------------------------------------- + p2_b(3 downto 0) <= port_bidir_f(port_value => p2_s(3 downto 0), + low_imp => p2l_low_imp_s); + p2_b(7 downto 4) <= port_bidir_f(port_value => p2_s(7 downto 4), + low_imp => p2h_low_imp_s); + + end process bidirs; + -- + ----------------------------------------------------------------------------- + +end struct; diff --git a/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/t48/system/t8039_notri-c.vhd b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/t48/system/t8039_notri-c.vhd new file mode 100644 index 0000000000000000000000000000000000000000..b39c43e6c4a1b45d5fbc7628b9dcbc9b118128f8 --- /dev/null +++ b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/t48/system/t8039_notri-c.vhd @@ -0,0 +1,28 @@ +------------------------------------------------------------------------------- +-- +-- T8039 Microcontroller System +-- 8039 toplevel without tri-states +-- +-- $Id: t8039_notri-c.vhd 295 2009-04-01 19:32:48Z arniml $ +-- +-- Copyright (c) 2004, Arnim Laeuger (arniml@opencores.org) +-- +-- All rights reserved +-- +------------------------------------------------------------------------------- + +configuration t8039_notri_struct_c0 of t8039_notri is + + for struct + + for ram_128_b : generic_ram_ena + use configuration work.generic_ram_ena_rtl_c0; + end for; + + for t48_core_b : t48_core + use configuration work.t48_core_struct_c0; + end for; + + end for; + +end t8039_notri_struct_c0; diff --git a/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/t48/system/t8039_notri.vhd b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/t48/system/t8039_notri.vhd new file mode 100644 index 0000000000000000000000000000000000000000..502ce4507087a8b2f8ec75ef4ccd824c090d4c8c --- /dev/null +++ b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/t48/system/t8039_notri.vhd @@ -0,0 +1,204 @@ +------------------------------------------------------------------------------- +-- +-- T8039 Microcontroller System +-- 8039 toplevel without tri-states +-- +-- $Id: t8039_notri.vhd 295 2009-04-01 19:32:48Z arniml $ +-- +-- Copyright (c) 2004, Arnim Laeuger (arniml@opencores.org) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.opencores.org/cvsweb.shtml/t48/ +-- +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; + +entity t8039_notri is + + generic ( + gate_port_input_g : integer := 1 + ); + + port ( + xtal_i : in std_logic; + xtal_en_i : in std_logic; + reset_n_i : in std_logic; + t0_i : in std_logic; + t0_o : out std_logic; + t0_dir_o : out std_logic; + int_n_i : in std_logic; + ea_i : in std_logic; + rd_n_o : out std_logic; + psen_n_o : out std_logic; + wr_n_o : out std_logic; + ale_o : out std_logic; + db_i : in std_logic_vector( 7 downto 0); + db_o : out std_logic_vector( 7 downto 0); + db_dir_o : out std_logic; + t1_i : in std_logic; + p2_i : in std_logic_vector( 7 downto 0); + p2_o : out std_logic_vector( 7 downto 0); + p2l_low_imp_o : out std_logic; + p2h_low_imp_o : out std_logic; + p1_i : in std_logic_vector( 7 downto 0); + p1_o : out std_logic_vector( 7 downto 0); + p1_low_imp_o : out std_logic; + prog_n_o : out std_logic + ); + +end t8039_notri; + + +library ieee; +use ieee.numeric_std.all; + +use work.t48_core_comp_pack.t48_core; +use work.t48_core_comp_pack.generic_ram_ena; + +architecture struct of t8039_notri is + + signal xtal3_s : std_logic; + signal dmem_addr_s : std_logic_vector( 7 downto 0); + signal dmem_we_s : std_logic; + signal dmem_data_from_s : std_logic_vector( 7 downto 0); + signal dmem_data_to_s : std_logic_vector( 7 downto 0); + signal pmem_data_s : std_logic_vector( 7 downto 0); + + signal p1_in_s, + p1_out_s : std_logic_vector( 7 downto 0); + signal p2_in_s, + p2_out_s : std_logic_vector( 7 downto 0); + + signal vdd_s : std_logic; + +begin + + vdd_s <= '1'; + + ----------------------------------------------------------------------------- + -- Check generics for valid values. + ----------------------------------------------------------------------------- + -- pragma translate_off + assert gate_port_input_g = 0 or gate_port_input_g = 1 + report "gate_port_input_g must be either 1 or 0!" + severity failure; + -- pragma translate_on + + + -- no Program memory available + pmem_data_s <= (others => '0'); + + + t48_core_b : t48_core + generic map ( + xtal_div_3_g => 1, + register_mnemonic_g => 1, + include_port1_g => 1, + include_port2_g => 1, + include_bus_g => 1, + include_timer_g => 1, + sample_t1_state_g => 4 + ) + port map ( + xtal_i => xtal_i, + xtal_en_i => xtal_en_i, + reset_i => reset_n_i, + t0_i => t0_i, + t0_o => t0_o, + t0_dir_o => t0_dir_o, + int_n_i => int_n_i, + ea_i => ea_i, + rd_n_o => rd_n_o, + psen_n_o => psen_n_o, + wr_n_o => wr_n_o, + ale_o => ale_o, + db_i => db_i, + db_o => db_o, + db_dir_o => db_dir_o, + t1_i => t1_i, + p2_i => p2_in_s, + p2_o => p2_out_s, + p2l_low_imp_o => p2l_low_imp_o, + p2h_low_imp_o => p2h_low_imp_o, + p1_i => p1_in_s, + p1_o => p1_out_s, + p1_low_imp_o => p1_low_imp_o, + prog_n_o => prog_n_o, + clk_i => xtal_i, + en_clk_i => xtal3_s, + xtal3_o => xtal3_s, + dmem_addr_o => dmem_addr_s, + dmem_we_o => dmem_we_s, + dmem_data_i => dmem_data_from_s, + dmem_data_o => dmem_data_to_s, + pmem_addr_o => open, + pmem_data_i => pmem_data_s + ); + + + ----------------------------------------------------------------------------- + -- Gate port 1 and 2 input bus with respetive output value + ----------------------------------------------------------------------------- + gate_ports: if gate_port_input_g = 1 generate + p1_in_s <= p1_i and p1_out_s; + p2_in_s <= p2_i and p2_out_s; + end generate; + + pass_ports: if gate_port_input_g = 0 generate + p1_in_s <= p1_i; + p2_in_s <= p2_i; + end generate; + + p1_o <= p1_out_s; + p2_o <= p2_out_s; + + + ram_128_b : generic_ram_ena + generic map ( + addr_width_g => 7, + data_width_g => 8 + ) + port map ( + clk_i => xtal_i, + a_i => dmem_addr_s(6 downto 0), + we_i => dmem_we_s, + ena_i => vdd_s, + d_i => dmem_data_to_s, + d_o => dmem_data_from_s + ); + +end struct; diff --git a/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/t48/system/t8041-c.vhd b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/t48/system/t8041-c.vhd new file mode 100644 index 0000000000000000000000000000000000000000..2d9b94091f810a5e80723ab7212e6557339ae150 --- /dev/null +++ b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/t48/system/t8041-c.vhd @@ -0,0 +1,21 @@ +------------------------------------------------------------------------------- +-- +-- T8041 Microcontroller System +-- +-- Copyright (c) 2004-2022, Arnim Laeuger (arniml@opencores.org) +-- +-- All rights reserved +-- +------------------------------------------------------------------------------- + +configuration t8041_struct_c0 of t8041 is + + for struct + + for t8041_notri_b : t8041_notri + use configuration work.t8041_notri_struct_c0; + end for; + + end for; + +end t8041_struct_c0; diff --git a/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/t48/system/t8041.vhd b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/t48/system/t8041.vhd new file mode 100644 index 0000000000000000000000000000000000000000..df7c03e334ac284beedd8725a816e9e6cc778454 --- /dev/null +++ b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/t48/system/t8041.vhd @@ -0,0 +1,170 @@ +------------------------------------------------------------------------------- +-- +-- T8041 Microcontroller System +-- +-- Copyright (c) 2004-2022, Arnim Laeuger (arniml@opencores.org) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.opencores.org/cvsweb.shtml/t48/ +-- +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; + +entity t8041 is + + port ( + xtal_i : in std_logic; + reset_n_i : in std_logic; + t0_i : in std_logic; + cs_n_i : in std_logic; + rd_n_i : in std_logic; + a0_i : in std_logic; + wr_n_i : in std_logic; + sync_o : out std_logic; + db_b : inout std_logic_vector( 7 downto 0); + t1_i : in std_logic; + p2_b : inout std_logic_vector( 7 downto 0); + p1_b : inout std_logic_vector( 7 downto 0); + prog_n_o : out std_logic + ); + +end t8041; + + +library ieee; +use ieee.numeric_std.all; + +use work.t48_system_comp_pack.t8041_notri; + +architecture struct of t8041 is + + signal db_s : std_logic_vector( 7 downto 0); + signal db_dir_s : std_logic; + signal p2_s : std_logic_vector( 7 downto 0); + signal p2l_low_imp_s : std_logic; + signal p2h_low_imp_s : std_logic; + signal p1_s : std_logic_vector( 7 downto 0); + signal p1_low_imp_s : std_logic; + + signal vdd_s : std_logic; + +begin + + vdd_s <= '1'; + + t8041_notri_b : t8041_notri + generic map ( + -- we don't need explicit gating of input ports + -- this is done implicitely by the bidirectional pads + gate_port_input_g => 0 + ) + + port map ( + xtal_i => xtal_i, + xtal_en_i => vdd_s, + reset_n_i => reset_n_i, + t0_i => t0_i, + cs_n_i => cs_n_i, + rd_n_i => rd_n_i, + a0_i => a0_i, + wr_n_i => wr_n_i, + sync_o => sync_o, + db_i => db_b, + db_o => db_s, + db_dir_o => db_dir_s, + t1_i => t1_i, + p2_i => p2_b, + p2_o => p2_s, + p2l_low_imp_o => p2l_low_imp_s, + p2h_low_imp_o => p2h_low_imp_s, + p1_i => p1_b, + p1_o => p1_s, + p1_low_imp_o => p1_low_imp_s, + prog_n_o => prog_n_o + ); + + ----------------------------------------------------------------------------- + -- Process bidirs + -- + -- Purpose: + -- Assign bidirectional signals. + -- + bidirs: process (db_b, db_s, db_dir_s, + p1_b, p1_s, p1_low_imp_s, + p2_b, p2_s, p2l_low_imp_s, p2h_low_imp_s) + + function port_bidir_f(port_value : in std_logic_vector; + low_imp : in std_logic) return std_logic_vector is + variable result_v : std_logic_vector(port_value'range); + begin + for idx in port_value'high downto port_value'low loop + if low_imp = '1' then + result_v(idx) := port_value(idx); + elsif port_value(idx) = '0' then + result_v(idx) := '0'; + else + result_v(idx) := 'Z'; + end if; + end loop; + + return result_v; + end; + + begin + -- Data Bus --------------------------------------------------------------- + if db_dir_s = '1' then + db_b <= db_s; + else + db_b <= (others => 'Z'); + end if; + + -- Port 1 ----------------------------------------------------------------- + p1_b <= port_bidir_f(port_value => p1_s, + low_imp => p1_low_imp_s); + + -- Port 2 ----------------------------------------------------------------- + p2_b(3 downto 0) <= port_bidir_f(port_value => p2_s(3 downto 0), + low_imp => p2l_low_imp_s); + p2_b(7 downto 4) <= port_bidir_f(port_value => p2_s(7 downto 4), + low_imp => p2h_low_imp_s); + + end process bidirs; + -- + ----------------------------------------------------------------------------- + + +end struct; diff --git a/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/t48/system/t8041_notri-c.vhd b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/t48/system/t8041_notri-c.vhd new file mode 100644 index 0000000000000000000000000000000000000000..14bd9363b71c67adb1f2bd8ffb4c1e4bbc5d097e --- /dev/null +++ b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/t48/system/t8041_notri-c.vhd @@ -0,0 +1,29 @@ +------------------------------------------------------------------------------- +-- +-- T8041 Microcontroller System +-- +-- Copyright (c) 2004-2022, Arnim Laeuger (arniml@opencores.org) +-- +-- All rights reserved +-- +------------------------------------------------------------------------------- + +configuration t8041_notri_struct_c0 of t8041_notri is + + for struct + + for rom_1k_b : t48_rom + use configuration work.t48_rom_lpm_c0; + end for; + + for ram_64_b : generic_ram_ena + use configuration work.generic_ram_ena_rtl_c0; + end for; + + for upi41_core_b : upi41_core + use configuration work.upi41_core_struct_c0; + end for; + + end for; + +end t8041_notri_struct_c0; diff --git a/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/t48/system/t8041_notri.vhd b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/t48/system/t8041_notri.vhd new file mode 100644 index 0000000000000000000000000000000000000000..f195d0c5e74fe9428786f0d7ce2973065bb7cbb6 --- /dev/null +++ b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/t48/system/t8041_notri.vhd @@ -0,0 +1,202 @@ +------------------------------------------------------------------------------- +-- +-- T8041 Microcontroller System +-- 8041 toplevel without tri-states +-- +-- Copyright (c) 2004-2022, Arnim Laeuger (arniml@opencores.org) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.opencores.org/cvsweb.shtml/t48/ +-- +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; + +entity t8041_notri is + + generic ( + gate_port_input_g : integer := 1 + ); + + port ( + xtal_i : in std_logic; + xtal_en_i : in std_logic; + reset_n_i : in std_logic; + t0_i : in std_logic; + cs_n_i : in std_logic; + rd_n_i : in std_logic; + a0_i : in std_logic; + wr_n_i : in std_logic; + sync_o : out std_logic; + db_i : in std_logic_vector( 7 downto 0); + db_o : out std_logic_vector( 7 downto 0); + db_dir_o : out std_logic; + t1_i : in std_logic; + p2_i : in std_logic_vector( 7 downto 0); + p2_o : out std_logic_vector( 7 downto 0); + p2l_low_imp_o : out std_logic; + p2h_low_imp_o : out std_logic; + p1_i : in std_logic_vector( 7 downto 0); + p1_o : out std_logic_vector( 7 downto 0); + p1_low_imp_o : out std_logic; + prog_n_o : out std_logic + ); + +end t8041_notri; + + +library ieee; +use ieee.numeric_std.all; + +use work.t48_core_comp_pack.upi41_core; +use work.t48_core_comp_pack.t48_rom; +use work.t48_core_comp_pack.generic_ram_ena; + +architecture struct of t8041_notri is + + -- Address width of internal ROM + constant rom_addr_width_c : natural := 10; + + signal xtal3_s : std_logic; + signal dmem_addr_s : std_logic_vector( 7 downto 0); + signal dmem_we_s : std_logic; + signal dmem_data_from_s : std_logic_vector( 7 downto 0); + signal dmem_data_to_s : std_logic_vector( 7 downto 0); + signal pmem_addr_s : std_logic_vector(10 downto 0); + signal pmem_data_s : std_logic_vector( 7 downto 0); + + signal p1_in_s, + p1_out_s : std_logic_vector( 7 downto 0); + signal p2_in_s, + p2_out_s : std_logic_vector( 7 downto 0); + + signal vdd_s : std_logic; + +begin + + vdd_s <= '1'; + + ----------------------------------------------------------------------------- + -- Check generics for valid values. + ----------------------------------------------------------------------------- + -- pragma translate_off + assert gate_port_input_g = 0 or gate_port_input_g = 1 + report "gate_port_input_g must be either 1 or 0!" + severity failure; + -- pragma translate_on + + + upi41_core_b : upi41_core + generic map ( + xtal_div_3_g => 1, + register_mnemonic_g => 1, + sample_t1_state_g => 4, + is_upi_type_a_g => 0 + ) + + port map ( + xtal_i => xtal_i, + xtal_en_i => xtal_en_i, + reset_i => reset_n_i, + t0_i => t0_i, + cs_n_i => cs_n_i, + rd_n_i => rd_n_i, + a0_i => a0_i, + wr_n_i => wr_n_i, + sync_o => sync_o, + db_i => db_i, + db_o => db_o, + db_dir_o => db_dir_o, + t1_i => t1_i, + p2_i => p2_in_s, + p2_o => p2_out_s, + p2l_low_imp_o => p2l_low_imp_o, + p2h_low_imp_o => p2h_low_imp_o, + p1_i => p1_in_s, + p1_o => p1_out_s, + p1_low_imp_o => p1_low_imp_o, + prog_n_o => prog_n_o, + clk_i => xtal_i, + en_clk_i => xtal3_s, + xtal3_o => xtal3_s, + dmem_addr_o => dmem_addr_s, + dmem_we_o => dmem_we_s, + dmem_data_i => dmem_data_from_s, + dmem_data_o => dmem_data_to_s, + pmem_addr_o => pmem_addr_s, + pmem_data_i => pmem_data_s + ); + + + ----------------------------------------------------------------------------- + -- Gate port 1 and 2 input bus with respetive output value + ----------------------------------------------------------------------------- + gate_ports: if gate_port_input_g = 1 generate + p1_in_s <= p1_i and p1_out_s; + p2_in_s <= p2_i and p2_out_s; + end generate; + + pass_ports: if gate_port_input_g = 0 generate + p1_in_s <= p1_i; + p2_in_s <= p2_i; + end generate; + + p1_o <= p1_out_s; + p2_o <= p2_out_s; + + + rom_1k_b : t48_rom + port map ( + clk_i => xtal_i, + rom_addr_i => pmem_addr_s(rom_addr_width_c-1 downto 0), + rom_data_o => pmem_data_s + ); + + ram_64_b : generic_ram_ena + generic map ( + addr_width_g => 6, + data_width_g => 8 + ) + port map ( + clk_i => xtal_i, + a_i => dmem_addr_s(5 downto 0), + we_i => dmem_we_s, + ena_i => vdd_s, + d_i => dmem_data_to_s, + d_o => dmem_data_from_s + ); + +end struct; diff --git a/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/t48/system/t8041a-c.vhd b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/t48/system/t8041a-c.vhd new file mode 100644 index 0000000000000000000000000000000000000000..86b422c08cd01986433a9967ddc5cfbca87cc3de --- /dev/null +++ b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/t48/system/t8041a-c.vhd @@ -0,0 +1,21 @@ +------------------------------------------------------------------------------- +-- +-- T8041A Microcontroller System +-- +-- Copyright (c) 2004-2022, Arnim Laeuger (arniml@opencores.org) +-- +-- All rights reserved +-- +------------------------------------------------------------------------------- + +configuration t8041a_struct_c0 of t8041a is + + for struct + + for t8041a_notri_b : t8041a_notri + use configuration work.t8041a_notri_struct_c0; + end for; + + end for; + +end t8041a_struct_c0; diff --git a/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/t48/system/t8041a.vhd b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/t48/system/t8041a.vhd new file mode 100644 index 0000000000000000000000000000000000000000..6b1f5a1609e0ee0e937551d8584e41fa3bcb9b31 --- /dev/null +++ b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/t48/system/t8041a.vhd @@ -0,0 +1,170 @@ +------------------------------------------------------------------------------- +-- +-- T8041A Microcontroller System +-- +-- Copyright (c) 2004-2022, Arnim Laeuger (arniml@opencores.org) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.opencores.org/cvsweb.shtml/t48/ +-- +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; + +entity t8041a is + + port ( + xtal_i : in std_logic; + reset_n_i : in std_logic; + t0_i : in std_logic; + cs_n_i : in std_logic; + rd_n_i : in std_logic; + a0_i : in std_logic; + wr_n_i : in std_logic; + sync_o : out std_logic; + db_b : inout std_logic_vector( 7 downto 0); + t1_i : in std_logic; + p2_b : inout std_logic_vector( 7 downto 0); + p1_b : inout std_logic_vector( 7 downto 0); + prog_n_o : out std_logic + ); + +end t8041a; + + +library ieee; +use ieee.numeric_std.all; + +use work.t48_system_comp_pack.t8041a_notri; + +architecture struct of t8041a is + + signal db_s : std_logic_vector( 7 downto 0); + signal db_dir_s : std_logic; + signal p2_s : std_logic_vector( 7 downto 0); + signal p2l_low_imp_s : std_logic; + signal p2h_low_imp_s : std_logic; + signal p1_s : std_logic_vector( 7 downto 0); + signal p1_low_imp_s : std_logic; + + signal vdd_s : std_logic; + +begin + + vdd_s <= '1'; + + t8041a_notri_b : t8041a_notri + generic map ( + -- we don't need explicit gating of input ports + -- this is done implicitely by the bidirectional pads + gate_port_input_g => 0 + ) + + port map ( + xtal_i => xtal_i, + xtal_en_i => vdd_s, + reset_n_i => reset_n_i, + t0_i => t0_i, + cs_n_i => cs_n_i, + rd_n_i => rd_n_i, + a0_i => a0_i, + wr_n_i => wr_n_i, + sync_o => sync_o, + db_i => db_b, + db_o => db_s, + db_dir_o => db_dir_s, + t1_i => t1_i, + p2_i => p2_b, + p2_o => p2_s, + p2l_low_imp_o => p2l_low_imp_s, + p2h_low_imp_o => p2h_low_imp_s, + p1_i => p1_b, + p1_o => p1_s, + p1_low_imp_o => p1_low_imp_s, + prog_n_o => prog_n_o + ); + + ----------------------------------------------------------------------------- + -- Process bidirs + -- + -- Purpose: + -- Assign bidirectional signals. + -- + bidirs: process (db_b, db_s, db_dir_s, + p1_b, p1_s, p1_low_imp_s, + p2_b, p2_s, p2l_low_imp_s, p2h_low_imp_s) + + function port_bidir_f(port_value : in std_logic_vector; + low_imp : in std_logic) return std_logic_vector is + variable result_v : std_logic_vector(port_value'range); + begin + for idx in port_value'high downto port_value'low loop + if low_imp = '1' then + result_v(idx) := port_value(idx); + elsif port_value(idx) = '0' then + result_v(idx) := '0'; + else + result_v(idx) := 'Z'; + end if; + end loop; + + return result_v; + end; + + begin + -- Data Bus --------------------------------------------------------------- + if db_dir_s = '1' then + db_b <= db_s; + else + db_b <= (others => 'Z'); + end if; + + -- Port 1 ----------------------------------------------------------------- + p1_b <= port_bidir_f(port_value => p1_s, + low_imp => p1_low_imp_s); + + -- Port 2 ----------------------------------------------------------------- + p2_b(3 downto 0) <= port_bidir_f(port_value => p2_s(3 downto 0), + low_imp => p2l_low_imp_s); + p2_b(7 downto 4) <= port_bidir_f(port_value => p2_s(7 downto 4), + low_imp => p2h_low_imp_s); + + end process bidirs; + -- + ----------------------------------------------------------------------------- + + +end struct; diff --git a/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/t48/system/t8041a_notri-c.vhd b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/t48/system/t8041a_notri-c.vhd new file mode 100644 index 0000000000000000000000000000000000000000..d2b74949e3c809e0f7999c4afcd0078c65443ebc --- /dev/null +++ b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/t48/system/t8041a_notri-c.vhd @@ -0,0 +1,29 @@ +------------------------------------------------------------------------------- +-- +-- T8041A Microcontroller System +-- +-- Copyright (c) 2004-2022, Arnim Laeuger (arniml@opencores.org) +-- +-- All rights reserved +-- +------------------------------------------------------------------------------- + +configuration t8041a_notri_struct_c0 of t8041a_notri is + + for struct + + for rom_1k_b : t48_rom + use configuration work.t48_rom_lpm_c0; + end for; + + for ram_64_b : generic_ram_ena + use configuration work.generic_ram_ena_rtl_c0; + end for; + + for upi41a_core_b : upi41_core + use configuration work.upi41_core_struct_c0; + end for; + + end for; + +end t8041a_notri_struct_c0; diff --git a/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/t48/system/t8041a_notri.vhd b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/t48/system/t8041a_notri.vhd new file mode 100644 index 0000000000000000000000000000000000000000..68b2021e3f39e2139e8431b096dd10cc80b90a9c --- /dev/null +++ b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/t48/system/t8041a_notri.vhd @@ -0,0 +1,202 @@ +------------------------------------------------------------------------------- +-- +-- T8041A Microcontroller System +-- 8041A toplevel without tri-states +-- +-- Copyright (c) 2004-2022, Arnim Laeuger (arniml@opencores.org) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.opencores.org/cvsweb.shtml/t48/ +-- +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; + +entity t8041a_notri is + + generic ( + gate_port_input_g : integer := 1 + ); + + port ( + xtal_i : in std_logic; + xtal_en_i : in std_logic; + reset_n_i : in std_logic; + t0_i : in std_logic; + cs_n_i : in std_logic; + rd_n_i : in std_logic; + a0_i : in std_logic; + wr_n_i : in std_logic; + sync_o : out std_logic; + db_i : in std_logic_vector( 7 downto 0); + db_o : out std_logic_vector( 7 downto 0); + db_dir_o : out std_logic; + t1_i : in std_logic; + p2_i : in std_logic_vector( 7 downto 0); + p2_o : out std_logic_vector( 7 downto 0); + p2l_low_imp_o : out std_logic; + p2h_low_imp_o : out std_logic; + p1_i : in std_logic_vector( 7 downto 0); + p1_o : out std_logic_vector( 7 downto 0); + p1_low_imp_o : out std_logic; + prog_n_o : out std_logic + ); + +end t8041a_notri; + + +library ieee; +use ieee.numeric_std.all; + +use work.t48_core_comp_pack.upi41_core; +use work.t48_core_comp_pack.t48_rom; +use work.t48_core_comp_pack.generic_ram_ena; + +architecture struct of t8041a_notri is + + -- Address width of internal ROM + constant rom_addr_width_c : natural := 10; + + signal xtal3_s : std_logic; + signal dmem_addr_s : std_logic_vector( 7 downto 0); + signal dmem_we_s : std_logic; + signal dmem_data_from_s : std_logic_vector( 7 downto 0); + signal dmem_data_to_s : std_logic_vector( 7 downto 0); + signal pmem_addr_s : std_logic_vector(10 downto 0); + signal pmem_data_s : std_logic_vector( 7 downto 0); + + signal p1_in_s, + p1_out_s : std_logic_vector( 7 downto 0); + signal p2_in_s, + p2_out_s : std_logic_vector( 7 downto 0); + + signal vdd_s : std_logic; + +begin + + vdd_s <= '1'; + + ----------------------------------------------------------------------------- + -- Check generics for valid values. + ----------------------------------------------------------------------------- + -- pragma translate_off + assert gate_port_input_g = 0 or gate_port_input_g = 1 + report "gate_port_input_g must be either 1 or 0!" + severity failure; + -- pragma translate_on + + + upi41a_core_b : upi41_core + generic map ( + xtal_div_3_g => 1, + register_mnemonic_g => 1, + sample_t1_state_g => 4, + is_upi_type_a_g => 1 + ) + + port map ( + xtal_i => xtal_i, + xtal_en_i => xtal_en_i, + reset_i => reset_n_i, + t0_i => t0_i, + cs_n_i => cs_n_i, + rd_n_i => rd_n_i, + a0_i => a0_i, + wr_n_i => wr_n_i, + sync_o => sync_o, + db_i => db_i, + db_o => db_o, + db_dir_o => db_dir_o, + t1_i => t1_i, + p2_i => p2_in_s, + p2_o => p2_out_s, + p2l_low_imp_o => p2l_low_imp_o, + p2h_low_imp_o => p2h_low_imp_o, + p1_i => p1_in_s, + p1_o => p1_out_s, + p1_low_imp_o => p1_low_imp_o, + prog_n_o => prog_n_o, + clk_i => xtal_i, + en_clk_i => xtal3_s, + xtal3_o => xtal3_s, + dmem_addr_o => dmem_addr_s, + dmem_we_o => dmem_we_s, + dmem_data_i => dmem_data_from_s, + dmem_data_o => dmem_data_to_s, + pmem_addr_o => pmem_addr_s, + pmem_data_i => pmem_data_s + ); + + + ----------------------------------------------------------------------------- + -- Gate port 1 and 2 input bus with respetive output value + ----------------------------------------------------------------------------- + gate_ports: if gate_port_input_g = 1 generate + p1_in_s <= p1_i and p1_out_s; + p2_in_s <= p2_i and p2_out_s; + end generate; + + pass_ports: if gate_port_input_g = 0 generate + p1_in_s <= p1_i; + p2_in_s <= p2_i; + end generate; + + p1_o <= p1_out_s; + p2_o <= p2_out_s; + + + rom_1k_b : t48_rom + port map ( + clk_i => xtal_i, + rom_addr_i => pmem_addr_s(rom_addr_width_c-1 downto 0), + rom_data_o => pmem_data_s + ); + + ram_64_b : generic_ram_ena + generic map ( + addr_width_g => 6, + data_width_g => 8 + ) + port map ( + clk_i => xtal_i, + a_i => dmem_addr_s(5 downto 0), + we_i => dmem_we_s, + ena_i => vdd_s, + d_i => dmem_data_to_s, + d_o => dmem_data_from_s + ); + +end struct; diff --git a/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/t48/system/t8042ah-c.vhd b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/t48/system/t8042ah-c.vhd new file mode 100644 index 0000000000000000000000000000000000000000..d973a2b6312615b07b25f6a45b5ea061ab74d34e --- /dev/null +++ b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/t48/system/t8042ah-c.vhd @@ -0,0 +1,21 @@ +------------------------------------------------------------------------------- +-- +-- T8042AH Microcontroller System +-- +-- Copyright (c) 2004-2022, Arnim Laeuger (arniml@opencores.org) +-- +-- All rights reserved +-- +------------------------------------------------------------------------------- + +configuration t8042ah_struct_c0 of t8042ah is + + for struct + + for t8042ah_notri_b : t8042ah_notri + use configuration work.t8042ah_notri_struct_c0; + end for; + + end for; + +end t8042ah_struct_c0; diff --git a/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/t48/system/t8042ah.vhd b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/t48/system/t8042ah.vhd new file mode 100644 index 0000000000000000000000000000000000000000..edf24b3873573958f2de3cb67a645feb6d076f67 --- /dev/null +++ b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/t48/system/t8042ah.vhd @@ -0,0 +1,170 @@ +------------------------------------------------------------------------------- +-- +-- T8042AH Microcontroller System +-- +-- Copyright (c) 2004-2022, Arnim Laeuger (arniml@opencores.org) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.opencores.org/cvsweb.shtml/t48/ +-- +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; + +entity t8042ah is + + port ( + xtal_i : in std_logic; + reset_n_i : in std_logic; + t0_i : in std_logic; + cs_n_i : in std_logic; + rd_n_i : in std_logic; + a0_i : in std_logic; + wr_n_i : in std_logic; + sync_o : out std_logic; + db_b : inout std_logic_vector( 7 downto 0); + t1_i : in std_logic; + p2_b : inout std_logic_vector( 7 downto 0); + p1_b : inout std_logic_vector( 7 downto 0); + prog_n_o : out std_logic + ); + +end t8042ah; + + +library ieee; +use ieee.numeric_std.all; + +use work.t48_system_comp_pack.t8042ah_notri; + +architecture struct of t8042ah is + + signal db_s : std_logic_vector( 7 downto 0); + signal db_dir_s : std_logic; + signal p2_s : std_logic_vector( 7 downto 0); + signal p2l_low_imp_s : std_logic; + signal p2h_low_imp_s : std_logic; + signal p1_s : std_logic_vector( 7 downto 0); + signal p1_low_imp_s : std_logic; + + signal vdd_s : std_logic; + +begin + + vdd_s <= '1'; + + t8042ah_notri_b : t8042ah_notri + generic map ( + -- we don't need explicit gating of input ports + -- this is done implicitely by the bidirectional pads + gate_port_input_g => 0 + ) + + port map ( + xtal_i => xtal_i, + xtal_en_i => vdd_s, + reset_n_i => reset_n_i, + t0_i => t0_i, + cs_n_i => cs_n_i, + rd_n_i => rd_n_i, + a0_i => a0_i, + wr_n_i => wr_n_i, + sync_o => sync_o, + db_i => db_b, + db_o => db_s, + db_dir_o => db_dir_s, + t1_i => t1_i, + p2_i => p2_b, + p2_o => p2_s, + p2l_low_imp_o => p2l_low_imp_s, + p2h_low_imp_o => p2h_low_imp_s, + p1_i => p1_b, + p1_o => p1_s, + p1_low_imp_o => p1_low_imp_s, + prog_n_o => prog_n_o + ); + + ----------------------------------------------------------------------------- + -- Process bidirs + -- + -- Purpose: + -- Assign bidirectional signals. + -- + bidirs: process (db_b, db_s, db_dir_s, + p1_b, p1_s, p1_low_imp_s, + p2_b, p2_s, p2l_low_imp_s, p2h_low_imp_s) + + function port_bidir_f(port_value : in std_logic_vector; + low_imp : in std_logic) return std_logic_vector is + variable result_v : std_logic_vector(port_value'range); + begin + for idx in port_value'high downto port_value'low loop + if low_imp = '1' then + result_v(idx) := port_value(idx); + elsif port_value(idx) = '0' then + result_v(idx) := '0'; + else + result_v(idx) := 'Z'; + end if; + end loop; + + return result_v; + end; + + begin + -- Data Bus --------------------------------------------------------------- + if db_dir_s = '1' then + db_b <= db_s; + else + db_b <= (others => 'Z'); + end if; + + -- Port 1 ----------------------------------------------------------------- + p1_b <= port_bidir_f(port_value => p1_s, + low_imp => p1_low_imp_s); + + -- Port 2 ----------------------------------------------------------------- + p2_b(3 downto 0) <= port_bidir_f(port_value => p2_s(3 downto 0), + low_imp => p2l_low_imp_s); + p2_b(7 downto 4) <= port_bidir_f(port_value => p2_s(7 downto 4), + low_imp => p2h_low_imp_s); + + end process bidirs; + -- + ----------------------------------------------------------------------------- + + +end struct; diff --git a/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/t48/system/t8042ah_notri-c.vhd b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/t48/system/t8042ah_notri-c.vhd new file mode 100644 index 0000000000000000000000000000000000000000..d088e668e2224112c44bf7638beb3982bd305965 --- /dev/null +++ b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/t48/system/t8042ah_notri-c.vhd @@ -0,0 +1,29 @@ +------------------------------------------------------------------------------- +-- +-- T8042AH Microcontroller System +-- +-- Copyright (c) 2004-2022, Arnim Laeuger (arniml@opencores.org) +-- +-- All rights reserved +-- +------------------------------------------------------------------------------- + +configuration t8042ah_notri_struct_c0 of t8042ah_notri is + + for struct + + for rom_2k_b : t49_rom + use configuration work.t49_rom_lpm_c0; + end for; + + for ram_256_b : generic_ram_ena + use configuration work.generic_ram_ena_rtl_c0; + end for; + + for upi41a_core_b : upi41_core + use configuration work.upi41_core_struct_c0; + end for; + + end for; + +end t8042ah_notri_struct_c0; diff --git a/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/t48/system/t8042ah_notri.vhd b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/t48/system/t8042ah_notri.vhd new file mode 100644 index 0000000000000000000000000000000000000000..57c600b3f729960277d82d7b9ed4f3ca6c2d91bb --- /dev/null +++ b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/t48/system/t8042ah_notri.vhd @@ -0,0 +1,202 @@ +------------------------------------------------------------------------------- +-- +-- T8042AH Microcontroller System +-- 8042AH toplevel without tri-states +-- +-- Copyright (c) 2004-2022, Arnim Laeuger (arniml@opencores.org) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.opencores.org/cvsweb.shtml/t48/ +-- +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; + +entity t8042ah_notri is + + generic ( + gate_port_input_g : integer := 1 + ); + + port ( + xtal_i : in std_logic; + xtal_en_i : in std_logic; + reset_n_i : in std_logic; + t0_i : in std_logic; + cs_n_i : in std_logic; + rd_n_i : in std_logic; + a0_i : in std_logic; + wr_n_i : in std_logic; + sync_o : out std_logic; + db_i : in std_logic_vector( 7 downto 0); + db_o : out std_logic_vector( 7 downto 0); + db_dir_o : out std_logic; + t1_i : in std_logic; + p2_i : in std_logic_vector( 7 downto 0); + p2_o : out std_logic_vector( 7 downto 0); + p2l_low_imp_o : out std_logic; + p2h_low_imp_o : out std_logic; + p1_i : in std_logic_vector( 7 downto 0); + p1_o : out std_logic_vector( 7 downto 0); + p1_low_imp_o : out std_logic; + prog_n_o : out std_logic + ); + +end t8042ah_notri; + + +library ieee; +use ieee.numeric_std.all; + +use work.t48_core_comp_pack.upi41_core; +use work.t48_core_comp_pack.t49_rom; +use work.t48_core_comp_pack.generic_ram_ena; + +architecture struct of t8042ah_notri is + + -- Address width of internal ROM + constant rom_addr_width_c : natural := 11; + + signal xtal3_s : std_logic; + signal dmem_addr_s : std_logic_vector( 7 downto 0); + signal dmem_we_s : std_logic; + signal dmem_data_from_s : std_logic_vector( 7 downto 0); + signal dmem_data_to_s : std_logic_vector( 7 downto 0); + signal pmem_addr_s : std_logic_vector(10 downto 0); + signal pmem_data_s : std_logic_vector( 7 downto 0); + + signal p1_in_s, + p1_out_s : std_logic_vector( 7 downto 0); + signal p2_in_s, + p2_out_s : std_logic_vector( 7 downto 0); + + signal vdd_s : std_logic; + +begin + + vdd_s <= '1'; + + ----------------------------------------------------------------------------- + -- Check generics for valid values. + ----------------------------------------------------------------------------- + -- pragma translate_off + assert gate_port_input_g = 0 or gate_port_input_g = 1 + report "gate_port_input_g must be either 1 or 0!" + severity failure; + -- pragma translate_on + + + upi41a_core_b : upi41_core + generic map ( + xtal_div_3_g => 1, + register_mnemonic_g => 1, + sample_t1_state_g => 4, + is_upi_type_a_g => 1 + ) + + port map ( + xtal_i => xtal_i, + xtal_en_i => xtal_en_i, + reset_i => reset_n_i, + t0_i => t0_i, + cs_n_i => cs_n_i, + rd_n_i => rd_n_i, + a0_i => a0_i, + wr_n_i => wr_n_i, + sync_o => sync_o, + db_i => db_i, + db_o => db_o, + db_dir_o => db_dir_o, + t1_i => t1_i, + p2_i => p2_in_s, + p2_o => p2_out_s, + p2l_low_imp_o => p2l_low_imp_o, + p2h_low_imp_o => p2h_low_imp_o, + p1_i => p1_in_s, + p1_o => p1_out_s, + p1_low_imp_o => p1_low_imp_o, + prog_n_o => prog_n_o, + clk_i => xtal_i, + en_clk_i => xtal3_s, + xtal3_o => xtal3_s, + dmem_addr_o => dmem_addr_s, + dmem_we_o => dmem_we_s, + dmem_data_i => dmem_data_from_s, + dmem_data_o => dmem_data_to_s, + pmem_addr_o => pmem_addr_s, + pmem_data_i => pmem_data_s + ); + + + ----------------------------------------------------------------------------- + -- Gate port 1 and 2 input bus with respetive output value + ----------------------------------------------------------------------------- + gate_ports: if gate_port_input_g = 1 generate + p1_in_s <= p1_i and p1_out_s; + p2_in_s <= p2_i and p2_out_s; + end generate; + + pass_ports: if gate_port_input_g = 0 generate + p1_in_s <= p1_i; + p2_in_s <= p2_i; + end generate; + + p1_o <= p1_out_s; + p2_o <= p2_out_s; + + + rom_2k_b : t49_rom + port map ( + clk_i => xtal_i, + rom_addr_i => pmem_addr_s(rom_addr_width_c-1 downto 0), + rom_data_o => pmem_data_s + ); + + ram_256_b : generic_ram_ena + generic map ( + addr_width_g => 8, + data_width_g => 8 + ) + port map ( + clk_i => xtal_i, + a_i => dmem_addr_s, + we_i => dmem_we_s, + ena_i => vdd_s, + d_i => dmem_data_to_s, + d_o => dmem_data_from_s + ); + +end struct; diff --git a/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/t48/system/t8048-c.vhd b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/t48/system/t8048-c.vhd new file mode 100644 index 0000000000000000000000000000000000000000..c79053d1b240214509f2372809e08494ab98feb0 --- /dev/null +++ b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/t48/system/t8048-c.vhd @@ -0,0 +1,23 @@ +------------------------------------------------------------------------------- +-- +-- T8048 Microcontroller System +-- +-- $Id: t8048-c.vhd 295 2009-04-01 19:32:48Z arniml $ +-- +-- Copyright (c) 2004, Arnim Laeuger (arniml@opencores.org) +-- +-- All rights reserved +-- +------------------------------------------------------------------------------- + +configuration t8048_struct_c0 of t8048 is + + for struct + + for t8048_notri_b : t8048_notri + use configuration work.t8048_notri_struct_c0; + end for; + + end for; + +end t8048_struct_c0; diff --git a/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/t48/system/t8048.vhd b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/t48/system/t8048.vhd new file mode 100644 index 0000000000000000000000000000000000000000..1a2e89f9180ce9b510004caaf9db9394fb67e45d --- /dev/null +++ b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/t48/system/t8048.vhd @@ -0,0 +1,186 @@ +------------------------------------------------------------------------------- +-- +-- T8048 Microcontroller System +-- +-- $Id: t8048.vhd 295 2009-04-01 19:32:48Z arniml $ +-- +-- Copyright (c) 2004, Arnim Laeuger (arniml@opencores.org) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.opencores.org/cvsweb.shtml/t48/ +-- +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; + +entity t8048 is + + port ( + xtal_i : in std_logic; + reset_n_i : in std_logic; + t0_b : inout std_logic; + int_n_i : in std_logic; + ea_i : in std_logic; + rd_n_o : out std_logic; + psen_n_o : out std_logic; + wr_n_o : out std_logic; + ale_o : out std_logic; + db_b : inout std_logic_vector( 7 downto 0); + t1_i : in std_logic; + p2_b : inout std_logic_vector( 7 downto 0); + p1_b : inout std_logic_vector( 7 downto 0); + prog_n_o : out std_logic + ); + +end t8048; + + +library ieee; +use ieee.numeric_std.all; + +use work.t48_system_comp_pack.t8048_notri; + +architecture struct of t8048 is + + signal t0_s : std_logic; + signal t0_dir_s : std_logic; + signal db_s : std_logic_vector( 7 downto 0); + signal db_dir_s : std_logic; + signal p2_s : std_logic_vector( 7 downto 0); + signal p2l_low_imp_s : std_logic; + signal p2h_low_imp_s : std_logic; + signal p1_s : std_logic_vector( 7 downto 0); + signal p1_low_imp_s : std_logic; + + signal vdd_s : std_logic; + +begin + + vdd_s <= '1'; + + t8048_notri_b : t8048_notri + generic map ( + -- we don't need explicit gating of input ports + -- this is done implicitely by the bidirectional pads + gate_port_input_g => 0 + ) + + port map ( + xtal_i => xtal_i, + xtal_en_i => vdd_s, + reset_n_i => reset_n_i, + t0_i => t0_b, + t0_o => t0_s, + t0_dir_o => t0_dir_s, + int_n_i => int_n_i, + ea_i => ea_i, + rd_n_o => rd_n_o, + psen_n_o => psen_n_o, + wr_n_o => wr_n_o, + ale_o => ale_o, + db_i => db_b, + db_o => db_s, + db_dir_o => db_dir_s, + t1_i => t1_i, + p2_i => p2_b, + p2_o => p2_s, + p2l_low_imp_o => p2l_low_imp_s, + p2h_low_imp_o => p2h_low_imp_s, + p1_i => p1_b, + p1_o => p1_s, + p1_low_imp_o => p1_low_imp_s, + prog_n_o => prog_n_o + ); + + ----------------------------------------------------------------------------- + -- Process bidirs + -- + -- Purpose: + -- Assign bidirectional signals. + -- + bidirs: process (t0_b, t0_s, t0_dir_s, + db_b, db_s, db_dir_s, + p1_b, p1_s, p1_low_imp_s, + p2_b, p2_s, p2l_low_imp_s, p2h_low_imp_s) + + function port_bidir_f(port_value : in std_logic_vector; + low_imp : in std_logic) return std_logic_vector is + variable result_v : std_logic_vector(port_value'range); + begin + for idx in port_value'high downto port_value'low loop + if low_imp = '1' then + result_v(idx) := port_value(idx); + elsif port_value(idx) = '0' then + result_v(idx) := '0'; + else + result_v(idx) := 'Z'; + end if; + end loop; + + return result_v; + end; + + begin + -- Test 0 ----------------------------------------------------------------- + if t0_dir_s = '1' then + t0_b <= t0_s; + else + t0_b <= 'Z'; + end if; + + -- Data Bus --------------------------------------------------------------- + if db_dir_s = '1' then + db_b <= db_s; + else + db_b <= (others => 'Z'); + end if; + + -- Port 1 ----------------------------------------------------------------- + p1_b <= port_bidir_f(port_value => p1_s, + low_imp => p1_low_imp_s); + + -- Port 2 ----------------------------------------------------------------- + p2_b(3 downto 0) <= port_bidir_f(port_value => p2_s(3 downto 0), + low_imp => p2l_low_imp_s); + p2_b(7 downto 4) <= port_bidir_f(port_value => p2_s(7 downto 4), + low_imp => p2h_low_imp_s); + + end process bidirs; + -- + ----------------------------------------------------------------------------- + + +end struct; diff --git a/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/t48/system/t8048_notri-c.vhd b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/t48/system/t8048_notri-c.vhd new file mode 100644 index 0000000000000000000000000000000000000000..19dc635dba38864efb6e99bcecb2165cbab98cf6 --- /dev/null +++ b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/t48/system/t8048_notri-c.vhd @@ -0,0 +1,31 @@ +------------------------------------------------------------------------------- +-- +-- T8048 Microcontroller System +-- +-- $Id: t8048_notri-c.vhd 295 2009-04-01 19:32:48Z arniml $ +-- +-- Copyright (c) 2004, Arnim Laeuger (arniml@opencores.org) +-- +-- All rights reserved +-- +------------------------------------------------------------------------------- + +configuration t8048_notri_struct_c0 of t8048_notri is + + for struct + + for rom_1k_b : t48_rom + use configuration work.t48_rom_lpm_c0; + end for; + + for ram_64_b : generic_ram_ena + use configuration work.generic_ram_ena_rtl_c0; + end for; + + for t48_core_b : t48_core + use configuration work.t48_core_struct_c0; + end for; + + end for; + +end t8048_notri_struct_c0; diff --git a/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/t48/system/t8048_notri.vhd b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/t48/system/t8048_notri.vhd new file mode 100644 index 0000000000000000000000000000000000000000..adbbec35098bbd0c627034479cb411e0860dd373 --- /dev/null +++ b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/t48/system/t8048_notri.vhd @@ -0,0 +1,244 @@ +------------------------------------------------------------------------------- +-- +-- T8048 Microcontroller System +-- 8048 toplevel without tri-states +-- +-- $Id: t8048_notri.vhd 295 2009-04-01 19:32:48Z arniml $ +-- +-- Copyright (c) 2004, Arnim Laeuger (arniml@opencores.org) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.opencores.org/cvsweb.shtml/t48/ +-- +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; + +entity t8048_notri is + + generic ( + gate_port_input_g : integer := 1 + ); + + port ( + xtal_i : in std_logic; + xtal_en_i : in std_logic; + reset_n_i : in std_logic; + t0_i : in std_logic; + t0_o : out std_logic; + t0_dir_o : out std_logic; + int_n_i : in std_logic; + ea_i : in std_logic; + rd_n_o : out std_logic; + psen_n_o : out std_logic; + wr_n_o : out std_logic; + ale_o : out std_logic; + db_i : in std_logic_vector( 7 downto 0); + db_o : out std_logic_vector( 7 downto 0); + db_dir_o : out std_logic; + t1_i : in std_logic; + p2_i : in std_logic_vector( 7 downto 0); + p2_o : out std_logic_vector( 7 downto 0); + p2l_low_imp_o : out std_logic; + p2h_low_imp_o : out std_logic; + p1_i : in std_logic_vector( 7 downto 0); + p1_o : out std_logic_vector( 7 downto 0); + p1_low_imp_o : out std_logic; + prog_n_o : out std_logic + ); + +end t8048_notri; + + +library ieee; +use ieee.numeric_std.all; + +use work.t48_core_comp_pack.t48_core; +use work.t48_core_comp_pack.t48_rom; +use work.t48_core_comp_pack.generic_ram_ena; + +architecture struct of t8048_notri is + + -- Address width of internal ROM + constant rom_addr_width_c : natural := 10; + + signal xtal3_s : std_logic; + signal dmem_addr_s : std_logic_vector( 7 downto 0); + signal dmem_we_s : std_logic; + signal dmem_data_from_s : std_logic_vector( 7 downto 0); + signal dmem_data_to_s : std_logic_vector( 7 downto 0); + signal pmem_addr_s : std_logic_vector(11 downto 0); + signal pmem_data_s : std_logic_vector( 7 downto 0); + + signal ea_s : std_logic; + + signal p1_in_s, + p1_out_s : std_logic_vector( 7 downto 0); + signal p2_in_s, + p2_out_s : std_logic_vector( 7 downto 0); + + signal vdd_s : std_logic; + +begin + + vdd_s <= '1'; + + ----------------------------------------------------------------------------- + -- Check generics for valid values. + ----------------------------------------------------------------------------- + -- pragma translate_off + assert gate_port_input_g = 0 or gate_port_input_g = 1 + report "gate_port_input_g must be either 1 or 0!" + severity failure; + -- pragma translate_on + + + t48_core_b : t48_core + generic map ( + xtal_div_3_g => 1, + register_mnemonic_g => 1, + include_port1_g => 1, + include_port2_g => 1, + include_bus_g => 1, + include_timer_g => 1, + sample_t1_state_g => 4 + ) + port map ( + xtal_i => xtal_i, + xtal_en_i => xtal_en_i, + reset_i => reset_n_i, + t0_i => t0_i, + t0_o => t0_o, + t0_dir_o => t0_dir_o, + int_n_i => int_n_i, + ea_i => ea_s, + rd_n_o => rd_n_o, + psen_n_o => psen_n_o, + wr_n_o => wr_n_o, + ale_o => ale_o, + db_i => db_i, + db_o => db_o, + db_dir_o => db_dir_o, + t1_i => t1_i, + p2_i => p2_in_s, + p2_o => p2_out_s, + p2l_low_imp_o => p2l_low_imp_o, + p2h_low_imp_o => p2h_low_imp_o, + p1_i => p1_in_s, + p1_o => p1_out_s, + p1_low_imp_o => p1_low_imp_o, + prog_n_o => prog_n_o, + clk_i => xtal_i, + en_clk_i => xtal3_s, + xtal3_o => xtal3_s, + dmem_addr_o => dmem_addr_s, + dmem_we_o => dmem_we_s, + dmem_data_i => dmem_data_from_s, + dmem_data_o => dmem_data_to_s, + pmem_addr_o => pmem_addr_s, + pmem_data_i => pmem_data_s + ); + + + ----------------------------------------------------------------------------- + -- Gate port 1 and 2 input bus with respetive output value + ----------------------------------------------------------------------------- + gate_ports: if gate_port_input_g = 1 generate + p1_in_s <= p1_i and p1_out_s; + p2_in_s <= p2_i and p2_out_s; + end generate; + + pass_ports: if gate_port_input_g = 0 generate + p1_in_s <= p1_i; + p2_in_s <= p2_i; + end generate; + + p1_o <= p1_out_s; + p2_o <= p2_out_s; + + + ----------------------------------------------------------------------------- + -- Process ea + -- + -- Purpose: + -- Detects access to external program memory. + -- Either by ea_i = '1' or when program memory address leaves address + -- range of internal ROM. + -- + ea: process (ea_i, + pmem_addr_s) + begin + if ea_i = '1' then + -- Forced external access + ea_s <= '1'; + + elsif unsigned(pmem_addr_s(11 downto rom_addr_width_c)) = 0 then + -- Internal access + ea_s <= '0'; + + else + -- Access to program memory out of internal range + ea_s <= '1'; + + end if; + + end process ea; + -- + ----------------------------------------------------------------------------- + + + rom_1k_b : t48_rom + port map ( + clk_i => xtal_i, + rom_addr_i => pmem_addr_s(rom_addr_width_c-1 downto 0), + rom_data_o => pmem_data_s + ); + + ram_64_b : generic_ram_ena + generic map ( + addr_width_g => 6, + data_width_g => 8 + ) + port map ( + clk_i => xtal_i, + a_i => dmem_addr_s(5 downto 0), + we_i => dmem_we_s, + ena_i => vdd_s, + d_i => dmem_data_to_s, + d_o => dmem_data_from_s + ); + +end struct; diff --git a/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/t48/system/t8050_wb-c.vhd b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/t48/system/t8050_wb-c.vhd new file mode 100644 index 0000000000000000000000000000000000000000..db42006660fc2bd8ee278ed9295dc66adaf6ed8a --- /dev/null +++ b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/t48/system/t8050_wb-c.vhd @@ -0,0 +1,35 @@ +------------------------------------------------------------------------------- +-- +-- T8048 Microcontroller System +-- +-- $Id: t8050_wb-c.vhd 295 2009-04-01 19:32:48Z arniml $ +-- +-- Copyright (c) 2005, Arnim Laeuger (arniml@opencores.org) +-- +-- All rights reserved +-- +------------------------------------------------------------------------------- + +configuration t8050_wb_struct_c0 of t8050_wb is + + for struct + + for rom_4k_b : syn_rom + use configuration work.syn_rom_lpm_c0; + end for; + + for ram_256_b : syn_ram + use configuration work.syn_ram_lpm_c0; + end for; + + for wb_master_b : t48_wb_master + use configuration work.t48_wb_master_rtl_c0; + end for; + + for t48_core_b : t48_core + use configuration work.t48_core_struct_c0; + end for; + + end for; + +end t8050_wb_struct_c0; diff --git a/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/t48/system/t8050_wb.vhd b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/t48/system/t8050_wb.vhd new file mode 100644 index 0000000000000000000000000000000000000000..3351a965bd64f145c3386824ffa096deff71ed2f --- /dev/null +++ b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/t48/system/t8050_wb.vhd @@ -0,0 +1,290 @@ +------------------------------------------------------------------------------- +-- +-- T8048 Microcontroller System +-- 8050 toplevel with Wishbone interface +-- +-- $Id: t8050_wb.vhd 295 2009-04-01 19:32:48Z arniml $ +-- +-- Copyright (c) 2005, Arnim Laeuger (arniml@opencores.org) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.opencores.org/cvsweb.shtml/t48/ +-- +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; + +entity t8050_wb is + + generic ( + gate_port_input_g : integer := 1 + ); + + port ( + -- T48 Interface ---------------------------------------------------------- + xtal_i : in std_logic; + reset_n_i : in std_logic; + t0_i : in std_logic; + t0_o : out std_logic; + t0_dir_o : out std_logic; + int_n_i : in std_logic; + ea_i : in std_logic; + rd_n_o : out std_logic; + psen_n_o : out std_logic; + wr_n_o : out std_logic; + ale_o : out std_logic; + t1_i : in std_logic; + p2_i : in std_logic_vector( 7 downto 0); + p2_o : out std_logic_vector( 7 downto 0); + p2l_low_imp_o : out std_logic; + p2h_low_imp_o : out std_logic; + p1_i : in std_logic_vector( 7 downto 0); + p1_o : out std_logic_vector( 7 downto 0); + p1_low_imp_o : out std_logic; + prog_n_o : out std_logic; + -- Wishbone Interface ----------------------------------------------------- + wb_cyc_o : out std_logic; + wb_stb_o : out std_logic; + wb_we_o : out std_logic; + wb_adr_o : out std_logic_vector(23 downto 0); + wb_ack_i : in std_logic; + wb_dat_i : in std_logic_vector( 7 downto 0); + wb_dat_o : out std_logic_vector( 7 downto 0) + + ); + +end t8050_wb; + + +library ieee; +use ieee.numeric_std.all; + +use work.t48_core_comp_pack.t48_core; +use work.t48_core_comp_pack.syn_rom; +use work.t48_core_comp_pack.syn_ram; +use work.t48_system_comp_pack.t48_wb_master; + +architecture struct of t8050_wb is + + -- Address width of internal ROM + constant rom_addr_width_c : natural := 12; + + signal xtal3_s : std_logic; + signal dmem_addr_s : std_logic_vector( 7 downto 0); + signal dmem_we_s : std_logic; + signal dmem_data_from_s : std_logic_vector( 7 downto 0); + signal dmem_data_to_s : std_logic_vector( 7 downto 0); + signal pmem_addr_s : std_logic_vector(11 downto 0); + signal pmem_data_s : std_logic_vector( 7 downto 0); + + signal ea_s : std_logic; + + signal ale_s : std_logic; + signal wr_n_s : std_logic; + signal rd_n_s : std_logic; + signal db_bus_to_t48, + db_bus_from_t48 : std_logic_vector( 7 downto 0); + + signal wb_en_clk_s : std_logic; + signal xtal_en_s : std_logic; + + signal p1_in_s, + p1_out_s : std_logic_vector( 7 downto 0); + signal p2_in_s, + p2_out_s : std_logic_vector( 7 downto 0); + +begin + + ----------------------------------------------------------------------------- + -- Check generics for valid values. + ----------------------------------------------------------------------------- + -- pragma translate_off + assert gate_port_input_g = 0 or gate_port_input_g = 1 + report "gate_port_input_g must be either 1 or 0!" + severity failure; + -- pragma translate_on + + + t48_core_b : t48_core + generic map ( + xtal_div_3_g => 1, + register_mnemonic_g => 1, + include_port1_g => 1, + include_port2_g => 1, + include_bus_g => 1, + include_timer_g => 1, + sample_t1_state_g => 4 + ) + port map ( + xtal_i => xtal_i, + xtal_en_i => xtal_en_s, + reset_i => reset_n_i, + t0_i => t0_i, + t0_o => t0_o, + t0_dir_o => t0_dir_o, + int_n_i => int_n_i, + ea_i => ea_s, + rd_n_o => rd_n_s, + psen_n_o => psen_n_o, + wr_n_o => wr_n_s, + ale_o => ale_s, + db_i => db_bus_to_t48, + db_o => db_bus_from_t48, + db_dir_o => open, + t1_i => t1_i, + p2_i => p2_in_s, + p2_o => p2_out_s, + p2l_low_imp_o => p2l_low_imp_o, + p2h_low_imp_o => p2h_low_imp_o, + p1_i => p1_in_s, + p1_o => p1_out_s, + p1_low_imp_o => p1_low_imp_o, + prog_n_o => prog_n_o, + clk_i => xtal_i, + en_clk_i => xtal3_s, + xtal3_o => xtal3_s, + dmem_addr_o => dmem_addr_s, + dmem_we_o => dmem_we_s, + dmem_data_i => dmem_data_from_s, + dmem_data_o => dmem_data_to_s, + pmem_addr_o => pmem_addr_s, + pmem_data_i => pmem_data_s + ); + + + ----------------------------------------------------------------------------- + -- Gate port 1 and 2 input bus with respetive output value + ----------------------------------------------------------------------------- + gate_ports: if gate_port_input_g = 1 generate + p1_in_s <= p1_i and p1_out_s; + p2_in_s <= p2_i and p2_out_s; + end generate; + + pass_ports: if gate_port_input_g = 0 generate + p1_in_s <= p1_i; + p2_in_s <= p2_i; + end generate; + + p1_o <= p1_out_s; + p2_o <= p2_out_s; + + ale_o <= ale_s; + wr_n_o <= wr_n_s; + rd_n_o <= rd_n_s; + + + ----------------------------------------------------------------------------- + -- Generate clock enable + ----------------------------------------------------------------------------- + xtal_en_s <= wb_en_clk_s; + + + ----------------------------------------------------------------------------- + -- Process ea + -- + -- Purpose: + -- Detects access to external program memory. + -- Either by ea_i = '1' or when program memory address leaves address + -- range of internal ROM. + -- + ea: process (ea_i, + pmem_addr_s) + begin + if ea_i = '1' then + -- Forced external access + ea_s <= '1'; + +-- elsif unsigned(pmem_addr_s(11 downto rom_addr_width_c)) = 0 then + else + -- Internal access + ea_s <= '0'; + +-- else +-- -- Access to program memory out of internal range +-- ea_s <= '1'; + + end if; + + end process ea; + -- + ----------------------------------------------------------------------------- + + + wb_master_b : t48_wb_master + port map ( + xtal_i => xtal_i, + res_i => reset_n_i, + en_clk_o => wb_en_clk_s, + ale_i => ale_s, + rd_n_i => rd_n_s, + wr_n_i => wr_n_s, + adr_i => p2_out_s(4), + db_bus_i => db_bus_from_t48, + db_bus_o => db_bus_to_t48, + wb_cyc_o => wb_cyc_o, + wb_stb_o => wb_stb_o, + wb_we_o => wb_we_o, + wb_adr_o => wb_adr_o, + wb_ack_i => wb_ack_i, + wb_dat_i => wb_dat_i, + wb_dat_o => wb_dat_o + ); + + + rom_4k_b : syn_rom + generic map ( + address_width_g => rom_addr_width_c + ) + port map ( + clk_i => xtal_i, + rom_addr_i => pmem_addr_s(rom_addr_width_c-1 downto 0), + rom_data_o => pmem_data_s + ); + + ram_256_b : syn_ram + generic map ( + address_width_g => 8 + ) + port map ( + clk_i => xtal_i, + res_i => reset_n_i, + ram_addr_i => dmem_addr_s(7 downto 0), + ram_data_i => dmem_data_to_s, + ram_we_i => dmem_we_s, + ram_data_o => dmem_data_from_s + ); + +end struct; diff --git a/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/t48/system/wb_master-c.vhd b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/t48/system/wb_master-c.vhd new file mode 100644 index 0000000000000000000000000000000000000000..45bf76741dcf789c08737e50ea8754af7dd5806b --- /dev/null +++ b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/t48/system/wb_master-c.vhd @@ -0,0 +1,18 @@ +------------------------------------------------------------------------------- +-- +-- The Wishbone master module. +-- +-- $Id: wb_master-c.vhd 295 2009-04-01 19:32:48Z arniml $ +-- +-- Copyright (c) 2004, Arnim Laeuger (arniml@opencores.org) +-- +-- All rights reserved +-- +------------------------------------------------------------------------------- + +configuration t48_wb_master_rtl_c0 of t48_wb_master is + + for rtl + end for; + +end t48_wb_master_rtl_c0; diff --git a/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/t48/system/wb_master.vhd b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/t48/system/wb_master.vhd new file mode 100644 index 0000000000000000000000000000000000000000..bc053fab45690e0cb5a67728961c954f1e064d46 --- /dev/null +++ b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/t48/system/wb_master.vhd @@ -0,0 +1,249 @@ +------------------------------------------------------------------------------- +-- +-- The Wishbone master module. +-- +-- $Id: wb_master.vhd 295 2009-04-01 19:32:48Z arniml $ +-- +-- Copyright (c) 2005, Arnim Laeuger (arniml@opencores.org) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.opencores.org/cvsweb.shtml/t48/ +-- +-- +-- Short description: +-- This design implements a simple Wishbone bus master. It connects to the +-- BUS interface of the T48 uController core. +-- +-- The CPU clock is suppressed with en_clk_o to stall the CPU until the +-- acknowledge signal from the peripheral is detected. +-- +-- The adr_i input selects between configuration and Wishbone address range: +-- 1 - configuration range +-- 0 - Wishbone range +-- +-- When configuration range is selected, two address register are accessible. +-- 000h -> adr1 +-- 001h -> adr2 +-- These registers can be read and written with movx to their addresses. +-- +-- When Wishbone range is selected, all movx generate Wishbone bus cycles +-- (either read or write) at following address: +-- Wishbone address = adr2 & adr1 & address of movx +-- +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; + +use work.t48_pack.all; + +entity t48_wb_master is + + port ( + xtal_i : in std_logic; + res_i : in std_logic; + en_clk_o : out std_logic; + -- T48 Interface ---------------------------------------------------------- + ale_i : in std_logic; + rd_n_i : in std_logic; + wr_n_i : in std_logic; + adr_i : in std_logic; + db_bus_i : in std_logic_vector( 7 downto 0); + db_bus_o : out std_logic_vector( 7 downto 0); + -- Wishbone Interface ----------------------------------------------------- + wb_cyc_o : out std_logic; + wb_stb_o : out std_logic; + wb_we_o : out std_logic; + wb_adr_o : out std_logic_vector(23 downto 0); + wb_ack_i : in std_logic; + wb_dat_i : in std_logic_vector( 7 downto 0); + wb_dat_o : out std_logic_vector( 7 downto 0) + ); + +end t48_wb_master; + + +architecture rtl of t48_wb_master is + + ----------------------------------------------------------------------------- + -- Controller FSM + ----------------------------------------------------------------------------- + type state_t is (IDLE, CYC, WAIT_INACT); + signal state_s, + state_q : state_t; + + ----------------------------------------------------------------------------- + -- Select signals for each range + ----------------------------------------------------------------------------- + signal sel_adr1_s, + sel_adr2_s, + sel_wb_s : boolean; + + signal wr_s, + rd_s : boolean; + + signal adr_q : std_logic_vector(23 downto 0); + signal wb_dat_q : std_logic_vector( 7 downto 0); + +begin + + ----------------------------------------------------------------------------- + -- Select signal generation + ----------------------------------------------------------------------------- + sel_adr1_s <= adr_i = '1' and adr_q(word_t'range) = "00000000"; + sel_adr2_s <= adr_i = '1' and adr_q(word_t'range) = "00000001"; + sel_wb_s <= adr_i = '0'; + + wr_s <= wr_n_i = '0'; + rd_s <= rd_n_i = '0'; + + + ----------------------------------------------------------------------------- + -- Process seq + -- + -- Purpose: + -- Implements the sequential elements. + -- + seq: process (res_i, xtal_i) + begin + if res_i = res_active_c then + adr_q <= (others => '0'); + wb_dat_q <= (others => '0'); + state_q <= IDLE; + + elsif xtal_i'event and xtal_i = clk_active_c then + -- Address register ----------------------------------------------------- + -- update lowest address byte + if ale_i = '1' then + adr_q(word_t'range) <= db_bus_i; + end if; + -- set adr1 part + if wr_s and sel_adr1_s then + adr_q(word_t'length*2 - 1 downto word_t'length) <= db_bus_i; + end if; + -- set adr2 part + if wr_s and sel_adr2_s then + adr_q(word_t'length*3 - 1 downto word_t'length*2) <= db_bus_i; + end if; + + -- Data from peripheral has to be saved --------------------------------- + if wb_ack_i = '1' then + wb_dat_q <= wb_dat_i; + end if; + + -- FSM state ------------------------------------------------------------ + state_q <= state_s; + + end if; + end process seq; + -- + ----------------------------------------------------------------------------- + + + ----------------------------------------------------------------------------- + -- Process fsm + -- + -- Purpose: + -- Implements the state transitions of the controller FSM. + -- + fsm: process (state_q, + wr_s, + rd_s, + sel_wb_s, + wb_ack_i) + begin + -- default assignments + wb_cyc_o <= '0'; + wb_stb_o <= '0'; + en_clk_o <= '1'; + state_s <= IDLE; + + case state_q is + -- Idle State: Wait for read or write access ---------------------------- + when IDLE => + if sel_wb_s and (wr_s or rd_s) then + state_s <= CYC; + end if; + + -- WB Cycle State: Start Wishbone cycle and wait for ack ---------------- + when CYC => + wb_cyc_o <= '1'; + wb_stb_o <= '1'; + en_clk_o <= '0'; + + if wb_ack_i = '1' then + state_s <= WAIT_INACT; + else + state_s <= CYC; + end if; + + -- Wait inact State: Wait for end of T48 access ------------------------- + when WAIT_INACT => + if not wr_s and not rd_s then + state_s <= IDLE; + else + state_s <= WAIT_INACT; + end if; + + when others => + null; + + end case; + + end process fsm; + -- + ----------------------------------------------------------------------------- + + + ----------------------------------------------------------------------------- + -- Output multiplexer + ----------------------------------------------------------------------------- + db_bus_o <= adr_q(word_t'length*2 - 1 downto word_t'length) + when sel_adr1_s else + adr_q(word_t'length*3 - 1 downto word_t'length*2) + when sel_adr2_s else + wb_dat_q; + + + ----------------------------------------------------------------------------- + -- Output mapping + ----------------------------------------------------------------------------- + wb_adr_o <= adr_q; + wb_dat_o <= db_bus_i; + wb_we_o <= '1' + when wr_s and sel_wb_s else + '0'; + +end rtl; diff --git a/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/t48/t48_comp_pack-p.vhd b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/t48/t48_comp_pack-p.vhd new file mode 100644 index 0000000000000000000000000000000000000000..b9567834b88c805a5a2170163ef2830d8ff862a1 --- /dev/null +++ b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/t48/t48_comp_pack-p.vhd @@ -0,0 +1,423 @@ +------------------------------------------------------------------------------- +-- +-- $Id: t48_comp_pack-p.vhd 317 2022-12-23 13:18:49Z arniml $ +-- +-- Copyright (c) 2004, 2005, Arnim Laeuger (arniml@opencores.org) +-- +-- All rights reserved +-- +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; + +use work.t48_alu_pack.alu_op_t; +use work.t48_cond_branch_pack.branch_conditions_t; +use work.t48_cond_branch_pack.comp_value_t; +use work.t48_decoder_pack.mnemonic_t; +use work.t48_dmem_ctrl_pack.dmem_addr_ident_t; +use work.t48_pmem_ctrl_pack.pmem_addr_ident_t; +use work.t48_pack.dmem_addr_t; +use work.t48_pack.pmem_addr_t; +use work.t48_pack.mstate_t; +use work.t48_pack.word_t; +use work.t48_pack.nibble_t; + +package t48_comp_pack is + + component t48_alu + port ( + clk_i : in std_logic; + res_i : in std_logic; + en_clk_i : in boolean; + data_i : in word_t; + data_o : out word_t; + write_accu_i : in boolean; + write_shadow_i : in boolean; + write_temp_reg_i : in boolean; + read_alu_i : in boolean; + carry_i : in std_logic; + carry_o : out std_logic; + aux_carry_o : out std_logic; + alu_op_i : in alu_op_t; + use_carry_i : in boolean; + da_high_i : in boolean; + da_overflow_o : out boolean; + accu_low_i : in boolean; + p06_temp_reg_i : in boolean; + p60_temp_reg_i : in boolean + ); + end component; + + component t48_bus_mux + port ( + alu_data_i : in word_t; + bus_data_i : in word_t; + dec_data_i : in word_t; + dm_data_i : in word_t; + pm_data_i : in word_t; + p1_data_i : in word_t; + p2_data_i : in word_t; + psw_data_i : in word_t; + tim_data_i : in word_t; + data_o : out word_t + ); + end component; + + component t48_clock_ctrl + generic ( + xtal_div_3_g : integer := 1 + ); + port ( + clk_i : in std_logic; + xtal_i : in std_logic; + xtal_en_i : in boolean; + res_i : in std_logic; + en_clk_i : in boolean; + xtal3_o : out boolean; + t0_o : out std_logic; + multi_cycle_i : in boolean; + assert_psen_i : in boolean; + assert_prog_i : in boolean; + assert_rd_i : in boolean; + assert_wr_i : in boolean; + mstate_o : out mstate_t; + second_cycle_o : out boolean; + ale_o : out boolean; + psen_o : out boolean; + prog_o : out boolean; + rd_o : out boolean; + wr_o : out boolean + ); + end component; + + component t48_cond_branch + port ( + clk_i : in std_logic; + res_i : in std_logic; + en_clk_i : in boolean; + compute_take_i : in boolean; + branch_cond_i : in branch_conditions_t; + take_branch_o : out boolean; + accu_i : in word_t; + t0_i : in std_logic; + t1_i : in std_logic; + int_n_i : in std_logic; + f0_i : in std_logic; + f1_i : in std_logic; + tf_i : in std_logic; + carry_i : in std_logic; + ibf_i : in std_logic := '0'; + obf_i : in std_logic := '0'; + comp_value_i : in comp_value_t + ); + end component; + + component t48_db_bus + port ( + clk_i : in std_logic; + res_i : in std_logic; + en_clk_i : in boolean; + ea_i : in std_logic; + data_i : in word_t; + data_o : out word_t; + write_bus_i : in boolean; + read_bus_i : in boolean; + output_pcl_i : in boolean; + bidir_bus_i : in boolean; + pcl_i : in word_t; + db_i : in word_t; + db_o : out word_t; + db_dir_o : out std_logic + ); + end component; + + component upi41_db_bus + generic ( + is_type_a_g : integer := 1 + ); + port ( + clk_i : in std_logic; + res_i : in std_logic; + en_clk_i : in boolean; + data_i : in word_t; + data_o : out word_t; + write_bus_i : in boolean; + read_bus_i : in boolean; + write_sts_i : in boolean; + set_f1_o : out boolean; + clear_f1_o : out boolean; + f0_i : in std_logic; + f1_i : in std_logic; + ibf_o : out std_logic; + obf_o : out std_logic; + int_n_o : out std_logic; + ibf_int_i : in boolean; + en_dma_i : in boolean; + en_flags_i : in boolean; + write_p2_i : in boolean; + mint_ibf_n_o : out std_logic; + mint_obf_o : out std_logic; + dma_o : out boolean; + drq_o : out std_logic; + dack_n_i : in std_logic; + a0_i : in std_logic; + cs_n_i : in std_logic; + rd_n_i : in std_logic; + wr_n_i : in std_logic; + db_i : in word_t; + db_o : out word_t; + db_dir_o : out std_logic + ); + end component; + + component t48_decoder + generic ( + register_mnemonic_g : integer := 1; + is_upi_g : integer := 0; + is_upi_type_a_g : integer := 0 + ); + port ( + clk_i : in std_logic; + res_i : in std_logic; + en_clk_i : in boolean; + xtal_i : in std_logic; + xtal_en_i : in boolean; + ea_i : in std_logic; + ale_i : in boolean; + int_n_i : in std_logic; + t0_dir_o : out std_logic; + data_i : in word_t; + data_o : out word_t; + alu_write_accu_o : out boolean; + alu_write_shadow_o : out boolean; + alu_write_temp_reg_o : out boolean; + alu_read_alu_o : out boolean; + bus_write_bus_o : out boolean; + bus_read_bus_o : out boolean; + bus_set_f1_i : in boolean := false; + bus_clear_f1_i : in boolean := false; + bus_ibf_int_o : out boolean; + bus_en_dma_o : out boolean; + bus_en_flags_o : out boolean; + bus_write_sts_o : out boolean; + dm_write_dmem_addr_o : out boolean; + dm_write_dmem_o : out boolean; + dm_read_dmem_o : out boolean; + p1_write_p1_o : out boolean; + p1_read_p1_o : out boolean; + p2_write_p2_o : out boolean; + p2_write_exp_o : out boolean; + p2_read_p2_o : out boolean; + pm_write_pcl_o : out boolean; + pm_read_pcl_o : out boolean; + pm_write_pch_o : out boolean; + pm_read_pch_o : out boolean; + pm_read_pmem_o : out boolean; + psw_read_psw_o : out boolean; + psw_read_sp_o : out boolean; + psw_write_psw_o : out boolean; + psw_write_sp_o : out boolean; + alu_carry_i : in std_logic; + alu_op_o : out alu_op_t; + alu_da_high_o : out boolean; + alu_accu_low_o : out boolean; + alu_da_overflow_i : in boolean; + alu_p06_temp_reg_o : out boolean; + alu_p60_temp_reg_o : out boolean; + alu_use_carry_o : out boolean; + bus_output_pcl_o : out boolean; + bus_bidir_bus_o : out boolean; + clk_multi_cycle_o : out boolean; + clk_assert_psen_o : out boolean; + clk_assert_prog_o : out boolean; + clk_assert_rd_o : out boolean; + clk_assert_wr_o : out boolean; + clk_mstate_i : in mstate_t; + clk_second_cycle_i : in boolean; + cnd_compute_take_o : out boolean; + cnd_branch_cond_o : out branch_conditions_t; + cnd_take_branch_i : in boolean; + cnd_comp_value_o : out comp_value_t; + cnd_f1_o : out std_logic; + cnd_tf_o : out std_logic; + dm_addr_type_o : out dmem_addr_ident_t; + tim_read_timer_o : out boolean; + tim_write_timer_o : out boolean; + tim_start_t_o : out boolean; + tim_start_cnt_o : out boolean; + tim_stop_tcnt_o : out boolean; + p1_read_reg_o : out boolean; + p2_read_reg_o : out boolean; + p2_read_exp_o : out boolean; + p2_output_pch_o : out boolean; + pm_inc_pc_o : out boolean; + pm_write_pmem_addr_o : out boolean; + pm_addr_type_o : out pmem_addr_ident_t; + psw_special_data_o : out std_logic; + psw_carry_i : in std_logic; + psw_aux_carry_i : in std_logic; + psw_f0_i : in std_logic; + psw_inc_stackp_o : out boolean; + psw_dec_stackp_o : out boolean; + psw_write_carry_o : out boolean; + psw_write_aux_carry_o : out boolean; + psw_write_f0_o : out boolean; + psw_write_bs_o : out boolean; + tim_overflow_i : in boolean + ); + end component; + + component t48_dmem_ctrl + port ( + clk_i : in std_logic; + res_i : in std_logic; + en_clk_i : in boolean; + data_i : in word_t; + write_dmem_addr_i : in boolean; + write_dmem_i : in boolean; + read_dmem_i : in boolean; + addr_type_i : in dmem_addr_ident_t; + bank_select_i : in std_logic; + data_o : out word_t; + dmem_data_i : in word_t; + dmem_addr_o : out dmem_addr_t; + dmem_we_o : out std_logic; + dmem_data_o : out word_t + ); + end component; + + component t48_int + port ( + clk_i : in std_logic; + res_i : in std_logic; + en_clk_i : in boolean; + xtal_i : in std_logic; + xtal_en_i : in boolean; + clk_mstate_i : in mstate_t; + jtf_executed_i : in boolean; + tim_overflow_i : in boolean; + tf_o : out std_logic; + en_tcnti_i : in boolean; + dis_tcnti_i : in boolean; + int_n_i : in std_logic; + ale_i : in boolean; + last_cycle_i : in boolean; + en_i_i : in boolean; + dis_i_i : in boolean; + ext_int_o : out boolean; + tim_int_o : out boolean; + retr_executed_i : in boolean; + int_executed_i : in boolean; + int_pending_o : out boolean; + int_in_progress_o : out boolean + ); + end component; + + component t48_timer + generic ( + sample_t1_state_g : integer := 4 + ); + port ( + clk_i : in std_logic; + res_i : in std_logic; + en_clk_i : in boolean; + t1_i : in std_logic; + clk_mstate_i : in mstate_t; + data_i : in word_t; + data_o : out word_t; + read_timer_i : in boolean; + write_timer_i : in boolean; + start_t_i : in boolean; + start_cnt_i : in boolean; + stop_tcnt_i : in boolean; + overflow_o : out std_logic + ); + end component; + + component t48_p1 + port ( + clk_i : in std_logic; + res_i : in std_logic; + en_clk_i : in boolean; + data_i : in word_t; + data_o : out word_t; + write_p1_i : in boolean; + read_p1_i : in boolean; + read_reg_i : in boolean; + p1_i : in word_t; + p1_o : out word_t; + p1_low_imp_o : out std_logic + ); + end component; + + component t48_p2 + port ( + clk_i : in std_logic; + res_i : in std_logic; + en_clk_i : in boolean; + xtal_i : in std_logic; + xtal_en_i : in boolean; + data_i : in word_t; + data_o : out word_t; + write_p2_i : in boolean; + write_exp_i : in boolean; + read_p2_i : in boolean; + read_reg_i : in boolean; + read_exp_i : in boolean; + output_pch_i : in boolean; + pch_i : in nibble_t; + p2_i : in word_t; + p2_o : out word_t; + p2l_low_imp_o : out std_logic; + p2h_low_imp_o : out std_logic + ); + end component; + + component t48_pmem_ctrl + port ( + clk_i : in std_logic; + res_i : in std_logic; + en_clk_i : in boolean; + data_i : in word_t; + data_o : out word_t; + write_pcl_i : in boolean; + read_pcl_i : in boolean; + write_pch_i : in boolean; + read_pch_i : in boolean; + inc_pc_i : in boolean; + write_pmem_addr_i : in boolean; + addr_type_i : in pmem_addr_ident_t; + read_pmem_i : in boolean; + pmem_addr_o : out pmem_addr_t; + pmem_data_i : in word_t + ); + end component; + + component t48_psw + port ( + clk_i : in std_logic; + res_i : in std_logic; + en_clk_i : in boolean; + data_i : in word_t; + data_o : out word_t; + read_psw_i : in boolean; + read_sp_i : in boolean; + write_psw_i : in boolean; + write_sp_i : in boolean; + special_data_i : in std_logic; + inc_stackp_i : in boolean; + dec_stackp_i : in boolean; + write_carry_i : in boolean; + write_aux_carry_i : in boolean; + write_f0_i : in boolean; + write_bs_i : in boolean; + carry_o : out std_logic; + aux_carry_i : in std_logic; + aux_carry_o : out std_logic; + f0_o : out std_logic; + bs_o : out std_logic + ); + end component; + +end t48_comp_pack; diff --git a/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/t48/t48_core-c.vhd b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/t48/t48_core-c.vhd new file mode 100644 index 0000000000000000000000000000000000000000..8ec7082d6d6d326c36f5d36181e01ea5e577c6dc --- /dev/null +++ b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/t48/t48_core-c.vhd @@ -0,0 +1,71 @@ +------------------------------------------------------------------------------- +-- +-- T48 Microcontroller Core +-- +-- $Id: t48_core-c.vhd 295 2009-04-01 19:32:48Z arniml $ +-- +------------------------------------------------------------------------------- + +configuration t48_core_struct_c0 of t48_core is + + for struct + + for alu_b : t48_alu + use configuration work.t48_alu_rtl_c0; + end for; + + for bus_mux_b : t48_bus_mux + use configuration work.t48_bus_mux_rtl_c0; + end for; + + for clock_ctrl_b : t48_clock_ctrl + use configuration work.t48_clock_ctrl_rtl_c0; + end for; + + for cond_branch_b : t48_cond_branch + use configuration work.t48_cond_branch_rtl_c0; + end for; + + for use_db_bus + for db_bus_b : t48_db_bus + use configuration work.t48_db_bus_rtl_c0; + end for; + end for; + + for decoder_b : t48_decoder + use configuration work.t48_decoder_rtl_c0; + end for; + + for dmem_ctrl_b : t48_dmem_ctrl + use configuration work.t48_dmem_ctrl_rtl_c0; + end for; + + for use_timer + for timer_b : t48_timer + use configuration work.t48_timer_rtl_c0; + end for; + end for; + + for use_p1 + for p1_b : t48_p1 + use configuration work.t48_p1_rtl_c0; + end for; + end for; + + for use_p2 + for p2_b : t48_p2 + use configuration work.t48_p2_rtl_c0; + end for; + end for; + + for pmem_ctrl_b : t48_pmem_ctrl + use configuration work.t48_pmem_ctrl_rtl_c0; + end for; + + for psw_b : t48_psw + use configuration work.t48_psw_rtl_c0; + end for; + + end for; + +end t48_core_struct_c0; diff --git a/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/t48/t48_core.v b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/t48/t48_core.v new file mode 100644 index 0000000000000000000000000000000000000000..aa3d7826568f97f6f27e419d6337f98ac0700e84 --- /dev/null +++ b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/t48/t48_core.v @@ -0,0 +1,14852 @@ +module t48_int + (input clk_i, + input res_i, + input en_clk_i, + input xtal_i, + input xtal_en_i, + input [2:0] clk_mstate_i, + input jtf_executed_i, + input tim_overflow_i, + input en_tcnti_i, + input dis_tcnti_i, + input int_n_i, + input ale_i, + input last_cycle_i, + input en_i_i, + input dis_i_i, + input retr_executed_i, + input int_executed_i, + output tf_o, + output ext_int_o, + output tim_int_o, + output int_pending_o, + output int_in_progress_o); + wire [1:0] int_state_s; + wire [1:0] int_state_q; + wire timer_flag_q; + wire timer_overflow_q; + wire timer_int_enable_q; + wire int_q; + wire int_enable_q; + wire ale_q; + wire int_type_q; + wire int_in_progress_q; + wire n4944_o; + wire n4946_o; + wire n4947_o; + wire [1:0] n4949_o; + wire n4951_o; + wire [1:0] n4953_o; + wire n4955_o; + wire [1:0] n4957_o; + wire n4959_o; + wire [2:0] n4960_o; + reg [1:0] n4962_o; + wire n4965_o; + wire n4968_o; + wire n4970_o; + wire n4971_o; + wire n4972_o; + wire n4973_o; + wire n4974_o; + wire n4976_o; + wire n4978_o; + wire n4980_o; + wire n4982_o; + wire n4984_o; + wire n4986_o; + wire n4987_o; + wire n4988_o; + wire n4989_o; + wire n4991_o; + wire n4998_o; + wire n4999_o; + wire n5000_o; + wire n5002_o; + wire n5003_o; + wire n5005_o; + wire n5036_o; + wire n5038_o; + wire n5039_o; + wire n5040_o; + wire n5048_o; + wire n5049_o; + wire n5051_o; + wire n5067_o; + wire n5068_o; + wire n5070_o; + wire n5072_o; + wire n5073_o; + wire [1:0] n5074_o; + reg [1:0] n5075_q; + wire n5076_o; + reg n5077_q; + wire n5078_o; + reg n5079_q; + wire n5080_o; + reg n5081_q; + wire n5082_o; + reg n5083_q; + wire n5084_o; + reg n5085_q; + wire n5086_o; + reg n5087_q; + wire n5088_o; + reg n5089_q; + wire n5090_o; + reg n5091_q; + assign tf_o = n5067_o; + assign ext_int_o = int_type_q; + assign tim_int_o = n5068_o; + assign int_pending_o = n5070_o; + assign int_in_progress_o = n5073_o; + /* int.vhd:91:10 */ + assign int_state_s = n4962_o; // (signal) + /* int.vhd:92:10 */ + assign int_state_q = n5075_q; // (signal) + /* int.vhd:94:10 */ + assign timer_flag_q = n5077_q; // (signal) + /* int.vhd:95:10 */ + assign timer_overflow_q = n5079_q; // (signal) + /* int.vhd:96:10 */ + assign timer_int_enable_q = n5081_q; // (signal) + /* int.vhd:97:10 */ + assign int_q = n5083_q; // (signal) + /* int.vhd:98:10 */ + assign int_enable_q = n5085_q; // (signal) + /* int.vhd:99:10 */ + assign ale_q = n5087_q; // (signal) + /* int.vhd:100:10 */ + assign int_type_q = n5089_q; // (signal) + /* int.vhd:101:10 */ + assign int_in_progress_q = n5091_q; // (signal) + /* int.vhd:123:30 */ + assign n4944_o = last_cycle_i & int_in_progress_q; + /* int.vhd:124:42 */ + assign n4946_o = clk_mstate_i == 3'b100; + /* int.vhd:124:25 */ + assign n4947_o = n4946_o & n4944_o; + /* int.vhd:123:9 */ + assign n4949_o = n4947_o ? 2'b01 : int_state_q; + /* int.vhd:122:7 */ + assign n4951_o = int_state_q == 2'b00; + /* int.vhd:129:9 */ + assign n4953_o = int_executed_i ? 2'b10 : int_state_q; + /* int.vhd:128:7 */ + assign n4955_o = int_state_q == 2'b01; + /* int.vhd:134:9 */ + assign n4957_o = retr_executed_i ? 2'b00 : int_state_q; + /* int.vhd:133:7 */ + assign n4959_o = int_state_q == 2'b10; + assign n4960_o = {n4959_o, n4955_o, n4951_o}; + /* int.vhd:121:5 */ + always @* + case (n4960_o) + 3'b100: n4962_o = n4957_o; + 3'b010: n4962_o = n4953_o; + 3'b001: n4962_o = n4949_o; + default: n4962_o = 2'b00; + endcase + /* int.vhd:158:14 */ + assign n4965_o = ~res_i; + /* int.vhd:174:9 */ + assign n4968_o = tim_overflow_i ? 1'b1 : timer_flag_q; + /* int.vhd:172:9 */ + assign n4970_o = jtf_executed_i ? 1'b0 : n4968_o; + /* int.vhd:178:24 */ + assign n4971_o = ~int_type_q; + /* int.vhd:178:36 */ + assign n4972_o = int_executed_i & n4971_o; + /* int.vhd:179:11 */ + assign n4973_o = ~timer_int_enable_q; + /* int.vhd:178:56 */ + assign n4974_o = n4972_o | n4973_o; + /* int.vhd:181:9 */ + assign n4976_o = tim_overflow_i ? 1'b1 : timer_overflow_q; + /* int.vhd:178:9 */ + assign n4978_o = n4974_o ? 1'b0 : n4976_o; + /* int.vhd:187:9 */ + assign n4980_o = en_tcnti_i ? 1'b1 : timer_int_enable_q; + /* int.vhd:185:9 */ + assign n4982_o = dis_tcnti_i ? 1'b0 : n4980_o; + /* int.vhd:193:9 */ + assign n4984_o = en_i_i ? 1'b1 : int_enable_q; + /* int.vhd:191:9 */ + assign n4986_o = dis_i_i ? 1'b0 : n4984_o; + /* int.vhd:199:22 */ + assign n4987_o = int_enable_q & int_q; + /* int.vhd:199:40 */ + assign n4988_o = n4987_o | timer_overflow_q; + /* int.vhd:202:14 */ + assign n4989_o = ~int_in_progress_q; + /* int.vhd:203:45 */ + assign n4991_o = int_enable_q & int_q; + /* t48_pack-p.vhd:66:5 */ + assign n4998_o = n4991_o ? 1'b1 : 1'b0; + /* int.vhd:199:9 */ + assign n4999_o = n5000_o ? n4998_o : int_type_q; + /* int.vhd:199:9 */ + assign n5000_o = n4988_o & n4989_o; + /* int.vhd:199:9 */ + assign n5002_o = n4988_o ? 1'b1 : int_in_progress_q; + /* int.vhd:197:9 */ + assign n5003_o = retr_executed_i ? int_type_q : n4999_o; + /* int.vhd:197:9 */ + assign n5005_o = retr_executed_i ? 1'b0 : n5002_o; + /* int.vhd:224:14 */ + assign n5036_o = ~res_i; + /* int.vhd:232:25 */ + assign n5038_o = ale_q & last_cycle_i; + /* int.vhd:233:22 */ + assign n5039_o = ~ale_i; + /* int.vhd:233:18 */ + assign n5040_o = n5039_o & n5038_o; + /* t48_pack-p.vhd:75:5 */ + assign n5048_o = int_n_i ? 1'b1 : 1'b0; + /* int.vhd:234:20 */ + assign n5049_o = ~n5048_o; + /* int.vhd:229:7 */ + assign n5051_o = xtal_en_i & n5040_o; + /* t48_pack-p.vhd:66:5 */ + assign n5067_o = timer_flag_q ? 1'b1 : 1'b0; + /* int.vhd:249:35 */ + assign n5068_o = ~int_type_q; + /* int.vhd:250:36 */ + assign n5070_o = int_state_q == 2'b01; + /* int.vhd:251:58 */ + assign n5072_o = int_state_q != 2'b00; + /* int.vhd:251:42 */ + assign n5073_o = n5072_o & int_in_progress_q; + /* int.vhd:167:5 */ + assign n5074_o = en_clk_i ? int_state_s : int_state_q; + /* int.vhd:167:5 */ + always @(posedge clk_i or posedge n4965_o) + if (n4965_o) + n5075_q <= 2'b00; + else + n5075_q <= n5074_o; + /* int.vhd:167:5 */ + assign n5076_o = en_clk_i ? n4970_o : timer_flag_q; + /* int.vhd:167:5 */ + always @(posedge clk_i or posedge n4965_o) + if (n4965_o) + n5077_q <= 1'b0; + else + n5077_q <= n5076_o; + /* int.vhd:167:5 */ + assign n5078_o = en_clk_i ? n4978_o : timer_overflow_q; + /* int.vhd:167:5 */ + always @(posedge clk_i or posedge n4965_o) + if (n4965_o) + n5079_q <= 1'b0; + else + n5079_q <= n5078_o; + /* int.vhd:167:5 */ + assign n5080_o = en_clk_i ? n4982_o : timer_int_enable_q; + /* int.vhd:167:5 */ + always @(posedge clk_i or posedge n4965_o) + if (n4965_o) + n5081_q <= 1'b0; + else + n5081_q <= n5080_o; + /* int.vhd:228:5 */ + assign n5082_o = n5051_o ? n5049_o : int_q; + /* int.vhd:228:5 */ + always @(posedge xtal_i or posedge n5036_o) + if (n5036_o) + n5083_q <= 1'b0; + else + n5083_q <= n5082_o; + /* int.vhd:167:5 */ + assign n5084_o = en_clk_i ? n4986_o : int_enable_q; + /* int.vhd:167:5 */ + always @(posedge clk_i or posedge n4965_o) + if (n4965_o) + n5085_q <= 1'b0; + else + n5085_q <= n5084_o; + /* int.vhd:228:5 */ + assign n5086_o = xtal_en_i ? ale_i : ale_q; + /* int.vhd:228:5 */ + always @(posedge xtal_i or posedge n5036_o) + if (n5036_o) + n5087_q <= 1'b0; + else + n5087_q <= n5086_o; + /* int.vhd:167:5 */ + assign n5088_o = en_clk_i ? n5003_o : int_type_q; + /* int.vhd:167:5 */ + always @(posedge clk_i or posedge n4965_o) + if (n4965_o) + n5089_q <= 1'b0; + else + n5089_q <= n5088_o; + /* int.vhd:167:5 */ + assign n5090_o = en_clk_i ? n5005_o : int_in_progress_q; + /* int.vhd:167:5 */ + always @(posedge clk_i or posedge n4965_o) + if (n4965_o) + n5091_q <= 1'b0; + else + n5091_q <= n5090_o; +endmodule + +module t48_psw + (input clk_i, + input res_i, + input en_clk_i, + input [7:0] data_i, + input read_psw_i, + input read_sp_i, + input write_psw_i, + input write_sp_i, + input special_data_i, + input inc_stackp_i, + input dec_stackp_i, + input write_carry_i, + input write_aux_carry_i, + input write_f0_i, + input write_bs_i, + input aux_carry_i, + output [7:0] data_o, + output carry_o, + output aux_carry_o, + output f0_o, + output bs_o); + wire [3:0] psw_q; + wire [2:0] sp_q; + wire n4876_o; + wire [2:0] n4880_o; + wire [2:0] n4881_o; + wire [2:0] n4883_o; + wire [2:0] n4884_o; + wire [2:0] n4886_o; + wire [2:0] n4887_o; + wire n4888_o; + wire n4889_o; + wire n4890_o; + wire n4891_o; + wire n4895_o; + wire n4896_o; + wire n4897_o; + wire n4898_o; + wire n4902_o; + wire n4903_o; + wire n4904_o; + wire n4905_o; + wire n4906_o; + wire n4907_o; + wire n4908_o; + wire n4909_o; + wire [3:0] n4910_o; + wire [3:0] n4922_o; + localparam [7:0] n4923_o = 8'b11111111; + wire [3:0] n4924_o; + wire [3:0] n4926_o; + wire [3:0] n4927_o; + wire n4929_o; + wire n4930_o; + wire n4931_o; + wire n4932_o; + wire [3:0] n4933_o; + reg [3:0] n4934_q; + wire [2:0] n4935_o; + reg [2:0] n4936_q; + wire [7:0] n4937_o; + assign data_o = n4937_o; + assign carry_o = n4929_o; + assign aux_carry_o = n4930_o; + assign f0_o = n4931_o; + assign bs_o = n4932_o; + /* psw.vhd:101:10 */ + assign psw_q = n4934_q; // (signal) + /* psw.vhd:103:10 */ + assign sp_q = n4936_q; // (signal) + /* psw.vhd:119:14 */ + assign n4876_o = ~res_i; + /* psw.vhd:131:34 */ + assign n4880_o = data_i[2:0]; + /* psw.vhd:130:9 */ + assign n4881_o = write_sp_i ? n4880_o : sp_q; + /* psw.vhd:136:25 */ + assign n4883_o = sp_q + 3'b001; + /* psw.vhd:135:9 */ + assign n4884_o = inc_stackp_i ? n4883_o : n4881_o; + /* psw.vhd:140:25 */ + assign n4886_o = sp_q - 3'b001; + /* psw.vhd:139:9 */ + assign n4887_o = dec_stackp_i ? n4886_o : n4884_o; + assign n4888_o = data_i[7]; + assign n4889_o = psw_q[3]; + /* psw.vhd:127:9 */ + assign n4890_o = write_psw_i ? n4888_o : n4889_o; + /* psw.vhd:144:9 */ + assign n4891_o = write_carry_i ? special_data_i : n4890_o; + assign n4895_o = data_i[6]; + assign n4896_o = psw_q[2]; + /* psw.vhd:127:9 */ + assign n4897_o = write_psw_i ? n4895_o : n4896_o; + /* psw.vhd:148:9 */ + assign n4898_o = write_aux_carry_i ? aux_carry_i : n4897_o; + assign n4902_o = data_i[5]; + assign n4903_o = psw_q[1]; + /* psw.vhd:127:9 */ + assign n4904_o = write_psw_i ? n4902_o : n4903_o; + /* psw.vhd:152:9 */ + assign n4905_o = write_f0_i ? special_data_i : n4904_o; + assign n4906_o = data_i[4]; + assign n4907_o = psw_q[0]; + /* psw.vhd:127:9 */ + assign n4908_o = write_psw_i ? n4906_o : n4907_o; + /* psw.vhd:156:9 */ + assign n4909_o = write_bs_i ? special_data_i : n4908_o; + assign n4910_o = {n4891_o, n4898_o, n4905_o, n4909_o}; + /* psw.vhd:182:5 */ + assign n4922_o = read_psw_i ? psw_q : 4'b1111; + assign n4924_o = n4923_o[3:0]; + /* psw.vhd:187:33 */ + assign n4926_o = {1'b1, sp_q}; + /* psw.vhd:186:5 */ + assign n4927_o = read_sp_i ? n4926_o : n4924_o; + /* psw.vhd:207:23 */ + assign n4929_o = psw_q[3]; + /* psw.vhd:208:23 */ + assign n4930_o = psw_q[2]; + /* psw.vhd:209:23 */ + assign n4931_o = psw_q[1]; + /* psw.vhd:210:23 */ + assign n4932_o = psw_q[0]; + /* psw.vhd:123:5 */ + assign n4933_o = en_clk_i ? n4910_o : psw_q; + /* psw.vhd:123:5 */ + always @(posedge clk_i or posedge n4876_o) + if (n4876_o) + n4934_q <= 4'b0000; + else + n4934_q <= n4933_o; + /* psw.vhd:123:5 */ + assign n4935_o = en_clk_i ? n4887_o : sp_q; + /* psw.vhd:123:5 */ + always @(posedge clk_i or posedge n4876_o) + if (n4876_o) + n4936_q <= 3'b000; + else + n4936_q <= n4935_o; + /* psw.vhd:119:5 */ + assign n4937_o = {n4922_o, n4927_o}; +endmodule + +module t48_pmem_ctrl + (input clk_i, + input res_i, + input en_clk_i, + input [7:0] data_i, + input write_pcl_i, + input read_pcl_i, + input write_pch_i, + input read_pch_i, + input inc_pc_i, + input write_pmem_addr_i, + input [1:0] addr_type_i, + input read_pmem_i, + input [7:0] pmem_data_i, + output [7:0] data_o, + output [11:0] pmem_addr_o); + wire [11:0] program_counter_q; + wire [11:0] pmem_addr_s; + wire [11:0] pmem_addr_q; + wire n4802_o; + wire [3:0] n4804_o; + wire [10:0] n4805_o; + wire [10:0] n4807_o; + wire [10:0] n4808_o; + wire [10:0] n4809_o; + wire [7:0] n4810_o; + wire [7:0] n4811_o; + wire [7:0] n4812_o; + wire [2:0] n4813_o; + wire [2:0] n4814_o; + wire [2:0] n4815_o; + wire n4816_o; + wire n4817_o; + wire n4818_o; + wire [11:0] n4819_o; + wire [7:0] n4820_o; + wire [7:0] n4821_o; + wire [3:0] n4822_o; + wire [3:0] n4823_o; + wire [3:0] n4824_o; + wire [11:0] n4826_o; + wire n4828_o; + wire n4838_o; + wire n4840_o; + wire n4843_o; + wire [2:0] n4844_o; + wire [7:0] n4845_o; + reg [7:0] n4846_o; + wire [3:0] n4847_o; + reg [3:0] n4848_o; + wire [7:0] n4852_o; + wire [3:0] n4853_o; + wire [3:0] n4855_o; + wire [3:0] n4856_o; + wire [3:0] n4857_o; + wire [3:0] n4858_o; + wire [3:0] n4860_o; + wire [7:0] n4861_o; + wire [7:0] n4862_o; + wire [11:0] n4865_o; + reg [11:0] n4866_q; + wire [11:0] n4867_o; + wire [11:0] n4868_o; + reg [11:0] n4869_q; + assign data_o = n4862_o; + assign pmem_addr_o = pmem_addr_q; + /* pmem_ctrl.vhd:98:10 */ + assign program_counter_q = n4866_q; // (signal) + /* pmem_ctrl.vhd:102:10 */ + assign pmem_addr_s = n4867_o; // (signal) + /* pmem_ctrl.vhd:103:10 */ + assign pmem_addr_q = n4869_q; // (signal) + /* pmem_ctrl.vhd:115:14 */ + assign n4802_o = ~res_i; + /* pmem_ctrl.vhd:127:28 */ + assign n4804_o = data_i[3:0]; + /* pmem_ctrl.vhd:133:30 */ + assign n4805_o = program_counter_q[10:0]; + /* pmem_ctrl.vhd:133:49 */ + assign n4807_o = n4805_o + 11'b00000000001; + /* p2.vhd:153:3 */ + assign n4808_o = program_counter_q[10:0]; + /* pmem_ctrl.vhd:128:9 */ + assign n4809_o = inc_pc_i ? n4807_o : n4808_o; + /* p2.vhd:115:5 */ + assign n4810_o = n4809_o[7:0]; + /* p2.vhd:115:5 */ + assign n4811_o = program_counter_q[7:0]; + /* pmem_ctrl.vhd:125:9 */ + assign n4812_o = write_pch_i ? n4811_o : n4810_o; + /* decoder.vhd:521:15 */ + assign n4813_o = n4809_o[10:8]; + /* decoder.vhd:521:15 */ + assign n4814_o = n4804_o[2:0]; + /* pmem_ctrl.vhd:125:9 */ + assign n4815_o = write_pch_i ? n4814_o : n4813_o; + /* p2.vhd:155:5 */ + assign n4816_o = n4804_o[3]; + assign n4817_o = program_counter_q[11]; + /* pmem_ctrl.vhd:125:9 */ + assign n4818_o = write_pch_i ? n4816_o : n4817_o; + assign n4819_o = {n4818_o, n4815_o, n4812_o}; + /* decoder_pack-p.vhd:115:14 */ + assign n4820_o = n4819_o[7:0]; + /* pmem_ctrl.vhd:123:9 */ + assign n4821_o = write_pcl_i ? data_i : n4820_o; + /* decoder_pack-p.vhd:114:14 */ + assign n4822_o = n4819_o[11:8]; + assign n4823_o = program_counter_q[11:8]; + /* pmem_ctrl.vhd:123:9 */ + assign n4824_o = write_pcl_i ? n4823_o : n4822_o; + assign n4826_o = {n4824_o, n4821_o}; + /* pmem_ctrl.vhd:120:7 */ + assign n4828_o = en_clk_i & write_pmem_addr_i; + /* pmem_ctrl.vhd:165:7 */ + assign n4838_o = addr_type_i == 2'b00; + /* pmem_ctrl.vhd:169:7 */ + assign n4840_o = addr_type_i == 2'b01; + /* pmem_ctrl.vhd:175:7 */ + assign n4843_o = addr_type_i == 2'b10; + assign n4844_o = {n4843_o, n4840_o, n4838_o}; + assign n4845_o = program_counter_q[7:0]; + /* pmem_ctrl.vhd:164:5 */ + always @* + case (n4844_o) + 3'b100: n4846_o = data_i; + 3'b010: n4846_o = data_i; + 3'b001: n4846_o = n4845_o; + default: n4846_o = n4845_o; + endcase + assign n4847_o = program_counter_q[11:8]; + /* pmem_ctrl.vhd:164:5 */ + always @* + case (n4844_o) + 3'b100: n4848_o = 4'b0011; + 3'b010: n4848_o = n4847_o; + 3'b001: n4848_o = n4847_o; + default: n4848_o = n4847_o; + endcase + /* pmem_ctrl.vhd:207:51 */ + assign n4852_o = program_counter_q[7:0]; + /* pmem_ctrl.vhd:209:63 */ + assign n4853_o = program_counter_q[11:8]; + /* pmem_ctrl.vhd:208:5 */ + assign n4855_o = read_pch_i ? n4853_o : 4'b1111; + assign n4856_o = n4852_o[3:0]; + /* pmem_ctrl.vhd:206:5 */ + assign n4857_o = read_pcl_i ? n4856_o : n4855_o; + assign n4858_o = n4852_o[7:4]; + /* pmem_ctrl.vhd:206:5 */ + assign n4860_o = read_pcl_i ? n4858_o : 4'b1111; + assign n4861_o = {n4860_o, n4857_o}; + /* pmem_ctrl.vhd:204:5 */ + assign n4862_o = read_pmem_i ? pmem_data_i : n4861_o; + /* pmem_ctrl.vhd:119:5 */ + assign n4865_o = en_clk_i ? n4826_o : program_counter_q; + /* pmem_ctrl.vhd:119:5 */ + always @(posedge clk_i or posedge n4802_o) + if (n4802_o) + n4866_q <= 12'b000000000000; + else + n4866_q <= n4865_o; + /* pmem_ctrl.vhd:115:5 */ + assign n4867_o = {n4848_o, n4846_o}; + /* pmem_ctrl.vhd:119:5 */ + assign n4868_o = n4828_o ? pmem_addr_s : pmem_addr_q; + /* pmem_ctrl.vhd:119:5 */ + always @(posedge clk_i or posedge n4802_o) + if (n4802_o) + n4869_q <= 12'b000000000000; + else + n4869_q <= n4868_o; +endmodule + +module t48_p2 + (input clk_i, + input res_i, + input en_clk_i, + input xtal_i, + input xtal_en_i, + input [7:0] data_i, + input write_p2_i, + input write_exp_i, + input read_p2_i, + input read_reg_i, + input read_exp_i, + input output_pch_i, + input [3:0] pch_i, + input [7:0] p2_i, + output [7:0] data_o, + output [7:0] p2_o, + output p2l_low_imp_o, + output p2h_low_imp_o); + wire [7:0] p2_q; + wire l_low_imp_q; + wire h_low_imp_q; + wire en_clk_q; + wire l_low_imp_del_q; + wire h_low_imp_del_q; + wire output_pch_q; + wire n4701_o; + wire [3:0] n4703_o; + wire [3:0] n4704_o; + wire [3:0] n4705_o; + wire n4708_o; + wire [3:0] n4709_o; + wire [3:0] n4710_o; + wire [3:0] n4711_o; + wire [3:0] n4712_o; + wire [3:0] n4713_o; + wire n4715_o; + wire n4719_o; + wire [7:0] n4721_o; + wire n4736_o; + wire [3:0] n4738_o; + wire [3:0] n4739_o; + wire [3:0] n4740_o; + wire n4741_o; + wire n4742_o; + wire n4743_o; + wire n4746_o; + wire n4747_o; + wire n4750_o; + wire [7:0] n4751_o; + wire [3:0] n4774_o; + wire [7:0] n4776_o; + wire [7:0] n4777_o; + wire [7:0] n4778_o; + wire [7:0] n4780_o; + wire [7:0] n4783_o; + reg [7:0] n4784_q; + wire n4785_o; + reg n4786_q; + wire n4787_o; + reg n4788_q; + wire n4789_o; + reg n4790_q; + wire n4791_o; + reg n4792_q; + wire n4793_o; + reg n4794_q; + wire n4795_o; + reg n4796_q; + wire [7:0] n4797_o; + reg [7:0] n4798_q; + assign data_o = n4780_o; + assign p2_o = n4798_q; + assign p2l_low_imp_o = l_low_imp_del_q; + assign p2h_low_imp_o = h_low_imp_del_q; + /* p2.vhd:89:10 */ + assign p2_q = n4784_q; // (signal) + /* p2.vhd:92:10 */ + assign l_low_imp_q = n4786_q; // (signal) + /* p2.vhd:93:10 */ + assign h_low_imp_q = n4788_q; // (signal) + /* p2.vhd:95:10 */ + assign en_clk_q = n4790_q; // (signal) + /* p2.vhd:96:10 */ + assign l_low_imp_del_q = n4792_q; // (signal) + /* p2.vhd:97:10 */ + assign h_low_imp_del_q = n4794_q; // (signal) + /* p2.vhd:98:10 */ + assign output_pch_q = n4796_q; // (signal) + /* p2.vhd:110:14 */ + assign n4701_o = ~res_i; + /* p2.vhd:129:41 */ + assign n4703_o = data_i[3:0]; + /* decoder.vhd:496:15 */ + assign n4704_o = p2_q[3:0]; + /* p2.vhd:127:9 */ + assign n4705_o = write_exp_i ? n4703_o : n4704_o; + /* p2.vhd:127:9 */ + assign n4708_o = write_exp_i ? 1'b1 : 1'b0; + /* decoder.vhd:521:15 */ + assign n4709_o = data_i[3:0]; + /* p2.vhd:121:9 */ + assign n4710_o = write_p2_i ? n4709_o : n4705_o; + /* decoder.vhd:521:15 */ + assign n4711_o = data_i[7:4]; + /* decoder.vhd:521:15 */ + assign n4712_o = p2_q[7:4]; + /* p2.vhd:121:9 */ + assign n4713_o = write_p2_i ? n4711_o : n4712_o; + /* p2.vhd:121:9 */ + assign n4715_o = write_p2_i ? 1'b1 : n4708_o; + /* p2.vhd:121:9 */ + assign n4719_o = write_p2_i ? 1'b1 : 1'b0; + assign n4721_o = {n4713_o, n4710_o}; + /* p2.vhd:155:14 */ + assign n4736_o = ~res_i; + /* decoder.vhd:506:15 */ + assign n4738_o = p2_q[3:0]; + /* p2.vhd:170:9 */ + assign n4739_o = output_pch_i ? pch_i : n4738_o; + /* decoder.vhd:499:26 */ + assign n4740_o = p2_q[7:4]; + /* p2.vhd:179:26 */ + assign n4741_o = output_pch_q ^ output_pch_i; + /* p2.vhd:179:44 */ + assign n4742_o = n4741_o | l_low_imp_q; + /* p2.vhd:178:21 */ + assign n4743_o = n4742_o & en_clk_q; + /* p2.vhd:178:9 */ + assign n4746_o = n4743_o ? 1'b1 : 1'b0; + /* p2.vhd:189:21 */ + assign n4747_o = h_low_imp_q & en_clk_q; + /* p2.vhd:189:9 */ + assign n4750_o = n4747_o ? 1'b1 : 1'b0; + /* decoder.vhd:499:22 */ + assign n4751_o = {n4740_o, n4739_o}; + /* p2.vhd:221:32 */ + assign n4774_o = p2_i[3:0]; + /* p2.vhd:221:26 */ + assign n4776_o = {4'b0000, n4774_o}; + /* p2.vhd:220:7 */ + assign n4777_o = read_exp_i ? n4776_o : p2_i; + /* p2.vhd:218:7 */ + assign n4778_o = read_reg_i ? p2_q : n4777_o; + /* p2.vhd:217:5 */ + assign n4780_o = read_p2_i ? n4778_o : 8'b11111111; + /* p2.vhd:115:5 */ + assign n4783_o = en_clk_i ? n4721_o : p2_q; + /* p2.vhd:115:5 */ + always @(posedge clk_i or posedge n4701_o) + if (n4701_o) + n4784_q <= 8'b11111111; + else + n4784_q <= n4783_o; + /* p2.vhd:115:5 */ + assign n4785_o = en_clk_i ? n4715_o : l_low_imp_q; + /* p2.vhd:115:5 */ + always @(posedge clk_i or posedge n4701_o) + if (n4701_o) + n4786_q <= 1'b0; + else + n4786_q <= n4785_o; + /* p2.vhd:115:5 */ + assign n4787_o = en_clk_i ? n4719_o : h_low_imp_q; + /* p2.vhd:115:5 */ + always @(posedge clk_i or posedge n4701_o) + if (n4701_o) + n4788_q <= 1'b0; + else + n4788_q <= n4787_o; + /* p2.vhd:162:5 */ + assign n4789_o = xtal_en_i ? en_clk_i : en_clk_q; + /* p2.vhd:162:5 */ + always @(posedge xtal_i or posedge n4736_o) + if (n4736_o) + n4790_q <= 1'b0; + else + n4790_q <= n4789_o; + /* p2.vhd:162:5 */ + assign n4791_o = xtal_en_i ? n4746_o : l_low_imp_del_q; + /* p2.vhd:162:5 */ + always @(posedge xtal_i or posedge n4736_o) + if (n4736_o) + n4792_q <= 1'b0; + else + n4792_q <= n4791_o; + /* p2.vhd:162:5 */ + assign n4793_o = xtal_en_i ? n4750_o : h_low_imp_del_q; + /* p2.vhd:162:5 */ + always @(posedge xtal_i or posedge n4736_o) + if (n4736_o) + n4794_q <= 1'b0; + else + n4794_q <= n4793_o; + /* p2.vhd:162:5 */ + assign n4795_o = xtal_en_i ? output_pch_i : output_pch_q; + /* p2.vhd:162:5 */ + always @(posedge xtal_i or posedge n4736_o) + if (n4736_o) + n4796_q <= 1'b0; + else + n4796_q <= n4795_o; + /* p2.vhd:162:5 */ + assign n4797_o = xtal_en_i ? n4751_o : n4798_q; + /* p2.vhd:162:5 */ + always @(posedge xtal_i or posedge n4736_o) + if (n4736_o) + n4798_q <= 8'b11111111; + else + n4798_q <= n4797_o; +endmodule + +module t48_p1 + (input clk_i, + input res_i, + input en_clk_i, + input [7:0] data_i, + input write_p1_i, + input read_p1_i, + input read_reg_i, + input [7:0] p1_i, + output [7:0] data_o, + output [7:0] p1_o, + output p1_low_imp_o); + wire [7:0] p1_q; + wire low_imp_q; + wire n4671_o; + wire n4676_o; + wire n4677_o; + wire [7:0] n4687_o; + wire [7:0] n4689_o; + wire [7:0] n4692_o; + reg [7:0] n4693_q; + wire n4694_o; + reg n4695_q; + assign data_o = n4689_o; + assign p1_o = p1_q; + assign p1_low_imp_o = low_imp_q; + /* p1.vhd:81:10 */ + assign p1_q = n4693_q; // (signal) + /* p1.vhd:84:10 */ + assign low_imp_q = n4695_q; // (signal) + /* p1.vhd:96:14 */ + assign n4671_o = ~res_i; + /* p1.vhd:103:9 */ + assign n4676_o = write_p1_i ? 1'b1 : 1'b0; + /* p1.vhd:101:7 */ + assign n4677_o = en_clk_i & write_p1_i; + /* p1.vhd:133:7 */ + assign n4687_o = read_reg_i ? p1_q : p1_i; + /* p1.vhd:132:5 */ + assign n4689_o = read_p1_i ? n4687_o : 8'b11111111; + /* p1.vhd:100:5 */ + assign n4692_o = n4677_o ? data_i : p1_q; + /* p1.vhd:100:5 */ + always @(posedge clk_i or posedge n4671_o) + if (n4671_o) + n4693_q <= 8'b11111111; + else + n4693_q <= n4692_o; + /* p1.vhd:100:5 */ + assign n4694_o = en_clk_i ? n4676_o : low_imp_q; + /* p1.vhd:100:5 */ + always @(posedge clk_i or posedge n4671_o) + if (n4671_o) + n4695_q <= 1'b0; + else + n4695_q <= n4694_o; +endmodule + +module t48_timer_4 + (input clk_i, + input res_i, + input en_clk_i, + input t1_i, + input [2:0] clk_mstate_i, + input [7:0] data_i, + input read_timer_i, + input write_timer_i, + input start_t_i, + input start_cnt_i, + input stop_tcnt_i, + output [7:0] data_o, + output overflow_o); + wire [7:0] counter_q; + wire overflow_q; + wire increment_s; + wire [1:0] inc_sel_q; + wire t1_q; + wire t1_inc_s; + wire [4:0] prescaler_q; + wire pre_inc_s; + wire n4557_o; + wire n4559_o; + wire n4561_o; + wire n4562_o; + wire n4563_o; + wire n4566_o; + wire n4568_o; + wire n4572_o; + wire n4574_o; + wire n4575_o; + wire n4578_o; + wire n4580_o; + wire n4582_o; + wire [2:0] n4583_o; + reg n4586_o; + wire n4590_o; + wire [7:0] n4593_o; + wire n4595_o; + wire n4598_o; + wire [7:0] n4599_o; + wire n4601_o; + wire [7:0] n4602_o; + wire n4604_o; + wire n4607_o; + wire n4609_o; + wire n4611_o; + wire n4614_o; + wire [4:0] n4616_o; + wire [4:0] n4617_o; + wire [4:0] n4619_o; + wire [1:0] n4621_o; + wire [1:0] n4623_o; + wire [1:0] n4625_o; + wire n4629_o; + wire [7:0] n4647_o; + wire n4656_o; + wire [7:0] n4657_o; + reg [7:0] n4658_q; + wire n4659_o; + reg n4660_q; + wire [1:0] n4661_o; + reg [1:0] n4662_q; + wire n4663_o; + reg n4664_q; + wire [4:0] n4665_o; + reg [4:0] n4666_q; + assign data_o = n4647_o; + assign overflow_o = n4656_o; + /* timer.vhd:89:10 */ + assign counter_q = n4658_q; // (signal) + /* timer.vhd:90:10 */ + assign overflow_q = n4660_q; // (signal) + /* timer.vhd:94:10 */ + assign increment_s = n4586_o; // (signal) + /* timer.vhd:95:10 */ + assign inc_sel_q = n4662_q; // (signal) + /* timer.vhd:98:10 */ + assign t1_q = n4664_q; // (signal) + /* timer.vhd:99:10 */ + assign t1_inc_s = n4568_o; // (signal) + /* timer.vhd:102:10 */ + assign prescaler_q = n4666_q; // (signal) + /* timer.vhd:103:10 */ + assign pre_inc_s = n4575_o; // (signal) + /* timer.vhd:134:48 */ + assign n4557_o = clk_mstate_i == 3'b011; + /* timer.vhd:134:31 */ + assign n4559_o = n4557_o & 1'b1; + /* timer.vhd:133:59 */ + assign n4561_o = 1'b0 | n4559_o; + /* timer.vhd:136:30 */ + assign n4562_o = ~t1_i; + /* timer.vhd:136:21 */ + assign n4563_o = n4562_o & t1_q; + /* timer.vhd:136:7 */ + assign n4566_o = n4563_o ? 1'b1 : 1'b0; + /* timer.vhd:133:5 */ + assign n4568_o = n4561_o ? n4566_o : 1'b0; + /* timer.vhd:146:29 */ + assign n4572_o = clk_mstate_i == 3'b011; + /* timer.vhd:146:55 */ + assign n4574_o = prescaler_q == 5'b11111; + /* timer.vhd:146:39 */ + assign n4575_o = n4574_o & n4572_o; + /* timer.vhd:163:7 */ + assign n4578_o = inc_sel_q == 2'b00; + /* timer.vhd:165:7 */ + assign n4580_o = inc_sel_q == 2'b01; + /* timer.vhd:167:7 */ + assign n4582_o = inc_sel_q == 2'b10; + assign n4583_o = {n4582_o, n4580_o, n4578_o}; + /* timer.vhd:162:5 */ + always @* + case (n4583_o) + 3'b100: n4586_o = t1_inc_s; + 3'b010: n4586_o = pre_inc_s; + 3'b001: n4586_o = 1'b0; + default: n4586_o = 1'b0; + endcase + /* timer.vhd:186:14 */ + assign n4590_o = ~res_i; + /* timer.vhd:203:37 */ + assign n4593_o = counter_q + 8'b00000001; + /* timer.vhd:205:24 */ + assign n4595_o = counter_q == 8'b11111111; + /* timer.vhd:205:11 */ + assign n4598_o = n4595_o ? 1'b1 : 1'b0; + /* timer.vhd:202:9 */ + assign n4599_o = increment_s ? n4593_o : counter_q; + /* timer.vhd:202:9 */ + assign n4601_o = increment_s ? n4598_o : 1'b0; + /* timer.vhd:199:9 */ + assign n4602_o = write_timer_i ? data_i : n4599_o; + /* timer.vhd:199:9 */ + assign n4604_o = write_timer_i ? 1'b0 : n4601_o; + /* timer.vhd:213:52 */ + assign n4607_o = clk_mstate_i == 3'b011; + /* timer.vhd:213:35 */ + assign n4609_o = n4607_o & 1'b1; + /* timer.vhd:212:63 */ + assign n4611_o = 1'b0 | n4609_o; + /* timer.vhd:221:28 */ + assign n4614_o = clk_mstate_i == 3'b010; + /* timer.vhd:222:39 */ + assign n4616_o = prescaler_q + 5'b00001; + /* timer.vhd:221:9 */ + assign n4617_o = n4614_o ? n4616_o : prescaler_q; + /* timer.vhd:218:9 */ + assign n4619_o = start_t_i ? 5'b00000 : n4617_o; + /* timer.vhd:231:9 */ + assign n4621_o = stop_tcnt_i ? 2'b00 : inc_sel_q; + /* timer.vhd:229:9 */ + assign n4623_o = start_cnt_i ? 2'b10 : n4621_o; + /* timer.vhd:227:9 */ + assign n4625_o = start_t_i ? 2'b01 : n4623_o; + /* timer.vhd:194:7 */ + assign n4629_o = en_clk_i & n4611_o; + /* timer.vhd:248:17 */ + assign n4647_o = read_timer_i ? counter_q : 8'b11111111; + /* t48_pack-p.vhd:66:5 */ + assign n4656_o = overflow_q ? 1'b1 : 1'b0; + /* timer.vhd:193:5 */ + assign n4657_o = en_clk_i ? n4602_o : counter_q; + /* timer.vhd:193:5 */ + always @(posedge clk_i or posedge n4590_o) + if (n4590_o) + n4658_q <= 8'b00000000; + else + n4658_q <= n4657_o; + /* timer.vhd:193:5 */ + assign n4659_o = en_clk_i ? n4604_o : overflow_q; + /* timer.vhd:193:5 */ + always @(posedge clk_i or posedge n4590_o) + if (n4590_o) + n4660_q <= 1'b0; + else + n4660_q <= n4659_o; + /* timer.vhd:193:5 */ + assign n4661_o = en_clk_i ? n4625_o : inc_sel_q; + /* timer.vhd:193:5 */ + always @(posedge clk_i or posedge n4590_o) + if (n4590_o) + n4662_q <= 2'b00; + else + n4662_q <= n4661_o; + /* timer.vhd:193:5 */ + assign n4663_o = n4629_o ? t1_i : t1_q; + /* timer.vhd:193:5 */ + always @(posedge clk_i or posedge n4590_o) + if (n4590_o) + n4664_q <= 1'b0; + else + n4664_q <= n4663_o; + /* timer.vhd:193:5 */ + assign n4665_o = en_clk_i ? n4619_o : prescaler_q; + /* timer.vhd:193:5 */ + always @(posedge clk_i or posedge n4590_o) + if (n4590_o) + n4666_q <= 5'b00000; + else + n4666_q <= n4665_o; +endmodule + +module t48_dmem_ctrl + (input clk_i, + input res_i, + input en_clk_i, + input [7:0] data_i, + input write_dmem_addr_i, + input write_dmem_i, + input read_dmem_i, + input [1:0] addr_type_i, + input bank_select_i, + input [7:0] dmem_data_i, + output [7:0] data_o, + output [7:0] dmem_addr_o, + output dmem_we_o, + output [7:0] dmem_data_o); + wire [7:0] dmem_addr_s; + wire [7:0] dmem_addr_q; + wire n4474_o; + wire [2:0] n4475_o; + localparam [7:0] n4476_o = 8'b00000000; + wire [1:0] n4479_o; + wire [1:0] n4480_o; + wire [2:0] n4481_o; + wire n4483_o; + wire [2:0] n4484_o; + wire [5:0] n4487_o; + wire [5:0] n4489_o; + localparam [7:0] n4490_o = 8'b00000000; + wire [1:0] n4491_o; + wire n4493_o; + wire n4496_o; + wire [3:0] n4497_o; + wire n4498_o; + wire n4499_o; + wire n4500_o; + wire n4501_o; + reg n4502_o; + wire [1:0] n4503_o; + wire [1:0] n4504_o; + wire [1:0] n4505_o; + wire [1:0] n4506_o; + reg [1:0] n4507_o; + wire [1:0] n4508_o; + wire [1:0] n4509_o; + wire [1:0] n4510_o; + reg [1:0] n4511_o; + wire n4512_o; + wire n4513_o; + wire n4514_o; + wire n4515_o; + reg n4516_o; + wire [1:0] n4517_o; + wire [1:0] n4518_o; + wire [1:0] n4519_o; + reg [1:0] n4520_o; + wire n4530_o; + wire n4533_o; + wire n4538_o; + wire [7:0] n4539_o; + wire [7:0] n4540_o; + wire n4549_o; + wire [7:0] n4550_o; + wire [7:0] n4551_o; + reg [7:0] n4552_q; + assign data_o = n4540_o; + assign dmem_addr_o = n4539_o; + assign dmem_we_o = n4549_o; + assign dmem_data_o = data_i; + /* dmem_ctrl.vhd:91:10 */ + assign dmem_addr_s = n4550_o; // (signal) + /* dmem_ctrl.vhd:92:10 */ + assign dmem_addr_q = n4552_q; // (signal) + /* dmem_ctrl.vhd:112:7 */ + assign n4474_o = addr_type_i == 2'b00; + /* dmem_ctrl.vhd:117:44 */ + assign n4475_o = data_i[2:0]; + /* decoder.vhd:155:5 */ + assign n4479_o = n4476_o[4:3]; + /* dmem_ctrl.vhd:119:9 */ + assign n4480_o = bank_select_i ? 2'b11 : n4479_o; + /* decoder.vhd:153:5 */ + assign n4481_o = n4476_o[7:5]; + /* dmem_ctrl.vhd:115:7 */ + assign n4483_o = addr_type_i == 2'b01; + /* dmem_ctrl.vhd:126:53 */ + assign n4484_o = data_i[2:0]; + /* decoder.vhd:142:5 */ + assign n4487_o = {2'b00, n4484_o, 1'b0}; + /* dmem_ctrl.vhd:128:51 */ + assign n4489_o = n4487_o + 6'b001000; + /* decoder.vhd:135:5 */ + assign n4491_o = n4490_o[7:6]; + /* dmem_ctrl.vhd:124:7 */ + assign n4493_o = addr_type_i == 2'b10; + /* dmem_ctrl.vhd:133:7 */ + assign n4496_o = addr_type_i == 2'b11; + /* decoder.vhd:125:5 */ + assign n4497_o = {n4496_o, n4493_o, n4483_o, n4474_o}; + /* decoder.vhd:124:5 */ + assign n4498_o = data_i[0]; + /* decoder.vhd:123:5 */ + assign n4499_o = n4475_o[0]; + /* decoder.vhd:121:5 */ + assign n4500_o = n4489_o[0]; + /* decoder.vhd:120:5 */ + assign n4501_o = dmem_addr_q[0]; + /* dmem_ctrl.vhd:111:5 */ + always @* + case (n4497_o) + 4'b1000: n4502_o = 1'b1; + 4'b0100: n4502_o = n4500_o; + 4'b0010: n4502_o = n4499_o; + 4'b0001: n4502_o = n4498_o; + default: n4502_o = n4501_o; + endcase + /* decoder.vhd:116:5 */ + assign n4503_o = data_i[2:1]; + /* decoder.vhd:115:5 */ + assign n4504_o = n4475_o[2:1]; + /* decoder.vhd:114:5 */ + assign n4505_o = n4489_o[2:1]; + /* decoder.vhd:113:5 */ + assign n4506_o = dmem_addr_q[2:1]; + /* dmem_ctrl.vhd:111:5 */ + always @* + case (n4497_o) + 4'b1000: n4507_o = n4506_o; + 4'b0100: n4507_o = n4505_o; + 4'b0010: n4507_o = n4504_o; + 4'b0001: n4507_o = n4503_o; + default: n4507_o = n4506_o; + endcase + /* decoder.vhd:109:5 */ + assign n4508_o = data_i[4:3]; + /* decoder.vhd:108:5 */ + assign n4509_o = n4489_o[4:3]; + /* decoder.vhd:107:5 */ + assign n4510_o = dmem_addr_q[4:3]; + /* dmem_ctrl.vhd:111:5 */ + always @* + case (n4497_o) + 4'b1000: n4511_o = n4510_o; + 4'b0100: n4511_o = n4509_o; + 4'b0010: n4511_o = n4480_o; + 4'b0001: n4511_o = n4508_o; + default: n4511_o = n4510_o; + endcase + /* decoder.vhd:105:5 */ + assign n4512_o = data_i[5]; + /* decoder.vhd:104:5 */ + assign n4513_o = n4481_o[0]; + /* decoder.vhd:103:5 */ + assign n4514_o = n4489_o[5]; + /* decoder.vhd:102:5 */ + assign n4515_o = dmem_addr_q[5]; + /* dmem_ctrl.vhd:111:5 */ + always @* + case (n4497_o) + 4'b1000: n4516_o = n4515_o; + 4'b0100: n4516_o = n4514_o; + 4'b0010: n4516_o = n4513_o; + 4'b0001: n4516_o = n4512_o; + default: n4516_o = n4515_o; + endcase + /* decoder.vhd:100:5 */ + assign n4517_o = data_i[7:6]; + /* decoder.vhd:99:5 */ + assign n4518_o = n4481_o[2:1]; + /* decoder.vhd:98:5 */ + assign n4519_o = dmem_addr_q[7:6]; + /* dmem_ctrl.vhd:111:5 */ + always @* + case (n4497_o) + 4'b1000: n4520_o = n4519_o; + 4'b0100: n4520_o = n4491_o; + 4'b0010: n4520_o = n4518_o; + 4'b0001: n4520_o = n4517_o; + default: n4520_o = n4519_o; + endcase + /* dmem_ctrl.vhd:165:14 */ + assign n4530_o = ~res_i; + /* dmem_ctrl.vhd:169:7 */ + assign n4533_o = en_clk_i & write_dmem_addr_i; + /* dmem_ctrl.vhd:188:41 */ + assign n4538_o = en_clk_i & write_dmem_addr_i; + /* dmem_ctrl.vhd:188:18 */ + assign n4539_o = n4538_o ? dmem_addr_s : dmem_addr_q; + /* dmem_ctrl.vhd:196:18 */ + assign n4540_o = read_dmem_i ? dmem_data_i : 8'b11111111; + /* t48_pack-p.vhd:66:5 */ + assign n4549_o = write_dmem_i ? 1'b1 : 1'b0; + assign n4550_o = {n4520_o, n4516_o, n4511_o, n4507_o, n4502_o}; + /* dmem_ctrl.vhd:168:5 */ + assign n4551_o = n4533_o ? dmem_addr_s : dmem_addr_q; + /* dmem_ctrl.vhd:168:5 */ + always @(posedge clk_i or posedge n4530_o) + if (n4530_o) + n4552_q <= 8'b00000000; + else + n4552_q <= n4551_o; +endmodule + +module t48_decoder_1_0_0 + (input clk_i, + input res_i, + input en_clk_i, + input xtal_i, + input xtal_en_i, + input ea_i, + input ale_i, + input int_n_i, + input [7:0] data_i, + input bus_set_f1_i, + input bus_clear_f1_i, + input alu_carry_i, + input alu_da_overflow_i, + input [2:0] clk_mstate_i, + input clk_second_cycle_i, + input cnd_take_branch_i, + input psw_carry_i, + input psw_aux_carry_i, + input psw_f0_i, + input tim_overflow_i, + output t0_dir_o, + output [7:0] data_o, + output alu_write_accu_o, + output alu_write_shadow_o, + output alu_write_temp_reg_o, + output alu_read_alu_o, + output bus_write_bus_o, + output bus_read_bus_o, + output bus_ibf_int_o, + output bus_en_dma_o, + output bus_en_flags_o, + output bus_write_sts_o, + output dm_write_dmem_addr_o, + output dm_write_dmem_o, + output dm_read_dmem_o, + output p1_write_p1_o, + output p1_read_p1_o, + output p2_write_p2_o, + output p2_write_exp_o, + output p2_read_p2_o, + output p2_read_exp_o, + output pm_write_pcl_o, + output pm_read_pcl_o, + output pm_write_pch_o, + output pm_read_pch_o, + output pm_read_pmem_o, + output psw_read_psw_o, + output psw_read_sp_o, + output psw_write_psw_o, + output psw_write_sp_o, + output [3:0] alu_op_o, + output alu_use_carry_o, + output alu_da_high_o, + output alu_accu_low_o, + output alu_p06_temp_reg_o, + output alu_p60_temp_reg_o, + output bus_output_pcl_o, + output bus_bidir_bus_o, + output clk_multi_cycle_o, + output clk_assert_psen_o, + output clk_assert_prog_o, + output clk_assert_rd_o, + output clk_assert_wr_o, + output cnd_compute_take_o, + output [3:0] cnd_branch_cond_o, + output [2:0] cnd_comp_value_o, + output cnd_f1_o, + output cnd_tf_o, + output [1:0] dm_addr_type_o, + output p1_read_reg_o, + output p2_read_reg_o, + output p2_output_pch_o, + output pm_inc_pc_o, + output pm_write_pmem_addr_o, + output [1:0] pm_addr_type_o, + output psw_special_data_o, + output psw_inc_stackp_o, + output psw_dec_stackp_o, + output psw_write_carry_o, + output psw_write_aux_carry_o, + output psw_write_f0_o, + output psw_write_bs_o, + output tim_read_timer_o, + output tim_write_timer_o, + output tim_start_t_o, + output tim_start_cnt_o, + output tim_stop_tcnt_o); + wire opc_multi_cycle_s; + wire opc_read_bus_s; + wire opc_inj_int_s; + wire [7:0] opc_opcode_q; + wire [5:0] opc_mnemonic_s; + wire last_cycle_s; + wire assert_psen_s; + wire branch_taken_s; + wire branch_taken_q; + wire pm_inc_pc_s; + wire pm_write_pmem_addr_s; + wire add_inc_pc_s; + wire add_write_pmem_addr_s; + wire clear_f1_s; + wire cpl_f1_s; + wire f1_q; + wire clear_mb_s; + wire set_mb_s; + wire mb_q; + wire ent0_clk_s; + wire t0_dir_q; + wire [7:0] data_s; + wire read_dec_s; + wire tf_s; + wire bus_read_bus_s; + wire add_read_bus_s; + wire dm_write_dmem_s; + wire p2_output_exp_s; + wire movx_first_cycle_s; + wire jtf_executed_s; + wire en_tcnti_s; + wire dis_tcnti_s; + wire en_i_s; + wire dis_i_s; + wire tim_int_s; + wire retr_executed_s; + wire int_executed_s; + wire int_pending_s; + wire int_in_progress_s; + wire [6:0] mnemonic_rec_s; + wire [5:0] mnemonic_q; + wire n1116_o; + wire n1118_o; + wire n1119_o; + wire n1121_o; + wire n1122_o; + wire n1124_o; + wire n1126_o; + wire n1128_o; + wire n1130_o; + wire n1132_o; + wire n1133_o; + wire n1135_o; + wire n1136_o; + wire n1138_o; + wire n1139_o; + wire n1141_o; + wire n1143_o; + wire n1144_o; + wire n1146_o; + wire n1147_o; + wire n1149_o; + wire n1151_o; + wire n1152_o; + wire n1154_o; + wire n1155_o; + wire n1157_o; + wire n1159_o; + wire n1160_o; + wire [7:0] n1161_o; + reg [5:0] n1171_o; + reg n1180_o; + wire n1183_o; + wire n1193_o; + wire n1195_o; + wire n1196_o; + wire n1198_o; + wire n1199_o; + wire n1201_o; + wire n1202_o; + wire n1204_o; + wire n1205_o; + wire n1207_o; + wire n1208_o; + wire n1210_o; + wire n1211_o; + wire n1213_o; + wire n1214_o; + wire n1216_o; + wire n1217_o; + wire n1219_o; + wire n1220_o; + wire n1222_o; + wire n1223_o; + wire n1225_o; + wire n1226_o; + wire n1228_o; + wire n1229_o; + wire n1231_o; + wire n1232_o; + wire n1234_o; + wire n1235_o; + wire n1237_o; + wire n1238_o; + wire n1240_o; + wire n1241_o; + wire n1243_o; + wire n1244_o; + wire n1246_o; + wire n1247_o; + wire n1249_o; + wire n1250_o; + wire n1252_o; + wire n1254_o; + wire n1255_o; + wire n1257_o; + wire n1259_o; + wire n1260_o; + wire n1262_o; + wire n1263_o; + wire n1265_o; + wire n1266_o; + wire n1268_o; + wire n1269_o; + wire n1271_o; + wire n1272_o; + wire n1274_o; + wire n1275_o; + wire n1277_o; + wire n1278_o; + wire n1280_o; + wire n1281_o; + wire n1283_o; + wire n1284_o; + wire n1286_o; + wire n1288_o; + wire n1290_o; + wire n1291_o; + wire n1293_o; + wire n1294_o; + wire n1296_o; + wire n1297_o; + wire n1299_o; + wire n1300_o; + wire n1302_o; + wire n1303_o; + wire n1305_o; + wire n1306_o; + wire n1308_o; + wire n1309_o; + wire n1311_o; + wire n1313_o; + wire n1315_o; + wire n1317_o; + wire n1318_o; + wire n1320_o; + wire n1322_o; + wire n1324_o; + wire n1326_o; + wire n1327_o; + wire n1329_o; + wire n1331_o; + wire n1333_o; + wire n1334_o; + wire n1336_o; + wire n1337_o; + wire n1339_o; + wire n1340_o; + wire n1342_o; + wire n1343_o; + wire n1345_o; + wire n1346_o; + wire n1348_o; + wire n1349_o; + wire n1351_o; + wire n1352_o; + wire n1354_o; + wire n1355_o; + wire n1357_o; + wire n1359_o; + wire n1360_o; + wire n1362_o; + wire n1364_o; + wire n1365_o; + wire n1367_o; + wire n1369_o; + wire n1370_o; + wire n1372_o; + wire n1373_o; + wire n1375_o; + wire n1376_o; + wire n1378_o; + wire n1379_o; + wire n1381_o; + wire n1382_o; + wire n1384_o; + wire n1385_o; + wire n1387_o; + wire n1388_o; + wire n1390_o; + wire n1392_o; + wire n1393_o; + wire n1395_o; + wire n1397_o; + wire n1398_o; + wire n1400_o; + wire n1401_o; + wire n1403_o; + wire n1404_o; + wire n1406_o; + wire n1407_o; + wire n1409_o; + wire n1410_o; + wire n1412_o; + wire n1413_o; + wire n1415_o; + wire n1416_o; + wire n1418_o; + wire n1419_o; + wire n1421_o; + wire n1422_o; + wire n1424_o; + wire n1425_o; + wire n1427_o; + wire n1429_o; + wire n1430_o; + wire n1432_o; + wire n1433_o; + wire n1435_o; + wire n1436_o; + wire n1438_o; + wire n1439_o; + wire n1441_o; + wire n1442_o; + wire n1444_o; + wire n1445_o; + wire n1447_o; + wire n1448_o; + wire n1450_o; + wire n1452_o; + wire n1453_o; + wire n1455_o; + wire n1457_o; + wire n1458_o; + wire n1460_o; + wire n1462_o; + wire n1463_o; + wire n1465_o; + wire n1466_o; + wire n1468_o; + wire n1469_o; + wire n1471_o; + wire n1472_o; + wire n1474_o; + wire n1475_o; + wire n1477_o; + wire n1478_o; + wire n1480_o; + wire n1481_o; + wire n1483_o; + wire n1485_o; + wire n1487_o; + wire n1488_o; + wire n1490_o; + wire n1491_o; + wire n1493_o; + wire n1494_o; + wire n1496_o; + wire n1498_o; + wire n1500_o; + wire n1501_o; + wire n1503_o; + wire n1505_o; + wire n1507_o; + wire n1509_o; + wire n1510_o; + wire n1512_o; + wire n1513_o; + wire n1515_o; + wire n1516_o; + wire n1518_o; + wire n1519_o; + wire n1521_o; + wire n1522_o; + wire n1524_o; + wire n1525_o; + wire n1527_o; + wire n1528_o; + wire n1530_o; + wire n1531_o; + wire n1533_o; + wire n1534_o; + wire n1536_o; + wire n1538_o; + wire n1540_o; + wire n1541_o; + wire n1543_o; + wire n1544_o; + wire n1546_o; + wire n1547_o; + wire n1549_o; + wire n1550_o; + wire n1552_o; + wire n1553_o; + wire n1555_o; + wire n1556_o; + wire n1558_o; + wire n1559_o; + wire n1561_o; + wire n1562_o; + wire n1564_o; + wire n1565_o; + wire n1567_o; + wire n1569_o; + wire n1570_o; + wire n1572_o; + wire n1573_o; + wire n1575_o; + wire n1576_o; + wire n1578_o; + wire n1579_o; + wire n1581_o; + wire n1582_o; + wire n1584_o; + wire n1585_o; + wire n1587_o; + wire n1588_o; + wire n1590_o; + wire n1591_o; + wire n1593_o; + wire n1594_o; + wire n1596_o; + wire n1598_o; + wire n1599_o; + wire n1601_o; + wire n1603_o; + wire n1604_o; + wire n1606_o; + wire n1607_o; + wire n1609_o; + wire n1610_o; + wire n1612_o; + wire n1614_o; + wire n1615_o; + wire n1617_o; + wire n1619_o; + wire n1621_o; + wire n1622_o; + wire n1624_o; + wire n1625_o; + wire n1627_o; + wire n1628_o; + wire n1630_o; + wire n1631_o; + wire n1633_o; + wire n1634_o; + wire n1636_o; + wire n1637_o; + wire n1639_o; + wire n1640_o; + wire n1642_o; + wire n1643_o; + wire n1645_o; + wire n1646_o; + wire n1648_o; + wire n1650_o; + wire n1652_o; + wire n1653_o; + wire n1655_o; + wire n1656_o; + wire n1658_o; + wire n1659_o; + wire n1661_o; + wire n1662_o; + wire n1664_o; + wire n1665_o; + wire n1667_o; + wire n1668_o; + wire n1670_o; + wire n1671_o; + wire n1673_o; + wire n1674_o; + wire n1676_o; + wire n1677_o; + wire n1679_o; + wire n1680_o; + wire n1682_o; + wire n1683_o; + wire n1685_o; + wire n1687_o; + wire n1688_o; + wire n1690_o; + wire n1692_o; + wire n1693_o; + wire n1695_o; + wire n1697_o; + wire n1698_o; + wire n1700_o; + wire n1702_o; + wire n1703_o; + wire n1705_o; + wire n1707_o; + wire n1709_o; + wire n1710_o; + wire n1712_o; + wire n1714_o; + wire n1716_o; + wire n1717_o; + wire n1719_o; + wire n1720_o; + wire n1722_o; + wire n1723_o; + wire n1725_o; + wire n1726_o; + wire n1728_o; + wire n1729_o; + wire n1731_o; + wire n1732_o; + wire n1734_o; + wire n1735_o; + wire n1737_o; + wire n1738_o; + wire n1740_o; + wire n1741_o; + wire n1743_o; + wire n1744_o; + wire n1746_o; + wire n1747_o; + wire n1749_o; + wire n1751_o; + wire n1752_o; + wire n1754_o; + wire n1755_o; + wire n1757_o; + wire n1758_o; + wire n1760_o; + wire n1761_o; + wire n1763_o; + wire n1764_o; + wire n1766_o; + wire n1767_o; + wire n1769_o; + wire n1770_o; + wire n1772_o; + wire n1773_o; + wire n1775_o; + wire n1776_o; + wire n1778_o; + wire [48:0] n1779_o; + reg [5:0] n1830_o; + reg n1854_o; + wire [6:0] n1858_o; + wire [6:0] n1859_o; + wire [6:0] n1860_o; + wire n1863_o; + wire [5:0] n1865_o; + wire [7:0] n1867_o; + wire [5:0] n1868_o; + wire [7:0] n1869_o; + wire [5:0] n1870_o; + wire n1880_o; + wire [5:0] n1882_o; + wire [5:0] n1883_o; + wire int_b_n1884; + wire int_b_n1886; + wire int_b_n1887; + wire int_b_n1888; + wire int_b_tf_o; + wire int_b_ext_int_o; + wire int_b_tim_int_o; + wire int_b_int_pending_o; + wire int_b_int_in_progress_o; + wire n1898_o; + wire n1899_o; + wire n1900_o; + wire n1903_o; + wire n1904_o; + wire n1905_o; + wire n1906_o; + wire n1907_o; + wire n1910_o; + wire n1911_o; + wire n1914_o; + wire n1916_o; + wire n1919_o; + wire n1921_o; + wire n1923_o; + wire n1925_o; + wire n1927_o; + wire n1928_o; + wire n1929_o; + wire n1932_o; + wire n1935_o; + wire n1937_o; + wire n1939_o; + wire n1941_o; + wire n1942_o; + wire n1943_o; + wire n1944_o; + wire n1945_o; + wire n1948_o; + wire n1950_o; + wire n1953_o; + wire n1955_o; + wire n1956_o; + wire n1957_o; + wire n1958_o; + wire n1959_o; + wire n1962_o; + wire n1965_o; + wire n1968_o; + wire n1970_o; + wire n1971_o; + wire n1972_o; + wire n1973_o; + wire n1974_o; + wire n1975_o; + wire n1976_o; + wire n1979_o; + wire n1981_o; + wire [4:0] n1982_o; + reg n1984_o; + reg n1987_o; + reg n1990_o; + reg n1993_o; + reg n1996_o; + reg n1999_o; + reg n2002_o; + reg n2005_o; + reg n2008_o; + wire n2015_o; + wire n2016_o; + wire n2018_o; + wire n2019_o; + wire n2020_o; + wire [2:0] n2021_o; + wire n2022_o; + wire [2:0] n2024_o; + wire [2:0] n2025_o; + localparam [7:0] n2026_o = 8'b00000000; + wire [4:0] n2027_o; + wire n2030_o; + wire [7:0] n2032_o; + localparam [7:0] n2033_o = 8'bX; + wire [7:0] n2034_o; + wire n2038_o; + wire n2040_o; + wire n2041_o; + wire n2043_o; + wire n2050_o; + wire n2053_o; + wire [1:0] n2056_o; + wire n2058_o; + wire n2063_o; + wire n2067_o; + wire n2070_o; + wire n2072_o; + wire [2:0] n2073_o; + reg n2076_o; + reg n2079_o; + reg n2082_o; + reg n2083_o; + reg n2086_o; + reg [3:0] n2089_o; + reg n2091_o; + reg [1:0] n2093_o; + reg n2095_o; + reg n2098_o; + reg n2101_o; + wire n2103_o; + wire n2105_o; + wire n2109_o; + wire n2112_o; + wire n2114_o; + wire [1:0] n2115_o; + reg n2118_o; + reg n2121_o; + reg n2124_o; + reg [3:0] n2127_o; + reg n2129_o; + reg n2131_o; + reg n2134_o; + reg n2137_o; + wire n2139_o; + wire n2141_o; + wire n2143_o; + wire [3:0] n2145_o; + wire n2147_o; + wire n2149_o; + wire n2151_o; + wire n2153_o; + wire n2155_o; + wire n2156_o; + wire n2157_o; + wire n2159_o; + wire n2166_o; + wire n2169_o; + wire [1:0] n2172_o; + wire n2174_o; + wire n2179_o; + wire n2184_o; + wire [2:0] n2185_o; + reg n2188_o; + reg n2191_o; + reg n2194_o; + reg n2195_o; + reg n2198_o; + reg [3:0] n2201_o; + reg [1:0] n2203_o; + wire n2205_o; + wire n2207_o; + wire n2212_o; + wire [1:0] n2213_o; + reg n2216_o; + reg n2219_o; + reg n2222_o; + reg [3:0] n2225_o; + wire n2227_o; + wire n2229_o; + wire n2231_o; + wire [3:0] n2233_o; + wire n2235_o; + wire n2236_o; + wire n2238_o; + wire [1:0] n2239_o; + wire n2241_o; + wire n2242_o; + wire n2243_o; + wire n2246_o; + wire n2249_o; + wire n2252_o; + wire n2255_o; + wire n2257_o; + wire n2259_o; + wire n2261_o; + wire n2263_o; + wire n2266_o; + wire n2269_o; + wire n2271_o; + wire n2273_o; + wire n2275_o; + wire n2277_o; + wire n2279_o; + wire n2281_o; + wire n2283_o; + wire [1:0] n2284_o; + wire n2286_o; + wire n2287_o; + wire n2288_o; + wire n2291_o; + wire n2294_o; + wire n2297_o; + wire n2299_o; + wire n2301_o; + wire n2303_o; + wire [2:0] n2304_o; + reg n2308_o; + reg n2312_o; + reg n2314_o; + reg n2316_o; + reg n2318_o; + reg [3:0] n2321_o; + wire n2323_o; + wire n2325_o; + wire n2327_o; + wire n2329_o; + wire n2331_o; + wire n2333_o; + wire n2335_o; + wire n2337_o; + wire [3:0] n2339_o; + wire n2341_o; + wire n2343_o; + wire n2345_o; + wire n2347_o; + wire n2348_o; + wire n2349_o; + wire n2352_o; + wire n2354_o; + wire n2356_o; + wire n2358_o; + wire [2:0] n2359_o; + reg n2362_o; + reg n2365_o; + reg n2368_o; + reg n2371_o; + reg n2374_o; + reg [1:0] n2378_o; + reg n2381_o; + reg n2383_o; + reg n2387_o; + localparam [7:0] n2389_o = 8'b00000000; + wire n2394_o; + wire n2395_o; + wire n2396_o; + wire [4:0] n2397_o; + wire n2399_o; + wire [7:0] n2400_o; + wire [7:0] n2401_o; + wire n2403_o; + wire n2405_o; + wire n2406_o; + wire [4:0] n2408_o; + wire [2:0] n2409_o; + wire [7:0] n2410_o; + wire [7:0] n2412_o; + wire n2415_o; + wire n2417_o; + wire [1:0] n2418_o; + reg n2420_o; + reg n2423_o; + reg n2426_o; + reg n2429_o; + reg [7:0] n2430_o; + reg n2432_o; + reg n2434_o; + wire n2436_o; + wire n2437_o; + wire n2439_o; + wire n2441_o; + wire n2443_o; + wire n2445_o; + wire n2447_o; + wire n2449_o; + wire [1:0] n2451_o; + wire n2453_o; + wire n2455_o; + wire n2457_o; + wire [7:0] n2458_o; + wire n2459_o; + wire n2461_o; + wire n2463_o; + wire n2465_o; + wire n2467_o; + wire n2470_o; + wire n2473_o; + wire [3:0] n2476_o; + wire n2478_o; + wire n2480_o; + wire n2483_o; + wire n2485_o; + wire n2487_o; + wire n2488_o; + wire n2489_o; + wire n2492_o; + wire n2495_o; + wire n2497_o; + wire n2499_o; + wire n2501_o; + wire n2503_o; + wire n2506_o; + wire n2509_o; + wire [3:0] n2512_o; + wire n2514_o; + wire n2516_o; + wire n2517_o; + wire n2519_o; + wire n2522_o; + wire n2524_o; + wire n2526_o; + wire n2527_o; + wire n2528_o; + wire n2529_o; + wire n2531_o; + wire n2534_o; + wire n2537_o; + wire n2539_o; + wire n2541_o; + wire n2543_o; + wire n2545_o; + wire n2547_o; + wire n2548_o; + wire n2551_o; + wire n2554_o; + wire n2556_o; + wire [3:0] n2559_o; + wire n2561_o; + wire n2563_o; + wire [2:0] n2564_o; + reg n2567_o; + reg n2569_o; + reg n2572_o; + reg [3:0] n2574_o; + reg n2578_o; + reg n2581_o; + reg n2584_o; + reg n2586_o; + reg n2589_o; + wire n2591_o; + wire n2592_o; + wire n2595_o; + wire n2598_o; + wire n2600_o; + wire n2601_o; + wire n2602_o; + wire n2605_o; + wire n2608_o; + wire n2610_o; + wire [1:0] n2611_o; + reg n2613_o; + reg n2615_o; + reg n2618_o; + reg n2620_o; + reg [3:0] n2623_o; + reg n2625_o; + wire n2627_o; + wire n2629_o; + wire n2630_o; + wire n2633_o; + wire n2636_o; + wire n2638_o; + wire n2640_o; + wire n2642_o; + wire n2644_o; + wire n2645_o; + wire n2648_o; + wire n2651_o; + wire n2653_o; + wire n2655_o; + wire n2657_o; + wire n2658_o; + wire n2660_o; + wire n2663_o; + wire [1:0] n2664_o; + reg n2667_o; + reg n2670_o; + reg n2673_o; + reg [3:0] n2676_o; + reg n2679_o; + reg [3:0] n2682_o; + wire n2683_o; + reg n2684_o; + reg n2687_o; + wire n2689_o; + wire n2690_o; + wire n2696_o; + wire n2699_o; + wire n2701_o; + wire n2703_o; + wire n2705_o; + wire n2707_o; + wire [3:0] n2709_o; + wire n2711_o; + wire [3:0] n2713_o; + wire n2714_o; + wire n2715_o; + wire n2717_o; + wire n2719_o; + wire n2721_o; + wire n2723_o; + wire n2724_o; + wire n2725_o; + wire n2728_o; + wire n2731_o; + wire n2733_o; + wire n2735_o; + wire n2737_o; + wire n2739_o; + wire n2742_o; + wire n2744_o; + wire n2746_o; + wire n2747_o; + wire n2748_o; + wire n2749_o; + wire n2752_o; + wire n2755_o; + wire n2758_o; + wire n2760_o; + wire n2762_o; + wire n2764_o; + wire n2766_o; + wire n2769_o; + wire n2772_o; + wire n2774_o; + wire n2776_o; + wire n2777_o; + wire n2780_o; + wire n2783_o; + wire n2785_o; + wire n2786_o; + wire n2787_o; + wire n2789_o; + wire n2796_o; + wire n2799_o; + wire [1:0] n2802_o; + wire n2804_o; + wire [1:0] n2805_o; + wire n2807_o; + wire n2810_o; + wire n2813_o; + wire n2815_o; + wire [1:0] n2816_o; + wire n2818_o; + wire n2821_o; + wire n2824_o; + wire n2826_o; + wire [2:0] n2827_o; + reg n2829_o; + reg n2831_o; + reg n2834_o; + reg n2835_o; + reg n2837_o; + reg [3:0] n2840_o; + reg [1:0] n2842_o; + reg n2844_o; + wire n2846_o; + wire n2847_o; + wire n2849_o; + wire n2852_o; + wire n2855_o; + wire n2857_o; + wire n2858_o; + wire n2864_o; + wire n2867_o; + wire n2869_o; + wire n2871_o; + wire n2873_o; + wire n2875_o; + wire n2877_o; + wire n2878_o; + wire n2880_o; + wire n2881_o; + wire n2884_o; + wire n2885_o; + wire n2886_o; + wire n2888_o; + wire n2889_o; + wire n2895_o; + wire n2898_o; + wire n2900_o; + wire n2902_o; + wire n2904_o; + wire n2906_o; + wire n2908_o; + wire n2909_o; + wire n2911_o; + wire n2912_o; + wire [3:0] n2915_o; + wire n2918_o; + wire [3:0] n2920_o; + wire n2922_o; + wire n2923_o; + wire n2929_o; + wire n2932_o; + wire n2934_o; + wire n2936_o; + wire [3:0] n2938_o; + wire n2940_o; + wire n2942_o; + wire n2944_o; + wire [4:0] n2946_o; + wire [2:0] n2947_o; + wire [7:0] n2948_o; + wire n2950_o; + wire [1:0] n2951_o; + reg n2954_o; + reg n2957_o; + reg n2960_o; + reg [7:0] n2961_o; + reg n2963_o; + wire n2965_o; + wire n2967_o; + wire n2969_o; + wire [7:0] n2970_o; + wire n2971_o; + wire n2973_o; + wire n2974_o; + wire n2976_o; + wire n2979_o; + wire [1:0] n2982_o; + wire n2984_o; + wire n2987_o; + wire n2990_o; + wire n2992_o; + wire n2994_o; + wire [1:0] n2996_o; + wire n2998_o; + wire n3000_o; + wire n3001_o; + wire n3003_o; + wire n3006_o; + wire n3008_o; + wire n3009_o; + wire n3015_o; + wire n3018_o; + wire n3020_o; + wire n3022_o; + wire n3024_o; + wire n3026_o; + wire n3027_o; + wire n3029_o; + wire n3032_o; + wire n3034_o; + wire n3035_o; + wire n3041_o; + wire n3044_o; + wire n3046_o; + wire n3048_o; + wire n3050_o; + wire n3052_o; + wire n3053_o; + wire n3055_o; + wire n3058_o; + wire n3060_o; + wire n3061_o; + wire n3067_o; + wire n3070_o; + wire n3072_o; + wire n3074_o; + wire n3076_o; + wire n3078_o; + wire n3079_o; + wire n3080_o; + wire [3:0] n3083_o; + wire n3084_o; + wire n3086_o; + wire n3087_o; + wire n3090_o; + wire n3091_o; + wire n3092_o; + wire n3094_o; + wire n3095_o; + wire n3101_o; + wire n3104_o; + wire n3106_o; + wire n3108_o; + wire n3110_o; + wire n3112_o; + wire n3114_o; + wire n3115_o; + wire n3117_o; + wire n3120_o; + wire n3123_o; + wire n3125_o; + wire n3126_o; + wire n3132_o; + wire n3135_o; + wire n3137_o; + wire n3139_o; + wire n3141_o; + wire n3143_o; + wire n3145_o; + wire n3146_o; + wire n3148_o; + wire n3149_o; + wire n3152_o; + wire n3155_o; + wire n3156_o; + wire n3157_o; + wire n3159_o; + wire n3160_o; + wire n3166_o; + wire n3169_o; + wire n3171_o; + wire n3173_o; + wire n3175_o; + wire n3177_o; + wire n3179_o; + wire n3181_o; + wire n3183_o; + wire n3184_o; + wire n3187_o; + wire n3189_o; + wire n3190_o; + wire n3191_o; + wire n3193_o; + wire n3200_o; + wire n3203_o; + wire [1:0] n3206_o; + wire n3208_o; + wire n3213_o; + wire [1:0] n3214_o; + reg n3217_o; + reg n3220_o; + reg n3221_o; + reg n3224_o; + reg [1:0] n3226_o; + wire n3228_o; + wire n3230_o; + wire n3233_o; + wire n3236_o; + wire n3239_o; + wire n3241_o; + wire n3243_o; + wire n3246_o; + wire n3249_o; + wire n3252_o; + wire n3254_o; + wire n3255_o; + wire n3256_o; + wire n3258_o; + wire n3265_o; + wire n3268_o; + wire [1:0] n3271_o; + wire n3273_o; + wire n3275_o; + wire [1:0] n3276_o; + reg n3279_o; + reg n3280_o; + reg n3282_o; + reg [1:0] n3284_o; + reg n3287_o; + wire n3289_o; + wire n3290_o; + wire n3292_o; + wire n3293_o; + wire n3294_o; + wire n3295_o; + wire n3297_o; + wire n3304_o; + wire n3307_o; + wire [1:0] n3310_o; + wire n3311_o; + wire n3313_o; + wire [1:0] n3315_o; + wire n3317_o; + wire n3318_o; + wire n3321_o; + wire n3323_o; + wire n3325_o; + wire n3328_o; + wire n3331_o; + wire n3333_o; + wire n3335_o; + wire n3336_o; + wire n3339_o; + wire n3342_o; + wire n3345_o; + wire n3348_o; + wire n3350_o; + wire n3352_o; + wire n3354_o; + wire n3356_o; + wire n3358_o; + wire n3359_o; + wire [1:0] n3361_o; + wire [3:0] n3362_o; + wire n3365_o; + wire n3368_o; + wire n3371_o; + wire [2:0] n3372_o; + wire [1:0] n3373_o; + wire [1:0] n3374_o; + wire [1:0] n3375_o; + reg [1:0] n3376_o; + wire n3378_o; + wire n3380_o; + wire n3382_o; + wire [2:0] n3383_o; + reg n3386_o; + reg n3390_o; + wire [1:0] n3391_o; + wire [1:0] n3392_o; + wire [1:0] n3393_o; + reg [1:0] n3394_o; + wire [1:0] n3395_o; + wire [1:0] n3396_o; + wire [1:0] n3397_o; + reg [1:0] n3398_o; + wire [3:0] n3399_o; + wire [3:0] n3400_o; + wire [3:0] n3401_o; + reg [3:0] n3402_o; + reg n3404_o; + reg n3408_o; + wire n3410_o; + wire n3412_o; + wire n3413_o; + wire n3416_o; + wire n3418_o; + wire n3420_o; + wire [7:0] n3421_o; + wire [7:0] n3422_o; + wire n3423_o; + wire n3424_o; + wire n3426_o; + wire n3427_o; + wire [1:0] n3428_o; + wire [7:0] n3430_o; + wire n3432_o; + wire n3435_o; + wire n3437_o; + wire [2:0] n3438_o; + reg n3442_o; + wire [3:0] n3443_o; + wire [3:0] n3444_o; + wire [3:0] n3445_o; + wire [3:0] n3446_o; + reg [3:0] n3447_o; + wire [3:0] n3448_o; + wire [3:0] n3449_o; + wire [3:0] n3450_o; + wire [3:0] n3451_o; + reg [3:0] n3452_o; + reg n3455_o; + reg n3459_o; + wire n3461_o; + wire n3463_o; + wire [1:0] n3464_o; + reg n3467_o; + reg n3470_o; + reg n3473_o; + reg n3477_o; + wire n3479_o; + wire n3481_o; + wire n3483_o; + wire n3485_o; + wire [7:0] n3486_o; + wire [7:0] n3487_o; + wire n3488_o; + wire n3489_o; + wire n3491_o; + wire n3492_o; + wire n3494_o; + wire n3495_o; + wire n3496_o; + wire [1:0] n3499_o; + wire n3502_o; + wire [1:0] n3504_o; + wire n3506_o; + wire n3509_o; + wire n3512_o; + wire n3514_o; + wire n3516_o; + wire [1:0] n3518_o; + wire n3520_o; + wire n3522_o; + wire n3523_o; + wire n3524_o; + wire n3527_o; + wire n3530_o; + wire n3531_o; + wire n3533_o; + wire n3534_o; + wire n3537_o; + wire n3540_o; + wire n3542_o; + wire [1:0] n3543_o; + reg n3545_o; + reg n3548_o; + reg n3551_o; + wire n3553_o; + wire n3554_o; + wire n3555_o; + wire n3558_o; + wire n3561_o; + wire n3564_o; + wire n3567_o; + wire n3569_o; + wire n3571_o; + wire n3573_o; + wire n3575_o; + wire n3577_o; + wire n3578_o; + wire n3579_o; + wire n3581_o; + wire n3583_o; + wire n3586_o; + wire n3588_o; + wire n3590_o; + wire n3591_o; + wire n3592_o; + wire n3594_o; + wire n3601_o; + wire n3604_o; + wire [1:0] n3607_o; + wire n3609_o; + wire n3614_o; + wire n3619_o; + wire [2:0] n3620_o; + reg n3623_o; + reg n3626_o; + reg n3629_o; + reg n3630_o; + reg n3633_o; + reg [3:0] n3636_o; + reg [1:0] n3638_o; + wire n3640_o; + wire n3642_o; + wire n3647_o; + wire [1:0] n3648_o; + reg n3651_o; + reg n3654_o; + reg n3657_o; + reg [3:0] n3660_o; + wire n3662_o; + wire n3664_o; + wire n3666_o; + wire [3:0] n3668_o; + wire n3670_o; + wire n3671_o; + wire n3673_o; + wire [1:0] n3674_o; + wire n3676_o; + wire n3677_o; + wire n3678_o; + wire n3681_o; + wire n3684_o; + wire n3687_o; + wire n3690_o; + wire n3692_o; + wire n3694_o; + wire n3696_o; + wire n3698_o; + wire n3701_o; + wire n3704_o; + wire n3706_o; + wire n3708_o; + wire n3710_o; + wire n3712_o; + wire n3714_o; + wire n3716_o; + wire n3718_o; + wire [1:0] n3719_o; + wire n3721_o; + wire n3722_o; + wire n3723_o; + wire n3726_o; + wire n3729_o; + wire n3732_o; + wire n3734_o; + wire n3736_o; + wire n3738_o; + wire [2:0] n3739_o; + reg n3743_o; + reg n3747_o; + reg n3749_o; + reg n3751_o; + reg n3753_o; + reg [3:0] n3756_o; + wire n3758_o; + wire n3760_o; + wire n3762_o; + wire n3764_o; + wire n3766_o; + wire n3768_o; + wire n3770_o; + wire n3772_o; + wire [3:0] n3774_o; + wire n3776_o; + wire n3778_o; + wire n3780_o; + wire n3782_o; + wire n3784_o; + wire n3787_o; + wire n3790_o; + wire n3792_o; + wire n3793_o; + wire n3794_o; + wire n3797_o; + wire n3798_o; + wire n3800_o; + wire n3801_o; + wire n3802_o; + wire n3803_o; + wire n3804_o; + wire n3807_o; + wire n3810_o; + wire n3813_o; + wire n3815_o; + wire n3817_o; + wire n3820_o; + wire n3822_o; + wire n3824_o; + wire n3826_o; + wire n3828_o; + wire n3829_o; + wire n3831_o; + wire n3833_o; + wire n3835_o; + wire [2:0] n3836_o; + reg n3839_o; + reg n3842_o; + reg n3845_o; + reg n3848_o; + reg [1:0] n3852_o; + reg n3855_o; + wire n3856_o; + wire n3859_o; + wire n3862_o; + wire n3864_o; + wire n3866_o; + wire [1:0] n3867_o; + reg n3870_o; + reg n3873_o; + reg n3875_o; + reg n3878_o; + reg n3880_o; + wire n3881_o; + wire n3882_o; + wire n3884_o; + wire n3886_o; + wire n3888_o; + wire n3890_o; + wire [1:0] n3892_o; + wire n3894_o; + wire n3896_o; + wire n3898_o; + wire n3900_o; + wire n3902_o; + wire n3903_o; + wire n3906_o; + wire n3908_o; + wire n3911_o; + wire n3914_o; + wire n3917_o; + wire [3:0] n3920_o; + wire n3922_o; + wire n3924_o; + wire n3926_o; + wire n3928_o; + wire n3930_o; + wire n3931_o; + wire n3932_o; + wire n3935_o; + wire n3937_o; + wire n3940_o; + wire n3943_o; + wire n3946_o; + wire [3:0] n3949_o; + wire n3951_o; + wire n3953_o; + wire n3955_o; + wire n3957_o; + wire n3959_o; + wire n3960_o; + wire n3963_o; + wire n3966_o; + wire n3968_o; + wire n3970_o; + wire n3972_o; + wire n3974_o; + wire n3975_o; + wire n3977_o; + wire n3980_o; + wire n3982_o; + wire n3984_o; + wire n3987_o; + wire n3989_o; + wire n3991_o; + wire n3992_o; + wire n3995_o; + wire n3998_o; + wire n4000_o; + wire n4002_o; + wire n4004_o; + wire n4006_o; + wire n4009_o; + wire n4012_o; + wire n4014_o; + wire n4015_o; + wire n4016_o; + wire n4018_o; + wire n4025_o; + wire n4028_o; + wire [1:0] n4031_o; + wire n4033_o; + wire n4034_o; + wire n4037_o; + wire n4039_o; + wire n4040_o; + wire [3:0] n4043_o; + wire n4045_o; + wire [2:0] n4046_o; + reg n4049_o; + reg n4052_o; + reg n4055_o; + reg n4056_o; + reg n4059_o; + reg [3:0] n4061_o; + reg n4063_o; + reg [1:0] n4065_o; + reg n4068_o; + wire n4070_o; + wire n4071_o; + wire n4072_o; + wire n4074_o; + wire n4081_o; + wire n4084_o; + wire [1:0] n4087_o; + wire n4089_o; + wire n4094_o; + wire n4099_o; + wire [2:0] n4100_o; + reg n4103_o; + reg n4106_o; + reg n4109_o; + reg n4110_o; + reg n4113_o; + reg [3:0] n4116_o; + reg [1:0] n4118_o; + wire n4120_o; + wire n4122_o; + wire n4127_o; + wire [1:0] n4128_o; + reg n4131_o; + reg n4134_o; + reg n4137_o; + reg [3:0] n4140_o; + wire n4142_o; + wire n4144_o; + wire n4146_o; + wire [3:0] n4148_o; + wire n4150_o; + wire [62:0] n4151_o; + reg n4153_o; + reg n4156_o; + reg n4159_o; + reg n4162_o; + reg n4165_o; + reg n4168_o; + reg n4171_o; + reg n4174_o; + reg n4177_o; + reg n4179_o; + reg n4181_o; + reg n4184_o; + reg n4187_o; + reg n4190_o; + reg n4193_o; + reg n4196_o; + reg n4199_o; + reg n4202_o; + reg n4205_o; + reg n4208_o; + reg n4211_o; + reg n4214_o; + reg n4217_o; + reg n4220_o; + reg n4223_o; + reg [3:0] n4227_o; + reg n4230_o; + reg n4233_o; + reg n4236_o; + reg n4239_o; + reg n4242_o; + reg n4246_o; + reg n4251_o; + reg n4255_o; + reg n4258_o; + reg n4261_o; + reg [3:0] n4271_o; + wire n4273_o; + reg n4274_o; + wire [1:0] n4275_o; + reg [1:0] n4277_o; + reg n4280_o; + reg n4283_o; + reg [1:0] n4286_o; + reg n4289_o; + reg n4292_o; + reg n4295_o; + reg n4298_o; + reg n4301_o; + reg n4304_o; + reg n4307_o; + reg n4310_o; + reg n4313_o; + reg n4316_o; + reg n4319_o; + reg n4322_o; + reg n4347_o; + reg n4350_o; + reg n4353_o; + reg n4356_o; + reg n4359_o; + reg n4362_o; + reg n4365_o; + reg n4368_o; + reg n4371_o; + reg [7:0] n4373_o; + reg n4374_o; + reg n4376_o; + reg n4379_o; + reg n4382_o; + reg n4385_o; + reg n4388_o; + reg n4391_o; + reg n4394_o; + reg n4397_o; + reg n4400_o; + reg n4403_o; + reg n4406_o; + wire n4410_o; + wire n4413_o; + wire n4415_o; + wire n4417_o; + wire n4419_o; + wire n4421_o; + wire n4422_o; + wire n4423_o; + wire n4425_o; + wire n4427_o; + wire n4429_o; + wire n4433_o; + wire n4435_o; + wire [7:0] n4449_o; + wire n4451_o; + wire n4452_o; + wire n4453_o; + wire n4454_o; + wire [7:0] n4455_o; + reg [7:0] n4456_q; + wire n4457_o; + reg n4458_q; + reg n4459_q; + wire n4460_o; + reg n4461_q; + wire n4462_o; + reg n4463_q; + wire [5:0] n4464_o; + reg [5:0] n4465_q; + wire [2:0] n4466_o; + assign t0_dir_o = t0_dir_q; + assign data_o = n4449_o; + assign alu_write_accu_o = n4153_o; + assign alu_write_shadow_o = n4156_o; + assign alu_write_temp_reg_o = n4159_o; + assign alu_read_alu_o = n4162_o; + assign bus_write_bus_o = n4165_o; + assign bus_read_bus_o = n4454_o; + assign bus_ibf_int_o = n4168_o; + assign bus_en_dma_o = n4171_o; + assign bus_en_flags_o = n4174_o; + assign bus_write_sts_o = n4177_o; + assign dm_write_dmem_addr_o = n4179_o; + assign dm_write_dmem_o = n4451_o; + assign dm_read_dmem_o = n4181_o; + assign p1_write_p1_o = n4184_o; + assign p1_read_p1_o = n4187_o; + assign p2_write_p2_o = n4190_o; + assign p2_write_exp_o = n4193_o; + assign p2_read_p2_o = n4196_o; + assign p2_read_exp_o = n4199_o; + assign pm_write_pcl_o = n4202_o; + assign pm_read_pcl_o = n4205_o; + assign pm_write_pch_o = n4208_o; + assign pm_read_pch_o = n4211_o; + assign pm_read_pmem_o = n1984_o; + assign psw_read_psw_o = n4214_o; + assign psw_read_sp_o = n4217_o; + assign psw_write_psw_o = n4220_o; + assign psw_write_sp_o = n4223_o; + assign alu_op_o = n4227_o; + assign alu_use_carry_o = n4230_o; + assign alu_da_high_o = n4233_o; + assign alu_accu_low_o = n4236_o; + assign alu_p06_temp_reg_o = n4239_o; + assign alu_p60_temp_reg_o = n4242_o; + assign bus_output_pcl_o = n1987_o; + assign bus_bidir_bus_o = n4246_o; + assign clk_multi_cycle_o = opc_multi_cycle_s; + assign clk_assert_psen_o = n1990_o; + assign clk_assert_prog_o = n4251_o; + assign clk_assert_rd_o = n4255_o; + assign clk_assert_wr_o = n4258_o; + assign cnd_compute_take_o = n4261_o; + assign cnd_branch_cond_o = n4271_o; + assign cnd_comp_value_o = n4466_o; + assign cnd_f1_o = f1_q; + assign cnd_tf_o = tf_s; + assign dm_addr_type_o = n4277_o; + assign p1_read_reg_o = n4280_o; + assign p2_read_reg_o = n4283_o; + assign p2_output_pch_o = n1993_o; + assign pm_inc_pc_o = n4452_o; + assign pm_write_pmem_addr_o = n4453_o; + assign pm_addr_type_o = n4286_o; + assign psw_special_data_o = n4289_o; + assign psw_inc_stackp_o = n4292_o; + assign psw_dec_stackp_o = n4295_o; + assign psw_write_carry_o = n4298_o; + assign psw_write_aux_carry_o = n4301_o; + assign psw_write_f0_o = n4304_o; + assign psw_write_bs_o = n4307_o; + assign tim_read_timer_o = n4310_o; + assign tim_write_timer_o = n4313_o; + assign tim_start_t_o = n4316_o; + assign tim_start_cnt_o = n4319_o; + assign tim_stop_tcnt_o = n4322_o; + /* decoder.vhd:187:10 */ + assign opc_multi_cycle_s = n1880_o; // (signal) + /* decoder.vhd:188:10 */ + assign opc_read_bus_s = n1996_o; // (signal) + /* decoder.vhd:189:10 */ + assign opc_inj_int_s = n1999_o; // (signal) + /* decoder.vhd:190:10 */ + assign opc_opcode_q = n4456_q; // (signal) + /* decoder.vhd:191:10 */ + assign opc_mnemonic_s = n1882_o; // (signal) + /* decoder.vhd:192:10 */ + assign last_cycle_s = n1900_o; // (signal) + /* decoder.vhd:195:10 */ + assign assert_psen_s = n4347_o; // (signal) + /* decoder.vhd:198:10 */ + assign branch_taken_s = n4350_o; // (signal) + /* decoder.vhd:199:10 */ + assign branch_taken_q = n4458_q; // (signal) + /* decoder.vhd:200:10 */ + assign pm_inc_pc_s = n2002_o; // (signal) + /* decoder.vhd:201:10 */ + assign pm_write_pmem_addr_s = n2005_o; // (signal) + /* decoder.vhd:203:10 */ + assign add_inc_pc_s = n4353_o; // (signal) + /* decoder.vhd:205:10 */ + assign add_write_pmem_addr_s = n4356_o; // (signal) + /* decoder.vhd:208:10 */ + assign clear_f1_s = n4359_o; // (signal) + /* decoder.vhd:209:10 */ + assign cpl_f1_s = n4362_o; // (signal) + /* decoder.vhd:210:10 */ + assign f1_q = n4459_q; // (signal) + /* decoder.vhd:212:10 */ + assign clear_mb_s = n4365_o; // (signal) + /* decoder.vhd:213:10 */ + assign set_mb_s = n4368_o; // (signal) + /* decoder.vhd:214:10 */ + assign mb_q = n4461_q; // (signal) + /* decoder.vhd:217:10 */ + assign ent0_clk_s = n4371_o; // (signal) + /* decoder.vhd:218:10 */ + assign t0_dir_q = n4463_q; // (signal) + /* decoder.vhd:220:10 */ + assign data_s = n4373_o; // (signal) + /* decoder.vhd:221:10 */ + assign read_dec_s = n4374_o; // (signal) + /* decoder.vhd:223:10 */ + assign tf_s = int_b_n1884; // (signal) + /* decoder.vhd:225:10 */ + assign bus_read_bus_s = n2008_o; // (signal) + /* decoder.vhd:226:10 */ + assign add_read_bus_s = n4376_o; // (signal) + /* decoder.vhd:228:10 */ + assign dm_write_dmem_s = n4379_o; // (signal) + /* decoder.vhd:230:10 */ + assign p2_output_exp_s = n4382_o; // (signal) + /* decoder.vhd:232:10 */ + assign movx_first_cycle_s = n4385_o; // (signal) + /* decoder.vhd:235:10 */ + assign jtf_executed_s = n4388_o; // (signal) + /* decoder.vhd:236:10 */ + assign en_tcnti_s = n4391_o; // (signal) + /* decoder.vhd:237:10 */ + assign dis_tcnti_s = n4394_o; // (signal) + /* decoder.vhd:238:10 */ + assign en_i_s = n4397_o; // (signal) + /* decoder.vhd:239:10 */ + assign dis_i_s = n4400_o; // (signal) + /* decoder.vhd:240:10 */ + assign tim_int_s = int_b_n1886; // (signal) + /* decoder.vhd:241:10 */ + assign retr_executed_s = n4403_o; // (signal) + /* decoder.vhd:242:10 */ + assign int_executed_s = n4406_o; // (signal) + /* decoder.vhd:243:10 */ + assign int_pending_s = int_b_n1887; // (signal) + /* decoder.vhd:244:10 */ + assign int_in_progress_s = int_b_n1888; // (signal) + /* decoder.vhd:247:10 */ + assign mnemonic_rec_s = n1860_o; // (signal) + /* decoder.vhd:248:10 */ + assign mnemonic_q = n4465_q; // (signal) + /* decoder_pack-p.vhd:419:7 */ + assign n1116_o = opc_opcode_q == 8'b10011000; + /* decoder_pack-p.vhd:419:23 */ + assign n1118_o = opc_opcode_q == 8'b10011001; + /* decoder_pack-p.vhd:419:23 */ + assign n1119_o = n1116_o | n1118_o; + /* decoder_pack-p.vhd:420:23 */ + assign n1121_o = opc_opcode_q == 8'b10011010; + /* decoder_pack-p.vhd:420:23 */ + assign n1122_o = n1119_o | n1121_o; + /* decoder_pack-p.vhd:425:7 */ + assign n1124_o = opc_opcode_q == 8'b01110101; + /* decoder_pack-p.vhd:429:7 */ + assign n1126_o = opc_opcode_q == 8'b00001000; + /* decoder_pack-p.vhd:434:7 */ + assign n1128_o = opc_opcode_q == 8'b10000110; + /* decoder_pack-p.vhd:439:7 */ + assign n1130_o = opc_opcode_q == 8'b10000000; + /* decoder_pack-p.vhd:439:23 */ + assign n1132_o = opc_opcode_q == 8'b10000001; + /* decoder_pack-p.vhd:439:23 */ + assign n1133_o = n1130_o | n1132_o; + /* decoder_pack-p.vhd:439:36 */ + assign n1135_o = opc_opcode_q == 8'b10010000; + /* decoder_pack-p.vhd:439:36 */ + assign n1136_o = n1133_o | n1135_o; + /* decoder_pack-p.vhd:440:23 */ + assign n1138_o = opc_opcode_q == 8'b10010001; + /* decoder_pack-p.vhd:440:23 */ + assign n1139_o = n1136_o | n1138_o; + /* decoder_pack-p.vhd:445:7 */ + assign n1141_o = opc_opcode_q == 8'b10001000; + /* decoder_pack-p.vhd:445:23 */ + assign n1143_o = opc_opcode_q == 8'b10001001; + /* decoder_pack-p.vhd:445:23 */ + assign n1144_o = n1141_o | n1143_o; + /* decoder_pack-p.vhd:446:23 */ + assign n1146_o = opc_opcode_q == 8'b10001010; + /* decoder_pack-p.vhd:446:23 */ + assign n1147_o = n1144_o | n1146_o; + /* decoder_pack-p.vhd:451:7 */ + assign n1149_o = opc_opcode_q == 8'b00111001; + /* decoder_pack-p.vhd:451:23 */ + assign n1151_o = opc_opcode_q == 8'b00111010; + /* decoder_pack-p.vhd:451:23 */ + assign n1152_o = n1149_o | n1151_o; + /* decoder_pack-p.vhd:451:36 */ + assign n1154_o = opc_opcode_q == 8'b00000010; + /* decoder_pack-p.vhd:451:36 */ + assign n1155_o = n1152_o | n1154_o; + /* decoder_pack-p.vhd:457:7 */ + assign n1157_o = opc_opcode_q == 8'b11100101; + /* decoder_pack-p.vhd:457:23 */ + assign n1159_o = opc_opcode_q == 8'b11110101; + /* decoder_pack-p.vhd:457:23 */ + assign n1160_o = n1157_o | n1159_o; + assign n1161_o = {n1160_o, n1155_o, n1147_o, n1139_o, n1128_o, n1126_o, n1124_o, n1122_o}; + /* decoder_pack-p.vhd:417:5 */ + always @* + case (n1161_o) + 8'b10000000: n1171_o = 6'b110010; + 8'b01000000: n1171_o = 6'b101110; + 8'b00100000: n1171_o = 6'b101100; + 8'b00010000: n1171_o = 6'b101000; + 8'b00001000: n1171_o = 6'b011011; + 8'b00000100: n1171_o = 6'b010101; + 8'b00000010: n1171_o = 6'b010010; + 8'b00000001: n1171_o = 6'b000101; + default: n1171_o = 6'b000000; + endcase + /* decoder_pack-p.vhd:417:5 */ + always @* + case (n1161_o) + 8'b10000000: n1180_o = 1'b0; + 8'b01000000: n1180_o = 1'b1; + 8'b00100000: n1180_o = 1'b1; + 8'b00010000: n1180_o = 1'b1; + 8'b00001000: n1180_o = 1'b1; + 8'b00000100: n1180_o = 1'b1; + 8'b00000010: n1180_o = 1'b0; + 8'b00000001: n1180_o = 1'b1; + default: n1180_o = 1'b0; + endcase + /* decoder_pack-p.vhd:466:19 */ + assign n1183_o = n1171_o == 6'b000000; + /* decoder_pack-p.vhd:123:7 */ + assign n1193_o = opc_opcode_q == 8'b01101000; + /* decoder_pack-p.vhd:123:23 */ + assign n1195_o = opc_opcode_q == 8'b01101001; + /* decoder_pack-p.vhd:123:23 */ + assign n1196_o = n1193_o | n1195_o; + /* decoder_pack-p.vhd:123:36 */ + assign n1198_o = opc_opcode_q == 8'b01101010; + /* decoder_pack-p.vhd:123:36 */ + assign n1199_o = n1196_o | n1198_o; + /* decoder_pack-p.vhd:123:49 */ + assign n1201_o = opc_opcode_q == 8'b01101011; + /* decoder_pack-p.vhd:123:49 */ + assign n1202_o = n1199_o | n1201_o; + /* decoder_pack-p.vhd:123:62 */ + assign n1204_o = opc_opcode_q == 8'b01101100; + /* decoder_pack-p.vhd:123:62 */ + assign n1205_o = n1202_o | n1204_o; + /* decoder_pack-p.vhd:124:23 */ + assign n1207_o = opc_opcode_q == 8'b01101101; + /* decoder_pack-p.vhd:124:23 */ + assign n1208_o = n1205_o | n1207_o; + /* decoder_pack-p.vhd:124:36 */ + assign n1210_o = opc_opcode_q == 8'b01101110; + /* decoder_pack-p.vhd:124:36 */ + assign n1211_o = n1208_o | n1210_o; + /* decoder_pack-p.vhd:124:49 */ + assign n1213_o = opc_opcode_q == 8'b01101111; + /* decoder_pack-p.vhd:124:49 */ + assign n1214_o = n1211_o | n1213_o; + /* decoder_pack-p.vhd:124:62 */ + assign n1216_o = opc_opcode_q == 8'b01100000; + /* decoder_pack-p.vhd:124:62 */ + assign n1217_o = n1214_o | n1216_o; + /* decoder_pack-p.vhd:125:23 */ + assign n1219_o = opc_opcode_q == 8'b01100001; + /* decoder_pack-p.vhd:125:23 */ + assign n1220_o = n1217_o | n1219_o; + /* decoder_pack-p.vhd:125:36 */ + assign n1222_o = opc_opcode_q == 8'b01111000; + /* decoder_pack-p.vhd:125:36 */ + assign n1223_o = n1220_o | n1222_o; + /* decoder_pack-p.vhd:126:23 */ + assign n1225_o = opc_opcode_q == 8'b01111001; + /* decoder_pack-p.vhd:126:23 */ + assign n1226_o = n1223_o | n1225_o; + /* decoder_pack-p.vhd:126:36 */ + assign n1228_o = opc_opcode_q == 8'b01111010; + /* decoder_pack-p.vhd:126:36 */ + assign n1229_o = n1226_o | n1228_o; + /* decoder_pack-p.vhd:126:49 */ + assign n1231_o = opc_opcode_q == 8'b01111011; + /* decoder_pack-p.vhd:126:49 */ + assign n1232_o = n1229_o | n1231_o; + /* decoder_pack-p.vhd:126:62 */ + assign n1234_o = opc_opcode_q == 8'b01111100; + /* decoder_pack-p.vhd:126:62 */ + assign n1235_o = n1232_o | n1234_o; + /* decoder_pack-p.vhd:127:23 */ + assign n1237_o = opc_opcode_q == 8'b01111101; + /* decoder_pack-p.vhd:127:23 */ + assign n1238_o = n1235_o | n1237_o; + /* decoder_pack-p.vhd:127:36 */ + assign n1240_o = opc_opcode_q == 8'b01111110; + /* decoder_pack-p.vhd:127:36 */ + assign n1241_o = n1238_o | n1240_o; + /* decoder_pack-p.vhd:127:49 */ + assign n1243_o = opc_opcode_q == 8'b01111111; + /* decoder_pack-p.vhd:127:49 */ + assign n1244_o = n1241_o | n1243_o; + /* decoder_pack-p.vhd:127:62 */ + assign n1246_o = opc_opcode_q == 8'b01110000; + /* decoder_pack-p.vhd:127:62 */ + assign n1247_o = n1244_o | n1246_o; + /* decoder_pack-p.vhd:128:23 */ + assign n1249_o = opc_opcode_q == 8'b01110001; + /* decoder_pack-p.vhd:128:23 */ + assign n1250_o = n1247_o | n1249_o; + /* decoder_pack-p.vhd:132:7 */ + assign n1252_o = opc_opcode_q == 8'b00000011; + /* decoder_pack-p.vhd:132:23 */ + assign n1254_o = opc_opcode_q == 8'b00010011; + /* decoder_pack-p.vhd:132:23 */ + assign n1255_o = n1252_o | n1254_o; + /* decoder_pack-p.vhd:138:7 */ + assign n1257_o = opc_opcode_q == 8'b01011000; + /* decoder_pack-p.vhd:138:23 */ + assign n1259_o = opc_opcode_q == 8'b01011001; + /* decoder_pack-p.vhd:138:23 */ + assign n1260_o = n1257_o | n1259_o; + /* decoder_pack-p.vhd:138:36 */ + assign n1262_o = opc_opcode_q == 8'b01011010; + /* decoder_pack-p.vhd:138:36 */ + assign n1263_o = n1260_o | n1262_o; + /* decoder_pack-p.vhd:138:49 */ + assign n1265_o = opc_opcode_q == 8'b01011011; + /* decoder_pack-p.vhd:138:49 */ + assign n1266_o = n1263_o | n1265_o; + /* decoder_pack-p.vhd:138:62 */ + assign n1268_o = opc_opcode_q == 8'b01011100; + /* decoder_pack-p.vhd:138:62 */ + assign n1269_o = n1266_o | n1268_o; + /* decoder_pack-p.vhd:139:23 */ + assign n1271_o = opc_opcode_q == 8'b01011101; + /* decoder_pack-p.vhd:139:23 */ + assign n1272_o = n1269_o | n1271_o; + /* decoder_pack-p.vhd:139:36 */ + assign n1274_o = opc_opcode_q == 8'b01011110; + /* decoder_pack-p.vhd:139:36 */ + assign n1275_o = n1272_o | n1274_o; + /* decoder_pack-p.vhd:139:49 */ + assign n1277_o = opc_opcode_q == 8'b01011111; + /* decoder_pack-p.vhd:139:49 */ + assign n1278_o = n1275_o | n1277_o; + /* decoder_pack-p.vhd:139:62 */ + assign n1280_o = opc_opcode_q == 8'b01010000; + /* decoder_pack-p.vhd:139:62 */ + assign n1281_o = n1278_o | n1280_o; + /* decoder_pack-p.vhd:140:23 */ + assign n1283_o = opc_opcode_q == 8'b01010001; + /* decoder_pack-p.vhd:140:23 */ + assign n1284_o = n1281_o | n1283_o; + /* decoder_pack-p.vhd:144:7 */ + assign n1286_o = opc_opcode_q == 8'b01010011; + /* decoder_pack-p.vhd:149:7 */ + assign n1288_o = opc_opcode_q == 8'b00010100; + /* decoder_pack-p.vhd:149:23 */ + assign n1290_o = opc_opcode_q == 8'b00110100; + /* decoder_pack-p.vhd:149:23 */ + assign n1291_o = n1288_o | n1290_o; + /* decoder_pack-p.vhd:149:36 */ + assign n1293_o = opc_opcode_q == 8'b01010100; + /* decoder_pack-p.vhd:149:36 */ + assign n1294_o = n1291_o | n1293_o; + /* decoder_pack-p.vhd:149:49 */ + assign n1296_o = opc_opcode_q == 8'b01110100; + /* decoder_pack-p.vhd:149:49 */ + assign n1297_o = n1294_o | n1296_o; + /* decoder_pack-p.vhd:149:62 */ + assign n1299_o = opc_opcode_q == 8'b10010100; + /* decoder_pack-p.vhd:149:62 */ + assign n1300_o = n1297_o | n1299_o; + /* decoder_pack-p.vhd:150:23 */ + assign n1302_o = opc_opcode_q == 8'b10110100; + /* decoder_pack-p.vhd:150:23 */ + assign n1303_o = n1300_o | n1302_o; + /* decoder_pack-p.vhd:150:36 */ + assign n1305_o = opc_opcode_q == 8'b11010100; + /* decoder_pack-p.vhd:150:36 */ + assign n1306_o = n1303_o | n1305_o; + /* decoder_pack-p.vhd:150:49 */ + assign n1308_o = opc_opcode_q == 8'b11110100; + /* decoder_pack-p.vhd:150:49 */ + assign n1309_o = n1306_o | n1308_o; + /* decoder_pack-p.vhd:155:7 */ + assign n1311_o = opc_opcode_q == 8'b00100111; + /* decoder_pack-p.vhd:159:7 */ + assign n1313_o = opc_opcode_q == 8'b10010111; + /* decoder_pack-p.vhd:163:7 */ + assign n1315_o = opc_opcode_q == 8'b10000101; + /* decoder_pack-p.vhd:163:23 */ + assign n1317_o = opc_opcode_q == 8'b10100101; + /* decoder_pack-p.vhd:163:23 */ + assign n1318_o = n1315_o | n1317_o; + /* decoder_pack-p.vhd:168:7 */ + assign n1320_o = opc_opcode_q == 8'b00110111; + /* decoder_pack-p.vhd:172:7 */ + assign n1322_o = opc_opcode_q == 8'b10100111; + /* decoder_pack-p.vhd:176:7 */ + assign n1324_o = opc_opcode_q == 8'b10010101; + /* decoder_pack-p.vhd:176:23 */ + assign n1326_o = opc_opcode_q == 8'b10110101; + /* decoder_pack-p.vhd:176:23 */ + assign n1327_o = n1324_o | n1326_o; + /* decoder_pack-p.vhd:181:7 */ + assign n1329_o = opc_opcode_q == 8'b01010111; + /* decoder_pack-p.vhd:185:7 */ + assign n1331_o = opc_opcode_q == 8'b11001000; + /* decoder_pack-p.vhd:185:23 */ + assign n1333_o = opc_opcode_q == 8'b11001001; + /* decoder_pack-p.vhd:185:23 */ + assign n1334_o = n1331_o | n1333_o; + /* decoder_pack-p.vhd:185:36 */ + assign n1336_o = opc_opcode_q == 8'b11001010; + /* decoder_pack-p.vhd:185:36 */ + assign n1337_o = n1334_o | n1336_o; + /* decoder_pack-p.vhd:185:49 */ + assign n1339_o = opc_opcode_q == 8'b11001011; + /* decoder_pack-p.vhd:185:49 */ + assign n1340_o = n1337_o | n1339_o; + /* decoder_pack-p.vhd:185:62 */ + assign n1342_o = opc_opcode_q == 8'b11001100; + /* decoder_pack-p.vhd:185:62 */ + assign n1343_o = n1340_o | n1342_o; + /* decoder_pack-p.vhd:186:23 */ + assign n1345_o = opc_opcode_q == 8'b11001101; + /* decoder_pack-p.vhd:186:23 */ + assign n1346_o = n1343_o | n1345_o; + /* decoder_pack-p.vhd:186:36 */ + assign n1348_o = opc_opcode_q == 8'b11001110; + /* decoder_pack-p.vhd:186:36 */ + assign n1349_o = n1346_o | n1348_o; + /* decoder_pack-p.vhd:186:49 */ + assign n1351_o = opc_opcode_q == 8'b11001111; + /* decoder_pack-p.vhd:186:49 */ + assign n1352_o = n1349_o | n1351_o; + /* decoder_pack-p.vhd:186:62 */ + assign n1354_o = opc_opcode_q == 8'b00000111; + /* decoder_pack-p.vhd:186:62 */ + assign n1355_o = n1352_o | n1354_o; + /* decoder_pack-p.vhd:191:7 */ + assign n1357_o = opc_opcode_q == 8'b00010101; + /* decoder_pack-p.vhd:191:23 */ + assign n1359_o = opc_opcode_q == 8'b00000101; + /* decoder_pack-p.vhd:191:23 */ + assign n1360_o = n1357_o | n1359_o; + /* decoder_pack-p.vhd:196:7 */ + assign n1362_o = opc_opcode_q == 8'b00110101; + /* decoder_pack-p.vhd:196:23 */ + assign n1364_o = opc_opcode_q == 8'b00100101; + /* decoder_pack-p.vhd:196:23 */ + assign n1365_o = n1362_o | n1364_o; + /* decoder_pack-p.vhd:201:7 */ + assign n1367_o = opc_opcode_q == 8'b11101000; + /* decoder_pack-p.vhd:201:23 */ + assign n1369_o = opc_opcode_q == 8'b11101001; + /* decoder_pack-p.vhd:201:23 */ + assign n1370_o = n1367_o | n1369_o; + /* decoder_pack-p.vhd:201:36 */ + assign n1372_o = opc_opcode_q == 8'b11101010; + /* decoder_pack-p.vhd:201:36 */ + assign n1373_o = n1370_o | n1372_o; + /* decoder_pack-p.vhd:201:49 */ + assign n1375_o = opc_opcode_q == 8'b11101011; + /* decoder_pack-p.vhd:201:49 */ + assign n1376_o = n1373_o | n1375_o; + /* decoder_pack-p.vhd:201:62 */ + assign n1378_o = opc_opcode_q == 8'b11101100; + /* decoder_pack-p.vhd:201:62 */ + assign n1379_o = n1376_o | n1378_o; + /* decoder_pack-p.vhd:202:23 */ + assign n1381_o = opc_opcode_q == 8'b11101101; + /* decoder_pack-p.vhd:202:23 */ + assign n1382_o = n1379_o | n1381_o; + /* decoder_pack-p.vhd:202:36 */ + assign n1384_o = opc_opcode_q == 8'b11101110; + /* decoder_pack-p.vhd:202:36 */ + assign n1385_o = n1382_o | n1384_o; + /* decoder_pack-p.vhd:202:49 */ + assign n1387_o = opc_opcode_q == 8'b11101111; + /* decoder_pack-p.vhd:202:49 */ + assign n1388_o = n1385_o | n1387_o; + /* decoder_pack-p.vhd:207:7 */ + assign n1390_o = opc_opcode_q == 8'b00001001; + /* decoder_pack-p.vhd:207:23 */ + assign n1392_o = opc_opcode_q == 8'b00001010; + /* decoder_pack-p.vhd:207:23 */ + assign n1393_o = n1390_o | n1392_o; + /* decoder_pack-p.vhd:212:7 */ + assign n1395_o = opc_opcode_q == 8'b00010111; + /* decoder_pack-p.vhd:212:23 */ + assign n1397_o = opc_opcode_q == 8'b00011000; + /* decoder_pack-p.vhd:212:23 */ + assign n1398_o = n1395_o | n1397_o; + /* decoder_pack-p.vhd:213:23 */ + assign n1400_o = opc_opcode_q == 8'b00011001; + /* decoder_pack-p.vhd:213:23 */ + assign n1401_o = n1398_o | n1400_o; + /* decoder_pack-p.vhd:213:36 */ + assign n1403_o = opc_opcode_q == 8'b00011010; + /* decoder_pack-p.vhd:213:36 */ + assign n1404_o = n1401_o | n1403_o; + /* decoder_pack-p.vhd:213:49 */ + assign n1406_o = opc_opcode_q == 8'b00011011; + /* decoder_pack-p.vhd:213:49 */ + assign n1407_o = n1404_o | n1406_o; + /* decoder_pack-p.vhd:213:62 */ + assign n1409_o = opc_opcode_q == 8'b00011100; + /* decoder_pack-p.vhd:213:62 */ + assign n1410_o = n1407_o | n1409_o; + /* decoder_pack-p.vhd:214:23 */ + assign n1412_o = opc_opcode_q == 8'b00011101; + /* decoder_pack-p.vhd:214:23 */ + assign n1413_o = n1410_o | n1412_o; + /* decoder_pack-p.vhd:214:36 */ + assign n1415_o = opc_opcode_q == 8'b00011110; + /* decoder_pack-p.vhd:214:36 */ + assign n1416_o = n1413_o | n1415_o; + /* decoder_pack-p.vhd:214:49 */ + assign n1418_o = opc_opcode_q == 8'b00011111; + /* decoder_pack-p.vhd:214:49 */ + assign n1419_o = n1416_o | n1418_o; + /* decoder_pack-p.vhd:214:62 */ + assign n1421_o = opc_opcode_q == 8'b00010000; + /* decoder_pack-p.vhd:214:62 */ + assign n1422_o = n1419_o | n1421_o; + /* decoder_pack-p.vhd:215:23 */ + assign n1424_o = opc_opcode_q == 8'b00010001; + /* decoder_pack-p.vhd:215:23 */ + assign n1425_o = n1422_o | n1424_o; + /* decoder_pack-p.vhd:219:7 */ + assign n1427_o = opc_opcode_q == 8'b00010010; + /* decoder_pack-p.vhd:219:23 */ + assign n1429_o = opc_opcode_q == 8'b00110010; + /* decoder_pack-p.vhd:219:23 */ + assign n1430_o = n1427_o | n1429_o; + /* decoder_pack-p.vhd:219:36 */ + assign n1432_o = opc_opcode_q == 8'b01010010; + /* decoder_pack-p.vhd:219:36 */ + assign n1433_o = n1430_o | n1432_o; + /* decoder_pack-p.vhd:219:49 */ + assign n1435_o = opc_opcode_q == 8'b01110010; + /* decoder_pack-p.vhd:219:49 */ + assign n1436_o = n1433_o | n1435_o; + /* decoder_pack-p.vhd:219:62 */ + assign n1438_o = opc_opcode_q == 8'b10010010; + /* decoder_pack-p.vhd:219:62 */ + assign n1439_o = n1436_o | n1438_o; + /* decoder_pack-p.vhd:220:23 */ + assign n1441_o = opc_opcode_q == 8'b10110010; + /* decoder_pack-p.vhd:220:23 */ + assign n1442_o = n1439_o | n1441_o; + /* decoder_pack-p.vhd:220:36 */ + assign n1444_o = opc_opcode_q == 8'b11010010; + /* decoder_pack-p.vhd:220:36 */ + assign n1445_o = n1442_o | n1444_o; + /* decoder_pack-p.vhd:220:49 */ + assign n1447_o = opc_opcode_q == 8'b11110010; + /* decoder_pack-p.vhd:220:49 */ + assign n1448_o = n1445_o | n1447_o; + /* decoder_pack-p.vhd:225:7 */ + assign n1450_o = opc_opcode_q == 8'b11110110; + /* decoder_pack-p.vhd:225:23 */ + assign n1452_o = opc_opcode_q == 8'b11100110; + /* decoder_pack-p.vhd:225:23 */ + assign n1453_o = n1450_o | n1452_o; + /* decoder_pack-p.vhd:231:7 */ + assign n1455_o = opc_opcode_q == 8'b10110110; + /* decoder_pack-p.vhd:231:23 */ + assign n1457_o = opc_opcode_q == 8'b01110110; + /* decoder_pack-p.vhd:231:23 */ + assign n1458_o = n1455_o | n1457_o; + /* decoder_pack-p.vhd:237:7 */ + assign n1460_o = opc_opcode_q == 8'b00000100; + /* decoder_pack-p.vhd:237:23 */ + assign n1462_o = opc_opcode_q == 8'b00100100; + /* decoder_pack-p.vhd:237:23 */ + assign n1463_o = n1460_o | n1462_o; + /* decoder_pack-p.vhd:237:36 */ + assign n1465_o = opc_opcode_q == 8'b01000100; + /* decoder_pack-p.vhd:237:36 */ + assign n1466_o = n1463_o | n1465_o; + /* decoder_pack-p.vhd:237:49 */ + assign n1468_o = opc_opcode_q == 8'b01100100; + /* decoder_pack-p.vhd:237:49 */ + assign n1469_o = n1466_o | n1468_o; + /* decoder_pack-p.vhd:237:62 */ + assign n1471_o = opc_opcode_q == 8'b10000100; + /* decoder_pack-p.vhd:237:62 */ + assign n1472_o = n1469_o | n1471_o; + /* decoder_pack-p.vhd:238:23 */ + assign n1474_o = opc_opcode_q == 8'b10100100; + /* decoder_pack-p.vhd:238:23 */ + assign n1475_o = n1472_o | n1474_o; + /* decoder_pack-p.vhd:238:36 */ + assign n1477_o = opc_opcode_q == 8'b11000100; + /* decoder_pack-p.vhd:238:36 */ + assign n1478_o = n1475_o | n1477_o; + /* decoder_pack-p.vhd:238:49 */ + assign n1480_o = opc_opcode_q == 8'b11100100; + /* decoder_pack-p.vhd:238:49 */ + assign n1481_o = n1478_o | n1480_o; + /* decoder_pack-p.vhd:243:7 */ + assign n1483_o = opc_opcode_q == 8'b10110011; + /* decoder_pack-p.vhd:248:7 */ + assign n1485_o = opc_opcode_q == 8'b00100110; + /* decoder_pack-p.vhd:248:23 */ + assign n1487_o = opc_opcode_q == 8'b01000110; + /* decoder_pack-p.vhd:248:23 */ + assign n1488_o = n1485_o | n1487_o; + /* decoder_pack-p.vhd:249:23 */ + assign n1490_o = opc_opcode_q == 8'b00110110; + /* decoder_pack-p.vhd:249:23 */ + assign n1491_o = n1488_o | n1490_o; + /* decoder_pack-p.vhd:250:23 */ + assign n1493_o = opc_opcode_q == 8'b01010110; + /* decoder_pack-p.vhd:250:23 */ + assign n1494_o = n1491_o | n1493_o; + /* decoder_pack-p.vhd:256:7 */ + assign n1496_o = opc_opcode_q == 8'b00010110; + /* decoder_pack-p.vhd:261:7 */ + assign n1498_o = opc_opcode_q == 8'b10010110; + /* decoder_pack-p.vhd:261:23 */ + assign n1500_o = opc_opcode_q == 8'b11000110; + /* decoder_pack-p.vhd:261:23 */ + assign n1501_o = n1498_o | n1500_o; + /* decoder_pack-p.vhd:267:7 */ + assign n1503_o = opc_opcode_q == 8'b00100011; + /* decoder_pack-p.vhd:272:7 */ + assign n1505_o = opc_opcode_q == 8'b11000111; + /* decoder_pack-p.vhd:276:7 */ + assign n1507_o = opc_opcode_q == 8'b11111000; + /* decoder_pack-p.vhd:276:23 */ + assign n1509_o = opc_opcode_q == 8'b11111001; + /* decoder_pack-p.vhd:276:23 */ + assign n1510_o = n1507_o | n1509_o; + /* decoder_pack-p.vhd:276:36 */ + assign n1512_o = opc_opcode_q == 8'b11111010; + /* decoder_pack-p.vhd:276:36 */ + assign n1513_o = n1510_o | n1512_o; + /* decoder_pack-p.vhd:276:49 */ + assign n1515_o = opc_opcode_q == 8'b11111011; + /* decoder_pack-p.vhd:276:49 */ + assign n1516_o = n1513_o | n1515_o; + /* decoder_pack-p.vhd:276:62 */ + assign n1518_o = opc_opcode_q == 8'b11111100; + /* decoder_pack-p.vhd:276:62 */ + assign n1519_o = n1516_o | n1518_o; + /* decoder_pack-p.vhd:277:23 */ + assign n1521_o = opc_opcode_q == 8'b11111101; + /* decoder_pack-p.vhd:277:23 */ + assign n1522_o = n1519_o | n1521_o; + /* decoder_pack-p.vhd:277:36 */ + assign n1524_o = opc_opcode_q == 8'b11111110; + /* decoder_pack-p.vhd:277:36 */ + assign n1525_o = n1522_o | n1524_o; + /* decoder_pack-p.vhd:277:49 */ + assign n1527_o = opc_opcode_q == 8'b11111111; + /* decoder_pack-p.vhd:277:49 */ + assign n1528_o = n1525_o | n1527_o; + /* decoder_pack-p.vhd:277:62 */ + assign n1530_o = opc_opcode_q == 8'b11110000; + /* decoder_pack-p.vhd:277:62 */ + assign n1531_o = n1528_o | n1530_o; + /* decoder_pack-p.vhd:278:23 */ + assign n1533_o = opc_opcode_q == 8'b11110001; + /* decoder_pack-p.vhd:278:23 */ + assign n1534_o = n1531_o | n1533_o; + /* decoder_pack-p.vhd:282:7 */ + assign n1536_o = opc_opcode_q == 8'b11010111; + /* decoder_pack-p.vhd:286:7 */ + assign n1538_o = opc_opcode_q == 8'b10101000; + /* decoder_pack-p.vhd:286:23 */ + assign n1540_o = opc_opcode_q == 8'b10101001; + /* decoder_pack-p.vhd:286:23 */ + assign n1541_o = n1538_o | n1540_o; + /* decoder_pack-p.vhd:286:36 */ + assign n1543_o = opc_opcode_q == 8'b10101010; + /* decoder_pack-p.vhd:286:36 */ + assign n1544_o = n1541_o | n1543_o; + /* decoder_pack-p.vhd:286:49 */ + assign n1546_o = opc_opcode_q == 8'b10101011; + /* decoder_pack-p.vhd:286:49 */ + assign n1547_o = n1544_o | n1546_o; + /* decoder_pack-p.vhd:286:62 */ + assign n1549_o = opc_opcode_q == 8'b10101100; + /* decoder_pack-p.vhd:286:62 */ + assign n1550_o = n1547_o | n1549_o; + /* decoder_pack-p.vhd:287:23 */ + assign n1552_o = opc_opcode_q == 8'b10101101; + /* decoder_pack-p.vhd:287:23 */ + assign n1553_o = n1550_o | n1552_o; + /* decoder_pack-p.vhd:287:36 */ + assign n1555_o = opc_opcode_q == 8'b10101110; + /* decoder_pack-p.vhd:287:36 */ + assign n1556_o = n1553_o | n1555_o; + /* decoder_pack-p.vhd:287:49 */ + assign n1558_o = opc_opcode_q == 8'b10101111; + /* decoder_pack-p.vhd:287:49 */ + assign n1559_o = n1556_o | n1558_o; + /* decoder_pack-p.vhd:287:62 */ + assign n1561_o = opc_opcode_q == 8'b10100000; + /* decoder_pack-p.vhd:287:62 */ + assign n1562_o = n1559_o | n1561_o; + /* decoder_pack-p.vhd:288:23 */ + assign n1564_o = opc_opcode_q == 8'b10100001; + /* decoder_pack-p.vhd:288:23 */ + assign n1565_o = n1562_o | n1564_o; + /* decoder_pack-p.vhd:292:7 */ + assign n1567_o = opc_opcode_q == 8'b10111000; + /* decoder_pack-p.vhd:292:23 */ + assign n1569_o = opc_opcode_q == 8'b10111001; + /* decoder_pack-p.vhd:292:23 */ + assign n1570_o = n1567_o | n1569_o; + /* decoder_pack-p.vhd:292:36 */ + assign n1572_o = opc_opcode_q == 8'b10111010; + /* decoder_pack-p.vhd:292:36 */ + assign n1573_o = n1570_o | n1572_o; + /* decoder_pack-p.vhd:292:49 */ + assign n1575_o = opc_opcode_q == 8'b10111011; + /* decoder_pack-p.vhd:292:49 */ + assign n1576_o = n1573_o | n1575_o; + /* decoder_pack-p.vhd:292:62 */ + assign n1578_o = opc_opcode_q == 8'b10111100; + /* decoder_pack-p.vhd:292:62 */ + assign n1579_o = n1576_o | n1578_o; + /* decoder_pack-p.vhd:293:23 */ + assign n1581_o = opc_opcode_q == 8'b10111101; + /* decoder_pack-p.vhd:293:23 */ + assign n1582_o = n1579_o | n1581_o; + /* decoder_pack-p.vhd:293:36 */ + assign n1584_o = opc_opcode_q == 8'b10111110; + /* decoder_pack-p.vhd:293:36 */ + assign n1585_o = n1582_o | n1584_o; + /* decoder_pack-p.vhd:293:49 */ + assign n1587_o = opc_opcode_q == 8'b10111111; + /* decoder_pack-p.vhd:293:49 */ + assign n1588_o = n1585_o | n1587_o; + /* decoder_pack-p.vhd:293:62 */ + assign n1590_o = opc_opcode_q == 8'b10110000; + /* decoder_pack-p.vhd:293:62 */ + assign n1591_o = n1588_o | n1590_o; + /* decoder_pack-p.vhd:294:23 */ + assign n1593_o = opc_opcode_q == 8'b10110001; + /* decoder_pack-p.vhd:294:23 */ + assign n1594_o = n1591_o | n1593_o; + /* decoder_pack-p.vhd:299:7 */ + assign n1596_o = opc_opcode_q == 8'b01100010; + /* decoder_pack-p.vhd:299:23 */ + assign n1598_o = opc_opcode_q == 8'b01000010; + /* decoder_pack-p.vhd:299:23 */ + assign n1599_o = n1596_o | n1598_o; + /* decoder_pack-p.vhd:304:7 */ + assign n1601_o = opc_opcode_q == 8'b00001100; + /* decoder_pack-p.vhd:304:23 */ + assign n1603_o = opc_opcode_q == 8'b00001101; + /* decoder_pack-p.vhd:304:23 */ + assign n1604_o = n1601_o | n1603_o; + /* decoder_pack-p.vhd:304:36 */ + assign n1606_o = opc_opcode_q == 8'b00001110; + /* decoder_pack-p.vhd:304:36 */ + assign n1607_o = n1604_o | n1606_o; + /* decoder_pack-p.vhd:304:49 */ + assign n1609_o = opc_opcode_q == 8'b00001111; + /* decoder_pack-p.vhd:304:49 */ + assign n1610_o = n1607_o | n1609_o; + /* decoder_pack-p.vhd:309:7 */ + assign n1612_o = opc_opcode_q == 8'b10100011; + /* decoder_pack-p.vhd:309:23 */ + assign n1614_o = opc_opcode_q == 8'b11100011; + /* decoder_pack-p.vhd:309:23 */ + assign n1615_o = n1612_o | n1614_o; + /* decoder_pack-p.vhd:315:7 */ + assign n1617_o = opc_opcode_q == 8'b00000000; + /* decoder_pack-p.vhd:319:7 */ + assign n1619_o = opc_opcode_q == 8'b01001000; + /* decoder_pack-p.vhd:319:23 */ + assign n1621_o = opc_opcode_q == 8'b01001001; + /* decoder_pack-p.vhd:319:23 */ + assign n1622_o = n1619_o | n1621_o; + /* decoder_pack-p.vhd:319:36 */ + assign n1624_o = opc_opcode_q == 8'b01001010; + /* decoder_pack-p.vhd:319:36 */ + assign n1625_o = n1622_o | n1624_o; + /* decoder_pack-p.vhd:319:49 */ + assign n1627_o = opc_opcode_q == 8'b01001011; + /* decoder_pack-p.vhd:319:49 */ + assign n1628_o = n1625_o | n1627_o; + /* decoder_pack-p.vhd:319:62 */ + assign n1630_o = opc_opcode_q == 8'b01001100; + /* decoder_pack-p.vhd:319:62 */ + assign n1631_o = n1628_o | n1630_o; + /* decoder_pack-p.vhd:320:23 */ + assign n1633_o = opc_opcode_q == 8'b01001101; + /* decoder_pack-p.vhd:320:23 */ + assign n1634_o = n1631_o | n1633_o; + /* decoder_pack-p.vhd:320:36 */ + assign n1636_o = opc_opcode_q == 8'b01001110; + /* decoder_pack-p.vhd:320:36 */ + assign n1637_o = n1634_o | n1636_o; + /* decoder_pack-p.vhd:320:49 */ + assign n1639_o = opc_opcode_q == 8'b01001111; + /* decoder_pack-p.vhd:320:49 */ + assign n1640_o = n1637_o | n1639_o; + /* decoder_pack-p.vhd:320:62 */ + assign n1642_o = opc_opcode_q == 8'b01000000; + /* decoder_pack-p.vhd:320:62 */ + assign n1643_o = n1640_o | n1642_o; + /* decoder_pack-p.vhd:321:23 */ + assign n1645_o = opc_opcode_q == 8'b01000001; + /* decoder_pack-p.vhd:321:23 */ + assign n1646_o = n1643_o | n1645_o; + /* decoder_pack-p.vhd:325:7 */ + assign n1648_o = opc_opcode_q == 8'b01000011; + /* decoder_pack-p.vhd:330:7 */ + assign n1650_o = opc_opcode_q == 8'b00111100; + /* decoder_pack-p.vhd:330:23 */ + assign n1652_o = opc_opcode_q == 8'b00111101; + /* decoder_pack-p.vhd:330:23 */ + assign n1653_o = n1650_o | n1652_o; + /* decoder_pack-p.vhd:330:36 */ + assign n1655_o = opc_opcode_q == 8'b00111110; + /* decoder_pack-p.vhd:330:36 */ + assign n1656_o = n1653_o | n1655_o; + /* decoder_pack-p.vhd:330:49 */ + assign n1658_o = opc_opcode_q == 8'b00111111; + /* decoder_pack-p.vhd:330:49 */ + assign n1659_o = n1656_o | n1658_o; + /* decoder_pack-p.vhd:330:62 */ + assign n1661_o = opc_opcode_q == 8'b10011100; + /* decoder_pack-p.vhd:330:62 */ + assign n1662_o = n1659_o | n1661_o; + /* decoder_pack-p.vhd:331:23 */ + assign n1664_o = opc_opcode_q == 8'b10011101; + /* decoder_pack-p.vhd:331:23 */ + assign n1665_o = n1662_o | n1664_o; + /* decoder_pack-p.vhd:331:36 */ + assign n1667_o = opc_opcode_q == 8'b10011110; + /* decoder_pack-p.vhd:331:36 */ + assign n1668_o = n1665_o | n1667_o; + /* decoder_pack-p.vhd:331:49 */ + assign n1670_o = opc_opcode_q == 8'b10011111; + /* decoder_pack-p.vhd:331:49 */ + assign n1671_o = n1668_o | n1670_o; + /* decoder_pack-p.vhd:331:62 */ + assign n1673_o = opc_opcode_q == 8'b10001100; + /* decoder_pack-p.vhd:331:62 */ + assign n1674_o = n1671_o | n1673_o; + /* decoder_pack-p.vhd:332:23 */ + assign n1676_o = opc_opcode_q == 8'b10001101; + /* decoder_pack-p.vhd:332:23 */ + assign n1677_o = n1674_o | n1676_o; + /* decoder_pack-p.vhd:332:36 */ + assign n1679_o = opc_opcode_q == 8'b10001110; + /* decoder_pack-p.vhd:332:36 */ + assign n1680_o = n1677_o | n1679_o; + /* decoder_pack-p.vhd:332:49 */ + assign n1682_o = opc_opcode_q == 8'b10001111; + /* decoder_pack-p.vhd:332:49 */ + assign n1683_o = n1680_o | n1682_o; + /* decoder_pack-p.vhd:337:7 */ + assign n1685_o = opc_opcode_q == 8'b10000011; + /* decoder_pack-p.vhd:337:23 */ + assign n1687_o = opc_opcode_q == 8'b10010011; + /* decoder_pack-p.vhd:337:23 */ + assign n1688_o = n1685_o | n1687_o; + /* decoder_pack-p.vhd:343:7 */ + assign n1690_o = opc_opcode_q == 8'b11100111; + /* decoder_pack-p.vhd:343:23 */ + assign n1692_o = opc_opcode_q == 8'b11110111; + /* decoder_pack-p.vhd:343:23 */ + assign n1693_o = n1690_o | n1692_o; + /* decoder_pack-p.vhd:348:7 */ + assign n1695_o = opc_opcode_q == 8'b01110111; + /* decoder_pack-p.vhd:348:23 */ + assign n1697_o = opc_opcode_q == 8'b01100111; + /* decoder_pack-p.vhd:348:23 */ + assign n1698_o = n1695_o | n1697_o; + /* decoder_pack-p.vhd:353:7 */ + assign n1700_o = opc_opcode_q == 8'b11000101; + /* decoder_pack-p.vhd:353:23 */ + assign n1702_o = opc_opcode_q == 8'b11010101; + /* decoder_pack-p.vhd:353:23 */ + assign n1703_o = n1700_o | n1702_o; + /* decoder_pack-p.vhd:358:7 */ + assign n1705_o = opc_opcode_q == 8'b01100101; + /* decoder_pack-p.vhd:362:7 */ + assign n1707_o = opc_opcode_q == 8'b01000101; + /* decoder_pack-p.vhd:362:23 */ + assign n1709_o = opc_opcode_q == 8'b01010101; + /* decoder_pack-p.vhd:362:23 */ + assign n1710_o = n1707_o | n1709_o; + /* decoder_pack-p.vhd:367:7 */ + assign n1712_o = opc_opcode_q == 8'b01000111; + /* decoder_pack-p.vhd:371:7 */ + assign n1714_o = opc_opcode_q == 8'b00101000; + /* decoder_pack-p.vhd:371:23 */ + assign n1716_o = opc_opcode_q == 8'b00101001; + /* decoder_pack-p.vhd:371:23 */ + assign n1717_o = n1714_o | n1716_o; + /* decoder_pack-p.vhd:371:36 */ + assign n1719_o = opc_opcode_q == 8'b00101010; + /* decoder_pack-p.vhd:371:36 */ + assign n1720_o = n1717_o | n1719_o; + /* decoder_pack-p.vhd:371:49 */ + assign n1722_o = opc_opcode_q == 8'b00101011; + /* decoder_pack-p.vhd:371:49 */ + assign n1723_o = n1720_o | n1722_o; + /* decoder_pack-p.vhd:371:62 */ + assign n1725_o = opc_opcode_q == 8'b00101100; + /* decoder_pack-p.vhd:371:62 */ + assign n1726_o = n1723_o | n1725_o; + /* decoder_pack-p.vhd:372:23 */ + assign n1728_o = opc_opcode_q == 8'b00101101; + /* decoder_pack-p.vhd:372:23 */ + assign n1729_o = n1726_o | n1728_o; + /* decoder_pack-p.vhd:372:36 */ + assign n1731_o = opc_opcode_q == 8'b00101110; + /* decoder_pack-p.vhd:372:36 */ + assign n1732_o = n1729_o | n1731_o; + /* decoder_pack-p.vhd:372:49 */ + assign n1734_o = opc_opcode_q == 8'b00101111; + /* decoder_pack-p.vhd:372:49 */ + assign n1735_o = n1732_o | n1734_o; + /* decoder_pack-p.vhd:372:62 */ + assign n1737_o = opc_opcode_q == 8'b00100000; + /* decoder_pack-p.vhd:372:62 */ + assign n1738_o = n1735_o | n1737_o; + /* decoder_pack-p.vhd:373:23 */ + assign n1740_o = opc_opcode_q == 8'b00100001; + /* decoder_pack-p.vhd:373:23 */ + assign n1741_o = n1738_o | n1740_o; + /* decoder_pack-p.vhd:373:36 */ + assign n1743_o = opc_opcode_q == 8'b00110000; + /* decoder_pack-p.vhd:373:36 */ + assign n1744_o = n1741_o | n1743_o; + /* decoder_pack-p.vhd:374:23 */ + assign n1746_o = opc_opcode_q == 8'b00110001; + /* decoder_pack-p.vhd:374:23 */ + assign n1747_o = n1744_o | n1746_o; + /* decoder_pack-p.vhd:378:7 */ + assign n1749_o = opc_opcode_q == 8'b11011000; + /* decoder_pack-p.vhd:378:23 */ + assign n1751_o = opc_opcode_q == 8'b11011001; + /* decoder_pack-p.vhd:378:23 */ + assign n1752_o = n1749_o | n1751_o; + /* decoder_pack-p.vhd:378:36 */ + assign n1754_o = opc_opcode_q == 8'b11011010; + /* decoder_pack-p.vhd:378:36 */ + assign n1755_o = n1752_o | n1754_o; + /* decoder_pack-p.vhd:378:49 */ + assign n1757_o = opc_opcode_q == 8'b11011011; + /* decoder_pack-p.vhd:378:49 */ + assign n1758_o = n1755_o | n1757_o; + /* decoder_pack-p.vhd:378:62 */ + assign n1760_o = opc_opcode_q == 8'b11011100; + /* decoder_pack-p.vhd:378:62 */ + assign n1761_o = n1758_o | n1760_o; + /* decoder_pack-p.vhd:379:23 */ + assign n1763_o = opc_opcode_q == 8'b11011101; + /* decoder_pack-p.vhd:379:23 */ + assign n1764_o = n1761_o | n1763_o; + /* decoder_pack-p.vhd:379:36 */ + assign n1766_o = opc_opcode_q == 8'b11011110; + /* decoder_pack-p.vhd:379:36 */ + assign n1767_o = n1764_o | n1766_o; + /* decoder_pack-p.vhd:379:49 */ + assign n1769_o = opc_opcode_q == 8'b11011111; + /* decoder_pack-p.vhd:379:49 */ + assign n1770_o = n1767_o | n1769_o; + /* decoder_pack-p.vhd:379:62 */ + assign n1772_o = opc_opcode_q == 8'b11010000; + /* decoder_pack-p.vhd:379:62 */ + assign n1773_o = n1770_o | n1772_o; + /* decoder_pack-p.vhd:380:23 */ + assign n1775_o = opc_opcode_q == 8'b11010001; + /* decoder_pack-p.vhd:380:23 */ + assign n1776_o = n1773_o | n1775_o; + /* decoder_pack-p.vhd:384:7 */ + assign n1778_o = opc_opcode_q == 8'b11010011; + assign n1779_o = {n1778_o, n1776_o, n1747_o, n1712_o, n1710_o, n1705_o, n1703_o, n1698_o, n1693_o, n1688_o, n1683_o, n1648_o, n1646_o, n1617_o, n1615_o, n1610_o, n1599_o, n1594_o, n1565_o, n1536_o, n1534_o, n1505_o, n1503_o, n1501_o, n1496_o, n1494_o, n1483_o, n1481_o, n1458_o, n1453_o, n1448_o, n1425_o, n1393_o, n1388_o, n1365_o, n1360_o, n1355_o, n1329_o, n1327_o, n1322_o, n1320_o, n1318_o, n1313_o, n1311_o, n1309_o, n1286_o, n1284_o, n1255_o, n1250_o}; + /* decoder_pack-p.vhd:121:5 */ + always @* + case (n1779_o) + 49'b1000000000000000000000000000000000000000000000000: n1830_o = 6'b111001; + 49'b0100000000000000000000000000000000000000000000000: n1830_o = 6'b111000; + 49'b0010000000000000000000000000000000000000000000000: n1830_o = 6'b110111; + 49'b0001000000000000000000000000000000000000000000000: n1830_o = 6'b110110; + 49'b0000100000000000000000000000000000000000000000000: n1830_o = 6'b110101; + 49'b0000010000000000000000000000000000000000000000000: n1830_o = 6'b110100; + 49'b0000001000000000000000000000000000000000000000000: n1830_o = 6'b110011; + 49'b0000000100000000000000000000000000000000000000000: n1830_o = 6'b110001; + 49'b0000000010000000000000000000000000000000000000000: n1830_o = 6'b110000; + 49'b0000000001000000000000000000000000000000000000000: n1830_o = 6'b101111; + 49'b0000000000100000000000000000000000000000000000000: n1830_o = 6'b101101; + 49'b0000000000010000000000000000000000000000000000000: n1830_o = 6'b101011; + 49'b0000000000001000000000000000000000000000000000000: n1830_o = 6'b101010; + 49'b0000000000000100000000000000000000000000000000000: n1830_o = 6'b101001; + 49'b0000000000000010000000000000000000000000000000000: n1830_o = 6'b100111; + 49'b0000000000000001000000000000000000000000000000000: n1830_o = 6'b100110; + 49'b0000000000000000100000000000000000000000000000000: n1830_o = 6'b100101; + 49'b0000000000000000010000000000000000000000000000000: n1830_o = 6'b100100; + 49'b0000000000000000001000000000000000000000000000000: n1830_o = 6'b100011; + 49'b0000000000000000000100000000000000000000000000000: n1830_o = 6'b100010; + 49'b0000000000000000000010000000000000000000000000000: n1830_o = 6'b100001; + 49'b0000000000000000000001000000000000000000000000000: n1830_o = 6'b100000; + 49'b0000000000000000000000100000000000000000000000000: n1830_o = 6'b011111; + 49'b0000000000000000000000010000000000000000000000000: n1830_o = 6'b011110; + 49'b0000000000000000000000001000000000000000000000000: n1830_o = 6'b011101; + 49'b0000000000000000000000000100000000000000000000000: n1830_o = 6'b011100; + 49'b0000000000000000000000000010000000000000000000000: n1830_o = 6'b011010; + 49'b0000000000000000000000000001000000000000000000000: n1830_o = 6'b011001; + 49'b0000000000000000000000000000100000000000000000000: n1830_o = 6'b011000; + 49'b0000000000000000000000000000010000000000000000000: n1830_o = 6'b010111; + 49'b0000000000000000000000000000001000000000000000000: n1830_o = 6'b010110; + 49'b0000000000000000000000000000000100000000000000000: n1830_o = 6'b010100; + 49'b0000000000000000000000000000000010000000000000000: n1830_o = 6'b010011; + 49'b0000000000000000000000000000000001000000000000000: n1830_o = 6'b010001; + 49'b0000000000000000000000000000000000100000000000000: n1830_o = 6'b010000; + 49'b0000000000000000000000000000000000010000000000000: n1830_o = 6'b001111; + 49'b0000000000000000000000000000000000001000000000000: n1830_o = 6'b001110; + 49'b0000000000000000000000000000000000000100000000000: n1830_o = 6'b001101; + 49'b0000000000000000000000000000000000000010000000000: n1830_o = 6'b001100; + 49'b0000000000000000000000000000000000000001000000000: n1830_o = 6'b001011; + 49'b0000000000000000000000000000000000000000100000000: n1830_o = 6'b001010; + 49'b0000000000000000000000000000000000000000010000000: n1830_o = 6'b001001; + 49'b0000000000000000000000000000000000000000001000000: n1830_o = 6'b001000; + 49'b0000000000000000000000000000000000000000000100000: n1830_o = 6'b000111; + 49'b0000000000000000000000000000000000000000000010000: n1830_o = 6'b000110; + 49'b0000000000000000000000000000000000000000000001000: n1830_o = 6'b000100; + 49'b0000000000000000000000000000000000000000000000100: n1830_o = 6'b000011; + 49'b0000000000000000000000000000000000000000000000010: n1830_o = 6'b000010; + 49'b0000000000000000000000000000000000000000000000001: n1830_o = 6'b000001; + default: n1830_o = 6'b101001; + endcase + /* decoder_pack-p.vhd:121:5 */ + always @* + case (n1779_o) + 49'b1000000000000000000000000000000000000000000000000: n1854_o = 1'b1; + 49'b0100000000000000000000000000000000000000000000000: n1854_o = 1'b0; + 49'b0010000000000000000000000000000000000000000000000: n1854_o = 1'b0; + 49'b0001000000000000000000000000000000000000000000000: n1854_o = 1'b0; + 49'b0000100000000000000000000000000000000000000000000: n1854_o = 1'b0; + 49'b0000010000000000000000000000000000000000000000000: n1854_o = 1'b0; + 49'b0000001000000000000000000000000000000000000000000: n1854_o = 1'b0; + 49'b0000000100000000000000000000000000000000000000000: n1854_o = 1'b0; + 49'b0000000010000000000000000000000000000000000000000: n1854_o = 1'b0; + 49'b0000000001000000000000000000000000000000000000000: n1854_o = 1'b1; + 49'b0000000000100000000000000000000000000000000000000: n1854_o = 1'b1; + 49'b0000000000010000000000000000000000000000000000000: n1854_o = 1'b1; + 49'b0000000000001000000000000000000000000000000000000: n1854_o = 1'b0; + 49'b0000000000000100000000000000000000000000000000000: n1854_o = 1'b0; + 49'b0000000000000010000000000000000000000000000000000: n1854_o = 1'b1; + 49'b0000000000000001000000000000000000000000000000000: n1854_o = 1'b1; + 49'b0000000000000000100000000000000000000000000000000: n1854_o = 1'b0; + 49'b0000000000000000010000000000000000000000000000000: n1854_o = 1'b1; + 49'b0000000000000000001000000000000000000000000000000: n1854_o = 1'b0; + 49'b0000000000000000000100000000000000000000000000000: n1854_o = 1'b0; + 49'b0000000000000000000010000000000000000000000000000: n1854_o = 1'b0; + 49'b0000000000000000000001000000000000000000000000000: n1854_o = 1'b0; + 49'b0000000000000000000000100000000000000000000000000: n1854_o = 1'b1; + 49'b0000000000000000000000010000000000000000000000000: n1854_o = 1'b1; + 49'b0000000000000000000000001000000000000000000000000: n1854_o = 1'b1; + 49'b0000000000000000000000000100000000000000000000000: n1854_o = 1'b1; + 49'b0000000000000000000000000010000000000000000000000: n1854_o = 1'b1; + 49'b0000000000000000000000000001000000000000000000000: n1854_o = 1'b1; + 49'b0000000000000000000000000000100000000000000000000: n1854_o = 1'b1; + 49'b0000000000000000000000000000010000000000000000000: n1854_o = 1'b1; + 49'b0000000000000000000000000000001000000000000000000: n1854_o = 1'b1; + 49'b0000000000000000000000000000000100000000000000000: n1854_o = 1'b0; + 49'b0000000000000000000000000000000010000000000000000: n1854_o = 1'b1; + 49'b0000000000000000000000000000000001000000000000000: n1854_o = 1'b1; + 49'b0000000000000000000000000000000000100000000000000: n1854_o = 1'b0; + 49'b0000000000000000000000000000000000010000000000000: n1854_o = 1'b0; + 49'b0000000000000000000000000000000000001000000000000: n1854_o = 1'b0; + 49'b0000000000000000000000000000000000000100000000000: n1854_o = 1'b0; + 49'b0000000000000000000000000000000000000010000000000: n1854_o = 1'b0; + 49'b0000000000000000000000000000000000000001000000000: n1854_o = 1'b0; + 49'b0000000000000000000000000000000000000000100000000: n1854_o = 1'b0; + 49'b0000000000000000000000000000000000000000010000000: n1854_o = 1'b0; + 49'b0000000000000000000000000000000000000000001000000: n1854_o = 1'b0; + 49'b0000000000000000000000000000000000000000000100000: n1854_o = 1'b0; + 49'b0000000000000000000000000000000000000000000010000: n1854_o = 1'b1; + 49'b0000000000000000000000000000000000000000000001000: n1854_o = 1'b1; + 49'b0000000000000000000000000000000000000000000000100: n1854_o = 1'b0; + 49'b0000000000000000000000000000000000000000000000010: n1854_o = 1'b1; + 49'b0000000000000000000000000000000000000000000000001: n1854_o = 1'b0; + default: n1854_o = 1'b0; + endcase + assign n1858_o = {n1854_o, n1830_o}; + assign n1859_o = {n1180_o, n1171_o}; + /* decoder_pack-p.vhd:466:5 */ + assign n1860_o = n1183_o ? n1858_o : n1859_o; + /* decoder.vhd:301:14 */ + assign n1863_o = ~res_i; + /* decoder.vhd:313:40 */ + assign n1865_o = mnemonic_rec_s[5:0]; + /* decoder.vhd:310:9 */ + assign n1867_o = opc_inj_int_s ? 8'b00010100 : opc_opcode_q; + /* decoder.vhd:310:9 */ + assign n1868_o = opc_inj_int_s ? mnemonic_q : n1865_o; + /* decoder.vhd:308:9 */ + assign n1869_o = opc_read_bus_s ? data_i : n1867_o; + /* decoder.vhd:308:9 */ + assign n1870_o = opc_read_bus_s ? mnemonic_q : n1868_o; + /* decoder.vhd:322:39 */ + assign n1880_o = mnemonic_rec_s[6]; + /* decoder.vhd:324:24 */ + assign n1882_o = 1'b1 ? mnemonic_q : n1883_o; + /* decoder.vhd:325:41 */ + assign n1883_o = mnemonic_rec_s[5:0]; + /* decoder.vhd:343:28 */ + assign int_b_n1884 = int_b_tf_o; // (signal) + /* decoder.vhd:352:28 */ + assign int_b_n1886 = int_b_tim_int_o; // (signal) + /* decoder.vhd:355:28 */ + assign int_b_n1887 = int_b_int_pending_o; // (signal) + /* decoder.vhd:356:28 */ + assign int_b_n1888 = int_b_int_in_progress_o; // (signal) + /* decoder.vhd:333:3 */ + t48_int int_b ( + .clk_i(clk_i), + .res_i(res_i), + .en_clk_i(en_clk_i), + .xtal_i(xtal_i), + .xtal_en_i(xtal_en_i), + .clk_mstate_i(clk_mstate_i), + .jtf_executed_i(jtf_executed_s), + .tim_overflow_i(tim_overflow_i), + .en_tcnti_i(en_tcnti_s), + .dis_tcnti_i(dis_tcnti_s), + .int_n_i(int_n_i), + .ale_i(ale_i), + .last_cycle_i(last_cycle_s), + .en_i_i(en_i_s), + .dis_i_i(dis_i_s), + .retr_executed_i(retr_executed_s), + .int_executed_i(int_executed_s), + .tf_o(int_b_tf_o), + .ext_int_o(), + .tim_int_o(int_b_tim_int_o), + .int_pending_o(int_b_int_pending_o), + .int_in_progress_o(int_b_int_in_progress_o)); + /* decoder.vhd:359:19 */ + assign n1898_o = ~opc_multi_cycle_s; + /* decoder.vhd:360:38 */ + assign n1899_o = clk_second_cycle_i & opc_multi_cycle_s; + /* decoder.vhd:359:41 */ + assign n1900_o = n1898_o | n1899_o; + /* decoder.vhd:393:26 */ + assign n1903_o = ~clk_second_cycle_i; + /* decoder.vhd:394:46 */ + assign n1904_o = assert_psen_s & clk_second_cycle_i; + /* decoder.vhd:393:49 */ + assign n1905_o = n1903_o | n1904_o; + /* decoder.vhd:399:19 */ + assign n1906_o = ~ea_i; + /* decoder.vhd:400:16 */ + assign n1907_o = ~int_pending_s; + /* decoder.vhd:400:13 */ + assign n1910_o = n1907_o ? 1'b1 : 1'b0; + /* decoder.vhd:405:16 */ + assign n1911_o = ~int_pending_s; + /* decoder.vhd:405:13 */ + assign n1914_o = n1911_o ? 1'b1 : 1'b0; + /* decoder.vhd:399:11 */ + assign n1916_o = n1906_o ? n1910_o : 1'b0; + /* decoder.vhd:399:11 */ + assign n1919_o = n1906_o ? 1'b0 : 1'b1; + /* decoder.vhd:399:11 */ + assign n1921_o = n1906_o ? 1'b0 : n1914_o; + /* decoder.vhd:398:9 */ + assign n1923_o = n1905_o ? n1916_o : 1'b0; + /* decoder.vhd:398:9 */ + assign n1925_o = n1905_o ? n1919_o : 1'b0; + /* decoder.vhd:398:9 */ + assign n1927_o = n1905_o ? n1921_o : 1'b0; + /* decoder.vhd:413:12 */ + assign n1928_o = ~clk_second_cycle_i; + /* decoder.vhd:414:14 */ + assign n1929_o = ~int_pending_s; + /* decoder.vhd:414:11 */ + assign n1932_o = n1929_o ? 1'b1 : 1'b0; + /* decoder.vhd:414:11 */ + assign n1935_o = n1929_o ? 1'b0 : 1'b1; + /* decoder.vhd:413:9 */ + assign n1937_o = n1928_o ? n1932_o : 1'b0; + /* decoder.vhd:413:9 */ + assign n1939_o = n1928_o ? n1935_o : 1'b0; + /* decoder.vhd:397:7 */ + assign n1941_o = clk_mstate_i == 3'b000; + /* decoder.vhd:422:31 */ + assign n1942_o = ~branch_taken_q; + /* decoder.vhd:422:27 */ + assign n1943_o = n1942_o & n1905_o; + /* decoder.vhd:423:12 */ + assign n1944_o = ~int_pending_s; + /* decoder.vhd:422:50 */ + assign n1945_o = n1944_o & n1943_o; + /* decoder.vhd:422:9 */ + assign n1948_o = n1945_o ? 1'b1 : 1'b0; + /* decoder.vhd:421:7 */ + assign n1950_o = clk_mstate_i == 3'b001; + /* decoder.vhd:428:9 */ + assign n1953_o = n1905_o ? 1'b1 : 1'b0; + /* decoder.vhd:427:7 */ + assign n1955_o = clk_mstate_i == 3'b010; + /* decoder.vhd:441:14 */ + assign n1956_o = ~clk_second_cycle_i; + /* decoder.vhd:441:37 */ + assign n1957_o = assert_psen_s & n1956_o; + /* decoder.vhd:442:13 */ + assign n1958_o = n1957_o | last_cycle_s; + /* decoder.vhd:440:23 */ + assign n1959_o = n1958_o & ea_i; + /* decoder.vhd:440:9 */ + assign n1962_o = n1959_o ? 1'b1 : 1'b0; + /* decoder.vhd:440:9 */ + assign n1965_o = n1959_o ? 1'b1 : 1'b0; + /* decoder.vhd:440:9 */ + assign n1968_o = n1959_o ? 1'b1 : 1'b0; + /* decoder.vhd:439:7 */ + assign n1970_o = clk_mstate_i == 3'b011; + /* decoder.vhd:450:28 */ + assign n1971_o = n1905_o | last_cycle_s; + /* decoder.vhd:449:23 */ + assign n1972_o = n1971_o & ea_i; + /* decoder.vhd:453:12 */ + assign n1973_o = ~p2_output_exp_s; + /* decoder.vhd:450:45 */ + assign n1974_o = n1973_o & n1972_o; + /* decoder.vhd:455:12 */ + assign n1975_o = ~movx_first_cycle_s; + /* decoder.vhd:453:32 */ + assign n1976_o = n1975_o & n1974_o; + /* decoder.vhd:449:9 */ + assign n1979_o = n1976_o ? 1'b1 : 1'b0; + /* decoder.vhd:448:7 */ + assign n1981_o = clk_mstate_i == 3'b100; + assign n1982_o = {n1981_o, n1970_o, n1955_o, n1950_o, n1941_o}; + /* decoder.vhd:396:5 */ + always @* + case (n1982_o) + 5'b10000: n1984_o = 1'b0; + 5'b01000: n1984_o = 1'b0; + 5'b00100: n1984_o = 1'b0; + 5'b00010: n1984_o = 1'b0; + 5'b00001: n1984_o = n1923_o; + default: n1984_o = 1'b0; + endcase + /* decoder.vhd:396:5 */ + always @* + case (n1982_o) + 5'b10000: n1987_o = 1'b0; + 5'b01000: n1987_o = n1962_o; + 5'b00100: n1987_o = 1'b0; + 5'b00010: n1987_o = 1'b0; + 5'b00001: n1987_o = 1'b0; + default: n1987_o = 1'b0; + endcase + /* decoder.vhd:396:5 */ + always @* + case (n1982_o) + 5'b10000: n1990_o = 1'b0; + 5'b01000: n1990_o = n1965_o; + 5'b00100: n1990_o = 1'b0; + 5'b00010: n1990_o = 1'b0; + 5'b00001: n1990_o = 1'b0; + default: n1990_o = 1'b0; + endcase + /* decoder.vhd:396:5 */ + always @* + case (n1982_o) + 5'b10000: n1993_o = n1979_o; + 5'b01000: n1993_o = n1968_o; + 5'b00100: n1993_o = 1'b0; + 5'b00010: n1993_o = 1'b0; + 5'b00001: n1993_o = n1925_o; + default: n1993_o = 1'b0; + endcase + /* decoder.vhd:396:5 */ + always @* + case (n1982_o) + 5'b10000: n1996_o = 1'b0; + 5'b01000: n1996_o = 1'b0; + 5'b00100: n1996_o = 1'b0; + 5'b00010: n1996_o = 1'b0; + 5'b00001: n1996_o = n1937_o; + default: n1996_o = 1'b0; + endcase + /* decoder.vhd:396:5 */ + always @* + case (n1982_o) + 5'b10000: n1999_o = 1'b0; + 5'b01000: n1999_o = 1'b0; + 5'b00100: n1999_o = 1'b0; + 5'b00010: n1999_o = 1'b0; + 5'b00001: n1999_o = n1939_o; + default: n1999_o = 1'b0; + endcase + /* decoder.vhd:396:5 */ + always @* + case (n1982_o) + 5'b10000: n2002_o = 1'b0; + 5'b01000: n2002_o = 1'b0; + 5'b00100: n2002_o = 1'b0; + 5'b00010: n2002_o = n1948_o; + 5'b00001: n2002_o = 1'b0; + default: n2002_o = 1'b0; + endcase + /* decoder.vhd:396:5 */ + always @* + case (n1982_o) + 5'b10000: n2005_o = 1'b0; + 5'b01000: n2005_o = 1'b0; + 5'b00100: n2005_o = n1953_o; + 5'b00010: n2005_o = 1'b0; + 5'b00001: n2005_o = 1'b0; + default: n2005_o = 1'b0; + endcase + /* decoder.vhd:396:5 */ + always @* + case (n1982_o) + 5'b10000: n2008_o = 1'b0; + 5'b01000: n2008_o = 1'b0; + 5'b00100: n2008_o = 1'b0; + 5'b00010: n2008_o = 1'b0; + 5'b00001: n2008_o = n1927_o; + default: n2008_o = 1'b0; + endcase + /* decoder.vhd:615:5 */ + assign n2015_o = int_in_progress_s ? 1'b0 : mb_q; + /* decoder.vhd:622:8 */ + assign n2016_o = ~clk_second_cycle_i; + /* decoder.vhd:622:48 */ + assign n2018_o = clk_mstate_i == 3'b001; + /* decoder.vhd:622:31 */ + assign n2019_o = n2018_o & n2016_o; + /* decoder.vhd:624:22 */ + assign n2020_o = opc_opcode_q[3]; + /* decoder.vhd:625:43 */ + assign n2021_o = opc_opcode_q[2:0]; + /* decoder.vhd:627:50 */ + assign n2022_o = opc_opcode_q[0]; + /* decoder.vhd:627:36 */ + assign n2024_o = {2'b00, n2022_o}; + /* decoder.vhd:624:7 */ + assign n2025_o = n2020_o ? n2021_o : n2024_o; + assign n2027_o = n2026_o[7:3]; + /* decoder.vhd:622:5 */ + assign n2030_o = n2019_o ? 1'b1 : 1'b0; + assign n2032_o = {n2027_o, n2025_o}; + /* decoder.vhd:622:5 */ + assign n2034_o = n2019_o ? n2032_o : 8'bX; + /* decoder.vhd:622:5 */ + assign n2038_o = n2019_o ? 1'b1 : 1'b0; + /* decoder.vhd:643:28 */ + assign n2040_o = opc_opcode_q[3]; + /* decoder.vhd:643:32 */ + assign n2041_o = ~n2040_o; + /* decoder.vhd:642:44 */ + assign n2043_o = 1'b0 | n2041_o; + /* decoder.vhd:642:13 */ + assign n2050_o = n2043_o ? 1'b1 : n2030_o; + /* decoder.vhd:642:13 */ + assign n2053_o = n2043_o ? 1'b1 : 1'b0; + /* decoder.vhd:642:13 */ + assign n2056_o = n2043_o ? 2'b00 : 2'b01; + /* decoder.vhd:641:11 */ + assign n2058_o = clk_mstate_i == 3'b010; + /* decoder.vhd:648:11 */ + assign n2063_o = clk_mstate_i == 3'b011; + /* decoder.vhd:655:28 */ + assign n2067_o = opc_opcode_q[4]; + /* decoder.vhd:655:13 */ + assign n2070_o = n2067_o ? 1'b1 : 1'b0; + /* decoder.vhd:652:11 */ + assign n2072_o = clk_mstate_i == 3'b100; + assign n2073_o = {n2072_o, n2063_o, n2058_o}; + /* decoder.vhd:639:9 */ + always @* + case (n2073_o) + 3'b100: n2076_o = 1'b1; + 3'b010: n2076_o = 1'b0; + 3'b001: n2076_o = 1'b0; + default: n2076_o = 1'b0; + endcase + /* decoder.vhd:639:9 */ + always @* + case (n2073_o) + 3'b100: n2079_o = 1'b0; + 3'b010: n2079_o = 1'b1; + 3'b001: n2079_o = 1'b0; + default: n2079_o = 1'b0; + endcase + /* decoder.vhd:639:9 */ + always @* + case (n2073_o) + 3'b100: n2082_o = 1'b1; + 3'b010: n2082_o = 1'b0; + 3'b001: n2082_o = 1'b0; + default: n2082_o = 1'b0; + endcase + /* decoder.vhd:639:9 */ + always @* + case (n2073_o) + 3'b100: n2083_o = n2030_o; + 3'b010: n2083_o = n2030_o; + 3'b001: n2083_o = n2050_o; + default: n2083_o = n2030_o; + endcase + /* decoder.vhd:639:9 */ + always @* + case (n2073_o) + 3'b100: n2086_o = 1'b0; + 3'b010: n2086_o = 1'b1; + 3'b001: n2086_o = n2053_o; + default: n2086_o = 1'b0; + endcase + /* decoder.vhd:639:9 */ + always @* + case (n2073_o) + 3'b100: n2089_o = 4'b1010; + 3'b010: n2089_o = 4'b1100; + 3'b001: n2089_o = 4'b1100; + default: n2089_o = 4'b1100; + endcase + /* decoder.vhd:639:9 */ + always @* + case (n2073_o) + 3'b100: n2091_o = n2070_o; + 3'b010: n2091_o = 1'b0; + 3'b001: n2091_o = 1'b0; + default: n2091_o = 1'b0; + endcase + /* decoder.vhd:639:9 */ + always @* + case (n2073_o) + 3'b100: n2093_o = 2'b01; + 3'b010: n2093_o = 2'b01; + 3'b001: n2093_o = n2056_o; + default: n2093_o = 2'b01; + endcase + /* decoder.vhd:639:9 */ + always @* + case (n2073_o) + 3'b100: n2095_o = alu_carry_i; + 3'b010: n2095_o = 1'b0; + 3'b001: n2095_o = 1'b0; + default: n2095_o = 1'b0; + endcase + /* decoder.vhd:639:9 */ + always @* + case (n2073_o) + 3'b100: n2098_o = 1'b1; + 3'b010: n2098_o = 1'b0; + 3'b001: n2098_o = 1'b0; + default: n2098_o = 1'b0; + endcase + /* decoder.vhd:639:9 */ + always @* + case (n2073_o) + 3'b100: n2101_o = 1'b1; + 3'b010: n2101_o = 1'b0; + 3'b001: n2101_o = 1'b0; + default: n2101_o = 1'b0; + endcase + /* decoder.vhd:638:7 */ + assign n2103_o = opc_mnemonic_s == 6'b000001; + /* decoder.vhd:675:13 */ + assign n2105_o = clk_mstate_i == 3'b000; + /* decoder.vhd:682:30 */ + assign n2109_o = opc_opcode_q[4]; + /* decoder.vhd:682:15 */ + assign n2112_o = n2109_o ? 1'b1 : 1'b0; + /* decoder.vhd:679:13 */ + assign n2114_o = clk_mstate_i == 3'b010; + assign n2115_o = {n2114_o, n2105_o}; + /* decoder.vhd:673:11 */ + always @* + case (n2115_o) + 2'b10: n2118_o = 1'b1; + 2'b01: n2118_o = 1'b0; + default: n2118_o = 1'b0; + endcase + /* decoder.vhd:673:11 */ + always @* + case (n2115_o) + 2'b10: n2121_o = 1'b0; + 2'b01: n2121_o = 1'b1; + default: n2121_o = 1'b0; + endcase + /* decoder.vhd:673:11 */ + always @* + case (n2115_o) + 2'b10: n2124_o = 1'b1; + 2'b01: n2124_o = 1'b0; + default: n2124_o = 1'b0; + endcase + /* decoder.vhd:673:11 */ + always @* + case (n2115_o) + 2'b10: n2127_o = 4'b1010; + 2'b01: n2127_o = 4'b1100; + default: n2127_o = 4'b1100; + endcase + /* decoder.vhd:673:11 */ + always @* + case (n2115_o) + 2'b10: n2129_o = n2112_o; + 2'b01: n2129_o = 1'b0; + default: n2129_o = 1'b0; + endcase + /* decoder.vhd:673:11 */ + always @* + case (n2115_o) + 2'b10: n2131_o = alu_carry_i; + 2'b01: n2131_o = 1'b0; + default: n2131_o = 1'b0; + endcase + /* decoder.vhd:673:11 */ + always @* + case (n2115_o) + 2'b10: n2134_o = 1'b1; + 2'b01: n2134_o = 1'b0; + default: n2134_o = 1'b0; + endcase + /* decoder.vhd:673:11 */ + always @* + case (n2115_o) + 2'b10: n2137_o = 1'b1; + 2'b01: n2137_o = 1'b0; + default: n2137_o = 1'b0; + endcase + /* decoder.vhd:672:9 */ + assign n2139_o = clk_second_cycle_i ? n2118_o : 1'b0; + /* decoder.vhd:672:9 */ + assign n2141_o = clk_second_cycle_i ? n2121_o : 1'b0; + /* decoder.vhd:672:9 */ + assign n2143_o = clk_second_cycle_i ? n2124_o : 1'b0; + /* decoder.vhd:672:9 */ + assign n2145_o = clk_second_cycle_i ? n2127_o : 4'b1100; + /* decoder.vhd:672:9 */ + assign n2147_o = clk_second_cycle_i ? n2129_o : 1'b0; + /* decoder.vhd:672:9 */ + assign n2149_o = clk_second_cycle_i ? n2131_o : 1'b0; + /* decoder.vhd:672:9 */ + assign n2151_o = clk_second_cycle_i ? n2134_o : 1'b0; + /* decoder.vhd:672:9 */ + assign n2153_o = clk_second_cycle_i ? n2137_o : 1'b0; + /* decoder.vhd:669:7 */ + assign n2155_o = opc_mnemonic_s == 6'b000010; + /* decoder.vhd:703:28 */ + assign n2156_o = opc_opcode_q[3]; + /* decoder.vhd:703:32 */ + assign n2157_o = ~n2156_o; + /* decoder.vhd:702:44 */ + assign n2159_o = 1'b0 | n2157_o; + /* decoder.vhd:702:13 */ + assign n2166_o = n2159_o ? 1'b1 : n2030_o; + /* decoder.vhd:702:13 */ + assign n2169_o = n2159_o ? 1'b1 : 1'b0; + /* decoder.vhd:702:13 */ + assign n2172_o = n2159_o ? 2'b00 : 2'b01; + /* decoder.vhd:701:11 */ + assign n2174_o = clk_mstate_i == 3'b010; + /* decoder.vhd:708:11 */ + assign n2179_o = clk_mstate_i == 3'b011; + /* decoder.vhd:712:11 */ + assign n2184_o = clk_mstate_i == 3'b100; + assign n2185_o = {n2184_o, n2179_o, n2174_o}; + /* decoder.vhd:699:9 */ + always @* + case (n2185_o) + 3'b100: n2188_o = 1'b1; + 3'b010: n2188_o = 1'b0; + 3'b001: n2188_o = 1'b0; + default: n2188_o = 1'b0; + endcase + /* decoder.vhd:699:9 */ + always @* + case (n2185_o) + 3'b100: n2191_o = 1'b0; + 3'b010: n2191_o = 1'b1; + 3'b001: n2191_o = 1'b0; + default: n2191_o = 1'b0; + endcase + /* decoder.vhd:699:9 */ + always @* + case (n2185_o) + 3'b100: n2194_o = 1'b1; + 3'b010: n2194_o = 1'b0; + 3'b001: n2194_o = 1'b0; + default: n2194_o = 1'b0; + endcase + /* decoder.vhd:699:9 */ + always @* + case (n2185_o) + 3'b100: n2195_o = n2030_o; + 3'b010: n2195_o = n2030_o; + 3'b001: n2195_o = n2166_o; + default: n2195_o = n2030_o; + endcase + /* decoder.vhd:699:9 */ + always @* + case (n2185_o) + 3'b100: n2198_o = 1'b0; + 3'b010: n2198_o = 1'b1; + 3'b001: n2198_o = n2169_o; + default: n2198_o = 1'b0; + endcase + /* decoder.vhd:699:9 */ + always @* + case (n2185_o) + 3'b100: n2201_o = 4'b0000; + 3'b010: n2201_o = 4'b1100; + 3'b001: n2201_o = 4'b1100; + default: n2201_o = 4'b1100; + endcase + /* decoder.vhd:699:9 */ + always @* + case (n2185_o) + 3'b100: n2203_o = 2'b01; + 3'b010: n2203_o = 2'b01; + 3'b001: n2203_o = n2172_o; + default: n2203_o = 2'b01; + endcase + /* decoder.vhd:698:7 */ + assign n2205_o = opc_mnemonic_s == 6'b000011; + /* decoder.vhd:727:13 */ + assign n2207_o = clk_mstate_i == 3'b000; + /* decoder.vhd:731:13 */ + assign n2212_o = clk_mstate_i == 3'b010; + assign n2213_o = {n2212_o, n2207_o}; + /* decoder.vhd:725:11 */ + always @* + case (n2213_o) + 2'b10: n2216_o = 1'b1; + 2'b01: n2216_o = 1'b0; + default: n2216_o = 1'b0; + endcase + /* decoder.vhd:725:11 */ + always @* + case (n2213_o) + 2'b10: n2219_o = 1'b0; + 2'b01: n2219_o = 1'b1; + default: n2219_o = 1'b0; + endcase + /* decoder.vhd:725:11 */ + always @* + case (n2213_o) + 2'b10: n2222_o = 1'b1; + 2'b01: n2222_o = 1'b0; + default: n2222_o = 1'b0; + endcase + /* decoder.vhd:725:11 */ + always @* + case (n2213_o) + 2'b10: n2225_o = 4'b0000; + 2'b01: n2225_o = 4'b1100; + default: n2225_o = 4'b1100; + endcase + /* decoder.vhd:724:9 */ + assign n2227_o = clk_second_cycle_i ? n2216_o : 1'b0; + /* decoder.vhd:724:9 */ + assign n2229_o = clk_second_cycle_i ? n2219_o : 1'b0; + /* decoder.vhd:724:9 */ + assign n2231_o = clk_second_cycle_i ? n2222_o : 1'b0; + /* decoder.vhd:724:9 */ + assign n2233_o = clk_second_cycle_i ? n2225_o : 4'b1100; + /* decoder.vhd:721:7 */ + assign n2235_o = opc_mnemonic_s == 6'b000100; + /* decoder.vhd:745:12 */ + assign n2236_o = ~clk_second_cycle_i; + /* decoder.vhd:747:27 */ + assign n2238_o = clk_mstate_i == 3'b100; + /* decoder.vhd:748:28 */ + assign n2239_o = opc_opcode_q[1:0]; + /* decoder.vhd:748:41 */ + assign n2241_o = n2239_o == 2'b00; + /* decoder.vhd:750:31 */ + assign n2242_o = opc_opcode_q[1]; + /* decoder.vhd:750:35 */ + assign n2243_o = ~n2242_o; + /* decoder.vhd:750:13 */ + assign n2246_o = n2243_o ? 1'b1 : 1'b0; + /* decoder.vhd:750:13 */ + assign n2249_o = n2243_o ? 1'b0 : 1'b1; + /* decoder.vhd:750:13 */ + assign n2252_o = n2243_o ? 1'b1 : 1'b0; + /* decoder.vhd:750:13 */ + assign n2255_o = n2243_o ? 1'b0 : 1'b1; + /* decoder.vhd:748:13 */ + assign n2257_o = n2241_o ? 1'b0 : n2246_o; + /* decoder.vhd:748:13 */ + assign n2259_o = n2241_o ? 1'b0 : n2249_o; + /* decoder.vhd:748:13 */ + assign n2261_o = n2241_o ? 1'b0 : n2252_o; + /* decoder.vhd:748:13 */ + assign n2263_o = n2241_o ? 1'b0 : n2255_o; + /* decoder.vhd:748:13 */ + assign n2266_o = n2241_o ? 1'b1 : 1'b0; + /* decoder.vhd:747:11 */ + assign n2269_o = n2238_o ? 1'b1 : 1'b0; + /* decoder.vhd:747:11 */ + assign n2271_o = n2238_o ? n2257_o : 1'b0; + /* decoder.vhd:747:11 */ + assign n2273_o = n2238_o ? n2259_o : 1'b0; + /* decoder.vhd:747:11 */ + assign n2275_o = n2238_o ? n2261_o : 1'b0; + /* decoder.vhd:747:11 */ + assign n2277_o = n2238_o ? n2263_o : 1'b0; + /* decoder.vhd:747:11 */ + assign n2279_o = n2238_o ? n2266_o : 1'b0; + /* decoder.vhd:765:13 */ + assign n2281_o = clk_mstate_i == 3'b000; + /* decoder.vhd:770:13 */ + assign n2283_o = clk_mstate_i == 3'b001; + /* decoder.vhd:779:30 */ + assign n2284_o = opc_opcode_q[1:0]; + /* decoder.vhd:779:43 */ + assign n2286_o = n2284_o == 2'b00; + /* decoder.vhd:781:33 */ + assign n2287_o = opc_opcode_q[1]; + /* decoder.vhd:781:37 */ + assign n2288_o = ~n2287_o; + /* decoder.vhd:781:15 */ + assign n2291_o = n2288_o ? 1'b1 : 1'b0; + /* decoder.vhd:781:15 */ + assign n2294_o = n2288_o ? 1'b0 : 1'b1; + /* decoder.vhd:779:15 */ + assign n2297_o = n2286_o ? 1'b1 : 1'b0; + /* decoder.vhd:779:15 */ + assign n2299_o = n2286_o ? 1'b0 : n2291_o; + /* decoder.vhd:779:15 */ + assign n2301_o = n2286_o ? 1'b0 : n2294_o; + /* decoder.vhd:775:13 */ + assign n2303_o = clk_mstate_i == 3'b010; + assign n2304_o = {n2303_o, n2283_o, n2281_o}; + /* decoder.vhd:762:11 */ + always @* + case (n2304_o) + 3'b100: n2308_o = 1'b0; + 3'b010: n2308_o = 1'b1; + 3'b001: n2308_o = 1'b1; + default: n2308_o = 1'b0; + endcase + /* decoder.vhd:762:11 */ + always @* + case (n2304_o) + 3'b100: n2312_o = 1'b1; + 3'b010: n2312_o = 1'b1; + 3'b001: n2312_o = 1'b0; + default: n2312_o = 1'b0; + endcase + /* decoder.vhd:762:11 */ + always @* + case (n2304_o) + 3'b100: n2314_o = n2297_o; + 3'b010: n2314_o = 1'b0; + 3'b001: n2314_o = 1'b0; + default: n2314_o = 1'b0; + endcase + /* decoder.vhd:762:11 */ + always @* + case (n2304_o) + 3'b100: n2316_o = n2299_o; + 3'b010: n2316_o = 1'b0; + 3'b001: n2316_o = 1'b0; + default: n2316_o = 1'b0; + endcase + /* decoder.vhd:762:11 */ + always @* + case (n2304_o) + 3'b100: n2318_o = n2301_o; + 3'b010: n2318_o = 1'b0; + 3'b001: n2318_o = 1'b0; + default: n2318_o = 1'b0; + endcase + /* decoder.vhd:762:11 */ + always @* + case (n2304_o) + 3'b100: n2321_o = 4'b0000; + 3'b010: n2321_o = 4'b1100; + 3'b001: n2321_o = 4'b1100; + default: n2321_o = 4'b1100; + endcase + /* decoder.vhd:745:9 */ + assign n2323_o = n2236_o ? 1'b0 : n2308_o; + /* decoder.vhd:745:9 */ + assign n2325_o = n2236_o ? n2269_o : 1'b0; + /* decoder.vhd:745:9 */ + assign n2327_o = n2236_o ? 1'b0 : n2312_o; + /* decoder.vhd:745:9 */ + assign n2329_o = n2236_o ? 1'b0 : n2314_o; + /* decoder.vhd:745:9 */ + assign n2331_o = n2236_o ? 1'b0 : n2316_o; + /* decoder.vhd:745:9 */ + assign n2333_o = n2236_o ? n2271_o : 1'b0; + /* decoder.vhd:745:9 */ + assign n2335_o = n2236_o ? 1'b0 : n2318_o; + /* decoder.vhd:745:9 */ + assign n2337_o = n2236_o ? n2273_o : 1'b0; + /* decoder.vhd:745:9 */ + assign n2339_o = n2236_o ? 4'b1100 : n2321_o; + /* decoder.vhd:745:9 */ + assign n2341_o = n2236_o ? n2275_o : 1'b0; + /* decoder.vhd:745:9 */ + assign n2343_o = n2236_o ? n2277_o : 1'b0; + /* decoder.vhd:745:9 */ + assign n2345_o = n2236_o ? n2279_o : 1'b0; + /* decoder.vhd:742:7 */ + assign n2347_o = opc_mnemonic_s == 6'b000101; + /* decoder.vhd:798:12 */ + assign n2348_o = ~clk_second_cycle_i; + /* decoder.vhd:811:18 */ + assign n2349_o = ~int_pending_s; + /* decoder.vhd:811:15 */ + assign n2352_o = n2349_o ? 1'b1 : 1'b0; + /* decoder.vhd:802:13 */ + assign n2354_o = clk_mstate_i == 3'b010; + /* decoder.vhd:816:13 */ + assign n2356_o = clk_mstate_i == 3'b011; + /* decoder.vhd:822:13 */ + assign n2358_o = clk_mstate_i == 3'b100; + assign n2359_o = {n2358_o, n2356_o, n2354_o}; + /* decoder.vhd:799:11 */ + always @* + case (n2359_o) + 3'b100: n2362_o = 1'b1; + 3'b010: n2362_o = n2030_o; + 3'b001: n2362_o = 1'b1; + default: n2362_o = n2030_o; + endcase + /* decoder.vhd:799:11 */ + always @* + case (n2359_o) + 3'b100: n2365_o = 1'b0; + 3'b010: n2365_o = 1'b1; + 3'b001: n2365_o = 1'b0; + default: n2365_o = 1'b0; + endcase + /* decoder.vhd:799:11 */ + always @* + case (n2359_o) + 3'b100: n2368_o = 1'b1; + 3'b010: n2368_o = 1'b0; + 3'b001: n2368_o = 1'b0; + default: n2368_o = 1'b0; + endcase + /* decoder.vhd:799:11 */ + always @* + case (n2359_o) + 3'b100: n2371_o = 1'b1; + 3'b010: n2371_o = 1'b0; + 3'b001: n2371_o = 1'b0; + default: n2371_o = 1'b0; + endcase + /* decoder.vhd:799:11 */ + always @* + case (n2359_o) + 3'b100: n2374_o = 1'b0; + 3'b010: n2374_o = 1'b0; + 3'b001: n2374_o = 1'b1; + default: n2374_o = 1'b0; + endcase + /* decoder.vhd:799:11 */ + always @* + case (n2359_o) + 3'b100: n2378_o = 2'b11; + 3'b010: n2378_o = 2'b01; + 3'b001: n2378_o = 2'b10; + default: n2378_o = 2'b01; + endcase + /* decoder.vhd:799:11 */ + always @* + case (n2359_o) + 3'b100: n2381_o = 1'b1; + 3'b010: n2381_o = 1'b0; + 3'b001: n2381_o = 1'b0; + default: n2381_o = 1'b0; + endcase + /* decoder.vhd:799:11 */ + always @* + case (n2359_o) + 3'b100: n2383_o = 1'b0; + 3'b010: n2383_o = 1'b0; + 3'b001: n2383_o = n2352_o; + default: n2383_o = 1'b0; + endcase + /* decoder.vhd:799:11 */ + always @* + case (n2359_o) + 3'b100: n2387_o = 1'b1; + 3'b010: n2387_o = 1'b1; + 3'b001: n2387_o = 1'b0; + default: n2387_o = 1'b0; + endcase + /* decoder.vhd:845:17 */ + assign n2394_o = tim_int_s ? 1'b0 : 1'b1; + assign n2395_o = n2389_o[2]; + /* decoder.vhd:845:17 */ + assign n2396_o = tim_int_s ? 1'b1 : n2395_o; + assign n2397_o = n2389_o[7:3]; + /* decoder.vhd:841:15 */ + assign n2399_o = int_pending_s ? n2394_o : 1'b0; + assign n2400_o = {n2397_o, n2396_o, 2'b11}; + /* decoder.vhd:841:15 */ + assign n2401_o = int_pending_s ? n2400_o : n2034_o; + /* decoder.vhd:841:15 */ + assign n2403_o = int_pending_s ? 1'b1 : n2038_o; + /* decoder.vhd:838:13 */ + assign n2405_o = clk_mstate_i == 3'b000; + /* decoder.vhd:856:18 */ + assign n2406_o = ~int_pending_s; + /* decoder.vhd:858:46 */ + assign n2408_o = {4'b0000, n2015_o}; + /* decoder.vhd:858:67 */ + assign n2409_o = opc_opcode_q[7:5]; + /* decoder.vhd:858:53 */ + assign n2410_o = {n2408_o, n2409_o}; + /* decoder.vhd:856:15 */ + assign n2412_o = n2406_o ? n2410_o : 8'b00000000; + /* decoder.vhd:856:15 */ + assign n2415_o = n2406_o ? 1'b0 : 1'b1; + /* decoder.vhd:853:13 */ + assign n2417_o = clk_mstate_i == 3'b001; + assign n2418_o = {n2417_o, n2405_o}; + /* decoder.vhd:836:11 */ + always @* + case (n2418_o) + 2'b10: n2420_o = 1'b0; + 2'b01: n2420_o = n2399_o; + default: n2420_o = 1'b0; + endcase + /* decoder.vhd:836:11 */ + always @* + case (n2418_o) + 2'b10: n2423_o = 1'b0; + 2'b01: n2423_o = 1'b1; + default: n2423_o = 1'b0; + endcase + /* decoder.vhd:836:11 */ + always @* + case (n2418_o) + 2'b10: n2426_o = 1'b1; + 2'b01: n2426_o = 1'b0; + default: n2426_o = 1'b0; + endcase + /* decoder.vhd:836:11 */ + always @* + case (n2418_o) + 2'b10: n2429_o = 1'b0; + 2'b01: n2429_o = 1'b1; + default: n2429_o = 1'b0; + endcase + /* decoder.vhd:836:11 */ + always @* + case (n2418_o) + 2'b10: n2430_o = n2412_o; + 2'b01: n2430_o = n2401_o; + default: n2430_o = n2034_o; + endcase + /* decoder.vhd:836:11 */ + always @* + case (n2418_o) + 2'b10: n2432_o = 1'b1; + 2'b01: n2432_o = n2403_o; + default: n2432_o = n2038_o; + endcase + /* decoder.vhd:836:11 */ + always @* + case (n2418_o) + 2'b10: n2434_o = n2415_o; + 2'b01: n2434_o = 1'b0; + default: n2434_o = 1'b0; + endcase + /* decoder.vhd:798:9 */ + assign n2436_o = n2348_o ? 1'b0 : n2420_o; + /* decoder.vhd:798:9 */ + assign n2437_o = n2348_o ? n2362_o : n2030_o; + /* decoder.vhd:798:9 */ + assign n2439_o = n2348_o ? 1'b0 : n2423_o; + /* decoder.vhd:798:9 */ + assign n2441_o = n2348_o ? n2365_o : 1'b0; + /* decoder.vhd:798:9 */ + assign n2443_o = n2348_o ? 1'b0 : n2426_o; + /* decoder.vhd:798:9 */ + assign n2445_o = n2348_o ? n2368_o : 1'b0; + /* decoder.vhd:798:9 */ + assign n2447_o = n2348_o ? n2371_o : 1'b0; + /* decoder.vhd:798:9 */ + assign n2449_o = n2348_o ? n2374_o : 1'b0; + /* decoder.vhd:798:9 */ + assign n2451_o = n2348_o ? n2378_o : 2'b01; + /* decoder.vhd:798:9 */ + assign n2453_o = n2348_o ? n2381_o : 1'b0; + /* decoder.vhd:798:9 */ + assign n2455_o = n2348_o ? 1'b0 : n2429_o; + /* decoder.vhd:798:9 */ + assign n2457_o = n2348_o ? n2383_o : 1'b0; + /* decoder.vhd:798:9 */ + assign n2458_o = n2348_o ? n2034_o : n2430_o; + /* decoder.vhd:798:9 */ + assign n2459_o = n2348_o ? n2038_o : n2432_o; + /* decoder.vhd:798:9 */ + assign n2461_o = n2348_o ? n2387_o : 1'b0; + /* decoder.vhd:798:9 */ + assign n2463_o = n2348_o ? 1'b0 : n2434_o; + /* decoder.vhd:795:7 */ + assign n2465_o = opc_mnemonic_s == 6'b000110; + /* decoder.vhd:875:25 */ + assign n2467_o = clk_mstate_i == 3'b010; + /* decoder.vhd:875:9 */ + assign n2470_o = n2467_o ? 1'b1 : 1'b0; + /* decoder.vhd:875:9 */ + assign n2473_o = n2467_o ? 1'b1 : 1'b0; + /* decoder.vhd:875:9 */ + assign n2476_o = n2467_o ? 4'b0100 : 4'b1100; + /* decoder.vhd:873:7 */ + assign n2478_o = opc_mnemonic_s == 6'b000111; + /* decoder.vhd:884:25 */ + assign n2480_o = clk_mstate_i == 3'b010; + /* decoder.vhd:884:9 */ + assign n2483_o = n2480_o ? 1'b1 : 1'b0; + /* decoder.vhd:882:7 */ + assign n2485_o = opc_mnemonic_s == 6'b001000; + /* decoder.vhd:892:25 */ + assign n2487_o = clk_mstate_i == 3'b010; + /* decoder.vhd:893:26 */ + assign n2488_o = opc_opcode_q[5]; + /* decoder.vhd:893:30 */ + assign n2489_o = ~n2488_o; + /* decoder.vhd:893:11 */ + assign n2492_o = n2489_o ? 1'b1 : 1'b0; + /* decoder.vhd:893:11 */ + assign n2495_o = n2489_o ? 1'b0 : 1'b1; + /* decoder.vhd:892:9 */ + assign n2497_o = n2487_o ? n2492_o : 1'b0; + /* decoder.vhd:892:9 */ + assign n2499_o = n2487_o ? n2495_o : 1'b0; + /* decoder.vhd:890:7 */ + assign n2501_o = opc_mnemonic_s == 6'b001001; + /* decoder.vhd:905:25 */ + assign n2503_o = clk_mstate_i == 3'b010; + /* decoder.vhd:905:9 */ + assign n2506_o = n2503_o ? 1'b1 : 1'b0; + /* decoder.vhd:905:9 */ + assign n2509_o = n2503_o ? 1'b1 : 1'b0; + /* decoder.vhd:905:9 */ + assign n2512_o = n2503_o ? 4'b0011 : 4'b1100; + /* decoder.vhd:903:7 */ + assign n2514_o = opc_mnemonic_s == 6'b001010; + /* decoder.vhd:914:25 */ + assign n2516_o = clk_mstate_i == 3'b010; + /* decoder.vhd:915:33 */ + assign n2517_o = ~psw_carry_i; + /* decoder.vhd:914:9 */ + assign n2519_o = n2516_o ? n2517_o : 1'b0; + /* decoder.vhd:914:9 */ + assign n2522_o = n2516_o ? 1'b1 : 1'b0; + /* decoder.vhd:912:7 */ + assign n2524_o = opc_mnemonic_s == 6'b001011; + /* decoder.vhd:922:25 */ + assign n2526_o = clk_mstate_i == 3'b010; + /* decoder.vhd:923:26 */ + assign n2527_o = opc_opcode_q[5]; + /* decoder.vhd:923:30 */ + assign n2528_o = ~n2527_o; + /* decoder.vhd:924:35 */ + assign n2529_o = ~psw_f0_i; + /* decoder.vhd:923:11 */ + assign n2531_o = n2528_o ? n2529_o : 1'b0; + /* decoder.vhd:923:11 */ + assign n2534_o = n2528_o ? 1'b1 : 1'b0; + /* decoder.vhd:923:11 */ + assign n2537_o = n2528_o ? 1'b0 : 1'b1; + /* decoder.vhd:922:9 */ + assign n2539_o = n2526_o ? n2531_o : 1'b0; + /* decoder.vhd:922:9 */ + assign n2541_o = n2526_o ? n2534_o : 1'b0; + /* decoder.vhd:922:9 */ + assign n2543_o = n2526_o ? n2537_o : 1'b0; + /* decoder.vhd:920:7 */ + assign n2545_o = opc_mnemonic_s == 6'b001100; + /* decoder.vhd:938:11 */ + assign n2547_o = clk_mstate_i == 3'b010; + /* decoder.vhd:944:38 */ + assign n2548_o = psw_aux_carry_i | alu_da_overflow_i; + /* decoder.vhd:944:13 */ + assign n2551_o = n2548_o ? 1'b1 : 1'b0; + /* decoder.vhd:944:13 */ + assign n2554_o = n2548_o ? 1'b1 : 1'b0; + /* decoder.vhd:943:11 */ + assign n2556_o = clk_mstate_i == 3'b011; + /* decoder.vhd:958:13 */ + assign n2559_o = alu_da_overflow_i ? 4'b1010 : 4'b1100; + /* decoder.vhd:958:13 */ + assign n2561_o = alu_da_overflow_i ? alu_carry_i : 1'b0; + /* decoder.vhd:955:11 */ + assign n2563_o = clk_mstate_i == 3'b100; + assign n2564_o = {n2563_o, n2556_o, n2547_o}; + /* decoder.vhd:936:9 */ + always @* + case (n2564_o) + 3'b100: n2567_o = 1'b1; + 3'b010: n2567_o = 1'b0; + 3'b001: n2567_o = 1'b0; + default: n2567_o = 1'b0; + endcase + /* decoder.vhd:936:9 */ + always @* + case (n2564_o) + 3'b100: n2569_o = 1'b0; + 3'b010: n2569_o = n2551_o; + 3'b001: n2569_o = 1'b0; + default: n2569_o = 1'b0; + endcase + /* decoder.vhd:936:9 */ + always @* + case (n2564_o) + 3'b100: n2572_o = 1'b1; + 3'b010: n2572_o = n2554_o; + 3'b001: n2572_o = 1'b0; + default: n2572_o = 1'b0; + endcase + /* decoder.vhd:936:9 */ + always @* + case (n2564_o) + 3'b100: n2574_o = n2559_o; + 3'b010: n2574_o = 4'b1010; + 3'b001: n2574_o = 4'b1010; + default: n2574_o = 4'b1010; + endcase + /* decoder.vhd:936:9 */ + always @* + case (n2564_o) + 3'b100: n2578_o = 1'b1; + 3'b010: n2578_o = 1'b0; + 3'b001: n2578_o = 1'b0; + default: n2578_o = 1'b0; + endcase + /* decoder.vhd:936:9 */ + always @* + case (n2564_o) + 3'b100: n2581_o = 1'b0; + 3'b010: n2581_o = 1'b0; + 3'b001: n2581_o = 1'b1; + default: n2581_o = 1'b0; + endcase + /* decoder.vhd:936:9 */ + always @* + case (n2564_o) + 3'b100: n2584_o = 1'b0; + 3'b010: n2584_o = 1'b1; + 3'b001: n2584_o = 1'b0; + default: n2584_o = 1'b0; + endcase + /* decoder.vhd:936:9 */ + always @* + case (n2564_o) + 3'b100: n2586_o = n2561_o; + 3'b010: n2586_o = 1'b0; + 3'b001: n2586_o = 1'b0; + default: n2586_o = 1'b0; + endcase + /* decoder.vhd:936:9 */ + always @* + case (n2564_o) + 3'b100: n2589_o = 1'b1; + 3'b010: n2589_o = 1'b0; + 3'b001: n2589_o = 1'b0; + default: n2589_o = 1'b0; + endcase + /* decoder.vhd:933:7 */ + assign n2591_o = opc_mnemonic_s == 6'b001101; + /* decoder.vhd:978:28 */ + assign n2592_o = opc_opcode_q[6]; + /* decoder.vhd:978:13 */ + assign n2595_o = n2592_o ? 1'b1 : 1'b0; + /* decoder.vhd:978:13 */ + assign n2598_o = n2592_o ? 1'b1 : 1'b0; + /* decoder.vhd:976:11 */ + assign n2600_o = clk_mstate_i == 3'b011; + /* decoder.vhd:987:28 */ + assign n2601_o = opc_opcode_q[6]; + /* decoder.vhd:987:32 */ + assign n2602_o = ~n2601_o; + /* decoder.vhd:987:13 */ + assign n2605_o = n2602_o ? 1'b1 : 1'b0; + /* decoder.vhd:987:13 */ + assign n2608_o = n2602_o ? 1'b0 : 1'b1; + /* decoder.vhd:983:11 */ + assign n2610_o = clk_mstate_i == 3'b100; + assign n2611_o = {n2610_o, n2600_o}; + /* decoder.vhd:975:9 */ + always @* + case (n2611_o) + 2'b10: n2613_o = n2605_o; + 2'b01: n2613_o = 1'b0; + default: n2613_o = 1'b0; + endcase + /* decoder.vhd:975:9 */ + always @* + case (n2611_o) + 2'b10: n2615_o = 1'b0; + 2'b01: n2615_o = n2595_o; + default: n2615_o = 1'b0; + endcase + /* decoder.vhd:975:9 */ + always @* + case (n2611_o) + 2'b10: n2618_o = 1'b1; + 2'b01: n2618_o = 1'b0; + default: n2618_o = 1'b0; + endcase + /* decoder.vhd:975:9 */ + always @* + case (n2611_o) + 2'b10: n2620_o = 1'b0; + 2'b01: n2620_o = n2598_o; + default: n2620_o = 1'b0; + endcase + /* decoder.vhd:975:9 */ + always @* + case (n2611_o) + 2'b10: n2623_o = 4'b1000; + 2'b01: n2623_o = 4'b1100; + default: n2623_o = 4'b1100; + endcase + /* decoder.vhd:975:9 */ + always @* + case (n2611_o) + 2'b10: n2625_o = n2608_o; + 2'b01: n2625_o = 1'b0; + default: n2625_o = 1'b0; + endcase + /* decoder.vhd:974:7 */ + assign n2627_o = opc_mnemonic_s == 6'b001110; + /* decoder.vhd:1002:25 */ + assign n2629_o = clk_mstate_i == 3'b010; + /* decoder.vhd:1003:26 */ + assign n2630_o = opc_opcode_q[4]; + /* decoder.vhd:1003:11 */ + assign n2633_o = n2630_o ? 1'b0 : 1'b1; + /* decoder.vhd:1003:11 */ + assign n2636_o = n2630_o ? 1'b1 : 1'b0; + /* decoder.vhd:1002:9 */ + assign n2638_o = n2629_o ? n2633_o : 1'b0; + /* decoder.vhd:1002:9 */ + assign n2640_o = n2629_o ? n2636_o : 1'b0; + /* decoder.vhd:1001:7 */ + assign n2642_o = opc_mnemonic_s == 6'b001111; + /* decoder.vhd:1012:25 */ + assign n2644_o = clk_mstate_i == 3'b010; + /* decoder.vhd:1013:26 */ + assign n2645_o = opc_opcode_q[4]; + /* decoder.vhd:1013:11 */ + assign n2648_o = n2645_o ? 1'b0 : 1'b1; + /* decoder.vhd:1013:11 */ + assign n2651_o = n2645_o ? 1'b1 : 1'b0; + /* decoder.vhd:1012:9 */ + assign n2653_o = n2644_o ? n2648_o : 1'b0; + /* decoder.vhd:1012:9 */ + assign n2655_o = n2644_o ? n2651_o : 1'b0; + /* decoder.vhd:1011:7 */ + assign n2657_o = opc_mnemonic_s == 6'b010000; + /* decoder.vhd:1024:12 */ + assign n2658_o = ~clk_second_cycle_i; + /* decoder.vhd:1027:13 */ + assign n2660_o = clk_mstate_i == 3'b011; + /* decoder.vhd:1033:13 */ + assign n2663_o = clk_mstate_i == 3'b100; + assign n2664_o = {n2663_o, n2660_o}; + /* decoder.vhd:1025:11 */ + always @* + case (n2664_o) + 2'b10: n2667_o = 1'b0; + 2'b01: n2667_o = 1'b1; + default: n2667_o = 1'b0; + endcase + /* decoder.vhd:1025:11 */ + always @* + case (n2664_o) + 2'b10: n2670_o = 1'b1; + 2'b01: n2670_o = 1'b0; + default: n2670_o = 1'b0; + endcase + /* decoder.vhd:1025:11 */ + always @* + case (n2664_o) + 2'b10: n2673_o = 1'b0; + 2'b01: n2673_o = 1'b1; + default: n2673_o = 1'b0; + endcase + /* decoder.vhd:1025:11 */ + always @* + case (n2664_o) + 2'b10: n2676_o = 4'b1000; + 2'b01: n2676_o = 4'b1100; + default: n2676_o = 4'b1100; + endcase + /* decoder.vhd:1025:11 */ + always @* + case (n2664_o) + 2'b10: n2679_o = 1'b1; + 2'b01: n2679_o = 1'b0; + default: n2679_o = 1'b0; + endcase + /* decoder.vhd:1025:11 */ + always @* + case (n2664_o) + 2'b10: n2682_o = 4'b0001; + 2'b01: n2682_o = 4'b0000; + default: n2682_o = 4'b0000; + endcase + assign n2683_o = opc_opcode_q[5]; + /* decoder.vhd:1025:11 */ + always @* + case (n2664_o) + 2'b10: n2684_o = 1'b0; + 2'b01: n2684_o = n2683_o; + default: n2684_o = n2683_o; + endcase + /* decoder.vhd:1025:11 */ + always @* + case (n2664_o) + 2'b10: n2687_o = 1'b1; + 2'b01: n2687_o = 1'b0; + default: n2687_o = 1'b0; + endcase + /* decoder.vhd:1050:27 */ + assign n2689_o = clk_mstate_i == 3'b000; + /* decoder.vhd:1050:37 */ + assign n2690_o = cnd_take_branch_i & n2689_o; + /* decoder.vhd:1050:11 */ + assign n2696_o = n2690_o ? 1'b1 : 1'b0; + /* decoder.vhd:1050:11 */ + assign n2699_o = n2690_o ? 1'b1 : 1'b0; + /* decoder.vhd:1024:9 */ + assign n2701_o = n2658_o ? n2667_o : 1'b0; + /* decoder.vhd:1024:9 */ + assign n2703_o = n2658_o ? n2670_o : 1'b0; + /* decoder.vhd:1024:9 */ + assign n2705_o = n2658_o ? n2673_o : 1'b0; + /* decoder.vhd:1024:9 */ + assign n2707_o = n2658_o ? 1'b0 : n2696_o; + /* decoder.vhd:1024:9 */ + assign n2709_o = n2658_o ? n2676_o : 4'b1100; + /* decoder.vhd:1024:9 */ + assign n2711_o = n2658_o ? n2679_o : 1'b0; + /* decoder.vhd:1024:9 */ + assign n2713_o = n2658_o ? n2682_o : 4'b0000; + assign n2714_o = opc_opcode_q[5]; + /* decoder.vhd:1024:9 */ + assign n2715_o = n2658_o ? n2684_o : n2714_o; + /* decoder.vhd:1024:9 */ + assign n2717_o = n2658_o ? 1'b0 : n2699_o; + /* decoder.vhd:1024:9 */ + assign n2719_o = n2658_o ? n2687_o : 1'b0; + /* decoder.vhd:1021:7 */ + assign n2721_o = opc_mnemonic_s == 6'b010001; + /* decoder.vhd:1058:25 */ + assign n2723_o = clk_mstate_i == 3'b011; + /* decoder.vhd:1059:26 */ + assign n2724_o = opc_opcode_q[4]; + /* decoder.vhd:1059:30 */ + assign n2725_o = ~n2724_o; + /* decoder.vhd:1059:11 */ + assign n2728_o = n2725_o ? 1'b1 : 1'b0; + /* decoder.vhd:1059:11 */ + assign n2731_o = n2725_o ? 1'b0 : 1'b1; + /* decoder.vhd:1058:9 */ + assign n2733_o = n2723_o ? n2728_o : 1'b0; + /* decoder.vhd:1058:9 */ + assign n2735_o = n2723_o ? n2731_o : 1'b0; + /* decoder.vhd:1057:7 */ + assign n2737_o = opc_mnemonic_s == 6'b111110; + /* decoder.vhd:1068:25 */ + assign n2739_o = clk_mstate_i == 3'b010; + /* decoder.vhd:1068:9 */ + assign n2742_o = n2739_o ? 1'b1 : 1'b0; + /* decoder.vhd:1067:7 */ + assign n2744_o = opc_mnemonic_s == 6'b010010; + /* decoder.vhd:1075:48 */ + assign n2746_o = clk_mstate_i == 3'b001; + /* decoder.vhd:1075:31 */ + assign n2747_o = n2746_o & clk_second_cycle_i; + /* decoder.vhd:1078:26 */ + assign n2748_o = opc_opcode_q[1]; + /* decoder.vhd:1078:30 */ + assign n2749_o = ~n2748_o; + /* decoder.vhd:1078:11 */ + assign n2752_o = n2749_o ? 1'b1 : 1'b0; + /* decoder.vhd:1078:11 */ + assign n2755_o = n2749_o ? 1'b0 : 1'b1; + /* decoder.vhd:1075:9 */ + assign n2758_o = n2747_o ? 1'b1 : 1'b0; + /* decoder.vhd:1075:9 */ + assign n2760_o = n2747_o ? n2752_o : 1'b0; + /* decoder.vhd:1075:9 */ + assign n2762_o = n2747_o ? n2755_o : 1'b0; + /* decoder.vhd:1073:7 */ + assign n2764_o = opc_mnemonic_s == 6'b010011; + /* decoder.vhd:1088:25 */ + assign n2766_o = clk_mstate_i == 3'b011; + /* decoder.vhd:1088:9 */ + assign n2769_o = n2766_o ? 1'b1 : 1'b0; + /* decoder.vhd:1088:9 */ + assign n2772_o = n2766_o ? 1'b1 : 1'b0; + /* decoder.vhd:1086:7 */ + assign n2774_o = opc_mnemonic_s == 6'b111010; + /* decoder.vhd:1099:48 */ + assign n2776_o = clk_mstate_i == 3'b001; + /* decoder.vhd:1099:31 */ + assign n2777_o = n2776_o & clk_second_cycle_i; + /* decoder.vhd:1099:9 */ + assign n2780_o = n2777_o ? 1'b1 : 1'b0; + /* decoder.vhd:1099:9 */ + assign n2783_o = n2777_o ? 1'b1 : 1'b0; + /* decoder.vhd:1095:7 */ + assign n2785_o = opc_mnemonic_s == 6'b010101; + /* decoder.vhd:1111:28 */ + assign n2786_o = opc_opcode_q[3]; + /* decoder.vhd:1111:32 */ + assign n2787_o = ~n2786_o; + /* decoder.vhd:1110:44 */ + assign n2789_o = 1'b0 | n2787_o; + /* decoder.vhd:1110:13 */ + assign n2796_o = n2789_o ? 1'b1 : n2030_o; + /* decoder.vhd:1110:13 */ + assign n2799_o = n2789_o ? 1'b1 : 1'b0; + /* decoder.vhd:1110:13 */ + assign n2802_o = n2789_o ? 2'b00 : 2'b01; + /* decoder.vhd:1109:11 */ + assign n2804_o = clk_mstate_i == 3'b010; + /* decoder.vhd:1117:28 */ + assign n2805_o = opc_opcode_q[3:2]; + /* decoder.vhd:1117:41 */ + assign n2807_o = n2805_o != 2'b01; + /* decoder.vhd:1117:13 */ + assign n2810_o = n2807_o ? 1'b1 : 1'b0; + /* decoder.vhd:1117:13 */ + assign n2813_o = n2807_o ? 1'b1 : 1'b0; + /* decoder.vhd:1115:11 */ + assign n2815_o = clk_mstate_i == 3'b011; + /* decoder.vhd:1126:28 */ + assign n2816_o = opc_opcode_q[3:2]; + /* decoder.vhd:1126:41 */ + assign n2818_o = n2816_o == 2'b01; + /* decoder.vhd:1126:13 */ + assign n2821_o = n2818_o ? 1'b1 : 1'b0; + /* decoder.vhd:1126:13 */ + assign n2824_o = n2818_o ? 1'b0 : 1'b1; + /* decoder.vhd:1122:11 */ + assign n2826_o = clk_mstate_i == 3'b100; + assign n2827_o = {n2826_o, n2815_o, n2804_o}; + /* decoder.vhd:1107:9 */ + always @* + case (n2827_o) + 3'b100: n2829_o = n2821_o; + 3'b010: n2829_o = 1'b0; + 3'b001: n2829_o = 1'b0; + default: n2829_o = 1'b0; + endcase + /* decoder.vhd:1107:9 */ + always @* + case (n2827_o) + 3'b100: n2831_o = 1'b0; + 3'b010: n2831_o = n2810_o; + 3'b001: n2831_o = 1'b0; + default: n2831_o = 1'b0; + endcase + /* decoder.vhd:1107:9 */ + always @* + case (n2827_o) + 3'b100: n2834_o = 1'b1; + 3'b010: n2834_o = 1'b0; + 3'b001: n2834_o = 1'b0; + default: n2834_o = 1'b0; + endcase + /* decoder.vhd:1107:9 */ + always @* + case (n2827_o) + 3'b100: n2835_o = n2030_o; + 3'b010: n2835_o = n2030_o; + 3'b001: n2835_o = n2796_o; + default: n2835_o = n2030_o; + endcase + /* decoder.vhd:1107:9 */ + always @* + case (n2827_o) + 3'b100: n2837_o = 1'b0; + 3'b010: n2837_o = n2813_o; + 3'b001: n2837_o = n2799_o; + default: n2837_o = 1'b0; + endcase + /* decoder.vhd:1107:9 */ + always @* + case (n2827_o) + 3'b100: n2840_o = 4'b1001; + 3'b010: n2840_o = 4'b1100; + 3'b001: n2840_o = 4'b1100; + default: n2840_o = 4'b1100; + endcase + /* decoder.vhd:1107:9 */ + always @* + case (n2827_o) + 3'b100: n2842_o = 2'b01; + 3'b010: n2842_o = 2'b01; + 3'b001: n2842_o = n2802_o; + default: n2842_o = 2'b01; + endcase + /* decoder.vhd:1107:9 */ + always @* + case (n2827_o) + 3'b100: n2844_o = n2824_o; + 3'b010: n2844_o = 1'b0; + 3'b001: n2844_o = 1'b0; + default: n2844_o = 1'b0; + endcase + /* decoder.vhd:1106:7 */ + assign n2846_o = opc_mnemonic_s == 6'b010100; + /* decoder.vhd:1144:12 */ + assign n2847_o = ~clk_second_cycle_i; + /* decoder.vhd:1146:27 */ + assign n2849_o = clk_mstate_i == 3'b010; + /* decoder.vhd:1146:11 */ + assign n2852_o = n2849_o ? 1'b1 : 1'b0; + /* decoder.vhd:1146:11 */ + assign n2855_o = n2849_o ? 1'b1 : 1'b0; + /* decoder.vhd:1155:27 */ + assign n2857_o = clk_mstate_i == 3'b000; + /* decoder.vhd:1155:37 */ + assign n2858_o = cnd_take_branch_i & n2857_o; + /* decoder.vhd:1155:11 */ + assign n2864_o = n2858_o ? 1'b1 : 1'b0; + /* decoder.vhd:1155:11 */ + assign n2867_o = n2858_o ? 1'b1 : 1'b0; + /* decoder.vhd:1144:9 */ + assign n2869_o = n2847_o ? n2852_o : 1'b0; + /* decoder.vhd:1144:9 */ + assign n2871_o = n2847_o ? 1'b0 : n2864_o; + /* decoder.vhd:1144:9 */ + assign n2873_o = n2847_o ? n2855_o : 1'b0; + /* decoder.vhd:1144:9 */ + assign n2875_o = n2847_o ? 1'b0 : n2867_o; + /* decoder.vhd:1140:7 */ + assign n2877_o = opc_mnemonic_s == 6'b010110; + /* decoder.vhd:1166:12 */ + assign n2878_o = ~clk_second_cycle_i; + /* decoder.vhd:1168:27 */ + assign n2880_o = clk_mstate_i == 3'b010; + /* decoder.vhd:1170:48 */ + assign n2881_o = opc_opcode_q[4]; + /* decoder.vhd:1168:11 */ + assign n2884_o = n2880_o ? 1'b1 : 1'b0; + assign n2885_o = opc_opcode_q[5]; + /* decoder.vhd:1166:9 */ + assign n2886_o = n2904_o ? n2881_o : n2885_o; + /* decoder.vhd:1176:27 */ + assign n2888_o = clk_mstate_i == 3'b000; + /* decoder.vhd:1176:37 */ + assign n2889_o = cnd_take_branch_i & n2888_o; + /* decoder.vhd:1176:11 */ + assign n2895_o = n2889_o ? 1'b1 : 1'b0; + /* decoder.vhd:1176:11 */ + assign n2898_o = n2889_o ? 1'b1 : 1'b0; + /* decoder.vhd:1166:9 */ + assign n2900_o = n2878_o ? 1'b0 : n2895_o; + /* decoder.vhd:1166:9 */ + assign n2902_o = n2878_o ? n2884_o : 1'b0; + /* decoder.vhd:1166:9 */ + assign n2904_o = n2878_o & n2880_o; + /* decoder.vhd:1166:9 */ + assign n2906_o = n2878_o ? 1'b0 : n2898_o; + /* decoder.vhd:1162:7 */ + assign n2908_o = opc_mnemonic_s == 6'b010111; + /* decoder.vhd:1186:12 */ + assign n2909_o = ~clk_second_cycle_i; + /* decoder.vhd:1188:27 */ + assign n2911_o = clk_mstate_i == 3'b010; + /* decoder.vhd:1190:28 */ + assign n2912_o = opc_opcode_q[7]; + /* decoder.vhd:1190:13 */ + assign n2915_o = n2912_o ? 4'b0011 : 4'b0100; + /* decoder.vhd:1188:11 */ + assign n2918_o = n2911_o ? 1'b1 : 1'b0; + /* decoder.vhd:1188:11 */ + assign n2920_o = n2911_o ? n2915_o : 4'b0000; + /* decoder.vhd:1203:27 */ + assign n2922_o = clk_mstate_i == 3'b000; + /* decoder.vhd:1203:37 */ + assign n2923_o = cnd_take_branch_i & n2922_o; + /* decoder.vhd:1203:11 */ + assign n2929_o = n2923_o ? 1'b1 : 1'b0; + /* decoder.vhd:1203:11 */ + assign n2932_o = n2923_o ? 1'b1 : 1'b0; + /* decoder.vhd:1186:9 */ + assign n2934_o = n2909_o ? 1'b0 : n2929_o; + /* decoder.vhd:1186:9 */ + assign n2936_o = n2909_o ? n2918_o : 1'b0; + /* decoder.vhd:1186:9 */ + assign n2938_o = n2909_o ? n2920_o : 4'b0000; + /* decoder.vhd:1186:9 */ + assign n2940_o = n2909_o ? 1'b0 : n2932_o; + /* decoder.vhd:1183:7 */ + assign n2942_o = opc_mnemonic_s == 6'b011000; + /* decoder.vhd:1217:13 */ + assign n2944_o = clk_mstate_i == 3'b000; + /* decoder.vhd:1223:40 */ + assign n2946_o = {4'b0000, n2015_o}; + /* decoder.vhd:1223:61 */ + assign n2947_o = opc_opcode_q[7:5]; + /* decoder.vhd:1223:47 */ + assign n2948_o = {n2946_o, n2947_o}; + /* decoder.vhd:1222:13 */ + assign n2950_o = clk_mstate_i == 3'b001; + assign n2951_o = {n2950_o, n2944_o}; + /* decoder.vhd:1215:11 */ + always @* + case (n2951_o) + 2'b10: n2954_o = 1'b0; + 2'b01: n2954_o = 1'b1; + default: n2954_o = 1'b0; + endcase + /* decoder.vhd:1215:11 */ + always @* + case (n2951_o) + 2'b10: n2957_o = 1'b1; + 2'b01: n2957_o = 1'b0; + default: n2957_o = 1'b0; + endcase + /* decoder.vhd:1215:11 */ + always @* + case (n2951_o) + 2'b10: n2960_o = 1'b0; + 2'b01: n2960_o = 1'b1; + default: n2960_o = 1'b0; + endcase + /* decoder.vhd:1215:11 */ + always @* + case (n2951_o) + 2'b10: n2961_o = n2948_o; + 2'b01: n2961_o = n2034_o; + default: n2961_o = n2034_o; + endcase + /* decoder.vhd:1215:11 */ + always @* + case (n2951_o) + 2'b10: n2963_o = 1'b1; + 2'b01: n2963_o = n2038_o; + default: n2963_o = n2038_o; + endcase + /* decoder.vhd:1214:9 */ + assign n2965_o = clk_second_cycle_i ? n2954_o : 1'b0; + /* decoder.vhd:1214:9 */ + assign n2967_o = clk_second_cycle_i ? n2957_o : 1'b0; + /* decoder.vhd:1214:9 */ + assign n2969_o = clk_second_cycle_i ? n2960_o : 1'b0; + /* decoder.vhd:1214:9 */ + assign n2970_o = clk_second_cycle_i ? n2961_o : n2034_o; + /* decoder.vhd:1214:9 */ + assign n2971_o = clk_second_cycle_i ? n2963_o : n2038_o; + /* decoder.vhd:1211:7 */ + assign n2973_o = opc_mnemonic_s == 6'b011001; + /* decoder.vhd:1238:12 */ + assign n2974_o = ~clk_second_cycle_i; + /* decoder.vhd:1241:27 */ + assign n2976_o = clk_mstate_i == 3'b010; + /* decoder.vhd:1241:11 */ + assign n2979_o = n2976_o ? 1'b1 : 1'b0; + /* decoder.vhd:1241:11 */ + assign n2982_o = n2976_o ? 2'b01 : 2'b00; + /* decoder.vhd:1247:27 */ + assign n2984_o = clk_mstate_i == 3'b000; + /* decoder.vhd:1247:11 */ + assign n2987_o = n2984_o ? 1'b1 : 1'b0; + /* decoder.vhd:1247:11 */ + assign n2990_o = n2984_o ? 1'b1 : 1'b0; + /* decoder.vhd:1238:9 */ + assign n2992_o = n2974_o ? n2979_o : 1'b0; + /* decoder.vhd:1238:9 */ + assign n2994_o = n2974_o ? 1'b0 : n2987_o; + /* decoder.vhd:1238:9 */ + assign n2996_o = n2974_o ? n2982_o : 2'b00; + /* decoder.vhd:1238:9 */ + assign n2998_o = n2974_o ? 1'b0 : n2990_o; + /* decoder.vhd:1235:7 */ + assign n3000_o = opc_mnemonic_s == 6'b011010; + /* decoder.vhd:1260:12 */ + assign n3001_o = ~clk_second_cycle_i; + /* decoder.vhd:1262:27 */ + assign n3003_o = clk_mstate_i == 3'b010; + /* decoder.vhd:1262:11 */ + assign n3006_o = n3003_o ? 1'b1 : 1'b0; + /* decoder.vhd:1269:27 */ + assign n3008_o = clk_mstate_i == 3'b000; + /* decoder.vhd:1269:37 */ + assign n3009_o = cnd_take_branch_i & n3008_o; + /* decoder.vhd:1269:11 */ + assign n3015_o = n3009_o ? 1'b1 : 1'b0; + /* decoder.vhd:1269:11 */ + assign n3018_o = n3009_o ? 1'b1 : 1'b0; + /* decoder.vhd:1260:9 */ + assign n3020_o = n3001_o ? 1'b0 : n3015_o; + /* decoder.vhd:1260:9 */ + assign n3022_o = n3001_o ? n3006_o : 1'b0; + /* decoder.vhd:1260:9 */ + assign n3024_o = n3001_o ? 1'b0 : n3018_o; + /* decoder.vhd:1256:7 */ + assign n3026_o = opc_mnemonic_s == 6'b011011; + /* decoder.vhd:1280:12 */ + assign n3027_o = ~clk_second_cycle_i; + /* decoder.vhd:1282:27 */ + assign n3029_o = clk_mstate_i == 3'b010; + /* decoder.vhd:1282:11 */ + assign n3032_o = n3029_o ? 1'b1 : 1'b0; + /* decoder.vhd:1289:27 */ + assign n3034_o = clk_mstate_i == 3'b000; + /* decoder.vhd:1289:37 */ + assign n3035_o = cnd_take_branch_i & n3034_o; + /* decoder.vhd:1289:11 */ + assign n3041_o = n3035_o ? 1'b1 : 1'b0; + /* decoder.vhd:1289:11 */ + assign n3044_o = n3035_o ? 1'b1 : 1'b0; + /* decoder.vhd:1280:9 */ + assign n3046_o = n3027_o ? 1'b0 : n3041_o; + /* decoder.vhd:1280:9 */ + assign n3048_o = n3027_o ? n3032_o : 1'b0; + /* decoder.vhd:1280:9 */ + assign n3050_o = n3027_o ? 1'b0 : n3044_o; + /* decoder.vhd:1276:7 */ + assign n3052_o = opc_mnemonic_s == 6'b111100; + /* decoder.vhd:1300:12 */ + assign n3053_o = ~clk_second_cycle_i; + /* decoder.vhd:1302:27 */ + assign n3055_o = clk_mstate_i == 3'b010; + /* decoder.vhd:1302:11 */ + assign n3058_o = n3055_o ? 1'b1 : 1'b0; + /* decoder.vhd:1309:27 */ + assign n3060_o = clk_mstate_i == 3'b000; + /* decoder.vhd:1309:37 */ + assign n3061_o = cnd_take_branch_i & n3060_o; + /* decoder.vhd:1309:11 */ + assign n3067_o = n3061_o ? 1'b1 : 1'b0; + /* decoder.vhd:1309:11 */ + assign n3070_o = n3061_o ? 1'b1 : 1'b0; + /* decoder.vhd:1300:9 */ + assign n3072_o = n3053_o ? 1'b0 : n3067_o; + /* decoder.vhd:1300:9 */ + assign n3074_o = n3053_o ? n3058_o : 1'b0; + /* decoder.vhd:1300:9 */ + assign n3076_o = n3053_o ? 1'b0 : n3070_o; + /* decoder.vhd:1296:7 */ + assign n3078_o = opc_mnemonic_s == 6'b111101; + /* decoder.vhd:1318:24 */ + assign n3079_o = opc_opcode_q[6]; + /* decoder.vhd:1318:28 */ + assign n3080_o = ~n3079_o; + /* decoder.vhd:1318:9 */ + assign n3083_o = n3080_o ? 4'b0110 : 4'b0111; + /* decoder.vhd:1324:12 */ + assign n3084_o = ~clk_second_cycle_i; + /* decoder.vhd:1326:27 */ + assign n3086_o = clk_mstate_i == 3'b010; + /* decoder.vhd:1328:48 */ + assign n3087_o = opc_opcode_q[4]; + /* decoder.vhd:1326:11 */ + assign n3090_o = n3086_o ? 1'b1 : 1'b0; + assign n3091_o = opc_opcode_q[5]; + /* decoder.vhd:1324:9 */ + assign n3092_o = n3110_o ? n3087_o : n3091_o; + /* decoder.vhd:1334:27 */ + assign n3094_o = clk_mstate_i == 3'b000; + /* decoder.vhd:1334:37 */ + assign n3095_o = cnd_take_branch_i & n3094_o; + /* decoder.vhd:1334:11 */ + assign n3101_o = n3095_o ? 1'b1 : 1'b0; + /* decoder.vhd:1334:11 */ + assign n3104_o = n3095_o ? 1'b1 : 1'b0; + /* decoder.vhd:1324:9 */ + assign n3106_o = n3084_o ? 1'b0 : n3101_o; + /* decoder.vhd:1324:9 */ + assign n3108_o = n3084_o ? n3090_o : 1'b0; + /* decoder.vhd:1324:9 */ + assign n3110_o = n3084_o & n3086_o; + /* decoder.vhd:1324:9 */ + assign n3112_o = n3084_o ? 1'b0 : n3104_o; + /* decoder.vhd:1316:7 */ + assign n3114_o = opc_mnemonic_s == 6'b011100; + /* decoder.vhd:1345:12 */ + assign n3115_o = ~clk_second_cycle_i; + /* decoder.vhd:1347:27 */ + assign n3117_o = clk_mstate_i == 3'b010; + /* decoder.vhd:1347:11 */ + assign n3120_o = n3117_o ? 1'b1 : 1'b0; + /* decoder.vhd:1347:11 */ + assign n3123_o = n3117_o ? 1'b1 : 1'b0; + /* decoder.vhd:1355:27 */ + assign n3125_o = clk_mstate_i == 3'b000; + /* decoder.vhd:1355:37 */ + assign n3126_o = cnd_take_branch_i & n3125_o; + /* decoder.vhd:1355:11 */ + assign n3132_o = n3126_o ? 1'b1 : 1'b0; + /* decoder.vhd:1355:11 */ + assign n3135_o = n3126_o ? 1'b1 : 1'b0; + /* decoder.vhd:1345:9 */ + assign n3137_o = n3115_o ? 1'b0 : n3132_o; + /* decoder.vhd:1345:9 */ + assign n3139_o = n3115_o ? n3120_o : 1'b0; + /* decoder.vhd:1345:9 */ + assign n3141_o = n3115_o ? 1'b0 : n3135_o; + /* decoder.vhd:1345:9 */ + assign n3143_o = n3115_o ? n3123_o : 1'b0; + /* decoder.vhd:1341:7 */ + assign n3145_o = opc_mnemonic_s == 6'b011101; + /* decoder.vhd:1366:12 */ + assign n3146_o = ~clk_second_cycle_i; + /* decoder.vhd:1368:27 */ + assign n3148_o = clk_mstate_i == 3'b010; + /* decoder.vhd:1371:48 */ + assign n3149_o = opc_opcode_q[6]; + /* decoder.vhd:1368:11 */ + assign n3152_o = n3148_o ? 1'b1 : 1'b0; + /* decoder.vhd:1368:11 */ + assign n3155_o = n3148_o ? 1'b1 : 1'b0; + assign n3156_o = opc_opcode_q[5]; + /* decoder.vhd:1366:9 */ + assign n3157_o = n3177_o ? n3149_o : n3156_o; + /* decoder.vhd:1377:27 */ + assign n3159_o = clk_mstate_i == 3'b000; + /* decoder.vhd:1377:37 */ + assign n3160_o = cnd_take_branch_i & n3159_o; + /* decoder.vhd:1377:11 */ + assign n3166_o = n3160_o ? 1'b1 : 1'b0; + /* decoder.vhd:1377:11 */ + assign n3169_o = n3160_o ? 1'b1 : 1'b0; + /* decoder.vhd:1366:9 */ + assign n3171_o = n3146_o ? n3152_o : 1'b0; + /* decoder.vhd:1366:9 */ + assign n3173_o = n3146_o ? 1'b0 : n3166_o; + /* decoder.vhd:1366:9 */ + assign n3175_o = n3146_o ? n3155_o : 1'b0; + /* decoder.vhd:1366:9 */ + assign n3177_o = n3146_o & n3148_o; + /* decoder.vhd:1366:9 */ + assign n3179_o = n3146_o ? 1'b0 : n3169_o; + /* decoder.vhd:1362:7 */ + assign n3181_o = opc_mnemonic_s == 6'b011110; + /* decoder.vhd:1389:48 */ + assign n3183_o = clk_mstate_i == 3'b000; + /* decoder.vhd:1389:31 */ + assign n3184_o = n3183_o & clk_second_cycle_i; + /* decoder.vhd:1389:9 */ + assign n3187_o = n3184_o ? 1'b1 : 1'b0; + /* decoder.vhd:1384:7 */ + assign n3189_o = opc_mnemonic_s == 6'b011111; + /* decoder.vhd:1399:28 */ + assign n3190_o = opc_opcode_q[3]; + /* decoder.vhd:1399:32 */ + assign n3191_o = ~n3190_o; + /* decoder.vhd:1398:44 */ + assign n3193_o = 1'b0 | n3191_o; + /* decoder.vhd:1398:13 */ + assign n3200_o = n3193_o ? 1'b1 : n2030_o; + /* decoder.vhd:1398:13 */ + assign n3203_o = n3193_o ? 1'b1 : 1'b0; + /* decoder.vhd:1398:13 */ + assign n3206_o = n3193_o ? 2'b00 : 2'b01; + /* decoder.vhd:1397:11 */ + assign n3208_o = clk_mstate_i == 3'b010; + /* decoder.vhd:1404:11 */ + assign n3213_o = clk_mstate_i == 3'b011; + assign n3214_o = {n3213_o, n3208_o}; + /* decoder.vhd:1395:9 */ + always @* + case (n3214_o) + 2'b10: n3217_o = 1'b1; + 2'b01: n3217_o = 1'b0; + default: n3217_o = 1'b0; + endcase + /* decoder.vhd:1395:9 */ + always @* + case (n3214_o) + 2'b10: n3220_o = 1'b1; + 2'b01: n3220_o = 1'b0; + default: n3220_o = 1'b0; + endcase + /* decoder.vhd:1395:9 */ + always @* + case (n3214_o) + 2'b10: n3221_o = n2030_o; + 2'b01: n3221_o = n3200_o; + default: n3221_o = n2030_o; + endcase + /* decoder.vhd:1395:9 */ + always @* + case (n3214_o) + 2'b10: n3224_o = 1'b1; + 2'b01: n3224_o = n3203_o; + default: n3224_o = 1'b0; + endcase + /* decoder.vhd:1395:9 */ + always @* + case (n3214_o) + 2'b10: n3226_o = 2'b01; + 2'b01: n3226_o = n3206_o; + default: n3226_o = 2'b01; + endcase + /* decoder.vhd:1394:7 */ + assign n3228_o = opc_mnemonic_s == 6'b100001; + /* decoder.vhd:1415:25 */ + assign n3230_o = clk_mstate_i == 3'b010; + /* decoder.vhd:1415:9 */ + assign n3233_o = n3230_o ? 1'b1 : 1'b0; + /* decoder.vhd:1415:9 */ + assign n3236_o = n3230_o ? 1'b1 : 1'b0; + /* decoder.vhd:1415:9 */ + assign n3239_o = n3230_o ? 1'b1 : 1'b0; + /* decoder.vhd:1414:7 */ + assign n3241_o = opc_mnemonic_s == 6'b100000; + /* decoder.vhd:1423:25 */ + assign n3243_o = clk_mstate_i == 3'b010; + /* decoder.vhd:1423:9 */ + assign n3246_o = n3243_o ? 1'b1 : 1'b0; + /* decoder.vhd:1423:9 */ + assign n3249_o = n3243_o ? 1'b1 : 1'b0; + /* decoder.vhd:1423:9 */ + assign n3252_o = n3243_o ? 1'b1 : 1'b0; + /* decoder.vhd:1422:7 */ + assign n3254_o = opc_mnemonic_s == 6'b100010; + /* decoder.vhd:1435:28 */ + assign n3255_o = opc_opcode_q[3]; + /* decoder.vhd:1435:32 */ + assign n3256_o = ~n3255_o; + /* decoder.vhd:1434:44 */ + assign n3258_o = 1'b0 | n3256_o; + /* decoder.vhd:1434:13 */ + assign n3265_o = n3258_o ? 1'b1 : n2030_o; + /* decoder.vhd:1434:13 */ + assign n3268_o = n3258_o ? 1'b1 : 1'b0; + /* decoder.vhd:1434:13 */ + assign n3271_o = n3258_o ? 2'b00 : 2'b01; + /* decoder.vhd:1433:11 */ + assign n3273_o = clk_mstate_i == 3'b010; + /* decoder.vhd:1440:11 */ + assign n3275_o = clk_mstate_i == 3'b100; + assign n3276_o = {n3275_o, n3273_o}; + /* decoder.vhd:1431:9 */ + always @* + case (n3276_o) + 2'b10: n3279_o = 1'b1; + 2'b01: n3279_o = 1'b0; + default: n3279_o = 1'b0; + endcase + /* decoder.vhd:1431:9 */ + always @* + case (n3276_o) + 2'b10: n3280_o = n2030_o; + 2'b01: n3280_o = n3265_o; + default: n3280_o = n2030_o; + endcase + /* decoder.vhd:1431:9 */ + always @* + case (n3276_o) + 2'b10: n3282_o = 1'b0; + 2'b01: n3282_o = n3268_o; + default: n3282_o = 1'b0; + endcase + /* decoder.vhd:1431:9 */ + always @* + case (n3276_o) + 2'b10: n3284_o = 2'b01; + 2'b01: n3284_o = n3271_o; + default: n3284_o = 2'b01; + endcase + /* decoder.vhd:1431:9 */ + always @* + case (n3276_o) + 2'b10: n3287_o = 1'b1; + 2'b01: n3287_o = 1'b0; + default: n3287_o = 1'b0; + endcase + /* decoder.vhd:1430:7 */ + assign n3289_o = opc_mnemonic_s == 6'b100011; + /* decoder.vhd:1454:12 */ + assign n3290_o = ~clk_second_cycle_i; + /* decoder.vhd:1454:52 */ + assign n3292_o = clk_mstate_i == 3'b010; + /* decoder.vhd:1454:35 */ + assign n3293_o = n3292_o & n3290_o; + /* decoder.vhd:1456:26 */ + assign n3294_o = opc_opcode_q[3]; + /* decoder.vhd:1456:30 */ + assign n3295_o = ~n3294_o; + /* decoder.vhd:1455:42 */ + assign n3297_o = 1'b0 | n3295_o; + /* decoder.vhd:1454:9 */ + assign n3304_o = n3311_o ? 1'b1 : n2030_o; + /* decoder.vhd:1455:11 */ + assign n3307_o = n3297_o ? 1'b1 : 1'b0; + /* decoder.vhd:1455:11 */ + assign n3310_o = n3297_o ? 2'b00 : 2'b01; + /* decoder.vhd:1454:9 */ + assign n3311_o = n3293_o & n3297_o; + /* decoder.vhd:1454:9 */ + assign n3313_o = n3293_o ? n3307_o : 1'b0; + /* decoder.vhd:1454:9 */ + assign n3315_o = n3293_o ? n3310_o : 2'b01; + /* decoder.vhd:1463:48 */ + assign n3317_o = clk_mstate_i == 3'b000; + /* decoder.vhd:1463:31 */ + assign n3318_o = n3317_o & clk_second_cycle_i; + /* decoder.vhd:1463:9 */ + assign n3321_o = n3318_o ? 1'b1 : 1'b0; + /* decoder.vhd:1450:7 */ + assign n3323_o = opc_mnemonic_s == 6'b100100; + /* decoder.vhd:1470:25 */ + assign n3325_o = clk_mstate_i == 3'b011; + /* decoder.vhd:1470:9 */ + assign n3328_o = n3325_o ? 1'b1 : 1'b0; + /* decoder.vhd:1470:9 */ + assign n3331_o = n3325_o ? 1'b1 : 1'b0; + /* decoder.vhd:1468:7 */ + assign n3333_o = opc_mnemonic_s == 6'b111111; + /* decoder.vhd:1478:25 */ + assign n3335_o = clk_mstate_i == 3'b010; + /* decoder.vhd:1479:26 */ + assign n3336_o = opc_opcode_q[5]; + /* decoder.vhd:1479:11 */ + assign n3339_o = n3336_o ? 1'b0 : 1'b1; + /* decoder.vhd:1479:11 */ + assign n3342_o = n3336_o ? 1'b1 : 1'b0; + /* decoder.vhd:1479:11 */ + assign n3345_o = n3336_o ? 1'b0 : 1'b1; + /* decoder.vhd:1479:11 */ + assign n3348_o = n3336_o ? 1'b1 : 1'b0; + /* decoder.vhd:1478:9 */ + assign n3350_o = n3335_o ? n3339_o : 1'b0; + /* decoder.vhd:1478:9 */ + assign n3352_o = n3335_o ? n3342_o : 1'b0; + /* decoder.vhd:1478:9 */ + assign n3354_o = n3335_o ? n3345_o : 1'b0; + /* decoder.vhd:1478:9 */ + assign n3356_o = n3335_o ? n3348_o : 1'b0; + /* decoder.vhd:1477:7 */ + assign n3358_o = opc_mnemonic_s == 6'b100101; + /* decoder.vhd:1492:12 */ + assign n3359_o = ~clk_second_cycle_i; + /* decoder.vhd:1498:53 */ + assign n3361_o = opc_opcode_q[1:0]; + /* decoder.vhd:1500:32 */ + assign n3362_o = opc_opcode_q[7:4]; + /* decoder.vhd:1501:17 */ + assign n3365_o = n3362_o == 4'b1001; + /* decoder.vhd:1503:17 */ + assign n3368_o = n3362_o == 4'b1000; + /* decoder.vhd:1505:17 */ + assign n3371_o = n3362_o == 4'b0011; + assign n3372_o = {n3371_o, n3368_o, n3365_o}; + assign n3373_o = n2032_o[3:2]; + assign n3374_o = n2033_o[3:2]; + /* decoder.vhd:622:5 */ + assign n3375_o = n2019_o ? n3373_o : n3374_o; + /* decoder.vhd:1500:15 */ + always @* + case (n3372_o) + 3'b100: n3376_o = 2'b01; + 3'b010: n3376_o = 2'b10; + 3'b001: n3376_o = 2'b11; + default: n3376_o = n3375_o; + endcase + /* decoder.vhd:1495:13 */ + assign n3378_o = clk_mstate_i == 3'b010; + /* decoder.vhd:1516:13 */ + assign n3380_o = clk_mstate_i == 3'b011; + /* decoder.vhd:1522:13 */ + assign n3382_o = clk_mstate_i == 3'b100; + assign n3383_o = {n3382_o, n3380_o, n3378_o}; + /* decoder.vhd:1493:11 */ + always @* + case (n3383_o) + 3'b100: n3386_o = 1'b0; + 3'b010: n3386_o = 1'b1; + 3'b001: n3386_o = 1'b0; + default: n3386_o = 1'b0; + endcase + /* decoder.vhd:1493:11 */ + always @* + case (n3383_o) + 3'b100: n3390_o = 1'b0; + 3'b010: n3390_o = 1'b1; + 3'b001: n3390_o = 1'b1; + default: n3390_o = 1'b0; + endcase + assign n3391_o = n2032_o[1:0]; + assign n3392_o = n2033_o[1:0]; + /* decoder.vhd:622:5 */ + assign n3393_o = n2019_o ? n3391_o : n3392_o; + /* decoder.vhd:1493:11 */ + always @* + case (n3383_o) + 3'b100: n3394_o = n3393_o; + 3'b010: n3394_o = n3393_o; + 3'b001: n3394_o = n3361_o; + default: n3394_o = n3393_o; + endcase + assign n3395_o = n2032_o[3:2]; + assign n3396_o = n2033_o[3:2]; + /* decoder.vhd:622:5 */ + assign n3397_o = n2019_o ? n3395_o : n3396_o; + /* decoder.vhd:1493:11 */ + always @* + case (n3383_o) + 3'b100: n3398_o = n3397_o; + 3'b010: n3398_o = n3397_o; + 3'b001: n3398_o = n3376_o; + default: n3398_o = n3397_o; + endcase + assign n3399_o = n2032_o[7:4]; + assign n3400_o = n2033_o[7:4]; + /* decoder.vhd:622:5 */ + assign n3401_o = n2019_o ? n3399_o : n3400_o; + /* decoder.vhd:1493:11 */ + always @* + case (n3383_o) + 3'b100: n3402_o = n3401_o; + 3'b010: n3402_o = n3401_o; + 3'b001: n3402_o = 4'b0000; + default: n3402_o = n3401_o; + endcase + /* decoder.vhd:1493:11 */ + always @* + case (n3383_o) + 3'b100: n3404_o = n2038_o; + 3'b010: n3404_o = n2038_o; + 3'b001: n3404_o = 1'b1; + default: n3404_o = n2038_o; + endcase + /* decoder.vhd:1493:11 */ + always @* + case (n3383_o) + 3'b100: n3408_o = 1'b1; + 3'b010: n3408_o = 1'b1; + 3'b001: n3408_o = 1'b0; + default: n3408_o = 1'b0; + endcase + /* decoder.vhd:1532:27 */ + assign n3410_o = clk_mstate_i == 3'b000; + /* decoder.vhd:1532:53 */ + assign n3412_o = clk_mstate_i == 3'b001; + /* decoder.vhd:1532:37 */ + assign n3413_o = n3410_o | n3412_o; + /* decoder.vhd:1532:11 */ + assign n3416_o = n3413_o ? 1'b1 : 1'b0; + /* decoder.vhd:1492:9 */ + assign n3418_o = n3359_o ? n3386_o : 1'b0; + /* decoder.vhd:1492:9 */ + assign n3420_o = n3359_o ? n3390_o : 1'b0; + assign n3421_o = {n3402_o, n3398_o, n3394_o}; + /* decoder.vhd:1492:9 */ + assign n3422_o = n3359_o ? n3421_o : n2034_o; + /* decoder.vhd:1492:9 */ + assign n3423_o = n3359_o ? n3404_o : n2038_o; + /* decoder.vhd:1492:9 */ + assign n3424_o = n3359_o ? n3408_o : n3416_o; + /* decoder.vhd:1489:7 */ + assign n3426_o = opc_mnemonic_s == 6'b101101; + /* decoder.vhd:1542:12 */ + assign n3427_o = ~clk_second_cycle_i; + /* decoder.vhd:1548:53 */ + assign n3428_o = opc_opcode_q[1:0]; + /* decoder.vhd:1547:48 */ + assign n3430_o = {6'b000000, n3428_o}; + /* decoder.vhd:1545:13 */ + assign n3432_o = clk_mstate_i == 3'b010; + /* decoder.vhd:1554:13 */ + assign n3435_o = clk_mstate_i == 3'b011; + /* decoder.vhd:1561:13 */ + assign n3437_o = clk_mstate_i == 3'b100; + assign n3438_o = {n3437_o, n3435_o, n3432_o}; + /* decoder.vhd:1543:11 */ + always @* + case (n3438_o) + 3'b100: n3442_o = 1'b0; + 3'b010: n3442_o = 1'b1; + 3'b001: n3442_o = 1'b1; + default: n3442_o = 1'b0; + endcase + assign n3443_o = n3430_o[3:0]; + assign n3444_o = n2032_o[3:0]; + assign n3445_o = n2033_o[3:0]; + /* decoder.vhd:622:5 */ + assign n3446_o = n2019_o ? n3444_o : n3445_o; + /* decoder.vhd:1543:11 */ + always @* + case (n3438_o) + 3'b100: n3447_o = n3446_o; + 3'b010: n3447_o = 4'b1111; + 3'b001: n3447_o = n3443_o; + default: n3447_o = n3446_o; + endcase + assign n3448_o = n3430_o[7:4]; + assign n3449_o = n2032_o[7:4]; + assign n3450_o = n2033_o[7:4]; + /* decoder.vhd:622:5 */ + assign n3451_o = n2019_o ? n3449_o : n3450_o; + /* decoder.vhd:1543:11 */ + always @* + case (n3438_o) + 3'b100: n3452_o = n3451_o; + 3'b010: n3452_o = n3451_o; + 3'b001: n3452_o = n3448_o; + default: n3452_o = n3451_o; + endcase + /* decoder.vhd:1543:11 */ + always @* + case (n3438_o) + 3'b100: n3455_o = n2038_o; + 3'b010: n3455_o = 1'b1; + 3'b001: n3455_o = 1'b1; + default: n3455_o = n2038_o; + endcase + /* decoder.vhd:1543:11 */ + always @* + case (n3438_o) + 3'b100: n3459_o = 1'b1; + 3'b010: n3459_o = 1'b1; + 3'b001: n3459_o = 1'b0; + default: n3459_o = 1'b0; + endcase + /* decoder.vhd:1572:13 */ + assign n3461_o = clk_mstate_i == 3'b000; + /* decoder.vhd:1577:13 */ + assign n3463_o = clk_mstate_i == 3'b001; + assign n3464_o = {n3463_o, n3461_o}; + /* decoder.vhd:1570:11 */ + always @* + case (n3464_o) + 2'b10: n3467_o = 1'b1; + 2'b01: n3467_o = 1'b0; + default: n3467_o = 1'b0; + endcase + /* decoder.vhd:1570:11 */ + always @* + case (n3464_o) + 2'b10: n3470_o = 1'b1; + 2'b01: n3470_o = 1'b0; + default: n3470_o = 1'b0; + endcase + /* decoder.vhd:1570:11 */ + always @* + case (n3464_o) + 2'b10: n3473_o = 1'b1; + 2'b01: n3473_o = 1'b0; + default: n3473_o = 1'b0; + endcase + /* decoder.vhd:1570:11 */ + always @* + case (n3464_o) + 2'b10: n3477_o = 1'b1; + 2'b01: n3477_o = 1'b1; + default: n3477_o = 1'b0; + endcase + /* decoder.vhd:1542:9 */ + assign n3479_o = n3427_o ? 1'b0 : n3467_o; + /* decoder.vhd:1542:9 */ + assign n3481_o = n3427_o ? n3442_o : 1'b0; + /* decoder.vhd:1542:9 */ + assign n3483_o = n3427_o ? 1'b0 : n3470_o; + /* decoder.vhd:1542:9 */ + assign n3485_o = n3427_o ? 1'b0 : n3473_o; + assign n3486_o = {n3452_o, n3447_o}; + /* decoder.vhd:1542:9 */ + assign n3487_o = n3427_o ? n3486_o : n2034_o; + /* decoder.vhd:1542:9 */ + assign n3488_o = n3427_o ? n3455_o : n2038_o; + /* decoder.vhd:1542:9 */ + assign n3489_o = n3427_o ? n3459_o : n3477_o; + /* decoder.vhd:1539:7 */ + assign n3491_o = opc_mnemonic_s == 6'b100110; + /* decoder.vhd:1594:12 */ + assign n3492_o = ~clk_second_cycle_i; + /* decoder.vhd:1597:27 */ + assign n3494_o = clk_mstate_i == 3'b010; + /* decoder.vhd:1599:28 */ + assign n3495_o = opc_opcode_q[6]; + /* decoder.vhd:1599:32 */ + assign n3496_o = ~n3495_o; + /* decoder.vhd:1599:13 */ + assign n3499_o = n3496_o ? 2'b01 : 2'b10; + /* decoder.vhd:1597:11 */ + assign n3502_o = n3494_o ? 1'b1 : 1'b0; + /* decoder.vhd:1597:11 */ + assign n3504_o = n3494_o ? n3499_o : 2'b00; + /* decoder.vhd:1607:27 */ + assign n3506_o = clk_mstate_i == 3'b000; + /* decoder.vhd:1607:11 */ + assign n3509_o = n3506_o ? 1'b1 : 1'b0; + /* decoder.vhd:1607:11 */ + assign n3512_o = n3506_o ? 1'b1 : 1'b0; + /* decoder.vhd:1594:9 */ + assign n3514_o = n3492_o ? 1'b0 : n3509_o; + /* decoder.vhd:1594:9 */ + assign n3516_o = n3492_o ? n3502_o : 1'b0; + /* decoder.vhd:1594:9 */ + assign n3518_o = n3492_o ? n3504_o : 2'b00; + /* decoder.vhd:1594:9 */ + assign n3520_o = n3492_o ? 1'b0 : n3512_o; + /* decoder.vhd:1591:7 */ + assign n3522_o = opc_mnemonic_s == 6'b100111; + /* decoder.vhd:1621:24 */ + assign n3523_o = opc_opcode_q[4]; + /* decoder.vhd:1621:28 */ + assign n3524_o = ~n3523_o; + /* decoder.vhd:1621:9 */ + assign n3527_o = n3524_o ? 1'b1 : 1'b0; + /* decoder.vhd:1621:9 */ + assign n3530_o = n3524_o ? 1'b0 : 1'b1; + /* decoder.vhd:1627:12 */ + assign n3531_o = ~clk_second_cycle_i; + /* decoder.vhd:1631:13 */ + assign n3533_o = clk_mstate_i == 3'b010; + /* decoder.vhd:1637:30 */ + assign n3534_o = opc_opcode_q[4]; + /* decoder.vhd:1637:15 */ + assign n3537_o = n3534_o ? 1'b1 : 1'b0; + /* decoder.vhd:1637:15 */ + assign n3540_o = n3534_o ? 1'b1 : 1'b0; + /* decoder.vhd:1636:13 */ + assign n3542_o = clk_mstate_i == 3'b100; + assign n3543_o = {n3542_o, n3533_o}; + /* decoder.vhd:1629:11 */ + always @* + case (n3543_o) + 2'b10: n3545_o = n3537_o; + 2'b01: n3545_o = 1'b0; + default: n3545_o = 1'b0; + endcase + /* decoder.vhd:1629:11 */ + always @* + case (n3543_o) + 2'b10: n3548_o = n3540_o; + 2'b01: n3548_o = 1'b1; + default: n3548_o = 1'b0; + endcase + /* decoder.vhd:1629:11 */ + always @* + case (n3543_o) + 2'b10: n3551_o = 1'b0; + 2'b01: n3551_o = 1'b1; + default: n3551_o = 1'b0; + endcase + /* decoder.vhd:1647:27 */ + assign n3553_o = clk_mstate_i == 3'b001; + /* decoder.vhd:1648:28 */ + assign n3554_o = opc_opcode_q[4]; + /* decoder.vhd:1648:32 */ + assign n3555_o = ~n3554_o; + /* decoder.vhd:1648:13 */ + assign n3558_o = n3555_o ? 1'b1 : 1'b0; + /* decoder.vhd:1648:13 */ + assign n3561_o = n3555_o ? 1'b0 : 1'b1; + /* decoder.vhd:1648:13 */ + assign n3564_o = n3555_o ? 1'b0 : 1'b1; + /* decoder.vhd:1648:13 */ + assign n3567_o = n3555_o ? 1'b1 : 1'b0; + /* decoder.vhd:1647:11 */ + assign n3569_o = n3553_o ? n3558_o : 1'b0; + /* decoder.vhd:1647:11 */ + assign n3571_o = n3553_o ? n3561_o : 1'b0; + /* decoder.vhd:1647:11 */ + assign n3573_o = n3553_o ? n3564_o : 1'b0; + /* decoder.vhd:1647:11 */ + assign n3575_o = n3553_o ? n3567_o : 1'b0; + /* decoder.vhd:1627:9 */ + assign n3577_o = n3531_o ? 1'b0 : n3569_o; + /* decoder.vhd:1627:9 */ + assign n3578_o = n3531_o ? n3545_o : n3571_o; + /* decoder.vhd:1627:9 */ + assign n3579_o = n3531_o ? n3548_o : n3573_o; + /* decoder.vhd:1627:9 */ + assign n3581_o = n3531_o ? n3551_o : 1'b0; + /* decoder.vhd:1627:9 */ + assign n3583_o = n3531_o ? 1'b0 : n3575_o; + /* decoder.vhd:1627:9 */ + assign n3586_o = n3531_o ? 1'b1 : 1'b0; + /* decoder.vhd:1618:7 */ + assign n3588_o = opc_mnemonic_s == 6'b101000; + /* decoder.vhd:1663:7 */ + assign n3590_o = opc_mnemonic_s == 6'b101001; + /* decoder.vhd:1672:28 */ + assign n3591_o = opc_opcode_q[3]; + /* decoder.vhd:1672:32 */ + assign n3592_o = ~n3591_o; + /* decoder.vhd:1671:44 */ + assign n3594_o = 1'b0 | n3592_o; + /* decoder.vhd:1671:13 */ + assign n3601_o = n3594_o ? 1'b1 : n2030_o; + /* decoder.vhd:1671:13 */ + assign n3604_o = n3594_o ? 1'b1 : 1'b0; + /* decoder.vhd:1671:13 */ + assign n3607_o = n3594_o ? 2'b00 : 2'b01; + /* decoder.vhd:1670:11 */ + assign n3609_o = clk_mstate_i == 3'b010; + /* decoder.vhd:1677:11 */ + assign n3614_o = clk_mstate_i == 3'b011; + /* decoder.vhd:1681:11 */ + assign n3619_o = clk_mstate_i == 3'b100; + assign n3620_o = {n3619_o, n3614_o, n3609_o}; + /* decoder.vhd:1668:9 */ + always @* + case (n3620_o) + 3'b100: n3623_o = 1'b1; + 3'b010: n3623_o = 1'b0; + 3'b001: n3623_o = 1'b0; + default: n3623_o = 1'b0; + endcase + /* decoder.vhd:1668:9 */ + always @* + case (n3620_o) + 3'b100: n3626_o = 1'b0; + 3'b010: n3626_o = 1'b1; + 3'b001: n3626_o = 1'b0; + default: n3626_o = 1'b0; + endcase + /* decoder.vhd:1668:9 */ + always @* + case (n3620_o) + 3'b100: n3629_o = 1'b1; + 3'b010: n3629_o = 1'b0; + 3'b001: n3629_o = 1'b0; + default: n3629_o = 1'b0; + endcase + /* decoder.vhd:1668:9 */ + always @* + case (n3620_o) + 3'b100: n3630_o = n2030_o; + 3'b010: n3630_o = n2030_o; + 3'b001: n3630_o = n3601_o; + default: n3630_o = n2030_o; + endcase + /* decoder.vhd:1668:9 */ + always @* + case (n3620_o) + 3'b100: n3633_o = 1'b0; + 3'b010: n3633_o = 1'b1; + 3'b001: n3633_o = n3604_o; + default: n3633_o = 1'b0; + endcase + /* decoder.vhd:1668:9 */ + always @* + case (n3620_o) + 3'b100: n3636_o = 4'b0001; + 3'b010: n3636_o = 4'b1100; + 3'b001: n3636_o = 4'b1100; + default: n3636_o = 4'b1100; + endcase + /* decoder.vhd:1668:9 */ + always @* + case (n3620_o) + 3'b100: n3638_o = 2'b01; + 3'b010: n3638_o = 2'b01; + 3'b001: n3638_o = n3607_o; + default: n3638_o = 2'b01; + endcase + /* decoder.vhd:1667:7 */ + assign n3640_o = opc_mnemonic_s == 6'b101010; + /* decoder.vhd:1696:13 */ + assign n3642_o = clk_mstate_i == 3'b000; + /* decoder.vhd:1700:13 */ + assign n3647_o = clk_mstate_i == 3'b010; + assign n3648_o = {n3647_o, n3642_o}; + /* decoder.vhd:1694:11 */ + always @* + case (n3648_o) + 2'b10: n3651_o = 1'b1; + 2'b01: n3651_o = 1'b0; + default: n3651_o = 1'b0; + endcase + /* decoder.vhd:1694:11 */ + always @* + case (n3648_o) + 2'b10: n3654_o = 1'b0; + 2'b01: n3654_o = 1'b1; + default: n3654_o = 1'b0; + endcase + /* decoder.vhd:1694:11 */ + always @* + case (n3648_o) + 2'b10: n3657_o = 1'b1; + 2'b01: n3657_o = 1'b0; + default: n3657_o = 1'b0; + endcase + /* decoder.vhd:1694:11 */ + always @* + case (n3648_o) + 2'b10: n3660_o = 4'b0001; + 2'b01: n3660_o = 4'b1100; + default: n3660_o = 4'b1100; + endcase + /* decoder.vhd:1693:9 */ + assign n3662_o = clk_second_cycle_i ? n3651_o : 1'b0; + /* decoder.vhd:1693:9 */ + assign n3664_o = clk_second_cycle_i ? n3654_o : 1'b0; + /* decoder.vhd:1693:9 */ + assign n3666_o = clk_second_cycle_i ? n3657_o : 1'b0; + /* decoder.vhd:1693:9 */ + assign n3668_o = clk_second_cycle_i ? n3660_o : 4'b1100; + /* decoder.vhd:1690:7 */ + assign n3670_o = opc_mnemonic_s == 6'b101011; + /* decoder.vhd:1714:12 */ + assign n3671_o = ~clk_second_cycle_i; + /* decoder.vhd:1716:27 */ + assign n3673_o = clk_mstate_i == 3'b100; + /* decoder.vhd:1717:28 */ + assign n3674_o = opc_opcode_q[1:0]; + /* decoder.vhd:1717:41 */ + assign n3676_o = n3674_o == 2'b00; + /* decoder.vhd:1719:31 */ + assign n3677_o = opc_opcode_q[1]; + /* decoder.vhd:1719:35 */ + assign n3678_o = ~n3677_o; + /* decoder.vhd:1719:13 */ + assign n3681_o = n3678_o ? 1'b1 : 1'b0; + /* decoder.vhd:1719:13 */ + assign n3684_o = n3678_o ? 1'b0 : 1'b1; + /* decoder.vhd:1719:13 */ + assign n3687_o = n3678_o ? 1'b1 : 1'b0; + /* decoder.vhd:1719:13 */ + assign n3690_o = n3678_o ? 1'b0 : 1'b1; + /* decoder.vhd:1717:13 */ + assign n3692_o = n3676_o ? 1'b0 : n3681_o; + /* decoder.vhd:1717:13 */ + assign n3694_o = n3676_o ? 1'b0 : n3684_o; + /* decoder.vhd:1717:13 */ + assign n3696_o = n3676_o ? 1'b0 : n3687_o; + /* decoder.vhd:1717:13 */ + assign n3698_o = n3676_o ? 1'b0 : n3690_o; + /* decoder.vhd:1717:13 */ + assign n3701_o = n3676_o ? 1'b1 : 1'b0; + /* decoder.vhd:1716:11 */ + assign n3704_o = n3673_o ? 1'b1 : 1'b0; + /* decoder.vhd:1716:11 */ + assign n3706_o = n3673_o ? n3692_o : 1'b0; + /* decoder.vhd:1716:11 */ + assign n3708_o = n3673_o ? n3694_o : 1'b0; + /* decoder.vhd:1716:11 */ + assign n3710_o = n3673_o ? n3696_o : 1'b0; + /* decoder.vhd:1716:11 */ + assign n3712_o = n3673_o ? n3698_o : 1'b0; + /* decoder.vhd:1716:11 */ + assign n3714_o = n3673_o ? n3701_o : 1'b0; + /* decoder.vhd:1734:13 */ + assign n3716_o = clk_mstate_i == 3'b000; + /* decoder.vhd:1739:13 */ + assign n3718_o = clk_mstate_i == 3'b001; + /* decoder.vhd:1748:30 */ + assign n3719_o = opc_opcode_q[1:0]; + /* decoder.vhd:1748:43 */ + assign n3721_o = n3719_o == 2'b00; + /* decoder.vhd:1750:33 */ + assign n3722_o = opc_opcode_q[1]; + /* decoder.vhd:1750:37 */ + assign n3723_o = ~n3722_o; + /* decoder.vhd:1750:15 */ + assign n3726_o = n3723_o ? 1'b1 : 1'b0; + /* decoder.vhd:1750:15 */ + assign n3729_o = n3723_o ? 1'b0 : 1'b1; + /* decoder.vhd:1748:15 */ + assign n3732_o = n3721_o ? 1'b1 : 1'b0; + /* decoder.vhd:1748:15 */ + assign n3734_o = n3721_o ? 1'b0 : n3726_o; + /* decoder.vhd:1748:15 */ + assign n3736_o = n3721_o ? 1'b0 : n3729_o; + /* decoder.vhd:1744:13 */ + assign n3738_o = clk_mstate_i == 3'b010; + assign n3739_o = {n3738_o, n3718_o, n3716_o}; + /* decoder.vhd:1731:11 */ + always @* + case (n3739_o) + 3'b100: n3743_o = 1'b0; + 3'b010: n3743_o = 1'b1; + 3'b001: n3743_o = 1'b1; + default: n3743_o = 1'b0; + endcase + /* decoder.vhd:1731:11 */ + always @* + case (n3739_o) + 3'b100: n3747_o = 1'b1; + 3'b010: n3747_o = 1'b1; + 3'b001: n3747_o = 1'b0; + default: n3747_o = 1'b0; + endcase + /* decoder.vhd:1731:11 */ + always @* + case (n3739_o) + 3'b100: n3749_o = n3732_o; + 3'b010: n3749_o = 1'b0; + 3'b001: n3749_o = 1'b0; + default: n3749_o = 1'b0; + endcase + /* decoder.vhd:1731:11 */ + always @* + case (n3739_o) + 3'b100: n3751_o = n3734_o; + 3'b010: n3751_o = 1'b0; + 3'b001: n3751_o = 1'b0; + default: n3751_o = 1'b0; + endcase + /* decoder.vhd:1731:11 */ + always @* + case (n3739_o) + 3'b100: n3753_o = n3736_o; + 3'b010: n3753_o = 1'b0; + 3'b001: n3753_o = 1'b0; + default: n3753_o = 1'b0; + endcase + /* decoder.vhd:1731:11 */ + always @* + case (n3739_o) + 3'b100: n3756_o = 4'b0001; + 3'b010: n3756_o = 4'b1100; + 3'b001: n3756_o = 4'b1100; + default: n3756_o = 4'b1100; + endcase + /* decoder.vhd:1714:9 */ + assign n3758_o = n3671_o ? 1'b0 : n3743_o; + /* decoder.vhd:1714:9 */ + assign n3760_o = n3671_o ? n3704_o : 1'b0; + /* decoder.vhd:1714:9 */ + assign n3762_o = n3671_o ? 1'b0 : n3747_o; + /* decoder.vhd:1714:9 */ + assign n3764_o = n3671_o ? 1'b0 : n3749_o; + /* decoder.vhd:1714:9 */ + assign n3766_o = n3671_o ? 1'b0 : n3751_o; + /* decoder.vhd:1714:9 */ + assign n3768_o = n3671_o ? n3706_o : 1'b0; + /* decoder.vhd:1714:9 */ + assign n3770_o = n3671_o ? 1'b0 : n3753_o; + /* decoder.vhd:1714:9 */ + assign n3772_o = n3671_o ? n3708_o : 1'b0; + /* decoder.vhd:1714:9 */ + assign n3774_o = n3671_o ? 4'b1100 : n3756_o; + /* decoder.vhd:1714:9 */ + assign n3776_o = n3671_o ? n3710_o : 1'b0; + /* decoder.vhd:1714:9 */ + assign n3778_o = n3671_o ? n3712_o : 1'b0; + /* decoder.vhd:1714:9 */ + assign n3780_o = n3671_o ? n3714_o : 1'b0; + /* decoder.vhd:1711:7 */ + assign n3782_o = opc_mnemonic_s == 6'b101100; + /* decoder.vhd:1766:25 */ + assign n3784_o = clk_mstate_i == 3'b011; + /* decoder.vhd:1766:9 */ + assign n3787_o = n3784_o ? 1'b1 : 1'b0; + /* decoder.vhd:1766:9 */ + assign n3790_o = n3784_o ? 1'b1 : 1'b0; + /* decoder.vhd:1764:7 */ + assign n3792_o = opc_mnemonic_s == 6'b111011; + /* decoder.vhd:1774:24 */ + assign n3793_o = opc_opcode_q[4]; + /* decoder.vhd:1774:28 */ + assign n3794_o = ~n3793_o; + /* decoder.vhd:1774:9 */ + assign n3797_o = n3794_o ? 1'b1 : 1'b0; + /* decoder.vhd:1779:12 */ + assign n3798_o = ~clk_second_cycle_i; + /* decoder.vhd:1779:52 */ + assign n3800_o = clk_mstate_i == 3'b011; + /* decoder.vhd:1779:35 */ + assign n3801_o = n3800_o & n3798_o; + /* decoder.vhd:1782:26 */ + assign n3802_o = opc_opcode_q[4]; + /* decoder.vhd:1783:28 */ + assign n3803_o = opc_opcode_q[1]; + /* decoder.vhd:1783:32 */ + assign n3804_o = ~n3803_o; + /* decoder.vhd:1783:13 */ + assign n3807_o = n3804_o ? 1'b1 : 1'b0; + /* decoder.vhd:1783:13 */ + assign n3810_o = n3804_o ? 1'b0 : 1'b1; + /* decoder.vhd:1782:11 */ + assign n3813_o = n3802_o ? 1'b0 : 1'b1; + /* decoder.vhd:1782:11 */ + assign n3815_o = n3802_o ? n3807_o : 1'b0; + /* decoder.vhd:1782:11 */ + assign n3817_o = n3802_o ? n3810_o : 1'b0; + /* decoder.vhd:1779:9 */ + assign n3820_o = n3801_o ? 1'b1 : 1'b0; + /* decoder.vhd:1779:9 */ + assign n3822_o = n3801_o ? n3813_o : 1'b0; + /* decoder.vhd:1779:9 */ + assign n3824_o = n3801_o ? n3815_o : 1'b0; + /* decoder.vhd:1779:9 */ + assign n3826_o = n3801_o ? n3817_o : 1'b0; + /* decoder.vhd:1773:7 */ + assign n3828_o = opc_mnemonic_s == 6'b101110; + /* decoder.vhd:1798:12 */ + assign n3829_o = ~clk_second_cycle_i; + /* decoder.vhd:1801:13 */ + assign n3831_o = clk_mstate_i == 3'b010; + /* decoder.vhd:1805:13 */ + assign n3833_o = clk_mstate_i == 3'b011; + /* decoder.vhd:1812:13 */ + assign n3835_o = clk_mstate_i == 3'b100; + assign n3836_o = {n3835_o, n3833_o, n3831_o}; + /* decoder.vhd:1799:11 */ + always @* + case (n3836_o) + 3'b100: n3839_o = 1'b1; + 3'b010: n3839_o = 1'b1; + 3'b001: n3839_o = n2030_o; + default: n3839_o = n2030_o; + endcase + /* decoder.vhd:1799:11 */ + always @* + case (n3836_o) + 3'b100: n3842_o = 1'b1; + 3'b010: n3842_o = 1'b0; + 3'b001: n3842_o = 1'b0; + default: n3842_o = 1'b0; + endcase + /* decoder.vhd:1799:11 */ + always @* + case (n3836_o) + 3'b100: n3845_o = 1'b1; + 3'b010: n3845_o = 1'b0; + 3'b001: n3845_o = 1'b0; + default: n3845_o = 1'b0; + endcase + /* decoder.vhd:1799:11 */ + always @* + case (n3836_o) + 3'b100: n3848_o = 1'b0; + 3'b010: n3848_o = 1'b1; + 3'b001: n3848_o = 1'b0; + default: n3848_o = 1'b0; + endcase + /* decoder.vhd:1799:11 */ + always @* + case (n3836_o) + 3'b100: n3852_o = 2'b11; + 3'b010: n3852_o = 2'b10; + 3'b001: n3852_o = 2'b01; + default: n3852_o = 2'b01; + endcase + /* decoder.vhd:1799:11 */ + always @* + case (n3836_o) + 3'b100: n3855_o = 1'b0; + 3'b010: n3855_o = 1'b0; + 3'b001: n3855_o = 1'b1; + default: n3855_o = 1'b0; + endcase + /* decoder.vhd:1829:30 */ + assign n3856_o = opc_opcode_q[4]; + /* decoder.vhd:1829:15 */ + assign n3859_o = n3856_o ? 1'b1 : 1'b0; + /* decoder.vhd:1829:15 */ + assign n3862_o = n3856_o ? 1'b1 : 1'b0; + /* decoder.vhd:1826:13 */ + assign n3864_o = clk_mstate_i == 3'b000; + /* decoder.vhd:1834:13 */ + assign n3866_o = clk_mstate_i == 3'b001; + assign n3867_o = {n3866_o, n3864_o}; + /* decoder.vhd:1824:11 */ + always @* + case (n3867_o) + 2'b10: n3870_o = 1'b0; + 2'b01: n3870_o = 1'b1; + default: n3870_o = 1'b0; + endcase + /* decoder.vhd:1824:11 */ + always @* + case (n3867_o) + 2'b10: n3873_o = 1'b0; + 2'b01: n3873_o = 1'b1; + default: n3873_o = 1'b0; + endcase + /* decoder.vhd:1824:11 */ + always @* + case (n3867_o) + 2'b10: n3875_o = 1'b0; + 2'b01: n3875_o = n3859_o; + default: n3875_o = 1'b0; + endcase + /* decoder.vhd:1824:11 */ + always @* + case (n3867_o) + 2'b10: n3878_o = 1'b1; + 2'b01: n3878_o = 1'b0; + default: n3878_o = 1'b0; + endcase + /* decoder.vhd:1824:11 */ + always @* + case (n3867_o) + 2'b10: n3880_o = 1'b0; + 2'b01: n3880_o = n3862_o; + default: n3880_o = 1'b0; + endcase + /* decoder.vhd:1798:9 */ + assign n3881_o = n3829_o ? n3839_o : n2030_o; + /* decoder.vhd:1798:9 */ + assign n3882_o = n3829_o ? n3842_o : n3870_o; + /* decoder.vhd:1798:9 */ + assign n3884_o = n3829_o ? n3845_o : 1'b0; + /* decoder.vhd:1798:9 */ + assign n3886_o = n3829_o ? 1'b0 : n3873_o; + /* decoder.vhd:1798:9 */ + assign n3888_o = n3829_o ? n3848_o : 1'b0; + /* decoder.vhd:1798:9 */ + assign n3890_o = n3829_o ? 1'b0 : n3875_o; + /* decoder.vhd:1798:9 */ + assign n3892_o = n3829_o ? n3852_o : 2'b01; + /* decoder.vhd:1798:9 */ + assign n3894_o = n3829_o ? n3855_o : 1'b0; + /* decoder.vhd:1798:9 */ + assign n3896_o = n3829_o ? 1'b0 : n3878_o; + /* decoder.vhd:1798:9 */ + assign n3898_o = n3829_o ? 1'b0 : n3880_o; + /* decoder.vhd:1797:7 */ + assign n3900_o = opc_mnemonic_s == 6'b101111; + /* decoder.vhd:1846:25 */ + assign n3902_o = clk_mstate_i == 3'b010; + /* decoder.vhd:1851:26 */ + assign n3903_o = opc_opcode_q[4]; + /* decoder.vhd:1851:11 */ + assign n3906_o = n3903_o ? 1'b1 : 1'b0; + /* decoder.vhd:1851:11 */ + assign n3908_o = n3903_o ? alu_carry_i : 1'b0; + /* decoder.vhd:1851:11 */ + assign n3911_o = n3903_o ? 1'b1 : 1'b0; + /* decoder.vhd:1846:9 */ + assign n3914_o = n3902_o ? 1'b1 : 1'b0; + /* decoder.vhd:1846:9 */ + assign n3917_o = n3902_o ? 1'b1 : 1'b0; + /* decoder.vhd:1846:9 */ + assign n3920_o = n3902_o ? 4'b0101 : 4'b1100; + /* decoder.vhd:1846:9 */ + assign n3922_o = n3902_o ? n3906_o : 1'b0; + /* decoder.vhd:1846:9 */ + assign n3924_o = n3902_o ? n3908_o : 1'b0; + /* decoder.vhd:1846:9 */ + assign n3926_o = n3902_o ? n3911_o : 1'b0; + /* decoder.vhd:1845:7 */ + assign n3928_o = opc_mnemonic_s == 6'b110000; + /* decoder.vhd:1860:25 */ + assign n3930_o = clk_mstate_i == 3'b010; + /* decoder.vhd:1865:26 */ + assign n3931_o = opc_opcode_q[4]; + /* decoder.vhd:1865:30 */ + assign n3932_o = ~n3931_o; + /* decoder.vhd:1865:11 */ + assign n3935_o = n3932_o ? 1'b1 : 1'b0; + /* decoder.vhd:1865:11 */ + assign n3937_o = n3932_o ? alu_carry_i : 1'b0; + /* decoder.vhd:1865:11 */ + assign n3940_o = n3932_o ? 1'b1 : 1'b0; + /* decoder.vhd:1860:9 */ + assign n3943_o = n3930_o ? 1'b1 : 1'b0; + /* decoder.vhd:1860:9 */ + assign n3946_o = n3930_o ? 1'b1 : 1'b0; + /* decoder.vhd:1860:9 */ + assign n3949_o = n3930_o ? 4'b0110 : 4'b1100; + /* decoder.vhd:1860:9 */ + assign n3951_o = n3930_o ? n3935_o : 1'b0; + /* decoder.vhd:1860:9 */ + assign n3953_o = n3930_o ? n3937_o : 1'b0; + /* decoder.vhd:1860:9 */ + assign n3955_o = n3930_o ? n3940_o : 1'b0; + /* decoder.vhd:1859:7 */ + assign n3957_o = opc_mnemonic_s == 6'b110001; + /* decoder.vhd:1874:25 */ + assign n3959_o = clk_mstate_i == 3'b010; + /* decoder.vhd:1875:26 */ + assign n3960_o = opc_opcode_q[4]; + /* decoder.vhd:1875:11 */ + assign n3963_o = n3960_o ? 1'b0 : 1'b1; + /* decoder.vhd:1875:11 */ + assign n3966_o = n3960_o ? 1'b1 : 1'b0; + /* decoder.vhd:1874:9 */ + assign n3968_o = n3959_o ? n3963_o : 1'b0; + /* decoder.vhd:1874:9 */ + assign n3970_o = n3959_o ? n3966_o : 1'b0; + /* decoder.vhd:1873:7 */ + assign n3972_o = opc_mnemonic_s == 6'b110010; + /* decoder.vhd:1884:25 */ + assign n3974_o = clk_mstate_i == 3'b010; + /* decoder.vhd:1885:45 */ + assign n3975_o = opc_opcode_q[4]; + /* decoder.vhd:1884:9 */ + assign n3977_o = n3974_o ? n3975_o : 1'b0; + /* decoder.vhd:1884:9 */ + assign n3980_o = n3974_o ? 1'b1 : 1'b0; + /* decoder.vhd:1883:7 */ + assign n3982_o = opc_mnemonic_s == 6'b110011; + /* decoder.vhd:1891:25 */ + assign n3984_o = clk_mstate_i == 3'b010; + /* decoder.vhd:1891:9 */ + assign n3987_o = n3984_o ? 1'b1 : 1'b0; + /* decoder.vhd:1890:7 */ + assign n3989_o = opc_mnemonic_s == 6'b110100; + /* decoder.vhd:1897:25 */ + assign n3991_o = clk_mstate_i == 3'b010; + /* decoder.vhd:1898:26 */ + assign n3992_o = opc_opcode_q[4]; + /* decoder.vhd:1898:11 */ + assign n3995_o = n3992_o ? 1'b1 : 1'b0; + /* decoder.vhd:1898:11 */ + assign n3998_o = n3992_o ? 1'b0 : 1'b1; + /* decoder.vhd:1897:9 */ + assign n4000_o = n3991_o ? n3995_o : 1'b0; + /* decoder.vhd:1897:9 */ + assign n4002_o = n3991_o ? n3998_o : 1'b0; + /* decoder.vhd:1896:7 */ + assign n4004_o = opc_mnemonic_s == 6'b110101; + /* decoder.vhd:1909:25 */ + assign n4006_o = clk_mstate_i == 3'b010; + /* decoder.vhd:1909:9 */ + assign n4009_o = n4006_o ? 1'b1 : 1'b0; + /* decoder.vhd:1909:9 */ + assign n4012_o = n4006_o ? 1'b1 : 1'b0; + /* decoder.vhd:1906:7 */ + assign n4014_o = opc_mnemonic_s == 6'b110110; + /* decoder.vhd:1920:28 */ + assign n4015_o = opc_opcode_q[3]; + /* decoder.vhd:1920:32 */ + assign n4016_o = ~n4015_o; + /* decoder.vhd:1919:44 */ + assign n4018_o = 1'b0 | n4016_o; + /* decoder.vhd:1919:13 */ + assign n4025_o = n4018_o ? 1'b1 : n2030_o; + /* decoder.vhd:1919:13 */ + assign n4028_o = n4018_o ? 1'b1 : 1'b0; + /* decoder.vhd:1919:13 */ + assign n4031_o = n4018_o ? 2'b00 : 2'b01; + /* decoder.vhd:1918:11 */ + assign n4033_o = clk_mstate_i == 3'b010; + /* decoder.vhd:1930:28 */ + assign n4034_o = opc_opcode_q[4]; + /* decoder.vhd:1930:13 */ + assign n4037_o = n4034_o ? 1'b1 : 1'b0; + /* decoder.vhd:1926:11 */ + assign n4039_o = clk_mstate_i == 3'b011; + /* decoder.vhd:1940:28 */ + assign n4040_o = opc_opcode_q[4]; + /* decoder.vhd:1940:13 */ + assign n4043_o = n4040_o ? 4'b1011 : 4'b1100; + /* decoder.vhd:1937:11 */ + assign n4045_o = clk_mstate_i == 3'b100; + assign n4046_o = {n4045_o, n4039_o, n4033_o}; + /* decoder.vhd:1916:9 */ + always @* + case (n4046_o) + 3'b100: n4049_o = 1'b0; + 3'b010: n4049_o = 1'b1; + 3'b001: n4049_o = 1'b0; + default: n4049_o = 1'b0; + endcase + /* decoder.vhd:1916:9 */ + always @* + case (n4046_o) + 3'b100: n4052_o = 1'b0; + 3'b010: n4052_o = 1'b1; + 3'b001: n4052_o = 1'b0; + default: n4052_o = 1'b0; + endcase + /* decoder.vhd:1916:9 */ + always @* + case (n4046_o) + 3'b100: n4055_o = 1'b1; + 3'b010: n4055_o = 1'b0; + 3'b001: n4055_o = 1'b0; + default: n4055_o = 1'b0; + endcase + /* decoder.vhd:1916:9 */ + always @* + case (n4046_o) + 3'b100: n4056_o = n2030_o; + 3'b010: n4056_o = n2030_o; + 3'b001: n4056_o = n4025_o; + default: n4056_o = n2030_o; + endcase + /* decoder.vhd:1916:9 */ + always @* + case (n4046_o) + 3'b100: n4059_o = 1'b0; + 3'b010: n4059_o = 1'b1; + 3'b001: n4059_o = n4028_o; + default: n4059_o = 1'b0; + endcase + /* decoder.vhd:1916:9 */ + always @* + case (n4046_o) + 3'b100: n4061_o = n4043_o; + 3'b010: n4061_o = 4'b1100; + 3'b001: n4061_o = 4'b1100; + default: n4061_o = 4'b1100; + endcase + /* decoder.vhd:1916:9 */ + always @* + case (n4046_o) + 3'b100: n4063_o = 1'b0; + 3'b010: n4063_o = n4037_o; + 3'b001: n4063_o = 1'b0; + default: n4063_o = 1'b0; + endcase + /* decoder.vhd:1916:9 */ + always @* + case (n4046_o) + 3'b100: n4065_o = 2'b01; + 3'b010: n4065_o = 2'b01; + 3'b001: n4065_o = n4031_o; + default: n4065_o = 2'b01; + endcase + /* decoder.vhd:1916:9 */ + always @* + case (n4046_o) + 3'b100: n4068_o = 1'b1; + 3'b010: n4068_o = 1'b0; + 3'b001: n4068_o = 1'b0; + default: n4068_o = 1'b0; + endcase + /* decoder.vhd:1915:7 */ + assign n4070_o = opc_mnemonic_s == 6'b110111; + /* decoder.vhd:1957:28 */ + assign n4071_o = opc_opcode_q[3]; + /* decoder.vhd:1957:32 */ + assign n4072_o = ~n4071_o; + /* decoder.vhd:1956:44 */ + assign n4074_o = 1'b0 | n4072_o; + /* decoder.vhd:1956:13 */ + assign n4081_o = n4074_o ? 1'b1 : n2030_o; + /* decoder.vhd:1956:13 */ + assign n4084_o = n4074_o ? 1'b1 : 1'b0; + /* decoder.vhd:1956:13 */ + assign n4087_o = n4074_o ? 2'b00 : 2'b01; + /* decoder.vhd:1955:11 */ + assign n4089_o = clk_mstate_i == 3'b010; + /* decoder.vhd:1962:11 */ + assign n4094_o = clk_mstate_i == 3'b011; + /* decoder.vhd:1966:11 */ + assign n4099_o = clk_mstate_i == 3'b100; + assign n4100_o = {n4099_o, n4094_o, n4089_o}; + /* decoder.vhd:1953:9 */ + always @* + case (n4100_o) + 3'b100: n4103_o = 1'b1; + 3'b010: n4103_o = 1'b0; + 3'b001: n4103_o = 1'b0; + default: n4103_o = 1'b0; + endcase + /* decoder.vhd:1953:9 */ + always @* + case (n4100_o) + 3'b100: n4106_o = 1'b0; + 3'b010: n4106_o = 1'b1; + 3'b001: n4106_o = 1'b0; + default: n4106_o = 1'b0; + endcase + /* decoder.vhd:1953:9 */ + always @* + case (n4100_o) + 3'b100: n4109_o = 1'b1; + 3'b010: n4109_o = 1'b0; + 3'b001: n4109_o = 1'b0; + default: n4109_o = 1'b0; + endcase + /* decoder.vhd:1953:9 */ + always @* + case (n4100_o) + 3'b100: n4110_o = n2030_o; + 3'b010: n4110_o = n2030_o; + 3'b001: n4110_o = n4081_o; + default: n4110_o = n2030_o; + endcase + /* decoder.vhd:1953:9 */ + always @* + case (n4100_o) + 3'b100: n4113_o = 1'b0; + 3'b010: n4113_o = 1'b1; + 3'b001: n4113_o = n4084_o; + default: n4113_o = 1'b0; + endcase + /* decoder.vhd:1953:9 */ + always @* + case (n4100_o) + 3'b100: n4116_o = 4'b0010; + 3'b010: n4116_o = 4'b1100; + 3'b001: n4116_o = 4'b1100; + default: n4116_o = 4'b1100; + endcase + /* decoder.vhd:1953:9 */ + always @* + case (n4100_o) + 3'b100: n4118_o = 2'b01; + 3'b010: n4118_o = 2'b01; + 3'b001: n4118_o = n4087_o; + default: n4118_o = 2'b01; + endcase + /* decoder.vhd:1952:7 */ + assign n4120_o = opc_mnemonic_s == 6'b111000; + /* decoder.vhd:1981:13 */ + assign n4122_o = clk_mstate_i == 3'b000; + /* decoder.vhd:1985:13 */ + assign n4127_o = clk_mstate_i == 3'b010; + assign n4128_o = {n4127_o, n4122_o}; + /* decoder.vhd:1979:11 */ + always @* + case (n4128_o) + 2'b10: n4131_o = 1'b1; + 2'b01: n4131_o = 1'b0; + default: n4131_o = 1'b0; + endcase + /* decoder.vhd:1979:11 */ + always @* + case (n4128_o) + 2'b10: n4134_o = 1'b0; + 2'b01: n4134_o = 1'b1; + default: n4134_o = 1'b0; + endcase + /* decoder.vhd:1979:11 */ + always @* + case (n4128_o) + 2'b10: n4137_o = 1'b1; + 2'b01: n4137_o = 1'b0; + default: n4137_o = 1'b0; + endcase + /* decoder.vhd:1979:11 */ + always @* + case (n4128_o) + 2'b10: n4140_o = 4'b0010; + 2'b01: n4140_o = 4'b1100; + default: n4140_o = 4'b1100; + endcase + /* decoder.vhd:1978:9 */ + assign n4142_o = clk_second_cycle_i ? n4131_o : 1'b0; + /* decoder.vhd:1978:9 */ + assign n4144_o = clk_second_cycle_i ? n4134_o : 1'b0; + /* decoder.vhd:1978:9 */ + assign n4146_o = clk_second_cycle_i ? n4137_o : 1'b0; + /* decoder.vhd:1978:9 */ + assign n4148_o = clk_second_cycle_i ? n4140_o : 4'b1100; + /* decoder.vhd:1975:7 */ + assign n4150_o = opc_mnemonic_s == 6'b111001; + assign n4151_o = {n4150_o, n4120_o, n4070_o, n4014_o, n4004_o, n3989_o, n3982_o, n3972_o, n3957_o, n3928_o, n3900_o, n3828_o, n3792_o, n3782_o, n3670_o, n3640_o, n3590_o, n3588_o, n3522_o, n3491_o, n3426_o, n3358_o, n3333_o, n3323_o, n3289_o, n3254_o, n3241_o, n3228_o, n3189_o, n3181_o, n3145_o, n3114_o, n3078_o, n3052_o, n3026_o, n3000_o, n2973_o, n2942_o, n2908_o, n2877_o, n2846_o, n2785_o, n2774_o, n2764_o, n2744_o, n2737_o, n2721_o, n2657_o, n2642_o, n2627_o, n2591_o, n2545_o, n2524_o, n2514_o, n2501_o, n2485_o, n2478_o, n2465_o, n2347_o, n2235_o, n2205_o, n2155_o, n2103_o}; + /* decoder.vhd:635:5 */ + always @* + case (n4151_o) + 63'b100000000000000000000000000000000000000000000000000000000000000: n4153_o = n4142_o; + 63'b010000000000000000000000000000000000000000000000000000000000000: n4153_o = n4103_o; + 63'b001000000000000000000000000000000000000000000000000000000000000: n4153_o = n4049_o; + 63'b000100000000000000000000000000000000000000000000000000000000000: n4153_o = n4009_o; + 63'b000010000000000000000000000000000000000000000000000000000000000: n4153_o = 1'b0; + 63'b000001000000000000000000000000000000000000000000000000000000000: n4153_o = 1'b0; + 63'b000000100000000000000000000000000000000000000000000000000000000: n4153_o = 1'b0; + 63'b000000010000000000000000000000000000000000000000000000000000000: n4153_o = 1'b0; + 63'b000000001000000000000000000000000000000000000000000000000000000: n4153_o = n3943_o; + 63'b000000000100000000000000000000000000000000000000000000000000000: n4153_o = n3914_o; + 63'b000000000010000000000000000000000000000000000000000000000000000: n4153_o = 1'b0; + 63'b000000000001000000000000000000000000000000000000000000000000000: n4153_o = 1'b0; + 63'b000000000000100000000000000000000000000000000000000000000000000: n4153_o = 1'b0; + 63'b000000000000010000000000000000000000000000000000000000000000000: n4153_o = 1'b0; + 63'b000000000000001000000000000000000000000000000000000000000000000: n4153_o = n3662_o; + 63'b000000000000000100000000000000000000000000000000000000000000000: n4153_o = n3623_o; + 63'b000000000000000010000000000000000000000000000000000000000000000: n4153_o = 1'b0; + 63'b000000000000000001000000000000000000000000000000000000000000000: n4153_o = n3577_o; + 63'b000000000000000000100000000000000000000000000000000000000000000: n4153_o = n3514_o; + 63'b000000000000000000010000000000000000000000000000000000000000000: n4153_o = n3479_o; + 63'b000000000000000000001000000000000000000000000000000000000000000: n4153_o = 1'b0; + 63'b000000000000000000000100000000000000000000000000000000000000000: n4153_o = n3350_o; + 63'b000000000000000000000010000000000000000000000000000000000000000: n4153_o = 1'b0; + 63'b000000000000000000000001000000000000000000000000000000000000000: n4153_o = 1'b0; + 63'b000000000000000000000000100000000000000000000000000000000000000: n4153_o = 1'b0; + 63'b000000000000000000000000010000000000000000000000000000000000000: n4153_o = 1'b0; + 63'b000000000000000000000000001000000000000000000000000000000000000: n4153_o = n3233_o; + 63'b000000000000000000000000000100000000000000000000000000000000000: n4153_o = n3217_o; + 63'b000000000000000000000000000010000000000000000000000000000000000: n4153_o = n3187_o; + 63'b000000000000000000000000000001000000000000000000000000000000000: n4153_o = 1'b0; + 63'b000000000000000000000000000000100000000000000000000000000000000: n4153_o = 1'b0; + 63'b000000000000000000000000000000010000000000000000000000000000000: n4153_o = 1'b0; + 63'b000000000000000000000000000000001000000000000000000000000000000: n4153_o = 1'b0; + 63'b000000000000000000000000000000000100000000000000000000000000000: n4153_o = 1'b0; + 63'b000000000000000000000000000000000010000000000000000000000000000: n4153_o = 1'b0; + 63'b000000000000000000000000000000000001000000000000000000000000000: n4153_o = 1'b0; + 63'b000000000000000000000000000000000000100000000000000000000000000: n4153_o = 1'b0; + 63'b000000000000000000000000000000000000010000000000000000000000000: n4153_o = 1'b0; + 63'b000000000000000000000000000000000000001000000000000000000000000: n4153_o = 1'b0; + 63'b000000000000000000000000000000000000000100000000000000000000000: n4153_o = 1'b0; + 63'b000000000000000000000000000000000000000010000000000000000000000: n4153_o = n2829_o; + 63'b000000000000000000000000000000000000000001000000000000000000000: n4153_o = n2780_o; + 63'b000000000000000000000000000000000000000000100000000000000000000: n4153_o = n2769_o; + 63'b000000000000000000000000000000000000000000010000000000000000000: n4153_o = n2758_o; + 63'b000000000000000000000000000000000000000000001000000000000000000: n4153_o = 1'b0; + 63'b000000000000000000000000000000000000000000000100000000000000000: n4153_o = 1'b0; + 63'b000000000000000000000000000000000000000000000010000000000000000: n4153_o = 1'b0; + 63'b000000000000000000000000000000000000000000000001000000000000000: n4153_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000100000000000000: n4153_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000010000000000000: n4153_o = n2613_o; + 63'b000000000000000000000000000000000000000000000000001000000000000: n4153_o = n2567_o; + 63'b000000000000000000000000000000000000000000000000000100000000000: n4153_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000010000000000: n4153_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000001000000000: n4153_o = n2506_o; + 63'b000000000000000000000000000000000000000000000000000000100000000: n4153_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000010000000: n4153_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000001000000: n4153_o = n2470_o; + 63'b000000000000000000000000000000000000000000000000000000000100000: n4153_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000010000: n4153_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000001000: n4153_o = n2227_o; + 63'b000000000000000000000000000000000000000000000000000000000000100: n4153_o = n2188_o; + 63'b000000000000000000000000000000000000000000000000000000000000010: n4153_o = n2139_o; + 63'b000000000000000000000000000000000000000000000000000000000000001: n4153_o = n2076_o; + default: n4153_o = 1'b0; + endcase + /* decoder.vhd:635:5 */ + always @* + case (n4151_o) + 63'b100000000000000000000000000000000000000000000000000000000000000: n4156_o = 1'b0; + 63'b010000000000000000000000000000000000000000000000000000000000000: n4156_o = 1'b0; + 63'b001000000000000000000000000000000000000000000000000000000000000: n4156_o = 1'b0; + 63'b000100000000000000000000000000000000000000000000000000000000000: n4156_o = 1'b0; + 63'b000010000000000000000000000000000000000000000000000000000000000: n4156_o = 1'b0; + 63'b000001000000000000000000000000000000000000000000000000000000000: n4156_o = 1'b0; + 63'b000000100000000000000000000000000000000000000000000000000000000: n4156_o = 1'b0; + 63'b000000010000000000000000000000000000000000000000000000000000000: n4156_o = 1'b0; + 63'b000000001000000000000000000000000000000000000000000000000000000: n4156_o = 1'b0; + 63'b000000000100000000000000000000000000000000000000000000000000000: n4156_o = 1'b0; + 63'b000000000010000000000000000000000000000000000000000000000000000: n4156_o = 1'b0; + 63'b000000000001000000000000000000000000000000000000000000000000000: n4156_o = 1'b0; + 63'b000000000000100000000000000000000000000000000000000000000000000: n4156_o = 1'b0; + 63'b000000000000010000000000000000000000000000000000000000000000000: n4156_o = n3758_o; + 63'b000000000000001000000000000000000000000000000000000000000000000: n4156_o = 1'b0; + 63'b000000000000000100000000000000000000000000000000000000000000000: n4156_o = 1'b0; + 63'b000000000000000010000000000000000000000000000000000000000000000: n4156_o = 1'b0; + 63'b000000000000000001000000000000000000000000000000000000000000000: n4156_o = 1'b0; + 63'b000000000000000000100000000000000000000000000000000000000000000: n4156_o = 1'b0; + 63'b000000000000000000010000000000000000000000000000000000000000000: n4156_o = 1'b0; + 63'b000000000000000000001000000000000000000000000000000000000000000: n4156_o = 1'b0; + 63'b000000000000000000000100000000000000000000000000000000000000000: n4156_o = 1'b0; + 63'b000000000000000000000010000000000000000000000000000000000000000: n4156_o = 1'b0; + 63'b000000000000000000000001000000000000000000000000000000000000000: n4156_o = 1'b0; + 63'b000000000000000000000000100000000000000000000000000000000000000: n4156_o = 1'b0; + 63'b000000000000000000000000010000000000000000000000000000000000000: n4156_o = 1'b0; + 63'b000000000000000000000000001000000000000000000000000000000000000: n4156_o = 1'b0; + 63'b000000000000000000000000000100000000000000000000000000000000000: n4156_o = 1'b0; + 63'b000000000000000000000000000010000000000000000000000000000000000: n4156_o = 1'b0; + 63'b000000000000000000000000000001000000000000000000000000000000000: n4156_o = 1'b0; + 63'b000000000000000000000000000000100000000000000000000000000000000: n4156_o = 1'b0; + 63'b000000000000000000000000000000010000000000000000000000000000000: n4156_o = 1'b0; + 63'b000000000000000000000000000000001000000000000000000000000000000: n4156_o = 1'b0; + 63'b000000000000000000000000000000000100000000000000000000000000000: n4156_o = 1'b0; + 63'b000000000000000000000000000000000010000000000000000000000000000: n4156_o = 1'b0; + 63'b000000000000000000000000000000000001000000000000000000000000000: n4156_o = 1'b0; + 63'b000000000000000000000000000000000000100000000000000000000000000: n4156_o = 1'b0; + 63'b000000000000000000000000000000000000010000000000000000000000000: n4156_o = 1'b0; + 63'b000000000000000000000000000000000000001000000000000000000000000: n4156_o = 1'b0; + 63'b000000000000000000000000000000000000000100000000000000000000000: n4156_o = 1'b0; + 63'b000000000000000000000000000000000000000010000000000000000000000: n4156_o = n2831_o; + 63'b000000000000000000000000000000000000000001000000000000000000000: n4156_o = 1'b0; + 63'b000000000000000000000000000000000000000000100000000000000000000: n4156_o = 1'b0; + 63'b000000000000000000000000000000000000000000010000000000000000000: n4156_o = 1'b0; + 63'b000000000000000000000000000000000000000000001000000000000000000: n4156_o = 1'b0; + 63'b000000000000000000000000000000000000000000000100000000000000000: n4156_o = 1'b0; + 63'b000000000000000000000000000000000000000000000010000000000000000: n4156_o = n2701_o; + 63'b000000000000000000000000000000000000000000000001000000000000000: n4156_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000100000000000000: n4156_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000010000000000000: n4156_o = n2615_o; + 63'b000000000000000000000000000000000000000000000000001000000000000: n4156_o = n2569_o; + 63'b000000000000000000000000000000000000000000000000000100000000000: n4156_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000010000000000: n4156_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000001000000000: n4156_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000100000000: n4156_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000010000000: n4156_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000001000000: n4156_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000100000: n4156_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000010000: n4156_o = n2323_o; + 63'b000000000000000000000000000000000000000000000000000000000001000: n4156_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000000100: n4156_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000000010: n4156_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000000001: n4156_o = 1'b0; + default: n4156_o = 1'b0; + endcase + /* decoder.vhd:635:5 */ + always @* + case (n4151_o) + 63'b100000000000000000000000000000000000000000000000000000000000000: n4159_o = n4144_o; + 63'b010000000000000000000000000000000000000000000000000000000000000: n4159_o = n4106_o; + 63'b001000000000000000000000000000000000000000000000000000000000000: n4159_o = n4052_o; + 63'b000100000000000000000000000000000000000000000000000000000000000: n4159_o = 1'b0; + 63'b000010000000000000000000000000000000000000000000000000000000000: n4159_o = 1'b0; + 63'b000001000000000000000000000000000000000000000000000000000000000: n4159_o = 1'b0; + 63'b000000100000000000000000000000000000000000000000000000000000000: n4159_o = 1'b0; + 63'b000000010000000000000000000000000000000000000000000000000000000: n4159_o = 1'b0; + 63'b000000001000000000000000000000000000000000000000000000000000000: n4159_o = 1'b0; + 63'b000000000100000000000000000000000000000000000000000000000000000: n4159_o = 1'b0; + 63'b000000000010000000000000000000000000000000000000000000000000000: n4159_o = 1'b0; + 63'b000000000001000000000000000000000000000000000000000000000000000: n4159_o = 1'b0; + 63'b000000000000100000000000000000000000000000000000000000000000000: n4159_o = 1'b0; + 63'b000000000000010000000000000000000000000000000000000000000000000: n4159_o = n3760_o; + 63'b000000000000001000000000000000000000000000000000000000000000000: n4159_o = n3664_o; + 63'b000000000000000100000000000000000000000000000000000000000000000: n4159_o = n3626_o; + 63'b000000000000000010000000000000000000000000000000000000000000000: n4159_o = 1'b0; + 63'b000000000000000001000000000000000000000000000000000000000000000: n4159_o = 1'b0; + 63'b000000000000000000100000000000000000000000000000000000000000000: n4159_o = 1'b0; + 63'b000000000000000000010000000000000000000000000000000000000000000: n4159_o = 1'b0; + 63'b000000000000000000001000000000000000000000000000000000000000000: n4159_o = 1'b0; + 63'b000000000000000000000100000000000000000000000000000000000000000: n4159_o = 1'b0; + 63'b000000000000000000000010000000000000000000000000000000000000000: n4159_o = 1'b0; + 63'b000000000000000000000001000000000000000000000000000000000000000: n4159_o = 1'b0; + 63'b000000000000000000000000100000000000000000000000000000000000000: n4159_o = 1'b0; + 63'b000000000000000000000000010000000000000000000000000000000000000: n4159_o = 1'b0; + 63'b000000000000000000000000001000000000000000000000000000000000000: n4159_o = 1'b0; + 63'b000000000000000000000000000100000000000000000000000000000000000: n4159_o = n3220_o; + 63'b000000000000000000000000000010000000000000000000000000000000000: n4159_o = 1'b0; + 63'b000000000000000000000000000001000000000000000000000000000000000: n4159_o = 1'b0; + 63'b000000000000000000000000000000100000000000000000000000000000000: n4159_o = 1'b0; + 63'b000000000000000000000000000000010000000000000000000000000000000: n4159_o = 1'b0; + 63'b000000000000000000000000000000001000000000000000000000000000000: n4159_o = 1'b0; + 63'b000000000000000000000000000000000100000000000000000000000000000: n4159_o = 1'b0; + 63'b000000000000000000000000000000000010000000000000000000000000000: n4159_o = 1'b0; + 63'b000000000000000000000000000000000001000000000000000000000000000: n4159_o = 1'b0; + 63'b000000000000000000000000000000000000100000000000000000000000000: n4159_o = 1'b0; + 63'b000000000000000000000000000000000000010000000000000000000000000: n4159_o = 1'b0; + 63'b000000000000000000000000000000000000001000000000000000000000000: n4159_o = 1'b0; + 63'b000000000000000000000000000000000000000100000000000000000000000: n4159_o = 1'b0; + 63'b000000000000000000000000000000000000000010000000000000000000000: n4159_o = 1'b0; + 63'b000000000000000000000000000000000000000001000000000000000000000: n4159_o = 1'b0; + 63'b000000000000000000000000000000000000000000100000000000000000000: n4159_o = 1'b0; + 63'b000000000000000000000000000000000000000000010000000000000000000: n4159_o = 1'b0; + 63'b000000000000000000000000000000000000000000001000000000000000000: n4159_o = 1'b0; + 63'b000000000000000000000000000000000000000000000100000000000000000: n4159_o = 1'b0; + 63'b000000000000000000000000000000000000000000000010000000000000000: n4159_o = 1'b0; + 63'b000000000000000000000000000000000000000000000001000000000000000: n4159_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000100000000000000: n4159_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000010000000000000: n4159_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000001000000000000: n4159_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000100000000000: n4159_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000010000000000: n4159_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000001000000000: n4159_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000100000000: n4159_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000010000000: n4159_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000001000000: n4159_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000100000: n4159_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000010000: n4159_o = n2325_o; + 63'b000000000000000000000000000000000000000000000000000000000001000: n4159_o = n2229_o; + 63'b000000000000000000000000000000000000000000000000000000000000100: n4159_o = n2191_o; + 63'b000000000000000000000000000000000000000000000000000000000000010: n4159_o = n2141_o; + 63'b000000000000000000000000000000000000000000000000000000000000001: n4159_o = n2079_o; + default: n4159_o = 1'b0; + endcase + /* decoder.vhd:635:5 */ + always @* + case (n4151_o) + 63'b100000000000000000000000000000000000000000000000000000000000000: n4162_o = n4146_o; + 63'b010000000000000000000000000000000000000000000000000000000000000: n4162_o = n4109_o; + 63'b001000000000000000000000000000000000000000000000000000000000000: n4162_o = n4055_o; + 63'b000100000000000000000000000000000000000000000000000000000000000: n4162_o = n4012_o; + 63'b000010000000000000000000000000000000000000000000000000000000000: n4162_o = 1'b0; + 63'b000001000000000000000000000000000000000000000000000000000000000: n4162_o = 1'b0; + 63'b000000100000000000000000000000000000000000000000000000000000000: n4162_o = 1'b0; + 63'b000000010000000000000000000000000000000000000000000000000000000: n4162_o = 1'b0; + 63'b000000001000000000000000000000000000000000000000000000000000000: n4162_o = n3946_o; + 63'b000000000100000000000000000000000000000000000000000000000000000: n4162_o = n3917_o; + 63'b000000000010000000000000000000000000000000000000000000000000000: n4162_o = 1'b0; + 63'b000000000001000000000000000000000000000000000000000000000000000: n4162_o = n3820_o; + 63'b000000000000100000000000000000000000000000000000000000000000000: n4162_o = n3787_o; + 63'b000000000000010000000000000000000000000000000000000000000000000: n4162_o = n3762_o; + 63'b000000000000001000000000000000000000000000000000000000000000000: n4162_o = n3666_o; + 63'b000000000000000100000000000000000000000000000000000000000000000: n4162_o = n3629_o; + 63'b000000000000000010000000000000000000000000000000000000000000000: n4162_o = 1'b0; + 63'b000000000000000001000000000000000000000000000000000000000000000: n4162_o = n3578_o; + 63'b000000000000000000100000000000000000000000000000000000000000000: n4162_o = n3516_o; + 63'b000000000000000000010000000000000000000000000000000000000000000: n4162_o = 1'b0; + 63'b000000000000000000001000000000000000000000000000000000000000000: n4162_o = n3418_o; + 63'b000000000000000000000100000000000000000000000000000000000000000: n4162_o = n3352_o; + 63'b000000000000000000000010000000000000000000000000000000000000000: n4162_o = n3328_o; + 63'b000000000000000000000001000000000000000000000000000000000000000: n4162_o = 1'b0; + 63'b000000000000000000000000100000000000000000000000000000000000000: n4162_o = n3279_o; + 63'b000000000000000000000000010000000000000000000000000000000000000: n4162_o = n3246_o; + 63'b000000000000000000000000001000000000000000000000000000000000000: n4162_o = 1'b0; + 63'b000000000000000000000000000100000000000000000000000000000000000: n4162_o = 1'b0; + 63'b000000000000000000000000000010000000000000000000000000000000000: n4162_o = 1'b0; + 63'b000000000000000000000000000001000000000000000000000000000000000: n4162_o = n3171_o; + 63'b000000000000000000000000000000100000000000000000000000000000000: n4162_o = 1'b0; + 63'b000000000000000000000000000000010000000000000000000000000000000: n4162_o = 1'b0; + 63'b000000000000000000000000000000001000000000000000000000000000000: n4162_o = 1'b0; + 63'b000000000000000000000000000000000100000000000000000000000000000: n4162_o = 1'b0; + 63'b000000000000000000000000000000000010000000000000000000000000000: n4162_o = 1'b0; + 63'b000000000000000000000000000000000001000000000000000000000000000: n4162_o = n2992_o; + 63'b000000000000000000000000000000000000100000000000000000000000000: n4162_o = 1'b0; + 63'b000000000000000000000000000000000000010000000000000000000000000: n4162_o = 1'b0; + 63'b000000000000000000000000000000000000001000000000000000000000000: n4162_o = 1'b0; + 63'b000000000000000000000000000000000000000100000000000000000000000: n4162_o = n2869_o; + 63'b000000000000000000000000000000000000000010000000000000000000000: n4162_o = n2834_o; + 63'b000000000000000000000000000000000000000001000000000000000000000: n4162_o = 1'b0; + 63'b000000000000000000000000000000000000000000100000000000000000000: n4162_o = 1'b0; + 63'b000000000000000000000000000000000000000000010000000000000000000: n4162_o = 1'b0; + 63'b000000000000000000000000000000000000000000001000000000000000000: n4162_o = 1'b0; + 63'b000000000000000000000000000000000000000000000100000000000000000: n4162_o = 1'b0; + 63'b000000000000000000000000000000000000000000000010000000000000000: n4162_o = n2703_o; + 63'b000000000000000000000000000000000000000000000001000000000000000: n4162_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000100000000000000: n4162_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000010000000000000: n4162_o = n2618_o; + 63'b000000000000000000000000000000000000000000000000001000000000000: n4162_o = n2572_o; + 63'b000000000000000000000000000000000000000000000000000100000000000: n4162_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000010000000000: n4162_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000001000000000: n4162_o = n2509_o; + 63'b000000000000000000000000000000000000000000000000000000100000000: n4162_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000010000000: n4162_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000001000000: n4162_o = n2473_o; + 63'b000000000000000000000000000000000000000000000000000000000100000: n4162_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000010000: n4162_o = n2327_o; + 63'b000000000000000000000000000000000000000000000000000000000001000: n4162_o = n2231_o; + 63'b000000000000000000000000000000000000000000000000000000000000100: n4162_o = n2194_o; + 63'b000000000000000000000000000000000000000000000000000000000000010: n4162_o = n2143_o; + 63'b000000000000000000000000000000000000000000000000000000000000001: n4162_o = n2082_o; + default: n4162_o = 1'b0; + endcase + /* decoder.vhd:635:5 */ + always @* + case (n4151_o) + 63'b100000000000000000000000000000000000000000000000000000000000000: n4165_o = 1'b0; + 63'b010000000000000000000000000000000000000000000000000000000000000: n4165_o = 1'b0; + 63'b001000000000000000000000000000000000000000000000000000000000000: n4165_o = 1'b0; + 63'b000100000000000000000000000000000000000000000000000000000000000: n4165_o = 1'b0; + 63'b000010000000000000000000000000000000000000000000000000000000000: n4165_o = 1'b0; + 63'b000001000000000000000000000000000000000000000000000000000000000: n4165_o = 1'b0; + 63'b000000100000000000000000000000000000000000000000000000000000000: n4165_o = 1'b0; + 63'b000000010000000000000000000000000000000000000000000000000000000: n4165_o = 1'b0; + 63'b000000001000000000000000000000000000000000000000000000000000000: n4165_o = 1'b0; + 63'b000000000100000000000000000000000000000000000000000000000000000: n4165_o = 1'b0; + 63'b000000000010000000000000000000000000000000000000000000000000000: n4165_o = 1'b0; + 63'b000000000001000000000000000000000000000000000000000000000000000: n4165_o = n3822_o; + 63'b000000000000100000000000000000000000000000000000000000000000000: n4165_o = n3790_o; + 63'b000000000000010000000000000000000000000000000000000000000000000: n4165_o = n3764_o; + 63'b000000000000001000000000000000000000000000000000000000000000000: n4165_o = 1'b0; + 63'b000000000000000100000000000000000000000000000000000000000000000: n4165_o = 1'b0; + 63'b000000000000000010000000000000000000000000000000000000000000000: n4165_o = 1'b0; + 63'b000000000000000001000000000000000000000000000000000000000000000: n4165_o = n3579_o; + 63'b000000000000000000100000000000000000000000000000000000000000000: n4165_o = 1'b0; + 63'b000000000000000000010000000000000000000000000000000000000000000: n4165_o = 1'b0; + 63'b000000000000000000001000000000000000000000000000000000000000000: n4165_o = 1'b0; + 63'b000000000000000000000100000000000000000000000000000000000000000: n4165_o = 1'b0; + 63'b000000000000000000000010000000000000000000000000000000000000000: n4165_o = 1'b0; + 63'b000000000000000000000001000000000000000000000000000000000000000: n4165_o = 1'b0; + 63'b000000000000000000000000100000000000000000000000000000000000000: n4165_o = 1'b0; + 63'b000000000000000000000000010000000000000000000000000000000000000: n4165_o = 1'b0; + 63'b000000000000000000000000001000000000000000000000000000000000000: n4165_o = 1'b0; + 63'b000000000000000000000000000100000000000000000000000000000000000: n4165_o = 1'b0; + 63'b000000000000000000000000000010000000000000000000000000000000000: n4165_o = 1'b0; + 63'b000000000000000000000000000001000000000000000000000000000000000: n4165_o = 1'b0; + 63'b000000000000000000000000000000100000000000000000000000000000000: n4165_o = 1'b0; + 63'b000000000000000000000000000000010000000000000000000000000000000: n4165_o = 1'b0; + 63'b000000000000000000000000000000001000000000000000000000000000000: n4165_o = 1'b0; + 63'b000000000000000000000000000000000100000000000000000000000000000: n4165_o = 1'b0; + 63'b000000000000000000000000000000000010000000000000000000000000000: n4165_o = 1'b0; + 63'b000000000000000000000000000000000001000000000000000000000000000: n4165_o = 1'b0; + 63'b000000000000000000000000000000000000100000000000000000000000000: n4165_o = 1'b0; + 63'b000000000000000000000000000000000000010000000000000000000000000: n4165_o = 1'b0; + 63'b000000000000000000000000000000000000001000000000000000000000000: n4165_o = 1'b0; + 63'b000000000000000000000000000000000000000100000000000000000000000: n4165_o = 1'b0; + 63'b000000000000000000000000000000000000000010000000000000000000000: n4165_o = 1'b0; + 63'b000000000000000000000000000000000000000001000000000000000000000: n4165_o = 1'b0; + 63'b000000000000000000000000000000000000000000100000000000000000000: n4165_o = 1'b0; + 63'b000000000000000000000000000000000000000000010000000000000000000: n4165_o = 1'b0; + 63'b000000000000000000000000000000000000000000001000000000000000000: n4165_o = 1'b0; + 63'b000000000000000000000000000000000000000000000100000000000000000: n4165_o = 1'b0; + 63'b000000000000000000000000000000000000000000000010000000000000000: n4165_o = 1'b0; + 63'b000000000000000000000000000000000000000000000001000000000000000: n4165_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000100000000000000: n4165_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000010000000000000: n4165_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000001000000000000: n4165_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000100000000000: n4165_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000010000000000: n4165_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000001000000000: n4165_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000100000000: n4165_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000010000000: n4165_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000001000000: n4165_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000100000: n4165_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000010000: n4165_o = n2329_o; + 63'b000000000000000000000000000000000000000000000000000000000001000: n4165_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000000100: n4165_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000000010: n4165_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000000001: n4165_o = 1'b0; + default: n4165_o = 1'b0; + endcase + /* decoder.vhd:635:5 */ + always @* + case (n4151_o) + 63'b100000000000000000000000000000000000000000000000000000000000000: n4168_o = 1'b0; + 63'b010000000000000000000000000000000000000000000000000000000000000: n4168_o = 1'b0; + 63'b001000000000000000000000000000000000000000000000000000000000000: n4168_o = 1'b0; + 63'b000100000000000000000000000000000000000000000000000000000000000: n4168_o = 1'b0; + 63'b000010000000000000000000000000000000000000000000000000000000000: n4168_o = 1'b0; + 63'b000001000000000000000000000000000000000000000000000000000000000: n4168_o = 1'b0; + 63'b000000100000000000000000000000000000000000000000000000000000000: n4168_o = 1'b0; + 63'b000000010000000000000000000000000000000000000000000000000000000: n4168_o = 1'b0; + 63'b000000001000000000000000000000000000000000000000000000000000000: n4168_o = 1'b0; + 63'b000000000100000000000000000000000000000000000000000000000000000: n4168_o = 1'b0; + 63'b000000000010000000000000000000000000000000000000000000000000000: n4168_o = 1'b0; + 63'b000000000001000000000000000000000000000000000000000000000000000: n4168_o = 1'b0; + 63'b000000000000100000000000000000000000000000000000000000000000000: n4168_o = 1'b0; + 63'b000000000000010000000000000000000000000000000000000000000000000: n4168_o = 1'b0; + 63'b000000000000001000000000000000000000000000000000000000000000000: n4168_o = 1'b0; + 63'b000000000000000100000000000000000000000000000000000000000000000: n4168_o = 1'b0; + 63'b000000000000000010000000000000000000000000000000000000000000000: n4168_o = 1'b0; + 63'b000000000000000001000000000000000000000000000000000000000000000: n4168_o = 1'b0; + 63'b000000000000000000100000000000000000000000000000000000000000000: n4168_o = 1'b0; + 63'b000000000000000000010000000000000000000000000000000000000000000: n4168_o = 1'b0; + 63'b000000000000000000001000000000000000000000000000000000000000000: n4168_o = 1'b0; + 63'b000000000000000000000100000000000000000000000000000000000000000: n4168_o = 1'b0; + 63'b000000000000000000000010000000000000000000000000000000000000000: n4168_o = 1'b0; + 63'b000000000000000000000001000000000000000000000000000000000000000: n4168_o = 1'b0; + 63'b000000000000000000000000100000000000000000000000000000000000000: n4168_o = 1'b0; + 63'b000000000000000000000000010000000000000000000000000000000000000: n4168_o = 1'b0; + 63'b000000000000000000000000001000000000000000000000000000000000000: n4168_o = 1'b0; + 63'b000000000000000000000000000100000000000000000000000000000000000: n4168_o = 1'b0; + 63'b000000000000000000000000000010000000000000000000000000000000000: n4168_o = 1'b0; + 63'b000000000000000000000000000001000000000000000000000000000000000: n4168_o = 1'b0; + 63'b000000000000000000000000000000100000000000000000000000000000000: n4168_o = 1'b0; + 63'b000000000000000000000000000000010000000000000000000000000000000: n4168_o = 1'b0; + 63'b000000000000000000000000000000001000000000000000000000000000000: n4168_o = 1'b0; + 63'b000000000000000000000000000000000100000000000000000000000000000: n4168_o = 1'b0; + 63'b000000000000000000000000000000000010000000000000000000000000000: n4168_o = 1'b0; + 63'b000000000000000000000000000000000001000000000000000000000000000: n4168_o = 1'b0; + 63'b000000000000000000000000000000000000100000000000000000000000000: n4168_o = 1'b0; + 63'b000000000000000000000000000000000000010000000000000000000000000: n4168_o = 1'b0; + 63'b000000000000000000000000000000000000001000000000000000000000000: n4168_o = 1'b0; + 63'b000000000000000000000000000000000000000100000000000000000000000: n4168_o = 1'b0; + 63'b000000000000000000000000000000000000000010000000000000000000000: n4168_o = 1'b0; + 63'b000000000000000000000000000000000000000001000000000000000000000: n4168_o = 1'b0; + 63'b000000000000000000000000000000000000000000100000000000000000000: n4168_o = 1'b0; + 63'b000000000000000000000000000000000000000000010000000000000000000: n4168_o = 1'b0; + 63'b000000000000000000000000000000000000000000001000000000000000000: n4168_o = 1'b0; + 63'b000000000000000000000000000000000000000000000100000000000000000: n4168_o = 1'b0; + 63'b000000000000000000000000000000000000000000000010000000000000000: n4168_o = 1'b0; + 63'b000000000000000000000000000000000000000000000001000000000000000: n4168_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000100000000000000: n4168_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000010000000000000: n4168_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000001000000000000: n4168_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000100000000000: n4168_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000010000000000: n4168_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000001000000000: n4168_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000100000000: n4168_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000010000000: n4168_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000001000000: n4168_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000100000: n4168_o = n2436_o; + 63'b000000000000000000000000000000000000000000000000000000000010000: n4168_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000001000: n4168_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000000100: n4168_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000000010: n4168_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000000001: n4168_o = 1'b0; + default: n4168_o = 1'b0; + endcase + /* decoder.vhd:635:5 */ + always @* + case (n4151_o) + 63'b100000000000000000000000000000000000000000000000000000000000000: n4171_o = 1'b0; + 63'b010000000000000000000000000000000000000000000000000000000000000: n4171_o = 1'b0; + 63'b001000000000000000000000000000000000000000000000000000000000000: n4171_o = 1'b0; + 63'b000100000000000000000000000000000000000000000000000000000000000: n4171_o = 1'b0; + 63'b000010000000000000000000000000000000000000000000000000000000000: n4171_o = 1'b0; + 63'b000001000000000000000000000000000000000000000000000000000000000: n4171_o = 1'b0; + 63'b000000100000000000000000000000000000000000000000000000000000000: n4171_o = 1'b0; + 63'b000000010000000000000000000000000000000000000000000000000000000: n4171_o = 1'b0; + 63'b000000001000000000000000000000000000000000000000000000000000000: n4171_o = 1'b0; + 63'b000000000100000000000000000000000000000000000000000000000000000: n4171_o = 1'b0; + 63'b000000000010000000000000000000000000000000000000000000000000000: n4171_o = 1'b0; + 63'b000000000001000000000000000000000000000000000000000000000000000: n4171_o = 1'b0; + 63'b000000000000100000000000000000000000000000000000000000000000000: n4171_o = 1'b0; + 63'b000000000000010000000000000000000000000000000000000000000000000: n4171_o = 1'b0; + 63'b000000000000001000000000000000000000000000000000000000000000000: n4171_o = 1'b0; + 63'b000000000000000100000000000000000000000000000000000000000000000: n4171_o = 1'b0; + 63'b000000000000000010000000000000000000000000000000000000000000000: n4171_o = 1'b0; + 63'b000000000000000001000000000000000000000000000000000000000000000: n4171_o = 1'b0; + 63'b000000000000000000100000000000000000000000000000000000000000000: n4171_o = 1'b0; + 63'b000000000000000000010000000000000000000000000000000000000000000: n4171_o = 1'b0; + 63'b000000000000000000001000000000000000000000000000000000000000000: n4171_o = 1'b0; + 63'b000000000000000000000100000000000000000000000000000000000000000: n4171_o = 1'b0; + 63'b000000000000000000000010000000000000000000000000000000000000000: n4171_o = 1'b0; + 63'b000000000000000000000001000000000000000000000000000000000000000: n4171_o = 1'b0; + 63'b000000000000000000000000100000000000000000000000000000000000000: n4171_o = 1'b0; + 63'b000000000000000000000000010000000000000000000000000000000000000: n4171_o = 1'b0; + 63'b000000000000000000000000001000000000000000000000000000000000000: n4171_o = 1'b0; + 63'b000000000000000000000000000100000000000000000000000000000000000: n4171_o = 1'b0; + 63'b000000000000000000000000000010000000000000000000000000000000000: n4171_o = 1'b0; + 63'b000000000000000000000000000001000000000000000000000000000000000: n4171_o = 1'b0; + 63'b000000000000000000000000000000100000000000000000000000000000000: n4171_o = 1'b0; + 63'b000000000000000000000000000000010000000000000000000000000000000: n4171_o = 1'b0; + 63'b000000000000000000000000000000001000000000000000000000000000000: n4171_o = 1'b0; + 63'b000000000000000000000000000000000100000000000000000000000000000: n4171_o = 1'b0; + 63'b000000000000000000000000000000000010000000000000000000000000000: n4171_o = 1'b0; + 63'b000000000000000000000000000000000001000000000000000000000000000: n4171_o = 1'b0; + 63'b000000000000000000000000000000000000100000000000000000000000000: n4171_o = 1'b0; + 63'b000000000000000000000000000000000000010000000000000000000000000: n4171_o = 1'b0; + 63'b000000000000000000000000000000000000001000000000000000000000000: n4171_o = 1'b0; + 63'b000000000000000000000000000000000000000100000000000000000000000: n4171_o = 1'b0; + 63'b000000000000000000000000000000000000000010000000000000000000000: n4171_o = 1'b0; + 63'b000000000000000000000000000000000000000001000000000000000000000: n4171_o = 1'b0; + 63'b000000000000000000000000000000000000000000100000000000000000000: n4171_o = 1'b0; + 63'b000000000000000000000000000000000000000000010000000000000000000: n4171_o = 1'b0; + 63'b000000000000000000000000000000000000000000001000000000000000000: n4171_o = 1'b0; + 63'b000000000000000000000000000000000000000000000100000000000000000: n4171_o = n2733_o; + 63'b000000000000000000000000000000000000000000000010000000000000000: n4171_o = 1'b0; + 63'b000000000000000000000000000000000000000000000001000000000000000: n4171_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000100000000000000: n4171_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000010000000000000: n4171_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000001000000000000: n4171_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000100000000000: n4171_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000010000000000: n4171_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000001000000000: n4171_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000100000000: n4171_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000010000000: n4171_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000001000000: n4171_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000100000: n4171_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000010000: n4171_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000001000: n4171_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000000100: n4171_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000000010: n4171_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000000001: n4171_o = 1'b0; + default: n4171_o = 1'b0; + endcase + /* decoder.vhd:635:5 */ + always @* + case (n4151_o) + 63'b100000000000000000000000000000000000000000000000000000000000000: n4174_o = 1'b0; + 63'b010000000000000000000000000000000000000000000000000000000000000: n4174_o = 1'b0; + 63'b001000000000000000000000000000000000000000000000000000000000000: n4174_o = 1'b0; + 63'b000100000000000000000000000000000000000000000000000000000000000: n4174_o = 1'b0; + 63'b000010000000000000000000000000000000000000000000000000000000000: n4174_o = 1'b0; + 63'b000001000000000000000000000000000000000000000000000000000000000: n4174_o = 1'b0; + 63'b000000100000000000000000000000000000000000000000000000000000000: n4174_o = 1'b0; + 63'b000000010000000000000000000000000000000000000000000000000000000: n4174_o = 1'b0; + 63'b000000001000000000000000000000000000000000000000000000000000000: n4174_o = 1'b0; + 63'b000000000100000000000000000000000000000000000000000000000000000: n4174_o = 1'b0; + 63'b000000000010000000000000000000000000000000000000000000000000000: n4174_o = 1'b0; + 63'b000000000001000000000000000000000000000000000000000000000000000: n4174_o = 1'b0; + 63'b000000000000100000000000000000000000000000000000000000000000000: n4174_o = 1'b0; + 63'b000000000000010000000000000000000000000000000000000000000000000: n4174_o = 1'b0; + 63'b000000000000001000000000000000000000000000000000000000000000000: n4174_o = 1'b0; + 63'b000000000000000100000000000000000000000000000000000000000000000: n4174_o = 1'b0; + 63'b000000000000000010000000000000000000000000000000000000000000000: n4174_o = 1'b0; + 63'b000000000000000001000000000000000000000000000000000000000000000: n4174_o = 1'b0; + 63'b000000000000000000100000000000000000000000000000000000000000000: n4174_o = 1'b0; + 63'b000000000000000000010000000000000000000000000000000000000000000: n4174_o = 1'b0; + 63'b000000000000000000001000000000000000000000000000000000000000000: n4174_o = 1'b0; + 63'b000000000000000000000100000000000000000000000000000000000000000: n4174_o = 1'b0; + 63'b000000000000000000000010000000000000000000000000000000000000000: n4174_o = 1'b0; + 63'b000000000000000000000001000000000000000000000000000000000000000: n4174_o = 1'b0; + 63'b000000000000000000000000100000000000000000000000000000000000000: n4174_o = 1'b0; + 63'b000000000000000000000000010000000000000000000000000000000000000: n4174_o = 1'b0; + 63'b000000000000000000000000001000000000000000000000000000000000000: n4174_o = 1'b0; + 63'b000000000000000000000000000100000000000000000000000000000000000: n4174_o = 1'b0; + 63'b000000000000000000000000000010000000000000000000000000000000000: n4174_o = 1'b0; + 63'b000000000000000000000000000001000000000000000000000000000000000: n4174_o = 1'b0; + 63'b000000000000000000000000000000100000000000000000000000000000000: n4174_o = 1'b0; + 63'b000000000000000000000000000000010000000000000000000000000000000: n4174_o = 1'b0; + 63'b000000000000000000000000000000001000000000000000000000000000000: n4174_o = 1'b0; + 63'b000000000000000000000000000000000100000000000000000000000000000: n4174_o = 1'b0; + 63'b000000000000000000000000000000000010000000000000000000000000000: n4174_o = 1'b0; + 63'b000000000000000000000000000000000001000000000000000000000000000: n4174_o = 1'b0; + 63'b000000000000000000000000000000000000100000000000000000000000000: n4174_o = 1'b0; + 63'b000000000000000000000000000000000000010000000000000000000000000: n4174_o = 1'b0; + 63'b000000000000000000000000000000000000001000000000000000000000000: n4174_o = 1'b0; + 63'b000000000000000000000000000000000000000100000000000000000000000: n4174_o = 1'b0; + 63'b000000000000000000000000000000000000000010000000000000000000000: n4174_o = 1'b0; + 63'b000000000000000000000000000000000000000001000000000000000000000: n4174_o = 1'b0; + 63'b000000000000000000000000000000000000000000100000000000000000000: n4174_o = 1'b0; + 63'b000000000000000000000000000000000000000000010000000000000000000: n4174_o = 1'b0; + 63'b000000000000000000000000000000000000000000001000000000000000000: n4174_o = 1'b0; + 63'b000000000000000000000000000000000000000000000100000000000000000: n4174_o = n2735_o; + 63'b000000000000000000000000000000000000000000000010000000000000000: n4174_o = 1'b0; + 63'b000000000000000000000000000000000000000000000001000000000000000: n4174_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000100000000000000: n4174_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000010000000000000: n4174_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000001000000000000: n4174_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000100000000000: n4174_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000010000000000: n4174_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000001000000000: n4174_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000100000000: n4174_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000010000000: n4174_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000001000000: n4174_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000100000: n4174_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000010000: n4174_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000001000: n4174_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000000100: n4174_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000000010: n4174_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000000001: n4174_o = 1'b0; + default: n4174_o = 1'b0; + endcase + /* decoder.vhd:635:5 */ + always @* + case (n4151_o) + 63'b100000000000000000000000000000000000000000000000000000000000000: n4177_o = 1'b0; + 63'b010000000000000000000000000000000000000000000000000000000000000: n4177_o = 1'b0; + 63'b001000000000000000000000000000000000000000000000000000000000000: n4177_o = 1'b0; + 63'b000100000000000000000000000000000000000000000000000000000000000: n4177_o = 1'b0; + 63'b000010000000000000000000000000000000000000000000000000000000000: n4177_o = 1'b0; + 63'b000001000000000000000000000000000000000000000000000000000000000: n4177_o = 1'b0; + 63'b000000100000000000000000000000000000000000000000000000000000000: n4177_o = 1'b0; + 63'b000000010000000000000000000000000000000000000000000000000000000: n4177_o = 1'b0; + 63'b000000001000000000000000000000000000000000000000000000000000000: n4177_o = 1'b0; + 63'b000000000100000000000000000000000000000000000000000000000000000: n4177_o = 1'b0; + 63'b000000000010000000000000000000000000000000000000000000000000000: n4177_o = 1'b0; + 63'b000000000001000000000000000000000000000000000000000000000000000: n4177_o = 1'b0; + 63'b000000000000100000000000000000000000000000000000000000000000000: n4177_o = 1'b0; + 63'b000000000000010000000000000000000000000000000000000000000000000: n4177_o = 1'b0; + 63'b000000000000001000000000000000000000000000000000000000000000000: n4177_o = 1'b0; + 63'b000000000000000100000000000000000000000000000000000000000000000: n4177_o = 1'b0; + 63'b000000000000000010000000000000000000000000000000000000000000000: n4177_o = 1'b0; + 63'b000000000000000001000000000000000000000000000000000000000000000: n4177_o = 1'b0; + 63'b000000000000000000100000000000000000000000000000000000000000000: n4177_o = 1'b0; + 63'b000000000000000000010000000000000000000000000000000000000000000: n4177_o = 1'b0; + 63'b000000000000000000001000000000000000000000000000000000000000000: n4177_o = 1'b0; + 63'b000000000000000000000100000000000000000000000000000000000000000: n4177_o = 1'b0; + 63'b000000000000000000000010000000000000000000000000000000000000000: n4177_o = n3331_o; + 63'b000000000000000000000001000000000000000000000000000000000000000: n4177_o = 1'b0; + 63'b000000000000000000000000100000000000000000000000000000000000000: n4177_o = 1'b0; + 63'b000000000000000000000000010000000000000000000000000000000000000: n4177_o = 1'b0; + 63'b000000000000000000000000001000000000000000000000000000000000000: n4177_o = 1'b0; + 63'b000000000000000000000000000100000000000000000000000000000000000: n4177_o = 1'b0; + 63'b000000000000000000000000000010000000000000000000000000000000000: n4177_o = 1'b0; + 63'b000000000000000000000000000001000000000000000000000000000000000: n4177_o = 1'b0; + 63'b000000000000000000000000000000100000000000000000000000000000000: n4177_o = 1'b0; + 63'b000000000000000000000000000000010000000000000000000000000000000: n4177_o = 1'b0; + 63'b000000000000000000000000000000001000000000000000000000000000000: n4177_o = 1'b0; + 63'b000000000000000000000000000000000100000000000000000000000000000: n4177_o = 1'b0; + 63'b000000000000000000000000000000000010000000000000000000000000000: n4177_o = 1'b0; + 63'b000000000000000000000000000000000001000000000000000000000000000: n4177_o = 1'b0; + 63'b000000000000000000000000000000000000100000000000000000000000000: n4177_o = 1'b0; + 63'b000000000000000000000000000000000000010000000000000000000000000: n4177_o = 1'b0; + 63'b000000000000000000000000000000000000001000000000000000000000000: n4177_o = 1'b0; + 63'b000000000000000000000000000000000000000100000000000000000000000: n4177_o = 1'b0; + 63'b000000000000000000000000000000000000000010000000000000000000000: n4177_o = 1'b0; + 63'b000000000000000000000000000000000000000001000000000000000000000: n4177_o = 1'b0; + 63'b000000000000000000000000000000000000000000100000000000000000000: n4177_o = 1'b0; + 63'b000000000000000000000000000000000000000000010000000000000000000: n4177_o = 1'b0; + 63'b000000000000000000000000000000000000000000001000000000000000000: n4177_o = 1'b0; + 63'b000000000000000000000000000000000000000000000100000000000000000: n4177_o = 1'b0; + 63'b000000000000000000000000000000000000000000000010000000000000000: n4177_o = 1'b0; + 63'b000000000000000000000000000000000000000000000001000000000000000: n4177_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000100000000000000: n4177_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000010000000000000: n4177_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000001000000000000: n4177_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000100000000000: n4177_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000010000000000: n4177_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000001000000000: n4177_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000100000000: n4177_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000010000000: n4177_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000001000000: n4177_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000100000: n4177_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000010000: n4177_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000001000: n4177_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000000100: n4177_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000000010: n4177_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000000001: n4177_o = 1'b0; + default: n4177_o = 1'b0; + endcase + /* decoder.vhd:635:5 */ + always @* + case (n4151_o) + 63'b100000000000000000000000000000000000000000000000000000000000000: n4179_o = n2030_o; + 63'b010000000000000000000000000000000000000000000000000000000000000: n4179_o = n4110_o; + 63'b001000000000000000000000000000000000000000000000000000000000000: n4179_o = n4056_o; + 63'b000100000000000000000000000000000000000000000000000000000000000: n4179_o = n2030_o; + 63'b000010000000000000000000000000000000000000000000000000000000000: n4179_o = n2030_o; + 63'b000001000000000000000000000000000000000000000000000000000000000: n4179_o = n2030_o; + 63'b000000100000000000000000000000000000000000000000000000000000000: n4179_o = n2030_o; + 63'b000000010000000000000000000000000000000000000000000000000000000: n4179_o = n2030_o; + 63'b000000001000000000000000000000000000000000000000000000000000000: n4179_o = n2030_o; + 63'b000000000100000000000000000000000000000000000000000000000000000: n4179_o = n2030_o; + 63'b000000000010000000000000000000000000000000000000000000000000000: n4179_o = n3881_o; + 63'b000000000001000000000000000000000000000000000000000000000000000: n4179_o = n2030_o; + 63'b000000000000100000000000000000000000000000000000000000000000000: n4179_o = n2030_o; + 63'b000000000000010000000000000000000000000000000000000000000000000: n4179_o = n2030_o; + 63'b000000000000001000000000000000000000000000000000000000000000000: n4179_o = n2030_o; + 63'b000000000000000100000000000000000000000000000000000000000000000: n4179_o = n3630_o; + 63'b000000000000000010000000000000000000000000000000000000000000000: n4179_o = n2030_o; + 63'b000000000000000001000000000000000000000000000000000000000000000: n4179_o = n2030_o; + 63'b000000000000000000100000000000000000000000000000000000000000000: n4179_o = n2030_o; + 63'b000000000000000000010000000000000000000000000000000000000000000: n4179_o = n2030_o; + 63'b000000000000000000001000000000000000000000000000000000000000000: n4179_o = n2030_o; + 63'b000000000000000000000100000000000000000000000000000000000000000: n4179_o = n2030_o; + 63'b000000000000000000000010000000000000000000000000000000000000000: n4179_o = n2030_o; + 63'b000000000000000000000001000000000000000000000000000000000000000: n4179_o = n3304_o; + 63'b000000000000000000000000100000000000000000000000000000000000000: n4179_o = n3280_o; + 63'b000000000000000000000000010000000000000000000000000000000000000: n4179_o = n2030_o; + 63'b000000000000000000000000001000000000000000000000000000000000000: n4179_o = n2030_o; + 63'b000000000000000000000000000100000000000000000000000000000000000: n4179_o = n3221_o; + 63'b000000000000000000000000000010000000000000000000000000000000000: n4179_o = n2030_o; + 63'b000000000000000000000000000001000000000000000000000000000000000: n4179_o = n2030_o; + 63'b000000000000000000000000000000100000000000000000000000000000000: n4179_o = n2030_o; + 63'b000000000000000000000000000000010000000000000000000000000000000: n4179_o = n2030_o; + 63'b000000000000000000000000000000001000000000000000000000000000000: n4179_o = n2030_o; + 63'b000000000000000000000000000000000100000000000000000000000000000: n4179_o = n2030_o; + 63'b000000000000000000000000000000000010000000000000000000000000000: n4179_o = n2030_o; + 63'b000000000000000000000000000000000001000000000000000000000000000: n4179_o = n2030_o; + 63'b000000000000000000000000000000000000100000000000000000000000000: n4179_o = n2030_o; + 63'b000000000000000000000000000000000000010000000000000000000000000: n4179_o = n2030_o; + 63'b000000000000000000000000000000000000001000000000000000000000000: n4179_o = n2030_o; + 63'b000000000000000000000000000000000000000100000000000000000000000: n4179_o = n2030_o; + 63'b000000000000000000000000000000000000000010000000000000000000000: n4179_o = n2835_o; + 63'b000000000000000000000000000000000000000001000000000000000000000: n4179_o = n2030_o; + 63'b000000000000000000000000000000000000000000100000000000000000000: n4179_o = n2030_o; + 63'b000000000000000000000000000000000000000000010000000000000000000: n4179_o = n2030_o; + 63'b000000000000000000000000000000000000000000001000000000000000000: n4179_o = n2030_o; + 63'b000000000000000000000000000000000000000000000100000000000000000: n4179_o = n2030_o; + 63'b000000000000000000000000000000000000000000000010000000000000000: n4179_o = n2030_o; + 63'b000000000000000000000000000000000000000000000001000000000000000: n4179_o = n2030_o; + 63'b000000000000000000000000000000000000000000000000100000000000000: n4179_o = n2030_o; + 63'b000000000000000000000000000000000000000000000000010000000000000: n4179_o = n2030_o; + 63'b000000000000000000000000000000000000000000000000001000000000000: n4179_o = n2030_o; + 63'b000000000000000000000000000000000000000000000000000100000000000: n4179_o = n2030_o; + 63'b000000000000000000000000000000000000000000000000000010000000000: n4179_o = n2030_o; + 63'b000000000000000000000000000000000000000000000000000001000000000: n4179_o = n2030_o; + 63'b000000000000000000000000000000000000000000000000000000100000000: n4179_o = n2030_o; + 63'b000000000000000000000000000000000000000000000000000000010000000: n4179_o = n2030_o; + 63'b000000000000000000000000000000000000000000000000000000001000000: n4179_o = n2030_o; + 63'b000000000000000000000000000000000000000000000000000000000100000: n4179_o = n2437_o; + 63'b000000000000000000000000000000000000000000000000000000000010000: n4179_o = n2030_o; + 63'b000000000000000000000000000000000000000000000000000000000001000: n4179_o = n2030_o; + 63'b000000000000000000000000000000000000000000000000000000000000100: n4179_o = n2195_o; + 63'b000000000000000000000000000000000000000000000000000000000000010: n4179_o = n2030_o; + 63'b000000000000000000000000000000000000000000000000000000000000001: n4179_o = n2083_o; + default: n4179_o = n2030_o; + endcase + /* decoder.vhd:635:5 */ + always @* + case (n4151_o) + 63'b100000000000000000000000000000000000000000000000000000000000000: n4181_o = 1'b0; + 63'b010000000000000000000000000000000000000000000000000000000000000: n4181_o = n4113_o; + 63'b001000000000000000000000000000000000000000000000000000000000000: n4181_o = n4059_o; + 63'b000100000000000000000000000000000000000000000000000000000000000: n4181_o = 1'b0; + 63'b000010000000000000000000000000000000000000000000000000000000000: n4181_o = 1'b0; + 63'b000001000000000000000000000000000000000000000000000000000000000: n4181_o = 1'b0; + 63'b000000100000000000000000000000000000000000000000000000000000000: n4181_o = 1'b0; + 63'b000000010000000000000000000000000000000000000000000000000000000: n4181_o = 1'b0; + 63'b000000001000000000000000000000000000000000000000000000000000000: n4181_o = 1'b0; + 63'b000000000100000000000000000000000000000000000000000000000000000: n4181_o = 1'b0; + 63'b000000000010000000000000000000000000000000000000000000000000000: n4181_o = n3882_o; + 63'b000000000001000000000000000000000000000000000000000000000000000: n4181_o = 1'b0; + 63'b000000000000100000000000000000000000000000000000000000000000000: n4181_o = 1'b0; + 63'b000000000000010000000000000000000000000000000000000000000000000: n4181_o = 1'b0; + 63'b000000000000001000000000000000000000000000000000000000000000000: n4181_o = 1'b0; + 63'b000000000000000100000000000000000000000000000000000000000000000: n4181_o = n3633_o; + 63'b000000000000000010000000000000000000000000000000000000000000000: n4181_o = 1'b0; + 63'b000000000000000001000000000000000000000000000000000000000000000: n4181_o = n3581_o; + 63'b000000000000000000100000000000000000000000000000000000000000000: n4181_o = 1'b0; + 63'b000000000000000000010000000000000000000000000000000000000000000: n4181_o = 1'b0; + 63'b000000000000000000001000000000000000000000000000000000000000000: n4181_o = 1'b0; + 63'b000000000000000000000100000000000000000000000000000000000000000: n4181_o = 1'b0; + 63'b000000000000000000000010000000000000000000000000000000000000000: n4181_o = 1'b0; + 63'b000000000000000000000001000000000000000000000000000000000000000: n4181_o = n3313_o; + 63'b000000000000000000000000100000000000000000000000000000000000000: n4181_o = n3282_o; + 63'b000000000000000000000000010000000000000000000000000000000000000: n4181_o = 1'b0; + 63'b000000000000000000000000001000000000000000000000000000000000000: n4181_o = 1'b0; + 63'b000000000000000000000000000100000000000000000000000000000000000: n4181_o = n3224_o; + 63'b000000000000000000000000000010000000000000000000000000000000000: n4181_o = 1'b0; + 63'b000000000000000000000000000001000000000000000000000000000000000: n4181_o = 1'b0; + 63'b000000000000000000000000000000100000000000000000000000000000000: n4181_o = 1'b0; + 63'b000000000000000000000000000000010000000000000000000000000000000: n4181_o = 1'b0; + 63'b000000000000000000000000000000001000000000000000000000000000000: n4181_o = 1'b0; + 63'b000000000000000000000000000000000100000000000000000000000000000: n4181_o = 1'b0; + 63'b000000000000000000000000000000000010000000000000000000000000000: n4181_o = 1'b0; + 63'b000000000000000000000000000000000001000000000000000000000000000: n4181_o = 1'b0; + 63'b000000000000000000000000000000000000100000000000000000000000000: n4181_o = 1'b0; + 63'b000000000000000000000000000000000000010000000000000000000000000: n4181_o = 1'b0; + 63'b000000000000000000000000000000000000001000000000000000000000000: n4181_o = 1'b0; + 63'b000000000000000000000000000000000000000100000000000000000000000: n4181_o = 1'b0; + 63'b000000000000000000000000000000000000000010000000000000000000000: n4181_o = n2837_o; + 63'b000000000000000000000000000000000000000001000000000000000000000: n4181_o = 1'b0; + 63'b000000000000000000000000000000000000000000100000000000000000000: n4181_o = 1'b0; + 63'b000000000000000000000000000000000000000000010000000000000000000: n4181_o = 1'b0; + 63'b000000000000000000000000000000000000000000001000000000000000000: n4181_o = 1'b0; + 63'b000000000000000000000000000000000000000000000100000000000000000: n4181_o = 1'b0; + 63'b000000000000000000000000000000000000000000000010000000000000000: n4181_o = n2705_o; + 63'b000000000000000000000000000000000000000000000001000000000000000: n4181_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000100000000000000: n4181_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000010000000000000: n4181_o = n2620_o; + 63'b000000000000000000000000000000000000000000000000001000000000000: n4181_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000100000000000: n4181_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000010000000000: n4181_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000001000000000: n4181_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000100000000: n4181_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000010000000: n4181_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000001000000: n4181_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000100000: n4181_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000010000: n4181_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000001000: n4181_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000000100: n4181_o = n2198_o; + 63'b000000000000000000000000000000000000000000000000000000000000010: n4181_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000000001: n4181_o = n2086_o; + default: n4181_o = 1'b0; + endcase + /* decoder.vhd:635:5 */ + always @* + case (n4151_o) + 63'b100000000000000000000000000000000000000000000000000000000000000: n4184_o = 1'b0; + 63'b010000000000000000000000000000000000000000000000000000000000000: n4184_o = 1'b0; + 63'b001000000000000000000000000000000000000000000000000000000000000: n4184_o = 1'b0; + 63'b000100000000000000000000000000000000000000000000000000000000000: n4184_o = 1'b0; + 63'b000010000000000000000000000000000000000000000000000000000000000: n4184_o = 1'b0; + 63'b000001000000000000000000000000000000000000000000000000000000000: n4184_o = 1'b0; + 63'b000000100000000000000000000000000000000000000000000000000000000: n4184_o = 1'b0; + 63'b000000010000000000000000000000000000000000000000000000000000000: n4184_o = 1'b0; + 63'b000000001000000000000000000000000000000000000000000000000000000: n4184_o = 1'b0; + 63'b000000000100000000000000000000000000000000000000000000000000000: n4184_o = 1'b0; + 63'b000000000010000000000000000000000000000000000000000000000000000: n4184_o = 1'b0; + 63'b000000000001000000000000000000000000000000000000000000000000000: n4184_o = n3824_o; + 63'b000000000000100000000000000000000000000000000000000000000000000: n4184_o = 1'b0; + 63'b000000000000010000000000000000000000000000000000000000000000000: n4184_o = n3766_o; + 63'b000000000000001000000000000000000000000000000000000000000000000: n4184_o = 1'b0; + 63'b000000000000000100000000000000000000000000000000000000000000000: n4184_o = 1'b0; + 63'b000000000000000010000000000000000000000000000000000000000000000: n4184_o = 1'b0; + 63'b000000000000000001000000000000000000000000000000000000000000000: n4184_o = 1'b0; + 63'b000000000000000000100000000000000000000000000000000000000000000: n4184_o = 1'b0; + 63'b000000000000000000010000000000000000000000000000000000000000000: n4184_o = 1'b0; + 63'b000000000000000000001000000000000000000000000000000000000000000: n4184_o = 1'b0; + 63'b000000000000000000000100000000000000000000000000000000000000000: n4184_o = 1'b0; + 63'b000000000000000000000010000000000000000000000000000000000000000: n4184_o = 1'b0; + 63'b000000000000000000000001000000000000000000000000000000000000000: n4184_o = 1'b0; + 63'b000000000000000000000000100000000000000000000000000000000000000: n4184_o = 1'b0; + 63'b000000000000000000000000010000000000000000000000000000000000000: n4184_o = 1'b0; + 63'b000000000000000000000000001000000000000000000000000000000000000: n4184_o = 1'b0; + 63'b000000000000000000000000000100000000000000000000000000000000000: n4184_o = 1'b0; + 63'b000000000000000000000000000010000000000000000000000000000000000: n4184_o = 1'b0; + 63'b000000000000000000000000000001000000000000000000000000000000000: n4184_o = 1'b0; + 63'b000000000000000000000000000000100000000000000000000000000000000: n4184_o = 1'b0; + 63'b000000000000000000000000000000010000000000000000000000000000000: n4184_o = 1'b0; + 63'b000000000000000000000000000000001000000000000000000000000000000: n4184_o = 1'b0; + 63'b000000000000000000000000000000000100000000000000000000000000000: n4184_o = 1'b0; + 63'b000000000000000000000000000000000010000000000000000000000000000: n4184_o = 1'b0; + 63'b000000000000000000000000000000000001000000000000000000000000000: n4184_o = 1'b0; + 63'b000000000000000000000000000000000000100000000000000000000000000: n4184_o = 1'b0; + 63'b000000000000000000000000000000000000010000000000000000000000000: n4184_o = 1'b0; + 63'b000000000000000000000000000000000000001000000000000000000000000: n4184_o = 1'b0; + 63'b000000000000000000000000000000000000000100000000000000000000000: n4184_o = 1'b0; + 63'b000000000000000000000000000000000000000010000000000000000000000: n4184_o = 1'b0; + 63'b000000000000000000000000000000000000000001000000000000000000000: n4184_o = 1'b0; + 63'b000000000000000000000000000000000000000000100000000000000000000: n4184_o = 1'b0; + 63'b000000000000000000000000000000000000000000010000000000000000000: n4184_o = 1'b0; + 63'b000000000000000000000000000000000000000000001000000000000000000: n4184_o = 1'b0; + 63'b000000000000000000000000000000000000000000000100000000000000000: n4184_o = 1'b0; + 63'b000000000000000000000000000000000000000000000010000000000000000: n4184_o = 1'b0; + 63'b000000000000000000000000000000000000000000000001000000000000000: n4184_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000100000000000000: n4184_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000010000000000000: n4184_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000001000000000000: n4184_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000100000000000: n4184_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000010000000000: n4184_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000001000000000: n4184_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000100000000: n4184_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000010000000: n4184_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000001000000: n4184_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000100000: n4184_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000010000: n4184_o = n2331_o; + 63'b000000000000000000000000000000000000000000000000000000000001000: n4184_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000000100: n4184_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000000010: n4184_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000000001: n4184_o = 1'b0; + default: n4184_o = 1'b0; + endcase + /* decoder.vhd:635:5 */ + always @* + case (n4151_o) + 63'b100000000000000000000000000000000000000000000000000000000000000: n4187_o = 1'b0; + 63'b010000000000000000000000000000000000000000000000000000000000000: n4187_o = 1'b0; + 63'b001000000000000000000000000000000000000000000000000000000000000: n4187_o = 1'b0; + 63'b000100000000000000000000000000000000000000000000000000000000000: n4187_o = 1'b0; + 63'b000010000000000000000000000000000000000000000000000000000000000: n4187_o = 1'b0; + 63'b000001000000000000000000000000000000000000000000000000000000000: n4187_o = 1'b0; + 63'b000000100000000000000000000000000000000000000000000000000000000: n4187_o = 1'b0; + 63'b000000010000000000000000000000000000000000000000000000000000000: n4187_o = 1'b0; + 63'b000000001000000000000000000000000000000000000000000000000000000: n4187_o = 1'b0; + 63'b000000000100000000000000000000000000000000000000000000000000000: n4187_o = 1'b0; + 63'b000000000010000000000000000000000000000000000000000000000000000: n4187_o = 1'b0; + 63'b000000000001000000000000000000000000000000000000000000000000000: n4187_o = 1'b0; + 63'b000000000000100000000000000000000000000000000000000000000000000: n4187_o = 1'b0; + 63'b000000000000010000000000000000000000000000000000000000000000000: n4187_o = n3768_o; + 63'b000000000000001000000000000000000000000000000000000000000000000: n4187_o = 1'b0; + 63'b000000000000000100000000000000000000000000000000000000000000000: n4187_o = 1'b0; + 63'b000000000000000010000000000000000000000000000000000000000000000: n4187_o = 1'b0; + 63'b000000000000000001000000000000000000000000000000000000000000000: n4187_o = 1'b0; + 63'b000000000000000000100000000000000000000000000000000000000000000: n4187_o = 1'b0; + 63'b000000000000000000010000000000000000000000000000000000000000000: n4187_o = 1'b0; + 63'b000000000000000000001000000000000000000000000000000000000000000: n4187_o = 1'b0; + 63'b000000000000000000000100000000000000000000000000000000000000000: n4187_o = 1'b0; + 63'b000000000000000000000010000000000000000000000000000000000000000: n4187_o = 1'b0; + 63'b000000000000000000000001000000000000000000000000000000000000000: n4187_o = 1'b0; + 63'b000000000000000000000000100000000000000000000000000000000000000: n4187_o = 1'b0; + 63'b000000000000000000000000010000000000000000000000000000000000000: n4187_o = 1'b0; + 63'b000000000000000000000000001000000000000000000000000000000000000: n4187_o = 1'b0; + 63'b000000000000000000000000000100000000000000000000000000000000000: n4187_o = 1'b0; + 63'b000000000000000000000000000010000000000000000000000000000000000: n4187_o = 1'b0; + 63'b000000000000000000000000000001000000000000000000000000000000000: n4187_o = 1'b0; + 63'b000000000000000000000000000000100000000000000000000000000000000: n4187_o = 1'b0; + 63'b000000000000000000000000000000010000000000000000000000000000000: n4187_o = 1'b0; + 63'b000000000000000000000000000000001000000000000000000000000000000: n4187_o = 1'b0; + 63'b000000000000000000000000000000000100000000000000000000000000000: n4187_o = 1'b0; + 63'b000000000000000000000000000000000010000000000000000000000000000: n4187_o = 1'b0; + 63'b000000000000000000000000000000000001000000000000000000000000000: n4187_o = 1'b0; + 63'b000000000000000000000000000000000000100000000000000000000000000: n4187_o = 1'b0; + 63'b000000000000000000000000000000000000010000000000000000000000000: n4187_o = 1'b0; + 63'b000000000000000000000000000000000000001000000000000000000000000: n4187_o = 1'b0; + 63'b000000000000000000000000000000000000000100000000000000000000000: n4187_o = 1'b0; + 63'b000000000000000000000000000000000000000010000000000000000000000: n4187_o = 1'b0; + 63'b000000000000000000000000000000000000000001000000000000000000000: n4187_o = 1'b0; + 63'b000000000000000000000000000000000000000000100000000000000000000: n4187_o = 1'b0; + 63'b000000000000000000000000000000000000000000010000000000000000000: n4187_o = n2760_o; + 63'b000000000000000000000000000000000000000000001000000000000000000: n4187_o = 1'b0; + 63'b000000000000000000000000000000000000000000000100000000000000000: n4187_o = 1'b0; + 63'b000000000000000000000000000000000000000000000010000000000000000: n4187_o = 1'b0; + 63'b000000000000000000000000000000000000000000000001000000000000000: n4187_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000100000000000000: n4187_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000010000000000000: n4187_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000001000000000000: n4187_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000100000000000: n4187_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000010000000000: n4187_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000001000000000: n4187_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000100000000: n4187_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000010000000: n4187_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000001000000: n4187_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000100000: n4187_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000010000: n4187_o = n2333_o; + 63'b000000000000000000000000000000000000000000000000000000000001000: n4187_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000000100: n4187_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000000010: n4187_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000000001: n4187_o = 1'b0; + default: n4187_o = 1'b0; + endcase + /* decoder.vhd:635:5 */ + always @* + case (n4151_o) + 63'b100000000000000000000000000000000000000000000000000000000000000: n4190_o = 1'b0; + 63'b010000000000000000000000000000000000000000000000000000000000000: n4190_o = 1'b0; + 63'b001000000000000000000000000000000000000000000000000000000000000: n4190_o = 1'b0; + 63'b000100000000000000000000000000000000000000000000000000000000000: n4190_o = 1'b0; + 63'b000010000000000000000000000000000000000000000000000000000000000: n4190_o = 1'b0; + 63'b000001000000000000000000000000000000000000000000000000000000000: n4190_o = 1'b0; + 63'b000000100000000000000000000000000000000000000000000000000000000: n4190_o = 1'b0; + 63'b000000010000000000000000000000000000000000000000000000000000000: n4190_o = 1'b0; + 63'b000000001000000000000000000000000000000000000000000000000000000: n4190_o = 1'b0; + 63'b000000000100000000000000000000000000000000000000000000000000000: n4190_o = 1'b0; + 63'b000000000010000000000000000000000000000000000000000000000000000: n4190_o = 1'b0; + 63'b000000000001000000000000000000000000000000000000000000000000000: n4190_o = n3826_o; + 63'b000000000000100000000000000000000000000000000000000000000000000: n4190_o = 1'b0; + 63'b000000000000010000000000000000000000000000000000000000000000000: n4190_o = n3770_o; + 63'b000000000000001000000000000000000000000000000000000000000000000: n4190_o = 1'b0; + 63'b000000000000000100000000000000000000000000000000000000000000000: n4190_o = 1'b0; + 63'b000000000000000010000000000000000000000000000000000000000000000: n4190_o = 1'b0; + 63'b000000000000000001000000000000000000000000000000000000000000000: n4190_o = 1'b0; + 63'b000000000000000000100000000000000000000000000000000000000000000: n4190_o = 1'b0; + 63'b000000000000000000010000000000000000000000000000000000000000000: n4190_o = 1'b0; + 63'b000000000000000000001000000000000000000000000000000000000000000: n4190_o = 1'b0; + 63'b000000000000000000000100000000000000000000000000000000000000000: n4190_o = 1'b0; + 63'b000000000000000000000010000000000000000000000000000000000000000: n4190_o = 1'b0; + 63'b000000000000000000000001000000000000000000000000000000000000000: n4190_o = 1'b0; + 63'b000000000000000000000000100000000000000000000000000000000000000: n4190_o = 1'b0; + 63'b000000000000000000000000010000000000000000000000000000000000000: n4190_o = 1'b0; + 63'b000000000000000000000000001000000000000000000000000000000000000: n4190_o = 1'b0; + 63'b000000000000000000000000000100000000000000000000000000000000000: n4190_o = 1'b0; + 63'b000000000000000000000000000010000000000000000000000000000000000: n4190_o = 1'b0; + 63'b000000000000000000000000000001000000000000000000000000000000000: n4190_o = 1'b0; + 63'b000000000000000000000000000000100000000000000000000000000000000: n4190_o = 1'b0; + 63'b000000000000000000000000000000010000000000000000000000000000000: n4190_o = 1'b0; + 63'b000000000000000000000000000000001000000000000000000000000000000: n4190_o = 1'b0; + 63'b000000000000000000000000000000000100000000000000000000000000000: n4190_o = 1'b0; + 63'b000000000000000000000000000000000010000000000000000000000000000: n4190_o = 1'b0; + 63'b000000000000000000000000000000000001000000000000000000000000000: n4190_o = 1'b0; + 63'b000000000000000000000000000000000000100000000000000000000000000: n4190_o = 1'b0; + 63'b000000000000000000000000000000000000010000000000000000000000000: n4190_o = 1'b0; + 63'b000000000000000000000000000000000000001000000000000000000000000: n4190_o = 1'b0; + 63'b000000000000000000000000000000000000000100000000000000000000000: n4190_o = 1'b0; + 63'b000000000000000000000000000000000000000010000000000000000000000: n4190_o = 1'b0; + 63'b000000000000000000000000000000000000000001000000000000000000000: n4190_o = 1'b0; + 63'b000000000000000000000000000000000000000000100000000000000000000: n4190_o = 1'b0; + 63'b000000000000000000000000000000000000000000010000000000000000000: n4190_o = 1'b0; + 63'b000000000000000000000000000000000000000000001000000000000000000: n4190_o = 1'b0; + 63'b000000000000000000000000000000000000000000000100000000000000000: n4190_o = 1'b0; + 63'b000000000000000000000000000000000000000000000010000000000000000: n4190_o = 1'b0; + 63'b000000000000000000000000000000000000000000000001000000000000000: n4190_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000100000000000000: n4190_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000010000000000000: n4190_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000001000000000000: n4190_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000100000000000: n4190_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000010000000000: n4190_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000001000000000: n4190_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000100000000: n4190_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000010000000: n4190_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000001000000: n4190_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000100000: n4190_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000010000: n4190_o = n2335_o; + 63'b000000000000000000000000000000000000000000000000000000000001000: n4190_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000000100: n4190_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000000010: n4190_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000000001: n4190_o = 1'b0; + default: n4190_o = 1'b0; + endcase + /* decoder.vhd:635:5 */ + always @* + case (n4151_o) + 63'b100000000000000000000000000000000000000000000000000000000000000: n4193_o = 1'b0; + 63'b010000000000000000000000000000000000000000000000000000000000000: n4193_o = 1'b0; + 63'b001000000000000000000000000000000000000000000000000000000000000: n4193_o = 1'b0; + 63'b000100000000000000000000000000000000000000000000000000000000000: n4193_o = 1'b0; + 63'b000010000000000000000000000000000000000000000000000000000000000: n4193_o = 1'b0; + 63'b000001000000000000000000000000000000000000000000000000000000000: n4193_o = 1'b0; + 63'b000000100000000000000000000000000000000000000000000000000000000: n4193_o = 1'b0; + 63'b000000010000000000000000000000000000000000000000000000000000000: n4193_o = 1'b0; + 63'b000000001000000000000000000000000000000000000000000000000000000: n4193_o = 1'b0; + 63'b000000000100000000000000000000000000000000000000000000000000000: n4193_o = 1'b0; + 63'b000000000010000000000000000000000000000000000000000000000000000: n4193_o = 1'b0; + 63'b000000000001000000000000000000000000000000000000000000000000000: n4193_o = 1'b0; + 63'b000000000000100000000000000000000000000000000000000000000000000: n4193_o = 1'b0; + 63'b000000000000010000000000000000000000000000000000000000000000000: n4193_o = 1'b0; + 63'b000000000000001000000000000000000000000000000000000000000000000: n4193_o = 1'b0; + 63'b000000000000000100000000000000000000000000000000000000000000000: n4193_o = 1'b0; + 63'b000000000000000010000000000000000000000000000000000000000000000: n4193_o = 1'b0; + 63'b000000000000000001000000000000000000000000000000000000000000000: n4193_o = 1'b0; + 63'b000000000000000000100000000000000000000000000000000000000000000: n4193_o = 1'b0; + 63'b000000000000000000010000000000000000000000000000000000000000000: n4193_o = n3481_o; + 63'b000000000000000000001000000000000000000000000000000000000000000: n4193_o = n3420_o; + 63'b000000000000000000000100000000000000000000000000000000000000000: n4193_o = 1'b0; + 63'b000000000000000000000010000000000000000000000000000000000000000: n4193_o = 1'b0; + 63'b000000000000000000000001000000000000000000000000000000000000000: n4193_o = 1'b0; + 63'b000000000000000000000000100000000000000000000000000000000000000: n4193_o = 1'b0; + 63'b000000000000000000000000010000000000000000000000000000000000000: n4193_o = 1'b0; + 63'b000000000000000000000000001000000000000000000000000000000000000: n4193_o = 1'b0; + 63'b000000000000000000000000000100000000000000000000000000000000000: n4193_o = 1'b0; + 63'b000000000000000000000000000010000000000000000000000000000000000: n4193_o = 1'b0; + 63'b000000000000000000000000000001000000000000000000000000000000000: n4193_o = 1'b0; + 63'b000000000000000000000000000000100000000000000000000000000000000: n4193_o = 1'b0; + 63'b000000000000000000000000000000010000000000000000000000000000000: n4193_o = 1'b0; + 63'b000000000000000000000000000000001000000000000000000000000000000: n4193_o = 1'b0; + 63'b000000000000000000000000000000000100000000000000000000000000000: n4193_o = 1'b0; + 63'b000000000000000000000000000000000010000000000000000000000000000: n4193_o = 1'b0; + 63'b000000000000000000000000000000000001000000000000000000000000000: n4193_o = 1'b0; + 63'b000000000000000000000000000000000000100000000000000000000000000: n4193_o = 1'b0; + 63'b000000000000000000000000000000000000010000000000000000000000000: n4193_o = 1'b0; + 63'b000000000000000000000000000000000000001000000000000000000000000: n4193_o = 1'b0; + 63'b000000000000000000000000000000000000000100000000000000000000000: n4193_o = 1'b0; + 63'b000000000000000000000000000000000000000010000000000000000000000: n4193_o = 1'b0; + 63'b000000000000000000000000000000000000000001000000000000000000000: n4193_o = 1'b0; + 63'b000000000000000000000000000000000000000000100000000000000000000: n4193_o = 1'b0; + 63'b000000000000000000000000000000000000000000010000000000000000000: n4193_o = 1'b0; + 63'b000000000000000000000000000000000000000000001000000000000000000: n4193_o = 1'b0; + 63'b000000000000000000000000000000000000000000000100000000000000000: n4193_o = 1'b0; + 63'b000000000000000000000000000000000000000000000010000000000000000: n4193_o = 1'b0; + 63'b000000000000000000000000000000000000000000000001000000000000000: n4193_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000100000000000000: n4193_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000010000000000000: n4193_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000001000000000000: n4193_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000100000000000: n4193_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000010000000000: n4193_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000001000000000: n4193_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000100000000: n4193_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000010000000: n4193_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000001000000: n4193_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000100000: n4193_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000010000: n4193_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000001000: n4193_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000000100: n4193_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000000010: n4193_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000000001: n4193_o = 1'b0; + default: n4193_o = 1'b0; + endcase + /* decoder.vhd:635:5 */ + always @* + case (n4151_o) + 63'b100000000000000000000000000000000000000000000000000000000000000: n4196_o = 1'b0; + 63'b010000000000000000000000000000000000000000000000000000000000000: n4196_o = 1'b0; + 63'b001000000000000000000000000000000000000000000000000000000000000: n4196_o = 1'b0; + 63'b000100000000000000000000000000000000000000000000000000000000000: n4196_o = 1'b0; + 63'b000010000000000000000000000000000000000000000000000000000000000: n4196_o = 1'b0; + 63'b000001000000000000000000000000000000000000000000000000000000000: n4196_o = 1'b0; + 63'b000000100000000000000000000000000000000000000000000000000000000: n4196_o = 1'b0; + 63'b000000010000000000000000000000000000000000000000000000000000000: n4196_o = 1'b0; + 63'b000000001000000000000000000000000000000000000000000000000000000: n4196_o = 1'b0; + 63'b000000000100000000000000000000000000000000000000000000000000000: n4196_o = 1'b0; + 63'b000000000010000000000000000000000000000000000000000000000000000: n4196_o = 1'b0; + 63'b000000000001000000000000000000000000000000000000000000000000000: n4196_o = 1'b0; + 63'b000000000000100000000000000000000000000000000000000000000000000: n4196_o = 1'b0; + 63'b000000000000010000000000000000000000000000000000000000000000000: n4196_o = n3772_o; + 63'b000000000000001000000000000000000000000000000000000000000000000: n4196_o = 1'b0; + 63'b000000000000000100000000000000000000000000000000000000000000000: n4196_o = 1'b0; + 63'b000000000000000010000000000000000000000000000000000000000000000: n4196_o = 1'b0; + 63'b000000000000000001000000000000000000000000000000000000000000000: n4196_o = 1'b0; + 63'b000000000000000000100000000000000000000000000000000000000000000: n4196_o = 1'b0; + 63'b000000000000000000010000000000000000000000000000000000000000000: n4196_o = n3483_o; + 63'b000000000000000000001000000000000000000000000000000000000000000: n4196_o = 1'b0; + 63'b000000000000000000000100000000000000000000000000000000000000000: n4196_o = 1'b0; + 63'b000000000000000000000010000000000000000000000000000000000000000: n4196_o = 1'b0; + 63'b000000000000000000000001000000000000000000000000000000000000000: n4196_o = 1'b0; + 63'b000000000000000000000000100000000000000000000000000000000000000: n4196_o = 1'b0; + 63'b000000000000000000000000010000000000000000000000000000000000000: n4196_o = 1'b0; + 63'b000000000000000000000000001000000000000000000000000000000000000: n4196_o = 1'b0; + 63'b000000000000000000000000000100000000000000000000000000000000000: n4196_o = 1'b0; + 63'b000000000000000000000000000010000000000000000000000000000000000: n4196_o = 1'b0; + 63'b000000000000000000000000000001000000000000000000000000000000000: n4196_o = 1'b0; + 63'b000000000000000000000000000000100000000000000000000000000000000: n4196_o = 1'b0; + 63'b000000000000000000000000000000010000000000000000000000000000000: n4196_o = 1'b0; + 63'b000000000000000000000000000000001000000000000000000000000000000: n4196_o = 1'b0; + 63'b000000000000000000000000000000000100000000000000000000000000000: n4196_o = 1'b0; + 63'b000000000000000000000000000000000010000000000000000000000000000: n4196_o = 1'b0; + 63'b000000000000000000000000000000000001000000000000000000000000000: n4196_o = 1'b0; + 63'b000000000000000000000000000000000000100000000000000000000000000: n4196_o = 1'b0; + 63'b000000000000000000000000000000000000010000000000000000000000000: n4196_o = 1'b0; + 63'b000000000000000000000000000000000000001000000000000000000000000: n4196_o = 1'b0; + 63'b000000000000000000000000000000000000000100000000000000000000000: n4196_o = 1'b0; + 63'b000000000000000000000000000000000000000010000000000000000000000: n4196_o = 1'b0; + 63'b000000000000000000000000000000000000000001000000000000000000000: n4196_o = 1'b0; + 63'b000000000000000000000000000000000000000000100000000000000000000: n4196_o = 1'b0; + 63'b000000000000000000000000000000000000000000010000000000000000000: n4196_o = n2762_o; + 63'b000000000000000000000000000000000000000000001000000000000000000: n4196_o = 1'b0; + 63'b000000000000000000000000000000000000000000000100000000000000000: n4196_o = 1'b0; + 63'b000000000000000000000000000000000000000000000010000000000000000: n4196_o = 1'b0; + 63'b000000000000000000000000000000000000000000000001000000000000000: n4196_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000100000000000000: n4196_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000010000000000000: n4196_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000001000000000000: n4196_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000100000000000: n4196_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000010000000000: n4196_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000001000000000: n4196_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000100000000: n4196_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000010000000: n4196_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000001000000: n4196_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000100000: n4196_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000010000: n4196_o = n2337_o; + 63'b000000000000000000000000000000000000000000000000000000000001000: n4196_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000000100: n4196_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000000010: n4196_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000000001: n4196_o = 1'b0; + default: n4196_o = 1'b0; + endcase + /* decoder.vhd:635:5 */ + always @* + case (n4151_o) + 63'b100000000000000000000000000000000000000000000000000000000000000: n4199_o = 1'b0; + 63'b010000000000000000000000000000000000000000000000000000000000000: n4199_o = 1'b0; + 63'b001000000000000000000000000000000000000000000000000000000000000: n4199_o = 1'b0; + 63'b000100000000000000000000000000000000000000000000000000000000000: n4199_o = 1'b0; + 63'b000010000000000000000000000000000000000000000000000000000000000: n4199_o = 1'b0; + 63'b000001000000000000000000000000000000000000000000000000000000000: n4199_o = 1'b0; + 63'b000000100000000000000000000000000000000000000000000000000000000: n4199_o = 1'b0; + 63'b000000010000000000000000000000000000000000000000000000000000000: n4199_o = 1'b0; + 63'b000000001000000000000000000000000000000000000000000000000000000: n4199_o = 1'b0; + 63'b000000000100000000000000000000000000000000000000000000000000000: n4199_o = 1'b0; + 63'b000000000010000000000000000000000000000000000000000000000000000: n4199_o = 1'b0; + 63'b000000000001000000000000000000000000000000000000000000000000000: n4199_o = 1'b0; + 63'b000000000000100000000000000000000000000000000000000000000000000: n4199_o = 1'b0; + 63'b000000000000010000000000000000000000000000000000000000000000000: n4199_o = 1'b0; + 63'b000000000000001000000000000000000000000000000000000000000000000: n4199_o = 1'b0; + 63'b000000000000000100000000000000000000000000000000000000000000000: n4199_o = 1'b0; + 63'b000000000000000010000000000000000000000000000000000000000000000: n4199_o = 1'b0; + 63'b000000000000000001000000000000000000000000000000000000000000000: n4199_o = 1'b0; + 63'b000000000000000000100000000000000000000000000000000000000000000: n4199_o = 1'b0; + 63'b000000000000000000010000000000000000000000000000000000000000000: n4199_o = n3485_o; + 63'b000000000000000000001000000000000000000000000000000000000000000: n4199_o = 1'b0; + 63'b000000000000000000000100000000000000000000000000000000000000000: n4199_o = 1'b0; + 63'b000000000000000000000010000000000000000000000000000000000000000: n4199_o = 1'b0; + 63'b000000000000000000000001000000000000000000000000000000000000000: n4199_o = 1'b0; + 63'b000000000000000000000000100000000000000000000000000000000000000: n4199_o = 1'b0; + 63'b000000000000000000000000010000000000000000000000000000000000000: n4199_o = 1'b0; + 63'b000000000000000000000000001000000000000000000000000000000000000: n4199_o = 1'b0; + 63'b000000000000000000000000000100000000000000000000000000000000000: n4199_o = 1'b0; + 63'b000000000000000000000000000010000000000000000000000000000000000: n4199_o = 1'b0; + 63'b000000000000000000000000000001000000000000000000000000000000000: n4199_o = 1'b0; + 63'b000000000000000000000000000000100000000000000000000000000000000: n4199_o = 1'b0; + 63'b000000000000000000000000000000010000000000000000000000000000000: n4199_o = 1'b0; + 63'b000000000000000000000000000000001000000000000000000000000000000: n4199_o = 1'b0; + 63'b000000000000000000000000000000000100000000000000000000000000000: n4199_o = 1'b0; + 63'b000000000000000000000000000000000010000000000000000000000000000: n4199_o = 1'b0; + 63'b000000000000000000000000000000000001000000000000000000000000000: n4199_o = 1'b0; + 63'b000000000000000000000000000000000000100000000000000000000000000: n4199_o = 1'b0; + 63'b000000000000000000000000000000000000010000000000000000000000000: n4199_o = 1'b0; + 63'b000000000000000000000000000000000000001000000000000000000000000: n4199_o = 1'b0; + 63'b000000000000000000000000000000000000000100000000000000000000000: n4199_o = 1'b0; + 63'b000000000000000000000000000000000000000010000000000000000000000: n4199_o = 1'b0; + 63'b000000000000000000000000000000000000000001000000000000000000000: n4199_o = 1'b0; + 63'b000000000000000000000000000000000000000000100000000000000000000: n4199_o = 1'b0; + 63'b000000000000000000000000000000000000000000010000000000000000000: n4199_o = 1'b0; + 63'b000000000000000000000000000000000000000000001000000000000000000: n4199_o = 1'b0; + 63'b000000000000000000000000000000000000000000000100000000000000000: n4199_o = 1'b0; + 63'b000000000000000000000000000000000000000000000010000000000000000: n4199_o = 1'b0; + 63'b000000000000000000000000000000000000000000000001000000000000000: n4199_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000100000000000000: n4199_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000010000000000000: n4199_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000001000000000000: n4199_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000100000000000: n4199_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000010000000000: n4199_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000001000000000: n4199_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000100000000: n4199_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000010000000: n4199_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000001000000: n4199_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000100000: n4199_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000010000: n4199_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000001000: n4199_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000000100: n4199_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000000010: n4199_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000000001: n4199_o = 1'b0; + default: n4199_o = 1'b0; + endcase + /* decoder.vhd:635:5 */ + always @* + case (n4151_o) + 63'b100000000000000000000000000000000000000000000000000000000000000: n4202_o = 1'b0; + 63'b010000000000000000000000000000000000000000000000000000000000000: n4202_o = 1'b0; + 63'b001000000000000000000000000000000000000000000000000000000000000: n4202_o = 1'b0; + 63'b000100000000000000000000000000000000000000000000000000000000000: n4202_o = 1'b0; + 63'b000010000000000000000000000000000000000000000000000000000000000: n4202_o = 1'b0; + 63'b000001000000000000000000000000000000000000000000000000000000000: n4202_o = 1'b0; + 63'b000000100000000000000000000000000000000000000000000000000000000: n4202_o = 1'b0; + 63'b000000010000000000000000000000000000000000000000000000000000000: n4202_o = 1'b0; + 63'b000000001000000000000000000000000000000000000000000000000000000: n4202_o = 1'b0; + 63'b000000000100000000000000000000000000000000000000000000000000000: n4202_o = 1'b0; + 63'b000000000010000000000000000000000000000000000000000000000000000: n4202_o = n3884_o; + 63'b000000000001000000000000000000000000000000000000000000000000000: n4202_o = 1'b0; + 63'b000000000000100000000000000000000000000000000000000000000000000: n4202_o = 1'b0; + 63'b000000000000010000000000000000000000000000000000000000000000000: n4202_o = 1'b0; + 63'b000000000000001000000000000000000000000000000000000000000000000: n4202_o = 1'b0; + 63'b000000000000000100000000000000000000000000000000000000000000000: n4202_o = 1'b0; + 63'b000000000000000010000000000000000000000000000000000000000000000: n4202_o = 1'b0; + 63'b000000000000000001000000000000000000000000000000000000000000000: n4202_o = 1'b0; + 63'b000000000000000000100000000000000000000000000000000000000000000: n4202_o = 1'b0; + 63'b000000000000000000010000000000000000000000000000000000000000000: n4202_o = 1'b0; + 63'b000000000000000000001000000000000000000000000000000000000000000: n4202_o = 1'b0; + 63'b000000000000000000000100000000000000000000000000000000000000000: n4202_o = 1'b0; + 63'b000000000000000000000010000000000000000000000000000000000000000: n4202_o = 1'b0; + 63'b000000000000000000000001000000000000000000000000000000000000000: n4202_o = 1'b0; + 63'b000000000000000000000000100000000000000000000000000000000000000: n4202_o = 1'b0; + 63'b000000000000000000000000010000000000000000000000000000000000000: n4202_o = 1'b0; + 63'b000000000000000000000000001000000000000000000000000000000000000: n4202_o = 1'b0; + 63'b000000000000000000000000000100000000000000000000000000000000000: n4202_o = 1'b0; + 63'b000000000000000000000000000010000000000000000000000000000000000: n4202_o = 1'b0; + 63'b000000000000000000000000000001000000000000000000000000000000000: n4202_o = n3173_o; + 63'b000000000000000000000000000000100000000000000000000000000000000: n4202_o = n3137_o; + 63'b000000000000000000000000000000010000000000000000000000000000000: n4202_o = n3106_o; + 63'b000000000000000000000000000000001000000000000000000000000000000: n4202_o = n3072_o; + 63'b000000000000000000000000000000000100000000000000000000000000000: n4202_o = n3046_o; + 63'b000000000000000000000000000000000010000000000000000000000000000: n4202_o = n3020_o; + 63'b000000000000000000000000000000000001000000000000000000000000000: n4202_o = n2994_o; + 63'b000000000000000000000000000000000000100000000000000000000000000: n4202_o = n2965_o; + 63'b000000000000000000000000000000000000010000000000000000000000000: n4202_o = n2934_o; + 63'b000000000000000000000000000000000000001000000000000000000000000: n4202_o = n2900_o; + 63'b000000000000000000000000000000000000000100000000000000000000000: n4202_o = n2871_o; + 63'b000000000000000000000000000000000000000010000000000000000000000: n4202_o = 1'b0; + 63'b000000000000000000000000000000000000000001000000000000000000000: n4202_o = 1'b0; + 63'b000000000000000000000000000000000000000000100000000000000000000: n4202_o = 1'b0; + 63'b000000000000000000000000000000000000000000010000000000000000000: n4202_o = 1'b0; + 63'b000000000000000000000000000000000000000000001000000000000000000: n4202_o = 1'b0; + 63'b000000000000000000000000000000000000000000000100000000000000000: n4202_o = 1'b0; + 63'b000000000000000000000000000000000000000000000010000000000000000: n4202_o = n2707_o; + 63'b000000000000000000000000000000000000000000000001000000000000000: n4202_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000100000000000000: n4202_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000010000000000000: n4202_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000001000000000000: n4202_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000100000000000: n4202_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000010000000000: n4202_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000001000000000: n4202_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000100000000: n4202_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000010000000: n4202_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000001000000: n4202_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000100000: n4202_o = n2439_o; + 63'b000000000000000000000000000000000000000000000000000000000010000: n4202_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000001000: n4202_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000000100: n4202_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000000010: n4202_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000000001: n4202_o = 1'b0; + default: n4202_o = 1'b0; + endcase + /* decoder.vhd:635:5 */ + always @* + case (n4151_o) + 63'b100000000000000000000000000000000000000000000000000000000000000: n4205_o = 1'b0; + 63'b010000000000000000000000000000000000000000000000000000000000000: n4205_o = 1'b0; + 63'b001000000000000000000000000000000000000000000000000000000000000: n4205_o = 1'b0; + 63'b000100000000000000000000000000000000000000000000000000000000000: n4205_o = 1'b0; + 63'b000010000000000000000000000000000000000000000000000000000000000: n4205_o = 1'b0; + 63'b000001000000000000000000000000000000000000000000000000000000000: n4205_o = 1'b0; + 63'b000000100000000000000000000000000000000000000000000000000000000: n4205_o = 1'b0; + 63'b000000010000000000000000000000000000000000000000000000000000000: n4205_o = 1'b0; + 63'b000000001000000000000000000000000000000000000000000000000000000: n4205_o = 1'b0; + 63'b000000000100000000000000000000000000000000000000000000000000000: n4205_o = 1'b0; + 63'b000000000010000000000000000000000000000000000000000000000000000: n4205_o = 1'b0; + 63'b000000000001000000000000000000000000000000000000000000000000000: n4205_o = 1'b0; + 63'b000000000000100000000000000000000000000000000000000000000000000: n4205_o = 1'b0; + 63'b000000000000010000000000000000000000000000000000000000000000000: n4205_o = 1'b0; + 63'b000000000000001000000000000000000000000000000000000000000000000: n4205_o = 1'b0; + 63'b000000000000000100000000000000000000000000000000000000000000000: n4205_o = 1'b0; + 63'b000000000000000010000000000000000000000000000000000000000000000: n4205_o = 1'b0; + 63'b000000000000000001000000000000000000000000000000000000000000000: n4205_o = 1'b0; + 63'b000000000000000000100000000000000000000000000000000000000000000: n4205_o = 1'b0; + 63'b000000000000000000010000000000000000000000000000000000000000000: n4205_o = 1'b0; + 63'b000000000000000000001000000000000000000000000000000000000000000: n4205_o = 1'b0; + 63'b000000000000000000000100000000000000000000000000000000000000000: n4205_o = 1'b0; + 63'b000000000000000000000010000000000000000000000000000000000000000: n4205_o = 1'b0; + 63'b000000000000000000000001000000000000000000000000000000000000000: n4205_o = 1'b0; + 63'b000000000000000000000000100000000000000000000000000000000000000: n4205_o = 1'b0; + 63'b000000000000000000000000010000000000000000000000000000000000000: n4205_o = 1'b0; + 63'b000000000000000000000000001000000000000000000000000000000000000: n4205_o = 1'b0; + 63'b000000000000000000000000000100000000000000000000000000000000000: n4205_o = 1'b0; + 63'b000000000000000000000000000010000000000000000000000000000000000: n4205_o = 1'b0; + 63'b000000000000000000000000000001000000000000000000000000000000000: n4205_o = 1'b0; + 63'b000000000000000000000000000000100000000000000000000000000000000: n4205_o = 1'b0; + 63'b000000000000000000000000000000010000000000000000000000000000000: n4205_o = 1'b0; + 63'b000000000000000000000000000000001000000000000000000000000000000: n4205_o = 1'b0; + 63'b000000000000000000000000000000000100000000000000000000000000000: n4205_o = 1'b0; + 63'b000000000000000000000000000000000010000000000000000000000000000: n4205_o = 1'b0; + 63'b000000000000000000000000000000000001000000000000000000000000000: n4205_o = 1'b0; + 63'b000000000000000000000000000000000000100000000000000000000000000: n4205_o = 1'b0; + 63'b000000000000000000000000000000000000010000000000000000000000000: n4205_o = 1'b0; + 63'b000000000000000000000000000000000000001000000000000000000000000: n4205_o = 1'b0; + 63'b000000000000000000000000000000000000000100000000000000000000000: n4205_o = 1'b0; + 63'b000000000000000000000000000000000000000010000000000000000000000: n4205_o = 1'b0; + 63'b000000000000000000000000000000000000000001000000000000000000000: n4205_o = 1'b0; + 63'b000000000000000000000000000000000000000000100000000000000000000: n4205_o = 1'b0; + 63'b000000000000000000000000000000000000000000010000000000000000000: n4205_o = 1'b0; + 63'b000000000000000000000000000000000000000000001000000000000000000: n4205_o = 1'b0; + 63'b000000000000000000000000000000000000000000000100000000000000000: n4205_o = 1'b0; + 63'b000000000000000000000000000000000000000000000010000000000000000: n4205_o = 1'b0; + 63'b000000000000000000000000000000000000000000000001000000000000000: n4205_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000100000000000000: n4205_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000010000000000000: n4205_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000001000000000000: n4205_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000100000000000: n4205_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000010000000000: n4205_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000001000000000: n4205_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000100000000: n4205_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000010000000: n4205_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000001000000: n4205_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000100000: n4205_o = n2441_o; + 63'b000000000000000000000000000000000000000000000000000000000010000: n4205_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000001000: n4205_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000000100: n4205_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000000010: n4205_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000000001: n4205_o = 1'b0; + default: n4205_o = 1'b0; + endcase + /* decoder.vhd:635:5 */ + always @* + case (n4151_o) + 63'b100000000000000000000000000000000000000000000000000000000000000: n4208_o = 1'b0; + 63'b010000000000000000000000000000000000000000000000000000000000000: n4208_o = 1'b0; + 63'b001000000000000000000000000000000000000000000000000000000000000: n4208_o = 1'b0; + 63'b000100000000000000000000000000000000000000000000000000000000000: n4208_o = 1'b0; + 63'b000010000000000000000000000000000000000000000000000000000000000: n4208_o = 1'b0; + 63'b000001000000000000000000000000000000000000000000000000000000000: n4208_o = 1'b0; + 63'b000000100000000000000000000000000000000000000000000000000000000: n4208_o = 1'b0; + 63'b000000010000000000000000000000000000000000000000000000000000000: n4208_o = 1'b0; + 63'b000000001000000000000000000000000000000000000000000000000000000: n4208_o = 1'b0; + 63'b000000000100000000000000000000000000000000000000000000000000000: n4208_o = 1'b0; + 63'b000000000010000000000000000000000000000000000000000000000000000: n4208_o = n3886_o; + 63'b000000000001000000000000000000000000000000000000000000000000000: n4208_o = 1'b0; + 63'b000000000000100000000000000000000000000000000000000000000000000: n4208_o = 1'b0; + 63'b000000000000010000000000000000000000000000000000000000000000000: n4208_o = 1'b0; + 63'b000000000000001000000000000000000000000000000000000000000000000: n4208_o = 1'b0; + 63'b000000000000000100000000000000000000000000000000000000000000000: n4208_o = 1'b0; + 63'b000000000000000010000000000000000000000000000000000000000000000: n4208_o = 1'b0; + 63'b000000000000000001000000000000000000000000000000000000000000000: n4208_o = 1'b0; + 63'b000000000000000000100000000000000000000000000000000000000000000: n4208_o = 1'b0; + 63'b000000000000000000010000000000000000000000000000000000000000000: n4208_o = 1'b0; + 63'b000000000000000000001000000000000000000000000000000000000000000: n4208_o = 1'b0; + 63'b000000000000000000000100000000000000000000000000000000000000000: n4208_o = 1'b0; + 63'b000000000000000000000010000000000000000000000000000000000000000: n4208_o = 1'b0; + 63'b000000000000000000000001000000000000000000000000000000000000000: n4208_o = 1'b0; + 63'b000000000000000000000000100000000000000000000000000000000000000: n4208_o = 1'b0; + 63'b000000000000000000000000010000000000000000000000000000000000000: n4208_o = 1'b0; + 63'b000000000000000000000000001000000000000000000000000000000000000: n4208_o = 1'b0; + 63'b000000000000000000000000000100000000000000000000000000000000000: n4208_o = 1'b0; + 63'b000000000000000000000000000010000000000000000000000000000000000: n4208_o = 1'b0; + 63'b000000000000000000000000000001000000000000000000000000000000000: n4208_o = 1'b0; + 63'b000000000000000000000000000000100000000000000000000000000000000: n4208_o = 1'b0; + 63'b000000000000000000000000000000010000000000000000000000000000000: n4208_o = 1'b0; + 63'b000000000000000000000000000000001000000000000000000000000000000: n4208_o = 1'b0; + 63'b000000000000000000000000000000000100000000000000000000000000000: n4208_o = 1'b0; + 63'b000000000000000000000000000000000010000000000000000000000000000: n4208_o = 1'b0; + 63'b000000000000000000000000000000000001000000000000000000000000000: n4208_o = 1'b0; + 63'b000000000000000000000000000000000000100000000000000000000000000: n4208_o = n2967_o; + 63'b000000000000000000000000000000000000010000000000000000000000000: n4208_o = 1'b0; + 63'b000000000000000000000000000000000000001000000000000000000000000: n4208_o = 1'b0; + 63'b000000000000000000000000000000000000000100000000000000000000000: n4208_o = 1'b0; + 63'b000000000000000000000000000000000000000010000000000000000000000: n4208_o = 1'b0; + 63'b000000000000000000000000000000000000000001000000000000000000000: n4208_o = 1'b0; + 63'b000000000000000000000000000000000000000000100000000000000000000: n4208_o = 1'b0; + 63'b000000000000000000000000000000000000000000010000000000000000000: n4208_o = 1'b0; + 63'b000000000000000000000000000000000000000000001000000000000000000: n4208_o = 1'b0; + 63'b000000000000000000000000000000000000000000000100000000000000000: n4208_o = 1'b0; + 63'b000000000000000000000000000000000000000000000010000000000000000: n4208_o = 1'b0; + 63'b000000000000000000000000000000000000000000000001000000000000000: n4208_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000100000000000000: n4208_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000010000000000000: n4208_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000001000000000000: n4208_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000100000000000: n4208_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000010000000000: n4208_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000001000000000: n4208_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000100000000: n4208_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000010000000: n4208_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000001000000: n4208_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000100000: n4208_o = n2443_o; + 63'b000000000000000000000000000000000000000000000000000000000010000: n4208_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000001000: n4208_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000000100: n4208_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000000010: n4208_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000000001: n4208_o = 1'b0; + default: n4208_o = 1'b0; + endcase + /* decoder.vhd:635:5 */ + always @* + case (n4151_o) + 63'b100000000000000000000000000000000000000000000000000000000000000: n4211_o = 1'b0; + 63'b010000000000000000000000000000000000000000000000000000000000000: n4211_o = 1'b0; + 63'b001000000000000000000000000000000000000000000000000000000000000: n4211_o = 1'b0; + 63'b000100000000000000000000000000000000000000000000000000000000000: n4211_o = 1'b0; + 63'b000010000000000000000000000000000000000000000000000000000000000: n4211_o = 1'b0; + 63'b000001000000000000000000000000000000000000000000000000000000000: n4211_o = 1'b0; + 63'b000000100000000000000000000000000000000000000000000000000000000: n4211_o = 1'b0; + 63'b000000010000000000000000000000000000000000000000000000000000000: n4211_o = 1'b0; + 63'b000000001000000000000000000000000000000000000000000000000000000: n4211_o = 1'b0; + 63'b000000000100000000000000000000000000000000000000000000000000000: n4211_o = 1'b0; + 63'b000000000010000000000000000000000000000000000000000000000000000: n4211_o = 1'b0; + 63'b000000000001000000000000000000000000000000000000000000000000000: n4211_o = 1'b0; + 63'b000000000000100000000000000000000000000000000000000000000000000: n4211_o = 1'b0; + 63'b000000000000010000000000000000000000000000000000000000000000000: n4211_o = 1'b0; + 63'b000000000000001000000000000000000000000000000000000000000000000: n4211_o = 1'b0; + 63'b000000000000000100000000000000000000000000000000000000000000000: n4211_o = 1'b0; + 63'b000000000000000010000000000000000000000000000000000000000000000: n4211_o = 1'b0; + 63'b000000000000000001000000000000000000000000000000000000000000000: n4211_o = 1'b0; + 63'b000000000000000000100000000000000000000000000000000000000000000: n4211_o = 1'b0; + 63'b000000000000000000010000000000000000000000000000000000000000000: n4211_o = 1'b0; + 63'b000000000000000000001000000000000000000000000000000000000000000: n4211_o = 1'b0; + 63'b000000000000000000000100000000000000000000000000000000000000000: n4211_o = 1'b0; + 63'b000000000000000000000010000000000000000000000000000000000000000: n4211_o = 1'b0; + 63'b000000000000000000000001000000000000000000000000000000000000000: n4211_o = 1'b0; + 63'b000000000000000000000000100000000000000000000000000000000000000: n4211_o = 1'b0; + 63'b000000000000000000000000010000000000000000000000000000000000000: n4211_o = 1'b0; + 63'b000000000000000000000000001000000000000000000000000000000000000: n4211_o = 1'b0; + 63'b000000000000000000000000000100000000000000000000000000000000000: n4211_o = 1'b0; + 63'b000000000000000000000000000010000000000000000000000000000000000: n4211_o = 1'b0; + 63'b000000000000000000000000000001000000000000000000000000000000000: n4211_o = 1'b0; + 63'b000000000000000000000000000000100000000000000000000000000000000: n4211_o = 1'b0; + 63'b000000000000000000000000000000010000000000000000000000000000000: n4211_o = 1'b0; + 63'b000000000000000000000000000000001000000000000000000000000000000: n4211_o = 1'b0; + 63'b000000000000000000000000000000000100000000000000000000000000000: n4211_o = 1'b0; + 63'b000000000000000000000000000000000010000000000000000000000000000: n4211_o = 1'b0; + 63'b000000000000000000000000000000000001000000000000000000000000000: n4211_o = 1'b0; + 63'b000000000000000000000000000000000000100000000000000000000000000: n4211_o = 1'b0; + 63'b000000000000000000000000000000000000010000000000000000000000000: n4211_o = 1'b0; + 63'b000000000000000000000000000000000000001000000000000000000000000: n4211_o = 1'b0; + 63'b000000000000000000000000000000000000000100000000000000000000000: n4211_o = 1'b0; + 63'b000000000000000000000000000000000000000010000000000000000000000: n4211_o = 1'b0; + 63'b000000000000000000000000000000000000000001000000000000000000000: n4211_o = 1'b0; + 63'b000000000000000000000000000000000000000000100000000000000000000: n4211_o = 1'b0; + 63'b000000000000000000000000000000000000000000010000000000000000000: n4211_o = 1'b0; + 63'b000000000000000000000000000000000000000000001000000000000000000: n4211_o = 1'b0; + 63'b000000000000000000000000000000000000000000000100000000000000000: n4211_o = 1'b0; + 63'b000000000000000000000000000000000000000000000010000000000000000: n4211_o = 1'b0; + 63'b000000000000000000000000000000000000000000000001000000000000000: n4211_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000100000000000000: n4211_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000010000000000000: n4211_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000001000000000000: n4211_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000100000000000: n4211_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000010000000000: n4211_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000001000000000: n4211_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000100000000: n4211_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000010000000: n4211_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000001000000: n4211_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000100000: n4211_o = n2445_o; + 63'b000000000000000000000000000000000000000000000000000000000010000: n4211_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000001000: n4211_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000000100: n4211_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000000010: n4211_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000000001: n4211_o = 1'b0; + default: n4211_o = 1'b0; + endcase + /* decoder.vhd:635:5 */ + always @* + case (n4151_o) + 63'b100000000000000000000000000000000000000000000000000000000000000: n4214_o = 1'b0; + 63'b010000000000000000000000000000000000000000000000000000000000000: n4214_o = 1'b0; + 63'b001000000000000000000000000000000000000000000000000000000000000: n4214_o = 1'b0; + 63'b000100000000000000000000000000000000000000000000000000000000000: n4214_o = 1'b0; + 63'b000010000000000000000000000000000000000000000000000000000000000: n4214_o = 1'b0; + 63'b000001000000000000000000000000000000000000000000000000000000000: n4214_o = 1'b0; + 63'b000000100000000000000000000000000000000000000000000000000000000: n4214_o = 1'b0; + 63'b000000010000000000000000000000000000000000000000000000000000000: n4214_o = 1'b0; + 63'b000000001000000000000000000000000000000000000000000000000000000: n4214_o = 1'b0; + 63'b000000000100000000000000000000000000000000000000000000000000000: n4214_o = 1'b0; + 63'b000000000010000000000000000000000000000000000000000000000000000: n4214_o = 1'b0; + 63'b000000000001000000000000000000000000000000000000000000000000000: n4214_o = 1'b0; + 63'b000000000000100000000000000000000000000000000000000000000000000: n4214_o = 1'b0; + 63'b000000000000010000000000000000000000000000000000000000000000000: n4214_o = 1'b0; + 63'b000000000000001000000000000000000000000000000000000000000000000: n4214_o = 1'b0; + 63'b000000000000000100000000000000000000000000000000000000000000000: n4214_o = 1'b0; + 63'b000000000000000010000000000000000000000000000000000000000000000: n4214_o = 1'b0; + 63'b000000000000000001000000000000000000000000000000000000000000000: n4214_o = 1'b0; + 63'b000000000000000000100000000000000000000000000000000000000000000: n4214_o = 1'b0; + 63'b000000000000000000010000000000000000000000000000000000000000000: n4214_o = 1'b0; + 63'b000000000000000000001000000000000000000000000000000000000000000: n4214_o = 1'b0; + 63'b000000000000000000000100000000000000000000000000000000000000000: n4214_o = 1'b0; + 63'b000000000000000000000010000000000000000000000000000000000000000: n4214_o = 1'b0; + 63'b000000000000000000000001000000000000000000000000000000000000000: n4214_o = 1'b0; + 63'b000000000000000000000000100000000000000000000000000000000000000: n4214_o = 1'b0; + 63'b000000000000000000000000010000000000000000000000000000000000000: n4214_o = 1'b0; + 63'b000000000000000000000000001000000000000000000000000000000000000: n4214_o = n3236_o; + 63'b000000000000000000000000000100000000000000000000000000000000000: n4214_o = 1'b0; + 63'b000000000000000000000000000010000000000000000000000000000000000: n4214_o = 1'b0; + 63'b000000000000000000000000000001000000000000000000000000000000000: n4214_o = 1'b0; + 63'b000000000000000000000000000000100000000000000000000000000000000: n4214_o = 1'b0; + 63'b000000000000000000000000000000010000000000000000000000000000000: n4214_o = 1'b0; + 63'b000000000000000000000000000000001000000000000000000000000000000: n4214_o = 1'b0; + 63'b000000000000000000000000000000000100000000000000000000000000000: n4214_o = 1'b0; + 63'b000000000000000000000000000000000010000000000000000000000000000: n4214_o = 1'b0; + 63'b000000000000000000000000000000000001000000000000000000000000000: n4214_o = 1'b0; + 63'b000000000000000000000000000000000000100000000000000000000000000: n4214_o = 1'b0; + 63'b000000000000000000000000000000000000010000000000000000000000000: n4214_o = 1'b0; + 63'b000000000000000000000000000000000000001000000000000000000000000: n4214_o = 1'b0; + 63'b000000000000000000000000000000000000000100000000000000000000000: n4214_o = 1'b0; + 63'b000000000000000000000000000000000000000010000000000000000000000: n4214_o = 1'b0; + 63'b000000000000000000000000000000000000000001000000000000000000000: n4214_o = 1'b0; + 63'b000000000000000000000000000000000000000000100000000000000000000: n4214_o = 1'b0; + 63'b000000000000000000000000000000000000000000010000000000000000000: n4214_o = 1'b0; + 63'b000000000000000000000000000000000000000000001000000000000000000: n4214_o = 1'b0; + 63'b000000000000000000000000000000000000000000000100000000000000000: n4214_o = 1'b0; + 63'b000000000000000000000000000000000000000000000010000000000000000: n4214_o = 1'b0; + 63'b000000000000000000000000000000000000000000000001000000000000000: n4214_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000100000000000000: n4214_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000010000000000000: n4214_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000001000000000000: n4214_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000100000000000: n4214_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000010000000000: n4214_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000001000000000: n4214_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000100000000: n4214_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000010000000: n4214_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000001000000: n4214_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000100000: n4214_o = n2447_o; + 63'b000000000000000000000000000000000000000000000000000000000010000: n4214_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000001000: n4214_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000000100: n4214_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000000010: n4214_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000000001: n4214_o = 1'b0; + default: n4214_o = 1'b0; + endcase + /* decoder.vhd:635:5 */ + always @* + case (n4151_o) + 63'b100000000000000000000000000000000000000000000000000000000000000: n4217_o = 1'b0; + 63'b010000000000000000000000000000000000000000000000000000000000000: n4217_o = 1'b0; + 63'b001000000000000000000000000000000000000000000000000000000000000: n4217_o = 1'b0; + 63'b000100000000000000000000000000000000000000000000000000000000000: n4217_o = 1'b0; + 63'b000010000000000000000000000000000000000000000000000000000000000: n4217_o = 1'b0; + 63'b000001000000000000000000000000000000000000000000000000000000000: n4217_o = 1'b0; + 63'b000000100000000000000000000000000000000000000000000000000000000: n4217_o = 1'b0; + 63'b000000010000000000000000000000000000000000000000000000000000000: n4217_o = 1'b0; + 63'b000000001000000000000000000000000000000000000000000000000000000: n4217_o = 1'b0; + 63'b000000000100000000000000000000000000000000000000000000000000000: n4217_o = 1'b0; + 63'b000000000010000000000000000000000000000000000000000000000000000: n4217_o = n3888_o; + 63'b000000000001000000000000000000000000000000000000000000000000000: n4217_o = 1'b0; + 63'b000000000000100000000000000000000000000000000000000000000000000: n4217_o = 1'b0; + 63'b000000000000010000000000000000000000000000000000000000000000000: n4217_o = 1'b0; + 63'b000000000000001000000000000000000000000000000000000000000000000: n4217_o = 1'b0; + 63'b000000000000000100000000000000000000000000000000000000000000000: n4217_o = 1'b0; + 63'b000000000000000010000000000000000000000000000000000000000000000: n4217_o = 1'b0; + 63'b000000000000000001000000000000000000000000000000000000000000000: n4217_o = 1'b0; + 63'b000000000000000000100000000000000000000000000000000000000000000: n4217_o = 1'b0; + 63'b000000000000000000010000000000000000000000000000000000000000000: n4217_o = 1'b0; + 63'b000000000000000000001000000000000000000000000000000000000000000: n4217_o = 1'b0; + 63'b000000000000000000000100000000000000000000000000000000000000000: n4217_o = 1'b0; + 63'b000000000000000000000010000000000000000000000000000000000000000: n4217_o = 1'b0; + 63'b000000000000000000000001000000000000000000000000000000000000000: n4217_o = 1'b0; + 63'b000000000000000000000000100000000000000000000000000000000000000: n4217_o = 1'b0; + 63'b000000000000000000000000010000000000000000000000000000000000000: n4217_o = 1'b0; + 63'b000000000000000000000000001000000000000000000000000000000000000: n4217_o = n3239_o; + 63'b000000000000000000000000000100000000000000000000000000000000000: n4217_o = 1'b0; + 63'b000000000000000000000000000010000000000000000000000000000000000: n4217_o = 1'b0; + 63'b000000000000000000000000000001000000000000000000000000000000000: n4217_o = 1'b0; + 63'b000000000000000000000000000000100000000000000000000000000000000: n4217_o = 1'b0; + 63'b000000000000000000000000000000010000000000000000000000000000000: n4217_o = 1'b0; + 63'b000000000000000000000000000000001000000000000000000000000000000: n4217_o = 1'b0; + 63'b000000000000000000000000000000000100000000000000000000000000000: n4217_o = 1'b0; + 63'b000000000000000000000000000000000010000000000000000000000000000: n4217_o = 1'b0; + 63'b000000000000000000000000000000000001000000000000000000000000000: n4217_o = 1'b0; + 63'b000000000000000000000000000000000000100000000000000000000000000: n4217_o = 1'b0; + 63'b000000000000000000000000000000000000010000000000000000000000000: n4217_o = 1'b0; + 63'b000000000000000000000000000000000000001000000000000000000000000: n4217_o = 1'b0; + 63'b000000000000000000000000000000000000000100000000000000000000000: n4217_o = 1'b0; + 63'b000000000000000000000000000000000000000010000000000000000000000: n4217_o = 1'b0; + 63'b000000000000000000000000000000000000000001000000000000000000000: n4217_o = 1'b0; + 63'b000000000000000000000000000000000000000000100000000000000000000: n4217_o = 1'b0; + 63'b000000000000000000000000000000000000000000010000000000000000000: n4217_o = 1'b0; + 63'b000000000000000000000000000000000000000000001000000000000000000: n4217_o = 1'b0; + 63'b000000000000000000000000000000000000000000000100000000000000000: n4217_o = 1'b0; + 63'b000000000000000000000000000000000000000000000010000000000000000: n4217_o = 1'b0; + 63'b000000000000000000000000000000000000000000000001000000000000000: n4217_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000100000000000000: n4217_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000010000000000000: n4217_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000001000000000000: n4217_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000100000000000: n4217_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000010000000000: n4217_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000001000000000: n4217_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000100000000: n4217_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000010000000: n4217_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000001000000: n4217_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000100000: n4217_o = n2449_o; + 63'b000000000000000000000000000000000000000000000000000000000010000: n4217_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000001000: n4217_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000000100: n4217_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000000010: n4217_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000000001: n4217_o = 1'b0; + default: n4217_o = 1'b0; + endcase + /* decoder.vhd:635:5 */ + always @* + case (n4151_o) + 63'b100000000000000000000000000000000000000000000000000000000000000: n4220_o = 1'b0; + 63'b010000000000000000000000000000000000000000000000000000000000000: n4220_o = 1'b0; + 63'b001000000000000000000000000000000000000000000000000000000000000: n4220_o = 1'b0; + 63'b000100000000000000000000000000000000000000000000000000000000000: n4220_o = 1'b0; + 63'b000010000000000000000000000000000000000000000000000000000000000: n4220_o = 1'b0; + 63'b000001000000000000000000000000000000000000000000000000000000000: n4220_o = 1'b0; + 63'b000000100000000000000000000000000000000000000000000000000000000: n4220_o = 1'b0; + 63'b000000010000000000000000000000000000000000000000000000000000000: n4220_o = 1'b0; + 63'b000000001000000000000000000000000000000000000000000000000000000: n4220_o = 1'b0; + 63'b000000000100000000000000000000000000000000000000000000000000000: n4220_o = 1'b0; + 63'b000000000010000000000000000000000000000000000000000000000000000: n4220_o = n3890_o; + 63'b000000000001000000000000000000000000000000000000000000000000000: n4220_o = 1'b0; + 63'b000000000000100000000000000000000000000000000000000000000000000: n4220_o = 1'b0; + 63'b000000000000010000000000000000000000000000000000000000000000000: n4220_o = 1'b0; + 63'b000000000000001000000000000000000000000000000000000000000000000: n4220_o = 1'b0; + 63'b000000000000000100000000000000000000000000000000000000000000000: n4220_o = 1'b0; + 63'b000000000000000010000000000000000000000000000000000000000000000: n4220_o = 1'b0; + 63'b000000000000000001000000000000000000000000000000000000000000000: n4220_o = 1'b0; + 63'b000000000000000000100000000000000000000000000000000000000000000: n4220_o = 1'b0; + 63'b000000000000000000010000000000000000000000000000000000000000000: n4220_o = 1'b0; + 63'b000000000000000000001000000000000000000000000000000000000000000: n4220_o = 1'b0; + 63'b000000000000000000000100000000000000000000000000000000000000000: n4220_o = 1'b0; + 63'b000000000000000000000010000000000000000000000000000000000000000: n4220_o = 1'b0; + 63'b000000000000000000000001000000000000000000000000000000000000000: n4220_o = 1'b0; + 63'b000000000000000000000000100000000000000000000000000000000000000: n4220_o = 1'b0; + 63'b000000000000000000000000010000000000000000000000000000000000000: n4220_o = n3249_o; + 63'b000000000000000000000000001000000000000000000000000000000000000: n4220_o = 1'b0; + 63'b000000000000000000000000000100000000000000000000000000000000000: n4220_o = 1'b0; + 63'b000000000000000000000000000010000000000000000000000000000000000: n4220_o = 1'b0; + 63'b000000000000000000000000000001000000000000000000000000000000000: n4220_o = 1'b0; + 63'b000000000000000000000000000000100000000000000000000000000000000: n4220_o = 1'b0; + 63'b000000000000000000000000000000010000000000000000000000000000000: n4220_o = 1'b0; + 63'b000000000000000000000000000000001000000000000000000000000000000: n4220_o = 1'b0; + 63'b000000000000000000000000000000000100000000000000000000000000000: n4220_o = 1'b0; + 63'b000000000000000000000000000000000010000000000000000000000000000: n4220_o = 1'b0; + 63'b000000000000000000000000000000000001000000000000000000000000000: n4220_o = 1'b0; + 63'b000000000000000000000000000000000000100000000000000000000000000: n4220_o = 1'b0; + 63'b000000000000000000000000000000000000010000000000000000000000000: n4220_o = 1'b0; + 63'b000000000000000000000000000000000000001000000000000000000000000: n4220_o = 1'b0; + 63'b000000000000000000000000000000000000000100000000000000000000000: n4220_o = 1'b0; + 63'b000000000000000000000000000000000000000010000000000000000000000: n4220_o = 1'b0; + 63'b000000000000000000000000000000000000000001000000000000000000000: n4220_o = 1'b0; + 63'b000000000000000000000000000000000000000000100000000000000000000: n4220_o = 1'b0; + 63'b000000000000000000000000000000000000000000010000000000000000000: n4220_o = 1'b0; + 63'b000000000000000000000000000000000000000000001000000000000000000: n4220_o = 1'b0; + 63'b000000000000000000000000000000000000000000000100000000000000000: n4220_o = 1'b0; + 63'b000000000000000000000000000000000000000000000010000000000000000: n4220_o = 1'b0; + 63'b000000000000000000000000000000000000000000000001000000000000000: n4220_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000100000000000000: n4220_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000010000000000000: n4220_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000001000000000000: n4220_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000100000000000: n4220_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000010000000000: n4220_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000001000000000: n4220_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000100000000: n4220_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000010000000: n4220_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000001000000: n4220_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000100000: n4220_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000010000: n4220_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000001000: n4220_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000000100: n4220_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000000010: n4220_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000000001: n4220_o = 1'b0; + default: n4220_o = 1'b0; + endcase + /* decoder.vhd:635:5 */ + always @* + case (n4151_o) + 63'b100000000000000000000000000000000000000000000000000000000000000: n4223_o = 1'b0; + 63'b010000000000000000000000000000000000000000000000000000000000000: n4223_o = 1'b0; + 63'b001000000000000000000000000000000000000000000000000000000000000: n4223_o = 1'b0; + 63'b000100000000000000000000000000000000000000000000000000000000000: n4223_o = 1'b0; + 63'b000010000000000000000000000000000000000000000000000000000000000: n4223_o = 1'b0; + 63'b000001000000000000000000000000000000000000000000000000000000000: n4223_o = 1'b0; + 63'b000000100000000000000000000000000000000000000000000000000000000: n4223_o = 1'b0; + 63'b000000010000000000000000000000000000000000000000000000000000000: n4223_o = 1'b0; + 63'b000000001000000000000000000000000000000000000000000000000000000: n4223_o = 1'b0; + 63'b000000000100000000000000000000000000000000000000000000000000000: n4223_o = 1'b0; + 63'b000000000010000000000000000000000000000000000000000000000000000: n4223_o = 1'b0; + 63'b000000000001000000000000000000000000000000000000000000000000000: n4223_o = 1'b0; + 63'b000000000000100000000000000000000000000000000000000000000000000: n4223_o = 1'b0; + 63'b000000000000010000000000000000000000000000000000000000000000000: n4223_o = 1'b0; + 63'b000000000000001000000000000000000000000000000000000000000000000: n4223_o = 1'b0; + 63'b000000000000000100000000000000000000000000000000000000000000000: n4223_o = 1'b0; + 63'b000000000000000010000000000000000000000000000000000000000000000: n4223_o = 1'b0; + 63'b000000000000000001000000000000000000000000000000000000000000000: n4223_o = 1'b0; + 63'b000000000000000000100000000000000000000000000000000000000000000: n4223_o = 1'b0; + 63'b000000000000000000010000000000000000000000000000000000000000000: n4223_o = 1'b0; + 63'b000000000000000000001000000000000000000000000000000000000000000: n4223_o = 1'b0; + 63'b000000000000000000000100000000000000000000000000000000000000000: n4223_o = 1'b0; + 63'b000000000000000000000010000000000000000000000000000000000000000: n4223_o = 1'b0; + 63'b000000000000000000000001000000000000000000000000000000000000000: n4223_o = 1'b0; + 63'b000000000000000000000000100000000000000000000000000000000000000: n4223_o = 1'b0; + 63'b000000000000000000000000010000000000000000000000000000000000000: n4223_o = n3252_o; + 63'b000000000000000000000000001000000000000000000000000000000000000: n4223_o = 1'b0; + 63'b000000000000000000000000000100000000000000000000000000000000000: n4223_o = 1'b0; + 63'b000000000000000000000000000010000000000000000000000000000000000: n4223_o = 1'b0; + 63'b000000000000000000000000000001000000000000000000000000000000000: n4223_o = 1'b0; + 63'b000000000000000000000000000000100000000000000000000000000000000: n4223_o = 1'b0; + 63'b000000000000000000000000000000010000000000000000000000000000000: n4223_o = 1'b0; + 63'b000000000000000000000000000000001000000000000000000000000000000: n4223_o = 1'b0; + 63'b000000000000000000000000000000000100000000000000000000000000000: n4223_o = 1'b0; + 63'b000000000000000000000000000000000010000000000000000000000000000: n4223_o = 1'b0; + 63'b000000000000000000000000000000000001000000000000000000000000000: n4223_o = 1'b0; + 63'b000000000000000000000000000000000000100000000000000000000000000: n4223_o = 1'b0; + 63'b000000000000000000000000000000000000010000000000000000000000000: n4223_o = 1'b0; + 63'b000000000000000000000000000000000000001000000000000000000000000: n4223_o = 1'b0; + 63'b000000000000000000000000000000000000000100000000000000000000000: n4223_o = 1'b0; + 63'b000000000000000000000000000000000000000010000000000000000000000: n4223_o = 1'b0; + 63'b000000000000000000000000000000000000000001000000000000000000000: n4223_o = 1'b0; + 63'b000000000000000000000000000000000000000000100000000000000000000: n4223_o = 1'b0; + 63'b000000000000000000000000000000000000000000010000000000000000000: n4223_o = 1'b0; + 63'b000000000000000000000000000000000000000000001000000000000000000: n4223_o = 1'b0; + 63'b000000000000000000000000000000000000000000000100000000000000000: n4223_o = 1'b0; + 63'b000000000000000000000000000000000000000000000010000000000000000: n4223_o = 1'b0; + 63'b000000000000000000000000000000000000000000000001000000000000000: n4223_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000100000000000000: n4223_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000010000000000000: n4223_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000001000000000000: n4223_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000100000000000: n4223_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000010000000000: n4223_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000001000000000: n4223_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000100000000: n4223_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000010000000: n4223_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000001000000: n4223_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000100000: n4223_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000010000: n4223_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000001000: n4223_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000000100: n4223_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000000010: n4223_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000000001: n4223_o = 1'b0; + default: n4223_o = 1'b0; + endcase + /* decoder.vhd:635:5 */ + always @* + case (n4151_o) + 63'b100000000000000000000000000000000000000000000000000000000000000: n4227_o = n4148_o; + 63'b010000000000000000000000000000000000000000000000000000000000000: n4227_o = n4116_o; + 63'b001000000000000000000000000000000000000000000000000000000000000: n4227_o = n4061_o; + 63'b000100000000000000000000000000000000000000000000000000000000000: n4227_o = 4'b0111; + 63'b000010000000000000000000000000000000000000000000000000000000000: n4227_o = 4'b1100; + 63'b000001000000000000000000000000000000000000000000000000000000000: n4227_o = 4'b1100; + 63'b000000100000000000000000000000000000000000000000000000000000000: n4227_o = 4'b1100; + 63'b000000010000000000000000000000000000000000000000000000000000000: n4227_o = 4'b1100; + 63'b000000001000000000000000000000000000000000000000000000000000000: n4227_o = n3949_o; + 63'b000000000100000000000000000000000000000000000000000000000000000: n4227_o = n3920_o; + 63'b000000000010000000000000000000000000000000000000000000000000000: n4227_o = 4'b1100; + 63'b000000000001000000000000000000000000000000000000000000000000000: n4227_o = 4'b1100; + 63'b000000000000100000000000000000000000000000000000000000000000000: n4227_o = 4'b1100; + 63'b000000000000010000000000000000000000000000000000000000000000000: n4227_o = n3774_o; + 63'b000000000000001000000000000000000000000000000000000000000000000: n4227_o = n3668_o; + 63'b000000000000000100000000000000000000000000000000000000000000000: n4227_o = n3636_o; + 63'b000000000000000010000000000000000000000000000000000000000000000: n4227_o = 4'b1100; + 63'b000000000000000001000000000000000000000000000000000000000000000: n4227_o = 4'b1100; + 63'b000000000000000000100000000000000000000000000000000000000000000: n4227_o = 4'b1100; + 63'b000000000000000000010000000000000000000000000000000000000000000: n4227_o = 4'b1100; + 63'b000000000000000000001000000000000000000000000000000000000000000: n4227_o = 4'b1100; + 63'b000000000000000000000100000000000000000000000000000000000000000: n4227_o = 4'b1100; + 63'b000000000000000000000010000000000000000000000000000000000000000: n4227_o = 4'b1100; + 63'b000000000000000000000001000000000000000000000000000000000000000: n4227_o = 4'b1100; + 63'b000000000000000000000000100000000000000000000000000000000000000: n4227_o = 4'b1100; + 63'b000000000000000000000000010000000000000000000000000000000000000: n4227_o = 4'b1100; + 63'b000000000000000000000000001000000000000000000000000000000000000: n4227_o = 4'b1100; + 63'b000000000000000000000000000100000000000000000000000000000000000: n4227_o = 4'b1100; + 63'b000000000000000000000000000010000000000000000000000000000000000: n4227_o = 4'b1100; + 63'b000000000000000000000000000001000000000000000000000000000000000: n4227_o = 4'b1100; + 63'b000000000000000000000000000000100000000000000000000000000000000: n4227_o = 4'b1100; + 63'b000000000000000000000000000000010000000000000000000000000000000: n4227_o = 4'b1100; + 63'b000000000000000000000000000000001000000000000000000000000000000: n4227_o = 4'b1100; + 63'b000000000000000000000000000000000100000000000000000000000000000: n4227_o = 4'b1100; + 63'b000000000000000000000000000000000010000000000000000000000000000: n4227_o = 4'b1100; + 63'b000000000000000000000000000000000001000000000000000000000000000: n4227_o = 4'b1100; + 63'b000000000000000000000000000000000000100000000000000000000000000: n4227_o = 4'b1100; + 63'b000000000000000000000000000000000000010000000000000000000000000: n4227_o = 4'b1100; + 63'b000000000000000000000000000000000000001000000000000000000000000: n4227_o = 4'b1100; + 63'b000000000000000000000000000000000000000100000000000000000000000: n4227_o = 4'b1100; + 63'b000000000000000000000000000000000000000010000000000000000000000: n4227_o = n2840_o; + 63'b000000000000000000000000000000000000000001000000000000000000000: n4227_o = 4'b1100; + 63'b000000000000000000000000000000000000000000100000000000000000000: n4227_o = 4'b1100; + 63'b000000000000000000000000000000000000000000010000000000000000000: n4227_o = 4'b1100; + 63'b000000000000000000000000000000000000000000001000000000000000000: n4227_o = 4'b1100; + 63'b000000000000000000000000000000000000000000000100000000000000000: n4227_o = 4'b1100; + 63'b000000000000000000000000000000000000000000000010000000000000000: n4227_o = n2709_o; + 63'b000000000000000000000000000000000000000000000001000000000000000: n4227_o = 4'b1100; + 63'b000000000000000000000000000000000000000000000000100000000000000: n4227_o = 4'b1100; + 63'b000000000000000000000000000000000000000000000000010000000000000: n4227_o = n2623_o; + 63'b000000000000000000000000000000000000000000000000001000000000000: n4227_o = n2574_o; + 63'b000000000000000000000000000000000000000000000000000100000000000: n4227_o = 4'b1100; + 63'b000000000000000000000000000000000000000000000000000010000000000: n4227_o = 4'b1100; + 63'b000000000000000000000000000000000000000000000000000001000000000: n4227_o = n2512_o; + 63'b000000000000000000000000000000000000000000000000000000100000000: n4227_o = 4'b1100; + 63'b000000000000000000000000000000000000000000000000000000010000000: n4227_o = 4'b1100; + 63'b000000000000000000000000000000000000000000000000000000001000000: n4227_o = n2476_o; + 63'b000000000000000000000000000000000000000000000000000000000100000: n4227_o = 4'b1100; + 63'b000000000000000000000000000000000000000000000000000000000010000: n4227_o = n2339_o; + 63'b000000000000000000000000000000000000000000000000000000000001000: n4227_o = n2233_o; + 63'b000000000000000000000000000000000000000000000000000000000000100: n4227_o = n2201_o; + 63'b000000000000000000000000000000000000000000000000000000000000010: n4227_o = n2145_o; + 63'b000000000000000000000000000000000000000000000000000000000000001: n4227_o = n2089_o; + default: n4227_o = 4'b1100; + endcase + /* decoder.vhd:635:5 */ + always @* + case (n4151_o) + 63'b100000000000000000000000000000000000000000000000000000000000000: n4230_o = 1'b0; + 63'b010000000000000000000000000000000000000000000000000000000000000: n4230_o = 1'b0; + 63'b001000000000000000000000000000000000000000000000000000000000000: n4230_o = 1'b0; + 63'b000100000000000000000000000000000000000000000000000000000000000: n4230_o = 1'b0; + 63'b000010000000000000000000000000000000000000000000000000000000000: n4230_o = 1'b0; + 63'b000001000000000000000000000000000000000000000000000000000000000: n4230_o = 1'b0; + 63'b000000100000000000000000000000000000000000000000000000000000000: n4230_o = 1'b0; + 63'b000000010000000000000000000000000000000000000000000000000000000: n4230_o = 1'b0; + 63'b000000001000000000000000000000000000000000000000000000000000000: n4230_o = n3951_o; + 63'b000000000100000000000000000000000000000000000000000000000000000: n4230_o = n3922_o; + 63'b000000000010000000000000000000000000000000000000000000000000000: n4230_o = 1'b0; + 63'b000000000001000000000000000000000000000000000000000000000000000: n4230_o = 1'b0; + 63'b000000000000100000000000000000000000000000000000000000000000000: n4230_o = 1'b0; + 63'b000000000000010000000000000000000000000000000000000000000000000: n4230_o = 1'b0; + 63'b000000000000001000000000000000000000000000000000000000000000000: n4230_o = 1'b0; + 63'b000000000000000100000000000000000000000000000000000000000000000: n4230_o = 1'b0; + 63'b000000000000000010000000000000000000000000000000000000000000000: n4230_o = 1'b0; + 63'b000000000000000001000000000000000000000000000000000000000000000: n4230_o = 1'b0; + 63'b000000000000000000100000000000000000000000000000000000000000000: n4230_o = 1'b0; + 63'b000000000000000000010000000000000000000000000000000000000000000: n4230_o = 1'b0; + 63'b000000000000000000001000000000000000000000000000000000000000000: n4230_o = 1'b0; + 63'b000000000000000000000100000000000000000000000000000000000000000: n4230_o = 1'b0; + 63'b000000000000000000000010000000000000000000000000000000000000000: n4230_o = 1'b0; + 63'b000000000000000000000001000000000000000000000000000000000000000: n4230_o = 1'b0; + 63'b000000000000000000000000100000000000000000000000000000000000000: n4230_o = 1'b0; + 63'b000000000000000000000000010000000000000000000000000000000000000: n4230_o = 1'b0; + 63'b000000000000000000000000001000000000000000000000000000000000000: n4230_o = 1'b0; + 63'b000000000000000000000000000100000000000000000000000000000000000: n4230_o = 1'b0; + 63'b000000000000000000000000000010000000000000000000000000000000000: n4230_o = 1'b0; + 63'b000000000000000000000000000001000000000000000000000000000000000: n4230_o = 1'b0; + 63'b000000000000000000000000000000100000000000000000000000000000000: n4230_o = 1'b0; + 63'b000000000000000000000000000000010000000000000000000000000000000: n4230_o = 1'b0; + 63'b000000000000000000000000000000001000000000000000000000000000000: n4230_o = 1'b0; + 63'b000000000000000000000000000000000100000000000000000000000000000: n4230_o = 1'b0; + 63'b000000000000000000000000000000000010000000000000000000000000000: n4230_o = 1'b0; + 63'b000000000000000000000000000000000001000000000000000000000000000: n4230_o = 1'b0; + 63'b000000000000000000000000000000000000100000000000000000000000000: n4230_o = 1'b0; + 63'b000000000000000000000000000000000000010000000000000000000000000: n4230_o = 1'b0; + 63'b000000000000000000000000000000000000001000000000000000000000000: n4230_o = 1'b0; + 63'b000000000000000000000000000000000000000100000000000000000000000: n4230_o = 1'b0; + 63'b000000000000000000000000000000000000000010000000000000000000000: n4230_o = 1'b0; + 63'b000000000000000000000000000000000000000001000000000000000000000: n4230_o = 1'b0; + 63'b000000000000000000000000000000000000000000100000000000000000000: n4230_o = 1'b0; + 63'b000000000000000000000000000000000000000000010000000000000000000: n4230_o = 1'b0; + 63'b000000000000000000000000000000000000000000001000000000000000000: n4230_o = 1'b0; + 63'b000000000000000000000000000000000000000000000100000000000000000: n4230_o = 1'b0; + 63'b000000000000000000000000000000000000000000000010000000000000000: n4230_o = 1'b0; + 63'b000000000000000000000000000000000000000000000001000000000000000: n4230_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000100000000000000: n4230_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000010000000000000: n4230_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000001000000000000: n4230_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000100000000000: n4230_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000010000000000: n4230_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000001000000000: n4230_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000100000000: n4230_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000010000000: n4230_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000001000000: n4230_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000100000: n4230_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000010000: n4230_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000001000: n4230_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000000100: n4230_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000000010: n4230_o = n2147_o; + 63'b000000000000000000000000000000000000000000000000000000000000001: n4230_o = n2091_o; + default: n4230_o = 1'b0; + endcase + /* decoder.vhd:635:5 */ + always @* + case (n4151_o) + 63'b100000000000000000000000000000000000000000000000000000000000000: n4233_o = 1'b0; + 63'b010000000000000000000000000000000000000000000000000000000000000: n4233_o = 1'b0; + 63'b001000000000000000000000000000000000000000000000000000000000000: n4233_o = 1'b0; + 63'b000100000000000000000000000000000000000000000000000000000000000: n4233_o = 1'b0; + 63'b000010000000000000000000000000000000000000000000000000000000000: n4233_o = 1'b0; + 63'b000001000000000000000000000000000000000000000000000000000000000: n4233_o = 1'b0; + 63'b000000100000000000000000000000000000000000000000000000000000000: n4233_o = 1'b0; + 63'b000000010000000000000000000000000000000000000000000000000000000: n4233_o = 1'b0; + 63'b000000001000000000000000000000000000000000000000000000000000000: n4233_o = 1'b0; + 63'b000000000100000000000000000000000000000000000000000000000000000: n4233_o = 1'b0; + 63'b000000000010000000000000000000000000000000000000000000000000000: n4233_o = 1'b0; + 63'b000000000001000000000000000000000000000000000000000000000000000: n4233_o = 1'b0; + 63'b000000000000100000000000000000000000000000000000000000000000000: n4233_o = 1'b0; + 63'b000000000000010000000000000000000000000000000000000000000000000: n4233_o = 1'b0; + 63'b000000000000001000000000000000000000000000000000000000000000000: n4233_o = 1'b0; + 63'b000000000000000100000000000000000000000000000000000000000000000: n4233_o = 1'b0; + 63'b000000000000000010000000000000000000000000000000000000000000000: n4233_o = 1'b0; + 63'b000000000000000001000000000000000000000000000000000000000000000: n4233_o = 1'b0; + 63'b000000000000000000100000000000000000000000000000000000000000000: n4233_o = 1'b0; + 63'b000000000000000000010000000000000000000000000000000000000000000: n4233_o = 1'b0; + 63'b000000000000000000001000000000000000000000000000000000000000000: n4233_o = 1'b0; + 63'b000000000000000000000100000000000000000000000000000000000000000: n4233_o = 1'b0; + 63'b000000000000000000000010000000000000000000000000000000000000000: n4233_o = 1'b0; + 63'b000000000000000000000001000000000000000000000000000000000000000: n4233_o = 1'b0; + 63'b000000000000000000000000100000000000000000000000000000000000000: n4233_o = 1'b0; + 63'b000000000000000000000000010000000000000000000000000000000000000: n4233_o = 1'b0; + 63'b000000000000000000000000001000000000000000000000000000000000000: n4233_o = 1'b0; + 63'b000000000000000000000000000100000000000000000000000000000000000: n4233_o = 1'b0; + 63'b000000000000000000000000000010000000000000000000000000000000000: n4233_o = 1'b0; + 63'b000000000000000000000000000001000000000000000000000000000000000: n4233_o = 1'b0; + 63'b000000000000000000000000000000100000000000000000000000000000000: n4233_o = 1'b0; + 63'b000000000000000000000000000000010000000000000000000000000000000: n4233_o = 1'b0; + 63'b000000000000000000000000000000001000000000000000000000000000000: n4233_o = 1'b0; + 63'b000000000000000000000000000000000100000000000000000000000000000: n4233_o = 1'b0; + 63'b000000000000000000000000000000000010000000000000000000000000000: n4233_o = 1'b0; + 63'b000000000000000000000000000000000001000000000000000000000000000: n4233_o = 1'b0; + 63'b000000000000000000000000000000000000100000000000000000000000000: n4233_o = 1'b0; + 63'b000000000000000000000000000000000000010000000000000000000000000: n4233_o = 1'b0; + 63'b000000000000000000000000000000000000001000000000000000000000000: n4233_o = 1'b0; + 63'b000000000000000000000000000000000000000100000000000000000000000: n4233_o = 1'b0; + 63'b000000000000000000000000000000000000000010000000000000000000000: n4233_o = 1'b0; + 63'b000000000000000000000000000000000000000001000000000000000000000: n4233_o = 1'b0; + 63'b000000000000000000000000000000000000000000100000000000000000000: n4233_o = 1'b0; + 63'b000000000000000000000000000000000000000000010000000000000000000: n4233_o = 1'b0; + 63'b000000000000000000000000000000000000000000001000000000000000000: n4233_o = 1'b0; + 63'b000000000000000000000000000000000000000000000100000000000000000: n4233_o = 1'b0; + 63'b000000000000000000000000000000000000000000000010000000000000000: n4233_o = 1'b0; + 63'b000000000000000000000000000000000000000000000001000000000000000: n4233_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000100000000000000: n4233_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000010000000000000: n4233_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000001000000000000: n4233_o = n2578_o; + 63'b000000000000000000000000000000000000000000000000000100000000000: n4233_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000010000000000: n4233_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000001000000000: n4233_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000100000000: n4233_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000010000000: n4233_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000001000000: n4233_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000100000: n4233_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000010000: n4233_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000001000: n4233_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000000100: n4233_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000000010: n4233_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000000001: n4233_o = 1'b0; + default: n4233_o = 1'b0; + endcase + /* decoder.vhd:635:5 */ + always @* + case (n4151_o) + 63'b100000000000000000000000000000000000000000000000000000000000000: n4236_o = 1'b0; + 63'b010000000000000000000000000000000000000000000000000000000000000: n4236_o = 1'b0; + 63'b001000000000000000000000000000000000000000000000000000000000000: n4236_o = n4063_o; + 63'b000100000000000000000000000000000000000000000000000000000000000: n4236_o = 1'b0; + 63'b000010000000000000000000000000000000000000000000000000000000000: n4236_o = 1'b0; + 63'b000001000000000000000000000000000000000000000000000000000000000: n4236_o = 1'b0; + 63'b000000100000000000000000000000000000000000000000000000000000000: n4236_o = 1'b0; + 63'b000000010000000000000000000000000000000000000000000000000000000: n4236_o = 1'b0; + 63'b000000001000000000000000000000000000000000000000000000000000000: n4236_o = 1'b0; + 63'b000000000100000000000000000000000000000000000000000000000000000: n4236_o = 1'b0; + 63'b000000000010000000000000000000000000000000000000000000000000000: n4236_o = 1'b0; + 63'b000000000001000000000000000000000000000000000000000000000000000: n4236_o = 1'b0; + 63'b000000000000100000000000000000000000000000000000000000000000000: n4236_o = 1'b0; + 63'b000000000000010000000000000000000000000000000000000000000000000: n4236_o = 1'b0; + 63'b000000000000001000000000000000000000000000000000000000000000000: n4236_o = 1'b0; + 63'b000000000000000100000000000000000000000000000000000000000000000: n4236_o = 1'b0; + 63'b000000000000000010000000000000000000000000000000000000000000000: n4236_o = 1'b0; + 63'b000000000000000001000000000000000000000000000000000000000000000: n4236_o = 1'b0; + 63'b000000000000000000100000000000000000000000000000000000000000000: n4236_o = 1'b0; + 63'b000000000000000000010000000000000000000000000000000000000000000: n4236_o = 1'b0; + 63'b000000000000000000001000000000000000000000000000000000000000000: n4236_o = 1'b0; + 63'b000000000000000000000100000000000000000000000000000000000000000: n4236_o = 1'b0; + 63'b000000000000000000000010000000000000000000000000000000000000000: n4236_o = 1'b0; + 63'b000000000000000000000001000000000000000000000000000000000000000: n4236_o = 1'b0; + 63'b000000000000000000000000100000000000000000000000000000000000000: n4236_o = 1'b0; + 63'b000000000000000000000000010000000000000000000000000000000000000: n4236_o = 1'b0; + 63'b000000000000000000000000001000000000000000000000000000000000000: n4236_o = 1'b0; + 63'b000000000000000000000000000100000000000000000000000000000000000: n4236_o = 1'b0; + 63'b000000000000000000000000000010000000000000000000000000000000000: n4236_o = 1'b0; + 63'b000000000000000000000000000001000000000000000000000000000000000: n4236_o = 1'b0; + 63'b000000000000000000000000000000100000000000000000000000000000000: n4236_o = 1'b0; + 63'b000000000000000000000000000000010000000000000000000000000000000: n4236_o = 1'b0; + 63'b000000000000000000000000000000001000000000000000000000000000000: n4236_o = 1'b0; + 63'b000000000000000000000000000000000100000000000000000000000000000: n4236_o = 1'b0; + 63'b000000000000000000000000000000000010000000000000000000000000000: n4236_o = 1'b0; + 63'b000000000000000000000000000000000001000000000000000000000000000: n4236_o = 1'b0; + 63'b000000000000000000000000000000000000100000000000000000000000000: n4236_o = 1'b0; + 63'b000000000000000000000000000000000000010000000000000000000000000: n4236_o = 1'b0; + 63'b000000000000000000000000000000000000001000000000000000000000000: n4236_o = 1'b0; + 63'b000000000000000000000000000000000000000100000000000000000000000: n4236_o = 1'b0; + 63'b000000000000000000000000000000000000000010000000000000000000000: n4236_o = 1'b0; + 63'b000000000000000000000000000000000000000001000000000000000000000: n4236_o = 1'b0; + 63'b000000000000000000000000000000000000000000100000000000000000000: n4236_o = 1'b0; + 63'b000000000000000000000000000000000000000000010000000000000000000: n4236_o = 1'b0; + 63'b000000000000000000000000000000000000000000001000000000000000000: n4236_o = 1'b0; + 63'b000000000000000000000000000000000000000000000100000000000000000: n4236_o = 1'b0; + 63'b000000000000000000000000000000000000000000000010000000000000000: n4236_o = 1'b0; + 63'b000000000000000000000000000000000000000000000001000000000000000: n4236_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000100000000000000: n4236_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000010000000000000: n4236_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000001000000000000: n4236_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000100000000000: n4236_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000010000000000: n4236_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000001000000000: n4236_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000100000000: n4236_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000010000000: n4236_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000001000000: n4236_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000100000: n4236_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000010000: n4236_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000001000: n4236_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000000100: n4236_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000000010: n4236_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000000001: n4236_o = 1'b0; + default: n4236_o = 1'b0; + endcase + /* decoder.vhd:635:5 */ + always @* + case (n4151_o) + 63'b100000000000000000000000000000000000000000000000000000000000000: n4239_o = 1'b0; + 63'b010000000000000000000000000000000000000000000000000000000000000: n4239_o = 1'b0; + 63'b001000000000000000000000000000000000000000000000000000000000000: n4239_o = 1'b0; + 63'b000100000000000000000000000000000000000000000000000000000000000: n4239_o = 1'b0; + 63'b000010000000000000000000000000000000000000000000000000000000000: n4239_o = 1'b0; + 63'b000001000000000000000000000000000000000000000000000000000000000: n4239_o = 1'b0; + 63'b000000100000000000000000000000000000000000000000000000000000000: n4239_o = 1'b0; + 63'b000000010000000000000000000000000000000000000000000000000000000: n4239_o = 1'b0; + 63'b000000001000000000000000000000000000000000000000000000000000000: n4239_o = 1'b0; + 63'b000000000100000000000000000000000000000000000000000000000000000: n4239_o = 1'b0; + 63'b000000000010000000000000000000000000000000000000000000000000000: n4239_o = 1'b0; + 63'b000000000001000000000000000000000000000000000000000000000000000: n4239_o = 1'b0; + 63'b000000000000100000000000000000000000000000000000000000000000000: n4239_o = 1'b0; + 63'b000000000000010000000000000000000000000000000000000000000000000: n4239_o = 1'b0; + 63'b000000000000001000000000000000000000000000000000000000000000000: n4239_o = 1'b0; + 63'b000000000000000100000000000000000000000000000000000000000000000: n4239_o = 1'b0; + 63'b000000000000000010000000000000000000000000000000000000000000000: n4239_o = 1'b0; + 63'b000000000000000001000000000000000000000000000000000000000000000: n4239_o = 1'b0; + 63'b000000000000000000100000000000000000000000000000000000000000000: n4239_o = 1'b0; + 63'b000000000000000000010000000000000000000000000000000000000000000: n4239_o = 1'b0; + 63'b000000000000000000001000000000000000000000000000000000000000000: n4239_o = 1'b0; + 63'b000000000000000000000100000000000000000000000000000000000000000: n4239_o = 1'b0; + 63'b000000000000000000000010000000000000000000000000000000000000000: n4239_o = 1'b0; + 63'b000000000000000000000001000000000000000000000000000000000000000: n4239_o = 1'b0; + 63'b000000000000000000000000100000000000000000000000000000000000000: n4239_o = 1'b0; + 63'b000000000000000000000000010000000000000000000000000000000000000: n4239_o = 1'b0; + 63'b000000000000000000000000001000000000000000000000000000000000000: n4239_o = 1'b0; + 63'b000000000000000000000000000100000000000000000000000000000000000: n4239_o = 1'b0; + 63'b000000000000000000000000000010000000000000000000000000000000000: n4239_o = 1'b0; + 63'b000000000000000000000000000001000000000000000000000000000000000: n4239_o = 1'b0; + 63'b000000000000000000000000000000100000000000000000000000000000000: n4239_o = 1'b0; + 63'b000000000000000000000000000000010000000000000000000000000000000: n4239_o = 1'b0; + 63'b000000000000000000000000000000001000000000000000000000000000000: n4239_o = 1'b0; + 63'b000000000000000000000000000000000100000000000000000000000000000: n4239_o = 1'b0; + 63'b000000000000000000000000000000000010000000000000000000000000000: n4239_o = 1'b0; + 63'b000000000000000000000000000000000001000000000000000000000000000: n4239_o = 1'b0; + 63'b000000000000000000000000000000000000100000000000000000000000000: n4239_o = 1'b0; + 63'b000000000000000000000000000000000000010000000000000000000000000: n4239_o = 1'b0; + 63'b000000000000000000000000000000000000001000000000000000000000000: n4239_o = 1'b0; + 63'b000000000000000000000000000000000000000100000000000000000000000: n4239_o = 1'b0; + 63'b000000000000000000000000000000000000000010000000000000000000000: n4239_o = 1'b0; + 63'b000000000000000000000000000000000000000001000000000000000000000: n4239_o = 1'b0; + 63'b000000000000000000000000000000000000000000100000000000000000000: n4239_o = 1'b0; + 63'b000000000000000000000000000000000000000000010000000000000000000: n4239_o = 1'b0; + 63'b000000000000000000000000000000000000000000001000000000000000000: n4239_o = 1'b0; + 63'b000000000000000000000000000000000000000000000100000000000000000: n4239_o = 1'b0; + 63'b000000000000000000000000000000000000000000000010000000000000000: n4239_o = 1'b0; + 63'b000000000000000000000000000000000000000000000001000000000000000: n4239_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000100000000000000: n4239_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000010000000000000: n4239_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000001000000000000: n4239_o = n2581_o; + 63'b000000000000000000000000000000000000000000000000000100000000000: n4239_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000010000000000: n4239_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000001000000000: n4239_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000100000000: n4239_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000010000000: n4239_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000001000000: n4239_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000100000: n4239_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000010000: n4239_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000001000: n4239_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000000100: n4239_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000000010: n4239_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000000001: n4239_o = 1'b0; + default: n4239_o = 1'b0; + endcase + /* decoder.vhd:635:5 */ + always @* + case (n4151_o) + 63'b100000000000000000000000000000000000000000000000000000000000000: n4242_o = 1'b0; + 63'b010000000000000000000000000000000000000000000000000000000000000: n4242_o = 1'b0; + 63'b001000000000000000000000000000000000000000000000000000000000000: n4242_o = 1'b0; + 63'b000100000000000000000000000000000000000000000000000000000000000: n4242_o = 1'b0; + 63'b000010000000000000000000000000000000000000000000000000000000000: n4242_o = 1'b0; + 63'b000001000000000000000000000000000000000000000000000000000000000: n4242_o = 1'b0; + 63'b000000100000000000000000000000000000000000000000000000000000000: n4242_o = 1'b0; + 63'b000000010000000000000000000000000000000000000000000000000000000: n4242_o = 1'b0; + 63'b000000001000000000000000000000000000000000000000000000000000000: n4242_o = 1'b0; + 63'b000000000100000000000000000000000000000000000000000000000000000: n4242_o = 1'b0; + 63'b000000000010000000000000000000000000000000000000000000000000000: n4242_o = 1'b0; + 63'b000000000001000000000000000000000000000000000000000000000000000: n4242_o = 1'b0; + 63'b000000000000100000000000000000000000000000000000000000000000000: n4242_o = 1'b0; + 63'b000000000000010000000000000000000000000000000000000000000000000: n4242_o = 1'b0; + 63'b000000000000001000000000000000000000000000000000000000000000000: n4242_o = 1'b0; + 63'b000000000000000100000000000000000000000000000000000000000000000: n4242_o = 1'b0; + 63'b000000000000000010000000000000000000000000000000000000000000000: n4242_o = 1'b0; + 63'b000000000000000001000000000000000000000000000000000000000000000: n4242_o = 1'b0; + 63'b000000000000000000100000000000000000000000000000000000000000000: n4242_o = 1'b0; + 63'b000000000000000000010000000000000000000000000000000000000000000: n4242_o = 1'b0; + 63'b000000000000000000001000000000000000000000000000000000000000000: n4242_o = 1'b0; + 63'b000000000000000000000100000000000000000000000000000000000000000: n4242_o = 1'b0; + 63'b000000000000000000000010000000000000000000000000000000000000000: n4242_o = 1'b0; + 63'b000000000000000000000001000000000000000000000000000000000000000: n4242_o = 1'b0; + 63'b000000000000000000000000100000000000000000000000000000000000000: n4242_o = 1'b0; + 63'b000000000000000000000000010000000000000000000000000000000000000: n4242_o = 1'b0; + 63'b000000000000000000000000001000000000000000000000000000000000000: n4242_o = 1'b0; + 63'b000000000000000000000000000100000000000000000000000000000000000: n4242_o = 1'b0; + 63'b000000000000000000000000000010000000000000000000000000000000000: n4242_o = 1'b0; + 63'b000000000000000000000000000001000000000000000000000000000000000: n4242_o = 1'b0; + 63'b000000000000000000000000000000100000000000000000000000000000000: n4242_o = 1'b0; + 63'b000000000000000000000000000000010000000000000000000000000000000: n4242_o = 1'b0; + 63'b000000000000000000000000000000001000000000000000000000000000000: n4242_o = 1'b0; + 63'b000000000000000000000000000000000100000000000000000000000000000: n4242_o = 1'b0; + 63'b000000000000000000000000000000000010000000000000000000000000000: n4242_o = 1'b0; + 63'b000000000000000000000000000000000001000000000000000000000000000: n4242_o = 1'b0; + 63'b000000000000000000000000000000000000100000000000000000000000000: n4242_o = 1'b0; + 63'b000000000000000000000000000000000000010000000000000000000000000: n4242_o = 1'b0; + 63'b000000000000000000000000000000000000001000000000000000000000000: n4242_o = 1'b0; + 63'b000000000000000000000000000000000000000100000000000000000000000: n4242_o = 1'b0; + 63'b000000000000000000000000000000000000000010000000000000000000000: n4242_o = 1'b0; + 63'b000000000000000000000000000000000000000001000000000000000000000: n4242_o = 1'b0; + 63'b000000000000000000000000000000000000000000100000000000000000000: n4242_o = 1'b0; + 63'b000000000000000000000000000000000000000000010000000000000000000: n4242_o = 1'b0; + 63'b000000000000000000000000000000000000000000001000000000000000000: n4242_o = 1'b0; + 63'b000000000000000000000000000000000000000000000100000000000000000: n4242_o = 1'b0; + 63'b000000000000000000000000000000000000000000000010000000000000000: n4242_o = 1'b0; + 63'b000000000000000000000000000000000000000000000001000000000000000: n4242_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000100000000000000: n4242_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000010000000000000: n4242_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000001000000000000: n4242_o = n2584_o; + 63'b000000000000000000000000000000000000000000000000000100000000000: n4242_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000010000000000: n4242_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000001000000000: n4242_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000100000000: n4242_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000010000000: n4242_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000001000000: n4242_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000100000: n4242_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000010000: n4242_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000001000: n4242_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000000100: n4242_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000000010: n4242_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000000001: n4242_o = 1'b0; + default: n4242_o = 1'b0; + endcase + /* decoder.vhd:635:5 */ + always @* + case (n4151_o) + 63'b100000000000000000000000000000000000000000000000000000000000000: n4246_o = 1'b0; + 63'b010000000000000000000000000000000000000000000000000000000000000: n4246_o = 1'b0; + 63'b001000000000000000000000000000000000000000000000000000000000000: n4246_o = 1'b0; + 63'b000100000000000000000000000000000000000000000000000000000000000: n4246_o = 1'b0; + 63'b000010000000000000000000000000000000000000000000000000000000000: n4246_o = 1'b0; + 63'b000001000000000000000000000000000000000000000000000000000000000: n4246_o = 1'b0; + 63'b000000100000000000000000000000000000000000000000000000000000000: n4246_o = 1'b0; + 63'b000000010000000000000000000000000000000000000000000000000000000: n4246_o = 1'b0; + 63'b000000001000000000000000000000000000000000000000000000000000000: n4246_o = 1'b0; + 63'b000000000100000000000000000000000000000000000000000000000000000: n4246_o = 1'b0; + 63'b000000000010000000000000000000000000000000000000000000000000000: n4246_o = 1'b0; + 63'b000000000001000000000000000000000000000000000000000000000000000: n4246_o = 1'b0; + 63'b000000000000100000000000000000000000000000000000000000000000000: n4246_o = 1'b0; + 63'b000000000000010000000000000000000000000000000000000000000000000: n4246_o = 1'b0; + 63'b000000000000001000000000000000000000000000000000000000000000000: n4246_o = 1'b0; + 63'b000000000000000100000000000000000000000000000000000000000000000: n4246_o = 1'b0; + 63'b000000000000000010000000000000000000000000000000000000000000000: n4246_o = 1'b0; + 63'b000000000000000001000000000000000000000000000000000000000000000: n4246_o = 1'b1; + 63'b000000000000000000100000000000000000000000000000000000000000000: n4246_o = 1'b0; + 63'b000000000000000000010000000000000000000000000000000000000000000: n4246_o = 1'b0; + 63'b000000000000000000001000000000000000000000000000000000000000000: n4246_o = 1'b0; + 63'b000000000000000000000100000000000000000000000000000000000000000: n4246_o = 1'b0; + 63'b000000000000000000000010000000000000000000000000000000000000000: n4246_o = 1'b0; + 63'b000000000000000000000001000000000000000000000000000000000000000: n4246_o = 1'b0; + 63'b000000000000000000000000100000000000000000000000000000000000000: n4246_o = 1'b0; + 63'b000000000000000000000000010000000000000000000000000000000000000: n4246_o = 1'b0; + 63'b000000000000000000000000001000000000000000000000000000000000000: n4246_o = 1'b0; + 63'b000000000000000000000000000100000000000000000000000000000000000: n4246_o = 1'b0; + 63'b000000000000000000000000000010000000000000000000000000000000000: n4246_o = 1'b0; + 63'b000000000000000000000000000001000000000000000000000000000000000: n4246_o = 1'b0; + 63'b000000000000000000000000000000100000000000000000000000000000000: n4246_o = 1'b0; + 63'b000000000000000000000000000000010000000000000000000000000000000: n4246_o = 1'b0; + 63'b000000000000000000000000000000001000000000000000000000000000000: n4246_o = 1'b0; + 63'b000000000000000000000000000000000100000000000000000000000000000: n4246_o = 1'b0; + 63'b000000000000000000000000000000000010000000000000000000000000000: n4246_o = 1'b0; + 63'b000000000000000000000000000000000001000000000000000000000000000: n4246_o = 1'b0; + 63'b000000000000000000000000000000000000100000000000000000000000000: n4246_o = 1'b0; + 63'b000000000000000000000000000000000000010000000000000000000000000: n4246_o = 1'b0; + 63'b000000000000000000000000000000000000001000000000000000000000000: n4246_o = 1'b0; + 63'b000000000000000000000000000000000000000100000000000000000000000: n4246_o = 1'b0; + 63'b000000000000000000000000000000000000000010000000000000000000000: n4246_o = 1'b0; + 63'b000000000000000000000000000000000000000001000000000000000000000: n4246_o = 1'b0; + 63'b000000000000000000000000000000000000000000100000000000000000000: n4246_o = 1'b0; + 63'b000000000000000000000000000000000000000000010000000000000000000: n4246_o = 1'b0; + 63'b000000000000000000000000000000000000000000001000000000000000000: n4246_o = 1'b0; + 63'b000000000000000000000000000000000000000000000100000000000000000: n4246_o = 1'b0; + 63'b000000000000000000000000000000000000000000000010000000000000000: n4246_o = 1'b0; + 63'b000000000000000000000000000000000000000000000001000000000000000: n4246_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000100000000000000: n4246_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000010000000000000: n4246_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000001000000000000: n4246_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000100000000000: n4246_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000010000000000: n4246_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000001000000000: n4246_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000100000000: n4246_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000010000000: n4246_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000001000000: n4246_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000100000: n4246_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000010000: n4246_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000001000: n4246_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000000100: n4246_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000000010: n4246_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000000001: n4246_o = 1'b0; + default: n4246_o = 1'b0; + endcase + /* decoder.vhd:635:5 */ + always @* + case (n4151_o) + 63'b100000000000000000000000000000000000000000000000000000000000000: n4251_o = 1'b0; + 63'b010000000000000000000000000000000000000000000000000000000000000: n4251_o = 1'b0; + 63'b001000000000000000000000000000000000000000000000000000000000000: n4251_o = 1'b0; + 63'b000100000000000000000000000000000000000000000000000000000000000: n4251_o = 1'b0; + 63'b000010000000000000000000000000000000000000000000000000000000000: n4251_o = 1'b0; + 63'b000001000000000000000000000000000000000000000000000000000000000: n4251_o = 1'b0; + 63'b000000100000000000000000000000000000000000000000000000000000000: n4251_o = 1'b0; + 63'b000000010000000000000000000000000000000000000000000000000000000: n4251_o = 1'b0; + 63'b000000001000000000000000000000000000000000000000000000000000000: n4251_o = 1'b0; + 63'b000000000100000000000000000000000000000000000000000000000000000: n4251_o = 1'b0; + 63'b000000000010000000000000000000000000000000000000000000000000000: n4251_o = 1'b0; + 63'b000000000001000000000000000000000000000000000000000000000000000: n4251_o = 1'b0; + 63'b000000000000100000000000000000000000000000000000000000000000000: n4251_o = 1'b0; + 63'b000000000000010000000000000000000000000000000000000000000000000: n4251_o = 1'b0; + 63'b000000000000001000000000000000000000000000000000000000000000000: n4251_o = 1'b0; + 63'b000000000000000100000000000000000000000000000000000000000000000: n4251_o = 1'b0; + 63'b000000000000000010000000000000000000000000000000000000000000000: n4251_o = 1'b0; + 63'b000000000000000001000000000000000000000000000000000000000000000: n4251_o = 1'b0; + 63'b000000000000000000100000000000000000000000000000000000000000000: n4251_o = 1'b0; + 63'b000000000000000000010000000000000000000000000000000000000000000: n4251_o = 1'b1; + 63'b000000000000000000001000000000000000000000000000000000000000000: n4251_o = 1'b1; + 63'b000000000000000000000100000000000000000000000000000000000000000: n4251_o = 1'b0; + 63'b000000000000000000000010000000000000000000000000000000000000000: n4251_o = 1'b0; + 63'b000000000000000000000001000000000000000000000000000000000000000: n4251_o = 1'b0; + 63'b000000000000000000000000100000000000000000000000000000000000000: n4251_o = 1'b0; + 63'b000000000000000000000000010000000000000000000000000000000000000: n4251_o = 1'b0; + 63'b000000000000000000000000001000000000000000000000000000000000000: n4251_o = 1'b0; + 63'b000000000000000000000000000100000000000000000000000000000000000: n4251_o = 1'b0; + 63'b000000000000000000000000000010000000000000000000000000000000000: n4251_o = 1'b0; + 63'b000000000000000000000000000001000000000000000000000000000000000: n4251_o = 1'b0; + 63'b000000000000000000000000000000100000000000000000000000000000000: n4251_o = 1'b0; + 63'b000000000000000000000000000000010000000000000000000000000000000: n4251_o = 1'b0; + 63'b000000000000000000000000000000001000000000000000000000000000000: n4251_o = 1'b0; + 63'b000000000000000000000000000000000100000000000000000000000000000: n4251_o = 1'b0; + 63'b000000000000000000000000000000000010000000000000000000000000000: n4251_o = 1'b0; + 63'b000000000000000000000000000000000001000000000000000000000000000: n4251_o = 1'b0; + 63'b000000000000000000000000000000000000100000000000000000000000000: n4251_o = 1'b0; + 63'b000000000000000000000000000000000000010000000000000000000000000: n4251_o = 1'b0; + 63'b000000000000000000000000000000000000001000000000000000000000000: n4251_o = 1'b0; + 63'b000000000000000000000000000000000000000100000000000000000000000: n4251_o = 1'b0; + 63'b000000000000000000000000000000000000000010000000000000000000000: n4251_o = 1'b0; + 63'b000000000000000000000000000000000000000001000000000000000000000: n4251_o = 1'b0; + 63'b000000000000000000000000000000000000000000100000000000000000000: n4251_o = 1'b0; + 63'b000000000000000000000000000000000000000000010000000000000000000: n4251_o = 1'b0; + 63'b000000000000000000000000000000000000000000001000000000000000000: n4251_o = 1'b0; + 63'b000000000000000000000000000000000000000000000100000000000000000: n4251_o = 1'b0; + 63'b000000000000000000000000000000000000000000000010000000000000000: n4251_o = 1'b0; + 63'b000000000000000000000000000000000000000000000001000000000000000: n4251_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000100000000000000: n4251_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000010000000000000: n4251_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000001000000000000: n4251_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000100000000000: n4251_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000010000000000: n4251_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000001000000000: n4251_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000100000000: n4251_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000010000000: n4251_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000001000000: n4251_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000100000: n4251_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000010000: n4251_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000001000: n4251_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000000100: n4251_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000000010: n4251_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000000001: n4251_o = 1'b0; + default: n4251_o = 1'b0; + endcase + /* decoder.vhd:635:5 */ + always @* + case (n4151_o) + 63'b100000000000000000000000000000000000000000000000000000000000000: n4255_o = 1'b0; + 63'b010000000000000000000000000000000000000000000000000000000000000: n4255_o = 1'b0; + 63'b001000000000000000000000000000000000000000000000000000000000000: n4255_o = 1'b0; + 63'b000100000000000000000000000000000000000000000000000000000000000: n4255_o = 1'b0; + 63'b000010000000000000000000000000000000000000000000000000000000000: n4255_o = 1'b0; + 63'b000001000000000000000000000000000000000000000000000000000000000: n4255_o = 1'b0; + 63'b000000100000000000000000000000000000000000000000000000000000000: n4255_o = 1'b0; + 63'b000000010000000000000000000000000000000000000000000000000000000: n4255_o = 1'b0; + 63'b000000001000000000000000000000000000000000000000000000000000000: n4255_o = 1'b0; + 63'b000000000100000000000000000000000000000000000000000000000000000: n4255_o = 1'b0; + 63'b000000000010000000000000000000000000000000000000000000000000000: n4255_o = 1'b0; + 63'b000000000001000000000000000000000000000000000000000000000000000: n4255_o = 1'b0; + 63'b000000000000100000000000000000000000000000000000000000000000000: n4255_o = 1'b0; + 63'b000000000000010000000000000000000000000000000000000000000000000: n4255_o = 1'b0; + 63'b000000000000001000000000000000000000000000000000000000000000000: n4255_o = 1'b0; + 63'b000000000000000100000000000000000000000000000000000000000000000: n4255_o = 1'b0; + 63'b000000000000000010000000000000000000000000000000000000000000000: n4255_o = 1'b0; + 63'b000000000000000001000000000000000000000000000000000000000000000: n4255_o = n3527_o; + 63'b000000000000000000100000000000000000000000000000000000000000000: n4255_o = 1'b0; + 63'b000000000000000000010000000000000000000000000000000000000000000: n4255_o = 1'b0; + 63'b000000000000000000001000000000000000000000000000000000000000000: n4255_o = 1'b0; + 63'b000000000000000000000100000000000000000000000000000000000000000: n4255_o = 1'b0; + 63'b000000000000000000000010000000000000000000000000000000000000000: n4255_o = 1'b0; + 63'b000000000000000000000001000000000000000000000000000000000000000: n4255_o = 1'b0; + 63'b000000000000000000000000100000000000000000000000000000000000000: n4255_o = 1'b0; + 63'b000000000000000000000000010000000000000000000000000000000000000: n4255_o = 1'b0; + 63'b000000000000000000000000001000000000000000000000000000000000000: n4255_o = 1'b0; + 63'b000000000000000000000000000100000000000000000000000000000000000: n4255_o = 1'b0; + 63'b000000000000000000000000000010000000000000000000000000000000000: n4255_o = 1'b0; + 63'b000000000000000000000000000001000000000000000000000000000000000: n4255_o = 1'b0; + 63'b000000000000000000000000000000100000000000000000000000000000000: n4255_o = 1'b0; + 63'b000000000000000000000000000000010000000000000000000000000000000: n4255_o = 1'b0; + 63'b000000000000000000000000000000001000000000000000000000000000000: n4255_o = 1'b0; + 63'b000000000000000000000000000000000100000000000000000000000000000: n4255_o = 1'b0; + 63'b000000000000000000000000000000000010000000000000000000000000000: n4255_o = 1'b0; + 63'b000000000000000000000000000000000001000000000000000000000000000: n4255_o = 1'b0; + 63'b000000000000000000000000000000000000100000000000000000000000000: n4255_o = 1'b0; + 63'b000000000000000000000000000000000000010000000000000000000000000: n4255_o = 1'b0; + 63'b000000000000000000000000000000000000001000000000000000000000000: n4255_o = 1'b0; + 63'b000000000000000000000000000000000000000100000000000000000000000: n4255_o = 1'b0; + 63'b000000000000000000000000000000000000000010000000000000000000000: n4255_o = 1'b0; + 63'b000000000000000000000000000000000000000001000000000000000000000: n4255_o = 1'b1; + 63'b000000000000000000000000000000000000000000100000000000000000000: n4255_o = 1'b0; + 63'b000000000000000000000000000000000000000000010000000000000000000: n4255_o = 1'b0; + 63'b000000000000000000000000000000000000000000001000000000000000000: n4255_o = 1'b0; + 63'b000000000000000000000000000000000000000000000100000000000000000: n4255_o = 1'b0; + 63'b000000000000000000000000000000000000000000000010000000000000000: n4255_o = 1'b0; + 63'b000000000000000000000000000000000000000000000001000000000000000: n4255_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000100000000000000: n4255_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000010000000000000: n4255_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000001000000000000: n4255_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000100000000000: n4255_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000010000000000: n4255_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000001000000000: n4255_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000100000000: n4255_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000010000000: n4255_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000001000000: n4255_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000100000: n4255_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000010000: n4255_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000001000: n4255_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000000100: n4255_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000000010: n4255_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000000001: n4255_o = 1'b0; + default: n4255_o = 1'b0; + endcase + /* decoder.vhd:635:5 */ + always @* + case (n4151_o) + 63'b100000000000000000000000000000000000000000000000000000000000000: n4258_o = 1'b0; + 63'b010000000000000000000000000000000000000000000000000000000000000: n4258_o = 1'b0; + 63'b001000000000000000000000000000000000000000000000000000000000000: n4258_o = 1'b0; + 63'b000100000000000000000000000000000000000000000000000000000000000: n4258_o = 1'b0; + 63'b000010000000000000000000000000000000000000000000000000000000000: n4258_o = 1'b0; + 63'b000001000000000000000000000000000000000000000000000000000000000: n4258_o = 1'b0; + 63'b000000100000000000000000000000000000000000000000000000000000000: n4258_o = 1'b0; + 63'b000000010000000000000000000000000000000000000000000000000000000: n4258_o = 1'b0; + 63'b000000001000000000000000000000000000000000000000000000000000000: n4258_o = 1'b0; + 63'b000000000100000000000000000000000000000000000000000000000000000: n4258_o = 1'b0; + 63'b000000000010000000000000000000000000000000000000000000000000000: n4258_o = 1'b0; + 63'b000000000001000000000000000000000000000000000000000000000000000: n4258_o = n3797_o; + 63'b000000000000100000000000000000000000000000000000000000000000000: n4258_o = 1'b0; + 63'b000000000000010000000000000000000000000000000000000000000000000: n4258_o = 1'b0; + 63'b000000000000001000000000000000000000000000000000000000000000000: n4258_o = 1'b0; + 63'b000000000000000100000000000000000000000000000000000000000000000: n4258_o = 1'b0; + 63'b000000000000000010000000000000000000000000000000000000000000000: n4258_o = 1'b0; + 63'b000000000000000001000000000000000000000000000000000000000000000: n4258_o = n3530_o; + 63'b000000000000000000100000000000000000000000000000000000000000000: n4258_o = 1'b0; + 63'b000000000000000000010000000000000000000000000000000000000000000: n4258_o = 1'b0; + 63'b000000000000000000001000000000000000000000000000000000000000000: n4258_o = 1'b0; + 63'b000000000000000000000100000000000000000000000000000000000000000: n4258_o = 1'b0; + 63'b000000000000000000000010000000000000000000000000000000000000000: n4258_o = 1'b0; + 63'b000000000000000000000001000000000000000000000000000000000000000: n4258_o = 1'b0; + 63'b000000000000000000000000100000000000000000000000000000000000000: n4258_o = 1'b0; + 63'b000000000000000000000000010000000000000000000000000000000000000: n4258_o = 1'b0; + 63'b000000000000000000000000001000000000000000000000000000000000000: n4258_o = 1'b0; + 63'b000000000000000000000000000100000000000000000000000000000000000: n4258_o = 1'b0; + 63'b000000000000000000000000000010000000000000000000000000000000000: n4258_o = 1'b0; + 63'b000000000000000000000000000001000000000000000000000000000000000: n4258_o = 1'b0; + 63'b000000000000000000000000000000100000000000000000000000000000000: n4258_o = 1'b0; + 63'b000000000000000000000000000000010000000000000000000000000000000: n4258_o = 1'b0; + 63'b000000000000000000000000000000001000000000000000000000000000000: n4258_o = 1'b0; + 63'b000000000000000000000000000000000100000000000000000000000000000: n4258_o = 1'b0; + 63'b000000000000000000000000000000000010000000000000000000000000000: n4258_o = 1'b0; + 63'b000000000000000000000000000000000001000000000000000000000000000: n4258_o = 1'b0; + 63'b000000000000000000000000000000000000100000000000000000000000000: n4258_o = 1'b0; + 63'b000000000000000000000000000000000000010000000000000000000000000: n4258_o = 1'b0; + 63'b000000000000000000000000000000000000001000000000000000000000000: n4258_o = 1'b0; + 63'b000000000000000000000000000000000000000100000000000000000000000: n4258_o = 1'b0; + 63'b000000000000000000000000000000000000000010000000000000000000000: n4258_o = 1'b0; + 63'b000000000000000000000000000000000000000001000000000000000000000: n4258_o = 1'b0; + 63'b000000000000000000000000000000000000000000100000000000000000000: n4258_o = 1'b0; + 63'b000000000000000000000000000000000000000000010000000000000000000: n4258_o = 1'b0; + 63'b000000000000000000000000000000000000000000001000000000000000000: n4258_o = 1'b0; + 63'b000000000000000000000000000000000000000000000100000000000000000: n4258_o = 1'b0; + 63'b000000000000000000000000000000000000000000000010000000000000000: n4258_o = 1'b0; + 63'b000000000000000000000000000000000000000000000001000000000000000: n4258_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000100000000000000: n4258_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000010000000000000: n4258_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000001000000000000: n4258_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000100000000000: n4258_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000010000000000: n4258_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000001000000000: n4258_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000100000000: n4258_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000010000000: n4258_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000001000000: n4258_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000100000: n4258_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000010000: n4258_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000001000: n4258_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000000100: n4258_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000000010: n4258_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000000001: n4258_o = 1'b0; + default: n4258_o = 1'b0; + endcase + /* decoder.vhd:635:5 */ + always @* + case (n4151_o) + 63'b100000000000000000000000000000000000000000000000000000000000000: n4261_o = 1'b0; + 63'b010000000000000000000000000000000000000000000000000000000000000: n4261_o = 1'b0; + 63'b001000000000000000000000000000000000000000000000000000000000000: n4261_o = 1'b0; + 63'b000100000000000000000000000000000000000000000000000000000000000: n4261_o = 1'b0; + 63'b000010000000000000000000000000000000000000000000000000000000000: n4261_o = 1'b0; + 63'b000001000000000000000000000000000000000000000000000000000000000: n4261_o = 1'b0; + 63'b000000100000000000000000000000000000000000000000000000000000000: n4261_o = 1'b0; + 63'b000000010000000000000000000000000000000000000000000000000000000: n4261_o = 1'b0; + 63'b000000001000000000000000000000000000000000000000000000000000000: n4261_o = 1'b0; + 63'b000000000100000000000000000000000000000000000000000000000000000: n4261_o = 1'b0; + 63'b000000000010000000000000000000000000000000000000000000000000000: n4261_o = 1'b0; + 63'b000000000001000000000000000000000000000000000000000000000000000: n4261_o = 1'b0; + 63'b000000000000100000000000000000000000000000000000000000000000000: n4261_o = 1'b0; + 63'b000000000000010000000000000000000000000000000000000000000000000: n4261_o = 1'b0; + 63'b000000000000001000000000000000000000000000000000000000000000000: n4261_o = 1'b0; + 63'b000000000000000100000000000000000000000000000000000000000000000: n4261_o = 1'b0; + 63'b000000000000000010000000000000000000000000000000000000000000000: n4261_o = 1'b0; + 63'b000000000000000001000000000000000000000000000000000000000000000: n4261_o = 1'b0; + 63'b000000000000000000100000000000000000000000000000000000000000000: n4261_o = 1'b0; + 63'b000000000000000000010000000000000000000000000000000000000000000: n4261_o = 1'b0; + 63'b000000000000000000001000000000000000000000000000000000000000000: n4261_o = 1'b0; + 63'b000000000000000000000100000000000000000000000000000000000000000: n4261_o = 1'b0; + 63'b000000000000000000000010000000000000000000000000000000000000000: n4261_o = 1'b0; + 63'b000000000000000000000001000000000000000000000000000000000000000: n4261_o = 1'b0; + 63'b000000000000000000000000100000000000000000000000000000000000000: n4261_o = 1'b0; + 63'b000000000000000000000000010000000000000000000000000000000000000: n4261_o = 1'b0; + 63'b000000000000000000000000001000000000000000000000000000000000000: n4261_o = 1'b0; + 63'b000000000000000000000000000100000000000000000000000000000000000: n4261_o = 1'b0; + 63'b000000000000000000000000000010000000000000000000000000000000000: n4261_o = 1'b0; + 63'b000000000000000000000000000001000000000000000000000000000000000: n4261_o = n3175_o; + 63'b000000000000000000000000000000100000000000000000000000000000000: n4261_o = n3139_o; + 63'b000000000000000000000000000000010000000000000000000000000000000: n4261_o = n3108_o; + 63'b000000000000000000000000000000001000000000000000000000000000000: n4261_o = n3074_o; + 63'b000000000000000000000000000000000100000000000000000000000000000: n4261_o = n3048_o; + 63'b000000000000000000000000000000000010000000000000000000000000000: n4261_o = n3022_o; + 63'b000000000000000000000000000000000001000000000000000000000000000: n4261_o = 1'b0; + 63'b000000000000000000000000000000000000100000000000000000000000000: n4261_o = 1'b0; + 63'b000000000000000000000000000000000000010000000000000000000000000: n4261_o = n2936_o; + 63'b000000000000000000000000000000000000001000000000000000000000000: n4261_o = n2902_o; + 63'b000000000000000000000000000000000000000100000000000000000000000: n4261_o = n2873_o; + 63'b000000000000000000000000000000000000000010000000000000000000000: n4261_o = 1'b0; + 63'b000000000000000000000000000000000000000001000000000000000000000: n4261_o = 1'b0; + 63'b000000000000000000000000000000000000000000100000000000000000000: n4261_o = 1'b0; + 63'b000000000000000000000000000000000000000000010000000000000000000: n4261_o = 1'b0; + 63'b000000000000000000000000000000000000000000001000000000000000000: n4261_o = 1'b0; + 63'b000000000000000000000000000000000000000000000100000000000000000: n4261_o = 1'b0; + 63'b000000000000000000000000000000000000000000000010000000000000000: n4261_o = n2711_o; + 63'b000000000000000000000000000000000000000000000001000000000000000: n4261_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000100000000000000: n4261_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000010000000000000: n4261_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000001000000000000: n4261_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000100000000000: n4261_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000010000000000: n4261_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000001000000000: n4261_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000100000000: n4261_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000010000000: n4261_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000001000000: n4261_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000100000: n4261_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000010000: n4261_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000001000: n4261_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000000100: n4261_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000000010: n4261_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000000001: n4261_o = 1'b0; + default: n4261_o = 1'b0; + endcase + /* decoder.vhd:635:5 */ + always @* + case (n4151_o) + 63'b100000000000000000000000000000000000000000000000000000000000000: n4271_o = 4'b0000; + 63'b010000000000000000000000000000000000000000000000000000000000000: n4271_o = 4'b0000; + 63'b001000000000000000000000000000000000000000000000000000000000000: n4271_o = 4'b0000; + 63'b000100000000000000000000000000000000000000000000000000000000000: n4271_o = 4'b0000; + 63'b000010000000000000000000000000000000000000000000000000000000000: n4271_o = 4'b0000; + 63'b000001000000000000000000000000000000000000000000000000000000000: n4271_o = 4'b0000; + 63'b000000100000000000000000000000000000000000000000000000000000000: n4271_o = 4'b0000; + 63'b000000010000000000000000000000000000000000000000000000000000000: n4271_o = 4'b0000; + 63'b000000001000000000000000000000000000000000000000000000000000000: n4271_o = 4'b0000; + 63'b000000000100000000000000000000000000000000000000000000000000000: n4271_o = 4'b0000; + 63'b000000000010000000000000000000000000000000000000000000000000000: n4271_o = 4'b0000; + 63'b000000000001000000000000000000000000000000000000000000000000000: n4271_o = 4'b0000; + 63'b000000000000100000000000000000000000000000000000000000000000000: n4271_o = 4'b0000; + 63'b000000000000010000000000000000000000000000000000000000000000000: n4271_o = 4'b0000; + 63'b000000000000001000000000000000000000000000000000000000000000000: n4271_o = 4'b0000; + 63'b000000000000000100000000000000000000000000000000000000000000000: n4271_o = 4'b0000; + 63'b000000000000000010000000000000000000000000000000000000000000000: n4271_o = 4'b0000; + 63'b000000000000000001000000000000000000000000000000000000000000000: n4271_o = 4'b0000; + 63'b000000000000000000100000000000000000000000000000000000000000000: n4271_o = 4'b0000; + 63'b000000000000000000010000000000000000000000000000000000000000000: n4271_o = 4'b0000; + 63'b000000000000000000001000000000000000000000000000000000000000000: n4271_o = 4'b0000; + 63'b000000000000000000000100000000000000000000000000000000000000000: n4271_o = 4'b0000; + 63'b000000000000000000000010000000000000000000000000000000000000000: n4271_o = 4'b0000; + 63'b000000000000000000000001000000000000000000000000000000000000000: n4271_o = 4'b0000; + 63'b000000000000000000000000100000000000000000000000000000000000000: n4271_o = 4'b0000; + 63'b000000000000000000000000010000000000000000000000000000000000000: n4271_o = 4'b0000; + 63'b000000000000000000000000001000000000000000000000000000000000000: n4271_o = 4'b0000; + 63'b000000000000000000000000000100000000000000000000000000000000000: n4271_o = 4'b0000; + 63'b000000000000000000000000000010000000000000000000000000000000000: n4271_o = 4'b0000; + 63'b000000000000000000000000000001000000000000000000000000000000000: n4271_o = 4'b0001; + 63'b000000000000000000000000000000100000000000000000000000000000000: n4271_o = 4'b1000; + 63'b000000000000000000000000000000010000000000000000000000000000000: n4271_o = n3083_o; + 63'b000000000000000000000000000000001000000000000000000000000000000: n4271_o = 4'b1010; + 63'b000000000000000000000000000000000100000000000000000000000000000: n4271_o = 4'b1001; + 63'b000000000000000000000000000000000010000000000000000000000000000: n4271_o = 4'b0101; + 63'b000000000000000000000000000000000001000000000000000000000000000: n4271_o = 4'b0000; + 63'b000000000000000000000000000000000000100000000000000000000000000: n4271_o = 4'b0000; + 63'b000000000000000000000000000000000000010000000000000000000000000: n4271_o = n2938_o; + 63'b000000000000000000000000000000000000001000000000000000000000000: n4271_o = 4'b0010; + 63'b000000000000000000000000000000000000000100000000000000000000000: n4271_o = 4'b0000; + 63'b000000000000000000000000000000000000000010000000000000000000000: n4271_o = 4'b0000; + 63'b000000000000000000000000000000000000000001000000000000000000000: n4271_o = 4'b0000; + 63'b000000000000000000000000000000000000000000100000000000000000000: n4271_o = 4'b0000; + 63'b000000000000000000000000000000000000000000010000000000000000000: n4271_o = 4'b0000; + 63'b000000000000000000000000000000000000000000001000000000000000000: n4271_o = 4'b0000; + 63'b000000000000000000000000000000000000000000000100000000000000000: n4271_o = 4'b0000; + 63'b000000000000000000000000000000000000000000000010000000000000000: n4271_o = n2713_o; + 63'b000000000000000000000000000000000000000000000001000000000000000: n4271_o = 4'b0000; + 63'b000000000000000000000000000000000000000000000000100000000000000: n4271_o = 4'b0000; + 63'b000000000000000000000000000000000000000000000000010000000000000: n4271_o = 4'b0000; + 63'b000000000000000000000000000000000000000000000000001000000000000: n4271_o = 4'b0000; + 63'b000000000000000000000000000000000000000000000000000100000000000: n4271_o = 4'b0000; + 63'b000000000000000000000000000000000000000000000000000010000000000: n4271_o = 4'b0000; + 63'b000000000000000000000000000000000000000000000000000001000000000: n4271_o = 4'b0000; + 63'b000000000000000000000000000000000000000000000000000000100000000: n4271_o = 4'b0000; + 63'b000000000000000000000000000000000000000000000000000000010000000: n4271_o = 4'b0000; + 63'b000000000000000000000000000000000000000000000000000000001000000: n4271_o = 4'b0000; + 63'b000000000000000000000000000000000000000000000000000000000100000: n4271_o = 4'b0000; + 63'b000000000000000000000000000000000000000000000000000000000010000: n4271_o = 4'b0000; + 63'b000000000000000000000000000000000000000000000000000000000001000: n4271_o = 4'b0000; + 63'b000000000000000000000000000000000000000000000000000000000000100: n4271_o = 4'b0000; + 63'b000000000000000000000000000000000000000000000000000000000000010: n4271_o = 4'b0000; + 63'b000000000000000000000000000000000000000000000000000000000000001: n4271_o = 4'b0000; + default: n4271_o = 4'b0000; + endcase + assign n4273_o = opc_opcode_q[5]; + /* decoder.vhd:635:5 */ + always @* + case (n4151_o) + 63'b100000000000000000000000000000000000000000000000000000000000000: n4274_o = n4273_o; + 63'b010000000000000000000000000000000000000000000000000000000000000: n4274_o = n4273_o; + 63'b001000000000000000000000000000000000000000000000000000000000000: n4274_o = n4273_o; + 63'b000100000000000000000000000000000000000000000000000000000000000: n4274_o = n4273_o; + 63'b000010000000000000000000000000000000000000000000000000000000000: n4274_o = n4273_o; + 63'b000001000000000000000000000000000000000000000000000000000000000: n4274_o = n4273_o; + 63'b000000100000000000000000000000000000000000000000000000000000000: n4274_o = n4273_o; + 63'b000000010000000000000000000000000000000000000000000000000000000: n4274_o = n4273_o; + 63'b000000001000000000000000000000000000000000000000000000000000000: n4274_o = n4273_o; + 63'b000000000100000000000000000000000000000000000000000000000000000: n4274_o = n4273_o; + 63'b000000000010000000000000000000000000000000000000000000000000000: n4274_o = n4273_o; + 63'b000000000001000000000000000000000000000000000000000000000000000: n4274_o = n4273_o; + 63'b000000000000100000000000000000000000000000000000000000000000000: n4274_o = n4273_o; + 63'b000000000000010000000000000000000000000000000000000000000000000: n4274_o = n4273_o; + 63'b000000000000001000000000000000000000000000000000000000000000000: n4274_o = n4273_o; + 63'b000000000000000100000000000000000000000000000000000000000000000: n4274_o = n4273_o; + 63'b000000000000000010000000000000000000000000000000000000000000000: n4274_o = n4273_o; + 63'b000000000000000001000000000000000000000000000000000000000000000: n4274_o = n4273_o; + 63'b000000000000000000100000000000000000000000000000000000000000000: n4274_o = n4273_o; + 63'b000000000000000000010000000000000000000000000000000000000000000: n4274_o = n4273_o; + 63'b000000000000000000001000000000000000000000000000000000000000000: n4274_o = n4273_o; + 63'b000000000000000000000100000000000000000000000000000000000000000: n4274_o = n4273_o; + 63'b000000000000000000000010000000000000000000000000000000000000000: n4274_o = n4273_o; + 63'b000000000000000000000001000000000000000000000000000000000000000: n4274_o = n4273_o; + 63'b000000000000000000000000100000000000000000000000000000000000000: n4274_o = n4273_o; + 63'b000000000000000000000000010000000000000000000000000000000000000: n4274_o = n4273_o; + 63'b000000000000000000000000001000000000000000000000000000000000000: n4274_o = n4273_o; + 63'b000000000000000000000000000100000000000000000000000000000000000: n4274_o = n4273_o; + 63'b000000000000000000000000000010000000000000000000000000000000000: n4274_o = n4273_o; + 63'b000000000000000000000000000001000000000000000000000000000000000: n4274_o = n3157_o; + 63'b000000000000000000000000000000100000000000000000000000000000000: n4274_o = n4273_o; + 63'b000000000000000000000000000000010000000000000000000000000000000: n4274_o = n3092_o; + 63'b000000000000000000000000000000001000000000000000000000000000000: n4274_o = n4273_o; + 63'b000000000000000000000000000000000100000000000000000000000000000: n4274_o = n4273_o; + 63'b000000000000000000000000000000000010000000000000000000000000000: n4274_o = n4273_o; + 63'b000000000000000000000000000000000001000000000000000000000000000: n4274_o = n4273_o; + 63'b000000000000000000000000000000000000100000000000000000000000000: n4274_o = n4273_o; + 63'b000000000000000000000000000000000000010000000000000000000000000: n4274_o = n4273_o; + 63'b000000000000000000000000000000000000001000000000000000000000000: n4274_o = n2886_o; + 63'b000000000000000000000000000000000000000100000000000000000000000: n4274_o = n4273_o; + 63'b000000000000000000000000000000000000000010000000000000000000000: n4274_o = n4273_o; + 63'b000000000000000000000000000000000000000001000000000000000000000: n4274_o = n4273_o; + 63'b000000000000000000000000000000000000000000100000000000000000000: n4274_o = n4273_o; + 63'b000000000000000000000000000000000000000000010000000000000000000: n4274_o = n4273_o; + 63'b000000000000000000000000000000000000000000001000000000000000000: n4274_o = n4273_o; + 63'b000000000000000000000000000000000000000000000100000000000000000: n4274_o = n4273_o; + 63'b000000000000000000000000000000000000000000000010000000000000000: n4274_o = n2715_o; + 63'b000000000000000000000000000000000000000000000001000000000000000: n4274_o = n4273_o; + 63'b000000000000000000000000000000000000000000000000100000000000000: n4274_o = n4273_o; + 63'b000000000000000000000000000000000000000000000000010000000000000: n4274_o = n4273_o; + 63'b000000000000000000000000000000000000000000000000001000000000000: n4274_o = n4273_o; + 63'b000000000000000000000000000000000000000000000000000100000000000: n4274_o = n4273_o; + 63'b000000000000000000000000000000000000000000000000000010000000000: n4274_o = n4273_o; + 63'b000000000000000000000000000000000000000000000000000001000000000: n4274_o = n4273_o; + 63'b000000000000000000000000000000000000000000000000000000100000000: n4274_o = n4273_o; + 63'b000000000000000000000000000000000000000000000000000000010000000: n4274_o = n4273_o; + 63'b000000000000000000000000000000000000000000000000000000001000000: n4274_o = n4273_o; + 63'b000000000000000000000000000000000000000000000000000000000100000: n4274_o = n4273_o; + 63'b000000000000000000000000000000000000000000000000000000000010000: n4274_o = n4273_o; + 63'b000000000000000000000000000000000000000000000000000000000001000: n4274_o = n4273_o; + 63'b000000000000000000000000000000000000000000000000000000000000100: n4274_o = n4273_o; + 63'b000000000000000000000000000000000000000000000000000000000000010: n4274_o = n4273_o; + 63'b000000000000000000000000000000000000000000000000000000000000001: n4274_o = n4273_o; + default: n4274_o = n4273_o; + endcase + assign n4275_o = opc_opcode_q[7:6]; + /* decoder.vhd:635:5 */ + always @* + case (n4151_o) + 63'b100000000000000000000000000000000000000000000000000000000000000: n4277_o = 2'b01; + 63'b010000000000000000000000000000000000000000000000000000000000000: n4277_o = n4118_o; + 63'b001000000000000000000000000000000000000000000000000000000000000: n4277_o = n4065_o; + 63'b000100000000000000000000000000000000000000000000000000000000000: n4277_o = 2'b01; + 63'b000010000000000000000000000000000000000000000000000000000000000: n4277_o = 2'b01; + 63'b000001000000000000000000000000000000000000000000000000000000000: n4277_o = 2'b01; + 63'b000000100000000000000000000000000000000000000000000000000000000: n4277_o = 2'b01; + 63'b000000010000000000000000000000000000000000000000000000000000000: n4277_o = 2'b01; + 63'b000000001000000000000000000000000000000000000000000000000000000: n4277_o = 2'b01; + 63'b000000000100000000000000000000000000000000000000000000000000000: n4277_o = 2'b01; + 63'b000000000010000000000000000000000000000000000000000000000000000: n4277_o = n3892_o; + 63'b000000000001000000000000000000000000000000000000000000000000000: n4277_o = 2'b01; + 63'b000000000000100000000000000000000000000000000000000000000000000: n4277_o = 2'b01; + 63'b000000000000010000000000000000000000000000000000000000000000000: n4277_o = 2'b01; + 63'b000000000000001000000000000000000000000000000000000000000000000: n4277_o = 2'b01; + 63'b000000000000000100000000000000000000000000000000000000000000000: n4277_o = n3638_o; + 63'b000000000000000010000000000000000000000000000000000000000000000: n4277_o = 2'b01; + 63'b000000000000000001000000000000000000000000000000000000000000000: n4277_o = 2'b01; + 63'b000000000000000000100000000000000000000000000000000000000000000: n4277_o = 2'b01; + 63'b000000000000000000010000000000000000000000000000000000000000000: n4277_o = 2'b01; + 63'b000000000000000000001000000000000000000000000000000000000000000: n4277_o = 2'b01; + 63'b000000000000000000000100000000000000000000000000000000000000000: n4277_o = 2'b01; + 63'b000000000000000000000010000000000000000000000000000000000000000: n4277_o = 2'b01; + 63'b000000000000000000000001000000000000000000000000000000000000000: n4277_o = n3315_o; + 63'b000000000000000000000000100000000000000000000000000000000000000: n4277_o = n3284_o; + 63'b000000000000000000000000010000000000000000000000000000000000000: n4277_o = 2'b01; + 63'b000000000000000000000000001000000000000000000000000000000000000: n4277_o = 2'b01; + 63'b000000000000000000000000000100000000000000000000000000000000000: n4277_o = n3226_o; + 63'b000000000000000000000000000010000000000000000000000000000000000: n4277_o = 2'b01; + 63'b000000000000000000000000000001000000000000000000000000000000000: n4277_o = 2'b01; + 63'b000000000000000000000000000000100000000000000000000000000000000: n4277_o = 2'b01; + 63'b000000000000000000000000000000010000000000000000000000000000000: n4277_o = 2'b01; + 63'b000000000000000000000000000000001000000000000000000000000000000: n4277_o = 2'b01; + 63'b000000000000000000000000000000000100000000000000000000000000000: n4277_o = 2'b01; + 63'b000000000000000000000000000000000010000000000000000000000000000: n4277_o = 2'b01; + 63'b000000000000000000000000000000000001000000000000000000000000000: n4277_o = 2'b01; + 63'b000000000000000000000000000000000000100000000000000000000000000: n4277_o = 2'b01; + 63'b000000000000000000000000000000000000010000000000000000000000000: n4277_o = 2'b01; + 63'b000000000000000000000000000000000000001000000000000000000000000: n4277_o = 2'b01; + 63'b000000000000000000000000000000000000000100000000000000000000000: n4277_o = 2'b01; + 63'b000000000000000000000000000000000000000010000000000000000000000: n4277_o = n2842_o; + 63'b000000000000000000000000000000000000000001000000000000000000000: n4277_o = 2'b01; + 63'b000000000000000000000000000000000000000000100000000000000000000: n4277_o = 2'b01; + 63'b000000000000000000000000000000000000000000010000000000000000000: n4277_o = 2'b01; + 63'b000000000000000000000000000000000000000000001000000000000000000: n4277_o = 2'b01; + 63'b000000000000000000000000000000000000000000000100000000000000000: n4277_o = 2'b01; + 63'b000000000000000000000000000000000000000000000010000000000000000: n4277_o = 2'b01; + 63'b000000000000000000000000000000000000000000000001000000000000000: n4277_o = 2'b01; + 63'b000000000000000000000000000000000000000000000000100000000000000: n4277_o = 2'b01; + 63'b000000000000000000000000000000000000000000000000010000000000000: n4277_o = 2'b01; + 63'b000000000000000000000000000000000000000000000000001000000000000: n4277_o = 2'b01; + 63'b000000000000000000000000000000000000000000000000000100000000000: n4277_o = 2'b01; + 63'b000000000000000000000000000000000000000000000000000010000000000: n4277_o = 2'b01; + 63'b000000000000000000000000000000000000000000000000000001000000000: n4277_o = 2'b01; + 63'b000000000000000000000000000000000000000000000000000000100000000: n4277_o = 2'b01; + 63'b000000000000000000000000000000000000000000000000000000010000000: n4277_o = 2'b01; + 63'b000000000000000000000000000000000000000000000000000000001000000: n4277_o = 2'b01; + 63'b000000000000000000000000000000000000000000000000000000000100000: n4277_o = n2451_o; + 63'b000000000000000000000000000000000000000000000000000000000010000: n4277_o = 2'b01; + 63'b000000000000000000000000000000000000000000000000000000000001000: n4277_o = 2'b01; + 63'b000000000000000000000000000000000000000000000000000000000000100: n4277_o = n2203_o; + 63'b000000000000000000000000000000000000000000000000000000000000010: n4277_o = 2'b01; + 63'b000000000000000000000000000000000000000000000000000000000000001: n4277_o = n2093_o; + default: n4277_o = 2'b01; + endcase + /* decoder.vhd:635:5 */ + always @* + case (n4151_o) + 63'b100000000000000000000000000000000000000000000000000000000000000: n4280_o = 1'b0; + 63'b010000000000000000000000000000000000000000000000000000000000000: n4280_o = 1'b0; + 63'b001000000000000000000000000000000000000000000000000000000000000: n4280_o = 1'b0; + 63'b000100000000000000000000000000000000000000000000000000000000000: n4280_o = 1'b0; + 63'b000010000000000000000000000000000000000000000000000000000000000: n4280_o = 1'b0; + 63'b000001000000000000000000000000000000000000000000000000000000000: n4280_o = 1'b0; + 63'b000000100000000000000000000000000000000000000000000000000000000: n4280_o = 1'b0; + 63'b000000010000000000000000000000000000000000000000000000000000000: n4280_o = 1'b0; + 63'b000000001000000000000000000000000000000000000000000000000000000: n4280_o = 1'b0; + 63'b000000000100000000000000000000000000000000000000000000000000000: n4280_o = 1'b0; + 63'b000000000010000000000000000000000000000000000000000000000000000: n4280_o = 1'b0; + 63'b000000000001000000000000000000000000000000000000000000000000000: n4280_o = 1'b0; + 63'b000000000000100000000000000000000000000000000000000000000000000: n4280_o = 1'b0; + 63'b000000000000010000000000000000000000000000000000000000000000000: n4280_o = n3776_o; + 63'b000000000000001000000000000000000000000000000000000000000000000: n4280_o = 1'b0; + 63'b000000000000000100000000000000000000000000000000000000000000000: n4280_o = 1'b0; + 63'b000000000000000010000000000000000000000000000000000000000000000: n4280_o = 1'b0; + 63'b000000000000000001000000000000000000000000000000000000000000000: n4280_o = 1'b0; + 63'b000000000000000000100000000000000000000000000000000000000000000: n4280_o = 1'b0; + 63'b000000000000000000010000000000000000000000000000000000000000000: n4280_o = 1'b0; + 63'b000000000000000000001000000000000000000000000000000000000000000: n4280_o = 1'b0; + 63'b000000000000000000000100000000000000000000000000000000000000000: n4280_o = 1'b0; + 63'b000000000000000000000010000000000000000000000000000000000000000: n4280_o = 1'b0; + 63'b000000000000000000000001000000000000000000000000000000000000000: n4280_o = 1'b0; + 63'b000000000000000000000000100000000000000000000000000000000000000: n4280_o = 1'b0; + 63'b000000000000000000000000010000000000000000000000000000000000000: n4280_o = 1'b0; + 63'b000000000000000000000000001000000000000000000000000000000000000: n4280_o = 1'b0; + 63'b000000000000000000000000000100000000000000000000000000000000000: n4280_o = 1'b0; + 63'b000000000000000000000000000010000000000000000000000000000000000: n4280_o = 1'b0; + 63'b000000000000000000000000000001000000000000000000000000000000000: n4280_o = 1'b0; + 63'b000000000000000000000000000000100000000000000000000000000000000: n4280_o = 1'b0; + 63'b000000000000000000000000000000010000000000000000000000000000000: n4280_o = 1'b0; + 63'b000000000000000000000000000000001000000000000000000000000000000: n4280_o = 1'b0; + 63'b000000000000000000000000000000000100000000000000000000000000000: n4280_o = 1'b0; + 63'b000000000000000000000000000000000010000000000000000000000000000: n4280_o = 1'b0; + 63'b000000000000000000000000000000000001000000000000000000000000000: n4280_o = 1'b0; + 63'b000000000000000000000000000000000000100000000000000000000000000: n4280_o = 1'b0; + 63'b000000000000000000000000000000000000010000000000000000000000000: n4280_o = 1'b0; + 63'b000000000000000000000000000000000000001000000000000000000000000: n4280_o = 1'b0; + 63'b000000000000000000000000000000000000000100000000000000000000000: n4280_o = 1'b0; + 63'b000000000000000000000000000000000000000010000000000000000000000: n4280_o = 1'b0; + 63'b000000000000000000000000000000000000000001000000000000000000000: n4280_o = 1'b0; + 63'b000000000000000000000000000000000000000000100000000000000000000: n4280_o = 1'b0; + 63'b000000000000000000000000000000000000000000010000000000000000000: n4280_o = 1'b0; + 63'b000000000000000000000000000000000000000000001000000000000000000: n4280_o = 1'b0; + 63'b000000000000000000000000000000000000000000000100000000000000000: n4280_o = 1'b0; + 63'b000000000000000000000000000000000000000000000010000000000000000: n4280_o = 1'b0; + 63'b000000000000000000000000000000000000000000000001000000000000000: n4280_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000100000000000000: n4280_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000010000000000000: n4280_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000001000000000000: n4280_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000100000000000: n4280_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000010000000000: n4280_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000001000000000: n4280_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000100000000: n4280_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000010000000: n4280_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000001000000: n4280_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000100000: n4280_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000010000: n4280_o = n2341_o; + 63'b000000000000000000000000000000000000000000000000000000000001000: n4280_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000000100: n4280_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000000010: n4280_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000000001: n4280_o = 1'b0; + default: n4280_o = 1'b0; + endcase + /* decoder.vhd:635:5 */ + always @* + case (n4151_o) + 63'b100000000000000000000000000000000000000000000000000000000000000: n4283_o = 1'b0; + 63'b010000000000000000000000000000000000000000000000000000000000000: n4283_o = 1'b0; + 63'b001000000000000000000000000000000000000000000000000000000000000: n4283_o = 1'b0; + 63'b000100000000000000000000000000000000000000000000000000000000000: n4283_o = 1'b0; + 63'b000010000000000000000000000000000000000000000000000000000000000: n4283_o = 1'b0; + 63'b000001000000000000000000000000000000000000000000000000000000000: n4283_o = 1'b0; + 63'b000000100000000000000000000000000000000000000000000000000000000: n4283_o = 1'b0; + 63'b000000010000000000000000000000000000000000000000000000000000000: n4283_o = 1'b0; + 63'b000000001000000000000000000000000000000000000000000000000000000: n4283_o = 1'b0; + 63'b000000000100000000000000000000000000000000000000000000000000000: n4283_o = 1'b0; + 63'b000000000010000000000000000000000000000000000000000000000000000: n4283_o = 1'b0; + 63'b000000000001000000000000000000000000000000000000000000000000000: n4283_o = 1'b0; + 63'b000000000000100000000000000000000000000000000000000000000000000: n4283_o = 1'b0; + 63'b000000000000010000000000000000000000000000000000000000000000000: n4283_o = n3778_o; + 63'b000000000000001000000000000000000000000000000000000000000000000: n4283_o = 1'b0; + 63'b000000000000000100000000000000000000000000000000000000000000000: n4283_o = 1'b0; + 63'b000000000000000010000000000000000000000000000000000000000000000: n4283_o = 1'b0; + 63'b000000000000000001000000000000000000000000000000000000000000000: n4283_o = 1'b0; + 63'b000000000000000000100000000000000000000000000000000000000000000: n4283_o = 1'b0; + 63'b000000000000000000010000000000000000000000000000000000000000000: n4283_o = 1'b0; + 63'b000000000000000000001000000000000000000000000000000000000000000: n4283_o = 1'b0; + 63'b000000000000000000000100000000000000000000000000000000000000000: n4283_o = 1'b0; + 63'b000000000000000000000010000000000000000000000000000000000000000: n4283_o = 1'b0; + 63'b000000000000000000000001000000000000000000000000000000000000000: n4283_o = 1'b0; + 63'b000000000000000000000000100000000000000000000000000000000000000: n4283_o = 1'b0; + 63'b000000000000000000000000010000000000000000000000000000000000000: n4283_o = 1'b0; + 63'b000000000000000000000000001000000000000000000000000000000000000: n4283_o = 1'b0; + 63'b000000000000000000000000000100000000000000000000000000000000000: n4283_o = 1'b0; + 63'b000000000000000000000000000010000000000000000000000000000000000: n4283_o = 1'b0; + 63'b000000000000000000000000000001000000000000000000000000000000000: n4283_o = 1'b0; + 63'b000000000000000000000000000000100000000000000000000000000000000: n4283_o = 1'b0; + 63'b000000000000000000000000000000010000000000000000000000000000000: n4283_o = 1'b0; + 63'b000000000000000000000000000000001000000000000000000000000000000: n4283_o = 1'b0; + 63'b000000000000000000000000000000000100000000000000000000000000000: n4283_o = 1'b0; + 63'b000000000000000000000000000000000010000000000000000000000000000: n4283_o = 1'b0; + 63'b000000000000000000000000000000000001000000000000000000000000000: n4283_o = 1'b0; + 63'b000000000000000000000000000000000000100000000000000000000000000: n4283_o = 1'b0; + 63'b000000000000000000000000000000000000010000000000000000000000000: n4283_o = 1'b0; + 63'b000000000000000000000000000000000000001000000000000000000000000: n4283_o = 1'b0; + 63'b000000000000000000000000000000000000000100000000000000000000000: n4283_o = 1'b0; + 63'b000000000000000000000000000000000000000010000000000000000000000: n4283_o = 1'b0; + 63'b000000000000000000000000000000000000000001000000000000000000000: n4283_o = 1'b0; + 63'b000000000000000000000000000000000000000000100000000000000000000: n4283_o = 1'b0; + 63'b000000000000000000000000000000000000000000010000000000000000000: n4283_o = 1'b0; + 63'b000000000000000000000000000000000000000000001000000000000000000: n4283_o = 1'b0; + 63'b000000000000000000000000000000000000000000000100000000000000000: n4283_o = 1'b0; + 63'b000000000000000000000000000000000000000000000010000000000000000: n4283_o = 1'b0; + 63'b000000000000000000000000000000000000000000000001000000000000000: n4283_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000100000000000000: n4283_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000010000000000000: n4283_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000001000000000000: n4283_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000100000000000: n4283_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000010000000000: n4283_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000001000000000: n4283_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000100000000: n4283_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000010000000: n4283_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000001000000: n4283_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000100000: n4283_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000010000: n4283_o = n2343_o; + 63'b000000000000000000000000000000000000000000000000000000000001000: n4283_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000000100: n4283_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000000010: n4283_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000000001: n4283_o = 1'b0; + default: n4283_o = 1'b0; + endcase + /* decoder.vhd:635:5 */ + always @* + case (n4151_o) + 63'b100000000000000000000000000000000000000000000000000000000000000: n4286_o = 2'b00; + 63'b010000000000000000000000000000000000000000000000000000000000000: n4286_o = 2'b00; + 63'b001000000000000000000000000000000000000000000000000000000000000: n4286_o = 2'b00; + 63'b000100000000000000000000000000000000000000000000000000000000000: n4286_o = 2'b00; + 63'b000010000000000000000000000000000000000000000000000000000000000: n4286_o = 2'b00; + 63'b000001000000000000000000000000000000000000000000000000000000000: n4286_o = 2'b00; + 63'b000000100000000000000000000000000000000000000000000000000000000: n4286_o = 2'b00; + 63'b000000010000000000000000000000000000000000000000000000000000000: n4286_o = 2'b00; + 63'b000000001000000000000000000000000000000000000000000000000000000: n4286_o = 2'b00; + 63'b000000000100000000000000000000000000000000000000000000000000000: n4286_o = 2'b00; + 63'b000000000010000000000000000000000000000000000000000000000000000: n4286_o = 2'b00; + 63'b000000000001000000000000000000000000000000000000000000000000000: n4286_o = 2'b00; + 63'b000000000000100000000000000000000000000000000000000000000000000: n4286_o = 2'b00; + 63'b000000000000010000000000000000000000000000000000000000000000000: n4286_o = 2'b00; + 63'b000000000000001000000000000000000000000000000000000000000000000: n4286_o = 2'b00; + 63'b000000000000000100000000000000000000000000000000000000000000000: n4286_o = 2'b00; + 63'b000000000000000010000000000000000000000000000000000000000000000: n4286_o = 2'b00; + 63'b000000000000000001000000000000000000000000000000000000000000000: n4286_o = 2'b00; + 63'b000000000000000000100000000000000000000000000000000000000000000: n4286_o = n3518_o; + 63'b000000000000000000010000000000000000000000000000000000000000000: n4286_o = 2'b00; + 63'b000000000000000000001000000000000000000000000000000000000000000: n4286_o = 2'b00; + 63'b000000000000000000000100000000000000000000000000000000000000000: n4286_o = 2'b00; + 63'b000000000000000000000010000000000000000000000000000000000000000: n4286_o = 2'b00; + 63'b000000000000000000000001000000000000000000000000000000000000000: n4286_o = 2'b00; + 63'b000000000000000000000000100000000000000000000000000000000000000: n4286_o = 2'b00; + 63'b000000000000000000000000010000000000000000000000000000000000000: n4286_o = 2'b00; + 63'b000000000000000000000000001000000000000000000000000000000000000: n4286_o = 2'b00; + 63'b000000000000000000000000000100000000000000000000000000000000000: n4286_o = 2'b00; + 63'b000000000000000000000000000010000000000000000000000000000000000: n4286_o = 2'b00; + 63'b000000000000000000000000000001000000000000000000000000000000000: n4286_o = 2'b00; + 63'b000000000000000000000000000000100000000000000000000000000000000: n4286_o = 2'b00; + 63'b000000000000000000000000000000010000000000000000000000000000000: n4286_o = 2'b00; + 63'b000000000000000000000000000000001000000000000000000000000000000: n4286_o = 2'b00; + 63'b000000000000000000000000000000000100000000000000000000000000000: n4286_o = 2'b00; + 63'b000000000000000000000000000000000010000000000000000000000000000: n4286_o = 2'b00; + 63'b000000000000000000000000000000000001000000000000000000000000000: n4286_o = n2996_o; + 63'b000000000000000000000000000000000000100000000000000000000000000: n4286_o = 2'b00; + 63'b000000000000000000000000000000000000010000000000000000000000000: n4286_o = 2'b00; + 63'b000000000000000000000000000000000000001000000000000000000000000: n4286_o = 2'b00; + 63'b000000000000000000000000000000000000000100000000000000000000000: n4286_o = 2'b00; + 63'b000000000000000000000000000000000000000010000000000000000000000: n4286_o = 2'b00; + 63'b000000000000000000000000000000000000000001000000000000000000000: n4286_o = 2'b00; + 63'b000000000000000000000000000000000000000000100000000000000000000: n4286_o = 2'b00; + 63'b000000000000000000000000000000000000000000010000000000000000000: n4286_o = 2'b00; + 63'b000000000000000000000000000000000000000000001000000000000000000: n4286_o = 2'b00; + 63'b000000000000000000000000000000000000000000000100000000000000000: n4286_o = 2'b00; + 63'b000000000000000000000000000000000000000000000010000000000000000: n4286_o = 2'b00; + 63'b000000000000000000000000000000000000000000000001000000000000000: n4286_o = 2'b00; + 63'b000000000000000000000000000000000000000000000000100000000000000: n4286_o = 2'b00; + 63'b000000000000000000000000000000000000000000000000010000000000000: n4286_o = 2'b00; + 63'b000000000000000000000000000000000000000000000000001000000000000: n4286_o = 2'b00; + 63'b000000000000000000000000000000000000000000000000000100000000000: n4286_o = 2'b00; + 63'b000000000000000000000000000000000000000000000000000010000000000: n4286_o = 2'b00; + 63'b000000000000000000000000000000000000000000000000000001000000000: n4286_o = 2'b00; + 63'b000000000000000000000000000000000000000000000000000000100000000: n4286_o = 2'b00; + 63'b000000000000000000000000000000000000000000000000000000010000000: n4286_o = 2'b00; + 63'b000000000000000000000000000000000000000000000000000000001000000: n4286_o = 2'b00; + 63'b000000000000000000000000000000000000000000000000000000000100000: n4286_o = 2'b00; + 63'b000000000000000000000000000000000000000000000000000000000010000: n4286_o = 2'b00; + 63'b000000000000000000000000000000000000000000000000000000000001000: n4286_o = 2'b00; + 63'b000000000000000000000000000000000000000000000000000000000000100: n4286_o = 2'b00; + 63'b000000000000000000000000000000000000000000000000000000000000010: n4286_o = 2'b00; + 63'b000000000000000000000000000000000000000000000000000000000000001: n4286_o = 2'b00; + default: n4286_o = 2'b00; + endcase + /* decoder.vhd:635:5 */ + always @* + case (n4151_o) + 63'b100000000000000000000000000000000000000000000000000000000000000: n4289_o = 1'b0; + 63'b010000000000000000000000000000000000000000000000000000000000000: n4289_o = 1'b0; + 63'b001000000000000000000000000000000000000000000000000000000000000: n4289_o = 1'b0; + 63'b000100000000000000000000000000000000000000000000000000000000000: n4289_o = 1'b0; + 63'b000010000000000000000000000000000000000000000000000000000000000: n4289_o = 1'b0; + 63'b000001000000000000000000000000000000000000000000000000000000000: n4289_o = 1'b0; + 63'b000000100000000000000000000000000000000000000000000000000000000: n4289_o = n3977_o; + 63'b000000010000000000000000000000000000000000000000000000000000000: n4289_o = 1'b0; + 63'b000000001000000000000000000000000000000000000000000000000000000: n4289_o = n3953_o; + 63'b000000000100000000000000000000000000000000000000000000000000000: n4289_o = n3924_o; + 63'b000000000010000000000000000000000000000000000000000000000000000: n4289_o = 1'b0; + 63'b000000000001000000000000000000000000000000000000000000000000000: n4289_o = 1'b0; + 63'b000000000000100000000000000000000000000000000000000000000000000: n4289_o = 1'b0; + 63'b000000000000010000000000000000000000000000000000000000000000000: n4289_o = 1'b0; + 63'b000000000000001000000000000000000000000000000000000000000000000: n4289_o = 1'b0; + 63'b000000000000000100000000000000000000000000000000000000000000000: n4289_o = 1'b0; + 63'b000000000000000010000000000000000000000000000000000000000000000: n4289_o = 1'b0; + 63'b000000000000000001000000000000000000000000000000000000000000000: n4289_o = 1'b0; + 63'b000000000000000000100000000000000000000000000000000000000000000: n4289_o = 1'b0; + 63'b000000000000000000010000000000000000000000000000000000000000000: n4289_o = 1'b0; + 63'b000000000000000000001000000000000000000000000000000000000000000: n4289_o = 1'b0; + 63'b000000000000000000000100000000000000000000000000000000000000000: n4289_o = 1'b0; + 63'b000000000000000000000010000000000000000000000000000000000000000: n4289_o = 1'b0; + 63'b000000000000000000000001000000000000000000000000000000000000000: n4289_o = 1'b0; + 63'b000000000000000000000000100000000000000000000000000000000000000: n4289_o = 1'b0; + 63'b000000000000000000000000010000000000000000000000000000000000000: n4289_o = 1'b0; + 63'b000000000000000000000000001000000000000000000000000000000000000: n4289_o = 1'b0; + 63'b000000000000000000000000000100000000000000000000000000000000000: n4289_o = 1'b0; + 63'b000000000000000000000000000010000000000000000000000000000000000: n4289_o = 1'b0; + 63'b000000000000000000000000000001000000000000000000000000000000000: n4289_o = 1'b0; + 63'b000000000000000000000000000000100000000000000000000000000000000: n4289_o = 1'b0; + 63'b000000000000000000000000000000010000000000000000000000000000000: n4289_o = 1'b0; + 63'b000000000000000000000000000000001000000000000000000000000000000: n4289_o = 1'b0; + 63'b000000000000000000000000000000000100000000000000000000000000000: n4289_o = 1'b0; + 63'b000000000000000000000000000000000010000000000000000000000000000: n4289_o = 1'b0; + 63'b000000000000000000000000000000000001000000000000000000000000000: n4289_o = 1'b0; + 63'b000000000000000000000000000000000000100000000000000000000000000: n4289_o = 1'b0; + 63'b000000000000000000000000000000000000010000000000000000000000000: n4289_o = 1'b0; + 63'b000000000000000000000000000000000000001000000000000000000000000: n4289_o = 1'b0; + 63'b000000000000000000000000000000000000000100000000000000000000000: n4289_o = 1'b0; + 63'b000000000000000000000000000000000000000010000000000000000000000: n4289_o = 1'b0; + 63'b000000000000000000000000000000000000000001000000000000000000000: n4289_o = 1'b0; + 63'b000000000000000000000000000000000000000000100000000000000000000: n4289_o = 1'b0; + 63'b000000000000000000000000000000000000000000010000000000000000000: n4289_o = 1'b0; + 63'b000000000000000000000000000000000000000000001000000000000000000: n4289_o = 1'b0; + 63'b000000000000000000000000000000000000000000000100000000000000000: n4289_o = 1'b0; + 63'b000000000000000000000000000000000000000000000010000000000000000: n4289_o = 1'b0; + 63'b000000000000000000000000000000000000000000000001000000000000000: n4289_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000100000000000000: n4289_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000010000000000000: n4289_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000001000000000000: n4289_o = n2586_o; + 63'b000000000000000000000000000000000000000000000000000100000000000: n4289_o = n2539_o; + 63'b000000000000000000000000000000000000000000000000000010000000000: n4289_o = n2519_o; + 63'b000000000000000000000000000000000000000000000000000001000000000: n4289_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000100000000: n4289_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000010000000: n4289_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000001000000: n4289_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000100000: n4289_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000010000: n4289_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000001000: n4289_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000000100: n4289_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000000010: n4289_o = n2149_o; + 63'b000000000000000000000000000000000000000000000000000000000000001: n4289_o = n2095_o; + default: n4289_o = 1'b0; + endcase + /* decoder.vhd:635:5 */ + always @* + case (n4151_o) + 63'b100000000000000000000000000000000000000000000000000000000000000: n4292_o = 1'b0; + 63'b010000000000000000000000000000000000000000000000000000000000000: n4292_o = 1'b0; + 63'b001000000000000000000000000000000000000000000000000000000000000: n4292_o = 1'b0; + 63'b000100000000000000000000000000000000000000000000000000000000000: n4292_o = 1'b0; + 63'b000010000000000000000000000000000000000000000000000000000000000: n4292_o = 1'b0; + 63'b000001000000000000000000000000000000000000000000000000000000000: n4292_o = 1'b0; + 63'b000000100000000000000000000000000000000000000000000000000000000: n4292_o = 1'b0; + 63'b000000010000000000000000000000000000000000000000000000000000000: n4292_o = 1'b0; + 63'b000000001000000000000000000000000000000000000000000000000000000: n4292_o = 1'b0; + 63'b000000000100000000000000000000000000000000000000000000000000000: n4292_o = 1'b0; + 63'b000000000010000000000000000000000000000000000000000000000000000: n4292_o = 1'b0; + 63'b000000000001000000000000000000000000000000000000000000000000000: n4292_o = 1'b0; + 63'b000000000000100000000000000000000000000000000000000000000000000: n4292_o = 1'b0; + 63'b000000000000010000000000000000000000000000000000000000000000000: n4292_o = 1'b0; + 63'b000000000000001000000000000000000000000000000000000000000000000: n4292_o = 1'b0; + 63'b000000000000000100000000000000000000000000000000000000000000000: n4292_o = 1'b0; + 63'b000000000000000010000000000000000000000000000000000000000000000: n4292_o = 1'b0; + 63'b000000000000000001000000000000000000000000000000000000000000000: n4292_o = 1'b0; + 63'b000000000000000000100000000000000000000000000000000000000000000: n4292_o = 1'b0; + 63'b000000000000000000010000000000000000000000000000000000000000000: n4292_o = 1'b0; + 63'b000000000000000000001000000000000000000000000000000000000000000: n4292_o = 1'b0; + 63'b000000000000000000000100000000000000000000000000000000000000000: n4292_o = 1'b0; + 63'b000000000000000000000010000000000000000000000000000000000000000: n4292_o = 1'b0; + 63'b000000000000000000000001000000000000000000000000000000000000000: n4292_o = 1'b0; + 63'b000000000000000000000000100000000000000000000000000000000000000: n4292_o = 1'b0; + 63'b000000000000000000000000010000000000000000000000000000000000000: n4292_o = 1'b0; + 63'b000000000000000000000000001000000000000000000000000000000000000: n4292_o = 1'b0; + 63'b000000000000000000000000000100000000000000000000000000000000000: n4292_o = 1'b0; + 63'b000000000000000000000000000010000000000000000000000000000000000: n4292_o = 1'b0; + 63'b000000000000000000000000000001000000000000000000000000000000000: n4292_o = 1'b0; + 63'b000000000000000000000000000000100000000000000000000000000000000: n4292_o = 1'b0; + 63'b000000000000000000000000000000010000000000000000000000000000000: n4292_o = 1'b0; + 63'b000000000000000000000000000000001000000000000000000000000000000: n4292_o = 1'b0; + 63'b000000000000000000000000000000000100000000000000000000000000000: n4292_o = 1'b0; + 63'b000000000000000000000000000000000010000000000000000000000000000: n4292_o = 1'b0; + 63'b000000000000000000000000000000000001000000000000000000000000000: n4292_o = 1'b0; + 63'b000000000000000000000000000000000000100000000000000000000000000: n4292_o = 1'b0; + 63'b000000000000000000000000000000000000010000000000000000000000000: n4292_o = 1'b0; + 63'b000000000000000000000000000000000000001000000000000000000000000: n4292_o = 1'b0; + 63'b000000000000000000000000000000000000000100000000000000000000000: n4292_o = 1'b0; + 63'b000000000000000000000000000000000000000010000000000000000000000: n4292_o = 1'b0; + 63'b000000000000000000000000000000000000000001000000000000000000000: n4292_o = 1'b0; + 63'b000000000000000000000000000000000000000000100000000000000000000: n4292_o = 1'b0; + 63'b000000000000000000000000000000000000000000010000000000000000000: n4292_o = 1'b0; + 63'b000000000000000000000000000000000000000000001000000000000000000: n4292_o = 1'b0; + 63'b000000000000000000000000000000000000000000000100000000000000000: n4292_o = 1'b0; + 63'b000000000000000000000000000000000000000000000010000000000000000: n4292_o = 1'b0; + 63'b000000000000000000000000000000000000000000000001000000000000000: n4292_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000100000000000000: n4292_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000010000000000000: n4292_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000001000000000000: n4292_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000100000000000: n4292_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000010000000000: n4292_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000001000000000: n4292_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000100000000: n4292_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000010000000: n4292_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000001000000: n4292_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000100000: n4292_o = n2453_o; + 63'b000000000000000000000000000000000000000000000000000000000010000: n4292_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000001000: n4292_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000000100: n4292_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000000010: n4292_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000000001: n4292_o = 1'b0; + default: n4292_o = 1'b0; + endcase + /* decoder.vhd:635:5 */ + always @* + case (n4151_o) + 63'b100000000000000000000000000000000000000000000000000000000000000: n4295_o = 1'b0; + 63'b010000000000000000000000000000000000000000000000000000000000000: n4295_o = 1'b0; + 63'b001000000000000000000000000000000000000000000000000000000000000: n4295_o = 1'b0; + 63'b000100000000000000000000000000000000000000000000000000000000000: n4295_o = 1'b0; + 63'b000010000000000000000000000000000000000000000000000000000000000: n4295_o = 1'b0; + 63'b000001000000000000000000000000000000000000000000000000000000000: n4295_o = 1'b0; + 63'b000000100000000000000000000000000000000000000000000000000000000: n4295_o = 1'b0; + 63'b000000010000000000000000000000000000000000000000000000000000000: n4295_o = 1'b0; + 63'b000000001000000000000000000000000000000000000000000000000000000: n4295_o = 1'b0; + 63'b000000000100000000000000000000000000000000000000000000000000000: n4295_o = 1'b0; + 63'b000000000010000000000000000000000000000000000000000000000000000: n4295_o = n3894_o; + 63'b000000000001000000000000000000000000000000000000000000000000000: n4295_o = 1'b0; + 63'b000000000000100000000000000000000000000000000000000000000000000: n4295_o = 1'b0; + 63'b000000000000010000000000000000000000000000000000000000000000000: n4295_o = 1'b0; + 63'b000000000000001000000000000000000000000000000000000000000000000: n4295_o = 1'b0; + 63'b000000000000000100000000000000000000000000000000000000000000000: n4295_o = 1'b0; + 63'b000000000000000010000000000000000000000000000000000000000000000: n4295_o = 1'b0; + 63'b000000000000000001000000000000000000000000000000000000000000000: n4295_o = 1'b0; + 63'b000000000000000000100000000000000000000000000000000000000000000: n4295_o = 1'b0; + 63'b000000000000000000010000000000000000000000000000000000000000000: n4295_o = 1'b0; + 63'b000000000000000000001000000000000000000000000000000000000000000: n4295_o = 1'b0; + 63'b000000000000000000000100000000000000000000000000000000000000000: n4295_o = 1'b0; + 63'b000000000000000000000010000000000000000000000000000000000000000: n4295_o = 1'b0; + 63'b000000000000000000000001000000000000000000000000000000000000000: n4295_o = 1'b0; + 63'b000000000000000000000000100000000000000000000000000000000000000: n4295_o = 1'b0; + 63'b000000000000000000000000010000000000000000000000000000000000000: n4295_o = 1'b0; + 63'b000000000000000000000000001000000000000000000000000000000000000: n4295_o = 1'b0; + 63'b000000000000000000000000000100000000000000000000000000000000000: n4295_o = 1'b0; + 63'b000000000000000000000000000010000000000000000000000000000000000: n4295_o = 1'b0; + 63'b000000000000000000000000000001000000000000000000000000000000000: n4295_o = 1'b0; + 63'b000000000000000000000000000000100000000000000000000000000000000: n4295_o = 1'b0; + 63'b000000000000000000000000000000010000000000000000000000000000000: n4295_o = 1'b0; + 63'b000000000000000000000000000000001000000000000000000000000000000: n4295_o = 1'b0; + 63'b000000000000000000000000000000000100000000000000000000000000000: n4295_o = 1'b0; + 63'b000000000000000000000000000000000010000000000000000000000000000: n4295_o = 1'b0; + 63'b000000000000000000000000000000000001000000000000000000000000000: n4295_o = 1'b0; + 63'b000000000000000000000000000000000000100000000000000000000000000: n4295_o = 1'b0; + 63'b000000000000000000000000000000000000010000000000000000000000000: n4295_o = 1'b0; + 63'b000000000000000000000000000000000000001000000000000000000000000: n4295_o = 1'b0; + 63'b000000000000000000000000000000000000000100000000000000000000000: n4295_o = 1'b0; + 63'b000000000000000000000000000000000000000010000000000000000000000: n4295_o = 1'b0; + 63'b000000000000000000000000000000000000000001000000000000000000000: n4295_o = 1'b0; + 63'b000000000000000000000000000000000000000000100000000000000000000: n4295_o = 1'b0; + 63'b000000000000000000000000000000000000000000010000000000000000000: n4295_o = 1'b0; + 63'b000000000000000000000000000000000000000000001000000000000000000: n4295_o = 1'b0; + 63'b000000000000000000000000000000000000000000000100000000000000000: n4295_o = 1'b0; + 63'b000000000000000000000000000000000000000000000010000000000000000: n4295_o = 1'b0; + 63'b000000000000000000000000000000000000000000000001000000000000000: n4295_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000100000000000000: n4295_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000010000000000000: n4295_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000001000000000000: n4295_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000100000000000: n4295_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000010000000000: n4295_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000001000000000: n4295_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000100000000: n4295_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000010000000: n4295_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000001000000: n4295_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000100000: n4295_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000010000: n4295_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000001000: n4295_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000000100: n4295_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000000010: n4295_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000000001: n4295_o = 1'b0; + default: n4295_o = 1'b0; + endcase + /* decoder.vhd:635:5 */ + always @* + case (n4151_o) + 63'b100000000000000000000000000000000000000000000000000000000000000: n4298_o = 1'b0; + 63'b010000000000000000000000000000000000000000000000000000000000000: n4298_o = 1'b0; + 63'b001000000000000000000000000000000000000000000000000000000000000: n4298_o = 1'b0; + 63'b000100000000000000000000000000000000000000000000000000000000000: n4298_o = 1'b0; + 63'b000010000000000000000000000000000000000000000000000000000000000: n4298_o = 1'b0; + 63'b000001000000000000000000000000000000000000000000000000000000000: n4298_o = 1'b0; + 63'b000000100000000000000000000000000000000000000000000000000000000: n4298_o = 1'b0; + 63'b000000010000000000000000000000000000000000000000000000000000000: n4298_o = 1'b0; + 63'b000000001000000000000000000000000000000000000000000000000000000: n4298_o = n3955_o; + 63'b000000000100000000000000000000000000000000000000000000000000000: n4298_o = n3926_o; + 63'b000000000010000000000000000000000000000000000000000000000000000: n4298_o = 1'b0; + 63'b000000000001000000000000000000000000000000000000000000000000000: n4298_o = 1'b0; + 63'b000000000000100000000000000000000000000000000000000000000000000: n4298_o = 1'b0; + 63'b000000000000010000000000000000000000000000000000000000000000000: n4298_o = 1'b0; + 63'b000000000000001000000000000000000000000000000000000000000000000: n4298_o = 1'b0; + 63'b000000000000000100000000000000000000000000000000000000000000000: n4298_o = 1'b0; + 63'b000000000000000010000000000000000000000000000000000000000000000: n4298_o = 1'b0; + 63'b000000000000000001000000000000000000000000000000000000000000000: n4298_o = 1'b0; + 63'b000000000000000000100000000000000000000000000000000000000000000: n4298_o = 1'b0; + 63'b000000000000000000010000000000000000000000000000000000000000000: n4298_o = 1'b0; + 63'b000000000000000000001000000000000000000000000000000000000000000: n4298_o = 1'b0; + 63'b000000000000000000000100000000000000000000000000000000000000000: n4298_o = 1'b0; + 63'b000000000000000000000010000000000000000000000000000000000000000: n4298_o = 1'b0; + 63'b000000000000000000000001000000000000000000000000000000000000000: n4298_o = 1'b0; + 63'b000000000000000000000000100000000000000000000000000000000000000: n4298_o = 1'b0; + 63'b000000000000000000000000010000000000000000000000000000000000000: n4298_o = 1'b0; + 63'b000000000000000000000000001000000000000000000000000000000000000: n4298_o = 1'b0; + 63'b000000000000000000000000000100000000000000000000000000000000000: n4298_o = 1'b0; + 63'b000000000000000000000000000010000000000000000000000000000000000: n4298_o = 1'b0; + 63'b000000000000000000000000000001000000000000000000000000000000000: n4298_o = 1'b0; + 63'b000000000000000000000000000000100000000000000000000000000000000: n4298_o = 1'b0; + 63'b000000000000000000000000000000010000000000000000000000000000000: n4298_o = 1'b0; + 63'b000000000000000000000000000000001000000000000000000000000000000: n4298_o = 1'b0; + 63'b000000000000000000000000000000000100000000000000000000000000000: n4298_o = 1'b0; + 63'b000000000000000000000000000000000010000000000000000000000000000: n4298_o = 1'b0; + 63'b000000000000000000000000000000000001000000000000000000000000000: n4298_o = 1'b0; + 63'b000000000000000000000000000000000000100000000000000000000000000: n4298_o = 1'b0; + 63'b000000000000000000000000000000000000010000000000000000000000000: n4298_o = 1'b0; + 63'b000000000000000000000000000000000000001000000000000000000000000: n4298_o = 1'b0; + 63'b000000000000000000000000000000000000000100000000000000000000000: n4298_o = 1'b0; + 63'b000000000000000000000000000000000000000010000000000000000000000: n4298_o = 1'b0; + 63'b000000000000000000000000000000000000000001000000000000000000000: n4298_o = 1'b0; + 63'b000000000000000000000000000000000000000000100000000000000000000: n4298_o = 1'b0; + 63'b000000000000000000000000000000000000000000010000000000000000000: n4298_o = 1'b0; + 63'b000000000000000000000000000000000000000000001000000000000000000: n4298_o = 1'b0; + 63'b000000000000000000000000000000000000000000000100000000000000000: n4298_o = 1'b0; + 63'b000000000000000000000000000000000000000000000010000000000000000: n4298_o = 1'b0; + 63'b000000000000000000000000000000000000000000000001000000000000000: n4298_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000100000000000000: n4298_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000010000000000000: n4298_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000001000000000000: n4298_o = n2589_o; + 63'b000000000000000000000000000000000000000000000000000100000000000: n4298_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000010000000000: n4298_o = n2522_o; + 63'b000000000000000000000000000000000000000000000000000001000000000: n4298_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000100000000: n4298_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000010000000: n4298_o = n2483_o; + 63'b000000000000000000000000000000000000000000000000000000001000000: n4298_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000100000: n4298_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000010000: n4298_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000001000: n4298_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000000100: n4298_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000000010: n4298_o = n2151_o; + 63'b000000000000000000000000000000000000000000000000000000000000001: n4298_o = n2098_o; + default: n4298_o = 1'b0; + endcase + /* decoder.vhd:635:5 */ + always @* + case (n4151_o) + 63'b100000000000000000000000000000000000000000000000000000000000000: n4301_o = 1'b0; + 63'b010000000000000000000000000000000000000000000000000000000000000: n4301_o = 1'b0; + 63'b001000000000000000000000000000000000000000000000000000000000000: n4301_o = 1'b0; + 63'b000100000000000000000000000000000000000000000000000000000000000: n4301_o = 1'b0; + 63'b000010000000000000000000000000000000000000000000000000000000000: n4301_o = 1'b0; + 63'b000001000000000000000000000000000000000000000000000000000000000: n4301_o = 1'b0; + 63'b000000100000000000000000000000000000000000000000000000000000000: n4301_o = 1'b0; + 63'b000000010000000000000000000000000000000000000000000000000000000: n4301_o = 1'b0; + 63'b000000001000000000000000000000000000000000000000000000000000000: n4301_o = 1'b0; + 63'b000000000100000000000000000000000000000000000000000000000000000: n4301_o = 1'b0; + 63'b000000000010000000000000000000000000000000000000000000000000000: n4301_o = 1'b0; + 63'b000000000001000000000000000000000000000000000000000000000000000: n4301_o = 1'b0; + 63'b000000000000100000000000000000000000000000000000000000000000000: n4301_o = 1'b0; + 63'b000000000000010000000000000000000000000000000000000000000000000: n4301_o = 1'b0; + 63'b000000000000001000000000000000000000000000000000000000000000000: n4301_o = 1'b0; + 63'b000000000000000100000000000000000000000000000000000000000000000: n4301_o = 1'b0; + 63'b000000000000000010000000000000000000000000000000000000000000000: n4301_o = 1'b0; + 63'b000000000000000001000000000000000000000000000000000000000000000: n4301_o = 1'b0; + 63'b000000000000000000100000000000000000000000000000000000000000000: n4301_o = 1'b0; + 63'b000000000000000000010000000000000000000000000000000000000000000: n4301_o = 1'b0; + 63'b000000000000000000001000000000000000000000000000000000000000000: n4301_o = 1'b0; + 63'b000000000000000000000100000000000000000000000000000000000000000: n4301_o = 1'b0; + 63'b000000000000000000000010000000000000000000000000000000000000000: n4301_o = 1'b0; + 63'b000000000000000000000001000000000000000000000000000000000000000: n4301_o = 1'b0; + 63'b000000000000000000000000100000000000000000000000000000000000000: n4301_o = 1'b0; + 63'b000000000000000000000000010000000000000000000000000000000000000: n4301_o = 1'b0; + 63'b000000000000000000000000001000000000000000000000000000000000000: n4301_o = 1'b0; + 63'b000000000000000000000000000100000000000000000000000000000000000: n4301_o = 1'b0; + 63'b000000000000000000000000000010000000000000000000000000000000000: n4301_o = 1'b0; + 63'b000000000000000000000000000001000000000000000000000000000000000: n4301_o = 1'b0; + 63'b000000000000000000000000000000100000000000000000000000000000000: n4301_o = 1'b0; + 63'b000000000000000000000000000000010000000000000000000000000000000: n4301_o = 1'b0; + 63'b000000000000000000000000000000001000000000000000000000000000000: n4301_o = 1'b0; + 63'b000000000000000000000000000000000100000000000000000000000000000: n4301_o = 1'b0; + 63'b000000000000000000000000000000000010000000000000000000000000000: n4301_o = 1'b0; + 63'b000000000000000000000000000000000001000000000000000000000000000: n4301_o = 1'b0; + 63'b000000000000000000000000000000000000100000000000000000000000000: n4301_o = 1'b0; + 63'b000000000000000000000000000000000000010000000000000000000000000: n4301_o = 1'b0; + 63'b000000000000000000000000000000000000001000000000000000000000000: n4301_o = 1'b0; + 63'b000000000000000000000000000000000000000100000000000000000000000: n4301_o = 1'b0; + 63'b000000000000000000000000000000000000000010000000000000000000000: n4301_o = 1'b0; + 63'b000000000000000000000000000000000000000001000000000000000000000: n4301_o = 1'b0; + 63'b000000000000000000000000000000000000000000100000000000000000000: n4301_o = 1'b0; + 63'b000000000000000000000000000000000000000000010000000000000000000: n4301_o = 1'b0; + 63'b000000000000000000000000000000000000000000001000000000000000000: n4301_o = 1'b0; + 63'b000000000000000000000000000000000000000000000100000000000000000: n4301_o = 1'b0; + 63'b000000000000000000000000000000000000000000000010000000000000000: n4301_o = 1'b0; + 63'b000000000000000000000000000000000000000000000001000000000000000: n4301_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000100000000000000: n4301_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000010000000000000: n4301_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000001000000000000: n4301_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000100000000000: n4301_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000010000000000: n4301_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000001000000000: n4301_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000100000000: n4301_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000010000000: n4301_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000001000000: n4301_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000100000: n4301_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000010000: n4301_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000001000: n4301_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000000100: n4301_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000000010: n4301_o = n2153_o; + 63'b000000000000000000000000000000000000000000000000000000000000001: n4301_o = n2101_o; + default: n4301_o = 1'b0; + endcase + /* decoder.vhd:635:5 */ + always @* + case (n4151_o) + 63'b100000000000000000000000000000000000000000000000000000000000000: n4304_o = 1'b0; + 63'b010000000000000000000000000000000000000000000000000000000000000: n4304_o = 1'b0; + 63'b001000000000000000000000000000000000000000000000000000000000000: n4304_o = 1'b0; + 63'b000100000000000000000000000000000000000000000000000000000000000: n4304_o = 1'b0; + 63'b000010000000000000000000000000000000000000000000000000000000000: n4304_o = 1'b0; + 63'b000001000000000000000000000000000000000000000000000000000000000: n4304_o = 1'b0; + 63'b000000100000000000000000000000000000000000000000000000000000000: n4304_o = 1'b0; + 63'b000000010000000000000000000000000000000000000000000000000000000: n4304_o = 1'b0; + 63'b000000001000000000000000000000000000000000000000000000000000000: n4304_o = 1'b0; + 63'b000000000100000000000000000000000000000000000000000000000000000: n4304_o = 1'b0; + 63'b000000000010000000000000000000000000000000000000000000000000000: n4304_o = 1'b0; + 63'b000000000001000000000000000000000000000000000000000000000000000: n4304_o = 1'b0; + 63'b000000000000100000000000000000000000000000000000000000000000000: n4304_o = 1'b0; + 63'b000000000000010000000000000000000000000000000000000000000000000: n4304_o = 1'b0; + 63'b000000000000001000000000000000000000000000000000000000000000000: n4304_o = 1'b0; + 63'b000000000000000100000000000000000000000000000000000000000000000: n4304_o = 1'b0; + 63'b000000000000000010000000000000000000000000000000000000000000000: n4304_o = 1'b0; + 63'b000000000000000001000000000000000000000000000000000000000000000: n4304_o = 1'b0; + 63'b000000000000000000100000000000000000000000000000000000000000000: n4304_o = 1'b0; + 63'b000000000000000000010000000000000000000000000000000000000000000: n4304_o = 1'b0; + 63'b000000000000000000001000000000000000000000000000000000000000000: n4304_o = 1'b0; + 63'b000000000000000000000100000000000000000000000000000000000000000: n4304_o = 1'b0; + 63'b000000000000000000000010000000000000000000000000000000000000000: n4304_o = 1'b0; + 63'b000000000000000000000001000000000000000000000000000000000000000: n4304_o = 1'b0; + 63'b000000000000000000000000100000000000000000000000000000000000000: n4304_o = 1'b0; + 63'b000000000000000000000000010000000000000000000000000000000000000: n4304_o = 1'b0; + 63'b000000000000000000000000001000000000000000000000000000000000000: n4304_o = 1'b0; + 63'b000000000000000000000000000100000000000000000000000000000000000: n4304_o = 1'b0; + 63'b000000000000000000000000000010000000000000000000000000000000000: n4304_o = 1'b0; + 63'b000000000000000000000000000001000000000000000000000000000000000: n4304_o = 1'b0; + 63'b000000000000000000000000000000100000000000000000000000000000000: n4304_o = 1'b0; + 63'b000000000000000000000000000000010000000000000000000000000000000: n4304_o = 1'b0; + 63'b000000000000000000000000000000001000000000000000000000000000000: n4304_o = 1'b0; + 63'b000000000000000000000000000000000100000000000000000000000000000: n4304_o = 1'b0; + 63'b000000000000000000000000000000000010000000000000000000000000000: n4304_o = 1'b0; + 63'b000000000000000000000000000000000001000000000000000000000000000: n4304_o = 1'b0; + 63'b000000000000000000000000000000000000100000000000000000000000000: n4304_o = 1'b0; + 63'b000000000000000000000000000000000000010000000000000000000000000: n4304_o = 1'b0; + 63'b000000000000000000000000000000000000001000000000000000000000000: n4304_o = 1'b0; + 63'b000000000000000000000000000000000000000100000000000000000000000: n4304_o = 1'b0; + 63'b000000000000000000000000000000000000000010000000000000000000000: n4304_o = 1'b0; + 63'b000000000000000000000000000000000000000001000000000000000000000: n4304_o = 1'b0; + 63'b000000000000000000000000000000000000000000100000000000000000000: n4304_o = 1'b0; + 63'b000000000000000000000000000000000000000000010000000000000000000: n4304_o = 1'b0; + 63'b000000000000000000000000000000000000000000001000000000000000000: n4304_o = 1'b0; + 63'b000000000000000000000000000000000000000000000100000000000000000: n4304_o = 1'b0; + 63'b000000000000000000000000000000000000000000000010000000000000000: n4304_o = 1'b0; + 63'b000000000000000000000000000000000000000000000001000000000000000: n4304_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000100000000000000: n4304_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000010000000000000: n4304_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000001000000000000: n4304_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000100000000000: n4304_o = n2541_o; + 63'b000000000000000000000000000000000000000000000000000010000000000: n4304_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000001000000000: n4304_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000100000000: n4304_o = n2497_o; + 63'b000000000000000000000000000000000000000000000000000000010000000: n4304_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000001000000: n4304_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000100000: n4304_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000010000: n4304_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000001000: n4304_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000000100: n4304_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000000010: n4304_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000000001: n4304_o = 1'b0; + default: n4304_o = 1'b0; + endcase + /* decoder.vhd:635:5 */ + always @* + case (n4151_o) + 63'b100000000000000000000000000000000000000000000000000000000000000: n4307_o = 1'b0; + 63'b010000000000000000000000000000000000000000000000000000000000000: n4307_o = 1'b0; + 63'b001000000000000000000000000000000000000000000000000000000000000: n4307_o = 1'b0; + 63'b000100000000000000000000000000000000000000000000000000000000000: n4307_o = 1'b0; + 63'b000010000000000000000000000000000000000000000000000000000000000: n4307_o = 1'b0; + 63'b000001000000000000000000000000000000000000000000000000000000000: n4307_o = 1'b0; + 63'b000000100000000000000000000000000000000000000000000000000000000: n4307_o = n3980_o; + 63'b000000010000000000000000000000000000000000000000000000000000000: n4307_o = 1'b0; + 63'b000000001000000000000000000000000000000000000000000000000000000: n4307_o = 1'b0; + 63'b000000000100000000000000000000000000000000000000000000000000000: n4307_o = 1'b0; + 63'b000000000010000000000000000000000000000000000000000000000000000: n4307_o = 1'b0; + 63'b000000000001000000000000000000000000000000000000000000000000000: n4307_o = 1'b0; + 63'b000000000000100000000000000000000000000000000000000000000000000: n4307_o = 1'b0; + 63'b000000000000010000000000000000000000000000000000000000000000000: n4307_o = 1'b0; + 63'b000000000000001000000000000000000000000000000000000000000000000: n4307_o = 1'b0; + 63'b000000000000000100000000000000000000000000000000000000000000000: n4307_o = 1'b0; + 63'b000000000000000010000000000000000000000000000000000000000000000: n4307_o = 1'b0; + 63'b000000000000000001000000000000000000000000000000000000000000000: n4307_o = 1'b0; + 63'b000000000000000000100000000000000000000000000000000000000000000: n4307_o = 1'b0; + 63'b000000000000000000010000000000000000000000000000000000000000000: n4307_o = 1'b0; + 63'b000000000000000000001000000000000000000000000000000000000000000: n4307_o = 1'b0; + 63'b000000000000000000000100000000000000000000000000000000000000000: n4307_o = 1'b0; + 63'b000000000000000000000010000000000000000000000000000000000000000: n4307_o = 1'b0; + 63'b000000000000000000000001000000000000000000000000000000000000000: n4307_o = 1'b0; + 63'b000000000000000000000000100000000000000000000000000000000000000: n4307_o = 1'b0; + 63'b000000000000000000000000010000000000000000000000000000000000000: n4307_o = 1'b0; + 63'b000000000000000000000000001000000000000000000000000000000000000: n4307_o = 1'b0; + 63'b000000000000000000000000000100000000000000000000000000000000000: n4307_o = 1'b0; + 63'b000000000000000000000000000010000000000000000000000000000000000: n4307_o = 1'b0; + 63'b000000000000000000000000000001000000000000000000000000000000000: n4307_o = 1'b0; + 63'b000000000000000000000000000000100000000000000000000000000000000: n4307_o = 1'b0; + 63'b000000000000000000000000000000010000000000000000000000000000000: n4307_o = 1'b0; + 63'b000000000000000000000000000000001000000000000000000000000000000: n4307_o = 1'b0; + 63'b000000000000000000000000000000000100000000000000000000000000000: n4307_o = 1'b0; + 63'b000000000000000000000000000000000010000000000000000000000000000: n4307_o = 1'b0; + 63'b000000000000000000000000000000000001000000000000000000000000000: n4307_o = 1'b0; + 63'b000000000000000000000000000000000000100000000000000000000000000: n4307_o = 1'b0; + 63'b000000000000000000000000000000000000010000000000000000000000000: n4307_o = 1'b0; + 63'b000000000000000000000000000000000000001000000000000000000000000: n4307_o = 1'b0; + 63'b000000000000000000000000000000000000000100000000000000000000000: n4307_o = 1'b0; + 63'b000000000000000000000000000000000000000010000000000000000000000: n4307_o = 1'b0; + 63'b000000000000000000000000000000000000000001000000000000000000000: n4307_o = 1'b0; + 63'b000000000000000000000000000000000000000000100000000000000000000: n4307_o = 1'b0; + 63'b000000000000000000000000000000000000000000010000000000000000000: n4307_o = 1'b0; + 63'b000000000000000000000000000000000000000000001000000000000000000: n4307_o = 1'b0; + 63'b000000000000000000000000000000000000000000000100000000000000000: n4307_o = 1'b0; + 63'b000000000000000000000000000000000000000000000010000000000000000: n4307_o = 1'b0; + 63'b000000000000000000000000000000000000000000000001000000000000000: n4307_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000100000000000000: n4307_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000010000000000000: n4307_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000001000000000000: n4307_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000100000000000: n4307_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000010000000000: n4307_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000001000000000: n4307_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000100000000: n4307_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000010000000: n4307_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000001000000: n4307_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000100000: n4307_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000010000: n4307_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000001000: n4307_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000000100: n4307_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000000010: n4307_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000000001: n4307_o = 1'b0; + default: n4307_o = 1'b0; + endcase + /* decoder.vhd:635:5 */ + always @* + case (n4151_o) + 63'b100000000000000000000000000000000000000000000000000000000000000: n4310_o = 1'b0; + 63'b010000000000000000000000000000000000000000000000000000000000000: n4310_o = 1'b0; + 63'b001000000000000000000000000000000000000000000000000000000000000: n4310_o = 1'b0; + 63'b000100000000000000000000000000000000000000000000000000000000000: n4310_o = 1'b0; + 63'b000010000000000000000000000000000000000000000000000000000000000: n4310_o = 1'b0; + 63'b000001000000000000000000000000000000000000000000000000000000000: n4310_o = 1'b0; + 63'b000000100000000000000000000000000000000000000000000000000000000: n4310_o = 1'b0; + 63'b000000010000000000000000000000000000000000000000000000000000000: n4310_o = 1'b0; + 63'b000000001000000000000000000000000000000000000000000000000000000: n4310_o = 1'b0; + 63'b000000000100000000000000000000000000000000000000000000000000000: n4310_o = 1'b0; + 63'b000000000010000000000000000000000000000000000000000000000000000: n4310_o = 1'b0; + 63'b000000000001000000000000000000000000000000000000000000000000000: n4310_o = 1'b0; + 63'b000000000000100000000000000000000000000000000000000000000000000: n4310_o = 1'b0; + 63'b000000000000010000000000000000000000000000000000000000000000000: n4310_o = 1'b0; + 63'b000000000000001000000000000000000000000000000000000000000000000: n4310_o = 1'b0; + 63'b000000000000000100000000000000000000000000000000000000000000000: n4310_o = 1'b0; + 63'b000000000000000010000000000000000000000000000000000000000000000: n4310_o = 1'b0; + 63'b000000000000000001000000000000000000000000000000000000000000000: n4310_o = 1'b0; + 63'b000000000000000000100000000000000000000000000000000000000000000: n4310_o = 1'b0; + 63'b000000000000000000010000000000000000000000000000000000000000000: n4310_o = 1'b0; + 63'b000000000000000000001000000000000000000000000000000000000000000: n4310_o = 1'b0; + 63'b000000000000000000000100000000000000000000000000000000000000000: n4310_o = n3354_o; + 63'b000000000000000000000010000000000000000000000000000000000000000: n4310_o = 1'b0; + 63'b000000000000000000000001000000000000000000000000000000000000000: n4310_o = 1'b0; + 63'b000000000000000000000000100000000000000000000000000000000000000: n4310_o = 1'b0; + 63'b000000000000000000000000010000000000000000000000000000000000000: n4310_o = 1'b0; + 63'b000000000000000000000000001000000000000000000000000000000000000: n4310_o = 1'b0; + 63'b000000000000000000000000000100000000000000000000000000000000000: n4310_o = 1'b0; + 63'b000000000000000000000000000010000000000000000000000000000000000: n4310_o = 1'b0; + 63'b000000000000000000000000000001000000000000000000000000000000000: n4310_o = 1'b0; + 63'b000000000000000000000000000000100000000000000000000000000000000: n4310_o = 1'b0; + 63'b000000000000000000000000000000010000000000000000000000000000000: n4310_o = 1'b0; + 63'b000000000000000000000000000000001000000000000000000000000000000: n4310_o = 1'b0; + 63'b000000000000000000000000000000000100000000000000000000000000000: n4310_o = 1'b0; + 63'b000000000000000000000000000000000010000000000000000000000000000: n4310_o = 1'b0; + 63'b000000000000000000000000000000000001000000000000000000000000000: n4310_o = 1'b0; + 63'b000000000000000000000000000000000000100000000000000000000000000: n4310_o = 1'b0; + 63'b000000000000000000000000000000000000010000000000000000000000000: n4310_o = 1'b0; + 63'b000000000000000000000000000000000000001000000000000000000000000: n4310_o = 1'b0; + 63'b000000000000000000000000000000000000000100000000000000000000000: n4310_o = 1'b0; + 63'b000000000000000000000000000000000000000010000000000000000000000: n4310_o = 1'b0; + 63'b000000000000000000000000000000000000000001000000000000000000000: n4310_o = 1'b0; + 63'b000000000000000000000000000000000000000000100000000000000000000: n4310_o = 1'b0; + 63'b000000000000000000000000000000000000000000010000000000000000000: n4310_o = 1'b0; + 63'b000000000000000000000000000000000000000000001000000000000000000: n4310_o = 1'b0; + 63'b000000000000000000000000000000000000000000000100000000000000000: n4310_o = 1'b0; + 63'b000000000000000000000000000000000000000000000010000000000000000: n4310_o = 1'b0; + 63'b000000000000000000000000000000000000000000000001000000000000000: n4310_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000100000000000000: n4310_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000010000000000000: n4310_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000001000000000000: n4310_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000100000000000: n4310_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000010000000000: n4310_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000001000000000: n4310_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000100000000: n4310_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000010000000: n4310_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000001000000: n4310_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000100000: n4310_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000010000: n4310_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000001000: n4310_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000000100: n4310_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000000010: n4310_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000000001: n4310_o = 1'b0; + default: n4310_o = 1'b0; + endcase + /* decoder.vhd:635:5 */ + always @* + case (n4151_o) + 63'b100000000000000000000000000000000000000000000000000000000000000: n4313_o = 1'b0; + 63'b010000000000000000000000000000000000000000000000000000000000000: n4313_o = 1'b0; + 63'b001000000000000000000000000000000000000000000000000000000000000: n4313_o = 1'b0; + 63'b000100000000000000000000000000000000000000000000000000000000000: n4313_o = 1'b0; + 63'b000010000000000000000000000000000000000000000000000000000000000: n4313_o = 1'b0; + 63'b000001000000000000000000000000000000000000000000000000000000000: n4313_o = 1'b0; + 63'b000000100000000000000000000000000000000000000000000000000000000: n4313_o = 1'b0; + 63'b000000010000000000000000000000000000000000000000000000000000000: n4313_o = 1'b0; + 63'b000000001000000000000000000000000000000000000000000000000000000: n4313_o = 1'b0; + 63'b000000000100000000000000000000000000000000000000000000000000000: n4313_o = 1'b0; + 63'b000000000010000000000000000000000000000000000000000000000000000: n4313_o = 1'b0; + 63'b000000000001000000000000000000000000000000000000000000000000000: n4313_o = 1'b0; + 63'b000000000000100000000000000000000000000000000000000000000000000: n4313_o = 1'b0; + 63'b000000000000010000000000000000000000000000000000000000000000000: n4313_o = 1'b0; + 63'b000000000000001000000000000000000000000000000000000000000000000: n4313_o = 1'b0; + 63'b000000000000000100000000000000000000000000000000000000000000000: n4313_o = 1'b0; + 63'b000000000000000010000000000000000000000000000000000000000000000: n4313_o = 1'b0; + 63'b000000000000000001000000000000000000000000000000000000000000000: n4313_o = 1'b0; + 63'b000000000000000000100000000000000000000000000000000000000000000: n4313_o = 1'b0; + 63'b000000000000000000010000000000000000000000000000000000000000000: n4313_o = 1'b0; + 63'b000000000000000000001000000000000000000000000000000000000000000: n4313_o = 1'b0; + 63'b000000000000000000000100000000000000000000000000000000000000000: n4313_o = n3356_o; + 63'b000000000000000000000010000000000000000000000000000000000000000: n4313_o = 1'b0; + 63'b000000000000000000000001000000000000000000000000000000000000000: n4313_o = 1'b0; + 63'b000000000000000000000000100000000000000000000000000000000000000: n4313_o = 1'b0; + 63'b000000000000000000000000010000000000000000000000000000000000000: n4313_o = 1'b0; + 63'b000000000000000000000000001000000000000000000000000000000000000: n4313_o = 1'b0; + 63'b000000000000000000000000000100000000000000000000000000000000000: n4313_o = 1'b0; + 63'b000000000000000000000000000010000000000000000000000000000000000: n4313_o = 1'b0; + 63'b000000000000000000000000000001000000000000000000000000000000000: n4313_o = 1'b0; + 63'b000000000000000000000000000000100000000000000000000000000000000: n4313_o = 1'b0; + 63'b000000000000000000000000000000010000000000000000000000000000000: n4313_o = 1'b0; + 63'b000000000000000000000000000000001000000000000000000000000000000: n4313_o = 1'b0; + 63'b000000000000000000000000000000000100000000000000000000000000000: n4313_o = 1'b0; + 63'b000000000000000000000000000000000010000000000000000000000000000: n4313_o = 1'b0; + 63'b000000000000000000000000000000000001000000000000000000000000000: n4313_o = 1'b0; + 63'b000000000000000000000000000000000000100000000000000000000000000: n4313_o = 1'b0; + 63'b000000000000000000000000000000000000010000000000000000000000000: n4313_o = 1'b0; + 63'b000000000000000000000000000000000000001000000000000000000000000: n4313_o = 1'b0; + 63'b000000000000000000000000000000000000000100000000000000000000000: n4313_o = 1'b0; + 63'b000000000000000000000000000000000000000010000000000000000000000: n4313_o = 1'b0; + 63'b000000000000000000000000000000000000000001000000000000000000000: n4313_o = 1'b0; + 63'b000000000000000000000000000000000000000000100000000000000000000: n4313_o = 1'b0; + 63'b000000000000000000000000000000000000000000010000000000000000000: n4313_o = 1'b0; + 63'b000000000000000000000000000000000000000000001000000000000000000: n4313_o = 1'b0; + 63'b000000000000000000000000000000000000000000000100000000000000000: n4313_o = 1'b0; + 63'b000000000000000000000000000000000000000000000010000000000000000: n4313_o = 1'b0; + 63'b000000000000000000000000000000000000000000000001000000000000000: n4313_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000100000000000000: n4313_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000010000000000000: n4313_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000001000000000000: n4313_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000100000000000: n4313_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000010000000000: n4313_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000001000000000: n4313_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000100000000: n4313_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000010000000: n4313_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000001000000: n4313_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000100000: n4313_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000010000: n4313_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000001000: n4313_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000000100: n4313_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000000010: n4313_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000000001: n4313_o = 1'b0; + default: n4313_o = 1'b0; + endcase + /* decoder.vhd:635:5 */ + always @* + case (n4151_o) + 63'b100000000000000000000000000000000000000000000000000000000000000: n4316_o = 1'b0; + 63'b010000000000000000000000000000000000000000000000000000000000000: n4316_o = 1'b0; + 63'b001000000000000000000000000000000000000000000000000000000000000: n4316_o = 1'b0; + 63'b000100000000000000000000000000000000000000000000000000000000000: n4316_o = 1'b0; + 63'b000010000000000000000000000000000000000000000000000000000000000: n4316_o = n4000_o; + 63'b000001000000000000000000000000000000000000000000000000000000000: n4316_o = 1'b0; + 63'b000000100000000000000000000000000000000000000000000000000000000: n4316_o = 1'b0; + 63'b000000010000000000000000000000000000000000000000000000000000000: n4316_o = 1'b0; + 63'b000000001000000000000000000000000000000000000000000000000000000: n4316_o = 1'b0; + 63'b000000000100000000000000000000000000000000000000000000000000000: n4316_o = 1'b0; + 63'b000000000010000000000000000000000000000000000000000000000000000: n4316_o = 1'b0; + 63'b000000000001000000000000000000000000000000000000000000000000000: n4316_o = 1'b0; + 63'b000000000000100000000000000000000000000000000000000000000000000: n4316_o = 1'b0; + 63'b000000000000010000000000000000000000000000000000000000000000000: n4316_o = 1'b0; + 63'b000000000000001000000000000000000000000000000000000000000000000: n4316_o = 1'b0; + 63'b000000000000000100000000000000000000000000000000000000000000000: n4316_o = 1'b0; + 63'b000000000000000010000000000000000000000000000000000000000000000: n4316_o = 1'b0; + 63'b000000000000000001000000000000000000000000000000000000000000000: n4316_o = 1'b0; + 63'b000000000000000000100000000000000000000000000000000000000000000: n4316_o = 1'b0; + 63'b000000000000000000010000000000000000000000000000000000000000000: n4316_o = 1'b0; + 63'b000000000000000000001000000000000000000000000000000000000000000: n4316_o = 1'b0; + 63'b000000000000000000000100000000000000000000000000000000000000000: n4316_o = 1'b0; + 63'b000000000000000000000010000000000000000000000000000000000000000: n4316_o = 1'b0; + 63'b000000000000000000000001000000000000000000000000000000000000000: n4316_o = 1'b0; + 63'b000000000000000000000000100000000000000000000000000000000000000: n4316_o = 1'b0; + 63'b000000000000000000000000010000000000000000000000000000000000000: n4316_o = 1'b0; + 63'b000000000000000000000000001000000000000000000000000000000000000: n4316_o = 1'b0; + 63'b000000000000000000000000000100000000000000000000000000000000000: n4316_o = 1'b0; + 63'b000000000000000000000000000010000000000000000000000000000000000: n4316_o = 1'b0; + 63'b000000000000000000000000000001000000000000000000000000000000000: n4316_o = 1'b0; + 63'b000000000000000000000000000000100000000000000000000000000000000: n4316_o = 1'b0; + 63'b000000000000000000000000000000010000000000000000000000000000000: n4316_o = 1'b0; + 63'b000000000000000000000000000000001000000000000000000000000000000: n4316_o = 1'b0; + 63'b000000000000000000000000000000000100000000000000000000000000000: n4316_o = 1'b0; + 63'b000000000000000000000000000000000010000000000000000000000000000: n4316_o = 1'b0; + 63'b000000000000000000000000000000000001000000000000000000000000000: n4316_o = 1'b0; + 63'b000000000000000000000000000000000000100000000000000000000000000: n4316_o = 1'b0; + 63'b000000000000000000000000000000000000010000000000000000000000000: n4316_o = 1'b0; + 63'b000000000000000000000000000000000000001000000000000000000000000: n4316_o = 1'b0; + 63'b000000000000000000000000000000000000000100000000000000000000000: n4316_o = 1'b0; + 63'b000000000000000000000000000000000000000010000000000000000000000: n4316_o = 1'b0; + 63'b000000000000000000000000000000000000000001000000000000000000000: n4316_o = 1'b0; + 63'b000000000000000000000000000000000000000000100000000000000000000: n4316_o = 1'b0; + 63'b000000000000000000000000000000000000000000010000000000000000000: n4316_o = 1'b0; + 63'b000000000000000000000000000000000000000000001000000000000000000: n4316_o = 1'b0; + 63'b000000000000000000000000000000000000000000000100000000000000000: n4316_o = 1'b0; + 63'b000000000000000000000000000000000000000000000010000000000000000: n4316_o = 1'b0; + 63'b000000000000000000000000000000000000000000000001000000000000000: n4316_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000100000000000000: n4316_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000010000000000000: n4316_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000001000000000000: n4316_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000100000000000: n4316_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000010000000000: n4316_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000001000000000: n4316_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000100000000: n4316_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000010000000: n4316_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000001000000: n4316_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000100000: n4316_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000010000: n4316_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000001000: n4316_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000000100: n4316_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000000010: n4316_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000000001: n4316_o = 1'b0; + default: n4316_o = 1'b0; + endcase + /* decoder.vhd:635:5 */ + always @* + case (n4151_o) + 63'b100000000000000000000000000000000000000000000000000000000000000: n4319_o = 1'b0; + 63'b010000000000000000000000000000000000000000000000000000000000000: n4319_o = 1'b0; + 63'b001000000000000000000000000000000000000000000000000000000000000: n4319_o = 1'b0; + 63'b000100000000000000000000000000000000000000000000000000000000000: n4319_o = 1'b0; + 63'b000010000000000000000000000000000000000000000000000000000000000: n4319_o = n4002_o; + 63'b000001000000000000000000000000000000000000000000000000000000000: n4319_o = 1'b0; + 63'b000000100000000000000000000000000000000000000000000000000000000: n4319_o = 1'b0; + 63'b000000010000000000000000000000000000000000000000000000000000000: n4319_o = 1'b0; + 63'b000000001000000000000000000000000000000000000000000000000000000: n4319_o = 1'b0; + 63'b000000000100000000000000000000000000000000000000000000000000000: n4319_o = 1'b0; + 63'b000000000010000000000000000000000000000000000000000000000000000: n4319_o = 1'b0; + 63'b000000000001000000000000000000000000000000000000000000000000000: n4319_o = 1'b0; + 63'b000000000000100000000000000000000000000000000000000000000000000: n4319_o = 1'b0; + 63'b000000000000010000000000000000000000000000000000000000000000000: n4319_o = 1'b0; + 63'b000000000000001000000000000000000000000000000000000000000000000: n4319_o = 1'b0; + 63'b000000000000000100000000000000000000000000000000000000000000000: n4319_o = 1'b0; + 63'b000000000000000010000000000000000000000000000000000000000000000: n4319_o = 1'b0; + 63'b000000000000000001000000000000000000000000000000000000000000000: n4319_o = 1'b0; + 63'b000000000000000000100000000000000000000000000000000000000000000: n4319_o = 1'b0; + 63'b000000000000000000010000000000000000000000000000000000000000000: n4319_o = 1'b0; + 63'b000000000000000000001000000000000000000000000000000000000000000: n4319_o = 1'b0; + 63'b000000000000000000000100000000000000000000000000000000000000000: n4319_o = 1'b0; + 63'b000000000000000000000010000000000000000000000000000000000000000: n4319_o = 1'b0; + 63'b000000000000000000000001000000000000000000000000000000000000000: n4319_o = 1'b0; + 63'b000000000000000000000000100000000000000000000000000000000000000: n4319_o = 1'b0; + 63'b000000000000000000000000010000000000000000000000000000000000000: n4319_o = 1'b0; + 63'b000000000000000000000000001000000000000000000000000000000000000: n4319_o = 1'b0; + 63'b000000000000000000000000000100000000000000000000000000000000000: n4319_o = 1'b0; + 63'b000000000000000000000000000010000000000000000000000000000000000: n4319_o = 1'b0; + 63'b000000000000000000000000000001000000000000000000000000000000000: n4319_o = 1'b0; + 63'b000000000000000000000000000000100000000000000000000000000000000: n4319_o = 1'b0; + 63'b000000000000000000000000000000010000000000000000000000000000000: n4319_o = 1'b0; + 63'b000000000000000000000000000000001000000000000000000000000000000: n4319_o = 1'b0; + 63'b000000000000000000000000000000000100000000000000000000000000000: n4319_o = 1'b0; + 63'b000000000000000000000000000000000010000000000000000000000000000: n4319_o = 1'b0; + 63'b000000000000000000000000000000000001000000000000000000000000000: n4319_o = 1'b0; + 63'b000000000000000000000000000000000000100000000000000000000000000: n4319_o = 1'b0; + 63'b000000000000000000000000000000000000010000000000000000000000000: n4319_o = 1'b0; + 63'b000000000000000000000000000000000000001000000000000000000000000: n4319_o = 1'b0; + 63'b000000000000000000000000000000000000000100000000000000000000000: n4319_o = 1'b0; + 63'b000000000000000000000000000000000000000010000000000000000000000: n4319_o = 1'b0; + 63'b000000000000000000000000000000000000000001000000000000000000000: n4319_o = 1'b0; + 63'b000000000000000000000000000000000000000000100000000000000000000: n4319_o = 1'b0; + 63'b000000000000000000000000000000000000000000010000000000000000000: n4319_o = 1'b0; + 63'b000000000000000000000000000000000000000000001000000000000000000: n4319_o = 1'b0; + 63'b000000000000000000000000000000000000000000000100000000000000000: n4319_o = 1'b0; + 63'b000000000000000000000000000000000000000000000010000000000000000: n4319_o = 1'b0; + 63'b000000000000000000000000000000000000000000000001000000000000000: n4319_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000100000000000000: n4319_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000010000000000000: n4319_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000001000000000000: n4319_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000100000000000: n4319_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000010000000000: n4319_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000001000000000: n4319_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000100000000: n4319_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000010000000: n4319_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000001000000: n4319_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000100000: n4319_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000010000: n4319_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000001000: n4319_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000000100: n4319_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000000010: n4319_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000000001: n4319_o = 1'b0; + default: n4319_o = 1'b0; + endcase + /* decoder.vhd:635:5 */ + always @* + case (n4151_o) + 63'b100000000000000000000000000000000000000000000000000000000000000: n4322_o = 1'b0; + 63'b010000000000000000000000000000000000000000000000000000000000000: n4322_o = 1'b0; + 63'b001000000000000000000000000000000000000000000000000000000000000: n4322_o = 1'b0; + 63'b000100000000000000000000000000000000000000000000000000000000000: n4322_o = 1'b0; + 63'b000010000000000000000000000000000000000000000000000000000000000: n4322_o = 1'b0; + 63'b000001000000000000000000000000000000000000000000000000000000000: n4322_o = n3987_o; + 63'b000000100000000000000000000000000000000000000000000000000000000: n4322_o = 1'b0; + 63'b000000010000000000000000000000000000000000000000000000000000000: n4322_o = 1'b0; + 63'b000000001000000000000000000000000000000000000000000000000000000: n4322_o = 1'b0; + 63'b000000000100000000000000000000000000000000000000000000000000000: n4322_o = 1'b0; + 63'b000000000010000000000000000000000000000000000000000000000000000: n4322_o = 1'b0; + 63'b000000000001000000000000000000000000000000000000000000000000000: n4322_o = 1'b0; + 63'b000000000000100000000000000000000000000000000000000000000000000: n4322_o = 1'b0; + 63'b000000000000010000000000000000000000000000000000000000000000000: n4322_o = 1'b0; + 63'b000000000000001000000000000000000000000000000000000000000000000: n4322_o = 1'b0; + 63'b000000000000000100000000000000000000000000000000000000000000000: n4322_o = 1'b0; + 63'b000000000000000010000000000000000000000000000000000000000000000: n4322_o = 1'b0; + 63'b000000000000000001000000000000000000000000000000000000000000000: n4322_o = 1'b0; + 63'b000000000000000000100000000000000000000000000000000000000000000: n4322_o = 1'b0; + 63'b000000000000000000010000000000000000000000000000000000000000000: n4322_o = 1'b0; + 63'b000000000000000000001000000000000000000000000000000000000000000: n4322_o = 1'b0; + 63'b000000000000000000000100000000000000000000000000000000000000000: n4322_o = 1'b0; + 63'b000000000000000000000010000000000000000000000000000000000000000: n4322_o = 1'b0; + 63'b000000000000000000000001000000000000000000000000000000000000000: n4322_o = 1'b0; + 63'b000000000000000000000000100000000000000000000000000000000000000: n4322_o = 1'b0; + 63'b000000000000000000000000010000000000000000000000000000000000000: n4322_o = 1'b0; + 63'b000000000000000000000000001000000000000000000000000000000000000: n4322_o = 1'b0; + 63'b000000000000000000000000000100000000000000000000000000000000000: n4322_o = 1'b0; + 63'b000000000000000000000000000010000000000000000000000000000000000: n4322_o = 1'b0; + 63'b000000000000000000000000000001000000000000000000000000000000000: n4322_o = 1'b0; + 63'b000000000000000000000000000000100000000000000000000000000000000: n4322_o = 1'b0; + 63'b000000000000000000000000000000010000000000000000000000000000000: n4322_o = 1'b0; + 63'b000000000000000000000000000000001000000000000000000000000000000: n4322_o = 1'b0; + 63'b000000000000000000000000000000000100000000000000000000000000000: n4322_o = 1'b0; + 63'b000000000000000000000000000000000010000000000000000000000000000: n4322_o = 1'b0; + 63'b000000000000000000000000000000000001000000000000000000000000000: n4322_o = 1'b0; + 63'b000000000000000000000000000000000000100000000000000000000000000: n4322_o = 1'b0; + 63'b000000000000000000000000000000000000010000000000000000000000000: n4322_o = 1'b0; + 63'b000000000000000000000000000000000000001000000000000000000000000: n4322_o = 1'b0; + 63'b000000000000000000000000000000000000000100000000000000000000000: n4322_o = 1'b0; + 63'b000000000000000000000000000000000000000010000000000000000000000: n4322_o = 1'b0; + 63'b000000000000000000000000000000000000000001000000000000000000000: n4322_o = 1'b0; + 63'b000000000000000000000000000000000000000000100000000000000000000: n4322_o = 1'b0; + 63'b000000000000000000000000000000000000000000010000000000000000000: n4322_o = 1'b0; + 63'b000000000000000000000000000000000000000000001000000000000000000: n4322_o = 1'b0; + 63'b000000000000000000000000000000000000000000000100000000000000000: n4322_o = 1'b0; + 63'b000000000000000000000000000000000000000000000010000000000000000: n4322_o = 1'b0; + 63'b000000000000000000000000000000000000000000000001000000000000000: n4322_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000100000000000000: n4322_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000010000000000000: n4322_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000001000000000000: n4322_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000100000000000: n4322_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000010000000000: n4322_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000001000000000: n4322_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000100000000: n4322_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000010000000: n4322_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000001000000: n4322_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000100000: n4322_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000010000: n4322_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000001000: n4322_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000000100: n4322_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000000010: n4322_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000000001: n4322_o = 1'b0; + default: n4322_o = 1'b0; + endcase + /* decoder.vhd:635:5 */ + always @* + case (n4151_o) + 63'b100000000000000000000000000000000000000000000000000000000000000: n4347_o = 1'b1; + 63'b010000000000000000000000000000000000000000000000000000000000000: n4347_o = 1'b0; + 63'b001000000000000000000000000000000000000000000000000000000000000: n4347_o = 1'b0; + 63'b000100000000000000000000000000000000000000000000000000000000000: n4347_o = 1'b0; + 63'b000010000000000000000000000000000000000000000000000000000000000: n4347_o = 1'b0; + 63'b000001000000000000000000000000000000000000000000000000000000000: n4347_o = 1'b0; + 63'b000000100000000000000000000000000000000000000000000000000000000: n4347_o = 1'b0; + 63'b000000010000000000000000000000000000000000000000000000000000000: n4347_o = 1'b0; + 63'b000000001000000000000000000000000000000000000000000000000000000: n4347_o = 1'b0; + 63'b000000000100000000000000000000000000000000000000000000000000000: n4347_o = 1'b0; + 63'b000000000010000000000000000000000000000000000000000000000000000: n4347_o = 1'b0; + 63'b000000000001000000000000000000000000000000000000000000000000000: n4347_o = 1'b0; + 63'b000000000000100000000000000000000000000000000000000000000000000: n4347_o = 1'b0; + 63'b000000000000010000000000000000000000000000000000000000000000000: n4347_o = 1'b1; + 63'b000000000000001000000000000000000000000000000000000000000000000: n4347_o = 1'b1; + 63'b000000000000000100000000000000000000000000000000000000000000000: n4347_o = 1'b0; + 63'b000000000000000010000000000000000000000000000000000000000000000: n4347_o = 1'b0; + 63'b000000000000000001000000000000000000000000000000000000000000000: n4347_o = 1'b0; + 63'b000000000000000000100000000000000000000000000000000000000000000: n4347_o = 1'b1; + 63'b000000000000000000010000000000000000000000000000000000000000000: n4347_o = 1'b0; + 63'b000000000000000000001000000000000000000000000000000000000000000: n4347_o = 1'b0; + 63'b000000000000000000000100000000000000000000000000000000000000000: n4347_o = 1'b0; + 63'b000000000000000000000010000000000000000000000000000000000000000: n4347_o = 1'b0; + 63'b000000000000000000000001000000000000000000000000000000000000000: n4347_o = 1'b1; + 63'b000000000000000000000000100000000000000000000000000000000000000: n4347_o = 1'b0; + 63'b000000000000000000000000010000000000000000000000000000000000000: n4347_o = 1'b0; + 63'b000000000000000000000000001000000000000000000000000000000000000: n4347_o = 1'b0; + 63'b000000000000000000000000000100000000000000000000000000000000000: n4347_o = 1'b0; + 63'b000000000000000000000000000010000000000000000000000000000000000: n4347_o = 1'b1; + 63'b000000000000000000000000000001000000000000000000000000000000000: n4347_o = 1'b1; + 63'b000000000000000000000000000000100000000000000000000000000000000: n4347_o = 1'b1; + 63'b000000000000000000000000000000010000000000000000000000000000000: n4347_o = 1'b1; + 63'b000000000000000000000000000000001000000000000000000000000000000: n4347_o = 1'b1; + 63'b000000000000000000000000000000000100000000000000000000000000000: n4347_o = 1'b1; + 63'b000000000000000000000000000000000010000000000000000000000000000: n4347_o = 1'b1; + 63'b000000000000000000000000000000000001000000000000000000000000000: n4347_o = 1'b1; + 63'b000000000000000000000000000000000000100000000000000000000000000: n4347_o = 1'b1; + 63'b000000000000000000000000000000000000010000000000000000000000000: n4347_o = 1'b1; + 63'b000000000000000000000000000000000000001000000000000000000000000: n4347_o = 1'b1; + 63'b000000000000000000000000000000000000000100000000000000000000000: n4347_o = 1'b1; + 63'b000000000000000000000000000000000000000010000000000000000000000: n4347_o = 1'b0; + 63'b000000000000000000000000000000000000000001000000000000000000000: n4347_o = 1'b0; + 63'b000000000000000000000000000000000000000000100000000000000000000: n4347_o = 1'b0; + 63'b000000000000000000000000000000000000000000010000000000000000000: n4347_o = 1'b0; + 63'b000000000000000000000000000000000000000000001000000000000000000: n4347_o = 1'b0; + 63'b000000000000000000000000000000000000000000000100000000000000000: n4347_o = 1'b0; + 63'b000000000000000000000000000000000000000000000010000000000000000: n4347_o = 1'b1; + 63'b000000000000000000000000000000000000000000000001000000000000000: n4347_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000100000000000000: n4347_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000010000000000000: n4347_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000001000000000000: n4347_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000100000000000: n4347_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000010000000000: n4347_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000001000000000: n4347_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000100000000: n4347_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000010000000: n4347_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000001000000: n4347_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000100000: n4347_o = 1'b1; + 63'b000000000000000000000000000000000000000000000000000000000010000: n4347_o = 1'b1; + 63'b000000000000000000000000000000000000000000000000000000000001000: n4347_o = 1'b1; + 63'b000000000000000000000000000000000000000000000000000000000000100: n4347_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000000010: n4347_o = 1'b1; + 63'b000000000000000000000000000000000000000000000000000000000000001: n4347_o = 1'b0; + default: n4347_o = 1'b0; + endcase + /* decoder.vhd:635:5 */ + always @* + case (n4151_o) + 63'b100000000000000000000000000000000000000000000000000000000000000: n4350_o = 1'b0; + 63'b010000000000000000000000000000000000000000000000000000000000000: n4350_o = 1'b0; + 63'b001000000000000000000000000000000000000000000000000000000000000: n4350_o = 1'b0; + 63'b000100000000000000000000000000000000000000000000000000000000000: n4350_o = 1'b0; + 63'b000010000000000000000000000000000000000000000000000000000000000: n4350_o = 1'b0; + 63'b000001000000000000000000000000000000000000000000000000000000000: n4350_o = 1'b0; + 63'b000000100000000000000000000000000000000000000000000000000000000: n4350_o = 1'b0; + 63'b000000010000000000000000000000000000000000000000000000000000000: n4350_o = 1'b0; + 63'b000000001000000000000000000000000000000000000000000000000000000: n4350_o = 1'b0; + 63'b000000000100000000000000000000000000000000000000000000000000000: n4350_o = 1'b0; + 63'b000000000010000000000000000000000000000000000000000000000000000: n4350_o = 1'b0; + 63'b000000000001000000000000000000000000000000000000000000000000000: n4350_o = 1'b0; + 63'b000000000000100000000000000000000000000000000000000000000000000: n4350_o = 1'b0; + 63'b000000000000010000000000000000000000000000000000000000000000000: n4350_o = 1'b0; + 63'b000000000000001000000000000000000000000000000000000000000000000: n4350_o = 1'b0; + 63'b000000000000000100000000000000000000000000000000000000000000000: n4350_o = 1'b0; + 63'b000000000000000010000000000000000000000000000000000000000000000: n4350_o = 1'b0; + 63'b000000000000000001000000000000000000000000000000000000000000000: n4350_o = 1'b0; + 63'b000000000000000000100000000000000000000000000000000000000000000: n4350_o = n3520_o; + 63'b000000000000000000010000000000000000000000000000000000000000000: n4350_o = 1'b0; + 63'b000000000000000000001000000000000000000000000000000000000000000: n4350_o = 1'b0; + 63'b000000000000000000000100000000000000000000000000000000000000000: n4350_o = 1'b0; + 63'b000000000000000000000010000000000000000000000000000000000000000: n4350_o = 1'b0; + 63'b000000000000000000000001000000000000000000000000000000000000000: n4350_o = 1'b0; + 63'b000000000000000000000000100000000000000000000000000000000000000: n4350_o = 1'b0; + 63'b000000000000000000000000010000000000000000000000000000000000000: n4350_o = 1'b0; + 63'b000000000000000000000000001000000000000000000000000000000000000: n4350_o = 1'b0; + 63'b000000000000000000000000000100000000000000000000000000000000000: n4350_o = 1'b0; + 63'b000000000000000000000000000010000000000000000000000000000000000: n4350_o = 1'b0; + 63'b000000000000000000000000000001000000000000000000000000000000000: n4350_o = n3179_o; + 63'b000000000000000000000000000000100000000000000000000000000000000: n4350_o = n3141_o; + 63'b000000000000000000000000000000010000000000000000000000000000000: n4350_o = n3112_o; + 63'b000000000000000000000000000000001000000000000000000000000000000: n4350_o = n3076_o; + 63'b000000000000000000000000000000000100000000000000000000000000000: n4350_o = n3050_o; + 63'b000000000000000000000000000000000010000000000000000000000000000: n4350_o = n3024_o; + 63'b000000000000000000000000000000000001000000000000000000000000000: n4350_o = n2998_o; + 63'b000000000000000000000000000000000000100000000000000000000000000: n4350_o = n2969_o; + 63'b000000000000000000000000000000000000010000000000000000000000000: n4350_o = n2940_o; + 63'b000000000000000000000000000000000000001000000000000000000000000: n4350_o = n2906_o; + 63'b000000000000000000000000000000000000000100000000000000000000000: n4350_o = n2875_o; + 63'b000000000000000000000000000000000000000010000000000000000000000: n4350_o = 1'b0; + 63'b000000000000000000000000000000000000000001000000000000000000000: n4350_o = 1'b0; + 63'b000000000000000000000000000000000000000000100000000000000000000: n4350_o = 1'b0; + 63'b000000000000000000000000000000000000000000010000000000000000000: n4350_o = 1'b0; + 63'b000000000000000000000000000000000000000000001000000000000000000: n4350_o = 1'b0; + 63'b000000000000000000000000000000000000000000000100000000000000000: n4350_o = 1'b0; + 63'b000000000000000000000000000000000000000000000010000000000000000: n4350_o = n2717_o; + 63'b000000000000000000000000000000000000000000000001000000000000000: n4350_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000100000000000000: n4350_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000010000000000000: n4350_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000001000000000000: n4350_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000100000000000: n4350_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000010000000000: n4350_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000001000000000: n4350_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000100000000: n4350_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000010000000: n4350_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000001000000: n4350_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000100000: n4350_o = n2455_o; + 63'b000000000000000000000000000000000000000000000000000000000010000: n4350_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000001000: n4350_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000000100: n4350_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000000010: n4350_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000000001: n4350_o = 1'b0; + default: n4350_o = 1'b0; + endcase + /* decoder.vhd:635:5 */ + always @* + case (n4151_o) + 63'b100000000000000000000000000000000000000000000000000000000000000: n4353_o = 1'b0; + 63'b010000000000000000000000000000000000000000000000000000000000000: n4353_o = 1'b0; + 63'b001000000000000000000000000000000000000000000000000000000000000: n4353_o = 1'b0; + 63'b000100000000000000000000000000000000000000000000000000000000000: n4353_o = 1'b0; + 63'b000010000000000000000000000000000000000000000000000000000000000: n4353_o = 1'b0; + 63'b000001000000000000000000000000000000000000000000000000000000000: n4353_o = 1'b0; + 63'b000000100000000000000000000000000000000000000000000000000000000: n4353_o = 1'b0; + 63'b000000010000000000000000000000000000000000000000000000000000000: n4353_o = 1'b0; + 63'b000000001000000000000000000000000000000000000000000000000000000: n4353_o = 1'b0; + 63'b000000000100000000000000000000000000000000000000000000000000000: n4353_o = 1'b0; + 63'b000000000010000000000000000000000000000000000000000000000000000: n4353_o = 1'b0; + 63'b000000000001000000000000000000000000000000000000000000000000000: n4353_o = 1'b0; + 63'b000000000000100000000000000000000000000000000000000000000000000: n4353_o = 1'b0; + 63'b000000000000010000000000000000000000000000000000000000000000000: n4353_o = 1'b0; + 63'b000000000000001000000000000000000000000000000000000000000000000: n4353_o = 1'b0; + 63'b000000000000000100000000000000000000000000000000000000000000000: n4353_o = 1'b0; + 63'b000000000000000010000000000000000000000000000000000000000000000: n4353_o = 1'b0; + 63'b000000000000000001000000000000000000000000000000000000000000000: n4353_o = 1'b0; + 63'b000000000000000000100000000000000000000000000000000000000000000: n4353_o = 1'b0; + 63'b000000000000000000010000000000000000000000000000000000000000000: n4353_o = 1'b0; + 63'b000000000000000000001000000000000000000000000000000000000000000: n4353_o = 1'b0; + 63'b000000000000000000000100000000000000000000000000000000000000000: n4353_o = 1'b0; + 63'b000000000000000000000010000000000000000000000000000000000000000: n4353_o = 1'b0; + 63'b000000000000000000000001000000000000000000000000000000000000000: n4353_o = 1'b0; + 63'b000000000000000000000000100000000000000000000000000000000000000: n4353_o = 1'b0; + 63'b000000000000000000000000010000000000000000000000000000000000000: n4353_o = 1'b0; + 63'b000000000000000000000000001000000000000000000000000000000000000: n4353_o = 1'b0; + 63'b000000000000000000000000000100000000000000000000000000000000000: n4353_o = 1'b0; + 63'b000000000000000000000000000010000000000000000000000000000000000: n4353_o = 1'b0; + 63'b000000000000000000000000000001000000000000000000000000000000000: n4353_o = 1'b0; + 63'b000000000000000000000000000000100000000000000000000000000000000: n4353_o = 1'b0; + 63'b000000000000000000000000000000010000000000000000000000000000000: n4353_o = 1'b0; + 63'b000000000000000000000000000000001000000000000000000000000000000: n4353_o = 1'b0; + 63'b000000000000000000000000000000000100000000000000000000000000000: n4353_o = 1'b0; + 63'b000000000000000000000000000000000010000000000000000000000000000: n4353_o = 1'b0; + 63'b000000000000000000000000000000000001000000000000000000000000000: n4353_o = 1'b0; + 63'b000000000000000000000000000000000000100000000000000000000000000: n4353_o = 1'b0; + 63'b000000000000000000000000000000000000010000000000000000000000000: n4353_o = 1'b0; + 63'b000000000000000000000000000000000000001000000000000000000000000: n4353_o = 1'b0; + 63'b000000000000000000000000000000000000000100000000000000000000000: n4353_o = 1'b0; + 63'b000000000000000000000000000000000000000010000000000000000000000: n4353_o = 1'b0; + 63'b000000000000000000000000000000000000000001000000000000000000000: n4353_o = 1'b0; + 63'b000000000000000000000000000000000000000000100000000000000000000: n4353_o = 1'b0; + 63'b000000000000000000000000000000000000000000010000000000000000000: n4353_o = 1'b0; + 63'b000000000000000000000000000000000000000000001000000000000000000: n4353_o = 1'b0; + 63'b000000000000000000000000000000000000000000000100000000000000000: n4353_o = 1'b0; + 63'b000000000000000000000000000000000000000000000010000000000000000: n4353_o = 1'b0; + 63'b000000000000000000000000000000000000000000000001000000000000000: n4353_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000100000000000000: n4353_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000010000000000000: n4353_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000001000000000000: n4353_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000100000000000: n4353_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000010000000000: n4353_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000001000000000: n4353_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000100000000: n4353_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000010000000: n4353_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000001000000: n4353_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000100000: n4353_o = n2457_o; + 63'b000000000000000000000000000000000000000000000000000000000010000: n4353_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000001000: n4353_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000000100: n4353_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000000010: n4353_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000000001: n4353_o = 1'b0; + default: n4353_o = 1'b0; + endcase + /* decoder.vhd:635:5 */ + always @* + case (n4151_o) + 63'b100000000000000000000000000000000000000000000000000000000000000: n4356_o = 1'b0; + 63'b010000000000000000000000000000000000000000000000000000000000000: n4356_o = 1'b0; + 63'b001000000000000000000000000000000000000000000000000000000000000: n4356_o = 1'b0; + 63'b000100000000000000000000000000000000000000000000000000000000000: n4356_o = 1'b0; + 63'b000010000000000000000000000000000000000000000000000000000000000: n4356_o = 1'b0; + 63'b000001000000000000000000000000000000000000000000000000000000000: n4356_o = 1'b0; + 63'b000000100000000000000000000000000000000000000000000000000000000: n4356_o = 1'b0; + 63'b000000010000000000000000000000000000000000000000000000000000000: n4356_o = 1'b0; + 63'b000000001000000000000000000000000000000000000000000000000000000: n4356_o = 1'b0; + 63'b000000000100000000000000000000000000000000000000000000000000000: n4356_o = 1'b0; + 63'b000000000010000000000000000000000000000000000000000000000000000: n4356_o = n3896_o; + 63'b000000000001000000000000000000000000000000000000000000000000000: n4356_o = 1'b0; + 63'b000000000000100000000000000000000000000000000000000000000000000: n4356_o = 1'b0; + 63'b000000000000010000000000000000000000000000000000000000000000000: n4356_o = 1'b0; + 63'b000000000000001000000000000000000000000000000000000000000000000: n4356_o = 1'b0; + 63'b000000000000000100000000000000000000000000000000000000000000000: n4356_o = 1'b0; + 63'b000000000000000010000000000000000000000000000000000000000000000: n4356_o = 1'b0; + 63'b000000000000000001000000000000000000000000000000000000000000000: n4356_o = 1'b0; + 63'b000000000000000000100000000000000000000000000000000000000000000: n4356_o = 1'b0; + 63'b000000000000000000010000000000000000000000000000000000000000000: n4356_o = 1'b0; + 63'b000000000000000000001000000000000000000000000000000000000000000: n4356_o = 1'b0; + 63'b000000000000000000000100000000000000000000000000000000000000000: n4356_o = 1'b0; + 63'b000000000000000000000010000000000000000000000000000000000000000: n4356_o = 1'b0; + 63'b000000000000000000000001000000000000000000000000000000000000000: n4356_o = 1'b0; + 63'b000000000000000000000000100000000000000000000000000000000000000: n4356_o = 1'b0; + 63'b000000000000000000000000010000000000000000000000000000000000000: n4356_o = 1'b0; + 63'b000000000000000000000000001000000000000000000000000000000000000: n4356_o = 1'b0; + 63'b000000000000000000000000000100000000000000000000000000000000000: n4356_o = 1'b0; + 63'b000000000000000000000000000010000000000000000000000000000000000: n4356_o = 1'b0; + 63'b000000000000000000000000000001000000000000000000000000000000000: n4356_o = 1'b0; + 63'b000000000000000000000000000000100000000000000000000000000000000: n4356_o = 1'b0; + 63'b000000000000000000000000000000010000000000000000000000000000000: n4356_o = 1'b0; + 63'b000000000000000000000000000000001000000000000000000000000000000: n4356_o = 1'b0; + 63'b000000000000000000000000000000000100000000000000000000000000000: n4356_o = 1'b0; + 63'b000000000000000000000000000000000010000000000000000000000000000: n4356_o = 1'b0; + 63'b000000000000000000000000000000000001000000000000000000000000000: n4356_o = 1'b0; + 63'b000000000000000000000000000000000000100000000000000000000000000: n4356_o = 1'b0; + 63'b000000000000000000000000000000000000010000000000000000000000000: n4356_o = 1'b0; + 63'b000000000000000000000000000000000000001000000000000000000000000: n4356_o = 1'b0; + 63'b000000000000000000000000000000000000000100000000000000000000000: n4356_o = 1'b0; + 63'b000000000000000000000000000000000000000010000000000000000000000: n4356_o = 1'b0; + 63'b000000000000000000000000000000000000000001000000000000000000000: n4356_o = 1'b0; + 63'b000000000000000000000000000000000000000000100000000000000000000: n4356_o = 1'b0; + 63'b000000000000000000000000000000000000000000010000000000000000000: n4356_o = 1'b0; + 63'b000000000000000000000000000000000000000000001000000000000000000: n4356_o = 1'b0; + 63'b000000000000000000000000000000000000000000000100000000000000000: n4356_o = 1'b0; + 63'b000000000000000000000000000000000000000000000010000000000000000: n4356_o = 1'b0; + 63'b000000000000000000000000000000000000000000000001000000000000000: n4356_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000100000000000000: n4356_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000010000000000000: n4356_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000001000000000000: n4356_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000100000000000: n4356_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000010000000000: n4356_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000001000000000: n4356_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000100000000: n4356_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000010000000: n4356_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000001000000: n4356_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000100000: n4356_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000010000: n4356_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000001000: n4356_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000000100: n4356_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000000010: n4356_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000000001: n4356_o = 1'b0; + default: n4356_o = 1'b0; + endcase + /* decoder.vhd:635:5 */ + always @* + case (n4151_o) + 63'b100000000000000000000000000000000000000000000000000000000000000: n4359_o = 1'b0; + 63'b010000000000000000000000000000000000000000000000000000000000000: n4359_o = 1'b0; + 63'b001000000000000000000000000000000000000000000000000000000000000: n4359_o = 1'b0; + 63'b000100000000000000000000000000000000000000000000000000000000000: n4359_o = 1'b0; + 63'b000010000000000000000000000000000000000000000000000000000000000: n4359_o = 1'b0; + 63'b000001000000000000000000000000000000000000000000000000000000000: n4359_o = 1'b0; + 63'b000000100000000000000000000000000000000000000000000000000000000: n4359_o = 1'b0; + 63'b000000010000000000000000000000000000000000000000000000000000000: n4359_o = 1'b0; + 63'b000000001000000000000000000000000000000000000000000000000000000: n4359_o = 1'b0; + 63'b000000000100000000000000000000000000000000000000000000000000000: n4359_o = 1'b0; + 63'b000000000010000000000000000000000000000000000000000000000000000: n4359_o = 1'b0; + 63'b000000000001000000000000000000000000000000000000000000000000000: n4359_o = 1'b0; + 63'b000000000000100000000000000000000000000000000000000000000000000: n4359_o = 1'b0; + 63'b000000000000010000000000000000000000000000000000000000000000000: n4359_o = 1'b0; + 63'b000000000000001000000000000000000000000000000000000000000000000: n4359_o = 1'b0; + 63'b000000000000000100000000000000000000000000000000000000000000000: n4359_o = 1'b0; + 63'b000000000000000010000000000000000000000000000000000000000000000: n4359_o = 1'b0; + 63'b000000000000000001000000000000000000000000000000000000000000000: n4359_o = 1'b0; + 63'b000000000000000000100000000000000000000000000000000000000000000: n4359_o = 1'b0; + 63'b000000000000000000010000000000000000000000000000000000000000000: n4359_o = 1'b0; + 63'b000000000000000000001000000000000000000000000000000000000000000: n4359_o = 1'b0; + 63'b000000000000000000000100000000000000000000000000000000000000000: n4359_o = 1'b0; + 63'b000000000000000000000010000000000000000000000000000000000000000: n4359_o = 1'b0; + 63'b000000000000000000000001000000000000000000000000000000000000000: n4359_o = 1'b0; + 63'b000000000000000000000000100000000000000000000000000000000000000: n4359_o = 1'b0; + 63'b000000000000000000000000010000000000000000000000000000000000000: n4359_o = 1'b0; + 63'b000000000000000000000000001000000000000000000000000000000000000: n4359_o = 1'b0; + 63'b000000000000000000000000000100000000000000000000000000000000000: n4359_o = 1'b0; + 63'b000000000000000000000000000010000000000000000000000000000000000: n4359_o = 1'b0; + 63'b000000000000000000000000000001000000000000000000000000000000000: n4359_o = 1'b0; + 63'b000000000000000000000000000000100000000000000000000000000000000: n4359_o = 1'b0; + 63'b000000000000000000000000000000010000000000000000000000000000000: n4359_o = 1'b0; + 63'b000000000000000000000000000000001000000000000000000000000000000: n4359_o = 1'b0; + 63'b000000000000000000000000000000000100000000000000000000000000000: n4359_o = 1'b0; + 63'b000000000000000000000000000000000010000000000000000000000000000: n4359_o = 1'b0; + 63'b000000000000000000000000000000000001000000000000000000000000000: n4359_o = 1'b0; + 63'b000000000000000000000000000000000000100000000000000000000000000: n4359_o = 1'b0; + 63'b000000000000000000000000000000000000010000000000000000000000000: n4359_o = 1'b0; + 63'b000000000000000000000000000000000000001000000000000000000000000: n4359_o = 1'b0; + 63'b000000000000000000000000000000000000000100000000000000000000000: n4359_o = 1'b0; + 63'b000000000000000000000000000000000000000010000000000000000000000: n4359_o = 1'b0; + 63'b000000000000000000000000000000000000000001000000000000000000000: n4359_o = 1'b0; + 63'b000000000000000000000000000000000000000000100000000000000000000: n4359_o = 1'b0; + 63'b000000000000000000000000000000000000000000010000000000000000000: n4359_o = 1'b0; + 63'b000000000000000000000000000000000000000000001000000000000000000: n4359_o = 1'b0; + 63'b000000000000000000000000000000000000000000000100000000000000000: n4359_o = 1'b0; + 63'b000000000000000000000000000000000000000000000010000000000000000: n4359_o = 1'b0; + 63'b000000000000000000000000000000000000000000000001000000000000000: n4359_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000100000000000000: n4359_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000010000000000000: n4359_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000001000000000000: n4359_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000100000000000: n4359_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000010000000000: n4359_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000001000000000: n4359_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000100000000: n4359_o = n2499_o; + 63'b000000000000000000000000000000000000000000000000000000010000000: n4359_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000001000000: n4359_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000100000: n4359_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000010000: n4359_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000001000: n4359_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000000100: n4359_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000000010: n4359_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000000001: n4359_o = 1'b0; + default: n4359_o = 1'b0; + endcase + /* decoder.vhd:635:5 */ + always @* + case (n4151_o) + 63'b100000000000000000000000000000000000000000000000000000000000000: n4362_o = 1'b0; + 63'b010000000000000000000000000000000000000000000000000000000000000: n4362_o = 1'b0; + 63'b001000000000000000000000000000000000000000000000000000000000000: n4362_o = 1'b0; + 63'b000100000000000000000000000000000000000000000000000000000000000: n4362_o = 1'b0; + 63'b000010000000000000000000000000000000000000000000000000000000000: n4362_o = 1'b0; + 63'b000001000000000000000000000000000000000000000000000000000000000: n4362_o = 1'b0; + 63'b000000100000000000000000000000000000000000000000000000000000000: n4362_o = 1'b0; + 63'b000000010000000000000000000000000000000000000000000000000000000: n4362_o = 1'b0; + 63'b000000001000000000000000000000000000000000000000000000000000000: n4362_o = 1'b0; + 63'b000000000100000000000000000000000000000000000000000000000000000: n4362_o = 1'b0; + 63'b000000000010000000000000000000000000000000000000000000000000000: n4362_o = 1'b0; + 63'b000000000001000000000000000000000000000000000000000000000000000: n4362_o = 1'b0; + 63'b000000000000100000000000000000000000000000000000000000000000000: n4362_o = 1'b0; + 63'b000000000000010000000000000000000000000000000000000000000000000: n4362_o = 1'b0; + 63'b000000000000001000000000000000000000000000000000000000000000000: n4362_o = 1'b0; + 63'b000000000000000100000000000000000000000000000000000000000000000: n4362_o = 1'b0; + 63'b000000000000000010000000000000000000000000000000000000000000000: n4362_o = 1'b0; + 63'b000000000000000001000000000000000000000000000000000000000000000: n4362_o = 1'b0; + 63'b000000000000000000100000000000000000000000000000000000000000000: n4362_o = 1'b0; + 63'b000000000000000000010000000000000000000000000000000000000000000: n4362_o = 1'b0; + 63'b000000000000000000001000000000000000000000000000000000000000000: n4362_o = 1'b0; + 63'b000000000000000000000100000000000000000000000000000000000000000: n4362_o = 1'b0; + 63'b000000000000000000000010000000000000000000000000000000000000000: n4362_o = 1'b0; + 63'b000000000000000000000001000000000000000000000000000000000000000: n4362_o = 1'b0; + 63'b000000000000000000000000100000000000000000000000000000000000000: n4362_o = 1'b0; + 63'b000000000000000000000000010000000000000000000000000000000000000: n4362_o = 1'b0; + 63'b000000000000000000000000001000000000000000000000000000000000000: n4362_o = 1'b0; + 63'b000000000000000000000000000100000000000000000000000000000000000: n4362_o = 1'b0; + 63'b000000000000000000000000000010000000000000000000000000000000000: n4362_o = 1'b0; + 63'b000000000000000000000000000001000000000000000000000000000000000: n4362_o = 1'b0; + 63'b000000000000000000000000000000100000000000000000000000000000000: n4362_o = 1'b0; + 63'b000000000000000000000000000000010000000000000000000000000000000: n4362_o = 1'b0; + 63'b000000000000000000000000000000001000000000000000000000000000000: n4362_o = 1'b0; + 63'b000000000000000000000000000000000100000000000000000000000000000: n4362_o = 1'b0; + 63'b000000000000000000000000000000000010000000000000000000000000000: n4362_o = 1'b0; + 63'b000000000000000000000000000000000001000000000000000000000000000: n4362_o = 1'b0; + 63'b000000000000000000000000000000000000100000000000000000000000000: n4362_o = 1'b0; + 63'b000000000000000000000000000000000000010000000000000000000000000: n4362_o = 1'b0; + 63'b000000000000000000000000000000000000001000000000000000000000000: n4362_o = 1'b0; + 63'b000000000000000000000000000000000000000100000000000000000000000: n4362_o = 1'b0; + 63'b000000000000000000000000000000000000000010000000000000000000000: n4362_o = 1'b0; + 63'b000000000000000000000000000000000000000001000000000000000000000: n4362_o = 1'b0; + 63'b000000000000000000000000000000000000000000100000000000000000000: n4362_o = 1'b0; + 63'b000000000000000000000000000000000000000000010000000000000000000: n4362_o = 1'b0; + 63'b000000000000000000000000000000000000000000001000000000000000000: n4362_o = 1'b0; + 63'b000000000000000000000000000000000000000000000100000000000000000: n4362_o = 1'b0; + 63'b000000000000000000000000000000000000000000000010000000000000000: n4362_o = 1'b0; + 63'b000000000000000000000000000000000000000000000001000000000000000: n4362_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000100000000000000: n4362_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000010000000000000: n4362_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000001000000000000: n4362_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000100000000000: n4362_o = n2543_o; + 63'b000000000000000000000000000000000000000000000000000010000000000: n4362_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000001000000000: n4362_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000100000000: n4362_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000010000000: n4362_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000001000000: n4362_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000100000: n4362_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000010000: n4362_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000001000: n4362_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000000100: n4362_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000000010: n4362_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000000001: n4362_o = 1'b0; + default: n4362_o = 1'b0; + endcase + /* decoder.vhd:635:5 */ + always @* + case (n4151_o) + 63'b100000000000000000000000000000000000000000000000000000000000000: n4365_o = 1'b0; + 63'b010000000000000000000000000000000000000000000000000000000000000: n4365_o = 1'b0; + 63'b001000000000000000000000000000000000000000000000000000000000000: n4365_o = 1'b0; + 63'b000100000000000000000000000000000000000000000000000000000000000: n4365_o = 1'b0; + 63'b000010000000000000000000000000000000000000000000000000000000000: n4365_o = 1'b0; + 63'b000001000000000000000000000000000000000000000000000000000000000: n4365_o = 1'b0; + 63'b000000100000000000000000000000000000000000000000000000000000000: n4365_o = 1'b0; + 63'b000000010000000000000000000000000000000000000000000000000000000: n4365_o = n3968_o; + 63'b000000001000000000000000000000000000000000000000000000000000000: n4365_o = 1'b0; + 63'b000000000100000000000000000000000000000000000000000000000000000: n4365_o = 1'b0; + 63'b000000000010000000000000000000000000000000000000000000000000000: n4365_o = 1'b0; + 63'b000000000001000000000000000000000000000000000000000000000000000: n4365_o = 1'b0; + 63'b000000000000100000000000000000000000000000000000000000000000000: n4365_o = 1'b0; + 63'b000000000000010000000000000000000000000000000000000000000000000: n4365_o = 1'b0; + 63'b000000000000001000000000000000000000000000000000000000000000000: n4365_o = 1'b0; + 63'b000000000000000100000000000000000000000000000000000000000000000: n4365_o = 1'b0; + 63'b000000000000000010000000000000000000000000000000000000000000000: n4365_o = 1'b0; + 63'b000000000000000001000000000000000000000000000000000000000000000: n4365_o = 1'b0; + 63'b000000000000000000100000000000000000000000000000000000000000000: n4365_o = 1'b0; + 63'b000000000000000000010000000000000000000000000000000000000000000: n4365_o = 1'b0; + 63'b000000000000000000001000000000000000000000000000000000000000000: n4365_o = 1'b0; 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+ 63'b000000000000000000000000000000000000000000000000000000000100000: n4365_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000010000: n4365_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000001000: n4365_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000000100: n4365_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000000010: n4365_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000000001: n4365_o = 1'b0; + default: n4365_o = 1'b0; + endcase + /* decoder.vhd:635:5 */ + always @* + case (n4151_o) + 63'b100000000000000000000000000000000000000000000000000000000000000: n4368_o = 1'b0; + 63'b010000000000000000000000000000000000000000000000000000000000000: n4368_o = 1'b0; + 63'b001000000000000000000000000000000000000000000000000000000000000: n4368_o = 1'b0; + 63'b000100000000000000000000000000000000000000000000000000000000000: n4368_o = 1'b0; + 63'b000010000000000000000000000000000000000000000000000000000000000: n4368_o = 1'b0; + 63'b000001000000000000000000000000000000000000000000000000000000000: n4368_o = 1'b0; + 63'b000000100000000000000000000000000000000000000000000000000000000: n4368_o = 1'b0; + 63'b000000010000000000000000000000000000000000000000000000000000000: n4368_o = n3970_o; + 63'b000000001000000000000000000000000000000000000000000000000000000: n4368_o = 1'b0; + 63'b000000000100000000000000000000000000000000000000000000000000000: n4368_o = 1'b0; + 63'b000000000010000000000000000000000000000000000000000000000000000: n4368_o = 1'b0; + 63'b000000000001000000000000000000000000000000000000000000000000000: n4368_o = 1'b0; + 63'b000000000000100000000000000000000000000000000000000000000000000: n4368_o = 1'b0; + 63'b000000000000010000000000000000000000000000000000000000000000000: n4368_o = 1'b0; + 63'b000000000000001000000000000000000000000000000000000000000000000: n4368_o = 1'b0; + 63'b000000000000000100000000000000000000000000000000000000000000000: n4368_o = 1'b0; + 63'b000000000000000010000000000000000000000000000000000000000000000: n4368_o = 1'b0; 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+ 63'b000000000000000000000000000000000000000000000000000001000000000: n4368_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000100000000: n4368_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000010000000: n4368_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000001000000: n4368_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000100000: n4368_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000010000: n4368_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000001000: n4368_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000000100: n4368_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000000010: n4368_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000000001: n4368_o = 1'b0; + default: n4368_o = 1'b0; + endcase + /* decoder.vhd:635:5 */ + always @* + case (n4151_o) + 63'b100000000000000000000000000000000000000000000000000000000000000: n4371_o = 1'b0; + 63'b010000000000000000000000000000000000000000000000000000000000000: n4371_o = 1'b0; + 63'b001000000000000000000000000000000000000000000000000000000000000: n4371_o = 1'b0; + 63'b000100000000000000000000000000000000000000000000000000000000000: n4371_o = 1'b0; + 63'b000010000000000000000000000000000000000000000000000000000000000: n4371_o = 1'b0; + 63'b000001000000000000000000000000000000000000000000000000000000000: n4371_o = 1'b0; + 63'b000000100000000000000000000000000000000000000000000000000000000: n4371_o = 1'b0; + 63'b000000010000000000000000000000000000000000000000000000000000000: n4371_o = 1'b0; + 63'b000000001000000000000000000000000000000000000000000000000000000: n4371_o = 1'b0; + 63'b000000000100000000000000000000000000000000000000000000000000000: n4371_o = 1'b0; + 63'b000000000010000000000000000000000000000000000000000000000000000: n4371_o = 1'b0; + 63'b000000000001000000000000000000000000000000000000000000000000000: n4371_o = 1'b0; + 63'b000000000000100000000000000000000000000000000000000000000000000: n4371_o = 1'b0; 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+ 63'b000000000000000000000000000000000000000000000000010000000000000: n4371_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000001000000000000: n4371_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000100000000000: n4371_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000010000000000: n4371_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000001000000000: n4371_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000100000000: n4371_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000010000000: n4371_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000001000000: n4371_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000100000: n4371_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000010000: n4371_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000001000: n4371_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000000100: n4371_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000000010: n4371_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000000001: n4371_o = 1'b0; + default: n4371_o = 1'b0; + endcase + /* decoder.vhd:635:5 */ + always @* + case (n4151_o) + 63'b100000000000000000000000000000000000000000000000000000000000000: n4373_o = n2034_o; + 63'b010000000000000000000000000000000000000000000000000000000000000: n4373_o = n2034_o; + 63'b001000000000000000000000000000000000000000000000000000000000000: n4373_o = n2034_o; + 63'b000100000000000000000000000000000000000000000000000000000000000: n4373_o = n2034_o; + 63'b000010000000000000000000000000000000000000000000000000000000000: n4373_o = n2034_o; + 63'b000001000000000000000000000000000000000000000000000000000000000: n4373_o = n2034_o; + 63'b000000100000000000000000000000000000000000000000000000000000000: n4373_o = n2034_o; + 63'b000000010000000000000000000000000000000000000000000000000000000: n4373_o = n2034_o; + 63'b000000001000000000000000000000000000000000000000000000000000000: n4373_o = n2034_o; + 63'b000000000100000000000000000000000000000000000000000000000000000: n4373_o = n2034_o; + 63'b000000000010000000000000000000000000000000000000000000000000000: n4373_o = n2034_o; + 63'b000000000001000000000000000000000000000000000000000000000000000: n4373_o = n2034_o; + 63'b000000000000100000000000000000000000000000000000000000000000000: n4373_o = n2034_o; + 63'b000000000000010000000000000000000000000000000000000000000000000: n4373_o = n2034_o; + 63'b000000000000001000000000000000000000000000000000000000000000000: n4373_o = n2034_o; + 63'b000000000000000100000000000000000000000000000000000000000000000: n4373_o = n2034_o; + 63'b000000000000000010000000000000000000000000000000000000000000000: n4373_o = n2034_o; + 63'b000000000000000001000000000000000000000000000000000000000000000: n4373_o = n2034_o; + 63'b000000000000000000100000000000000000000000000000000000000000000: n4373_o = n2034_o; + 63'b000000000000000000010000000000000000000000000000000000000000000: n4373_o = n3487_o; + 63'b000000000000000000001000000000000000000000000000000000000000000: n4373_o = n3422_o; + 63'b000000000000000000000100000000000000000000000000000000000000000: n4373_o = n2034_o; + 63'b000000000000000000000010000000000000000000000000000000000000000: n4373_o = n2034_o; + 63'b000000000000000000000001000000000000000000000000000000000000000: n4373_o = n2034_o; + 63'b000000000000000000000000100000000000000000000000000000000000000: n4373_o = n2034_o; + 63'b000000000000000000000000010000000000000000000000000000000000000: n4373_o = n2034_o; + 63'b000000000000000000000000001000000000000000000000000000000000000: n4373_o = n2034_o; + 63'b000000000000000000000000000100000000000000000000000000000000000: n4373_o = n2034_o; + 63'b000000000000000000000000000010000000000000000000000000000000000: n4373_o = n2034_o; + 63'b000000000000000000000000000001000000000000000000000000000000000: n4373_o = n2034_o; + 63'b000000000000000000000000000000100000000000000000000000000000000: n4373_o = n2034_o; + 63'b000000000000000000000000000000010000000000000000000000000000000: n4373_o = n2034_o; + 63'b000000000000000000000000000000001000000000000000000000000000000: n4373_o = n2034_o; + 63'b000000000000000000000000000000000100000000000000000000000000000: n4373_o = n2034_o; + 63'b000000000000000000000000000000000010000000000000000000000000000: n4373_o = n2034_o; + 63'b000000000000000000000000000000000001000000000000000000000000000: n4373_o = n2034_o; + 63'b000000000000000000000000000000000000100000000000000000000000000: n4373_o = n2970_o; + 63'b000000000000000000000000000000000000010000000000000000000000000: n4373_o = n2034_o; + 63'b000000000000000000000000000000000000001000000000000000000000000: n4373_o = n2034_o; + 63'b000000000000000000000000000000000000000100000000000000000000000: n4373_o = n2034_o; + 63'b000000000000000000000000000000000000000010000000000000000000000: n4373_o = n2034_o; + 63'b000000000000000000000000000000000000000001000000000000000000000: n4373_o = n2034_o; + 63'b000000000000000000000000000000000000000000100000000000000000000: n4373_o = n2034_o; + 63'b000000000000000000000000000000000000000000010000000000000000000: n4373_o = n2034_o; + 63'b000000000000000000000000000000000000000000001000000000000000000: n4373_o = n2034_o; + 63'b000000000000000000000000000000000000000000000100000000000000000: n4373_o = n2034_o; + 63'b000000000000000000000000000000000000000000000010000000000000000: n4373_o = n2034_o; + 63'b000000000000000000000000000000000000000000000001000000000000000: n4373_o = n2034_o; + 63'b000000000000000000000000000000000000000000000000100000000000000: n4373_o = n2034_o; + 63'b000000000000000000000000000000000000000000000000010000000000000: n4373_o = n2034_o; + 63'b000000000000000000000000000000000000000000000000001000000000000: n4373_o = n2034_o; + 63'b000000000000000000000000000000000000000000000000000100000000000: n4373_o = n2034_o; + 63'b000000000000000000000000000000000000000000000000000010000000000: n4373_o = n2034_o; + 63'b000000000000000000000000000000000000000000000000000001000000000: n4373_o = n2034_o; + 63'b000000000000000000000000000000000000000000000000000000100000000: n4373_o = n2034_o; + 63'b000000000000000000000000000000000000000000000000000000010000000: n4373_o = n2034_o; + 63'b000000000000000000000000000000000000000000000000000000001000000: n4373_o = n2034_o; + 63'b000000000000000000000000000000000000000000000000000000000100000: n4373_o = n2458_o; + 63'b000000000000000000000000000000000000000000000000000000000010000: n4373_o = n2034_o; + 63'b000000000000000000000000000000000000000000000000000000000001000: n4373_o = n2034_o; + 63'b000000000000000000000000000000000000000000000000000000000000100: n4373_o = n2034_o; + 63'b000000000000000000000000000000000000000000000000000000000000010: n4373_o = n2034_o; + 63'b000000000000000000000000000000000000000000000000000000000000001: n4373_o = n2034_o; + default: n4373_o = n2034_o; + endcase + /* decoder.vhd:635:5 */ + always @* + case (n4151_o) + 63'b100000000000000000000000000000000000000000000000000000000000000: n4374_o = n2038_o; + 63'b010000000000000000000000000000000000000000000000000000000000000: n4374_o = n2038_o; + 63'b001000000000000000000000000000000000000000000000000000000000000: n4374_o = n2038_o; + 63'b000100000000000000000000000000000000000000000000000000000000000: n4374_o = n2038_o; + 63'b000010000000000000000000000000000000000000000000000000000000000: n4374_o = n2038_o; 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+ 63'b000000000000000000000000000001000000000000000000000000000000000: n4374_o = n2038_o; + 63'b000000000000000000000000000000100000000000000000000000000000000: n4374_o = n2038_o; + 63'b000000000000000000000000000000010000000000000000000000000000000: n4374_o = n2038_o; + 63'b000000000000000000000000000000001000000000000000000000000000000: n4374_o = n2038_o; + 63'b000000000000000000000000000000000100000000000000000000000000000: n4374_o = n2038_o; + 63'b000000000000000000000000000000000010000000000000000000000000000: n4374_o = n2038_o; + 63'b000000000000000000000000000000000001000000000000000000000000000: n4374_o = n2038_o; + 63'b000000000000000000000000000000000000100000000000000000000000000: n4374_o = n2971_o; + 63'b000000000000000000000000000000000000010000000000000000000000000: n4374_o = n2038_o; + 63'b000000000000000000000000000000000000001000000000000000000000000: n4374_o = n2038_o; + 63'b000000000000000000000000000000000000000100000000000000000000000: n4374_o = n2038_o; + 63'b000000000000000000000000000000000000000010000000000000000000000: n4374_o = n2038_o; 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+ 63'b000000000000000000000000000000000000000000000000000001000000000: n4374_o = n2038_o; + 63'b000000000000000000000000000000000000000000000000000000100000000: n4374_o = n2038_o; + 63'b000000000000000000000000000000000000000000000000000000010000000: n4374_o = n2038_o; + 63'b000000000000000000000000000000000000000000000000000000001000000: n4374_o = n2038_o; + 63'b000000000000000000000000000000000000000000000000000000000100000: n4374_o = n2459_o; + 63'b000000000000000000000000000000000000000000000000000000000010000: n4374_o = n2038_o; + 63'b000000000000000000000000000000000000000000000000000000000001000: n4374_o = n2038_o; + 63'b000000000000000000000000000000000000000000000000000000000000100: n4374_o = n2038_o; + 63'b000000000000000000000000000000000000000000000000000000000000010: n4374_o = n2038_o; + 63'b000000000000000000000000000000000000000000000000000000000000001: n4374_o = n2038_o; + default: n4374_o = n2038_o; + endcase + /* decoder.vhd:635:5 */ + always @* + case (n4151_o) + 63'b100000000000000000000000000000000000000000000000000000000000000: n4376_o = 1'b0; + 63'b010000000000000000000000000000000000000000000000000000000000000: n4376_o = 1'b0; + 63'b001000000000000000000000000000000000000000000000000000000000000: n4376_o = 1'b0; + 63'b000100000000000000000000000000000000000000000000000000000000000: n4376_o = 1'b0; + 63'b000010000000000000000000000000000000000000000000000000000000000: n4376_o = 1'b0; + 63'b000001000000000000000000000000000000000000000000000000000000000: n4376_o = 1'b0; + 63'b000000100000000000000000000000000000000000000000000000000000000: n4376_o = 1'b0; + 63'b000000010000000000000000000000000000000000000000000000000000000: n4376_o = 1'b0; + 63'b000000001000000000000000000000000000000000000000000000000000000: n4376_o = 1'b0; + 63'b000000000100000000000000000000000000000000000000000000000000000: n4376_o = 1'b0; + 63'b000000000010000000000000000000000000000000000000000000000000000: n4376_o = 1'b0; + 63'b000000000001000000000000000000000000000000000000000000000000000: n4376_o = 1'b0; + 63'b000000000000100000000000000000000000000000000000000000000000000: n4376_o = 1'b0; + 63'b000000000000010000000000000000000000000000000000000000000000000: n4376_o = n3780_o; + 63'b000000000000001000000000000000000000000000000000000000000000000: n4376_o = 1'b0; + 63'b000000000000000100000000000000000000000000000000000000000000000: n4376_o = 1'b0; + 63'b000000000000000010000000000000000000000000000000000000000000000: n4376_o = 1'b0; + 63'b000000000000000001000000000000000000000000000000000000000000000: n4376_o = n3583_o; + 63'b000000000000000000100000000000000000000000000000000000000000000: n4376_o = 1'b0; + 63'b000000000000000000010000000000000000000000000000000000000000000: n4376_o = 1'b0; + 63'b000000000000000000001000000000000000000000000000000000000000000: n4376_o = 1'b0; + 63'b000000000000000000000100000000000000000000000000000000000000000: n4376_o = 1'b0; + 63'b000000000000000000000010000000000000000000000000000000000000000: n4376_o = 1'b0; + 63'b000000000000000000000001000000000000000000000000000000000000000: n4376_o = 1'b0; + 63'b000000000000000000000000100000000000000000000000000000000000000: n4376_o = 1'b0; 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+ 63'b000000000000000000000000000000000000010000000000000000000000000: n4376_o = 1'b0; + 63'b000000000000000000000000000000000000001000000000000000000000000: n4376_o = 1'b0; + 63'b000000000000000000000000000000000000000100000000000000000000000: n4376_o = 1'b0; + 63'b000000000000000000000000000000000000000010000000000000000000000: n4376_o = 1'b0; + 63'b000000000000000000000000000000000000000001000000000000000000000: n4376_o = n2783_o; + 63'b000000000000000000000000000000000000000000100000000000000000000: n4376_o = n2772_o; + 63'b000000000000000000000000000000000000000000010000000000000000000: n4376_o = 1'b0; + 63'b000000000000000000000000000000000000000000001000000000000000000: n4376_o = 1'b0; + 63'b000000000000000000000000000000000000000000000100000000000000000: n4376_o = 1'b0; + 63'b000000000000000000000000000000000000000000000010000000000000000: n4376_o = 1'b0; + 63'b000000000000000000000000000000000000000000000001000000000000000: n4376_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000100000000000000: n4376_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000010000000000000: n4376_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000001000000000000: n4376_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000100000000000: n4376_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000010000000000: n4376_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000001000000000: n4376_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000100000000: n4376_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000010000000: n4376_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000001000000: n4376_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000100000: n4376_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000010000: n4376_o = n2345_o; + 63'b000000000000000000000000000000000000000000000000000000000001000: n4376_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000000100: n4376_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000000010: n4376_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000000001: n4376_o = 1'b0; + default: n4376_o = 1'b0; + endcase + /* decoder.vhd:635:5 */ + always @* + case (n4151_o) + 63'b100000000000000000000000000000000000000000000000000000000000000: n4379_o = 1'b0; + 63'b010000000000000000000000000000000000000000000000000000000000000: n4379_o = 1'b0; + 63'b001000000000000000000000000000000000000000000000000000000000000: n4379_o = n4068_o; + 63'b000100000000000000000000000000000000000000000000000000000000000: n4379_o = 1'b0; + 63'b000010000000000000000000000000000000000000000000000000000000000: n4379_o = 1'b0; + 63'b000001000000000000000000000000000000000000000000000000000000000: n4379_o = 1'b0; + 63'b000000100000000000000000000000000000000000000000000000000000000: n4379_o = 1'b0; + 63'b000000010000000000000000000000000000000000000000000000000000000: n4379_o = 1'b0; + 63'b000000001000000000000000000000000000000000000000000000000000000: n4379_o = 1'b0; + 63'b000000000100000000000000000000000000000000000000000000000000000: n4379_o = 1'b0; + 63'b000000000010000000000000000000000000000000000000000000000000000: n4379_o = 1'b0; + 63'b000000000001000000000000000000000000000000000000000000000000000: n4379_o = 1'b0; + 63'b000000000000100000000000000000000000000000000000000000000000000: n4379_o = 1'b0; + 63'b000000000000010000000000000000000000000000000000000000000000000: n4379_o = 1'b0; + 63'b000000000000001000000000000000000000000000000000000000000000000: n4379_o = 1'b0; + 63'b000000000000000100000000000000000000000000000000000000000000000: n4379_o = 1'b0; + 63'b000000000000000010000000000000000000000000000000000000000000000: n4379_o = 1'b0; + 63'b000000000000000001000000000000000000000000000000000000000000000: n4379_o = 1'b0; + 63'b000000000000000000100000000000000000000000000000000000000000000: n4379_o = 1'b0; + 63'b000000000000000000010000000000000000000000000000000000000000000: n4379_o = 1'b0; + 63'b000000000000000000001000000000000000000000000000000000000000000: n4379_o = 1'b0; + 63'b000000000000000000000100000000000000000000000000000000000000000: n4379_o = 1'b0; + 63'b000000000000000000000010000000000000000000000000000000000000000: n4379_o = 1'b0; + 63'b000000000000000000000001000000000000000000000000000000000000000: n4379_o = n3321_o; + 63'b000000000000000000000000100000000000000000000000000000000000000: n4379_o = n3287_o; + 63'b000000000000000000000000010000000000000000000000000000000000000: n4379_o = 1'b0; + 63'b000000000000000000000000001000000000000000000000000000000000000: n4379_o = 1'b0; + 63'b000000000000000000000000000100000000000000000000000000000000000: n4379_o = 1'b0; + 63'b000000000000000000000000000010000000000000000000000000000000000: n4379_o = 1'b0; + 63'b000000000000000000000000000001000000000000000000000000000000000: n4379_o = 1'b0; + 63'b000000000000000000000000000000100000000000000000000000000000000: n4379_o = 1'b0; + 63'b000000000000000000000000000000010000000000000000000000000000000: n4379_o = 1'b0; + 63'b000000000000000000000000000000001000000000000000000000000000000: n4379_o = 1'b0; + 63'b000000000000000000000000000000000100000000000000000000000000000: n4379_o = 1'b0; + 63'b000000000000000000000000000000000010000000000000000000000000000: n4379_o = 1'b0; + 63'b000000000000000000000000000000000001000000000000000000000000000: n4379_o = 1'b0; + 63'b000000000000000000000000000000000000100000000000000000000000000: n4379_o = 1'b0; + 63'b000000000000000000000000000000000000010000000000000000000000000: n4379_o = 1'b0; + 63'b000000000000000000000000000000000000001000000000000000000000000: n4379_o = 1'b0; + 63'b000000000000000000000000000000000000000100000000000000000000000: n4379_o = 1'b0; + 63'b000000000000000000000000000000000000000010000000000000000000000: n4379_o = n2844_o; + 63'b000000000000000000000000000000000000000001000000000000000000000: n4379_o = 1'b0; + 63'b000000000000000000000000000000000000000000100000000000000000000: n4379_o = 1'b0; + 63'b000000000000000000000000000000000000000000010000000000000000000: n4379_o = 1'b0; + 63'b000000000000000000000000000000000000000000001000000000000000000: n4379_o = 1'b0; + 63'b000000000000000000000000000000000000000000000100000000000000000: n4379_o = 1'b0; + 63'b000000000000000000000000000000000000000000000010000000000000000: n4379_o = n2719_o; + 63'b000000000000000000000000000000000000000000000001000000000000000: n4379_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000100000000000000: n4379_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000010000000000000: n4379_o = n2625_o; + 63'b000000000000000000000000000000000000000000000000001000000000000: n4379_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000100000000000: n4379_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000010000000000: n4379_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000001000000000: n4379_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000100000000: n4379_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000010000000: n4379_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000001000000: n4379_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000100000: n4379_o = n2461_o; + 63'b000000000000000000000000000000000000000000000000000000000010000: n4379_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000001000: n4379_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000000100: n4379_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000000010: n4379_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000000001: n4379_o = 1'b0; + default: n4379_o = 1'b0; + endcase + /* decoder.vhd:635:5 */ + always @* + case (n4151_o) + 63'b100000000000000000000000000000000000000000000000000000000000000: n4382_o = 1'b0; + 63'b010000000000000000000000000000000000000000000000000000000000000: n4382_o = 1'b0; + 63'b001000000000000000000000000000000000000000000000000000000000000: n4382_o = 1'b0; + 63'b000100000000000000000000000000000000000000000000000000000000000: n4382_o = 1'b0; + 63'b000010000000000000000000000000000000000000000000000000000000000: n4382_o = 1'b0; + 63'b000001000000000000000000000000000000000000000000000000000000000: n4382_o = 1'b0; + 63'b000000100000000000000000000000000000000000000000000000000000000: n4382_o = 1'b0; + 63'b000000010000000000000000000000000000000000000000000000000000000: n4382_o = 1'b0; + 63'b000000001000000000000000000000000000000000000000000000000000000: n4382_o = 1'b0; + 63'b000000000100000000000000000000000000000000000000000000000000000: n4382_o = 1'b0; + 63'b000000000010000000000000000000000000000000000000000000000000000: n4382_o = 1'b0; + 63'b000000000001000000000000000000000000000000000000000000000000000: n4382_o = 1'b0; + 63'b000000000000100000000000000000000000000000000000000000000000000: n4382_o = 1'b0; + 63'b000000000000010000000000000000000000000000000000000000000000000: n4382_o = 1'b0; + 63'b000000000000001000000000000000000000000000000000000000000000000: n4382_o = 1'b0; + 63'b000000000000000100000000000000000000000000000000000000000000000: n4382_o = 1'b0; + 63'b000000000000000010000000000000000000000000000000000000000000000: n4382_o = 1'b0; + 63'b000000000000000001000000000000000000000000000000000000000000000: n4382_o = 1'b0; + 63'b000000000000000000100000000000000000000000000000000000000000000: n4382_o = 1'b0; + 63'b000000000000000000010000000000000000000000000000000000000000000: n4382_o = n3489_o; + 63'b000000000000000000001000000000000000000000000000000000000000000: n4382_o = n3424_o; + 63'b000000000000000000000100000000000000000000000000000000000000000: n4382_o = 1'b0; + 63'b000000000000000000000010000000000000000000000000000000000000000: n4382_o = 1'b0; + 63'b000000000000000000000001000000000000000000000000000000000000000: n4382_o = 1'b0; + 63'b000000000000000000000000100000000000000000000000000000000000000: n4382_o = 1'b0; + 63'b000000000000000000000000010000000000000000000000000000000000000: n4382_o = 1'b0; + 63'b000000000000000000000000001000000000000000000000000000000000000: n4382_o = 1'b0; + 63'b000000000000000000000000000100000000000000000000000000000000000: n4382_o = 1'b0; + 63'b000000000000000000000000000010000000000000000000000000000000000: n4382_o = 1'b0; + 63'b000000000000000000000000000001000000000000000000000000000000000: n4382_o = 1'b0; + 63'b000000000000000000000000000000100000000000000000000000000000000: n4382_o = 1'b0; + 63'b000000000000000000000000000000010000000000000000000000000000000: n4382_o = 1'b0; + 63'b000000000000000000000000000000001000000000000000000000000000000: n4382_o = 1'b0; + 63'b000000000000000000000000000000000100000000000000000000000000000: n4382_o = 1'b0; + 63'b000000000000000000000000000000000010000000000000000000000000000: n4382_o = 1'b0; + 63'b000000000000000000000000000000000001000000000000000000000000000: n4382_o = 1'b0; + 63'b000000000000000000000000000000000000100000000000000000000000000: n4382_o = 1'b0; + 63'b000000000000000000000000000000000000010000000000000000000000000: n4382_o = 1'b0; + 63'b000000000000000000000000000000000000001000000000000000000000000: n4382_o = 1'b0; + 63'b000000000000000000000000000000000000000100000000000000000000000: n4382_o = 1'b0; + 63'b000000000000000000000000000000000000000010000000000000000000000: n4382_o = 1'b0; + 63'b000000000000000000000000000000000000000001000000000000000000000: n4382_o = 1'b0; + 63'b000000000000000000000000000000000000000000100000000000000000000: n4382_o = 1'b0; + 63'b000000000000000000000000000000000000000000010000000000000000000: n4382_o = 1'b0; + 63'b000000000000000000000000000000000000000000001000000000000000000: n4382_o = 1'b0; + 63'b000000000000000000000000000000000000000000000100000000000000000: n4382_o = 1'b0; + 63'b000000000000000000000000000000000000000000000010000000000000000: n4382_o = 1'b0; + 63'b000000000000000000000000000000000000000000000001000000000000000: n4382_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000100000000000000: n4382_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000010000000000000: n4382_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000001000000000000: n4382_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000100000000000: n4382_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000010000000000: n4382_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000001000000000: n4382_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000100000000: n4382_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000010000000: n4382_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000001000000: n4382_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000100000: n4382_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000010000: n4382_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000001000: n4382_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000000100: n4382_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000000010: n4382_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000000001: n4382_o = 1'b0; + default: n4382_o = 1'b0; + endcase + /* decoder.vhd:635:5 */ + always @* + case (n4151_o) + 63'b100000000000000000000000000000000000000000000000000000000000000: n4385_o = 1'b0; + 63'b010000000000000000000000000000000000000000000000000000000000000: n4385_o = 1'b0; + 63'b001000000000000000000000000000000000000000000000000000000000000: n4385_o = 1'b0; + 63'b000100000000000000000000000000000000000000000000000000000000000: n4385_o = 1'b0; + 63'b000010000000000000000000000000000000000000000000000000000000000: n4385_o = 1'b0; + 63'b000001000000000000000000000000000000000000000000000000000000000: n4385_o = 1'b0; + 63'b000000100000000000000000000000000000000000000000000000000000000: n4385_o = 1'b0; + 63'b000000010000000000000000000000000000000000000000000000000000000: n4385_o = 1'b0; + 63'b000000001000000000000000000000000000000000000000000000000000000: n4385_o = 1'b0; + 63'b000000000100000000000000000000000000000000000000000000000000000: n4385_o = 1'b0; + 63'b000000000010000000000000000000000000000000000000000000000000000: n4385_o = 1'b0; + 63'b000000000001000000000000000000000000000000000000000000000000000: n4385_o = 1'b0; + 63'b000000000000100000000000000000000000000000000000000000000000000: n4385_o = 1'b0; + 63'b000000000000010000000000000000000000000000000000000000000000000: n4385_o = 1'b0; + 63'b000000000000001000000000000000000000000000000000000000000000000: n4385_o = 1'b0; + 63'b000000000000000100000000000000000000000000000000000000000000000: n4385_o = 1'b0; + 63'b000000000000000010000000000000000000000000000000000000000000000: n4385_o = 1'b0; + 63'b000000000000000001000000000000000000000000000000000000000000000: n4385_o = n3586_o; + 63'b000000000000000000100000000000000000000000000000000000000000000: n4385_o = 1'b0; + 63'b000000000000000000010000000000000000000000000000000000000000000: n4385_o = 1'b0; + 63'b000000000000000000001000000000000000000000000000000000000000000: n4385_o = 1'b0; + 63'b000000000000000000000100000000000000000000000000000000000000000: n4385_o = 1'b0; + 63'b000000000000000000000010000000000000000000000000000000000000000: n4385_o = 1'b0; + 63'b000000000000000000000001000000000000000000000000000000000000000: n4385_o = 1'b0; + 63'b000000000000000000000000100000000000000000000000000000000000000: n4385_o = 1'b0; + 63'b000000000000000000000000010000000000000000000000000000000000000: n4385_o = 1'b0; + 63'b000000000000000000000000001000000000000000000000000000000000000: n4385_o = 1'b0; + 63'b000000000000000000000000000100000000000000000000000000000000000: n4385_o = 1'b0; + 63'b000000000000000000000000000010000000000000000000000000000000000: n4385_o = 1'b0; + 63'b000000000000000000000000000001000000000000000000000000000000000: n4385_o = 1'b0; + 63'b000000000000000000000000000000100000000000000000000000000000000: n4385_o = 1'b0; + 63'b000000000000000000000000000000010000000000000000000000000000000: n4385_o = 1'b0; + 63'b000000000000000000000000000000001000000000000000000000000000000: n4385_o = 1'b0; + 63'b000000000000000000000000000000000100000000000000000000000000000: n4385_o = 1'b0; + 63'b000000000000000000000000000000000010000000000000000000000000000: n4385_o = 1'b0; + 63'b000000000000000000000000000000000001000000000000000000000000000: n4385_o = 1'b0; + 63'b000000000000000000000000000000000000100000000000000000000000000: n4385_o = 1'b0; + 63'b000000000000000000000000000000000000010000000000000000000000000: n4385_o = 1'b0; + 63'b000000000000000000000000000000000000001000000000000000000000000: n4385_o = 1'b0; + 63'b000000000000000000000000000000000000000100000000000000000000000: n4385_o = 1'b0; + 63'b000000000000000000000000000000000000000010000000000000000000000: n4385_o = 1'b0; + 63'b000000000000000000000000000000000000000001000000000000000000000: n4385_o = 1'b0; + 63'b000000000000000000000000000000000000000000100000000000000000000: n4385_o = 1'b0; + 63'b000000000000000000000000000000000000000000010000000000000000000: n4385_o = 1'b0; + 63'b000000000000000000000000000000000000000000001000000000000000000: n4385_o = 1'b0; + 63'b000000000000000000000000000000000000000000000100000000000000000: n4385_o = 1'b0; + 63'b000000000000000000000000000000000000000000000010000000000000000: n4385_o = 1'b0; + 63'b000000000000000000000000000000000000000000000001000000000000000: n4385_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000100000000000000: n4385_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000010000000000000: n4385_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000001000000000000: n4385_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000100000000000: n4385_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000010000000000: n4385_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000001000000000: n4385_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000100000000: n4385_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000010000000: n4385_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000001000000: n4385_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000100000: n4385_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000010000: n4385_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000001000: n4385_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000000100: n4385_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000000010: n4385_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000000001: n4385_o = 1'b0; + default: n4385_o = 1'b0; + endcase + /* decoder.vhd:635:5 */ + always @* + case (n4151_o) + 63'b100000000000000000000000000000000000000000000000000000000000000: n4388_o = 1'b0; + 63'b010000000000000000000000000000000000000000000000000000000000000: n4388_o = 1'b0; + 63'b001000000000000000000000000000000000000000000000000000000000000: n4388_o = 1'b0; + 63'b000100000000000000000000000000000000000000000000000000000000000: n4388_o = 1'b0; + 63'b000010000000000000000000000000000000000000000000000000000000000: n4388_o = 1'b0; + 63'b000001000000000000000000000000000000000000000000000000000000000: n4388_o = 1'b0; + 63'b000000100000000000000000000000000000000000000000000000000000000: n4388_o = 1'b0; + 63'b000000010000000000000000000000000000000000000000000000000000000: n4388_o = 1'b0; + 63'b000000001000000000000000000000000000000000000000000000000000000: n4388_o = 1'b0; + 63'b000000000100000000000000000000000000000000000000000000000000000: n4388_o = 1'b0; + 63'b000000000010000000000000000000000000000000000000000000000000000: n4388_o = 1'b0; + 63'b000000000001000000000000000000000000000000000000000000000000000: n4388_o = 1'b0; + 63'b000000000000100000000000000000000000000000000000000000000000000: n4388_o = 1'b0; + 63'b000000000000010000000000000000000000000000000000000000000000000: n4388_o = 1'b0; + 63'b000000000000001000000000000000000000000000000000000000000000000: n4388_o = 1'b0; + 63'b000000000000000100000000000000000000000000000000000000000000000: n4388_o = 1'b0; + 63'b000000000000000010000000000000000000000000000000000000000000000: n4388_o = 1'b0; + 63'b000000000000000001000000000000000000000000000000000000000000000: n4388_o = 1'b0; + 63'b000000000000000000100000000000000000000000000000000000000000000: n4388_o = 1'b0; + 63'b000000000000000000010000000000000000000000000000000000000000000: n4388_o = 1'b0; + 63'b000000000000000000001000000000000000000000000000000000000000000: n4388_o = 1'b0; + 63'b000000000000000000000100000000000000000000000000000000000000000: n4388_o = 1'b0; + 63'b000000000000000000000010000000000000000000000000000000000000000: n4388_o = 1'b0; + 63'b000000000000000000000001000000000000000000000000000000000000000: n4388_o = 1'b0; + 63'b000000000000000000000000100000000000000000000000000000000000000: n4388_o = 1'b0; + 63'b000000000000000000000000010000000000000000000000000000000000000: n4388_o = 1'b0; + 63'b000000000000000000000000001000000000000000000000000000000000000: n4388_o = 1'b0; + 63'b000000000000000000000000000100000000000000000000000000000000000: n4388_o = 1'b0; + 63'b000000000000000000000000000010000000000000000000000000000000000: n4388_o = 1'b0; + 63'b000000000000000000000000000001000000000000000000000000000000000: n4388_o = 1'b0; + 63'b000000000000000000000000000000100000000000000000000000000000000: n4388_o = n3143_o; + 63'b000000000000000000000000000000010000000000000000000000000000000: n4388_o = 1'b0; + 63'b000000000000000000000000000000001000000000000000000000000000000: n4388_o = 1'b0; + 63'b000000000000000000000000000000000100000000000000000000000000000: n4388_o = 1'b0; + 63'b000000000000000000000000000000000010000000000000000000000000000: n4388_o = 1'b0; + 63'b000000000000000000000000000000000001000000000000000000000000000: n4388_o = 1'b0; + 63'b000000000000000000000000000000000000100000000000000000000000000: n4388_o = 1'b0; + 63'b000000000000000000000000000000000000010000000000000000000000000: n4388_o = 1'b0; + 63'b000000000000000000000000000000000000001000000000000000000000000: n4388_o = 1'b0; + 63'b000000000000000000000000000000000000000100000000000000000000000: n4388_o = 1'b0; + 63'b000000000000000000000000000000000000000010000000000000000000000: n4388_o = 1'b0; + 63'b000000000000000000000000000000000000000001000000000000000000000: n4388_o = 1'b0; + 63'b000000000000000000000000000000000000000000100000000000000000000: n4388_o = 1'b0; + 63'b000000000000000000000000000000000000000000010000000000000000000: n4388_o = 1'b0; + 63'b000000000000000000000000000000000000000000001000000000000000000: n4388_o = 1'b0; + 63'b000000000000000000000000000000000000000000000100000000000000000: n4388_o = 1'b0; + 63'b000000000000000000000000000000000000000000000010000000000000000: n4388_o = 1'b0; + 63'b000000000000000000000000000000000000000000000001000000000000000: n4388_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000100000000000000: n4388_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000010000000000000: n4388_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000001000000000000: n4388_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000100000000000: n4388_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000010000000000: n4388_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000001000000000: n4388_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000100000000: n4388_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000010000000: n4388_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000001000000: n4388_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000100000: n4388_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000010000: n4388_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000001000: n4388_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000000100: n4388_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000000010: n4388_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000000001: n4388_o = 1'b0; + default: n4388_o = 1'b0; + endcase + /* decoder.vhd:635:5 */ + always @* + case (n4151_o) + 63'b100000000000000000000000000000000000000000000000000000000000000: n4391_o = 1'b0; + 63'b010000000000000000000000000000000000000000000000000000000000000: n4391_o = 1'b0; + 63'b001000000000000000000000000000000000000000000000000000000000000: n4391_o = 1'b0; + 63'b000100000000000000000000000000000000000000000000000000000000000: n4391_o = 1'b0; + 63'b000010000000000000000000000000000000000000000000000000000000000: n4391_o = 1'b0; + 63'b000001000000000000000000000000000000000000000000000000000000000: n4391_o = 1'b0; + 63'b000000100000000000000000000000000000000000000000000000000000000: n4391_o = 1'b0; + 63'b000000010000000000000000000000000000000000000000000000000000000: n4391_o = 1'b0; + 63'b000000001000000000000000000000000000000000000000000000000000000: n4391_o = 1'b0; + 63'b000000000100000000000000000000000000000000000000000000000000000: n4391_o = 1'b0; + 63'b000000000010000000000000000000000000000000000000000000000000000: n4391_o = 1'b0; + 63'b000000000001000000000000000000000000000000000000000000000000000: n4391_o = 1'b0; + 63'b000000000000100000000000000000000000000000000000000000000000000: n4391_o = 1'b0; + 63'b000000000000010000000000000000000000000000000000000000000000000: n4391_o = 1'b0; + 63'b000000000000001000000000000000000000000000000000000000000000000: n4391_o = 1'b0; + 63'b000000000000000100000000000000000000000000000000000000000000000: n4391_o = 1'b0; + 63'b000000000000000010000000000000000000000000000000000000000000000: n4391_o = 1'b0; + 63'b000000000000000001000000000000000000000000000000000000000000000: n4391_o = 1'b0; + 63'b000000000000000000100000000000000000000000000000000000000000000: n4391_o = 1'b0; + 63'b000000000000000000010000000000000000000000000000000000000000000: n4391_o = 1'b0; + 63'b000000000000000000001000000000000000000000000000000000000000000: n4391_o = 1'b0; + 63'b000000000000000000000100000000000000000000000000000000000000000: n4391_o = 1'b0; + 63'b000000000000000000000010000000000000000000000000000000000000000: n4391_o = 1'b0; + 63'b000000000000000000000001000000000000000000000000000000000000000: n4391_o = 1'b0; + 63'b000000000000000000000000100000000000000000000000000000000000000: n4391_o = 1'b0; + 63'b000000000000000000000000010000000000000000000000000000000000000: n4391_o = 1'b0; + 63'b000000000000000000000000001000000000000000000000000000000000000: n4391_o = 1'b0; + 63'b000000000000000000000000000100000000000000000000000000000000000: n4391_o = 1'b0; + 63'b000000000000000000000000000010000000000000000000000000000000000: n4391_o = 1'b0; + 63'b000000000000000000000000000001000000000000000000000000000000000: n4391_o = 1'b0; + 63'b000000000000000000000000000000100000000000000000000000000000000: n4391_o = 1'b0; + 63'b000000000000000000000000000000010000000000000000000000000000000: n4391_o = 1'b0; + 63'b000000000000000000000000000000001000000000000000000000000000000: n4391_o = 1'b0; + 63'b000000000000000000000000000000000100000000000000000000000000000: n4391_o = 1'b0; + 63'b000000000000000000000000000000000010000000000000000000000000000: n4391_o = 1'b0; + 63'b000000000000000000000000000000000001000000000000000000000000000: n4391_o = 1'b0; + 63'b000000000000000000000000000000000000100000000000000000000000000: n4391_o = 1'b0; + 63'b000000000000000000000000000000000000010000000000000000000000000: n4391_o = 1'b0; + 63'b000000000000000000000000000000000000001000000000000000000000000: n4391_o = 1'b0; + 63'b000000000000000000000000000000000000000100000000000000000000000: n4391_o = 1'b0; + 63'b000000000000000000000000000000000000000010000000000000000000000: n4391_o = 1'b0; + 63'b000000000000000000000000000000000000000001000000000000000000000: n4391_o = 1'b0; + 63'b000000000000000000000000000000000000000000100000000000000000000: n4391_o = 1'b0; + 63'b000000000000000000000000000000000000000000010000000000000000000: n4391_o = 1'b0; + 63'b000000000000000000000000000000000000000000001000000000000000000: n4391_o = 1'b0; + 63'b000000000000000000000000000000000000000000000100000000000000000: n4391_o = 1'b0; + 63'b000000000000000000000000000000000000000000000010000000000000000: n4391_o = 1'b0; + 63'b000000000000000000000000000000000000000000000001000000000000000: n4391_o = n2653_o; + 63'b000000000000000000000000000000000000000000000000100000000000000: n4391_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000010000000000000: n4391_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000001000000000000: n4391_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000100000000000: n4391_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000010000000000: n4391_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000001000000000: n4391_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000100000000: n4391_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000010000000: n4391_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000001000000: n4391_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000100000: n4391_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000010000: n4391_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000001000: n4391_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000000100: n4391_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000000010: n4391_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000000001: n4391_o = 1'b0; + default: n4391_o = 1'b0; + endcase + /* decoder.vhd:635:5 */ + always @* + case (n4151_o) + 63'b100000000000000000000000000000000000000000000000000000000000000: n4394_o = 1'b0; + 63'b010000000000000000000000000000000000000000000000000000000000000: n4394_o = 1'b0; + 63'b001000000000000000000000000000000000000000000000000000000000000: n4394_o = 1'b0; + 63'b000100000000000000000000000000000000000000000000000000000000000: n4394_o = 1'b0; + 63'b000010000000000000000000000000000000000000000000000000000000000: n4394_o = 1'b0; + 63'b000001000000000000000000000000000000000000000000000000000000000: n4394_o = 1'b0; + 63'b000000100000000000000000000000000000000000000000000000000000000: n4394_o = 1'b0; + 63'b000000010000000000000000000000000000000000000000000000000000000: n4394_o = 1'b0; + 63'b000000001000000000000000000000000000000000000000000000000000000: n4394_o = 1'b0; + 63'b000000000100000000000000000000000000000000000000000000000000000: n4394_o = 1'b0; + 63'b000000000010000000000000000000000000000000000000000000000000000: n4394_o = 1'b0; + 63'b000000000001000000000000000000000000000000000000000000000000000: n4394_o = 1'b0; + 63'b000000000000100000000000000000000000000000000000000000000000000: n4394_o = 1'b0; + 63'b000000000000010000000000000000000000000000000000000000000000000: n4394_o = 1'b0; + 63'b000000000000001000000000000000000000000000000000000000000000000: n4394_o = 1'b0; + 63'b000000000000000100000000000000000000000000000000000000000000000: n4394_o = 1'b0; + 63'b000000000000000010000000000000000000000000000000000000000000000: n4394_o = 1'b0; + 63'b000000000000000001000000000000000000000000000000000000000000000: n4394_o = 1'b0; + 63'b000000000000000000100000000000000000000000000000000000000000000: n4394_o = 1'b0; + 63'b000000000000000000010000000000000000000000000000000000000000000: n4394_o = 1'b0; + 63'b000000000000000000001000000000000000000000000000000000000000000: n4394_o = 1'b0; + 63'b000000000000000000000100000000000000000000000000000000000000000: n4394_o = 1'b0; + 63'b000000000000000000000010000000000000000000000000000000000000000: n4394_o = 1'b0; + 63'b000000000000000000000001000000000000000000000000000000000000000: n4394_o = 1'b0; + 63'b000000000000000000000000100000000000000000000000000000000000000: n4394_o = 1'b0; + 63'b000000000000000000000000010000000000000000000000000000000000000: n4394_o = 1'b0; + 63'b000000000000000000000000001000000000000000000000000000000000000: n4394_o = 1'b0; + 63'b000000000000000000000000000100000000000000000000000000000000000: n4394_o = 1'b0; + 63'b000000000000000000000000000010000000000000000000000000000000000: n4394_o = 1'b0; + 63'b000000000000000000000000000001000000000000000000000000000000000: n4394_o = 1'b0; + 63'b000000000000000000000000000000100000000000000000000000000000000: n4394_o = 1'b0; + 63'b000000000000000000000000000000010000000000000000000000000000000: n4394_o = 1'b0; + 63'b000000000000000000000000000000001000000000000000000000000000000: n4394_o = 1'b0; + 63'b000000000000000000000000000000000100000000000000000000000000000: n4394_o = 1'b0; + 63'b000000000000000000000000000000000010000000000000000000000000000: n4394_o = 1'b0; + 63'b000000000000000000000000000000000001000000000000000000000000000: n4394_o = 1'b0; + 63'b000000000000000000000000000000000000100000000000000000000000000: n4394_o = 1'b0; + 63'b000000000000000000000000000000000000010000000000000000000000000: n4394_o = 1'b0; + 63'b000000000000000000000000000000000000001000000000000000000000000: n4394_o = 1'b0; + 63'b000000000000000000000000000000000000000100000000000000000000000: n4394_o = 1'b0; + 63'b000000000000000000000000000000000000000010000000000000000000000: n4394_o = 1'b0; + 63'b000000000000000000000000000000000000000001000000000000000000000: n4394_o = 1'b0; + 63'b000000000000000000000000000000000000000000100000000000000000000: n4394_o = 1'b0; + 63'b000000000000000000000000000000000000000000010000000000000000000: n4394_o = 1'b0; + 63'b000000000000000000000000000000000000000000001000000000000000000: n4394_o = 1'b0; + 63'b000000000000000000000000000000000000000000000100000000000000000: n4394_o = 1'b0; + 63'b000000000000000000000000000000000000000000000010000000000000000: n4394_o = 1'b0; + 63'b000000000000000000000000000000000000000000000001000000000000000: n4394_o = n2655_o; + 63'b000000000000000000000000000000000000000000000000100000000000000: n4394_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000010000000000000: n4394_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000001000000000000: n4394_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000100000000000: n4394_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000010000000000: n4394_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000001000000000: n4394_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000100000000: n4394_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000010000000: n4394_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000001000000: n4394_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000100000: n4394_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000010000: n4394_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000001000: n4394_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000000100: n4394_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000000010: n4394_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000000001: n4394_o = 1'b0; + default: n4394_o = 1'b0; + endcase + /* decoder.vhd:635:5 */ + always @* + case (n4151_o) + 63'b100000000000000000000000000000000000000000000000000000000000000: n4397_o = 1'b0; + 63'b010000000000000000000000000000000000000000000000000000000000000: n4397_o = 1'b0; + 63'b001000000000000000000000000000000000000000000000000000000000000: n4397_o = 1'b0; + 63'b000100000000000000000000000000000000000000000000000000000000000: n4397_o = 1'b0; + 63'b000010000000000000000000000000000000000000000000000000000000000: n4397_o = 1'b0; + 63'b000001000000000000000000000000000000000000000000000000000000000: n4397_o = 1'b0; + 63'b000000100000000000000000000000000000000000000000000000000000000: n4397_o = 1'b0; + 63'b000000010000000000000000000000000000000000000000000000000000000: n4397_o = 1'b0; + 63'b000000001000000000000000000000000000000000000000000000000000000: n4397_o = 1'b0; + 63'b000000000100000000000000000000000000000000000000000000000000000: n4397_o = 1'b0; + 63'b000000000010000000000000000000000000000000000000000000000000000: n4397_o = 1'b0; + 63'b000000000001000000000000000000000000000000000000000000000000000: n4397_o = 1'b0; + 63'b000000000000100000000000000000000000000000000000000000000000000: n4397_o = 1'b0; + 63'b000000000000010000000000000000000000000000000000000000000000000: n4397_o = 1'b0; + 63'b000000000000001000000000000000000000000000000000000000000000000: n4397_o = 1'b0; + 63'b000000000000000100000000000000000000000000000000000000000000000: n4397_o = 1'b0; + 63'b000000000000000010000000000000000000000000000000000000000000000: n4397_o = 1'b0; + 63'b000000000000000001000000000000000000000000000000000000000000000: n4397_o = 1'b0; + 63'b000000000000000000100000000000000000000000000000000000000000000: n4397_o = 1'b0; + 63'b000000000000000000010000000000000000000000000000000000000000000: n4397_o = 1'b0; + 63'b000000000000000000001000000000000000000000000000000000000000000: n4397_o = 1'b0; + 63'b000000000000000000000100000000000000000000000000000000000000000: n4397_o = 1'b0; + 63'b000000000000000000000010000000000000000000000000000000000000000: n4397_o = 1'b0; + 63'b000000000000000000000001000000000000000000000000000000000000000: n4397_o = 1'b0; + 63'b000000000000000000000000100000000000000000000000000000000000000: n4397_o = 1'b0; + 63'b000000000000000000000000010000000000000000000000000000000000000: n4397_o = 1'b0; + 63'b000000000000000000000000001000000000000000000000000000000000000: n4397_o = 1'b0; + 63'b000000000000000000000000000100000000000000000000000000000000000: n4397_o = 1'b0; + 63'b000000000000000000000000000010000000000000000000000000000000000: n4397_o = 1'b0; + 63'b000000000000000000000000000001000000000000000000000000000000000: n4397_o = 1'b0; + 63'b000000000000000000000000000000100000000000000000000000000000000: n4397_o = 1'b0; + 63'b000000000000000000000000000000010000000000000000000000000000000: n4397_o = 1'b0; + 63'b000000000000000000000000000000001000000000000000000000000000000: n4397_o = 1'b0; + 63'b000000000000000000000000000000000100000000000000000000000000000: n4397_o = 1'b0; + 63'b000000000000000000000000000000000010000000000000000000000000000: n4397_o = 1'b0; + 63'b000000000000000000000000000000000001000000000000000000000000000: n4397_o = 1'b0; + 63'b000000000000000000000000000000000000100000000000000000000000000: n4397_o = 1'b0; + 63'b000000000000000000000000000000000000010000000000000000000000000: n4397_o = 1'b0; + 63'b000000000000000000000000000000000000001000000000000000000000000: n4397_o = 1'b0; + 63'b000000000000000000000000000000000000000100000000000000000000000: n4397_o = 1'b0; + 63'b000000000000000000000000000000000000000010000000000000000000000: n4397_o = 1'b0; + 63'b000000000000000000000000000000000000000001000000000000000000000: n4397_o = 1'b0; + 63'b000000000000000000000000000000000000000000100000000000000000000: n4397_o = 1'b0; + 63'b000000000000000000000000000000000000000000010000000000000000000: n4397_o = 1'b0; + 63'b000000000000000000000000000000000000000000001000000000000000000: n4397_o = 1'b0; + 63'b000000000000000000000000000000000000000000000100000000000000000: n4397_o = 1'b0; + 63'b000000000000000000000000000000000000000000000010000000000000000: n4397_o = 1'b0; + 63'b000000000000000000000000000000000000000000000001000000000000000: n4397_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000100000000000000: n4397_o = n2638_o; + 63'b000000000000000000000000000000000000000000000000010000000000000: n4397_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000001000000000000: n4397_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000100000000000: n4397_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000010000000000: n4397_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000001000000000: n4397_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000100000000: n4397_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000010000000: n4397_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000001000000: n4397_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000100000: n4397_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000010000: n4397_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000001000: n4397_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000000100: n4397_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000000010: n4397_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000000001: n4397_o = 1'b0; + default: n4397_o = 1'b0; + endcase + /* decoder.vhd:635:5 */ + always @* + case (n4151_o) + 63'b100000000000000000000000000000000000000000000000000000000000000: n4400_o = 1'b0; + 63'b010000000000000000000000000000000000000000000000000000000000000: n4400_o = 1'b0; + 63'b001000000000000000000000000000000000000000000000000000000000000: n4400_o = 1'b0; + 63'b000100000000000000000000000000000000000000000000000000000000000: n4400_o = 1'b0; + 63'b000010000000000000000000000000000000000000000000000000000000000: n4400_o = 1'b0; + 63'b000001000000000000000000000000000000000000000000000000000000000: n4400_o = 1'b0; + 63'b000000100000000000000000000000000000000000000000000000000000000: n4400_o = 1'b0; + 63'b000000010000000000000000000000000000000000000000000000000000000: n4400_o = 1'b0; + 63'b000000001000000000000000000000000000000000000000000000000000000: n4400_o = 1'b0; + 63'b000000000100000000000000000000000000000000000000000000000000000: n4400_o = 1'b0; + 63'b000000000010000000000000000000000000000000000000000000000000000: n4400_o = 1'b0; + 63'b000000000001000000000000000000000000000000000000000000000000000: n4400_o = 1'b0; + 63'b000000000000100000000000000000000000000000000000000000000000000: n4400_o = 1'b0; + 63'b000000000000010000000000000000000000000000000000000000000000000: n4400_o = 1'b0; + 63'b000000000000001000000000000000000000000000000000000000000000000: n4400_o = 1'b0; + 63'b000000000000000100000000000000000000000000000000000000000000000: n4400_o = 1'b0; + 63'b000000000000000010000000000000000000000000000000000000000000000: n4400_o = 1'b0; + 63'b000000000000000001000000000000000000000000000000000000000000000: n4400_o = 1'b0; + 63'b000000000000000000100000000000000000000000000000000000000000000: n4400_o = 1'b0; + 63'b000000000000000000010000000000000000000000000000000000000000000: n4400_o = 1'b0; + 63'b000000000000000000001000000000000000000000000000000000000000000: n4400_o = 1'b0; + 63'b000000000000000000000100000000000000000000000000000000000000000: n4400_o = 1'b0; + 63'b000000000000000000000010000000000000000000000000000000000000000: n4400_o = 1'b0; + 63'b000000000000000000000001000000000000000000000000000000000000000: n4400_o = 1'b0; + 63'b000000000000000000000000100000000000000000000000000000000000000: n4400_o = 1'b0; + 63'b000000000000000000000000010000000000000000000000000000000000000: n4400_o = 1'b0; + 63'b000000000000000000000000001000000000000000000000000000000000000: n4400_o = 1'b0; + 63'b000000000000000000000000000100000000000000000000000000000000000: n4400_o = 1'b0; + 63'b000000000000000000000000000010000000000000000000000000000000000: n4400_o = 1'b0; + 63'b000000000000000000000000000001000000000000000000000000000000000: n4400_o = 1'b0; + 63'b000000000000000000000000000000100000000000000000000000000000000: n4400_o = 1'b0; + 63'b000000000000000000000000000000010000000000000000000000000000000: n4400_o = 1'b0; + 63'b000000000000000000000000000000001000000000000000000000000000000: n4400_o = 1'b0; + 63'b000000000000000000000000000000000100000000000000000000000000000: n4400_o = 1'b0; + 63'b000000000000000000000000000000000010000000000000000000000000000: n4400_o = 1'b0; + 63'b000000000000000000000000000000000001000000000000000000000000000: n4400_o = 1'b0; + 63'b000000000000000000000000000000000000100000000000000000000000000: n4400_o = 1'b0; + 63'b000000000000000000000000000000000000010000000000000000000000000: n4400_o = 1'b0; + 63'b000000000000000000000000000000000000001000000000000000000000000: n4400_o = 1'b0; + 63'b000000000000000000000000000000000000000100000000000000000000000: n4400_o = 1'b0; + 63'b000000000000000000000000000000000000000010000000000000000000000: n4400_o = 1'b0; + 63'b000000000000000000000000000000000000000001000000000000000000000: n4400_o = 1'b0; + 63'b000000000000000000000000000000000000000000100000000000000000000: n4400_o = 1'b0; + 63'b000000000000000000000000000000000000000000010000000000000000000: n4400_o = 1'b0; + 63'b000000000000000000000000000000000000000000001000000000000000000: n4400_o = 1'b0; + 63'b000000000000000000000000000000000000000000000100000000000000000: n4400_o = 1'b0; + 63'b000000000000000000000000000000000000000000000010000000000000000: n4400_o = 1'b0; + 63'b000000000000000000000000000000000000000000000001000000000000000: n4400_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000100000000000000: n4400_o = n2640_o; + 63'b000000000000000000000000000000000000000000000000010000000000000: n4400_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000001000000000000: n4400_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000100000000000: n4400_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000010000000000: n4400_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000001000000000: n4400_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000100000000: n4400_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000010000000: n4400_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000001000000: n4400_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000100000: n4400_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000010000: n4400_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000001000: n4400_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000000100: n4400_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000000010: n4400_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000000001: n4400_o = 1'b0; + default: n4400_o = 1'b0; + endcase + /* decoder.vhd:635:5 */ + always @* + case (n4151_o) + 63'b100000000000000000000000000000000000000000000000000000000000000: n4403_o = 1'b0; + 63'b010000000000000000000000000000000000000000000000000000000000000: n4403_o = 1'b0; + 63'b001000000000000000000000000000000000000000000000000000000000000: n4403_o = 1'b0; + 63'b000100000000000000000000000000000000000000000000000000000000000: n4403_o = 1'b0; + 63'b000010000000000000000000000000000000000000000000000000000000000: n4403_o = 1'b0; + 63'b000001000000000000000000000000000000000000000000000000000000000: n4403_o = 1'b0; + 63'b000000100000000000000000000000000000000000000000000000000000000: n4403_o = 1'b0; + 63'b000000010000000000000000000000000000000000000000000000000000000: n4403_o = 1'b0; + 63'b000000001000000000000000000000000000000000000000000000000000000: n4403_o = 1'b0; + 63'b000000000100000000000000000000000000000000000000000000000000000: n4403_o = 1'b0; + 63'b000000000010000000000000000000000000000000000000000000000000000: n4403_o = n3898_o; + 63'b000000000001000000000000000000000000000000000000000000000000000: n4403_o = 1'b0; + 63'b000000000000100000000000000000000000000000000000000000000000000: n4403_o = 1'b0; + 63'b000000000000010000000000000000000000000000000000000000000000000: n4403_o = 1'b0; + 63'b000000000000001000000000000000000000000000000000000000000000000: n4403_o = 1'b0; + 63'b000000000000000100000000000000000000000000000000000000000000000: n4403_o = 1'b0; + 63'b000000000000000010000000000000000000000000000000000000000000000: n4403_o = 1'b0; + 63'b000000000000000001000000000000000000000000000000000000000000000: n4403_o = 1'b0; + 63'b000000000000000000100000000000000000000000000000000000000000000: n4403_o = 1'b0; + 63'b000000000000000000010000000000000000000000000000000000000000000: n4403_o = 1'b0; + 63'b000000000000000000001000000000000000000000000000000000000000000: n4403_o = 1'b0; + 63'b000000000000000000000100000000000000000000000000000000000000000: n4403_o = 1'b0; + 63'b000000000000000000000010000000000000000000000000000000000000000: n4403_o = 1'b0; + 63'b000000000000000000000001000000000000000000000000000000000000000: n4403_o = 1'b0; + 63'b000000000000000000000000100000000000000000000000000000000000000: n4403_o = 1'b0; + 63'b000000000000000000000000010000000000000000000000000000000000000: n4403_o = 1'b0; + 63'b000000000000000000000000001000000000000000000000000000000000000: n4403_o = 1'b0; + 63'b000000000000000000000000000100000000000000000000000000000000000: n4403_o = 1'b0; + 63'b000000000000000000000000000010000000000000000000000000000000000: n4403_o = 1'b0; + 63'b000000000000000000000000000001000000000000000000000000000000000: n4403_o = 1'b0; + 63'b000000000000000000000000000000100000000000000000000000000000000: n4403_o = 1'b0; + 63'b000000000000000000000000000000010000000000000000000000000000000: n4403_o = 1'b0; + 63'b000000000000000000000000000000001000000000000000000000000000000: n4403_o = 1'b0; + 63'b000000000000000000000000000000000100000000000000000000000000000: n4403_o = 1'b0; + 63'b000000000000000000000000000000000010000000000000000000000000000: n4403_o = 1'b0; + 63'b000000000000000000000000000000000001000000000000000000000000000: n4403_o = 1'b0; + 63'b000000000000000000000000000000000000100000000000000000000000000: n4403_o = 1'b0; + 63'b000000000000000000000000000000000000010000000000000000000000000: n4403_o = 1'b0; + 63'b000000000000000000000000000000000000001000000000000000000000000: n4403_o = 1'b0; + 63'b000000000000000000000000000000000000000100000000000000000000000: n4403_o = 1'b0; + 63'b000000000000000000000000000000000000000010000000000000000000000: n4403_o = 1'b0; + 63'b000000000000000000000000000000000000000001000000000000000000000: n4403_o = 1'b0; + 63'b000000000000000000000000000000000000000000100000000000000000000: n4403_o = 1'b0; + 63'b000000000000000000000000000000000000000000010000000000000000000: n4403_o = 1'b0; + 63'b000000000000000000000000000000000000000000001000000000000000000: n4403_o = 1'b0; + 63'b000000000000000000000000000000000000000000000100000000000000000: n4403_o = 1'b0; + 63'b000000000000000000000000000000000000000000000010000000000000000: n4403_o = 1'b0; + 63'b000000000000000000000000000000000000000000000001000000000000000: n4403_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000100000000000000: n4403_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000010000000000000: n4403_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000001000000000000: n4403_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000100000000000: n4403_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000010000000000: n4403_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000001000000000: n4403_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000100000000: n4403_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000010000000: n4403_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000001000000: n4403_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000100000: n4403_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000010000: n4403_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000001000: n4403_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000000100: n4403_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000000010: n4403_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000000001: n4403_o = 1'b0; + default: n4403_o = 1'b0; + endcase + /* decoder.vhd:635:5 */ + always @* + case (n4151_o) + 63'b100000000000000000000000000000000000000000000000000000000000000: n4406_o = 1'b0; + 63'b010000000000000000000000000000000000000000000000000000000000000: n4406_o = 1'b0; + 63'b001000000000000000000000000000000000000000000000000000000000000: n4406_o = 1'b0; + 63'b000100000000000000000000000000000000000000000000000000000000000: n4406_o = 1'b0; + 63'b000010000000000000000000000000000000000000000000000000000000000: n4406_o = 1'b0; + 63'b000001000000000000000000000000000000000000000000000000000000000: n4406_o = 1'b0; + 63'b000000100000000000000000000000000000000000000000000000000000000: n4406_o = 1'b0; + 63'b000000010000000000000000000000000000000000000000000000000000000: n4406_o = 1'b0; + 63'b000000001000000000000000000000000000000000000000000000000000000: n4406_o = 1'b0; + 63'b000000000100000000000000000000000000000000000000000000000000000: n4406_o = 1'b0; + 63'b000000000010000000000000000000000000000000000000000000000000000: n4406_o = 1'b0; + 63'b000000000001000000000000000000000000000000000000000000000000000: n4406_o = 1'b0; + 63'b000000000000100000000000000000000000000000000000000000000000000: n4406_o = 1'b0; + 63'b000000000000010000000000000000000000000000000000000000000000000: n4406_o = 1'b0; + 63'b000000000000001000000000000000000000000000000000000000000000000: n4406_o = 1'b0; + 63'b000000000000000100000000000000000000000000000000000000000000000: n4406_o = 1'b0; + 63'b000000000000000010000000000000000000000000000000000000000000000: n4406_o = 1'b0; + 63'b000000000000000001000000000000000000000000000000000000000000000: n4406_o = 1'b0; + 63'b000000000000000000100000000000000000000000000000000000000000000: n4406_o = 1'b0; + 63'b000000000000000000010000000000000000000000000000000000000000000: n4406_o = 1'b0; + 63'b000000000000000000001000000000000000000000000000000000000000000: n4406_o = 1'b0; + 63'b000000000000000000000100000000000000000000000000000000000000000: n4406_o = 1'b0; + 63'b000000000000000000000010000000000000000000000000000000000000000: n4406_o = 1'b0; + 63'b000000000000000000000001000000000000000000000000000000000000000: n4406_o = 1'b0; + 63'b000000000000000000000000100000000000000000000000000000000000000: n4406_o = 1'b0; + 63'b000000000000000000000000010000000000000000000000000000000000000: n4406_o = 1'b0; + 63'b000000000000000000000000001000000000000000000000000000000000000: n4406_o = 1'b0; + 63'b000000000000000000000000000100000000000000000000000000000000000: n4406_o = 1'b0; + 63'b000000000000000000000000000010000000000000000000000000000000000: n4406_o = 1'b0; + 63'b000000000000000000000000000001000000000000000000000000000000000: n4406_o = 1'b0; + 63'b000000000000000000000000000000100000000000000000000000000000000: n4406_o = 1'b0; + 63'b000000000000000000000000000000010000000000000000000000000000000: n4406_o = 1'b0; + 63'b000000000000000000000000000000001000000000000000000000000000000: n4406_o = 1'b0; + 63'b000000000000000000000000000000000100000000000000000000000000000: n4406_o = 1'b0; + 63'b000000000000000000000000000000000010000000000000000000000000000: n4406_o = 1'b0; + 63'b000000000000000000000000000000000001000000000000000000000000000: n4406_o = 1'b0; + 63'b000000000000000000000000000000000000100000000000000000000000000: n4406_o = 1'b0; + 63'b000000000000000000000000000000000000010000000000000000000000000: n4406_o = 1'b0; + 63'b000000000000000000000000000000000000001000000000000000000000000: n4406_o = 1'b0; + 63'b000000000000000000000000000000000000000100000000000000000000000: n4406_o = 1'b0; + 63'b000000000000000000000000000000000000000010000000000000000000000: n4406_o = 1'b0; + 63'b000000000000000000000000000000000000000001000000000000000000000: n4406_o = 1'b0; + 63'b000000000000000000000000000000000000000000100000000000000000000: n4406_o = 1'b0; + 63'b000000000000000000000000000000000000000000010000000000000000000: n4406_o = 1'b0; + 63'b000000000000000000000000000000000000000000001000000000000000000: n4406_o = 1'b0; + 63'b000000000000000000000000000000000000000000000100000000000000000: n4406_o = 1'b0; + 63'b000000000000000000000000000000000000000000000010000000000000000: n4406_o = 1'b0; + 63'b000000000000000000000000000000000000000000000001000000000000000: n4406_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000100000000000000: n4406_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000010000000000000: n4406_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000001000000000000: n4406_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000100000000000: n4406_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000010000000000: n4406_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000001000000000: n4406_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000100000000: n4406_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000010000000: n4406_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000001000000: n4406_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000100000: n4406_o = n2463_o; + 63'b000000000000000000000000000000000000000000000000000000000010000: n4406_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000001000: n4406_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000000100: n4406_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000000010: n4406_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000000001: n4406_o = 1'b0; + default: n4406_o = 1'b0; + endcase + /* decoder.vhd:2020:14 */ + assign n4410_o = ~res_i; + /* decoder.vhd:2035:7 */ + assign n4413_o = bus_clear_f1_i ? 1'b0 : f1_q; + /* decoder.vhd:2033:7 */ + assign n4415_o = bus_set_f1_i ? 1'b1 : n4413_o; + /* decoder.vhd:2044:28 */ + assign n4417_o = clk_mstate_i == 3'b100; + /* decoder.vhd:2044:9 */ + assign n4419_o = n4417_o ? 1'b0 : branch_taken_q; + /* decoder.vhd:2042:9 */ + assign n4421_o = branch_taken_s ? 1'b1 : n4419_o; + /* decoder.vhd:2053:27 */ + assign n4422_o = ~f1_q; + /* decoder.vhd:2052:9 */ + assign n4423_o = cpl_f1_s ? n4422_o : n4415_o; + /* decoder.vhd:2050:9 */ + assign n4425_o = clear_f1_s ? 1'b0 : n4423_o; + /* decoder.vhd:2059:9 */ + assign n4427_o = set_mb_s ? 1'b1 : mb_q; + /* decoder.vhd:2057:9 */ + assign n4429_o = clear_mb_s ? 1'b0 : n4427_o; + /* decoder.vhd:2039:7 */ + assign n4433_o = en_clk_i ? n4425_o : n4415_o; + /* decoder.vhd:2039:7 */ + assign n4435_o = en_clk_i & ent0_clk_s; + /* decoder.vhd:2115:27 */ + assign n4449_o = read_dec_s ? data_s : 8'b11111111; + /* decoder.vhd:2117:48 */ + assign n4451_o = en_clk_i & dm_write_dmem_s; + /* decoder.vhd:2118:48 */ + assign n4452_o = pm_inc_pc_s | add_inc_pc_s; + /* decoder.vhd:2119:48 */ + assign n4453_o = pm_write_pmem_addr_s | add_write_pmem_addr_s; + /* decoder.vhd:2121:48 */ + assign n4454_o = bus_read_bus_s | add_read_bus_s; + /* decoder.vhd:305:5 */ + assign n4455_o = en_clk_i ? n1869_o : opc_opcode_q; + /* decoder.vhd:305:5 */ + always @(posedge clk_i or posedge n1863_o) + if (n1863_o) + n4456_q <= 8'b00000000; + else + n4456_q <= n4455_o; + /* decoder.vhd:2031:5 */ + assign n4457_o = en_clk_i ? n4421_o : branch_taken_q; + /* decoder.vhd:2031:5 */ + always @(posedge clk_i or posedge n4410_o) + if (n4410_o) + n4458_q <= 1'b0; + else + n4458_q <= n4457_o; + /* decoder.vhd:2031:5 */ + always @(posedge clk_i or posedge n4410_o) + if (n4410_o) + n4459_q <= 1'b0; + else + n4459_q <= n4433_o; + /* decoder.vhd:2031:5 */ + assign n4460_o = en_clk_i ? n4429_o : mb_q; + /* decoder.vhd:2031:5 */ + always @(posedge clk_i or posedge n4410_o) + if (n4410_o) + n4461_q <= 1'b0; + else + n4461_q <= n4460_o; + /* decoder.vhd:2031:5 */ + assign n4462_o = n4435_o ? 1'b1 : t0_dir_q; + /* decoder.vhd:2031:5 */ + always @(posedge clk_i or posedge n4410_o) + if (n4410_o) + n4463_q <= 1'b0; + else + n4463_q <= n4462_o; + /* decoder.vhd:305:5 */ + assign n4464_o = en_clk_i ? n1870_o : mnemonic_q; + /* decoder.vhd:305:5 */ + always @(posedge clk_i or posedge n1863_o) + if (n1863_o) + n4465_q <= 6'b101001; + else + n4465_q <= n4464_o; + /* decoder.vhd:301:5 */ + assign n4466_o = {n4275_o, n4274_o}; +endmodule + +module t48_db_bus + (input clk_i, + input res_i, + input en_clk_i, + input ea_i, + input [7:0] data_i, + input write_bus_i, + input read_bus_i, + input output_pcl_i, + input bidir_bus_i, + input [7:0] pcl_i, + input [7:0] db_i, + output [7:0] data_o, + output [7:0] db_o, + output db_dir_o); + wire [7:0] bus_q; + wire db_dir_q; + wire db_dir_qq; + wire n998_o; + wire n1001_o; + wire n1002_o; + wire n1004_o; + wire n1007_o; + wire n1008_o; + wire [7:0] n1021_o; + wire n1029_o; + wire n1030_o; + wire n1032_o; + wire [7:0] n1033_o; + wire [7:0] n1034_o; + reg [7:0] n1035_q; + wire n1036_o; + reg n1037_q; + wire n1038_o; + reg n1039_q; + assign data_o = n1033_o; + assign db_o = n1021_o; + assign db_dir_o = n1030_o; + /* db_bus.vhd:85:10 */ + assign bus_q = n1035_q; // (signal) + /* db_bus.vhd:88:10 */ + assign db_dir_q = n1037_q; // (signal) + /* db_bus.vhd:89:10 */ + assign db_dir_qq = n1039_q; // (signal) + /* db_bus.vhd:101:14 */ + assign n998_o = ~res_i; + /* db_bus.vhd:108:9 */ + assign n1001_o = write_bus_i ? 1'b1 : db_dir_q; + /* db_bus.vhd:120:26 */ + assign n1002_o = ea_i | bidir_bus_i; + /* db_bus.vhd:120:9 */ + assign n1004_o = n1002_o ? 1'b0 : db_dir_q; + /* db_bus.vhd:115:9 */ + assign n1007_o = write_bus_i ? 1'b1 : n1004_o; + /* db_bus.vhd:107:7 */ + assign n1008_o = en_clk_i & write_bus_i; + /* db_bus.vhd:138:15 */ + assign n1021_o = output_pcl_i ? pcl_i : bus_q; + /* t48_pack-p.vhd:66:5 */ + assign n1029_o = output_pcl_i ? 1'b1 : 1'b0; + /* db_bus.vhd:140:25 */ + assign n1030_o = db_dir_qq | n1029_o; + /* db_bus.vhd:143:20 */ + assign n1032_o = ~read_bus_i; + /* db_bus.vhd:143:15 */ + assign n1033_o = n1032_o ? 8'b11111111 : db_i; + /* db_bus.vhd:106:5 */ + assign n1034_o = n1008_o ? data_i : bus_q; + /* db_bus.vhd:106:5 */ + always @(posedge clk_i or posedge n998_o) + if (n998_o) + n1035_q <= 8'b00000000; + else + n1035_q <= n1034_o; + /* db_bus.vhd:106:5 */ + assign n1036_o = en_clk_i ? n1007_o : db_dir_q; + /* db_bus.vhd:106:5 */ + always @(posedge clk_i or posedge n998_o) + if (n998_o) + n1037_q <= 1'b0; + else + n1037_q <= n1036_o; + /* db_bus.vhd:106:5 */ + assign n1038_o = en_clk_i ? n1001_o : db_dir_qq; + /* db_bus.vhd:106:5 */ + always @(posedge clk_i or posedge n998_o) + if (n998_o) + n1039_q <= 1'b0; + else + n1039_q <= n1038_o; +endmodule + +module t48_cond_branch + (input clk_i, + input res_i, + input en_clk_i, + input compute_take_i, + input [3:0] branch_cond_i, + input [7:0] accu_i, + input t0_i, + input t1_i, + input int_n_i, + input f0_i, + input f1_i, + input tf_i, + input carry_i, + input ibf_i, + input obf_i, + input [2:0] comp_value_i, + output take_branch_o); + wire take_branch_s; + wire take_branch_q; + wire n910_o; + wire n912_o; + wire n913_o; + wire n915_o; + wire n916_o; + wire n917_o; + wire n918_o; + wire n919_o; + wire n920_o; + wire n921_o; + wire n922_o; + wire n923_o; + wire n924_o; + wire n925_o; + wire n926_o; + wire n927_o; + wire n928_o; + wire n929_o; + wire n930_o; + wire n931_o; + wire n932_o; + wire n934_o; + wire n935_o; + wire n936_o; + wire n938_o; + wire n940_o; + wire n942_o; + wire n943_o; + wire n945_o; + wire n946_o; + wire n947_o; + wire n949_o; + wire n950_o; + wire n951_o; + wire n953_o; + wire n955_o; + wire n956_o; + wire n958_o; + wire n960_o; + wire [10:0] n961_o; + reg n963_o; + wire n970_o; + wire n973_o; + wire n978_o; + reg n979_q; + wire n980_o; + wire n981_o; + wire n982_o; + wire n983_o; + wire n984_o; + wire n985_o; + wire n986_o; + wire n987_o; + wire [1:0] n988_o; + reg n989_o; + wire [1:0] n990_o; + reg n991_o; + wire n992_o; + wire n993_o; + assign take_branch_o = take_branch_q; + /* cond_branch.vhd:90:10 */ + assign take_branch_s = n963_o; // (signal) + /* cond_branch.vhd:91:10 */ + assign take_branch_q = n979_q; // (signal) + /* cond_branch.vhd:119:9 */ + assign n910_o = n993_o ? 1'b1 : 1'b0; + /* cond_branch.vhd:118:7 */ + assign n912_o = branch_cond_i == 4'b0000; + /* cond_branch.vhd:126:33 */ + assign n913_o = accu_i[7]; + /* cond_branch.vhd:126:24 */ + assign n915_o = 1'b0 | n913_o; + /* cond_branch.vhd:126:33 */ + assign n916_o = accu_i[6]; + /* cond_branch.vhd:126:24 */ + assign n917_o = n915_o | n916_o; + /* cond_branch.vhd:126:33 */ + assign n918_o = accu_i[5]; + /* cond_branch.vhd:126:24 */ + assign n919_o = n917_o | n918_o; + /* cond_branch.vhd:126:33 */ + assign n920_o = accu_i[4]; + /* cond_branch.vhd:126:24 */ + assign n921_o = n919_o | n920_o; + /* cond_branch.vhd:126:33 */ + assign n922_o = accu_i[3]; + /* cond_branch.vhd:126:24 */ + assign n923_o = n921_o | n922_o; + /* cond_branch.vhd:126:33 */ + assign n924_o = accu_i[2]; + /* cond_branch.vhd:126:24 */ + assign n925_o = n923_o | n924_o; + /* cond_branch.vhd:126:33 */ + assign n926_o = accu_i[1]; + /* cond_branch.vhd:126:24 */ + assign n927_o = n925_o | n926_o; + /* cond_branch.vhd:126:33 */ + assign n928_o = accu_i[0]; + /* cond_branch.vhd:126:24 */ + assign n929_o = n927_o | n928_o; + /* cond_branch.vhd:128:49 */ + assign n930_o = comp_value_i[0]; + /* cond_branch.vhd:128:33 */ + assign n931_o = ~n930_o; + /* cond_branch.vhd:128:31 */ + assign n932_o = n929_o == n931_o; + /* cond_branch.vhd:124:7 */ + assign n934_o = branch_cond_i == 4'b0001; + /* cond_branch.vhd:132:48 */ + assign n935_o = comp_value_i[0]; + /* cond_branch.vhd:132:34 */ + assign n936_o = carry_i == n935_o; + /* cond_branch.vhd:131:7 */ + assign n938_o = branch_cond_i == 4'b0010; + /* cond_branch.vhd:135:7 */ + assign n940_o = branch_cond_i == 4'b0011; + /* cond_branch.vhd:139:7 */ + assign n942_o = branch_cond_i == 4'b0100; + /* cond_branch.vhd:144:34 */ + assign n943_o = ~int_n_i; + /* cond_branch.vhd:143:7 */ + assign n945_o = branch_cond_i == 4'b0101; + /* cond_branch.vhd:148:45 */ + assign n946_o = comp_value_i[0]; + /* cond_branch.vhd:148:31 */ + assign n947_o = t0_i == n946_o; + /* cond_branch.vhd:147:7 */ + assign n949_o = branch_cond_i == 4'b0110; + /* cond_branch.vhd:152:45 */ + assign n950_o = comp_value_i[0]; + /* cond_branch.vhd:152:31 */ + assign n951_o = t1_i == n950_o; + /* cond_branch.vhd:151:7 */ + assign n953_o = branch_cond_i == 4'b0111; + /* cond_branch.vhd:155:7 */ + assign n955_o = branch_cond_i == 4'b1000; + /* cond_branch.vhd:160:32 */ + assign n956_o = ~ibf_i; + /* cond_branch.vhd:159:7 */ + assign n958_o = branch_cond_i == 4'b1001; + /* cond_branch.vhd:163:7 */ + assign n960_o = branch_cond_i == 4'b1010; + /* clock_ctrl.vhd:206:5 */ + assign n961_o = {n960_o, n958_o, n955_o, n953_o, n949_o, n945_o, n942_o, n940_o, n938_o, n934_o, n912_o}; + /* cond_branch.vhd:116:5 */ + always @* + case (n961_o) + 11'b10000000000: n963_o = obf_i; + 11'b01000000000: n963_o = n956_o; + 11'b00100000000: n963_o = tf_i; + 11'b00010000000: n963_o = n951_o; + 11'b00001000000: n963_o = n947_o; + 11'b00000100000: n963_o = n943_o; + 11'b00000010000: n963_o = f1_i; + 11'b00000001000: n963_o = f0_i; + 11'b00000000100: n963_o = n936_o; + 11'b00000000010: n963_o = n932_o; + 11'b00000000001: n963_o = n910_o; + default: n963_o = 1'b0; + endcase + /* cond_branch.vhd:188:14 */ + assign n970_o = ~res_i; + /* cond_branch.vhd:192:7 */ + assign n973_o = en_clk_i & compute_take_i; + /* cond_branch.vhd:191:5 */ + assign n978_o = n973_o ? take_branch_s : take_branch_q; + /* cond_branch.vhd:191:5 */ + always @(posedge clk_i or posedge n970_o) + if (n970_o) + n979_q <= 1'b0; + else + n979_q <= n978_o; + /* cond_branch.vhd:64:5 */ + assign n980_o = accu_i[0]; + assign n981_o = accu_i[1]; + /* cond_branch.vhd:191:5 */ + assign n982_o = accu_i[2]; + /* cond_branch.vhd:186:3 */ + assign n983_o = accu_i[3]; + assign n984_o = accu_i[4]; + assign n985_o = accu_i[5]; + /* cond_branch.vhd:116:5 */ + assign n986_o = accu_i[6]; + assign n987_o = accu_i[7]; + /* cond_branch.vhd:119:18 */ + assign n988_o = comp_value_i[1:0]; + /* cond_branch.vhd:119:18 */ + always @* + case (n988_o) + 2'b00: n989_o = n980_o; + 2'b01: n989_o = n981_o; + 2'b10: n989_o = n982_o; + 2'b11: n989_o = n983_o; + endcase + /* cond_branch.vhd:119:18 */ + assign n990_o = comp_value_i[1:0]; + /* cond_branch.vhd:119:18 */ + always @* + case (n990_o) + 2'b00: n991_o = n984_o; + 2'b01: n991_o = n985_o; + 2'b10: n991_o = n986_o; + 2'b11: n991_o = n987_o; + endcase + /* cond_branch.vhd:119:18 */ + assign n992_o = comp_value_i[2]; + /* cond_branch.vhd:119:18 */ + assign n993_o = n992_o ? n991_o : n989_o; +endmodule + +module t48_clock_ctrl_1 + (input clk_i, + input xtal_i, + input xtal_en_i, + input res_i, + input en_clk_i, + input multi_cycle_i, + input assert_psen_i, + input assert_prog_i, + input assert_rd_i, + input assert_wr_i, + output xtal3_o, + output t0_o, + output [2:0] mstate_o, + output second_cycle_o, + output ale_o, + output psen_o, + output prog_o, + output rd_o, + output wr_o); + wire [1:0] xtal_q; + wire xtal2_s; + wire xtal3_s; + wire x2_s; + wire x3_s; + wire t0_q; + wire [2:0] mstate_q; + wire ale_q; + wire psen_q; + wire prog_q; + wire rd_q; + wire wr_q; + wire second_cycle_q; + wire multi_cycle_q; + wire n686_o; + wire n689_o; + wire [1:0] n691_o; + wire [1:0] n693_o; + wire n696_o; + wire n714_o; + wire n715_o; + wire n716_o; + wire n720_o; + wire n721_o; + wire n722_o; + wire n739_o; + wire n747_o; + wire n749_o; + wire n751_o; + wire n752_o; + wire n754_o; + wire n756_o; + wire n757_o; + wire n758_o; + wire n760_o; + wire n762_o; + wire n764_o; + wire n766_o; + wire n768_o; + wire n770_o; + wire n772_o; + wire n774_o; + wire n776_o; + wire n778_o; + wire n779_o; + wire n780_o; + wire n781_o; + wire n782_o; + wire n783_o; + wire n785_o; + wire n787_o; + wire n789_o; + wire [4:0] n790_o; + reg n792_o; + reg n794_o; + reg n796_o; + reg n798_o; + reg n800_o; + wire n818_o; + wire n821_o; + wire n823_o; + wire n825_o; + wire n827_o; + wire n829_o; + wire [4:0] n830_o; + reg [2:0] n837_o; + wire n846_o; + wire n849_o; + wire n851_o; + wire n852_o; + wire n854_o; + wire n855_o; + wire n857_o; + wire n858_o; + wire n859_o; + wire n861_o; + wire n863_o; + wire [1:0] n887_o; + reg [1:0] n888_q; + wire n889_o; + reg n890_q; + wire [2:0] n891_o; + reg [2:0] n892_q; + reg n893_q; + reg n894_q; + reg n895_q; + reg n896_q; + reg n897_q; + wire n898_o; + reg n899_q; + wire n900_o; + reg n901_q; + assign xtal3_o = xtal3_s; + assign t0_o = t0_q; + assign mstate_o = mstate_q; + assign second_cycle_o = second_cycle_q; + assign ale_o = ale_q; + assign psen_o = psen_q; + assign prog_o = prog_q; + assign rd_o = rd_q; + assign wr_o = wr_q; + /* clock_ctrl.vhd:90:10 */ + assign xtal_q = n888_q; // (signal) + /* clock_ctrl.vhd:92:10 */ + assign xtal2_s = n739_o; // (signal) + /* clock_ctrl.vhd:93:10 */ + assign xtal3_s = n747_o; // (signal) + /* clock_ctrl.vhd:95:10 */ + assign x2_s = n716_o; // (signal) + /* clock_ctrl.vhd:96:10 */ + assign x3_s = n722_o; // (signal) + /* clock_ctrl.vhd:98:10 */ + assign t0_q = n890_q; // (signal) + /* clock_ctrl.vhd:102:10 */ + assign mstate_q = n892_q; // (signal) + /* clock_ctrl.vhd:104:10 */ + assign ale_q = n893_q; // (signal) + /* clock_ctrl.vhd:105:10 */ + assign psen_q = n894_q; // (signal) + /* clock_ctrl.vhd:106:10 */ + assign prog_q = n895_q; // (signal) + /* clock_ctrl.vhd:107:10 */ + assign rd_q = n896_q; // (signal) + /* clock_ctrl.vhd:108:10 */ + assign wr_q = n897_q; // (signal) + /* clock_ctrl.vhd:112:10 */ + assign second_cycle_q = n899_q; // (signal) + /* clock_ctrl.vhd:113:10 */ + assign multi_cycle_q = n901_q; // (signal) + /* clock_ctrl.vhd:137:16 */ + assign n686_o = ~res_i; + /* clock_ctrl.vhd:143:21 */ + assign n689_o = $unsigned(xtal_q) < $unsigned(2'b10); + /* clock_ctrl.vhd:144:30 */ + assign n691_o = xtal_q + 2'b01; + /* clock_ctrl.vhd:143:11 */ + assign n693_o = n689_o ? n691_o : 2'b00; + /* clock_ctrl.vhd:149:11 */ + assign n696_o = xtal3_s ? 1'b1 : 1'b0; + /* clock_ctrl.vhd:164:25 */ + assign n714_o = xtal_q == 2'b01; + /* clock_ctrl.vhd:164:29 */ + assign n715_o = xtal_en_i & n714_o; + /* clock_ctrl.vhd:164:13 */ + assign n716_o = n715_o ? 1'b1 : 1'b0; + /* clock_ctrl.vhd:167:25 */ + assign n720_o = xtal_q == 2'b10; + /* clock_ctrl.vhd:167:29 */ + assign n721_o = xtal_en_i & n720_o; + /* clock_ctrl.vhd:167:13 */ + assign n722_o = n721_o ? 1'b1 : 1'b0; + /* t48_pack-p.vhd:75:5 */ + assign n739_o = x2_s ? 1'b1 : 1'b0; + /* t48_pack-p.vhd:75:5 */ + assign n747_o = x3_s ? 1'b1 : 1'b0; + /* clock_ctrl.vhd:206:14 */ + assign n749_o = ~res_i; + /* clock_ctrl.vhd:218:26 */ + assign n751_o = ~second_cycle_q; + /* clock_ctrl.vhd:218:22 */ + assign n752_o = n751_o & xtal2_s; + /* clock_ctrl.vhd:218:11 */ + assign n754_o = n757_o ? 1'b1 : rd_q; + /* clock_ctrl.vhd:218:11 */ + assign n756_o = n758_o ? 1'b1 : wr_q; + /* clock_ctrl.vhd:218:11 */ + assign n757_o = n752_o & assert_rd_i; + /* clock_ctrl.vhd:218:11 */ + assign n758_o = n752_o & assert_wr_i; + /* clock_ctrl.vhd:216:9 */ + assign n760_o = mstate_q == 3'b100; + /* clock_ctrl.vhd:228:11 */ + assign n762_o = xtal3_s ? 1'b0 : psen_q; + /* clock_ctrl.vhd:227:9 */ + assign n764_o = mstate_q == 3'b000; + /* clock_ctrl.vhd:233:11 */ + assign n766_o = xtal3_s ? 1'b0 : prog_q; + /* clock_ctrl.vhd:233:11 */ + assign n768_o = xtal3_s ? 1'b0 : rd_q; + /* clock_ctrl.vhd:233:11 */ + assign n770_o = xtal3_s ? 1'b0 : wr_q; + /* clock_ctrl.vhd:232:9 */ + assign n772_o = mstate_q == 3'b001; + /* clock_ctrl.vhd:243:11 */ + assign n774_o = xtal3_s ? 1'b1 : ale_q; + /* clock_ctrl.vhd:241:9 */ + assign n776_o = mstate_q == 3'b010; + /* clock_ctrl.vhd:248:11 */ + assign n778_o = n779_o ? 1'b1 : psen_q; + /* clock_ctrl.vhd:248:11 */ + assign n779_o = xtal3_s & assert_psen_i; + /* clock_ctrl.vhd:257:22 */ + assign n780_o = multi_cycle_q & xtal3_s; + /* clock_ctrl.vhd:258:32 */ + assign n781_o = ~second_cycle_q; + /* clock_ctrl.vhd:258:28 */ + assign n782_o = n781_o & n780_o; + /* clock_ctrl.vhd:258:51 */ + assign n783_o = assert_prog_i & n782_o; + /* clock_ctrl.vhd:257:11 */ + assign n785_o = n783_o ? 1'b1 : prog_q; + /* clock_ctrl.vhd:263:11 */ + assign n787_o = xtal2_s ? 1'b0 : ale_q; + /* clock_ctrl.vhd:247:9 */ + assign n789_o = mstate_q == 3'b011; + assign n790_o = {n789_o, n776_o, n772_o, n764_o, n760_o}; + /* clock_ctrl.vhd:215:7 */ + always @* + case (n790_o) + 5'b10000: n792_o = n787_o; + 5'b01000: n792_o = n774_o; + 5'b00100: n792_o = ale_q; + 5'b00010: n792_o = ale_q; + 5'b00001: n792_o = ale_q; + default: n792_o = 1'b0; + endcase + /* clock_ctrl.vhd:215:7 */ + always @* + case (n790_o) + 5'b10000: n794_o = n778_o; + 5'b01000: n794_o = psen_q; + 5'b00100: n794_o = psen_q; + 5'b00010: n794_o = n762_o; + 5'b00001: n794_o = psen_q; + default: n794_o = 1'b0; + endcase + /* clock_ctrl.vhd:215:7 */ + always @* + case (n790_o) + 5'b10000: n796_o = n785_o; + 5'b01000: n796_o = prog_q; + 5'b00100: n796_o = n766_o; + 5'b00010: n796_o = prog_q; + 5'b00001: n796_o = prog_q; + default: n796_o = 1'b0; + endcase + /* clock_ctrl.vhd:215:7 */ + always @* + case (n790_o) + 5'b10000: n798_o = rd_q; + 5'b01000: n798_o = rd_q; + 5'b00100: n798_o = n768_o; + 5'b00010: n798_o = rd_q; + 5'b00001: n798_o = n754_o; + default: n798_o = 1'b0; + endcase + /* clock_ctrl.vhd:215:7 */ + always @* + case (n790_o) + 5'b10000: n800_o = wr_q; + 5'b01000: n800_o = wr_q; + 5'b00100: n800_o = n770_o; + 5'b00010: n800_o = wr_q; + 5'b00001: n800_o = n756_o; + default: n800_o = 1'b0; + endcase + /* clock_ctrl.vhd:292:14 */ + assign n818_o = ~res_i; + /* clock_ctrl.vhd:303:11 */ + assign n821_o = mstate_q == 3'b100; + /* clock_ctrl.vhd:306:11 */ + assign n823_o = mstate_q == 3'b000; + /* clock_ctrl.vhd:309:11 */ + assign n825_o = mstate_q == 3'b001; + /* clock_ctrl.vhd:312:11 */ + assign n827_o = mstate_q == 3'b010; + /* clock_ctrl.vhd:315:11 */ + assign n829_o = mstate_q == 3'b011; + assign n830_o = {n829_o, n827_o, n825_o, n823_o, n821_o}; + /* clock_ctrl.vhd:302:9 */ + always @* + case (n830_o) + 5'b10000: n837_o = 3'b100; + 5'b01000: n837_o = 3'b011; + 5'b00100: n837_o = 3'b010; + 5'b00010: n837_o = 3'b001; + 5'b00001: n837_o = 3'b000; + default: n837_o = 3'b000; + endcase + /* clock_ctrl.vhd:349:14 */ + assign n846_o = ~res_i; + /* clock_ctrl.vhd:356:30 */ + assign n849_o = mstate_q == 3'b001; + /* clock_ctrl.vhd:357:30 */ + assign n851_o = mstate_q == 3'b100; + /* clock_ctrl.vhd:360:21 */ + assign n852_o = multi_cycle_i & n849_o; + /* clock_ctrl.vhd:360:9 */ + assign n854_o = n852_o ? 1'b1 : multi_cycle_q; + /* clock_ctrl.vhd:365:26 */ + assign n855_o = n851_o & multi_cycle_q; + /* clock_ctrl.vhd:365:9 */ + assign n857_o = n855_o ? 1'b1 : second_cycle_q; + /* clock_ctrl.vhd:371:27 */ + assign n858_o = second_cycle_q & multi_cycle_q; + /* clock_ctrl.vhd:370:21 */ + assign n859_o = n858_o & n851_o; + /* clock_ctrl.vhd:370:9 */ + assign n861_o = n859_o ? 1'b0 : n857_o; + /* clock_ctrl.vhd:370:9 */ + assign n863_o = n859_o ? 1'b0 : n854_o; + /* clock_ctrl.vhd:141:7 */ + assign n887_o = xtal_en_i ? n693_o : xtal_q; + /* clock_ctrl.vhd:141:7 */ + always @(posedge xtal_i or posedge n686_o) + if (n686_o) + n888_q <= 2'b00; + else + n888_q <= n887_o; + /* clock_ctrl.vhd:141:7 */ + assign n889_o = xtal_en_i ? n696_o : t0_q; + /* clock_ctrl.vhd:141:7 */ + always @(posedge xtal_i or posedge n686_o) + if (n686_o) + n890_q <= 1'b0; + else + n890_q <= n889_o; + /* clock_ctrl.vhd:299:5 */ + assign n891_o = en_clk_i ? n837_o : mstate_q; + /* clock_ctrl.vhd:299:5 */ + always @(posedge clk_i or posedge n818_o) + if (n818_o) + n892_q <= 3'b010; + else + n892_q <= n891_o; + /* clock_ctrl.vhd:213:5 */ + always @(posedge xtal_i or posedge n749_o) + if (n749_o) + n893_q <= 1'b0; + else + n893_q <= n792_o; + /* clock_ctrl.vhd:213:5 */ + always @(posedge xtal_i or posedge n749_o) + if (n749_o) + n894_q <= 1'b0; + else + n894_q <= n794_o; + /* clock_ctrl.vhd:213:5 */ + always @(posedge xtal_i or posedge n749_o) + if (n749_o) + n895_q <= 1'b0; + else + n895_q <= n796_o; + /* clock_ctrl.vhd:213:5 */ + always @(posedge xtal_i or posedge n749_o) + if (n749_o) + n896_q <= 1'b0; + else + n896_q <= n798_o; + /* clock_ctrl.vhd:213:5 */ + always @(posedge xtal_i or posedge n749_o) + if (n749_o) + n897_q <= 1'b0; + else + n897_q <= n800_o; + /* clock_ctrl.vhd:353:5 */ + assign n898_o = en_clk_i ? n861_o : second_cycle_q; + /* clock_ctrl.vhd:353:5 */ + always @(posedge clk_i or posedge n846_o) + if (n846_o) + n899_q <= 1'b0; + else + n899_q <= n898_o; + /* clock_ctrl.vhd:353:5 */ + assign n900_o = en_clk_i ? n863_o : multi_cycle_q; + /* clock_ctrl.vhd:353:5 */ + always @(posedge clk_i or posedge n846_o) + if (n846_o) + n901_q <= 1'b0; + else + n901_q <= n900_o; +endmodule + +module t48_bus_mux + (input [7:0] alu_data_i, + input [7:0] bus_data_i, + input [7:0] dec_data_i, + input [7:0] dm_data_i, + input [7:0] pm_data_i, + input [7:0] p1_data_i, + input [7:0] p2_data_i, + input [7:0] psw_data_i, + input [7:0] tim_data_i, + output [7:0] data_o); + wire [7:0] n668_o; + wire [7:0] n669_o; + wire [7:0] n670_o; + wire [7:0] n671_o; + wire [7:0] n672_o; + wire [7:0] n673_o; + wire [7:0] n674_o; + wire [7:0] n675_o; + assign data_o = n675_o; + /* bus_mux.vhd:89:26 */ + assign n668_o = alu_data_i & bus_data_i; + /* bus_mux.vhd:90:26 */ + assign n669_o = n668_o & dec_data_i; + /* bus_mux.vhd:91:26 */ + assign n670_o = n669_o & dm_data_i; + /* bus_mux.vhd:92:26 */ + assign n671_o = n670_o & pm_data_i; + /* bus_mux.vhd:93:26 */ + assign n672_o = n671_o & p1_data_i; + /* bus_mux.vhd:94:26 */ + assign n673_o = n672_o & p2_data_i; + /* bus_mux.vhd:95:26 */ + assign n674_o = n673_o & psw_data_i; + /* bus_mux.vhd:96:26 */ + assign n675_o = n674_o & tim_data_i; +endmodule + +module t48_alu + (input clk_i, + input res_i, + input en_clk_i, + input [7:0] data_i, + input write_accu_i, + input write_shadow_i, + input write_temp_reg_i, + input read_alu_i, + input carry_i, + input [3:0] alu_op_i, + input use_carry_i, + input da_high_i, + input accu_low_i, + input p06_temp_reg_i, + input p60_temp_reg_i, + output [7:0] data_o, + output carry_o, + output aux_carry_o, + output da_overflow_o); + wire [7:0] accumulator_q; + wire [7:0] accu_shadow_q; + wire [7:0] temp_req_q; + wire [7:0] in_a_s; + wire [7:0] in_b_s; + wire [7:0] data_s; + wire [8:0] add_result_s; + wire n417_o; + wire [3:0] n419_o; + wire [3:0] n420_o; + wire [3:0] n421_o; + wire [3:0] n422_o; + wire [3:0] n423_o; + wire [3:0] n424_o; + wire [7:0] n425_o; + wire [7:0] n427_o; + wire [7:0] n428_o; + wire [7:0] n430_o; + wire [7:0] n432_o; + wire n433_o; + wire [7:0] n447_o; + wire n449_o; + wire [7:0] n450_o; + wire n452_o; + wire [7:0] n453_o; + wire n455_o; + wire [7:0] n456_o; + wire n457_o; + wire n459_o; + wire [7:0] n460_o; + wire n462_o; + wire n464_o; + wire [6:0] n465_o; + wire n466_o; + wire n467_o; + wire n468_o; + wire n470_o; + wire [6:0] n471_o; + wire n472_o; + wire n473_o; + wire n474_o; + wire n476_o; + wire [3:0] n477_o; + wire [3:0] n478_o; + wire n480_o; + wire [7:0] n481_o; + wire n483_o; + wire [7:0] n484_o; + wire n486_o; + wire [3:0] n487_o; + wire [3:0] n488_o; + wire [7:0] n489_o; + wire n491_o; + wire n493_o; + wire [12:0] n494_o; + reg n496_o; + wire n498_o; + wire n499_o; + wire n500_o; + wire n501_o; + wire n502_o; + wire n504_o; + wire n505_o; + wire n506_o; + wire n507_o; + wire n508_o; + wire n509_o; + reg n511_o; + wire [2:0] n512_o; + wire [2:0] n513_o; + wire [2:0] n514_o; + wire [2:0] n515_o; + wire [2:0] n516_o; + wire [2:0] n518_o; + wire [2:0] n519_o; + wire [2:0] n520_o; + wire [2:0] n521_o; + wire [2:0] n522_o; + wire [2:0] n523_o; + wire [2:0] n524_o; + reg [2:0] n526_o; + wire [2:0] n527_o; + wire [2:0] n528_o; + wire [2:0] n529_o; + wire [2:0] n530_o; + wire [2:0] n531_o; + wire [2:0] n533_o; + wire [2:0] n534_o; + wire [2:0] n535_o; + wire [2:0] n536_o; + wire [2:0] n537_o; + wire [2:0] n538_o; + wire [2:0] n539_o; + reg [2:0] n541_o; + wire n542_o; + wire n543_o; + wire n544_o; + wire n545_o; + wire n546_o; + wire n548_o; + wire n549_o; + wire n550_o; + wire n551_o; + wire n552_o; + wire n553_o; + reg n555_o; + wire n567_o; + wire n570_o; + localparam [8:0] n571_o = 9'b000000000; + wire [7:0] n572_o; + wire [8:0] n574_o; + wire [8:0] n576_o; + localparam [8:0] n578_o = 9'b000000000; + wire [7:0] n579_o; + wire n581_o; + wire n583_o; + wire [1:0] n584_o; + wire n586_o; + reg n587_o; + wire [7:0] n589_o; + reg [7:0] n590_o; + wire [8:0] n592_o; + wire [8:0] n593_o; + wire [8:0] n594_o; + wire [8:0] n595_o; + wire n596_o; + wire n597_o; + wire [1:0] n598_o; + wire n599_o; + wire n602_o; + wire n604_o; + wire n606_o; + wire n607_o; + wire n608_o; + wire n609_o; + wire n612_o; + wire n614_o; + wire n616_o; + wire n617_o; + wire [1:0] n618_o; + reg n620_o; + wire [3:0] n627_o; + wire [3:0] n628_o; + wire [3:0] n629_o; + wire n637_o; + wire n639_o; + wire n640_o; + wire n642_o; + wire n643_o; + wire n645_o; + wire n646_o; + wire n648_o; + wire n649_o; + wire n651_o; + wire n652_o; + reg n655_o; + wire [7:0] n658_o; + wire [7:0] n660_o; + reg [7:0] n661_q; + wire [7:0] n662_o; + reg [7:0] n663_q; + wire [7:0] n664_o; + reg [7:0] n665_q; + wire [7:0] n666_o; + assign data_o = n658_o; + assign carry_o = n496_o; + assign aux_carry_o = n620_o; + assign da_overflow_o = n655_o; + /* alu.vhd:99:10 */ + assign accumulator_q = n661_q; // (signal) + /* alu.vhd:100:10 */ + assign accu_shadow_q = n663_q; // (signal) + /* alu.vhd:101:10 */ + assign temp_req_q = n665_q; // (signal) + /* alu.vhd:103:10 */ + assign in_a_s = accu_shadow_q; // (signal) + /* alu.vhd:104:10 */ + assign in_b_s = temp_req_q; // (signal) + /* alu.vhd:106:10 */ + assign data_s = n666_o; // (signal) + /* alu.vhd:108:10 */ + assign add_result_s = n595_o; // (signal) + /* alu.vhd:122:14 */ + assign n417_o = ~res_i; + /* alu.vhd:132:52 */ + assign n419_o = data_i[3:0]; + /* t48_core.vhd:568:26 */ + assign n420_o = data_i[3:0]; + /* alu.vhd:131:11 */ + assign n421_o = accu_low_i ? n419_o : n420_o; + /* t48_core.vhd:551:5 */ + assign n422_o = data_i[7:4]; + /* t48_core.vhd:551:5 */ + assign n423_o = accumulator_q[7:4]; + /* alu.vhd:131:11 */ + assign n424_o = accu_low_i ? n423_o : n422_o; + /* t48_core.vhd:551:5 */ + assign n425_o = {n424_o, n421_o}; + /* alu.vhd:138:9 */ + assign n427_o = write_shadow_i ? data_i : accumulator_q; + /* alu.vhd:152:9 */ + assign n428_o = write_temp_reg_i ? data_i : temp_req_q; + /* alu.vhd:149:9 */ + assign n430_o = p60_temp_reg_i ? 8'b01100000 : n428_o; + /* alu.vhd:146:9 */ + assign n432_o = p06_temp_reg_i ? 8'b00000110 : n430_o; + /* alu.vhd:128:7 */ + assign n433_o = en_clk_i & write_accu_i; + /* alu.vhd:203:26 */ + assign n447_o = in_a_s & in_b_s; + /* alu.vhd:202:7 */ + assign n449_o = alu_op_i == 4'b0000; + /* alu.vhd:207:26 */ + assign n450_o = in_a_s | in_b_s; + /* alu.vhd:206:7 */ + assign n452_o = alu_op_i == 4'b0001; + /* alu.vhd:211:26 */ + assign n453_o = in_a_s ^ in_b_s; + /* alu.vhd:210:7 */ + assign n455_o = alu_op_i == 4'b0010; + /* alu.vhd:215:32 */ + assign n456_o = add_result_s[7:0]; + /* alu.vhd:216:32 */ + assign n457_o = add_result_s[8]; + /* alu.vhd:214:7 */ + assign n459_o = alu_op_i == 4'b1010; + /* alu.vhd:220:19 */ + assign n460_o = ~in_a_s; + /* alu.vhd:219:7 */ + assign n462_o = alu_op_i == 4'b0011; + /* alu.vhd:223:7 */ + assign n464_o = alu_op_i == 4'b0100; + /* alu.vhd:228:37 */ + assign n465_o = in_a_s[6:0]; + /* alu.vhd:229:37 */ + assign n466_o = in_a_s[7]; + /* alu.vhd:234:37 */ + assign n467_o = in_a_s[7]; + /* alu.vhd:231:9 */ + assign n468_o = use_carry_i ? carry_i : n467_o; + /* alu.vhd:227:7 */ + assign n470_o = alu_op_i == 4'b0101; + /* alu.vhd:239:37 */ + assign n471_o = in_a_s[7:1]; + /* alu.vhd:240:37 */ + assign n472_o = in_a_s[0]; + /* alu.vhd:245:37 */ + assign n473_o = in_a_s[0]; + /* alu.vhd:242:9 */ + assign n474_o = use_carry_i ? carry_i : n473_o; + /* alu.vhd:238:7 */ + assign n476_o = alu_op_i == 4'b0110; + /* alu.vhd:250:37 */ + assign n477_o = in_a_s[7:4]; + /* alu.vhd:251:37 */ + assign n478_o = in_a_s[3:0]; + /* alu.vhd:249:7 */ + assign n480_o = alu_op_i == 4'b0111; + /* alu.vhd:255:31 */ + assign n481_o = add_result_s[7:0]; + /* alu.vhd:254:7 */ + assign n483_o = alu_op_i == 4'b1000; + /* alu.vhd:259:31 */ + assign n484_o = add_result_s[7:0]; + /* alu.vhd:258:7 */ + assign n486_o = alu_op_i == 4'b1001; + /* alu.vhd:263:25 */ + assign n487_o = in_b_s[7:4]; + /* alu.vhd:263:46 */ + assign n488_o = in_a_s[3:0]; + /* alu.vhd:263:38 */ + assign n489_o = {n487_o, n488_o}; + /* alu.vhd:262:7 */ + assign n491_o = alu_op_i == 4'b1011; + /* alu.vhd:266:7 */ + assign n493_o = alu_op_i == 4'b1100; + /* t48_core.vhd:418:33 */ + assign n494_o = {n493_o, n491_o, n486_o, n483_o, n480_o, n476_o, n470_o, n464_o, n462_o, n459_o, n455_o, n452_o, n449_o}; + /* alu.vhd:200:5 */ + always @* + case (n494_o) + 13'b1000000000000: n496_o = 1'b0; + 13'b0100000000000: n496_o = 1'b0; + 13'b0010000000000: n496_o = 1'b0; + 13'b0001000000000: n496_o = 1'b0; + 13'b0000100000000: n496_o = 1'b0; + 13'b0000010000000: n496_o = n472_o; + 13'b0000001000000: n496_o = n466_o; + 13'b0000000100000: n496_o = 1'b0; + 13'b0000000010000: n496_o = 1'b0; + 13'b0000000001000: n496_o = n457_o; + 13'b0000000000100: n496_o = 1'b0; + 13'b0000000000010: n496_o = 1'b0; + 13'b0000000000001: n496_o = 1'b0; + default: n496_o = 1'b0; + endcase + /* t48_core.vhd:414:33 */ + assign n498_o = n447_o[0]; + /* t48_core.vhd:413:33 */ + assign n499_o = n450_o[0]; + /* t48_core.vhd:412:33 */ + assign n500_o = n453_o[0]; + /* t48_core.vhd:411:33 */ + assign n501_o = n456_o[0]; + /* t48_core.vhd:410:33 */ + assign n502_o = n460_o[0]; + /* t48_core.vhd:408:33 */ + assign n504_o = n471_o[0]; + /* t48_core.vhd:407:33 */ + assign n505_o = n477_o[0]; + /* t48_core.vhd:405:33 */ + assign n506_o = n481_o[0]; + /* t48_core.vhd:392:3 */ + assign n507_o = n484_o[0]; + /* t48_core.vhd:392:3 */ + assign n508_o = n489_o[0]; + /* t48_core.vhd:392:3 */ + assign n509_o = in_a_s[0]; + /* alu.vhd:200:5 */ + always @* + case (n494_o) + 13'b1000000000000: n511_o = n509_o; + 13'b0100000000000: n511_o = n508_o; + 13'b0010000000000: n511_o = n507_o; + 13'b0001000000000: n511_o = n506_o; + 13'b0000100000000: n511_o = n505_o; + 13'b0000010000000: n511_o = n504_o; + 13'b0000001000000: n511_o = n468_o; + 13'b0000000100000: n511_o = 1'b0; + 13'b0000000010000: n511_o = n502_o; + 13'b0000000001000: n511_o = n501_o; + 13'b0000000000100: n511_o = n500_o; + 13'b0000000000010: n511_o = n499_o; + 13'b0000000000001: n511_o = n498_o; + default: n511_o = 1'b0; + endcase + /* t48_core.vhd:392:3 */ + assign n512_o = n447_o[3:1]; + /* t48_core.vhd:392:3 */ + assign n513_o = n450_o[3:1]; + /* t48_core.vhd:392:3 */ + assign n514_o = n453_o[3:1]; + /* t48_core.vhd:392:3 */ + assign n515_o = n456_o[3:1]; + /* t48_core.vhd:392:3 */ + assign n516_o = n460_o[3:1]; + /* t48_core.vhd:392:3 */ + assign n518_o = n465_o[2:0]; + /* t48_core.vhd:392:3 */ + assign n519_o = n471_o[3:1]; + /* t48_core.vhd:392:3 */ + assign n520_o = n477_o[3:1]; + /* t48_core.vhd:392:3 */ + assign n521_o = n481_o[3:1]; + /* t48_core.vhd:392:3 */ + assign n522_o = n484_o[3:1]; + /* t48_core.vhd:392:3 */ + assign n523_o = n489_o[3:1]; + /* t48_core.vhd:392:3 */ + assign n524_o = in_a_s[3:1]; + /* alu.vhd:200:5 */ + always @* + case (n494_o) + 13'b1000000000000: n526_o = n524_o; + 13'b0100000000000: n526_o = n523_o; + 13'b0010000000000: n526_o = n522_o; + 13'b0001000000000: n526_o = n521_o; + 13'b0000100000000: n526_o = n520_o; + 13'b0000010000000: n526_o = n519_o; + 13'b0000001000000: n526_o = n518_o; + 13'b0000000100000: n526_o = 3'b000; + 13'b0000000010000: n526_o = n516_o; + 13'b0000000001000: n526_o = n515_o; + 13'b0000000000100: n526_o = n514_o; + 13'b0000000000010: n526_o = n513_o; + 13'b0000000000001: n526_o = n512_o; + default: n526_o = 3'b000; + endcase + /* t48_core.vhd:392:3 */ + assign n527_o = n447_o[6:4]; + /* t48_core.vhd:392:3 */ + assign n528_o = n450_o[6:4]; + /* t48_core.vhd:392:3 */ + assign n529_o = n453_o[6:4]; + /* t48_core.vhd:392:3 */ + assign n530_o = n456_o[6:4]; + /* t48_core.vhd:392:3 */ + assign n531_o = n460_o[6:4]; + /* t48_core.vhd:392:3 */ + assign n533_o = n465_o[5:3]; + /* t48_core.vhd:392:3 */ + assign n534_o = n471_o[6:4]; + /* t48_core.vhd:392:3 */ + assign n535_o = n478_o[2:0]; + /* t48_core.vhd:392:3 */ + assign n536_o = n481_o[6:4]; + /* t48_core.vhd:392:3 */ + assign n537_o = n484_o[6:4]; + /* t48_core.vhd:392:3 */ + assign n538_o = n489_o[6:4]; + /* t48_core.vhd:392:3 */ + assign n539_o = in_a_s[6:4]; + /* alu.vhd:200:5 */ + always @* + case (n494_o) + 13'b1000000000000: n541_o = n539_o; + 13'b0100000000000: n541_o = n538_o; + 13'b0010000000000: n541_o = n537_o; + 13'b0001000000000: n541_o = n536_o; + 13'b0000100000000: n541_o = n535_o; + 13'b0000010000000: n541_o = n534_o; + 13'b0000001000000: n541_o = n533_o; + 13'b0000000100000: n541_o = 3'b000; + 13'b0000000010000: n541_o = n531_o; + 13'b0000000001000: n541_o = n530_o; + 13'b0000000000100: n541_o = n529_o; + 13'b0000000000010: n541_o = n528_o; + 13'b0000000000001: n541_o = n527_o; + default: n541_o = 3'b000; + endcase + /* t48_core.vhd:392:3 */ + assign n542_o = n447_o[7]; + /* t48_core.vhd:392:3 */ + assign n543_o = n450_o[7]; + /* t48_core.vhd:392:3 */ + assign n544_o = n453_o[7]; + /* t48_core.vhd:392:3 */ + assign n545_o = n456_o[7]; + /* t48_core.vhd:392:3 */ + assign n546_o = n460_o[7]; + /* t48_core.vhd:392:3 */ + assign n548_o = n465_o[6]; + /* t48_core.vhd:392:3 */ + assign n549_o = n478_o[3]; + /* t48_core.vhd:392:3 */ + assign n550_o = n481_o[7]; + /* t48_core.vhd:392:3 */ + assign n551_o = n484_o[7]; + /* t48_core.vhd:392:3 */ + assign n552_o = n489_o[7]; + /* t48_core.vhd:392:3 */ + assign n553_o = in_a_s[7]; + /* alu.vhd:200:5 */ + always @* + case (n494_o) + 13'b1000000000000: n555_o = n553_o; + 13'b0100000000000: n555_o = n552_o; + 13'b0010000000000: n555_o = n551_o; + 13'b0001000000000: n555_o = n550_o; + 13'b0000100000000: n555_o = n549_o; + 13'b0000010000000: n555_o = n474_o; + 13'b0000001000000: n555_o = n548_o; + 13'b0000000100000: n555_o = 1'b0; + 13'b0000000010000: n555_o = n546_o; + 13'b0000000001000: n555_o = n545_o; + 13'b0000000000100: n555_o = n544_o; + 13'b0000000000010: n555_o = n543_o; + 13'b0000000000001: n555_o = n542_o; + default: n555_o = 1'b0; + endcase + /* alu.vhd:307:20 */ + assign n567_o = carry_i & use_carry_i; + /* alu.vhd:307:5 */ + assign n570_o = n567_o ? 1'b1 : 1'b0; + /* t48_core.vhd:347:3 */ + assign n572_o = n571_o[8:1]; + /* alu.vhd:313:20 */ + assign n574_o = {1'b0, in_a_s}; + /* alu.vhd:314:20 */ + assign n576_o = {1'b0, in_b_s}; + /* t48_core.vhd:338:25 */ + assign n579_o = n578_o[8:1]; + /* alu.vhd:317:7 */ + assign n581_o = alu_op_i == 4'b1001; + /* alu.vhd:320:7 */ + assign n583_o = alu_op_i == 4'b1000; + /* t48_core.vhd:321:3 */ + assign n584_o = {n583_o, n581_o}; + /* t48_core.vhd:321:3 */ + assign n586_o = n576_o[0]; + /* alu.vhd:316:5 */ + always @* + case (n584_o) + 2'b10: n587_o = 1'b1; + 2'b01: n587_o = 1'b1; + default: n587_o = n586_o; + endcase + /* t48_core.vhd:321:3 */ + assign n589_o = n576_o[8:1]; + /* alu.vhd:316:5 */ + always @* + case (n584_o) + 2'b10: n590_o = 8'b11111111; + 2'b01: n590_o = n579_o; + default: n590_o = n589_o; + endcase + /* t48_core.vhd:307:3 */ + assign n592_o = {n590_o, n587_o}; + /* alu.vhd:327:35 */ + assign n593_o = n574_o + n592_o; + /* t48_core.vhd:297:29 */ + assign n594_o = {n572_o, n570_o}; + /* alu.vhd:328:35 */ + assign n595_o = n593_o + n594_o; + /* alu.vhd:334:32 */ + assign n596_o = in_a_s[4]; + /* alu.vhd:334:44 */ + assign n597_o = in_b_s[4]; + /* alu.vhd:334:36 */ + assign n598_o = {n596_o, n597_o}; + /* alu.vhd:339:20 */ + assign n599_o = n595_o[4]; + /* alu.vhd:339:9 */ + assign n602_o = n599_o ? 1'b1 : 1'b0; + /* alu.vhd:338:7 */ + assign n604_o = n598_o == 2'b00; + /* alu.vhd:338:17 */ + assign n606_o = n598_o == 2'b11; + /* alu.vhd:338:17 */ + assign n607_o = n604_o | n606_o; + /* alu.vhd:344:20 */ + assign n608_o = n595_o[4]; + /* alu.vhd:344:24 */ + assign n609_o = ~n608_o; + /* alu.vhd:344:9 */ + assign n612_o = n609_o ? 1'b1 : 1'b0; + /* alu.vhd:343:7 */ + assign n614_o = n598_o == 2'b01; + /* alu.vhd:343:17 */ + assign n616_o = n598_o == 2'b10; + /* alu.vhd:343:17 */ + assign n617_o = n614_o | n616_o; + /* t48_core.vhd:87:5 */ + assign n618_o = {n617_o, n607_o}; + /* alu.vhd:337:5 */ + always @* + case (n618_o) + 2'b10: n620_o = n612_o; + 2'b01: n620_o = n602_o; + default: n620_o = 1'b0; + endcase + /* alu.vhd:389:35 */ + assign n627_o = accu_shadow_q[7:4]; + /* alu.vhd:391:35 */ + assign n628_o = accu_shadow_q[3:0]; + /* alu.vhd:388:5 */ + assign n629_o = da_high_i ? n627_o : n628_o; + /* alu.vhd:373:9 */ + assign n637_o = n629_o == 4'b1010; + /* alu.vhd:373:21 */ + assign n639_o = n629_o == 4'b1011; + /* alu.vhd:373:21 */ + assign n640_o = n637_o | n639_o; + /* alu.vhd:374:21 */ + assign n642_o = n629_o == 4'b1100; + /* alu.vhd:374:21 */ + assign n643_o = n640_o | n642_o; + /* alu.vhd:375:21 */ + assign n645_o = n629_o == 4'b1101; + /* alu.vhd:375:21 */ + assign n646_o = n643_o | n645_o; + /* alu.vhd:376:21 */ + assign n648_o = n629_o == 4'b1110; + /* alu.vhd:376:21 */ + assign n649_o = n646_o | n648_o; + /* alu.vhd:377:21 */ + assign n651_o = n629_o == 4'b1111; + /* alu.vhd:377:21 */ + assign n652_o = n649_o | n651_o; + /* alu.vhd:372:7 */ + always @* + case (n652_o) + 1'b1: n655_o = 1'b1; + default: n655_o = 1'b0; + endcase + /* alu.vhd:412:13 */ + assign n658_o = read_alu_i ? data_s : 8'b11111111; + /* alu.vhd:127:5 */ + assign n660_o = n433_o ? n425_o : accumulator_q; + /* alu.vhd:127:5 */ + always @(posedge clk_i or posedge n417_o) + if (n417_o) + n661_q <= 8'b00000000; + else + n661_q <= n660_o; + /* alu.vhd:127:5 */ + assign n662_o = en_clk_i ? n427_o : accu_shadow_q; + /* alu.vhd:127:5 */ + always @(posedge clk_i or posedge n417_o) + if (n417_o) + n663_q <= 8'b00000000; + else + n663_q <= n662_o; + /* alu.vhd:127:5 */ + assign n664_o = en_clk_i ? n432_o : temp_req_q; + /* alu.vhd:127:5 */ + always @(posedge clk_i or posedge n417_o) + if (n417_o) + n665_q <= 8'b00000000; + else + n665_q <= n664_o; + /* alu.vhd:122:5 */ + assign n666_o = {n555_o, n541_o, n526_o, n511_o}; +endmodule + +module t48_core + (input xtal_i, + input xtal_en_i, + input reset_i, + input t0_i, + input int_n_i, + input ea_i, + input [7:0] db_i, + input t1_i, + input [7:0] p2_i, + input [7:0] p1_i, + input clk_i, + input en_clk_i, + input [7:0] dmem_data_i, + input [7:0] pmem_data_i, + output t0_o, + output t0_dir_o, + output rd_n_o, + output psen_n_o, + output wr_n_o, + output ale_o, + output [7:0] db_o, + output db_dir_o, + output [7:0] p2_o, + output p2l_low_imp_o, + output p2h_low_imp_o, + output [7:0] p1_o, + output p1_low_imp_o, + output prog_n_o, + output xtal3_o, + output [7:0] dmem_addr_o, + output dmem_we_o, + output [7:0] dmem_data_o, + output [11:0] pmem_addr_o); + wire [7:0] t48_data_s; + wire xtal_en_s; + wire en_clk_s; + wire t0_s; + wire t1_s; + wire [7:0] alu_data_s; + wire alu_write_accu_s; + wire alu_write_shadow_s; + wire alu_write_temp_reg_s; + wire alu_read_alu_s; + wire alu_carry_s; + wire alu_aux_carry_s; + wire [3:0] alu_op_s; + wire alu_use_carry_s; + wire alu_da_high_s; + wire alu_da_overflow_s; + wire alu_accu_low_s; + wire alu_p06_temp_reg_s; + wire alu_p60_temp_reg_s; + wire bus_write_bus_s; + wire bus_read_bus_s; + wire bus_output_pcl_s; + wire bus_bidir_bus_s; + wire [7:0] bus_data_s; + wire clk_multi_cycle_s; + wire clk_assert_psen_s; + wire clk_assert_prog_s; + wire clk_assert_rd_s; + wire clk_assert_wr_s; + wire [2:0] clk_mstate_s; + wire clk_second_cycle_s; + wire psen_s; + wire prog_s; + wire rd_s; + wire wr_s; + wire ale_s; + wire xtal3_s; + wire cnd_compute_take_s; + wire [3:0] cnd_branch_cond_s; + wire cnd_take_branch_s; + wire [2:0] cnd_comp_value_s; + wire cnd_f1_s; + wire cnd_tf_s; + wire dm_write_dmem_addr_s; + wire dm_write_dmem_s; + wire dm_read_dmem_s; + wire [1:0] dm_addr_type_s; + wire [7:0] dm_data_s; + wire [7:0] dec_data_s; + wire p1_write_p1_s; + wire p1_read_p1_s; + wire p1_read_reg_s; + wire [7:0] p1_data_s; + wire p2_write_p2_s; + wire p2_write_exp_s; + wire p2_read_p2_s; + wire p2_read_reg_s; + wire p2_read_exp_s; + wire p2_output_pch_s; + wire [7:0] p2_data_s; + wire pm_write_pcl_s; + wire pm_read_pcl_s; + wire pm_write_pch_s; + wire pm_read_pch_s; + wire pm_read_pmem_s; + wire pm_inc_pc_s; + wire pm_write_pmem_addr_s; + wire [7:0] pm_data_s; + wire [1:0] pm_addr_type_s; + wire [11:0] pmem_addr_s; + wire psw_read_psw_s; + wire psw_read_sp_s; + wire psw_write_psw_s; + wire psw_write_sp_s; + wire psw_carry_s; + wire psw_aux_carry_s; + wire psw_f0_s; + wire psw_bs_s; + wire psw_special_data_s; + wire psw_inc_stackp_s; + wire psw_dec_stackp_s; + wire psw_write_carry_s; + wire psw_write_aux_carry_s; + wire psw_write_f0_s; + wire psw_write_bs_s; + wire [7:0] psw_data_s; + wire tim_overflow_s; + wire tim_of_s; + wire tim_read_timer_s; + wire tim_write_timer_s; + wire tim_start_t_s; + wire tim_start_cnt_s; + wire tim_stop_tcnt_s; + wire [7:0] tim_data_s; + wire n26_o; + wire n34_o; + wire [7:0] alu_b_n35; + wire alu_b_n36; + wire alu_b_n37; + wire alu_b_n38; + wire [7:0] alu_b_data_o; + wire alu_b_carry_o; + wire alu_b_aux_carry_o; + wire alu_b_da_overflow_o; + wire [7:0] bus_mux_b_n47; + wire [7:0] bus_mux_b_data_o; + wire clock_ctrl_b_n50; + wire clock_ctrl_b_n51; + wire [2:0] clock_ctrl_b_n52; + wire clock_ctrl_b_n53; + wire clock_ctrl_b_n54; + wire clock_ctrl_b_n55; + wire clock_ctrl_b_n56; + wire clock_ctrl_b_n57; + wire clock_ctrl_b_n58; + wire clock_ctrl_b_xtal3_o; + wire clock_ctrl_b_t0_o; + wire [2:0] clock_ctrl_b_mstate_o; + wire clock_ctrl_b_second_cycle_o; + wire clock_ctrl_b_ale_o; + wire clock_ctrl_b_psen_o; + wire clock_ctrl_b_prog_o; + wire clock_ctrl_b_rd_o; + wire clock_ctrl_b_wr_o; + wire cond_branch_b_n77; + localparam n78_o = 1'b0; + localparam n79_o = 1'b0; + wire cond_branch_b_take_branch_o; + wire [7:0] use_db_bus_db_bus_b_n82; + wire [7:0] n83_o; + wire [7:0] use_db_bus_db_bus_b_n84; + wire use_db_bus_db_bus_b_n85; + wire [7:0] use_db_bus_db_bus_b_data_o; + wire [7:0] use_db_bus_db_bus_b_db_o; + wire use_db_bus_db_bus_b_db_dir_o; + wire decoder_b_n92; + wire [7:0] decoder_b_n93; + wire decoder_b_n94; + wire decoder_b_n95; + wire decoder_b_n96; + wire decoder_b_n97; + wire decoder_b_n98; + wire decoder_b_n99; + localparam n100_o = 1'b0; + localparam n101_o = 1'b0; + wire decoder_b_n106; + wire decoder_b_n107; + wire decoder_b_n108; + wire decoder_b_n109; + wire decoder_b_n110; + wire decoder_b_n111; + wire decoder_b_n112; + wire decoder_b_n113; + wire decoder_b_n114; + wire decoder_b_n115; + wire decoder_b_n116; + wire decoder_b_n117; + wire decoder_b_n118; + wire decoder_b_n119; + wire decoder_b_n120; + wire decoder_b_n121; + wire decoder_b_n122; + wire [3:0] decoder_b_n123; + wire decoder_b_n124; + wire decoder_b_n125; + wire decoder_b_n126; + wire decoder_b_n127; + wire decoder_b_n128; + wire decoder_b_n129; + wire decoder_b_n130; + wire decoder_b_n131; + wire decoder_b_n132; + wire decoder_b_n133; + wire decoder_b_n134; + wire decoder_b_n135; + wire decoder_b_n136; + wire [3:0] decoder_b_n137; + wire [2:0] decoder_b_n138; + wire decoder_b_n139; + wire decoder_b_n140; + wire [1:0] decoder_b_n141; + wire decoder_b_n142; + wire decoder_b_n143; + wire decoder_b_n144; + wire decoder_b_n145; + wire decoder_b_n146; + wire decoder_b_n147; + wire decoder_b_n148; + wire decoder_b_n149; + wire decoder_b_n150; + wire decoder_b_n151; + wire decoder_b_n152; + wire [1:0] decoder_b_n153; + wire decoder_b_n154; + wire decoder_b_n155; + wire decoder_b_n156; + wire decoder_b_n157; + wire decoder_b_n158; + wire decoder_b_n159; + wire decoder_b_n160; + wire decoder_b_t0_dir_o; + wire [7:0] decoder_b_data_o; + wire decoder_b_alu_write_accu_o; + wire decoder_b_alu_write_shadow_o; + wire decoder_b_alu_write_temp_reg_o; + wire decoder_b_alu_read_alu_o; + wire decoder_b_bus_write_bus_o; + wire decoder_b_bus_read_bus_o; + wire decoder_b_bus_ibf_int_o; + wire decoder_b_bus_en_dma_o; + wire decoder_b_bus_en_flags_o; + wire decoder_b_bus_write_sts_o; + wire decoder_b_dm_write_dmem_addr_o; + wire decoder_b_dm_write_dmem_o; + wire decoder_b_dm_read_dmem_o; + wire decoder_b_p1_write_p1_o; + wire decoder_b_p1_read_p1_o; + wire decoder_b_p2_write_p2_o; + wire decoder_b_p2_write_exp_o; + wire decoder_b_p2_read_p2_o; + wire decoder_b_p2_read_exp_o; + wire decoder_b_pm_write_pcl_o; + wire decoder_b_pm_read_pcl_o; + wire decoder_b_pm_write_pch_o; + wire decoder_b_pm_read_pch_o; + wire decoder_b_pm_read_pmem_o; + wire decoder_b_psw_read_psw_o; + wire decoder_b_psw_read_sp_o; + wire decoder_b_psw_write_psw_o; + wire decoder_b_psw_write_sp_o; + wire [3:0] decoder_b_alu_op_o; + wire decoder_b_alu_use_carry_o; + wire decoder_b_alu_da_high_o; + wire decoder_b_alu_accu_low_o; + wire decoder_b_alu_p06_temp_reg_o; + wire decoder_b_alu_p60_temp_reg_o; + wire decoder_b_bus_output_pcl_o; + wire decoder_b_bus_bidir_bus_o; + wire decoder_b_clk_multi_cycle_o; + wire decoder_b_clk_assert_psen_o; + wire decoder_b_clk_assert_prog_o; + wire decoder_b_clk_assert_rd_o; + wire decoder_b_clk_assert_wr_o; + wire decoder_b_cnd_compute_take_o; + wire [3:0] decoder_b_cnd_branch_cond_o; + wire [2:0] decoder_b_cnd_comp_value_o; + wire decoder_b_cnd_f1_o; + wire decoder_b_cnd_tf_o; + wire [1:0] decoder_b_dm_addr_type_o; + wire decoder_b_p1_read_reg_o; + wire decoder_b_p2_read_reg_o; + wire decoder_b_p2_output_pch_o; + wire decoder_b_pm_inc_pc_o; + wire decoder_b_pm_write_pmem_addr_o; + wire [1:0] decoder_b_pm_addr_type_o; + wire decoder_b_psw_special_data_o; + wire decoder_b_psw_inc_stackp_o; + wire decoder_b_psw_dec_stackp_o; + wire decoder_b_psw_write_carry_o; + wire decoder_b_psw_write_aux_carry_o; + wire decoder_b_psw_write_f0_o; + wire decoder_b_psw_write_bs_o; + wire decoder_b_tim_read_timer_o; + wire decoder_b_tim_write_timer_o; + wire decoder_b_tim_start_t_o; + wire decoder_b_tim_start_cnt_o; + wire decoder_b_tim_stop_tcnt_o; + wire [7:0] dmem_ctrl_b_n291; + wire [7:0] dmem_ctrl_b_n292; + wire dmem_ctrl_b_n293; + wire [7:0] dmem_ctrl_b_n294; + wire [7:0] dmem_ctrl_b_data_o; + wire [7:0] dmem_ctrl_b_dmem_addr_o; + wire dmem_ctrl_b_dmem_we_o; + wire [7:0] dmem_ctrl_b_dmem_data_o; + wire [7:0] use_timer_timer_b_n303; + wire use_timer_timer_b_n304; + wire [7:0] use_timer_timer_b_data_o; + wire use_timer_timer_b_overflow_o; + wire n316_o; + wire [7:0] use_p1_p1_b_n317; + wire [7:0] use_p1_p1_b_n318; + wire use_p1_p1_b_n319; + wire [7:0] use_p1_p1_b_data_o; + wire [7:0] use_p1_p1_b_p1_o; + wire use_p1_p1_b_p1_low_imp_o; + wire [7:0] use_p2_p2_b_n326; + wire [3:0] n327_o; + wire [7:0] use_p2_p2_b_n328; + wire use_p2_p2_b_n329; + wire use_p2_p2_b_n330; + wire [7:0] use_p2_p2_b_data_o; + wire [7:0] use_p2_p2_b_p2_o; + wire use_p2_p2_b_p2l_low_imp_o; + wire use_p2_p2_b_p2h_low_imp_o; + wire [7:0] pmem_ctrl_b_n339; + wire [11:0] pmem_ctrl_b_n340; + wire [7:0] pmem_ctrl_b_data_o; + wire [11:0] pmem_ctrl_b_pmem_addr_o; + wire [7:0] psw_b_n345; + wire psw_b_n346; + wire psw_b_n347; + wire psw_b_n348; + wire psw_b_n349; + wire [7:0] psw_b_data_o; + wire psw_b_carry_o; + wire psw_b_aux_carry_o; + wire psw_b_f0_o; + wire psw_b_bs_o; + wire n367_o; + wire n369_o; + wire n376_o; + wire n378_o; + wire n385_o; + wire n387_o; + wire n394_o; + wire n396_o; + wire n403_o; + wire n411_o; + assign t0_o = clock_ctrl_b_n51; + assign t0_dir_o = decoder_b_n92; + assign rd_n_o = n394_o; + assign psen_n_o = n376_o; + assign wr_n_o = n403_o; + assign ale_o = n367_o; + assign db_o = use_db_bus_db_bus_b_n84; + assign db_dir_o = use_db_bus_db_bus_b_n85; + assign p2_o = use_p2_p2_b_n328; + assign p2l_low_imp_o = use_p2_p2_b_n329; + assign p2h_low_imp_o = use_p2_p2_b_n330; + assign p1_o = use_p1_p1_b_n318; + assign p1_low_imp_o = use_p1_p1_b_n319; + assign prog_n_o = n385_o; + assign xtal3_o = n411_o; + assign dmem_addr_o = dmem_ctrl_b_n292; + assign dmem_we_o = dmem_ctrl_b_n293; + assign dmem_data_o = dmem_ctrl_b_n294; + assign pmem_addr_o = pmem_addr_s; + /* t48_core.vhd:136:10 */ + assign t48_data_s = bus_mux_b_n47; // (signal) + /* t48_core.vhd:138:10 */ + assign xtal_en_s = n26_o; // (signal) + /* t48_core.vhd:139:10 */ + assign en_clk_s = n34_o; // (signal) + /* t48_core.vhd:141:10 */ + assign t0_s = t0_i; // (signal) + /* t48_core.vhd:141:16 */ + assign t1_s = t1_i; // (signal) + /* t48_core.vhd:144:10 */ + assign alu_data_s = alu_b_n35; // (signal) + /* t48_core.vhd:145:10 */ + assign alu_write_accu_s = decoder_b_n94; // (signal) + /* t48_core.vhd:146:10 */ + assign alu_write_shadow_s = decoder_b_n95; // (signal) + /* t48_core.vhd:147:10 */ + assign alu_write_temp_reg_s = decoder_b_n96; // (signal) + /* t48_core.vhd:148:10 */ + assign alu_read_alu_s = decoder_b_n97; // (signal) + /* t48_core.vhd:149:10 */ + assign alu_carry_s = alu_b_n36; // (signal) + /* t48_core.vhd:150:10 */ + assign alu_aux_carry_s = alu_b_n37; // (signal) + /* t48_core.vhd:151:10 */ + assign alu_op_s = decoder_b_n123; // (signal) + /* t48_core.vhd:152:10 */ + assign alu_use_carry_s = decoder_b_n128; // (signal) + /* t48_core.vhd:153:10 */ + assign alu_da_high_s = decoder_b_n124; // (signal) + /* t48_core.vhd:154:10 */ + assign alu_da_overflow_s = alu_b_n38; // (signal) + /* t48_core.vhd:155:10 */ + assign alu_accu_low_s = decoder_b_n125; // (signal) + /* t48_core.vhd:156:10 */ + assign alu_p06_temp_reg_s = decoder_b_n126; // (signal) + /* t48_core.vhd:157:10 */ + assign alu_p60_temp_reg_s = decoder_b_n127; // (signal) + /* t48_core.vhd:160:10 */ + assign bus_write_bus_s = decoder_b_n98; // (signal) + /* t48_core.vhd:161:10 */ + assign bus_read_bus_s = decoder_b_n99; // (signal) + /* t48_core.vhd:162:10 */ + assign bus_output_pcl_s = decoder_b_n129; // (signal) + /* t48_core.vhd:163:10 */ + assign bus_bidir_bus_s = decoder_b_n130; // (signal) + /* t48_core.vhd:164:10 */ + assign bus_data_s = use_db_bus_db_bus_b_n82; // (signal) + /* t48_core.vhd:167:10 */ + assign clk_multi_cycle_s = decoder_b_n131; // (signal) + /* t48_core.vhd:168:10 */ + assign clk_assert_psen_s = decoder_b_n132; // (signal) + /* t48_core.vhd:169:10 */ + assign clk_assert_prog_s = decoder_b_n133; // (signal) + /* t48_core.vhd:170:10 */ + assign clk_assert_rd_s = decoder_b_n134; // (signal) + /* t48_core.vhd:171:10 */ + assign clk_assert_wr_s = decoder_b_n135; // (signal) + /* t48_core.vhd:172:10 */ + assign clk_mstate_s = clock_ctrl_b_n52; // (signal) + /* t48_core.vhd:173:10 */ + assign clk_second_cycle_s = clock_ctrl_b_n53; // (signal) + /* t48_core.vhd:174:10 */ + assign psen_s = clock_ctrl_b_n55; // (signal) + /* t48_core.vhd:175:10 */ + assign prog_s = clock_ctrl_b_n56; // (signal) + /* t48_core.vhd:176:10 */ + assign rd_s = clock_ctrl_b_n57; // (signal) + /* t48_core.vhd:177:10 */ + assign wr_s = clock_ctrl_b_n58; // (signal) + /* t48_core.vhd:178:10 */ + assign ale_s = clock_ctrl_b_n54; // (signal) + /* t48_core.vhd:179:10 */ + assign xtal3_s = clock_ctrl_b_n50; // (signal) + /* t48_core.vhd:182:10 */ + assign cnd_compute_take_s = decoder_b_n136; // (signal) + /* t48_core.vhd:183:10 */ + assign cnd_branch_cond_s = decoder_b_n137; // (signal) + /* t48_core.vhd:184:10 */ + assign cnd_take_branch_s = cond_branch_b_n77; // (signal) + /* t48_core.vhd:185:10 */ + assign cnd_comp_value_s = decoder_b_n138; // (signal) + /* t48_core.vhd:186:10 */ + assign cnd_f1_s = decoder_b_n139; // (signal) + /* t48_core.vhd:187:10 */ + assign cnd_tf_s = decoder_b_n140; // (signal) + /* t48_core.vhd:190:10 */ + assign dm_write_dmem_addr_s = decoder_b_n106; // (signal) + /* t48_core.vhd:191:10 */ + assign dm_write_dmem_s = decoder_b_n107; // (signal) + /* t48_core.vhd:192:10 */ + assign dm_read_dmem_s = decoder_b_n108; // (signal) + /* t48_core.vhd:193:10 */ + assign dm_addr_type_s = decoder_b_n141; // (signal) + /* t48_core.vhd:194:10 */ + assign dm_data_s = dmem_ctrl_b_n291; // (signal) + /* t48_core.vhd:197:10 */ + assign dec_data_s = decoder_b_n93; // (signal) + /* t48_core.vhd:200:10 */ + assign p1_write_p1_s = decoder_b_n109; // (signal) + /* t48_core.vhd:201:10 */ + assign p1_read_p1_s = decoder_b_n110; // (signal) + /* t48_core.vhd:202:10 */ + assign p1_read_reg_s = decoder_b_n147; // (signal) + /* t48_core.vhd:203:10 */ + assign p1_data_s = use_p1_p1_b_n317; // (signal) + /* t48_core.vhd:206:10 */ + assign p2_write_p2_s = decoder_b_n111; // (signal) + /* t48_core.vhd:207:10 */ + assign p2_write_exp_s = decoder_b_n112; // (signal) + /* t48_core.vhd:208:10 */ + assign p2_read_p2_s = decoder_b_n113; // (signal) + /* t48_core.vhd:209:10 */ + assign p2_read_reg_s = decoder_b_n148; // (signal) + /* t48_core.vhd:210:10 */ + assign p2_read_exp_s = decoder_b_n149; // (signal) + /* t48_core.vhd:211:10 */ + assign p2_output_pch_s = decoder_b_n150; // (signal) + /* t48_core.vhd:212:10 */ + assign p2_data_s = use_p2_p2_b_n326; // (signal) + /* t48_core.vhd:215:10 */ + assign pm_write_pcl_s = decoder_b_n114; // (signal) + /* t48_core.vhd:216:10 */ + assign pm_read_pcl_s = decoder_b_n115; // (signal) + /* t48_core.vhd:217:10 */ + assign pm_write_pch_s = decoder_b_n116; // (signal) + /* t48_core.vhd:218:10 */ + assign pm_read_pch_s = decoder_b_n117; // (signal) + /* t48_core.vhd:219:10 */ + assign pm_read_pmem_s = decoder_b_n118; // (signal) + /* t48_core.vhd:220:10 */ + assign pm_inc_pc_s = decoder_b_n151; // (signal) + /* t48_core.vhd:221:10 */ + assign pm_write_pmem_addr_s = decoder_b_n152; // (signal) + /* t48_core.vhd:222:10 */ + assign pm_data_s = pmem_ctrl_b_n339; // (signal) + /* t48_core.vhd:223:10 */ + assign pm_addr_type_s = decoder_b_n153; // (signal) + /* t48_core.vhd:224:10 */ + assign pmem_addr_s = pmem_ctrl_b_n340; // (signal) + /* t48_core.vhd:227:10 */ + assign psw_read_psw_s = decoder_b_n119; // (signal) + /* t48_core.vhd:228:10 */ + assign psw_read_sp_s = decoder_b_n120; // (signal) + /* t48_core.vhd:229:10 */ + assign psw_write_psw_s = decoder_b_n121; // (signal) + /* t48_core.vhd:230:10 */ + assign psw_write_sp_s = decoder_b_n122; // (signal) + /* t48_core.vhd:231:10 */ + assign psw_carry_s = psw_b_n346; // (signal) + /* t48_core.vhd:232:10 */ + assign psw_aux_carry_s = psw_b_n347; // (signal) + /* t48_core.vhd:233:10 */ + assign psw_f0_s = psw_b_n348; // (signal) + /* t48_core.vhd:234:10 */ + assign psw_bs_s = psw_b_n349; // (signal) + /* t48_core.vhd:235:10 */ + assign psw_special_data_s = decoder_b_n154; // (signal) + /* t48_core.vhd:236:10 */ + assign psw_inc_stackp_s = decoder_b_n155; // (signal) + /* t48_core.vhd:237:10 */ + assign psw_dec_stackp_s = decoder_b_n156; // (signal) + /* t48_core.vhd:238:10 */ + assign psw_write_carry_s = decoder_b_n157; // (signal) + /* t48_core.vhd:239:10 */ + assign psw_write_aux_carry_s = decoder_b_n158; // (signal) + /* t48_core.vhd:240:10 */ + assign psw_write_f0_s = decoder_b_n159; // (signal) + /* t48_core.vhd:241:10 */ + assign psw_write_bs_s = decoder_b_n160; // (signal) + /* t48_core.vhd:242:10 */ + assign psw_data_s = psw_b_n345; // (signal) + /* t48_core.vhd:245:10 */ + assign tim_overflow_s = n316_o; // (signal) + /* t48_core.vhd:246:10 */ + assign tim_of_s = use_timer_timer_b_n304; // (signal) + /* t48_core.vhd:247:10 */ + assign tim_read_timer_s = decoder_b_n142; // (signal) + /* t48_core.vhd:248:10 */ + assign tim_write_timer_s = decoder_b_n143; // (signal) + /* t48_core.vhd:249:10 */ + assign tim_start_t_s = decoder_b_n144; // (signal) + /* t48_core.vhd:250:10 */ + assign tim_start_cnt_s = decoder_b_n145; // (signal) + /* t48_core.vhd:251:10 */ + assign tim_stop_tcnt_s = decoder_b_n146; // (signal) + /* t48_core.vhd:252:10 */ + assign tim_data_s = use_timer_timer_b_n303; // (signal) + /* t48_pack-p.vhd:75:5 */ + assign n26_o = xtal_en_i ? 1'b1 : 1'b0; + /* t48_pack-p.vhd:75:5 */ + assign n34_o = en_clk_i ? 1'b1 : 1'b0; + /* t48_core.vhd:290:29 */ + assign alu_b_n35 = alu_b_data_o; // (signal) + /* t48_core.vhd:296:29 */ + assign alu_b_n36 = alu_b_carry_o; // (signal) + /* t48_core.vhd:297:29 */ + assign alu_b_n37 = alu_b_aux_carry_o; // (signal) + /* t48_core.vhd:301:29 */ + assign alu_b_n38 = alu_b_da_overflow_o; // (signal) + /* t48_core.vhd:284:3 */ + t48_alu alu_b ( + .clk_i(clk_i), + .res_i(reset_i), + .en_clk_i(en_clk_s), + .data_i(t48_data_s), + .write_accu_i(alu_write_accu_s), + .write_shadow_i(alu_write_shadow_s), + .write_temp_reg_i(alu_write_temp_reg_s), + .read_alu_i(alu_read_alu_s), + .carry_i(psw_carry_s), + .alu_op_i(alu_op_s), + .use_carry_i(alu_use_carry_s), + .da_high_i(alu_da_high_s), + .accu_low_i(alu_accu_low_s), + .p06_temp_reg_i(alu_p06_temp_reg_s), + .p60_temp_reg_i(alu_p60_temp_reg_s), + .data_o(alu_b_data_o), + .carry_o(alu_b_carry_o), + .aux_carry_o(alu_b_aux_carry_o), + .da_overflow_o(alu_b_da_overflow_o)); + /* t48_core.vhd:318:21 */ + assign bus_mux_b_n47 = bus_mux_b_data_o; // (signal) + /* t48_core.vhd:307:3 */ + t48_bus_mux bus_mux_b ( + .alu_data_i(alu_data_s), + .bus_data_i(bus_data_s), + .dec_data_i(dec_data_s), + .dm_data_i(dm_data_s), + .pm_data_i(pm_data_s), + .p1_data_i(p1_data_s), + .p2_data_i(p2_data_s), + .psw_data_i(psw_data_s), + .tim_data_i(tim_data_s), + .data_o(bus_mux_b_data_o)); + /* t48_core.vhd:331:25 */ + assign clock_ctrl_b_n50 = clock_ctrl_b_xtal3_o; // (signal) + /* t48_core.vhd:332:25 */ + assign clock_ctrl_b_n51 = clock_ctrl_b_t0_o; // (signal) + /* t48_core.vhd:338:25 */ + assign clock_ctrl_b_n52 = clock_ctrl_b_mstate_o; // (signal) + /* t48_core.vhd:339:25 */ + assign clock_ctrl_b_n53 = clock_ctrl_b_second_cycle_o; // (signal) + /* t48_core.vhd:340:25 */ + assign clock_ctrl_b_n54 = clock_ctrl_b_ale_o; // (signal) + /* t48_core.vhd:341:25 */ + assign clock_ctrl_b_n55 = clock_ctrl_b_psen_o; // (signal) + /* t48_core.vhd:342:25 */ + assign clock_ctrl_b_n56 = clock_ctrl_b_prog_o; // (signal) + /* t48_core.vhd:343:25 */ + assign clock_ctrl_b_n57 = clock_ctrl_b_rd_o; // (signal) + /* t48_core.vhd:344:25 */ + assign clock_ctrl_b_n58 = clock_ctrl_b_wr_o; // (signal) + /* t48_core.vhd:321:3 */ + t48_clock_ctrl_1 clock_ctrl_b ( + .clk_i(clk_i), + .xtal_i(xtal_i), + .xtal_en_i(xtal_en_s), + .res_i(reset_i), + .en_clk_i(en_clk_s), + .multi_cycle_i(clk_multi_cycle_s), + .assert_psen_i(clk_assert_psen_s), + .assert_prog_i(clk_assert_prog_s), + .assert_rd_i(clk_assert_rd_s), + .assert_wr_i(clk_assert_wr_s), + .xtal3_o(clock_ctrl_b_xtal3_o), + .t0_o(clock_ctrl_b_t0_o), + .mstate_o(clock_ctrl_b_mstate_o), + .second_cycle_o(clock_ctrl_b_second_cycle_o), + .ale_o(clock_ctrl_b_ale_o), + .psen_o(clock_ctrl_b_psen_o), + .prog_o(clock_ctrl_b_prog_o), + .rd_o(clock_ctrl_b_rd_o), + .wr_o(clock_ctrl_b_wr_o)); + /* t48_core.vhd:354:25 */ + assign cond_branch_b_n77 = cond_branch_b_take_branch_o; // (signal) + /* t48_core.vhd:347:3 */ + t48_cond_branch cond_branch_b ( + .clk_i(clk_i), + .res_i(reset_i), + .en_clk_i(en_clk_s), + .compute_take_i(cnd_compute_take_s), + .branch_cond_i(cnd_branch_cond_s), + .accu_i(alu_data_s), + .t0_i(t0_s), + .t1_i(t1_s), + .int_n_i(int_n_i), + .f0_i(psw_f0_s), + .f1_i(cnd_f1_s), + .tf_i(cnd_tf_s), + .carry_i(psw_carry_s), + .ibf_i(n78_o), + .obf_i(n79_o), + .comp_value_i(cnd_comp_value_s), + .take_branch_o(cond_branch_b_take_branch_o)); + /* t48_core.vhd:374:25 */ + assign use_db_bus_db_bus_b_n82 = use_db_bus_db_bus_b_data_o; // (signal) + /* t48_core.vhd:379:36 */ + assign n83_o = pmem_addr_s[7:0]; + /* t48_core.vhd:381:25 */ + assign use_db_bus_db_bus_b_n84 = use_db_bus_db_bus_b_db_o; // (signal) + /* t48_core.vhd:382:25 */ + assign use_db_bus_db_bus_b_n85 = use_db_bus_db_bus_b_db_dir_o; // (signal) + /* t48_core.vhd:367:5 */ + t48_db_bus use_db_bus_db_bus_b ( + .clk_i(clk_i), + .res_i(reset_i), + .en_clk_i(en_clk_s), + .ea_i(ea_i), + .data_i(t48_data_s), + .write_bus_i(bus_write_bus_s), + .read_bus_i(bus_read_bus_s), + .output_pcl_i(bus_output_pcl_s), + .bidir_bus_i(bus_bidir_bus_s), + .pcl_i(n83_o), + .db_i(db_i), + .data_o(use_db_bus_db_bus_b_data_o), + .db_o(use_db_bus_db_bus_b_db_o), + .db_dir_o(use_db_bus_db_bus_b_db_dir_o)); + /* t48_core.vhd:405:33 */ + assign decoder_b_n92 = decoder_b_t0_dir_o; // (signal) + /* t48_core.vhd:407:33 */ + assign decoder_b_n93 = decoder_b_data_o; // (signal) + /* t48_core.vhd:408:33 */ + assign decoder_b_n94 = decoder_b_alu_write_accu_o; // (signal) + /* t48_core.vhd:409:33 */ + assign decoder_b_n95 = decoder_b_alu_write_shadow_o; // (signal) + /* t48_core.vhd:410:33 */ + assign decoder_b_n96 = decoder_b_alu_write_temp_reg_o; // (signal) + /* t48_core.vhd:411:33 */ + assign decoder_b_n97 = decoder_b_alu_read_alu_o; // (signal) + /* t48_core.vhd:412:33 */ + assign decoder_b_n98 = decoder_b_bus_write_bus_o; // (signal) + /* t48_core.vhd:413:33 */ + assign decoder_b_n99 = decoder_b_bus_read_bus_o; // (signal) + /* t48_core.vhd:414:33 */ + assign decoder_b_n106 = decoder_b_dm_write_dmem_addr_o; // (signal) + /* t48_core.vhd:415:33 */ + assign decoder_b_n107 = decoder_b_dm_write_dmem_o; // (signal) + /* t48_core.vhd:416:33 */ + assign decoder_b_n108 = decoder_b_dm_read_dmem_o; // (signal) + /* t48_core.vhd:417:33 */ + assign decoder_b_n109 = decoder_b_p1_write_p1_o; // (signal) + /* t48_core.vhd:418:33 */ + assign decoder_b_n110 = decoder_b_p1_read_p1_o; // (signal) + /* t48_core.vhd:420:33 */ + assign decoder_b_n111 = decoder_b_p2_write_p2_o; // (signal) + /* t48_core.vhd:421:33 */ + assign decoder_b_n112 = decoder_b_p2_write_exp_o; // (signal) + /* t48_core.vhd:422:33 */ + assign decoder_b_n113 = decoder_b_p2_read_p2_o; // (signal) + /* t48_core.vhd:419:33 */ + assign decoder_b_n114 = decoder_b_pm_write_pcl_o; // (signal) + /* t48_core.vhd:423:33 */ + assign decoder_b_n115 = decoder_b_pm_read_pcl_o; // (signal) + /* t48_core.vhd:424:33 */ + assign decoder_b_n116 = decoder_b_pm_write_pch_o; // (signal) + /* t48_core.vhd:425:33 */ + assign decoder_b_n117 = decoder_b_pm_read_pch_o; // (signal) + /* t48_core.vhd:426:33 */ + assign decoder_b_n118 = decoder_b_pm_read_pmem_o; // (signal) + /* t48_core.vhd:427:33 */ + assign decoder_b_n119 = decoder_b_psw_read_psw_o; // (signal) + /* t48_core.vhd:428:33 */ + assign decoder_b_n120 = decoder_b_psw_read_sp_o; // (signal) + /* t48_core.vhd:429:33 */ + assign decoder_b_n121 = decoder_b_psw_write_psw_o; // (signal) + /* t48_core.vhd:430:33 */ + assign decoder_b_n122 = decoder_b_psw_write_sp_o; // (signal) + /* t48_core.vhd:432:33 */ + assign decoder_b_n123 = decoder_b_alu_op_o; // (signal) + /* t48_core.vhd:434:33 */ + assign decoder_b_n124 = decoder_b_alu_da_high_o; // (signal) + /* t48_core.vhd:436:33 */ + assign decoder_b_n125 = decoder_b_alu_accu_low_o; // (signal) + /* t48_core.vhd:437:33 */ + assign decoder_b_n126 = decoder_b_alu_p06_temp_reg_o; // (signal) + /* t48_core.vhd:438:33 */ + assign decoder_b_n127 = decoder_b_alu_p60_temp_reg_o; // (signal) + /* t48_core.vhd:433:33 */ + assign decoder_b_n128 = decoder_b_alu_use_carry_o; // (signal) + /* t48_core.vhd:439:33 */ + assign decoder_b_n129 = decoder_b_bus_output_pcl_o; // (signal) + /* t48_core.vhd:440:33 */ + assign decoder_b_n130 = decoder_b_bus_bidir_bus_o; // (signal) + /* t48_core.vhd:441:33 */ + assign decoder_b_n131 = decoder_b_clk_multi_cycle_o; // (signal) + /* t48_core.vhd:442:33 */ + assign decoder_b_n132 = decoder_b_clk_assert_psen_o; // (signal) + /* t48_core.vhd:443:33 */ + assign decoder_b_n133 = decoder_b_clk_assert_prog_o; // (signal) + /* t48_core.vhd:444:33 */ + assign decoder_b_n134 = decoder_b_clk_assert_rd_o; // (signal) + /* t48_core.vhd:445:33 */ + assign decoder_b_n135 = decoder_b_clk_assert_wr_o; // (signal) + /* t48_core.vhd:448:33 */ + assign decoder_b_n136 = decoder_b_cnd_compute_take_o; // (signal) + /* t48_core.vhd:449:33 */ + assign decoder_b_n137 = decoder_b_cnd_branch_cond_o; // (signal) + /* t48_core.vhd:451:33 */ + assign decoder_b_n138 = decoder_b_cnd_comp_value_o; // (signal) + /* t48_core.vhd:452:33 */ + assign decoder_b_n139 = decoder_b_cnd_f1_o; // (signal) + /* t48_core.vhd:453:33 */ + assign decoder_b_n140 = decoder_b_cnd_tf_o; // (signal) + /* t48_core.vhd:454:33 */ + assign decoder_b_n141 = decoder_b_dm_addr_type_o; // (signal) + /* t48_core.vhd:455:33 */ + assign decoder_b_n142 = decoder_b_tim_read_timer_o; // (signal) + /* t48_core.vhd:456:33 */ + assign decoder_b_n143 = decoder_b_tim_write_timer_o; // (signal) + /* t48_core.vhd:457:33 */ + assign decoder_b_n144 = decoder_b_tim_start_t_o; // (signal) + /* t48_core.vhd:458:33 */ + assign decoder_b_n145 = decoder_b_tim_start_cnt_o; // (signal) + /* t48_core.vhd:459:33 */ + assign decoder_b_n146 = decoder_b_tim_stop_tcnt_o; // (signal) + /* t48_core.vhd:460:33 */ + assign decoder_b_n147 = decoder_b_p1_read_reg_o; // (signal) + /* t48_core.vhd:461:33 */ + assign decoder_b_n148 = decoder_b_p2_read_reg_o; // (signal) + /* t48_core.vhd:462:33 */ + assign decoder_b_n149 = decoder_b_p2_read_exp_o; // (signal) + /* t48_core.vhd:463:33 */ + assign decoder_b_n150 = decoder_b_p2_output_pch_o; // (signal) + /* t48_core.vhd:464:33 */ + assign decoder_b_n151 = decoder_b_pm_inc_pc_o; // (signal) + /* t48_core.vhd:465:33 */ + assign decoder_b_n152 = decoder_b_pm_write_pmem_addr_o; // (signal) + /* t48_core.vhd:466:33 */ + assign decoder_b_n153 = decoder_b_pm_addr_type_o; // (signal) + /* t48_core.vhd:467:33 */ + assign decoder_b_n154 = decoder_b_psw_special_data_o; // (signal) + /* t48_core.vhd:471:33 */ + assign decoder_b_n155 = decoder_b_psw_inc_stackp_o; // (signal) + /* t48_core.vhd:472:33 */ + assign decoder_b_n156 = decoder_b_psw_dec_stackp_o; // (signal) + /* t48_core.vhd:473:33 */ + assign decoder_b_n157 = decoder_b_psw_write_carry_o; // (signal) + /* t48_core.vhd:474:33 */ + assign decoder_b_n158 = decoder_b_psw_write_aux_carry_o; // (signal) + /* t48_core.vhd:475:33 */ + assign decoder_b_n159 = decoder_b_psw_write_f0_o; // (signal) + /* t48_core.vhd:476:33 */ + assign decoder_b_n160 = decoder_b_psw_write_bs_o; // (signal) + /* t48_core.vhd:392:3 */ + t48_decoder_1_0_0 decoder_b ( + .clk_i(clk_i), + .res_i(reset_i), + .en_clk_i(en_clk_s), + .xtal_i(xtal_i), + .xtal_en_i(xtal_en_s), + .ea_i(ea_i), + .ale_i(ale_s), + .int_n_i(int_n_i), + .data_i(t48_data_s), + .bus_set_f1_i(n100_o), + .bus_clear_f1_i(n101_o), + .alu_carry_i(alu_carry_s), + .alu_da_overflow_i(alu_da_overflow_s), + .clk_mstate_i(clk_mstate_s), + .clk_second_cycle_i(clk_second_cycle_s), + .cnd_take_branch_i(cnd_take_branch_s), + .psw_carry_i(psw_carry_s), + .psw_aux_carry_i(psw_aux_carry_s), + .psw_f0_i(psw_f0_s), + .tim_overflow_i(tim_overflow_s), + .t0_dir_o(decoder_b_t0_dir_o), + .data_o(decoder_b_data_o), + .alu_write_accu_o(decoder_b_alu_write_accu_o), + .alu_write_shadow_o(decoder_b_alu_write_shadow_o), + .alu_write_temp_reg_o(decoder_b_alu_write_temp_reg_o), + .alu_read_alu_o(decoder_b_alu_read_alu_o), + .bus_write_bus_o(decoder_b_bus_write_bus_o), + .bus_read_bus_o(decoder_b_bus_read_bus_o), + .bus_ibf_int_o(), + .bus_en_dma_o(), + .bus_en_flags_o(), + .bus_write_sts_o(), + .dm_write_dmem_addr_o(decoder_b_dm_write_dmem_addr_o), + .dm_write_dmem_o(decoder_b_dm_write_dmem_o), + .dm_read_dmem_o(decoder_b_dm_read_dmem_o), + .p1_write_p1_o(decoder_b_p1_write_p1_o), + .p1_read_p1_o(decoder_b_p1_read_p1_o), + .p2_write_p2_o(decoder_b_p2_write_p2_o), + .p2_write_exp_o(decoder_b_p2_write_exp_o), + .p2_read_p2_o(decoder_b_p2_read_p2_o), + .p2_read_exp_o(decoder_b_p2_read_exp_o), + .pm_write_pcl_o(decoder_b_pm_write_pcl_o), + .pm_read_pcl_o(decoder_b_pm_read_pcl_o), + .pm_write_pch_o(decoder_b_pm_write_pch_o), + .pm_read_pch_o(decoder_b_pm_read_pch_o), + .pm_read_pmem_o(decoder_b_pm_read_pmem_o), + .psw_read_psw_o(decoder_b_psw_read_psw_o), + .psw_read_sp_o(decoder_b_psw_read_sp_o), + .psw_write_psw_o(decoder_b_psw_write_psw_o), + .psw_write_sp_o(decoder_b_psw_write_sp_o), + .alu_op_o(decoder_b_alu_op_o), + .alu_use_carry_o(decoder_b_alu_use_carry_o), + .alu_da_high_o(decoder_b_alu_da_high_o), + .alu_accu_low_o(decoder_b_alu_accu_low_o), + .alu_p06_temp_reg_o(decoder_b_alu_p06_temp_reg_o), + .alu_p60_temp_reg_o(decoder_b_alu_p60_temp_reg_o), + .bus_output_pcl_o(decoder_b_bus_output_pcl_o), + .bus_bidir_bus_o(decoder_b_bus_bidir_bus_o), + .clk_multi_cycle_o(decoder_b_clk_multi_cycle_o), + .clk_assert_psen_o(decoder_b_clk_assert_psen_o), + .clk_assert_prog_o(decoder_b_clk_assert_prog_o), + .clk_assert_rd_o(decoder_b_clk_assert_rd_o), + .clk_assert_wr_o(decoder_b_clk_assert_wr_o), + .cnd_compute_take_o(decoder_b_cnd_compute_take_o), + .cnd_branch_cond_o(decoder_b_cnd_branch_cond_o), + .cnd_comp_value_o(decoder_b_cnd_comp_value_o), + .cnd_f1_o(decoder_b_cnd_f1_o), + .cnd_tf_o(decoder_b_cnd_tf_o), + .dm_addr_type_o(decoder_b_dm_addr_type_o), + .p1_read_reg_o(decoder_b_p1_read_reg_o), + .p2_read_reg_o(decoder_b_p2_read_reg_o), + .p2_output_pch_o(decoder_b_p2_output_pch_o), + .pm_inc_pc_o(decoder_b_pm_inc_pc_o), + .pm_write_pmem_addr_o(decoder_b_pm_write_pmem_addr_o), + .pm_addr_type_o(decoder_b_pm_addr_type_o), + .psw_special_data_o(decoder_b_psw_special_data_o), + .psw_inc_stackp_o(decoder_b_psw_inc_stackp_o), + .psw_dec_stackp_o(decoder_b_psw_dec_stackp_o), + .psw_write_carry_o(decoder_b_psw_write_carry_o), + .psw_write_aux_carry_o(decoder_b_psw_write_aux_carry_o), + .psw_write_f0_o(decoder_b_psw_write_f0_o), + .psw_write_bs_o(decoder_b_psw_write_bs_o), + .tim_read_timer_o(decoder_b_tim_read_timer_o), + .tim_write_timer_o(decoder_b_tim_write_timer_o), + .tim_start_t_o(decoder_b_tim_start_t_o), + .tim_start_cnt_o(decoder_b_tim_start_cnt_o), + .tim_stop_tcnt_o(decoder_b_tim_stop_tcnt_o)); + /* t48_core.vhd:491:28 */ + assign dmem_ctrl_b_n291 = dmem_ctrl_b_data_o; // (signal) + /* t48_core.vhd:493:28 */ + assign dmem_ctrl_b_n292 = dmem_ctrl_b_dmem_addr_o; // (signal) + /* t48_core.vhd:494:28 */ + assign dmem_ctrl_b_n293 = dmem_ctrl_b_dmem_we_o; // (signal) + /* t48_core.vhd:495:28 */ + assign dmem_ctrl_b_n294 = dmem_ctrl_b_dmem_data_o; // (signal) + /* t48_core.vhd:480:3 */ + t48_dmem_ctrl dmem_ctrl_b ( + .clk_i(clk_i), + .res_i(reset_i), + .en_clk_i(en_clk_s), + .data_i(t48_data_s), + .write_dmem_addr_i(dm_write_dmem_addr_s), + .write_dmem_i(dm_write_dmem_s), + .read_dmem_i(dm_read_dmem_s), + .addr_type_i(dm_addr_type_s), + .bank_select_i(psw_bs_s), + .dmem_data_i(dmem_data_i), + .data_o(dmem_ctrl_b_data_o), + .dmem_addr_o(dmem_ctrl_b_dmem_addr_o), + .dmem_we_o(dmem_ctrl_b_dmem_we_o), + .dmem_data_o(dmem_ctrl_b_dmem_data_o)); + /* t48_core.vhd:510:26 */ + assign use_timer_timer_b_n303 = use_timer_timer_b_data_o; // (signal) + /* t48_core.vhd:516:26 */ + assign use_timer_timer_b_n304 = use_timer_timer_b_overflow_o; // (signal) + /* t48_core.vhd:499:5 */ + t48_timer_4 use_timer_timer_b ( + .clk_i(clk_i), + .res_i(reset_i), + .en_clk_i(en_clk_s), + .t1_i(t1_s), + .clk_mstate_i(clk_mstate_s), + .data_i(t48_data_s), + .read_timer_i(tim_read_timer_s), + .write_timer_i(tim_write_timer_s), + .start_t_i(tim_start_t_s), + .start_cnt_i(tim_start_cnt_s), + .stop_tcnt_i(tim_stop_tcnt_s), + .data_o(use_timer_timer_b_data_o), + .overflow_o(use_timer_timer_b_overflow_o)); + /* t48_pack-p.vhd:75:5 */ + assign n316_o = tim_of_s ? 1'b1 : 1'b0; + /* t48_core.vhd:534:25 */ + assign use_p1_p1_b_n317 = use_p1_p1_b_data_o; // (signal) + /* t48_core.vhd:539:25 */ + assign use_p1_p1_b_n318 = use_p1_p1_b_p1_o; // (signal) + /* t48_core.vhd:540:25 */ + assign use_p1_p1_b_n319 = use_p1_p1_b_p1_low_imp_o; // (signal) + /* t48_core.vhd:528:5 */ + t48_p1 use_p1_p1_b ( + .clk_i(clk_i), + .res_i(reset_i), + .en_clk_i(en_clk_s), + .data_i(t48_data_s), + .write_p1_i(p1_write_p1_s), + .read_p1_i(p1_read_p1_s), + .read_reg_i(p1_read_reg_s), + .p1_i(p1_i), + .data_o(use_p1_p1_b_data_o), + .p1_o(use_p1_p1_b_p1_o), + .p1_low_imp_o(use_p1_p1_b_p1_low_imp_o)); + /* t48_core.vhd:559:26 */ + assign use_p2_p2_b_n326 = use_p2_p2_b_data_o; // (signal) + /* t48_core.vhd:566:37 */ + assign n327_o = pmem_addr_s[11:8]; + /* t48_core.vhd:568:26 */ + assign use_p2_p2_b_n328 = use_p2_p2_b_p2_o; // (signal) + /* t48_core.vhd:569:26 */ + assign use_p2_p2_b_n329 = use_p2_p2_b_p2l_low_imp_o; // (signal) + /* t48_core.vhd:570:26 */ + assign use_p2_p2_b_n330 = use_p2_p2_b_p2h_low_imp_o; // (signal) + /* t48_core.vhd:551:5 */ + t48_p2 use_p2_p2_b ( + .clk_i(clk_i), + .res_i(reset_i), + .en_clk_i(en_clk_s), + .xtal_i(xtal_i), + .xtal_en_i(xtal_en_s), + .data_i(t48_data_s), + .write_p2_i(p2_write_p2_s), + .write_exp_i(p2_write_exp_s), + .read_p2_i(p2_read_p2_s), + .read_reg_i(p2_read_reg_s), + .read_exp_i(p2_read_exp_s), + .output_pch_i(p2_output_pch_s), + .pch_i(n327_o), + .p2_i(p2_i), + .data_o(use_p2_p2_b_data_o), + .p2_o(use_p2_p2_b_p2_o), + .p2l_low_imp_o(use_p2_p2_b_p2l_low_imp_o), + .p2h_low_imp_o(use_p2_p2_b_p2h_low_imp_o)); + /* t48_core.vhd:587:28 */ + assign pmem_ctrl_b_n339 = pmem_ctrl_b_data_o; // (signal) + /* t48_core.vhd:596:28 */ + assign pmem_ctrl_b_n340 = pmem_ctrl_b_pmem_addr_o; // (signal) + /* t48_core.vhd:581:3 */ + t48_pmem_ctrl pmem_ctrl_b ( + .clk_i(clk_i), + .res_i(reset_i), + .en_clk_i(en_clk_s), + .data_i(t48_data_s), + .write_pcl_i(pm_write_pcl_s), + .read_pcl_i(pm_read_pcl_s), + .write_pch_i(pm_write_pch_s), + .read_pch_i(pm_read_pch_s), + .inc_pc_i(pm_inc_pc_s), + .write_pmem_addr_i(pm_write_pmem_addr_s), + .addr_type_i(pm_addr_type_s), + .read_pmem_i(pm_read_pmem_s), + .pmem_data_i(pmem_data_i), + .data_o(pmem_ctrl_b_data_o), + .pmem_addr_o(pmem_ctrl_b_pmem_addr_o)); + /* t48_core.vhd:606:29 */ + assign psw_b_n345 = psw_b_data_o; // (signal) + /* t48_core.vhd:618:29 */ + assign psw_b_n346 = psw_b_carry_o; // (signal) + /* t48_core.vhd:620:29 */ + assign psw_b_n347 = psw_b_aux_carry_o; // (signal) + /* t48_core.vhd:621:29 */ + assign psw_b_n348 = psw_b_f0_o; // (signal) + /* t48_core.vhd:622:29 */ + assign psw_b_n349 = psw_b_bs_o; // (signal) + /* t48_core.vhd:600:3 */ + t48_psw psw_b ( + .clk_i(clk_i), + .res_i(reset_i), + .en_clk_i(en_clk_s), + .data_i(t48_data_s), + .read_psw_i(psw_read_psw_s), + .read_sp_i(psw_read_sp_s), + .write_psw_i(psw_write_psw_s), + .write_sp_i(psw_write_sp_s), + .special_data_i(psw_special_data_s), + .inc_stackp_i(psw_inc_stackp_s), + .dec_stackp_i(psw_dec_stackp_s), + .write_carry_i(psw_write_carry_s), + .write_aux_carry_i(psw_write_aux_carry_s), + .write_f0_i(psw_write_f0_s), + .write_bs_i(psw_write_bs_s), + .aux_carry_i(alu_aux_carry_s), + .data_o(psw_b_data_o), + .carry_o(psw_b_carry_o), + .aux_carry_o(psw_b_aux_carry_o), + .f0_o(psw_b_f0_o), + .bs_o(psw_b_bs_o)); + /* t48_pack-p.vhd:66:5 */ + assign n367_o = ale_s ? 1'b1 : 1'b0; + /* t48_core.vhd:630:30 */ + assign n369_o = ~psen_s; + /* t48_pack-p.vhd:66:5 */ + assign n376_o = n369_o ? 1'b1 : 1'b0; + /* t48_core.vhd:631:30 */ + assign n378_o = ~prog_s; + /* t48_pack-p.vhd:66:5 */ + assign n385_o = n378_o ? 1'b1 : 1'b0; + /* t48_core.vhd:632:30 */ + assign n387_o = ~rd_s; + /* t48_pack-p.vhd:66:5 */ + assign n394_o = n387_o ? 1'b1 : 1'b0; + /* t48_core.vhd:633:30 */ + assign n396_o = ~wr_s; + /* t48_pack-p.vhd:66:5 */ + assign n403_o = n396_o ? 1'b1 : 1'b0; + /* t48_pack-p.vhd:66:5 */ + assign n411_o = xtal3_s ? 1'b1 : 1'b0; +endmodule + diff --git a/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/t48/t48_core.vhd b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/t48/t48_core.vhd new file mode 100644 index 0000000000000000000000000000000000000000..59f38a9363c13332d807508485aa1a4849b49e0d --- /dev/null +++ b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/t48/t48_core.vhd @@ -0,0 +1,637 @@ +------------------------------------------------------------------------------- +-- +-- T48 Microcontroller Core +-- +-- $Id: t48_core.vhd 302 2021-01-24 13:22:57Z arniml $ +-- +-- Copyright (c) 2004, 2005, Arnim Laeuger (arniml@opencores.org) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.opencores.org/cvsweb.shtml/t48/ +-- +-- Limitations : +-- ============= +-- +-- Compared to the original MCS-48 architecture, the following limitations +-- apply: +-- +-- * Single-step mode not implemented. +-- Not selected for future implementation. +-- +-- * Reading of internal Program Memory not implemented. +-- Not selected for future implementation. +-- +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; + +entity t48_core is + + generic ( + -- divide XTAL1 by 3 to derive Clock States + xtal_div_3_g : integer := 1; + -- store mnemonic in flip-flops (registered-out) + register_mnemonic_g : integer := 1; + -- include the port 1 module + include_port1_g : integer := 1; + -- include the port 2 module + include_port2_g : integer := 1; + -- include the BUS module + include_bus_g : integer := 1; + -- include the timer module + include_timer_g : integer := 1; + -- state in which T1 is sampled (3 or 4) + sample_t1_state_g : integer := 4 + ); + + port ( + -- T48 Interface ---------------------------------------------------------- + xtal_i : in std_logic; + xtal_en_i : in std_logic; + reset_i : in std_logic; + t0_i : in std_logic; + t0_o : out std_logic; + t0_dir_o : out std_logic; + int_n_i : in std_logic; + ea_i : in std_logic; + rd_n_o : out std_logic; + psen_n_o : out std_logic; + wr_n_o : out std_logic; + ale_o : out std_logic; + db_i : in std_logic_vector( 7 downto 0); + db_o : out std_logic_vector( 7 downto 0); + db_dir_o : out std_logic; + t1_i : in std_logic; + p2_i : in std_logic_vector( 7 downto 0); + p2_o : out std_logic_vector( 7 downto 0); + p2l_low_imp_o : out std_logic; + p2h_low_imp_o : out std_logic; + p1_i : in std_logic_vector( 7 downto 0); + p1_o : out std_logic_vector( 7 downto 0); + p1_low_imp_o : out std_logic; + prog_n_o : out std_logic; + -- Core Interface --------------------------------------------------------- + clk_i : in std_logic; + en_clk_i : in std_logic; + xtal3_o : out std_logic; + dmem_addr_o : out std_logic_vector( 7 downto 0); + dmem_we_o : out std_logic; + dmem_data_i : in std_logic_vector( 7 downto 0); + dmem_data_o : out std_logic_vector( 7 downto 0); + pmem_addr_o : out std_logic_vector(11 downto 0); + pmem_data_i : in std_logic_vector( 7 downto 0) + ); + +end t48_core; + + +use work.t48_alu_pack.alu_op_t; +use work.t48_cond_branch_pack.branch_conditions_t; +use work.t48_cond_branch_pack.comp_value_t; +use work.t48_dmem_ctrl_pack.dmem_addr_ident_t; +use work.t48_pmem_ctrl_pack.pmem_addr_ident_t; +use work.t48_comp_pack.all; +use work.t48_pack.bus_idle_level_c; +use work.t48_pack.word_t; +use work.t48_pack.pmem_addr_t; +use work.t48_pack.mstate_t; +use work.t48_pack.to_stdLogic; +use work.t48_pack.to_boolean; + +architecture struct of t48_core is + + signal t48_data_s : word_t; + + signal xtal_en_s : boolean; + signal en_clk_s : boolean; + + signal t0_s, t1_s : std_logic; + + -- ALU signals + signal alu_data_s : word_t; + signal alu_write_accu_s : boolean; + signal alu_write_shadow_s : boolean; + signal alu_write_temp_reg_s : boolean; + signal alu_read_alu_s : boolean; + signal alu_carry_s : std_logic; + signal alu_aux_carry_s : std_logic; + signal alu_op_s : alu_op_t; + signal alu_use_carry_s : boolean; + signal alu_da_high_s : boolean; + signal alu_da_overflow_s : boolean; + signal alu_accu_low_s : boolean; + signal alu_p06_temp_reg_s : boolean; + signal alu_p60_temp_reg_s : boolean; + + -- BUS signals + signal bus_write_bus_s : boolean; + signal bus_read_bus_s : boolean; + signal bus_output_pcl_s : boolean; + signal bus_bidir_bus_s : boolean; + signal bus_data_s : word_t; + + -- Clock Controller signals + signal clk_multi_cycle_s : boolean; + signal clk_assert_psen_s : boolean; + signal clk_assert_prog_s : boolean; + signal clk_assert_rd_s : boolean; + signal clk_assert_wr_s : boolean; + signal clk_mstate_s : mstate_t; + signal clk_second_cycle_s : boolean; + signal psen_s : boolean; + signal prog_s : boolean; + signal rd_s : boolean; + signal wr_s : boolean; + signal ale_s : boolean; + signal xtal3_s : boolean; + + -- Conditional Branch Logic signals + signal cnd_compute_take_s : boolean; + signal cnd_branch_cond_s : branch_conditions_t; + signal cnd_take_branch_s : boolean; + signal cnd_comp_value_s : comp_value_t; + signal cnd_f1_s : std_logic; + signal cnd_tf_s : std_logic; + + -- Data Memory Controller signals + signal dm_write_dmem_addr_s : boolean; + signal dm_write_dmem_s : boolean; + signal dm_read_dmem_s : boolean; + signal dm_addr_type_s : dmem_addr_ident_t; + signal dm_data_s : word_t; + + -- Decoder signals + signal dec_data_s : word_t; + + -- Port 1 signals + signal p1_write_p1_s : boolean; + signal p1_read_p1_s : boolean; + signal p1_read_reg_s : boolean; + signal p1_data_s : word_t; + + -- Port 2 signals + signal p2_write_p2_s : boolean; + signal p2_write_exp_s : boolean; + signal p2_read_p2_s : boolean; + signal p2_read_reg_s : boolean; + signal p2_read_exp_s : boolean; + signal p2_output_pch_s : boolean; + signal p2_data_s : word_t; + + -- Program Memory Controller signals + signal pm_write_pcl_s : boolean; + signal pm_read_pcl_s : boolean; + signal pm_write_pch_s : boolean; + signal pm_read_pch_s : boolean; + signal pm_read_pmem_s : boolean; + signal pm_inc_pc_s : boolean; + signal pm_write_pmem_addr_s : boolean; + signal pm_data_s : word_t; + signal pm_addr_type_s : pmem_addr_ident_t; + signal pmem_addr_s : pmem_addr_t; + + -- PSW signals + signal psw_read_psw_s : boolean; + signal psw_read_sp_s : boolean; + signal psw_write_psw_s : boolean; + signal psw_write_sp_s : boolean; + signal psw_carry_s : std_logic; + signal psw_aux_carry_s : std_logic; + signal psw_f0_s : std_logic; + signal psw_bs_s : std_logic; + signal psw_special_data_s : std_logic; + signal psw_inc_stackp_s : boolean; + signal psw_dec_stackp_s : boolean; + signal psw_write_carry_s : boolean; + signal psw_write_aux_carry_s : boolean; + signal psw_write_f0_s : boolean; + signal psw_write_bs_s : boolean; + signal psw_data_s : word_t; + + -- Timer signals + signal tim_overflow_s : boolean; + signal tim_of_s : std_logic; + signal tim_read_timer_s : boolean; + signal tim_write_timer_s : boolean; + signal tim_start_t_s : boolean; + signal tim_start_cnt_s : boolean; + signal tim_stop_tcnt_s : boolean; + signal tim_data_s : word_t; + +begin + + ----------------------------------------------------------------------------- + -- Check generics for valid values. + ----------------------------------------------------------------------------- + -- pragma translate_off + assert include_timer_g = 0 or include_timer_g = 1 + report "include_timer_g must be either 1 or 0!" + severity failure; + + assert include_port1_g = 0 or include_port1_g = 1 + report "include_port1_g must be either 1 or 0!" + severity failure; + + assert include_port2_g = 0 or include_port2_g = 1 + report "include_port2_g must be either 1 or 0!" + severity failure; + + assert include_bus_g = 0 or include_bus_g = 1 + report "include_bus_g must be either 1 or 0!" + severity failure; + -- pragma translate_on + + + xtal_en_s <= to_boolean(xtal_en_i); + en_clk_s <= to_boolean(en_clk_i); + + t0_s <= To_X01Z(t0_i); + t1_s <= To_X01Z(t1_i); + + alu_b : t48_alu + port map ( + clk_i => clk_i, + res_i => reset_i, + en_clk_i => en_clk_s, + data_i => t48_data_s, + data_o => alu_data_s, + write_accu_i => alu_write_accu_s, + write_shadow_i => alu_write_shadow_s, + write_temp_reg_i => alu_write_temp_reg_s, + read_alu_i => alu_read_alu_s, + carry_i => psw_carry_s, + carry_o => alu_carry_s, + aux_carry_o => alu_aux_carry_s, + alu_op_i => alu_op_s, + use_carry_i => alu_use_carry_s, + da_high_i => alu_da_high_s, + da_overflow_o => alu_da_overflow_s, + accu_low_i => alu_accu_low_s, + p06_temp_reg_i => alu_p06_temp_reg_s, + p60_temp_reg_i => alu_p60_temp_reg_s + ); + + bus_mux_b : t48_bus_mux + port map ( + alu_data_i => alu_data_s, + bus_data_i => bus_data_s, + dec_data_i => dec_data_s, + dm_data_i => dm_data_s, + pm_data_i => pm_data_s, + p1_data_i => p1_data_s, + p2_data_i => p2_data_s, + psw_data_i => psw_data_s, + tim_data_i => tim_data_s, + data_o => t48_data_s + ); + + clock_ctrl_b : t48_clock_ctrl + generic map ( + xtal_div_3_g => xtal_div_3_g + ) + port map ( + clk_i => clk_i, + xtal_i => xtal_i, + xtal_en_i => xtal_en_s, + res_i => reset_i, + en_clk_i => en_clk_s, + xtal3_o => xtal3_s, + t0_o => t0_o, + multi_cycle_i => clk_multi_cycle_s, + assert_psen_i => clk_assert_psen_s, + assert_prog_i => clk_assert_prog_s, + assert_rd_i => clk_assert_rd_s, + assert_wr_i => clk_assert_wr_s, + mstate_o => clk_mstate_s, + second_cycle_o => clk_second_cycle_s, + ale_o => ale_s, + psen_o => psen_s, + prog_o => prog_s, + rd_o => rd_s, + wr_o => wr_s + ); + + cond_branch_b : t48_cond_branch + port map ( + clk_i => clk_i, + res_i => reset_i, + en_clk_i => en_clk_s, + compute_take_i => cnd_compute_take_s, + branch_cond_i => cnd_branch_cond_s, + take_branch_o => cnd_take_branch_s, + accu_i => alu_data_s, + t0_i => t0_s, + t1_i => t1_s, + int_n_i => int_n_i, + f0_i => psw_f0_s, + f1_i => cnd_f1_s, + tf_i => cnd_tf_s, + carry_i => psw_carry_s, + comp_value_i => cnd_comp_value_s + ); + + use_db_bus: if include_bus_g = 1 generate + db_bus_b : t48_db_bus + port map ( + clk_i => clk_i, + res_i => reset_i, + en_clk_i => en_clk_s, + ea_i => ea_i, + data_i => t48_data_s, + data_o => bus_data_s, + write_bus_i => bus_write_bus_s, + read_bus_i => bus_read_bus_s, + output_pcl_i => bus_output_pcl_s, + bidir_bus_i => bus_bidir_bus_s, + pcl_i => pmem_addr_s(word_t'range), + db_i => db_i, + db_o => db_o, + db_dir_o => db_dir_o + ); + end generate; + + skip_db_bus: if include_bus_g = 0 generate + bus_data_s <= (others => bus_idle_level_c); + db_o <= (others => '0'); + db_dir_o <= '0'; + end generate; + + decoder_b : t48_decoder + generic map ( + register_mnemonic_g => register_mnemonic_g + ) + port map ( + clk_i => clk_i, + res_i => reset_i, + en_clk_i => en_clk_s, + xtal_i => xtal_i, + xtal_en_i => xtal_en_s, + ea_i => ea_i, + ale_i => ale_s, + int_n_i => int_n_i, + t0_dir_o => t0_dir_o, + data_i => t48_data_s, + data_o => dec_data_s, + alu_write_accu_o => alu_write_accu_s, + alu_write_shadow_o => alu_write_shadow_s, + alu_write_temp_reg_o => alu_write_temp_reg_s, + alu_read_alu_o => alu_read_alu_s, + bus_write_bus_o => bus_write_bus_s, + bus_read_bus_o => bus_read_bus_s, + dm_write_dmem_addr_o => dm_write_dmem_addr_s, + dm_write_dmem_o => dm_write_dmem_s, + dm_read_dmem_o => dm_read_dmem_s, + p1_write_p1_o => p1_write_p1_s, + p1_read_p1_o => p1_read_p1_s, + pm_write_pcl_o => pm_write_pcl_s, + p2_write_p2_o => p2_write_p2_s, + p2_write_exp_o => p2_write_exp_s, + p2_read_p2_o => p2_read_p2_s, + pm_read_pcl_o => pm_read_pcl_s, + pm_write_pch_o => pm_write_pch_s, + pm_read_pch_o => pm_read_pch_s, + pm_read_pmem_o => pm_read_pmem_s, + psw_read_psw_o => psw_read_psw_s, + psw_read_sp_o => psw_read_sp_s, + psw_write_psw_o => psw_write_psw_s, + psw_write_sp_o => psw_write_sp_s, + alu_carry_i => alu_carry_s, + alu_op_o => alu_op_s, + alu_use_carry_o => alu_use_carry_s, + alu_da_high_o => alu_da_high_s, + alu_da_overflow_i => alu_da_overflow_s, + alu_accu_low_o => alu_accu_low_s, + alu_p06_temp_reg_o => alu_p06_temp_reg_s, + alu_p60_temp_reg_o => alu_p60_temp_reg_s, + bus_output_pcl_o => bus_output_pcl_s, + bus_bidir_bus_o => bus_bidir_bus_s, + clk_multi_cycle_o => clk_multi_cycle_s, + clk_assert_psen_o => clk_assert_psen_s, + clk_assert_prog_o => clk_assert_prog_s, + clk_assert_rd_o => clk_assert_rd_s, + clk_assert_wr_o => clk_assert_wr_s, + clk_mstate_i => clk_mstate_s, + clk_second_cycle_i => clk_second_cycle_s, + cnd_compute_take_o => cnd_compute_take_s, + cnd_branch_cond_o => cnd_branch_cond_s, + cnd_take_branch_i => cnd_take_branch_s, + cnd_comp_value_o => cnd_comp_value_s, + cnd_f1_o => cnd_f1_s, + cnd_tf_o => cnd_tf_s, + dm_addr_type_o => dm_addr_type_s, + tim_read_timer_o => tim_read_timer_s, + tim_write_timer_o => tim_write_timer_s, + tim_start_t_o => tim_start_t_s, + tim_start_cnt_o => tim_start_cnt_s, + tim_stop_tcnt_o => tim_stop_tcnt_s, + p1_read_reg_o => p1_read_reg_s, + p2_read_reg_o => p2_read_reg_s, + p2_read_exp_o => p2_read_exp_s, + p2_output_pch_o => p2_output_pch_s, + pm_inc_pc_o => pm_inc_pc_s, + pm_write_pmem_addr_o => pm_write_pmem_addr_s, + pm_addr_type_o => pm_addr_type_s, + psw_special_data_o => psw_special_data_s, + psw_carry_i => psw_carry_s, + psw_aux_carry_i => psw_aux_carry_s, + psw_f0_i => psw_f0_s, + psw_inc_stackp_o => psw_inc_stackp_s, + psw_dec_stackp_o => psw_dec_stackp_s, + psw_write_carry_o => psw_write_carry_s, + psw_write_aux_carry_o => psw_write_aux_carry_s, + psw_write_f0_o => psw_write_f0_s, + psw_write_bs_o => psw_write_bs_s, + tim_overflow_i => tim_overflow_s + ); + + dmem_ctrl_b : t48_dmem_ctrl + port map ( + clk_i => clk_i, + res_i => reset_i, + en_clk_i => en_clk_s, + data_i => t48_data_s, + write_dmem_addr_i => dm_write_dmem_addr_s, + write_dmem_i => dm_write_dmem_s, + read_dmem_i => dm_read_dmem_s, + addr_type_i => dm_addr_type_s, + bank_select_i => psw_bs_s, + data_o => dm_data_s, + dmem_data_i => dmem_data_i, + dmem_addr_o => dmem_addr_o, + dmem_we_o => dmem_we_o, + dmem_data_o => dmem_data_o + ); + + use_timer: if include_timer_g = 1 generate + timer_b : t48_timer + generic map ( + sample_t1_state_g => sample_t1_state_g + ) + port map ( + clk_i => clk_i, + res_i => reset_i, + en_clk_i => en_clk_s, + t1_i => t1_s, + clk_mstate_i => clk_mstate_s, + data_i => t48_data_s, + data_o => tim_data_s, + read_timer_i => tim_read_timer_s, + write_timer_i => tim_write_timer_s, + start_t_i => tim_start_t_s, + start_cnt_i => tim_start_cnt_s, + stop_tcnt_i => tim_stop_tcnt_s, + overflow_o => tim_of_s + ); + end generate; + + skip_timer: if include_timer_g = 0 generate + tim_data_s <= (others => bus_idle_level_c); + tim_of_s <= '0'; + end generate; + + tim_overflow_s <= to_boolean(tim_of_s); + + use_p1: if include_port1_g = 1 generate + p1_b : t48_p1 + port map ( + clk_i => clk_i, + res_i => reset_i, + en_clk_i => en_clk_s, + data_i => t48_data_s, + data_o => p1_data_s, + write_p1_i => p1_write_p1_s, + read_p1_i => p1_read_p1_s, + read_reg_i => p1_read_reg_s, + p1_i => p1_i, + p1_o => p1_o, + p1_low_imp_o => p1_low_imp_o + ); + end generate; + + skip_p1: if include_port1_g = 0 generate + p1_data_s <= (others => bus_idle_level_c); + p1_o <= (others => '0'); + p1_low_imp_o <= '0'; + end generate; + + use_p2: if include_port2_g = 1 generate + p2_b : t48_p2 + port map ( + clk_i => clk_i, + res_i => reset_i, + en_clk_i => en_clk_s, + xtal_i => xtal_i, + xtal_en_i => xtal_en_s, + data_i => t48_data_s, + data_o => p2_data_s, + write_p2_i => p2_write_p2_s, + write_exp_i => p2_write_exp_s, + read_p2_i => p2_read_p2_s, + read_reg_i => p2_read_reg_s, + read_exp_i => p2_read_exp_s, + output_pch_i => p2_output_pch_s, + pch_i => pmem_addr_s(11 downto 8), + p2_i => p2_i, + p2_o => p2_o, + p2l_low_imp_o => p2l_low_imp_o, + p2h_low_imp_o => p2h_low_imp_o + ); + end generate; + + skip_p2: if include_port2_g = 0 generate + p2_data_s <= (others => bus_idle_level_c); + p2_o <= (others => '0'); + p2l_low_imp_o <= '0'; + p2h_low_imp_o <= '0'; + end generate; + + pmem_ctrl_b : t48_pmem_ctrl + port map ( + clk_i => clk_i, + res_i => reset_i, + en_clk_i => en_clk_s, + data_i => t48_data_s, + data_o => pm_data_s, + write_pcl_i => pm_write_pcl_s, + read_pcl_i => pm_read_pcl_s, + write_pch_i => pm_write_pch_s, + read_pch_i => pm_read_pch_s, + inc_pc_i => pm_inc_pc_s, + write_pmem_addr_i => pm_write_pmem_addr_s, + addr_type_i => pm_addr_type_s, + read_pmem_i => pm_read_pmem_s, + pmem_addr_o => pmem_addr_s, + pmem_data_i => pmem_data_i + ); + + psw_b : t48_psw + port map ( + clk_i => clk_i, + res_i => reset_i, + en_clk_i => en_clk_s, + data_i => t48_data_s, + data_o => psw_data_s, + read_psw_i => psw_read_psw_s, + read_sp_i => psw_read_sp_s, + write_psw_i => psw_write_psw_s, + write_sp_i => psw_write_sp_s, + special_data_i => psw_special_data_s, + inc_stackp_i => psw_inc_stackp_s, + dec_stackp_i => psw_dec_stackp_s, + write_carry_i => psw_write_carry_s, + write_aux_carry_i => psw_write_aux_carry_s, + write_f0_i => psw_write_f0_s, + write_bs_i => psw_write_bs_s, + carry_o => psw_carry_s, + aux_carry_i => alu_aux_carry_s, + aux_carry_o => psw_aux_carry_s, + f0_o => psw_f0_s, + bs_o => psw_bs_s + ); + + + ----------------------------------------------------------------------------- + -- Output Mapping. + ----------------------------------------------------------------------------- + ale_o <= to_stdLogic(ale_s); + psen_n_o <= to_stdLogic(not psen_s); + prog_n_o <= to_stdLogic(not prog_s); + rd_n_o <= to_stdLogic(not rd_s); + wr_n_o <= to_stdLogic(not wr_s); + xtal3_o <= to_stdLogic(xtal3_s); + pmem_addr_o <= pmem_addr_s; + +end struct; diff --git a/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/t48/t48_core_comp_pack-p.vhd b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/t48/t48_core_comp_pack-p.vhd new file mode 100644 index 0000000000000000000000000000000000000000..1a4575157c554aac9b4d6e02fcb8f6a333c563be --- /dev/null +++ b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/t48/t48_core_comp_pack-p.vhd @@ -0,0 +1,137 @@ +------------------------------------------------------------------------------- +-- +-- $Id: t48_core_comp_pack-p.vhd 314 2022-12-22 09:05:13Z arniml $ +-- +-- Copyright (c) 2004, Arnim Laeuger (arniml@opencores.org) +-- +-- All rights reserved +-- +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; + +package t48_core_comp_pack is + + component t48_core + generic ( + xtal_div_3_g : integer := 1; + register_mnemonic_g : integer := 1; + include_port1_g : integer := 1; + include_port2_g : integer := 1; + include_bus_g : integer := 1; + include_timer_g : integer := 1; + sample_t1_state_g : integer := 4 + ); + + port ( + xtal_i : in std_logic; + xtal_en_i : in std_logic; + reset_i : in std_logic; + t0_i : in std_logic; + t0_o : out std_logic; + t0_dir_o : out std_logic; + int_n_i : in std_logic; + ea_i : in std_logic; + rd_n_o : out std_logic; + psen_n_o : out std_logic; + wr_n_o : out std_logic; + ale_o : out std_logic; + db_i : in std_logic_vector( 7 downto 0); + db_o : out std_logic_vector( 7 downto 0); + db_dir_o : out std_logic; + t1_i : in std_logic; + p2_i : in std_logic_vector( 7 downto 0); + p2_o : out std_logic_vector( 7 downto 0); + p2l_low_imp_o : out std_logic; + p2h_low_imp_o : out std_logic; + p1_i : in std_logic_vector( 7 downto 0); + p1_o : out std_logic_vector( 7 downto 0); + p1_low_imp_o : out std_logic; + prog_n_o : out std_logic; + clk_i : in std_logic; + en_clk_i : in std_logic; + xtal3_o : out std_logic; + dmem_addr_o : out std_logic_vector( 7 downto 0); + dmem_we_o : out std_logic; + dmem_data_i : in std_logic_vector( 7 downto 0); + dmem_data_o : out std_logic_vector( 7 downto 0); + pmem_addr_o : out std_logic_vector(11 downto 0); + pmem_data_i : in std_logic_vector( 7 downto 0) + ); + end component; + + component upi41_core + generic ( + xtal_div_3_g : integer := 1; + register_mnemonic_g : integer := 1; + sample_t1_state_g : integer := 4; + is_upi_type_a_g : integer := 1 + ); + + port ( + xtal_i : in std_logic; + xtal_en_i : in std_logic; + reset_i : in std_logic; + t0_i : in std_logic; + cs_n_i : in std_logic; + rd_n_i : in std_logic; + a0_i : in std_logic; + wr_n_i : in std_logic; + sync_o : out std_logic; + db_i : in std_logic_vector( 7 downto 0); + db_o : out std_logic_vector( 7 downto 0); + db_dir_o : out std_logic; + t1_i : in std_logic; + p2_i : in std_logic_vector( 7 downto 0); + p2_o : out std_logic_vector( 7 downto 0); + p2l_low_imp_o : out std_logic; + p2h_low_imp_o : out std_logic; + p1_i : in std_logic_vector( 7 downto 0); + p1_o : out std_logic_vector( 7 downto 0); + p1_low_imp_o : out std_logic; + prog_n_o : out std_logic; + clk_i : in std_logic; + en_clk_i : in std_logic; + xtal3_o : out std_logic; + dmem_addr_o : out std_logic_vector( 7 downto 0); + dmem_we_o : out std_logic; + dmem_data_i : in std_logic_vector( 7 downto 0); + dmem_data_o : out std_logic_vector( 7 downto 0); + pmem_addr_o : out std_logic_vector(10 downto 0); + pmem_data_i : in std_logic_vector( 7 downto 0) + ); + end component; + + component generic_ram_ena + generic ( + addr_width_g : integer := 10; + data_width_g : integer := 8 + ); + port ( + clk_i : in std_logic; + a_i : in std_logic_vector(addr_width_g-1 downto 0); + we_i : in std_logic; + ena_i : in std_logic; + d_i : in std_logic_vector(data_width_g-1 downto 0); + d_o : out std_logic_vector(data_width_g-1 downto 0) + ); + end component; + + component t48_rom + port ( + clk_i : in std_logic; + rom_addr_i : in std_logic_vector(9 downto 0); + rom_data_o : out std_logic_vector(7 downto 0) + ); + end component; + + component t49_rom + port ( + clk_i : in std_logic; + rom_addr_i : in std_logic_vector(10 downto 0); + rom_data_o : out std_logic_vector( 7 downto 0) + ); + end component; + +end t48_core_comp_pack; diff --git a/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/t48/t48_pack-p.vhd b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/t48/t48_pack-p.vhd new file mode 100644 index 0000000000000000000000000000000000000000..9d20d7e754182b3dd707a335fecb3ea6cc9d3df8 --- /dev/null +++ b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/t48/t48_pack-p.vhd @@ -0,0 +1,82 @@ +------------------------------------------------------------------------------- +-- +-- $Id: t48_pack-p.vhd 295 2009-04-01 19:32:48Z arniml $ +-- +-- Copyright (c) 2004, Arnim Laeuger (arniml@opencores.org) +-- +-- All rights reserved +-- +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; + +package t48_pack is + + ----------------------------------------------------------------------------- + -- Global constants + ----------------------------------------------------------------------------- + + -- clock active level + constant clk_active_c : std_logic := '1'; + -- reset active level + constant res_active_c : std_logic := '0'; + -- idle level on internal data bus + constant bus_idle_level_c : std_logic := '1'; + + -- global data word width + constant word_width_c : natural := 8; + + -- data memory address width + constant dmem_addr_width_c : natural := 8; + -- program memory address width + constant pmem_addr_width_c : natural := 12; + + + ----------------------------------------------------------------------------- + -- Global data types + ----------------------------------------------------------------------------- + + -- the global data word width type + subtype word_t is std_logic_vector(word_width_c-1 downto 0); + subtype nibble_t is std_logic_vector(word_width_c/2-1 downto 0); + -- the global data memory address type + subtype dmem_addr_t is std_logic_vector(dmem_addr_width_c-1 downto 0); + -- the global program memory address type + subtype pmem_addr_t is std_logic_vector(pmem_addr_width_c-1 downto 0); + subtype page_t is std_logic_vector(pmem_addr_width_c-1 downto word_width_c); + + -- the machine states + type mstate_t is (MSTATE1, MSTATE2, MSTATE3, MSTATE4, MSTATE5); + + + ----------------------------------------------------------------------------- + -- Global functions + ----------------------------------------------------------------------------- + + function to_stdLogic(input: boolean) return std_logic; + function to_boolean(input: std_logic) return boolean; + +end t48_pack; + +package body t48_pack is + + function to_stdLogic(input: boolean) return std_logic is + begin + if input then + return '1'; + else + return '0'; + end if; + end to_stdLogic; + + function to_boolean(input: std_logic) return boolean is + begin + if input = '1' then + return true; + else + return false; + end if; + end to_boolean; + +end t48_pack; diff --git a/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/t48/t48_tb_pack-p.vhd b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/t48/t48_tb_pack-p.vhd new file mode 100644 index 0000000000000000000000000000000000000000..157320f4f411fa532c125e7c47298a81660f928c --- /dev/null +++ b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/t48/t48_tb_pack-p.vhd @@ -0,0 +1,22 @@ +------------------------------------------------------------------------------- +-- +-- $Id: t48_tb_pack-p.vhd 295 2009-04-01 19:32:48Z arniml $ +-- +-- Copyright (c) 2004, Arnim Laeuger (arniml@opencores.org) +-- +-- All rights reserved +-- +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; + +package t48_tb_pack is + + -- Instruction strobe visibility + signal tb_istrobe_s : std_logic; + + -- Accumulator visibilty + signal tb_accu_s : std_logic_vector(7 downto 0); + +end t48_tb_pack; diff --git a/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/t48/timer-c.vhd b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/t48/timer-c.vhd new file mode 100644 index 0000000000000000000000000000000000000000..83a5da3352926fddaaa4c9d8784c393397bf7cce --- /dev/null +++ b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/t48/timer-c.vhd @@ -0,0 +1,16 @@ +------------------------------------------------------------------------------- +-- +-- The Timer/Counter unit. +-- +-- $Id: timer-c.vhd 295 2009-04-01 19:32:48Z arniml $ +-- +-- All rights reserved +-- +------------------------------------------------------------------------------- + +configuration t48_timer_rtl_c0 of t48_timer is + + for rtl + end for; + +end t48_timer_rtl_c0; diff --git a/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/t48/timer.vhd b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/t48/timer.vhd new file mode 100644 index 0000000000000000000000000000000000000000..37f3e8bbc83ffcb3309a6d04939205031b8bc658 --- /dev/null +++ b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/t48/timer.vhd @@ -0,0 +1,252 @@ +------------------------------------------------------------------------------- +-- +-- The Timer/Counter unit. +-- +-- $Id: timer.vhd 295 2009-04-01 19:32:48Z arniml $ +-- +-- Copyright (c) 2004, Arnim Laeuger (arniml@opencores.org) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.opencores.org/cvsweb.shtml/t48/ +-- +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; + +use work.t48_pack.word_t; +use work.t48_pack.mstate_t; + +entity t48_timer is + + generic ( + -- state in which T1 is sampled (3 or 4) + sample_t1_state_g : integer := 4 + ); + + port ( + -- Global Interface ------------------------------------------------------- + clk_i : in std_logic; + res_i : in std_logic; + en_clk_i : in boolean; + t1_i : in std_logic; + clk_mstate_i : in mstate_t; + -- T48 Bus Interface ------------------------------------------------------ + data_i : in word_t; + data_o : out word_t; + read_timer_i : in boolean; + write_timer_i : in boolean; + -- Decoder Interface ------------------------------------------------------ + start_t_i : in boolean; + start_cnt_i : in boolean; + stop_tcnt_i : in boolean; + overflow_o : out std_logic + ); + +end t48_timer; + + +library ieee; +use ieee.numeric_std.all; + +use work.t48_pack.all; + +architecture rtl of t48_timer is + + -- the 8 bit counter core + signal counter_q : unsigned(word_t'range); + signal overflow_q : boolean; + + -- increment signal for the counter core + type inc_type_t is (NONE, TIMER, COUNTER); + signal increment_s : boolean; + signal inc_sel_q : inc_type_t; + + -- T1 edge detector + signal t1_q : std_logic; + signal t1_inc_s : boolean; + + -- timer prescaler + signal prescaler_q : unsigned(4 downto 0); + signal pre_inc_s : boolean; + +begin + + ----------------------------------------------------------------------------- + -- Verify the generics + ----------------------------------------------------------------------------- + + -- pragma translate_off + assert (sample_t1_state_g = 3) or (sample_t1_state_g = 4) + report "sample_t1_state_g must be either 3 or 4!" + severity failure; + -- pragma translate_on + + + ----------------------------------------------------------------------------- + -- Process t1_edge + -- + -- Purpose: + -- Implements the edge detector for T1. + -- + t1_edge: process (t1_i, + t1_q, + clk_mstate_i) + begin + t1_inc_s <= false; + + -- sample in state according to generic + -- Old devices: sample at the beginning of state 3 + -- New devices: sample in state 4 + if (sample_t1_state_g = 3 and clk_mstate_i = MSTATE3) or + (sample_t1_state_g = 4 and clk_mstate_i = MSTATE4) then + -- detect falling edge + if t1_q = '1' and t1_i = '0' then + t1_inc_s <= true; + end if; + end if; + + end process t1_edge; + -- + ----------------------------------------------------------------------------- + + + pre_inc_s <= clk_mstate_i = MSTATE4 and prescaler_q = 31; + + + ----------------------------------------------------------------------------- + -- Process inc_sel + -- + -- Purpose: + -- Select increment source (timer, counter or none). + -- + inc_sel: process (inc_sel_q, + pre_inc_s, + t1_inc_s) + begin + -- default assignment + increment_s <= false; + + case inc_sel_q is + when NONE => + increment_s <= false; + when TIMER => + increment_s <= pre_inc_s; + when COUNTER => + increment_s <= t1_inc_s; + when others => + null; + end case; + + end process inc_sel; + -- + ----------------------------------------------------------------------------- + + + ----------------------------------------------------------------------------- + -- Process regs + -- + -- Purpose: + -- Implements the counter, the prescaler and other registers. + -- + regs: process (res_i, clk_i) + begin + if res_i = res_active_c then + overflow_q <= false; + t1_q <= '0'; + prescaler_q <= (others => '0'); + inc_sel_q <= NONE; + counter_q <= (others => '0'); + + elsif clk_i'event and clk_i = clk_active_c then + if en_clk_i then + + -- Counter Core and overflow ------------------------------------------ + overflow_q <= false; + + if write_timer_i then + counter_q <= unsigned(data_i); + + elsif increment_s then + counter_q <= counter_q + 1; + + if counter_q = 255 then + overflow_q <= true; + end if; + + end if; + + -- T1 edge detector --------------------------------------------------- + if (sample_t1_state_g = 3 and clk_mstate_i = MSTATE3) or + (sample_t1_state_g = 4 and clk_mstate_i = MSTATE4) then + t1_q <= t1_i; + end if; + + -- Prescaler ---------------------------------------------------------- + if start_t_i then + prescaler_q <= (others => '0'); + + elsif clk_mstate_i = MSTATE3 then + prescaler_q <= prescaler_q + 1; + + end if; + + -- Increment Selector ------------------------------------------------- + if start_t_i then + inc_sel_q <= TIMER; + elsif start_cnt_i then + inc_sel_q <= COUNTER; + elsif stop_tcnt_i then + inc_sel_q <= NONE; + end if; + + end if; + + end if; + + end process regs; + -- + ----------------------------------------------------------------------------- + + + ----------------------------------------------------------------------------- + -- Output Mapping. + ----------------------------------------------------------------------------- + data_o <= std_logic_vector(counter_q) + when read_timer_i else + (others => bus_idle_level_c); + overflow_o <= to_stdLogic(overflow_q); + +end rtl; diff --git a/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/t48/upi41_core-c.vhd b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/t48/upi41_core-c.vhd new file mode 100644 index 0000000000000000000000000000000000000000..7616946d2ccbc68056bb9be7638722781871e4f4 --- /dev/null +++ b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/t48/upi41_core-c.vhd @@ -0,0 +1,61 @@ +------------------------------------------------------------------------------- +-- +-- UPI-41 Microcontroller Core +-- +------------------------------------------------------------------------------- + +configuration upi41_core_struct_c0 of upi41_core is + + for struct + + for alu_b : t48_alu + use configuration work.t48_alu_rtl_c0; + end for; + + for bus_mux_b : t48_bus_mux + use configuration work.t48_bus_mux_rtl_c0; + end for; + + for clock_ctrl_b : t48_clock_ctrl + use configuration work.t48_clock_ctrl_rtl_c0; + end for; + + for cond_branch_b : t48_cond_branch + use configuration work.t48_cond_branch_rtl_c0; + end for; + + for db_bus_b : upi41_db_bus + use configuration work.upi41_db_bus_rtl_c0; + end for; + + for decoder_b : t48_decoder + use configuration work.t48_decoder_rtl_c0; + end for; + + for dmem_ctrl_b : t48_dmem_ctrl + use configuration work.t48_dmem_ctrl_rtl_c0; + end for; + + for timer_b : t48_timer + use configuration work.t48_timer_rtl_c0; + end for; + + for p1_b : t48_p1 + use configuration work.t48_p1_rtl_c0; + end for; + + for p2_b : t48_p2 + use configuration work.t48_p2_rtl_c0; + end for; + + for pmem_ctrl_b : t48_pmem_ctrl + use configuration work.t48_pmem_ctrl_rtl_c0; + end for; + + for psw_b : t48_psw + use configuration work.t48_psw_rtl_c0; + end for; + + end for; + +end upi41_core_struct_c0; diff --git a/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/t48/upi41_core.v b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/t48/upi41_core.v new file mode 100644 index 0000000000000000000000000000000000000000..9d9387af0152ad47a2259cd01ab33f9702283734 --- /dev/null +++ b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/t48/upi41_core.v @@ -0,0 +1,15251 @@ +module t48_int + (input clk_i, + input res_i, + input en_clk_i, + input xtal_i, + input xtal_en_i, + input [2:0] clk_mstate_i, + input jtf_executed_i, + input tim_overflow_i, + input en_tcnti_i, + input dis_tcnti_i, + input int_n_i, + input ale_i, + input last_cycle_i, + input en_i_i, + input dis_i_i, + input retr_executed_i, + input int_executed_i, + output tf_o, + output ext_int_o, + output tim_int_o, + output int_pending_o, + output int_in_progress_o); + wire [1:0] int_state_s; + wire [1:0] int_state_q; + wire timer_flag_q; + wire timer_overflow_q; + wire timer_int_enable_q; + wire int_q; + wire int_enable_q; + wire ale_q; + wire int_type_q; + wire int_in_progress_q; + wire n5070_o; + wire n5072_o; + wire n5073_o; + wire [1:0] n5075_o; + wire n5077_o; + wire [1:0] n5079_o; + wire n5081_o; + wire [1:0] n5083_o; + wire n5085_o; + wire [2:0] n5086_o; + reg [1:0] n5088_o; + wire n5091_o; + wire n5094_o; + wire n5096_o; + wire n5097_o; + wire n5098_o; + wire n5099_o; + wire n5100_o; + wire n5102_o; + wire n5104_o; + wire n5106_o; + wire n5108_o; + wire n5110_o; + wire n5112_o; + wire n5113_o; + wire n5114_o; + wire n5115_o; + wire n5117_o; + wire n5124_o; + wire n5125_o; + wire n5126_o; + wire n5128_o; + wire n5129_o; + wire n5131_o; + wire n5162_o; + wire n5164_o; + wire n5165_o; + wire n5166_o; + wire n5174_o; + wire n5175_o; + wire n5177_o; + wire n5193_o; + wire n5194_o; + wire n5196_o; + wire n5198_o; + wire n5199_o; + wire [1:0] n5200_o; + reg [1:0] n5201_q; + wire n5202_o; + reg n5203_q; + wire n5204_o; + reg n5205_q; + wire n5206_o; + reg n5207_q; + wire n5208_o; + reg n5209_q; + wire n5210_o; + reg n5211_q; + wire n5212_o; + reg n5213_q; + wire n5214_o; + reg n5215_q; + wire n5216_o; + reg n5217_q; + assign tf_o = n5193_o; + assign ext_int_o = int_type_q; + assign tim_int_o = n5194_o; + assign int_pending_o = n5196_o; + assign int_in_progress_o = n5199_o; + /* int.vhd:91:10 */ + assign int_state_s = n5088_o; // (signal) + /* int.vhd:92:10 */ + assign int_state_q = n5201_q; // (signal) + /* int.vhd:94:10 */ + assign timer_flag_q = n5203_q; // (signal) + /* int.vhd:95:10 */ + assign timer_overflow_q = n5205_q; // (signal) + /* int.vhd:96:10 */ + assign timer_int_enable_q = n5207_q; // (signal) + /* int.vhd:97:10 */ + assign int_q = n5209_q; // (signal) + /* int.vhd:98:10 */ + assign int_enable_q = n5211_q; // (signal) + /* int.vhd:99:10 */ + assign ale_q = n5213_q; // (signal) + /* int.vhd:100:10 */ + assign int_type_q = n5215_q; // (signal) + /* int.vhd:101:10 */ + assign int_in_progress_q = n5217_q; // (signal) + /* int.vhd:123:30 */ + assign n5070_o = int_in_progress_q & last_cycle_i; + /* int.vhd:124:42 */ + assign n5072_o = clk_mstate_i == 3'b100; + /* int.vhd:124:25 */ + assign n5073_o = n5070_o & n5072_o; + /* int.vhd:123:9 */ + assign n5075_o = n5073_o ? 2'b01 : int_state_q; + /* int.vhd:122:7 */ + assign n5077_o = int_state_q == 2'b00; + /* int.vhd:129:9 */ + assign n5079_o = int_executed_i ? 2'b10 : int_state_q; + /* int.vhd:128:7 */ + assign n5081_o = int_state_q == 2'b01; + /* int.vhd:134:9 */ + assign n5083_o = retr_executed_i ? 2'b00 : int_state_q; + /* int.vhd:133:7 */ + assign n5085_o = int_state_q == 2'b10; + assign n5086_o = {n5085_o, n5081_o, n5077_o}; + /* int.vhd:121:5 */ + always @* + case (n5086_o) + 3'b100: n5088_o = n5083_o; + 3'b010: n5088_o = n5079_o; + 3'b001: n5088_o = n5075_o; + default: n5088_o = 2'b00; + endcase + /* int.vhd:158:14 */ + assign n5091_o = ~res_i; + /* int.vhd:174:9 */ + assign n5094_o = tim_overflow_i ? 1'b1 : timer_flag_q; + /* int.vhd:172:9 */ + assign n5096_o = jtf_executed_i ? 1'b0 : n5094_o; + /* int.vhd:178:24 */ + assign n5097_o = ~int_type_q; + /* int.vhd:178:36 */ + assign n5098_o = n5097_o & int_executed_i; + /* int.vhd:179:11 */ + assign n5099_o = ~timer_int_enable_q; + /* int.vhd:178:56 */ + assign n5100_o = n5098_o | n5099_o; + /* int.vhd:181:9 */ + assign n5102_o = tim_overflow_i ? 1'b1 : timer_overflow_q; + /* int.vhd:178:9 */ + assign n5104_o = n5100_o ? 1'b0 : n5102_o; + /* int.vhd:187:9 */ + assign n5106_o = en_tcnti_i ? 1'b1 : timer_int_enable_q; + /* int.vhd:185:9 */ + assign n5108_o = dis_tcnti_i ? 1'b0 : n5106_o; + /* int.vhd:193:9 */ + assign n5110_o = en_i_i ? 1'b1 : int_enable_q; + /* int.vhd:191:9 */ + assign n5112_o = dis_i_i ? 1'b0 : n5110_o; + /* int.vhd:199:22 */ + assign n5113_o = int_q & int_enable_q; + /* int.vhd:199:40 */ + assign n5114_o = n5113_o | timer_overflow_q; + /* int.vhd:202:14 */ + assign n5115_o = ~int_in_progress_q; + /* int.vhd:203:45 */ + assign n5117_o = int_q & int_enable_q; + /* t48_pack-p.vhd:66:5 */ + assign n5124_o = n5117_o ? 1'b1 : 1'b0; + /* int.vhd:199:9 */ + assign n5125_o = n5126_o ? n5124_o : int_type_q; + /* int.vhd:199:9 */ + assign n5126_o = n5114_o & n5115_o; + /* int.vhd:199:9 */ + assign n5128_o = n5114_o ? 1'b1 : int_in_progress_q; + /* int.vhd:197:9 */ + assign n5129_o = retr_executed_i ? int_type_q : n5125_o; + /* int.vhd:197:9 */ + assign n5131_o = retr_executed_i ? 1'b0 : n5128_o; + /* int.vhd:224:14 */ + assign n5162_o = ~res_i; + /* int.vhd:232:25 */ + assign n5164_o = last_cycle_i & ale_q; + /* int.vhd:233:22 */ + assign n5165_o = ~ale_i; + /* int.vhd:233:18 */ + assign n5166_o = n5164_o & n5165_o; + /* t48_pack-p.vhd:75:5 */ + assign n5174_o = int_n_i ? 1'b1 : 1'b0; + /* int.vhd:234:20 */ + assign n5175_o = ~n5174_o; + /* int.vhd:229:7 */ + assign n5177_o = xtal_en_i & n5166_o; + /* t48_pack-p.vhd:66:5 */ + assign n5193_o = timer_flag_q ? 1'b1 : 1'b0; + /* int.vhd:249:35 */ + assign n5194_o = ~int_type_q; + /* int.vhd:250:36 */ + assign n5196_o = int_state_q == 2'b01; + /* int.vhd:251:58 */ + assign n5198_o = int_state_q != 2'b00; + /* int.vhd:251:42 */ + assign n5199_o = int_in_progress_q & n5198_o; + /* int.vhd:167:5 */ + assign n5200_o = en_clk_i ? int_state_s : int_state_q; + /* int.vhd:167:5 */ + always @(posedge clk_i or posedge n5091_o) + if (n5091_o) + n5201_q <= 2'b00; + else + n5201_q <= n5200_o; + /* int.vhd:167:5 */ + assign n5202_o = en_clk_i ? n5096_o : timer_flag_q; + /* int.vhd:167:5 */ + always @(posedge clk_i or posedge n5091_o) + if (n5091_o) + n5203_q <= 1'b0; + else + n5203_q <= n5202_o; + /* int.vhd:167:5 */ + assign n5204_o = en_clk_i ? n5104_o : timer_overflow_q; + /* int.vhd:167:5 */ + always @(posedge clk_i or posedge n5091_o) + if (n5091_o) + n5205_q <= 1'b0; + else + n5205_q <= n5204_o; + /* int.vhd:167:5 */ + assign n5206_o = en_clk_i ? n5108_o : timer_int_enable_q; + /* int.vhd:167:5 */ + always @(posedge clk_i or posedge n5091_o) + if (n5091_o) + n5207_q <= 1'b0; + else + n5207_q <= n5206_o; + /* int.vhd:228:5 */ + assign n5208_o = n5177_o ? n5175_o : int_q; + /* int.vhd:228:5 */ + always @(posedge xtal_i or posedge n5162_o) + if (n5162_o) + n5209_q <= 1'b0; + else + n5209_q <= n5208_o; + /* int.vhd:167:5 */ + assign n5210_o = en_clk_i ? n5112_o : int_enable_q; + /* int.vhd:167:5 */ + always @(posedge clk_i or posedge n5091_o) + if (n5091_o) + n5211_q <= 1'b0; + else + n5211_q <= n5210_o; + /* int.vhd:228:5 */ + assign n5212_o = xtal_en_i ? ale_i : ale_q; + /* int.vhd:228:5 */ + always @(posedge xtal_i or posedge n5162_o) + if (n5162_o) + n5213_q <= 1'b0; + else + n5213_q <= n5212_o; + /* int.vhd:167:5 */ + assign n5214_o = en_clk_i ? n5129_o : int_type_q; + /* int.vhd:167:5 */ + always @(posedge clk_i or posedge n5091_o) + if (n5091_o) + n5215_q <= 1'b0; + else + n5215_q <= n5214_o; + /* int.vhd:167:5 */ + assign n5216_o = en_clk_i ? n5131_o : int_in_progress_q; + /* int.vhd:167:5 */ + always @(posedge clk_i or posedge n5091_o) + if (n5091_o) + n5217_q <= 1'b0; + else + n5217_q <= n5216_o; +endmodule + +module t48_psw + (input clk_i, + input res_i, + input en_clk_i, + input [7:0] data_i, + input read_psw_i, + input read_sp_i, + input write_psw_i, + input write_sp_i, + input special_data_i, + input inc_stackp_i, + input dec_stackp_i, + input write_carry_i, + input write_aux_carry_i, + input write_f0_i, + input write_bs_i, + input aux_carry_i, + output [7:0] data_o, + output carry_o, + output aux_carry_o, + output f0_o, + output bs_o); + wire [3:0] psw_q; + wire [2:0] sp_q; + wire n5002_o; + wire [2:0] n5006_o; + wire [2:0] n5007_o; + wire [2:0] n5009_o; + wire [2:0] n5010_o; + wire [2:0] n5012_o; + wire [2:0] n5013_o; + wire n5014_o; + wire n5015_o; + wire n5016_o; + wire n5017_o; + wire n5021_o; + wire n5022_o; + wire n5023_o; + wire n5024_o; + wire n5028_o; + wire n5029_o; + wire n5030_o; + wire n5031_o; + wire n5032_o; + wire n5033_o; + wire n5034_o; + wire n5035_o; + wire [3:0] n5036_o; + wire [3:0] n5048_o; + localparam [7:0] n5049_o = 8'b11111111; + wire [3:0] n5050_o; + wire [3:0] n5052_o; + wire [3:0] n5053_o; + wire n5055_o; + wire n5056_o; + wire n5057_o; + wire n5058_o; + wire [3:0] n5059_o; + reg [3:0] n5060_q; + wire [2:0] n5061_o; + reg [2:0] n5062_q; + wire [7:0] n5063_o; + assign data_o = n5063_o; + assign carry_o = n5055_o; + assign aux_carry_o = n5056_o; + assign f0_o = n5057_o; + assign bs_o = n5058_o; + /* psw.vhd:101:10 */ + assign psw_q = n5060_q; // (signal) + /* psw.vhd:103:10 */ + assign sp_q = n5062_q; // (signal) + /* psw.vhd:119:14 */ + assign n5002_o = ~res_i; + /* psw.vhd:131:34 */ + assign n5006_o = data_i[2:0]; + /* psw.vhd:130:9 */ + assign n5007_o = write_sp_i ? n5006_o : sp_q; + /* psw.vhd:136:25 */ + assign n5009_o = sp_q + 3'b001; + /* psw.vhd:135:9 */ + assign n5010_o = inc_stackp_i ? n5009_o : n5007_o; + /* psw.vhd:140:25 */ + assign n5012_o = sp_q - 3'b001; + /* psw.vhd:139:9 */ + assign n5013_o = dec_stackp_i ? n5012_o : n5010_o; + assign n5014_o = data_i[7]; + assign n5015_o = psw_q[3]; + /* psw.vhd:127:9 */ + assign n5016_o = write_psw_i ? n5014_o : n5015_o; + /* psw.vhd:144:9 */ + assign n5017_o = write_carry_i ? special_data_i : n5016_o; + assign n5021_o = data_i[6]; + assign n5022_o = psw_q[2]; + /* psw.vhd:127:9 */ + assign n5023_o = write_psw_i ? n5021_o : n5022_o; + /* psw.vhd:148:9 */ + assign n5024_o = write_aux_carry_i ? aux_carry_i : n5023_o; + assign n5028_o = data_i[5]; + assign n5029_o = psw_q[1]; + /* psw.vhd:127:9 */ + assign n5030_o = write_psw_i ? n5028_o : n5029_o; + /* psw.vhd:152:9 */ + assign n5031_o = write_f0_i ? special_data_i : n5030_o; + assign n5032_o = data_i[4]; + assign n5033_o = psw_q[0]; + /* psw.vhd:127:9 */ + assign n5034_o = write_psw_i ? n5032_o : n5033_o; + /* psw.vhd:156:9 */ + assign n5035_o = write_bs_i ? special_data_i : n5034_o; + assign n5036_o = {n5017_o, n5024_o, n5031_o, n5035_o}; + /* psw.vhd:182:5 */ + assign n5048_o = read_psw_i ? psw_q : 4'b1111; + assign n5050_o = n5049_o[3:0]; + /* psw.vhd:187:33 */ + assign n5052_o = {1'b1, sp_q}; + /* psw.vhd:186:5 */ + assign n5053_o = read_sp_i ? n5052_o : n5050_o; + /* psw.vhd:207:23 */ + assign n5055_o = psw_q[3]; + /* psw.vhd:208:23 */ + assign n5056_o = psw_q[2]; + /* psw.vhd:209:23 */ + assign n5057_o = psw_q[1]; + /* psw.vhd:210:23 */ + assign n5058_o = psw_q[0]; + /* psw.vhd:123:5 */ + assign n5059_o = en_clk_i ? n5036_o : psw_q; + /* psw.vhd:123:5 */ + always @(posedge clk_i or posedge n5002_o) + if (n5002_o) + n5060_q <= 4'b0000; + else + n5060_q <= n5059_o; + /* psw.vhd:123:5 */ + assign n5061_o = en_clk_i ? n5013_o : sp_q; + /* psw.vhd:123:5 */ + always @(posedge clk_i or posedge n5002_o) + if (n5002_o) + n5062_q <= 3'b000; + else + n5062_q <= n5061_o; + /* psw.vhd:119:5 */ + assign n5063_o = {n5048_o, n5053_o}; +endmodule + +module t48_pmem_ctrl + (input clk_i, + input res_i, + input en_clk_i, + input [7:0] data_i, + input write_pcl_i, + input read_pcl_i, + input write_pch_i, + input read_pch_i, + input inc_pc_i, + input write_pmem_addr_i, + input [1:0] addr_type_i, + input read_pmem_i, + input [7:0] pmem_data_i, + output [7:0] data_o, + output [11:0] pmem_addr_o); + wire [11:0] program_counter_q; + wire [11:0] pmem_addr_s; + wire [11:0] pmem_addr_q; + wire n4928_o; + wire [3:0] n4930_o; + wire [10:0] n4931_o; + wire [10:0] n4933_o; + wire [10:0] n4934_o; + wire [10:0] n4935_o; + wire [7:0] n4936_o; + wire [7:0] n4937_o; + wire [7:0] n4938_o; + wire [2:0] n4939_o; + wire [2:0] n4940_o; + wire [2:0] n4941_o; + wire n4942_o; + wire n4943_o; + wire n4944_o; + wire [11:0] n4945_o; + wire [7:0] n4946_o; + wire [7:0] n4947_o; + wire [3:0] n4948_o; + wire [3:0] n4949_o; + wire [3:0] n4950_o; + wire [11:0] n4952_o; + wire n4954_o; + wire n4964_o; + wire n4966_o; + wire n4969_o; + wire [2:0] n4970_o; + wire [7:0] n4971_o; + reg [7:0] n4972_o; + wire [3:0] n4973_o; + reg [3:0] n4974_o; + wire [7:0] n4978_o; + wire [3:0] n4979_o; + wire [3:0] n4981_o; + wire [3:0] n4982_o; + wire [3:0] n4983_o; + wire [3:0] n4984_o; + wire [3:0] n4986_o; + wire [7:0] n4987_o; + wire [7:0] n4988_o; + wire [11:0] n4991_o; + reg [11:0] n4992_q; + wire [11:0] n4993_o; + wire [11:0] n4994_o; + reg [11:0] n4995_q; + assign data_o = n4988_o; + assign pmem_addr_o = pmem_addr_q; + /* pmem_ctrl.vhd:98:10 */ + assign program_counter_q = n4992_q; // (signal) + /* pmem_ctrl.vhd:102:10 */ + assign pmem_addr_s = n4993_o; // (signal) + /* pmem_ctrl.vhd:103:10 */ + assign pmem_addr_q = n4995_q; // (signal) + /* pmem_ctrl.vhd:115:14 */ + assign n4928_o = ~res_i; + /* pmem_ctrl.vhd:127:28 */ + assign n4930_o = data_i[3:0]; + /* pmem_ctrl.vhd:133:30 */ + assign n4931_o = program_counter_q[10:0]; + /* pmem_ctrl.vhd:133:49 */ + assign n4933_o = n4931_o + 11'b00000000001; + /* p2.vhd:153:3 */ + assign n4934_o = program_counter_q[10:0]; + /* pmem_ctrl.vhd:128:9 */ + assign n4935_o = inc_pc_i ? n4933_o : n4934_o; + /* p2.vhd:115:5 */ + assign n4936_o = n4935_o[7:0]; + /* p2.vhd:115:5 */ + assign n4937_o = program_counter_q[7:0]; + /* pmem_ctrl.vhd:125:9 */ + assign n4938_o = write_pch_i ? n4937_o : n4936_o; + /* decoder.vhd:521:15 */ + assign n4939_o = n4935_o[10:8]; + /* decoder.vhd:521:15 */ + assign n4940_o = n4930_o[2:0]; + /* pmem_ctrl.vhd:125:9 */ + assign n4941_o = write_pch_i ? n4940_o : n4939_o; + /* p2.vhd:155:5 */ + assign n4942_o = n4930_o[3]; + assign n4943_o = program_counter_q[11]; + /* pmem_ctrl.vhd:125:9 */ + assign n4944_o = write_pch_i ? n4942_o : n4943_o; + /* decoder_pack-p.vhd:116:14 */ + assign n4945_o = {n4944_o, n4941_o, n4938_o}; + assign n4946_o = n4945_o[7:0]; + /* pmem_ctrl.vhd:123:9 */ + assign n4947_o = write_pcl_i ? data_i : n4946_o; + assign n4948_o = n4945_o[11:8]; + /* decoder_pack-p.vhd:114:14 */ + assign n4949_o = program_counter_q[11:8]; + /* pmem_ctrl.vhd:123:9 */ + assign n4950_o = write_pcl_i ? n4949_o : n4948_o; + /* decoder_pack-p.vhd:112:12 */ + assign n4952_o = {n4950_o, n4947_o}; + /* pmem_ctrl.vhd:120:7 */ + assign n4954_o = en_clk_i & write_pmem_addr_i; + /* pmem_ctrl.vhd:165:7 */ + assign n4964_o = addr_type_i == 2'b00; + /* pmem_ctrl.vhd:169:7 */ + assign n4966_o = addr_type_i == 2'b01; + /* pmem_ctrl.vhd:175:7 */ + assign n4969_o = addr_type_i == 2'b10; + /* decoder_pack-p.vhd:545:14 */ + assign n4970_o = {n4969_o, n4966_o, n4964_o}; + assign n4971_o = program_counter_q[7:0]; + /* pmem_ctrl.vhd:164:5 */ + always @* + case (n4970_o) + 3'b100: n4972_o = data_i; + 3'b010: n4972_o = data_i; + 3'b001: n4972_o = n4971_o; + default: n4972_o = n4971_o; + endcase + assign n4973_o = program_counter_q[11:8]; + /* pmem_ctrl.vhd:164:5 */ + always @* + case (n4970_o) + 3'b100: n4974_o = 4'b0011; + 3'b010: n4974_o = n4973_o; + 3'b001: n4974_o = n4973_o; + default: n4974_o = n4973_o; + endcase + /* pmem_ctrl.vhd:207:51 */ + assign n4978_o = program_counter_q[7:0]; + /* pmem_ctrl.vhd:209:63 */ + assign n4979_o = program_counter_q[11:8]; + /* pmem_ctrl.vhd:208:5 */ + assign n4981_o = read_pch_i ? n4979_o : 4'b1111; + assign n4982_o = n4978_o[3:0]; + /* pmem_ctrl.vhd:206:5 */ + assign n4983_o = read_pcl_i ? n4982_o : n4981_o; + assign n4984_o = n4978_o[7:4]; + /* pmem_ctrl.vhd:206:5 */ + assign n4986_o = read_pcl_i ? n4984_o : 4'b1111; + assign n4987_o = {n4986_o, n4983_o}; + /* pmem_ctrl.vhd:204:5 */ + assign n4988_o = read_pmem_i ? pmem_data_i : n4987_o; + /* pmem_ctrl.vhd:119:5 */ + assign n4991_o = en_clk_i ? n4952_o : program_counter_q; + /* pmem_ctrl.vhd:119:5 */ + always @(posedge clk_i or posedge n4928_o) + if (n4928_o) + n4992_q <= 12'b000000000000; + else + n4992_q <= n4991_o; + /* pmem_ctrl.vhd:115:5 */ + assign n4993_o = {n4974_o, n4972_o}; + /* pmem_ctrl.vhd:119:5 */ + assign n4994_o = n4954_o ? pmem_addr_s : pmem_addr_q; + /* pmem_ctrl.vhd:119:5 */ + always @(posedge clk_i or posedge n4928_o) + if (n4928_o) + n4995_q <= 12'b000000000000; + else + n4995_q <= n4994_o; +endmodule + +module t48_p2 + (input clk_i, + input res_i, + input en_clk_i, + input xtal_i, + input xtal_en_i, + input [7:0] data_i, + input write_p2_i, + input write_exp_i, + input read_p2_i, + input read_reg_i, + input read_exp_i, + input output_pch_i, + input [3:0] pch_i, + input [7:0] p2_i, + output [7:0] data_o, + output [7:0] p2_o, + output p2l_low_imp_o, + output p2h_low_imp_o); + wire [7:0] p2_q; + wire l_low_imp_q; + wire h_low_imp_q; + wire en_clk_q; + wire l_low_imp_del_q; + wire h_low_imp_del_q; + wire output_pch_q; + wire n4827_o; + wire [3:0] n4829_o; + wire [3:0] n4830_o; + wire [3:0] n4831_o; + wire n4834_o; + wire [3:0] n4835_o; + wire [3:0] n4836_o; + wire [3:0] n4837_o; + wire [3:0] n4838_o; + wire [3:0] n4839_o; + wire n4841_o; + wire n4845_o; + wire [7:0] n4847_o; + wire n4862_o; + wire [3:0] n4864_o; + wire [3:0] n4865_o; + wire [3:0] n4866_o; + wire n4867_o; + wire n4868_o; + wire n4869_o; + wire n4872_o; + wire n4873_o; + wire n4876_o; + wire [7:0] n4877_o; + wire [3:0] n4900_o; + wire [7:0] n4902_o; + wire [7:0] n4903_o; + wire [7:0] n4904_o; + wire [7:0] n4906_o; + wire [7:0] n4909_o; + reg [7:0] n4910_q; + wire n4911_o; + reg n4912_q; + wire n4913_o; + reg n4914_q; + wire n4915_o; + reg n4916_q; + wire n4917_o; + reg n4918_q; + wire n4919_o; + reg n4920_q; + wire n4921_o; + reg n4922_q; + wire [7:0] n4923_o; + reg [7:0] n4924_q; + assign data_o = n4906_o; + assign p2_o = n4924_q; + assign p2l_low_imp_o = l_low_imp_del_q; + assign p2h_low_imp_o = h_low_imp_del_q; + /* p2.vhd:89:10 */ + assign p2_q = n4910_q; // (signal) + /* p2.vhd:92:10 */ + assign l_low_imp_q = n4912_q; // (signal) + /* p2.vhd:93:10 */ + assign h_low_imp_q = n4914_q; // (signal) + /* p2.vhd:95:10 */ + assign en_clk_q = n4916_q; // (signal) + /* p2.vhd:96:10 */ + assign l_low_imp_del_q = n4918_q; // (signal) + /* p2.vhd:97:10 */ + assign h_low_imp_del_q = n4920_q; // (signal) + /* p2.vhd:98:10 */ + assign output_pch_q = n4922_q; // (signal) + /* p2.vhd:110:14 */ + assign n4827_o = ~res_i; + /* p2.vhd:129:41 */ + assign n4829_o = data_i[3:0]; + /* decoder.vhd:496:15 */ + assign n4830_o = p2_q[3:0]; + /* p2.vhd:127:9 */ + assign n4831_o = write_exp_i ? n4829_o : n4830_o; + /* p2.vhd:127:9 */ + assign n4834_o = write_exp_i ? 1'b1 : 1'b0; + /* decoder.vhd:521:15 */ + assign n4835_o = data_i[3:0]; + /* p2.vhd:121:9 */ + assign n4836_o = write_p2_i ? n4835_o : n4831_o; + /* decoder.vhd:521:15 */ + assign n4837_o = data_i[7:4]; + /* decoder.vhd:521:15 */ + assign n4838_o = p2_q[7:4]; + /* p2.vhd:121:9 */ + assign n4839_o = write_p2_i ? n4837_o : n4838_o; + /* p2.vhd:121:9 */ + assign n4841_o = write_p2_i ? 1'b1 : n4834_o; + /* p2.vhd:121:9 */ + assign n4845_o = write_p2_i ? 1'b1 : 1'b0; + assign n4847_o = {n4839_o, n4836_o}; + /* p2.vhd:155:14 */ + assign n4862_o = ~res_i; + /* decoder.vhd:506:15 */ + assign n4864_o = p2_q[3:0]; + /* p2.vhd:170:9 */ + assign n4865_o = output_pch_i ? pch_i : n4864_o; + /* decoder.vhd:499:26 */ + assign n4866_o = p2_q[7:4]; + /* p2.vhd:179:26 */ + assign n4867_o = output_pch_q ^ output_pch_i; + /* p2.vhd:179:44 */ + assign n4868_o = n4867_o | l_low_imp_q; + /* p2.vhd:178:21 */ + assign n4869_o = en_clk_q & n4868_o; + /* p2.vhd:178:9 */ + assign n4872_o = n4869_o ? 1'b1 : 1'b0; + /* p2.vhd:189:21 */ + assign n4873_o = en_clk_q & h_low_imp_q; + /* p2.vhd:189:9 */ + assign n4876_o = n4873_o ? 1'b1 : 1'b0; + /* decoder.vhd:499:22 */ + assign n4877_o = {n4866_o, n4865_o}; + /* p2.vhd:221:32 */ + assign n4900_o = p2_i[3:0]; + /* p2.vhd:221:26 */ + assign n4902_o = {4'b0000, n4900_o}; + /* p2.vhd:220:7 */ + assign n4903_o = read_exp_i ? n4902_o : p2_i; + /* p2.vhd:218:7 */ + assign n4904_o = read_reg_i ? p2_q : n4903_o; + /* p2.vhd:217:5 */ + assign n4906_o = read_p2_i ? n4904_o : 8'b11111111; + /* p2.vhd:115:5 */ + assign n4909_o = en_clk_i ? n4847_o : p2_q; + /* p2.vhd:115:5 */ + always @(posedge clk_i or posedge n4827_o) + if (n4827_o) + n4910_q <= 8'b11111111; + else + n4910_q <= n4909_o; + /* p2.vhd:115:5 */ + assign n4911_o = en_clk_i ? n4841_o : l_low_imp_q; + /* p2.vhd:115:5 */ + always @(posedge clk_i or posedge n4827_o) + if (n4827_o) + n4912_q <= 1'b0; + else + n4912_q <= n4911_o; + /* p2.vhd:115:5 */ + assign n4913_o = en_clk_i ? n4845_o : h_low_imp_q; + /* p2.vhd:115:5 */ + always @(posedge clk_i or posedge n4827_o) + if (n4827_o) + n4914_q <= 1'b0; + else + n4914_q <= n4913_o; + /* p2.vhd:162:5 */ + assign n4915_o = xtal_en_i ? en_clk_i : en_clk_q; + /* p2.vhd:162:5 */ + always @(posedge xtal_i or posedge n4862_o) + if (n4862_o) + n4916_q <= 1'b0; + else + n4916_q <= n4915_o; + /* p2.vhd:162:5 */ + assign n4917_o = xtal_en_i ? n4872_o : l_low_imp_del_q; + /* p2.vhd:162:5 */ + always @(posedge xtal_i or posedge n4862_o) + if (n4862_o) + n4918_q <= 1'b0; + else + n4918_q <= n4917_o; + /* p2.vhd:162:5 */ + assign n4919_o = xtal_en_i ? n4876_o : h_low_imp_del_q; + /* p2.vhd:162:5 */ + always @(posedge xtal_i or posedge n4862_o) + if (n4862_o) + n4920_q <= 1'b0; + else + n4920_q <= n4919_o; + /* p2.vhd:162:5 */ + assign n4921_o = xtal_en_i ? output_pch_i : output_pch_q; + /* p2.vhd:162:5 */ + always @(posedge xtal_i or posedge n4862_o) + if (n4862_o) + n4922_q <= 1'b0; + else + n4922_q <= n4921_o; + /* p2.vhd:162:5 */ + assign n4923_o = xtal_en_i ? n4877_o : n4924_q; + /* p2.vhd:162:5 */ + always @(posedge xtal_i or posedge n4862_o) + if (n4862_o) + n4924_q <= 8'b11111111; + else + n4924_q <= n4923_o; +endmodule + +module t48_p1 + (input clk_i, + input res_i, + input en_clk_i, + input [7:0] data_i, + input write_p1_i, + input read_p1_i, + input read_reg_i, + input [7:0] p1_i, + output [7:0] data_o, + output [7:0] p1_o, + output p1_low_imp_o); + wire [7:0] p1_q; + wire low_imp_q; + wire n4797_o; + wire n4802_o; + wire n4803_o; + wire [7:0] n4813_o; + wire [7:0] n4815_o; + wire [7:0] n4818_o; + reg [7:0] n4819_q; + wire n4820_o; + reg n4821_q; + assign data_o = n4815_o; + assign p1_o = p1_q; + assign p1_low_imp_o = low_imp_q; + /* p1.vhd:81:10 */ + assign p1_q = n4819_q; // (signal) + /* p1.vhd:84:10 */ + assign low_imp_q = n4821_q; // (signal) + /* p1.vhd:96:14 */ + assign n4797_o = ~res_i; + /* p1.vhd:103:9 */ + assign n4802_o = write_p1_i ? 1'b1 : 1'b0; + /* p1.vhd:101:7 */ + assign n4803_o = en_clk_i & write_p1_i; + /* p1.vhd:133:7 */ + assign n4813_o = read_reg_i ? p1_q : p1_i; + /* p1.vhd:132:5 */ + assign n4815_o = read_p1_i ? n4813_o : 8'b11111111; + /* p1.vhd:100:5 */ + assign n4818_o = n4803_o ? data_i : p1_q; + /* p1.vhd:100:5 */ + always @(posedge clk_i or posedge n4797_o) + if (n4797_o) + n4819_q <= 8'b11111111; + else + n4819_q <= n4818_o; + /* p1.vhd:100:5 */ + assign n4820_o = en_clk_i ? n4802_o : low_imp_q; + /* p1.vhd:100:5 */ + always @(posedge clk_i or posedge n4797_o) + if (n4797_o) + n4821_q <= 1'b0; + else + n4821_q <= n4820_o; +endmodule + +module t48_timer_4 + (input clk_i, + input res_i, + input en_clk_i, + input t1_i, + input [2:0] clk_mstate_i, + input [7:0] data_i, + input read_timer_i, + input write_timer_i, + input start_t_i, + input start_cnt_i, + input stop_tcnt_i, + output [7:0] data_o, + output overflow_o); + wire [7:0] counter_q; + wire overflow_q; + wire increment_s; + wire [1:0] inc_sel_q; + wire t1_q; + wire t1_inc_s; + wire [4:0] prescaler_q; + wire pre_inc_s; + wire n4683_o; + wire n4685_o; + wire n4687_o; + wire n4688_o; + wire n4689_o; + wire n4692_o; + wire n4694_o; + wire n4698_o; + wire n4700_o; + wire n4701_o; + wire n4704_o; + wire n4706_o; + wire n4708_o; + wire [2:0] n4709_o; + reg n4712_o; + wire n4716_o; + wire [7:0] n4719_o; + wire n4721_o; + wire n4724_o; + wire [7:0] n4725_o; + wire n4727_o; + wire [7:0] n4728_o; + wire n4730_o; + wire n4733_o; + wire n4735_o; + wire n4737_o; + wire n4740_o; + wire [4:0] n4742_o; + wire [4:0] n4743_o; + wire [4:0] n4745_o; + wire [1:0] n4747_o; + wire [1:0] n4749_o; + wire [1:0] n4751_o; + wire n4755_o; + wire [7:0] n4773_o; + wire n4782_o; + wire [7:0] n4783_o; + reg [7:0] n4784_q; + wire n4785_o; + reg n4786_q; + wire [1:0] n4787_o; + reg [1:0] n4788_q; + wire n4789_o; + reg n4790_q; + wire [4:0] n4791_o; + reg [4:0] n4792_q; + assign data_o = n4773_o; + assign overflow_o = n4782_o; + /* timer.vhd:89:10 */ + assign counter_q = n4784_q; // (signal) + /* timer.vhd:90:10 */ + assign overflow_q = n4786_q; // (signal) + /* timer.vhd:94:10 */ + assign increment_s = n4712_o; // (signal) + /* timer.vhd:95:10 */ + assign inc_sel_q = n4788_q; // (signal) + /* timer.vhd:98:10 */ + assign t1_q = n4790_q; // (signal) + /* timer.vhd:99:10 */ + assign t1_inc_s = n4694_o; // (signal) + /* timer.vhd:102:10 */ + assign prescaler_q = n4792_q; // (signal) + /* timer.vhd:103:10 */ + assign pre_inc_s = n4701_o; // (signal) + /* timer.vhd:134:48 */ + assign n4683_o = clk_mstate_i == 3'b011; + /* timer.vhd:134:31 */ + assign n4685_o = 1'b1 & n4683_o; + /* timer.vhd:133:59 */ + assign n4687_o = 1'b0 | n4685_o; + /* timer.vhd:136:30 */ + assign n4688_o = ~t1_i; + /* timer.vhd:136:21 */ + assign n4689_o = t1_q & n4688_o; + /* timer.vhd:136:7 */ + assign n4692_o = n4689_o ? 1'b1 : 1'b0; + /* timer.vhd:133:5 */ + assign n4694_o = n4687_o ? n4692_o : 1'b0; + /* timer.vhd:146:29 */ + assign n4698_o = clk_mstate_i == 3'b011; + /* timer.vhd:146:55 */ + assign n4700_o = prescaler_q == 5'b11111; + /* timer.vhd:146:39 */ + assign n4701_o = n4698_o & n4700_o; + /* timer.vhd:163:7 */ + assign n4704_o = inc_sel_q == 2'b00; + /* timer.vhd:165:7 */ + assign n4706_o = inc_sel_q == 2'b01; + /* timer.vhd:167:7 */ + assign n4708_o = inc_sel_q == 2'b10; + assign n4709_o = {n4708_o, n4706_o, n4704_o}; + /* timer.vhd:162:5 */ + always @* + case (n4709_o) + 3'b100: n4712_o = t1_inc_s; + 3'b010: n4712_o = pre_inc_s; + 3'b001: n4712_o = 1'b0; + default: n4712_o = 1'b0; + endcase + /* timer.vhd:186:14 */ + assign n4716_o = ~res_i; + /* timer.vhd:203:37 */ + assign n4719_o = counter_q + 8'b00000001; + /* timer.vhd:205:24 */ + assign n4721_o = counter_q == 8'b11111111; + /* timer.vhd:205:11 */ + assign n4724_o = n4721_o ? 1'b1 : 1'b0; + /* timer.vhd:202:9 */ + assign n4725_o = increment_s ? n4719_o : counter_q; + /* timer.vhd:202:9 */ + assign n4727_o = increment_s ? n4724_o : 1'b0; + /* timer.vhd:199:9 */ + assign n4728_o = write_timer_i ? data_i : n4725_o; + /* timer.vhd:199:9 */ + assign n4730_o = write_timer_i ? 1'b0 : n4727_o; + /* timer.vhd:213:52 */ + assign n4733_o = clk_mstate_i == 3'b011; + /* timer.vhd:213:35 */ + assign n4735_o = 1'b1 & n4733_o; + /* timer.vhd:212:63 */ + assign n4737_o = 1'b0 | n4735_o; + /* timer.vhd:221:28 */ + assign n4740_o = clk_mstate_i == 3'b010; + /* timer.vhd:222:39 */ + assign n4742_o = prescaler_q + 5'b00001; + /* timer.vhd:221:9 */ + assign n4743_o = n4740_o ? n4742_o : prescaler_q; + /* timer.vhd:218:9 */ + assign n4745_o = start_t_i ? 5'b00000 : n4743_o; + /* timer.vhd:231:9 */ + assign n4747_o = stop_tcnt_i ? 2'b00 : inc_sel_q; + /* timer.vhd:229:9 */ + assign n4749_o = start_cnt_i ? 2'b10 : n4747_o; + /* timer.vhd:227:9 */ + assign n4751_o = start_t_i ? 2'b01 : n4749_o; + /* timer.vhd:194:7 */ + assign n4755_o = en_clk_i & n4737_o; + /* timer.vhd:248:17 */ + assign n4773_o = read_timer_i ? counter_q : 8'b11111111; + /* t48_pack-p.vhd:66:5 */ + assign n4782_o = overflow_q ? 1'b1 : 1'b0; + /* timer.vhd:193:5 */ + assign n4783_o = en_clk_i ? n4728_o : counter_q; + /* timer.vhd:193:5 */ + always @(posedge clk_i or posedge n4716_o) + if (n4716_o) + n4784_q <= 8'b00000000; + else + n4784_q <= n4783_o; + /* timer.vhd:193:5 */ + assign n4785_o = en_clk_i ? n4730_o : overflow_q; + /* timer.vhd:193:5 */ + always @(posedge clk_i or posedge n4716_o) + if (n4716_o) + n4786_q <= 1'b0; + else + n4786_q <= n4785_o; + /* timer.vhd:193:5 */ + assign n4787_o = en_clk_i ? n4751_o : inc_sel_q; + /* timer.vhd:193:5 */ + always @(posedge clk_i or posedge n4716_o) + if (n4716_o) + n4788_q <= 2'b00; + else + n4788_q <= n4787_o; + /* timer.vhd:193:5 */ + assign n4789_o = n4755_o ? t1_i : t1_q; + /* timer.vhd:193:5 */ + always @(posedge clk_i or posedge n4716_o) + if (n4716_o) + n4790_q <= 1'b0; + else + n4790_q <= n4789_o; + /* timer.vhd:193:5 */ + assign n4791_o = en_clk_i ? n4745_o : prescaler_q; + /* timer.vhd:193:5 */ + always @(posedge clk_i or posedge n4716_o) + if (n4716_o) + n4792_q <= 5'b00000; + else + n4792_q <= n4791_o; +endmodule + +module t48_dmem_ctrl + (input clk_i, + input res_i, + input en_clk_i, + input [7:0] data_i, + input write_dmem_addr_i, + input write_dmem_i, + input read_dmem_i, + input [1:0] addr_type_i, + input bank_select_i, + input [7:0] dmem_data_i, + output [7:0] data_o, + output [7:0] dmem_addr_o, + output dmem_we_o, + output [7:0] dmem_data_o); + wire [7:0] dmem_addr_s; + wire [7:0] dmem_addr_q; + wire n4600_o; + wire [2:0] n4601_o; + localparam [7:0] n4602_o = 8'b00000000; + wire [1:0] n4605_o; + wire [1:0] n4606_o; + wire [2:0] n4607_o; + wire n4609_o; + wire [2:0] n4610_o; + wire [5:0] n4613_o; + wire [5:0] n4615_o; + localparam [7:0] n4616_o = 8'b00000000; + wire [1:0] n4617_o; + wire n4619_o; + wire n4622_o; + wire [3:0] n4623_o; + wire n4624_o; + wire n4625_o; + wire n4626_o; + wire n4627_o; + reg n4628_o; + wire [1:0] n4629_o; + wire [1:0] n4630_o; + wire [1:0] n4631_o; + wire [1:0] n4632_o; + reg [1:0] n4633_o; + wire [1:0] n4634_o; + wire [1:0] n4635_o; + wire [1:0] n4636_o; + reg [1:0] n4637_o; + wire n4638_o; + wire n4639_o; + wire n4640_o; + wire n4641_o; + reg n4642_o; + wire [1:0] n4643_o; + wire [1:0] n4644_o; + wire [1:0] n4645_o; + reg [1:0] n4646_o; + wire n4656_o; + wire n4659_o; + wire n4664_o; + wire [7:0] n4665_o; + wire [7:0] n4666_o; + wire n4675_o; + wire [7:0] n4676_o; + wire [7:0] n4677_o; + reg [7:0] n4678_q; + assign data_o = n4666_o; + assign dmem_addr_o = n4665_o; + assign dmem_we_o = n4675_o; + assign dmem_data_o = data_i; + /* dmem_ctrl.vhd:91:10 */ + assign dmem_addr_s = n4676_o; // (signal) + /* dmem_ctrl.vhd:92:10 */ + assign dmem_addr_q = n4678_q; // (signal) + /* dmem_ctrl.vhd:112:7 */ + assign n4600_o = addr_type_i == 2'b00; + /* dmem_ctrl.vhd:117:44 */ + assign n4601_o = data_i[2:0]; + /* decoder.vhd:155:5 */ + assign n4605_o = n4602_o[4:3]; + /* dmem_ctrl.vhd:119:9 */ + assign n4606_o = bank_select_i ? 2'b11 : n4605_o; + /* decoder.vhd:153:5 */ + assign n4607_o = n4602_o[7:5]; + /* dmem_ctrl.vhd:115:7 */ + assign n4609_o = addr_type_i == 2'b01; + /* dmem_ctrl.vhd:126:53 */ + assign n4610_o = data_i[2:0]; + /* decoder.vhd:142:5 */ + assign n4613_o = {2'b00, n4610_o, 1'b0}; + /* dmem_ctrl.vhd:128:51 */ + assign n4615_o = n4613_o + 6'b001000; + /* decoder.vhd:135:5 */ + assign n4617_o = n4616_o[7:6]; + /* dmem_ctrl.vhd:124:7 */ + assign n4619_o = addr_type_i == 2'b10; + /* dmem_ctrl.vhd:133:7 */ + assign n4622_o = addr_type_i == 2'b11; + /* decoder.vhd:125:5 */ + assign n4623_o = {n4622_o, n4619_o, n4609_o, n4600_o}; + /* decoder.vhd:124:5 */ + assign n4624_o = data_i[0]; + /* decoder.vhd:123:5 */ + assign n4625_o = n4601_o[0]; + /* decoder.vhd:121:5 */ + assign n4626_o = n4615_o[0]; + /* decoder.vhd:120:5 */ + assign n4627_o = dmem_addr_q[0]; + /* dmem_ctrl.vhd:111:5 */ + always @* + case (n4623_o) + 4'b1000: n4628_o = 1'b1; + 4'b0100: n4628_o = n4626_o; + 4'b0010: n4628_o = n4625_o; + 4'b0001: n4628_o = n4624_o; + default: n4628_o = n4627_o; + endcase + /* decoder.vhd:116:5 */ + assign n4629_o = data_i[2:1]; + /* decoder.vhd:115:5 */ + assign n4630_o = n4601_o[2:1]; + /* decoder.vhd:114:5 */ + assign n4631_o = n4615_o[2:1]; + /* decoder.vhd:113:5 */ + assign n4632_o = dmem_addr_q[2:1]; + /* dmem_ctrl.vhd:111:5 */ + always @* + case (n4623_o) + 4'b1000: n4633_o = n4632_o; + 4'b0100: n4633_o = n4631_o; + 4'b0010: n4633_o = n4630_o; + 4'b0001: n4633_o = n4629_o; + default: n4633_o = n4632_o; + endcase + /* decoder.vhd:109:5 */ + assign n4634_o = data_i[4:3]; + /* decoder.vhd:108:5 */ + assign n4635_o = n4615_o[4:3]; + /* decoder.vhd:107:5 */ + assign n4636_o = dmem_addr_q[4:3]; + /* dmem_ctrl.vhd:111:5 */ + always @* + case (n4623_o) + 4'b1000: n4637_o = n4636_o; + 4'b0100: n4637_o = n4635_o; + 4'b0010: n4637_o = n4606_o; + 4'b0001: n4637_o = n4634_o; + default: n4637_o = n4636_o; + endcase + /* decoder.vhd:105:5 */ + assign n4638_o = data_i[5]; + /* decoder.vhd:104:5 */ + assign n4639_o = n4607_o[0]; + /* decoder.vhd:103:5 */ + assign n4640_o = n4615_o[5]; + /* decoder.vhd:102:5 */ + assign n4641_o = dmem_addr_q[5]; + /* dmem_ctrl.vhd:111:5 */ + always @* + case (n4623_o) + 4'b1000: n4642_o = n4641_o; + 4'b0100: n4642_o = n4640_o; + 4'b0010: n4642_o = n4639_o; + 4'b0001: n4642_o = n4638_o; + default: n4642_o = n4641_o; + endcase + /* decoder.vhd:100:5 */ + assign n4643_o = data_i[7:6]; + /* decoder.vhd:99:5 */ + assign n4644_o = n4607_o[2:1]; + /* decoder.vhd:98:5 */ + assign n4645_o = dmem_addr_q[7:6]; + /* dmem_ctrl.vhd:111:5 */ + always @* + case (n4623_o) + 4'b1000: n4646_o = n4645_o; + 4'b0100: n4646_o = n4617_o; + 4'b0010: n4646_o = n4644_o; + 4'b0001: n4646_o = n4643_o; + default: n4646_o = n4645_o; + endcase + /* dmem_ctrl.vhd:165:14 */ + assign n4656_o = ~res_i; + /* dmem_ctrl.vhd:169:7 */ + assign n4659_o = en_clk_i & write_dmem_addr_i; + /* dmem_ctrl.vhd:188:41 */ + assign n4664_o = write_dmem_addr_i & en_clk_i; + /* dmem_ctrl.vhd:188:18 */ + assign n4665_o = n4664_o ? dmem_addr_s : dmem_addr_q; + /* dmem_ctrl.vhd:196:18 */ + assign n4666_o = read_dmem_i ? dmem_data_i : 8'b11111111; + /* t48_pack-p.vhd:66:5 */ + assign n4675_o = write_dmem_i ? 1'b1 : 1'b0; + assign n4676_o = {n4646_o, n4642_o, n4637_o, n4633_o, n4628_o}; + /* dmem_ctrl.vhd:168:5 */ + assign n4677_o = n4659_o ? dmem_addr_s : dmem_addr_q; + /* dmem_ctrl.vhd:168:5 */ + always @(posedge clk_i or posedge n4656_o) + if (n4656_o) + n4678_q <= 8'b00000000; + else + n4678_q <= n4677_o; +endmodule + +module t48_decoder_1_1_1 + (input clk_i, + input res_i, + input en_clk_i, + input xtal_i, + input xtal_en_i, + input ea_i, + input ale_i, + input int_n_i, + input [7:0] data_i, + input bus_set_f1_i, + input bus_clear_f1_i, + input alu_carry_i, + input alu_da_overflow_i, + input [2:0] clk_mstate_i, + input clk_second_cycle_i, + input cnd_take_branch_i, + input psw_carry_i, + input psw_aux_carry_i, + input psw_f0_i, + input tim_overflow_i, + output t0_dir_o, + output [7:0] data_o, + output alu_write_accu_o, + output alu_write_shadow_o, + output alu_write_temp_reg_o, + output alu_read_alu_o, + output bus_write_bus_o, + output bus_read_bus_o, + output bus_ibf_int_o, + output bus_en_dma_o, + output bus_en_flags_o, + output bus_write_sts_o, + output dm_write_dmem_addr_o, + output dm_write_dmem_o, + output dm_read_dmem_o, + output p1_write_p1_o, + output p1_read_p1_o, + output p2_write_p2_o, + output p2_write_exp_o, + output p2_read_p2_o, + output p2_read_exp_o, + output pm_write_pcl_o, + output pm_read_pcl_o, + output pm_write_pch_o, + output pm_read_pch_o, + output pm_read_pmem_o, + output psw_read_psw_o, + output psw_read_sp_o, + output psw_write_psw_o, + output psw_write_sp_o, + output [3:0] alu_op_o, + output alu_use_carry_o, + output alu_da_high_o, + output alu_accu_low_o, + output alu_p06_temp_reg_o, + output alu_p60_temp_reg_o, + output bus_output_pcl_o, + output bus_bidir_bus_o, + output clk_multi_cycle_o, + output clk_assert_psen_o, + output clk_assert_prog_o, + output clk_assert_rd_o, + output clk_assert_wr_o, + output cnd_compute_take_o, + output [3:0] cnd_branch_cond_o, + output [2:0] cnd_comp_value_o, + output cnd_f1_o, + output cnd_tf_o, + output [1:0] dm_addr_type_o, + output p1_read_reg_o, + output p2_read_reg_o, + output p2_output_pch_o, + output pm_inc_pc_o, + output pm_write_pmem_addr_o, + output [1:0] pm_addr_type_o, + output psw_special_data_o, + output psw_inc_stackp_o, + output psw_dec_stackp_o, + output psw_write_carry_o, + output psw_write_aux_carry_o, + output psw_write_f0_o, + output psw_write_bs_o, + output tim_read_timer_o, + output tim_write_timer_o, + output tim_start_t_o, + output tim_start_cnt_o, + output tim_stop_tcnt_o); + wire opc_multi_cycle_s; + wire opc_read_bus_s; + wire opc_inj_int_s; + wire [7:0] opc_opcode_q; + wire [5:0] opc_mnemonic_s; + wire last_cycle_s; + wire assert_psen_s; + wire branch_taken_s; + wire branch_taken_q; + wire pm_inc_pc_s; + wire pm_write_pmem_addr_s; + wire add_inc_pc_s; + wire add_write_pmem_addr_s; + wire clear_f1_s; + wire cpl_f1_s; + wire f1_q; + wire clear_mb_s; + wire set_mb_s; + wire mb_q; + wire ent0_clk_s; + wire t0_dir_q; + wire [7:0] data_s; + wire read_dec_s; + wire tf_s; + wire bus_read_bus_s; + wire add_read_bus_s; + wire dm_write_dmem_s; + wire p2_output_exp_s; + wire movx_first_cycle_s; + wire jtf_executed_s; + wire en_tcnti_s; + wire dis_tcnti_s; + wire en_i_s; + wire dis_i_s; + wire tim_int_s; + wire retr_executed_s; + wire int_executed_s; + wire int_pending_s; + wire int_in_progress_s; + wire [6:0] mnemonic_rec_s; + wire [5:0] mnemonic_q; + wire n1240_o; + wire n1242_o; + wire n1243_o; + wire n1245_o; + wire [1:0] n1246_o; + reg [5:0] n1250_o; + wire n1253_o; + wire n1263_o; + wire n1265_o; + wire n1266_o; + wire n1268_o; + wire n1270_o; + wire n1272_o; + wire n1274_o; + wire n1276_o; + wire n1277_o; + wire n1279_o; + wire n1281_o; + wire n1283_o; + wire n1284_o; + wire [6:0] n1285_o; + reg [5:0] n1294_o; + reg n1302_o; + wire n1305_o; + wire n1315_o; + wire n1317_o; + wire n1318_o; + wire n1320_o; + wire n1321_o; + wire n1323_o; + wire n1324_o; + wire n1326_o; + wire n1327_o; + wire n1329_o; + wire n1330_o; + wire n1332_o; + wire n1333_o; + wire n1335_o; + wire n1336_o; + wire n1338_o; + wire n1339_o; + wire n1341_o; + wire n1342_o; + wire n1344_o; + wire n1345_o; + wire n1347_o; + wire n1348_o; + wire n1350_o; + wire n1351_o; + wire n1353_o; + wire n1354_o; + wire n1356_o; + wire n1357_o; + wire n1359_o; + wire n1360_o; + wire n1362_o; + wire n1363_o; + wire n1365_o; + wire n1366_o; + wire n1368_o; + wire n1369_o; + wire n1371_o; + wire n1372_o; + wire n1374_o; + wire n1376_o; + wire n1377_o; + wire n1379_o; + wire n1381_o; + wire n1382_o; + wire n1384_o; + wire n1385_o; + wire n1387_o; + wire n1388_o; + wire n1390_o; + wire n1391_o; + wire n1393_o; + wire n1394_o; + wire n1396_o; + wire n1397_o; + wire n1399_o; + wire n1400_o; + wire n1402_o; + wire n1403_o; + wire n1405_o; + wire n1406_o; + wire n1408_o; + wire n1410_o; + wire n1412_o; + wire n1413_o; + wire n1415_o; + wire n1416_o; + wire n1418_o; + wire n1419_o; + wire n1421_o; + wire n1422_o; + wire n1424_o; + wire n1425_o; + wire n1427_o; + wire n1428_o; + wire n1430_o; + wire n1431_o; + wire n1433_o; + wire n1435_o; + wire n1437_o; + wire n1439_o; + wire n1440_o; + wire n1442_o; + wire n1444_o; + wire n1446_o; + wire n1448_o; + wire n1449_o; + wire n1451_o; + wire n1453_o; + wire n1455_o; + wire n1456_o; + wire n1458_o; + wire n1459_o; + wire n1461_o; + wire n1462_o; + wire n1464_o; + wire n1465_o; + wire n1467_o; + wire n1468_o; + wire n1470_o; + wire n1471_o; + wire n1473_o; + wire n1474_o; + wire n1476_o; + wire n1477_o; + wire n1479_o; + wire n1481_o; + wire n1482_o; + wire n1484_o; + wire n1486_o; + wire n1487_o; + wire n1489_o; + wire n1491_o; + wire n1492_o; + wire n1494_o; + wire n1495_o; + wire n1497_o; + wire n1498_o; + wire n1500_o; + wire n1501_o; + wire n1503_o; + wire n1504_o; + wire n1506_o; + wire n1507_o; + wire n1509_o; + wire n1510_o; + wire n1512_o; + wire n1514_o; + wire n1515_o; + wire n1517_o; + wire n1519_o; + wire n1520_o; + wire n1522_o; + wire n1523_o; + wire n1525_o; + wire n1526_o; + wire n1528_o; + wire n1529_o; + wire n1531_o; + wire n1532_o; + wire n1534_o; + wire n1535_o; + wire n1537_o; + wire n1538_o; + wire n1540_o; + wire n1541_o; + wire n1543_o; + wire n1544_o; + wire n1546_o; + wire n1547_o; + wire n1549_o; + wire n1551_o; + wire n1552_o; + wire n1554_o; + wire n1555_o; + wire n1557_o; + wire n1558_o; + wire n1560_o; + wire n1561_o; + wire n1563_o; + wire n1564_o; + wire n1566_o; + wire n1567_o; + wire n1569_o; + wire n1570_o; + wire n1572_o; + wire n1574_o; + wire n1575_o; + wire n1577_o; + wire n1579_o; + wire n1580_o; + wire n1582_o; + wire n1584_o; + wire n1585_o; + wire n1587_o; + wire n1588_o; + wire n1590_o; + wire n1591_o; + wire n1593_o; + wire n1594_o; + wire n1596_o; + wire n1597_o; + wire n1599_o; + wire n1600_o; + wire n1602_o; + wire n1603_o; + wire n1605_o; + wire n1607_o; + wire n1609_o; + wire n1610_o; + wire n1612_o; + wire n1613_o; + wire n1615_o; + wire n1616_o; + wire n1618_o; + wire n1620_o; + wire n1622_o; + wire n1623_o; + wire n1625_o; + wire n1627_o; + wire n1629_o; + wire n1631_o; + wire n1632_o; + wire n1634_o; + wire n1635_o; + wire n1637_o; + wire n1638_o; + wire n1640_o; + wire n1641_o; + wire n1643_o; + wire n1644_o; + wire n1646_o; + wire n1647_o; + wire n1649_o; + wire n1650_o; + wire n1652_o; + wire n1653_o; + wire n1655_o; + wire n1656_o; + wire n1658_o; + wire n1660_o; + wire n1662_o; + wire n1663_o; + wire n1665_o; + wire n1666_o; + wire n1668_o; + wire n1669_o; + wire n1671_o; + wire n1672_o; + wire n1674_o; + wire n1675_o; + wire n1677_o; + wire n1678_o; + wire n1680_o; + wire n1681_o; + wire n1683_o; + wire n1684_o; + wire n1686_o; + wire n1687_o; + wire n1689_o; + wire n1691_o; + wire n1692_o; + wire n1694_o; + wire n1695_o; + wire n1697_o; + wire n1698_o; + wire n1700_o; + wire n1701_o; + wire n1703_o; + wire n1704_o; + wire n1706_o; + wire n1707_o; + wire n1709_o; + wire n1710_o; + wire n1712_o; + wire n1713_o; + wire n1715_o; + wire n1716_o; + wire n1718_o; + wire n1720_o; + wire n1721_o; + wire n1723_o; + wire n1725_o; + wire n1726_o; + wire n1728_o; + wire n1729_o; + wire n1731_o; + wire n1732_o; + wire n1734_o; + wire n1736_o; + wire n1737_o; + wire n1739_o; + wire n1741_o; + wire n1743_o; + wire n1744_o; + wire n1746_o; + wire n1747_o; + wire n1749_o; + wire n1750_o; + wire n1752_o; + wire n1753_o; + wire n1755_o; + wire n1756_o; + wire n1758_o; + wire n1759_o; + wire n1761_o; + wire n1762_o; + wire n1764_o; + wire n1765_o; + wire n1767_o; + wire n1768_o; + wire n1770_o; + wire n1772_o; + wire n1774_o; + wire n1775_o; + wire n1777_o; + wire n1778_o; + wire n1780_o; + wire n1781_o; + wire n1783_o; + wire n1784_o; + wire n1786_o; + wire n1787_o; + wire n1789_o; + wire n1790_o; + wire n1792_o; + wire n1793_o; + wire n1795_o; + wire n1796_o; + wire n1798_o; + wire n1799_o; + wire n1801_o; + wire n1802_o; + wire n1804_o; + wire n1805_o; + wire n1807_o; + wire n1809_o; + wire n1810_o; + wire n1812_o; + wire n1814_o; + wire n1815_o; + wire n1817_o; + wire n1819_o; + wire n1820_o; + wire n1822_o; + wire n1824_o; + wire n1825_o; + wire n1827_o; + wire n1829_o; + wire n1831_o; + wire n1832_o; + wire n1834_o; + wire n1836_o; + wire n1838_o; + wire n1839_o; + wire n1841_o; + wire n1842_o; + wire n1844_o; + wire n1845_o; + wire n1847_o; + wire n1848_o; + wire n1850_o; + wire n1851_o; + wire n1853_o; + wire n1854_o; + wire n1856_o; + wire n1857_o; + wire n1859_o; + wire n1860_o; + wire n1862_o; + wire n1863_o; + wire n1865_o; + wire n1866_o; + wire n1868_o; + wire n1869_o; + wire n1871_o; + wire n1873_o; + wire n1874_o; + wire n1876_o; + wire n1877_o; + wire n1879_o; + wire n1880_o; + wire n1882_o; + wire n1883_o; + wire n1885_o; + wire n1886_o; + wire n1888_o; + wire n1889_o; + wire n1891_o; + wire n1892_o; + wire n1894_o; + wire n1895_o; + wire n1897_o; + wire n1898_o; + wire n1900_o; + wire [48:0] n1901_o; + reg [5:0] n1952_o; + reg n1976_o; + wire [6:0] n1980_o; + wire [6:0] n1981_o; + wire [6:0] n1982_o; + wire [6:0] n1985_o; + wire [6:0] n1986_o; + wire n1989_o; + wire [5:0] n1991_o; + wire [7:0] n1993_o; + wire [5:0] n1994_o; + wire [7:0] n1995_o; + wire [5:0] n1996_o; + wire n2006_o; + wire [5:0] n2008_o; + wire [5:0] n2009_o; + wire int_b_n2010; + wire int_b_n2012; + wire int_b_n2013; + wire int_b_n2014; + wire int_b_tf_o; + wire int_b_ext_int_o; + wire int_b_tim_int_o; + wire int_b_int_pending_o; + wire int_b_int_in_progress_o; + wire n2024_o; + wire n2025_o; + wire n2026_o; + wire n2029_o; + wire n2030_o; + wire n2031_o; + wire n2032_o; + wire n2033_o; + wire n2036_o; + wire n2037_o; + wire n2040_o; + wire n2042_o; + wire n2045_o; + wire n2047_o; + wire n2049_o; + wire n2051_o; + wire n2053_o; + wire n2054_o; + wire n2055_o; + wire n2058_o; + wire n2061_o; + wire n2063_o; + wire n2065_o; + wire n2067_o; + wire n2068_o; + wire n2069_o; + wire n2070_o; + wire n2071_o; + wire n2074_o; + wire n2076_o; + wire n2079_o; + wire n2081_o; + wire n2082_o; + wire n2083_o; + wire n2084_o; + wire n2085_o; + wire n2088_o; + wire n2091_o; + wire n2094_o; + wire n2096_o; + wire n2097_o; + wire n2098_o; + wire n2099_o; + wire n2100_o; + wire n2101_o; + wire n2102_o; + wire n2105_o; + wire n2107_o; + wire [4:0] n2108_o; + reg n2110_o; + reg n2113_o; + reg n2116_o; + reg n2119_o; + reg n2122_o; + reg n2125_o; + reg n2128_o; + reg n2131_o; + reg n2134_o; + wire n2141_o; + wire n2142_o; + wire n2144_o; + wire n2145_o; + wire n2146_o; + wire [2:0] n2147_o; + wire n2148_o; + wire [2:0] n2150_o; + wire [2:0] n2151_o; + localparam [7:0] n2152_o = 8'b00000000; + wire [4:0] n2153_o; + wire n2156_o; + wire [7:0] n2158_o; + localparam [7:0] n2159_o = 8'bX; + wire [7:0] n2160_o; + wire n2164_o; + wire n2166_o; + wire n2167_o; + wire n2169_o; + wire n2176_o; + wire n2179_o; + wire [1:0] n2182_o; + wire n2184_o; + wire n2189_o; + wire n2193_o; + wire n2196_o; + wire n2198_o; + wire [2:0] n2199_o; + reg n2202_o; + reg n2205_o; + reg n2208_o; + reg n2209_o; + reg n2212_o; + reg [3:0] n2215_o; + reg n2217_o; + reg [1:0] n2219_o; + reg n2221_o; + reg n2224_o; + reg n2227_o; + wire n2229_o; + wire n2231_o; + wire n2235_o; + wire n2238_o; + wire n2240_o; + wire [1:0] n2241_o; + reg n2244_o; + reg n2247_o; + reg n2250_o; + reg [3:0] n2253_o; + reg n2255_o; + reg n2257_o; + reg n2260_o; + reg n2263_o; + wire n2265_o; + wire n2267_o; + wire n2269_o; + wire [3:0] n2271_o; + wire n2273_o; + wire n2275_o; + wire n2277_o; + wire n2279_o; + wire n2281_o; + wire n2282_o; + wire n2283_o; + wire n2285_o; + wire n2292_o; + wire n2295_o; + wire [1:0] n2298_o; + wire n2300_o; + wire n2305_o; + wire n2310_o; + wire [2:0] n2311_o; + reg n2314_o; + reg n2317_o; + reg n2320_o; + reg n2321_o; + reg n2324_o; + reg [3:0] n2327_o; + reg [1:0] n2329_o; + wire n2331_o; + wire n2333_o; + wire n2338_o; + wire [1:0] n2339_o; + reg n2342_o; + reg n2345_o; + reg n2348_o; + reg [3:0] n2351_o; + wire n2353_o; + wire n2355_o; + wire n2357_o; + wire [3:0] n2359_o; + wire n2361_o; + wire n2362_o; + wire n2364_o; + wire [1:0] n2365_o; + wire n2367_o; + wire n2368_o; + wire n2369_o; + wire n2372_o; + wire n2375_o; + wire n2378_o; + wire n2381_o; + wire n2383_o; + wire n2385_o; + wire n2387_o; + wire n2389_o; + wire n2392_o; + wire n2395_o; + wire n2397_o; + wire n2399_o; + wire n2401_o; + wire n2403_o; + wire n2405_o; + wire n2407_o; + wire n2409_o; + wire [1:0] n2410_o; + wire n2412_o; + wire n2413_o; + wire n2414_o; + wire n2417_o; + wire n2420_o; + wire n2423_o; + wire n2425_o; + wire n2427_o; + wire n2429_o; + wire [2:0] n2430_o; + reg n2434_o; + reg n2438_o; + reg n2440_o; + reg n2442_o; + reg n2444_o; + reg [3:0] n2447_o; + wire n2449_o; + wire n2451_o; + wire n2453_o; + wire n2455_o; + wire n2457_o; + wire n2459_o; + wire n2461_o; + wire n2463_o; + wire [3:0] n2465_o; + wire n2467_o; + wire n2469_o; + wire n2471_o; + wire n2473_o; + wire n2474_o; + wire n2475_o; + wire n2478_o; + wire n2480_o; + wire n2482_o; + wire n2484_o; + wire [2:0] n2485_o; + reg n2488_o; + reg n2491_o; + reg n2494_o; + reg n2497_o; + reg n2500_o; + reg [1:0] n2504_o; + reg n2507_o; + reg n2509_o; + reg n2513_o; + localparam [7:0] n2515_o = 8'b00000000; + wire n2520_o; + wire n2521_o; + wire n2522_o; + wire [4:0] n2523_o; + wire n2525_o; + wire [7:0] n2526_o; + wire [7:0] n2527_o; + wire n2529_o; + wire n2531_o; + wire n2532_o; + wire [4:0] n2534_o; + wire [2:0] n2535_o; + wire [7:0] n2536_o; + wire [7:0] n2538_o; + wire n2541_o; + wire n2543_o; + wire [1:0] n2544_o; + reg n2546_o; + reg n2549_o; + reg n2552_o; + reg n2555_o; + reg [7:0] n2556_o; + reg n2558_o; + reg n2560_o; + wire n2562_o; + wire n2563_o; + wire n2565_o; + wire n2567_o; + wire n2569_o; + wire n2571_o; + wire n2573_o; + wire n2575_o; + wire [1:0] n2577_o; + wire n2579_o; + wire n2581_o; + wire n2583_o; + wire [7:0] n2584_o; + wire n2585_o; + wire n2587_o; + wire n2589_o; + wire n2591_o; + wire n2593_o; + wire n2596_o; + wire n2599_o; + wire [3:0] n2602_o; + wire n2604_o; + wire n2606_o; + wire n2609_o; + wire n2611_o; + wire n2613_o; + wire n2614_o; + wire n2615_o; + wire n2618_o; + wire n2621_o; + wire n2623_o; + wire n2625_o; + wire n2627_o; + wire n2629_o; + wire n2632_o; + wire n2635_o; + wire [3:0] n2638_o; + wire n2640_o; + wire n2642_o; + wire n2643_o; + wire n2645_o; + wire n2648_o; + wire n2650_o; + wire n2652_o; + wire n2653_o; + wire n2654_o; + wire n2655_o; + wire n2657_o; + wire n2660_o; + wire n2663_o; + wire n2665_o; + wire n2667_o; + wire n2669_o; + wire n2671_o; + wire n2673_o; + wire n2674_o; + wire n2677_o; + wire n2680_o; + wire n2682_o; + wire [3:0] n2685_o; + wire n2687_o; + wire n2689_o; + wire [2:0] n2690_o; + reg n2693_o; + reg n2695_o; + reg n2698_o; + reg [3:0] n2700_o; + reg n2704_o; + reg n2707_o; + reg n2710_o; + reg n2712_o; + reg n2715_o; + wire n2717_o; + wire n2718_o; + wire n2721_o; + wire n2724_o; + wire n2726_o; + wire n2727_o; + wire n2728_o; + wire n2731_o; + wire n2734_o; + wire n2736_o; + wire [1:0] n2737_o; + reg n2739_o; + reg n2741_o; + reg n2744_o; + reg n2746_o; + reg [3:0] n2749_o; + reg n2751_o; + wire n2753_o; + wire n2755_o; + wire n2756_o; + wire n2759_o; + wire n2762_o; + wire n2764_o; + wire n2766_o; + wire n2768_o; + wire n2770_o; + wire n2771_o; + wire n2774_o; + wire n2777_o; + wire n2779_o; + wire n2781_o; + wire n2783_o; + wire n2784_o; + wire n2786_o; + wire n2789_o; + wire [1:0] n2790_o; + reg n2793_o; + reg n2796_o; + reg n2799_o; + reg [3:0] n2802_o; + reg n2805_o; + reg [3:0] n2808_o; + wire n2809_o; + reg n2810_o; + reg n2813_o; + wire n2815_o; + wire n2816_o; + wire n2822_o; + wire n2825_o; + wire n2827_o; + wire n2829_o; + wire n2831_o; + wire n2833_o; + wire [3:0] n2835_o; + wire n2837_o; + wire [3:0] n2839_o; + wire n2840_o; + wire n2841_o; + wire n2843_o; + wire n2845_o; + wire n2847_o; + wire n2849_o; + wire n2850_o; + wire n2851_o; + wire n2854_o; + wire n2857_o; + wire n2859_o; + wire n2861_o; + wire n2863_o; + wire n2865_o; + wire n2868_o; + wire n2870_o; + wire n2872_o; + wire n2873_o; + wire n2874_o; + wire n2875_o; + wire n2878_o; + wire n2881_o; + wire n2884_o; + wire n2886_o; + wire n2888_o; + wire n2890_o; + wire n2892_o; + wire n2895_o; + wire n2898_o; + wire n2900_o; + wire n2902_o; + wire n2903_o; + wire n2906_o; + wire n2909_o; + wire n2911_o; + wire n2912_o; + wire n2913_o; + wire n2915_o; + wire n2922_o; + wire n2925_o; + wire [1:0] n2928_o; + wire n2930_o; + wire [1:0] n2931_o; + wire n2933_o; + wire n2936_o; + wire n2939_o; + wire n2941_o; + wire [1:0] n2942_o; + wire n2944_o; + wire n2947_o; + wire n2950_o; + wire n2952_o; + wire [2:0] n2953_o; + reg n2955_o; + reg n2957_o; + reg n2960_o; + reg n2961_o; + reg n2963_o; + reg [3:0] n2966_o; + reg [1:0] n2968_o; + reg n2970_o; + wire n2972_o; + wire n2973_o; + wire n2975_o; + wire n2978_o; + wire n2981_o; + wire n2983_o; + wire n2984_o; + wire n2990_o; + wire n2993_o; + wire n2995_o; + wire n2997_o; + wire n2999_o; + wire n3001_o; + wire n3003_o; + wire n3004_o; + wire n3006_o; + wire n3007_o; + wire n3010_o; + wire n3011_o; + wire n3012_o; + wire n3014_o; + wire n3015_o; + wire n3021_o; + wire n3024_o; + wire n3026_o; + wire n3028_o; + wire n3030_o; + wire n3032_o; + wire n3034_o; + wire n3035_o; + wire n3037_o; + wire n3038_o; + wire [3:0] n3041_o; + wire n3044_o; + wire [3:0] n3046_o; + wire n3048_o; + wire n3049_o; + wire n3055_o; + wire n3058_o; + wire n3060_o; + wire n3062_o; + wire [3:0] n3064_o; + wire n3066_o; + wire n3068_o; + wire n3070_o; + wire [4:0] n3072_o; + wire [2:0] n3073_o; + wire [7:0] n3074_o; + wire n3076_o; + wire [1:0] n3077_o; + reg n3080_o; + reg n3083_o; + reg n3086_o; + reg [7:0] n3087_o; + reg n3089_o; + wire n3091_o; + wire n3093_o; + wire n3095_o; + wire [7:0] n3096_o; + wire n3097_o; + wire n3099_o; + wire n3100_o; + wire n3102_o; + wire n3105_o; + wire [1:0] n3108_o; + wire n3110_o; + wire n3113_o; + wire n3116_o; + wire n3118_o; + wire n3120_o; + wire [1:0] n3122_o; + wire n3124_o; + wire n3126_o; + wire n3127_o; + wire n3129_o; + wire n3132_o; + wire n3134_o; + wire n3135_o; + wire n3141_o; + wire n3144_o; + wire n3146_o; + wire n3148_o; + wire n3150_o; + wire n3152_o; + wire n3153_o; + wire n3155_o; + wire n3158_o; + wire n3160_o; + wire n3161_o; + wire n3167_o; + wire n3170_o; + wire n3172_o; + wire n3174_o; + wire n3176_o; + wire n3178_o; + wire n3179_o; + wire n3181_o; + wire n3184_o; + wire n3186_o; + wire n3187_o; + wire n3193_o; + wire n3196_o; + wire n3198_o; + wire n3200_o; + wire n3202_o; + wire n3204_o; + wire n3205_o; + wire n3206_o; + wire [3:0] n3209_o; + wire n3210_o; + wire n3212_o; + wire n3213_o; + wire n3216_o; + wire n3217_o; + wire n3218_o; + wire n3220_o; + wire n3221_o; + wire n3227_o; + wire n3230_o; + wire n3232_o; + wire n3234_o; + wire n3236_o; + wire n3238_o; + wire n3240_o; + wire n3241_o; + wire n3243_o; + wire n3246_o; + wire n3249_o; + wire n3251_o; + wire n3252_o; + wire n3258_o; + wire n3261_o; + wire n3263_o; + wire n3265_o; + wire n3267_o; + wire n3269_o; + wire n3271_o; + wire n3272_o; + wire n3274_o; + wire n3275_o; + wire n3278_o; + wire n3281_o; + wire n3282_o; + wire n3283_o; + wire n3285_o; + wire n3286_o; + wire n3292_o; + wire n3295_o; + wire n3297_o; + wire n3299_o; + wire n3301_o; + wire n3303_o; + wire n3305_o; + wire n3307_o; + wire n3309_o; + wire n3310_o; + wire n3313_o; + wire n3315_o; + wire n3316_o; + wire n3317_o; + wire n3319_o; + wire n3326_o; + wire n3329_o; + wire [1:0] n3332_o; + wire n3334_o; + wire n3339_o; + wire [1:0] n3340_o; + reg n3343_o; + reg n3346_o; + reg n3347_o; + reg n3350_o; + reg [1:0] n3352_o; + wire n3354_o; + wire n3356_o; + wire n3359_o; + wire n3362_o; + wire n3365_o; + wire n3367_o; + wire n3369_o; + wire n3372_o; + wire n3375_o; + wire n3378_o; + wire n3380_o; + wire n3381_o; + wire n3382_o; + wire n3384_o; + wire n3391_o; + wire n3394_o; + wire [1:0] n3397_o; + wire n3399_o; + wire n3401_o; + wire [1:0] n3402_o; + reg n3405_o; + reg n3406_o; + reg n3408_o; + reg [1:0] n3410_o; + reg n3413_o; + wire n3415_o; + wire n3416_o; + wire n3418_o; + wire n3419_o; + wire n3420_o; + wire n3421_o; + wire n3423_o; + wire n3430_o; + wire n3433_o; + wire [1:0] n3436_o; + wire n3437_o; + wire n3439_o; + wire [1:0] n3441_o; + wire n3443_o; + wire n3444_o; + wire n3447_o; + wire n3449_o; + wire n3451_o; + wire n3454_o; + wire n3457_o; + wire n3459_o; + wire n3461_o; + wire n3462_o; + wire n3465_o; + wire n3468_o; + wire n3471_o; + wire n3474_o; + wire n3476_o; + wire n3478_o; + wire n3480_o; + wire n3482_o; + wire n3484_o; + wire n3485_o; + wire [1:0] n3487_o; + wire [3:0] n3488_o; + wire n3491_o; + wire n3494_o; + wire n3497_o; + wire [2:0] n3498_o; + wire [1:0] n3499_o; + wire [1:0] n3500_o; + wire [1:0] n3501_o; + reg [1:0] n3502_o; + wire n3504_o; + wire n3506_o; + wire n3508_o; + wire [2:0] n3509_o; + reg n3512_o; + reg n3516_o; + wire [1:0] n3517_o; + wire [1:0] n3518_o; + wire [1:0] n3519_o; + reg [1:0] n3520_o; + wire [1:0] n3521_o; + wire [1:0] n3522_o; + wire [1:0] n3523_o; + reg [1:0] n3524_o; + wire [3:0] n3525_o; + wire [3:0] n3526_o; + wire [3:0] n3527_o; + reg [3:0] n3528_o; + reg n3530_o; + reg n3534_o; + wire n3536_o; + wire n3538_o; + wire n3539_o; + wire n3542_o; + wire n3544_o; + wire n3546_o; + wire [7:0] n3547_o; + wire [7:0] n3548_o; + wire n3549_o; + wire n3550_o; + wire n3552_o; + wire n3553_o; + wire [1:0] n3554_o; + wire [7:0] n3556_o; + wire n3558_o; + wire n3561_o; + wire n3563_o; + wire [2:0] n3564_o; + reg n3568_o; + wire [3:0] n3569_o; + wire [3:0] n3570_o; + wire [3:0] n3571_o; + wire [3:0] n3572_o; + reg [3:0] n3573_o; + wire [3:0] n3574_o; + wire [3:0] n3575_o; + wire [3:0] n3576_o; + wire [3:0] n3577_o; + reg [3:0] n3578_o; + reg n3581_o; + reg n3585_o; + wire n3587_o; + wire n3589_o; + wire [1:0] n3590_o; + reg n3593_o; + reg n3596_o; + reg n3599_o; + reg n3603_o; + wire n3605_o; + wire n3607_o; + wire n3609_o; + wire n3611_o; + wire [7:0] n3612_o; + wire [7:0] n3613_o; + wire n3614_o; + wire n3615_o; + wire n3617_o; + wire n3618_o; + wire n3620_o; + wire n3621_o; + wire n3622_o; + wire [1:0] n3625_o; + wire n3628_o; + wire [1:0] n3630_o; + wire n3632_o; + wire n3635_o; + wire n3638_o; + wire n3640_o; + wire n3642_o; + wire [1:0] n3644_o; + wire n3646_o; + wire n3648_o; + wire n3649_o; + wire n3650_o; + wire n3653_o; + wire n3656_o; + wire n3657_o; + wire n3659_o; + wire n3660_o; + wire n3663_o; + wire n3666_o; + wire n3668_o; + wire [1:0] n3669_o; + reg n3671_o; + reg n3674_o; + reg n3677_o; + wire n3679_o; + wire n3680_o; + wire n3681_o; + wire n3684_o; + wire n3687_o; + wire n3690_o; + wire n3693_o; + wire n3695_o; + wire n3697_o; + wire n3699_o; + wire n3701_o; + wire n3703_o; + wire n3704_o; + wire n3705_o; + wire n3707_o; + wire n3709_o; + wire n3712_o; + wire n3714_o; + wire n3716_o; + wire n3717_o; + wire n3718_o; + wire n3720_o; + wire n3727_o; + wire n3730_o; + wire [1:0] n3733_o; + wire n3735_o; + wire n3740_o; + wire n3745_o; + wire [2:0] n3746_o; + reg n3749_o; + reg n3752_o; + reg n3755_o; + reg n3756_o; + reg n3759_o; + reg [3:0] n3762_o; + reg [1:0] n3764_o; + wire n3766_o; + wire n3768_o; + wire n3773_o; + wire [1:0] n3774_o; + reg n3777_o; + reg n3780_o; + reg n3783_o; + reg [3:0] n3786_o; + wire n3788_o; + wire n3790_o; + wire n3792_o; + wire [3:0] n3794_o; + wire n3796_o; + wire n3797_o; + wire n3799_o; + wire [1:0] n3800_o; + wire n3802_o; + wire n3803_o; + wire n3804_o; + wire n3807_o; + wire n3810_o; + wire n3813_o; + wire n3816_o; + wire n3818_o; + wire n3820_o; + wire n3822_o; + wire n3824_o; + wire n3827_o; + wire n3830_o; + wire n3832_o; + wire n3834_o; + wire n3836_o; + wire n3838_o; + wire n3840_o; + wire n3842_o; + wire n3844_o; + wire [1:0] n3845_o; + wire n3847_o; + wire n3848_o; + wire n3849_o; + wire n3852_o; + wire n3855_o; + wire n3858_o; + wire n3860_o; + wire n3862_o; + wire n3864_o; + wire [2:0] n3865_o; + reg n3869_o; + reg n3873_o; + reg n3875_o; + reg n3877_o; + reg n3879_o; + reg [3:0] n3882_o; + wire n3884_o; + wire n3886_o; + wire n3888_o; + wire n3890_o; + wire n3892_o; + wire n3894_o; + wire n3896_o; + wire n3898_o; + wire [3:0] n3900_o; + wire n3902_o; + wire n3904_o; + wire n3906_o; + wire n3908_o; + wire n3910_o; + wire n3913_o; + wire n3916_o; + wire n3918_o; + wire n3919_o; + wire n3920_o; + wire n3923_o; + wire n3924_o; + wire n3926_o; + wire n3927_o; + wire n3928_o; + wire n3929_o; + wire n3930_o; + wire n3933_o; + wire n3936_o; + wire n3939_o; + wire n3941_o; + wire n3943_o; + wire n3946_o; + wire n3948_o; + wire n3950_o; + wire n3952_o; + wire n3954_o; + wire n3955_o; + wire n3957_o; + wire n3959_o; + wire n3961_o; + wire [2:0] n3962_o; + reg n3965_o; + reg n3968_o; + reg n3971_o; + reg n3974_o; + reg [1:0] n3978_o; + reg n3981_o; + wire n3982_o; + wire n3985_o; + wire n3988_o; + wire n3990_o; + wire n3992_o; + wire [1:0] n3993_o; + reg n3996_o; + reg n3999_o; + reg n4001_o; + reg n4004_o; + reg n4006_o; + wire n4007_o; + wire n4008_o; + wire n4010_o; + wire n4012_o; + wire n4014_o; + wire n4016_o; + wire [1:0] n4018_o; + wire n4020_o; + wire n4022_o; + wire n4024_o; + wire n4026_o; + wire n4028_o; + wire n4029_o; + wire n4032_o; + wire n4034_o; + wire n4037_o; + wire n4040_o; + wire n4043_o; + wire [3:0] n4046_o; + wire n4048_o; + wire n4050_o; + wire n4052_o; + wire n4054_o; + wire n4056_o; + wire n4057_o; + wire n4058_o; + wire n4061_o; + wire n4063_o; + wire n4066_o; + wire n4069_o; + wire n4072_o; + wire [3:0] n4075_o; + wire n4077_o; + wire n4079_o; + wire n4081_o; + wire n4083_o; + wire n4085_o; + wire n4086_o; + wire n4089_o; + wire n4092_o; + wire n4094_o; + wire n4096_o; + wire n4098_o; + wire n4100_o; + wire n4101_o; + wire n4103_o; + wire n4106_o; + wire n4108_o; + wire n4110_o; + wire n4113_o; + wire n4115_o; + wire n4117_o; + wire n4118_o; + wire n4121_o; + wire n4124_o; + wire n4126_o; + wire n4128_o; + wire n4130_o; + wire n4132_o; + wire n4135_o; + wire n4138_o; + wire n4140_o; + wire n4141_o; + wire n4142_o; + wire n4144_o; + wire n4151_o; + wire n4154_o; + wire [1:0] n4157_o; + wire n4159_o; + wire n4160_o; + wire n4163_o; + wire n4165_o; + wire n4166_o; + wire [3:0] n4169_o; + wire n4171_o; + wire [2:0] n4172_o; + reg n4175_o; + reg n4178_o; + reg n4181_o; + reg n4182_o; + reg n4185_o; + reg [3:0] n4187_o; + reg n4189_o; + reg [1:0] n4191_o; + reg n4194_o; + wire n4196_o; + wire n4197_o; + wire n4198_o; + wire n4200_o; + wire n4207_o; + wire n4210_o; + wire [1:0] n4213_o; + wire n4215_o; + wire n4220_o; + wire n4225_o; + wire [2:0] n4226_o; + reg n4229_o; + reg n4232_o; + reg n4235_o; + reg n4236_o; + reg n4239_o; + reg [3:0] n4242_o; + reg [1:0] n4244_o; + wire n4246_o; + wire n4248_o; + wire n4253_o; + wire [1:0] n4254_o; + reg n4257_o; + reg n4260_o; + reg n4263_o; + reg [3:0] n4266_o; + wire n4268_o; + wire n4270_o; + wire n4272_o; + wire [3:0] n4274_o; + wire n4276_o; + wire [62:0] n4277_o; + reg n4279_o; + reg n4282_o; + reg n4285_o; + reg n4288_o; + reg n4291_o; + reg n4294_o; + reg n4297_o; + reg n4300_o; + reg n4303_o; + reg n4305_o; + reg n4307_o; + reg n4310_o; + reg n4313_o; + reg n4316_o; + reg n4319_o; + reg n4322_o; + reg n4325_o; + reg n4328_o; + reg n4331_o; + reg n4334_o; + reg n4337_o; + reg n4340_o; + reg n4343_o; + reg n4346_o; + reg n4349_o; + reg [3:0] n4353_o; + reg n4356_o; + reg n4359_o; + reg n4362_o; + reg n4365_o; + reg n4368_o; + reg n4372_o; + reg n4377_o; + reg n4381_o; + reg n4384_o; + reg n4387_o; + reg [3:0] n4397_o; + wire n4399_o; + reg n4400_o; + wire [1:0] n4401_o; + reg [1:0] n4403_o; + reg n4406_o; + reg n4409_o; + reg [1:0] n4412_o; + reg n4415_o; + reg n4418_o; + reg n4421_o; + reg n4424_o; + reg n4427_o; + reg n4430_o; + reg n4433_o; + reg n4436_o; + reg n4439_o; + reg n4442_o; + reg n4445_o; + reg n4448_o; + reg n4473_o; + reg n4476_o; + reg n4479_o; + reg n4482_o; + reg n4485_o; + reg n4488_o; + reg n4491_o; + reg n4494_o; + reg n4497_o; + reg [7:0] n4499_o; + reg n4500_o; + reg n4502_o; + reg n4505_o; + reg n4508_o; + reg n4511_o; + reg n4514_o; + reg n4517_o; + reg n4520_o; + reg n4523_o; + reg n4526_o; + reg n4529_o; + reg n4532_o; + wire n4536_o; + wire n4539_o; + wire n4541_o; + wire n4543_o; + wire n4545_o; + wire n4547_o; + wire n4548_o; + wire n4549_o; + wire n4551_o; + wire n4553_o; + wire n4555_o; + wire n4559_o; + wire n4561_o; + wire [7:0] n4575_o; + wire n4577_o; + wire n4578_o; + wire n4579_o; + wire n4580_o; + wire [7:0] n4581_o; + reg [7:0] n4582_q; + wire n4583_o; + reg n4584_q; + reg n4585_q; + wire n4586_o; + reg n4587_q; + wire n4588_o; + reg n4589_q; + wire [5:0] n4590_o; + reg [5:0] n4591_q; + wire [2:0] n4592_o; + assign t0_dir_o = t0_dir_q; + assign data_o = n4575_o; + assign alu_write_accu_o = n4279_o; + assign alu_write_shadow_o = n4282_o; + assign alu_write_temp_reg_o = n4285_o; + assign alu_read_alu_o = n4288_o; + assign bus_write_bus_o = n4291_o; + assign bus_read_bus_o = n4580_o; + assign bus_ibf_int_o = n4294_o; + assign bus_en_dma_o = n4297_o; + assign bus_en_flags_o = n4300_o; + assign bus_write_sts_o = n4303_o; + assign dm_write_dmem_addr_o = n4305_o; + assign dm_write_dmem_o = n4577_o; + assign dm_read_dmem_o = n4307_o; + assign p1_write_p1_o = n4310_o; + assign p1_read_p1_o = n4313_o; + assign p2_write_p2_o = n4316_o; + assign p2_write_exp_o = n4319_o; + assign p2_read_p2_o = n4322_o; + assign p2_read_exp_o = n4325_o; + assign pm_write_pcl_o = n4328_o; + assign pm_read_pcl_o = n4331_o; + assign pm_write_pch_o = n4334_o; + assign pm_read_pch_o = n4337_o; + assign pm_read_pmem_o = n2110_o; + assign psw_read_psw_o = n4340_o; + assign psw_read_sp_o = n4343_o; + assign psw_write_psw_o = n4346_o; + assign psw_write_sp_o = n4349_o; + assign alu_op_o = n4353_o; + assign alu_use_carry_o = n4356_o; + assign alu_da_high_o = n4359_o; + assign alu_accu_low_o = n4362_o; + assign alu_p06_temp_reg_o = n4365_o; + assign alu_p60_temp_reg_o = n4368_o; + assign bus_output_pcl_o = n2113_o; + assign bus_bidir_bus_o = n4372_o; + assign clk_multi_cycle_o = opc_multi_cycle_s; + assign clk_assert_psen_o = n2116_o; + assign clk_assert_prog_o = n4377_o; + assign clk_assert_rd_o = n4381_o; + assign clk_assert_wr_o = n4384_o; + assign cnd_compute_take_o = n4387_o; + assign cnd_branch_cond_o = n4397_o; + assign cnd_comp_value_o = n4592_o; + assign cnd_f1_o = f1_q; + assign cnd_tf_o = tf_s; + assign dm_addr_type_o = n4403_o; + assign p1_read_reg_o = n4406_o; + assign p2_read_reg_o = n4409_o; + assign p2_output_pch_o = n2119_o; + assign pm_inc_pc_o = n4578_o; + assign pm_write_pmem_addr_o = n4579_o; + assign pm_addr_type_o = n4412_o; + assign psw_special_data_o = n4415_o; + assign psw_inc_stackp_o = n4418_o; + assign psw_dec_stackp_o = n4421_o; + assign psw_write_carry_o = n4424_o; + assign psw_write_aux_carry_o = n4427_o; + assign psw_write_f0_o = n4430_o; + assign psw_write_bs_o = n4433_o; + assign tim_read_timer_o = n4436_o; + assign tim_write_timer_o = n4439_o; + assign tim_start_t_o = n4442_o; + assign tim_start_cnt_o = n4445_o; + assign tim_stop_tcnt_o = n4448_o; + /* decoder.vhd:187:10 */ + assign opc_multi_cycle_s = n2006_o; // (signal) + /* decoder.vhd:188:10 */ + assign opc_read_bus_s = n2122_o; // (signal) + /* decoder.vhd:189:10 */ + assign opc_inj_int_s = n2125_o; // (signal) + /* decoder.vhd:190:10 */ + assign opc_opcode_q = n4582_q; // (signal) + /* decoder.vhd:191:10 */ + assign opc_mnemonic_s = n2008_o; // (signal) + /* decoder.vhd:192:10 */ + assign last_cycle_s = n2026_o; // (signal) + /* decoder.vhd:195:10 */ + assign assert_psen_s = n4473_o; // (signal) + /* decoder.vhd:198:10 */ + assign branch_taken_s = n4476_o; // (signal) + /* decoder.vhd:199:10 */ + assign branch_taken_q = n4584_q; // (signal) + /* decoder.vhd:200:10 */ + assign pm_inc_pc_s = n2128_o; // (signal) + /* decoder.vhd:201:10 */ + assign pm_write_pmem_addr_s = n2131_o; // (signal) + /* decoder.vhd:203:10 */ + assign add_inc_pc_s = n4479_o; // (signal) + /* decoder.vhd:205:10 */ + assign add_write_pmem_addr_s = n4482_o; // (signal) + /* decoder.vhd:208:10 */ + assign clear_f1_s = n4485_o; // (signal) + /* decoder.vhd:209:10 */ + assign cpl_f1_s = n4488_o; // (signal) + /* decoder.vhd:210:10 */ + assign f1_q = n4585_q; // (signal) + /* decoder.vhd:212:10 */ + assign clear_mb_s = n4491_o; // (signal) + /* decoder.vhd:213:10 */ + assign set_mb_s = n4494_o; // (signal) + /* decoder.vhd:214:10 */ + assign mb_q = n4587_q; // (signal) + /* decoder.vhd:217:10 */ + assign ent0_clk_s = n4497_o; // (signal) + /* decoder.vhd:218:10 */ + assign t0_dir_q = n4589_q; // (signal) + /* decoder.vhd:220:10 */ + assign data_s = n4499_o; // (signal) + /* decoder.vhd:221:10 */ + assign read_dec_s = n4500_o; // (signal) + /* decoder.vhd:223:10 */ + assign tf_s = int_b_n2010; // (signal) + /* decoder.vhd:225:10 */ + assign bus_read_bus_s = n2134_o; // (signal) + /* decoder.vhd:226:10 */ + assign add_read_bus_s = n4502_o; // (signal) + /* decoder.vhd:228:10 */ + assign dm_write_dmem_s = n4505_o; // (signal) + /* decoder.vhd:230:10 */ + assign p2_output_exp_s = n4508_o; // (signal) + /* decoder.vhd:232:10 */ + assign movx_first_cycle_s = n4511_o; // (signal) + /* decoder.vhd:235:10 */ + assign jtf_executed_s = n4514_o; // (signal) + /* decoder.vhd:236:10 */ + assign en_tcnti_s = n4517_o; // (signal) + /* decoder.vhd:237:10 */ + assign dis_tcnti_s = n4520_o; // (signal) + /* decoder.vhd:238:10 */ + assign en_i_s = n4523_o; // (signal) + /* decoder.vhd:239:10 */ + assign dis_i_s = n4526_o; // (signal) + /* decoder.vhd:240:10 */ + assign tim_int_s = int_b_n2012; // (signal) + /* decoder.vhd:241:10 */ + assign retr_executed_s = n4529_o; // (signal) + /* decoder.vhd:242:10 */ + assign int_executed_s = n4532_o; // (signal) + /* decoder.vhd:243:10 */ + assign int_pending_s = int_b_n2013; // (signal) + /* decoder.vhd:244:10 */ + assign int_in_progress_s = int_b_n2014; // (signal) + /* decoder.vhd:247:10 */ + assign mnemonic_rec_s = n1986_o; // (signal) + /* decoder.vhd:248:10 */ + assign mnemonic_q = n4591_q; // (signal) + /* decoder_pack-p.vhd:553:7 */ + assign n1240_o = opc_opcode_q == 8'b11100101; + /* decoder_pack-p.vhd:553:23 */ + assign n1242_o = opc_opcode_q == 8'b11110101; + /* decoder_pack-p.vhd:553:23 */ + assign n1243_o = n1240_o | n1242_o; + /* decoder_pack-p.vhd:558:7 */ + assign n1245_o = opc_opcode_q == 8'b10010000; + assign n1246_o = {n1245_o, n1243_o}; + /* decoder_pack-p.vhd:551:5 */ + always @* + case (n1246_o) + 2'b10: n1250_o = 6'b111111; + 2'b01: n1250_o = 6'b111110; + default: n1250_o = 6'b000000; + endcase + /* decoder_pack-p.vhd:566:19 */ + assign n1253_o = n1250_o == 6'b000000; + /* decoder_pack-p.vhd:491:7 */ + assign n1263_o = opc_opcode_q == 8'b10011001; + /* decoder_pack-p.vhd:491:23 */ + assign n1265_o = opc_opcode_q == 8'b10011010; + /* decoder_pack-p.vhd:491:23 */ + assign n1266_o = n1263_o | n1265_o; + /* decoder_pack-p.vhd:496:7 */ + assign n1268_o = opc_opcode_q == 8'b00100010; + /* decoder_pack-p.vhd:500:7 */ + assign n1270_o = opc_opcode_q == 8'b11010110; + /* decoder_pack-p.vhd:505:7 */ + assign n1272_o = opc_opcode_q == 8'b10000110; + /* decoder_pack-p.vhd:510:7 */ + assign n1274_o = opc_opcode_q == 8'b10001001; + /* decoder_pack-p.vhd:510:23 */ + assign n1276_o = opc_opcode_q == 8'b10001010; + /* decoder_pack-p.vhd:510:23 */ + assign n1277_o = n1274_o | n1276_o; + /* decoder_pack-p.vhd:515:7 */ + assign n1279_o = opc_opcode_q == 8'b00000010; + /* decoder_pack-p.vhd:519:7 */ + assign n1281_o = opc_opcode_q == 8'b00111001; + /* decoder_pack-p.vhd:519:23 */ + assign n1283_o = opc_opcode_q == 8'b00111010; + /* decoder_pack-p.vhd:519:23 */ + assign n1284_o = n1281_o | n1283_o; + assign n1285_o = {n1284_o, n1279_o, n1277_o, n1272_o, n1270_o, n1268_o, n1266_o}; + /* decoder_pack-p.vhd:489:5 */ + always @* + case (n1285_o) + 7'b1000000: n1294_o = 6'b101110; + 7'b0100000: n1294_o = 6'b111011; + 7'b0010000: n1294_o = 6'b101100; + 7'b0001000: n1294_o = 6'b111101; + 7'b0000100: n1294_o = 6'b111100; + 7'b0000010: n1294_o = 6'b111010; + 7'b0000001: n1294_o = 6'b000101; + default: n1294_o = 6'b000000; + endcase + /* decoder_pack-p.vhd:489:5 */ + always @* + case (n1285_o) + 7'b1000000: n1302_o = 1'b1; + 7'b0100000: n1302_o = 1'b0; + 7'b0010000: n1302_o = 1'b1; + 7'b0001000: n1302_o = 1'b1; + 7'b0000100: n1302_o = 1'b1; + 7'b0000010: n1302_o = 1'b0; + 7'b0000001: n1302_o = 1'b1; + default: n1302_o = 1'b0; + endcase + /* decoder_pack-p.vhd:528:19 */ + assign n1305_o = n1294_o == 6'b000000; + /* decoder_pack-p.vhd:123:7 */ + assign n1315_o = opc_opcode_q == 8'b01101000; + /* decoder_pack-p.vhd:123:23 */ + assign n1317_o = opc_opcode_q == 8'b01101001; + /* decoder_pack-p.vhd:123:23 */ + assign n1318_o = n1315_o | n1317_o; + /* decoder_pack-p.vhd:123:36 */ + assign n1320_o = opc_opcode_q == 8'b01101010; + /* decoder_pack-p.vhd:123:36 */ + assign n1321_o = n1318_o | n1320_o; + /* decoder_pack-p.vhd:123:49 */ + assign n1323_o = opc_opcode_q == 8'b01101011; + /* decoder_pack-p.vhd:123:49 */ + assign n1324_o = n1321_o | n1323_o; + /* decoder_pack-p.vhd:123:62 */ + assign n1326_o = opc_opcode_q == 8'b01101100; + /* decoder_pack-p.vhd:123:62 */ + assign n1327_o = n1324_o | n1326_o; + /* decoder_pack-p.vhd:124:23 */ + assign n1329_o = opc_opcode_q == 8'b01101101; + /* decoder_pack-p.vhd:124:23 */ + assign n1330_o = n1327_o | n1329_o; + /* decoder_pack-p.vhd:124:36 */ + assign n1332_o = opc_opcode_q == 8'b01101110; + /* decoder_pack-p.vhd:124:36 */ + assign n1333_o = n1330_o | n1332_o; + /* decoder_pack-p.vhd:124:49 */ + assign n1335_o = opc_opcode_q == 8'b01101111; + /* decoder_pack-p.vhd:124:49 */ + assign n1336_o = n1333_o | n1335_o; + /* decoder_pack-p.vhd:124:62 */ + assign n1338_o = opc_opcode_q == 8'b01100000; + /* decoder_pack-p.vhd:124:62 */ + assign n1339_o = n1336_o | n1338_o; + /* decoder_pack-p.vhd:125:23 */ + assign n1341_o = opc_opcode_q == 8'b01100001; + /* decoder_pack-p.vhd:125:23 */ + assign n1342_o = n1339_o | n1341_o; + /* decoder_pack-p.vhd:125:36 */ + assign n1344_o = opc_opcode_q == 8'b01111000; + /* decoder_pack-p.vhd:125:36 */ + assign n1345_o = n1342_o | n1344_o; + /* decoder_pack-p.vhd:126:23 */ + assign n1347_o = opc_opcode_q == 8'b01111001; + /* decoder_pack-p.vhd:126:23 */ + assign n1348_o = n1345_o | n1347_o; + /* decoder_pack-p.vhd:126:36 */ + assign n1350_o = opc_opcode_q == 8'b01111010; + /* decoder_pack-p.vhd:126:36 */ + assign n1351_o = n1348_o | n1350_o; + /* decoder_pack-p.vhd:126:49 */ + assign n1353_o = opc_opcode_q == 8'b01111011; + /* decoder_pack-p.vhd:126:49 */ + assign n1354_o = n1351_o | n1353_o; + /* decoder_pack-p.vhd:126:62 */ + assign n1356_o = opc_opcode_q == 8'b01111100; + /* decoder_pack-p.vhd:126:62 */ + assign n1357_o = n1354_o | n1356_o; + /* decoder_pack-p.vhd:127:23 */ + assign n1359_o = opc_opcode_q == 8'b01111101; + /* decoder_pack-p.vhd:127:23 */ + assign n1360_o = n1357_o | n1359_o; + /* decoder_pack-p.vhd:127:36 */ + assign n1362_o = opc_opcode_q == 8'b01111110; + /* decoder_pack-p.vhd:127:36 */ + assign n1363_o = n1360_o | n1362_o; + /* decoder_pack-p.vhd:127:49 */ + assign n1365_o = opc_opcode_q == 8'b01111111; + /* decoder_pack-p.vhd:127:49 */ + assign n1366_o = n1363_o | n1365_o; + /* decoder_pack-p.vhd:127:62 */ + assign n1368_o = opc_opcode_q == 8'b01110000; + /* decoder_pack-p.vhd:127:62 */ + assign n1369_o = n1366_o | n1368_o; + /* decoder_pack-p.vhd:128:23 */ + assign n1371_o = opc_opcode_q == 8'b01110001; + /* decoder_pack-p.vhd:128:23 */ + assign n1372_o = n1369_o | n1371_o; + /* decoder_pack-p.vhd:132:7 */ + assign n1374_o = opc_opcode_q == 8'b00000011; + /* decoder_pack-p.vhd:132:23 */ + assign n1376_o = opc_opcode_q == 8'b00010011; + /* decoder_pack-p.vhd:132:23 */ + assign n1377_o = n1374_o | n1376_o; + /* decoder_pack-p.vhd:138:7 */ + assign n1379_o = opc_opcode_q == 8'b01011000; + /* decoder_pack-p.vhd:138:23 */ + assign n1381_o = opc_opcode_q == 8'b01011001; + /* decoder_pack-p.vhd:138:23 */ + assign n1382_o = n1379_o | n1381_o; + /* decoder_pack-p.vhd:138:36 */ + assign n1384_o = opc_opcode_q == 8'b01011010; + /* decoder_pack-p.vhd:138:36 */ + assign n1385_o = n1382_o | n1384_o; + /* decoder_pack-p.vhd:138:49 */ + assign n1387_o = opc_opcode_q == 8'b01011011; + /* decoder_pack-p.vhd:138:49 */ + assign n1388_o = n1385_o | n1387_o; + /* decoder_pack-p.vhd:138:62 */ + assign n1390_o = opc_opcode_q == 8'b01011100; + /* decoder_pack-p.vhd:138:62 */ + assign n1391_o = n1388_o | n1390_o; + /* decoder_pack-p.vhd:139:23 */ + assign n1393_o = opc_opcode_q == 8'b01011101; + /* decoder_pack-p.vhd:139:23 */ + assign n1394_o = n1391_o | n1393_o; + /* decoder_pack-p.vhd:139:36 */ + assign n1396_o = opc_opcode_q == 8'b01011110; + /* decoder_pack-p.vhd:139:36 */ + assign n1397_o = n1394_o | n1396_o; + /* decoder_pack-p.vhd:139:49 */ + assign n1399_o = opc_opcode_q == 8'b01011111; + /* decoder_pack-p.vhd:139:49 */ + assign n1400_o = n1397_o | n1399_o; + /* decoder_pack-p.vhd:139:62 */ + assign n1402_o = opc_opcode_q == 8'b01010000; + /* decoder_pack-p.vhd:139:62 */ + assign n1403_o = n1400_o | n1402_o; + /* decoder_pack-p.vhd:140:23 */ + assign n1405_o = opc_opcode_q == 8'b01010001; + /* decoder_pack-p.vhd:140:23 */ + assign n1406_o = n1403_o | n1405_o; + /* decoder_pack-p.vhd:144:7 */ + assign n1408_o = opc_opcode_q == 8'b01010011; + /* decoder_pack-p.vhd:149:7 */ + assign n1410_o = opc_opcode_q == 8'b00010100; + /* decoder_pack-p.vhd:149:23 */ + assign n1412_o = opc_opcode_q == 8'b00110100; + /* decoder_pack-p.vhd:149:23 */ + assign n1413_o = n1410_o | n1412_o; + /* decoder_pack-p.vhd:149:36 */ + assign n1415_o = opc_opcode_q == 8'b01010100; + /* decoder_pack-p.vhd:149:36 */ + assign n1416_o = n1413_o | n1415_o; + /* decoder_pack-p.vhd:149:49 */ + assign n1418_o = opc_opcode_q == 8'b01110100; + /* decoder_pack-p.vhd:149:49 */ + assign n1419_o = n1416_o | n1418_o; + /* decoder_pack-p.vhd:149:62 */ + assign n1421_o = opc_opcode_q == 8'b10010100; + /* decoder_pack-p.vhd:149:62 */ + assign n1422_o = n1419_o | n1421_o; + /* decoder_pack-p.vhd:150:23 */ + assign n1424_o = opc_opcode_q == 8'b10110100; + /* decoder_pack-p.vhd:150:23 */ + assign n1425_o = n1422_o | n1424_o; + /* decoder_pack-p.vhd:150:36 */ + assign n1427_o = opc_opcode_q == 8'b11010100; + /* decoder_pack-p.vhd:150:36 */ + assign n1428_o = n1425_o | n1427_o; + /* decoder_pack-p.vhd:150:49 */ + assign n1430_o = opc_opcode_q == 8'b11110100; + /* decoder_pack-p.vhd:150:49 */ + assign n1431_o = n1428_o | n1430_o; + /* decoder_pack-p.vhd:155:7 */ + assign n1433_o = opc_opcode_q == 8'b00100111; + /* decoder_pack-p.vhd:159:7 */ + assign n1435_o = opc_opcode_q == 8'b10010111; + /* decoder_pack-p.vhd:163:7 */ + assign n1437_o = opc_opcode_q == 8'b10000101; + /* decoder_pack-p.vhd:163:23 */ + assign n1439_o = opc_opcode_q == 8'b10100101; + /* decoder_pack-p.vhd:163:23 */ + assign n1440_o = n1437_o | n1439_o; + /* decoder_pack-p.vhd:168:7 */ + assign n1442_o = opc_opcode_q == 8'b00110111; + /* decoder_pack-p.vhd:172:7 */ + assign n1444_o = opc_opcode_q == 8'b10100111; + /* decoder_pack-p.vhd:176:7 */ + assign n1446_o = opc_opcode_q == 8'b10010101; + /* decoder_pack-p.vhd:176:23 */ + assign n1448_o = opc_opcode_q == 8'b10110101; + /* decoder_pack-p.vhd:176:23 */ + assign n1449_o = n1446_o | n1448_o; + /* decoder_pack-p.vhd:181:7 */ + assign n1451_o = opc_opcode_q == 8'b01010111; + /* decoder_pack-p.vhd:185:7 */ + assign n1453_o = opc_opcode_q == 8'b11001000; + /* decoder_pack-p.vhd:185:23 */ + assign n1455_o = opc_opcode_q == 8'b11001001; + /* decoder_pack-p.vhd:185:23 */ + assign n1456_o = n1453_o | n1455_o; + /* decoder_pack-p.vhd:185:36 */ + assign n1458_o = opc_opcode_q == 8'b11001010; + /* decoder_pack-p.vhd:185:36 */ + assign n1459_o = n1456_o | n1458_o; + /* decoder_pack-p.vhd:185:49 */ + assign n1461_o = opc_opcode_q == 8'b11001011; + /* decoder_pack-p.vhd:185:49 */ + assign n1462_o = n1459_o | n1461_o; + /* decoder_pack-p.vhd:185:62 */ + assign n1464_o = opc_opcode_q == 8'b11001100; + /* decoder_pack-p.vhd:185:62 */ + assign n1465_o = n1462_o | n1464_o; + /* decoder_pack-p.vhd:186:23 */ + assign n1467_o = opc_opcode_q == 8'b11001101; + /* decoder_pack-p.vhd:186:23 */ + assign n1468_o = n1465_o | n1467_o; + /* decoder_pack-p.vhd:186:36 */ + assign n1470_o = opc_opcode_q == 8'b11001110; + /* decoder_pack-p.vhd:186:36 */ + assign n1471_o = n1468_o | n1470_o; + /* decoder_pack-p.vhd:186:49 */ + assign n1473_o = opc_opcode_q == 8'b11001111; + /* decoder_pack-p.vhd:186:49 */ + assign n1474_o = n1471_o | n1473_o; + /* decoder_pack-p.vhd:186:62 */ + assign n1476_o = opc_opcode_q == 8'b00000111; + /* decoder_pack-p.vhd:186:62 */ + assign n1477_o = n1474_o | n1476_o; + /* decoder_pack-p.vhd:191:7 */ + assign n1479_o = opc_opcode_q == 8'b00010101; + /* decoder_pack-p.vhd:191:23 */ + assign n1481_o = opc_opcode_q == 8'b00000101; + /* decoder_pack-p.vhd:191:23 */ + assign n1482_o = n1479_o | n1481_o; + /* decoder_pack-p.vhd:196:7 */ + assign n1484_o = opc_opcode_q == 8'b00110101; + /* decoder_pack-p.vhd:196:23 */ + assign n1486_o = opc_opcode_q == 8'b00100101; + /* decoder_pack-p.vhd:196:23 */ + assign n1487_o = n1484_o | n1486_o; + /* decoder_pack-p.vhd:201:7 */ + assign n1489_o = opc_opcode_q == 8'b11101000; + /* decoder_pack-p.vhd:201:23 */ + assign n1491_o = opc_opcode_q == 8'b11101001; + /* decoder_pack-p.vhd:201:23 */ + assign n1492_o = n1489_o | n1491_o; + /* decoder_pack-p.vhd:201:36 */ + assign n1494_o = opc_opcode_q == 8'b11101010; + /* decoder_pack-p.vhd:201:36 */ + assign n1495_o = n1492_o | n1494_o; + /* decoder_pack-p.vhd:201:49 */ + assign n1497_o = opc_opcode_q == 8'b11101011; + /* decoder_pack-p.vhd:201:49 */ + assign n1498_o = n1495_o | n1497_o; + /* decoder_pack-p.vhd:201:62 */ + assign n1500_o = opc_opcode_q == 8'b11101100; + /* decoder_pack-p.vhd:201:62 */ + assign n1501_o = n1498_o | n1500_o; + /* decoder_pack-p.vhd:202:23 */ + assign n1503_o = opc_opcode_q == 8'b11101101; + /* decoder_pack-p.vhd:202:23 */ + assign n1504_o = n1501_o | n1503_o; + /* decoder_pack-p.vhd:202:36 */ + assign n1506_o = opc_opcode_q == 8'b11101110; + /* decoder_pack-p.vhd:202:36 */ + assign n1507_o = n1504_o | n1506_o; + /* decoder_pack-p.vhd:202:49 */ + assign n1509_o = opc_opcode_q == 8'b11101111; + /* decoder_pack-p.vhd:202:49 */ + assign n1510_o = n1507_o | n1509_o; + /* decoder_pack-p.vhd:207:7 */ + assign n1512_o = opc_opcode_q == 8'b00001001; + /* decoder_pack-p.vhd:207:23 */ + assign n1514_o = opc_opcode_q == 8'b00001010; + /* decoder_pack-p.vhd:207:23 */ + assign n1515_o = n1512_o | n1514_o; + /* decoder_pack-p.vhd:212:7 */ + assign n1517_o = opc_opcode_q == 8'b00010111; + /* decoder_pack-p.vhd:212:23 */ + assign n1519_o = opc_opcode_q == 8'b00011000; + /* decoder_pack-p.vhd:212:23 */ + assign n1520_o = n1517_o | n1519_o; + /* decoder_pack-p.vhd:213:23 */ + assign n1522_o = opc_opcode_q == 8'b00011001; + /* decoder_pack-p.vhd:213:23 */ + assign n1523_o = n1520_o | n1522_o; + /* decoder_pack-p.vhd:213:36 */ + assign n1525_o = opc_opcode_q == 8'b00011010; + /* decoder_pack-p.vhd:213:36 */ + assign n1526_o = n1523_o | n1525_o; + /* decoder_pack-p.vhd:213:49 */ + assign n1528_o = opc_opcode_q == 8'b00011011; + /* decoder_pack-p.vhd:213:49 */ + assign n1529_o = n1526_o | n1528_o; + /* decoder_pack-p.vhd:213:62 */ + assign n1531_o = opc_opcode_q == 8'b00011100; + /* decoder_pack-p.vhd:213:62 */ + assign n1532_o = n1529_o | n1531_o; + /* decoder_pack-p.vhd:214:23 */ + assign n1534_o = opc_opcode_q == 8'b00011101; + /* decoder_pack-p.vhd:214:23 */ + assign n1535_o = n1532_o | n1534_o; + /* decoder_pack-p.vhd:214:36 */ + assign n1537_o = opc_opcode_q == 8'b00011110; + /* decoder_pack-p.vhd:214:36 */ + assign n1538_o = n1535_o | n1537_o; + /* decoder_pack-p.vhd:214:49 */ + assign n1540_o = opc_opcode_q == 8'b00011111; + /* decoder_pack-p.vhd:214:49 */ + assign n1541_o = n1538_o | n1540_o; + /* decoder_pack-p.vhd:214:62 */ + assign n1543_o = opc_opcode_q == 8'b00010000; + /* decoder_pack-p.vhd:214:62 */ + assign n1544_o = n1541_o | n1543_o; + /* decoder_pack-p.vhd:215:23 */ + assign n1546_o = opc_opcode_q == 8'b00010001; + /* decoder_pack-p.vhd:215:23 */ + assign n1547_o = n1544_o | n1546_o; + /* decoder_pack-p.vhd:219:7 */ + assign n1549_o = opc_opcode_q == 8'b00010010; + /* decoder_pack-p.vhd:219:23 */ + assign n1551_o = opc_opcode_q == 8'b00110010; + /* decoder_pack-p.vhd:219:23 */ + assign n1552_o = n1549_o | n1551_o; + /* decoder_pack-p.vhd:219:36 */ + assign n1554_o = opc_opcode_q == 8'b01010010; + /* decoder_pack-p.vhd:219:36 */ + assign n1555_o = n1552_o | n1554_o; + /* decoder_pack-p.vhd:219:49 */ + assign n1557_o = opc_opcode_q == 8'b01110010; + /* decoder_pack-p.vhd:219:49 */ + assign n1558_o = n1555_o | n1557_o; + /* decoder_pack-p.vhd:219:62 */ + assign n1560_o = opc_opcode_q == 8'b10010010; + /* decoder_pack-p.vhd:219:62 */ + assign n1561_o = n1558_o | n1560_o; + /* decoder_pack-p.vhd:220:23 */ + assign n1563_o = opc_opcode_q == 8'b10110010; + /* decoder_pack-p.vhd:220:23 */ + assign n1564_o = n1561_o | n1563_o; + /* decoder_pack-p.vhd:220:36 */ + assign n1566_o = opc_opcode_q == 8'b11010010; + /* decoder_pack-p.vhd:220:36 */ + assign n1567_o = n1564_o | n1566_o; + /* decoder_pack-p.vhd:220:49 */ + assign n1569_o = opc_opcode_q == 8'b11110010; + /* decoder_pack-p.vhd:220:49 */ + assign n1570_o = n1567_o | n1569_o; + /* decoder_pack-p.vhd:225:7 */ + assign n1572_o = opc_opcode_q == 8'b11110110; + /* decoder_pack-p.vhd:225:23 */ + assign n1574_o = opc_opcode_q == 8'b11100110; + /* decoder_pack-p.vhd:225:23 */ + assign n1575_o = n1572_o | n1574_o; + /* decoder_pack-p.vhd:231:7 */ + assign n1577_o = opc_opcode_q == 8'b10110110; + /* decoder_pack-p.vhd:231:23 */ + assign n1579_o = opc_opcode_q == 8'b01110110; + /* decoder_pack-p.vhd:231:23 */ + assign n1580_o = n1577_o | n1579_o; + /* decoder_pack-p.vhd:237:7 */ + assign n1582_o = opc_opcode_q == 8'b00000100; + /* decoder_pack-p.vhd:237:23 */ + assign n1584_o = opc_opcode_q == 8'b00100100; + /* decoder_pack-p.vhd:237:23 */ + assign n1585_o = n1582_o | n1584_o; + /* decoder_pack-p.vhd:237:36 */ + assign n1587_o = opc_opcode_q == 8'b01000100; + /* decoder_pack-p.vhd:237:36 */ + assign n1588_o = n1585_o | n1587_o; + /* decoder_pack-p.vhd:237:49 */ + assign n1590_o = opc_opcode_q == 8'b01100100; + /* decoder_pack-p.vhd:237:49 */ + assign n1591_o = n1588_o | n1590_o; + /* decoder_pack-p.vhd:237:62 */ + assign n1593_o = opc_opcode_q == 8'b10000100; + /* decoder_pack-p.vhd:237:62 */ + assign n1594_o = n1591_o | n1593_o; + /* decoder_pack-p.vhd:238:23 */ + assign n1596_o = opc_opcode_q == 8'b10100100; + /* decoder_pack-p.vhd:238:23 */ + assign n1597_o = n1594_o | n1596_o; + /* decoder_pack-p.vhd:238:36 */ + assign n1599_o = opc_opcode_q == 8'b11000100; + /* decoder_pack-p.vhd:238:36 */ + assign n1600_o = n1597_o | n1599_o; + /* decoder_pack-p.vhd:238:49 */ + assign n1602_o = opc_opcode_q == 8'b11100100; + /* decoder_pack-p.vhd:238:49 */ + assign n1603_o = n1600_o | n1602_o; + /* decoder_pack-p.vhd:243:7 */ + assign n1605_o = opc_opcode_q == 8'b10110011; + /* decoder_pack-p.vhd:248:7 */ + assign n1607_o = opc_opcode_q == 8'b00100110; + /* decoder_pack-p.vhd:248:23 */ + assign n1609_o = opc_opcode_q == 8'b01000110; + /* decoder_pack-p.vhd:248:23 */ + assign n1610_o = n1607_o | n1609_o; + /* decoder_pack-p.vhd:249:23 */ + assign n1612_o = opc_opcode_q == 8'b00110110; + /* decoder_pack-p.vhd:249:23 */ + assign n1613_o = n1610_o | n1612_o; + /* decoder_pack-p.vhd:250:23 */ + assign n1615_o = opc_opcode_q == 8'b01010110; + /* decoder_pack-p.vhd:250:23 */ + assign n1616_o = n1613_o | n1615_o; + /* decoder_pack-p.vhd:256:7 */ + assign n1618_o = opc_opcode_q == 8'b00010110; + /* decoder_pack-p.vhd:261:7 */ + assign n1620_o = opc_opcode_q == 8'b10010110; + /* decoder_pack-p.vhd:261:23 */ + assign n1622_o = opc_opcode_q == 8'b11000110; + /* decoder_pack-p.vhd:261:23 */ + assign n1623_o = n1620_o | n1622_o; + /* decoder_pack-p.vhd:267:7 */ + assign n1625_o = opc_opcode_q == 8'b00100011; + /* decoder_pack-p.vhd:272:7 */ + assign n1627_o = opc_opcode_q == 8'b11000111; + /* decoder_pack-p.vhd:276:7 */ + assign n1629_o = opc_opcode_q == 8'b11111000; + /* decoder_pack-p.vhd:276:23 */ + assign n1631_o = opc_opcode_q == 8'b11111001; + /* decoder_pack-p.vhd:276:23 */ + assign n1632_o = n1629_o | n1631_o; + /* decoder_pack-p.vhd:276:36 */ + assign n1634_o = opc_opcode_q == 8'b11111010; + /* decoder_pack-p.vhd:276:36 */ + assign n1635_o = n1632_o | n1634_o; + /* decoder_pack-p.vhd:276:49 */ + assign n1637_o = opc_opcode_q == 8'b11111011; + /* decoder_pack-p.vhd:276:49 */ + assign n1638_o = n1635_o | n1637_o; + /* decoder_pack-p.vhd:276:62 */ + assign n1640_o = opc_opcode_q == 8'b11111100; + /* decoder_pack-p.vhd:276:62 */ + assign n1641_o = n1638_o | n1640_o; + /* decoder_pack-p.vhd:277:23 */ + assign n1643_o = opc_opcode_q == 8'b11111101; + /* decoder_pack-p.vhd:277:23 */ + assign n1644_o = n1641_o | n1643_o; + /* decoder_pack-p.vhd:277:36 */ + assign n1646_o = opc_opcode_q == 8'b11111110; + /* decoder_pack-p.vhd:277:36 */ + assign n1647_o = n1644_o | n1646_o; + /* decoder_pack-p.vhd:277:49 */ + assign n1649_o = opc_opcode_q == 8'b11111111; + /* decoder_pack-p.vhd:277:49 */ + assign n1650_o = n1647_o | n1649_o; + /* decoder_pack-p.vhd:277:62 */ + assign n1652_o = opc_opcode_q == 8'b11110000; + /* decoder_pack-p.vhd:277:62 */ + assign n1653_o = n1650_o | n1652_o; + /* decoder_pack-p.vhd:278:23 */ + assign n1655_o = opc_opcode_q == 8'b11110001; + /* decoder_pack-p.vhd:278:23 */ + assign n1656_o = n1653_o | n1655_o; + /* decoder_pack-p.vhd:282:7 */ + assign n1658_o = opc_opcode_q == 8'b11010111; + /* decoder_pack-p.vhd:286:7 */ + assign n1660_o = opc_opcode_q == 8'b10101000; + /* decoder_pack-p.vhd:286:23 */ + assign n1662_o = opc_opcode_q == 8'b10101001; + /* decoder_pack-p.vhd:286:23 */ + assign n1663_o = n1660_o | n1662_o; + /* decoder_pack-p.vhd:286:36 */ + assign n1665_o = opc_opcode_q == 8'b10101010; + /* decoder_pack-p.vhd:286:36 */ + assign n1666_o = n1663_o | n1665_o; + /* decoder_pack-p.vhd:286:49 */ + assign n1668_o = opc_opcode_q == 8'b10101011; + /* decoder_pack-p.vhd:286:49 */ + assign n1669_o = n1666_o | n1668_o; + /* decoder_pack-p.vhd:286:62 */ + assign n1671_o = opc_opcode_q == 8'b10101100; + /* decoder_pack-p.vhd:286:62 */ + assign n1672_o = n1669_o | n1671_o; + /* decoder_pack-p.vhd:287:23 */ + assign n1674_o = opc_opcode_q == 8'b10101101; + /* decoder_pack-p.vhd:287:23 */ + assign n1675_o = n1672_o | n1674_o; + /* decoder_pack-p.vhd:287:36 */ + assign n1677_o = opc_opcode_q == 8'b10101110; + /* decoder_pack-p.vhd:287:36 */ + assign n1678_o = n1675_o | n1677_o; + /* decoder_pack-p.vhd:287:49 */ + assign n1680_o = opc_opcode_q == 8'b10101111; + /* decoder_pack-p.vhd:287:49 */ + assign n1681_o = n1678_o | n1680_o; + /* decoder_pack-p.vhd:287:62 */ + assign n1683_o = opc_opcode_q == 8'b10100000; + /* decoder_pack-p.vhd:287:62 */ + assign n1684_o = n1681_o | n1683_o; + /* decoder_pack-p.vhd:288:23 */ + assign n1686_o = opc_opcode_q == 8'b10100001; + /* decoder_pack-p.vhd:288:23 */ + assign n1687_o = n1684_o | n1686_o; + /* decoder_pack-p.vhd:292:7 */ + assign n1689_o = opc_opcode_q == 8'b10111000; + /* decoder_pack-p.vhd:292:23 */ + assign n1691_o = opc_opcode_q == 8'b10111001; + /* decoder_pack-p.vhd:292:23 */ + assign n1692_o = n1689_o | n1691_o; + /* decoder_pack-p.vhd:292:36 */ + assign n1694_o = opc_opcode_q == 8'b10111010; + /* decoder_pack-p.vhd:292:36 */ + assign n1695_o = n1692_o | n1694_o; + /* decoder_pack-p.vhd:292:49 */ + assign n1697_o = opc_opcode_q == 8'b10111011; + /* decoder_pack-p.vhd:292:49 */ + assign n1698_o = n1695_o | n1697_o; + /* decoder_pack-p.vhd:292:62 */ + assign n1700_o = opc_opcode_q == 8'b10111100; + /* decoder_pack-p.vhd:292:62 */ + assign n1701_o = n1698_o | n1700_o; + /* decoder_pack-p.vhd:293:23 */ + assign n1703_o = opc_opcode_q == 8'b10111101; + /* decoder_pack-p.vhd:293:23 */ + assign n1704_o = n1701_o | n1703_o; + /* decoder_pack-p.vhd:293:36 */ + assign n1706_o = opc_opcode_q == 8'b10111110; + /* decoder_pack-p.vhd:293:36 */ + assign n1707_o = n1704_o | n1706_o; + /* decoder_pack-p.vhd:293:49 */ + assign n1709_o = opc_opcode_q == 8'b10111111; + /* decoder_pack-p.vhd:293:49 */ + assign n1710_o = n1707_o | n1709_o; + /* decoder_pack-p.vhd:293:62 */ + assign n1712_o = opc_opcode_q == 8'b10110000; + /* decoder_pack-p.vhd:293:62 */ + assign n1713_o = n1710_o | n1712_o; + /* decoder_pack-p.vhd:294:23 */ + assign n1715_o = opc_opcode_q == 8'b10110001; + /* decoder_pack-p.vhd:294:23 */ + assign n1716_o = n1713_o | n1715_o; + /* decoder_pack-p.vhd:299:7 */ + assign n1718_o = opc_opcode_q == 8'b01100010; + /* decoder_pack-p.vhd:299:23 */ + assign n1720_o = opc_opcode_q == 8'b01000010; + /* decoder_pack-p.vhd:299:23 */ + assign n1721_o = n1718_o | n1720_o; + /* decoder_pack-p.vhd:304:7 */ + assign n1723_o = opc_opcode_q == 8'b00001100; + /* decoder_pack-p.vhd:304:23 */ + assign n1725_o = opc_opcode_q == 8'b00001101; + /* decoder_pack-p.vhd:304:23 */ + assign n1726_o = n1723_o | n1725_o; + /* decoder_pack-p.vhd:304:36 */ + assign n1728_o = opc_opcode_q == 8'b00001110; + /* decoder_pack-p.vhd:304:36 */ + assign n1729_o = n1726_o | n1728_o; + /* decoder_pack-p.vhd:304:49 */ + assign n1731_o = opc_opcode_q == 8'b00001111; + /* decoder_pack-p.vhd:304:49 */ + assign n1732_o = n1729_o | n1731_o; + /* decoder_pack-p.vhd:309:7 */ + assign n1734_o = opc_opcode_q == 8'b10100011; + /* decoder_pack-p.vhd:309:23 */ + assign n1736_o = opc_opcode_q == 8'b11100011; + /* decoder_pack-p.vhd:309:23 */ + assign n1737_o = n1734_o | n1736_o; + /* decoder_pack-p.vhd:315:7 */ + assign n1739_o = opc_opcode_q == 8'b00000000; + /* decoder_pack-p.vhd:319:7 */ + assign n1741_o = opc_opcode_q == 8'b01001000; + /* decoder_pack-p.vhd:319:23 */ + assign n1743_o = opc_opcode_q == 8'b01001001; + /* decoder_pack-p.vhd:319:23 */ + assign n1744_o = n1741_o | n1743_o; + /* decoder_pack-p.vhd:319:36 */ + assign n1746_o = opc_opcode_q == 8'b01001010; + /* decoder_pack-p.vhd:319:36 */ + assign n1747_o = n1744_o | n1746_o; + /* decoder_pack-p.vhd:319:49 */ + assign n1749_o = opc_opcode_q == 8'b01001011; + /* decoder_pack-p.vhd:319:49 */ + assign n1750_o = n1747_o | n1749_o; + /* decoder_pack-p.vhd:319:62 */ + assign n1752_o = opc_opcode_q == 8'b01001100; + /* decoder_pack-p.vhd:319:62 */ + assign n1753_o = n1750_o | n1752_o; + /* decoder_pack-p.vhd:320:23 */ + assign n1755_o = opc_opcode_q == 8'b01001101; + /* decoder_pack-p.vhd:320:23 */ + assign n1756_o = n1753_o | n1755_o; + /* decoder_pack-p.vhd:320:36 */ + assign n1758_o = opc_opcode_q == 8'b01001110; + /* decoder_pack-p.vhd:320:36 */ + assign n1759_o = n1756_o | n1758_o; + /* decoder_pack-p.vhd:320:49 */ + assign n1761_o = opc_opcode_q == 8'b01001111; + /* decoder_pack-p.vhd:320:49 */ + assign n1762_o = n1759_o | n1761_o; + /* decoder_pack-p.vhd:320:62 */ + assign n1764_o = opc_opcode_q == 8'b01000000; + /* decoder_pack-p.vhd:320:62 */ + assign n1765_o = n1762_o | n1764_o; + /* decoder_pack-p.vhd:321:23 */ + assign n1767_o = opc_opcode_q == 8'b01000001; + /* decoder_pack-p.vhd:321:23 */ + assign n1768_o = n1765_o | n1767_o; + /* decoder_pack-p.vhd:325:7 */ + assign n1770_o = opc_opcode_q == 8'b01000011; + /* decoder_pack-p.vhd:330:7 */ + assign n1772_o = opc_opcode_q == 8'b00111100; + /* decoder_pack-p.vhd:330:23 */ + assign n1774_o = opc_opcode_q == 8'b00111101; + /* decoder_pack-p.vhd:330:23 */ + assign n1775_o = n1772_o | n1774_o; + /* decoder_pack-p.vhd:330:36 */ + assign n1777_o = opc_opcode_q == 8'b00111110; + /* decoder_pack-p.vhd:330:36 */ + assign n1778_o = n1775_o | n1777_o; + /* decoder_pack-p.vhd:330:49 */ + assign n1780_o = opc_opcode_q == 8'b00111111; + /* decoder_pack-p.vhd:330:49 */ + assign n1781_o = n1778_o | n1780_o; + /* decoder_pack-p.vhd:330:62 */ + assign n1783_o = opc_opcode_q == 8'b10011100; + /* decoder_pack-p.vhd:330:62 */ + assign n1784_o = n1781_o | n1783_o; + /* decoder_pack-p.vhd:331:23 */ + assign n1786_o = opc_opcode_q == 8'b10011101; + /* decoder_pack-p.vhd:331:23 */ + assign n1787_o = n1784_o | n1786_o; + /* decoder_pack-p.vhd:331:36 */ + assign n1789_o = opc_opcode_q == 8'b10011110; + /* decoder_pack-p.vhd:331:36 */ + assign n1790_o = n1787_o | n1789_o; + /* decoder_pack-p.vhd:331:49 */ + assign n1792_o = opc_opcode_q == 8'b10011111; + /* decoder_pack-p.vhd:331:49 */ + assign n1793_o = n1790_o | n1792_o; + /* decoder_pack-p.vhd:331:62 */ + assign n1795_o = opc_opcode_q == 8'b10001100; + /* decoder_pack-p.vhd:331:62 */ + assign n1796_o = n1793_o | n1795_o; + /* decoder_pack-p.vhd:332:23 */ + assign n1798_o = opc_opcode_q == 8'b10001101; + /* decoder_pack-p.vhd:332:23 */ + assign n1799_o = n1796_o | n1798_o; + /* decoder_pack-p.vhd:332:36 */ + assign n1801_o = opc_opcode_q == 8'b10001110; + /* decoder_pack-p.vhd:332:36 */ + assign n1802_o = n1799_o | n1801_o; + /* decoder_pack-p.vhd:332:49 */ + assign n1804_o = opc_opcode_q == 8'b10001111; + /* decoder_pack-p.vhd:332:49 */ + assign n1805_o = n1802_o | n1804_o; + /* decoder_pack-p.vhd:337:7 */ + assign n1807_o = opc_opcode_q == 8'b10000011; + /* decoder_pack-p.vhd:337:23 */ + assign n1809_o = opc_opcode_q == 8'b10010011; + /* decoder_pack-p.vhd:337:23 */ + assign n1810_o = n1807_o | n1809_o; + /* decoder_pack-p.vhd:343:7 */ + assign n1812_o = opc_opcode_q == 8'b11100111; + /* decoder_pack-p.vhd:343:23 */ + assign n1814_o = opc_opcode_q == 8'b11110111; + /* decoder_pack-p.vhd:343:23 */ + assign n1815_o = n1812_o | n1814_o; + /* decoder_pack-p.vhd:348:7 */ + assign n1817_o = opc_opcode_q == 8'b01110111; + /* decoder_pack-p.vhd:348:23 */ + assign n1819_o = opc_opcode_q == 8'b01100111; + /* decoder_pack-p.vhd:348:23 */ + assign n1820_o = n1817_o | n1819_o; + /* decoder_pack-p.vhd:353:7 */ + assign n1822_o = opc_opcode_q == 8'b11000101; + /* decoder_pack-p.vhd:353:23 */ + assign n1824_o = opc_opcode_q == 8'b11010101; + /* decoder_pack-p.vhd:353:23 */ + assign n1825_o = n1822_o | n1824_o; + /* decoder_pack-p.vhd:358:7 */ + assign n1827_o = opc_opcode_q == 8'b01100101; + /* decoder_pack-p.vhd:362:7 */ + assign n1829_o = opc_opcode_q == 8'b01000101; + /* decoder_pack-p.vhd:362:23 */ + assign n1831_o = opc_opcode_q == 8'b01010101; + /* decoder_pack-p.vhd:362:23 */ + assign n1832_o = n1829_o | n1831_o; + /* decoder_pack-p.vhd:367:7 */ + assign n1834_o = opc_opcode_q == 8'b01000111; + /* decoder_pack-p.vhd:371:7 */ + assign n1836_o = opc_opcode_q == 8'b00101000; + /* decoder_pack-p.vhd:371:23 */ + assign n1838_o = opc_opcode_q == 8'b00101001; + /* decoder_pack-p.vhd:371:23 */ + assign n1839_o = n1836_o | n1838_o; + /* decoder_pack-p.vhd:371:36 */ + assign n1841_o = opc_opcode_q == 8'b00101010; + /* decoder_pack-p.vhd:371:36 */ + assign n1842_o = n1839_o | n1841_o; + /* decoder_pack-p.vhd:371:49 */ + assign n1844_o = opc_opcode_q == 8'b00101011; + /* decoder_pack-p.vhd:371:49 */ + assign n1845_o = n1842_o | n1844_o; + /* decoder_pack-p.vhd:371:62 */ + assign n1847_o = opc_opcode_q == 8'b00101100; + /* decoder_pack-p.vhd:371:62 */ + assign n1848_o = n1845_o | n1847_o; + /* decoder_pack-p.vhd:372:23 */ + assign n1850_o = opc_opcode_q == 8'b00101101; + /* decoder_pack-p.vhd:372:23 */ + assign n1851_o = n1848_o | n1850_o; + /* decoder_pack-p.vhd:372:36 */ + assign n1853_o = opc_opcode_q == 8'b00101110; + /* decoder_pack-p.vhd:372:36 */ + assign n1854_o = n1851_o | n1853_o; + /* decoder_pack-p.vhd:372:49 */ + assign n1856_o = opc_opcode_q == 8'b00101111; + /* decoder_pack-p.vhd:372:49 */ + assign n1857_o = n1854_o | n1856_o; + /* decoder_pack-p.vhd:372:62 */ + assign n1859_o = opc_opcode_q == 8'b00100000; + /* decoder_pack-p.vhd:372:62 */ + assign n1860_o = n1857_o | n1859_o; + /* decoder_pack-p.vhd:373:23 */ + assign n1862_o = opc_opcode_q == 8'b00100001; + /* decoder_pack-p.vhd:373:23 */ + assign n1863_o = n1860_o | n1862_o; + /* decoder_pack-p.vhd:373:36 */ + assign n1865_o = opc_opcode_q == 8'b00110000; + /* decoder_pack-p.vhd:373:36 */ + assign n1866_o = n1863_o | n1865_o; + /* decoder_pack-p.vhd:374:23 */ + assign n1868_o = opc_opcode_q == 8'b00110001; + /* decoder_pack-p.vhd:374:23 */ + assign n1869_o = n1866_o | n1868_o; + /* decoder_pack-p.vhd:378:7 */ + assign n1871_o = opc_opcode_q == 8'b11011000; + /* decoder_pack-p.vhd:378:23 */ + assign n1873_o = opc_opcode_q == 8'b11011001; + /* decoder_pack-p.vhd:378:23 */ + assign n1874_o = n1871_o | n1873_o; + /* decoder_pack-p.vhd:378:36 */ + assign n1876_o = opc_opcode_q == 8'b11011010; + /* decoder_pack-p.vhd:378:36 */ + assign n1877_o = n1874_o | n1876_o; + /* decoder_pack-p.vhd:378:49 */ + assign n1879_o = opc_opcode_q == 8'b11011011; + /* decoder_pack-p.vhd:378:49 */ + assign n1880_o = n1877_o | n1879_o; + /* decoder_pack-p.vhd:378:62 */ + assign n1882_o = opc_opcode_q == 8'b11011100; + /* decoder_pack-p.vhd:378:62 */ + assign n1883_o = n1880_o | n1882_o; + /* decoder_pack-p.vhd:379:23 */ + assign n1885_o = opc_opcode_q == 8'b11011101; + /* decoder_pack-p.vhd:379:23 */ + assign n1886_o = n1883_o | n1885_o; + /* decoder_pack-p.vhd:379:36 */ + assign n1888_o = opc_opcode_q == 8'b11011110; + /* decoder_pack-p.vhd:379:36 */ + assign n1889_o = n1886_o | n1888_o; + /* decoder_pack-p.vhd:379:49 */ + assign n1891_o = opc_opcode_q == 8'b11011111; + /* decoder_pack-p.vhd:379:49 */ + assign n1892_o = n1889_o | n1891_o; + /* decoder_pack-p.vhd:379:62 */ + assign n1894_o = opc_opcode_q == 8'b11010000; + /* decoder_pack-p.vhd:379:62 */ + assign n1895_o = n1892_o | n1894_o; + /* decoder_pack-p.vhd:380:23 */ + assign n1897_o = opc_opcode_q == 8'b11010001; + /* decoder_pack-p.vhd:380:23 */ + assign n1898_o = n1895_o | n1897_o; + /* decoder_pack-p.vhd:384:7 */ + assign n1900_o = opc_opcode_q == 8'b11010011; + assign n1901_o = {n1900_o, n1898_o, n1869_o, n1834_o, n1832_o, n1827_o, n1825_o, n1820_o, n1815_o, n1810_o, n1805_o, n1770_o, n1768_o, n1739_o, n1737_o, n1732_o, n1721_o, n1716_o, n1687_o, n1658_o, n1656_o, n1627_o, n1625_o, n1623_o, n1618_o, n1616_o, n1605_o, n1603_o, n1580_o, n1575_o, n1570_o, n1547_o, n1515_o, n1510_o, n1487_o, n1482_o, n1477_o, n1451_o, n1449_o, n1444_o, n1442_o, n1440_o, n1435_o, n1433_o, n1431_o, n1408_o, n1406_o, n1377_o, n1372_o}; + /* decoder_pack-p.vhd:121:5 */ + always @* + case (n1901_o) + 49'b1000000000000000000000000000000000000000000000000: n1952_o = 6'b111001; + 49'b0100000000000000000000000000000000000000000000000: n1952_o = 6'b111000; + 49'b0010000000000000000000000000000000000000000000000: n1952_o = 6'b110111; + 49'b0001000000000000000000000000000000000000000000000: n1952_o = 6'b110110; + 49'b0000100000000000000000000000000000000000000000000: n1952_o = 6'b110101; + 49'b0000010000000000000000000000000000000000000000000: n1952_o = 6'b110100; + 49'b0000001000000000000000000000000000000000000000000: n1952_o = 6'b110011; + 49'b0000000100000000000000000000000000000000000000000: n1952_o = 6'b110001; + 49'b0000000010000000000000000000000000000000000000000: n1952_o = 6'b110000; + 49'b0000000001000000000000000000000000000000000000000: n1952_o = 6'b101111; + 49'b0000000000100000000000000000000000000000000000000: n1952_o = 6'b101101; + 49'b0000000000010000000000000000000000000000000000000: n1952_o = 6'b101011; + 49'b0000000000001000000000000000000000000000000000000: n1952_o = 6'b101010; + 49'b0000000000000100000000000000000000000000000000000: n1952_o = 6'b101001; + 49'b0000000000000010000000000000000000000000000000000: n1952_o = 6'b100111; + 49'b0000000000000001000000000000000000000000000000000: n1952_o = 6'b100110; + 49'b0000000000000000100000000000000000000000000000000: n1952_o = 6'b100101; + 49'b0000000000000000010000000000000000000000000000000: n1952_o = 6'b100100; + 49'b0000000000000000001000000000000000000000000000000: n1952_o = 6'b100011; + 49'b0000000000000000000100000000000000000000000000000: n1952_o = 6'b100010; + 49'b0000000000000000000010000000000000000000000000000: n1952_o = 6'b100001; + 49'b0000000000000000000001000000000000000000000000000: n1952_o = 6'b100000; + 49'b0000000000000000000000100000000000000000000000000: n1952_o = 6'b011111; + 49'b0000000000000000000000010000000000000000000000000: n1952_o = 6'b011110; + 49'b0000000000000000000000001000000000000000000000000: n1952_o = 6'b011101; + 49'b0000000000000000000000000100000000000000000000000: n1952_o = 6'b011100; + 49'b0000000000000000000000000010000000000000000000000: n1952_o = 6'b011010; + 49'b0000000000000000000000000001000000000000000000000: n1952_o = 6'b011001; + 49'b0000000000000000000000000000100000000000000000000: n1952_o = 6'b011000; + 49'b0000000000000000000000000000010000000000000000000: n1952_o = 6'b010111; + 49'b0000000000000000000000000000001000000000000000000: n1952_o = 6'b010110; + 49'b0000000000000000000000000000000100000000000000000: n1952_o = 6'b010100; + 49'b0000000000000000000000000000000010000000000000000: n1952_o = 6'b010011; + 49'b0000000000000000000000000000000001000000000000000: n1952_o = 6'b010001; + 49'b0000000000000000000000000000000000100000000000000: n1952_o = 6'b010000; + 49'b0000000000000000000000000000000000010000000000000: n1952_o = 6'b001111; + 49'b0000000000000000000000000000000000001000000000000: n1952_o = 6'b001110; + 49'b0000000000000000000000000000000000000100000000000: n1952_o = 6'b001101; + 49'b0000000000000000000000000000000000000010000000000: n1952_o = 6'b001100; + 49'b0000000000000000000000000000000000000001000000000: n1952_o = 6'b001011; + 49'b0000000000000000000000000000000000000000100000000: n1952_o = 6'b001010; + 49'b0000000000000000000000000000000000000000010000000: n1952_o = 6'b001001; + 49'b0000000000000000000000000000000000000000001000000: n1952_o = 6'b001000; + 49'b0000000000000000000000000000000000000000000100000: n1952_o = 6'b000111; + 49'b0000000000000000000000000000000000000000000010000: n1952_o = 6'b000110; + 49'b0000000000000000000000000000000000000000000001000: n1952_o = 6'b000100; + 49'b0000000000000000000000000000000000000000000000100: n1952_o = 6'b000011; + 49'b0000000000000000000000000000000000000000000000010: n1952_o = 6'b000010; + 49'b0000000000000000000000000000000000000000000000001: n1952_o = 6'b000001; + default: n1952_o = 6'b101001; + endcase + /* decoder_pack-p.vhd:121:5 */ + always @* + case (n1901_o) + 49'b1000000000000000000000000000000000000000000000000: n1976_o = 1'b1; + 49'b0100000000000000000000000000000000000000000000000: n1976_o = 1'b0; + 49'b0010000000000000000000000000000000000000000000000: n1976_o = 1'b0; + 49'b0001000000000000000000000000000000000000000000000: n1976_o = 1'b0; + 49'b0000100000000000000000000000000000000000000000000: n1976_o = 1'b0; + 49'b0000010000000000000000000000000000000000000000000: n1976_o = 1'b0; + 49'b0000001000000000000000000000000000000000000000000: n1976_o = 1'b0; + 49'b0000000100000000000000000000000000000000000000000: n1976_o = 1'b0; + 49'b0000000010000000000000000000000000000000000000000: n1976_o = 1'b0; + 49'b0000000001000000000000000000000000000000000000000: n1976_o = 1'b1; + 49'b0000000000100000000000000000000000000000000000000: n1976_o = 1'b1; + 49'b0000000000010000000000000000000000000000000000000: n1976_o = 1'b1; + 49'b0000000000001000000000000000000000000000000000000: n1976_o = 1'b0; + 49'b0000000000000100000000000000000000000000000000000: n1976_o = 1'b0; + 49'b0000000000000010000000000000000000000000000000000: n1976_o = 1'b1; + 49'b0000000000000001000000000000000000000000000000000: n1976_o = 1'b1; + 49'b0000000000000000100000000000000000000000000000000: n1976_o = 1'b0; + 49'b0000000000000000010000000000000000000000000000000: n1976_o = 1'b1; + 49'b0000000000000000001000000000000000000000000000000: n1976_o = 1'b0; + 49'b0000000000000000000100000000000000000000000000000: n1976_o = 1'b0; + 49'b0000000000000000000010000000000000000000000000000: n1976_o = 1'b0; + 49'b0000000000000000000001000000000000000000000000000: n1976_o = 1'b0; + 49'b0000000000000000000000100000000000000000000000000: n1976_o = 1'b1; + 49'b0000000000000000000000010000000000000000000000000: n1976_o = 1'b1; + 49'b0000000000000000000000001000000000000000000000000: n1976_o = 1'b1; + 49'b0000000000000000000000000100000000000000000000000: n1976_o = 1'b1; + 49'b0000000000000000000000000010000000000000000000000: n1976_o = 1'b1; + 49'b0000000000000000000000000001000000000000000000000: n1976_o = 1'b1; + 49'b0000000000000000000000000000100000000000000000000: n1976_o = 1'b1; + 49'b0000000000000000000000000000010000000000000000000: n1976_o = 1'b1; + 49'b0000000000000000000000000000001000000000000000000: n1976_o = 1'b1; + 49'b0000000000000000000000000000000100000000000000000: n1976_o = 1'b0; + 49'b0000000000000000000000000000000010000000000000000: n1976_o = 1'b1; + 49'b0000000000000000000000000000000001000000000000000: n1976_o = 1'b1; + 49'b0000000000000000000000000000000000100000000000000: n1976_o = 1'b0; + 49'b0000000000000000000000000000000000010000000000000: n1976_o = 1'b0; + 49'b0000000000000000000000000000000000001000000000000: n1976_o = 1'b0; + 49'b0000000000000000000000000000000000000100000000000: n1976_o = 1'b0; + 49'b0000000000000000000000000000000000000010000000000: n1976_o = 1'b0; + 49'b0000000000000000000000000000000000000001000000000: n1976_o = 1'b0; + 49'b0000000000000000000000000000000000000000100000000: n1976_o = 1'b0; + 49'b0000000000000000000000000000000000000000010000000: n1976_o = 1'b0; + 49'b0000000000000000000000000000000000000000001000000: n1976_o = 1'b0; + 49'b0000000000000000000000000000000000000000000100000: n1976_o = 1'b0; + 49'b0000000000000000000000000000000000000000000010000: n1976_o = 1'b1; + 49'b0000000000000000000000000000000000000000000001000: n1976_o = 1'b1; + 49'b0000000000000000000000000000000000000000000000100: n1976_o = 1'b0; + 49'b0000000000000000000000000000000000000000000000010: n1976_o = 1'b1; + 49'b0000000000000000000000000000000000000000000000001: n1976_o = 1'b0; + default: n1976_o = 1'b0; + endcase + assign n1980_o = {n1976_o, n1952_o}; + assign n1981_o = {n1302_o, n1294_o}; + /* decoder_pack-p.vhd:528:5 */ + assign n1982_o = n1305_o ? n1980_o : n1981_o; + assign n1985_o = {1'b0, n1250_o}; + /* decoder_pack-p.vhd:566:5 */ + assign n1986_o = n1253_o ? n1982_o : n1985_o; + /* decoder.vhd:301:14 */ + assign n1989_o = ~res_i; + /* decoder.vhd:313:40 */ + assign n1991_o = mnemonic_rec_s[5:0]; + /* decoder.vhd:310:9 */ + assign n1993_o = opc_inj_int_s ? 8'b00010100 : opc_opcode_q; + /* decoder.vhd:310:9 */ + assign n1994_o = opc_inj_int_s ? mnemonic_q : n1991_o; + /* decoder.vhd:308:9 */ + assign n1995_o = opc_read_bus_s ? data_i : n1993_o; + /* decoder.vhd:308:9 */ + assign n1996_o = opc_read_bus_s ? mnemonic_q : n1994_o; + /* decoder.vhd:322:39 */ + assign n2006_o = mnemonic_rec_s[6]; + /* decoder.vhd:324:24 */ + assign n2008_o = 1'b1 ? mnemonic_q : n2009_o; + /* decoder.vhd:325:41 */ + assign n2009_o = mnemonic_rec_s[5:0]; + /* decoder.vhd:343:28 */ + assign int_b_n2010 = int_b_tf_o; // (signal) + /* decoder.vhd:352:28 */ + assign int_b_n2012 = int_b_tim_int_o; // (signal) + /* decoder.vhd:355:28 */ + assign int_b_n2013 = int_b_int_pending_o; // (signal) + /* decoder.vhd:356:28 */ + assign int_b_n2014 = int_b_int_in_progress_o; // (signal) + /* decoder.vhd:333:3 */ + t48_int int_b ( + .clk_i(clk_i), + .res_i(res_i), + .en_clk_i(en_clk_i), + .xtal_i(xtal_i), + .xtal_en_i(xtal_en_i), + .clk_mstate_i(clk_mstate_i), + .jtf_executed_i(jtf_executed_s), + .tim_overflow_i(tim_overflow_i), + .en_tcnti_i(en_tcnti_s), + .dis_tcnti_i(dis_tcnti_s), + .int_n_i(int_n_i), + .ale_i(ale_i), + .last_cycle_i(last_cycle_s), + .en_i_i(en_i_s), + .dis_i_i(dis_i_s), + .retr_executed_i(retr_executed_s), + .int_executed_i(int_executed_s), + .tf_o(int_b_tf_o), + .ext_int_o(), + .tim_int_o(int_b_tim_int_o), + .int_pending_o(int_b_int_pending_o), + .int_in_progress_o(int_b_int_in_progress_o)); + /* decoder.vhd:359:19 */ + assign n2024_o = ~opc_multi_cycle_s; + /* decoder.vhd:360:38 */ + assign n2025_o = opc_multi_cycle_s & clk_second_cycle_i; + /* decoder.vhd:359:41 */ + assign n2026_o = n2024_o | n2025_o; + /* decoder.vhd:393:26 */ + assign n2029_o = ~clk_second_cycle_i; + /* decoder.vhd:394:46 */ + assign n2030_o = clk_second_cycle_i & assert_psen_s; + /* decoder.vhd:393:49 */ + assign n2031_o = n2029_o | n2030_o; + /* decoder.vhd:399:19 */ + assign n2032_o = ~ea_i; + /* decoder.vhd:400:16 */ + assign n2033_o = ~int_pending_s; + /* decoder.vhd:400:13 */ + assign n2036_o = n2033_o ? 1'b1 : 1'b0; + /* decoder.vhd:405:16 */ + assign n2037_o = ~int_pending_s; + /* decoder.vhd:405:13 */ + assign n2040_o = n2037_o ? 1'b1 : 1'b0; + /* decoder.vhd:399:11 */ + assign n2042_o = n2032_o ? n2036_o : 1'b0; + /* decoder.vhd:399:11 */ + assign n2045_o = n2032_o ? 1'b0 : 1'b1; + /* decoder.vhd:399:11 */ + assign n2047_o = n2032_o ? 1'b0 : n2040_o; + /* decoder.vhd:398:9 */ + assign n2049_o = n2031_o ? n2042_o : 1'b0; + /* decoder.vhd:398:9 */ + assign n2051_o = n2031_o ? n2045_o : 1'b0; + /* decoder.vhd:398:9 */ + assign n2053_o = n2031_o ? n2047_o : 1'b0; + /* decoder.vhd:413:12 */ + assign n2054_o = ~clk_second_cycle_i; + /* decoder.vhd:414:14 */ + assign n2055_o = ~int_pending_s; + /* decoder.vhd:414:11 */ + assign n2058_o = n2055_o ? 1'b1 : 1'b0; + /* decoder.vhd:414:11 */ + assign n2061_o = n2055_o ? 1'b0 : 1'b1; + /* decoder.vhd:413:9 */ + assign n2063_o = n2054_o ? n2058_o : 1'b0; + /* decoder.vhd:413:9 */ + assign n2065_o = n2054_o ? n2061_o : 1'b0; + /* decoder.vhd:397:7 */ + assign n2067_o = clk_mstate_i == 3'b000; + /* decoder.vhd:422:31 */ + assign n2068_o = ~branch_taken_q; + /* decoder.vhd:422:27 */ + assign n2069_o = n2031_o & n2068_o; + /* decoder.vhd:423:12 */ + assign n2070_o = ~int_pending_s; + /* decoder.vhd:422:50 */ + assign n2071_o = n2069_o & n2070_o; + /* decoder.vhd:422:9 */ + assign n2074_o = n2071_o ? 1'b1 : 1'b0; + /* decoder.vhd:421:7 */ + assign n2076_o = clk_mstate_i == 3'b001; + /* decoder.vhd:428:9 */ + assign n2079_o = n2031_o ? 1'b1 : 1'b0; + /* decoder.vhd:427:7 */ + assign n2081_o = clk_mstate_i == 3'b010; + /* decoder.vhd:441:14 */ + assign n2082_o = ~clk_second_cycle_i; + /* decoder.vhd:441:37 */ + assign n2083_o = n2082_o & assert_psen_s; + /* decoder.vhd:442:13 */ + assign n2084_o = n2083_o | last_cycle_s; + /* decoder.vhd:440:23 */ + assign n2085_o = ea_i & n2084_o; + /* decoder.vhd:440:9 */ + assign n2088_o = n2085_o ? 1'b1 : 1'b0; + /* decoder.vhd:440:9 */ + assign n2091_o = n2085_o ? 1'b1 : 1'b0; + /* decoder.vhd:440:9 */ + assign n2094_o = n2085_o ? 1'b1 : 1'b0; + /* decoder.vhd:439:7 */ + assign n2096_o = clk_mstate_i == 3'b011; + /* decoder.vhd:450:28 */ + assign n2097_o = n2031_o | last_cycle_s; + /* decoder.vhd:449:23 */ + assign n2098_o = ea_i & n2097_o; + /* decoder.vhd:453:12 */ + assign n2099_o = ~p2_output_exp_s; + /* decoder.vhd:450:45 */ + assign n2100_o = n2098_o & n2099_o; + /* decoder.vhd:455:12 */ + assign n2101_o = ~movx_first_cycle_s; + /* decoder.vhd:453:32 */ + assign n2102_o = n2100_o & n2101_o; + /* decoder.vhd:449:9 */ + assign n2105_o = n2102_o ? 1'b1 : 1'b0; + /* decoder.vhd:448:7 */ + assign n2107_o = clk_mstate_i == 3'b100; + assign n2108_o = {n2107_o, n2096_o, n2081_o, n2076_o, n2067_o}; + /* decoder.vhd:396:5 */ + always @* + case (n2108_o) + 5'b10000: n2110_o = 1'b0; + 5'b01000: n2110_o = 1'b0; + 5'b00100: n2110_o = 1'b0; + 5'b00010: n2110_o = 1'b0; + 5'b00001: n2110_o = n2049_o; + default: n2110_o = 1'b0; + endcase + /* decoder.vhd:396:5 */ + always @* + case (n2108_o) + 5'b10000: n2113_o = 1'b0; + 5'b01000: n2113_o = n2088_o; + 5'b00100: n2113_o = 1'b0; + 5'b00010: n2113_o = 1'b0; + 5'b00001: n2113_o = 1'b0; + default: n2113_o = 1'b0; + endcase + /* decoder.vhd:396:5 */ + always @* + case (n2108_o) + 5'b10000: n2116_o = 1'b0; + 5'b01000: n2116_o = n2091_o; + 5'b00100: n2116_o = 1'b0; + 5'b00010: n2116_o = 1'b0; + 5'b00001: n2116_o = 1'b0; + default: n2116_o = 1'b0; + endcase + /* decoder.vhd:396:5 */ + always @* + case (n2108_o) + 5'b10000: n2119_o = n2105_o; + 5'b01000: n2119_o = n2094_o; + 5'b00100: n2119_o = 1'b0; + 5'b00010: n2119_o = 1'b0; + 5'b00001: n2119_o = n2051_o; + default: n2119_o = 1'b0; + endcase + /* decoder.vhd:396:5 */ + always @* + case (n2108_o) + 5'b10000: n2122_o = 1'b0; + 5'b01000: n2122_o = 1'b0; + 5'b00100: n2122_o = 1'b0; + 5'b00010: n2122_o = 1'b0; + 5'b00001: n2122_o = n2063_o; + default: n2122_o = 1'b0; + endcase + /* decoder.vhd:396:5 */ + always @* + case (n2108_o) + 5'b10000: n2125_o = 1'b0; + 5'b01000: n2125_o = 1'b0; + 5'b00100: n2125_o = 1'b0; + 5'b00010: n2125_o = 1'b0; + 5'b00001: n2125_o = n2065_o; + default: n2125_o = 1'b0; + endcase + /* decoder.vhd:396:5 */ + always @* + case (n2108_o) + 5'b10000: n2128_o = 1'b0; + 5'b01000: n2128_o = 1'b0; + 5'b00100: n2128_o = 1'b0; + 5'b00010: n2128_o = n2074_o; + 5'b00001: n2128_o = 1'b0; + default: n2128_o = 1'b0; + endcase + /* decoder.vhd:396:5 */ + always @* + case (n2108_o) + 5'b10000: n2131_o = 1'b0; + 5'b01000: n2131_o = 1'b0; + 5'b00100: n2131_o = n2079_o; + 5'b00010: n2131_o = 1'b0; + 5'b00001: n2131_o = 1'b0; + default: n2131_o = 1'b0; + endcase + /* decoder.vhd:396:5 */ + always @* + case (n2108_o) + 5'b10000: n2134_o = 1'b0; + 5'b01000: n2134_o = 1'b0; + 5'b00100: n2134_o = 1'b0; + 5'b00010: n2134_o = 1'b0; + 5'b00001: n2134_o = n2053_o; + default: n2134_o = 1'b0; + endcase + /* decoder.vhd:615:5 */ + assign n2141_o = int_in_progress_s ? 1'b0 : mb_q; + /* decoder.vhd:622:8 */ + assign n2142_o = ~clk_second_cycle_i; + /* decoder.vhd:622:48 */ + assign n2144_o = clk_mstate_i == 3'b001; + /* decoder.vhd:622:31 */ + assign n2145_o = n2142_o & n2144_o; + /* decoder.vhd:624:22 */ + assign n2146_o = opc_opcode_q[3]; + /* decoder.vhd:625:43 */ + assign n2147_o = opc_opcode_q[2:0]; + /* decoder.vhd:627:50 */ + assign n2148_o = opc_opcode_q[0]; + /* decoder.vhd:627:36 */ + assign n2150_o = {2'b00, n2148_o}; + /* decoder.vhd:624:7 */ + assign n2151_o = n2146_o ? n2147_o : n2150_o; + assign n2153_o = n2152_o[7:3]; + /* decoder.vhd:622:5 */ + assign n2156_o = n2145_o ? 1'b1 : 1'b0; + assign n2158_o = {n2153_o, n2151_o}; + /* decoder.vhd:622:5 */ + assign n2160_o = n2145_o ? n2158_o : 8'bX; + /* decoder.vhd:622:5 */ + assign n2164_o = n2145_o ? 1'b1 : 1'b0; + /* decoder.vhd:643:28 */ + assign n2166_o = opc_opcode_q[3]; + /* decoder.vhd:643:32 */ + assign n2167_o = ~n2166_o; + /* decoder.vhd:642:44 */ + assign n2169_o = 1'b0 | n2167_o; + /* decoder.vhd:642:13 */ + assign n2176_o = n2169_o ? 1'b1 : n2156_o; + /* decoder.vhd:642:13 */ + assign n2179_o = n2169_o ? 1'b1 : 1'b0; + /* decoder.vhd:642:13 */ + assign n2182_o = n2169_o ? 2'b00 : 2'b01; + /* decoder.vhd:641:11 */ + assign n2184_o = clk_mstate_i == 3'b010; + /* decoder.vhd:648:11 */ + assign n2189_o = clk_mstate_i == 3'b011; + /* decoder.vhd:655:28 */ + assign n2193_o = opc_opcode_q[4]; + /* decoder.vhd:655:13 */ + assign n2196_o = n2193_o ? 1'b1 : 1'b0; + /* decoder.vhd:652:11 */ + assign n2198_o = clk_mstate_i == 3'b100; + assign n2199_o = {n2198_o, n2189_o, n2184_o}; + /* decoder.vhd:639:9 */ + always @* + case (n2199_o) + 3'b100: n2202_o = 1'b1; + 3'b010: n2202_o = 1'b0; + 3'b001: n2202_o = 1'b0; + default: n2202_o = 1'b0; + endcase + /* decoder.vhd:639:9 */ + always @* + case (n2199_o) + 3'b100: n2205_o = 1'b0; + 3'b010: n2205_o = 1'b1; + 3'b001: n2205_o = 1'b0; + default: n2205_o = 1'b0; + endcase + /* decoder.vhd:639:9 */ + always @* + case (n2199_o) + 3'b100: n2208_o = 1'b1; + 3'b010: n2208_o = 1'b0; + 3'b001: n2208_o = 1'b0; + default: n2208_o = 1'b0; + endcase + /* decoder.vhd:639:9 */ + always @* + case (n2199_o) + 3'b100: n2209_o = n2156_o; + 3'b010: n2209_o = n2156_o; + 3'b001: n2209_o = n2176_o; + default: n2209_o = n2156_o; + endcase + /* decoder.vhd:639:9 */ + always @* + case (n2199_o) + 3'b100: n2212_o = 1'b0; + 3'b010: n2212_o = 1'b1; + 3'b001: n2212_o = n2179_o; + default: n2212_o = 1'b0; + endcase + /* decoder.vhd:639:9 */ + always @* + case (n2199_o) + 3'b100: n2215_o = 4'b1010; + 3'b010: n2215_o = 4'b1100; + 3'b001: n2215_o = 4'b1100; + default: n2215_o = 4'b1100; + endcase + /* decoder.vhd:639:9 */ + always @* + case (n2199_o) + 3'b100: n2217_o = n2196_o; + 3'b010: n2217_o = 1'b0; + 3'b001: n2217_o = 1'b0; + default: n2217_o = 1'b0; + endcase + /* decoder.vhd:639:9 */ + always @* + case (n2199_o) + 3'b100: n2219_o = 2'b01; + 3'b010: n2219_o = 2'b01; + 3'b001: n2219_o = n2182_o; + default: n2219_o = 2'b01; + endcase + /* decoder.vhd:639:9 */ + always @* + case (n2199_o) + 3'b100: n2221_o = alu_carry_i; + 3'b010: n2221_o = 1'b0; + 3'b001: n2221_o = 1'b0; + default: n2221_o = 1'b0; + endcase + /* decoder.vhd:639:9 */ + always @* + case (n2199_o) + 3'b100: n2224_o = 1'b1; + 3'b010: n2224_o = 1'b0; + 3'b001: n2224_o = 1'b0; + default: n2224_o = 1'b0; + endcase + /* decoder.vhd:639:9 */ + always @* + case (n2199_o) + 3'b100: n2227_o = 1'b1; + 3'b010: n2227_o = 1'b0; + 3'b001: n2227_o = 1'b0; + default: n2227_o = 1'b0; + endcase + /* decoder.vhd:638:7 */ + assign n2229_o = opc_mnemonic_s == 6'b000001; + /* decoder.vhd:675:13 */ + assign n2231_o = clk_mstate_i == 3'b000; + /* decoder.vhd:682:30 */ + assign n2235_o = opc_opcode_q[4]; + /* decoder.vhd:682:15 */ + assign n2238_o = n2235_o ? 1'b1 : 1'b0; + /* decoder.vhd:679:13 */ + assign n2240_o = clk_mstate_i == 3'b010; + assign n2241_o = {n2240_o, n2231_o}; + /* decoder.vhd:673:11 */ + always @* + case (n2241_o) + 2'b10: n2244_o = 1'b1; + 2'b01: n2244_o = 1'b0; + default: n2244_o = 1'b0; + endcase + /* decoder.vhd:673:11 */ + always @* + case (n2241_o) + 2'b10: n2247_o = 1'b0; + 2'b01: n2247_o = 1'b1; + default: n2247_o = 1'b0; + endcase + /* decoder.vhd:673:11 */ + always @* + case (n2241_o) + 2'b10: n2250_o = 1'b1; + 2'b01: n2250_o = 1'b0; + default: n2250_o = 1'b0; + endcase + /* decoder.vhd:673:11 */ + always @* + case (n2241_o) + 2'b10: n2253_o = 4'b1010; + 2'b01: n2253_o = 4'b1100; + default: n2253_o = 4'b1100; + endcase + /* decoder.vhd:673:11 */ + always @* + case (n2241_o) + 2'b10: n2255_o = n2238_o; + 2'b01: n2255_o = 1'b0; + default: n2255_o = 1'b0; + endcase + /* decoder.vhd:673:11 */ + always @* + case (n2241_o) + 2'b10: n2257_o = alu_carry_i; + 2'b01: n2257_o = 1'b0; + default: n2257_o = 1'b0; + endcase + /* decoder.vhd:673:11 */ + always @* + case (n2241_o) + 2'b10: n2260_o = 1'b1; + 2'b01: n2260_o = 1'b0; + default: n2260_o = 1'b0; + endcase + /* decoder.vhd:673:11 */ + always @* + case (n2241_o) + 2'b10: n2263_o = 1'b1; + 2'b01: n2263_o = 1'b0; + default: n2263_o = 1'b0; + endcase + /* decoder.vhd:672:9 */ + assign n2265_o = clk_second_cycle_i ? n2244_o : 1'b0; + /* decoder.vhd:672:9 */ + assign n2267_o = clk_second_cycle_i ? n2247_o : 1'b0; + /* decoder.vhd:672:9 */ + assign n2269_o = clk_second_cycle_i ? n2250_o : 1'b0; + /* decoder.vhd:672:9 */ + assign n2271_o = clk_second_cycle_i ? n2253_o : 4'b1100; + /* decoder.vhd:672:9 */ + assign n2273_o = clk_second_cycle_i ? n2255_o : 1'b0; + /* decoder.vhd:672:9 */ + assign n2275_o = clk_second_cycle_i ? n2257_o : 1'b0; + /* decoder.vhd:672:9 */ + assign n2277_o = clk_second_cycle_i ? n2260_o : 1'b0; + /* decoder.vhd:672:9 */ + assign n2279_o = clk_second_cycle_i ? n2263_o : 1'b0; + /* decoder.vhd:669:7 */ + assign n2281_o = opc_mnemonic_s == 6'b000010; + /* decoder.vhd:703:28 */ + assign n2282_o = opc_opcode_q[3]; + /* decoder.vhd:703:32 */ + assign n2283_o = ~n2282_o; + /* decoder.vhd:702:44 */ + assign n2285_o = 1'b0 | n2283_o; + /* decoder.vhd:702:13 */ + assign n2292_o = n2285_o ? 1'b1 : n2156_o; + /* decoder.vhd:702:13 */ + assign n2295_o = n2285_o ? 1'b1 : 1'b0; + /* decoder.vhd:702:13 */ + assign n2298_o = n2285_o ? 2'b00 : 2'b01; + /* decoder.vhd:701:11 */ + assign n2300_o = clk_mstate_i == 3'b010; + /* decoder.vhd:708:11 */ + assign n2305_o = clk_mstate_i == 3'b011; + /* decoder.vhd:712:11 */ + assign n2310_o = clk_mstate_i == 3'b100; + assign n2311_o = {n2310_o, n2305_o, n2300_o}; + /* decoder.vhd:699:9 */ + always @* + case (n2311_o) + 3'b100: n2314_o = 1'b1; + 3'b010: n2314_o = 1'b0; + 3'b001: n2314_o = 1'b0; + default: n2314_o = 1'b0; + endcase + /* decoder.vhd:699:9 */ + always @* + case (n2311_o) + 3'b100: n2317_o = 1'b0; + 3'b010: n2317_o = 1'b1; + 3'b001: n2317_o = 1'b0; + default: n2317_o = 1'b0; + endcase + /* decoder.vhd:699:9 */ + always @* + case (n2311_o) + 3'b100: n2320_o = 1'b1; + 3'b010: n2320_o = 1'b0; + 3'b001: n2320_o = 1'b0; + default: n2320_o = 1'b0; + endcase + /* decoder.vhd:699:9 */ + always @* + case (n2311_o) + 3'b100: n2321_o = n2156_o; + 3'b010: n2321_o = n2156_o; + 3'b001: n2321_o = n2292_o; + default: n2321_o = n2156_o; + endcase + /* decoder.vhd:699:9 */ + always @* + case (n2311_o) + 3'b100: n2324_o = 1'b0; + 3'b010: n2324_o = 1'b1; + 3'b001: n2324_o = n2295_o; + default: n2324_o = 1'b0; + endcase + /* decoder.vhd:699:9 */ + always @* + case (n2311_o) + 3'b100: n2327_o = 4'b0000; + 3'b010: n2327_o = 4'b1100; + 3'b001: n2327_o = 4'b1100; + default: n2327_o = 4'b1100; + endcase + /* decoder.vhd:699:9 */ + always @* + case (n2311_o) + 3'b100: n2329_o = 2'b01; + 3'b010: n2329_o = 2'b01; + 3'b001: n2329_o = n2298_o; + default: n2329_o = 2'b01; + endcase + /* decoder.vhd:698:7 */ + assign n2331_o = opc_mnemonic_s == 6'b000011; + /* decoder.vhd:727:13 */ + assign n2333_o = clk_mstate_i == 3'b000; + /* decoder.vhd:731:13 */ + assign n2338_o = clk_mstate_i == 3'b010; + assign n2339_o = {n2338_o, n2333_o}; + /* decoder.vhd:725:11 */ + always @* + case (n2339_o) + 2'b10: n2342_o = 1'b1; + 2'b01: n2342_o = 1'b0; + default: n2342_o = 1'b0; + endcase + /* decoder.vhd:725:11 */ + always @* + case (n2339_o) + 2'b10: n2345_o = 1'b0; + 2'b01: n2345_o = 1'b1; + default: n2345_o = 1'b0; + endcase + /* decoder.vhd:725:11 */ + always @* + case (n2339_o) + 2'b10: n2348_o = 1'b1; + 2'b01: n2348_o = 1'b0; + default: n2348_o = 1'b0; + endcase + /* decoder.vhd:725:11 */ + always @* + case (n2339_o) + 2'b10: n2351_o = 4'b0000; + 2'b01: n2351_o = 4'b1100; + default: n2351_o = 4'b1100; + endcase + /* decoder.vhd:724:9 */ + assign n2353_o = clk_second_cycle_i ? n2342_o : 1'b0; + /* decoder.vhd:724:9 */ + assign n2355_o = clk_second_cycle_i ? n2345_o : 1'b0; + /* decoder.vhd:724:9 */ + assign n2357_o = clk_second_cycle_i ? n2348_o : 1'b0; + /* decoder.vhd:724:9 */ + assign n2359_o = clk_second_cycle_i ? n2351_o : 4'b1100; + /* decoder.vhd:721:7 */ + assign n2361_o = opc_mnemonic_s == 6'b000100; + /* decoder.vhd:745:12 */ + assign n2362_o = ~clk_second_cycle_i; + /* decoder.vhd:747:27 */ + assign n2364_o = clk_mstate_i == 3'b100; + /* decoder.vhd:748:28 */ + assign n2365_o = opc_opcode_q[1:0]; + /* decoder.vhd:748:41 */ + assign n2367_o = n2365_o == 2'b00; + /* decoder.vhd:750:31 */ + assign n2368_o = opc_opcode_q[1]; + /* decoder.vhd:750:35 */ + assign n2369_o = ~n2368_o; + /* decoder.vhd:750:13 */ + assign n2372_o = n2369_o ? 1'b1 : 1'b0; + /* decoder.vhd:750:13 */ + assign n2375_o = n2369_o ? 1'b0 : 1'b1; + /* decoder.vhd:750:13 */ + assign n2378_o = n2369_o ? 1'b1 : 1'b0; + /* decoder.vhd:750:13 */ + assign n2381_o = n2369_o ? 1'b0 : 1'b1; + /* decoder.vhd:748:13 */ + assign n2383_o = n2367_o ? 1'b0 : n2372_o; + /* decoder.vhd:748:13 */ + assign n2385_o = n2367_o ? 1'b0 : n2375_o; + /* decoder.vhd:748:13 */ + assign n2387_o = n2367_o ? 1'b0 : n2378_o; + /* decoder.vhd:748:13 */ + assign n2389_o = n2367_o ? 1'b0 : n2381_o; + /* decoder.vhd:748:13 */ + assign n2392_o = n2367_o ? 1'b1 : 1'b0; + /* decoder.vhd:747:11 */ + assign n2395_o = n2364_o ? 1'b1 : 1'b0; + /* decoder.vhd:747:11 */ + assign n2397_o = n2364_o ? n2383_o : 1'b0; + /* decoder.vhd:747:11 */ + assign n2399_o = n2364_o ? n2385_o : 1'b0; + /* decoder.vhd:747:11 */ + assign n2401_o = n2364_o ? n2387_o : 1'b0; + /* decoder.vhd:747:11 */ + assign n2403_o = n2364_o ? n2389_o : 1'b0; + /* decoder.vhd:747:11 */ + assign n2405_o = n2364_o ? n2392_o : 1'b0; + /* decoder.vhd:765:13 */ + assign n2407_o = clk_mstate_i == 3'b000; + /* decoder.vhd:770:13 */ + assign n2409_o = clk_mstate_i == 3'b001; + /* decoder.vhd:779:30 */ + assign n2410_o = opc_opcode_q[1:0]; + /* decoder.vhd:779:43 */ + assign n2412_o = n2410_o == 2'b00; + /* decoder.vhd:781:33 */ + assign n2413_o = opc_opcode_q[1]; + /* decoder.vhd:781:37 */ + assign n2414_o = ~n2413_o; + /* decoder.vhd:781:15 */ + assign n2417_o = n2414_o ? 1'b1 : 1'b0; + /* decoder.vhd:781:15 */ + assign n2420_o = n2414_o ? 1'b0 : 1'b1; + /* decoder.vhd:779:15 */ + assign n2423_o = n2412_o ? 1'b1 : 1'b0; + /* decoder.vhd:779:15 */ + assign n2425_o = n2412_o ? 1'b0 : n2417_o; + /* decoder.vhd:779:15 */ + assign n2427_o = n2412_o ? 1'b0 : n2420_o; + /* decoder.vhd:775:13 */ + assign n2429_o = clk_mstate_i == 3'b010; + assign n2430_o = {n2429_o, n2409_o, n2407_o}; + /* decoder.vhd:762:11 */ + always @* + case (n2430_o) + 3'b100: n2434_o = 1'b0; + 3'b010: n2434_o = 1'b1; + 3'b001: n2434_o = 1'b1; + default: n2434_o = 1'b0; + endcase + /* decoder.vhd:762:11 */ + always @* + case (n2430_o) + 3'b100: n2438_o = 1'b1; + 3'b010: n2438_o = 1'b1; + 3'b001: n2438_o = 1'b0; + default: n2438_o = 1'b0; + endcase + /* decoder.vhd:762:11 */ + always @* + case (n2430_o) + 3'b100: n2440_o = n2423_o; + 3'b010: n2440_o = 1'b0; + 3'b001: n2440_o = 1'b0; + default: n2440_o = 1'b0; + endcase + /* decoder.vhd:762:11 */ + always @* + case (n2430_o) + 3'b100: n2442_o = n2425_o; + 3'b010: n2442_o = 1'b0; + 3'b001: n2442_o = 1'b0; + default: n2442_o = 1'b0; + endcase + /* decoder.vhd:762:11 */ + always @* + case (n2430_o) + 3'b100: n2444_o = n2427_o; + 3'b010: n2444_o = 1'b0; + 3'b001: n2444_o = 1'b0; + default: n2444_o = 1'b0; + endcase + /* decoder.vhd:762:11 */ + always @* + case (n2430_o) + 3'b100: n2447_o = 4'b0000; + 3'b010: n2447_o = 4'b1100; + 3'b001: n2447_o = 4'b1100; + default: n2447_o = 4'b1100; + endcase + /* decoder.vhd:745:9 */ + assign n2449_o = n2362_o ? 1'b0 : n2434_o; + /* decoder.vhd:745:9 */ + assign n2451_o = n2362_o ? n2395_o : 1'b0; + /* decoder.vhd:745:9 */ + assign n2453_o = n2362_o ? 1'b0 : n2438_o; + /* decoder.vhd:745:9 */ + assign n2455_o = n2362_o ? 1'b0 : n2440_o; + /* decoder.vhd:745:9 */ + assign n2457_o = n2362_o ? 1'b0 : n2442_o; + /* decoder.vhd:745:9 */ + assign n2459_o = n2362_o ? n2397_o : 1'b0; + /* decoder.vhd:745:9 */ + assign n2461_o = n2362_o ? 1'b0 : n2444_o; + /* decoder.vhd:745:9 */ + assign n2463_o = n2362_o ? n2399_o : 1'b0; + /* decoder.vhd:745:9 */ + assign n2465_o = n2362_o ? 4'b1100 : n2447_o; + /* decoder.vhd:745:9 */ + assign n2467_o = n2362_o ? n2401_o : 1'b0; + /* decoder.vhd:745:9 */ + assign n2469_o = n2362_o ? n2403_o : 1'b0; + /* decoder.vhd:745:9 */ + assign n2471_o = n2362_o ? n2405_o : 1'b0; + /* decoder.vhd:742:7 */ + assign n2473_o = opc_mnemonic_s == 6'b000101; + /* decoder.vhd:798:12 */ + assign n2474_o = ~clk_second_cycle_i; + /* decoder.vhd:811:18 */ + assign n2475_o = ~int_pending_s; + /* decoder.vhd:811:15 */ + assign n2478_o = n2475_o ? 1'b1 : 1'b0; + /* decoder.vhd:802:13 */ + assign n2480_o = clk_mstate_i == 3'b010; + /* decoder.vhd:816:13 */ + assign n2482_o = clk_mstate_i == 3'b011; + /* decoder.vhd:822:13 */ + assign n2484_o = clk_mstate_i == 3'b100; + assign n2485_o = {n2484_o, n2482_o, n2480_o}; + /* decoder.vhd:799:11 */ + always @* + case (n2485_o) + 3'b100: n2488_o = 1'b1; + 3'b010: n2488_o = n2156_o; + 3'b001: n2488_o = 1'b1; + default: n2488_o = n2156_o; + endcase + /* decoder.vhd:799:11 */ + always @* + case (n2485_o) + 3'b100: n2491_o = 1'b0; + 3'b010: n2491_o = 1'b1; + 3'b001: n2491_o = 1'b0; + default: n2491_o = 1'b0; + endcase + /* decoder.vhd:799:11 */ + always @* + case (n2485_o) + 3'b100: n2494_o = 1'b1; + 3'b010: n2494_o = 1'b0; + 3'b001: n2494_o = 1'b0; + default: n2494_o = 1'b0; + endcase + /* decoder.vhd:799:11 */ + always @* + case (n2485_o) + 3'b100: n2497_o = 1'b1; + 3'b010: n2497_o = 1'b0; + 3'b001: n2497_o = 1'b0; + default: n2497_o = 1'b0; + endcase + /* decoder.vhd:799:11 */ + always @* + case (n2485_o) + 3'b100: n2500_o = 1'b0; + 3'b010: n2500_o = 1'b0; + 3'b001: n2500_o = 1'b1; + default: n2500_o = 1'b0; + endcase + /* decoder.vhd:799:11 */ + always @* + case (n2485_o) + 3'b100: n2504_o = 2'b11; + 3'b010: n2504_o = 2'b01; + 3'b001: n2504_o = 2'b10; + default: n2504_o = 2'b01; + endcase + /* decoder.vhd:799:11 */ + always @* + case (n2485_o) + 3'b100: n2507_o = 1'b1; + 3'b010: n2507_o = 1'b0; + 3'b001: n2507_o = 1'b0; + default: n2507_o = 1'b0; + endcase + /* decoder.vhd:799:11 */ + always @* + case (n2485_o) + 3'b100: n2509_o = 1'b0; + 3'b010: n2509_o = 1'b0; + 3'b001: n2509_o = n2478_o; + default: n2509_o = 1'b0; + endcase + /* decoder.vhd:799:11 */ + always @* + case (n2485_o) + 3'b100: n2513_o = 1'b1; + 3'b010: n2513_o = 1'b1; + 3'b001: n2513_o = 1'b0; + default: n2513_o = 1'b0; + endcase + /* decoder.vhd:845:17 */ + assign n2520_o = tim_int_s ? 1'b0 : 1'b1; + assign n2521_o = n2515_o[2]; + /* decoder.vhd:845:17 */ + assign n2522_o = tim_int_s ? 1'b1 : n2521_o; + assign n2523_o = n2515_o[7:3]; + /* decoder.vhd:841:15 */ + assign n2525_o = int_pending_s ? n2520_o : 1'b0; + assign n2526_o = {n2523_o, n2522_o, 2'b11}; + /* decoder.vhd:841:15 */ + assign n2527_o = int_pending_s ? n2526_o : n2160_o; + /* decoder.vhd:841:15 */ + assign n2529_o = int_pending_s ? 1'b1 : n2164_o; + /* decoder.vhd:838:13 */ + assign n2531_o = clk_mstate_i == 3'b000; + /* decoder.vhd:856:18 */ + assign n2532_o = ~int_pending_s; + /* decoder.vhd:858:46 */ + assign n2534_o = {4'b0000, n2141_o}; + /* decoder.vhd:858:67 */ + assign n2535_o = opc_opcode_q[7:5]; + /* decoder.vhd:858:53 */ + assign n2536_o = {n2534_o, n2535_o}; + /* decoder.vhd:856:15 */ + assign n2538_o = n2532_o ? n2536_o : 8'b00000000; + /* decoder.vhd:856:15 */ + assign n2541_o = n2532_o ? 1'b0 : 1'b1; + /* decoder.vhd:853:13 */ + assign n2543_o = clk_mstate_i == 3'b001; + assign n2544_o = {n2543_o, n2531_o}; + /* decoder.vhd:836:11 */ + always @* + case (n2544_o) + 2'b10: n2546_o = 1'b0; + 2'b01: n2546_o = n2525_o; + default: n2546_o = 1'b0; + endcase + /* decoder.vhd:836:11 */ + always @* + case (n2544_o) + 2'b10: n2549_o = 1'b0; + 2'b01: n2549_o = 1'b1; + default: n2549_o = 1'b0; + endcase + /* decoder.vhd:836:11 */ + always @* + case (n2544_o) + 2'b10: n2552_o = 1'b1; + 2'b01: n2552_o = 1'b0; + default: n2552_o = 1'b0; + endcase + /* decoder.vhd:836:11 */ + always @* + case (n2544_o) + 2'b10: n2555_o = 1'b0; + 2'b01: n2555_o = 1'b1; + default: n2555_o = 1'b0; + endcase + /* decoder.vhd:836:11 */ + always @* + case (n2544_o) + 2'b10: n2556_o = n2538_o; + 2'b01: n2556_o = n2527_o; + default: n2556_o = n2160_o; + endcase + /* decoder.vhd:836:11 */ + always @* + case (n2544_o) + 2'b10: n2558_o = 1'b1; + 2'b01: n2558_o = n2529_o; + default: n2558_o = n2164_o; + endcase + /* decoder.vhd:836:11 */ + always @* + case (n2544_o) + 2'b10: n2560_o = n2541_o; + 2'b01: n2560_o = 1'b0; + default: n2560_o = 1'b0; + endcase + /* decoder.vhd:798:9 */ + assign n2562_o = n2474_o ? 1'b0 : n2546_o; + /* decoder.vhd:798:9 */ + assign n2563_o = n2474_o ? n2488_o : n2156_o; + /* decoder.vhd:798:9 */ + assign n2565_o = n2474_o ? 1'b0 : n2549_o; + /* decoder.vhd:798:9 */ + assign n2567_o = n2474_o ? n2491_o : 1'b0; + /* decoder.vhd:798:9 */ + assign n2569_o = n2474_o ? 1'b0 : n2552_o; + /* decoder.vhd:798:9 */ + assign n2571_o = n2474_o ? n2494_o : 1'b0; + /* decoder.vhd:798:9 */ + assign n2573_o = n2474_o ? n2497_o : 1'b0; + /* decoder.vhd:798:9 */ + assign n2575_o = n2474_o ? n2500_o : 1'b0; + /* decoder.vhd:798:9 */ + assign n2577_o = n2474_o ? n2504_o : 2'b01; + /* decoder.vhd:798:9 */ + assign n2579_o = n2474_o ? n2507_o : 1'b0; + /* decoder.vhd:798:9 */ + assign n2581_o = n2474_o ? 1'b0 : n2555_o; + /* decoder.vhd:798:9 */ + assign n2583_o = n2474_o ? n2509_o : 1'b0; + /* decoder.vhd:798:9 */ + assign n2584_o = n2474_o ? n2160_o : n2556_o; + /* decoder.vhd:798:9 */ + assign n2585_o = n2474_o ? n2164_o : n2558_o; + /* decoder.vhd:798:9 */ + assign n2587_o = n2474_o ? n2513_o : 1'b0; + /* decoder.vhd:798:9 */ + assign n2589_o = n2474_o ? 1'b0 : n2560_o; + /* decoder.vhd:795:7 */ + assign n2591_o = opc_mnemonic_s == 6'b000110; + /* decoder.vhd:875:25 */ + assign n2593_o = clk_mstate_i == 3'b010; + /* decoder.vhd:875:9 */ + assign n2596_o = n2593_o ? 1'b1 : 1'b0; + /* decoder.vhd:875:9 */ + assign n2599_o = n2593_o ? 1'b1 : 1'b0; + /* decoder.vhd:875:9 */ + assign n2602_o = n2593_o ? 4'b0100 : 4'b1100; + /* decoder.vhd:873:7 */ + assign n2604_o = opc_mnemonic_s == 6'b000111; + /* decoder.vhd:884:25 */ + assign n2606_o = clk_mstate_i == 3'b010; + /* decoder.vhd:884:9 */ + assign n2609_o = n2606_o ? 1'b1 : 1'b0; + /* decoder.vhd:882:7 */ + assign n2611_o = opc_mnemonic_s == 6'b001000; + /* decoder.vhd:892:25 */ + assign n2613_o = clk_mstate_i == 3'b010; + /* decoder.vhd:893:26 */ + assign n2614_o = opc_opcode_q[5]; + /* decoder.vhd:893:30 */ + assign n2615_o = ~n2614_o; + /* decoder.vhd:893:11 */ + assign n2618_o = n2615_o ? 1'b1 : 1'b0; + /* decoder.vhd:893:11 */ + assign n2621_o = n2615_o ? 1'b0 : 1'b1; + /* decoder.vhd:892:9 */ + assign n2623_o = n2613_o ? n2618_o : 1'b0; + /* decoder.vhd:892:9 */ + assign n2625_o = n2613_o ? n2621_o : 1'b0; + /* decoder.vhd:890:7 */ + assign n2627_o = opc_mnemonic_s == 6'b001001; + /* decoder.vhd:905:25 */ + assign n2629_o = clk_mstate_i == 3'b010; + /* decoder.vhd:905:9 */ + assign n2632_o = n2629_o ? 1'b1 : 1'b0; + /* decoder.vhd:905:9 */ + assign n2635_o = n2629_o ? 1'b1 : 1'b0; + /* decoder.vhd:905:9 */ + assign n2638_o = n2629_o ? 4'b0011 : 4'b1100; + /* decoder.vhd:903:7 */ + assign n2640_o = opc_mnemonic_s == 6'b001010; + /* decoder.vhd:914:25 */ + assign n2642_o = clk_mstate_i == 3'b010; + /* decoder.vhd:915:33 */ + assign n2643_o = ~psw_carry_i; + /* decoder.vhd:914:9 */ + assign n2645_o = n2642_o ? n2643_o : 1'b0; + /* decoder.vhd:914:9 */ + assign n2648_o = n2642_o ? 1'b1 : 1'b0; + /* decoder.vhd:912:7 */ + assign n2650_o = opc_mnemonic_s == 6'b001011; + /* decoder.vhd:922:25 */ + assign n2652_o = clk_mstate_i == 3'b010; + /* decoder.vhd:923:26 */ + assign n2653_o = opc_opcode_q[5]; + /* decoder.vhd:923:30 */ + assign n2654_o = ~n2653_o; + /* decoder.vhd:924:35 */ + assign n2655_o = ~psw_f0_i; + /* decoder.vhd:923:11 */ + assign n2657_o = n2654_o ? n2655_o : 1'b0; + /* decoder.vhd:923:11 */ + assign n2660_o = n2654_o ? 1'b1 : 1'b0; + /* decoder.vhd:923:11 */ + assign n2663_o = n2654_o ? 1'b0 : 1'b1; + /* decoder.vhd:922:9 */ + assign n2665_o = n2652_o ? n2657_o : 1'b0; + /* decoder.vhd:922:9 */ + assign n2667_o = n2652_o ? n2660_o : 1'b0; + /* decoder.vhd:922:9 */ + assign n2669_o = n2652_o ? n2663_o : 1'b0; + /* decoder.vhd:920:7 */ + assign n2671_o = opc_mnemonic_s == 6'b001100; + /* decoder.vhd:938:11 */ + assign n2673_o = clk_mstate_i == 3'b010; + /* decoder.vhd:944:38 */ + assign n2674_o = psw_aux_carry_i | alu_da_overflow_i; + /* decoder.vhd:944:13 */ + assign n2677_o = n2674_o ? 1'b1 : 1'b0; + /* decoder.vhd:944:13 */ + assign n2680_o = n2674_o ? 1'b1 : 1'b0; + /* decoder.vhd:943:11 */ + assign n2682_o = clk_mstate_i == 3'b011; + /* decoder.vhd:958:13 */ + assign n2685_o = alu_da_overflow_i ? 4'b1010 : 4'b1100; + /* decoder.vhd:958:13 */ + assign n2687_o = alu_da_overflow_i ? alu_carry_i : 1'b0; + /* decoder.vhd:955:11 */ + assign n2689_o = clk_mstate_i == 3'b100; + assign n2690_o = {n2689_o, n2682_o, n2673_o}; + /* decoder.vhd:936:9 */ + always @* + case (n2690_o) + 3'b100: n2693_o = 1'b1; + 3'b010: n2693_o = 1'b0; + 3'b001: n2693_o = 1'b0; + default: n2693_o = 1'b0; + endcase + /* decoder.vhd:936:9 */ + always @* + case (n2690_o) + 3'b100: n2695_o = 1'b0; + 3'b010: n2695_o = n2677_o; + 3'b001: n2695_o = 1'b0; + default: n2695_o = 1'b0; + endcase + /* decoder.vhd:936:9 */ + always @* + case (n2690_o) + 3'b100: n2698_o = 1'b1; + 3'b010: n2698_o = n2680_o; + 3'b001: n2698_o = 1'b0; + default: n2698_o = 1'b0; + endcase + /* decoder.vhd:936:9 */ + always @* + case (n2690_o) + 3'b100: n2700_o = n2685_o; + 3'b010: n2700_o = 4'b1010; + 3'b001: n2700_o = 4'b1010; + default: n2700_o = 4'b1010; + endcase + /* decoder.vhd:936:9 */ + always @* + case (n2690_o) + 3'b100: n2704_o = 1'b1; + 3'b010: n2704_o = 1'b0; + 3'b001: n2704_o = 1'b0; + default: n2704_o = 1'b0; + endcase + /* decoder.vhd:936:9 */ + always @* + case (n2690_o) + 3'b100: n2707_o = 1'b0; + 3'b010: n2707_o = 1'b0; + 3'b001: n2707_o = 1'b1; + default: n2707_o = 1'b0; + endcase + /* decoder.vhd:936:9 */ + always @* + case (n2690_o) + 3'b100: n2710_o = 1'b0; + 3'b010: n2710_o = 1'b1; + 3'b001: n2710_o = 1'b0; + default: n2710_o = 1'b0; + endcase + /* decoder.vhd:936:9 */ + always @* + case (n2690_o) + 3'b100: n2712_o = n2687_o; + 3'b010: n2712_o = 1'b0; + 3'b001: n2712_o = 1'b0; + default: n2712_o = 1'b0; + endcase + /* decoder.vhd:936:9 */ + always @* + case (n2690_o) + 3'b100: n2715_o = 1'b1; + 3'b010: n2715_o = 1'b0; + 3'b001: n2715_o = 1'b0; + default: n2715_o = 1'b0; + endcase + /* decoder.vhd:933:7 */ + assign n2717_o = opc_mnemonic_s == 6'b001101; + /* decoder.vhd:978:28 */ + assign n2718_o = opc_opcode_q[6]; + /* decoder.vhd:978:13 */ + assign n2721_o = n2718_o ? 1'b1 : 1'b0; + /* decoder.vhd:978:13 */ + assign n2724_o = n2718_o ? 1'b1 : 1'b0; + /* decoder.vhd:976:11 */ + assign n2726_o = clk_mstate_i == 3'b011; + /* decoder.vhd:987:28 */ + assign n2727_o = opc_opcode_q[6]; + /* decoder.vhd:987:32 */ + assign n2728_o = ~n2727_o; + /* decoder.vhd:987:13 */ + assign n2731_o = n2728_o ? 1'b1 : 1'b0; + /* decoder.vhd:987:13 */ + assign n2734_o = n2728_o ? 1'b0 : 1'b1; + /* decoder.vhd:983:11 */ + assign n2736_o = clk_mstate_i == 3'b100; + assign n2737_o = {n2736_o, n2726_o}; + /* decoder.vhd:975:9 */ + always @* + case (n2737_o) + 2'b10: n2739_o = n2731_o; + 2'b01: n2739_o = 1'b0; + default: n2739_o = 1'b0; + endcase + /* decoder.vhd:975:9 */ + always @* + case (n2737_o) + 2'b10: n2741_o = 1'b0; + 2'b01: n2741_o = n2721_o; + default: n2741_o = 1'b0; + endcase + /* decoder.vhd:975:9 */ + always @* + case (n2737_o) + 2'b10: n2744_o = 1'b1; + 2'b01: n2744_o = 1'b0; + default: n2744_o = 1'b0; + endcase + /* decoder.vhd:975:9 */ + always @* + case (n2737_o) + 2'b10: n2746_o = 1'b0; + 2'b01: n2746_o = n2724_o; + default: n2746_o = 1'b0; + endcase + /* decoder.vhd:975:9 */ + always @* + case (n2737_o) + 2'b10: n2749_o = 4'b1000; + 2'b01: n2749_o = 4'b1100; + default: n2749_o = 4'b1100; + endcase + /* decoder.vhd:975:9 */ + always @* + case (n2737_o) + 2'b10: n2751_o = n2734_o; + 2'b01: n2751_o = 1'b0; + default: n2751_o = 1'b0; + endcase + /* decoder.vhd:974:7 */ + assign n2753_o = opc_mnemonic_s == 6'b001110; + /* decoder.vhd:1002:25 */ + assign n2755_o = clk_mstate_i == 3'b010; + /* decoder.vhd:1003:26 */ + assign n2756_o = opc_opcode_q[4]; + /* decoder.vhd:1003:11 */ + assign n2759_o = n2756_o ? 1'b0 : 1'b1; + /* decoder.vhd:1003:11 */ + assign n2762_o = n2756_o ? 1'b1 : 1'b0; + /* decoder.vhd:1002:9 */ + assign n2764_o = n2755_o ? n2759_o : 1'b0; + /* decoder.vhd:1002:9 */ + assign n2766_o = n2755_o ? n2762_o : 1'b0; + /* decoder.vhd:1001:7 */ + assign n2768_o = opc_mnemonic_s == 6'b001111; + /* decoder.vhd:1012:25 */ + assign n2770_o = clk_mstate_i == 3'b010; + /* decoder.vhd:1013:26 */ + assign n2771_o = opc_opcode_q[4]; + /* decoder.vhd:1013:11 */ + assign n2774_o = n2771_o ? 1'b0 : 1'b1; + /* decoder.vhd:1013:11 */ + assign n2777_o = n2771_o ? 1'b1 : 1'b0; + /* decoder.vhd:1012:9 */ + assign n2779_o = n2770_o ? n2774_o : 1'b0; + /* decoder.vhd:1012:9 */ + assign n2781_o = n2770_o ? n2777_o : 1'b0; + /* decoder.vhd:1011:7 */ + assign n2783_o = opc_mnemonic_s == 6'b010000; + /* decoder.vhd:1024:12 */ + assign n2784_o = ~clk_second_cycle_i; + /* decoder.vhd:1027:13 */ + assign n2786_o = clk_mstate_i == 3'b011; + /* decoder.vhd:1033:13 */ + assign n2789_o = clk_mstate_i == 3'b100; + assign n2790_o = {n2789_o, n2786_o}; + /* decoder.vhd:1025:11 */ + always @* + case (n2790_o) + 2'b10: n2793_o = 1'b0; + 2'b01: n2793_o = 1'b1; + default: n2793_o = 1'b0; + endcase + /* decoder.vhd:1025:11 */ + always @* + case (n2790_o) + 2'b10: n2796_o = 1'b1; + 2'b01: n2796_o = 1'b0; + default: n2796_o = 1'b0; + endcase + /* decoder.vhd:1025:11 */ + always @* + case (n2790_o) + 2'b10: n2799_o = 1'b0; + 2'b01: n2799_o = 1'b1; + default: n2799_o = 1'b0; + endcase + /* decoder.vhd:1025:11 */ + always @* + case (n2790_o) + 2'b10: n2802_o = 4'b1000; + 2'b01: n2802_o = 4'b1100; + default: n2802_o = 4'b1100; + endcase + /* decoder.vhd:1025:11 */ + always @* + case (n2790_o) + 2'b10: n2805_o = 1'b1; + 2'b01: n2805_o = 1'b0; + default: n2805_o = 1'b0; + endcase + /* decoder.vhd:1025:11 */ + always @* + case (n2790_o) + 2'b10: n2808_o = 4'b0001; + 2'b01: n2808_o = 4'b0000; + default: n2808_o = 4'b0000; + endcase + assign n2809_o = opc_opcode_q[5]; + /* decoder.vhd:1025:11 */ + always @* + case (n2790_o) + 2'b10: n2810_o = 1'b0; + 2'b01: n2810_o = n2809_o; + default: n2810_o = n2809_o; + endcase + /* decoder.vhd:1025:11 */ + always @* + case (n2790_o) + 2'b10: n2813_o = 1'b1; + 2'b01: n2813_o = 1'b0; + default: n2813_o = 1'b0; + endcase + /* decoder.vhd:1050:27 */ + assign n2815_o = clk_mstate_i == 3'b000; + /* decoder.vhd:1050:37 */ + assign n2816_o = n2815_o & cnd_take_branch_i; + /* decoder.vhd:1050:11 */ + assign n2822_o = n2816_o ? 1'b1 : 1'b0; + /* decoder.vhd:1050:11 */ + assign n2825_o = n2816_o ? 1'b1 : 1'b0; + /* decoder.vhd:1024:9 */ + assign n2827_o = n2784_o ? n2793_o : 1'b0; + /* decoder.vhd:1024:9 */ + assign n2829_o = n2784_o ? n2796_o : 1'b0; + /* decoder.vhd:1024:9 */ + assign n2831_o = n2784_o ? n2799_o : 1'b0; + /* decoder.vhd:1024:9 */ + assign n2833_o = n2784_o ? 1'b0 : n2822_o; + /* decoder.vhd:1024:9 */ + assign n2835_o = n2784_o ? n2802_o : 4'b1100; + /* decoder.vhd:1024:9 */ + assign n2837_o = n2784_o ? n2805_o : 1'b0; + /* decoder.vhd:1024:9 */ + assign n2839_o = n2784_o ? n2808_o : 4'b0000; + assign n2840_o = opc_opcode_q[5]; + /* decoder.vhd:1024:9 */ + assign n2841_o = n2784_o ? n2810_o : n2840_o; + /* decoder.vhd:1024:9 */ + assign n2843_o = n2784_o ? 1'b0 : n2825_o; + /* decoder.vhd:1024:9 */ + assign n2845_o = n2784_o ? n2813_o : 1'b0; + /* decoder.vhd:1021:7 */ + assign n2847_o = opc_mnemonic_s == 6'b010001; + /* decoder.vhd:1058:25 */ + assign n2849_o = clk_mstate_i == 3'b011; + /* decoder.vhd:1059:26 */ + assign n2850_o = opc_opcode_q[4]; + /* decoder.vhd:1059:30 */ + assign n2851_o = ~n2850_o; + /* decoder.vhd:1059:11 */ + assign n2854_o = n2851_o ? 1'b1 : 1'b0; + /* decoder.vhd:1059:11 */ + assign n2857_o = n2851_o ? 1'b0 : 1'b1; + /* decoder.vhd:1058:9 */ + assign n2859_o = n2849_o ? n2854_o : 1'b0; + /* decoder.vhd:1058:9 */ + assign n2861_o = n2849_o ? n2857_o : 1'b0; + /* decoder.vhd:1057:7 */ + assign n2863_o = opc_mnemonic_s == 6'b111110; + /* decoder.vhd:1068:25 */ + assign n2865_o = clk_mstate_i == 3'b010; + /* decoder.vhd:1068:9 */ + assign n2868_o = n2865_o ? 1'b1 : 1'b0; + /* decoder.vhd:1067:7 */ + assign n2870_o = opc_mnemonic_s == 6'b010010; + /* decoder.vhd:1075:48 */ + assign n2872_o = clk_mstate_i == 3'b001; + /* decoder.vhd:1075:31 */ + assign n2873_o = clk_second_cycle_i & n2872_o; + /* decoder.vhd:1078:26 */ + assign n2874_o = opc_opcode_q[1]; + /* decoder.vhd:1078:30 */ + assign n2875_o = ~n2874_o; + /* decoder.vhd:1078:11 */ + assign n2878_o = n2875_o ? 1'b1 : 1'b0; + /* decoder.vhd:1078:11 */ + assign n2881_o = n2875_o ? 1'b0 : 1'b1; + /* decoder.vhd:1075:9 */ + assign n2884_o = n2873_o ? 1'b1 : 1'b0; + /* decoder.vhd:1075:9 */ + assign n2886_o = n2873_o ? n2878_o : 1'b0; + /* decoder.vhd:1075:9 */ + assign n2888_o = n2873_o ? n2881_o : 1'b0; + /* decoder.vhd:1073:7 */ + assign n2890_o = opc_mnemonic_s == 6'b010011; + /* decoder.vhd:1088:25 */ + assign n2892_o = clk_mstate_i == 3'b011; + /* decoder.vhd:1088:9 */ + assign n2895_o = n2892_o ? 1'b1 : 1'b0; + /* decoder.vhd:1088:9 */ + assign n2898_o = n2892_o ? 1'b1 : 1'b0; + /* decoder.vhd:1086:7 */ + assign n2900_o = opc_mnemonic_s == 6'b111010; + /* decoder.vhd:1099:48 */ + assign n2902_o = clk_mstate_i == 3'b001; + /* decoder.vhd:1099:31 */ + assign n2903_o = clk_second_cycle_i & n2902_o; + /* decoder.vhd:1099:9 */ + assign n2906_o = n2903_o ? 1'b1 : 1'b0; + /* decoder.vhd:1099:9 */ + assign n2909_o = n2903_o ? 1'b1 : 1'b0; + /* decoder.vhd:1095:7 */ + assign n2911_o = opc_mnemonic_s == 6'b010101; + /* decoder.vhd:1111:28 */ + assign n2912_o = opc_opcode_q[3]; + /* decoder.vhd:1111:32 */ + assign n2913_o = ~n2912_o; + /* decoder.vhd:1110:44 */ + assign n2915_o = 1'b0 | n2913_o; + /* decoder.vhd:1110:13 */ + assign n2922_o = n2915_o ? 1'b1 : n2156_o; + /* decoder.vhd:1110:13 */ + assign n2925_o = n2915_o ? 1'b1 : 1'b0; + /* decoder.vhd:1110:13 */ + assign n2928_o = n2915_o ? 2'b00 : 2'b01; + /* decoder.vhd:1109:11 */ + assign n2930_o = clk_mstate_i == 3'b010; + /* decoder.vhd:1117:28 */ + assign n2931_o = opc_opcode_q[3:2]; + /* decoder.vhd:1117:41 */ + assign n2933_o = n2931_o != 2'b01; + /* decoder.vhd:1117:13 */ + assign n2936_o = n2933_o ? 1'b1 : 1'b0; + /* decoder.vhd:1117:13 */ + assign n2939_o = n2933_o ? 1'b1 : 1'b0; + /* decoder.vhd:1115:11 */ + assign n2941_o = clk_mstate_i == 3'b011; + /* decoder.vhd:1126:28 */ + assign n2942_o = opc_opcode_q[3:2]; + /* decoder.vhd:1126:41 */ + assign n2944_o = n2942_o == 2'b01; + /* decoder.vhd:1126:13 */ + assign n2947_o = n2944_o ? 1'b1 : 1'b0; + /* decoder.vhd:1126:13 */ + assign n2950_o = n2944_o ? 1'b0 : 1'b1; + /* decoder.vhd:1122:11 */ + assign n2952_o = clk_mstate_i == 3'b100; + assign n2953_o = {n2952_o, n2941_o, n2930_o}; + /* decoder.vhd:1107:9 */ + always @* + case (n2953_o) + 3'b100: n2955_o = n2947_o; + 3'b010: n2955_o = 1'b0; + 3'b001: n2955_o = 1'b0; + default: n2955_o = 1'b0; + endcase + /* decoder.vhd:1107:9 */ + always @* + case (n2953_o) + 3'b100: n2957_o = 1'b0; + 3'b010: n2957_o = n2936_o; + 3'b001: n2957_o = 1'b0; + default: n2957_o = 1'b0; + endcase + /* decoder.vhd:1107:9 */ + always @* + case (n2953_o) + 3'b100: n2960_o = 1'b1; + 3'b010: n2960_o = 1'b0; + 3'b001: n2960_o = 1'b0; + default: n2960_o = 1'b0; + endcase + /* decoder.vhd:1107:9 */ + always @* + case (n2953_o) + 3'b100: n2961_o = n2156_o; + 3'b010: n2961_o = n2156_o; + 3'b001: n2961_o = n2922_o; + default: n2961_o = n2156_o; + endcase + /* decoder.vhd:1107:9 */ + always @* + case (n2953_o) + 3'b100: n2963_o = 1'b0; + 3'b010: n2963_o = n2939_o; + 3'b001: n2963_o = n2925_o; + default: n2963_o = 1'b0; + endcase + /* decoder.vhd:1107:9 */ + always @* + case (n2953_o) + 3'b100: n2966_o = 4'b1001; + 3'b010: n2966_o = 4'b1100; + 3'b001: n2966_o = 4'b1100; + default: n2966_o = 4'b1100; + endcase + /* decoder.vhd:1107:9 */ + always @* + case (n2953_o) + 3'b100: n2968_o = 2'b01; + 3'b010: n2968_o = 2'b01; + 3'b001: n2968_o = n2928_o; + default: n2968_o = 2'b01; + endcase + /* decoder.vhd:1107:9 */ + always @* + case (n2953_o) + 3'b100: n2970_o = n2950_o; + 3'b010: n2970_o = 1'b0; + 3'b001: n2970_o = 1'b0; + default: n2970_o = 1'b0; + endcase + /* decoder.vhd:1106:7 */ + assign n2972_o = opc_mnemonic_s == 6'b010100; + /* decoder.vhd:1144:12 */ + assign n2973_o = ~clk_second_cycle_i; + /* decoder.vhd:1146:27 */ + assign n2975_o = clk_mstate_i == 3'b010; + /* decoder.vhd:1146:11 */ + assign n2978_o = n2975_o ? 1'b1 : 1'b0; + /* decoder.vhd:1146:11 */ + assign n2981_o = n2975_o ? 1'b1 : 1'b0; + /* decoder.vhd:1155:27 */ + assign n2983_o = clk_mstate_i == 3'b000; + /* decoder.vhd:1155:37 */ + assign n2984_o = n2983_o & cnd_take_branch_i; + /* decoder.vhd:1155:11 */ + assign n2990_o = n2984_o ? 1'b1 : 1'b0; + /* decoder.vhd:1155:11 */ + assign n2993_o = n2984_o ? 1'b1 : 1'b0; + /* decoder.vhd:1144:9 */ + assign n2995_o = n2973_o ? n2978_o : 1'b0; + /* decoder.vhd:1144:9 */ + assign n2997_o = n2973_o ? 1'b0 : n2990_o; + /* decoder.vhd:1144:9 */ + assign n2999_o = n2973_o ? n2981_o : 1'b0; + /* decoder.vhd:1144:9 */ + assign n3001_o = n2973_o ? 1'b0 : n2993_o; + /* decoder.vhd:1140:7 */ + assign n3003_o = opc_mnemonic_s == 6'b010110; + /* decoder.vhd:1166:12 */ + assign n3004_o = ~clk_second_cycle_i; + /* decoder.vhd:1168:27 */ + assign n3006_o = clk_mstate_i == 3'b010; + /* decoder.vhd:1170:48 */ + assign n3007_o = opc_opcode_q[4]; + /* decoder.vhd:1168:11 */ + assign n3010_o = n3006_o ? 1'b1 : 1'b0; + assign n3011_o = opc_opcode_q[5]; + /* decoder.vhd:1166:9 */ + assign n3012_o = n3030_o ? n3007_o : n3011_o; + /* decoder.vhd:1176:27 */ + assign n3014_o = clk_mstate_i == 3'b000; + /* decoder.vhd:1176:37 */ + assign n3015_o = n3014_o & cnd_take_branch_i; + /* decoder.vhd:1176:11 */ + assign n3021_o = n3015_o ? 1'b1 : 1'b0; + /* decoder.vhd:1176:11 */ + assign n3024_o = n3015_o ? 1'b1 : 1'b0; + /* decoder.vhd:1166:9 */ + assign n3026_o = n3004_o ? 1'b0 : n3021_o; + /* decoder.vhd:1166:9 */ + assign n3028_o = n3004_o ? n3010_o : 1'b0; + /* decoder.vhd:1166:9 */ + assign n3030_o = n3004_o & n3006_o; + /* decoder.vhd:1166:9 */ + assign n3032_o = n3004_o ? 1'b0 : n3024_o; + /* decoder.vhd:1162:7 */ + assign n3034_o = opc_mnemonic_s == 6'b010111; + /* decoder.vhd:1186:12 */ + assign n3035_o = ~clk_second_cycle_i; + /* decoder.vhd:1188:27 */ + assign n3037_o = clk_mstate_i == 3'b010; + /* decoder.vhd:1190:28 */ + assign n3038_o = opc_opcode_q[7]; + /* decoder.vhd:1190:13 */ + assign n3041_o = n3038_o ? 4'b0011 : 4'b0100; + /* decoder.vhd:1188:11 */ + assign n3044_o = n3037_o ? 1'b1 : 1'b0; + /* decoder.vhd:1188:11 */ + assign n3046_o = n3037_o ? n3041_o : 4'b0000; + /* decoder.vhd:1203:27 */ + assign n3048_o = clk_mstate_i == 3'b000; + /* decoder.vhd:1203:37 */ + assign n3049_o = n3048_o & cnd_take_branch_i; + /* decoder.vhd:1203:11 */ + assign n3055_o = n3049_o ? 1'b1 : 1'b0; + /* decoder.vhd:1203:11 */ + assign n3058_o = n3049_o ? 1'b1 : 1'b0; + /* decoder.vhd:1186:9 */ + assign n3060_o = n3035_o ? 1'b0 : n3055_o; + /* decoder.vhd:1186:9 */ + assign n3062_o = n3035_o ? n3044_o : 1'b0; + /* decoder.vhd:1186:9 */ + assign n3064_o = n3035_o ? n3046_o : 4'b0000; + /* decoder.vhd:1186:9 */ + assign n3066_o = n3035_o ? 1'b0 : n3058_o; + /* decoder.vhd:1183:7 */ + assign n3068_o = opc_mnemonic_s == 6'b011000; + /* decoder.vhd:1217:13 */ + assign n3070_o = clk_mstate_i == 3'b000; + /* decoder.vhd:1223:40 */ + assign n3072_o = {4'b0000, n2141_o}; + /* decoder.vhd:1223:61 */ + assign n3073_o = opc_opcode_q[7:5]; + /* decoder.vhd:1223:47 */ + assign n3074_o = {n3072_o, n3073_o}; + /* decoder.vhd:1222:13 */ + assign n3076_o = clk_mstate_i == 3'b001; + assign n3077_o = {n3076_o, n3070_o}; + /* decoder.vhd:1215:11 */ + always @* + case (n3077_o) + 2'b10: n3080_o = 1'b0; + 2'b01: n3080_o = 1'b1; + default: n3080_o = 1'b0; + endcase + /* decoder.vhd:1215:11 */ + always @* + case (n3077_o) + 2'b10: n3083_o = 1'b1; + 2'b01: n3083_o = 1'b0; + default: n3083_o = 1'b0; + endcase + /* decoder.vhd:1215:11 */ + always @* + case (n3077_o) + 2'b10: n3086_o = 1'b0; + 2'b01: n3086_o = 1'b1; + default: n3086_o = 1'b0; + endcase + /* decoder.vhd:1215:11 */ + always @* + case (n3077_o) + 2'b10: n3087_o = n3074_o; + 2'b01: n3087_o = n2160_o; + default: n3087_o = n2160_o; + endcase + /* decoder.vhd:1215:11 */ + always @* + case (n3077_o) + 2'b10: n3089_o = 1'b1; + 2'b01: n3089_o = n2164_o; + default: n3089_o = n2164_o; + endcase + /* decoder.vhd:1214:9 */ + assign n3091_o = clk_second_cycle_i ? n3080_o : 1'b0; + /* decoder.vhd:1214:9 */ + assign n3093_o = clk_second_cycle_i ? n3083_o : 1'b0; + /* decoder.vhd:1214:9 */ + assign n3095_o = clk_second_cycle_i ? n3086_o : 1'b0; + /* decoder.vhd:1214:9 */ + assign n3096_o = clk_second_cycle_i ? n3087_o : n2160_o; + /* decoder.vhd:1214:9 */ + assign n3097_o = clk_second_cycle_i ? n3089_o : n2164_o; + /* decoder.vhd:1211:7 */ + assign n3099_o = opc_mnemonic_s == 6'b011001; + /* decoder.vhd:1238:12 */ + assign n3100_o = ~clk_second_cycle_i; + /* decoder.vhd:1241:27 */ + assign n3102_o = clk_mstate_i == 3'b010; + /* decoder.vhd:1241:11 */ + assign n3105_o = n3102_o ? 1'b1 : 1'b0; + /* decoder.vhd:1241:11 */ + assign n3108_o = n3102_o ? 2'b01 : 2'b00; + /* decoder.vhd:1247:27 */ + assign n3110_o = clk_mstate_i == 3'b000; + /* decoder.vhd:1247:11 */ + assign n3113_o = n3110_o ? 1'b1 : 1'b0; + /* decoder.vhd:1247:11 */ + assign n3116_o = n3110_o ? 1'b1 : 1'b0; + /* decoder.vhd:1238:9 */ + assign n3118_o = n3100_o ? n3105_o : 1'b0; + /* decoder.vhd:1238:9 */ + assign n3120_o = n3100_o ? 1'b0 : n3113_o; + /* decoder.vhd:1238:9 */ + assign n3122_o = n3100_o ? n3108_o : 2'b00; + /* decoder.vhd:1238:9 */ + assign n3124_o = n3100_o ? 1'b0 : n3116_o; + /* decoder.vhd:1235:7 */ + assign n3126_o = opc_mnemonic_s == 6'b011010; + /* decoder.vhd:1260:12 */ + assign n3127_o = ~clk_second_cycle_i; + /* decoder.vhd:1262:27 */ + assign n3129_o = clk_mstate_i == 3'b010; + /* decoder.vhd:1262:11 */ + assign n3132_o = n3129_o ? 1'b1 : 1'b0; + /* decoder.vhd:1269:27 */ + assign n3134_o = clk_mstate_i == 3'b000; + /* decoder.vhd:1269:37 */ + assign n3135_o = n3134_o & cnd_take_branch_i; + /* decoder.vhd:1269:11 */ + assign n3141_o = n3135_o ? 1'b1 : 1'b0; + /* decoder.vhd:1269:11 */ + assign n3144_o = n3135_o ? 1'b1 : 1'b0; + /* decoder.vhd:1260:9 */ + assign n3146_o = n3127_o ? 1'b0 : n3141_o; + /* decoder.vhd:1260:9 */ + assign n3148_o = n3127_o ? n3132_o : 1'b0; + /* decoder.vhd:1260:9 */ + assign n3150_o = n3127_o ? 1'b0 : n3144_o; + /* decoder.vhd:1256:7 */ + assign n3152_o = opc_mnemonic_s == 6'b011011; + /* decoder.vhd:1280:12 */ + assign n3153_o = ~clk_second_cycle_i; + /* decoder.vhd:1282:27 */ + assign n3155_o = clk_mstate_i == 3'b010; + /* decoder.vhd:1282:11 */ + assign n3158_o = n3155_o ? 1'b1 : 1'b0; + /* decoder.vhd:1289:27 */ + assign n3160_o = clk_mstate_i == 3'b000; + /* decoder.vhd:1289:37 */ + assign n3161_o = n3160_o & cnd_take_branch_i; + /* decoder.vhd:1289:11 */ + assign n3167_o = n3161_o ? 1'b1 : 1'b0; + /* decoder.vhd:1289:11 */ + assign n3170_o = n3161_o ? 1'b1 : 1'b0; + /* decoder.vhd:1280:9 */ + assign n3172_o = n3153_o ? 1'b0 : n3167_o; + /* decoder.vhd:1280:9 */ + assign n3174_o = n3153_o ? n3158_o : 1'b0; + /* decoder.vhd:1280:9 */ + assign n3176_o = n3153_o ? 1'b0 : n3170_o; + /* decoder.vhd:1276:7 */ + assign n3178_o = opc_mnemonic_s == 6'b111100; + /* decoder.vhd:1300:12 */ + assign n3179_o = ~clk_second_cycle_i; + /* decoder.vhd:1302:27 */ + assign n3181_o = clk_mstate_i == 3'b010; + /* decoder.vhd:1302:11 */ + assign n3184_o = n3181_o ? 1'b1 : 1'b0; + /* decoder.vhd:1309:27 */ + assign n3186_o = clk_mstate_i == 3'b000; + /* decoder.vhd:1309:37 */ + assign n3187_o = n3186_o & cnd_take_branch_i; + /* decoder.vhd:1309:11 */ + assign n3193_o = n3187_o ? 1'b1 : 1'b0; + /* decoder.vhd:1309:11 */ + assign n3196_o = n3187_o ? 1'b1 : 1'b0; + /* decoder.vhd:1300:9 */ + assign n3198_o = n3179_o ? 1'b0 : n3193_o; + /* decoder.vhd:1300:9 */ + assign n3200_o = n3179_o ? n3184_o : 1'b0; + /* decoder.vhd:1300:9 */ + assign n3202_o = n3179_o ? 1'b0 : n3196_o; + /* decoder.vhd:1296:7 */ + assign n3204_o = opc_mnemonic_s == 6'b111101; + /* decoder.vhd:1318:24 */ + assign n3205_o = opc_opcode_q[6]; + /* decoder.vhd:1318:28 */ + assign n3206_o = ~n3205_o; + /* decoder.vhd:1318:9 */ + assign n3209_o = n3206_o ? 4'b0110 : 4'b0111; + /* decoder.vhd:1324:12 */ + assign n3210_o = ~clk_second_cycle_i; + /* decoder.vhd:1326:27 */ + assign n3212_o = clk_mstate_i == 3'b010; + /* decoder.vhd:1328:48 */ + assign n3213_o = opc_opcode_q[4]; + /* decoder.vhd:1326:11 */ + assign n3216_o = n3212_o ? 1'b1 : 1'b0; + assign n3217_o = opc_opcode_q[5]; + /* decoder.vhd:1324:9 */ + assign n3218_o = n3236_o ? n3213_o : n3217_o; + /* decoder.vhd:1334:27 */ + assign n3220_o = clk_mstate_i == 3'b000; + /* decoder.vhd:1334:37 */ + assign n3221_o = n3220_o & cnd_take_branch_i; + /* decoder.vhd:1334:11 */ + assign n3227_o = n3221_o ? 1'b1 : 1'b0; + /* decoder.vhd:1334:11 */ + assign n3230_o = n3221_o ? 1'b1 : 1'b0; + /* decoder.vhd:1324:9 */ + assign n3232_o = n3210_o ? 1'b0 : n3227_o; + /* decoder.vhd:1324:9 */ + assign n3234_o = n3210_o ? n3216_o : 1'b0; + /* decoder.vhd:1324:9 */ + assign n3236_o = n3210_o & n3212_o; + /* decoder.vhd:1324:9 */ + assign n3238_o = n3210_o ? 1'b0 : n3230_o; + /* decoder.vhd:1316:7 */ + assign n3240_o = opc_mnemonic_s == 6'b011100; + /* decoder.vhd:1345:12 */ + assign n3241_o = ~clk_second_cycle_i; + /* decoder.vhd:1347:27 */ + assign n3243_o = clk_mstate_i == 3'b010; + /* decoder.vhd:1347:11 */ + assign n3246_o = n3243_o ? 1'b1 : 1'b0; + /* decoder.vhd:1347:11 */ + assign n3249_o = n3243_o ? 1'b1 : 1'b0; + /* decoder.vhd:1355:27 */ + assign n3251_o = clk_mstate_i == 3'b000; + /* decoder.vhd:1355:37 */ + assign n3252_o = n3251_o & cnd_take_branch_i; + /* decoder.vhd:1355:11 */ + assign n3258_o = n3252_o ? 1'b1 : 1'b0; + /* decoder.vhd:1355:11 */ + assign n3261_o = n3252_o ? 1'b1 : 1'b0; + /* decoder.vhd:1345:9 */ + assign n3263_o = n3241_o ? 1'b0 : n3258_o; + /* decoder.vhd:1345:9 */ + assign n3265_o = n3241_o ? n3246_o : 1'b0; + /* decoder.vhd:1345:9 */ + assign n3267_o = n3241_o ? 1'b0 : n3261_o; + /* decoder.vhd:1345:9 */ + assign n3269_o = n3241_o ? n3249_o : 1'b0; + /* decoder.vhd:1341:7 */ + assign n3271_o = opc_mnemonic_s == 6'b011101; + /* decoder.vhd:1366:12 */ + assign n3272_o = ~clk_second_cycle_i; + /* decoder.vhd:1368:27 */ + assign n3274_o = clk_mstate_i == 3'b010; + /* decoder.vhd:1371:48 */ + assign n3275_o = opc_opcode_q[6]; + /* decoder.vhd:1368:11 */ + assign n3278_o = n3274_o ? 1'b1 : 1'b0; + /* decoder.vhd:1368:11 */ + assign n3281_o = n3274_o ? 1'b1 : 1'b0; + assign n3282_o = opc_opcode_q[5]; + /* decoder.vhd:1366:9 */ + assign n3283_o = n3303_o ? n3275_o : n3282_o; + /* decoder.vhd:1377:27 */ + assign n3285_o = clk_mstate_i == 3'b000; + /* decoder.vhd:1377:37 */ + assign n3286_o = n3285_o & cnd_take_branch_i; + /* decoder.vhd:1377:11 */ + assign n3292_o = n3286_o ? 1'b1 : 1'b0; + /* decoder.vhd:1377:11 */ + assign n3295_o = n3286_o ? 1'b1 : 1'b0; + /* decoder.vhd:1366:9 */ + assign n3297_o = n3272_o ? n3278_o : 1'b0; + /* decoder.vhd:1366:9 */ + assign n3299_o = n3272_o ? 1'b0 : n3292_o; + /* decoder.vhd:1366:9 */ + assign n3301_o = n3272_o ? n3281_o : 1'b0; + /* decoder.vhd:1366:9 */ + assign n3303_o = n3272_o & n3274_o; + /* decoder.vhd:1366:9 */ + assign n3305_o = n3272_o ? 1'b0 : n3295_o; + /* decoder.vhd:1362:7 */ + assign n3307_o = opc_mnemonic_s == 6'b011110; + /* decoder.vhd:1389:48 */ + assign n3309_o = clk_mstate_i == 3'b000; + /* decoder.vhd:1389:31 */ + assign n3310_o = clk_second_cycle_i & n3309_o; + /* decoder.vhd:1389:9 */ + assign n3313_o = n3310_o ? 1'b1 : 1'b0; + /* decoder.vhd:1384:7 */ + assign n3315_o = opc_mnemonic_s == 6'b011111; + /* decoder.vhd:1399:28 */ + assign n3316_o = opc_opcode_q[3]; + /* decoder.vhd:1399:32 */ + assign n3317_o = ~n3316_o; + /* decoder.vhd:1398:44 */ + assign n3319_o = 1'b0 | n3317_o; + /* decoder.vhd:1398:13 */ + assign n3326_o = n3319_o ? 1'b1 : n2156_o; + /* decoder.vhd:1398:13 */ + assign n3329_o = n3319_o ? 1'b1 : 1'b0; + /* decoder.vhd:1398:13 */ + assign n3332_o = n3319_o ? 2'b00 : 2'b01; + /* decoder.vhd:1397:11 */ + assign n3334_o = clk_mstate_i == 3'b010; + /* decoder.vhd:1404:11 */ + assign n3339_o = clk_mstate_i == 3'b011; + assign n3340_o = {n3339_o, n3334_o}; + /* decoder.vhd:1395:9 */ + always @* + case (n3340_o) + 2'b10: n3343_o = 1'b1; + 2'b01: n3343_o = 1'b0; + default: n3343_o = 1'b0; + endcase + /* decoder.vhd:1395:9 */ + always @* + case (n3340_o) + 2'b10: n3346_o = 1'b1; + 2'b01: n3346_o = 1'b0; + default: n3346_o = 1'b0; + endcase + /* decoder.vhd:1395:9 */ + always @* + case (n3340_o) + 2'b10: n3347_o = n2156_o; + 2'b01: n3347_o = n3326_o; + default: n3347_o = n2156_o; + endcase + /* decoder.vhd:1395:9 */ + always @* + case (n3340_o) + 2'b10: n3350_o = 1'b1; + 2'b01: n3350_o = n3329_o; + default: n3350_o = 1'b0; + endcase + /* decoder.vhd:1395:9 */ + always @* + case (n3340_o) + 2'b10: n3352_o = 2'b01; + 2'b01: n3352_o = n3332_o; + default: n3352_o = 2'b01; + endcase + /* decoder.vhd:1394:7 */ + assign n3354_o = opc_mnemonic_s == 6'b100001; + /* decoder.vhd:1415:25 */ + assign n3356_o = clk_mstate_i == 3'b010; + /* decoder.vhd:1415:9 */ + assign n3359_o = n3356_o ? 1'b1 : 1'b0; + /* decoder.vhd:1415:9 */ + assign n3362_o = n3356_o ? 1'b1 : 1'b0; + /* decoder.vhd:1415:9 */ + assign n3365_o = n3356_o ? 1'b1 : 1'b0; + /* decoder.vhd:1414:7 */ + assign n3367_o = opc_mnemonic_s == 6'b100000; + /* decoder.vhd:1423:25 */ + assign n3369_o = clk_mstate_i == 3'b010; + /* decoder.vhd:1423:9 */ + assign n3372_o = n3369_o ? 1'b1 : 1'b0; + /* decoder.vhd:1423:9 */ + assign n3375_o = n3369_o ? 1'b1 : 1'b0; + /* decoder.vhd:1423:9 */ + assign n3378_o = n3369_o ? 1'b1 : 1'b0; + /* decoder.vhd:1422:7 */ + assign n3380_o = opc_mnemonic_s == 6'b100010; + /* decoder.vhd:1435:28 */ + assign n3381_o = opc_opcode_q[3]; + /* decoder.vhd:1435:32 */ + assign n3382_o = ~n3381_o; + /* decoder.vhd:1434:44 */ + assign n3384_o = 1'b0 | n3382_o; + /* decoder.vhd:1434:13 */ + assign n3391_o = n3384_o ? 1'b1 : n2156_o; + /* decoder.vhd:1434:13 */ + assign n3394_o = n3384_o ? 1'b1 : 1'b0; + /* decoder.vhd:1434:13 */ + assign n3397_o = n3384_o ? 2'b00 : 2'b01; + /* decoder.vhd:1433:11 */ + assign n3399_o = clk_mstate_i == 3'b010; + /* decoder.vhd:1440:11 */ + assign n3401_o = clk_mstate_i == 3'b100; + assign n3402_o = {n3401_o, n3399_o}; + /* decoder.vhd:1431:9 */ + always @* + case (n3402_o) + 2'b10: n3405_o = 1'b1; + 2'b01: n3405_o = 1'b0; + default: n3405_o = 1'b0; + endcase + /* decoder.vhd:1431:9 */ + always @* + case (n3402_o) + 2'b10: n3406_o = n2156_o; + 2'b01: n3406_o = n3391_o; + default: n3406_o = n2156_o; + endcase + /* decoder.vhd:1431:9 */ + always @* + case (n3402_o) + 2'b10: n3408_o = 1'b0; + 2'b01: n3408_o = n3394_o; + default: n3408_o = 1'b0; + endcase + /* decoder.vhd:1431:9 */ + always @* + case (n3402_o) + 2'b10: n3410_o = 2'b01; + 2'b01: n3410_o = n3397_o; + default: n3410_o = 2'b01; + endcase + /* decoder.vhd:1431:9 */ + always @* + case (n3402_o) + 2'b10: n3413_o = 1'b1; + 2'b01: n3413_o = 1'b0; + default: n3413_o = 1'b0; + endcase + /* decoder.vhd:1430:7 */ + assign n3415_o = opc_mnemonic_s == 6'b100011; + /* decoder.vhd:1454:12 */ + assign n3416_o = ~clk_second_cycle_i; + /* decoder.vhd:1454:52 */ + assign n3418_o = clk_mstate_i == 3'b010; + /* decoder.vhd:1454:35 */ + assign n3419_o = n3416_o & n3418_o; + /* decoder.vhd:1456:26 */ + assign n3420_o = opc_opcode_q[3]; + /* decoder.vhd:1456:30 */ + assign n3421_o = ~n3420_o; + /* decoder.vhd:1455:42 */ + assign n3423_o = 1'b0 | n3421_o; + /* decoder.vhd:1454:9 */ + assign n3430_o = n3437_o ? 1'b1 : n2156_o; + /* decoder.vhd:1455:11 */ + assign n3433_o = n3423_o ? 1'b1 : 1'b0; + /* decoder.vhd:1455:11 */ + assign n3436_o = n3423_o ? 2'b00 : 2'b01; + /* decoder.vhd:1454:9 */ + assign n3437_o = n3419_o & n3423_o; + /* decoder.vhd:1454:9 */ + assign n3439_o = n3419_o ? n3433_o : 1'b0; + /* decoder.vhd:1454:9 */ + assign n3441_o = n3419_o ? n3436_o : 2'b01; + /* decoder.vhd:1463:48 */ + assign n3443_o = clk_mstate_i == 3'b000; + /* decoder.vhd:1463:31 */ + assign n3444_o = clk_second_cycle_i & n3443_o; + /* decoder.vhd:1463:9 */ + assign n3447_o = n3444_o ? 1'b1 : 1'b0; + /* decoder.vhd:1450:7 */ + assign n3449_o = opc_mnemonic_s == 6'b100100; + /* decoder.vhd:1470:25 */ + assign n3451_o = clk_mstate_i == 3'b011; + /* decoder.vhd:1470:9 */ + assign n3454_o = n3451_o ? 1'b1 : 1'b0; + /* decoder.vhd:1470:9 */ + assign n3457_o = n3451_o ? 1'b1 : 1'b0; + /* decoder.vhd:1468:7 */ + assign n3459_o = opc_mnemonic_s == 6'b111111; + /* decoder.vhd:1478:25 */ + assign n3461_o = clk_mstate_i == 3'b010; + /* decoder.vhd:1479:26 */ + assign n3462_o = opc_opcode_q[5]; + /* decoder.vhd:1479:11 */ + assign n3465_o = n3462_o ? 1'b0 : 1'b1; + /* decoder.vhd:1479:11 */ + assign n3468_o = n3462_o ? 1'b1 : 1'b0; + /* decoder.vhd:1479:11 */ + assign n3471_o = n3462_o ? 1'b0 : 1'b1; + /* decoder.vhd:1479:11 */ + assign n3474_o = n3462_o ? 1'b1 : 1'b0; + /* decoder.vhd:1478:9 */ + assign n3476_o = n3461_o ? n3465_o : 1'b0; + /* decoder.vhd:1478:9 */ + assign n3478_o = n3461_o ? n3468_o : 1'b0; + /* decoder.vhd:1478:9 */ + assign n3480_o = n3461_o ? n3471_o : 1'b0; + /* decoder.vhd:1478:9 */ + assign n3482_o = n3461_o ? n3474_o : 1'b0; + /* decoder.vhd:1477:7 */ + assign n3484_o = opc_mnemonic_s == 6'b100101; + /* decoder.vhd:1492:12 */ + assign n3485_o = ~clk_second_cycle_i; + /* decoder.vhd:1498:53 */ + assign n3487_o = opc_opcode_q[1:0]; + /* decoder.vhd:1500:32 */ + assign n3488_o = opc_opcode_q[7:4]; + /* decoder.vhd:1501:17 */ + assign n3491_o = n3488_o == 4'b1001; + /* decoder.vhd:1503:17 */ + assign n3494_o = n3488_o == 4'b1000; + /* decoder.vhd:1505:17 */ + assign n3497_o = n3488_o == 4'b0011; + assign n3498_o = {n3497_o, n3494_o, n3491_o}; + assign n3499_o = n2158_o[3:2]; + assign n3500_o = n2159_o[3:2]; + /* decoder.vhd:622:5 */ + assign n3501_o = n2145_o ? n3499_o : n3500_o; + /* decoder.vhd:1500:15 */ + always @* + case (n3498_o) + 3'b100: n3502_o = 2'b01; + 3'b010: n3502_o = 2'b10; + 3'b001: n3502_o = 2'b11; + default: n3502_o = n3501_o; + endcase + /* decoder.vhd:1495:13 */ + assign n3504_o = clk_mstate_i == 3'b010; + /* decoder.vhd:1516:13 */ + assign n3506_o = clk_mstate_i == 3'b011; + /* decoder.vhd:1522:13 */ + assign n3508_o = clk_mstate_i == 3'b100; + assign n3509_o = {n3508_o, n3506_o, n3504_o}; + /* decoder.vhd:1493:11 */ + always @* + case (n3509_o) + 3'b100: n3512_o = 1'b0; + 3'b010: n3512_o = 1'b1; + 3'b001: n3512_o = 1'b0; + default: n3512_o = 1'b0; + endcase + /* decoder.vhd:1493:11 */ + always @* + case (n3509_o) + 3'b100: n3516_o = 1'b0; + 3'b010: n3516_o = 1'b1; + 3'b001: n3516_o = 1'b1; + default: n3516_o = 1'b0; + endcase + assign n3517_o = n2158_o[1:0]; + assign n3518_o = n2159_o[1:0]; + /* decoder.vhd:622:5 */ + assign n3519_o = n2145_o ? n3517_o : n3518_o; + /* decoder.vhd:1493:11 */ + always @* + case (n3509_o) + 3'b100: n3520_o = n3519_o; + 3'b010: n3520_o = n3519_o; + 3'b001: n3520_o = n3487_o; + default: n3520_o = n3519_o; + endcase + assign n3521_o = n2158_o[3:2]; + assign n3522_o = n2159_o[3:2]; + /* decoder.vhd:622:5 */ + assign n3523_o = n2145_o ? n3521_o : n3522_o; + /* decoder.vhd:1493:11 */ + always @* + case (n3509_o) + 3'b100: n3524_o = n3523_o; + 3'b010: n3524_o = n3523_o; + 3'b001: n3524_o = n3502_o; + default: n3524_o = n3523_o; + endcase + assign n3525_o = n2158_o[7:4]; + assign n3526_o = n2159_o[7:4]; + /* decoder.vhd:622:5 */ + assign n3527_o = n2145_o ? n3525_o : n3526_o; + /* decoder.vhd:1493:11 */ + always @* + case (n3509_o) + 3'b100: n3528_o = n3527_o; + 3'b010: n3528_o = n3527_o; + 3'b001: n3528_o = 4'b0000; + default: n3528_o = n3527_o; + endcase + /* decoder.vhd:1493:11 */ + always @* + case (n3509_o) + 3'b100: n3530_o = n2164_o; + 3'b010: n3530_o = n2164_o; + 3'b001: n3530_o = 1'b1; + default: n3530_o = n2164_o; + endcase + /* decoder.vhd:1493:11 */ + always @* + case (n3509_o) + 3'b100: n3534_o = 1'b1; + 3'b010: n3534_o = 1'b1; + 3'b001: n3534_o = 1'b0; + default: n3534_o = 1'b0; + endcase + /* decoder.vhd:1532:27 */ + assign n3536_o = clk_mstate_i == 3'b000; + /* decoder.vhd:1532:53 */ + assign n3538_o = clk_mstate_i == 3'b001; + /* decoder.vhd:1532:37 */ + assign n3539_o = n3536_o | n3538_o; + /* decoder.vhd:1532:11 */ + assign n3542_o = n3539_o ? 1'b1 : 1'b0; + /* decoder.vhd:1492:9 */ + assign n3544_o = n3485_o ? n3512_o : 1'b0; + /* decoder.vhd:1492:9 */ + assign n3546_o = n3485_o ? n3516_o : 1'b0; + assign n3547_o = {n3528_o, n3524_o, n3520_o}; + /* decoder.vhd:1492:9 */ + assign n3548_o = n3485_o ? n3547_o : n2160_o; + /* decoder.vhd:1492:9 */ + assign n3549_o = n3485_o ? n3530_o : n2164_o; + /* decoder.vhd:1492:9 */ + assign n3550_o = n3485_o ? n3534_o : n3542_o; + /* decoder.vhd:1489:7 */ + assign n3552_o = opc_mnemonic_s == 6'b101101; + /* decoder.vhd:1542:12 */ + assign n3553_o = ~clk_second_cycle_i; + /* decoder.vhd:1548:53 */ + assign n3554_o = opc_opcode_q[1:0]; + /* decoder.vhd:1547:48 */ + assign n3556_o = {6'b000000, n3554_o}; + /* decoder.vhd:1545:13 */ + assign n3558_o = clk_mstate_i == 3'b010; + /* decoder.vhd:1554:13 */ + assign n3561_o = clk_mstate_i == 3'b011; + /* decoder.vhd:1561:13 */ + assign n3563_o = clk_mstate_i == 3'b100; + assign n3564_o = {n3563_o, n3561_o, n3558_o}; + /* decoder.vhd:1543:11 */ + always @* + case (n3564_o) + 3'b100: n3568_o = 1'b0; + 3'b010: n3568_o = 1'b1; + 3'b001: n3568_o = 1'b1; + default: n3568_o = 1'b0; + endcase + assign n3569_o = n3556_o[3:0]; + assign n3570_o = n2158_o[3:0]; + assign n3571_o = n2159_o[3:0]; + /* decoder.vhd:622:5 */ + assign n3572_o = n2145_o ? n3570_o : n3571_o; + /* decoder.vhd:1543:11 */ + always @* + case (n3564_o) + 3'b100: n3573_o = n3572_o; + 3'b010: n3573_o = 4'b1111; + 3'b001: n3573_o = n3569_o; + default: n3573_o = n3572_o; + endcase + assign n3574_o = n3556_o[7:4]; + assign n3575_o = n2158_o[7:4]; + assign n3576_o = n2159_o[7:4]; + /* decoder.vhd:622:5 */ + assign n3577_o = n2145_o ? n3575_o : n3576_o; + /* decoder.vhd:1543:11 */ + always @* + case (n3564_o) + 3'b100: n3578_o = n3577_o; + 3'b010: n3578_o = n3577_o; + 3'b001: n3578_o = n3574_o; + default: n3578_o = n3577_o; + endcase + /* decoder.vhd:1543:11 */ + always @* + case (n3564_o) + 3'b100: n3581_o = n2164_o; + 3'b010: n3581_o = 1'b1; + 3'b001: n3581_o = 1'b1; + default: n3581_o = n2164_o; + endcase + /* decoder.vhd:1543:11 */ + always @* + case (n3564_o) + 3'b100: n3585_o = 1'b1; + 3'b010: n3585_o = 1'b1; + 3'b001: n3585_o = 1'b0; + default: n3585_o = 1'b0; + endcase + /* decoder.vhd:1572:13 */ + assign n3587_o = clk_mstate_i == 3'b000; + /* decoder.vhd:1577:13 */ + assign n3589_o = clk_mstate_i == 3'b001; + assign n3590_o = {n3589_o, n3587_o}; + /* decoder.vhd:1570:11 */ + always @* + case (n3590_o) + 2'b10: n3593_o = 1'b1; + 2'b01: n3593_o = 1'b0; + default: n3593_o = 1'b0; + endcase + /* decoder.vhd:1570:11 */ + always @* + case (n3590_o) + 2'b10: n3596_o = 1'b1; + 2'b01: n3596_o = 1'b0; + default: n3596_o = 1'b0; + endcase + /* decoder.vhd:1570:11 */ + always @* + case (n3590_o) + 2'b10: n3599_o = 1'b1; + 2'b01: n3599_o = 1'b0; + default: n3599_o = 1'b0; + endcase + /* decoder.vhd:1570:11 */ + always @* + case (n3590_o) + 2'b10: n3603_o = 1'b1; + 2'b01: n3603_o = 1'b1; + default: n3603_o = 1'b0; + endcase + /* decoder.vhd:1542:9 */ + assign n3605_o = n3553_o ? 1'b0 : n3593_o; + /* decoder.vhd:1542:9 */ + assign n3607_o = n3553_o ? n3568_o : 1'b0; + /* decoder.vhd:1542:9 */ + assign n3609_o = n3553_o ? 1'b0 : n3596_o; + /* decoder.vhd:1542:9 */ + assign n3611_o = n3553_o ? 1'b0 : n3599_o; + assign n3612_o = {n3578_o, n3573_o}; + /* decoder.vhd:1542:9 */ + assign n3613_o = n3553_o ? n3612_o : n2160_o; + /* decoder.vhd:1542:9 */ + assign n3614_o = n3553_o ? n3581_o : n2164_o; + /* decoder.vhd:1542:9 */ + assign n3615_o = n3553_o ? n3585_o : n3603_o; + /* decoder.vhd:1539:7 */ + assign n3617_o = opc_mnemonic_s == 6'b100110; + /* decoder.vhd:1594:12 */ + assign n3618_o = ~clk_second_cycle_i; + /* decoder.vhd:1597:27 */ + assign n3620_o = clk_mstate_i == 3'b010; + /* decoder.vhd:1599:28 */ + assign n3621_o = opc_opcode_q[6]; + /* decoder.vhd:1599:32 */ + assign n3622_o = ~n3621_o; + /* decoder.vhd:1599:13 */ + assign n3625_o = n3622_o ? 2'b01 : 2'b10; + /* decoder.vhd:1597:11 */ + assign n3628_o = n3620_o ? 1'b1 : 1'b0; + /* decoder.vhd:1597:11 */ + assign n3630_o = n3620_o ? n3625_o : 2'b00; + /* decoder.vhd:1607:27 */ + assign n3632_o = clk_mstate_i == 3'b000; + /* decoder.vhd:1607:11 */ + assign n3635_o = n3632_o ? 1'b1 : 1'b0; + /* decoder.vhd:1607:11 */ + assign n3638_o = n3632_o ? 1'b1 : 1'b0; + /* decoder.vhd:1594:9 */ + assign n3640_o = n3618_o ? 1'b0 : n3635_o; + /* decoder.vhd:1594:9 */ + assign n3642_o = n3618_o ? n3628_o : 1'b0; + /* decoder.vhd:1594:9 */ + assign n3644_o = n3618_o ? n3630_o : 2'b00; + /* decoder.vhd:1594:9 */ + assign n3646_o = n3618_o ? 1'b0 : n3638_o; + /* decoder.vhd:1591:7 */ + assign n3648_o = opc_mnemonic_s == 6'b100111; + /* decoder.vhd:1621:24 */ + assign n3649_o = opc_opcode_q[4]; + /* decoder.vhd:1621:28 */ + assign n3650_o = ~n3649_o; + /* decoder.vhd:1621:9 */ + assign n3653_o = n3650_o ? 1'b1 : 1'b0; + /* decoder.vhd:1621:9 */ + assign n3656_o = n3650_o ? 1'b0 : 1'b1; + /* decoder.vhd:1627:12 */ + assign n3657_o = ~clk_second_cycle_i; + /* decoder.vhd:1631:13 */ + assign n3659_o = clk_mstate_i == 3'b010; + /* decoder.vhd:1637:30 */ + assign n3660_o = opc_opcode_q[4]; + /* decoder.vhd:1637:15 */ + assign n3663_o = n3660_o ? 1'b1 : 1'b0; + /* decoder.vhd:1637:15 */ + assign n3666_o = n3660_o ? 1'b1 : 1'b0; + /* decoder.vhd:1636:13 */ + assign n3668_o = clk_mstate_i == 3'b100; + assign n3669_o = {n3668_o, n3659_o}; + /* decoder.vhd:1629:11 */ + always @* + case (n3669_o) + 2'b10: n3671_o = n3663_o; + 2'b01: n3671_o = 1'b0; + default: n3671_o = 1'b0; + endcase + /* decoder.vhd:1629:11 */ + always @* + case (n3669_o) + 2'b10: n3674_o = n3666_o; + 2'b01: n3674_o = 1'b1; + default: n3674_o = 1'b0; + endcase + /* decoder.vhd:1629:11 */ + always @* + case (n3669_o) + 2'b10: n3677_o = 1'b0; + 2'b01: n3677_o = 1'b1; + default: n3677_o = 1'b0; + endcase + /* decoder.vhd:1647:27 */ + assign n3679_o = clk_mstate_i == 3'b001; + /* decoder.vhd:1648:28 */ + assign n3680_o = opc_opcode_q[4]; + /* decoder.vhd:1648:32 */ + assign n3681_o = ~n3680_o; + /* decoder.vhd:1648:13 */ + assign n3684_o = n3681_o ? 1'b1 : 1'b0; + /* decoder.vhd:1648:13 */ + assign n3687_o = n3681_o ? 1'b0 : 1'b1; + /* decoder.vhd:1648:13 */ + assign n3690_o = n3681_o ? 1'b0 : 1'b1; + /* decoder.vhd:1648:13 */ + assign n3693_o = n3681_o ? 1'b1 : 1'b0; + /* decoder.vhd:1647:11 */ + assign n3695_o = n3679_o ? n3684_o : 1'b0; + /* decoder.vhd:1647:11 */ + assign n3697_o = n3679_o ? n3687_o : 1'b0; + /* decoder.vhd:1647:11 */ + assign n3699_o = n3679_o ? n3690_o : 1'b0; + /* decoder.vhd:1647:11 */ + assign n3701_o = n3679_o ? n3693_o : 1'b0; + /* decoder.vhd:1627:9 */ + assign n3703_o = n3657_o ? 1'b0 : n3695_o; + /* decoder.vhd:1627:9 */ + assign n3704_o = n3657_o ? n3671_o : n3697_o; + /* decoder.vhd:1627:9 */ + assign n3705_o = n3657_o ? n3674_o : n3699_o; + /* decoder.vhd:1627:9 */ + assign n3707_o = n3657_o ? n3677_o : 1'b0; + /* decoder.vhd:1627:9 */ + assign n3709_o = n3657_o ? 1'b0 : n3701_o; + /* decoder.vhd:1627:9 */ + assign n3712_o = n3657_o ? 1'b1 : 1'b0; + /* decoder.vhd:1618:7 */ + assign n3714_o = opc_mnemonic_s == 6'b101000; + /* decoder.vhd:1663:7 */ + assign n3716_o = opc_mnemonic_s == 6'b101001; + /* decoder.vhd:1672:28 */ + assign n3717_o = opc_opcode_q[3]; + /* decoder.vhd:1672:32 */ + assign n3718_o = ~n3717_o; + /* decoder.vhd:1671:44 */ + assign n3720_o = 1'b0 | n3718_o; + /* decoder.vhd:1671:13 */ + assign n3727_o = n3720_o ? 1'b1 : n2156_o; + /* decoder.vhd:1671:13 */ + assign n3730_o = n3720_o ? 1'b1 : 1'b0; + /* decoder.vhd:1671:13 */ + assign n3733_o = n3720_o ? 2'b00 : 2'b01; + /* decoder.vhd:1670:11 */ + assign n3735_o = clk_mstate_i == 3'b010; + /* decoder.vhd:1677:11 */ + assign n3740_o = clk_mstate_i == 3'b011; + /* decoder.vhd:1681:11 */ + assign n3745_o = clk_mstate_i == 3'b100; + assign n3746_o = {n3745_o, n3740_o, n3735_o}; + /* decoder.vhd:1668:9 */ + always @* + case (n3746_o) + 3'b100: n3749_o = 1'b1; + 3'b010: n3749_o = 1'b0; + 3'b001: n3749_o = 1'b0; + default: n3749_o = 1'b0; + endcase + /* decoder.vhd:1668:9 */ + always @* + case (n3746_o) + 3'b100: n3752_o = 1'b0; + 3'b010: n3752_o = 1'b1; + 3'b001: n3752_o = 1'b0; + default: n3752_o = 1'b0; + endcase + /* decoder.vhd:1668:9 */ + always @* + case (n3746_o) + 3'b100: n3755_o = 1'b1; + 3'b010: n3755_o = 1'b0; + 3'b001: n3755_o = 1'b0; + default: n3755_o = 1'b0; + endcase + /* decoder.vhd:1668:9 */ + always @* + case (n3746_o) + 3'b100: n3756_o = n2156_o; + 3'b010: n3756_o = n2156_o; + 3'b001: n3756_o = n3727_o; + default: n3756_o = n2156_o; + endcase + /* decoder.vhd:1668:9 */ + always @* + case (n3746_o) + 3'b100: n3759_o = 1'b0; + 3'b010: n3759_o = 1'b1; + 3'b001: n3759_o = n3730_o; + default: n3759_o = 1'b0; + endcase + /* decoder.vhd:1668:9 */ + always @* + case (n3746_o) + 3'b100: n3762_o = 4'b0001; + 3'b010: n3762_o = 4'b1100; + 3'b001: n3762_o = 4'b1100; + default: n3762_o = 4'b1100; + endcase + /* decoder.vhd:1668:9 */ + always @* + case (n3746_o) + 3'b100: n3764_o = 2'b01; + 3'b010: n3764_o = 2'b01; + 3'b001: n3764_o = n3733_o; + default: n3764_o = 2'b01; + endcase + /* decoder.vhd:1667:7 */ + assign n3766_o = opc_mnemonic_s == 6'b101010; + /* decoder.vhd:1696:13 */ + assign n3768_o = clk_mstate_i == 3'b000; + /* decoder.vhd:1700:13 */ + assign n3773_o = clk_mstate_i == 3'b010; + assign n3774_o = {n3773_o, n3768_o}; + /* decoder.vhd:1694:11 */ + always @* + case (n3774_o) + 2'b10: n3777_o = 1'b1; + 2'b01: n3777_o = 1'b0; + default: n3777_o = 1'b0; + endcase + /* decoder.vhd:1694:11 */ + always @* + case (n3774_o) + 2'b10: n3780_o = 1'b0; + 2'b01: n3780_o = 1'b1; + default: n3780_o = 1'b0; + endcase + /* decoder.vhd:1694:11 */ + always @* + case (n3774_o) + 2'b10: n3783_o = 1'b1; + 2'b01: n3783_o = 1'b0; + default: n3783_o = 1'b0; + endcase + /* decoder.vhd:1694:11 */ + always @* + case (n3774_o) + 2'b10: n3786_o = 4'b0001; + 2'b01: n3786_o = 4'b1100; + default: n3786_o = 4'b1100; + endcase + /* decoder.vhd:1693:9 */ + assign n3788_o = clk_second_cycle_i ? n3777_o : 1'b0; + /* decoder.vhd:1693:9 */ + assign n3790_o = clk_second_cycle_i ? n3780_o : 1'b0; + /* decoder.vhd:1693:9 */ + assign n3792_o = clk_second_cycle_i ? n3783_o : 1'b0; + /* decoder.vhd:1693:9 */ + assign n3794_o = clk_second_cycle_i ? n3786_o : 4'b1100; + /* decoder.vhd:1690:7 */ + assign n3796_o = opc_mnemonic_s == 6'b101011; + /* decoder.vhd:1714:12 */ + assign n3797_o = ~clk_second_cycle_i; + /* decoder.vhd:1716:27 */ + assign n3799_o = clk_mstate_i == 3'b100; + /* decoder.vhd:1717:28 */ + assign n3800_o = opc_opcode_q[1:0]; + /* decoder.vhd:1717:41 */ + assign n3802_o = n3800_o == 2'b00; + /* decoder.vhd:1719:31 */ + assign n3803_o = opc_opcode_q[1]; + /* decoder.vhd:1719:35 */ + assign n3804_o = ~n3803_o; + /* decoder.vhd:1719:13 */ + assign n3807_o = n3804_o ? 1'b1 : 1'b0; + /* decoder.vhd:1719:13 */ + assign n3810_o = n3804_o ? 1'b0 : 1'b1; + /* decoder.vhd:1719:13 */ + assign n3813_o = n3804_o ? 1'b1 : 1'b0; + /* decoder.vhd:1719:13 */ + assign n3816_o = n3804_o ? 1'b0 : 1'b1; + /* decoder.vhd:1717:13 */ + assign n3818_o = n3802_o ? 1'b0 : n3807_o; + /* decoder.vhd:1717:13 */ + assign n3820_o = n3802_o ? 1'b0 : n3810_o; + /* decoder.vhd:1717:13 */ + assign n3822_o = n3802_o ? 1'b0 : n3813_o; + /* decoder.vhd:1717:13 */ + assign n3824_o = n3802_o ? 1'b0 : n3816_o; + /* decoder.vhd:1717:13 */ + assign n3827_o = n3802_o ? 1'b1 : 1'b0; + /* decoder.vhd:1716:11 */ + assign n3830_o = n3799_o ? 1'b1 : 1'b0; + /* decoder.vhd:1716:11 */ + assign n3832_o = n3799_o ? n3818_o : 1'b0; + /* decoder.vhd:1716:11 */ + assign n3834_o = n3799_o ? n3820_o : 1'b0; + /* decoder.vhd:1716:11 */ + assign n3836_o = n3799_o ? n3822_o : 1'b0; + /* decoder.vhd:1716:11 */ + assign n3838_o = n3799_o ? n3824_o : 1'b0; + /* decoder.vhd:1716:11 */ + assign n3840_o = n3799_o ? n3827_o : 1'b0; + /* decoder.vhd:1734:13 */ + assign n3842_o = clk_mstate_i == 3'b000; + /* decoder.vhd:1739:13 */ + assign n3844_o = clk_mstate_i == 3'b001; + /* decoder.vhd:1748:30 */ + assign n3845_o = opc_opcode_q[1:0]; + /* decoder.vhd:1748:43 */ + assign n3847_o = n3845_o == 2'b00; + /* decoder.vhd:1750:33 */ + assign n3848_o = opc_opcode_q[1]; + /* decoder.vhd:1750:37 */ + assign n3849_o = ~n3848_o; + /* decoder.vhd:1750:15 */ + assign n3852_o = n3849_o ? 1'b1 : 1'b0; + /* decoder.vhd:1750:15 */ + assign n3855_o = n3849_o ? 1'b0 : 1'b1; + /* decoder.vhd:1748:15 */ + assign n3858_o = n3847_o ? 1'b1 : 1'b0; + /* decoder.vhd:1748:15 */ + assign n3860_o = n3847_o ? 1'b0 : n3852_o; + /* decoder.vhd:1748:15 */ + assign n3862_o = n3847_o ? 1'b0 : n3855_o; + /* decoder.vhd:1744:13 */ + assign n3864_o = clk_mstate_i == 3'b010; + assign n3865_o = {n3864_o, n3844_o, n3842_o}; + /* decoder.vhd:1731:11 */ + always @* + case (n3865_o) + 3'b100: n3869_o = 1'b0; + 3'b010: n3869_o = 1'b1; + 3'b001: n3869_o = 1'b1; + default: n3869_o = 1'b0; + endcase + /* decoder.vhd:1731:11 */ + always @* + case (n3865_o) + 3'b100: n3873_o = 1'b1; + 3'b010: n3873_o = 1'b1; + 3'b001: n3873_o = 1'b0; + default: n3873_o = 1'b0; + endcase + /* decoder.vhd:1731:11 */ + always @* + case (n3865_o) + 3'b100: n3875_o = n3858_o; + 3'b010: n3875_o = 1'b0; + 3'b001: n3875_o = 1'b0; + default: n3875_o = 1'b0; + endcase + /* decoder.vhd:1731:11 */ + always @* + case (n3865_o) + 3'b100: n3877_o = n3860_o; + 3'b010: n3877_o = 1'b0; + 3'b001: n3877_o = 1'b0; + default: n3877_o = 1'b0; + endcase + /* decoder.vhd:1731:11 */ + always @* + case (n3865_o) + 3'b100: n3879_o = n3862_o; + 3'b010: n3879_o = 1'b0; + 3'b001: n3879_o = 1'b0; + default: n3879_o = 1'b0; + endcase + /* decoder.vhd:1731:11 */ + always @* + case (n3865_o) + 3'b100: n3882_o = 4'b0001; + 3'b010: n3882_o = 4'b1100; + 3'b001: n3882_o = 4'b1100; + default: n3882_o = 4'b1100; + endcase + /* decoder.vhd:1714:9 */ + assign n3884_o = n3797_o ? 1'b0 : n3869_o; + /* decoder.vhd:1714:9 */ + assign n3886_o = n3797_o ? n3830_o : 1'b0; + /* decoder.vhd:1714:9 */ + assign n3888_o = n3797_o ? 1'b0 : n3873_o; + /* decoder.vhd:1714:9 */ + assign n3890_o = n3797_o ? 1'b0 : n3875_o; + /* decoder.vhd:1714:9 */ + assign n3892_o = n3797_o ? 1'b0 : n3877_o; + /* decoder.vhd:1714:9 */ + assign n3894_o = n3797_o ? n3832_o : 1'b0; + /* decoder.vhd:1714:9 */ + assign n3896_o = n3797_o ? 1'b0 : n3879_o; + /* decoder.vhd:1714:9 */ + assign n3898_o = n3797_o ? n3834_o : 1'b0; + /* decoder.vhd:1714:9 */ + assign n3900_o = n3797_o ? 4'b1100 : n3882_o; + /* decoder.vhd:1714:9 */ + assign n3902_o = n3797_o ? n3836_o : 1'b0; + /* decoder.vhd:1714:9 */ + assign n3904_o = n3797_o ? n3838_o : 1'b0; + /* decoder.vhd:1714:9 */ + assign n3906_o = n3797_o ? n3840_o : 1'b0; + /* decoder.vhd:1711:7 */ + assign n3908_o = opc_mnemonic_s == 6'b101100; + /* decoder.vhd:1766:25 */ + assign n3910_o = clk_mstate_i == 3'b011; + /* decoder.vhd:1766:9 */ + assign n3913_o = n3910_o ? 1'b1 : 1'b0; + /* decoder.vhd:1766:9 */ + assign n3916_o = n3910_o ? 1'b1 : 1'b0; + /* decoder.vhd:1764:7 */ + assign n3918_o = opc_mnemonic_s == 6'b111011; + /* decoder.vhd:1774:24 */ + assign n3919_o = opc_opcode_q[4]; + /* decoder.vhd:1774:28 */ + assign n3920_o = ~n3919_o; + /* decoder.vhd:1774:9 */ + assign n3923_o = n3920_o ? 1'b1 : 1'b0; + /* decoder.vhd:1779:12 */ + assign n3924_o = ~clk_second_cycle_i; + /* decoder.vhd:1779:52 */ + assign n3926_o = clk_mstate_i == 3'b011; + /* decoder.vhd:1779:35 */ + assign n3927_o = n3924_o & n3926_o; + /* decoder.vhd:1782:26 */ + assign n3928_o = opc_opcode_q[4]; + /* decoder.vhd:1783:28 */ + assign n3929_o = opc_opcode_q[1]; + /* decoder.vhd:1783:32 */ + assign n3930_o = ~n3929_o; + /* decoder.vhd:1783:13 */ + assign n3933_o = n3930_o ? 1'b1 : 1'b0; + /* decoder.vhd:1783:13 */ + assign n3936_o = n3930_o ? 1'b0 : 1'b1; + /* decoder.vhd:1782:11 */ + assign n3939_o = n3928_o ? 1'b0 : 1'b1; + /* decoder.vhd:1782:11 */ + assign n3941_o = n3928_o ? n3933_o : 1'b0; + /* decoder.vhd:1782:11 */ + assign n3943_o = n3928_o ? n3936_o : 1'b0; + /* decoder.vhd:1779:9 */ + assign n3946_o = n3927_o ? 1'b1 : 1'b0; + /* decoder.vhd:1779:9 */ + assign n3948_o = n3927_o ? n3939_o : 1'b0; + /* decoder.vhd:1779:9 */ + assign n3950_o = n3927_o ? n3941_o : 1'b0; + /* decoder.vhd:1779:9 */ + assign n3952_o = n3927_o ? n3943_o : 1'b0; + /* decoder.vhd:1773:7 */ + assign n3954_o = opc_mnemonic_s == 6'b101110; + /* decoder.vhd:1798:12 */ + assign n3955_o = ~clk_second_cycle_i; + /* decoder.vhd:1801:13 */ + assign n3957_o = clk_mstate_i == 3'b010; + /* decoder.vhd:1805:13 */ + assign n3959_o = clk_mstate_i == 3'b011; + /* decoder.vhd:1812:13 */ + assign n3961_o = clk_mstate_i == 3'b100; + assign n3962_o = {n3961_o, n3959_o, n3957_o}; + /* decoder.vhd:1799:11 */ + always @* + case (n3962_o) + 3'b100: n3965_o = 1'b1; + 3'b010: n3965_o = 1'b1; + 3'b001: n3965_o = n2156_o; + default: n3965_o = n2156_o; + endcase + /* decoder.vhd:1799:11 */ + always @* + case (n3962_o) + 3'b100: n3968_o = 1'b1; + 3'b010: n3968_o = 1'b0; + 3'b001: n3968_o = 1'b0; + default: n3968_o = 1'b0; + endcase + /* decoder.vhd:1799:11 */ + always @* + case (n3962_o) + 3'b100: n3971_o = 1'b1; + 3'b010: n3971_o = 1'b0; + 3'b001: n3971_o = 1'b0; + default: n3971_o = 1'b0; + endcase + /* decoder.vhd:1799:11 */ + always @* + case (n3962_o) + 3'b100: n3974_o = 1'b0; + 3'b010: n3974_o = 1'b1; + 3'b001: n3974_o = 1'b0; + default: n3974_o = 1'b0; + endcase + /* decoder.vhd:1799:11 */ + always @* + case (n3962_o) + 3'b100: n3978_o = 2'b11; + 3'b010: n3978_o = 2'b10; + 3'b001: n3978_o = 2'b01; + default: n3978_o = 2'b01; + endcase + /* decoder.vhd:1799:11 */ + always @* + case (n3962_o) + 3'b100: n3981_o = 1'b0; + 3'b010: n3981_o = 1'b0; + 3'b001: n3981_o = 1'b1; + default: n3981_o = 1'b0; + endcase + /* decoder.vhd:1829:30 */ + assign n3982_o = opc_opcode_q[4]; + /* decoder.vhd:1829:15 */ + assign n3985_o = n3982_o ? 1'b1 : 1'b0; + /* decoder.vhd:1829:15 */ + assign n3988_o = n3982_o ? 1'b1 : 1'b0; + /* decoder.vhd:1826:13 */ + assign n3990_o = clk_mstate_i == 3'b000; + /* decoder.vhd:1834:13 */ + assign n3992_o = clk_mstate_i == 3'b001; + assign n3993_o = {n3992_o, n3990_o}; + /* decoder.vhd:1824:11 */ + always @* + case (n3993_o) + 2'b10: n3996_o = 1'b0; + 2'b01: n3996_o = 1'b1; + default: n3996_o = 1'b0; + endcase + /* decoder.vhd:1824:11 */ + always @* + case (n3993_o) + 2'b10: n3999_o = 1'b0; + 2'b01: n3999_o = 1'b1; + default: n3999_o = 1'b0; + endcase + /* decoder.vhd:1824:11 */ + always @* + case (n3993_o) + 2'b10: n4001_o = 1'b0; + 2'b01: n4001_o = n3985_o; + default: n4001_o = 1'b0; + endcase + /* decoder.vhd:1824:11 */ + always @* + case (n3993_o) + 2'b10: n4004_o = 1'b1; + 2'b01: n4004_o = 1'b0; + default: n4004_o = 1'b0; + endcase + /* decoder.vhd:1824:11 */ + always @* + case (n3993_o) + 2'b10: n4006_o = 1'b0; + 2'b01: n4006_o = n3988_o; + default: n4006_o = 1'b0; + endcase + /* decoder.vhd:1798:9 */ + assign n4007_o = n3955_o ? n3965_o : n2156_o; + /* decoder.vhd:1798:9 */ + assign n4008_o = n3955_o ? n3968_o : n3996_o; + /* decoder.vhd:1798:9 */ + assign n4010_o = n3955_o ? n3971_o : 1'b0; + /* decoder.vhd:1798:9 */ + assign n4012_o = n3955_o ? 1'b0 : n3999_o; + /* decoder.vhd:1798:9 */ + assign n4014_o = n3955_o ? n3974_o : 1'b0; + /* decoder.vhd:1798:9 */ + assign n4016_o = n3955_o ? 1'b0 : n4001_o; + /* decoder.vhd:1798:9 */ + assign n4018_o = n3955_o ? n3978_o : 2'b01; + /* decoder.vhd:1798:9 */ + assign n4020_o = n3955_o ? n3981_o : 1'b0; + /* decoder.vhd:1798:9 */ + assign n4022_o = n3955_o ? 1'b0 : n4004_o; + /* decoder.vhd:1798:9 */ + assign n4024_o = n3955_o ? 1'b0 : n4006_o; + /* decoder.vhd:1797:7 */ + assign n4026_o = opc_mnemonic_s == 6'b101111; + /* decoder.vhd:1846:25 */ + assign n4028_o = clk_mstate_i == 3'b010; + /* decoder.vhd:1851:26 */ + assign n4029_o = opc_opcode_q[4]; + /* decoder.vhd:1851:11 */ + assign n4032_o = n4029_o ? 1'b1 : 1'b0; + /* decoder.vhd:1851:11 */ + assign n4034_o = n4029_o ? alu_carry_i : 1'b0; + /* decoder.vhd:1851:11 */ + assign n4037_o = n4029_o ? 1'b1 : 1'b0; + /* decoder.vhd:1846:9 */ + assign n4040_o = n4028_o ? 1'b1 : 1'b0; + /* decoder.vhd:1846:9 */ + assign n4043_o = n4028_o ? 1'b1 : 1'b0; + /* decoder.vhd:1846:9 */ + assign n4046_o = n4028_o ? 4'b0101 : 4'b1100; + /* decoder.vhd:1846:9 */ + assign n4048_o = n4028_o ? n4032_o : 1'b0; + /* decoder.vhd:1846:9 */ + assign n4050_o = n4028_o ? n4034_o : 1'b0; + /* decoder.vhd:1846:9 */ + assign n4052_o = n4028_o ? n4037_o : 1'b0; + /* decoder.vhd:1845:7 */ + assign n4054_o = opc_mnemonic_s == 6'b110000; + /* decoder.vhd:1860:25 */ + assign n4056_o = clk_mstate_i == 3'b010; + /* decoder.vhd:1865:26 */ + assign n4057_o = opc_opcode_q[4]; + /* decoder.vhd:1865:30 */ + assign n4058_o = ~n4057_o; + /* decoder.vhd:1865:11 */ + assign n4061_o = n4058_o ? 1'b1 : 1'b0; + /* decoder.vhd:1865:11 */ + assign n4063_o = n4058_o ? alu_carry_i : 1'b0; + /* decoder.vhd:1865:11 */ + assign n4066_o = n4058_o ? 1'b1 : 1'b0; + /* decoder.vhd:1860:9 */ + assign n4069_o = n4056_o ? 1'b1 : 1'b0; + /* decoder.vhd:1860:9 */ + assign n4072_o = n4056_o ? 1'b1 : 1'b0; + /* decoder.vhd:1860:9 */ + assign n4075_o = n4056_o ? 4'b0110 : 4'b1100; + /* decoder.vhd:1860:9 */ + assign n4077_o = n4056_o ? n4061_o : 1'b0; + /* decoder.vhd:1860:9 */ + assign n4079_o = n4056_o ? n4063_o : 1'b0; + /* decoder.vhd:1860:9 */ + assign n4081_o = n4056_o ? n4066_o : 1'b0; + /* decoder.vhd:1859:7 */ + assign n4083_o = opc_mnemonic_s == 6'b110001; + /* decoder.vhd:1874:25 */ + assign n4085_o = clk_mstate_i == 3'b010; + /* decoder.vhd:1875:26 */ + assign n4086_o = opc_opcode_q[4]; + /* decoder.vhd:1875:11 */ + assign n4089_o = n4086_o ? 1'b0 : 1'b1; + /* decoder.vhd:1875:11 */ + assign n4092_o = n4086_o ? 1'b1 : 1'b0; + /* decoder.vhd:1874:9 */ + assign n4094_o = n4085_o ? n4089_o : 1'b0; + /* decoder.vhd:1874:9 */ + assign n4096_o = n4085_o ? n4092_o : 1'b0; + /* decoder.vhd:1873:7 */ + assign n4098_o = opc_mnemonic_s == 6'b110010; + /* decoder.vhd:1884:25 */ + assign n4100_o = clk_mstate_i == 3'b010; + /* decoder.vhd:1885:45 */ + assign n4101_o = opc_opcode_q[4]; + /* decoder.vhd:1884:9 */ + assign n4103_o = n4100_o ? n4101_o : 1'b0; + /* decoder.vhd:1884:9 */ + assign n4106_o = n4100_o ? 1'b1 : 1'b0; + /* decoder.vhd:1883:7 */ + assign n4108_o = opc_mnemonic_s == 6'b110011; + /* decoder.vhd:1891:25 */ + assign n4110_o = clk_mstate_i == 3'b010; + /* decoder.vhd:1891:9 */ + assign n4113_o = n4110_o ? 1'b1 : 1'b0; + /* decoder.vhd:1890:7 */ + assign n4115_o = opc_mnemonic_s == 6'b110100; + /* decoder.vhd:1897:25 */ + assign n4117_o = clk_mstate_i == 3'b010; + /* decoder.vhd:1898:26 */ + assign n4118_o = opc_opcode_q[4]; + /* decoder.vhd:1898:11 */ + assign n4121_o = n4118_o ? 1'b1 : 1'b0; + /* decoder.vhd:1898:11 */ + assign n4124_o = n4118_o ? 1'b0 : 1'b1; + /* decoder.vhd:1897:9 */ + assign n4126_o = n4117_o ? n4121_o : 1'b0; + /* decoder.vhd:1897:9 */ + assign n4128_o = n4117_o ? n4124_o : 1'b0; + /* decoder.vhd:1896:7 */ + assign n4130_o = opc_mnemonic_s == 6'b110101; + /* decoder.vhd:1909:25 */ + assign n4132_o = clk_mstate_i == 3'b010; + /* decoder.vhd:1909:9 */ + assign n4135_o = n4132_o ? 1'b1 : 1'b0; + /* decoder.vhd:1909:9 */ + assign n4138_o = n4132_o ? 1'b1 : 1'b0; + /* decoder.vhd:1906:7 */ + assign n4140_o = opc_mnemonic_s == 6'b110110; + /* decoder.vhd:1920:28 */ + assign n4141_o = opc_opcode_q[3]; + /* decoder.vhd:1920:32 */ + assign n4142_o = ~n4141_o; + /* decoder.vhd:1919:44 */ + assign n4144_o = 1'b0 | n4142_o; + /* decoder.vhd:1919:13 */ + assign n4151_o = n4144_o ? 1'b1 : n2156_o; + /* decoder.vhd:1919:13 */ + assign n4154_o = n4144_o ? 1'b1 : 1'b0; + /* decoder.vhd:1919:13 */ + assign n4157_o = n4144_o ? 2'b00 : 2'b01; + /* decoder.vhd:1918:11 */ + assign n4159_o = clk_mstate_i == 3'b010; + /* decoder.vhd:1930:28 */ + assign n4160_o = opc_opcode_q[4]; + /* decoder.vhd:1930:13 */ + assign n4163_o = n4160_o ? 1'b1 : 1'b0; + /* decoder.vhd:1926:11 */ + assign n4165_o = clk_mstate_i == 3'b011; + /* decoder.vhd:1940:28 */ + assign n4166_o = opc_opcode_q[4]; + /* decoder.vhd:1940:13 */ + assign n4169_o = n4166_o ? 4'b1011 : 4'b1100; + /* decoder.vhd:1937:11 */ + assign n4171_o = clk_mstate_i == 3'b100; + assign n4172_o = {n4171_o, n4165_o, n4159_o}; + /* decoder.vhd:1916:9 */ + always @* + case (n4172_o) + 3'b100: n4175_o = 1'b0; + 3'b010: n4175_o = 1'b1; + 3'b001: n4175_o = 1'b0; + default: n4175_o = 1'b0; + endcase + /* decoder.vhd:1916:9 */ + always @* + case (n4172_o) + 3'b100: n4178_o = 1'b0; + 3'b010: n4178_o = 1'b1; + 3'b001: n4178_o = 1'b0; + default: n4178_o = 1'b0; + endcase + /* decoder.vhd:1916:9 */ + always @* + case (n4172_o) + 3'b100: n4181_o = 1'b1; + 3'b010: n4181_o = 1'b0; + 3'b001: n4181_o = 1'b0; + default: n4181_o = 1'b0; + endcase + /* decoder.vhd:1916:9 */ + always @* + case (n4172_o) + 3'b100: n4182_o = n2156_o; + 3'b010: n4182_o = n2156_o; + 3'b001: n4182_o = n4151_o; + default: n4182_o = n2156_o; + endcase + /* decoder.vhd:1916:9 */ + always @* + case (n4172_o) + 3'b100: n4185_o = 1'b0; + 3'b010: n4185_o = 1'b1; + 3'b001: n4185_o = n4154_o; + default: n4185_o = 1'b0; + endcase + /* decoder.vhd:1916:9 */ + always @* + case (n4172_o) + 3'b100: n4187_o = n4169_o; + 3'b010: n4187_o = 4'b1100; + 3'b001: n4187_o = 4'b1100; + default: n4187_o = 4'b1100; + endcase + /* decoder.vhd:1916:9 */ + always @* + case (n4172_o) + 3'b100: n4189_o = 1'b0; + 3'b010: n4189_o = n4163_o; + 3'b001: n4189_o = 1'b0; + default: n4189_o = 1'b0; + endcase + /* decoder.vhd:1916:9 */ + always @* + case (n4172_o) + 3'b100: n4191_o = 2'b01; + 3'b010: n4191_o = 2'b01; + 3'b001: n4191_o = n4157_o; + default: n4191_o = 2'b01; + endcase + /* decoder.vhd:1916:9 */ + always @* + case (n4172_o) + 3'b100: n4194_o = 1'b1; + 3'b010: n4194_o = 1'b0; + 3'b001: n4194_o = 1'b0; + default: n4194_o = 1'b0; + endcase + /* decoder.vhd:1915:7 */ + assign n4196_o = opc_mnemonic_s == 6'b110111; + /* decoder.vhd:1957:28 */ + assign n4197_o = opc_opcode_q[3]; + /* decoder.vhd:1957:32 */ + assign n4198_o = ~n4197_o; + /* decoder.vhd:1956:44 */ + assign n4200_o = 1'b0 | n4198_o; + /* decoder.vhd:1956:13 */ + assign n4207_o = n4200_o ? 1'b1 : n2156_o; + /* decoder.vhd:1956:13 */ + assign n4210_o = n4200_o ? 1'b1 : 1'b0; + /* decoder.vhd:1956:13 */ + assign n4213_o = n4200_o ? 2'b00 : 2'b01; + /* decoder.vhd:1955:11 */ + assign n4215_o = clk_mstate_i == 3'b010; + /* decoder.vhd:1962:11 */ + assign n4220_o = clk_mstate_i == 3'b011; + /* decoder.vhd:1966:11 */ + assign n4225_o = clk_mstate_i == 3'b100; + assign n4226_o = {n4225_o, n4220_o, n4215_o}; + /* decoder.vhd:1953:9 */ + always @* + case (n4226_o) + 3'b100: n4229_o = 1'b1; + 3'b010: n4229_o = 1'b0; + 3'b001: n4229_o = 1'b0; + default: n4229_o = 1'b0; + endcase + /* decoder.vhd:1953:9 */ + always @* + case (n4226_o) + 3'b100: n4232_o = 1'b0; + 3'b010: n4232_o = 1'b1; + 3'b001: n4232_o = 1'b0; + default: n4232_o = 1'b0; + endcase + /* decoder.vhd:1953:9 */ + always @* + case (n4226_o) + 3'b100: n4235_o = 1'b1; + 3'b010: n4235_o = 1'b0; + 3'b001: n4235_o = 1'b0; + default: n4235_o = 1'b0; + endcase + /* decoder.vhd:1953:9 */ + always @* + case (n4226_o) + 3'b100: n4236_o = n2156_o; + 3'b010: n4236_o = n2156_o; + 3'b001: n4236_o = n4207_o; + default: n4236_o = n2156_o; + endcase + /* decoder.vhd:1953:9 */ + always @* + case (n4226_o) + 3'b100: n4239_o = 1'b0; + 3'b010: n4239_o = 1'b1; + 3'b001: n4239_o = n4210_o; + default: n4239_o = 1'b0; + endcase + /* decoder.vhd:1953:9 */ + always @* + case (n4226_o) + 3'b100: n4242_o = 4'b0010; + 3'b010: n4242_o = 4'b1100; + 3'b001: n4242_o = 4'b1100; + default: n4242_o = 4'b1100; + endcase + /* decoder.vhd:1953:9 */ + always @* + case (n4226_o) + 3'b100: n4244_o = 2'b01; + 3'b010: n4244_o = 2'b01; + 3'b001: n4244_o = n4213_o; + default: n4244_o = 2'b01; + endcase + /* decoder.vhd:1952:7 */ + assign n4246_o = opc_mnemonic_s == 6'b111000; + /* decoder.vhd:1981:13 */ + assign n4248_o = clk_mstate_i == 3'b000; + /* decoder.vhd:1985:13 */ + assign n4253_o = clk_mstate_i == 3'b010; + assign n4254_o = {n4253_o, n4248_o}; + /* decoder.vhd:1979:11 */ + always @* + case (n4254_o) + 2'b10: n4257_o = 1'b1; + 2'b01: n4257_o = 1'b0; + default: n4257_o = 1'b0; + endcase + /* decoder.vhd:1979:11 */ + always @* + case (n4254_o) + 2'b10: n4260_o = 1'b0; + 2'b01: n4260_o = 1'b1; + default: n4260_o = 1'b0; + endcase + /* decoder.vhd:1979:11 */ + always @* + case (n4254_o) + 2'b10: n4263_o = 1'b1; + 2'b01: n4263_o = 1'b0; + default: n4263_o = 1'b0; + endcase + /* decoder.vhd:1979:11 */ + always @* + case (n4254_o) + 2'b10: n4266_o = 4'b0010; + 2'b01: n4266_o = 4'b1100; + default: n4266_o = 4'b1100; + endcase + /* decoder.vhd:1978:9 */ + assign n4268_o = clk_second_cycle_i ? n4257_o : 1'b0; + /* decoder.vhd:1978:9 */ + assign n4270_o = clk_second_cycle_i ? n4260_o : 1'b0; + /* decoder.vhd:1978:9 */ + assign n4272_o = clk_second_cycle_i ? n4263_o : 1'b0; + /* decoder.vhd:1978:9 */ + assign n4274_o = clk_second_cycle_i ? n4266_o : 4'b1100; + /* decoder.vhd:1975:7 */ + assign n4276_o = opc_mnemonic_s == 6'b111001; + assign n4277_o = {n4276_o, n4246_o, n4196_o, n4140_o, n4130_o, n4115_o, n4108_o, n4098_o, n4083_o, n4054_o, n4026_o, n3954_o, n3918_o, n3908_o, n3796_o, n3766_o, n3716_o, n3714_o, n3648_o, n3617_o, n3552_o, n3484_o, n3459_o, n3449_o, n3415_o, n3380_o, n3367_o, n3354_o, n3315_o, n3307_o, n3271_o, n3240_o, n3204_o, n3178_o, n3152_o, n3126_o, n3099_o, n3068_o, n3034_o, n3003_o, n2972_o, n2911_o, n2900_o, n2890_o, n2870_o, n2863_o, n2847_o, n2783_o, n2768_o, n2753_o, n2717_o, n2671_o, n2650_o, n2640_o, n2627_o, n2611_o, n2604_o, n2591_o, n2473_o, n2361_o, n2331_o, n2281_o, n2229_o}; + /* decoder.vhd:635:5 */ + always @* + case (n4277_o) + 63'b100000000000000000000000000000000000000000000000000000000000000: n4279_o = n4268_o; + 63'b010000000000000000000000000000000000000000000000000000000000000: n4279_o = n4229_o; + 63'b001000000000000000000000000000000000000000000000000000000000000: n4279_o = n4175_o; + 63'b000100000000000000000000000000000000000000000000000000000000000: n4279_o = n4135_o; + 63'b000010000000000000000000000000000000000000000000000000000000000: n4279_o = 1'b0; + 63'b000001000000000000000000000000000000000000000000000000000000000: n4279_o = 1'b0; + 63'b000000100000000000000000000000000000000000000000000000000000000: n4279_o = 1'b0; + 63'b000000010000000000000000000000000000000000000000000000000000000: n4279_o = 1'b0; + 63'b000000001000000000000000000000000000000000000000000000000000000: n4279_o = n4069_o; + 63'b000000000100000000000000000000000000000000000000000000000000000: n4279_o = n4040_o; + 63'b000000000010000000000000000000000000000000000000000000000000000: n4279_o = 1'b0; + 63'b000000000001000000000000000000000000000000000000000000000000000: n4279_o = 1'b0; + 63'b000000000000100000000000000000000000000000000000000000000000000: n4279_o = 1'b0; + 63'b000000000000010000000000000000000000000000000000000000000000000: n4279_o = 1'b0; + 63'b000000000000001000000000000000000000000000000000000000000000000: n4279_o = n3788_o; + 63'b000000000000000100000000000000000000000000000000000000000000000: n4279_o = n3749_o; + 63'b000000000000000010000000000000000000000000000000000000000000000: n4279_o = 1'b0; + 63'b000000000000000001000000000000000000000000000000000000000000000: n4279_o = n3703_o; + 63'b000000000000000000100000000000000000000000000000000000000000000: n4279_o = n3640_o; + 63'b000000000000000000010000000000000000000000000000000000000000000: n4279_o = n3605_o; + 63'b000000000000000000001000000000000000000000000000000000000000000: n4279_o = 1'b0; + 63'b000000000000000000000100000000000000000000000000000000000000000: n4279_o = n3476_o; + 63'b000000000000000000000010000000000000000000000000000000000000000: n4279_o = 1'b0; + 63'b000000000000000000000001000000000000000000000000000000000000000: n4279_o = 1'b0; + 63'b000000000000000000000000100000000000000000000000000000000000000: n4279_o = 1'b0; + 63'b000000000000000000000000010000000000000000000000000000000000000: n4279_o = 1'b0; + 63'b000000000000000000000000001000000000000000000000000000000000000: n4279_o = n3359_o; + 63'b000000000000000000000000000100000000000000000000000000000000000: n4279_o = n3343_o; + 63'b000000000000000000000000000010000000000000000000000000000000000: n4279_o = n3313_o; + 63'b000000000000000000000000000001000000000000000000000000000000000: n4279_o = 1'b0; + 63'b000000000000000000000000000000100000000000000000000000000000000: n4279_o = 1'b0; + 63'b000000000000000000000000000000010000000000000000000000000000000: n4279_o = 1'b0; + 63'b000000000000000000000000000000001000000000000000000000000000000: n4279_o = 1'b0; + 63'b000000000000000000000000000000000100000000000000000000000000000: n4279_o = 1'b0; + 63'b000000000000000000000000000000000010000000000000000000000000000: n4279_o = 1'b0; + 63'b000000000000000000000000000000000001000000000000000000000000000: n4279_o = 1'b0; + 63'b000000000000000000000000000000000000100000000000000000000000000: n4279_o = 1'b0; + 63'b000000000000000000000000000000000000010000000000000000000000000: n4279_o = 1'b0; + 63'b000000000000000000000000000000000000001000000000000000000000000: n4279_o = 1'b0; + 63'b000000000000000000000000000000000000000100000000000000000000000: n4279_o = 1'b0; + 63'b000000000000000000000000000000000000000010000000000000000000000: n4279_o = n2955_o; + 63'b000000000000000000000000000000000000000001000000000000000000000: n4279_o = n2906_o; + 63'b000000000000000000000000000000000000000000100000000000000000000: n4279_o = n2895_o; + 63'b000000000000000000000000000000000000000000010000000000000000000: n4279_o = n2884_o; + 63'b000000000000000000000000000000000000000000001000000000000000000: n4279_o = 1'b0; + 63'b000000000000000000000000000000000000000000000100000000000000000: n4279_o = 1'b0; + 63'b000000000000000000000000000000000000000000000010000000000000000: n4279_o = 1'b0; + 63'b000000000000000000000000000000000000000000000001000000000000000: n4279_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000100000000000000: n4279_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000010000000000000: n4279_o = n2739_o; + 63'b000000000000000000000000000000000000000000000000001000000000000: n4279_o = n2693_o; + 63'b000000000000000000000000000000000000000000000000000100000000000: n4279_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000010000000000: n4279_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000001000000000: n4279_o = n2632_o; + 63'b000000000000000000000000000000000000000000000000000000100000000: n4279_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000010000000: n4279_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000001000000: n4279_o = n2596_o; + 63'b000000000000000000000000000000000000000000000000000000000100000: n4279_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000010000: n4279_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000001000: n4279_o = n2353_o; + 63'b000000000000000000000000000000000000000000000000000000000000100: n4279_o = n2314_o; + 63'b000000000000000000000000000000000000000000000000000000000000010: n4279_o = n2265_o; + 63'b000000000000000000000000000000000000000000000000000000000000001: n4279_o = n2202_o; + default: n4279_o = 1'b0; + endcase + /* decoder.vhd:635:5 */ + always @* + case (n4277_o) + 63'b100000000000000000000000000000000000000000000000000000000000000: n4282_o = 1'b0; + 63'b010000000000000000000000000000000000000000000000000000000000000: n4282_o = 1'b0; + 63'b001000000000000000000000000000000000000000000000000000000000000: n4282_o = 1'b0; + 63'b000100000000000000000000000000000000000000000000000000000000000: n4282_o = 1'b0; + 63'b000010000000000000000000000000000000000000000000000000000000000: n4282_o = 1'b0; + 63'b000001000000000000000000000000000000000000000000000000000000000: n4282_o = 1'b0; + 63'b000000100000000000000000000000000000000000000000000000000000000: n4282_o = 1'b0; + 63'b000000010000000000000000000000000000000000000000000000000000000: n4282_o = 1'b0; + 63'b000000001000000000000000000000000000000000000000000000000000000: n4282_o = 1'b0; + 63'b000000000100000000000000000000000000000000000000000000000000000: n4282_o = 1'b0; + 63'b000000000010000000000000000000000000000000000000000000000000000: n4282_o = 1'b0; + 63'b000000000001000000000000000000000000000000000000000000000000000: n4282_o = 1'b0; + 63'b000000000000100000000000000000000000000000000000000000000000000: n4282_o = 1'b0; + 63'b000000000000010000000000000000000000000000000000000000000000000: n4282_o = n3884_o; + 63'b000000000000001000000000000000000000000000000000000000000000000: n4282_o = 1'b0; + 63'b000000000000000100000000000000000000000000000000000000000000000: n4282_o = 1'b0; + 63'b000000000000000010000000000000000000000000000000000000000000000: n4282_o = 1'b0; + 63'b000000000000000001000000000000000000000000000000000000000000000: n4282_o = 1'b0; + 63'b000000000000000000100000000000000000000000000000000000000000000: n4282_o = 1'b0; + 63'b000000000000000000010000000000000000000000000000000000000000000: n4282_o = 1'b0; + 63'b000000000000000000001000000000000000000000000000000000000000000: n4282_o = 1'b0; + 63'b000000000000000000000100000000000000000000000000000000000000000: n4282_o = 1'b0; + 63'b000000000000000000000010000000000000000000000000000000000000000: n4282_o = 1'b0; + 63'b000000000000000000000001000000000000000000000000000000000000000: n4282_o = 1'b0; + 63'b000000000000000000000000100000000000000000000000000000000000000: n4282_o = 1'b0; + 63'b000000000000000000000000010000000000000000000000000000000000000: n4282_o = 1'b0; + 63'b000000000000000000000000001000000000000000000000000000000000000: n4282_o = 1'b0; + 63'b000000000000000000000000000100000000000000000000000000000000000: n4282_o = 1'b0; + 63'b000000000000000000000000000010000000000000000000000000000000000: n4282_o = 1'b0; + 63'b000000000000000000000000000001000000000000000000000000000000000: n4282_o = 1'b0; + 63'b000000000000000000000000000000100000000000000000000000000000000: n4282_o = 1'b0; + 63'b000000000000000000000000000000010000000000000000000000000000000: n4282_o = 1'b0; + 63'b000000000000000000000000000000001000000000000000000000000000000: n4282_o = 1'b0; + 63'b000000000000000000000000000000000100000000000000000000000000000: n4282_o = 1'b0; + 63'b000000000000000000000000000000000010000000000000000000000000000: n4282_o = 1'b0; + 63'b000000000000000000000000000000000001000000000000000000000000000: n4282_o = 1'b0; + 63'b000000000000000000000000000000000000100000000000000000000000000: n4282_o = 1'b0; + 63'b000000000000000000000000000000000000010000000000000000000000000: n4282_o = 1'b0; + 63'b000000000000000000000000000000000000001000000000000000000000000: n4282_o = 1'b0; + 63'b000000000000000000000000000000000000000100000000000000000000000: n4282_o = 1'b0; + 63'b000000000000000000000000000000000000000010000000000000000000000: n4282_o = n2957_o; + 63'b000000000000000000000000000000000000000001000000000000000000000: n4282_o = 1'b0; + 63'b000000000000000000000000000000000000000000100000000000000000000: n4282_o = 1'b0; + 63'b000000000000000000000000000000000000000000010000000000000000000: n4282_o = 1'b0; + 63'b000000000000000000000000000000000000000000001000000000000000000: n4282_o = 1'b0; + 63'b000000000000000000000000000000000000000000000100000000000000000: n4282_o = 1'b0; + 63'b000000000000000000000000000000000000000000000010000000000000000: n4282_o = n2827_o; + 63'b000000000000000000000000000000000000000000000001000000000000000: n4282_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000100000000000000: n4282_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000010000000000000: n4282_o = n2741_o; + 63'b000000000000000000000000000000000000000000000000001000000000000: n4282_o = n2695_o; + 63'b000000000000000000000000000000000000000000000000000100000000000: n4282_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000010000000000: n4282_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000001000000000: n4282_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000100000000: n4282_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000010000000: n4282_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000001000000: n4282_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000100000: n4282_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000010000: n4282_o = n2449_o; + 63'b000000000000000000000000000000000000000000000000000000000001000: n4282_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000000100: n4282_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000000010: n4282_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000000001: n4282_o = 1'b0; + default: n4282_o = 1'b0; + endcase + /* decoder.vhd:635:5 */ + always @* + case (n4277_o) + 63'b100000000000000000000000000000000000000000000000000000000000000: n4285_o = n4270_o; + 63'b010000000000000000000000000000000000000000000000000000000000000: n4285_o = n4232_o; + 63'b001000000000000000000000000000000000000000000000000000000000000: n4285_o = n4178_o; + 63'b000100000000000000000000000000000000000000000000000000000000000: n4285_o = 1'b0; + 63'b000010000000000000000000000000000000000000000000000000000000000: n4285_o = 1'b0; + 63'b000001000000000000000000000000000000000000000000000000000000000: n4285_o = 1'b0; + 63'b000000100000000000000000000000000000000000000000000000000000000: n4285_o = 1'b0; + 63'b000000010000000000000000000000000000000000000000000000000000000: n4285_o = 1'b0; + 63'b000000001000000000000000000000000000000000000000000000000000000: n4285_o = 1'b0; + 63'b000000000100000000000000000000000000000000000000000000000000000: n4285_o = 1'b0; + 63'b000000000010000000000000000000000000000000000000000000000000000: n4285_o = 1'b0; + 63'b000000000001000000000000000000000000000000000000000000000000000: n4285_o = 1'b0; + 63'b000000000000100000000000000000000000000000000000000000000000000: n4285_o = 1'b0; + 63'b000000000000010000000000000000000000000000000000000000000000000: n4285_o = n3886_o; + 63'b000000000000001000000000000000000000000000000000000000000000000: n4285_o = n3790_o; + 63'b000000000000000100000000000000000000000000000000000000000000000: n4285_o = n3752_o; + 63'b000000000000000010000000000000000000000000000000000000000000000: n4285_o = 1'b0; + 63'b000000000000000001000000000000000000000000000000000000000000000: n4285_o = 1'b0; + 63'b000000000000000000100000000000000000000000000000000000000000000: n4285_o = 1'b0; + 63'b000000000000000000010000000000000000000000000000000000000000000: n4285_o = 1'b0; + 63'b000000000000000000001000000000000000000000000000000000000000000: n4285_o = 1'b0; + 63'b000000000000000000000100000000000000000000000000000000000000000: n4285_o = 1'b0; + 63'b000000000000000000000010000000000000000000000000000000000000000: n4285_o = 1'b0; + 63'b000000000000000000000001000000000000000000000000000000000000000: n4285_o = 1'b0; + 63'b000000000000000000000000100000000000000000000000000000000000000: n4285_o = 1'b0; + 63'b000000000000000000000000010000000000000000000000000000000000000: n4285_o = 1'b0; + 63'b000000000000000000000000001000000000000000000000000000000000000: n4285_o = 1'b0; + 63'b000000000000000000000000000100000000000000000000000000000000000: n4285_o = n3346_o; + 63'b000000000000000000000000000010000000000000000000000000000000000: n4285_o = 1'b0; + 63'b000000000000000000000000000001000000000000000000000000000000000: n4285_o = 1'b0; + 63'b000000000000000000000000000000100000000000000000000000000000000: n4285_o = 1'b0; + 63'b000000000000000000000000000000010000000000000000000000000000000: n4285_o = 1'b0; + 63'b000000000000000000000000000000001000000000000000000000000000000: n4285_o = 1'b0; + 63'b000000000000000000000000000000000100000000000000000000000000000: n4285_o = 1'b0; + 63'b000000000000000000000000000000000010000000000000000000000000000: n4285_o = 1'b0; + 63'b000000000000000000000000000000000001000000000000000000000000000: n4285_o = 1'b0; + 63'b000000000000000000000000000000000000100000000000000000000000000: n4285_o = 1'b0; + 63'b000000000000000000000000000000000000010000000000000000000000000: n4285_o = 1'b0; + 63'b000000000000000000000000000000000000001000000000000000000000000: n4285_o = 1'b0; + 63'b000000000000000000000000000000000000000100000000000000000000000: n4285_o = 1'b0; + 63'b000000000000000000000000000000000000000010000000000000000000000: n4285_o = 1'b0; + 63'b000000000000000000000000000000000000000001000000000000000000000: n4285_o = 1'b0; + 63'b000000000000000000000000000000000000000000100000000000000000000: n4285_o = 1'b0; + 63'b000000000000000000000000000000000000000000010000000000000000000: n4285_o = 1'b0; + 63'b000000000000000000000000000000000000000000001000000000000000000: n4285_o = 1'b0; + 63'b000000000000000000000000000000000000000000000100000000000000000: n4285_o = 1'b0; + 63'b000000000000000000000000000000000000000000000010000000000000000: n4285_o = 1'b0; + 63'b000000000000000000000000000000000000000000000001000000000000000: n4285_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000100000000000000: n4285_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000010000000000000: n4285_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000001000000000000: n4285_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000100000000000: n4285_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000010000000000: n4285_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000001000000000: n4285_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000100000000: n4285_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000010000000: n4285_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000001000000: n4285_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000100000: n4285_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000010000: n4285_o = n2451_o; + 63'b000000000000000000000000000000000000000000000000000000000001000: n4285_o = n2355_o; + 63'b000000000000000000000000000000000000000000000000000000000000100: n4285_o = n2317_o; + 63'b000000000000000000000000000000000000000000000000000000000000010: n4285_o = n2267_o; + 63'b000000000000000000000000000000000000000000000000000000000000001: n4285_o = n2205_o; + default: n4285_o = 1'b0; + endcase + /* decoder.vhd:635:5 */ + always @* + case (n4277_o) + 63'b100000000000000000000000000000000000000000000000000000000000000: n4288_o = n4272_o; + 63'b010000000000000000000000000000000000000000000000000000000000000: n4288_o = n4235_o; + 63'b001000000000000000000000000000000000000000000000000000000000000: n4288_o = n4181_o; + 63'b000100000000000000000000000000000000000000000000000000000000000: n4288_o = n4138_o; + 63'b000010000000000000000000000000000000000000000000000000000000000: n4288_o = 1'b0; + 63'b000001000000000000000000000000000000000000000000000000000000000: n4288_o = 1'b0; + 63'b000000100000000000000000000000000000000000000000000000000000000: n4288_o = 1'b0; + 63'b000000010000000000000000000000000000000000000000000000000000000: n4288_o = 1'b0; + 63'b000000001000000000000000000000000000000000000000000000000000000: n4288_o = n4072_o; + 63'b000000000100000000000000000000000000000000000000000000000000000: n4288_o = n4043_o; + 63'b000000000010000000000000000000000000000000000000000000000000000: n4288_o = 1'b0; + 63'b000000000001000000000000000000000000000000000000000000000000000: n4288_o = n3946_o; + 63'b000000000000100000000000000000000000000000000000000000000000000: n4288_o = n3913_o; + 63'b000000000000010000000000000000000000000000000000000000000000000: n4288_o = n3888_o; + 63'b000000000000001000000000000000000000000000000000000000000000000: n4288_o = n3792_o; + 63'b000000000000000100000000000000000000000000000000000000000000000: n4288_o = n3755_o; + 63'b000000000000000010000000000000000000000000000000000000000000000: n4288_o = 1'b0; + 63'b000000000000000001000000000000000000000000000000000000000000000: n4288_o = n3704_o; + 63'b000000000000000000100000000000000000000000000000000000000000000: n4288_o = n3642_o; + 63'b000000000000000000010000000000000000000000000000000000000000000: n4288_o = 1'b0; + 63'b000000000000000000001000000000000000000000000000000000000000000: n4288_o = n3544_o; + 63'b000000000000000000000100000000000000000000000000000000000000000: n4288_o = n3478_o; + 63'b000000000000000000000010000000000000000000000000000000000000000: n4288_o = n3454_o; + 63'b000000000000000000000001000000000000000000000000000000000000000: n4288_o = 1'b0; + 63'b000000000000000000000000100000000000000000000000000000000000000: n4288_o = n3405_o; + 63'b000000000000000000000000010000000000000000000000000000000000000: n4288_o = n3372_o; + 63'b000000000000000000000000001000000000000000000000000000000000000: n4288_o = 1'b0; + 63'b000000000000000000000000000100000000000000000000000000000000000: n4288_o = 1'b0; + 63'b000000000000000000000000000010000000000000000000000000000000000: n4288_o = 1'b0; + 63'b000000000000000000000000000001000000000000000000000000000000000: n4288_o = n3297_o; + 63'b000000000000000000000000000000100000000000000000000000000000000: n4288_o = 1'b0; + 63'b000000000000000000000000000000010000000000000000000000000000000: n4288_o = 1'b0; + 63'b000000000000000000000000000000001000000000000000000000000000000: n4288_o = 1'b0; + 63'b000000000000000000000000000000000100000000000000000000000000000: n4288_o = 1'b0; + 63'b000000000000000000000000000000000010000000000000000000000000000: n4288_o = 1'b0; + 63'b000000000000000000000000000000000001000000000000000000000000000: n4288_o = n3118_o; + 63'b000000000000000000000000000000000000100000000000000000000000000: n4288_o = 1'b0; + 63'b000000000000000000000000000000000000010000000000000000000000000: n4288_o = 1'b0; + 63'b000000000000000000000000000000000000001000000000000000000000000: n4288_o = 1'b0; + 63'b000000000000000000000000000000000000000100000000000000000000000: n4288_o = n2995_o; + 63'b000000000000000000000000000000000000000010000000000000000000000: n4288_o = n2960_o; + 63'b000000000000000000000000000000000000000001000000000000000000000: n4288_o = 1'b0; + 63'b000000000000000000000000000000000000000000100000000000000000000: n4288_o = 1'b0; + 63'b000000000000000000000000000000000000000000010000000000000000000: n4288_o = 1'b0; + 63'b000000000000000000000000000000000000000000001000000000000000000: n4288_o = 1'b0; + 63'b000000000000000000000000000000000000000000000100000000000000000: n4288_o = 1'b0; + 63'b000000000000000000000000000000000000000000000010000000000000000: n4288_o = n2829_o; + 63'b000000000000000000000000000000000000000000000001000000000000000: n4288_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000100000000000000: n4288_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000010000000000000: n4288_o = n2744_o; + 63'b000000000000000000000000000000000000000000000000001000000000000: n4288_o = n2698_o; + 63'b000000000000000000000000000000000000000000000000000100000000000: n4288_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000010000000000: n4288_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000001000000000: n4288_o = n2635_o; + 63'b000000000000000000000000000000000000000000000000000000100000000: n4288_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000010000000: n4288_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000001000000: n4288_o = n2599_o; + 63'b000000000000000000000000000000000000000000000000000000000100000: n4288_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000010000: n4288_o = n2453_o; + 63'b000000000000000000000000000000000000000000000000000000000001000: n4288_o = n2357_o; + 63'b000000000000000000000000000000000000000000000000000000000000100: n4288_o = n2320_o; + 63'b000000000000000000000000000000000000000000000000000000000000010: n4288_o = n2269_o; + 63'b000000000000000000000000000000000000000000000000000000000000001: n4288_o = n2208_o; + default: n4288_o = 1'b0; + endcase + /* decoder.vhd:635:5 */ + always @* + case (n4277_o) + 63'b100000000000000000000000000000000000000000000000000000000000000: n4291_o = 1'b0; + 63'b010000000000000000000000000000000000000000000000000000000000000: n4291_o = 1'b0; + 63'b001000000000000000000000000000000000000000000000000000000000000: n4291_o = 1'b0; + 63'b000100000000000000000000000000000000000000000000000000000000000: n4291_o = 1'b0; + 63'b000010000000000000000000000000000000000000000000000000000000000: n4291_o = 1'b0; + 63'b000001000000000000000000000000000000000000000000000000000000000: n4291_o = 1'b0; + 63'b000000100000000000000000000000000000000000000000000000000000000: n4291_o = 1'b0; + 63'b000000010000000000000000000000000000000000000000000000000000000: n4291_o = 1'b0; + 63'b000000001000000000000000000000000000000000000000000000000000000: n4291_o = 1'b0; + 63'b000000000100000000000000000000000000000000000000000000000000000: n4291_o = 1'b0; + 63'b000000000010000000000000000000000000000000000000000000000000000: n4291_o = 1'b0; + 63'b000000000001000000000000000000000000000000000000000000000000000: n4291_o = n3948_o; + 63'b000000000000100000000000000000000000000000000000000000000000000: n4291_o = n3916_o; + 63'b000000000000010000000000000000000000000000000000000000000000000: n4291_o = n3890_o; + 63'b000000000000001000000000000000000000000000000000000000000000000: n4291_o = 1'b0; + 63'b000000000000000100000000000000000000000000000000000000000000000: n4291_o = 1'b0; + 63'b000000000000000010000000000000000000000000000000000000000000000: n4291_o = 1'b0; + 63'b000000000000000001000000000000000000000000000000000000000000000: n4291_o = n3705_o; + 63'b000000000000000000100000000000000000000000000000000000000000000: n4291_o = 1'b0; + 63'b000000000000000000010000000000000000000000000000000000000000000: n4291_o = 1'b0; + 63'b000000000000000000001000000000000000000000000000000000000000000: n4291_o = 1'b0; + 63'b000000000000000000000100000000000000000000000000000000000000000: n4291_o = 1'b0; + 63'b000000000000000000000010000000000000000000000000000000000000000: n4291_o = 1'b0; + 63'b000000000000000000000001000000000000000000000000000000000000000: n4291_o = 1'b0; + 63'b000000000000000000000000100000000000000000000000000000000000000: n4291_o = 1'b0; + 63'b000000000000000000000000010000000000000000000000000000000000000: n4291_o = 1'b0; + 63'b000000000000000000000000001000000000000000000000000000000000000: n4291_o = 1'b0; + 63'b000000000000000000000000000100000000000000000000000000000000000: n4291_o = 1'b0; + 63'b000000000000000000000000000010000000000000000000000000000000000: n4291_o = 1'b0; + 63'b000000000000000000000000000001000000000000000000000000000000000: n4291_o = 1'b0; + 63'b000000000000000000000000000000100000000000000000000000000000000: n4291_o = 1'b0; + 63'b000000000000000000000000000000010000000000000000000000000000000: n4291_o = 1'b0; + 63'b000000000000000000000000000000001000000000000000000000000000000: n4291_o = 1'b0; + 63'b000000000000000000000000000000000100000000000000000000000000000: n4291_o = 1'b0; + 63'b000000000000000000000000000000000010000000000000000000000000000: n4291_o = 1'b0; + 63'b000000000000000000000000000000000001000000000000000000000000000: n4291_o = 1'b0; + 63'b000000000000000000000000000000000000100000000000000000000000000: n4291_o = 1'b0; + 63'b000000000000000000000000000000000000010000000000000000000000000: n4291_o = 1'b0; + 63'b000000000000000000000000000000000000001000000000000000000000000: n4291_o = 1'b0; + 63'b000000000000000000000000000000000000000100000000000000000000000: n4291_o = 1'b0; + 63'b000000000000000000000000000000000000000010000000000000000000000: n4291_o = 1'b0; + 63'b000000000000000000000000000000000000000001000000000000000000000: n4291_o = 1'b0; + 63'b000000000000000000000000000000000000000000100000000000000000000: n4291_o = 1'b0; + 63'b000000000000000000000000000000000000000000010000000000000000000: n4291_o = 1'b0; + 63'b000000000000000000000000000000000000000000001000000000000000000: n4291_o = 1'b0; + 63'b000000000000000000000000000000000000000000000100000000000000000: n4291_o = 1'b0; + 63'b000000000000000000000000000000000000000000000010000000000000000: n4291_o = 1'b0; + 63'b000000000000000000000000000000000000000000000001000000000000000: n4291_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000100000000000000: n4291_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000010000000000000: n4291_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000001000000000000: n4291_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000100000000000: n4291_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000010000000000: n4291_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000001000000000: n4291_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000100000000: n4291_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000010000000: n4291_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000001000000: n4291_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000100000: n4291_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000010000: n4291_o = n2455_o; + 63'b000000000000000000000000000000000000000000000000000000000001000: n4291_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000000100: n4291_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000000010: n4291_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000000001: n4291_o = 1'b0; + default: n4291_o = 1'b0; + endcase + /* decoder.vhd:635:5 */ + always @* + case (n4277_o) + 63'b100000000000000000000000000000000000000000000000000000000000000: n4294_o = 1'b0; + 63'b010000000000000000000000000000000000000000000000000000000000000: n4294_o = 1'b0; + 63'b001000000000000000000000000000000000000000000000000000000000000: n4294_o = 1'b0; + 63'b000100000000000000000000000000000000000000000000000000000000000: n4294_o = 1'b0; + 63'b000010000000000000000000000000000000000000000000000000000000000: n4294_o = 1'b0; + 63'b000001000000000000000000000000000000000000000000000000000000000: n4294_o = 1'b0; + 63'b000000100000000000000000000000000000000000000000000000000000000: n4294_o = 1'b0; + 63'b000000010000000000000000000000000000000000000000000000000000000: n4294_o = 1'b0; + 63'b000000001000000000000000000000000000000000000000000000000000000: n4294_o = 1'b0; + 63'b000000000100000000000000000000000000000000000000000000000000000: n4294_o = 1'b0; + 63'b000000000010000000000000000000000000000000000000000000000000000: n4294_o = 1'b0; + 63'b000000000001000000000000000000000000000000000000000000000000000: n4294_o = 1'b0; + 63'b000000000000100000000000000000000000000000000000000000000000000: n4294_o = 1'b0; + 63'b000000000000010000000000000000000000000000000000000000000000000: n4294_o = 1'b0; + 63'b000000000000001000000000000000000000000000000000000000000000000: n4294_o = 1'b0; + 63'b000000000000000100000000000000000000000000000000000000000000000: n4294_o = 1'b0; + 63'b000000000000000010000000000000000000000000000000000000000000000: n4294_o = 1'b0; + 63'b000000000000000001000000000000000000000000000000000000000000000: n4294_o = 1'b0; + 63'b000000000000000000100000000000000000000000000000000000000000000: n4294_o = 1'b0; + 63'b000000000000000000010000000000000000000000000000000000000000000: n4294_o = 1'b0; + 63'b000000000000000000001000000000000000000000000000000000000000000: n4294_o = 1'b0; + 63'b000000000000000000000100000000000000000000000000000000000000000: n4294_o = 1'b0; + 63'b000000000000000000000010000000000000000000000000000000000000000: n4294_o = 1'b0; + 63'b000000000000000000000001000000000000000000000000000000000000000: n4294_o = 1'b0; + 63'b000000000000000000000000100000000000000000000000000000000000000: n4294_o = 1'b0; + 63'b000000000000000000000000010000000000000000000000000000000000000: n4294_o = 1'b0; + 63'b000000000000000000000000001000000000000000000000000000000000000: n4294_o = 1'b0; + 63'b000000000000000000000000000100000000000000000000000000000000000: n4294_o = 1'b0; + 63'b000000000000000000000000000010000000000000000000000000000000000: n4294_o = 1'b0; + 63'b000000000000000000000000000001000000000000000000000000000000000: n4294_o = 1'b0; + 63'b000000000000000000000000000000100000000000000000000000000000000: n4294_o = 1'b0; + 63'b000000000000000000000000000000010000000000000000000000000000000: n4294_o = 1'b0; + 63'b000000000000000000000000000000001000000000000000000000000000000: n4294_o = 1'b0; + 63'b000000000000000000000000000000000100000000000000000000000000000: n4294_o = 1'b0; + 63'b000000000000000000000000000000000010000000000000000000000000000: n4294_o = 1'b0; + 63'b000000000000000000000000000000000001000000000000000000000000000: n4294_o = 1'b0; + 63'b000000000000000000000000000000000000100000000000000000000000000: n4294_o = 1'b0; + 63'b000000000000000000000000000000000000010000000000000000000000000: n4294_o = 1'b0; + 63'b000000000000000000000000000000000000001000000000000000000000000: n4294_o = 1'b0; + 63'b000000000000000000000000000000000000000100000000000000000000000: n4294_o = 1'b0; + 63'b000000000000000000000000000000000000000010000000000000000000000: n4294_o = 1'b0; + 63'b000000000000000000000000000000000000000001000000000000000000000: n4294_o = 1'b0; + 63'b000000000000000000000000000000000000000000100000000000000000000: n4294_o = 1'b0; + 63'b000000000000000000000000000000000000000000010000000000000000000: n4294_o = 1'b0; + 63'b000000000000000000000000000000000000000000001000000000000000000: n4294_o = 1'b0; + 63'b000000000000000000000000000000000000000000000100000000000000000: n4294_o = 1'b0; + 63'b000000000000000000000000000000000000000000000010000000000000000: n4294_o = 1'b0; + 63'b000000000000000000000000000000000000000000000001000000000000000: n4294_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000100000000000000: n4294_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000010000000000000: n4294_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000001000000000000: n4294_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000100000000000: n4294_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000010000000000: n4294_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000001000000000: n4294_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000100000000: n4294_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000010000000: n4294_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000001000000: n4294_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000100000: n4294_o = n2562_o; + 63'b000000000000000000000000000000000000000000000000000000000010000: n4294_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000001000: n4294_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000000100: n4294_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000000010: n4294_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000000001: n4294_o = 1'b0; + default: n4294_o = 1'b0; + endcase + /* decoder.vhd:635:5 */ + always @* + case (n4277_o) + 63'b100000000000000000000000000000000000000000000000000000000000000: n4297_o = 1'b0; + 63'b010000000000000000000000000000000000000000000000000000000000000: n4297_o = 1'b0; + 63'b001000000000000000000000000000000000000000000000000000000000000: n4297_o = 1'b0; + 63'b000100000000000000000000000000000000000000000000000000000000000: n4297_o = 1'b0; + 63'b000010000000000000000000000000000000000000000000000000000000000: n4297_o = 1'b0; + 63'b000001000000000000000000000000000000000000000000000000000000000: n4297_o = 1'b0; + 63'b000000100000000000000000000000000000000000000000000000000000000: n4297_o = 1'b0; + 63'b000000010000000000000000000000000000000000000000000000000000000: n4297_o = 1'b0; + 63'b000000001000000000000000000000000000000000000000000000000000000: n4297_o = 1'b0; + 63'b000000000100000000000000000000000000000000000000000000000000000: n4297_o = 1'b0; + 63'b000000000010000000000000000000000000000000000000000000000000000: n4297_o = 1'b0; + 63'b000000000001000000000000000000000000000000000000000000000000000: n4297_o = 1'b0; + 63'b000000000000100000000000000000000000000000000000000000000000000: n4297_o = 1'b0; + 63'b000000000000010000000000000000000000000000000000000000000000000: n4297_o = 1'b0; + 63'b000000000000001000000000000000000000000000000000000000000000000: n4297_o = 1'b0; + 63'b000000000000000100000000000000000000000000000000000000000000000: n4297_o = 1'b0; + 63'b000000000000000010000000000000000000000000000000000000000000000: n4297_o = 1'b0; + 63'b000000000000000001000000000000000000000000000000000000000000000: n4297_o = 1'b0; + 63'b000000000000000000100000000000000000000000000000000000000000000: n4297_o = 1'b0; + 63'b000000000000000000010000000000000000000000000000000000000000000: n4297_o = 1'b0; + 63'b000000000000000000001000000000000000000000000000000000000000000: n4297_o = 1'b0; + 63'b000000000000000000000100000000000000000000000000000000000000000: n4297_o = 1'b0; + 63'b000000000000000000000010000000000000000000000000000000000000000: n4297_o = 1'b0; + 63'b000000000000000000000001000000000000000000000000000000000000000: n4297_o = 1'b0; + 63'b000000000000000000000000100000000000000000000000000000000000000: n4297_o = 1'b0; + 63'b000000000000000000000000010000000000000000000000000000000000000: n4297_o = 1'b0; + 63'b000000000000000000000000001000000000000000000000000000000000000: n4297_o = 1'b0; + 63'b000000000000000000000000000100000000000000000000000000000000000: n4297_o = 1'b0; + 63'b000000000000000000000000000010000000000000000000000000000000000: n4297_o = 1'b0; + 63'b000000000000000000000000000001000000000000000000000000000000000: n4297_o = 1'b0; + 63'b000000000000000000000000000000100000000000000000000000000000000: n4297_o = 1'b0; + 63'b000000000000000000000000000000010000000000000000000000000000000: n4297_o = 1'b0; + 63'b000000000000000000000000000000001000000000000000000000000000000: n4297_o = 1'b0; + 63'b000000000000000000000000000000000100000000000000000000000000000: n4297_o = 1'b0; + 63'b000000000000000000000000000000000010000000000000000000000000000: n4297_o = 1'b0; + 63'b000000000000000000000000000000000001000000000000000000000000000: n4297_o = 1'b0; + 63'b000000000000000000000000000000000000100000000000000000000000000: n4297_o = 1'b0; + 63'b000000000000000000000000000000000000010000000000000000000000000: n4297_o = 1'b0; + 63'b000000000000000000000000000000000000001000000000000000000000000: n4297_o = 1'b0; + 63'b000000000000000000000000000000000000000100000000000000000000000: n4297_o = 1'b0; + 63'b000000000000000000000000000000000000000010000000000000000000000: n4297_o = 1'b0; + 63'b000000000000000000000000000000000000000001000000000000000000000: n4297_o = 1'b0; + 63'b000000000000000000000000000000000000000000100000000000000000000: n4297_o = 1'b0; + 63'b000000000000000000000000000000000000000000010000000000000000000: n4297_o = 1'b0; + 63'b000000000000000000000000000000000000000000001000000000000000000: n4297_o = 1'b0; + 63'b000000000000000000000000000000000000000000000100000000000000000: n4297_o = n2859_o; + 63'b000000000000000000000000000000000000000000000010000000000000000: n4297_o = 1'b0; + 63'b000000000000000000000000000000000000000000000001000000000000000: n4297_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000100000000000000: n4297_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000010000000000000: n4297_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000001000000000000: n4297_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000100000000000: n4297_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000010000000000: n4297_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000001000000000: n4297_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000100000000: n4297_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000010000000: n4297_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000001000000: n4297_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000100000: n4297_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000010000: n4297_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000001000: n4297_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000000100: n4297_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000000010: n4297_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000000001: n4297_o = 1'b0; + default: n4297_o = 1'b0; + endcase + /* decoder.vhd:635:5 */ + always @* + case (n4277_o) + 63'b100000000000000000000000000000000000000000000000000000000000000: n4300_o = 1'b0; + 63'b010000000000000000000000000000000000000000000000000000000000000: n4300_o = 1'b0; + 63'b001000000000000000000000000000000000000000000000000000000000000: n4300_o = 1'b0; + 63'b000100000000000000000000000000000000000000000000000000000000000: n4300_o = 1'b0; + 63'b000010000000000000000000000000000000000000000000000000000000000: n4300_o = 1'b0; + 63'b000001000000000000000000000000000000000000000000000000000000000: n4300_o = 1'b0; + 63'b000000100000000000000000000000000000000000000000000000000000000: n4300_o = 1'b0; + 63'b000000010000000000000000000000000000000000000000000000000000000: n4300_o = 1'b0; + 63'b000000001000000000000000000000000000000000000000000000000000000: n4300_o = 1'b0; + 63'b000000000100000000000000000000000000000000000000000000000000000: n4300_o = 1'b0; + 63'b000000000010000000000000000000000000000000000000000000000000000: n4300_o = 1'b0; + 63'b000000000001000000000000000000000000000000000000000000000000000: n4300_o = 1'b0; + 63'b000000000000100000000000000000000000000000000000000000000000000: n4300_o = 1'b0; + 63'b000000000000010000000000000000000000000000000000000000000000000: n4300_o = 1'b0; + 63'b000000000000001000000000000000000000000000000000000000000000000: n4300_o = 1'b0; + 63'b000000000000000100000000000000000000000000000000000000000000000: n4300_o = 1'b0; + 63'b000000000000000010000000000000000000000000000000000000000000000: n4300_o = 1'b0; + 63'b000000000000000001000000000000000000000000000000000000000000000: n4300_o = 1'b0; + 63'b000000000000000000100000000000000000000000000000000000000000000: n4300_o = 1'b0; + 63'b000000000000000000010000000000000000000000000000000000000000000: n4300_o = 1'b0; + 63'b000000000000000000001000000000000000000000000000000000000000000: n4300_o = 1'b0; + 63'b000000000000000000000100000000000000000000000000000000000000000: n4300_o = 1'b0; + 63'b000000000000000000000010000000000000000000000000000000000000000: n4300_o = 1'b0; + 63'b000000000000000000000001000000000000000000000000000000000000000: n4300_o = 1'b0; + 63'b000000000000000000000000100000000000000000000000000000000000000: n4300_o = 1'b0; + 63'b000000000000000000000000010000000000000000000000000000000000000: n4300_o = 1'b0; + 63'b000000000000000000000000001000000000000000000000000000000000000: n4300_o = 1'b0; + 63'b000000000000000000000000000100000000000000000000000000000000000: n4300_o = 1'b0; + 63'b000000000000000000000000000010000000000000000000000000000000000: n4300_o = 1'b0; + 63'b000000000000000000000000000001000000000000000000000000000000000: n4300_o = 1'b0; + 63'b000000000000000000000000000000100000000000000000000000000000000: n4300_o = 1'b0; + 63'b000000000000000000000000000000010000000000000000000000000000000: n4300_o = 1'b0; + 63'b000000000000000000000000000000001000000000000000000000000000000: n4300_o = 1'b0; + 63'b000000000000000000000000000000000100000000000000000000000000000: n4300_o = 1'b0; + 63'b000000000000000000000000000000000010000000000000000000000000000: n4300_o = 1'b0; + 63'b000000000000000000000000000000000001000000000000000000000000000: n4300_o = 1'b0; + 63'b000000000000000000000000000000000000100000000000000000000000000: n4300_o = 1'b0; + 63'b000000000000000000000000000000000000010000000000000000000000000: n4300_o = 1'b0; + 63'b000000000000000000000000000000000000001000000000000000000000000: n4300_o = 1'b0; + 63'b000000000000000000000000000000000000000100000000000000000000000: n4300_o = 1'b0; + 63'b000000000000000000000000000000000000000010000000000000000000000: n4300_o = 1'b0; + 63'b000000000000000000000000000000000000000001000000000000000000000: n4300_o = 1'b0; + 63'b000000000000000000000000000000000000000000100000000000000000000: n4300_o = 1'b0; + 63'b000000000000000000000000000000000000000000010000000000000000000: n4300_o = 1'b0; + 63'b000000000000000000000000000000000000000000001000000000000000000: n4300_o = 1'b0; + 63'b000000000000000000000000000000000000000000000100000000000000000: n4300_o = n2861_o; + 63'b000000000000000000000000000000000000000000000010000000000000000: n4300_o = 1'b0; + 63'b000000000000000000000000000000000000000000000001000000000000000: n4300_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000100000000000000: n4300_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000010000000000000: n4300_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000001000000000000: n4300_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000100000000000: n4300_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000010000000000: n4300_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000001000000000: n4300_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000100000000: n4300_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000010000000: n4300_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000001000000: n4300_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000100000: n4300_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000010000: n4300_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000001000: n4300_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000000100: n4300_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000000010: n4300_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000000001: n4300_o = 1'b0; + default: n4300_o = 1'b0; + endcase + /* decoder.vhd:635:5 */ + always @* + case (n4277_o) + 63'b100000000000000000000000000000000000000000000000000000000000000: n4303_o = 1'b0; + 63'b010000000000000000000000000000000000000000000000000000000000000: n4303_o = 1'b0; + 63'b001000000000000000000000000000000000000000000000000000000000000: n4303_o = 1'b0; + 63'b000100000000000000000000000000000000000000000000000000000000000: n4303_o = 1'b0; + 63'b000010000000000000000000000000000000000000000000000000000000000: n4303_o = 1'b0; + 63'b000001000000000000000000000000000000000000000000000000000000000: n4303_o = 1'b0; + 63'b000000100000000000000000000000000000000000000000000000000000000: n4303_o = 1'b0; + 63'b000000010000000000000000000000000000000000000000000000000000000: n4303_o = 1'b0; + 63'b000000001000000000000000000000000000000000000000000000000000000: n4303_o = 1'b0; + 63'b000000000100000000000000000000000000000000000000000000000000000: n4303_o = 1'b0; + 63'b000000000010000000000000000000000000000000000000000000000000000: n4303_o = 1'b0; + 63'b000000000001000000000000000000000000000000000000000000000000000: n4303_o = 1'b0; + 63'b000000000000100000000000000000000000000000000000000000000000000: n4303_o = 1'b0; + 63'b000000000000010000000000000000000000000000000000000000000000000: n4303_o = 1'b0; + 63'b000000000000001000000000000000000000000000000000000000000000000: n4303_o = 1'b0; + 63'b000000000000000100000000000000000000000000000000000000000000000: n4303_o = 1'b0; + 63'b000000000000000010000000000000000000000000000000000000000000000: n4303_o = 1'b0; + 63'b000000000000000001000000000000000000000000000000000000000000000: n4303_o = 1'b0; + 63'b000000000000000000100000000000000000000000000000000000000000000: n4303_o = 1'b0; + 63'b000000000000000000010000000000000000000000000000000000000000000: n4303_o = 1'b0; + 63'b000000000000000000001000000000000000000000000000000000000000000: n4303_o = 1'b0; + 63'b000000000000000000000100000000000000000000000000000000000000000: n4303_o = 1'b0; + 63'b000000000000000000000010000000000000000000000000000000000000000: n4303_o = n3457_o; + 63'b000000000000000000000001000000000000000000000000000000000000000: n4303_o = 1'b0; + 63'b000000000000000000000000100000000000000000000000000000000000000: n4303_o = 1'b0; + 63'b000000000000000000000000010000000000000000000000000000000000000: n4303_o = 1'b0; + 63'b000000000000000000000000001000000000000000000000000000000000000: n4303_o = 1'b0; + 63'b000000000000000000000000000100000000000000000000000000000000000: n4303_o = 1'b0; + 63'b000000000000000000000000000010000000000000000000000000000000000: n4303_o = 1'b0; + 63'b000000000000000000000000000001000000000000000000000000000000000: n4303_o = 1'b0; + 63'b000000000000000000000000000000100000000000000000000000000000000: n4303_o = 1'b0; + 63'b000000000000000000000000000000010000000000000000000000000000000: n4303_o = 1'b0; + 63'b000000000000000000000000000000001000000000000000000000000000000: n4303_o = 1'b0; + 63'b000000000000000000000000000000000100000000000000000000000000000: n4303_o = 1'b0; + 63'b000000000000000000000000000000000010000000000000000000000000000: n4303_o = 1'b0; + 63'b000000000000000000000000000000000001000000000000000000000000000: n4303_o = 1'b0; + 63'b000000000000000000000000000000000000100000000000000000000000000: n4303_o = 1'b0; + 63'b000000000000000000000000000000000000010000000000000000000000000: n4303_o = 1'b0; + 63'b000000000000000000000000000000000000001000000000000000000000000: n4303_o = 1'b0; + 63'b000000000000000000000000000000000000000100000000000000000000000: n4303_o = 1'b0; + 63'b000000000000000000000000000000000000000010000000000000000000000: n4303_o = 1'b0; + 63'b000000000000000000000000000000000000000001000000000000000000000: n4303_o = 1'b0; + 63'b000000000000000000000000000000000000000000100000000000000000000: n4303_o = 1'b0; + 63'b000000000000000000000000000000000000000000010000000000000000000: n4303_o = 1'b0; + 63'b000000000000000000000000000000000000000000001000000000000000000: n4303_o = 1'b0; + 63'b000000000000000000000000000000000000000000000100000000000000000: n4303_o = 1'b0; + 63'b000000000000000000000000000000000000000000000010000000000000000: n4303_o = 1'b0; + 63'b000000000000000000000000000000000000000000000001000000000000000: n4303_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000100000000000000: n4303_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000010000000000000: n4303_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000001000000000000: n4303_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000100000000000: n4303_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000010000000000: n4303_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000001000000000: n4303_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000100000000: n4303_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000010000000: n4303_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000001000000: n4303_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000100000: n4303_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000010000: n4303_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000001000: n4303_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000000100: n4303_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000000010: n4303_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000000001: n4303_o = 1'b0; + default: n4303_o = 1'b0; + endcase + /* decoder.vhd:635:5 */ + always @* + case (n4277_o) + 63'b100000000000000000000000000000000000000000000000000000000000000: n4305_o = n2156_o; + 63'b010000000000000000000000000000000000000000000000000000000000000: n4305_o = n4236_o; + 63'b001000000000000000000000000000000000000000000000000000000000000: n4305_o = n4182_o; + 63'b000100000000000000000000000000000000000000000000000000000000000: n4305_o = n2156_o; + 63'b000010000000000000000000000000000000000000000000000000000000000: n4305_o = n2156_o; + 63'b000001000000000000000000000000000000000000000000000000000000000: n4305_o = n2156_o; + 63'b000000100000000000000000000000000000000000000000000000000000000: n4305_o = n2156_o; + 63'b000000010000000000000000000000000000000000000000000000000000000: n4305_o = n2156_o; + 63'b000000001000000000000000000000000000000000000000000000000000000: n4305_o = n2156_o; + 63'b000000000100000000000000000000000000000000000000000000000000000: n4305_o = n2156_o; + 63'b000000000010000000000000000000000000000000000000000000000000000: n4305_o = n4007_o; + 63'b000000000001000000000000000000000000000000000000000000000000000: n4305_o = n2156_o; + 63'b000000000000100000000000000000000000000000000000000000000000000: n4305_o = n2156_o; + 63'b000000000000010000000000000000000000000000000000000000000000000: n4305_o = n2156_o; + 63'b000000000000001000000000000000000000000000000000000000000000000: n4305_o = n2156_o; + 63'b000000000000000100000000000000000000000000000000000000000000000: n4305_o = n3756_o; + 63'b000000000000000010000000000000000000000000000000000000000000000: n4305_o = n2156_o; + 63'b000000000000000001000000000000000000000000000000000000000000000: n4305_o = n2156_o; + 63'b000000000000000000100000000000000000000000000000000000000000000: n4305_o = n2156_o; + 63'b000000000000000000010000000000000000000000000000000000000000000: n4305_o = n2156_o; + 63'b000000000000000000001000000000000000000000000000000000000000000: n4305_o = n2156_o; + 63'b000000000000000000000100000000000000000000000000000000000000000: n4305_o = n2156_o; + 63'b000000000000000000000010000000000000000000000000000000000000000: n4305_o = n2156_o; + 63'b000000000000000000000001000000000000000000000000000000000000000: n4305_o = n3430_o; + 63'b000000000000000000000000100000000000000000000000000000000000000: n4305_o = n3406_o; + 63'b000000000000000000000000010000000000000000000000000000000000000: n4305_o = n2156_o; + 63'b000000000000000000000000001000000000000000000000000000000000000: n4305_o = n2156_o; + 63'b000000000000000000000000000100000000000000000000000000000000000: n4305_o = n3347_o; + 63'b000000000000000000000000000010000000000000000000000000000000000: n4305_o = n2156_o; + 63'b000000000000000000000000000001000000000000000000000000000000000: n4305_o = n2156_o; + 63'b000000000000000000000000000000100000000000000000000000000000000: n4305_o = n2156_o; + 63'b000000000000000000000000000000010000000000000000000000000000000: n4305_o = n2156_o; + 63'b000000000000000000000000000000001000000000000000000000000000000: n4305_o = n2156_o; + 63'b000000000000000000000000000000000100000000000000000000000000000: n4305_o = n2156_o; + 63'b000000000000000000000000000000000010000000000000000000000000000: n4305_o = n2156_o; + 63'b000000000000000000000000000000000001000000000000000000000000000: n4305_o = n2156_o; + 63'b000000000000000000000000000000000000100000000000000000000000000: n4305_o = n2156_o; + 63'b000000000000000000000000000000000000010000000000000000000000000: n4305_o = n2156_o; + 63'b000000000000000000000000000000000000001000000000000000000000000: n4305_o = n2156_o; + 63'b000000000000000000000000000000000000000100000000000000000000000: n4305_o = n2156_o; + 63'b000000000000000000000000000000000000000010000000000000000000000: n4305_o = n2961_o; + 63'b000000000000000000000000000000000000000001000000000000000000000: n4305_o = n2156_o; + 63'b000000000000000000000000000000000000000000100000000000000000000: n4305_o = n2156_o; + 63'b000000000000000000000000000000000000000000010000000000000000000: n4305_o = n2156_o; + 63'b000000000000000000000000000000000000000000001000000000000000000: n4305_o = n2156_o; + 63'b000000000000000000000000000000000000000000000100000000000000000: n4305_o = n2156_o; + 63'b000000000000000000000000000000000000000000000010000000000000000: n4305_o = n2156_o; + 63'b000000000000000000000000000000000000000000000001000000000000000: n4305_o = n2156_o; + 63'b000000000000000000000000000000000000000000000000100000000000000: n4305_o = n2156_o; + 63'b000000000000000000000000000000000000000000000000010000000000000: n4305_o = n2156_o; + 63'b000000000000000000000000000000000000000000000000001000000000000: n4305_o = n2156_o; + 63'b000000000000000000000000000000000000000000000000000100000000000: n4305_o = n2156_o; + 63'b000000000000000000000000000000000000000000000000000010000000000: n4305_o = n2156_o; + 63'b000000000000000000000000000000000000000000000000000001000000000: n4305_o = n2156_o; + 63'b000000000000000000000000000000000000000000000000000000100000000: n4305_o = n2156_o; + 63'b000000000000000000000000000000000000000000000000000000010000000: n4305_o = n2156_o; + 63'b000000000000000000000000000000000000000000000000000000001000000: n4305_o = n2156_o; + 63'b000000000000000000000000000000000000000000000000000000000100000: n4305_o = n2563_o; + 63'b000000000000000000000000000000000000000000000000000000000010000: n4305_o = n2156_o; + 63'b000000000000000000000000000000000000000000000000000000000001000: n4305_o = n2156_o; + 63'b000000000000000000000000000000000000000000000000000000000000100: n4305_o = n2321_o; + 63'b000000000000000000000000000000000000000000000000000000000000010: n4305_o = n2156_o; + 63'b000000000000000000000000000000000000000000000000000000000000001: n4305_o = n2209_o; + default: n4305_o = n2156_o; + endcase + /* decoder.vhd:635:5 */ + always @* + case (n4277_o) + 63'b100000000000000000000000000000000000000000000000000000000000000: n4307_o = 1'b0; + 63'b010000000000000000000000000000000000000000000000000000000000000: n4307_o = n4239_o; + 63'b001000000000000000000000000000000000000000000000000000000000000: n4307_o = n4185_o; + 63'b000100000000000000000000000000000000000000000000000000000000000: n4307_o = 1'b0; + 63'b000010000000000000000000000000000000000000000000000000000000000: n4307_o = 1'b0; + 63'b000001000000000000000000000000000000000000000000000000000000000: n4307_o = 1'b0; + 63'b000000100000000000000000000000000000000000000000000000000000000: n4307_o = 1'b0; + 63'b000000010000000000000000000000000000000000000000000000000000000: n4307_o = 1'b0; + 63'b000000001000000000000000000000000000000000000000000000000000000: n4307_o = 1'b0; + 63'b000000000100000000000000000000000000000000000000000000000000000: n4307_o = 1'b0; + 63'b000000000010000000000000000000000000000000000000000000000000000: n4307_o = n4008_o; + 63'b000000000001000000000000000000000000000000000000000000000000000: n4307_o = 1'b0; + 63'b000000000000100000000000000000000000000000000000000000000000000: n4307_o = 1'b0; + 63'b000000000000010000000000000000000000000000000000000000000000000: n4307_o = 1'b0; + 63'b000000000000001000000000000000000000000000000000000000000000000: n4307_o = 1'b0; + 63'b000000000000000100000000000000000000000000000000000000000000000: n4307_o = n3759_o; + 63'b000000000000000010000000000000000000000000000000000000000000000: n4307_o = 1'b0; + 63'b000000000000000001000000000000000000000000000000000000000000000: n4307_o = n3707_o; + 63'b000000000000000000100000000000000000000000000000000000000000000: n4307_o = 1'b0; + 63'b000000000000000000010000000000000000000000000000000000000000000: n4307_o = 1'b0; + 63'b000000000000000000001000000000000000000000000000000000000000000: n4307_o = 1'b0; + 63'b000000000000000000000100000000000000000000000000000000000000000: n4307_o = 1'b0; + 63'b000000000000000000000010000000000000000000000000000000000000000: n4307_o = 1'b0; + 63'b000000000000000000000001000000000000000000000000000000000000000: n4307_o = n3439_o; + 63'b000000000000000000000000100000000000000000000000000000000000000: n4307_o = n3408_o; + 63'b000000000000000000000000010000000000000000000000000000000000000: n4307_o = 1'b0; + 63'b000000000000000000000000001000000000000000000000000000000000000: n4307_o = 1'b0; + 63'b000000000000000000000000000100000000000000000000000000000000000: n4307_o = n3350_o; + 63'b000000000000000000000000000010000000000000000000000000000000000: n4307_o = 1'b0; + 63'b000000000000000000000000000001000000000000000000000000000000000: n4307_o = 1'b0; + 63'b000000000000000000000000000000100000000000000000000000000000000: n4307_o = 1'b0; + 63'b000000000000000000000000000000010000000000000000000000000000000: n4307_o = 1'b0; + 63'b000000000000000000000000000000001000000000000000000000000000000: n4307_o = 1'b0; + 63'b000000000000000000000000000000000100000000000000000000000000000: n4307_o = 1'b0; + 63'b000000000000000000000000000000000010000000000000000000000000000: n4307_o = 1'b0; + 63'b000000000000000000000000000000000001000000000000000000000000000: n4307_o = 1'b0; + 63'b000000000000000000000000000000000000100000000000000000000000000: n4307_o = 1'b0; + 63'b000000000000000000000000000000000000010000000000000000000000000: n4307_o = 1'b0; + 63'b000000000000000000000000000000000000001000000000000000000000000: n4307_o = 1'b0; + 63'b000000000000000000000000000000000000000100000000000000000000000: n4307_o = 1'b0; + 63'b000000000000000000000000000000000000000010000000000000000000000: n4307_o = n2963_o; + 63'b000000000000000000000000000000000000000001000000000000000000000: n4307_o = 1'b0; + 63'b000000000000000000000000000000000000000000100000000000000000000: n4307_o = 1'b0; + 63'b000000000000000000000000000000000000000000010000000000000000000: n4307_o = 1'b0; + 63'b000000000000000000000000000000000000000000001000000000000000000: n4307_o = 1'b0; + 63'b000000000000000000000000000000000000000000000100000000000000000: n4307_o = 1'b0; + 63'b000000000000000000000000000000000000000000000010000000000000000: n4307_o = n2831_o; + 63'b000000000000000000000000000000000000000000000001000000000000000: n4307_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000100000000000000: n4307_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000010000000000000: n4307_o = n2746_o; + 63'b000000000000000000000000000000000000000000000000001000000000000: n4307_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000100000000000: n4307_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000010000000000: n4307_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000001000000000: n4307_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000100000000: n4307_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000010000000: n4307_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000001000000: n4307_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000100000: n4307_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000010000: n4307_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000001000: n4307_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000000100: n4307_o = n2324_o; + 63'b000000000000000000000000000000000000000000000000000000000000010: n4307_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000000001: n4307_o = n2212_o; + default: n4307_o = 1'b0; + endcase + /* decoder.vhd:635:5 */ + always @* + case (n4277_o) + 63'b100000000000000000000000000000000000000000000000000000000000000: n4310_o = 1'b0; + 63'b010000000000000000000000000000000000000000000000000000000000000: n4310_o = 1'b0; + 63'b001000000000000000000000000000000000000000000000000000000000000: n4310_o = 1'b0; + 63'b000100000000000000000000000000000000000000000000000000000000000: n4310_o = 1'b0; + 63'b000010000000000000000000000000000000000000000000000000000000000: n4310_o = 1'b0; + 63'b000001000000000000000000000000000000000000000000000000000000000: n4310_o = 1'b0; + 63'b000000100000000000000000000000000000000000000000000000000000000: n4310_o = 1'b0; + 63'b000000010000000000000000000000000000000000000000000000000000000: n4310_o = 1'b0; + 63'b000000001000000000000000000000000000000000000000000000000000000: n4310_o = 1'b0; + 63'b000000000100000000000000000000000000000000000000000000000000000: n4310_o = 1'b0; + 63'b000000000010000000000000000000000000000000000000000000000000000: n4310_o = 1'b0; + 63'b000000000001000000000000000000000000000000000000000000000000000: n4310_o = n3950_o; + 63'b000000000000100000000000000000000000000000000000000000000000000: n4310_o = 1'b0; + 63'b000000000000010000000000000000000000000000000000000000000000000: n4310_o = n3892_o; + 63'b000000000000001000000000000000000000000000000000000000000000000: n4310_o = 1'b0; + 63'b000000000000000100000000000000000000000000000000000000000000000: n4310_o = 1'b0; + 63'b000000000000000010000000000000000000000000000000000000000000000: n4310_o = 1'b0; + 63'b000000000000000001000000000000000000000000000000000000000000000: n4310_o = 1'b0; + 63'b000000000000000000100000000000000000000000000000000000000000000: n4310_o = 1'b0; + 63'b000000000000000000010000000000000000000000000000000000000000000: n4310_o = 1'b0; + 63'b000000000000000000001000000000000000000000000000000000000000000: n4310_o = 1'b0; + 63'b000000000000000000000100000000000000000000000000000000000000000: n4310_o = 1'b0; + 63'b000000000000000000000010000000000000000000000000000000000000000: n4310_o = 1'b0; + 63'b000000000000000000000001000000000000000000000000000000000000000: n4310_o = 1'b0; + 63'b000000000000000000000000100000000000000000000000000000000000000: n4310_o = 1'b0; + 63'b000000000000000000000000010000000000000000000000000000000000000: n4310_o = 1'b0; + 63'b000000000000000000000000001000000000000000000000000000000000000: n4310_o = 1'b0; + 63'b000000000000000000000000000100000000000000000000000000000000000: n4310_o = 1'b0; + 63'b000000000000000000000000000010000000000000000000000000000000000: n4310_o = 1'b0; + 63'b000000000000000000000000000001000000000000000000000000000000000: n4310_o = 1'b0; + 63'b000000000000000000000000000000100000000000000000000000000000000: n4310_o = 1'b0; + 63'b000000000000000000000000000000010000000000000000000000000000000: n4310_o = 1'b0; + 63'b000000000000000000000000000000001000000000000000000000000000000: n4310_o = 1'b0; + 63'b000000000000000000000000000000000100000000000000000000000000000: n4310_o = 1'b0; + 63'b000000000000000000000000000000000010000000000000000000000000000: n4310_o = 1'b0; + 63'b000000000000000000000000000000000001000000000000000000000000000: n4310_o = 1'b0; + 63'b000000000000000000000000000000000000100000000000000000000000000: n4310_o = 1'b0; + 63'b000000000000000000000000000000000000010000000000000000000000000: n4310_o = 1'b0; + 63'b000000000000000000000000000000000000001000000000000000000000000: n4310_o = 1'b0; + 63'b000000000000000000000000000000000000000100000000000000000000000: n4310_o = 1'b0; + 63'b000000000000000000000000000000000000000010000000000000000000000: n4310_o = 1'b0; + 63'b000000000000000000000000000000000000000001000000000000000000000: n4310_o = 1'b0; + 63'b000000000000000000000000000000000000000000100000000000000000000: n4310_o = 1'b0; + 63'b000000000000000000000000000000000000000000010000000000000000000: n4310_o = 1'b0; + 63'b000000000000000000000000000000000000000000001000000000000000000: n4310_o = 1'b0; + 63'b000000000000000000000000000000000000000000000100000000000000000: n4310_o = 1'b0; + 63'b000000000000000000000000000000000000000000000010000000000000000: n4310_o = 1'b0; + 63'b000000000000000000000000000000000000000000000001000000000000000: n4310_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000100000000000000: n4310_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000010000000000000: n4310_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000001000000000000: n4310_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000100000000000: n4310_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000010000000000: n4310_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000001000000000: n4310_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000100000000: n4310_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000010000000: n4310_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000001000000: n4310_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000100000: n4310_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000010000: n4310_o = n2457_o; + 63'b000000000000000000000000000000000000000000000000000000000001000: n4310_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000000100: n4310_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000000010: n4310_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000000001: n4310_o = 1'b0; + default: n4310_o = 1'b0; + endcase + /* decoder.vhd:635:5 */ + always @* + case (n4277_o) + 63'b100000000000000000000000000000000000000000000000000000000000000: n4313_o = 1'b0; + 63'b010000000000000000000000000000000000000000000000000000000000000: n4313_o = 1'b0; + 63'b001000000000000000000000000000000000000000000000000000000000000: n4313_o = 1'b0; + 63'b000100000000000000000000000000000000000000000000000000000000000: n4313_o = 1'b0; + 63'b000010000000000000000000000000000000000000000000000000000000000: n4313_o = 1'b0; + 63'b000001000000000000000000000000000000000000000000000000000000000: n4313_o = 1'b0; + 63'b000000100000000000000000000000000000000000000000000000000000000: n4313_o = 1'b0; + 63'b000000010000000000000000000000000000000000000000000000000000000: n4313_o = 1'b0; + 63'b000000001000000000000000000000000000000000000000000000000000000: n4313_o = 1'b0; + 63'b000000000100000000000000000000000000000000000000000000000000000: n4313_o = 1'b0; + 63'b000000000010000000000000000000000000000000000000000000000000000: n4313_o = 1'b0; + 63'b000000000001000000000000000000000000000000000000000000000000000: n4313_o = 1'b0; + 63'b000000000000100000000000000000000000000000000000000000000000000: n4313_o = 1'b0; + 63'b000000000000010000000000000000000000000000000000000000000000000: n4313_o = n3894_o; + 63'b000000000000001000000000000000000000000000000000000000000000000: n4313_o = 1'b0; + 63'b000000000000000100000000000000000000000000000000000000000000000: n4313_o = 1'b0; + 63'b000000000000000010000000000000000000000000000000000000000000000: n4313_o = 1'b0; + 63'b000000000000000001000000000000000000000000000000000000000000000: n4313_o = 1'b0; + 63'b000000000000000000100000000000000000000000000000000000000000000: n4313_o = 1'b0; + 63'b000000000000000000010000000000000000000000000000000000000000000: n4313_o = 1'b0; + 63'b000000000000000000001000000000000000000000000000000000000000000: n4313_o = 1'b0; + 63'b000000000000000000000100000000000000000000000000000000000000000: n4313_o = 1'b0; + 63'b000000000000000000000010000000000000000000000000000000000000000: n4313_o = 1'b0; + 63'b000000000000000000000001000000000000000000000000000000000000000: n4313_o = 1'b0; + 63'b000000000000000000000000100000000000000000000000000000000000000: n4313_o = 1'b0; + 63'b000000000000000000000000010000000000000000000000000000000000000: n4313_o = 1'b0; + 63'b000000000000000000000000001000000000000000000000000000000000000: n4313_o = 1'b0; + 63'b000000000000000000000000000100000000000000000000000000000000000: n4313_o = 1'b0; + 63'b000000000000000000000000000010000000000000000000000000000000000: n4313_o = 1'b0; + 63'b000000000000000000000000000001000000000000000000000000000000000: n4313_o = 1'b0; + 63'b000000000000000000000000000000100000000000000000000000000000000: n4313_o = 1'b0; + 63'b000000000000000000000000000000010000000000000000000000000000000: n4313_o = 1'b0; + 63'b000000000000000000000000000000001000000000000000000000000000000: n4313_o = 1'b0; + 63'b000000000000000000000000000000000100000000000000000000000000000: n4313_o = 1'b0; + 63'b000000000000000000000000000000000010000000000000000000000000000: n4313_o = 1'b0; + 63'b000000000000000000000000000000000001000000000000000000000000000: n4313_o = 1'b0; + 63'b000000000000000000000000000000000000100000000000000000000000000: n4313_o = 1'b0; + 63'b000000000000000000000000000000000000010000000000000000000000000: n4313_o = 1'b0; + 63'b000000000000000000000000000000000000001000000000000000000000000: n4313_o = 1'b0; + 63'b000000000000000000000000000000000000000100000000000000000000000: n4313_o = 1'b0; + 63'b000000000000000000000000000000000000000010000000000000000000000: n4313_o = 1'b0; + 63'b000000000000000000000000000000000000000001000000000000000000000: n4313_o = 1'b0; + 63'b000000000000000000000000000000000000000000100000000000000000000: n4313_o = 1'b0; + 63'b000000000000000000000000000000000000000000010000000000000000000: n4313_o = n2886_o; + 63'b000000000000000000000000000000000000000000001000000000000000000: n4313_o = 1'b0; + 63'b000000000000000000000000000000000000000000000100000000000000000: n4313_o = 1'b0; + 63'b000000000000000000000000000000000000000000000010000000000000000: n4313_o = 1'b0; + 63'b000000000000000000000000000000000000000000000001000000000000000: n4313_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000100000000000000: n4313_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000010000000000000: n4313_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000001000000000000: n4313_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000100000000000: n4313_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000010000000000: n4313_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000001000000000: n4313_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000100000000: n4313_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000010000000: n4313_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000001000000: n4313_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000100000: n4313_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000010000: n4313_o = n2459_o; + 63'b000000000000000000000000000000000000000000000000000000000001000: n4313_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000000100: n4313_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000000010: n4313_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000000001: n4313_o = 1'b0; + default: n4313_o = 1'b0; + endcase + /* decoder.vhd:635:5 */ + always @* + case (n4277_o) + 63'b100000000000000000000000000000000000000000000000000000000000000: n4316_o = 1'b0; + 63'b010000000000000000000000000000000000000000000000000000000000000: n4316_o = 1'b0; + 63'b001000000000000000000000000000000000000000000000000000000000000: n4316_o = 1'b0; + 63'b000100000000000000000000000000000000000000000000000000000000000: n4316_o = 1'b0; + 63'b000010000000000000000000000000000000000000000000000000000000000: n4316_o = 1'b0; + 63'b000001000000000000000000000000000000000000000000000000000000000: n4316_o = 1'b0; + 63'b000000100000000000000000000000000000000000000000000000000000000: n4316_o = 1'b0; + 63'b000000010000000000000000000000000000000000000000000000000000000: n4316_o = 1'b0; + 63'b000000001000000000000000000000000000000000000000000000000000000: n4316_o = 1'b0; + 63'b000000000100000000000000000000000000000000000000000000000000000: n4316_o = 1'b0; + 63'b000000000010000000000000000000000000000000000000000000000000000: n4316_o = 1'b0; + 63'b000000000001000000000000000000000000000000000000000000000000000: n4316_o = n3952_o; + 63'b000000000000100000000000000000000000000000000000000000000000000: n4316_o = 1'b0; + 63'b000000000000010000000000000000000000000000000000000000000000000: n4316_o = n3896_o; + 63'b000000000000001000000000000000000000000000000000000000000000000: n4316_o = 1'b0; + 63'b000000000000000100000000000000000000000000000000000000000000000: n4316_o = 1'b0; + 63'b000000000000000010000000000000000000000000000000000000000000000: n4316_o = 1'b0; + 63'b000000000000000001000000000000000000000000000000000000000000000: n4316_o = 1'b0; + 63'b000000000000000000100000000000000000000000000000000000000000000: n4316_o = 1'b0; + 63'b000000000000000000010000000000000000000000000000000000000000000: n4316_o = 1'b0; + 63'b000000000000000000001000000000000000000000000000000000000000000: n4316_o = 1'b0; + 63'b000000000000000000000100000000000000000000000000000000000000000: n4316_o = 1'b0; + 63'b000000000000000000000010000000000000000000000000000000000000000: n4316_o = 1'b0; + 63'b000000000000000000000001000000000000000000000000000000000000000: n4316_o = 1'b0; + 63'b000000000000000000000000100000000000000000000000000000000000000: n4316_o = 1'b0; + 63'b000000000000000000000000010000000000000000000000000000000000000: n4316_o = 1'b0; + 63'b000000000000000000000000001000000000000000000000000000000000000: n4316_o = 1'b0; + 63'b000000000000000000000000000100000000000000000000000000000000000: n4316_o = 1'b0; + 63'b000000000000000000000000000010000000000000000000000000000000000: n4316_o = 1'b0; + 63'b000000000000000000000000000001000000000000000000000000000000000: n4316_o = 1'b0; + 63'b000000000000000000000000000000100000000000000000000000000000000: n4316_o = 1'b0; + 63'b000000000000000000000000000000010000000000000000000000000000000: n4316_o = 1'b0; + 63'b000000000000000000000000000000001000000000000000000000000000000: n4316_o = 1'b0; + 63'b000000000000000000000000000000000100000000000000000000000000000: n4316_o = 1'b0; + 63'b000000000000000000000000000000000010000000000000000000000000000: n4316_o = 1'b0; + 63'b000000000000000000000000000000000001000000000000000000000000000: n4316_o = 1'b0; + 63'b000000000000000000000000000000000000100000000000000000000000000: n4316_o = 1'b0; + 63'b000000000000000000000000000000000000010000000000000000000000000: n4316_o = 1'b0; + 63'b000000000000000000000000000000000000001000000000000000000000000: n4316_o = 1'b0; + 63'b000000000000000000000000000000000000000100000000000000000000000: n4316_o = 1'b0; + 63'b000000000000000000000000000000000000000010000000000000000000000: n4316_o = 1'b0; + 63'b000000000000000000000000000000000000000001000000000000000000000: n4316_o = 1'b0; + 63'b000000000000000000000000000000000000000000100000000000000000000: n4316_o = 1'b0; + 63'b000000000000000000000000000000000000000000010000000000000000000: n4316_o = 1'b0; + 63'b000000000000000000000000000000000000000000001000000000000000000: n4316_o = 1'b0; + 63'b000000000000000000000000000000000000000000000100000000000000000: n4316_o = 1'b0; + 63'b000000000000000000000000000000000000000000000010000000000000000: n4316_o = 1'b0; + 63'b000000000000000000000000000000000000000000000001000000000000000: n4316_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000100000000000000: n4316_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000010000000000000: n4316_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000001000000000000: n4316_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000100000000000: n4316_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000010000000000: n4316_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000001000000000: n4316_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000100000000: n4316_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000010000000: n4316_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000001000000: n4316_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000100000: n4316_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000010000: n4316_o = n2461_o; + 63'b000000000000000000000000000000000000000000000000000000000001000: n4316_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000000100: n4316_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000000010: n4316_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000000001: n4316_o = 1'b0; + default: n4316_o = 1'b0; + endcase + /* decoder.vhd:635:5 */ + always @* + case (n4277_o) + 63'b100000000000000000000000000000000000000000000000000000000000000: n4319_o = 1'b0; + 63'b010000000000000000000000000000000000000000000000000000000000000: n4319_o = 1'b0; + 63'b001000000000000000000000000000000000000000000000000000000000000: n4319_o = 1'b0; + 63'b000100000000000000000000000000000000000000000000000000000000000: n4319_o = 1'b0; + 63'b000010000000000000000000000000000000000000000000000000000000000: n4319_o = 1'b0; + 63'b000001000000000000000000000000000000000000000000000000000000000: n4319_o = 1'b0; + 63'b000000100000000000000000000000000000000000000000000000000000000: n4319_o = 1'b0; + 63'b000000010000000000000000000000000000000000000000000000000000000: n4319_o = 1'b0; + 63'b000000001000000000000000000000000000000000000000000000000000000: n4319_o = 1'b0; + 63'b000000000100000000000000000000000000000000000000000000000000000: n4319_o = 1'b0; + 63'b000000000010000000000000000000000000000000000000000000000000000: n4319_o = 1'b0; + 63'b000000000001000000000000000000000000000000000000000000000000000: n4319_o = 1'b0; + 63'b000000000000100000000000000000000000000000000000000000000000000: n4319_o = 1'b0; + 63'b000000000000010000000000000000000000000000000000000000000000000: n4319_o = 1'b0; + 63'b000000000000001000000000000000000000000000000000000000000000000: n4319_o = 1'b0; + 63'b000000000000000100000000000000000000000000000000000000000000000: n4319_o = 1'b0; + 63'b000000000000000010000000000000000000000000000000000000000000000: n4319_o = 1'b0; + 63'b000000000000000001000000000000000000000000000000000000000000000: n4319_o = 1'b0; + 63'b000000000000000000100000000000000000000000000000000000000000000: n4319_o = 1'b0; + 63'b000000000000000000010000000000000000000000000000000000000000000: n4319_o = n3607_o; + 63'b000000000000000000001000000000000000000000000000000000000000000: n4319_o = n3546_o; + 63'b000000000000000000000100000000000000000000000000000000000000000: n4319_o = 1'b0; + 63'b000000000000000000000010000000000000000000000000000000000000000: n4319_o = 1'b0; + 63'b000000000000000000000001000000000000000000000000000000000000000: n4319_o = 1'b0; + 63'b000000000000000000000000100000000000000000000000000000000000000: n4319_o = 1'b0; + 63'b000000000000000000000000010000000000000000000000000000000000000: n4319_o = 1'b0; + 63'b000000000000000000000000001000000000000000000000000000000000000: n4319_o = 1'b0; + 63'b000000000000000000000000000100000000000000000000000000000000000: n4319_o = 1'b0; + 63'b000000000000000000000000000010000000000000000000000000000000000: n4319_o = 1'b0; + 63'b000000000000000000000000000001000000000000000000000000000000000: n4319_o = 1'b0; + 63'b000000000000000000000000000000100000000000000000000000000000000: n4319_o = 1'b0; + 63'b000000000000000000000000000000010000000000000000000000000000000: n4319_o = 1'b0; + 63'b000000000000000000000000000000001000000000000000000000000000000: n4319_o = 1'b0; + 63'b000000000000000000000000000000000100000000000000000000000000000: n4319_o = 1'b0; + 63'b000000000000000000000000000000000010000000000000000000000000000: n4319_o = 1'b0; + 63'b000000000000000000000000000000000001000000000000000000000000000: n4319_o = 1'b0; + 63'b000000000000000000000000000000000000100000000000000000000000000: n4319_o = 1'b0; + 63'b000000000000000000000000000000000000010000000000000000000000000: n4319_o = 1'b0; + 63'b000000000000000000000000000000000000001000000000000000000000000: n4319_o = 1'b0; + 63'b000000000000000000000000000000000000000100000000000000000000000: n4319_o = 1'b0; + 63'b000000000000000000000000000000000000000010000000000000000000000: n4319_o = 1'b0; + 63'b000000000000000000000000000000000000000001000000000000000000000: n4319_o = 1'b0; + 63'b000000000000000000000000000000000000000000100000000000000000000: n4319_o = 1'b0; + 63'b000000000000000000000000000000000000000000010000000000000000000: n4319_o = 1'b0; + 63'b000000000000000000000000000000000000000000001000000000000000000: n4319_o = 1'b0; + 63'b000000000000000000000000000000000000000000000100000000000000000: n4319_o = 1'b0; + 63'b000000000000000000000000000000000000000000000010000000000000000: n4319_o = 1'b0; + 63'b000000000000000000000000000000000000000000000001000000000000000: n4319_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000100000000000000: n4319_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000010000000000000: n4319_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000001000000000000: n4319_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000100000000000: n4319_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000010000000000: n4319_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000001000000000: n4319_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000100000000: n4319_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000010000000: n4319_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000001000000: n4319_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000100000: n4319_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000010000: n4319_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000001000: n4319_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000000100: n4319_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000000010: n4319_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000000001: n4319_o = 1'b0; + default: n4319_o = 1'b0; + endcase + /* decoder.vhd:635:5 */ + always @* + case (n4277_o) + 63'b100000000000000000000000000000000000000000000000000000000000000: n4322_o = 1'b0; + 63'b010000000000000000000000000000000000000000000000000000000000000: n4322_o = 1'b0; + 63'b001000000000000000000000000000000000000000000000000000000000000: n4322_o = 1'b0; + 63'b000100000000000000000000000000000000000000000000000000000000000: n4322_o = 1'b0; + 63'b000010000000000000000000000000000000000000000000000000000000000: n4322_o = 1'b0; + 63'b000001000000000000000000000000000000000000000000000000000000000: n4322_o = 1'b0; + 63'b000000100000000000000000000000000000000000000000000000000000000: n4322_o = 1'b0; + 63'b000000010000000000000000000000000000000000000000000000000000000: n4322_o = 1'b0; + 63'b000000001000000000000000000000000000000000000000000000000000000: n4322_o = 1'b0; + 63'b000000000100000000000000000000000000000000000000000000000000000: n4322_o = 1'b0; + 63'b000000000010000000000000000000000000000000000000000000000000000: n4322_o = 1'b0; + 63'b000000000001000000000000000000000000000000000000000000000000000: n4322_o = 1'b0; + 63'b000000000000100000000000000000000000000000000000000000000000000: n4322_o = 1'b0; + 63'b000000000000010000000000000000000000000000000000000000000000000: n4322_o = n3898_o; + 63'b000000000000001000000000000000000000000000000000000000000000000: n4322_o = 1'b0; + 63'b000000000000000100000000000000000000000000000000000000000000000: n4322_o = 1'b0; + 63'b000000000000000010000000000000000000000000000000000000000000000: n4322_o = 1'b0; + 63'b000000000000000001000000000000000000000000000000000000000000000: n4322_o = 1'b0; + 63'b000000000000000000100000000000000000000000000000000000000000000: n4322_o = 1'b0; + 63'b000000000000000000010000000000000000000000000000000000000000000: n4322_o = n3609_o; + 63'b000000000000000000001000000000000000000000000000000000000000000: n4322_o = 1'b0; + 63'b000000000000000000000100000000000000000000000000000000000000000: n4322_o = 1'b0; + 63'b000000000000000000000010000000000000000000000000000000000000000: n4322_o = 1'b0; + 63'b000000000000000000000001000000000000000000000000000000000000000: n4322_o = 1'b0; + 63'b000000000000000000000000100000000000000000000000000000000000000: n4322_o = 1'b0; + 63'b000000000000000000000000010000000000000000000000000000000000000: n4322_o = 1'b0; + 63'b000000000000000000000000001000000000000000000000000000000000000: n4322_o = 1'b0; + 63'b000000000000000000000000000100000000000000000000000000000000000: n4322_o = 1'b0; + 63'b000000000000000000000000000010000000000000000000000000000000000: n4322_o = 1'b0; + 63'b000000000000000000000000000001000000000000000000000000000000000: n4322_o = 1'b0; + 63'b000000000000000000000000000000100000000000000000000000000000000: n4322_o = 1'b0; + 63'b000000000000000000000000000000010000000000000000000000000000000: n4322_o = 1'b0; + 63'b000000000000000000000000000000001000000000000000000000000000000: n4322_o = 1'b0; + 63'b000000000000000000000000000000000100000000000000000000000000000: n4322_o = 1'b0; + 63'b000000000000000000000000000000000010000000000000000000000000000: n4322_o = 1'b0; + 63'b000000000000000000000000000000000001000000000000000000000000000: n4322_o = 1'b0; + 63'b000000000000000000000000000000000000100000000000000000000000000: n4322_o = 1'b0; + 63'b000000000000000000000000000000000000010000000000000000000000000: n4322_o = 1'b0; + 63'b000000000000000000000000000000000000001000000000000000000000000: n4322_o = 1'b0; + 63'b000000000000000000000000000000000000000100000000000000000000000: n4322_o = 1'b0; + 63'b000000000000000000000000000000000000000010000000000000000000000: n4322_o = 1'b0; + 63'b000000000000000000000000000000000000000001000000000000000000000: n4322_o = 1'b0; + 63'b000000000000000000000000000000000000000000100000000000000000000: n4322_o = 1'b0; + 63'b000000000000000000000000000000000000000000010000000000000000000: n4322_o = n2888_o; + 63'b000000000000000000000000000000000000000000001000000000000000000: n4322_o = 1'b0; + 63'b000000000000000000000000000000000000000000000100000000000000000: n4322_o = 1'b0; + 63'b000000000000000000000000000000000000000000000010000000000000000: n4322_o = 1'b0; + 63'b000000000000000000000000000000000000000000000001000000000000000: n4322_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000100000000000000: n4322_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000010000000000000: n4322_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000001000000000000: n4322_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000100000000000: n4322_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000010000000000: n4322_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000001000000000: n4322_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000100000000: n4322_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000010000000: n4322_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000001000000: n4322_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000100000: n4322_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000010000: n4322_o = n2463_o; + 63'b000000000000000000000000000000000000000000000000000000000001000: n4322_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000000100: n4322_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000000010: n4322_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000000001: n4322_o = 1'b0; + default: n4322_o = 1'b0; + endcase + /* decoder.vhd:635:5 */ + always @* + case (n4277_o) + 63'b100000000000000000000000000000000000000000000000000000000000000: n4325_o = 1'b0; + 63'b010000000000000000000000000000000000000000000000000000000000000: n4325_o = 1'b0; + 63'b001000000000000000000000000000000000000000000000000000000000000: n4325_o = 1'b0; + 63'b000100000000000000000000000000000000000000000000000000000000000: n4325_o = 1'b0; + 63'b000010000000000000000000000000000000000000000000000000000000000: n4325_o = 1'b0; + 63'b000001000000000000000000000000000000000000000000000000000000000: n4325_o = 1'b0; + 63'b000000100000000000000000000000000000000000000000000000000000000: n4325_o = 1'b0; + 63'b000000010000000000000000000000000000000000000000000000000000000: n4325_o = 1'b0; + 63'b000000001000000000000000000000000000000000000000000000000000000: n4325_o = 1'b0; + 63'b000000000100000000000000000000000000000000000000000000000000000: n4325_o = 1'b0; + 63'b000000000010000000000000000000000000000000000000000000000000000: n4325_o = 1'b0; + 63'b000000000001000000000000000000000000000000000000000000000000000: n4325_o = 1'b0; + 63'b000000000000100000000000000000000000000000000000000000000000000: n4325_o = 1'b0; + 63'b000000000000010000000000000000000000000000000000000000000000000: n4325_o = 1'b0; + 63'b000000000000001000000000000000000000000000000000000000000000000: n4325_o = 1'b0; + 63'b000000000000000100000000000000000000000000000000000000000000000: n4325_o = 1'b0; + 63'b000000000000000010000000000000000000000000000000000000000000000: n4325_o = 1'b0; + 63'b000000000000000001000000000000000000000000000000000000000000000: n4325_o = 1'b0; + 63'b000000000000000000100000000000000000000000000000000000000000000: n4325_o = 1'b0; + 63'b000000000000000000010000000000000000000000000000000000000000000: n4325_o = n3611_o; + 63'b000000000000000000001000000000000000000000000000000000000000000: n4325_o = 1'b0; + 63'b000000000000000000000100000000000000000000000000000000000000000: n4325_o = 1'b0; + 63'b000000000000000000000010000000000000000000000000000000000000000: n4325_o = 1'b0; + 63'b000000000000000000000001000000000000000000000000000000000000000: n4325_o = 1'b0; + 63'b000000000000000000000000100000000000000000000000000000000000000: n4325_o = 1'b0; + 63'b000000000000000000000000010000000000000000000000000000000000000: n4325_o = 1'b0; + 63'b000000000000000000000000001000000000000000000000000000000000000: n4325_o = 1'b0; + 63'b000000000000000000000000000100000000000000000000000000000000000: n4325_o = 1'b0; + 63'b000000000000000000000000000010000000000000000000000000000000000: n4325_o = 1'b0; + 63'b000000000000000000000000000001000000000000000000000000000000000: n4325_o = 1'b0; + 63'b000000000000000000000000000000100000000000000000000000000000000: n4325_o = 1'b0; + 63'b000000000000000000000000000000010000000000000000000000000000000: n4325_o = 1'b0; + 63'b000000000000000000000000000000001000000000000000000000000000000: n4325_o = 1'b0; + 63'b000000000000000000000000000000000100000000000000000000000000000: n4325_o = 1'b0; + 63'b000000000000000000000000000000000010000000000000000000000000000: n4325_o = 1'b0; + 63'b000000000000000000000000000000000001000000000000000000000000000: n4325_o = 1'b0; + 63'b000000000000000000000000000000000000100000000000000000000000000: n4325_o = 1'b0; + 63'b000000000000000000000000000000000000010000000000000000000000000: n4325_o = 1'b0; + 63'b000000000000000000000000000000000000001000000000000000000000000: n4325_o = 1'b0; + 63'b000000000000000000000000000000000000000100000000000000000000000: n4325_o = 1'b0; + 63'b000000000000000000000000000000000000000010000000000000000000000: n4325_o = 1'b0; + 63'b000000000000000000000000000000000000000001000000000000000000000: n4325_o = 1'b0; + 63'b000000000000000000000000000000000000000000100000000000000000000: n4325_o = 1'b0; + 63'b000000000000000000000000000000000000000000010000000000000000000: n4325_o = 1'b0; + 63'b000000000000000000000000000000000000000000001000000000000000000: n4325_o = 1'b0; + 63'b000000000000000000000000000000000000000000000100000000000000000: n4325_o = 1'b0; + 63'b000000000000000000000000000000000000000000000010000000000000000: n4325_o = 1'b0; + 63'b000000000000000000000000000000000000000000000001000000000000000: n4325_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000100000000000000: n4325_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000010000000000000: n4325_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000001000000000000: n4325_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000100000000000: n4325_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000010000000000: n4325_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000001000000000: n4325_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000100000000: n4325_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000010000000: n4325_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000001000000: n4325_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000100000: n4325_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000010000: n4325_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000001000: n4325_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000000100: n4325_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000000010: n4325_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000000001: n4325_o = 1'b0; + default: n4325_o = 1'b0; + endcase + /* decoder.vhd:635:5 */ + always @* + case (n4277_o) + 63'b100000000000000000000000000000000000000000000000000000000000000: n4328_o = 1'b0; + 63'b010000000000000000000000000000000000000000000000000000000000000: n4328_o = 1'b0; + 63'b001000000000000000000000000000000000000000000000000000000000000: n4328_o = 1'b0; + 63'b000100000000000000000000000000000000000000000000000000000000000: n4328_o = 1'b0; + 63'b000010000000000000000000000000000000000000000000000000000000000: n4328_o = 1'b0; + 63'b000001000000000000000000000000000000000000000000000000000000000: n4328_o = 1'b0; + 63'b000000100000000000000000000000000000000000000000000000000000000: n4328_o = 1'b0; + 63'b000000010000000000000000000000000000000000000000000000000000000: n4328_o = 1'b0; + 63'b000000001000000000000000000000000000000000000000000000000000000: n4328_o = 1'b0; + 63'b000000000100000000000000000000000000000000000000000000000000000: n4328_o = 1'b0; + 63'b000000000010000000000000000000000000000000000000000000000000000: n4328_o = n4010_o; + 63'b000000000001000000000000000000000000000000000000000000000000000: n4328_o = 1'b0; + 63'b000000000000100000000000000000000000000000000000000000000000000: n4328_o = 1'b0; + 63'b000000000000010000000000000000000000000000000000000000000000000: n4328_o = 1'b0; + 63'b000000000000001000000000000000000000000000000000000000000000000: n4328_o = 1'b0; + 63'b000000000000000100000000000000000000000000000000000000000000000: n4328_o = 1'b0; + 63'b000000000000000010000000000000000000000000000000000000000000000: n4328_o = 1'b0; + 63'b000000000000000001000000000000000000000000000000000000000000000: n4328_o = 1'b0; + 63'b000000000000000000100000000000000000000000000000000000000000000: n4328_o = 1'b0; + 63'b000000000000000000010000000000000000000000000000000000000000000: n4328_o = 1'b0; + 63'b000000000000000000001000000000000000000000000000000000000000000: n4328_o = 1'b0; + 63'b000000000000000000000100000000000000000000000000000000000000000: n4328_o = 1'b0; + 63'b000000000000000000000010000000000000000000000000000000000000000: n4328_o = 1'b0; + 63'b000000000000000000000001000000000000000000000000000000000000000: n4328_o = 1'b0; + 63'b000000000000000000000000100000000000000000000000000000000000000: n4328_o = 1'b0; + 63'b000000000000000000000000010000000000000000000000000000000000000: n4328_o = 1'b0; + 63'b000000000000000000000000001000000000000000000000000000000000000: n4328_o = 1'b0; + 63'b000000000000000000000000000100000000000000000000000000000000000: n4328_o = 1'b0; + 63'b000000000000000000000000000010000000000000000000000000000000000: n4328_o = 1'b0; + 63'b000000000000000000000000000001000000000000000000000000000000000: n4328_o = n3299_o; + 63'b000000000000000000000000000000100000000000000000000000000000000: n4328_o = n3263_o; + 63'b000000000000000000000000000000010000000000000000000000000000000: n4328_o = n3232_o; + 63'b000000000000000000000000000000001000000000000000000000000000000: n4328_o = n3198_o; + 63'b000000000000000000000000000000000100000000000000000000000000000: n4328_o = n3172_o; + 63'b000000000000000000000000000000000010000000000000000000000000000: n4328_o = n3146_o; + 63'b000000000000000000000000000000000001000000000000000000000000000: n4328_o = n3120_o; + 63'b000000000000000000000000000000000000100000000000000000000000000: n4328_o = n3091_o; + 63'b000000000000000000000000000000000000010000000000000000000000000: n4328_o = n3060_o; + 63'b000000000000000000000000000000000000001000000000000000000000000: n4328_o = n3026_o; + 63'b000000000000000000000000000000000000000100000000000000000000000: n4328_o = n2997_o; + 63'b000000000000000000000000000000000000000010000000000000000000000: n4328_o = 1'b0; + 63'b000000000000000000000000000000000000000001000000000000000000000: n4328_o = 1'b0; + 63'b000000000000000000000000000000000000000000100000000000000000000: n4328_o = 1'b0; + 63'b000000000000000000000000000000000000000000010000000000000000000: n4328_o = 1'b0; + 63'b000000000000000000000000000000000000000000001000000000000000000: n4328_o = 1'b0; + 63'b000000000000000000000000000000000000000000000100000000000000000: n4328_o = 1'b0; + 63'b000000000000000000000000000000000000000000000010000000000000000: n4328_o = n2833_o; + 63'b000000000000000000000000000000000000000000000001000000000000000: n4328_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000100000000000000: n4328_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000010000000000000: n4328_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000001000000000000: n4328_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000100000000000: n4328_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000010000000000: n4328_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000001000000000: n4328_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000100000000: n4328_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000010000000: n4328_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000001000000: n4328_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000100000: n4328_o = n2565_o; + 63'b000000000000000000000000000000000000000000000000000000000010000: n4328_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000001000: n4328_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000000100: n4328_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000000010: n4328_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000000001: n4328_o = 1'b0; + default: n4328_o = 1'b0; + endcase + /* decoder.vhd:635:5 */ + always @* + case (n4277_o) + 63'b100000000000000000000000000000000000000000000000000000000000000: n4331_o = 1'b0; + 63'b010000000000000000000000000000000000000000000000000000000000000: n4331_o = 1'b0; + 63'b001000000000000000000000000000000000000000000000000000000000000: n4331_o = 1'b0; + 63'b000100000000000000000000000000000000000000000000000000000000000: n4331_o = 1'b0; + 63'b000010000000000000000000000000000000000000000000000000000000000: n4331_o = 1'b0; + 63'b000001000000000000000000000000000000000000000000000000000000000: n4331_o = 1'b0; + 63'b000000100000000000000000000000000000000000000000000000000000000: n4331_o = 1'b0; + 63'b000000010000000000000000000000000000000000000000000000000000000: n4331_o = 1'b0; + 63'b000000001000000000000000000000000000000000000000000000000000000: n4331_o = 1'b0; + 63'b000000000100000000000000000000000000000000000000000000000000000: n4331_o = 1'b0; + 63'b000000000010000000000000000000000000000000000000000000000000000: n4331_o = 1'b0; + 63'b000000000001000000000000000000000000000000000000000000000000000: n4331_o = 1'b0; + 63'b000000000000100000000000000000000000000000000000000000000000000: n4331_o = 1'b0; + 63'b000000000000010000000000000000000000000000000000000000000000000: n4331_o = 1'b0; + 63'b000000000000001000000000000000000000000000000000000000000000000: n4331_o = 1'b0; + 63'b000000000000000100000000000000000000000000000000000000000000000: n4331_o = 1'b0; + 63'b000000000000000010000000000000000000000000000000000000000000000: n4331_o = 1'b0; + 63'b000000000000000001000000000000000000000000000000000000000000000: n4331_o = 1'b0; + 63'b000000000000000000100000000000000000000000000000000000000000000: n4331_o = 1'b0; + 63'b000000000000000000010000000000000000000000000000000000000000000: n4331_o = 1'b0; + 63'b000000000000000000001000000000000000000000000000000000000000000: n4331_o = 1'b0; + 63'b000000000000000000000100000000000000000000000000000000000000000: n4331_o = 1'b0; + 63'b000000000000000000000010000000000000000000000000000000000000000: n4331_o = 1'b0; + 63'b000000000000000000000001000000000000000000000000000000000000000: n4331_o = 1'b0; + 63'b000000000000000000000000100000000000000000000000000000000000000: n4331_o = 1'b0; + 63'b000000000000000000000000010000000000000000000000000000000000000: n4331_o = 1'b0; + 63'b000000000000000000000000001000000000000000000000000000000000000: n4331_o = 1'b0; + 63'b000000000000000000000000000100000000000000000000000000000000000: n4331_o = 1'b0; + 63'b000000000000000000000000000010000000000000000000000000000000000: n4331_o = 1'b0; + 63'b000000000000000000000000000001000000000000000000000000000000000: n4331_o = 1'b0; + 63'b000000000000000000000000000000100000000000000000000000000000000: n4331_o = 1'b0; + 63'b000000000000000000000000000000010000000000000000000000000000000: n4331_o = 1'b0; + 63'b000000000000000000000000000000001000000000000000000000000000000: n4331_o = 1'b0; + 63'b000000000000000000000000000000000100000000000000000000000000000: n4331_o = 1'b0; + 63'b000000000000000000000000000000000010000000000000000000000000000: n4331_o = 1'b0; + 63'b000000000000000000000000000000000001000000000000000000000000000: n4331_o = 1'b0; + 63'b000000000000000000000000000000000000100000000000000000000000000: n4331_o = 1'b0; + 63'b000000000000000000000000000000000000010000000000000000000000000: n4331_o = 1'b0; + 63'b000000000000000000000000000000000000001000000000000000000000000: n4331_o = 1'b0; + 63'b000000000000000000000000000000000000000100000000000000000000000: n4331_o = 1'b0; + 63'b000000000000000000000000000000000000000010000000000000000000000: n4331_o = 1'b0; + 63'b000000000000000000000000000000000000000001000000000000000000000: n4331_o = 1'b0; + 63'b000000000000000000000000000000000000000000100000000000000000000: n4331_o = 1'b0; + 63'b000000000000000000000000000000000000000000010000000000000000000: n4331_o = 1'b0; + 63'b000000000000000000000000000000000000000000001000000000000000000: n4331_o = 1'b0; + 63'b000000000000000000000000000000000000000000000100000000000000000: n4331_o = 1'b0; + 63'b000000000000000000000000000000000000000000000010000000000000000: n4331_o = 1'b0; + 63'b000000000000000000000000000000000000000000000001000000000000000: n4331_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000100000000000000: n4331_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000010000000000000: n4331_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000001000000000000: n4331_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000100000000000: n4331_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000010000000000: n4331_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000001000000000: n4331_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000100000000: n4331_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000010000000: n4331_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000001000000: n4331_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000100000: n4331_o = n2567_o; + 63'b000000000000000000000000000000000000000000000000000000000010000: n4331_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000001000: n4331_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000000100: n4331_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000000010: n4331_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000000001: n4331_o = 1'b0; + default: n4331_o = 1'b0; + endcase + /* decoder.vhd:635:5 */ + always @* + case (n4277_o) + 63'b100000000000000000000000000000000000000000000000000000000000000: n4334_o = 1'b0; + 63'b010000000000000000000000000000000000000000000000000000000000000: n4334_o = 1'b0; + 63'b001000000000000000000000000000000000000000000000000000000000000: n4334_o = 1'b0; + 63'b000100000000000000000000000000000000000000000000000000000000000: n4334_o = 1'b0; + 63'b000010000000000000000000000000000000000000000000000000000000000: n4334_o = 1'b0; + 63'b000001000000000000000000000000000000000000000000000000000000000: n4334_o = 1'b0; + 63'b000000100000000000000000000000000000000000000000000000000000000: n4334_o = 1'b0; + 63'b000000010000000000000000000000000000000000000000000000000000000: n4334_o = 1'b0; + 63'b000000001000000000000000000000000000000000000000000000000000000: n4334_o = 1'b0; + 63'b000000000100000000000000000000000000000000000000000000000000000: n4334_o = 1'b0; + 63'b000000000010000000000000000000000000000000000000000000000000000: n4334_o = n4012_o; + 63'b000000000001000000000000000000000000000000000000000000000000000: n4334_o = 1'b0; + 63'b000000000000100000000000000000000000000000000000000000000000000: n4334_o = 1'b0; + 63'b000000000000010000000000000000000000000000000000000000000000000: n4334_o = 1'b0; + 63'b000000000000001000000000000000000000000000000000000000000000000: n4334_o = 1'b0; + 63'b000000000000000100000000000000000000000000000000000000000000000: n4334_o = 1'b0; + 63'b000000000000000010000000000000000000000000000000000000000000000: n4334_o = 1'b0; + 63'b000000000000000001000000000000000000000000000000000000000000000: n4334_o = 1'b0; + 63'b000000000000000000100000000000000000000000000000000000000000000: n4334_o = 1'b0; + 63'b000000000000000000010000000000000000000000000000000000000000000: n4334_o = 1'b0; + 63'b000000000000000000001000000000000000000000000000000000000000000: n4334_o = 1'b0; + 63'b000000000000000000000100000000000000000000000000000000000000000: n4334_o = 1'b0; + 63'b000000000000000000000010000000000000000000000000000000000000000: n4334_o = 1'b0; + 63'b000000000000000000000001000000000000000000000000000000000000000: n4334_o = 1'b0; + 63'b000000000000000000000000100000000000000000000000000000000000000: n4334_o = 1'b0; + 63'b000000000000000000000000010000000000000000000000000000000000000: n4334_o = 1'b0; + 63'b000000000000000000000000001000000000000000000000000000000000000: n4334_o = 1'b0; + 63'b000000000000000000000000000100000000000000000000000000000000000: n4334_o = 1'b0; + 63'b000000000000000000000000000010000000000000000000000000000000000: n4334_o = 1'b0; + 63'b000000000000000000000000000001000000000000000000000000000000000: n4334_o = 1'b0; + 63'b000000000000000000000000000000100000000000000000000000000000000: n4334_o = 1'b0; + 63'b000000000000000000000000000000010000000000000000000000000000000: n4334_o = 1'b0; + 63'b000000000000000000000000000000001000000000000000000000000000000: n4334_o = 1'b0; + 63'b000000000000000000000000000000000100000000000000000000000000000: n4334_o = 1'b0; + 63'b000000000000000000000000000000000010000000000000000000000000000: n4334_o = 1'b0; + 63'b000000000000000000000000000000000001000000000000000000000000000: n4334_o = 1'b0; + 63'b000000000000000000000000000000000000100000000000000000000000000: n4334_o = n3093_o; + 63'b000000000000000000000000000000000000010000000000000000000000000: n4334_o = 1'b0; + 63'b000000000000000000000000000000000000001000000000000000000000000: n4334_o = 1'b0; + 63'b000000000000000000000000000000000000000100000000000000000000000: n4334_o = 1'b0; + 63'b000000000000000000000000000000000000000010000000000000000000000: n4334_o = 1'b0; + 63'b000000000000000000000000000000000000000001000000000000000000000: n4334_o = 1'b0; + 63'b000000000000000000000000000000000000000000100000000000000000000: n4334_o = 1'b0; + 63'b000000000000000000000000000000000000000000010000000000000000000: n4334_o = 1'b0; + 63'b000000000000000000000000000000000000000000001000000000000000000: n4334_o = 1'b0; + 63'b000000000000000000000000000000000000000000000100000000000000000: n4334_o = 1'b0; + 63'b000000000000000000000000000000000000000000000010000000000000000: n4334_o = 1'b0; + 63'b000000000000000000000000000000000000000000000001000000000000000: n4334_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000100000000000000: n4334_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000010000000000000: n4334_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000001000000000000: n4334_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000100000000000: n4334_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000010000000000: n4334_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000001000000000: n4334_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000100000000: n4334_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000010000000: n4334_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000001000000: n4334_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000100000: n4334_o = n2569_o; + 63'b000000000000000000000000000000000000000000000000000000000010000: n4334_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000001000: n4334_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000000100: n4334_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000000010: n4334_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000000001: n4334_o = 1'b0; + default: n4334_o = 1'b0; + endcase + /* decoder.vhd:635:5 */ + always @* + case (n4277_o) + 63'b100000000000000000000000000000000000000000000000000000000000000: n4337_o = 1'b0; + 63'b010000000000000000000000000000000000000000000000000000000000000: n4337_o = 1'b0; + 63'b001000000000000000000000000000000000000000000000000000000000000: n4337_o = 1'b0; + 63'b000100000000000000000000000000000000000000000000000000000000000: n4337_o = 1'b0; + 63'b000010000000000000000000000000000000000000000000000000000000000: n4337_o = 1'b0; + 63'b000001000000000000000000000000000000000000000000000000000000000: n4337_o = 1'b0; + 63'b000000100000000000000000000000000000000000000000000000000000000: n4337_o = 1'b0; + 63'b000000010000000000000000000000000000000000000000000000000000000: n4337_o = 1'b0; + 63'b000000001000000000000000000000000000000000000000000000000000000: n4337_o = 1'b0; + 63'b000000000100000000000000000000000000000000000000000000000000000: n4337_o = 1'b0; + 63'b000000000010000000000000000000000000000000000000000000000000000: n4337_o = 1'b0; + 63'b000000000001000000000000000000000000000000000000000000000000000: n4337_o = 1'b0; + 63'b000000000000100000000000000000000000000000000000000000000000000: n4337_o = 1'b0; + 63'b000000000000010000000000000000000000000000000000000000000000000: n4337_o = 1'b0; + 63'b000000000000001000000000000000000000000000000000000000000000000: n4337_o = 1'b0; + 63'b000000000000000100000000000000000000000000000000000000000000000: n4337_o = 1'b0; + 63'b000000000000000010000000000000000000000000000000000000000000000: n4337_o = 1'b0; + 63'b000000000000000001000000000000000000000000000000000000000000000: n4337_o = 1'b0; + 63'b000000000000000000100000000000000000000000000000000000000000000: n4337_o = 1'b0; + 63'b000000000000000000010000000000000000000000000000000000000000000: n4337_o = 1'b0; + 63'b000000000000000000001000000000000000000000000000000000000000000: n4337_o = 1'b0; + 63'b000000000000000000000100000000000000000000000000000000000000000: n4337_o = 1'b0; + 63'b000000000000000000000010000000000000000000000000000000000000000: n4337_o = 1'b0; + 63'b000000000000000000000001000000000000000000000000000000000000000: n4337_o = 1'b0; + 63'b000000000000000000000000100000000000000000000000000000000000000: n4337_o = 1'b0; + 63'b000000000000000000000000010000000000000000000000000000000000000: n4337_o = 1'b0; + 63'b000000000000000000000000001000000000000000000000000000000000000: n4337_o = 1'b0; + 63'b000000000000000000000000000100000000000000000000000000000000000: n4337_o = 1'b0; + 63'b000000000000000000000000000010000000000000000000000000000000000: n4337_o = 1'b0; + 63'b000000000000000000000000000001000000000000000000000000000000000: n4337_o = 1'b0; + 63'b000000000000000000000000000000100000000000000000000000000000000: n4337_o = 1'b0; + 63'b000000000000000000000000000000010000000000000000000000000000000: n4337_o = 1'b0; + 63'b000000000000000000000000000000001000000000000000000000000000000: n4337_o = 1'b0; + 63'b000000000000000000000000000000000100000000000000000000000000000: n4337_o = 1'b0; + 63'b000000000000000000000000000000000010000000000000000000000000000: n4337_o = 1'b0; + 63'b000000000000000000000000000000000001000000000000000000000000000: n4337_o = 1'b0; + 63'b000000000000000000000000000000000000100000000000000000000000000: n4337_o = 1'b0; + 63'b000000000000000000000000000000000000010000000000000000000000000: n4337_o = 1'b0; + 63'b000000000000000000000000000000000000001000000000000000000000000: n4337_o = 1'b0; + 63'b000000000000000000000000000000000000000100000000000000000000000: n4337_o = 1'b0; + 63'b000000000000000000000000000000000000000010000000000000000000000: n4337_o = 1'b0; + 63'b000000000000000000000000000000000000000001000000000000000000000: n4337_o = 1'b0; + 63'b000000000000000000000000000000000000000000100000000000000000000: n4337_o = 1'b0; + 63'b000000000000000000000000000000000000000000010000000000000000000: n4337_o = 1'b0; + 63'b000000000000000000000000000000000000000000001000000000000000000: n4337_o = 1'b0; + 63'b000000000000000000000000000000000000000000000100000000000000000: n4337_o = 1'b0; + 63'b000000000000000000000000000000000000000000000010000000000000000: n4337_o = 1'b0; + 63'b000000000000000000000000000000000000000000000001000000000000000: n4337_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000100000000000000: n4337_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000010000000000000: n4337_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000001000000000000: n4337_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000100000000000: n4337_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000010000000000: n4337_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000001000000000: n4337_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000100000000: n4337_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000010000000: n4337_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000001000000: n4337_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000100000: n4337_o = n2571_o; + 63'b000000000000000000000000000000000000000000000000000000000010000: n4337_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000001000: n4337_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000000100: n4337_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000000010: n4337_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000000001: n4337_o = 1'b0; + default: n4337_o = 1'b0; + endcase + /* decoder.vhd:635:5 */ + always @* + case (n4277_o) + 63'b100000000000000000000000000000000000000000000000000000000000000: n4340_o = 1'b0; + 63'b010000000000000000000000000000000000000000000000000000000000000: n4340_o = 1'b0; + 63'b001000000000000000000000000000000000000000000000000000000000000: n4340_o = 1'b0; + 63'b000100000000000000000000000000000000000000000000000000000000000: n4340_o = 1'b0; + 63'b000010000000000000000000000000000000000000000000000000000000000: n4340_o = 1'b0; + 63'b000001000000000000000000000000000000000000000000000000000000000: n4340_o = 1'b0; + 63'b000000100000000000000000000000000000000000000000000000000000000: n4340_o = 1'b0; + 63'b000000010000000000000000000000000000000000000000000000000000000: n4340_o = 1'b0; + 63'b000000001000000000000000000000000000000000000000000000000000000: n4340_o = 1'b0; + 63'b000000000100000000000000000000000000000000000000000000000000000: n4340_o = 1'b0; + 63'b000000000010000000000000000000000000000000000000000000000000000: n4340_o = 1'b0; + 63'b000000000001000000000000000000000000000000000000000000000000000: n4340_o = 1'b0; + 63'b000000000000100000000000000000000000000000000000000000000000000: n4340_o = 1'b0; + 63'b000000000000010000000000000000000000000000000000000000000000000: n4340_o = 1'b0; + 63'b000000000000001000000000000000000000000000000000000000000000000: n4340_o = 1'b0; + 63'b000000000000000100000000000000000000000000000000000000000000000: n4340_o = 1'b0; + 63'b000000000000000010000000000000000000000000000000000000000000000: n4340_o = 1'b0; + 63'b000000000000000001000000000000000000000000000000000000000000000: n4340_o = 1'b0; + 63'b000000000000000000100000000000000000000000000000000000000000000: n4340_o = 1'b0; + 63'b000000000000000000010000000000000000000000000000000000000000000: n4340_o = 1'b0; + 63'b000000000000000000001000000000000000000000000000000000000000000: n4340_o = 1'b0; + 63'b000000000000000000000100000000000000000000000000000000000000000: n4340_o = 1'b0; + 63'b000000000000000000000010000000000000000000000000000000000000000: n4340_o = 1'b0; + 63'b000000000000000000000001000000000000000000000000000000000000000: n4340_o = 1'b0; + 63'b000000000000000000000000100000000000000000000000000000000000000: n4340_o = 1'b0; + 63'b000000000000000000000000010000000000000000000000000000000000000: n4340_o = 1'b0; + 63'b000000000000000000000000001000000000000000000000000000000000000: n4340_o = n3362_o; + 63'b000000000000000000000000000100000000000000000000000000000000000: n4340_o = 1'b0; + 63'b000000000000000000000000000010000000000000000000000000000000000: n4340_o = 1'b0; + 63'b000000000000000000000000000001000000000000000000000000000000000: n4340_o = 1'b0; + 63'b000000000000000000000000000000100000000000000000000000000000000: n4340_o = 1'b0; + 63'b000000000000000000000000000000010000000000000000000000000000000: n4340_o = 1'b0; + 63'b000000000000000000000000000000001000000000000000000000000000000: n4340_o = 1'b0; + 63'b000000000000000000000000000000000100000000000000000000000000000: n4340_o = 1'b0; + 63'b000000000000000000000000000000000010000000000000000000000000000: n4340_o = 1'b0; + 63'b000000000000000000000000000000000001000000000000000000000000000: n4340_o = 1'b0; + 63'b000000000000000000000000000000000000100000000000000000000000000: n4340_o = 1'b0; + 63'b000000000000000000000000000000000000010000000000000000000000000: n4340_o = 1'b0; + 63'b000000000000000000000000000000000000001000000000000000000000000: n4340_o = 1'b0; + 63'b000000000000000000000000000000000000000100000000000000000000000: n4340_o = 1'b0; + 63'b000000000000000000000000000000000000000010000000000000000000000: n4340_o = 1'b0; + 63'b000000000000000000000000000000000000000001000000000000000000000: n4340_o = 1'b0; + 63'b000000000000000000000000000000000000000000100000000000000000000: n4340_o = 1'b0; + 63'b000000000000000000000000000000000000000000010000000000000000000: n4340_o = 1'b0; + 63'b000000000000000000000000000000000000000000001000000000000000000: n4340_o = 1'b0; + 63'b000000000000000000000000000000000000000000000100000000000000000: n4340_o = 1'b0; + 63'b000000000000000000000000000000000000000000000010000000000000000: n4340_o = 1'b0; + 63'b000000000000000000000000000000000000000000000001000000000000000: n4340_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000100000000000000: n4340_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000010000000000000: n4340_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000001000000000000: n4340_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000100000000000: n4340_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000010000000000: n4340_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000001000000000: n4340_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000100000000: n4340_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000010000000: n4340_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000001000000: n4340_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000100000: n4340_o = n2573_o; + 63'b000000000000000000000000000000000000000000000000000000000010000: n4340_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000001000: n4340_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000000100: n4340_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000000010: n4340_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000000001: n4340_o = 1'b0; + default: n4340_o = 1'b0; + endcase + /* decoder.vhd:635:5 */ + always @* + case (n4277_o) + 63'b100000000000000000000000000000000000000000000000000000000000000: n4343_o = 1'b0; + 63'b010000000000000000000000000000000000000000000000000000000000000: n4343_o = 1'b0; + 63'b001000000000000000000000000000000000000000000000000000000000000: n4343_o = 1'b0; + 63'b000100000000000000000000000000000000000000000000000000000000000: n4343_o = 1'b0; + 63'b000010000000000000000000000000000000000000000000000000000000000: n4343_o = 1'b0; + 63'b000001000000000000000000000000000000000000000000000000000000000: n4343_o = 1'b0; + 63'b000000100000000000000000000000000000000000000000000000000000000: n4343_o = 1'b0; + 63'b000000010000000000000000000000000000000000000000000000000000000: n4343_o = 1'b0; + 63'b000000001000000000000000000000000000000000000000000000000000000: n4343_o = 1'b0; + 63'b000000000100000000000000000000000000000000000000000000000000000: n4343_o = 1'b0; + 63'b000000000010000000000000000000000000000000000000000000000000000: n4343_o = n4014_o; + 63'b000000000001000000000000000000000000000000000000000000000000000: n4343_o = 1'b0; + 63'b000000000000100000000000000000000000000000000000000000000000000: n4343_o = 1'b0; + 63'b000000000000010000000000000000000000000000000000000000000000000: n4343_o = 1'b0; + 63'b000000000000001000000000000000000000000000000000000000000000000: n4343_o = 1'b0; + 63'b000000000000000100000000000000000000000000000000000000000000000: n4343_o = 1'b0; + 63'b000000000000000010000000000000000000000000000000000000000000000: n4343_o = 1'b0; + 63'b000000000000000001000000000000000000000000000000000000000000000: n4343_o = 1'b0; + 63'b000000000000000000100000000000000000000000000000000000000000000: n4343_o = 1'b0; + 63'b000000000000000000010000000000000000000000000000000000000000000: n4343_o = 1'b0; + 63'b000000000000000000001000000000000000000000000000000000000000000: n4343_o = 1'b0; + 63'b000000000000000000000100000000000000000000000000000000000000000: n4343_o = 1'b0; + 63'b000000000000000000000010000000000000000000000000000000000000000: n4343_o = 1'b0; + 63'b000000000000000000000001000000000000000000000000000000000000000: n4343_o = 1'b0; + 63'b000000000000000000000000100000000000000000000000000000000000000: n4343_o = 1'b0; + 63'b000000000000000000000000010000000000000000000000000000000000000: n4343_o = 1'b0; + 63'b000000000000000000000000001000000000000000000000000000000000000: n4343_o = n3365_o; + 63'b000000000000000000000000000100000000000000000000000000000000000: n4343_o = 1'b0; + 63'b000000000000000000000000000010000000000000000000000000000000000: n4343_o = 1'b0; + 63'b000000000000000000000000000001000000000000000000000000000000000: n4343_o = 1'b0; + 63'b000000000000000000000000000000100000000000000000000000000000000: n4343_o = 1'b0; + 63'b000000000000000000000000000000010000000000000000000000000000000: n4343_o = 1'b0; + 63'b000000000000000000000000000000001000000000000000000000000000000: n4343_o = 1'b0; + 63'b000000000000000000000000000000000100000000000000000000000000000: n4343_o = 1'b0; + 63'b000000000000000000000000000000000010000000000000000000000000000: n4343_o = 1'b0; + 63'b000000000000000000000000000000000001000000000000000000000000000: n4343_o = 1'b0; + 63'b000000000000000000000000000000000000100000000000000000000000000: n4343_o = 1'b0; + 63'b000000000000000000000000000000000000010000000000000000000000000: n4343_o = 1'b0; + 63'b000000000000000000000000000000000000001000000000000000000000000: n4343_o = 1'b0; + 63'b000000000000000000000000000000000000000100000000000000000000000: n4343_o = 1'b0; + 63'b000000000000000000000000000000000000000010000000000000000000000: n4343_o = 1'b0; + 63'b000000000000000000000000000000000000000001000000000000000000000: n4343_o = 1'b0; + 63'b000000000000000000000000000000000000000000100000000000000000000: n4343_o = 1'b0; + 63'b000000000000000000000000000000000000000000010000000000000000000: n4343_o = 1'b0; + 63'b000000000000000000000000000000000000000000001000000000000000000: n4343_o = 1'b0; + 63'b000000000000000000000000000000000000000000000100000000000000000: n4343_o = 1'b0; + 63'b000000000000000000000000000000000000000000000010000000000000000: n4343_o = 1'b0; + 63'b000000000000000000000000000000000000000000000001000000000000000: n4343_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000100000000000000: n4343_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000010000000000000: n4343_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000001000000000000: n4343_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000100000000000: n4343_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000010000000000: n4343_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000001000000000: n4343_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000100000000: n4343_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000010000000: n4343_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000001000000: n4343_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000100000: n4343_o = n2575_o; + 63'b000000000000000000000000000000000000000000000000000000000010000: n4343_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000001000: n4343_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000000100: n4343_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000000010: n4343_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000000001: n4343_o = 1'b0; + default: n4343_o = 1'b0; + endcase + /* decoder.vhd:635:5 */ + always @* + case (n4277_o) + 63'b100000000000000000000000000000000000000000000000000000000000000: n4346_o = 1'b0; + 63'b010000000000000000000000000000000000000000000000000000000000000: n4346_o = 1'b0; + 63'b001000000000000000000000000000000000000000000000000000000000000: n4346_o = 1'b0; + 63'b000100000000000000000000000000000000000000000000000000000000000: n4346_o = 1'b0; + 63'b000010000000000000000000000000000000000000000000000000000000000: n4346_o = 1'b0; + 63'b000001000000000000000000000000000000000000000000000000000000000: n4346_o = 1'b0; + 63'b000000100000000000000000000000000000000000000000000000000000000: n4346_o = 1'b0; + 63'b000000010000000000000000000000000000000000000000000000000000000: n4346_o = 1'b0; + 63'b000000001000000000000000000000000000000000000000000000000000000: n4346_o = 1'b0; + 63'b000000000100000000000000000000000000000000000000000000000000000: n4346_o = 1'b0; + 63'b000000000010000000000000000000000000000000000000000000000000000: n4346_o = n4016_o; + 63'b000000000001000000000000000000000000000000000000000000000000000: n4346_o = 1'b0; + 63'b000000000000100000000000000000000000000000000000000000000000000: n4346_o = 1'b0; + 63'b000000000000010000000000000000000000000000000000000000000000000: n4346_o = 1'b0; + 63'b000000000000001000000000000000000000000000000000000000000000000: n4346_o = 1'b0; + 63'b000000000000000100000000000000000000000000000000000000000000000: n4346_o = 1'b0; + 63'b000000000000000010000000000000000000000000000000000000000000000: n4346_o = 1'b0; + 63'b000000000000000001000000000000000000000000000000000000000000000: n4346_o = 1'b0; + 63'b000000000000000000100000000000000000000000000000000000000000000: n4346_o = 1'b0; + 63'b000000000000000000010000000000000000000000000000000000000000000: n4346_o = 1'b0; + 63'b000000000000000000001000000000000000000000000000000000000000000: n4346_o = 1'b0; + 63'b000000000000000000000100000000000000000000000000000000000000000: n4346_o = 1'b0; + 63'b000000000000000000000010000000000000000000000000000000000000000: n4346_o = 1'b0; + 63'b000000000000000000000001000000000000000000000000000000000000000: n4346_o = 1'b0; + 63'b000000000000000000000000100000000000000000000000000000000000000: n4346_o = 1'b0; + 63'b000000000000000000000000010000000000000000000000000000000000000: n4346_o = n3375_o; + 63'b000000000000000000000000001000000000000000000000000000000000000: n4346_o = 1'b0; + 63'b000000000000000000000000000100000000000000000000000000000000000: n4346_o = 1'b0; + 63'b000000000000000000000000000010000000000000000000000000000000000: n4346_o = 1'b0; + 63'b000000000000000000000000000001000000000000000000000000000000000: n4346_o = 1'b0; + 63'b000000000000000000000000000000100000000000000000000000000000000: n4346_o = 1'b0; + 63'b000000000000000000000000000000010000000000000000000000000000000: n4346_o = 1'b0; + 63'b000000000000000000000000000000001000000000000000000000000000000: n4346_o = 1'b0; + 63'b000000000000000000000000000000000100000000000000000000000000000: n4346_o = 1'b0; + 63'b000000000000000000000000000000000010000000000000000000000000000: n4346_o = 1'b0; + 63'b000000000000000000000000000000000001000000000000000000000000000: n4346_o = 1'b0; + 63'b000000000000000000000000000000000000100000000000000000000000000: n4346_o = 1'b0; + 63'b000000000000000000000000000000000000010000000000000000000000000: n4346_o = 1'b0; + 63'b000000000000000000000000000000000000001000000000000000000000000: n4346_o = 1'b0; + 63'b000000000000000000000000000000000000000100000000000000000000000: n4346_o = 1'b0; + 63'b000000000000000000000000000000000000000010000000000000000000000: n4346_o = 1'b0; + 63'b000000000000000000000000000000000000000001000000000000000000000: n4346_o = 1'b0; + 63'b000000000000000000000000000000000000000000100000000000000000000: n4346_o = 1'b0; + 63'b000000000000000000000000000000000000000000010000000000000000000: n4346_o = 1'b0; + 63'b000000000000000000000000000000000000000000001000000000000000000: n4346_o = 1'b0; + 63'b000000000000000000000000000000000000000000000100000000000000000: n4346_o = 1'b0; + 63'b000000000000000000000000000000000000000000000010000000000000000: n4346_o = 1'b0; + 63'b000000000000000000000000000000000000000000000001000000000000000: n4346_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000100000000000000: n4346_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000010000000000000: n4346_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000001000000000000: n4346_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000100000000000: n4346_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000010000000000: n4346_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000001000000000: n4346_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000100000000: n4346_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000010000000: n4346_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000001000000: n4346_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000100000: n4346_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000010000: n4346_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000001000: n4346_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000000100: n4346_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000000010: n4346_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000000001: n4346_o = 1'b0; + default: n4346_o = 1'b0; + endcase + /* decoder.vhd:635:5 */ + always @* + case (n4277_o) + 63'b100000000000000000000000000000000000000000000000000000000000000: n4349_o = 1'b0; + 63'b010000000000000000000000000000000000000000000000000000000000000: n4349_o = 1'b0; + 63'b001000000000000000000000000000000000000000000000000000000000000: n4349_o = 1'b0; + 63'b000100000000000000000000000000000000000000000000000000000000000: n4349_o = 1'b0; + 63'b000010000000000000000000000000000000000000000000000000000000000: n4349_o = 1'b0; + 63'b000001000000000000000000000000000000000000000000000000000000000: n4349_o = 1'b0; + 63'b000000100000000000000000000000000000000000000000000000000000000: n4349_o = 1'b0; + 63'b000000010000000000000000000000000000000000000000000000000000000: n4349_o = 1'b0; + 63'b000000001000000000000000000000000000000000000000000000000000000: n4349_o = 1'b0; + 63'b000000000100000000000000000000000000000000000000000000000000000: n4349_o = 1'b0; + 63'b000000000010000000000000000000000000000000000000000000000000000: n4349_o = 1'b0; + 63'b000000000001000000000000000000000000000000000000000000000000000: n4349_o = 1'b0; + 63'b000000000000100000000000000000000000000000000000000000000000000: n4349_o = 1'b0; + 63'b000000000000010000000000000000000000000000000000000000000000000: n4349_o = 1'b0; + 63'b000000000000001000000000000000000000000000000000000000000000000: n4349_o = 1'b0; + 63'b000000000000000100000000000000000000000000000000000000000000000: n4349_o = 1'b0; + 63'b000000000000000010000000000000000000000000000000000000000000000: n4349_o = 1'b0; + 63'b000000000000000001000000000000000000000000000000000000000000000: n4349_o = 1'b0; + 63'b000000000000000000100000000000000000000000000000000000000000000: n4349_o = 1'b0; + 63'b000000000000000000010000000000000000000000000000000000000000000: n4349_o = 1'b0; + 63'b000000000000000000001000000000000000000000000000000000000000000: n4349_o = 1'b0; + 63'b000000000000000000000100000000000000000000000000000000000000000: n4349_o = 1'b0; + 63'b000000000000000000000010000000000000000000000000000000000000000: n4349_o = 1'b0; + 63'b000000000000000000000001000000000000000000000000000000000000000: n4349_o = 1'b0; + 63'b000000000000000000000000100000000000000000000000000000000000000: n4349_o = 1'b0; + 63'b000000000000000000000000010000000000000000000000000000000000000: n4349_o = n3378_o; + 63'b000000000000000000000000001000000000000000000000000000000000000: n4349_o = 1'b0; + 63'b000000000000000000000000000100000000000000000000000000000000000: n4349_o = 1'b0; + 63'b000000000000000000000000000010000000000000000000000000000000000: n4349_o = 1'b0; + 63'b000000000000000000000000000001000000000000000000000000000000000: n4349_o = 1'b0; + 63'b000000000000000000000000000000100000000000000000000000000000000: n4349_o = 1'b0; + 63'b000000000000000000000000000000010000000000000000000000000000000: n4349_o = 1'b0; + 63'b000000000000000000000000000000001000000000000000000000000000000: n4349_o = 1'b0; + 63'b000000000000000000000000000000000100000000000000000000000000000: n4349_o = 1'b0; + 63'b000000000000000000000000000000000010000000000000000000000000000: n4349_o = 1'b0; + 63'b000000000000000000000000000000000001000000000000000000000000000: n4349_o = 1'b0; + 63'b000000000000000000000000000000000000100000000000000000000000000: n4349_o = 1'b0; + 63'b000000000000000000000000000000000000010000000000000000000000000: n4349_o = 1'b0; + 63'b000000000000000000000000000000000000001000000000000000000000000: n4349_o = 1'b0; + 63'b000000000000000000000000000000000000000100000000000000000000000: n4349_o = 1'b0; + 63'b000000000000000000000000000000000000000010000000000000000000000: n4349_o = 1'b0; + 63'b000000000000000000000000000000000000000001000000000000000000000: n4349_o = 1'b0; + 63'b000000000000000000000000000000000000000000100000000000000000000: n4349_o = 1'b0; + 63'b000000000000000000000000000000000000000000010000000000000000000: n4349_o = 1'b0; + 63'b000000000000000000000000000000000000000000001000000000000000000: n4349_o = 1'b0; + 63'b000000000000000000000000000000000000000000000100000000000000000: n4349_o = 1'b0; + 63'b000000000000000000000000000000000000000000000010000000000000000: n4349_o = 1'b0; + 63'b000000000000000000000000000000000000000000000001000000000000000: n4349_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000100000000000000: n4349_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000010000000000000: n4349_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000001000000000000: n4349_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000100000000000: n4349_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000010000000000: n4349_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000001000000000: n4349_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000100000000: n4349_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000010000000: n4349_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000001000000: n4349_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000100000: n4349_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000010000: n4349_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000001000: n4349_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000000100: n4349_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000000010: n4349_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000000001: n4349_o = 1'b0; + default: n4349_o = 1'b0; + endcase + /* decoder.vhd:635:5 */ + always @* + case (n4277_o) + 63'b100000000000000000000000000000000000000000000000000000000000000: n4353_o = n4274_o; + 63'b010000000000000000000000000000000000000000000000000000000000000: n4353_o = n4242_o; + 63'b001000000000000000000000000000000000000000000000000000000000000: n4353_o = n4187_o; + 63'b000100000000000000000000000000000000000000000000000000000000000: n4353_o = 4'b0111; + 63'b000010000000000000000000000000000000000000000000000000000000000: n4353_o = 4'b1100; + 63'b000001000000000000000000000000000000000000000000000000000000000: n4353_o = 4'b1100; + 63'b000000100000000000000000000000000000000000000000000000000000000: n4353_o = 4'b1100; + 63'b000000010000000000000000000000000000000000000000000000000000000: n4353_o = 4'b1100; + 63'b000000001000000000000000000000000000000000000000000000000000000: n4353_o = n4075_o; + 63'b000000000100000000000000000000000000000000000000000000000000000: n4353_o = n4046_o; + 63'b000000000010000000000000000000000000000000000000000000000000000: n4353_o = 4'b1100; + 63'b000000000001000000000000000000000000000000000000000000000000000: n4353_o = 4'b1100; + 63'b000000000000100000000000000000000000000000000000000000000000000: n4353_o = 4'b1100; + 63'b000000000000010000000000000000000000000000000000000000000000000: n4353_o = n3900_o; + 63'b000000000000001000000000000000000000000000000000000000000000000: n4353_o = n3794_o; + 63'b000000000000000100000000000000000000000000000000000000000000000: n4353_o = n3762_o; + 63'b000000000000000010000000000000000000000000000000000000000000000: n4353_o = 4'b1100; + 63'b000000000000000001000000000000000000000000000000000000000000000: n4353_o = 4'b1100; + 63'b000000000000000000100000000000000000000000000000000000000000000: n4353_o = 4'b1100; + 63'b000000000000000000010000000000000000000000000000000000000000000: n4353_o = 4'b1100; + 63'b000000000000000000001000000000000000000000000000000000000000000: n4353_o = 4'b1100; + 63'b000000000000000000000100000000000000000000000000000000000000000: n4353_o = 4'b1100; + 63'b000000000000000000000010000000000000000000000000000000000000000: n4353_o = 4'b1100; + 63'b000000000000000000000001000000000000000000000000000000000000000: n4353_o = 4'b1100; + 63'b000000000000000000000000100000000000000000000000000000000000000: n4353_o = 4'b1100; + 63'b000000000000000000000000010000000000000000000000000000000000000: n4353_o = 4'b1100; + 63'b000000000000000000000000001000000000000000000000000000000000000: n4353_o = 4'b1100; + 63'b000000000000000000000000000100000000000000000000000000000000000: n4353_o = 4'b1100; + 63'b000000000000000000000000000010000000000000000000000000000000000: n4353_o = 4'b1100; + 63'b000000000000000000000000000001000000000000000000000000000000000: n4353_o = 4'b1100; + 63'b000000000000000000000000000000100000000000000000000000000000000: n4353_o = 4'b1100; + 63'b000000000000000000000000000000010000000000000000000000000000000: n4353_o = 4'b1100; + 63'b000000000000000000000000000000001000000000000000000000000000000: n4353_o = 4'b1100; + 63'b000000000000000000000000000000000100000000000000000000000000000: n4353_o = 4'b1100; + 63'b000000000000000000000000000000000010000000000000000000000000000: n4353_o = 4'b1100; + 63'b000000000000000000000000000000000001000000000000000000000000000: n4353_o = 4'b1100; + 63'b000000000000000000000000000000000000100000000000000000000000000: n4353_o = 4'b1100; + 63'b000000000000000000000000000000000000010000000000000000000000000: n4353_o = 4'b1100; + 63'b000000000000000000000000000000000000001000000000000000000000000: n4353_o = 4'b1100; + 63'b000000000000000000000000000000000000000100000000000000000000000: n4353_o = 4'b1100; + 63'b000000000000000000000000000000000000000010000000000000000000000: n4353_o = n2966_o; + 63'b000000000000000000000000000000000000000001000000000000000000000: n4353_o = 4'b1100; + 63'b000000000000000000000000000000000000000000100000000000000000000: n4353_o = 4'b1100; + 63'b000000000000000000000000000000000000000000010000000000000000000: n4353_o = 4'b1100; + 63'b000000000000000000000000000000000000000000001000000000000000000: n4353_o = 4'b1100; + 63'b000000000000000000000000000000000000000000000100000000000000000: n4353_o = 4'b1100; + 63'b000000000000000000000000000000000000000000000010000000000000000: n4353_o = n2835_o; + 63'b000000000000000000000000000000000000000000000001000000000000000: n4353_o = 4'b1100; + 63'b000000000000000000000000000000000000000000000000100000000000000: n4353_o = 4'b1100; + 63'b000000000000000000000000000000000000000000000000010000000000000: n4353_o = n2749_o; + 63'b000000000000000000000000000000000000000000000000001000000000000: n4353_o = n2700_o; + 63'b000000000000000000000000000000000000000000000000000100000000000: n4353_o = 4'b1100; + 63'b000000000000000000000000000000000000000000000000000010000000000: n4353_o = 4'b1100; + 63'b000000000000000000000000000000000000000000000000000001000000000: n4353_o = n2638_o; + 63'b000000000000000000000000000000000000000000000000000000100000000: n4353_o = 4'b1100; + 63'b000000000000000000000000000000000000000000000000000000010000000: n4353_o = 4'b1100; + 63'b000000000000000000000000000000000000000000000000000000001000000: n4353_o = n2602_o; + 63'b000000000000000000000000000000000000000000000000000000000100000: n4353_o = 4'b1100; + 63'b000000000000000000000000000000000000000000000000000000000010000: n4353_o = n2465_o; + 63'b000000000000000000000000000000000000000000000000000000000001000: n4353_o = n2359_o; + 63'b000000000000000000000000000000000000000000000000000000000000100: n4353_o = n2327_o; + 63'b000000000000000000000000000000000000000000000000000000000000010: n4353_o = n2271_o; + 63'b000000000000000000000000000000000000000000000000000000000000001: n4353_o = n2215_o; + default: n4353_o = 4'b1100; + endcase + /* decoder.vhd:635:5 */ + always @* + case (n4277_o) + 63'b100000000000000000000000000000000000000000000000000000000000000: n4356_o = 1'b0; + 63'b010000000000000000000000000000000000000000000000000000000000000: n4356_o = 1'b0; + 63'b001000000000000000000000000000000000000000000000000000000000000: n4356_o = 1'b0; + 63'b000100000000000000000000000000000000000000000000000000000000000: n4356_o = 1'b0; + 63'b000010000000000000000000000000000000000000000000000000000000000: n4356_o = 1'b0; + 63'b000001000000000000000000000000000000000000000000000000000000000: n4356_o = 1'b0; + 63'b000000100000000000000000000000000000000000000000000000000000000: n4356_o = 1'b0; + 63'b000000010000000000000000000000000000000000000000000000000000000: n4356_o = 1'b0; + 63'b000000001000000000000000000000000000000000000000000000000000000: n4356_o = n4077_o; + 63'b000000000100000000000000000000000000000000000000000000000000000: n4356_o = n4048_o; + 63'b000000000010000000000000000000000000000000000000000000000000000: n4356_o = 1'b0; + 63'b000000000001000000000000000000000000000000000000000000000000000: n4356_o = 1'b0; + 63'b000000000000100000000000000000000000000000000000000000000000000: n4356_o = 1'b0; + 63'b000000000000010000000000000000000000000000000000000000000000000: n4356_o = 1'b0; + 63'b000000000000001000000000000000000000000000000000000000000000000: n4356_o = 1'b0; + 63'b000000000000000100000000000000000000000000000000000000000000000: n4356_o = 1'b0; + 63'b000000000000000010000000000000000000000000000000000000000000000: n4356_o = 1'b0; + 63'b000000000000000001000000000000000000000000000000000000000000000: n4356_o = 1'b0; + 63'b000000000000000000100000000000000000000000000000000000000000000: n4356_o = 1'b0; + 63'b000000000000000000010000000000000000000000000000000000000000000: n4356_o = 1'b0; + 63'b000000000000000000001000000000000000000000000000000000000000000: n4356_o = 1'b0; + 63'b000000000000000000000100000000000000000000000000000000000000000: n4356_o = 1'b0; + 63'b000000000000000000000010000000000000000000000000000000000000000: n4356_o = 1'b0; + 63'b000000000000000000000001000000000000000000000000000000000000000: n4356_o = 1'b0; + 63'b000000000000000000000000100000000000000000000000000000000000000: n4356_o = 1'b0; + 63'b000000000000000000000000010000000000000000000000000000000000000: n4356_o = 1'b0; + 63'b000000000000000000000000001000000000000000000000000000000000000: n4356_o = 1'b0; + 63'b000000000000000000000000000100000000000000000000000000000000000: n4356_o = 1'b0; + 63'b000000000000000000000000000010000000000000000000000000000000000: n4356_o = 1'b0; + 63'b000000000000000000000000000001000000000000000000000000000000000: n4356_o = 1'b0; + 63'b000000000000000000000000000000100000000000000000000000000000000: n4356_o = 1'b0; + 63'b000000000000000000000000000000010000000000000000000000000000000: n4356_o = 1'b0; + 63'b000000000000000000000000000000001000000000000000000000000000000: n4356_o = 1'b0; + 63'b000000000000000000000000000000000100000000000000000000000000000: n4356_o = 1'b0; + 63'b000000000000000000000000000000000010000000000000000000000000000: n4356_o = 1'b0; + 63'b000000000000000000000000000000000001000000000000000000000000000: n4356_o = 1'b0; + 63'b000000000000000000000000000000000000100000000000000000000000000: n4356_o = 1'b0; + 63'b000000000000000000000000000000000000010000000000000000000000000: n4356_o = 1'b0; + 63'b000000000000000000000000000000000000001000000000000000000000000: n4356_o = 1'b0; + 63'b000000000000000000000000000000000000000100000000000000000000000: n4356_o = 1'b0; + 63'b000000000000000000000000000000000000000010000000000000000000000: n4356_o = 1'b0; + 63'b000000000000000000000000000000000000000001000000000000000000000: n4356_o = 1'b0; + 63'b000000000000000000000000000000000000000000100000000000000000000: n4356_o = 1'b0; + 63'b000000000000000000000000000000000000000000010000000000000000000: n4356_o = 1'b0; + 63'b000000000000000000000000000000000000000000001000000000000000000: n4356_o = 1'b0; + 63'b000000000000000000000000000000000000000000000100000000000000000: n4356_o = 1'b0; + 63'b000000000000000000000000000000000000000000000010000000000000000: n4356_o = 1'b0; + 63'b000000000000000000000000000000000000000000000001000000000000000: n4356_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000100000000000000: n4356_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000010000000000000: n4356_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000001000000000000: n4356_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000100000000000: n4356_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000010000000000: n4356_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000001000000000: n4356_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000100000000: n4356_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000010000000: n4356_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000001000000: n4356_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000100000: n4356_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000010000: n4356_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000001000: n4356_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000000100: n4356_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000000010: n4356_o = n2273_o; + 63'b000000000000000000000000000000000000000000000000000000000000001: n4356_o = n2217_o; + default: n4356_o = 1'b0; + endcase + /* decoder.vhd:635:5 */ + always @* + case (n4277_o) + 63'b100000000000000000000000000000000000000000000000000000000000000: n4359_o = 1'b0; + 63'b010000000000000000000000000000000000000000000000000000000000000: n4359_o = 1'b0; + 63'b001000000000000000000000000000000000000000000000000000000000000: n4359_o = 1'b0; + 63'b000100000000000000000000000000000000000000000000000000000000000: n4359_o = 1'b0; + 63'b000010000000000000000000000000000000000000000000000000000000000: n4359_o = 1'b0; + 63'b000001000000000000000000000000000000000000000000000000000000000: n4359_o = 1'b0; + 63'b000000100000000000000000000000000000000000000000000000000000000: n4359_o = 1'b0; + 63'b000000010000000000000000000000000000000000000000000000000000000: n4359_o = 1'b0; + 63'b000000001000000000000000000000000000000000000000000000000000000: n4359_o = 1'b0; + 63'b000000000100000000000000000000000000000000000000000000000000000: n4359_o = 1'b0; + 63'b000000000010000000000000000000000000000000000000000000000000000: n4359_o = 1'b0; + 63'b000000000001000000000000000000000000000000000000000000000000000: n4359_o = 1'b0; + 63'b000000000000100000000000000000000000000000000000000000000000000: n4359_o = 1'b0; + 63'b000000000000010000000000000000000000000000000000000000000000000: n4359_o = 1'b0; + 63'b000000000000001000000000000000000000000000000000000000000000000: n4359_o = 1'b0; + 63'b000000000000000100000000000000000000000000000000000000000000000: n4359_o = 1'b0; + 63'b000000000000000010000000000000000000000000000000000000000000000: n4359_o = 1'b0; + 63'b000000000000000001000000000000000000000000000000000000000000000: n4359_o = 1'b0; + 63'b000000000000000000100000000000000000000000000000000000000000000: n4359_o = 1'b0; + 63'b000000000000000000010000000000000000000000000000000000000000000: n4359_o = 1'b0; + 63'b000000000000000000001000000000000000000000000000000000000000000: n4359_o = 1'b0; + 63'b000000000000000000000100000000000000000000000000000000000000000: n4359_o = 1'b0; + 63'b000000000000000000000010000000000000000000000000000000000000000: n4359_o = 1'b0; + 63'b000000000000000000000001000000000000000000000000000000000000000: n4359_o = 1'b0; + 63'b000000000000000000000000100000000000000000000000000000000000000: n4359_o = 1'b0; + 63'b000000000000000000000000010000000000000000000000000000000000000: n4359_o = 1'b0; + 63'b000000000000000000000000001000000000000000000000000000000000000: n4359_o = 1'b0; + 63'b000000000000000000000000000100000000000000000000000000000000000: n4359_o = 1'b0; + 63'b000000000000000000000000000010000000000000000000000000000000000: n4359_o = 1'b0; + 63'b000000000000000000000000000001000000000000000000000000000000000: n4359_o = 1'b0; + 63'b000000000000000000000000000000100000000000000000000000000000000: n4359_o = 1'b0; + 63'b000000000000000000000000000000010000000000000000000000000000000: n4359_o = 1'b0; + 63'b000000000000000000000000000000001000000000000000000000000000000: n4359_o = 1'b0; + 63'b000000000000000000000000000000000100000000000000000000000000000: n4359_o = 1'b0; + 63'b000000000000000000000000000000000010000000000000000000000000000: n4359_o = 1'b0; + 63'b000000000000000000000000000000000001000000000000000000000000000: n4359_o = 1'b0; + 63'b000000000000000000000000000000000000100000000000000000000000000: n4359_o = 1'b0; + 63'b000000000000000000000000000000000000010000000000000000000000000: n4359_o = 1'b0; + 63'b000000000000000000000000000000000000001000000000000000000000000: n4359_o = 1'b0; + 63'b000000000000000000000000000000000000000100000000000000000000000: n4359_o = 1'b0; + 63'b000000000000000000000000000000000000000010000000000000000000000: n4359_o = 1'b0; + 63'b000000000000000000000000000000000000000001000000000000000000000: n4359_o = 1'b0; + 63'b000000000000000000000000000000000000000000100000000000000000000: n4359_o = 1'b0; + 63'b000000000000000000000000000000000000000000010000000000000000000: n4359_o = 1'b0; + 63'b000000000000000000000000000000000000000000001000000000000000000: n4359_o = 1'b0; + 63'b000000000000000000000000000000000000000000000100000000000000000: n4359_o = 1'b0; + 63'b000000000000000000000000000000000000000000000010000000000000000: n4359_o = 1'b0; + 63'b000000000000000000000000000000000000000000000001000000000000000: n4359_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000100000000000000: n4359_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000010000000000000: n4359_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000001000000000000: n4359_o = n2704_o; + 63'b000000000000000000000000000000000000000000000000000100000000000: n4359_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000010000000000: n4359_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000001000000000: n4359_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000100000000: n4359_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000010000000: n4359_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000001000000: n4359_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000100000: n4359_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000010000: n4359_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000001000: n4359_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000000100: n4359_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000000010: n4359_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000000001: n4359_o = 1'b0; + default: n4359_o = 1'b0; + endcase + /* decoder.vhd:635:5 */ + always @* + case (n4277_o) + 63'b100000000000000000000000000000000000000000000000000000000000000: n4362_o = 1'b0; + 63'b010000000000000000000000000000000000000000000000000000000000000: n4362_o = 1'b0; + 63'b001000000000000000000000000000000000000000000000000000000000000: n4362_o = n4189_o; + 63'b000100000000000000000000000000000000000000000000000000000000000: n4362_o = 1'b0; + 63'b000010000000000000000000000000000000000000000000000000000000000: n4362_o = 1'b0; + 63'b000001000000000000000000000000000000000000000000000000000000000: n4362_o = 1'b0; + 63'b000000100000000000000000000000000000000000000000000000000000000: n4362_o = 1'b0; + 63'b000000010000000000000000000000000000000000000000000000000000000: n4362_o = 1'b0; + 63'b000000001000000000000000000000000000000000000000000000000000000: n4362_o = 1'b0; + 63'b000000000100000000000000000000000000000000000000000000000000000: n4362_o = 1'b0; + 63'b000000000010000000000000000000000000000000000000000000000000000: n4362_o = 1'b0; + 63'b000000000001000000000000000000000000000000000000000000000000000: n4362_o = 1'b0; + 63'b000000000000100000000000000000000000000000000000000000000000000: n4362_o = 1'b0; + 63'b000000000000010000000000000000000000000000000000000000000000000: n4362_o = 1'b0; + 63'b000000000000001000000000000000000000000000000000000000000000000: n4362_o = 1'b0; + 63'b000000000000000100000000000000000000000000000000000000000000000: n4362_o = 1'b0; + 63'b000000000000000010000000000000000000000000000000000000000000000: n4362_o = 1'b0; + 63'b000000000000000001000000000000000000000000000000000000000000000: n4362_o = 1'b0; + 63'b000000000000000000100000000000000000000000000000000000000000000: n4362_o = 1'b0; + 63'b000000000000000000010000000000000000000000000000000000000000000: n4362_o = 1'b0; + 63'b000000000000000000001000000000000000000000000000000000000000000: n4362_o = 1'b0; + 63'b000000000000000000000100000000000000000000000000000000000000000: n4362_o = 1'b0; + 63'b000000000000000000000010000000000000000000000000000000000000000: n4362_o = 1'b0; + 63'b000000000000000000000001000000000000000000000000000000000000000: n4362_o = 1'b0; + 63'b000000000000000000000000100000000000000000000000000000000000000: n4362_o = 1'b0; + 63'b000000000000000000000000010000000000000000000000000000000000000: n4362_o = 1'b0; + 63'b000000000000000000000000001000000000000000000000000000000000000: n4362_o = 1'b0; + 63'b000000000000000000000000000100000000000000000000000000000000000: n4362_o = 1'b0; + 63'b000000000000000000000000000010000000000000000000000000000000000: n4362_o = 1'b0; + 63'b000000000000000000000000000001000000000000000000000000000000000: n4362_o = 1'b0; + 63'b000000000000000000000000000000100000000000000000000000000000000: n4362_o = 1'b0; + 63'b000000000000000000000000000000010000000000000000000000000000000: n4362_o = 1'b0; + 63'b000000000000000000000000000000001000000000000000000000000000000: n4362_o = 1'b0; + 63'b000000000000000000000000000000000100000000000000000000000000000: n4362_o = 1'b0; + 63'b000000000000000000000000000000000010000000000000000000000000000: n4362_o = 1'b0; + 63'b000000000000000000000000000000000001000000000000000000000000000: n4362_o = 1'b0; + 63'b000000000000000000000000000000000000100000000000000000000000000: n4362_o = 1'b0; + 63'b000000000000000000000000000000000000010000000000000000000000000: n4362_o = 1'b0; + 63'b000000000000000000000000000000000000001000000000000000000000000: n4362_o = 1'b0; + 63'b000000000000000000000000000000000000000100000000000000000000000: n4362_o = 1'b0; + 63'b000000000000000000000000000000000000000010000000000000000000000: n4362_o = 1'b0; + 63'b000000000000000000000000000000000000000001000000000000000000000: n4362_o = 1'b0; + 63'b000000000000000000000000000000000000000000100000000000000000000: n4362_o = 1'b0; + 63'b000000000000000000000000000000000000000000010000000000000000000: n4362_o = 1'b0; + 63'b000000000000000000000000000000000000000000001000000000000000000: n4362_o = 1'b0; + 63'b000000000000000000000000000000000000000000000100000000000000000: n4362_o = 1'b0; + 63'b000000000000000000000000000000000000000000000010000000000000000: n4362_o = 1'b0; + 63'b000000000000000000000000000000000000000000000001000000000000000: n4362_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000100000000000000: n4362_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000010000000000000: n4362_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000001000000000000: n4362_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000100000000000: n4362_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000010000000000: n4362_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000001000000000: n4362_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000100000000: n4362_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000010000000: n4362_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000001000000: n4362_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000100000: n4362_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000010000: n4362_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000001000: n4362_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000000100: n4362_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000000010: n4362_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000000001: n4362_o = 1'b0; + default: n4362_o = 1'b0; + endcase + /* decoder.vhd:635:5 */ + always @* + case (n4277_o) + 63'b100000000000000000000000000000000000000000000000000000000000000: n4365_o = 1'b0; + 63'b010000000000000000000000000000000000000000000000000000000000000: n4365_o = 1'b0; + 63'b001000000000000000000000000000000000000000000000000000000000000: n4365_o = 1'b0; + 63'b000100000000000000000000000000000000000000000000000000000000000: n4365_o = 1'b0; + 63'b000010000000000000000000000000000000000000000000000000000000000: n4365_o = 1'b0; + 63'b000001000000000000000000000000000000000000000000000000000000000: n4365_o = 1'b0; + 63'b000000100000000000000000000000000000000000000000000000000000000: n4365_o = 1'b0; + 63'b000000010000000000000000000000000000000000000000000000000000000: n4365_o = 1'b0; + 63'b000000001000000000000000000000000000000000000000000000000000000: n4365_o = 1'b0; + 63'b000000000100000000000000000000000000000000000000000000000000000: n4365_o = 1'b0; + 63'b000000000010000000000000000000000000000000000000000000000000000: n4365_o = 1'b0; + 63'b000000000001000000000000000000000000000000000000000000000000000: n4365_o = 1'b0; + 63'b000000000000100000000000000000000000000000000000000000000000000: n4365_o = 1'b0; + 63'b000000000000010000000000000000000000000000000000000000000000000: n4365_o = 1'b0; + 63'b000000000000001000000000000000000000000000000000000000000000000: n4365_o = 1'b0; + 63'b000000000000000100000000000000000000000000000000000000000000000: n4365_o = 1'b0; + 63'b000000000000000010000000000000000000000000000000000000000000000: n4365_o = 1'b0; + 63'b000000000000000001000000000000000000000000000000000000000000000: n4365_o = 1'b0; + 63'b000000000000000000100000000000000000000000000000000000000000000: n4365_o = 1'b0; + 63'b000000000000000000010000000000000000000000000000000000000000000: n4365_o = 1'b0; + 63'b000000000000000000001000000000000000000000000000000000000000000: n4365_o = 1'b0; + 63'b000000000000000000000100000000000000000000000000000000000000000: n4365_o = 1'b0; + 63'b000000000000000000000010000000000000000000000000000000000000000: n4365_o = 1'b0; + 63'b000000000000000000000001000000000000000000000000000000000000000: n4365_o = 1'b0; + 63'b000000000000000000000000100000000000000000000000000000000000000: n4365_o = 1'b0; + 63'b000000000000000000000000010000000000000000000000000000000000000: n4365_o = 1'b0; + 63'b000000000000000000000000001000000000000000000000000000000000000: n4365_o = 1'b0; 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+ 63'b000000000000000000000000000000000000000000000000000100000000000: n4365_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000010000000000: n4365_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000001000000000: n4365_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000100000000: n4365_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000010000000: n4365_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000001000000: n4365_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000100000: n4365_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000010000: n4365_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000001000: n4365_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000000100: n4365_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000000010: n4365_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000000001: n4365_o = 1'b0; + default: n4365_o = 1'b0; + endcase + /* decoder.vhd:635:5 */ + always @* + case (n4277_o) + 63'b100000000000000000000000000000000000000000000000000000000000000: n4368_o = 1'b0; + 63'b010000000000000000000000000000000000000000000000000000000000000: n4368_o = 1'b0; + 63'b001000000000000000000000000000000000000000000000000000000000000: n4368_o = 1'b0; + 63'b000100000000000000000000000000000000000000000000000000000000000: n4368_o = 1'b0; + 63'b000010000000000000000000000000000000000000000000000000000000000: n4368_o = 1'b0; + 63'b000001000000000000000000000000000000000000000000000000000000000: n4368_o = 1'b0; + 63'b000000100000000000000000000000000000000000000000000000000000000: n4368_o = 1'b0; + 63'b000000010000000000000000000000000000000000000000000000000000000: n4368_o = 1'b0; + 63'b000000001000000000000000000000000000000000000000000000000000000: n4368_o = 1'b0; + 63'b000000000100000000000000000000000000000000000000000000000000000: n4368_o = 1'b0; + 63'b000000000010000000000000000000000000000000000000000000000000000: n4368_o = 1'b0; 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+ 63'b000000000000000000000000000000000000000000000000000000000001000: n4368_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000000100: n4368_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000000010: n4368_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000000001: n4368_o = 1'b0; + default: n4368_o = 1'b0; + endcase + /* decoder.vhd:635:5 */ + always @* + case (n4277_o) + 63'b100000000000000000000000000000000000000000000000000000000000000: n4372_o = 1'b0; + 63'b010000000000000000000000000000000000000000000000000000000000000: n4372_o = 1'b0; + 63'b001000000000000000000000000000000000000000000000000000000000000: n4372_o = 1'b0; + 63'b000100000000000000000000000000000000000000000000000000000000000: n4372_o = 1'b0; + 63'b000010000000000000000000000000000000000000000000000000000000000: n4372_o = 1'b0; + 63'b000001000000000000000000000000000000000000000000000000000000000: n4372_o = 1'b0; + 63'b000000100000000000000000000000000000000000000000000000000000000: n4372_o = 1'b0; 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+ 63'b000000000000000000000000000000010000000000000000000000000000000: n4372_o = 1'b0; + 63'b000000000000000000000000000000001000000000000000000000000000000: n4372_o = 1'b0; + 63'b000000000000000000000000000000000100000000000000000000000000000: n4372_o = 1'b0; + 63'b000000000000000000000000000000000010000000000000000000000000000: n4372_o = 1'b0; + 63'b000000000000000000000000000000000001000000000000000000000000000: n4372_o = 1'b0; + 63'b000000000000000000000000000000000000100000000000000000000000000: n4372_o = 1'b0; + 63'b000000000000000000000000000000000000010000000000000000000000000: n4372_o = 1'b0; + 63'b000000000000000000000000000000000000001000000000000000000000000: n4372_o = 1'b0; + 63'b000000000000000000000000000000000000000100000000000000000000000: n4372_o = 1'b0; + 63'b000000000000000000000000000000000000000010000000000000000000000: n4372_o = 1'b0; + 63'b000000000000000000000000000000000000000001000000000000000000000: n4372_o = 1'b0; + 63'b000000000000000000000000000000000000000000100000000000000000000: n4372_o = 1'b0; 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+ 63'b000000000000000000000000000000000000000000000000000000010000000: n4372_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000001000000: n4372_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000100000: n4372_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000010000: n4372_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000001000: n4372_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000000100: n4372_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000000010: n4372_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000000001: n4372_o = 1'b0; + default: n4372_o = 1'b0; + endcase + /* decoder.vhd:635:5 */ + always @* + case (n4277_o) + 63'b100000000000000000000000000000000000000000000000000000000000000: n4377_o = 1'b0; + 63'b010000000000000000000000000000000000000000000000000000000000000: n4377_o = 1'b0; + 63'b001000000000000000000000000000000000000000000000000000000000000: n4377_o = 1'b0; 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+ 63'b000000000000000000000000000000000000000000000000000100000000000: n4377_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000010000000000: n4377_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000001000000000: n4377_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000100000000: n4377_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000010000000: n4377_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000001000000: n4377_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000100000: n4377_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000010000: n4377_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000001000: n4377_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000000100: n4377_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000000010: n4377_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000000001: n4377_o = 1'b0; + default: n4377_o = 1'b0; + endcase + /* decoder.vhd:635:5 */ + always @* + case (n4277_o) + 63'b100000000000000000000000000000000000000000000000000000000000000: n4381_o = 1'b0; + 63'b010000000000000000000000000000000000000000000000000000000000000: n4381_o = 1'b0; + 63'b001000000000000000000000000000000000000000000000000000000000000: n4381_o = 1'b0; + 63'b000100000000000000000000000000000000000000000000000000000000000: n4381_o = 1'b0; + 63'b000010000000000000000000000000000000000000000000000000000000000: n4381_o = 1'b0; + 63'b000001000000000000000000000000000000000000000000000000000000000: n4381_o = 1'b0; + 63'b000000100000000000000000000000000000000000000000000000000000000: n4381_o = 1'b0; + 63'b000000010000000000000000000000000000000000000000000000000000000: n4381_o = 1'b0; + 63'b000000001000000000000000000000000000000000000000000000000000000: n4381_o = 1'b0; + 63'b000000000100000000000000000000000000000000000000000000000000000: n4381_o = 1'b0; + 63'b000000000010000000000000000000000000000000000000000000000000000: n4381_o = 1'b0; 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+ 63'b000000000000000000000000000000000000000000000001000000000000000: n4381_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000100000000000000: n4381_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000010000000000000: n4381_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000001000000000000: n4381_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000100000000000: n4381_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000010000000000: n4381_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000001000000000: n4381_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000100000000: n4381_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000010000000: n4381_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000001000000: n4381_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000100000: n4381_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000010000: n4381_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000001000: n4381_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000000100: n4381_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000000010: n4381_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000000001: n4381_o = 1'b0; + default: n4381_o = 1'b0; + endcase + /* decoder.vhd:635:5 */ + always @* + case (n4277_o) + 63'b100000000000000000000000000000000000000000000000000000000000000: n4384_o = 1'b0; + 63'b010000000000000000000000000000000000000000000000000000000000000: n4384_o = 1'b0; + 63'b001000000000000000000000000000000000000000000000000000000000000: n4384_o = 1'b0; + 63'b000100000000000000000000000000000000000000000000000000000000000: n4384_o = 1'b0; + 63'b000010000000000000000000000000000000000000000000000000000000000: n4384_o = 1'b0; + 63'b000001000000000000000000000000000000000000000000000000000000000: n4384_o = 1'b0; + 63'b000000100000000000000000000000000000000000000000000000000000000: n4384_o = 1'b0; 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+ 63'b000000000000000000000000000000010000000000000000000000000000000: n4384_o = 1'b0; + 63'b000000000000000000000000000000001000000000000000000000000000000: n4384_o = 1'b0; + 63'b000000000000000000000000000000000100000000000000000000000000000: n4384_o = 1'b0; + 63'b000000000000000000000000000000000010000000000000000000000000000: n4384_o = 1'b0; + 63'b000000000000000000000000000000000001000000000000000000000000000: n4384_o = 1'b0; + 63'b000000000000000000000000000000000000100000000000000000000000000: n4384_o = 1'b0; + 63'b000000000000000000000000000000000000010000000000000000000000000: n4384_o = 1'b0; + 63'b000000000000000000000000000000000000001000000000000000000000000: n4384_o = 1'b0; + 63'b000000000000000000000000000000000000000100000000000000000000000: n4384_o = 1'b0; + 63'b000000000000000000000000000000000000000010000000000000000000000: n4384_o = 1'b0; + 63'b000000000000000000000000000000000000000001000000000000000000000: n4384_o = 1'b0; + 63'b000000000000000000000000000000000000000000100000000000000000000: n4384_o = 1'b0; + 63'b000000000000000000000000000000000000000000010000000000000000000: n4384_o = 1'b0; + 63'b000000000000000000000000000000000000000000001000000000000000000: n4384_o = 1'b0; + 63'b000000000000000000000000000000000000000000000100000000000000000: n4384_o = 1'b0; + 63'b000000000000000000000000000000000000000000000010000000000000000: n4384_o = 1'b0; + 63'b000000000000000000000000000000000000000000000001000000000000000: n4384_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000100000000000000: n4384_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000010000000000000: n4384_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000001000000000000: n4384_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000100000000000: n4384_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000010000000000: n4384_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000001000000000: n4384_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000100000000: n4384_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000010000000: n4384_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000001000000: n4384_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000100000: n4384_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000010000: n4384_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000001000: n4384_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000000100: n4384_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000000010: n4384_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000000001: n4384_o = 1'b0; + default: n4384_o = 1'b0; + endcase + /* decoder.vhd:635:5 */ + always @* + case (n4277_o) + 63'b100000000000000000000000000000000000000000000000000000000000000: n4387_o = 1'b0; + 63'b010000000000000000000000000000000000000000000000000000000000000: n4387_o = 1'b0; + 63'b001000000000000000000000000000000000000000000000000000000000000: n4387_o = 1'b0; + 63'b000100000000000000000000000000000000000000000000000000000000000: n4387_o = 1'b0; + 63'b000010000000000000000000000000000000000000000000000000000000000: n4387_o = 1'b0; + 63'b000001000000000000000000000000000000000000000000000000000000000: n4387_o = 1'b0; + 63'b000000100000000000000000000000000000000000000000000000000000000: n4387_o = 1'b0; + 63'b000000010000000000000000000000000000000000000000000000000000000: n4387_o = 1'b0; + 63'b000000001000000000000000000000000000000000000000000000000000000: n4387_o = 1'b0; + 63'b000000000100000000000000000000000000000000000000000000000000000: n4387_o = 1'b0; + 63'b000000000010000000000000000000000000000000000000000000000000000: n4387_o = 1'b0; + 63'b000000000001000000000000000000000000000000000000000000000000000: n4387_o = 1'b0; + 63'b000000000000100000000000000000000000000000000000000000000000000: n4387_o = 1'b0; + 63'b000000000000010000000000000000000000000000000000000000000000000: n4387_o = 1'b0; + 63'b000000000000001000000000000000000000000000000000000000000000000: n4387_o = 1'b0; + 63'b000000000000000100000000000000000000000000000000000000000000000: n4387_o = 1'b0; + 63'b000000000000000010000000000000000000000000000000000000000000000: n4387_o = 1'b0; + 63'b000000000000000001000000000000000000000000000000000000000000000: n4387_o = 1'b0; + 63'b000000000000000000100000000000000000000000000000000000000000000: n4387_o = 1'b0; + 63'b000000000000000000010000000000000000000000000000000000000000000: n4387_o = 1'b0; + 63'b000000000000000000001000000000000000000000000000000000000000000: n4387_o = 1'b0; + 63'b000000000000000000000100000000000000000000000000000000000000000: n4387_o = 1'b0; + 63'b000000000000000000000010000000000000000000000000000000000000000: n4387_o = 1'b0; + 63'b000000000000000000000001000000000000000000000000000000000000000: n4387_o = 1'b0; + 63'b000000000000000000000000100000000000000000000000000000000000000: n4387_o = 1'b0; + 63'b000000000000000000000000010000000000000000000000000000000000000: n4387_o = 1'b0; + 63'b000000000000000000000000001000000000000000000000000000000000000: n4387_o = 1'b0; + 63'b000000000000000000000000000100000000000000000000000000000000000: n4387_o = 1'b0; + 63'b000000000000000000000000000010000000000000000000000000000000000: n4387_o = 1'b0; + 63'b000000000000000000000000000001000000000000000000000000000000000: n4387_o = n3301_o; + 63'b000000000000000000000000000000100000000000000000000000000000000: n4387_o = n3265_o; + 63'b000000000000000000000000000000010000000000000000000000000000000: n4387_o = n3234_o; + 63'b000000000000000000000000000000001000000000000000000000000000000: n4387_o = n3200_o; + 63'b000000000000000000000000000000000100000000000000000000000000000: n4387_o = n3174_o; + 63'b000000000000000000000000000000000010000000000000000000000000000: n4387_o = n3148_o; + 63'b000000000000000000000000000000000001000000000000000000000000000: n4387_o = 1'b0; + 63'b000000000000000000000000000000000000100000000000000000000000000: n4387_o = 1'b0; + 63'b000000000000000000000000000000000000010000000000000000000000000: n4387_o = n3062_o; + 63'b000000000000000000000000000000000000001000000000000000000000000: n4387_o = n3028_o; + 63'b000000000000000000000000000000000000000100000000000000000000000: n4387_o = n2999_o; + 63'b000000000000000000000000000000000000000010000000000000000000000: n4387_o = 1'b0; + 63'b000000000000000000000000000000000000000001000000000000000000000: n4387_o = 1'b0; + 63'b000000000000000000000000000000000000000000100000000000000000000: n4387_o = 1'b0; + 63'b000000000000000000000000000000000000000000010000000000000000000: n4387_o = 1'b0; + 63'b000000000000000000000000000000000000000000001000000000000000000: n4387_o = 1'b0; + 63'b000000000000000000000000000000000000000000000100000000000000000: n4387_o = 1'b0; + 63'b000000000000000000000000000000000000000000000010000000000000000: n4387_o = n2837_o; + 63'b000000000000000000000000000000000000000000000001000000000000000: n4387_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000100000000000000: n4387_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000010000000000000: n4387_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000001000000000000: n4387_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000100000000000: n4387_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000010000000000: n4387_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000001000000000: n4387_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000100000000: n4387_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000010000000: n4387_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000001000000: n4387_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000100000: n4387_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000010000: n4387_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000001000: n4387_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000000100: n4387_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000000010: n4387_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000000001: n4387_o = 1'b0; + default: n4387_o = 1'b0; + endcase + /* decoder.vhd:635:5 */ + always @* + case (n4277_o) + 63'b100000000000000000000000000000000000000000000000000000000000000: n4397_o = 4'b0000; + 63'b010000000000000000000000000000000000000000000000000000000000000: n4397_o = 4'b0000; + 63'b001000000000000000000000000000000000000000000000000000000000000: n4397_o = 4'b0000; + 63'b000100000000000000000000000000000000000000000000000000000000000: n4397_o = 4'b0000; + 63'b000010000000000000000000000000000000000000000000000000000000000: n4397_o = 4'b0000; + 63'b000001000000000000000000000000000000000000000000000000000000000: n4397_o = 4'b0000; + 63'b000000100000000000000000000000000000000000000000000000000000000: n4397_o = 4'b0000; + 63'b000000010000000000000000000000000000000000000000000000000000000: n4397_o = 4'b0000; + 63'b000000001000000000000000000000000000000000000000000000000000000: n4397_o = 4'b0000; + 63'b000000000100000000000000000000000000000000000000000000000000000: n4397_o = 4'b0000; + 63'b000000000010000000000000000000000000000000000000000000000000000: n4397_o = 4'b0000; + 63'b000000000001000000000000000000000000000000000000000000000000000: n4397_o = 4'b0000; + 63'b000000000000100000000000000000000000000000000000000000000000000: n4397_o = 4'b0000; + 63'b000000000000010000000000000000000000000000000000000000000000000: n4397_o = 4'b0000; + 63'b000000000000001000000000000000000000000000000000000000000000000: n4397_o = 4'b0000; + 63'b000000000000000100000000000000000000000000000000000000000000000: n4397_o = 4'b0000; + 63'b000000000000000010000000000000000000000000000000000000000000000: n4397_o = 4'b0000; + 63'b000000000000000001000000000000000000000000000000000000000000000: n4397_o = 4'b0000; + 63'b000000000000000000100000000000000000000000000000000000000000000: n4397_o = 4'b0000; + 63'b000000000000000000010000000000000000000000000000000000000000000: n4397_o = 4'b0000; + 63'b000000000000000000001000000000000000000000000000000000000000000: n4397_o = 4'b0000; + 63'b000000000000000000000100000000000000000000000000000000000000000: n4397_o = 4'b0000; + 63'b000000000000000000000010000000000000000000000000000000000000000: n4397_o = 4'b0000; + 63'b000000000000000000000001000000000000000000000000000000000000000: n4397_o = 4'b0000; + 63'b000000000000000000000000100000000000000000000000000000000000000: n4397_o = 4'b0000; + 63'b000000000000000000000000010000000000000000000000000000000000000: n4397_o = 4'b0000; + 63'b000000000000000000000000001000000000000000000000000000000000000: n4397_o = 4'b0000; + 63'b000000000000000000000000000100000000000000000000000000000000000: n4397_o = 4'b0000; + 63'b000000000000000000000000000010000000000000000000000000000000000: n4397_o = 4'b0000; + 63'b000000000000000000000000000001000000000000000000000000000000000: n4397_o = 4'b0001; + 63'b000000000000000000000000000000100000000000000000000000000000000: n4397_o = 4'b1000; + 63'b000000000000000000000000000000010000000000000000000000000000000: n4397_o = n3209_o; + 63'b000000000000000000000000000000001000000000000000000000000000000: n4397_o = 4'b1010; + 63'b000000000000000000000000000000000100000000000000000000000000000: n4397_o = 4'b1001; + 63'b000000000000000000000000000000000010000000000000000000000000000: n4397_o = 4'b0101; + 63'b000000000000000000000000000000000001000000000000000000000000000: n4397_o = 4'b0000; + 63'b000000000000000000000000000000000000100000000000000000000000000: n4397_o = 4'b0000; + 63'b000000000000000000000000000000000000010000000000000000000000000: n4397_o = n3064_o; + 63'b000000000000000000000000000000000000001000000000000000000000000: n4397_o = 4'b0010; + 63'b000000000000000000000000000000000000000100000000000000000000000: n4397_o = 4'b0000; + 63'b000000000000000000000000000000000000000010000000000000000000000: n4397_o = 4'b0000; + 63'b000000000000000000000000000000000000000001000000000000000000000: n4397_o = 4'b0000; + 63'b000000000000000000000000000000000000000000100000000000000000000: n4397_o = 4'b0000; + 63'b000000000000000000000000000000000000000000010000000000000000000: n4397_o = 4'b0000; + 63'b000000000000000000000000000000000000000000001000000000000000000: n4397_o = 4'b0000; + 63'b000000000000000000000000000000000000000000000100000000000000000: n4397_o = 4'b0000; + 63'b000000000000000000000000000000000000000000000010000000000000000: n4397_o = n2839_o; + 63'b000000000000000000000000000000000000000000000001000000000000000: n4397_o = 4'b0000; + 63'b000000000000000000000000000000000000000000000000100000000000000: n4397_o = 4'b0000; + 63'b000000000000000000000000000000000000000000000000010000000000000: n4397_o = 4'b0000; + 63'b000000000000000000000000000000000000000000000000001000000000000: n4397_o = 4'b0000; + 63'b000000000000000000000000000000000000000000000000000100000000000: n4397_o = 4'b0000; + 63'b000000000000000000000000000000000000000000000000000010000000000: n4397_o = 4'b0000; + 63'b000000000000000000000000000000000000000000000000000001000000000: n4397_o = 4'b0000; + 63'b000000000000000000000000000000000000000000000000000000100000000: n4397_o = 4'b0000; + 63'b000000000000000000000000000000000000000000000000000000010000000: n4397_o = 4'b0000; + 63'b000000000000000000000000000000000000000000000000000000001000000: n4397_o = 4'b0000; + 63'b000000000000000000000000000000000000000000000000000000000100000: n4397_o = 4'b0000; + 63'b000000000000000000000000000000000000000000000000000000000010000: n4397_o = 4'b0000; + 63'b000000000000000000000000000000000000000000000000000000000001000: n4397_o = 4'b0000; + 63'b000000000000000000000000000000000000000000000000000000000000100: n4397_o = 4'b0000; + 63'b000000000000000000000000000000000000000000000000000000000000010: n4397_o = 4'b0000; + 63'b000000000000000000000000000000000000000000000000000000000000001: n4397_o = 4'b0000; + default: n4397_o = 4'b0000; + endcase + assign n4399_o = opc_opcode_q[5]; + /* decoder.vhd:635:5 */ + always @* + case (n4277_o) + 63'b100000000000000000000000000000000000000000000000000000000000000: n4400_o = n4399_o; + 63'b010000000000000000000000000000000000000000000000000000000000000: n4400_o = n4399_o; + 63'b001000000000000000000000000000000000000000000000000000000000000: n4400_o = n4399_o; + 63'b000100000000000000000000000000000000000000000000000000000000000: n4400_o = n4399_o; + 63'b000010000000000000000000000000000000000000000000000000000000000: n4400_o = n4399_o; + 63'b000001000000000000000000000000000000000000000000000000000000000: n4400_o = n4399_o; + 63'b000000100000000000000000000000000000000000000000000000000000000: n4400_o = n4399_o; + 63'b000000010000000000000000000000000000000000000000000000000000000: n4400_o = n4399_o; + 63'b000000001000000000000000000000000000000000000000000000000000000: n4400_o = n4399_o; + 63'b000000000100000000000000000000000000000000000000000000000000000: n4400_o = n4399_o; + 63'b000000000010000000000000000000000000000000000000000000000000000: n4400_o = n4399_o; + 63'b000000000001000000000000000000000000000000000000000000000000000: n4400_o = n4399_o; + 63'b000000000000100000000000000000000000000000000000000000000000000: n4400_o = n4399_o; + 63'b000000000000010000000000000000000000000000000000000000000000000: n4400_o = n4399_o; + 63'b000000000000001000000000000000000000000000000000000000000000000: n4400_o = n4399_o; + 63'b000000000000000100000000000000000000000000000000000000000000000: n4400_o = n4399_o; + 63'b000000000000000010000000000000000000000000000000000000000000000: n4400_o = n4399_o; + 63'b000000000000000001000000000000000000000000000000000000000000000: n4400_o = n4399_o; + 63'b000000000000000000100000000000000000000000000000000000000000000: n4400_o = n4399_o; + 63'b000000000000000000010000000000000000000000000000000000000000000: n4400_o = n4399_o; + 63'b000000000000000000001000000000000000000000000000000000000000000: n4400_o = n4399_o; + 63'b000000000000000000000100000000000000000000000000000000000000000: n4400_o = n4399_o; + 63'b000000000000000000000010000000000000000000000000000000000000000: n4400_o = n4399_o; + 63'b000000000000000000000001000000000000000000000000000000000000000: n4400_o = n4399_o; + 63'b000000000000000000000000100000000000000000000000000000000000000: n4400_o = n4399_o; + 63'b000000000000000000000000010000000000000000000000000000000000000: n4400_o = n4399_o; + 63'b000000000000000000000000001000000000000000000000000000000000000: n4400_o = n4399_o; + 63'b000000000000000000000000000100000000000000000000000000000000000: n4400_o = n4399_o; + 63'b000000000000000000000000000010000000000000000000000000000000000: n4400_o = n4399_o; + 63'b000000000000000000000000000001000000000000000000000000000000000: n4400_o = n3283_o; + 63'b000000000000000000000000000000100000000000000000000000000000000: n4400_o = n4399_o; + 63'b000000000000000000000000000000010000000000000000000000000000000: n4400_o = n3218_o; + 63'b000000000000000000000000000000001000000000000000000000000000000: n4400_o = n4399_o; + 63'b000000000000000000000000000000000100000000000000000000000000000: n4400_o = n4399_o; + 63'b000000000000000000000000000000000010000000000000000000000000000: n4400_o = n4399_o; + 63'b000000000000000000000000000000000001000000000000000000000000000: n4400_o = n4399_o; + 63'b000000000000000000000000000000000000100000000000000000000000000: n4400_o = n4399_o; + 63'b000000000000000000000000000000000000010000000000000000000000000: n4400_o = n4399_o; + 63'b000000000000000000000000000000000000001000000000000000000000000: n4400_o = n3012_o; + 63'b000000000000000000000000000000000000000100000000000000000000000: n4400_o = n4399_o; + 63'b000000000000000000000000000000000000000010000000000000000000000: n4400_o = n4399_o; + 63'b000000000000000000000000000000000000000001000000000000000000000: n4400_o = n4399_o; + 63'b000000000000000000000000000000000000000000100000000000000000000: n4400_o = n4399_o; + 63'b000000000000000000000000000000000000000000010000000000000000000: n4400_o = n4399_o; + 63'b000000000000000000000000000000000000000000001000000000000000000: n4400_o = n4399_o; + 63'b000000000000000000000000000000000000000000000100000000000000000: n4400_o = n4399_o; + 63'b000000000000000000000000000000000000000000000010000000000000000: n4400_o = n2841_o; + 63'b000000000000000000000000000000000000000000000001000000000000000: n4400_o = n4399_o; + 63'b000000000000000000000000000000000000000000000000100000000000000: n4400_o = n4399_o; + 63'b000000000000000000000000000000000000000000000000010000000000000: n4400_o = n4399_o; + 63'b000000000000000000000000000000000000000000000000001000000000000: n4400_o = n4399_o; + 63'b000000000000000000000000000000000000000000000000000100000000000: n4400_o = n4399_o; + 63'b000000000000000000000000000000000000000000000000000010000000000: n4400_o = n4399_o; + 63'b000000000000000000000000000000000000000000000000000001000000000: n4400_o = n4399_o; + 63'b000000000000000000000000000000000000000000000000000000100000000: n4400_o = n4399_o; + 63'b000000000000000000000000000000000000000000000000000000010000000: n4400_o = n4399_o; + 63'b000000000000000000000000000000000000000000000000000000001000000: n4400_o = n4399_o; + 63'b000000000000000000000000000000000000000000000000000000000100000: n4400_o = n4399_o; + 63'b000000000000000000000000000000000000000000000000000000000010000: n4400_o = n4399_o; + 63'b000000000000000000000000000000000000000000000000000000000001000: n4400_o = n4399_o; + 63'b000000000000000000000000000000000000000000000000000000000000100: n4400_o = n4399_o; + 63'b000000000000000000000000000000000000000000000000000000000000010: n4400_o = n4399_o; + 63'b000000000000000000000000000000000000000000000000000000000000001: n4400_o = n4399_o; + default: n4400_o = n4399_o; + endcase + assign n4401_o = opc_opcode_q[7:6]; + /* decoder.vhd:635:5 */ + always @* + case (n4277_o) + 63'b100000000000000000000000000000000000000000000000000000000000000: n4403_o = 2'b01; + 63'b010000000000000000000000000000000000000000000000000000000000000: n4403_o = n4244_o; + 63'b001000000000000000000000000000000000000000000000000000000000000: n4403_o = n4191_o; + 63'b000100000000000000000000000000000000000000000000000000000000000: n4403_o = 2'b01; + 63'b000010000000000000000000000000000000000000000000000000000000000: n4403_o = 2'b01; + 63'b000001000000000000000000000000000000000000000000000000000000000: n4403_o = 2'b01; + 63'b000000100000000000000000000000000000000000000000000000000000000: n4403_o = 2'b01; + 63'b000000010000000000000000000000000000000000000000000000000000000: n4403_o = 2'b01; + 63'b000000001000000000000000000000000000000000000000000000000000000: n4403_o = 2'b01; + 63'b000000000100000000000000000000000000000000000000000000000000000: n4403_o = 2'b01; + 63'b000000000010000000000000000000000000000000000000000000000000000: n4403_o = n4018_o; + 63'b000000000001000000000000000000000000000000000000000000000000000: n4403_o = 2'b01; + 63'b000000000000100000000000000000000000000000000000000000000000000: n4403_o = 2'b01; + 63'b000000000000010000000000000000000000000000000000000000000000000: n4403_o = 2'b01; + 63'b000000000000001000000000000000000000000000000000000000000000000: n4403_o = 2'b01; + 63'b000000000000000100000000000000000000000000000000000000000000000: n4403_o = n3764_o; + 63'b000000000000000010000000000000000000000000000000000000000000000: n4403_o = 2'b01; + 63'b000000000000000001000000000000000000000000000000000000000000000: n4403_o = 2'b01; + 63'b000000000000000000100000000000000000000000000000000000000000000: n4403_o = 2'b01; + 63'b000000000000000000010000000000000000000000000000000000000000000: n4403_o = 2'b01; + 63'b000000000000000000001000000000000000000000000000000000000000000: n4403_o = 2'b01; + 63'b000000000000000000000100000000000000000000000000000000000000000: n4403_o = 2'b01; + 63'b000000000000000000000010000000000000000000000000000000000000000: n4403_o = 2'b01; + 63'b000000000000000000000001000000000000000000000000000000000000000: n4403_o = n3441_o; + 63'b000000000000000000000000100000000000000000000000000000000000000: n4403_o = n3410_o; + 63'b000000000000000000000000010000000000000000000000000000000000000: n4403_o = 2'b01; + 63'b000000000000000000000000001000000000000000000000000000000000000: n4403_o = 2'b01; + 63'b000000000000000000000000000100000000000000000000000000000000000: n4403_o = n3352_o; + 63'b000000000000000000000000000010000000000000000000000000000000000: n4403_o = 2'b01; + 63'b000000000000000000000000000001000000000000000000000000000000000: n4403_o = 2'b01; + 63'b000000000000000000000000000000100000000000000000000000000000000: n4403_o = 2'b01; + 63'b000000000000000000000000000000010000000000000000000000000000000: n4403_o = 2'b01; + 63'b000000000000000000000000000000001000000000000000000000000000000: n4403_o = 2'b01; + 63'b000000000000000000000000000000000100000000000000000000000000000: n4403_o = 2'b01; + 63'b000000000000000000000000000000000010000000000000000000000000000: n4403_o = 2'b01; + 63'b000000000000000000000000000000000001000000000000000000000000000: n4403_o = 2'b01; + 63'b000000000000000000000000000000000000100000000000000000000000000: n4403_o = 2'b01; + 63'b000000000000000000000000000000000000010000000000000000000000000: n4403_o = 2'b01; + 63'b000000000000000000000000000000000000001000000000000000000000000: n4403_o = 2'b01; + 63'b000000000000000000000000000000000000000100000000000000000000000: n4403_o = 2'b01; + 63'b000000000000000000000000000000000000000010000000000000000000000: n4403_o = n2968_o; + 63'b000000000000000000000000000000000000000001000000000000000000000: n4403_o = 2'b01; + 63'b000000000000000000000000000000000000000000100000000000000000000: n4403_o = 2'b01; + 63'b000000000000000000000000000000000000000000010000000000000000000: n4403_o = 2'b01; + 63'b000000000000000000000000000000000000000000001000000000000000000: n4403_o = 2'b01; + 63'b000000000000000000000000000000000000000000000100000000000000000: n4403_o = 2'b01; + 63'b000000000000000000000000000000000000000000000010000000000000000: n4403_o = 2'b01; + 63'b000000000000000000000000000000000000000000000001000000000000000: n4403_o = 2'b01; + 63'b000000000000000000000000000000000000000000000000100000000000000: n4403_o = 2'b01; + 63'b000000000000000000000000000000000000000000000000010000000000000: n4403_o = 2'b01; + 63'b000000000000000000000000000000000000000000000000001000000000000: n4403_o = 2'b01; + 63'b000000000000000000000000000000000000000000000000000100000000000: n4403_o = 2'b01; + 63'b000000000000000000000000000000000000000000000000000010000000000: n4403_o = 2'b01; + 63'b000000000000000000000000000000000000000000000000000001000000000: n4403_o = 2'b01; + 63'b000000000000000000000000000000000000000000000000000000100000000: n4403_o = 2'b01; + 63'b000000000000000000000000000000000000000000000000000000010000000: n4403_o = 2'b01; + 63'b000000000000000000000000000000000000000000000000000000001000000: n4403_o = 2'b01; + 63'b000000000000000000000000000000000000000000000000000000000100000: n4403_o = n2577_o; + 63'b000000000000000000000000000000000000000000000000000000000010000: n4403_o = 2'b01; + 63'b000000000000000000000000000000000000000000000000000000000001000: n4403_o = 2'b01; + 63'b000000000000000000000000000000000000000000000000000000000000100: n4403_o = n2329_o; + 63'b000000000000000000000000000000000000000000000000000000000000010: n4403_o = 2'b01; + 63'b000000000000000000000000000000000000000000000000000000000000001: n4403_o = n2219_o; + default: n4403_o = 2'b01; + endcase + /* decoder.vhd:635:5 */ + always @* + case (n4277_o) + 63'b100000000000000000000000000000000000000000000000000000000000000: n4406_o = 1'b0; + 63'b010000000000000000000000000000000000000000000000000000000000000: n4406_o = 1'b0; + 63'b001000000000000000000000000000000000000000000000000000000000000: n4406_o = 1'b0; + 63'b000100000000000000000000000000000000000000000000000000000000000: n4406_o = 1'b0; + 63'b000010000000000000000000000000000000000000000000000000000000000: n4406_o = 1'b0; + 63'b000001000000000000000000000000000000000000000000000000000000000: n4406_o = 1'b0; + 63'b000000100000000000000000000000000000000000000000000000000000000: n4406_o = 1'b0; + 63'b000000010000000000000000000000000000000000000000000000000000000: n4406_o = 1'b0; + 63'b000000001000000000000000000000000000000000000000000000000000000: n4406_o = 1'b0; + 63'b000000000100000000000000000000000000000000000000000000000000000: n4406_o = 1'b0; + 63'b000000000010000000000000000000000000000000000000000000000000000: n4406_o = 1'b0; + 63'b000000000001000000000000000000000000000000000000000000000000000: n4406_o = 1'b0; + 63'b000000000000100000000000000000000000000000000000000000000000000: n4406_o = 1'b0; + 63'b000000000000010000000000000000000000000000000000000000000000000: n4406_o = n3902_o; + 63'b000000000000001000000000000000000000000000000000000000000000000: n4406_o = 1'b0; + 63'b000000000000000100000000000000000000000000000000000000000000000: n4406_o = 1'b0; + 63'b000000000000000010000000000000000000000000000000000000000000000: n4406_o = 1'b0; + 63'b000000000000000001000000000000000000000000000000000000000000000: n4406_o = 1'b0; + 63'b000000000000000000100000000000000000000000000000000000000000000: n4406_o = 1'b0; + 63'b000000000000000000010000000000000000000000000000000000000000000: n4406_o = 1'b0; + 63'b000000000000000000001000000000000000000000000000000000000000000: n4406_o = 1'b0; + 63'b000000000000000000000100000000000000000000000000000000000000000: n4406_o = 1'b0; + 63'b000000000000000000000010000000000000000000000000000000000000000: n4406_o = 1'b0; + 63'b000000000000000000000001000000000000000000000000000000000000000: n4406_o = 1'b0; + 63'b000000000000000000000000100000000000000000000000000000000000000: n4406_o = 1'b0; + 63'b000000000000000000000000010000000000000000000000000000000000000: n4406_o = 1'b0; + 63'b000000000000000000000000001000000000000000000000000000000000000: n4406_o = 1'b0; + 63'b000000000000000000000000000100000000000000000000000000000000000: n4406_o = 1'b0; + 63'b000000000000000000000000000010000000000000000000000000000000000: n4406_o = 1'b0; + 63'b000000000000000000000000000001000000000000000000000000000000000: n4406_o = 1'b0; + 63'b000000000000000000000000000000100000000000000000000000000000000: n4406_o = 1'b0; + 63'b000000000000000000000000000000010000000000000000000000000000000: n4406_o = 1'b0; + 63'b000000000000000000000000000000001000000000000000000000000000000: n4406_o = 1'b0; + 63'b000000000000000000000000000000000100000000000000000000000000000: n4406_o = 1'b0; + 63'b000000000000000000000000000000000010000000000000000000000000000: n4406_o = 1'b0; + 63'b000000000000000000000000000000000001000000000000000000000000000: n4406_o = 1'b0; + 63'b000000000000000000000000000000000000100000000000000000000000000: n4406_o = 1'b0; + 63'b000000000000000000000000000000000000010000000000000000000000000: n4406_o = 1'b0; + 63'b000000000000000000000000000000000000001000000000000000000000000: n4406_o = 1'b0; + 63'b000000000000000000000000000000000000000100000000000000000000000: n4406_o = 1'b0; + 63'b000000000000000000000000000000000000000010000000000000000000000: n4406_o = 1'b0; + 63'b000000000000000000000000000000000000000001000000000000000000000: n4406_o = 1'b0; + 63'b000000000000000000000000000000000000000000100000000000000000000: n4406_o = 1'b0; + 63'b000000000000000000000000000000000000000000010000000000000000000: n4406_o = 1'b0; + 63'b000000000000000000000000000000000000000000001000000000000000000: n4406_o = 1'b0; + 63'b000000000000000000000000000000000000000000000100000000000000000: n4406_o = 1'b0; + 63'b000000000000000000000000000000000000000000000010000000000000000: n4406_o = 1'b0; + 63'b000000000000000000000000000000000000000000000001000000000000000: n4406_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000100000000000000: n4406_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000010000000000000: n4406_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000001000000000000: n4406_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000100000000000: n4406_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000010000000000: n4406_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000001000000000: n4406_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000100000000: n4406_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000010000000: n4406_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000001000000: n4406_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000100000: n4406_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000010000: n4406_o = n2467_o; + 63'b000000000000000000000000000000000000000000000000000000000001000: n4406_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000000100: n4406_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000000010: n4406_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000000001: n4406_o = 1'b0; + default: n4406_o = 1'b0; + endcase + /* decoder.vhd:635:5 */ + always @* + case (n4277_o) + 63'b100000000000000000000000000000000000000000000000000000000000000: n4409_o = 1'b0; + 63'b010000000000000000000000000000000000000000000000000000000000000: n4409_o = 1'b0; + 63'b001000000000000000000000000000000000000000000000000000000000000: n4409_o = 1'b0; + 63'b000100000000000000000000000000000000000000000000000000000000000: n4409_o = 1'b0; + 63'b000010000000000000000000000000000000000000000000000000000000000: n4409_o = 1'b0; + 63'b000001000000000000000000000000000000000000000000000000000000000: n4409_o = 1'b0; + 63'b000000100000000000000000000000000000000000000000000000000000000: n4409_o = 1'b0; + 63'b000000010000000000000000000000000000000000000000000000000000000: n4409_o = 1'b0; + 63'b000000001000000000000000000000000000000000000000000000000000000: n4409_o = 1'b0; + 63'b000000000100000000000000000000000000000000000000000000000000000: n4409_o = 1'b0; + 63'b000000000010000000000000000000000000000000000000000000000000000: n4409_o = 1'b0; + 63'b000000000001000000000000000000000000000000000000000000000000000: n4409_o = 1'b0; + 63'b000000000000100000000000000000000000000000000000000000000000000: n4409_o = 1'b0; + 63'b000000000000010000000000000000000000000000000000000000000000000: n4409_o = n3904_o; + 63'b000000000000001000000000000000000000000000000000000000000000000: n4409_o = 1'b0; + 63'b000000000000000100000000000000000000000000000000000000000000000: n4409_o = 1'b0; + 63'b000000000000000010000000000000000000000000000000000000000000000: n4409_o = 1'b0; + 63'b000000000000000001000000000000000000000000000000000000000000000: n4409_o = 1'b0; + 63'b000000000000000000100000000000000000000000000000000000000000000: n4409_o = 1'b0; + 63'b000000000000000000010000000000000000000000000000000000000000000: n4409_o = 1'b0; + 63'b000000000000000000001000000000000000000000000000000000000000000: n4409_o = 1'b0; + 63'b000000000000000000000100000000000000000000000000000000000000000: n4409_o = 1'b0; + 63'b000000000000000000000010000000000000000000000000000000000000000: n4409_o = 1'b0; + 63'b000000000000000000000001000000000000000000000000000000000000000: n4409_o = 1'b0; + 63'b000000000000000000000000100000000000000000000000000000000000000: n4409_o = 1'b0; + 63'b000000000000000000000000010000000000000000000000000000000000000: n4409_o = 1'b0; + 63'b000000000000000000000000001000000000000000000000000000000000000: n4409_o = 1'b0; + 63'b000000000000000000000000000100000000000000000000000000000000000: n4409_o = 1'b0; + 63'b000000000000000000000000000010000000000000000000000000000000000: n4409_o = 1'b0; + 63'b000000000000000000000000000001000000000000000000000000000000000: n4409_o = 1'b0; + 63'b000000000000000000000000000000100000000000000000000000000000000: n4409_o = 1'b0; + 63'b000000000000000000000000000000010000000000000000000000000000000: n4409_o = 1'b0; + 63'b000000000000000000000000000000001000000000000000000000000000000: n4409_o = 1'b0; + 63'b000000000000000000000000000000000100000000000000000000000000000: n4409_o = 1'b0; + 63'b000000000000000000000000000000000010000000000000000000000000000: n4409_o = 1'b0; + 63'b000000000000000000000000000000000001000000000000000000000000000: n4409_o = 1'b0; + 63'b000000000000000000000000000000000000100000000000000000000000000: n4409_o = 1'b0; + 63'b000000000000000000000000000000000000010000000000000000000000000: n4409_o = 1'b0; + 63'b000000000000000000000000000000000000001000000000000000000000000: n4409_o = 1'b0; + 63'b000000000000000000000000000000000000000100000000000000000000000: n4409_o = 1'b0; + 63'b000000000000000000000000000000000000000010000000000000000000000: n4409_o = 1'b0; + 63'b000000000000000000000000000000000000000001000000000000000000000: n4409_o = 1'b0; + 63'b000000000000000000000000000000000000000000100000000000000000000: n4409_o = 1'b0; + 63'b000000000000000000000000000000000000000000010000000000000000000: n4409_o = 1'b0; + 63'b000000000000000000000000000000000000000000001000000000000000000: n4409_o = 1'b0; + 63'b000000000000000000000000000000000000000000000100000000000000000: n4409_o = 1'b0; + 63'b000000000000000000000000000000000000000000000010000000000000000: n4409_o = 1'b0; + 63'b000000000000000000000000000000000000000000000001000000000000000: n4409_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000100000000000000: n4409_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000010000000000000: n4409_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000001000000000000: n4409_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000100000000000: n4409_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000010000000000: n4409_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000001000000000: n4409_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000100000000: n4409_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000010000000: n4409_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000001000000: n4409_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000100000: n4409_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000010000: n4409_o = n2469_o; + 63'b000000000000000000000000000000000000000000000000000000000001000: n4409_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000000100: n4409_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000000010: n4409_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000000001: n4409_o = 1'b0; + default: n4409_o = 1'b0; + endcase + /* decoder.vhd:635:5 */ + always @* + case (n4277_o) + 63'b100000000000000000000000000000000000000000000000000000000000000: n4412_o = 2'b00; + 63'b010000000000000000000000000000000000000000000000000000000000000: n4412_o = 2'b00; + 63'b001000000000000000000000000000000000000000000000000000000000000: n4412_o = 2'b00; + 63'b000100000000000000000000000000000000000000000000000000000000000: n4412_o = 2'b00; + 63'b000010000000000000000000000000000000000000000000000000000000000: n4412_o = 2'b00; + 63'b000001000000000000000000000000000000000000000000000000000000000: n4412_o = 2'b00; + 63'b000000100000000000000000000000000000000000000000000000000000000: n4412_o = 2'b00; + 63'b000000010000000000000000000000000000000000000000000000000000000: n4412_o = 2'b00; + 63'b000000001000000000000000000000000000000000000000000000000000000: n4412_o = 2'b00; + 63'b000000000100000000000000000000000000000000000000000000000000000: n4412_o = 2'b00; + 63'b000000000010000000000000000000000000000000000000000000000000000: n4412_o = 2'b00; + 63'b000000000001000000000000000000000000000000000000000000000000000: n4412_o = 2'b00; + 63'b000000000000100000000000000000000000000000000000000000000000000: n4412_o = 2'b00; + 63'b000000000000010000000000000000000000000000000000000000000000000: n4412_o = 2'b00; + 63'b000000000000001000000000000000000000000000000000000000000000000: n4412_o = 2'b00; + 63'b000000000000000100000000000000000000000000000000000000000000000: n4412_o = 2'b00; + 63'b000000000000000010000000000000000000000000000000000000000000000: n4412_o = 2'b00; + 63'b000000000000000001000000000000000000000000000000000000000000000: n4412_o = 2'b00; + 63'b000000000000000000100000000000000000000000000000000000000000000: n4412_o = n3644_o; + 63'b000000000000000000010000000000000000000000000000000000000000000: n4412_o = 2'b00; + 63'b000000000000000000001000000000000000000000000000000000000000000: n4412_o = 2'b00; + 63'b000000000000000000000100000000000000000000000000000000000000000: n4412_o = 2'b00; + 63'b000000000000000000000010000000000000000000000000000000000000000: n4412_o = 2'b00; + 63'b000000000000000000000001000000000000000000000000000000000000000: n4412_o = 2'b00; + 63'b000000000000000000000000100000000000000000000000000000000000000: n4412_o = 2'b00; + 63'b000000000000000000000000010000000000000000000000000000000000000: n4412_o = 2'b00; + 63'b000000000000000000000000001000000000000000000000000000000000000: n4412_o = 2'b00; + 63'b000000000000000000000000000100000000000000000000000000000000000: n4412_o = 2'b00; + 63'b000000000000000000000000000010000000000000000000000000000000000: n4412_o = 2'b00; + 63'b000000000000000000000000000001000000000000000000000000000000000: n4412_o = 2'b00; + 63'b000000000000000000000000000000100000000000000000000000000000000: n4412_o = 2'b00; + 63'b000000000000000000000000000000010000000000000000000000000000000: n4412_o = 2'b00; + 63'b000000000000000000000000000000001000000000000000000000000000000: n4412_o = 2'b00; + 63'b000000000000000000000000000000000100000000000000000000000000000: n4412_o = 2'b00; + 63'b000000000000000000000000000000000010000000000000000000000000000: n4412_o = 2'b00; + 63'b000000000000000000000000000000000001000000000000000000000000000: n4412_o = n3122_o; + 63'b000000000000000000000000000000000000100000000000000000000000000: n4412_o = 2'b00; + 63'b000000000000000000000000000000000000010000000000000000000000000: n4412_o = 2'b00; + 63'b000000000000000000000000000000000000001000000000000000000000000: n4412_o = 2'b00; + 63'b000000000000000000000000000000000000000100000000000000000000000: n4412_o = 2'b00; + 63'b000000000000000000000000000000000000000010000000000000000000000: n4412_o = 2'b00; + 63'b000000000000000000000000000000000000000001000000000000000000000: n4412_o = 2'b00; + 63'b000000000000000000000000000000000000000000100000000000000000000: n4412_o = 2'b00; + 63'b000000000000000000000000000000000000000000010000000000000000000: n4412_o = 2'b00; + 63'b000000000000000000000000000000000000000000001000000000000000000: n4412_o = 2'b00; + 63'b000000000000000000000000000000000000000000000100000000000000000: n4412_o = 2'b00; + 63'b000000000000000000000000000000000000000000000010000000000000000: n4412_o = 2'b00; + 63'b000000000000000000000000000000000000000000000001000000000000000: n4412_o = 2'b00; + 63'b000000000000000000000000000000000000000000000000100000000000000: n4412_o = 2'b00; + 63'b000000000000000000000000000000000000000000000000010000000000000: n4412_o = 2'b00; + 63'b000000000000000000000000000000000000000000000000001000000000000: n4412_o = 2'b00; + 63'b000000000000000000000000000000000000000000000000000100000000000: n4412_o = 2'b00; + 63'b000000000000000000000000000000000000000000000000000010000000000: n4412_o = 2'b00; + 63'b000000000000000000000000000000000000000000000000000001000000000: n4412_o = 2'b00; + 63'b000000000000000000000000000000000000000000000000000000100000000: n4412_o = 2'b00; + 63'b000000000000000000000000000000000000000000000000000000010000000: n4412_o = 2'b00; + 63'b000000000000000000000000000000000000000000000000000000001000000: n4412_o = 2'b00; + 63'b000000000000000000000000000000000000000000000000000000000100000: n4412_o = 2'b00; + 63'b000000000000000000000000000000000000000000000000000000000010000: n4412_o = 2'b00; + 63'b000000000000000000000000000000000000000000000000000000000001000: n4412_o = 2'b00; + 63'b000000000000000000000000000000000000000000000000000000000000100: n4412_o = 2'b00; + 63'b000000000000000000000000000000000000000000000000000000000000010: n4412_o = 2'b00; + 63'b000000000000000000000000000000000000000000000000000000000000001: n4412_o = 2'b00; + default: n4412_o = 2'b00; + endcase + /* decoder.vhd:635:5 */ + always @* + case (n4277_o) + 63'b100000000000000000000000000000000000000000000000000000000000000: n4415_o = 1'b0; + 63'b010000000000000000000000000000000000000000000000000000000000000: n4415_o = 1'b0; + 63'b001000000000000000000000000000000000000000000000000000000000000: n4415_o = 1'b0; + 63'b000100000000000000000000000000000000000000000000000000000000000: n4415_o = 1'b0; + 63'b000010000000000000000000000000000000000000000000000000000000000: n4415_o = 1'b0; + 63'b000001000000000000000000000000000000000000000000000000000000000: n4415_o = 1'b0; + 63'b000000100000000000000000000000000000000000000000000000000000000: n4415_o = n4103_o; + 63'b000000010000000000000000000000000000000000000000000000000000000: n4415_o = 1'b0; + 63'b000000001000000000000000000000000000000000000000000000000000000: n4415_o = n4079_o; + 63'b000000000100000000000000000000000000000000000000000000000000000: n4415_o = n4050_o; + 63'b000000000010000000000000000000000000000000000000000000000000000: n4415_o = 1'b0; + 63'b000000000001000000000000000000000000000000000000000000000000000: n4415_o = 1'b0; + 63'b000000000000100000000000000000000000000000000000000000000000000: n4415_o = 1'b0; + 63'b000000000000010000000000000000000000000000000000000000000000000: n4415_o = 1'b0; + 63'b000000000000001000000000000000000000000000000000000000000000000: n4415_o = 1'b0; + 63'b000000000000000100000000000000000000000000000000000000000000000: n4415_o = 1'b0; + 63'b000000000000000010000000000000000000000000000000000000000000000: n4415_o = 1'b0; + 63'b000000000000000001000000000000000000000000000000000000000000000: n4415_o = 1'b0; + 63'b000000000000000000100000000000000000000000000000000000000000000: n4415_o = 1'b0; + 63'b000000000000000000010000000000000000000000000000000000000000000: n4415_o = 1'b0; + 63'b000000000000000000001000000000000000000000000000000000000000000: n4415_o = 1'b0; + 63'b000000000000000000000100000000000000000000000000000000000000000: n4415_o = 1'b0; + 63'b000000000000000000000010000000000000000000000000000000000000000: n4415_o = 1'b0; + 63'b000000000000000000000001000000000000000000000000000000000000000: n4415_o = 1'b0; + 63'b000000000000000000000000100000000000000000000000000000000000000: n4415_o = 1'b0; + 63'b000000000000000000000000010000000000000000000000000000000000000: n4415_o = 1'b0; + 63'b000000000000000000000000001000000000000000000000000000000000000: n4415_o = 1'b0; + 63'b000000000000000000000000000100000000000000000000000000000000000: n4415_o = 1'b0; + 63'b000000000000000000000000000010000000000000000000000000000000000: n4415_o = 1'b0; + 63'b000000000000000000000000000001000000000000000000000000000000000: n4415_o = 1'b0; + 63'b000000000000000000000000000000100000000000000000000000000000000: n4415_o = 1'b0; + 63'b000000000000000000000000000000010000000000000000000000000000000: n4415_o = 1'b0; + 63'b000000000000000000000000000000001000000000000000000000000000000: n4415_o = 1'b0; + 63'b000000000000000000000000000000000100000000000000000000000000000: n4415_o = 1'b0; + 63'b000000000000000000000000000000000010000000000000000000000000000: n4415_o = 1'b0; + 63'b000000000000000000000000000000000001000000000000000000000000000: n4415_o = 1'b0; + 63'b000000000000000000000000000000000000100000000000000000000000000: n4415_o = 1'b0; + 63'b000000000000000000000000000000000000010000000000000000000000000: n4415_o = 1'b0; + 63'b000000000000000000000000000000000000001000000000000000000000000: n4415_o = 1'b0; + 63'b000000000000000000000000000000000000000100000000000000000000000: n4415_o = 1'b0; + 63'b000000000000000000000000000000000000000010000000000000000000000: n4415_o = 1'b0; + 63'b000000000000000000000000000000000000000001000000000000000000000: n4415_o = 1'b0; + 63'b000000000000000000000000000000000000000000100000000000000000000: n4415_o = 1'b0; + 63'b000000000000000000000000000000000000000000010000000000000000000: n4415_o = 1'b0; + 63'b000000000000000000000000000000000000000000001000000000000000000: n4415_o = 1'b0; + 63'b000000000000000000000000000000000000000000000100000000000000000: n4415_o = 1'b0; + 63'b000000000000000000000000000000000000000000000010000000000000000: n4415_o = 1'b0; + 63'b000000000000000000000000000000000000000000000001000000000000000: n4415_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000100000000000000: n4415_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000010000000000000: n4415_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000001000000000000: n4415_o = n2712_o; + 63'b000000000000000000000000000000000000000000000000000100000000000: n4415_o = n2665_o; + 63'b000000000000000000000000000000000000000000000000000010000000000: n4415_o = n2645_o; + 63'b000000000000000000000000000000000000000000000000000001000000000: n4415_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000100000000: n4415_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000010000000: n4415_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000001000000: n4415_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000100000: n4415_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000010000: n4415_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000001000: n4415_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000000100: n4415_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000000010: n4415_o = n2275_o; + 63'b000000000000000000000000000000000000000000000000000000000000001: n4415_o = n2221_o; + default: n4415_o = 1'b0; + endcase + /* decoder.vhd:635:5 */ + always @* + case (n4277_o) + 63'b100000000000000000000000000000000000000000000000000000000000000: n4418_o = 1'b0; + 63'b010000000000000000000000000000000000000000000000000000000000000: n4418_o = 1'b0; + 63'b001000000000000000000000000000000000000000000000000000000000000: n4418_o = 1'b0; + 63'b000100000000000000000000000000000000000000000000000000000000000: n4418_o = 1'b0; + 63'b000010000000000000000000000000000000000000000000000000000000000: n4418_o = 1'b0; + 63'b000001000000000000000000000000000000000000000000000000000000000: n4418_o = 1'b0; + 63'b000000100000000000000000000000000000000000000000000000000000000: n4418_o = 1'b0; + 63'b000000010000000000000000000000000000000000000000000000000000000: n4418_o = 1'b0; + 63'b000000001000000000000000000000000000000000000000000000000000000: n4418_o = 1'b0; + 63'b000000000100000000000000000000000000000000000000000000000000000: n4418_o = 1'b0; + 63'b000000000010000000000000000000000000000000000000000000000000000: n4418_o = 1'b0; + 63'b000000000001000000000000000000000000000000000000000000000000000: n4418_o = 1'b0; + 63'b000000000000100000000000000000000000000000000000000000000000000: n4418_o = 1'b0; + 63'b000000000000010000000000000000000000000000000000000000000000000: n4418_o = 1'b0; + 63'b000000000000001000000000000000000000000000000000000000000000000: n4418_o = 1'b0; + 63'b000000000000000100000000000000000000000000000000000000000000000: n4418_o = 1'b0; + 63'b000000000000000010000000000000000000000000000000000000000000000: n4418_o = 1'b0; + 63'b000000000000000001000000000000000000000000000000000000000000000: n4418_o = 1'b0; + 63'b000000000000000000100000000000000000000000000000000000000000000: n4418_o = 1'b0; + 63'b000000000000000000010000000000000000000000000000000000000000000: n4418_o = 1'b0; + 63'b000000000000000000001000000000000000000000000000000000000000000: n4418_o = 1'b0; + 63'b000000000000000000000100000000000000000000000000000000000000000: n4418_o = 1'b0; + 63'b000000000000000000000010000000000000000000000000000000000000000: n4418_o = 1'b0; + 63'b000000000000000000000001000000000000000000000000000000000000000: n4418_o = 1'b0; + 63'b000000000000000000000000100000000000000000000000000000000000000: n4418_o = 1'b0; + 63'b000000000000000000000000010000000000000000000000000000000000000: n4418_o = 1'b0; + 63'b000000000000000000000000001000000000000000000000000000000000000: n4418_o = 1'b0; + 63'b000000000000000000000000000100000000000000000000000000000000000: n4418_o = 1'b0; + 63'b000000000000000000000000000010000000000000000000000000000000000: n4418_o = 1'b0; + 63'b000000000000000000000000000001000000000000000000000000000000000: n4418_o = 1'b0; + 63'b000000000000000000000000000000100000000000000000000000000000000: n4418_o = 1'b0; + 63'b000000000000000000000000000000010000000000000000000000000000000: n4418_o = 1'b0; + 63'b000000000000000000000000000000001000000000000000000000000000000: n4418_o = 1'b0; + 63'b000000000000000000000000000000000100000000000000000000000000000: n4418_o = 1'b0; + 63'b000000000000000000000000000000000010000000000000000000000000000: n4418_o = 1'b0; + 63'b000000000000000000000000000000000001000000000000000000000000000: n4418_o = 1'b0; + 63'b000000000000000000000000000000000000100000000000000000000000000: n4418_o = 1'b0; + 63'b000000000000000000000000000000000000010000000000000000000000000: n4418_o = 1'b0; + 63'b000000000000000000000000000000000000001000000000000000000000000: n4418_o = 1'b0; + 63'b000000000000000000000000000000000000000100000000000000000000000: n4418_o = 1'b0; + 63'b000000000000000000000000000000000000000010000000000000000000000: n4418_o = 1'b0; + 63'b000000000000000000000000000000000000000001000000000000000000000: n4418_o = 1'b0; + 63'b000000000000000000000000000000000000000000100000000000000000000: n4418_o = 1'b0; + 63'b000000000000000000000000000000000000000000010000000000000000000: n4418_o = 1'b0; + 63'b000000000000000000000000000000000000000000001000000000000000000: n4418_o = 1'b0; + 63'b000000000000000000000000000000000000000000000100000000000000000: n4418_o = 1'b0; + 63'b000000000000000000000000000000000000000000000010000000000000000: n4418_o = 1'b0; + 63'b000000000000000000000000000000000000000000000001000000000000000: n4418_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000100000000000000: n4418_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000010000000000000: n4418_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000001000000000000: n4418_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000100000000000: n4418_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000010000000000: n4418_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000001000000000: n4418_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000100000000: n4418_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000010000000: n4418_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000001000000: n4418_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000100000: n4418_o = n2579_o; + 63'b000000000000000000000000000000000000000000000000000000000010000: n4418_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000001000: n4418_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000000100: n4418_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000000010: n4418_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000000001: n4418_o = 1'b0; + default: n4418_o = 1'b0; + endcase + /* decoder.vhd:635:5 */ + always @* + case (n4277_o) + 63'b100000000000000000000000000000000000000000000000000000000000000: n4421_o = 1'b0; + 63'b010000000000000000000000000000000000000000000000000000000000000: n4421_o = 1'b0; + 63'b001000000000000000000000000000000000000000000000000000000000000: n4421_o = 1'b0; + 63'b000100000000000000000000000000000000000000000000000000000000000: n4421_o = 1'b0; + 63'b000010000000000000000000000000000000000000000000000000000000000: n4421_o = 1'b0; + 63'b000001000000000000000000000000000000000000000000000000000000000: n4421_o = 1'b0; + 63'b000000100000000000000000000000000000000000000000000000000000000: n4421_o = 1'b0; + 63'b000000010000000000000000000000000000000000000000000000000000000: n4421_o = 1'b0; + 63'b000000001000000000000000000000000000000000000000000000000000000: n4421_o = 1'b0; + 63'b000000000100000000000000000000000000000000000000000000000000000: n4421_o = 1'b0; + 63'b000000000010000000000000000000000000000000000000000000000000000: n4421_o = n4020_o; + 63'b000000000001000000000000000000000000000000000000000000000000000: n4421_o = 1'b0; + 63'b000000000000100000000000000000000000000000000000000000000000000: n4421_o = 1'b0; + 63'b000000000000010000000000000000000000000000000000000000000000000: n4421_o = 1'b0; + 63'b000000000000001000000000000000000000000000000000000000000000000: n4421_o = 1'b0; + 63'b000000000000000100000000000000000000000000000000000000000000000: n4421_o = 1'b0; + 63'b000000000000000010000000000000000000000000000000000000000000000: n4421_o = 1'b0; + 63'b000000000000000001000000000000000000000000000000000000000000000: n4421_o = 1'b0; + 63'b000000000000000000100000000000000000000000000000000000000000000: n4421_o = 1'b0; + 63'b000000000000000000010000000000000000000000000000000000000000000: n4421_o = 1'b0; + 63'b000000000000000000001000000000000000000000000000000000000000000: n4421_o = 1'b0; + 63'b000000000000000000000100000000000000000000000000000000000000000: n4421_o = 1'b0; + 63'b000000000000000000000010000000000000000000000000000000000000000: n4421_o = 1'b0; + 63'b000000000000000000000001000000000000000000000000000000000000000: n4421_o = 1'b0; + 63'b000000000000000000000000100000000000000000000000000000000000000: n4421_o = 1'b0; + 63'b000000000000000000000000010000000000000000000000000000000000000: n4421_o = 1'b0; + 63'b000000000000000000000000001000000000000000000000000000000000000: n4421_o = 1'b0; + 63'b000000000000000000000000000100000000000000000000000000000000000: n4421_o = 1'b0; + 63'b000000000000000000000000000010000000000000000000000000000000000: n4421_o = 1'b0; + 63'b000000000000000000000000000001000000000000000000000000000000000: n4421_o = 1'b0; + 63'b000000000000000000000000000000100000000000000000000000000000000: n4421_o = 1'b0; + 63'b000000000000000000000000000000010000000000000000000000000000000: n4421_o = 1'b0; + 63'b000000000000000000000000000000001000000000000000000000000000000: n4421_o = 1'b0; + 63'b000000000000000000000000000000000100000000000000000000000000000: n4421_o = 1'b0; + 63'b000000000000000000000000000000000010000000000000000000000000000: n4421_o = 1'b0; + 63'b000000000000000000000000000000000001000000000000000000000000000: n4421_o = 1'b0; + 63'b000000000000000000000000000000000000100000000000000000000000000: n4421_o = 1'b0; + 63'b000000000000000000000000000000000000010000000000000000000000000: n4421_o = 1'b0; + 63'b000000000000000000000000000000000000001000000000000000000000000: n4421_o = 1'b0; + 63'b000000000000000000000000000000000000000100000000000000000000000: n4421_o = 1'b0; + 63'b000000000000000000000000000000000000000010000000000000000000000: n4421_o = 1'b0; + 63'b000000000000000000000000000000000000000001000000000000000000000: n4421_o = 1'b0; + 63'b000000000000000000000000000000000000000000100000000000000000000: n4421_o = 1'b0; + 63'b000000000000000000000000000000000000000000010000000000000000000: n4421_o = 1'b0; + 63'b000000000000000000000000000000000000000000001000000000000000000: n4421_o = 1'b0; + 63'b000000000000000000000000000000000000000000000100000000000000000: n4421_o = 1'b0; + 63'b000000000000000000000000000000000000000000000010000000000000000: n4421_o = 1'b0; + 63'b000000000000000000000000000000000000000000000001000000000000000: n4421_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000100000000000000: n4421_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000010000000000000: n4421_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000001000000000000: n4421_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000100000000000: n4421_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000010000000000: n4421_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000001000000000: n4421_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000100000000: n4421_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000010000000: n4421_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000001000000: n4421_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000100000: n4421_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000010000: n4421_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000001000: n4421_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000000100: n4421_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000000010: n4421_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000000001: n4421_o = 1'b0; + default: n4421_o = 1'b0; + endcase + /* decoder.vhd:635:5 */ + always @* + case (n4277_o) + 63'b100000000000000000000000000000000000000000000000000000000000000: n4424_o = 1'b0; + 63'b010000000000000000000000000000000000000000000000000000000000000: n4424_o = 1'b0; + 63'b001000000000000000000000000000000000000000000000000000000000000: n4424_o = 1'b0; + 63'b000100000000000000000000000000000000000000000000000000000000000: n4424_o = 1'b0; + 63'b000010000000000000000000000000000000000000000000000000000000000: n4424_o = 1'b0; + 63'b000001000000000000000000000000000000000000000000000000000000000: n4424_o = 1'b0; + 63'b000000100000000000000000000000000000000000000000000000000000000: n4424_o = 1'b0; + 63'b000000010000000000000000000000000000000000000000000000000000000: n4424_o = 1'b0; + 63'b000000001000000000000000000000000000000000000000000000000000000: n4424_o = n4081_o; + 63'b000000000100000000000000000000000000000000000000000000000000000: n4424_o = n4052_o; + 63'b000000000010000000000000000000000000000000000000000000000000000: n4424_o = 1'b0; + 63'b000000000001000000000000000000000000000000000000000000000000000: n4424_o = 1'b0; + 63'b000000000000100000000000000000000000000000000000000000000000000: n4424_o = 1'b0; + 63'b000000000000010000000000000000000000000000000000000000000000000: n4424_o = 1'b0; + 63'b000000000000001000000000000000000000000000000000000000000000000: n4424_o = 1'b0; + 63'b000000000000000100000000000000000000000000000000000000000000000: n4424_o = 1'b0; + 63'b000000000000000010000000000000000000000000000000000000000000000: n4424_o = 1'b0; + 63'b000000000000000001000000000000000000000000000000000000000000000: n4424_o = 1'b0; + 63'b000000000000000000100000000000000000000000000000000000000000000: n4424_o = 1'b0; + 63'b000000000000000000010000000000000000000000000000000000000000000: n4424_o = 1'b0; + 63'b000000000000000000001000000000000000000000000000000000000000000: n4424_o = 1'b0; + 63'b000000000000000000000100000000000000000000000000000000000000000: n4424_o = 1'b0; + 63'b000000000000000000000010000000000000000000000000000000000000000: n4424_o = 1'b0; + 63'b000000000000000000000001000000000000000000000000000000000000000: n4424_o = 1'b0; + 63'b000000000000000000000000100000000000000000000000000000000000000: n4424_o = 1'b0; + 63'b000000000000000000000000010000000000000000000000000000000000000: n4424_o = 1'b0; + 63'b000000000000000000000000001000000000000000000000000000000000000: n4424_o = 1'b0; + 63'b000000000000000000000000000100000000000000000000000000000000000: n4424_o = 1'b0; + 63'b000000000000000000000000000010000000000000000000000000000000000: n4424_o = 1'b0; + 63'b000000000000000000000000000001000000000000000000000000000000000: n4424_o = 1'b0; + 63'b000000000000000000000000000000100000000000000000000000000000000: n4424_o = 1'b0; + 63'b000000000000000000000000000000010000000000000000000000000000000: n4424_o = 1'b0; + 63'b000000000000000000000000000000001000000000000000000000000000000: n4424_o = 1'b0; + 63'b000000000000000000000000000000000100000000000000000000000000000: n4424_o = 1'b0; + 63'b000000000000000000000000000000000010000000000000000000000000000: n4424_o = 1'b0; + 63'b000000000000000000000000000000000001000000000000000000000000000: n4424_o = 1'b0; + 63'b000000000000000000000000000000000000100000000000000000000000000: n4424_o = 1'b0; + 63'b000000000000000000000000000000000000010000000000000000000000000: n4424_o = 1'b0; + 63'b000000000000000000000000000000000000001000000000000000000000000: n4424_o = 1'b0; + 63'b000000000000000000000000000000000000000100000000000000000000000: n4424_o = 1'b0; + 63'b000000000000000000000000000000000000000010000000000000000000000: n4424_o = 1'b0; + 63'b000000000000000000000000000000000000000001000000000000000000000: n4424_o = 1'b0; + 63'b000000000000000000000000000000000000000000100000000000000000000: n4424_o = 1'b0; + 63'b000000000000000000000000000000000000000000010000000000000000000: n4424_o = 1'b0; + 63'b000000000000000000000000000000000000000000001000000000000000000: n4424_o = 1'b0; + 63'b000000000000000000000000000000000000000000000100000000000000000: n4424_o = 1'b0; + 63'b000000000000000000000000000000000000000000000010000000000000000: n4424_o = 1'b0; + 63'b000000000000000000000000000000000000000000000001000000000000000: n4424_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000100000000000000: n4424_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000010000000000000: n4424_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000001000000000000: n4424_o = n2715_o; + 63'b000000000000000000000000000000000000000000000000000100000000000: n4424_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000010000000000: n4424_o = n2648_o; + 63'b000000000000000000000000000000000000000000000000000001000000000: n4424_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000100000000: n4424_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000010000000: n4424_o = n2609_o; + 63'b000000000000000000000000000000000000000000000000000000001000000: n4424_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000100000: n4424_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000010000: n4424_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000001000: n4424_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000000100: n4424_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000000010: n4424_o = n2277_o; + 63'b000000000000000000000000000000000000000000000000000000000000001: n4424_o = n2224_o; + default: n4424_o = 1'b0; + endcase + /* decoder.vhd:635:5 */ + always @* + case (n4277_o) + 63'b100000000000000000000000000000000000000000000000000000000000000: n4427_o = 1'b0; + 63'b010000000000000000000000000000000000000000000000000000000000000: n4427_o = 1'b0; + 63'b001000000000000000000000000000000000000000000000000000000000000: n4427_o = 1'b0; + 63'b000100000000000000000000000000000000000000000000000000000000000: n4427_o = 1'b0; + 63'b000010000000000000000000000000000000000000000000000000000000000: n4427_o = 1'b0; + 63'b000001000000000000000000000000000000000000000000000000000000000: n4427_o = 1'b0; + 63'b000000100000000000000000000000000000000000000000000000000000000: n4427_o = 1'b0; + 63'b000000010000000000000000000000000000000000000000000000000000000: n4427_o = 1'b0; + 63'b000000001000000000000000000000000000000000000000000000000000000: n4427_o = 1'b0; + 63'b000000000100000000000000000000000000000000000000000000000000000: n4427_o = 1'b0; + 63'b000000000010000000000000000000000000000000000000000000000000000: n4427_o = 1'b0; + 63'b000000000001000000000000000000000000000000000000000000000000000: n4427_o = 1'b0; + 63'b000000000000100000000000000000000000000000000000000000000000000: n4427_o = 1'b0; + 63'b000000000000010000000000000000000000000000000000000000000000000: n4427_o = 1'b0; + 63'b000000000000001000000000000000000000000000000000000000000000000: n4427_o = 1'b0; + 63'b000000000000000100000000000000000000000000000000000000000000000: n4427_o = 1'b0; + 63'b000000000000000010000000000000000000000000000000000000000000000: n4427_o = 1'b0; + 63'b000000000000000001000000000000000000000000000000000000000000000: n4427_o = 1'b0; + 63'b000000000000000000100000000000000000000000000000000000000000000: n4427_o = 1'b0; + 63'b000000000000000000010000000000000000000000000000000000000000000: n4427_o = 1'b0; + 63'b000000000000000000001000000000000000000000000000000000000000000: n4427_o = 1'b0; + 63'b000000000000000000000100000000000000000000000000000000000000000: n4427_o = 1'b0; + 63'b000000000000000000000010000000000000000000000000000000000000000: n4427_o = 1'b0; + 63'b000000000000000000000001000000000000000000000000000000000000000: n4427_o = 1'b0; + 63'b000000000000000000000000100000000000000000000000000000000000000: n4427_o = 1'b0; + 63'b000000000000000000000000010000000000000000000000000000000000000: n4427_o = 1'b0; + 63'b000000000000000000000000001000000000000000000000000000000000000: n4427_o = 1'b0; + 63'b000000000000000000000000000100000000000000000000000000000000000: n4427_o = 1'b0; + 63'b000000000000000000000000000010000000000000000000000000000000000: n4427_o = 1'b0; + 63'b000000000000000000000000000001000000000000000000000000000000000: n4427_o = 1'b0; + 63'b000000000000000000000000000000100000000000000000000000000000000: n4427_o = 1'b0; + 63'b000000000000000000000000000000010000000000000000000000000000000: n4427_o = 1'b0; + 63'b000000000000000000000000000000001000000000000000000000000000000: n4427_o = 1'b0; + 63'b000000000000000000000000000000000100000000000000000000000000000: n4427_o = 1'b0; + 63'b000000000000000000000000000000000010000000000000000000000000000: n4427_o = 1'b0; + 63'b000000000000000000000000000000000001000000000000000000000000000: n4427_o = 1'b0; + 63'b000000000000000000000000000000000000100000000000000000000000000: n4427_o = 1'b0; + 63'b000000000000000000000000000000000000010000000000000000000000000: n4427_o = 1'b0; + 63'b000000000000000000000000000000000000001000000000000000000000000: n4427_o = 1'b0; + 63'b000000000000000000000000000000000000000100000000000000000000000: n4427_o = 1'b0; + 63'b000000000000000000000000000000000000000010000000000000000000000: n4427_o = 1'b0; + 63'b000000000000000000000000000000000000000001000000000000000000000: n4427_o = 1'b0; + 63'b000000000000000000000000000000000000000000100000000000000000000: n4427_o = 1'b0; + 63'b000000000000000000000000000000000000000000010000000000000000000: n4427_o = 1'b0; + 63'b000000000000000000000000000000000000000000001000000000000000000: n4427_o = 1'b0; + 63'b000000000000000000000000000000000000000000000100000000000000000: n4427_o = 1'b0; + 63'b000000000000000000000000000000000000000000000010000000000000000: n4427_o = 1'b0; + 63'b000000000000000000000000000000000000000000000001000000000000000: n4427_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000100000000000000: n4427_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000010000000000000: n4427_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000001000000000000: n4427_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000100000000000: n4427_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000010000000000: n4427_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000001000000000: n4427_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000100000000: n4427_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000010000000: n4427_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000001000000: n4427_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000100000: n4427_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000010000: n4427_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000001000: n4427_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000000100: n4427_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000000010: n4427_o = n2279_o; + 63'b000000000000000000000000000000000000000000000000000000000000001: n4427_o = n2227_o; + default: n4427_o = 1'b0; + endcase + /* decoder.vhd:635:5 */ + always @* + case (n4277_o) + 63'b100000000000000000000000000000000000000000000000000000000000000: n4430_o = 1'b0; + 63'b010000000000000000000000000000000000000000000000000000000000000: n4430_o = 1'b0; + 63'b001000000000000000000000000000000000000000000000000000000000000: n4430_o = 1'b0; + 63'b000100000000000000000000000000000000000000000000000000000000000: n4430_o = 1'b0; + 63'b000010000000000000000000000000000000000000000000000000000000000: n4430_o = 1'b0; + 63'b000001000000000000000000000000000000000000000000000000000000000: n4430_o = 1'b0; + 63'b000000100000000000000000000000000000000000000000000000000000000: n4430_o = 1'b0; + 63'b000000010000000000000000000000000000000000000000000000000000000: n4430_o = 1'b0; + 63'b000000001000000000000000000000000000000000000000000000000000000: n4430_o = 1'b0; + 63'b000000000100000000000000000000000000000000000000000000000000000: n4430_o = 1'b0; + 63'b000000000010000000000000000000000000000000000000000000000000000: n4430_o = 1'b0; + 63'b000000000001000000000000000000000000000000000000000000000000000: n4430_o = 1'b0; + 63'b000000000000100000000000000000000000000000000000000000000000000: n4430_o = 1'b0; + 63'b000000000000010000000000000000000000000000000000000000000000000: n4430_o = 1'b0; + 63'b000000000000001000000000000000000000000000000000000000000000000: n4430_o = 1'b0; + 63'b000000000000000100000000000000000000000000000000000000000000000: n4430_o = 1'b0; + 63'b000000000000000010000000000000000000000000000000000000000000000: n4430_o = 1'b0; + 63'b000000000000000001000000000000000000000000000000000000000000000: n4430_o = 1'b0; + 63'b000000000000000000100000000000000000000000000000000000000000000: n4430_o = 1'b0; + 63'b000000000000000000010000000000000000000000000000000000000000000: n4430_o = 1'b0; + 63'b000000000000000000001000000000000000000000000000000000000000000: n4430_o = 1'b0; + 63'b000000000000000000000100000000000000000000000000000000000000000: n4430_o = 1'b0; + 63'b000000000000000000000010000000000000000000000000000000000000000: n4430_o = 1'b0; + 63'b000000000000000000000001000000000000000000000000000000000000000: n4430_o = 1'b0; + 63'b000000000000000000000000100000000000000000000000000000000000000: n4430_o = 1'b0; + 63'b000000000000000000000000010000000000000000000000000000000000000: n4430_o = 1'b0; + 63'b000000000000000000000000001000000000000000000000000000000000000: n4430_o = 1'b0; + 63'b000000000000000000000000000100000000000000000000000000000000000: n4430_o = 1'b0; + 63'b000000000000000000000000000010000000000000000000000000000000000: n4430_o = 1'b0; + 63'b000000000000000000000000000001000000000000000000000000000000000: n4430_o = 1'b0; + 63'b000000000000000000000000000000100000000000000000000000000000000: n4430_o = 1'b0; + 63'b000000000000000000000000000000010000000000000000000000000000000: n4430_o = 1'b0; + 63'b000000000000000000000000000000001000000000000000000000000000000: n4430_o = 1'b0; + 63'b000000000000000000000000000000000100000000000000000000000000000: n4430_o = 1'b0; + 63'b000000000000000000000000000000000010000000000000000000000000000: n4430_o = 1'b0; + 63'b000000000000000000000000000000000001000000000000000000000000000: n4430_o = 1'b0; + 63'b000000000000000000000000000000000000100000000000000000000000000: n4430_o = 1'b0; + 63'b000000000000000000000000000000000000010000000000000000000000000: n4430_o = 1'b0; + 63'b000000000000000000000000000000000000001000000000000000000000000: n4430_o = 1'b0; + 63'b000000000000000000000000000000000000000100000000000000000000000: n4430_o = 1'b0; + 63'b000000000000000000000000000000000000000010000000000000000000000: n4430_o = 1'b0; + 63'b000000000000000000000000000000000000000001000000000000000000000: n4430_o = 1'b0; + 63'b000000000000000000000000000000000000000000100000000000000000000: n4430_o = 1'b0; + 63'b000000000000000000000000000000000000000000010000000000000000000: n4430_o = 1'b0; + 63'b000000000000000000000000000000000000000000001000000000000000000: n4430_o = 1'b0; + 63'b000000000000000000000000000000000000000000000100000000000000000: n4430_o = 1'b0; + 63'b000000000000000000000000000000000000000000000010000000000000000: n4430_o = 1'b0; + 63'b000000000000000000000000000000000000000000000001000000000000000: n4430_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000100000000000000: n4430_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000010000000000000: n4430_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000001000000000000: n4430_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000100000000000: n4430_o = n2667_o; + 63'b000000000000000000000000000000000000000000000000000010000000000: n4430_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000001000000000: n4430_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000100000000: n4430_o = n2623_o; + 63'b000000000000000000000000000000000000000000000000000000010000000: n4430_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000001000000: n4430_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000100000: n4430_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000010000: n4430_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000001000: n4430_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000000100: n4430_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000000010: n4430_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000000001: n4430_o = 1'b0; + default: n4430_o = 1'b0; + endcase + /* decoder.vhd:635:5 */ + always @* + case (n4277_o) + 63'b100000000000000000000000000000000000000000000000000000000000000: n4433_o = 1'b0; + 63'b010000000000000000000000000000000000000000000000000000000000000: n4433_o = 1'b0; + 63'b001000000000000000000000000000000000000000000000000000000000000: n4433_o = 1'b0; + 63'b000100000000000000000000000000000000000000000000000000000000000: n4433_o = 1'b0; + 63'b000010000000000000000000000000000000000000000000000000000000000: n4433_o = 1'b0; + 63'b000001000000000000000000000000000000000000000000000000000000000: n4433_o = 1'b0; + 63'b000000100000000000000000000000000000000000000000000000000000000: n4433_o = n4106_o; + 63'b000000010000000000000000000000000000000000000000000000000000000: n4433_o = 1'b0; + 63'b000000001000000000000000000000000000000000000000000000000000000: n4433_o = 1'b0; + 63'b000000000100000000000000000000000000000000000000000000000000000: n4433_o = 1'b0; + 63'b000000000010000000000000000000000000000000000000000000000000000: n4433_o = 1'b0; + 63'b000000000001000000000000000000000000000000000000000000000000000: n4433_o = 1'b0; + 63'b000000000000100000000000000000000000000000000000000000000000000: n4433_o = 1'b0; + 63'b000000000000010000000000000000000000000000000000000000000000000: n4433_o = 1'b0; + 63'b000000000000001000000000000000000000000000000000000000000000000: n4433_o = 1'b0; + 63'b000000000000000100000000000000000000000000000000000000000000000: n4433_o = 1'b0; + 63'b000000000000000010000000000000000000000000000000000000000000000: n4433_o = 1'b0; + 63'b000000000000000001000000000000000000000000000000000000000000000: n4433_o = 1'b0; + 63'b000000000000000000100000000000000000000000000000000000000000000: n4433_o = 1'b0; + 63'b000000000000000000010000000000000000000000000000000000000000000: n4433_o = 1'b0; + 63'b000000000000000000001000000000000000000000000000000000000000000: n4433_o = 1'b0; + 63'b000000000000000000000100000000000000000000000000000000000000000: n4433_o = 1'b0; + 63'b000000000000000000000010000000000000000000000000000000000000000: n4433_o = 1'b0; + 63'b000000000000000000000001000000000000000000000000000000000000000: n4433_o = 1'b0; + 63'b000000000000000000000000100000000000000000000000000000000000000: n4433_o = 1'b0; + 63'b000000000000000000000000010000000000000000000000000000000000000: n4433_o = 1'b0; + 63'b000000000000000000000000001000000000000000000000000000000000000: n4433_o = 1'b0; + 63'b000000000000000000000000000100000000000000000000000000000000000: n4433_o = 1'b0; + 63'b000000000000000000000000000010000000000000000000000000000000000: n4433_o = 1'b0; + 63'b000000000000000000000000000001000000000000000000000000000000000: n4433_o = 1'b0; + 63'b000000000000000000000000000000100000000000000000000000000000000: n4433_o = 1'b0; + 63'b000000000000000000000000000000010000000000000000000000000000000: n4433_o = 1'b0; + 63'b000000000000000000000000000000001000000000000000000000000000000: n4433_o = 1'b0; + 63'b000000000000000000000000000000000100000000000000000000000000000: n4433_o = 1'b0; + 63'b000000000000000000000000000000000010000000000000000000000000000: n4433_o = 1'b0; + 63'b000000000000000000000000000000000001000000000000000000000000000: n4433_o = 1'b0; + 63'b000000000000000000000000000000000000100000000000000000000000000: n4433_o = 1'b0; + 63'b000000000000000000000000000000000000010000000000000000000000000: n4433_o = 1'b0; + 63'b000000000000000000000000000000000000001000000000000000000000000: n4433_o = 1'b0; + 63'b000000000000000000000000000000000000000100000000000000000000000: n4433_o = 1'b0; + 63'b000000000000000000000000000000000000000010000000000000000000000: n4433_o = 1'b0; + 63'b000000000000000000000000000000000000000001000000000000000000000: n4433_o = 1'b0; + 63'b000000000000000000000000000000000000000000100000000000000000000: n4433_o = 1'b0; + 63'b000000000000000000000000000000000000000000010000000000000000000: n4433_o = 1'b0; + 63'b000000000000000000000000000000000000000000001000000000000000000: n4433_o = 1'b0; + 63'b000000000000000000000000000000000000000000000100000000000000000: n4433_o = 1'b0; + 63'b000000000000000000000000000000000000000000000010000000000000000: n4433_o = 1'b0; + 63'b000000000000000000000000000000000000000000000001000000000000000: n4433_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000100000000000000: n4433_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000010000000000000: n4433_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000001000000000000: n4433_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000100000000000: n4433_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000010000000000: n4433_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000001000000000: n4433_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000100000000: n4433_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000010000000: n4433_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000001000000: n4433_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000100000: n4433_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000010000: n4433_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000001000: n4433_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000000100: n4433_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000000010: n4433_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000000001: n4433_o = 1'b0; + default: n4433_o = 1'b0; + endcase + /* decoder.vhd:635:5 */ + always @* + case (n4277_o) + 63'b100000000000000000000000000000000000000000000000000000000000000: n4436_o = 1'b0; + 63'b010000000000000000000000000000000000000000000000000000000000000: n4436_o = 1'b0; + 63'b001000000000000000000000000000000000000000000000000000000000000: n4436_o = 1'b0; + 63'b000100000000000000000000000000000000000000000000000000000000000: n4436_o = 1'b0; + 63'b000010000000000000000000000000000000000000000000000000000000000: n4436_o = 1'b0; + 63'b000001000000000000000000000000000000000000000000000000000000000: n4436_o = 1'b0; + 63'b000000100000000000000000000000000000000000000000000000000000000: n4436_o = 1'b0; + 63'b000000010000000000000000000000000000000000000000000000000000000: n4436_o = 1'b0; + 63'b000000001000000000000000000000000000000000000000000000000000000: n4436_o = 1'b0; + 63'b000000000100000000000000000000000000000000000000000000000000000: n4436_o = 1'b0; + 63'b000000000010000000000000000000000000000000000000000000000000000: n4436_o = 1'b0; + 63'b000000000001000000000000000000000000000000000000000000000000000: n4436_o = 1'b0; + 63'b000000000000100000000000000000000000000000000000000000000000000: n4436_o = 1'b0; + 63'b000000000000010000000000000000000000000000000000000000000000000: n4436_o = 1'b0; + 63'b000000000000001000000000000000000000000000000000000000000000000: n4436_o = 1'b0; + 63'b000000000000000100000000000000000000000000000000000000000000000: n4436_o = 1'b0; + 63'b000000000000000010000000000000000000000000000000000000000000000: n4436_o = 1'b0; + 63'b000000000000000001000000000000000000000000000000000000000000000: n4436_o = 1'b0; + 63'b000000000000000000100000000000000000000000000000000000000000000: n4436_o = 1'b0; + 63'b000000000000000000010000000000000000000000000000000000000000000: n4436_o = 1'b0; + 63'b000000000000000000001000000000000000000000000000000000000000000: n4436_o = 1'b0; + 63'b000000000000000000000100000000000000000000000000000000000000000: n4436_o = n3480_o; + 63'b000000000000000000000010000000000000000000000000000000000000000: n4436_o = 1'b0; + 63'b000000000000000000000001000000000000000000000000000000000000000: n4436_o = 1'b0; + 63'b000000000000000000000000100000000000000000000000000000000000000: n4436_o = 1'b0; + 63'b000000000000000000000000010000000000000000000000000000000000000: n4436_o = 1'b0; + 63'b000000000000000000000000001000000000000000000000000000000000000: n4436_o = 1'b0; + 63'b000000000000000000000000000100000000000000000000000000000000000: n4436_o = 1'b0; + 63'b000000000000000000000000000010000000000000000000000000000000000: n4436_o = 1'b0; + 63'b000000000000000000000000000001000000000000000000000000000000000: n4436_o = 1'b0; + 63'b000000000000000000000000000000100000000000000000000000000000000: n4436_o = 1'b0; + 63'b000000000000000000000000000000010000000000000000000000000000000: n4436_o = 1'b0; + 63'b000000000000000000000000000000001000000000000000000000000000000: n4436_o = 1'b0; + 63'b000000000000000000000000000000000100000000000000000000000000000: n4436_o = 1'b0; + 63'b000000000000000000000000000000000010000000000000000000000000000: n4436_o = 1'b0; + 63'b000000000000000000000000000000000001000000000000000000000000000: n4436_o = 1'b0; + 63'b000000000000000000000000000000000000100000000000000000000000000: n4436_o = 1'b0; + 63'b000000000000000000000000000000000000010000000000000000000000000: n4436_o = 1'b0; + 63'b000000000000000000000000000000000000001000000000000000000000000: n4436_o = 1'b0; + 63'b000000000000000000000000000000000000000100000000000000000000000: n4436_o = 1'b0; + 63'b000000000000000000000000000000000000000010000000000000000000000: n4436_o = 1'b0; + 63'b000000000000000000000000000000000000000001000000000000000000000: n4436_o = 1'b0; + 63'b000000000000000000000000000000000000000000100000000000000000000: n4436_o = 1'b0; + 63'b000000000000000000000000000000000000000000010000000000000000000: n4436_o = 1'b0; + 63'b000000000000000000000000000000000000000000001000000000000000000: n4436_o = 1'b0; + 63'b000000000000000000000000000000000000000000000100000000000000000: n4436_o = 1'b0; + 63'b000000000000000000000000000000000000000000000010000000000000000: n4436_o = 1'b0; + 63'b000000000000000000000000000000000000000000000001000000000000000: n4436_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000100000000000000: n4436_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000010000000000000: n4436_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000001000000000000: n4436_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000100000000000: n4436_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000010000000000: n4436_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000001000000000: n4436_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000100000000: n4436_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000010000000: n4436_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000001000000: n4436_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000100000: n4436_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000010000: n4436_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000001000: n4436_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000000100: n4436_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000000010: n4436_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000000001: n4436_o = 1'b0; + default: n4436_o = 1'b0; + endcase + /* decoder.vhd:635:5 */ + always @* + case (n4277_o) + 63'b100000000000000000000000000000000000000000000000000000000000000: n4439_o = 1'b0; + 63'b010000000000000000000000000000000000000000000000000000000000000: n4439_o = 1'b0; + 63'b001000000000000000000000000000000000000000000000000000000000000: n4439_o = 1'b0; + 63'b000100000000000000000000000000000000000000000000000000000000000: n4439_o = 1'b0; + 63'b000010000000000000000000000000000000000000000000000000000000000: n4439_o = 1'b0; + 63'b000001000000000000000000000000000000000000000000000000000000000: n4439_o = 1'b0; + 63'b000000100000000000000000000000000000000000000000000000000000000: n4439_o = 1'b0; + 63'b000000010000000000000000000000000000000000000000000000000000000: n4439_o = 1'b0; + 63'b000000001000000000000000000000000000000000000000000000000000000: n4439_o = 1'b0; + 63'b000000000100000000000000000000000000000000000000000000000000000: n4439_o = 1'b0; + 63'b000000000010000000000000000000000000000000000000000000000000000: n4439_o = 1'b0; + 63'b000000000001000000000000000000000000000000000000000000000000000: n4439_o = 1'b0; + 63'b000000000000100000000000000000000000000000000000000000000000000: n4439_o = 1'b0; + 63'b000000000000010000000000000000000000000000000000000000000000000: n4439_o = 1'b0; + 63'b000000000000001000000000000000000000000000000000000000000000000: n4439_o = 1'b0; + 63'b000000000000000100000000000000000000000000000000000000000000000: n4439_o = 1'b0; + 63'b000000000000000010000000000000000000000000000000000000000000000: n4439_o = 1'b0; + 63'b000000000000000001000000000000000000000000000000000000000000000: n4439_o = 1'b0; + 63'b000000000000000000100000000000000000000000000000000000000000000: n4439_o = 1'b0; + 63'b000000000000000000010000000000000000000000000000000000000000000: n4439_o = 1'b0; + 63'b000000000000000000001000000000000000000000000000000000000000000: n4439_o = 1'b0; + 63'b000000000000000000000100000000000000000000000000000000000000000: n4439_o = n3482_o; + 63'b000000000000000000000010000000000000000000000000000000000000000: n4439_o = 1'b0; + 63'b000000000000000000000001000000000000000000000000000000000000000: n4439_o = 1'b0; + 63'b000000000000000000000000100000000000000000000000000000000000000: n4439_o = 1'b0; + 63'b000000000000000000000000010000000000000000000000000000000000000: n4439_o = 1'b0; + 63'b000000000000000000000000001000000000000000000000000000000000000: n4439_o = 1'b0; + 63'b000000000000000000000000000100000000000000000000000000000000000: n4439_o = 1'b0; + 63'b000000000000000000000000000010000000000000000000000000000000000: n4439_o = 1'b0; + 63'b000000000000000000000000000001000000000000000000000000000000000: n4439_o = 1'b0; + 63'b000000000000000000000000000000100000000000000000000000000000000: n4439_o = 1'b0; + 63'b000000000000000000000000000000010000000000000000000000000000000: n4439_o = 1'b0; + 63'b000000000000000000000000000000001000000000000000000000000000000: n4439_o = 1'b0; + 63'b000000000000000000000000000000000100000000000000000000000000000: n4439_o = 1'b0; + 63'b000000000000000000000000000000000010000000000000000000000000000: n4439_o = 1'b0; + 63'b000000000000000000000000000000000001000000000000000000000000000: n4439_o = 1'b0; + 63'b000000000000000000000000000000000000100000000000000000000000000: n4439_o = 1'b0; + 63'b000000000000000000000000000000000000010000000000000000000000000: n4439_o = 1'b0; + 63'b000000000000000000000000000000000000001000000000000000000000000: n4439_o = 1'b0; + 63'b000000000000000000000000000000000000000100000000000000000000000: n4439_o = 1'b0; + 63'b000000000000000000000000000000000000000010000000000000000000000: n4439_o = 1'b0; + 63'b000000000000000000000000000000000000000001000000000000000000000: n4439_o = 1'b0; + 63'b000000000000000000000000000000000000000000100000000000000000000: n4439_o = 1'b0; + 63'b000000000000000000000000000000000000000000010000000000000000000: n4439_o = 1'b0; + 63'b000000000000000000000000000000000000000000001000000000000000000: n4439_o = 1'b0; + 63'b000000000000000000000000000000000000000000000100000000000000000: n4439_o = 1'b0; + 63'b000000000000000000000000000000000000000000000010000000000000000: n4439_o = 1'b0; + 63'b000000000000000000000000000000000000000000000001000000000000000: n4439_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000100000000000000: n4439_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000010000000000000: n4439_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000001000000000000: n4439_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000100000000000: n4439_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000010000000000: n4439_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000001000000000: n4439_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000100000000: n4439_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000010000000: n4439_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000001000000: n4439_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000100000: n4439_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000010000: n4439_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000001000: n4439_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000000100: n4439_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000000010: n4439_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000000001: n4439_o = 1'b0; + default: n4439_o = 1'b0; + endcase + /* decoder.vhd:635:5 */ + always @* + case (n4277_o) + 63'b100000000000000000000000000000000000000000000000000000000000000: n4442_o = 1'b0; + 63'b010000000000000000000000000000000000000000000000000000000000000: n4442_o = 1'b0; + 63'b001000000000000000000000000000000000000000000000000000000000000: n4442_o = 1'b0; + 63'b000100000000000000000000000000000000000000000000000000000000000: n4442_o = 1'b0; + 63'b000010000000000000000000000000000000000000000000000000000000000: n4442_o = n4126_o; + 63'b000001000000000000000000000000000000000000000000000000000000000: n4442_o = 1'b0; + 63'b000000100000000000000000000000000000000000000000000000000000000: n4442_o = 1'b0; + 63'b000000010000000000000000000000000000000000000000000000000000000: n4442_o = 1'b0; + 63'b000000001000000000000000000000000000000000000000000000000000000: n4442_o = 1'b0; + 63'b000000000100000000000000000000000000000000000000000000000000000: n4442_o = 1'b0; + 63'b000000000010000000000000000000000000000000000000000000000000000: n4442_o = 1'b0; + 63'b000000000001000000000000000000000000000000000000000000000000000: n4442_o = 1'b0; + 63'b000000000000100000000000000000000000000000000000000000000000000: n4442_o = 1'b0; + 63'b000000000000010000000000000000000000000000000000000000000000000: n4442_o = 1'b0; + 63'b000000000000001000000000000000000000000000000000000000000000000: n4442_o = 1'b0; + 63'b000000000000000100000000000000000000000000000000000000000000000: n4442_o = 1'b0; + 63'b000000000000000010000000000000000000000000000000000000000000000: n4442_o = 1'b0; + 63'b000000000000000001000000000000000000000000000000000000000000000: n4442_o = 1'b0; + 63'b000000000000000000100000000000000000000000000000000000000000000: n4442_o = 1'b0; + 63'b000000000000000000010000000000000000000000000000000000000000000: n4442_o = 1'b0; + 63'b000000000000000000001000000000000000000000000000000000000000000: n4442_o = 1'b0; + 63'b000000000000000000000100000000000000000000000000000000000000000: n4442_o = 1'b0; + 63'b000000000000000000000010000000000000000000000000000000000000000: n4442_o = 1'b0; + 63'b000000000000000000000001000000000000000000000000000000000000000: n4442_o = 1'b0; + 63'b000000000000000000000000100000000000000000000000000000000000000: n4442_o = 1'b0; + 63'b000000000000000000000000010000000000000000000000000000000000000: n4442_o = 1'b0; + 63'b000000000000000000000000001000000000000000000000000000000000000: n4442_o = 1'b0; + 63'b000000000000000000000000000100000000000000000000000000000000000: n4442_o = 1'b0; + 63'b000000000000000000000000000010000000000000000000000000000000000: n4442_o = 1'b0; + 63'b000000000000000000000000000001000000000000000000000000000000000: n4442_o = 1'b0; + 63'b000000000000000000000000000000100000000000000000000000000000000: n4442_o = 1'b0; + 63'b000000000000000000000000000000010000000000000000000000000000000: n4442_o = 1'b0; + 63'b000000000000000000000000000000001000000000000000000000000000000: n4442_o = 1'b0; + 63'b000000000000000000000000000000000100000000000000000000000000000: n4442_o = 1'b0; + 63'b000000000000000000000000000000000010000000000000000000000000000: n4442_o = 1'b0; + 63'b000000000000000000000000000000000001000000000000000000000000000: n4442_o = 1'b0; + 63'b000000000000000000000000000000000000100000000000000000000000000: n4442_o = 1'b0; + 63'b000000000000000000000000000000000000010000000000000000000000000: n4442_o = 1'b0; + 63'b000000000000000000000000000000000000001000000000000000000000000: n4442_o = 1'b0; + 63'b000000000000000000000000000000000000000100000000000000000000000: n4442_o = 1'b0; + 63'b000000000000000000000000000000000000000010000000000000000000000: n4442_o = 1'b0; + 63'b000000000000000000000000000000000000000001000000000000000000000: n4442_o = 1'b0; + 63'b000000000000000000000000000000000000000000100000000000000000000: n4442_o = 1'b0; + 63'b000000000000000000000000000000000000000000010000000000000000000: n4442_o = 1'b0; + 63'b000000000000000000000000000000000000000000001000000000000000000: n4442_o = 1'b0; + 63'b000000000000000000000000000000000000000000000100000000000000000: n4442_o = 1'b0; + 63'b000000000000000000000000000000000000000000000010000000000000000: n4442_o = 1'b0; + 63'b000000000000000000000000000000000000000000000001000000000000000: n4442_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000100000000000000: n4442_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000010000000000000: n4442_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000001000000000000: n4442_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000100000000000: n4442_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000010000000000: n4442_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000001000000000: n4442_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000100000000: n4442_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000010000000: n4442_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000001000000: n4442_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000100000: n4442_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000010000: n4442_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000001000: n4442_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000000100: n4442_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000000010: n4442_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000000001: n4442_o = 1'b0; + default: n4442_o = 1'b0; + endcase + /* decoder.vhd:635:5 */ + always @* + case (n4277_o) + 63'b100000000000000000000000000000000000000000000000000000000000000: n4445_o = 1'b0; + 63'b010000000000000000000000000000000000000000000000000000000000000: n4445_o = 1'b0; + 63'b001000000000000000000000000000000000000000000000000000000000000: n4445_o = 1'b0; + 63'b000100000000000000000000000000000000000000000000000000000000000: n4445_o = 1'b0; + 63'b000010000000000000000000000000000000000000000000000000000000000: n4445_o = n4128_o; + 63'b000001000000000000000000000000000000000000000000000000000000000: n4445_o = 1'b0; + 63'b000000100000000000000000000000000000000000000000000000000000000: n4445_o = 1'b0; + 63'b000000010000000000000000000000000000000000000000000000000000000: n4445_o = 1'b0; + 63'b000000001000000000000000000000000000000000000000000000000000000: n4445_o = 1'b0; + 63'b000000000100000000000000000000000000000000000000000000000000000: n4445_o = 1'b0; + 63'b000000000010000000000000000000000000000000000000000000000000000: n4445_o = 1'b0; + 63'b000000000001000000000000000000000000000000000000000000000000000: n4445_o = 1'b0; + 63'b000000000000100000000000000000000000000000000000000000000000000: n4445_o = 1'b0; + 63'b000000000000010000000000000000000000000000000000000000000000000: n4445_o = 1'b0; + 63'b000000000000001000000000000000000000000000000000000000000000000: n4445_o = 1'b0; + 63'b000000000000000100000000000000000000000000000000000000000000000: n4445_o = 1'b0; + 63'b000000000000000010000000000000000000000000000000000000000000000: n4445_o = 1'b0; + 63'b000000000000000001000000000000000000000000000000000000000000000: n4445_o = 1'b0; + 63'b000000000000000000100000000000000000000000000000000000000000000: n4445_o = 1'b0; + 63'b000000000000000000010000000000000000000000000000000000000000000: n4445_o = 1'b0; + 63'b000000000000000000001000000000000000000000000000000000000000000: n4445_o = 1'b0; + 63'b000000000000000000000100000000000000000000000000000000000000000: n4445_o = 1'b0; + 63'b000000000000000000000010000000000000000000000000000000000000000: n4445_o = 1'b0; + 63'b000000000000000000000001000000000000000000000000000000000000000: n4445_o = 1'b0; + 63'b000000000000000000000000100000000000000000000000000000000000000: n4445_o = 1'b0; + 63'b000000000000000000000000010000000000000000000000000000000000000: n4445_o = 1'b0; + 63'b000000000000000000000000001000000000000000000000000000000000000: n4445_o = 1'b0; + 63'b000000000000000000000000000100000000000000000000000000000000000: n4445_o = 1'b0; + 63'b000000000000000000000000000010000000000000000000000000000000000: n4445_o = 1'b0; + 63'b000000000000000000000000000001000000000000000000000000000000000: n4445_o = 1'b0; + 63'b000000000000000000000000000000100000000000000000000000000000000: n4445_o = 1'b0; + 63'b000000000000000000000000000000010000000000000000000000000000000: n4445_o = 1'b0; + 63'b000000000000000000000000000000001000000000000000000000000000000: n4445_o = 1'b0; + 63'b000000000000000000000000000000000100000000000000000000000000000: n4445_o = 1'b0; + 63'b000000000000000000000000000000000010000000000000000000000000000: n4445_o = 1'b0; + 63'b000000000000000000000000000000000001000000000000000000000000000: n4445_o = 1'b0; + 63'b000000000000000000000000000000000000100000000000000000000000000: n4445_o = 1'b0; + 63'b000000000000000000000000000000000000010000000000000000000000000: n4445_o = 1'b0; + 63'b000000000000000000000000000000000000001000000000000000000000000: n4445_o = 1'b0; + 63'b000000000000000000000000000000000000000100000000000000000000000: n4445_o = 1'b0; + 63'b000000000000000000000000000000000000000010000000000000000000000: n4445_o = 1'b0; + 63'b000000000000000000000000000000000000000001000000000000000000000: n4445_o = 1'b0; + 63'b000000000000000000000000000000000000000000100000000000000000000: n4445_o = 1'b0; + 63'b000000000000000000000000000000000000000000010000000000000000000: n4445_o = 1'b0; + 63'b000000000000000000000000000000000000000000001000000000000000000: n4445_o = 1'b0; + 63'b000000000000000000000000000000000000000000000100000000000000000: n4445_o = 1'b0; + 63'b000000000000000000000000000000000000000000000010000000000000000: n4445_o = 1'b0; + 63'b000000000000000000000000000000000000000000000001000000000000000: n4445_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000100000000000000: n4445_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000010000000000000: n4445_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000001000000000000: n4445_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000100000000000: n4445_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000010000000000: n4445_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000001000000000: n4445_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000100000000: n4445_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000010000000: n4445_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000001000000: n4445_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000100000: n4445_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000010000: n4445_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000001000: n4445_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000000100: n4445_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000000010: n4445_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000000001: n4445_o = 1'b0; + default: n4445_o = 1'b0; + endcase + /* decoder.vhd:635:5 */ + always @* + case (n4277_o) + 63'b100000000000000000000000000000000000000000000000000000000000000: n4448_o = 1'b0; + 63'b010000000000000000000000000000000000000000000000000000000000000: n4448_o = 1'b0; + 63'b001000000000000000000000000000000000000000000000000000000000000: n4448_o = 1'b0; + 63'b000100000000000000000000000000000000000000000000000000000000000: n4448_o = 1'b0; + 63'b000010000000000000000000000000000000000000000000000000000000000: n4448_o = 1'b0; + 63'b000001000000000000000000000000000000000000000000000000000000000: n4448_o = n4113_o; + 63'b000000100000000000000000000000000000000000000000000000000000000: n4448_o = 1'b0; + 63'b000000010000000000000000000000000000000000000000000000000000000: n4448_o = 1'b0; + 63'b000000001000000000000000000000000000000000000000000000000000000: n4448_o = 1'b0; + 63'b000000000100000000000000000000000000000000000000000000000000000: n4448_o = 1'b0; + 63'b000000000010000000000000000000000000000000000000000000000000000: n4448_o = 1'b0; + 63'b000000000001000000000000000000000000000000000000000000000000000: n4448_o = 1'b0; + 63'b000000000000100000000000000000000000000000000000000000000000000: n4448_o = 1'b0; + 63'b000000000000010000000000000000000000000000000000000000000000000: n4448_o = 1'b0; + 63'b000000000000001000000000000000000000000000000000000000000000000: n4448_o = 1'b0; + 63'b000000000000000100000000000000000000000000000000000000000000000: n4448_o = 1'b0; + 63'b000000000000000010000000000000000000000000000000000000000000000: n4448_o = 1'b0; + 63'b000000000000000001000000000000000000000000000000000000000000000: n4448_o = 1'b0; + 63'b000000000000000000100000000000000000000000000000000000000000000: n4448_o = 1'b0; + 63'b000000000000000000010000000000000000000000000000000000000000000: n4448_o = 1'b0; + 63'b000000000000000000001000000000000000000000000000000000000000000: n4448_o = 1'b0; + 63'b000000000000000000000100000000000000000000000000000000000000000: n4448_o = 1'b0; + 63'b000000000000000000000010000000000000000000000000000000000000000: n4448_o = 1'b0; + 63'b000000000000000000000001000000000000000000000000000000000000000: n4448_o = 1'b0; + 63'b000000000000000000000000100000000000000000000000000000000000000: n4448_o = 1'b0; + 63'b000000000000000000000000010000000000000000000000000000000000000: n4448_o = 1'b0; + 63'b000000000000000000000000001000000000000000000000000000000000000: n4448_o = 1'b0; + 63'b000000000000000000000000000100000000000000000000000000000000000: n4448_o = 1'b0; + 63'b000000000000000000000000000010000000000000000000000000000000000: n4448_o = 1'b0; + 63'b000000000000000000000000000001000000000000000000000000000000000: n4448_o = 1'b0; + 63'b000000000000000000000000000000100000000000000000000000000000000: n4448_o = 1'b0; + 63'b000000000000000000000000000000010000000000000000000000000000000: n4448_o = 1'b0; + 63'b000000000000000000000000000000001000000000000000000000000000000: n4448_o = 1'b0; + 63'b000000000000000000000000000000000100000000000000000000000000000: n4448_o = 1'b0; + 63'b000000000000000000000000000000000010000000000000000000000000000: n4448_o = 1'b0; + 63'b000000000000000000000000000000000001000000000000000000000000000: n4448_o = 1'b0; + 63'b000000000000000000000000000000000000100000000000000000000000000: n4448_o = 1'b0; + 63'b000000000000000000000000000000000000010000000000000000000000000: n4448_o = 1'b0; + 63'b000000000000000000000000000000000000001000000000000000000000000: n4448_o = 1'b0; + 63'b000000000000000000000000000000000000000100000000000000000000000: n4448_o = 1'b0; + 63'b000000000000000000000000000000000000000010000000000000000000000: n4448_o = 1'b0; + 63'b000000000000000000000000000000000000000001000000000000000000000: n4448_o = 1'b0; + 63'b000000000000000000000000000000000000000000100000000000000000000: n4448_o = 1'b0; + 63'b000000000000000000000000000000000000000000010000000000000000000: n4448_o = 1'b0; + 63'b000000000000000000000000000000000000000000001000000000000000000: n4448_o = 1'b0; + 63'b000000000000000000000000000000000000000000000100000000000000000: n4448_o = 1'b0; + 63'b000000000000000000000000000000000000000000000010000000000000000: n4448_o = 1'b0; + 63'b000000000000000000000000000000000000000000000001000000000000000: n4448_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000100000000000000: n4448_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000010000000000000: n4448_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000001000000000000: n4448_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000100000000000: n4448_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000010000000000: n4448_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000001000000000: n4448_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000100000000: n4448_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000010000000: n4448_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000001000000: n4448_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000100000: n4448_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000010000: n4448_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000001000: n4448_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000000100: n4448_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000000010: n4448_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000000001: n4448_o = 1'b0; + default: n4448_o = 1'b0; + endcase + /* decoder.vhd:635:5 */ + always @* + case (n4277_o) + 63'b100000000000000000000000000000000000000000000000000000000000000: n4473_o = 1'b1; + 63'b010000000000000000000000000000000000000000000000000000000000000: n4473_o = 1'b0; + 63'b001000000000000000000000000000000000000000000000000000000000000: n4473_o = 1'b0; + 63'b000100000000000000000000000000000000000000000000000000000000000: n4473_o = 1'b0; + 63'b000010000000000000000000000000000000000000000000000000000000000: n4473_o = 1'b0; + 63'b000001000000000000000000000000000000000000000000000000000000000: n4473_o = 1'b0; + 63'b000000100000000000000000000000000000000000000000000000000000000: n4473_o = 1'b0; + 63'b000000010000000000000000000000000000000000000000000000000000000: n4473_o = 1'b0; + 63'b000000001000000000000000000000000000000000000000000000000000000: n4473_o = 1'b0; + 63'b000000000100000000000000000000000000000000000000000000000000000: n4473_o = 1'b0; + 63'b000000000010000000000000000000000000000000000000000000000000000: n4473_o = 1'b0; + 63'b000000000001000000000000000000000000000000000000000000000000000: n4473_o = 1'b0; + 63'b000000000000100000000000000000000000000000000000000000000000000: n4473_o = 1'b0; + 63'b000000000000010000000000000000000000000000000000000000000000000: n4473_o = 1'b1; + 63'b000000000000001000000000000000000000000000000000000000000000000: n4473_o = 1'b1; + 63'b000000000000000100000000000000000000000000000000000000000000000: n4473_o = 1'b0; + 63'b000000000000000010000000000000000000000000000000000000000000000: n4473_o = 1'b0; + 63'b000000000000000001000000000000000000000000000000000000000000000: n4473_o = 1'b0; + 63'b000000000000000000100000000000000000000000000000000000000000000: n4473_o = 1'b1; + 63'b000000000000000000010000000000000000000000000000000000000000000: n4473_o = 1'b0; + 63'b000000000000000000001000000000000000000000000000000000000000000: n4473_o = 1'b0; + 63'b000000000000000000000100000000000000000000000000000000000000000: n4473_o = 1'b0; + 63'b000000000000000000000010000000000000000000000000000000000000000: n4473_o = 1'b0; + 63'b000000000000000000000001000000000000000000000000000000000000000: n4473_o = 1'b1; + 63'b000000000000000000000000100000000000000000000000000000000000000: n4473_o = 1'b0; + 63'b000000000000000000000000010000000000000000000000000000000000000: n4473_o = 1'b0; + 63'b000000000000000000000000001000000000000000000000000000000000000: n4473_o = 1'b0; + 63'b000000000000000000000000000100000000000000000000000000000000000: n4473_o = 1'b0; + 63'b000000000000000000000000000010000000000000000000000000000000000: n4473_o = 1'b1; + 63'b000000000000000000000000000001000000000000000000000000000000000: n4473_o = 1'b1; + 63'b000000000000000000000000000000100000000000000000000000000000000: n4473_o = 1'b1; + 63'b000000000000000000000000000000010000000000000000000000000000000: n4473_o = 1'b1; + 63'b000000000000000000000000000000001000000000000000000000000000000: n4473_o = 1'b1; + 63'b000000000000000000000000000000000100000000000000000000000000000: n4473_o = 1'b1; + 63'b000000000000000000000000000000000010000000000000000000000000000: n4473_o = 1'b1; + 63'b000000000000000000000000000000000001000000000000000000000000000: n4473_o = 1'b1; + 63'b000000000000000000000000000000000000100000000000000000000000000: n4473_o = 1'b1; + 63'b000000000000000000000000000000000000010000000000000000000000000: n4473_o = 1'b1; + 63'b000000000000000000000000000000000000001000000000000000000000000: n4473_o = 1'b1; + 63'b000000000000000000000000000000000000000100000000000000000000000: n4473_o = 1'b1; + 63'b000000000000000000000000000000000000000010000000000000000000000: n4473_o = 1'b0; + 63'b000000000000000000000000000000000000000001000000000000000000000: n4473_o = 1'b0; + 63'b000000000000000000000000000000000000000000100000000000000000000: n4473_o = 1'b0; + 63'b000000000000000000000000000000000000000000010000000000000000000: n4473_o = 1'b0; + 63'b000000000000000000000000000000000000000000001000000000000000000: n4473_o = 1'b0; + 63'b000000000000000000000000000000000000000000000100000000000000000: n4473_o = 1'b0; + 63'b000000000000000000000000000000000000000000000010000000000000000: n4473_o = 1'b1; + 63'b000000000000000000000000000000000000000000000001000000000000000: n4473_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000100000000000000: n4473_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000010000000000000: n4473_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000001000000000000: n4473_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000100000000000: n4473_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000010000000000: n4473_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000001000000000: n4473_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000100000000: n4473_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000010000000: n4473_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000001000000: n4473_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000100000: n4473_o = 1'b1; + 63'b000000000000000000000000000000000000000000000000000000000010000: n4473_o = 1'b1; + 63'b000000000000000000000000000000000000000000000000000000000001000: n4473_o = 1'b1; + 63'b000000000000000000000000000000000000000000000000000000000000100: n4473_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000000010: n4473_o = 1'b1; + 63'b000000000000000000000000000000000000000000000000000000000000001: n4473_o = 1'b0; + default: n4473_o = 1'b0; + endcase + /* decoder.vhd:635:5 */ + always @* + case (n4277_o) + 63'b100000000000000000000000000000000000000000000000000000000000000: n4476_o = 1'b0; + 63'b010000000000000000000000000000000000000000000000000000000000000: n4476_o = 1'b0; + 63'b001000000000000000000000000000000000000000000000000000000000000: n4476_o = 1'b0; + 63'b000100000000000000000000000000000000000000000000000000000000000: n4476_o = 1'b0; + 63'b000010000000000000000000000000000000000000000000000000000000000: n4476_o = 1'b0; + 63'b000001000000000000000000000000000000000000000000000000000000000: n4476_o = 1'b0; + 63'b000000100000000000000000000000000000000000000000000000000000000: n4476_o = 1'b0; + 63'b000000010000000000000000000000000000000000000000000000000000000: n4476_o = 1'b0; + 63'b000000001000000000000000000000000000000000000000000000000000000: n4476_o = 1'b0; + 63'b000000000100000000000000000000000000000000000000000000000000000: n4476_o = 1'b0; + 63'b000000000010000000000000000000000000000000000000000000000000000: n4476_o = 1'b0; + 63'b000000000001000000000000000000000000000000000000000000000000000: n4476_o = 1'b0; + 63'b000000000000100000000000000000000000000000000000000000000000000: n4476_o = 1'b0; + 63'b000000000000010000000000000000000000000000000000000000000000000: n4476_o = 1'b0; + 63'b000000000000001000000000000000000000000000000000000000000000000: n4476_o = 1'b0; + 63'b000000000000000100000000000000000000000000000000000000000000000: n4476_o = 1'b0; + 63'b000000000000000010000000000000000000000000000000000000000000000: n4476_o = 1'b0; + 63'b000000000000000001000000000000000000000000000000000000000000000: n4476_o = 1'b0; + 63'b000000000000000000100000000000000000000000000000000000000000000: n4476_o = n3646_o; + 63'b000000000000000000010000000000000000000000000000000000000000000: n4476_o = 1'b0; + 63'b000000000000000000001000000000000000000000000000000000000000000: n4476_o = 1'b0; + 63'b000000000000000000000100000000000000000000000000000000000000000: n4476_o = 1'b0; + 63'b000000000000000000000010000000000000000000000000000000000000000: n4476_o = 1'b0; + 63'b000000000000000000000001000000000000000000000000000000000000000: n4476_o = 1'b0; + 63'b000000000000000000000000100000000000000000000000000000000000000: n4476_o = 1'b0; + 63'b000000000000000000000000010000000000000000000000000000000000000: n4476_o = 1'b0; + 63'b000000000000000000000000001000000000000000000000000000000000000: n4476_o = 1'b0; + 63'b000000000000000000000000000100000000000000000000000000000000000: n4476_o = 1'b0; + 63'b000000000000000000000000000010000000000000000000000000000000000: n4476_o = 1'b0; + 63'b000000000000000000000000000001000000000000000000000000000000000: n4476_o = n3305_o; + 63'b000000000000000000000000000000100000000000000000000000000000000: n4476_o = n3267_o; + 63'b000000000000000000000000000000010000000000000000000000000000000: n4476_o = n3238_o; + 63'b000000000000000000000000000000001000000000000000000000000000000: n4476_o = n3202_o; + 63'b000000000000000000000000000000000100000000000000000000000000000: n4476_o = n3176_o; + 63'b000000000000000000000000000000000010000000000000000000000000000: n4476_o = n3150_o; + 63'b000000000000000000000000000000000001000000000000000000000000000: n4476_o = n3124_o; + 63'b000000000000000000000000000000000000100000000000000000000000000: n4476_o = n3095_o; + 63'b000000000000000000000000000000000000010000000000000000000000000: n4476_o = n3066_o; + 63'b000000000000000000000000000000000000001000000000000000000000000: n4476_o = n3032_o; + 63'b000000000000000000000000000000000000000100000000000000000000000: n4476_o = n3001_o; + 63'b000000000000000000000000000000000000000010000000000000000000000: n4476_o = 1'b0; + 63'b000000000000000000000000000000000000000001000000000000000000000: n4476_o = 1'b0; + 63'b000000000000000000000000000000000000000000100000000000000000000: n4476_o = 1'b0; + 63'b000000000000000000000000000000000000000000010000000000000000000: n4476_o = 1'b0; + 63'b000000000000000000000000000000000000000000001000000000000000000: n4476_o = 1'b0; + 63'b000000000000000000000000000000000000000000000100000000000000000: n4476_o = 1'b0; + 63'b000000000000000000000000000000000000000000000010000000000000000: n4476_o = n2843_o; + 63'b000000000000000000000000000000000000000000000001000000000000000: n4476_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000100000000000000: n4476_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000010000000000000: n4476_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000001000000000000: n4476_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000100000000000: n4476_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000010000000000: n4476_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000001000000000: n4476_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000100000000: n4476_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000010000000: n4476_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000001000000: n4476_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000100000: n4476_o = n2581_o; + 63'b000000000000000000000000000000000000000000000000000000000010000: n4476_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000001000: n4476_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000000100: n4476_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000000010: n4476_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000000001: n4476_o = 1'b0; + default: n4476_o = 1'b0; + endcase + /* decoder.vhd:635:5 */ + always @* + case (n4277_o) + 63'b100000000000000000000000000000000000000000000000000000000000000: n4479_o = 1'b0; + 63'b010000000000000000000000000000000000000000000000000000000000000: n4479_o = 1'b0; + 63'b001000000000000000000000000000000000000000000000000000000000000: n4479_o = 1'b0; + 63'b000100000000000000000000000000000000000000000000000000000000000: n4479_o = 1'b0; + 63'b000010000000000000000000000000000000000000000000000000000000000: n4479_o = 1'b0; + 63'b000001000000000000000000000000000000000000000000000000000000000: n4479_o = 1'b0; + 63'b000000100000000000000000000000000000000000000000000000000000000: n4479_o = 1'b0; + 63'b000000010000000000000000000000000000000000000000000000000000000: n4479_o = 1'b0; + 63'b000000001000000000000000000000000000000000000000000000000000000: n4479_o = 1'b0; + 63'b000000000100000000000000000000000000000000000000000000000000000: n4479_o = 1'b0; + 63'b000000000010000000000000000000000000000000000000000000000000000: n4479_o = 1'b0; + 63'b000000000001000000000000000000000000000000000000000000000000000: n4479_o = 1'b0; + 63'b000000000000100000000000000000000000000000000000000000000000000: n4479_o = 1'b0; + 63'b000000000000010000000000000000000000000000000000000000000000000: n4479_o = 1'b0; + 63'b000000000000001000000000000000000000000000000000000000000000000: n4479_o = 1'b0; + 63'b000000000000000100000000000000000000000000000000000000000000000: n4479_o = 1'b0; + 63'b000000000000000010000000000000000000000000000000000000000000000: n4479_o = 1'b0; + 63'b000000000000000001000000000000000000000000000000000000000000000: n4479_o = 1'b0; + 63'b000000000000000000100000000000000000000000000000000000000000000: n4479_o = 1'b0; + 63'b000000000000000000010000000000000000000000000000000000000000000: n4479_o = 1'b0; + 63'b000000000000000000001000000000000000000000000000000000000000000: n4479_o = 1'b0; + 63'b000000000000000000000100000000000000000000000000000000000000000: n4479_o = 1'b0; + 63'b000000000000000000000010000000000000000000000000000000000000000: n4479_o = 1'b0; + 63'b000000000000000000000001000000000000000000000000000000000000000: n4479_o = 1'b0; + 63'b000000000000000000000000100000000000000000000000000000000000000: n4479_o = 1'b0; + 63'b000000000000000000000000010000000000000000000000000000000000000: n4479_o = 1'b0; + 63'b000000000000000000000000001000000000000000000000000000000000000: n4479_o = 1'b0; + 63'b000000000000000000000000000100000000000000000000000000000000000: n4479_o = 1'b0; + 63'b000000000000000000000000000010000000000000000000000000000000000: n4479_o = 1'b0; + 63'b000000000000000000000000000001000000000000000000000000000000000: n4479_o = 1'b0; + 63'b000000000000000000000000000000100000000000000000000000000000000: n4479_o = 1'b0; + 63'b000000000000000000000000000000010000000000000000000000000000000: n4479_o = 1'b0; + 63'b000000000000000000000000000000001000000000000000000000000000000: n4479_o = 1'b0; + 63'b000000000000000000000000000000000100000000000000000000000000000: n4479_o = 1'b0; + 63'b000000000000000000000000000000000010000000000000000000000000000: n4479_o = 1'b0; + 63'b000000000000000000000000000000000001000000000000000000000000000: n4479_o = 1'b0; + 63'b000000000000000000000000000000000000100000000000000000000000000: n4479_o = 1'b0; + 63'b000000000000000000000000000000000000010000000000000000000000000: n4479_o = 1'b0; + 63'b000000000000000000000000000000000000001000000000000000000000000: n4479_o = 1'b0; + 63'b000000000000000000000000000000000000000100000000000000000000000: n4479_o = 1'b0; + 63'b000000000000000000000000000000000000000010000000000000000000000: n4479_o = 1'b0; + 63'b000000000000000000000000000000000000000001000000000000000000000: n4479_o = 1'b0; + 63'b000000000000000000000000000000000000000000100000000000000000000: n4479_o = 1'b0; + 63'b000000000000000000000000000000000000000000010000000000000000000: n4479_o = 1'b0; + 63'b000000000000000000000000000000000000000000001000000000000000000: n4479_o = 1'b0; + 63'b000000000000000000000000000000000000000000000100000000000000000: n4479_o = 1'b0; + 63'b000000000000000000000000000000000000000000000010000000000000000: n4479_o = 1'b0; + 63'b000000000000000000000000000000000000000000000001000000000000000: n4479_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000100000000000000: n4479_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000010000000000000: n4479_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000001000000000000: n4479_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000100000000000: n4479_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000010000000000: n4479_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000001000000000: n4479_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000100000000: n4479_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000010000000: n4479_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000001000000: n4479_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000100000: n4479_o = n2583_o; + 63'b000000000000000000000000000000000000000000000000000000000010000: n4479_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000001000: n4479_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000000100: n4479_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000000010: n4479_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000000001: n4479_o = 1'b0; + default: n4479_o = 1'b0; + endcase + /* decoder.vhd:635:5 */ + always @* + case (n4277_o) + 63'b100000000000000000000000000000000000000000000000000000000000000: n4482_o = 1'b0; + 63'b010000000000000000000000000000000000000000000000000000000000000: n4482_o = 1'b0; + 63'b001000000000000000000000000000000000000000000000000000000000000: n4482_o = 1'b0; + 63'b000100000000000000000000000000000000000000000000000000000000000: n4482_o = 1'b0; + 63'b000010000000000000000000000000000000000000000000000000000000000: n4482_o = 1'b0; + 63'b000001000000000000000000000000000000000000000000000000000000000: n4482_o = 1'b0; + 63'b000000100000000000000000000000000000000000000000000000000000000: n4482_o = 1'b0; + 63'b000000010000000000000000000000000000000000000000000000000000000: n4482_o = 1'b0; + 63'b000000001000000000000000000000000000000000000000000000000000000: n4482_o = 1'b0; + 63'b000000000100000000000000000000000000000000000000000000000000000: n4482_o = 1'b0; + 63'b000000000010000000000000000000000000000000000000000000000000000: n4482_o = n4022_o; + 63'b000000000001000000000000000000000000000000000000000000000000000: n4482_o = 1'b0; + 63'b000000000000100000000000000000000000000000000000000000000000000: n4482_o = 1'b0; + 63'b000000000000010000000000000000000000000000000000000000000000000: n4482_o = 1'b0; + 63'b000000000000001000000000000000000000000000000000000000000000000: n4482_o = 1'b0; + 63'b000000000000000100000000000000000000000000000000000000000000000: n4482_o = 1'b0; + 63'b000000000000000010000000000000000000000000000000000000000000000: n4482_o = 1'b0; + 63'b000000000000000001000000000000000000000000000000000000000000000: n4482_o = 1'b0; + 63'b000000000000000000100000000000000000000000000000000000000000000: n4482_o = 1'b0; + 63'b000000000000000000010000000000000000000000000000000000000000000: n4482_o = 1'b0; + 63'b000000000000000000001000000000000000000000000000000000000000000: n4482_o = 1'b0; + 63'b000000000000000000000100000000000000000000000000000000000000000: n4482_o = 1'b0; + 63'b000000000000000000000010000000000000000000000000000000000000000: n4482_o = 1'b0; + 63'b000000000000000000000001000000000000000000000000000000000000000: n4482_o = 1'b0; + 63'b000000000000000000000000100000000000000000000000000000000000000: n4482_o = 1'b0; + 63'b000000000000000000000000010000000000000000000000000000000000000: n4482_o = 1'b0; + 63'b000000000000000000000000001000000000000000000000000000000000000: n4482_o = 1'b0; + 63'b000000000000000000000000000100000000000000000000000000000000000: n4482_o = 1'b0; + 63'b000000000000000000000000000010000000000000000000000000000000000: n4482_o = 1'b0; + 63'b000000000000000000000000000001000000000000000000000000000000000: n4482_o = 1'b0; + 63'b000000000000000000000000000000100000000000000000000000000000000: n4482_o = 1'b0; + 63'b000000000000000000000000000000010000000000000000000000000000000: n4482_o = 1'b0; + 63'b000000000000000000000000000000001000000000000000000000000000000: n4482_o = 1'b0; + 63'b000000000000000000000000000000000100000000000000000000000000000: n4482_o = 1'b0; + 63'b000000000000000000000000000000000010000000000000000000000000000: n4482_o = 1'b0; + 63'b000000000000000000000000000000000001000000000000000000000000000: n4482_o = 1'b0; + 63'b000000000000000000000000000000000000100000000000000000000000000: n4482_o = 1'b0; + 63'b000000000000000000000000000000000000010000000000000000000000000: n4482_o = 1'b0; + 63'b000000000000000000000000000000000000001000000000000000000000000: n4482_o = 1'b0; + 63'b000000000000000000000000000000000000000100000000000000000000000: n4482_o = 1'b0; + 63'b000000000000000000000000000000000000000010000000000000000000000: n4482_o = 1'b0; + 63'b000000000000000000000000000000000000000001000000000000000000000: n4482_o = 1'b0; + 63'b000000000000000000000000000000000000000000100000000000000000000: n4482_o = 1'b0; + 63'b000000000000000000000000000000000000000000010000000000000000000: n4482_o = 1'b0; + 63'b000000000000000000000000000000000000000000001000000000000000000: n4482_o = 1'b0; + 63'b000000000000000000000000000000000000000000000100000000000000000: n4482_o = 1'b0; + 63'b000000000000000000000000000000000000000000000010000000000000000: n4482_o = 1'b0; + 63'b000000000000000000000000000000000000000000000001000000000000000: n4482_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000100000000000000: n4482_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000010000000000000: n4482_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000001000000000000: n4482_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000100000000000: n4482_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000010000000000: n4482_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000001000000000: n4482_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000100000000: n4482_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000010000000: n4482_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000001000000: n4482_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000100000: n4482_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000010000: n4482_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000001000: n4482_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000000100: n4482_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000000010: n4482_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000000001: n4482_o = 1'b0; + default: n4482_o = 1'b0; + endcase + /* decoder.vhd:635:5 */ + always @* + case (n4277_o) + 63'b100000000000000000000000000000000000000000000000000000000000000: n4485_o = 1'b0; + 63'b010000000000000000000000000000000000000000000000000000000000000: n4485_o = 1'b0; + 63'b001000000000000000000000000000000000000000000000000000000000000: n4485_o = 1'b0; + 63'b000100000000000000000000000000000000000000000000000000000000000: n4485_o = 1'b0; + 63'b000010000000000000000000000000000000000000000000000000000000000: n4485_o = 1'b0; + 63'b000001000000000000000000000000000000000000000000000000000000000: n4485_o = 1'b0; + 63'b000000100000000000000000000000000000000000000000000000000000000: n4485_o = 1'b0; + 63'b000000010000000000000000000000000000000000000000000000000000000: n4485_o = 1'b0; + 63'b000000001000000000000000000000000000000000000000000000000000000: n4485_o = 1'b0; + 63'b000000000100000000000000000000000000000000000000000000000000000: n4485_o = 1'b0; + 63'b000000000010000000000000000000000000000000000000000000000000000: n4485_o = 1'b0; + 63'b000000000001000000000000000000000000000000000000000000000000000: n4485_o = 1'b0; + 63'b000000000000100000000000000000000000000000000000000000000000000: n4485_o = 1'b0; + 63'b000000000000010000000000000000000000000000000000000000000000000: n4485_o = 1'b0; + 63'b000000000000001000000000000000000000000000000000000000000000000: n4485_o = 1'b0; + 63'b000000000000000100000000000000000000000000000000000000000000000: n4485_o = 1'b0; + 63'b000000000000000010000000000000000000000000000000000000000000000: n4485_o = 1'b0; + 63'b000000000000000001000000000000000000000000000000000000000000000: n4485_o = 1'b0; + 63'b000000000000000000100000000000000000000000000000000000000000000: n4485_o = 1'b0; + 63'b000000000000000000010000000000000000000000000000000000000000000: n4485_o = 1'b0; + 63'b000000000000000000001000000000000000000000000000000000000000000: n4485_o = 1'b0; + 63'b000000000000000000000100000000000000000000000000000000000000000: n4485_o = 1'b0; + 63'b000000000000000000000010000000000000000000000000000000000000000: n4485_o = 1'b0; + 63'b000000000000000000000001000000000000000000000000000000000000000: n4485_o = 1'b0; + 63'b000000000000000000000000100000000000000000000000000000000000000: n4485_o = 1'b0; + 63'b000000000000000000000000010000000000000000000000000000000000000: n4485_o = 1'b0; + 63'b000000000000000000000000001000000000000000000000000000000000000: n4485_o = 1'b0; + 63'b000000000000000000000000000100000000000000000000000000000000000: n4485_o = 1'b0; + 63'b000000000000000000000000000010000000000000000000000000000000000: n4485_o = 1'b0; + 63'b000000000000000000000000000001000000000000000000000000000000000: n4485_o = 1'b0; + 63'b000000000000000000000000000000100000000000000000000000000000000: n4485_o = 1'b0; + 63'b000000000000000000000000000000010000000000000000000000000000000: n4485_o = 1'b0; + 63'b000000000000000000000000000000001000000000000000000000000000000: n4485_o = 1'b0; + 63'b000000000000000000000000000000000100000000000000000000000000000: n4485_o = 1'b0; + 63'b000000000000000000000000000000000010000000000000000000000000000: n4485_o = 1'b0; + 63'b000000000000000000000000000000000001000000000000000000000000000: n4485_o = 1'b0; + 63'b000000000000000000000000000000000000100000000000000000000000000: n4485_o = 1'b0; + 63'b000000000000000000000000000000000000010000000000000000000000000: n4485_o = 1'b0; + 63'b000000000000000000000000000000000000001000000000000000000000000: n4485_o = 1'b0; + 63'b000000000000000000000000000000000000000100000000000000000000000: n4485_o = 1'b0; + 63'b000000000000000000000000000000000000000010000000000000000000000: n4485_o = 1'b0; + 63'b000000000000000000000000000000000000000001000000000000000000000: n4485_o = 1'b0; + 63'b000000000000000000000000000000000000000000100000000000000000000: n4485_o = 1'b0; + 63'b000000000000000000000000000000000000000000010000000000000000000: n4485_o = 1'b0; + 63'b000000000000000000000000000000000000000000001000000000000000000: n4485_o = 1'b0; + 63'b000000000000000000000000000000000000000000000100000000000000000: n4485_o = 1'b0; + 63'b000000000000000000000000000000000000000000000010000000000000000: n4485_o = 1'b0; + 63'b000000000000000000000000000000000000000000000001000000000000000: n4485_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000100000000000000: n4485_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000010000000000000: n4485_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000001000000000000: n4485_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000100000000000: n4485_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000010000000000: n4485_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000001000000000: n4485_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000100000000: n4485_o = n2625_o; + 63'b000000000000000000000000000000000000000000000000000000010000000: n4485_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000001000000: n4485_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000100000: n4485_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000010000: n4485_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000001000: n4485_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000000100: n4485_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000000010: n4485_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000000001: n4485_o = 1'b0; + default: n4485_o = 1'b0; + endcase + /* decoder.vhd:635:5 */ + always @* + case (n4277_o) + 63'b100000000000000000000000000000000000000000000000000000000000000: n4488_o = 1'b0; + 63'b010000000000000000000000000000000000000000000000000000000000000: n4488_o = 1'b0; + 63'b001000000000000000000000000000000000000000000000000000000000000: n4488_o = 1'b0; + 63'b000100000000000000000000000000000000000000000000000000000000000: n4488_o = 1'b0; + 63'b000010000000000000000000000000000000000000000000000000000000000: n4488_o = 1'b0; + 63'b000001000000000000000000000000000000000000000000000000000000000: n4488_o = 1'b0; + 63'b000000100000000000000000000000000000000000000000000000000000000: n4488_o = 1'b0; + 63'b000000010000000000000000000000000000000000000000000000000000000: n4488_o = 1'b0; + 63'b000000001000000000000000000000000000000000000000000000000000000: n4488_o = 1'b0; + 63'b000000000100000000000000000000000000000000000000000000000000000: n4488_o = 1'b0; + 63'b000000000010000000000000000000000000000000000000000000000000000: n4488_o = 1'b0; + 63'b000000000001000000000000000000000000000000000000000000000000000: n4488_o = 1'b0; + 63'b000000000000100000000000000000000000000000000000000000000000000: n4488_o = 1'b0; + 63'b000000000000010000000000000000000000000000000000000000000000000: n4488_o = 1'b0; + 63'b000000000000001000000000000000000000000000000000000000000000000: n4488_o = 1'b0; + 63'b000000000000000100000000000000000000000000000000000000000000000: n4488_o = 1'b0; + 63'b000000000000000010000000000000000000000000000000000000000000000: n4488_o = 1'b0; + 63'b000000000000000001000000000000000000000000000000000000000000000: n4488_o = 1'b0; + 63'b000000000000000000100000000000000000000000000000000000000000000: n4488_o = 1'b0; + 63'b000000000000000000010000000000000000000000000000000000000000000: n4488_o = 1'b0; + 63'b000000000000000000001000000000000000000000000000000000000000000: n4488_o = 1'b0; + 63'b000000000000000000000100000000000000000000000000000000000000000: n4488_o = 1'b0; + 63'b000000000000000000000010000000000000000000000000000000000000000: n4488_o = 1'b0; + 63'b000000000000000000000001000000000000000000000000000000000000000: n4488_o = 1'b0; + 63'b000000000000000000000000100000000000000000000000000000000000000: n4488_o = 1'b0; + 63'b000000000000000000000000010000000000000000000000000000000000000: n4488_o = 1'b0; + 63'b000000000000000000000000001000000000000000000000000000000000000: n4488_o = 1'b0; + 63'b000000000000000000000000000100000000000000000000000000000000000: n4488_o = 1'b0; + 63'b000000000000000000000000000010000000000000000000000000000000000: n4488_o = 1'b0; + 63'b000000000000000000000000000001000000000000000000000000000000000: n4488_o = 1'b0; + 63'b000000000000000000000000000000100000000000000000000000000000000: n4488_o = 1'b0; + 63'b000000000000000000000000000000010000000000000000000000000000000: n4488_o = 1'b0; + 63'b000000000000000000000000000000001000000000000000000000000000000: n4488_o = 1'b0; + 63'b000000000000000000000000000000000100000000000000000000000000000: n4488_o = 1'b0; + 63'b000000000000000000000000000000000010000000000000000000000000000: n4488_o = 1'b0; + 63'b000000000000000000000000000000000001000000000000000000000000000: n4488_o = 1'b0; + 63'b000000000000000000000000000000000000100000000000000000000000000: n4488_o = 1'b0; + 63'b000000000000000000000000000000000000010000000000000000000000000: n4488_o = 1'b0; + 63'b000000000000000000000000000000000000001000000000000000000000000: n4488_o = 1'b0; + 63'b000000000000000000000000000000000000000100000000000000000000000: n4488_o = 1'b0; + 63'b000000000000000000000000000000000000000010000000000000000000000: n4488_o = 1'b0; + 63'b000000000000000000000000000000000000000001000000000000000000000: n4488_o = 1'b0; + 63'b000000000000000000000000000000000000000000100000000000000000000: n4488_o = 1'b0; + 63'b000000000000000000000000000000000000000000010000000000000000000: n4488_o = 1'b0; + 63'b000000000000000000000000000000000000000000001000000000000000000: n4488_o = 1'b0; + 63'b000000000000000000000000000000000000000000000100000000000000000: n4488_o = 1'b0; + 63'b000000000000000000000000000000000000000000000010000000000000000: n4488_o = 1'b0; + 63'b000000000000000000000000000000000000000000000001000000000000000: n4488_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000100000000000000: n4488_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000010000000000000: n4488_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000001000000000000: n4488_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000100000000000: n4488_o = n2669_o; + 63'b000000000000000000000000000000000000000000000000000010000000000: n4488_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000001000000000: n4488_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000100000000: n4488_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000010000000: n4488_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000001000000: n4488_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000100000: n4488_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000010000: n4488_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000001000: n4488_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000000100: n4488_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000000010: n4488_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000000001: n4488_o = 1'b0; + default: n4488_o = 1'b0; + endcase + /* decoder.vhd:635:5 */ + always @* + case (n4277_o) + 63'b100000000000000000000000000000000000000000000000000000000000000: n4491_o = 1'b0; + 63'b010000000000000000000000000000000000000000000000000000000000000: n4491_o = 1'b0; + 63'b001000000000000000000000000000000000000000000000000000000000000: n4491_o = 1'b0; + 63'b000100000000000000000000000000000000000000000000000000000000000: n4491_o = 1'b0; + 63'b000010000000000000000000000000000000000000000000000000000000000: n4491_o = 1'b0; + 63'b000001000000000000000000000000000000000000000000000000000000000: n4491_o = 1'b0; + 63'b000000100000000000000000000000000000000000000000000000000000000: n4491_o = 1'b0; + 63'b000000010000000000000000000000000000000000000000000000000000000: n4491_o = n4094_o; + 63'b000000001000000000000000000000000000000000000000000000000000000: n4491_o = 1'b0; + 63'b000000000100000000000000000000000000000000000000000000000000000: n4491_o = 1'b0; + 63'b000000000010000000000000000000000000000000000000000000000000000: n4491_o = 1'b0; + 63'b000000000001000000000000000000000000000000000000000000000000000: n4491_o = 1'b0; + 63'b000000000000100000000000000000000000000000000000000000000000000: n4491_o = 1'b0; + 63'b000000000000010000000000000000000000000000000000000000000000000: n4491_o = 1'b0; + 63'b000000000000001000000000000000000000000000000000000000000000000: n4491_o = 1'b0; + 63'b000000000000000100000000000000000000000000000000000000000000000: n4491_o = 1'b0; + 63'b000000000000000010000000000000000000000000000000000000000000000: n4491_o = 1'b0; + 63'b000000000000000001000000000000000000000000000000000000000000000: n4491_o = 1'b0; + 63'b000000000000000000100000000000000000000000000000000000000000000: n4491_o = 1'b0; + 63'b000000000000000000010000000000000000000000000000000000000000000: n4491_o = 1'b0; + 63'b000000000000000000001000000000000000000000000000000000000000000: n4491_o = 1'b0; + 63'b000000000000000000000100000000000000000000000000000000000000000: n4491_o = 1'b0; + 63'b000000000000000000000010000000000000000000000000000000000000000: n4491_o = 1'b0; + 63'b000000000000000000000001000000000000000000000000000000000000000: n4491_o = 1'b0; + 63'b000000000000000000000000100000000000000000000000000000000000000: n4491_o = 1'b0; + 63'b000000000000000000000000010000000000000000000000000000000000000: n4491_o = 1'b0; + 63'b000000000000000000000000001000000000000000000000000000000000000: n4491_o = 1'b0; + 63'b000000000000000000000000000100000000000000000000000000000000000: n4491_o = 1'b0; + 63'b000000000000000000000000000010000000000000000000000000000000000: n4491_o = 1'b0; + 63'b000000000000000000000000000001000000000000000000000000000000000: n4491_o = 1'b0; + 63'b000000000000000000000000000000100000000000000000000000000000000: n4491_o = 1'b0; + 63'b000000000000000000000000000000010000000000000000000000000000000: n4491_o = 1'b0; + 63'b000000000000000000000000000000001000000000000000000000000000000: n4491_o = 1'b0; + 63'b000000000000000000000000000000000100000000000000000000000000000: n4491_o = 1'b0; + 63'b000000000000000000000000000000000010000000000000000000000000000: n4491_o = 1'b0; + 63'b000000000000000000000000000000000001000000000000000000000000000: n4491_o = 1'b0; + 63'b000000000000000000000000000000000000100000000000000000000000000: n4491_o = 1'b0; + 63'b000000000000000000000000000000000000010000000000000000000000000: n4491_o = 1'b0; + 63'b000000000000000000000000000000000000001000000000000000000000000: n4491_o = 1'b0; + 63'b000000000000000000000000000000000000000100000000000000000000000: n4491_o = 1'b0; + 63'b000000000000000000000000000000000000000010000000000000000000000: n4491_o = 1'b0; + 63'b000000000000000000000000000000000000000001000000000000000000000: n4491_o = 1'b0; + 63'b000000000000000000000000000000000000000000100000000000000000000: n4491_o = 1'b0; + 63'b000000000000000000000000000000000000000000010000000000000000000: n4491_o = 1'b0; + 63'b000000000000000000000000000000000000000000001000000000000000000: n4491_o = 1'b0; + 63'b000000000000000000000000000000000000000000000100000000000000000: n4491_o = 1'b0; + 63'b000000000000000000000000000000000000000000000010000000000000000: n4491_o = 1'b0; + 63'b000000000000000000000000000000000000000000000001000000000000000: n4491_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000100000000000000: n4491_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000010000000000000: n4491_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000001000000000000: n4491_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000100000000000: n4491_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000010000000000: n4491_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000001000000000: n4491_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000100000000: n4491_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000010000000: n4491_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000001000000: n4491_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000100000: n4491_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000010000: n4491_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000001000: n4491_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000000100: n4491_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000000010: n4491_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000000001: n4491_o = 1'b0; + default: n4491_o = 1'b0; + endcase + /* decoder.vhd:635:5 */ + always @* + case (n4277_o) + 63'b100000000000000000000000000000000000000000000000000000000000000: n4494_o = 1'b0; + 63'b010000000000000000000000000000000000000000000000000000000000000: n4494_o = 1'b0; + 63'b001000000000000000000000000000000000000000000000000000000000000: n4494_o = 1'b0; + 63'b000100000000000000000000000000000000000000000000000000000000000: n4494_o = 1'b0; + 63'b000010000000000000000000000000000000000000000000000000000000000: n4494_o = 1'b0; + 63'b000001000000000000000000000000000000000000000000000000000000000: n4494_o = 1'b0; + 63'b000000100000000000000000000000000000000000000000000000000000000: n4494_o = 1'b0; + 63'b000000010000000000000000000000000000000000000000000000000000000: n4494_o = n4096_o; + 63'b000000001000000000000000000000000000000000000000000000000000000: n4494_o = 1'b0; + 63'b000000000100000000000000000000000000000000000000000000000000000: n4494_o = 1'b0; + 63'b000000000010000000000000000000000000000000000000000000000000000: n4494_o = 1'b0; + 63'b000000000001000000000000000000000000000000000000000000000000000: n4494_o = 1'b0; + 63'b000000000000100000000000000000000000000000000000000000000000000: n4494_o = 1'b0; + 63'b000000000000010000000000000000000000000000000000000000000000000: n4494_o = 1'b0; + 63'b000000000000001000000000000000000000000000000000000000000000000: n4494_o = 1'b0; + 63'b000000000000000100000000000000000000000000000000000000000000000: n4494_o = 1'b0; + 63'b000000000000000010000000000000000000000000000000000000000000000: n4494_o = 1'b0; + 63'b000000000000000001000000000000000000000000000000000000000000000: n4494_o = 1'b0; + 63'b000000000000000000100000000000000000000000000000000000000000000: n4494_o = 1'b0; + 63'b000000000000000000010000000000000000000000000000000000000000000: n4494_o = 1'b0; + 63'b000000000000000000001000000000000000000000000000000000000000000: n4494_o = 1'b0; + 63'b000000000000000000000100000000000000000000000000000000000000000: n4494_o = 1'b0; + 63'b000000000000000000000010000000000000000000000000000000000000000: n4494_o = 1'b0; + 63'b000000000000000000000001000000000000000000000000000000000000000: n4494_o = 1'b0; + 63'b000000000000000000000000100000000000000000000000000000000000000: n4494_o = 1'b0; + 63'b000000000000000000000000010000000000000000000000000000000000000: n4494_o = 1'b0; + 63'b000000000000000000000000001000000000000000000000000000000000000: n4494_o = 1'b0; + 63'b000000000000000000000000000100000000000000000000000000000000000: n4494_o = 1'b0; + 63'b000000000000000000000000000010000000000000000000000000000000000: n4494_o = 1'b0; + 63'b000000000000000000000000000001000000000000000000000000000000000: n4494_o = 1'b0; + 63'b000000000000000000000000000000100000000000000000000000000000000: n4494_o = 1'b0; + 63'b000000000000000000000000000000010000000000000000000000000000000: n4494_o = 1'b0; + 63'b000000000000000000000000000000001000000000000000000000000000000: n4494_o = 1'b0; + 63'b000000000000000000000000000000000100000000000000000000000000000: n4494_o = 1'b0; + 63'b000000000000000000000000000000000010000000000000000000000000000: n4494_o = 1'b0; + 63'b000000000000000000000000000000000001000000000000000000000000000: n4494_o = 1'b0; + 63'b000000000000000000000000000000000000100000000000000000000000000: n4494_o = 1'b0; + 63'b000000000000000000000000000000000000010000000000000000000000000: n4494_o = 1'b0; + 63'b000000000000000000000000000000000000001000000000000000000000000: n4494_o = 1'b0; + 63'b000000000000000000000000000000000000000100000000000000000000000: n4494_o = 1'b0; + 63'b000000000000000000000000000000000000000010000000000000000000000: n4494_o = 1'b0; + 63'b000000000000000000000000000000000000000001000000000000000000000: n4494_o = 1'b0; + 63'b000000000000000000000000000000000000000000100000000000000000000: n4494_o = 1'b0; + 63'b000000000000000000000000000000000000000000010000000000000000000: n4494_o = 1'b0; + 63'b000000000000000000000000000000000000000000001000000000000000000: n4494_o = 1'b0; + 63'b000000000000000000000000000000000000000000000100000000000000000: n4494_o = 1'b0; + 63'b000000000000000000000000000000000000000000000010000000000000000: n4494_o = 1'b0; + 63'b000000000000000000000000000000000000000000000001000000000000000: n4494_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000100000000000000: n4494_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000010000000000000: n4494_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000001000000000000: n4494_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000100000000000: n4494_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000010000000000: n4494_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000001000000000: n4494_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000100000000: n4494_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000010000000: n4494_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000001000000: n4494_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000100000: n4494_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000010000: n4494_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000001000: n4494_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000000100: n4494_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000000010: n4494_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000000001: n4494_o = 1'b0; + default: n4494_o = 1'b0; + endcase + /* decoder.vhd:635:5 */ + always @* + case (n4277_o) + 63'b100000000000000000000000000000000000000000000000000000000000000: n4497_o = 1'b0; + 63'b010000000000000000000000000000000000000000000000000000000000000: n4497_o = 1'b0; + 63'b001000000000000000000000000000000000000000000000000000000000000: n4497_o = 1'b0; + 63'b000100000000000000000000000000000000000000000000000000000000000: n4497_o = 1'b0; + 63'b000010000000000000000000000000000000000000000000000000000000000: n4497_o = 1'b0; + 63'b000001000000000000000000000000000000000000000000000000000000000: n4497_o = 1'b0; + 63'b000000100000000000000000000000000000000000000000000000000000000: n4497_o = 1'b0; + 63'b000000010000000000000000000000000000000000000000000000000000000: n4497_o = 1'b0; + 63'b000000001000000000000000000000000000000000000000000000000000000: n4497_o = 1'b0; + 63'b000000000100000000000000000000000000000000000000000000000000000: n4497_o = 1'b0; + 63'b000000000010000000000000000000000000000000000000000000000000000: n4497_o = 1'b0; + 63'b000000000001000000000000000000000000000000000000000000000000000: n4497_o = 1'b0; + 63'b000000000000100000000000000000000000000000000000000000000000000: n4497_o = 1'b0; + 63'b000000000000010000000000000000000000000000000000000000000000000: n4497_o = 1'b0; + 63'b000000000000001000000000000000000000000000000000000000000000000: n4497_o = 1'b0; + 63'b000000000000000100000000000000000000000000000000000000000000000: n4497_o = 1'b0; + 63'b000000000000000010000000000000000000000000000000000000000000000: n4497_o = 1'b0; + 63'b000000000000000001000000000000000000000000000000000000000000000: n4497_o = 1'b0; + 63'b000000000000000000100000000000000000000000000000000000000000000: n4497_o = 1'b0; + 63'b000000000000000000010000000000000000000000000000000000000000000: n4497_o = 1'b0; + 63'b000000000000000000001000000000000000000000000000000000000000000: n4497_o = 1'b0; + 63'b000000000000000000000100000000000000000000000000000000000000000: n4497_o = 1'b0; + 63'b000000000000000000000010000000000000000000000000000000000000000: n4497_o = 1'b0; + 63'b000000000000000000000001000000000000000000000000000000000000000: n4497_o = 1'b0; + 63'b000000000000000000000000100000000000000000000000000000000000000: n4497_o = 1'b0; + 63'b000000000000000000000000010000000000000000000000000000000000000: n4497_o = 1'b0; + 63'b000000000000000000000000001000000000000000000000000000000000000: n4497_o = 1'b0; + 63'b000000000000000000000000000100000000000000000000000000000000000: n4497_o = 1'b0; + 63'b000000000000000000000000000010000000000000000000000000000000000: n4497_o = 1'b0; + 63'b000000000000000000000000000001000000000000000000000000000000000: n4497_o = 1'b0; + 63'b000000000000000000000000000000100000000000000000000000000000000: n4497_o = 1'b0; + 63'b000000000000000000000000000000010000000000000000000000000000000: n4497_o = 1'b0; + 63'b000000000000000000000000000000001000000000000000000000000000000: n4497_o = 1'b0; + 63'b000000000000000000000000000000000100000000000000000000000000000: n4497_o = 1'b0; + 63'b000000000000000000000000000000000010000000000000000000000000000: n4497_o = 1'b0; + 63'b000000000000000000000000000000000001000000000000000000000000000: n4497_o = 1'b0; + 63'b000000000000000000000000000000000000100000000000000000000000000: n4497_o = 1'b0; + 63'b000000000000000000000000000000000000010000000000000000000000000: n4497_o = 1'b0; + 63'b000000000000000000000000000000000000001000000000000000000000000: n4497_o = 1'b0; + 63'b000000000000000000000000000000000000000100000000000000000000000: n4497_o = 1'b0; + 63'b000000000000000000000000000000000000000010000000000000000000000: n4497_o = 1'b0; + 63'b000000000000000000000000000000000000000001000000000000000000000: n4497_o = 1'b0; + 63'b000000000000000000000000000000000000000000100000000000000000000: n4497_o = 1'b0; + 63'b000000000000000000000000000000000000000000010000000000000000000: n4497_o = 1'b0; + 63'b000000000000000000000000000000000000000000001000000000000000000: n4497_o = n2868_o; + 63'b000000000000000000000000000000000000000000000100000000000000000: n4497_o = 1'b0; + 63'b000000000000000000000000000000000000000000000010000000000000000: n4497_o = 1'b0; + 63'b000000000000000000000000000000000000000000000001000000000000000: n4497_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000100000000000000: n4497_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000010000000000000: n4497_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000001000000000000: n4497_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000100000000000: n4497_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000010000000000: n4497_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000001000000000: n4497_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000100000000: n4497_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000010000000: n4497_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000001000000: n4497_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000100000: n4497_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000010000: n4497_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000001000: n4497_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000000100: n4497_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000000010: n4497_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000000001: n4497_o = 1'b0; + default: n4497_o = 1'b0; + endcase + /* decoder.vhd:635:5 */ + always @* + case (n4277_o) + 63'b100000000000000000000000000000000000000000000000000000000000000: n4499_o = n2160_o; + 63'b010000000000000000000000000000000000000000000000000000000000000: n4499_o = n2160_o; + 63'b001000000000000000000000000000000000000000000000000000000000000: n4499_o = n2160_o; + 63'b000100000000000000000000000000000000000000000000000000000000000: n4499_o = n2160_o; + 63'b000010000000000000000000000000000000000000000000000000000000000: n4499_o = n2160_o; + 63'b000001000000000000000000000000000000000000000000000000000000000: n4499_o = n2160_o; + 63'b000000100000000000000000000000000000000000000000000000000000000: n4499_o = n2160_o; + 63'b000000010000000000000000000000000000000000000000000000000000000: n4499_o = n2160_o; + 63'b000000001000000000000000000000000000000000000000000000000000000: n4499_o = n2160_o; + 63'b000000000100000000000000000000000000000000000000000000000000000: n4499_o = n2160_o; + 63'b000000000010000000000000000000000000000000000000000000000000000: n4499_o = n2160_o; + 63'b000000000001000000000000000000000000000000000000000000000000000: n4499_o = n2160_o; + 63'b000000000000100000000000000000000000000000000000000000000000000: n4499_o = n2160_o; + 63'b000000000000010000000000000000000000000000000000000000000000000: n4499_o = n2160_o; + 63'b000000000000001000000000000000000000000000000000000000000000000: n4499_o = n2160_o; + 63'b000000000000000100000000000000000000000000000000000000000000000: n4499_o = n2160_o; + 63'b000000000000000010000000000000000000000000000000000000000000000: n4499_o = n2160_o; + 63'b000000000000000001000000000000000000000000000000000000000000000: n4499_o = n2160_o; + 63'b000000000000000000100000000000000000000000000000000000000000000: n4499_o = n2160_o; + 63'b000000000000000000010000000000000000000000000000000000000000000: n4499_o = n3613_o; + 63'b000000000000000000001000000000000000000000000000000000000000000: n4499_o = n3548_o; + 63'b000000000000000000000100000000000000000000000000000000000000000: n4499_o = n2160_o; + 63'b000000000000000000000010000000000000000000000000000000000000000: n4499_o = n2160_o; + 63'b000000000000000000000001000000000000000000000000000000000000000: n4499_o = n2160_o; + 63'b000000000000000000000000100000000000000000000000000000000000000: n4499_o = n2160_o; + 63'b000000000000000000000000010000000000000000000000000000000000000: n4499_o = n2160_o; + 63'b000000000000000000000000001000000000000000000000000000000000000: n4499_o = n2160_o; + 63'b000000000000000000000000000100000000000000000000000000000000000: n4499_o = n2160_o; + 63'b000000000000000000000000000010000000000000000000000000000000000: n4499_o = n2160_o; + 63'b000000000000000000000000000001000000000000000000000000000000000: n4499_o = n2160_o; + 63'b000000000000000000000000000000100000000000000000000000000000000: n4499_o = n2160_o; + 63'b000000000000000000000000000000010000000000000000000000000000000: n4499_o = n2160_o; + 63'b000000000000000000000000000000001000000000000000000000000000000: n4499_o = n2160_o; + 63'b000000000000000000000000000000000100000000000000000000000000000: n4499_o = n2160_o; + 63'b000000000000000000000000000000000010000000000000000000000000000: n4499_o = n2160_o; + 63'b000000000000000000000000000000000001000000000000000000000000000: n4499_o = n2160_o; + 63'b000000000000000000000000000000000000100000000000000000000000000: n4499_o = n3096_o; + 63'b000000000000000000000000000000000000010000000000000000000000000: n4499_o = n2160_o; + 63'b000000000000000000000000000000000000001000000000000000000000000: n4499_o = n2160_o; + 63'b000000000000000000000000000000000000000100000000000000000000000: n4499_o = n2160_o; + 63'b000000000000000000000000000000000000000010000000000000000000000: n4499_o = n2160_o; + 63'b000000000000000000000000000000000000000001000000000000000000000: n4499_o = n2160_o; + 63'b000000000000000000000000000000000000000000100000000000000000000: n4499_o = n2160_o; + 63'b000000000000000000000000000000000000000000010000000000000000000: n4499_o = n2160_o; + 63'b000000000000000000000000000000000000000000001000000000000000000: n4499_o = n2160_o; + 63'b000000000000000000000000000000000000000000000100000000000000000: n4499_o = n2160_o; + 63'b000000000000000000000000000000000000000000000010000000000000000: n4499_o = n2160_o; + 63'b000000000000000000000000000000000000000000000001000000000000000: n4499_o = n2160_o; + 63'b000000000000000000000000000000000000000000000000100000000000000: n4499_o = n2160_o; + 63'b000000000000000000000000000000000000000000000000010000000000000: n4499_o = n2160_o; + 63'b000000000000000000000000000000000000000000000000001000000000000: n4499_o = n2160_o; + 63'b000000000000000000000000000000000000000000000000000100000000000: n4499_o = n2160_o; + 63'b000000000000000000000000000000000000000000000000000010000000000: n4499_o = n2160_o; + 63'b000000000000000000000000000000000000000000000000000001000000000: n4499_o = n2160_o; + 63'b000000000000000000000000000000000000000000000000000000100000000: n4499_o = n2160_o; + 63'b000000000000000000000000000000000000000000000000000000010000000: n4499_o = n2160_o; + 63'b000000000000000000000000000000000000000000000000000000001000000: n4499_o = n2160_o; + 63'b000000000000000000000000000000000000000000000000000000000100000: n4499_o = n2584_o; + 63'b000000000000000000000000000000000000000000000000000000000010000: n4499_o = n2160_o; + 63'b000000000000000000000000000000000000000000000000000000000001000: n4499_o = n2160_o; + 63'b000000000000000000000000000000000000000000000000000000000000100: n4499_o = n2160_o; + 63'b000000000000000000000000000000000000000000000000000000000000010: n4499_o = n2160_o; + 63'b000000000000000000000000000000000000000000000000000000000000001: n4499_o = n2160_o; + default: n4499_o = n2160_o; + endcase + /* decoder.vhd:635:5 */ + always @* + case (n4277_o) + 63'b100000000000000000000000000000000000000000000000000000000000000: n4500_o = n2164_o; + 63'b010000000000000000000000000000000000000000000000000000000000000: n4500_o = n2164_o; + 63'b001000000000000000000000000000000000000000000000000000000000000: n4500_o = n2164_o; + 63'b000100000000000000000000000000000000000000000000000000000000000: n4500_o = n2164_o; + 63'b000010000000000000000000000000000000000000000000000000000000000: n4500_o = n2164_o; + 63'b000001000000000000000000000000000000000000000000000000000000000: n4500_o = n2164_o; + 63'b000000100000000000000000000000000000000000000000000000000000000: n4500_o = n2164_o; + 63'b000000010000000000000000000000000000000000000000000000000000000: n4500_o = n2164_o; + 63'b000000001000000000000000000000000000000000000000000000000000000: n4500_o = n2164_o; + 63'b000000000100000000000000000000000000000000000000000000000000000: n4500_o = n2164_o; + 63'b000000000010000000000000000000000000000000000000000000000000000: n4500_o = n2164_o; + 63'b000000000001000000000000000000000000000000000000000000000000000: n4500_o = n2164_o; + 63'b000000000000100000000000000000000000000000000000000000000000000: n4500_o = n2164_o; + 63'b000000000000010000000000000000000000000000000000000000000000000: n4500_o = n2164_o; + 63'b000000000000001000000000000000000000000000000000000000000000000: n4500_o = n2164_o; + 63'b000000000000000100000000000000000000000000000000000000000000000: n4500_o = n2164_o; + 63'b000000000000000010000000000000000000000000000000000000000000000: n4500_o = n2164_o; + 63'b000000000000000001000000000000000000000000000000000000000000000: n4500_o = n2164_o; + 63'b000000000000000000100000000000000000000000000000000000000000000: n4500_o = n2164_o; + 63'b000000000000000000010000000000000000000000000000000000000000000: n4500_o = n3614_o; + 63'b000000000000000000001000000000000000000000000000000000000000000: n4500_o = n3549_o; + 63'b000000000000000000000100000000000000000000000000000000000000000: n4500_o = n2164_o; + 63'b000000000000000000000010000000000000000000000000000000000000000: n4500_o = n2164_o; + 63'b000000000000000000000001000000000000000000000000000000000000000: n4500_o = n2164_o; + 63'b000000000000000000000000100000000000000000000000000000000000000: n4500_o = n2164_o; + 63'b000000000000000000000000010000000000000000000000000000000000000: n4500_o = n2164_o; + 63'b000000000000000000000000001000000000000000000000000000000000000: n4500_o = n2164_o; + 63'b000000000000000000000000000100000000000000000000000000000000000: n4500_o = n2164_o; + 63'b000000000000000000000000000010000000000000000000000000000000000: n4500_o = n2164_o; + 63'b000000000000000000000000000001000000000000000000000000000000000: n4500_o = n2164_o; + 63'b000000000000000000000000000000100000000000000000000000000000000: n4500_o = n2164_o; + 63'b000000000000000000000000000000010000000000000000000000000000000: n4500_o = n2164_o; + 63'b000000000000000000000000000000001000000000000000000000000000000: n4500_o = n2164_o; + 63'b000000000000000000000000000000000100000000000000000000000000000: n4500_o = n2164_o; + 63'b000000000000000000000000000000000010000000000000000000000000000: n4500_o = n2164_o; + 63'b000000000000000000000000000000000001000000000000000000000000000: n4500_o = n2164_o; + 63'b000000000000000000000000000000000000100000000000000000000000000: n4500_o = n3097_o; + 63'b000000000000000000000000000000000000010000000000000000000000000: n4500_o = n2164_o; + 63'b000000000000000000000000000000000000001000000000000000000000000: n4500_o = n2164_o; + 63'b000000000000000000000000000000000000000100000000000000000000000: n4500_o = n2164_o; + 63'b000000000000000000000000000000000000000010000000000000000000000: n4500_o = n2164_o; + 63'b000000000000000000000000000000000000000001000000000000000000000: n4500_o = n2164_o; + 63'b000000000000000000000000000000000000000000100000000000000000000: n4500_o = n2164_o; + 63'b000000000000000000000000000000000000000000010000000000000000000: n4500_o = n2164_o; + 63'b000000000000000000000000000000000000000000001000000000000000000: n4500_o = n2164_o; + 63'b000000000000000000000000000000000000000000000100000000000000000: n4500_o = n2164_o; + 63'b000000000000000000000000000000000000000000000010000000000000000: n4500_o = n2164_o; + 63'b000000000000000000000000000000000000000000000001000000000000000: n4500_o = n2164_o; + 63'b000000000000000000000000000000000000000000000000100000000000000: n4500_o = n2164_o; + 63'b000000000000000000000000000000000000000000000000010000000000000: n4500_o = n2164_o; + 63'b000000000000000000000000000000000000000000000000001000000000000: n4500_o = n2164_o; + 63'b000000000000000000000000000000000000000000000000000100000000000: n4500_o = n2164_o; + 63'b000000000000000000000000000000000000000000000000000010000000000: n4500_o = n2164_o; + 63'b000000000000000000000000000000000000000000000000000001000000000: n4500_o = n2164_o; + 63'b000000000000000000000000000000000000000000000000000000100000000: n4500_o = n2164_o; + 63'b000000000000000000000000000000000000000000000000000000010000000: n4500_o = n2164_o; + 63'b000000000000000000000000000000000000000000000000000000001000000: n4500_o = n2164_o; + 63'b000000000000000000000000000000000000000000000000000000000100000: n4500_o = n2585_o; + 63'b000000000000000000000000000000000000000000000000000000000010000: n4500_o = n2164_o; + 63'b000000000000000000000000000000000000000000000000000000000001000: n4500_o = n2164_o; + 63'b000000000000000000000000000000000000000000000000000000000000100: n4500_o = n2164_o; + 63'b000000000000000000000000000000000000000000000000000000000000010: n4500_o = n2164_o; + 63'b000000000000000000000000000000000000000000000000000000000000001: n4500_o = n2164_o; + default: n4500_o = n2164_o; + endcase + /* decoder.vhd:635:5 */ + always @* + case (n4277_o) + 63'b100000000000000000000000000000000000000000000000000000000000000: n4502_o = 1'b0; + 63'b010000000000000000000000000000000000000000000000000000000000000: n4502_o = 1'b0; + 63'b001000000000000000000000000000000000000000000000000000000000000: n4502_o = 1'b0; + 63'b000100000000000000000000000000000000000000000000000000000000000: n4502_o = 1'b0; + 63'b000010000000000000000000000000000000000000000000000000000000000: n4502_o = 1'b0; + 63'b000001000000000000000000000000000000000000000000000000000000000: n4502_o = 1'b0; + 63'b000000100000000000000000000000000000000000000000000000000000000: n4502_o = 1'b0; + 63'b000000010000000000000000000000000000000000000000000000000000000: n4502_o = 1'b0; + 63'b000000001000000000000000000000000000000000000000000000000000000: n4502_o = 1'b0; + 63'b000000000100000000000000000000000000000000000000000000000000000: n4502_o = 1'b0; + 63'b000000000010000000000000000000000000000000000000000000000000000: n4502_o = 1'b0; + 63'b000000000001000000000000000000000000000000000000000000000000000: n4502_o = 1'b0; + 63'b000000000000100000000000000000000000000000000000000000000000000: n4502_o = 1'b0; + 63'b000000000000010000000000000000000000000000000000000000000000000: n4502_o = n3906_o; + 63'b000000000000001000000000000000000000000000000000000000000000000: n4502_o = 1'b0; + 63'b000000000000000100000000000000000000000000000000000000000000000: n4502_o = 1'b0; + 63'b000000000000000010000000000000000000000000000000000000000000000: n4502_o = 1'b0; + 63'b000000000000000001000000000000000000000000000000000000000000000: n4502_o = n3709_o; + 63'b000000000000000000100000000000000000000000000000000000000000000: n4502_o = 1'b0; + 63'b000000000000000000010000000000000000000000000000000000000000000: n4502_o = 1'b0; + 63'b000000000000000000001000000000000000000000000000000000000000000: n4502_o = 1'b0; + 63'b000000000000000000000100000000000000000000000000000000000000000: n4502_o = 1'b0; + 63'b000000000000000000000010000000000000000000000000000000000000000: n4502_o = 1'b0; + 63'b000000000000000000000001000000000000000000000000000000000000000: n4502_o = 1'b0; + 63'b000000000000000000000000100000000000000000000000000000000000000: n4502_o = 1'b0; + 63'b000000000000000000000000010000000000000000000000000000000000000: n4502_o = 1'b0; + 63'b000000000000000000000000001000000000000000000000000000000000000: n4502_o = 1'b0; + 63'b000000000000000000000000000100000000000000000000000000000000000: n4502_o = 1'b0; + 63'b000000000000000000000000000010000000000000000000000000000000000: n4502_o = 1'b0; + 63'b000000000000000000000000000001000000000000000000000000000000000: n4502_o = 1'b0; + 63'b000000000000000000000000000000100000000000000000000000000000000: n4502_o = 1'b0; + 63'b000000000000000000000000000000010000000000000000000000000000000: n4502_o = 1'b0; + 63'b000000000000000000000000000000001000000000000000000000000000000: n4502_o = 1'b0; + 63'b000000000000000000000000000000000100000000000000000000000000000: n4502_o = 1'b0; + 63'b000000000000000000000000000000000010000000000000000000000000000: n4502_o = 1'b0; + 63'b000000000000000000000000000000000001000000000000000000000000000: n4502_o = 1'b0; + 63'b000000000000000000000000000000000000100000000000000000000000000: n4502_o = 1'b0; + 63'b000000000000000000000000000000000000010000000000000000000000000: n4502_o = 1'b0; + 63'b000000000000000000000000000000000000001000000000000000000000000: n4502_o = 1'b0; + 63'b000000000000000000000000000000000000000100000000000000000000000: n4502_o = 1'b0; + 63'b000000000000000000000000000000000000000010000000000000000000000: n4502_o = 1'b0; + 63'b000000000000000000000000000000000000000001000000000000000000000: n4502_o = n2909_o; + 63'b000000000000000000000000000000000000000000100000000000000000000: n4502_o = n2898_o; + 63'b000000000000000000000000000000000000000000010000000000000000000: n4502_o = 1'b0; + 63'b000000000000000000000000000000000000000000001000000000000000000: n4502_o = 1'b0; + 63'b000000000000000000000000000000000000000000000100000000000000000: n4502_o = 1'b0; + 63'b000000000000000000000000000000000000000000000010000000000000000: n4502_o = 1'b0; + 63'b000000000000000000000000000000000000000000000001000000000000000: n4502_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000100000000000000: n4502_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000010000000000000: n4502_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000001000000000000: n4502_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000100000000000: n4502_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000010000000000: n4502_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000001000000000: n4502_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000100000000: n4502_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000010000000: n4502_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000001000000: n4502_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000100000: n4502_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000010000: n4502_o = n2471_o; + 63'b000000000000000000000000000000000000000000000000000000000001000: n4502_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000000100: n4502_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000000010: n4502_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000000001: n4502_o = 1'b0; + default: n4502_o = 1'b0; + endcase + /* decoder.vhd:635:5 */ + always @* + case (n4277_o) + 63'b100000000000000000000000000000000000000000000000000000000000000: n4505_o = 1'b0; + 63'b010000000000000000000000000000000000000000000000000000000000000: n4505_o = 1'b0; + 63'b001000000000000000000000000000000000000000000000000000000000000: n4505_o = n4194_o; + 63'b000100000000000000000000000000000000000000000000000000000000000: n4505_o = 1'b0; + 63'b000010000000000000000000000000000000000000000000000000000000000: n4505_o = 1'b0; + 63'b000001000000000000000000000000000000000000000000000000000000000: n4505_o = 1'b0; + 63'b000000100000000000000000000000000000000000000000000000000000000: n4505_o = 1'b0; + 63'b000000010000000000000000000000000000000000000000000000000000000: n4505_o = 1'b0; + 63'b000000001000000000000000000000000000000000000000000000000000000: n4505_o = 1'b0; + 63'b000000000100000000000000000000000000000000000000000000000000000: n4505_o = 1'b0; + 63'b000000000010000000000000000000000000000000000000000000000000000: n4505_o = 1'b0; + 63'b000000000001000000000000000000000000000000000000000000000000000: n4505_o = 1'b0; + 63'b000000000000100000000000000000000000000000000000000000000000000: n4505_o = 1'b0; + 63'b000000000000010000000000000000000000000000000000000000000000000: n4505_o = 1'b0; + 63'b000000000000001000000000000000000000000000000000000000000000000: n4505_o = 1'b0; + 63'b000000000000000100000000000000000000000000000000000000000000000: n4505_o = 1'b0; + 63'b000000000000000010000000000000000000000000000000000000000000000: n4505_o = 1'b0; + 63'b000000000000000001000000000000000000000000000000000000000000000: n4505_o = 1'b0; + 63'b000000000000000000100000000000000000000000000000000000000000000: n4505_o = 1'b0; + 63'b000000000000000000010000000000000000000000000000000000000000000: n4505_o = 1'b0; + 63'b000000000000000000001000000000000000000000000000000000000000000: n4505_o = 1'b0; + 63'b000000000000000000000100000000000000000000000000000000000000000: n4505_o = 1'b0; + 63'b000000000000000000000010000000000000000000000000000000000000000: n4505_o = 1'b0; + 63'b000000000000000000000001000000000000000000000000000000000000000: n4505_o = n3447_o; + 63'b000000000000000000000000100000000000000000000000000000000000000: n4505_o = n3413_o; + 63'b000000000000000000000000010000000000000000000000000000000000000: n4505_o = 1'b0; + 63'b000000000000000000000000001000000000000000000000000000000000000: n4505_o = 1'b0; + 63'b000000000000000000000000000100000000000000000000000000000000000: n4505_o = 1'b0; + 63'b000000000000000000000000000010000000000000000000000000000000000: n4505_o = 1'b0; + 63'b000000000000000000000000000001000000000000000000000000000000000: n4505_o = 1'b0; + 63'b000000000000000000000000000000100000000000000000000000000000000: n4505_o = 1'b0; + 63'b000000000000000000000000000000010000000000000000000000000000000: n4505_o = 1'b0; + 63'b000000000000000000000000000000001000000000000000000000000000000: n4505_o = 1'b0; + 63'b000000000000000000000000000000000100000000000000000000000000000: n4505_o = 1'b0; + 63'b000000000000000000000000000000000010000000000000000000000000000: n4505_o = 1'b0; + 63'b000000000000000000000000000000000001000000000000000000000000000: n4505_o = 1'b0; + 63'b000000000000000000000000000000000000100000000000000000000000000: n4505_o = 1'b0; + 63'b000000000000000000000000000000000000010000000000000000000000000: n4505_o = 1'b0; + 63'b000000000000000000000000000000000000001000000000000000000000000: n4505_o = 1'b0; + 63'b000000000000000000000000000000000000000100000000000000000000000: n4505_o = 1'b0; + 63'b000000000000000000000000000000000000000010000000000000000000000: n4505_o = n2970_o; + 63'b000000000000000000000000000000000000000001000000000000000000000: n4505_o = 1'b0; + 63'b000000000000000000000000000000000000000000100000000000000000000: n4505_o = 1'b0; + 63'b000000000000000000000000000000000000000000010000000000000000000: n4505_o = 1'b0; + 63'b000000000000000000000000000000000000000000001000000000000000000: n4505_o = 1'b0; + 63'b000000000000000000000000000000000000000000000100000000000000000: n4505_o = 1'b0; + 63'b000000000000000000000000000000000000000000000010000000000000000: n4505_o = n2845_o; + 63'b000000000000000000000000000000000000000000000001000000000000000: n4505_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000100000000000000: n4505_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000010000000000000: n4505_o = n2751_o; + 63'b000000000000000000000000000000000000000000000000001000000000000: n4505_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000100000000000: n4505_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000010000000000: n4505_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000001000000000: n4505_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000100000000: n4505_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000010000000: n4505_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000001000000: n4505_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000100000: n4505_o = n2587_o; + 63'b000000000000000000000000000000000000000000000000000000000010000: n4505_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000001000: n4505_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000000100: n4505_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000000010: n4505_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000000001: n4505_o = 1'b0; + default: n4505_o = 1'b0; + endcase + /* decoder.vhd:635:5 */ + always @* + case (n4277_o) + 63'b100000000000000000000000000000000000000000000000000000000000000: n4508_o = 1'b0; + 63'b010000000000000000000000000000000000000000000000000000000000000: n4508_o = 1'b0; + 63'b001000000000000000000000000000000000000000000000000000000000000: n4508_o = 1'b0; + 63'b000100000000000000000000000000000000000000000000000000000000000: n4508_o = 1'b0; + 63'b000010000000000000000000000000000000000000000000000000000000000: n4508_o = 1'b0; + 63'b000001000000000000000000000000000000000000000000000000000000000: n4508_o = 1'b0; + 63'b000000100000000000000000000000000000000000000000000000000000000: n4508_o = 1'b0; + 63'b000000010000000000000000000000000000000000000000000000000000000: n4508_o = 1'b0; + 63'b000000001000000000000000000000000000000000000000000000000000000: n4508_o = 1'b0; + 63'b000000000100000000000000000000000000000000000000000000000000000: n4508_o = 1'b0; + 63'b000000000010000000000000000000000000000000000000000000000000000: n4508_o = 1'b0; + 63'b000000000001000000000000000000000000000000000000000000000000000: n4508_o = 1'b0; + 63'b000000000000100000000000000000000000000000000000000000000000000: n4508_o = 1'b0; + 63'b000000000000010000000000000000000000000000000000000000000000000: n4508_o = 1'b0; + 63'b000000000000001000000000000000000000000000000000000000000000000: n4508_o = 1'b0; + 63'b000000000000000100000000000000000000000000000000000000000000000: n4508_o = 1'b0; + 63'b000000000000000010000000000000000000000000000000000000000000000: n4508_o = 1'b0; + 63'b000000000000000001000000000000000000000000000000000000000000000: n4508_o = 1'b0; + 63'b000000000000000000100000000000000000000000000000000000000000000: n4508_o = 1'b0; + 63'b000000000000000000010000000000000000000000000000000000000000000: n4508_o = n3615_o; + 63'b000000000000000000001000000000000000000000000000000000000000000: n4508_o = n3550_o; + 63'b000000000000000000000100000000000000000000000000000000000000000: n4508_o = 1'b0; + 63'b000000000000000000000010000000000000000000000000000000000000000: n4508_o = 1'b0; + 63'b000000000000000000000001000000000000000000000000000000000000000: n4508_o = 1'b0; + 63'b000000000000000000000000100000000000000000000000000000000000000: n4508_o = 1'b0; + 63'b000000000000000000000000010000000000000000000000000000000000000: n4508_o = 1'b0; + 63'b000000000000000000000000001000000000000000000000000000000000000: n4508_o = 1'b0; + 63'b000000000000000000000000000100000000000000000000000000000000000: n4508_o = 1'b0; + 63'b000000000000000000000000000010000000000000000000000000000000000: n4508_o = 1'b0; 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+ 63'b000000000000000000000000000000000000000001000000000000000000000: n4508_o = 1'b0; + 63'b000000000000000000000000000000000000000000100000000000000000000: n4508_o = 1'b0; + 63'b000000000000000000000000000000000000000000010000000000000000000: n4508_o = 1'b0; + 63'b000000000000000000000000000000000000000000001000000000000000000: n4508_o = 1'b0; + 63'b000000000000000000000000000000000000000000000100000000000000000: n4508_o = 1'b0; + 63'b000000000000000000000000000000000000000000000010000000000000000: n4508_o = 1'b0; + 63'b000000000000000000000000000000000000000000000001000000000000000: n4508_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000100000000000000: n4508_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000010000000000000: n4508_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000001000000000000: n4508_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000100000000000: n4508_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000010000000000: n4508_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000001000000000: n4508_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000100000000: n4508_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000010000000: n4508_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000001000000: n4508_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000100000: n4508_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000010000: n4508_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000001000: n4508_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000000100: n4508_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000000010: n4508_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000000001: n4508_o = 1'b0; + default: n4508_o = 1'b0; + endcase + /* decoder.vhd:635:5 */ + always @* + case (n4277_o) + 63'b100000000000000000000000000000000000000000000000000000000000000: n4511_o = 1'b0; + 63'b010000000000000000000000000000000000000000000000000000000000000: n4511_o = 1'b0; + 63'b001000000000000000000000000000000000000000000000000000000000000: n4511_o = 1'b0; + 63'b000100000000000000000000000000000000000000000000000000000000000: n4511_o = 1'b0; + 63'b000010000000000000000000000000000000000000000000000000000000000: n4511_o = 1'b0; + 63'b000001000000000000000000000000000000000000000000000000000000000: n4511_o = 1'b0; + 63'b000000100000000000000000000000000000000000000000000000000000000: n4511_o = 1'b0; + 63'b000000010000000000000000000000000000000000000000000000000000000: n4511_o = 1'b0; + 63'b000000001000000000000000000000000000000000000000000000000000000: n4511_o = 1'b0; + 63'b000000000100000000000000000000000000000000000000000000000000000: n4511_o = 1'b0; + 63'b000000000010000000000000000000000000000000000000000000000000000: n4511_o = 1'b0; + 63'b000000000001000000000000000000000000000000000000000000000000000: n4511_o = 1'b0; + 63'b000000000000100000000000000000000000000000000000000000000000000: n4511_o = 1'b0; + 63'b000000000000010000000000000000000000000000000000000000000000000: n4511_o = 1'b0; + 63'b000000000000001000000000000000000000000000000000000000000000000: n4511_o = 1'b0; + 63'b000000000000000100000000000000000000000000000000000000000000000: n4511_o = 1'b0; + 63'b000000000000000010000000000000000000000000000000000000000000000: n4511_o = 1'b0; + 63'b000000000000000001000000000000000000000000000000000000000000000: n4511_o = n3712_o; + 63'b000000000000000000100000000000000000000000000000000000000000000: n4511_o = 1'b0; + 63'b000000000000000000010000000000000000000000000000000000000000000: n4511_o = 1'b0; + 63'b000000000000000000001000000000000000000000000000000000000000000: n4511_o = 1'b0; + 63'b000000000000000000000100000000000000000000000000000000000000000: n4511_o = 1'b0; + 63'b000000000000000000000010000000000000000000000000000000000000000: n4511_o = 1'b0; + 63'b000000000000000000000001000000000000000000000000000000000000000: n4511_o = 1'b0; + 63'b000000000000000000000000100000000000000000000000000000000000000: n4511_o = 1'b0; + 63'b000000000000000000000000010000000000000000000000000000000000000: n4511_o = 1'b0; + 63'b000000000000000000000000001000000000000000000000000000000000000: n4511_o = 1'b0; + 63'b000000000000000000000000000100000000000000000000000000000000000: n4511_o = 1'b0; + 63'b000000000000000000000000000010000000000000000000000000000000000: n4511_o = 1'b0; + 63'b000000000000000000000000000001000000000000000000000000000000000: n4511_o = 1'b0; + 63'b000000000000000000000000000000100000000000000000000000000000000: n4511_o = 1'b0; + 63'b000000000000000000000000000000010000000000000000000000000000000: n4511_o = 1'b0; + 63'b000000000000000000000000000000001000000000000000000000000000000: n4511_o = 1'b0; + 63'b000000000000000000000000000000000100000000000000000000000000000: n4511_o = 1'b0; + 63'b000000000000000000000000000000000010000000000000000000000000000: n4511_o = 1'b0; + 63'b000000000000000000000000000000000001000000000000000000000000000: n4511_o = 1'b0; + 63'b000000000000000000000000000000000000100000000000000000000000000: n4511_o = 1'b0; + 63'b000000000000000000000000000000000000010000000000000000000000000: n4511_o = 1'b0; + 63'b000000000000000000000000000000000000001000000000000000000000000: n4511_o = 1'b0; + 63'b000000000000000000000000000000000000000100000000000000000000000: n4511_o = 1'b0; + 63'b000000000000000000000000000000000000000010000000000000000000000: n4511_o = 1'b0; + 63'b000000000000000000000000000000000000000001000000000000000000000: n4511_o = 1'b0; + 63'b000000000000000000000000000000000000000000100000000000000000000: n4511_o = 1'b0; + 63'b000000000000000000000000000000000000000000010000000000000000000: n4511_o = 1'b0; + 63'b000000000000000000000000000000000000000000001000000000000000000: n4511_o = 1'b0; + 63'b000000000000000000000000000000000000000000000100000000000000000: n4511_o = 1'b0; + 63'b000000000000000000000000000000000000000000000010000000000000000: n4511_o = 1'b0; + 63'b000000000000000000000000000000000000000000000001000000000000000: n4511_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000100000000000000: n4511_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000010000000000000: n4511_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000001000000000000: n4511_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000100000000000: n4511_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000010000000000: n4511_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000001000000000: n4511_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000100000000: n4511_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000010000000: n4511_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000001000000: n4511_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000100000: n4511_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000010000: n4511_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000001000: n4511_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000000100: n4511_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000000010: n4511_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000000001: n4511_o = 1'b0; + default: n4511_o = 1'b0; + endcase + /* decoder.vhd:635:5 */ + always @* + case (n4277_o) + 63'b100000000000000000000000000000000000000000000000000000000000000: n4514_o = 1'b0; + 63'b010000000000000000000000000000000000000000000000000000000000000: n4514_o = 1'b0; + 63'b001000000000000000000000000000000000000000000000000000000000000: n4514_o = 1'b0; + 63'b000100000000000000000000000000000000000000000000000000000000000: n4514_o = 1'b0; + 63'b000010000000000000000000000000000000000000000000000000000000000: n4514_o = 1'b0; + 63'b000001000000000000000000000000000000000000000000000000000000000: n4514_o = 1'b0; + 63'b000000100000000000000000000000000000000000000000000000000000000: n4514_o = 1'b0; + 63'b000000010000000000000000000000000000000000000000000000000000000: n4514_o = 1'b0; + 63'b000000001000000000000000000000000000000000000000000000000000000: n4514_o = 1'b0; + 63'b000000000100000000000000000000000000000000000000000000000000000: n4514_o = 1'b0; + 63'b000000000010000000000000000000000000000000000000000000000000000: n4514_o = 1'b0; + 63'b000000000001000000000000000000000000000000000000000000000000000: n4514_o = 1'b0; + 63'b000000000000100000000000000000000000000000000000000000000000000: n4514_o = 1'b0; + 63'b000000000000010000000000000000000000000000000000000000000000000: n4514_o = 1'b0; + 63'b000000000000001000000000000000000000000000000000000000000000000: n4514_o = 1'b0; + 63'b000000000000000100000000000000000000000000000000000000000000000: n4514_o = 1'b0; + 63'b000000000000000010000000000000000000000000000000000000000000000: n4514_o = 1'b0; + 63'b000000000000000001000000000000000000000000000000000000000000000: n4514_o = 1'b0; + 63'b000000000000000000100000000000000000000000000000000000000000000: n4514_o = 1'b0; + 63'b000000000000000000010000000000000000000000000000000000000000000: n4514_o = 1'b0; + 63'b000000000000000000001000000000000000000000000000000000000000000: n4514_o = 1'b0; + 63'b000000000000000000000100000000000000000000000000000000000000000: n4514_o = 1'b0; + 63'b000000000000000000000010000000000000000000000000000000000000000: n4514_o = 1'b0; + 63'b000000000000000000000001000000000000000000000000000000000000000: n4514_o = 1'b0; + 63'b000000000000000000000000100000000000000000000000000000000000000: n4514_o = 1'b0; + 63'b000000000000000000000000010000000000000000000000000000000000000: n4514_o = 1'b0; + 63'b000000000000000000000000001000000000000000000000000000000000000: n4514_o = 1'b0; + 63'b000000000000000000000000000100000000000000000000000000000000000: n4514_o = 1'b0; + 63'b000000000000000000000000000010000000000000000000000000000000000: n4514_o = 1'b0; + 63'b000000000000000000000000000001000000000000000000000000000000000: n4514_o = 1'b0; + 63'b000000000000000000000000000000100000000000000000000000000000000: n4514_o = n3269_o; + 63'b000000000000000000000000000000010000000000000000000000000000000: n4514_o = 1'b0; + 63'b000000000000000000000000000000001000000000000000000000000000000: n4514_o = 1'b0; + 63'b000000000000000000000000000000000100000000000000000000000000000: n4514_o = 1'b0; + 63'b000000000000000000000000000000000010000000000000000000000000000: n4514_o = 1'b0; + 63'b000000000000000000000000000000000001000000000000000000000000000: n4514_o = 1'b0; + 63'b000000000000000000000000000000000000100000000000000000000000000: n4514_o = 1'b0; + 63'b000000000000000000000000000000000000010000000000000000000000000: n4514_o = 1'b0; + 63'b000000000000000000000000000000000000001000000000000000000000000: n4514_o = 1'b0; + 63'b000000000000000000000000000000000000000100000000000000000000000: n4514_o = 1'b0; + 63'b000000000000000000000000000000000000000010000000000000000000000: n4514_o = 1'b0; + 63'b000000000000000000000000000000000000000001000000000000000000000: n4514_o = 1'b0; + 63'b000000000000000000000000000000000000000000100000000000000000000: n4514_o = 1'b0; + 63'b000000000000000000000000000000000000000000010000000000000000000: n4514_o = 1'b0; + 63'b000000000000000000000000000000000000000000001000000000000000000: n4514_o = 1'b0; + 63'b000000000000000000000000000000000000000000000100000000000000000: n4514_o = 1'b0; + 63'b000000000000000000000000000000000000000000000010000000000000000: n4514_o = 1'b0; + 63'b000000000000000000000000000000000000000000000001000000000000000: n4514_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000100000000000000: n4514_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000010000000000000: n4514_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000001000000000000: n4514_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000100000000000: n4514_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000010000000000: n4514_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000001000000000: n4514_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000100000000: n4514_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000010000000: n4514_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000001000000: n4514_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000100000: n4514_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000010000: n4514_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000001000: n4514_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000000100: n4514_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000000010: n4514_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000000001: n4514_o = 1'b0; + default: n4514_o = 1'b0; + endcase + /* decoder.vhd:635:5 */ + always @* + case (n4277_o) + 63'b100000000000000000000000000000000000000000000000000000000000000: n4517_o = 1'b0; + 63'b010000000000000000000000000000000000000000000000000000000000000: n4517_o = 1'b0; + 63'b001000000000000000000000000000000000000000000000000000000000000: n4517_o = 1'b0; + 63'b000100000000000000000000000000000000000000000000000000000000000: n4517_o = 1'b0; + 63'b000010000000000000000000000000000000000000000000000000000000000: n4517_o = 1'b0; + 63'b000001000000000000000000000000000000000000000000000000000000000: n4517_o = 1'b0; + 63'b000000100000000000000000000000000000000000000000000000000000000: n4517_o = 1'b0; + 63'b000000010000000000000000000000000000000000000000000000000000000: n4517_o = 1'b0; + 63'b000000001000000000000000000000000000000000000000000000000000000: n4517_o = 1'b0; + 63'b000000000100000000000000000000000000000000000000000000000000000: n4517_o = 1'b0; + 63'b000000000010000000000000000000000000000000000000000000000000000: n4517_o = 1'b0; + 63'b000000000001000000000000000000000000000000000000000000000000000: n4517_o = 1'b0; + 63'b000000000000100000000000000000000000000000000000000000000000000: n4517_o = 1'b0; + 63'b000000000000010000000000000000000000000000000000000000000000000: n4517_o = 1'b0; + 63'b000000000000001000000000000000000000000000000000000000000000000: n4517_o = 1'b0; + 63'b000000000000000100000000000000000000000000000000000000000000000: n4517_o = 1'b0; + 63'b000000000000000010000000000000000000000000000000000000000000000: n4517_o = 1'b0; + 63'b000000000000000001000000000000000000000000000000000000000000000: n4517_o = 1'b0; + 63'b000000000000000000100000000000000000000000000000000000000000000: n4517_o = 1'b0; + 63'b000000000000000000010000000000000000000000000000000000000000000: n4517_o = 1'b0; + 63'b000000000000000000001000000000000000000000000000000000000000000: n4517_o = 1'b0; + 63'b000000000000000000000100000000000000000000000000000000000000000: n4517_o = 1'b0; + 63'b000000000000000000000010000000000000000000000000000000000000000: n4517_o = 1'b0; + 63'b000000000000000000000001000000000000000000000000000000000000000: n4517_o = 1'b0; + 63'b000000000000000000000000100000000000000000000000000000000000000: n4517_o = 1'b0; + 63'b000000000000000000000000010000000000000000000000000000000000000: n4517_o = 1'b0; + 63'b000000000000000000000000001000000000000000000000000000000000000: n4517_o = 1'b0; + 63'b000000000000000000000000000100000000000000000000000000000000000: n4517_o = 1'b0; + 63'b000000000000000000000000000010000000000000000000000000000000000: n4517_o = 1'b0; + 63'b000000000000000000000000000001000000000000000000000000000000000: n4517_o = 1'b0; + 63'b000000000000000000000000000000100000000000000000000000000000000: n4517_o = 1'b0; + 63'b000000000000000000000000000000010000000000000000000000000000000: n4517_o = 1'b0; + 63'b000000000000000000000000000000001000000000000000000000000000000: n4517_o = 1'b0; + 63'b000000000000000000000000000000000100000000000000000000000000000: n4517_o = 1'b0; + 63'b000000000000000000000000000000000010000000000000000000000000000: n4517_o = 1'b0; + 63'b000000000000000000000000000000000001000000000000000000000000000: n4517_o = 1'b0; + 63'b000000000000000000000000000000000000100000000000000000000000000: n4517_o = 1'b0; + 63'b000000000000000000000000000000000000010000000000000000000000000: n4517_o = 1'b0; + 63'b000000000000000000000000000000000000001000000000000000000000000: n4517_o = 1'b0; + 63'b000000000000000000000000000000000000000100000000000000000000000: n4517_o = 1'b0; + 63'b000000000000000000000000000000000000000010000000000000000000000: n4517_o = 1'b0; + 63'b000000000000000000000000000000000000000001000000000000000000000: n4517_o = 1'b0; + 63'b000000000000000000000000000000000000000000100000000000000000000: n4517_o = 1'b0; + 63'b000000000000000000000000000000000000000000010000000000000000000: n4517_o = 1'b0; + 63'b000000000000000000000000000000000000000000001000000000000000000: n4517_o = 1'b0; + 63'b000000000000000000000000000000000000000000000100000000000000000: n4517_o = 1'b0; + 63'b000000000000000000000000000000000000000000000010000000000000000: n4517_o = 1'b0; + 63'b000000000000000000000000000000000000000000000001000000000000000: n4517_o = n2779_o; + 63'b000000000000000000000000000000000000000000000000100000000000000: n4517_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000010000000000000: n4517_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000001000000000000: n4517_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000100000000000: n4517_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000010000000000: n4517_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000001000000000: n4517_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000100000000: n4517_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000010000000: n4517_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000001000000: n4517_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000100000: n4517_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000010000: n4517_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000001000: n4517_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000000100: n4517_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000000010: n4517_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000000001: n4517_o = 1'b0; + default: n4517_o = 1'b0; + endcase + /* decoder.vhd:635:5 */ + always @* + case (n4277_o) + 63'b100000000000000000000000000000000000000000000000000000000000000: n4520_o = 1'b0; + 63'b010000000000000000000000000000000000000000000000000000000000000: n4520_o = 1'b0; + 63'b001000000000000000000000000000000000000000000000000000000000000: n4520_o = 1'b0; + 63'b000100000000000000000000000000000000000000000000000000000000000: n4520_o = 1'b0; + 63'b000010000000000000000000000000000000000000000000000000000000000: n4520_o = 1'b0; + 63'b000001000000000000000000000000000000000000000000000000000000000: n4520_o = 1'b0; + 63'b000000100000000000000000000000000000000000000000000000000000000: n4520_o = 1'b0; + 63'b000000010000000000000000000000000000000000000000000000000000000: n4520_o = 1'b0; + 63'b000000001000000000000000000000000000000000000000000000000000000: n4520_o = 1'b0; + 63'b000000000100000000000000000000000000000000000000000000000000000: n4520_o = 1'b0; + 63'b000000000010000000000000000000000000000000000000000000000000000: n4520_o = 1'b0; + 63'b000000000001000000000000000000000000000000000000000000000000000: n4520_o = 1'b0; + 63'b000000000000100000000000000000000000000000000000000000000000000: n4520_o = 1'b0; + 63'b000000000000010000000000000000000000000000000000000000000000000: n4520_o = 1'b0; + 63'b000000000000001000000000000000000000000000000000000000000000000: n4520_o = 1'b0; + 63'b000000000000000100000000000000000000000000000000000000000000000: n4520_o = 1'b0; + 63'b000000000000000010000000000000000000000000000000000000000000000: n4520_o = 1'b0; + 63'b000000000000000001000000000000000000000000000000000000000000000: n4520_o = 1'b0; + 63'b000000000000000000100000000000000000000000000000000000000000000: n4520_o = 1'b0; + 63'b000000000000000000010000000000000000000000000000000000000000000: n4520_o = 1'b0; + 63'b000000000000000000001000000000000000000000000000000000000000000: n4520_o = 1'b0; + 63'b000000000000000000000100000000000000000000000000000000000000000: n4520_o = 1'b0; + 63'b000000000000000000000010000000000000000000000000000000000000000: n4520_o = 1'b0; + 63'b000000000000000000000001000000000000000000000000000000000000000: n4520_o = 1'b0; + 63'b000000000000000000000000100000000000000000000000000000000000000: n4520_o = 1'b0; + 63'b000000000000000000000000010000000000000000000000000000000000000: n4520_o = 1'b0; + 63'b000000000000000000000000001000000000000000000000000000000000000: n4520_o = 1'b0; + 63'b000000000000000000000000000100000000000000000000000000000000000: n4520_o = 1'b0; + 63'b000000000000000000000000000010000000000000000000000000000000000: n4520_o = 1'b0; + 63'b000000000000000000000000000001000000000000000000000000000000000: n4520_o = 1'b0; + 63'b000000000000000000000000000000100000000000000000000000000000000: n4520_o = 1'b0; + 63'b000000000000000000000000000000010000000000000000000000000000000: n4520_o = 1'b0; + 63'b000000000000000000000000000000001000000000000000000000000000000: n4520_o = 1'b0; + 63'b000000000000000000000000000000000100000000000000000000000000000: n4520_o = 1'b0; + 63'b000000000000000000000000000000000010000000000000000000000000000: n4520_o = 1'b0; + 63'b000000000000000000000000000000000001000000000000000000000000000: n4520_o = 1'b0; + 63'b000000000000000000000000000000000000100000000000000000000000000: n4520_o = 1'b0; + 63'b000000000000000000000000000000000000010000000000000000000000000: n4520_o = 1'b0; + 63'b000000000000000000000000000000000000001000000000000000000000000: n4520_o = 1'b0; + 63'b000000000000000000000000000000000000000100000000000000000000000: n4520_o = 1'b0; + 63'b000000000000000000000000000000000000000010000000000000000000000: n4520_o = 1'b0; + 63'b000000000000000000000000000000000000000001000000000000000000000: n4520_o = 1'b0; + 63'b000000000000000000000000000000000000000000100000000000000000000: n4520_o = 1'b0; + 63'b000000000000000000000000000000000000000000010000000000000000000: n4520_o = 1'b0; + 63'b000000000000000000000000000000000000000000001000000000000000000: n4520_o = 1'b0; + 63'b000000000000000000000000000000000000000000000100000000000000000: n4520_o = 1'b0; + 63'b000000000000000000000000000000000000000000000010000000000000000: n4520_o = 1'b0; + 63'b000000000000000000000000000000000000000000000001000000000000000: n4520_o = n2781_o; + 63'b000000000000000000000000000000000000000000000000100000000000000: n4520_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000010000000000000: n4520_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000001000000000000: n4520_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000100000000000: n4520_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000010000000000: n4520_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000001000000000: n4520_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000100000000: n4520_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000010000000: n4520_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000001000000: n4520_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000100000: n4520_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000010000: n4520_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000001000: n4520_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000000100: n4520_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000000010: n4520_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000000001: n4520_o = 1'b0; + default: n4520_o = 1'b0; + endcase + /* decoder.vhd:635:5 */ + always @* + case (n4277_o) + 63'b100000000000000000000000000000000000000000000000000000000000000: n4523_o = 1'b0; + 63'b010000000000000000000000000000000000000000000000000000000000000: n4523_o = 1'b0; + 63'b001000000000000000000000000000000000000000000000000000000000000: n4523_o = 1'b0; + 63'b000100000000000000000000000000000000000000000000000000000000000: n4523_o = 1'b0; + 63'b000010000000000000000000000000000000000000000000000000000000000: n4523_o = 1'b0; + 63'b000001000000000000000000000000000000000000000000000000000000000: n4523_o = 1'b0; + 63'b000000100000000000000000000000000000000000000000000000000000000: n4523_o = 1'b0; + 63'b000000010000000000000000000000000000000000000000000000000000000: n4523_o = 1'b0; + 63'b000000001000000000000000000000000000000000000000000000000000000: n4523_o = 1'b0; + 63'b000000000100000000000000000000000000000000000000000000000000000: n4523_o = 1'b0; + 63'b000000000010000000000000000000000000000000000000000000000000000: n4523_o = 1'b0; + 63'b000000000001000000000000000000000000000000000000000000000000000: n4523_o = 1'b0; + 63'b000000000000100000000000000000000000000000000000000000000000000: n4523_o = 1'b0; + 63'b000000000000010000000000000000000000000000000000000000000000000: n4523_o = 1'b0; + 63'b000000000000001000000000000000000000000000000000000000000000000: n4523_o = 1'b0; + 63'b000000000000000100000000000000000000000000000000000000000000000: n4523_o = 1'b0; + 63'b000000000000000010000000000000000000000000000000000000000000000: n4523_o = 1'b0; + 63'b000000000000000001000000000000000000000000000000000000000000000: n4523_o = 1'b0; + 63'b000000000000000000100000000000000000000000000000000000000000000: n4523_o = 1'b0; + 63'b000000000000000000010000000000000000000000000000000000000000000: n4523_o = 1'b0; + 63'b000000000000000000001000000000000000000000000000000000000000000: n4523_o = 1'b0; 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+ 63'b000000000000000000000000000000000000000000000100000000000000000: n4523_o = 1'b0; + 63'b000000000000000000000000000000000000000000000010000000000000000: n4523_o = 1'b0; + 63'b000000000000000000000000000000000000000000000001000000000000000: n4523_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000100000000000000: n4523_o = n2764_o; + 63'b000000000000000000000000000000000000000000000000010000000000000: n4523_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000001000000000000: n4523_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000100000000000: n4523_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000010000000000: n4523_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000001000000000: n4523_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000100000000: n4523_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000010000000: n4523_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000001000000: n4523_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000100000: n4523_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000010000: n4523_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000001000: n4523_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000000100: n4523_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000000010: n4523_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000000001: n4523_o = 1'b0; + default: n4523_o = 1'b0; + endcase + /* decoder.vhd:635:5 */ + always @* + case (n4277_o) + 63'b100000000000000000000000000000000000000000000000000000000000000: n4526_o = 1'b0; + 63'b010000000000000000000000000000000000000000000000000000000000000: n4526_o = 1'b0; + 63'b001000000000000000000000000000000000000000000000000000000000000: n4526_o = 1'b0; + 63'b000100000000000000000000000000000000000000000000000000000000000: n4526_o = 1'b0; + 63'b000010000000000000000000000000000000000000000000000000000000000: n4526_o = 1'b0; + 63'b000001000000000000000000000000000000000000000000000000000000000: n4526_o = 1'b0; + 63'b000000100000000000000000000000000000000000000000000000000000000: n4526_o = 1'b0; + 63'b000000010000000000000000000000000000000000000000000000000000000: n4526_o = 1'b0; + 63'b000000001000000000000000000000000000000000000000000000000000000: n4526_o = 1'b0; + 63'b000000000100000000000000000000000000000000000000000000000000000: n4526_o = 1'b0; + 63'b000000000010000000000000000000000000000000000000000000000000000: n4526_o = 1'b0; + 63'b000000000001000000000000000000000000000000000000000000000000000: n4526_o = 1'b0; + 63'b000000000000100000000000000000000000000000000000000000000000000: n4526_o = 1'b0; + 63'b000000000000010000000000000000000000000000000000000000000000000: n4526_o = 1'b0; + 63'b000000000000001000000000000000000000000000000000000000000000000: n4526_o = 1'b0; + 63'b000000000000000100000000000000000000000000000000000000000000000: n4526_o = 1'b0; + 63'b000000000000000010000000000000000000000000000000000000000000000: n4526_o = 1'b0; + 63'b000000000000000001000000000000000000000000000000000000000000000: n4526_o = 1'b0; + 63'b000000000000000000100000000000000000000000000000000000000000000: n4526_o = 1'b0; + 63'b000000000000000000010000000000000000000000000000000000000000000: n4526_o = 1'b0; + 63'b000000000000000000001000000000000000000000000000000000000000000: n4526_o = 1'b0; + 63'b000000000000000000000100000000000000000000000000000000000000000: n4526_o = 1'b0; + 63'b000000000000000000000010000000000000000000000000000000000000000: n4526_o = 1'b0; + 63'b000000000000000000000001000000000000000000000000000000000000000: n4526_o = 1'b0; + 63'b000000000000000000000000100000000000000000000000000000000000000: n4526_o = 1'b0; + 63'b000000000000000000000000010000000000000000000000000000000000000: n4526_o = 1'b0; + 63'b000000000000000000000000001000000000000000000000000000000000000: n4526_o = 1'b0; + 63'b000000000000000000000000000100000000000000000000000000000000000: n4526_o = 1'b0; + 63'b000000000000000000000000000010000000000000000000000000000000000: n4526_o = 1'b0; + 63'b000000000000000000000000000001000000000000000000000000000000000: n4526_o = 1'b0; + 63'b000000000000000000000000000000100000000000000000000000000000000: n4526_o = 1'b0; + 63'b000000000000000000000000000000010000000000000000000000000000000: n4526_o = 1'b0; + 63'b000000000000000000000000000000001000000000000000000000000000000: n4526_o = 1'b0; + 63'b000000000000000000000000000000000100000000000000000000000000000: n4526_o = 1'b0; + 63'b000000000000000000000000000000000010000000000000000000000000000: n4526_o = 1'b0; + 63'b000000000000000000000000000000000001000000000000000000000000000: n4526_o = 1'b0; + 63'b000000000000000000000000000000000000100000000000000000000000000: n4526_o = 1'b0; + 63'b000000000000000000000000000000000000010000000000000000000000000: n4526_o = 1'b0; + 63'b000000000000000000000000000000000000001000000000000000000000000: n4526_o = 1'b0; + 63'b000000000000000000000000000000000000000100000000000000000000000: n4526_o = 1'b0; + 63'b000000000000000000000000000000000000000010000000000000000000000: n4526_o = 1'b0; + 63'b000000000000000000000000000000000000000001000000000000000000000: n4526_o = 1'b0; + 63'b000000000000000000000000000000000000000000100000000000000000000: n4526_o = 1'b0; + 63'b000000000000000000000000000000000000000000010000000000000000000: n4526_o = 1'b0; + 63'b000000000000000000000000000000000000000000001000000000000000000: n4526_o = 1'b0; + 63'b000000000000000000000000000000000000000000000100000000000000000: n4526_o = 1'b0; + 63'b000000000000000000000000000000000000000000000010000000000000000: n4526_o = 1'b0; + 63'b000000000000000000000000000000000000000000000001000000000000000: n4526_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000100000000000000: n4526_o = n2766_o; + 63'b000000000000000000000000000000000000000000000000010000000000000: n4526_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000001000000000000: n4526_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000100000000000: n4526_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000010000000000: n4526_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000001000000000: n4526_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000100000000: n4526_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000010000000: n4526_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000001000000: n4526_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000100000: n4526_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000010000: n4526_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000001000: n4526_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000000100: n4526_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000000010: n4526_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000000001: n4526_o = 1'b0; + default: n4526_o = 1'b0; + endcase + /* decoder.vhd:635:5 */ + always @* + case (n4277_o) + 63'b100000000000000000000000000000000000000000000000000000000000000: n4529_o = 1'b0; + 63'b010000000000000000000000000000000000000000000000000000000000000: n4529_o = 1'b0; + 63'b001000000000000000000000000000000000000000000000000000000000000: n4529_o = 1'b0; + 63'b000100000000000000000000000000000000000000000000000000000000000: n4529_o = 1'b0; + 63'b000010000000000000000000000000000000000000000000000000000000000: n4529_o = 1'b0; + 63'b000001000000000000000000000000000000000000000000000000000000000: n4529_o = 1'b0; + 63'b000000100000000000000000000000000000000000000000000000000000000: n4529_o = 1'b0; + 63'b000000010000000000000000000000000000000000000000000000000000000: n4529_o = 1'b0; + 63'b000000001000000000000000000000000000000000000000000000000000000: n4529_o = 1'b0; + 63'b000000000100000000000000000000000000000000000000000000000000000: n4529_o = 1'b0; + 63'b000000000010000000000000000000000000000000000000000000000000000: n4529_o = n4024_o; + 63'b000000000001000000000000000000000000000000000000000000000000000: n4529_o = 1'b0; + 63'b000000000000100000000000000000000000000000000000000000000000000: n4529_o = 1'b0; + 63'b000000000000010000000000000000000000000000000000000000000000000: n4529_o = 1'b0; + 63'b000000000000001000000000000000000000000000000000000000000000000: n4529_o = 1'b0; + 63'b000000000000000100000000000000000000000000000000000000000000000: n4529_o = 1'b0; + 63'b000000000000000010000000000000000000000000000000000000000000000: n4529_o = 1'b0; + 63'b000000000000000001000000000000000000000000000000000000000000000: n4529_o = 1'b0; + 63'b000000000000000000100000000000000000000000000000000000000000000: n4529_o = 1'b0; + 63'b000000000000000000010000000000000000000000000000000000000000000: n4529_o = 1'b0; + 63'b000000000000000000001000000000000000000000000000000000000000000: n4529_o = 1'b0; + 63'b000000000000000000000100000000000000000000000000000000000000000: n4529_o = 1'b0; + 63'b000000000000000000000010000000000000000000000000000000000000000: n4529_o = 1'b0; + 63'b000000000000000000000001000000000000000000000000000000000000000: n4529_o = 1'b0; + 63'b000000000000000000000000100000000000000000000000000000000000000: n4529_o = 1'b0; + 63'b000000000000000000000000010000000000000000000000000000000000000: n4529_o = 1'b0; + 63'b000000000000000000000000001000000000000000000000000000000000000: n4529_o = 1'b0; + 63'b000000000000000000000000000100000000000000000000000000000000000: n4529_o = 1'b0; + 63'b000000000000000000000000000010000000000000000000000000000000000: n4529_o = 1'b0; + 63'b000000000000000000000000000001000000000000000000000000000000000: n4529_o = 1'b0; + 63'b000000000000000000000000000000100000000000000000000000000000000: n4529_o = 1'b0; + 63'b000000000000000000000000000000010000000000000000000000000000000: n4529_o = 1'b0; + 63'b000000000000000000000000000000001000000000000000000000000000000: n4529_o = 1'b0; + 63'b000000000000000000000000000000000100000000000000000000000000000: n4529_o = 1'b0; + 63'b000000000000000000000000000000000010000000000000000000000000000: n4529_o = 1'b0; + 63'b000000000000000000000000000000000001000000000000000000000000000: n4529_o = 1'b0; + 63'b000000000000000000000000000000000000100000000000000000000000000: n4529_o = 1'b0; + 63'b000000000000000000000000000000000000010000000000000000000000000: n4529_o = 1'b0; + 63'b000000000000000000000000000000000000001000000000000000000000000: n4529_o = 1'b0; + 63'b000000000000000000000000000000000000000100000000000000000000000: n4529_o = 1'b0; + 63'b000000000000000000000000000000000000000010000000000000000000000: n4529_o = 1'b0; + 63'b000000000000000000000000000000000000000001000000000000000000000: n4529_o = 1'b0; + 63'b000000000000000000000000000000000000000000100000000000000000000: n4529_o = 1'b0; + 63'b000000000000000000000000000000000000000000010000000000000000000: n4529_o = 1'b0; + 63'b000000000000000000000000000000000000000000001000000000000000000: n4529_o = 1'b0; + 63'b000000000000000000000000000000000000000000000100000000000000000: n4529_o = 1'b0; + 63'b000000000000000000000000000000000000000000000010000000000000000: n4529_o = 1'b0; + 63'b000000000000000000000000000000000000000000000001000000000000000: n4529_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000100000000000000: n4529_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000010000000000000: n4529_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000001000000000000: n4529_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000100000000000: n4529_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000010000000000: n4529_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000001000000000: n4529_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000100000000: n4529_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000010000000: n4529_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000001000000: n4529_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000100000: n4529_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000010000: n4529_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000001000: n4529_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000000100: n4529_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000000010: n4529_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000000001: n4529_o = 1'b0; + default: n4529_o = 1'b0; + endcase + /* decoder.vhd:635:5 */ + always @* + case (n4277_o) + 63'b100000000000000000000000000000000000000000000000000000000000000: n4532_o = 1'b0; + 63'b010000000000000000000000000000000000000000000000000000000000000: n4532_o = 1'b0; + 63'b001000000000000000000000000000000000000000000000000000000000000: n4532_o = 1'b0; + 63'b000100000000000000000000000000000000000000000000000000000000000: n4532_o = 1'b0; + 63'b000010000000000000000000000000000000000000000000000000000000000: n4532_o = 1'b0; + 63'b000001000000000000000000000000000000000000000000000000000000000: n4532_o = 1'b0; + 63'b000000100000000000000000000000000000000000000000000000000000000: n4532_o = 1'b0; + 63'b000000010000000000000000000000000000000000000000000000000000000: n4532_o = 1'b0; + 63'b000000001000000000000000000000000000000000000000000000000000000: n4532_o = 1'b0; + 63'b000000000100000000000000000000000000000000000000000000000000000: n4532_o = 1'b0; + 63'b000000000010000000000000000000000000000000000000000000000000000: n4532_o = 1'b0; + 63'b000000000001000000000000000000000000000000000000000000000000000: n4532_o = 1'b0; + 63'b000000000000100000000000000000000000000000000000000000000000000: n4532_o = 1'b0; + 63'b000000000000010000000000000000000000000000000000000000000000000: n4532_o = 1'b0; + 63'b000000000000001000000000000000000000000000000000000000000000000: n4532_o = 1'b0; + 63'b000000000000000100000000000000000000000000000000000000000000000: n4532_o = 1'b0; + 63'b000000000000000010000000000000000000000000000000000000000000000: n4532_o = 1'b0; + 63'b000000000000000001000000000000000000000000000000000000000000000: n4532_o = 1'b0; + 63'b000000000000000000100000000000000000000000000000000000000000000: n4532_o = 1'b0; + 63'b000000000000000000010000000000000000000000000000000000000000000: n4532_o = 1'b0; + 63'b000000000000000000001000000000000000000000000000000000000000000: n4532_o = 1'b0; + 63'b000000000000000000000100000000000000000000000000000000000000000: n4532_o = 1'b0; + 63'b000000000000000000000010000000000000000000000000000000000000000: n4532_o = 1'b0; + 63'b000000000000000000000001000000000000000000000000000000000000000: n4532_o = 1'b0; + 63'b000000000000000000000000100000000000000000000000000000000000000: n4532_o = 1'b0; + 63'b000000000000000000000000010000000000000000000000000000000000000: n4532_o = 1'b0; + 63'b000000000000000000000000001000000000000000000000000000000000000: n4532_o = 1'b0; + 63'b000000000000000000000000000100000000000000000000000000000000000: n4532_o = 1'b0; + 63'b000000000000000000000000000010000000000000000000000000000000000: n4532_o = 1'b0; + 63'b000000000000000000000000000001000000000000000000000000000000000: n4532_o = 1'b0; + 63'b000000000000000000000000000000100000000000000000000000000000000: n4532_o = 1'b0; + 63'b000000000000000000000000000000010000000000000000000000000000000: n4532_o = 1'b0; + 63'b000000000000000000000000000000001000000000000000000000000000000: n4532_o = 1'b0; + 63'b000000000000000000000000000000000100000000000000000000000000000: n4532_o = 1'b0; + 63'b000000000000000000000000000000000010000000000000000000000000000: n4532_o = 1'b0; + 63'b000000000000000000000000000000000001000000000000000000000000000: n4532_o = 1'b0; + 63'b000000000000000000000000000000000000100000000000000000000000000: n4532_o = 1'b0; + 63'b000000000000000000000000000000000000010000000000000000000000000: n4532_o = 1'b0; + 63'b000000000000000000000000000000000000001000000000000000000000000: n4532_o = 1'b0; + 63'b000000000000000000000000000000000000000100000000000000000000000: n4532_o = 1'b0; + 63'b000000000000000000000000000000000000000010000000000000000000000: n4532_o = 1'b0; + 63'b000000000000000000000000000000000000000001000000000000000000000: n4532_o = 1'b0; + 63'b000000000000000000000000000000000000000000100000000000000000000: n4532_o = 1'b0; + 63'b000000000000000000000000000000000000000000010000000000000000000: n4532_o = 1'b0; + 63'b000000000000000000000000000000000000000000001000000000000000000: n4532_o = 1'b0; + 63'b000000000000000000000000000000000000000000000100000000000000000: n4532_o = 1'b0; + 63'b000000000000000000000000000000000000000000000010000000000000000: n4532_o = 1'b0; + 63'b000000000000000000000000000000000000000000000001000000000000000: n4532_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000100000000000000: n4532_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000010000000000000: n4532_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000001000000000000: n4532_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000100000000000: n4532_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000010000000000: n4532_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000001000000000: n4532_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000100000000: n4532_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000010000000: n4532_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000001000000: n4532_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000100000: n4532_o = n2589_o; + 63'b000000000000000000000000000000000000000000000000000000000010000: n4532_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000001000: n4532_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000000100: n4532_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000000010: n4532_o = 1'b0; + 63'b000000000000000000000000000000000000000000000000000000000000001: n4532_o = 1'b0; + default: n4532_o = 1'b0; + endcase + /* decoder.vhd:2020:14 */ + assign n4536_o = ~res_i; + /* decoder.vhd:2035:7 */ + assign n4539_o = bus_clear_f1_i ? 1'b0 : f1_q; + /* decoder.vhd:2033:7 */ + assign n4541_o = bus_set_f1_i ? 1'b1 : n4539_o; + /* decoder.vhd:2044:28 */ + assign n4543_o = clk_mstate_i == 3'b100; + /* decoder.vhd:2044:9 */ + assign n4545_o = n4543_o ? 1'b0 : branch_taken_q; + /* decoder.vhd:2042:9 */ + assign n4547_o = branch_taken_s ? 1'b1 : n4545_o; + /* decoder.vhd:2053:27 */ + assign n4548_o = ~f1_q; + /* decoder.vhd:2052:9 */ + assign n4549_o = cpl_f1_s ? n4548_o : n4541_o; + /* decoder.vhd:2050:9 */ + assign n4551_o = clear_f1_s ? 1'b0 : n4549_o; + /* decoder.vhd:2059:9 */ + assign n4553_o = set_mb_s ? 1'b1 : mb_q; + /* decoder.vhd:2057:9 */ + assign n4555_o = clear_mb_s ? 1'b0 : n4553_o; + /* decoder.vhd:2039:7 */ + assign n4559_o = en_clk_i ? n4551_o : n4541_o; + /* decoder.vhd:2039:7 */ + assign n4561_o = en_clk_i & ent0_clk_s; + /* decoder.vhd:2115:27 */ + assign n4575_o = read_dec_s ? data_s : 8'b11111111; + /* decoder.vhd:2117:48 */ + assign n4577_o = dm_write_dmem_s & en_clk_i; + /* decoder.vhd:2118:48 */ + assign n4578_o = pm_inc_pc_s | add_inc_pc_s; + /* decoder.vhd:2119:48 */ + assign n4579_o = pm_write_pmem_addr_s | add_write_pmem_addr_s; + /* decoder.vhd:2121:48 */ + assign n4580_o = bus_read_bus_s | add_read_bus_s; + /* decoder.vhd:305:5 */ + assign n4581_o = en_clk_i ? n1995_o : opc_opcode_q; + /* decoder.vhd:305:5 */ + always @(posedge clk_i or posedge n1989_o) + if (n1989_o) + n4582_q <= 8'b00000000; + else + n4582_q <= n4581_o; + /* decoder.vhd:2031:5 */ + assign n4583_o = en_clk_i ? n4547_o : branch_taken_q; + /* decoder.vhd:2031:5 */ + always @(posedge clk_i or posedge n4536_o) + if (n4536_o) + n4584_q <= 1'b0; + else + n4584_q <= n4583_o; + /* decoder.vhd:2031:5 */ + always @(posedge clk_i or posedge n4536_o) + if (n4536_o) + n4585_q <= 1'b0; + else + n4585_q <= n4559_o; + /* decoder.vhd:2031:5 */ + assign n4586_o = en_clk_i ? n4555_o : mb_q; + /* decoder.vhd:2031:5 */ + always @(posedge clk_i or posedge n4536_o) + if (n4536_o) + n4587_q <= 1'b0; + else + n4587_q <= n4586_o; + /* decoder.vhd:2031:5 */ + assign n4588_o = n4561_o ? 1'b1 : t0_dir_q; + /* decoder.vhd:2031:5 */ + always @(posedge clk_i or posedge n4536_o) + if (n4536_o) + n4589_q <= 1'b0; + else + n4589_q <= n4588_o; + /* decoder.vhd:305:5 */ + assign n4590_o = en_clk_i ? n1996_o : mnemonic_q; + /* decoder.vhd:305:5 */ + always @(posedge clk_i or posedge n1989_o) + if (n1989_o) + n4591_q <= 6'b101001; + else + n4591_q <= n4590_o; + /* decoder.vhd:301:5 */ + assign n4592_o = {n4401_o, n4400_o}; +endmodule + +module upi41_db_bus_1 + (input clk_i, + input res_i, + input en_clk_i, + input [7:0] data_i, + input write_bus_i, + input read_bus_i, + input write_sts_i, + input f0_i, + input f1_i, + input ibf_int_i, + input en_dma_i, + input en_flags_i, + input write_p2_i, + input dack_n_i, + input a0_i, + input cs_n_i, + input rd_n_i, + input wr_n_i, + input [7:0] db_i, + output [7:0] data_o, + output set_f1_o, + output clear_f1_o, + output ibf_o, + output obf_o, + output int_n_o, + output mint_ibf_n_o, + output mint_obf_o, + output dma_o, + output drq_o, + output [7:0] db_o, + output db_dir_o); + wire read_s; + wire read_q; + wire read_hold_q; + wire write_s; + wire write_q; + wire read_pulse_s; + wire write_pulse_s; + wire a0_q; + wire ibf_q; + wire obf_q; + wire [7:0] dbbin_q; + wire [7:0] dbbout_q; + wire [3:0] sts_q; + wire dma_q; + wire flags_q; + wire ext_acc_s; + wire dack_s; + wire n1002_o; + wire n1003_o; + wire n1004_o; + wire n1005_o; + wire n1006_o; + wire n1007_o; + wire n1008_o; + wire n1009_o; + wire n1011_o; + wire n1014_o; + wire n1016_o; + wire n1017_o; + wire n1018_o; + wire n1020_o; + wire n1034_o; + wire n1035_o; + wire n1036_o; + wire n1037_o; + wire n1039_o; + wire n1041_o; + wire n1042_o; + wire n1044_o; + wire n1046_o; + wire [7:0] n1047_o; + wire n1048_o; + wire n1049_o; + wire n1051_o; + wire [7:0] n1052_o; + wire n1053_o; + wire n1054_o; + wire n1056_o; + wire [3:0] n1057_o; + wire [3:0] n1058_o; + wire n1060_o; + wire [3:0] n1061_o; + wire n1062_o; + wire n1064_o; + wire [3:0] n1066_o; + wire n1068_o; + wire n1070_o; + wire n1075_o; + wire n1076_o; + wire n1077_o; + wire n1079_o; + wire n1080_o; + wire n1081_o; + wire n1082_o; + wire n1083_o; + wire n1084_o; + wire n1086_o; + wire n1087_o; + wire n1116_o; + wire n1117_o; + wire n1118_o; + wire n1119_o; + wire [7:0] n1120_o; + wire [4:0] n1121_o; + wire [5:0] n1122_o; + wire [6:0] n1123_o; + wire [7:0] n1124_o; + wire [7:0] n1126_o; + wire [4:0] n1128_o; + wire [5:0] n1129_o; + wire [6:0] n1130_o; + wire [7:0] n1131_o; + wire n1133_o; + wire n1134_o; + wire [7:0] n1136_o; + wire n1139_o; + wire n1140_o; + wire n1143_o; + wire n1144_o; + wire n1145_o; + reg n1147_q; + reg n1148_q; + reg n1149_q; + reg n1150_q; + reg n1151_q; + reg n1152_q; + reg [7:0] n1153_q; + wire [7:0] n1154_o; + reg [7:0] n1155_q; + wire [3:0] n1156_o; + reg [3:0] n1157_q; + wire n1158_o; + reg n1159_q; + wire n1160_o; + reg n1161_q; + reg n1162_q; + reg n1163_q; + assign data_o = n1136_o; + assign set_f1_o = n1116_o; + assign clear_f1_o = n1118_o; + assign ibf_o = ibf_q; + assign obf_o = obf_q; + assign int_n_o = n1162_q; + assign mint_ibf_n_o = n1140_o; + assign mint_obf_o = n1145_o; + assign dma_o = dma_q; + assign drq_o = n1163_q; + assign db_o = n1120_o; + assign db_dir_o = n1134_o; + /* upi41_db_bus.vhd:103:10 */ + assign read_s = n1007_o; // (signal) + /* upi41_db_bus.vhd:103:18 */ + assign read_q = n1147_q; // (signal) + /* upi41_db_bus.vhd:104:10 */ + assign read_hold_q = n1148_q; // (signal) + /* upi41_db_bus.vhd:105:10 */ + assign write_s = n1009_o; // (signal) + /* upi41_db_bus.vhd:105:19 */ + assign write_q = n1149_q; // (signal) + /* upi41_db_bus.vhd:106:10 */ + assign read_pulse_s = n1035_o; // (signal) + /* upi41_db_bus.vhd:106:24 */ + assign write_pulse_s = n1037_o; // (signal) + /* upi41_db_bus.vhd:108:10 */ + assign a0_q = n1150_q; // (signal) + /* upi41_db_bus.vhd:110:10 */ + assign ibf_q = n1151_q; // (signal) + /* upi41_db_bus.vhd:110:17 */ + assign obf_q = n1152_q; // (signal) + /* upi41_db_bus.vhd:113:10 */ + assign dbbin_q = n1153_q; // (signal) + /* upi41_db_bus.vhd:114:10 */ + assign dbbout_q = n1155_q; // (signal) + /* upi41_db_bus.vhd:116:10 */ + assign sts_q = n1157_q; // (signal) + /* upi41_db_bus.vhd:118:10 */ + assign dma_q = n1159_q; // (signal) + /* upi41_db_bus.vhd:119:10 */ + assign flags_q = n1161_q; // (signal) + /* upi41_db_bus.vhd:121:10 */ + assign ext_acc_s = n1005_o; // (signal) + /* upi41_db_bus.vhd:122:10 */ + assign dack_s = n1003_o; // (signal) + /* upi41_db_bus.vhd:142:25 */ + assign n1002_o = ~dack_n_i; + /* upi41_db_bus.vhd:142:31 */ + assign n1003_o = n1002_o & dma_q; + /* upi41_db_bus.vhd:143:23 */ + assign n1004_o = ~cs_n_i; + /* upi41_db_bus.vhd:143:29 */ + assign n1005_o = n1004_o | dack_s; + /* upi41_db_bus.vhd:144:37 */ + assign n1006_o = ~rd_n_i; + /* upi41_db_bus.vhd:144:26 */ + assign n1007_o = ext_acc_s & n1006_o; + /* upi41_db_bus.vhd:145:37 */ + assign n1008_o = ~wr_n_i; + /* upi41_db_bus.vhd:145:26 */ + assign n1009_o = ext_acc_s & n1008_o; + /* upi41_db_bus.vhd:149:14 */ + assign n1011_o = ~res_i; + /* upi41_db_bus.vhd:161:7 */ + assign n1014_o = ext_acc_s ? 1'b0 : read_hold_q; + /* upi41_db_bus.vhd:159:7 */ + assign n1016_o = read_s ? 1'b1 : n1014_o; + /* upi41_db_bus.vhd:167:20 */ + assign n1017_o = read_s | write_s; + /* upi41_db_bus.vhd:167:7 */ + assign n1018_o = n1017_o ? a0_i : a0_q; + /* upi41_db_bus.vhd:165:7 */ + assign n1020_o = dack_s ? 1'b0 : n1018_o; + /* upi41_db_bus.vhd:174:31 */ + assign n1034_o = ~read_s; + /* upi41_db_bus.vhd:174:27 */ + assign n1035_o = read_q & n1034_o; + /* upi41_db_bus.vhd:175:32 */ + assign n1036_o = ~write_s; + /* upi41_db_bus.vhd:175:28 */ + assign n1037_o = write_q & n1036_o; + /* upi41_db_bus.vhd:185:14 */ + assign n1039_o = ~res_i; + /* upi41_db_bus.vhd:198:32 */ + assign n1041_o = ~a0_q; + /* upi41_db_bus.vhd:198:23 */ + assign n1042_o = read_pulse_s & n1041_o; + /* upi41_db_bus.vhd:200:7 */ + assign n1044_o = write_pulse_s ? 1'b0 : n1162_q; + /* upi41_db_bus.vhd:200:7 */ + assign n1046_o = write_pulse_s ? 1'b1 : ibf_q; + /* upi41_db_bus.vhd:200:7 */ + assign n1047_o = write_pulse_s ? db_i : dbbin_q; + /* upi41_db_bus.vhd:198:7 */ + assign n1048_o = n1042_o ? n1162_q : n1044_o; + /* upi41_db_bus.vhd:198:7 */ + assign n1049_o = n1042_o ? ibf_q : n1046_o; + /* upi41_db_bus.vhd:198:7 */ + assign n1051_o = n1042_o ? 1'b0 : obf_q; + /* upi41_db_bus.vhd:198:7 */ + assign n1052_o = n1042_o ? dbbin_q : n1047_o; + /* upi41_db_bus.vhd:206:29 */ + assign n1053_o = read_s | write_s; + /* upi41_db_bus.vhd:206:17 */ + assign n1054_o = dack_s & n1053_o; + /* upi41_db_bus.vhd:206:7 */ + assign n1056_o = n1054_o ? 1'b0 : n1163_q; + /* upi41_db_bus.vhd:217:29 */ + assign n1057_o = data_i[7:4]; + /* upi41_db_bus.vhd:216:9 */ + assign n1058_o = write_sts_i ? n1057_o : sts_q; + /* upi41_db_bus.vhd:214:9 */ + assign n1060_o = read_bus_i ? 1'b0 : n1049_o; + /* upi41_db_bus.vhd:214:9 */ + assign n1061_o = read_bus_i ? sts_q : n1058_o; + /* upi41_db_bus.vhd:211:9 */ + assign n1062_o = write_bus_i ? n1049_o : n1060_o; + /* upi41_db_bus.vhd:210:7 */ + assign n1064_o = n1083_o ? 1'b1 : n1051_o; + /* upi41_db_bus.vhd:211:9 */ + assign n1066_o = write_bus_i ? sts_q : n1061_o; + /* upi41_db_bus.vhd:210:7 */ + assign n1068_o = n1080_o ? 1'b1 : n1048_o; + /* upi41_db_bus.vhd:225:11 */ + assign n1070_o = en_dma_i ? 1'b0 : n1056_o; + /* upi41_db_bus.vhd:233:20 */ + assign n1075_o = dma_q & write_p2_i; + /* upi41_db_bus.vhd:233:45 */ + assign n1076_o = data_i[6]; + /* upi41_db_bus.vhd:233:35 */ + assign n1077_o = n1075_o & n1076_o; + /* upi41_db_bus.vhd:233:11 */ + assign n1079_o = n1077_o ? 1'b1 : n1070_o; + /* upi41_db_bus.vhd:210:7 */ + assign n1080_o = en_clk_i & ibf_int_i; + /* upi41_db_bus.vhd:210:7 */ + assign n1081_o = en_clk_i ? n1079_o : n1056_o; + /* upi41_db_bus.vhd:210:7 */ + assign n1082_o = en_clk_i ? n1062_o : n1049_o; + /* upi41_db_bus.vhd:210:7 */ + assign n1083_o = en_clk_i & write_bus_i; + /* upi41_db_bus.vhd:210:7 */ + assign n1084_o = en_clk_i & write_bus_i; + /* upi41_db_bus.vhd:210:7 */ + assign n1086_o = en_clk_i & en_dma_i; + /* upi41_db_bus.vhd:210:7 */ + assign n1087_o = en_clk_i & en_flags_i; + /* upi41_db_bus.vhd:250:31 */ + assign n1116_o = write_pulse_s & a0_q; + /* upi41_db_bus.vhd:251:40 */ + assign n1117_o = ~a0_q; + /* upi41_db_bus.vhd:251:31 */ + assign n1118_o = write_pulse_s & n1117_o; + /* upi41_db_bus.vhd:254:36 */ + assign n1119_o = ~a0_q; + /* upi41_db_bus.vhd:254:26 */ + assign n1120_o = n1119_o ? dbbout_q : n1126_o; + /* upi41_db_bus.vhd:255:23 */ + assign n1121_o = {sts_q, f1_i}; + /* upi41_db_bus.vhd:255:30 */ + assign n1122_o = {n1121_o, f0_i}; + /* upi41_db_bus.vhd:255:37 */ + assign n1123_o = {n1122_o, ibf_q}; + /* upi41_db_bus.vhd:255:45 */ + assign n1124_o = {n1123_o, obf_q}; + /* upi41_db_bus.vhd:254:42 */ + assign n1126_o = 1'b1 ? n1124_o : n1131_o; + /* upi41_db_bus.vhd:256:24 */ + assign n1128_o = {4'b0000, f1_i}; + /* upi41_db_bus.vhd:256:31 */ + assign n1129_o = {n1128_o, f0_i}; + /* upi41_db_bus.vhd:256:38 */ + assign n1130_o = {n1129_o, ibf_q}; + /* upi41_db_bus.vhd:256:46 */ + assign n1131_o = {n1130_o, obf_q}; + /* upi41_db_bus.vhd:257:36 */ + assign n1133_o = ext_acc_s & read_hold_q; + /* upi41_db_bus.vhd:257:21 */ + assign n1134_o = n1133_o ? 1'b1 : 1'b0; + /* upi41_db_bus.vhd:259:17 */ + assign n1136_o = read_bus_i ? dbbin_q : 8'b11111111; + /* upi41_db_bus.vhd:262:36 */ + assign n1139_o = flags_q & ibf_q; + /* upi41_db_bus.vhd:262:23 */ + assign n1140_o = n1139_o ? 1'b0 : 1'b1; + /* upi41_db_bus.vhd:263:46 */ + assign n1143_o = ~obf_q; + /* upi41_db_bus.vhd:263:36 */ + assign n1144_o = flags_q & n1143_o; + /* upi41_db_bus.vhd:263:23 */ + assign n1145_o = n1144_o ? 1'b0 : 1'b1; + /* upi41_db_bus.vhd:155:5 */ + always @(posedge clk_i or posedge n1011_o) + if (n1011_o) + n1147_q <= 1'b0; + else + n1147_q <= read_s; + /* upi41_db_bus.vhd:155:5 */ + always @(posedge clk_i or posedge n1011_o) + if (n1011_o) + n1148_q <= 1'b0; + else + n1148_q <= n1016_o; + /* upi41_db_bus.vhd:155:5 */ + always @(posedge clk_i or posedge n1011_o) + if (n1011_o) + n1149_q <= 1'b0; + else + n1149_q <= write_s; + /* upi41_db_bus.vhd:155:5 */ + always @(posedge clk_i or posedge n1011_o) + if (n1011_o) + n1150_q <= 1'b0; + else + n1150_q <= n1020_o; + /* upi41_db_bus.vhd:196:5 */ + always @(posedge clk_i or posedge n1039_o) + if (n1039_o) + n1151_q <= 1'b0; + else + n1151_q <= n1082_o; + /* upi41_db_bus.vhd:196:5 */ + always @(posedge clk_i or posedge n1039_o) + if (n1039_o) + n1152_q <= 1'b0; + else + n1152_q <= n1064_o; + /* upi41_db_bus.vhd:196:5 */ + always @(posedge clk_i or posedge n1039_o) + if (n1039_o) + n1153_q <= 8'b00000000; + else + n1153_q <= n1052_o; + /* upi41_db_bus.vhd:196:5 */ + assign n1154_o = n1084_o ? data_i : dbbout_q; + /* upi41_db_bus.vhd:196:5 */ + always @(posedge clk_i or posedge n1039_o) + if (n1039_o) + n1155_q <= 8'b00000000; + else + n1155_q <= n1154_o; + /* upi41_db_bus.vhd:196:5 */ + assign n1156_o = en_clk_i ? n1066_o : sts_q; + /* upi41_db_bus.vhd:196:5 */ + always @(posedge clk_i or posedge n1039_o) + if (n1039_o) + n1157_q <= 4'b0000; + else + n1157_q <= n1156_o; + /* upi41_db_bus.vhd:196:5 */ + assign n1158_o = n1086_o ? 1'b1 : dma_q; + /* upi41_db_bus.vhd:196:5 */ + always @(posedge clk_i or posedge n1039_o) + if (n1039_o) + n1159_q <= 1'b0; + else + n1159_q <= n1158_o; + /* upi41_db_bus.vhd:196:5 */ + assign n1160_o = n1087_o ? 1'b1 : flags_q; + /* upi41_db_bus.vhd:196:5 */ + always @(posedge clk_i or posedge n1039_o) + if (n1039_o) + n1161_q <= 1'b0; + else + n1161_q <= n1160_o; + /* upi41_db_bus.vhd:196:5 */ + always @(posedge clk_i or posedge n1039_o) + if (n1039_o) + n1162_q <= 1'b1; + else + n1162_q <= n1068_o; + /* upi41_db_bus.vhd:196:5 */ + always @(posedge clk_i or posedge n1039_o) + if (n1039_o) + n1163_q <= 1'b0; + else + n1163_q <= n1081_o; +endmodule + +module t48_cond_branch + (input clk_i, + input res_i, + input en_clk_i, + input compute_take_i, + input [3:0] branch_cond_i, + input [7:0] accu_i, + input t0_i, + input t1_i, + input int_n_i, + input f0_i, + input f1_i, + input tf_i, + input carry_i, + input ibf_i, + input obf_i, + input [2:0] comp_value_i, + output take_branch_o); + wire take_branch_s; + wire take_branch_q; + wire n906_o; + wire n908_o; + wire n909_o; + wire n911_o; + wire n912_o; + wire n913_o; + wire n914_o; + wire n915_o; + wire n916_o; + wire n917_o; + wire n918_o; + wire n919_o; + wire n920_o; + wire n921_o; + wire n922_o; + wire n923_o; + wire n924_o; + wire n925_o; + wire n926_o; + wire n927_o; + wire n928_o; + wire n930_o; + wire n931_o; + wire n932_o; + wire n934_o; + wire n936_o; + wire n938_o; + wire n939_o; + wire n941_o; + wire n942_o; + wire n943_o; + wire n945_o; + wire n946_o; + wire n947_o; + wire n949_o; + wire n951_o; + wire n952_o; + wire n954_o; + wire n956_o; + wire [10:0] n957_o; + reg n959_o; + wire n966_o; + wire n969_o; + wire n974_o; + reg n975_q; + wire n976_o; + wire n977_o; + wire n978_o; + wire n979_o; + wire n980_o; + wire n981_o; + wire n982_o; + wire n983_o; + wire [1:0] n984_o; + reg n985_o; + wire [1:0] n986_o; + reg n987_o; + wire n988_o; + wire n989_o; + assign take_branch_o = take_branch_q; + /* cond_branch.vhd:90:10 */ + assign take_branch_s = n959_o; // (signal) + /* cond_branch.vhd:91:10 */ + assign take_branch_q = n975_q; // (signal) + /* cond_branch.vhd:119:9 */ + assign n906_o = n989_o ? 1'b1 : 1'b0; + /* cond_branch.vhd:118:7 */ + assign n908_o = branch_cond_i == 4'b0000; + /* cond_branch.vhd:126:33 */ + assign n909_o = accu_i[7]; + /* cond_branch.vhd:126:24 */ + assign n911_o = 1'b0 | n909_o; + /* cond_branch.vhd:126:33 */ + assign n912_o = accu_i[6]; + /* cond_branch.vhd:126:24 */ + assign n913_o = n911_o | n912_o; + /* cond_branch.vhd:126:33 */ + assign n914_o = accu_i[5]; + /* cond_branch.vhd:126:24 */ + assign n915_o = n913_o | n914_o; + /* cond_branch.vhd:126:33 */ + assign n916_o = accu_i[4]; + /* cond_branch.vhd:126:24 */ + assign n917_o = n915_o | n916_o; + /* cond_branch.vhd:126:33 */ + assign n918_o = accu_i[3]; + /* cond_branch.vhd:126:24 */ + assign n919_o = n917_o | n918_o; + /* cond_branch.vhd:126:33 */ + assign n920_o = accu_i[2]; + /* cond_branch.vhd:126:24 */ + assign n921_o = n919_o | n920_o; + /* cond_branch.vhd:126:33 */ + assign n922_o = accu_i[1]; + /* cond_branch.vhd:126:24 */ + assign n923_o = n921_o | n922_o; + /* cond_branch.vhd:126:33 */ + assign n924_o = accu_i[0]; + /* cond_branch.vhd:126:24 */ + assign n925_o = n923_o | n924_o; + /* cond_branch.vhd:128:49 */ + assign n926_o = comp_value_i[0]; + /* cond_branch.vhd:128:33 */ + assign n927_o = ~n926_o; + /* cond_branch.vhd:128:31 */ + assign n928_o = n925_o == n927_o; + /* cond_branch.vhd:124:7 */ + assign n930_o = branch_cond_i == 4'b0001; + /* cond_branch.vhd:132:48 */ + assign n931_o = comp_value_i[0]; + /* cond_branch.vhd:132:34 */ + assign n932_o = carry_i == n931_o; + /* cond_branch.vhd:131:7 */ + assign n934_o = branch_cond_i == 4'b0010; + /* cond_branch.vhd:135:7 */ + assign n936_o = branch_cond_i == 4'b0011; + /* cond_branch.vhd:139:7 */ + assign n938_o = branch_cond_i == 4'b0100; + /* cond_branch.vhd:144:34 */ + assign n939_o = ~int_n_i; + /* cond_branch.vhd:143:7 */ + assign n941_o = branch_cond_i == 4'b0101; + /* cond_branch.vhd:148:45 */ + assign n942_o = comp_value_i[0]; + /* cond_branch.vhd:148:31 */ + assign n943_o = t0_i == n942_o; + /* cond_branch.vhd:147:7 */ + assign n945_o = branch_cond_i == 4'b0110; + /* cond_branch.vhd:152:45 */ + assign n946_o = comp_value_i[0]; + /* cond_branch.vhd:152:31 */ + assign n947_o = t1_i == n946_o; + /* cond_branch.vhd:151:7 */ + assign n949_o = branch_cond_i == 4'b0111; + /* cond_branch.vhd:155:7 */ + assign n951_o = branch_cond_i == 4'b1000; + /* cond_branch.vhd:160:32 */ + assign n952_o = ~ibf_i; + /* cond_branch.vhd:159:7 */ + assign n954_o = branch_cond_i == 4'b1001; + /* cond_branch.vhd:163:7 */ + assign n956_o = branch_cond_i == 4'b1010; + /* clock_ctrl.vhd:206:5 */ + assign n957_o = {n956_o, n954_o, n951_o, n949_o, n945_o, n941_o, n938_o, n936_o, n934_o, n930_o, n908_o}; + /* cond_branch.vhd:116:5 */ + always @* + case (n957_o) + 11'b10000000000: n959_o = obf_i; + 11'b01000000000: n959_o = n952_o; + 11'b00100000000: n959_o = tf_i; + 11'b00010000000: n959_o = n947_o; + 11'b00001000000: n959_o = n943_o; + 11'b00000100000: n959_o = n939_o; + 11'b00000010000: n959_o = f1_i; + 11'b00000001000: n959_o = f0_i; + 11'b00000000100: n959_o = n932_o; + 11'b00000000010: n959_o = n928_o; + 11'b00000000001: n959_o = n906_o; + default: n959_o = 1'b0; + endcase + /* cond_branch.vhd:188:14 */ + assign n966_o = ~res_i; + /* cond_branch.vhd:192:7 */ + assign n969_o = en_clk_i & compute_take_i; + /* cond_branch.vhd:191:5 */ + assign n974_o = n969_o ? take_branch_s : take_branch_q; + /* cond_branch.vhd:191:5 */ + always @(posedge clk_i or posedge n966_o) + if (n966_o) + n975_q <= 1'b0; + else + n975_q <= n974_o; + /* cond_branch.vhd:64:5 */ + assign n976_o = accu_i[0]; + assign n977_o = accu_i[1]; + /* cond_branch.vhd:191:5 */ + assign n978_o = accu_i[2]; + /* cond_branch.vhd:186:3 */ + assign n979_o = accu_i[3]; + assign n980_o = accu_i[4]; + assign n981_o = accu_i[5]; + /* cond_branch.vhd:116:5 */ + assign n982_o = accu_i[6]; + assign n983_o = accu_i[7]; + /* cond_branch.vhd:119:18 */ + assign n984_o = comp_value_i[1:0]; + /* cond_branch.vhd:119:18 */ + always @* + case (n984_o) + 2'b00: n985_o = n976_o; + 2'b01: n985_o = n977_o; + 2'b10: n985_o = n978_o; + 2'b11: n985_o = n979_o; + endcase + /* cond_branch.vhd:119:18 */ + assign n986_o = comp_value_i[1:0]; + /* cond_branch.vhd:119:18 */ + always @* + case (n986_o) + 2'b00: n987_o = n980_o; + 2'b01: n987_o = n981_o; + 2'b10: n987_o = n982_o; + 2'b11: n987_o = n983_o; + endcase + /* cond_branch.vhd:119:18 */ + assign n988_o = comp_value_i[2]; + /* cond_branch.vhd:119:18 */ + assign n989_o = n988_o ? n987_o : n985_o; +endmodule + +module t48_clock_ctrl_1 + (input clk_i, + input xtal_i, + input xtal_en_i, + input res_i, + input en_clk_i, + input multi_cycle_i, + input assert_psen_i, + input assert_prog_i, + input assert_rd_i, + input assert_wr_i, + output xtal3_o, + output t0_o, + output [2:0] mstate_o, + output second_cycle_o, + output ale_o, + output psen_o, + output prog_o, + output rd_o, + output wr_o); + wire [1:0] xtal_q; + wire xtal2_s; + wire xtal3_s; + wire x2_s; + wire x3_s; + wire t0_q; + wire [2:0] mstate_q; + wire ale_q; + wire psen_q; + wire prog_q; + wire rd_q; + wire wr_q; + wire second_cycle_q; + wire multi_cycle_q; + wire n682_o; + wire n685_o; + wire [1:0] n687_o; + wire [1:0] n689_o; + wire n692_o; + wire n710_o; + wire n711_o; + wire n712_o; + wire n716_o; + wire n717_o; + wire n718_o; + wire n735_o; + wire n743_o; + wire n745_o; + wire n747_o; + wire n748_o; + wire n750_o; + wire n752_o; + wire n753_o; + wire n754_o; + wire n756_o; + wire n758_o; + wire n760_o; + wire n762_o; + wire n764_o; + wire n766_o; + wire n768_o; + wire n770_o; + wire n772_o; + wire n774_o; + wire n775_o; + wire n776_o; + wire n777_o; + wire n778_o; + wire n779_o; + wire n781_o; + wire n783_o; + wire n785_o; + wire [4:0] n786_o; + reg n788_o; + reg n790_o; + reg n792_o; + reg n794_o; + reg n796_o; + wire n814_o; + wire n817_o; + wire n819_o; + wire n821_o; + wire n823_o; + wire n825_o; + wire [4:0] n826_o; + reg [2:0] n833_o; + wire n842_o; + wire n845_o; + wire n847_o; + wire n848_o; + wire n850_o; + wire n851_o; + wire n853_o; + wire n854_o; + wire n855_o; + wire n857_o; + wire n859_o; + wire [1:0] n883_o; + reg [1:0] n884_q; + wire n885_o; + reg n886_q; + wire [2:0] n887_o; + reg [2:0] n888_q; + reg n889_q; + reg n890_q; + reg n891_q; + reg n892_q; + reg n893_q; + wire n894_o; + reg n895_q; + wire n896_o; + reg n897_q; + assign xtal3_o = xtal3_s; + assign t0_o = t0_q; + assign mstate_o = mstate_q; + assign second_cycle_o = second_cycle_q; + assign ale_o = ale_q; + assign psen_o = psen_q; + assign prog_o = prog_q; + assign rd_o = rd_q; + assign wr_o = wr_q; + /* clock_ctrl.vhd:90:10 */ + assign xtal_q = n884_q; // (signal) + /* clock_ctrl.vhd:92:10 */ + assign xtal2_s = n735_o; // (signal) + /* clock_ctrl.vhd:93:10 */ + assign xtal3_s = n743_o; // (signal) + /* clock_ctrl.vhd:95:10 */ + assign x2_s = n712_o; // (signal) + /* clock_ctrl.vhd:96:10 */ + assign x3_s = n718_o; // (signal) + /* clock_ctrl.vhd:98:10 */ + assign t0_q = n886_q; // (signal) + /* clock_ctrl.vhd:102:10 */ + assign mstate_q = n888_q; // (signal) + /* clock_ctrl.vhd:104:10 */ + assign ale_q = n889_q; // (signal) + /* clock_ctrl.vhd:105:10 */ + assign psen_q = n890_q; // (signal) + /* clock_ctrl.vhd:106:10 */ + assign prog_q = n891_q; // (signal) + /* clock_ctrl.vhd:107:10 */ + assign rd_q = n892_q; // (signal) + /* clock_ctrl.vhd:108:10 */ + assign wr_q = n893_q; // (signal) + /* clock_ctrl.vhd:112:10 */ + assign second_cycle_q = n895_q; // (signal) + /* clock_ctrl.vhd:113:10 */ + assign multi_cycle_q = n897_q; // (signal) + /* clock_ctrl.vhd:137:16 */ + assign n682_o = ~res_i; + /* clock_ctrl.vhd:143:21 */ + assign n685_o = $unsigned(xtal_q) < $unsigned(2'b10); + /* clock_ctrl.vhd:144:30 */ + assign n687_o = xtal_q + 2'b01; + /* clock_ctrl.vhd:143:11 */ + assign n689_o = n685_o ? n687_o : 2'b00; + /* clock_ctrl.vhd:149:11 */ + assign n692_o = xtal3_s ? 1'b1 : 1'b0; + /* clock_ctrl.vhd:164:25 */ + assign n710_o = xtal_q == 2'b01; + /* clock_ctrl.vhd:164:29 */ + assign n711_o = n710_o & xtal_en_i; + /* clock_ctrl.vhd:164:13 */ + assign n712_o = n711_o ? 1'b1 : 1'b0; + /* clock_ctrl.vhd:167:25 */ + assign n716_o = xtal_q == 2'b10; + /* clock_ctrl.vhd:167:29 */ + assign n717_o = n716_o & xtal_en_i; + /* clock_ctrl.vhd:167:13 */ + assign n718_o = n717_o ? 1'b1 : 1'b0; + /* t48_pack-p.vhd:75:5 */ + assign n735_o = x2_s ? 1'b1 : 1'b0; + /* t48_pack-p.vhd:75:5 */ + assign n743_o = x3_s ? 1'b1 : 1'b0; + /* clock_ctrl.vhd:206:14 */ + assign n745_o = ~res_i; + /* clock_ctrl.vhd:218:26 */ + assign n747_o = ~second_cycle_q; + /* clock_ctrl.vhd:218:22 */ + assign n748_o = xtal2_s & n747_o; + /* clock_ctrl.vhd:218:11 */ + assign n750_o = n753_o ? 1'b1 : rd_q; + /* clock_ctrl.vhd:218:11 */ + assign n752_o = n754_o ? 1'b1 : wr_q; + /* clock_ctrl.vhd:218:11 */ + assign n753_o = n748_o & assert_rd_i; + /* clock_ctrl.vhd:218:11 */ + assign n754_o = n748_o & assert_wr_i; + /* clock_ctrl.vhd:216:9 */ + assign n756_o = mstate_q == 3'b100; + /* clock_ctrl.vhd:228:11 */ + assign n758_o = xtal3_s ? 1'b0 : psen_q; + /* clock_ctrl.vhd:227:9 */ + assign n760_o = mstate_q == 3'b000; + /* clock_ctrl.vhd:233:11 */ + assign n762_o = xtal3_s ? 1'b0 : prog_q; + /* clock_ctrl.vhd:233:11 */ + assign n764_o = xtal3_s ? 1'b0 : rd_q; + /* clock_ctrl.vhd:233:11 */ + assign n766_o = xtal3_s ? 1'b0 : wr_q; + /* clock_ctrl.vhd:232:9 */ + assign n768_o = mstate_q == 3'b001; + /* clock_ctrl.vhd:243:11 */ + assign n770_o = xtal3_s ? 1'b1 : ale_q; + /* clock_ctrl.vhd:241:9 */ + assign n772_o = mstate_q == 3'b010; + /* clock_ctrl.vhd:248:11 */ + assign n774_o = n775_o ? 1'b1 : psen_q; + /* clock_ctrl.vhd:248:11 */ + assign n775_o = xtal3_s & assert_psen_i; + /* clock_ctrl.vhd:257:22 */ + assign n776_o = xtal3_s & multi_cycle_q; + /* clock_ctrl.vhd:258:32 */ + assign n777_o = ~second_cycle_q; + /* clock_ctrl.vhd:258:28 */ + assign n778_o = n776_o & n777_o; + /* clock_ctrl.vhd:258:51 */ + assign n779_o = n778_o & assert_prog_i; + /* clock_ctrl.vhd:257:11 */ + assign n781_o = n779_o ? 1'b1 : prog_q; + /* clock_ctrl.vhd:263:11 */ + assign n783_o = xtal2_s ? 1'b0 : ale_q; + /* clock_ctrl.vhd:247:9 */ + assign n785_o = mstate_q == 3'b011; + assign n786_o = {n785_o, n772_o, n768_o, n760_o, n756_o}; + /* clock_ctrl.vhd:215:7 */ + always @* + case (n786_o) + 5'b10000: n788_o = n783_o; + 5'b01000: n788_o = n770_o; + 5'b00100: n788_o = ale_q; + 5'b00010: n788_o = ale_q; + 5'b00001: n788_o = ale_q; + default: n788_o = 1'b0; + endcase + /* clock_ctrl.vhd:215:7 */ + always @* + case (n786_o) + 5'b10000: n790_o = n774_o; + 5'b01000: n790_o = psen_q; + 5'b00100: n790_o = psen_q; + 5'b00010: n790_o = n758_o; + 5'b00001: n790_o = psen_q; + default: n790_o = 1'b0; + endcase + /* clock_ctrl.vhd:215:7 */ + always @* + case (n786_o) + 5'b10000: n792_o = n781_o; + 5'b01000: n792_o = prog_q; + 5'b00100: n792_o = n762_o; + 5'b00010: n792_o = prog_q; + 5'b00001: n792_o = prog_q; + default: n792_o = 1'b0; + endcase + /* clock_ctrl.vhd:215:7 */ + always @* + case (n786_o) + 5'b10000: n794_o = rd_q; + 5'b01000: n794_o = rd_q; + 5'b00100: n794_o = n764_o; + 5'b00010: n794_o = rd_q; + 5'b00001: n794_o = n750_o; + default: n794_o = 1'b0; + endcase + /* clock_ctrl.vhd:215:7 */ + always @* + case (n786_o) + 5'b10000: n796_o = wr_q; + 5'b01000: n796_o = wr_q; + 5'b00100: n796_o = n766_o; + 5'b00010: n796_o = wr_q; + 5'b00001: n796_o = n752_o; + default: n796_o = 1'b0; + endcase + /* clock_ctrl.vhd:292:14 */ + assign n814_o = ~res_i; + /* clock_ctrl.vhd:303:11 */ + assign n817_o = mstate_q == 3'b100; + /* clock_ctrl.vhd:306:11 */ + assign n819_o = mstate_q == 3'b000; + /* clock_ctrl.vhd:309:11 */ + assign n821_o = mstate_q == 3'b001; + /* clock_ctrl.vhd:312:11 */ + assign n823_o = mstate_q == 3'b010; + /* clock_ctrl.vhd:315:11 */ + assign n825_o = mstate_q == 3'b011; + assign n826_o = {n825_o, n823_o, n821_o, n819_o, n817_o}; + /* clock_ctrl.vhd:302:9 */ + always @* + case (n826_o) + 5'b10000: n833_o = 3'b100; + 5'b01000: n833_o = 3'b011; + 5'b00100: n833_o = 3'b010; + 5'b00010: n833_o = 3'b001; + 5'b00001: n833_o = 3'b000; + default: n833_o = 3'b000; + endcase + /* clock_ctrl.vhd:349:14 */ + assign n842_o = ~res_i; + /* clock_ctrl.vhd:356:30 */ + assign n845_o = mstate_q == 3'b001; + /* clock_ctrl.vhd:357:30 */ + assign n847_o = mstate_q == 3'b100; + /* clock_ctrl.vhd:360:21 */ + assign n848_o = n845_o & multi_cycle_i; + /* clock_ctrl.vhd:360:9 */ + assign n850_o = n848_o ? 1'b1 : multi_cycle_q; + /* clock_ctrl.vhd:365:26 */ + assign n851_o = multi_cycle_q & n847_o; + /* clock_ctrl.vhd:365:9 */ + assign n853_o = n851_o ? 1'b1 : second_cycle_q; + /* clock_ctrl.vhd:371:27 */ + assign n854_o = multi_cycle_q & second_cycle_q; + /* clock_ctrl.vhd:370:21 */ + assign n855_o = n847_o & n854_o; + /* clock_ctrl.vhd:370:9 */ + assign n857_o = n855_o ? 1'b0 : n853_o; + /* clock_ctrl.vhd:370:9 */ + assign n859_o = n855_o ? 1'b0 : n850_o; + /* clock_ctrl.vhd:141:7 */ + assign n883_o = xtal_en_i ? n689_o : xtal_q; + /* clock_ctrl.vhd:141:7 */ + always @(posedge xtal_i or posedge n682_o) + if (n682_o) + n884_q <= 2'b00; + else + n884_q <= n883_o; + /* clock_ctrl.vhd:141:7 */ + assign n885_o = xtal_en_i ? n692_o : t0_q; + /* clock_ctrl.vhd:141:7 */ + always @(posedge xtal_i or posedge n682_o) + if (n682_o) + n886_q <= 1'b0; + else + n886_q <= n885_o; + /* clock_ctrl.vhd:299:5 */ + assign n887_o = en_clk_i ? n833_o : mstate_q; + /* clock_ctrl.vhd:299:5 */ + always @(posedge clk_i or posedge n814_o) + if (n814_o) + n888_q <= 3'b010; + else + n888_q <= n887_o; + /* clock_ctrl.vhd:213:5 */ + always @(posedge xtal_i or posedge n745_o) + if (n745_o) + n889_q <= 1'b0; + else + n889_q <= n788_o; + /* clock_ctrl.vhd:213:5 */ + always @(posedge xtal_i or posedge n745_o) + if (n745_o) + n890_q <= 1'b0; + else + n890_q <= n790_o; + /* clock_ctrl.vhd:213:5 */ + always @(posedge xtal_i or posedge n745_o) + if (n745_o) + n891_q <= 1'b0; + else + n891_q <= n792_o; + /* clock_ctrl.vhd:213:5 */ + always @(posedge xtal_i or posedge n745_o) + if (n745_o) + n892_q <= 1'b0; + else + n892_q <= n794_o; + /* clock_ctrl.vhd:213:5 */ + always @(posedge xtal_i or posedge n745_o) + if (n745_o) + n893_q <= 1'b0; + else + n893_q <= n796_o; + /* clock_ctrl.vhd:353:5 */ + assign n894_o = en_clk_i ? n857_o : second_cycle_q; + /* clock_ctrl.vhd:353:5 */ + always @(posedge clk_i or posedge n842_o) + if (n842_o) + n895_q <= 1'b0; + else + n895_q <= n894_o; + /* clock_ctrl.vhd:353:5 */ + assign n896_o = en_clk_i ? n859_o : multi_cycle_q; + /* clock_ctrl.vhd:353:5 */ + always @(posedge clk_i or posedge n842_o) + if (n842_o) + n897_q <= 1'b0; + else + n897_q <= n896_o; +endmodule + +module t48_bus_mux + (input [7:0] alu_data_i, + input [7:0] bus_data_i, + input [7:0] dec_data_i, + input [7:0] dm_data_i, + input [7:0] pm_data_i, + input [7:0] p1_data_i, + input [7:0] p2_data_i, + input [7:0] psw_data_i, + input [7:0] tim_data_i, + output [7:0] data_o); + wire [7:0] n664_o; + wire [7:0] n665_o; + wire [7:0] n666_o; + wire [7:0] n667_o; + wire [7:0] n668_o; + wire [7:0] n669_o; + wire [7:0] n670_o; + wire [7:0] n671_o; + assign data_o = n671_o; + /* bus_mux.vhd:89:26 */ + assign n664_o = alu_data_i & bus_data_i; + /* bus_mux.vhd:90:26 */ + assign n665_o = n664_o & dec_data_i; + /* bus_mux.vhd:91:26 */ + assign n666_o = n665_o & dm_data_i; + /* bus_mux.vhd:92:26 */ + assign n667_o = n666_o & pm_data_i; + /* bus_mux.vhd:93:26 */ + assign n668_o = n667_o & p1_data_i; + /* bus_mux.vhd:94:26 */ + assign n669_o = n668_o & p2_data_i; + /* bus_mux.vhd:95:26 */ + assign n670_o = n669_o & psw_data_i; + /* bus_mux.vhd:96:26 */ + assign n671_o = n670_o & tim_data_i; +endmodule + +module t48_alu + (input clk_i, + input res_i, + input en_clk_i, + input [7:0] data_i, + input write_accu_i, + input write_shadow_i, + input write_temp_reg_i, + input read_alu_i, + input carry_i, + input [3:0] alu_op_i, + input use_carry_i, + input da_high_i, + input accu_low_i, + input p06_temp_reg_i, + input p60_temp_reg_i, + output [7:0] data_o, + output carry_o, + output aux_carry_o, + output da_overflow_o); + wire [7:0] accumulator_q; + wire [7:0] accu_shadow_q; + wire [7:0] temp_req_q; + wire [7:0] in_a_s; + wire [7:0] in_b_s; + wire [7:0] data_s; + wire [8:0] add_result_s; + wire n413_o; + wire [3:0] n415_o; + wire [3:0] n416_o; + wire [3:0] n417_o; + wire [3:0] n418_o; + wire [3:0] n419_o; + wire [3:0] n420_o; + wire [7:0] n421_o; + wire [7:0] n423_o; + wire [7:0] n424_o; + wire [7:0] n426_o; + wire [7:0] n428_o; + wire n429_o; + wire [7:0] n443_o; + wire n445_o; + wire [7:0] n446_o; + wire n448_o; + wire [7:0] n449_o; + wire n451_o; + wire [7:0] n452_o; + wire n453_o; + wire n455_o; + wire [7:0] n456_o; + wire n458_o; + wire n460_o; + wire [6:0] n461_o; + wire n462_o; + wire n463_o; + wire n464_o; + wire n466_o; + wire [6:0] n467_o; + wire n468_o; + wire n469_o; + wire n470_o; + wire n472_o; + wire [3:0] n473_o; + wire [3:0] n474_o; + wire n476_o; + wire [7:0] n477_o; + wire n479_o; + wire [7:0] n480_o; + wire n482_o; + wire [3:0] n483_o; + wire [3:0] n484_o; + wire [7:0] n485_o; + wire n487_o; + wire n489_o; + wire [12:0] n490_o; + reg n492_o; + wire n494_o; + wire n495_o; + wire n496_o; + wire n497_o; + wire n498_o; + wire n500_o; + wire n501_o; + wire n502_o; + wire n503_o; + wire n504_o; + wire n505_o; + reg n507_o; + wire [2:0] n508_o; + wire [2:0] n509_o; + wire [2:0] n510_o; + wire [2:0] n511_o; + wire [2:0] n512_o; + wire [2:0] n514_o; + wire [2:0] n515_o; + wire [2:0] n516_o; + wire [2:0] n517_o; + wire [2:0] n518_o; + wire [2:0] n519_o; + wire [2:0] n520_o; + reg [2:0] n522_o; + wire [2:0] n523_o; + wire [2:0] n524_o; + wire [2:0] n525_o; + wire [2:0] n526_o; + wire [2:0] n527_o; + wire [2:0] n529_o; + wire [2:0] n530_o; + wire [2:0] n531_o; + wire [2:0] n532_o; + wire [2:0] n533_o; + wire [2:0] n534_o; + wire [2:0] n535_o; + reg [2:0] n537_o; + wire n538_o; + wire n539_o; + wire n540_o; + wire n541_o; + wire n542_o; + wire n544_o; + wire n545_o; + wire n546_o; + wire n547_o; + wire n548_o; + wire n549_o; + reg n551_o; + wire n563_o; + wire n566_o; + localparam [8:0] n567_o = 9'b000000000; + wire [7:0] n568_o; + wire [8:0] n570_o; + wire [8:0] n572_o; + localparam [8:0] n574_o = 9'b000000000; + wire [7:0] n575_o; + wire n577_o; + wire n579_o; + wire [1:0] n580_o; + wire n582_o; + reg n583_o; + wire [7:0] n585_o; + reg [7:0] n586_o; + wire [8:0] n588_o; + wire [8:0] n589_o; + wire [8:0] n590_o; + wire [8:0] n591_o; + wire n592_o; + wire n593_o; + wire [1:0] n594_o; + wire n595_o; + wire n598_o; + wire n600_o; + wire n602_o; + wire n603_o; + wire n604_o; + wire n605_o; + wire n608_o; + wire n610_o; + wire n612_o; + wire n613_o; + wire [1:0] n614_o; + reg n616_o; + wire [3:0] n623_o; + wire [3:0] n624_o; + wire [3:0] n625_o; + wire n633_o; + wire n635_o; + wire n636_o; + wire n638_o; + wire n639_o; + wire n641_o; + wire n642_o; + wire n644_o; + wire n645_o; + wire n647_o; + wire n648_o; + reg n651_o; + wire [7:0] n654_o; + wire [7:0] n656_o; + reg [7:0] n657_q; + wire [7:0] n658_o; + reg [7:0] n659_q; + wire [7:0] n660_o; + reg [7:0] n661_q; + wire [7:0] n662_o; + assign data_o = n654_o; + assign carry_o = n492_o; + assign aux_carry_o = n616_o; + assign da_overflow_o = n651_o; + /* alu.vhd:99:10 */ + assign accumulator_q = n657_q; // (signal) + /* alu.vhd:100:10 */ + assign accu_shadow_q = n659_q; // (signal) + /* alu.vhd:101:10 */ + assign temp_req_q = n661_q; // (signal) + /* alu.vhd:103:10 */ + assign in_a_s = accu_shadow_q; // (signal) + /* alu.vhd:104:10 */ + assign in_b_s = temp_req_q; // (signal) + /* alu.vhd:106:10 */ + assign data_s = n662_o; // (signal) + /* alu.vhd:108:10 */ + assign add_result_s = n591_o; // (signal) + /* alu.vhd:122:14 */ + assign n413_o = ~res_i; + /* alu.vhd:132:52 */ + assign n415_o = data_i[3:0]; + /* upi41_core.vhd:562:24 */ + assign n416_o = data_i[3:0]; + /* alu.vhd:131:11 */ + assign n417_o = accu_low_i ? n415_o : n416_o; + /* upi41_core.vhd:545:3 */ + assign n418_o = data_i[7:4]; + /* upi41_core.vhd:545:3 */ + assign n419_o = accumulator_q[7:4]; + /* alu.vhd:131:11 */ + assign n420_o = accu_low_i ? n419_o : n418_o; + /* upi41_core.vhd:545:3 */ + assign n421_o = {n420_o, n417_o}; + /* alu.vhd:138:9 */ + assign n423_o = write_shadow_i ? data_i : accumulator_q; + /* alu.vhd:152:9 */ + assign n424_o = write_temp_reg_i ? data_i : temp_req_q; + /* alu.vhd:149:9 */ + assign n426_o = p60_temp_reg_i ? 8'b01100000 : n424_o; + /* alu.vhd:146:9 */ + assign n428_o = p06_temp_reg_i ? 8'b00000110 : n426_o; + /* alu.vhd:128:7 */ + assign n429_o = en_clk_i & write_accu_i; + /* alu.vhd:203:26 */ + assign n443_o = in_a_s & in_b_s; + /* alu.vhd:202:7 */ + assign n445_o = alu_op_i == 4'b0000; + /* alu.vhd:207:26 */ + assign n446_o = in_a_s | in_b_s; + /* alu.vhd:206:7 */ + assign n448_o = alu_op_i == 4'b0001; + /* alu.vhd:211:26 */ + assign n449_o = in_a_s ^ in_b_s; + /* alu.vhd:210:7 */ + assign n451_o = alu_op_i == 4'b0010; + /* alu.vhd:215:32 */ + assign n452_o = add_result_s[7:0]; + /* alu.vhd:216:32 */ + assign n453_o = add_result_s[8]; + /* alu.vhd:214:7 */ + assign n455_o = alu_op_i == 4'b1010; + /* alu.vhd:220:19 */ + assign n456_o = ~in_a_s; + /* alu.vhd:219:7 */ + assign n458_o = alu_op_i == 4'b0011; + /* alu.vhd:223:7 */ + assign n460_o = alu_op_i == 4'b0100; + /* alu.vhd:228:37 */ + assign n461_o = in_a_s[6:0]; + /* alu.vhd:229:37 */ + assign n462_o = in_a_s[7]; + /* alu.vhd:234:37 */ + assign n463_o = in_a_s[7]; + /* alu.vhd:231:9 */ + assign n464_o = use_carry_i ? carry_i : n463_o; + /* alu.vhd:227:7 */ + assign n466_o = alu_op_i == 4'b0101; + /* alu.vhd:239:37 */ + assign n467_o = in_a_s[7:1]; + /* alu.vhd:240:37 */ + assign n468_o = in_a_s[0]; + /* alu.vhd:245:37 */ + assign n469_o = in_a_s[0]; + /* alu.vhd:242:9 */ + assign n470_o = use_carry_i ? carry_i : n469_o; + /* alu.vhd:238:7 */ + assign n472_o = alu_op_i == 4'b0110; + /* alu.vhd:250:37 */ + assign n473_o = in_a_s[7:4]; + /* alu.vhd:251:37 */ + assign n474_o = in_a_s[3:0]; + /* alu.vhd:249:7 */ + assign n476_o = alu_op_i == 4'b0111; + /* alu.vhd:255:31 */ + assign n477_o = add_result_s[7:0]; + /* alu.vhd:254:7 */ + assign n479_o = alu_op_i == 4'b1000; + /* alu.vhd:259:31 */ + assign n480_o = add_result_s[7:0]; + /* alu.vhd:258:7 */ + assign n482_o = alu_op_i == 4'b1001; + /* alu.vhd:263:25 */ + assign n483_o = in_b_s[7:4]; + /* alu.vhd:263:46 */ + assign n484_o = in_a_s[3:0]; + /* alu.vhd:263:38 */ + assign n485_o = {n483_o, n484_o}; + /* alu.vhd:262:7 */ + assign n487_o = alu_op_i == 4'b1011; + /* alu.vhd:266:7 */ + assign n489_o = alu_op_i == 4'b1100; + /* upi41_core.vhd:426:33 */ + assign n490_o = {n489_o, n487_o, n482_o, n479_o, n476_o, n472_o, n466_o, n460_o, n458_o, n455_o, n451_o, n448_o, n445_o}; + /* alu.vhd:200:5 */ + always @* + case (n490_o) + 13'b1000000000000: n492_o = 1'b0; + 13'b0100000000000: n492_o = 1'b0; + 13'b0010000000000: n492_o = 1'b0; + 13'b0001000000000: n492_o = 1'b0; + 13'b0000100000000: n492_o = 1'b0; + 13'b0000010000000: n492_o = n468_o; + 13'b0000001000000: n492_o = n462_o; + 13'b0000000100000: n492_o = 1'b0; + 13'b0000000010000: n492_o = 1'b0; + 13'b0000000001000: n492_o = n453_o; + 13'b0000000000100: n492_o = 1'b0; + 13'b0000000000010: n492_o = 1'b0; + 13'b0000000000001: n492_o = 1'b0; + default: n492_o = 1'b0; + endcase + /* upi41_core.vhd:422:33 */ + assign n494_o = n443_o[0]; + /* upi41_core.vhd:421:33 */ + assign n495_o = n446_o[0]; + /* upi41_core.vhd:420:33 */ + assign n496_o = n449_o[0]; + /* upi41_core.vhd:417:33 */ + assign n497_o = n452_o[0]; + /* upi41_core.vhd:416:33 */ + assign n498_o = n456_o[0]; + /* upi41_core.vhd:414:33 */ + assign n500_o = n467_o[0]; + /* upi41_core.vhd:413:33 */ + assign n501_o = n473_o[0]; + /* upi41_core.vhd:412:33 */ + assign n502_o = n477_o[0]; + /* upi41_core.vhd:411:33 */ + assign n503_o = n480_o[0]; + /* upi41_core.vhd:394:3 */ + assign n504_o = n485_o[0]; + /* upi41_core.vhd:394:3 */ + assign n505_o = in_a_s[0]; + /* alu.vhd:200:5 */ + always @* + case (n490_o) + 13'b1000000000000: n507_o = n505_o; + 13'b0100000000000: n507_o = n504_o; + 13'b0010000000000: n507_o = n503_o; + 13'b0001000000000: n507_o = n502_o; + 13'b0000100000000: n507_o = n501_o; + 13'b0000010000000: n507_o = n500_o; + 13'b0000001000000: n507_o = n464_o; + 13'b0000000100000: n507_o = 1'b0; + 13'b0000000010000: n507_o = n498_o; + 13'b0000000001000: n507_o = n497_o; + 13'b0000000000100: n507_o = n496_o; + 13'b0000000000010: n507_o = n495_o; + 13'b0000000000001: n507_o = n494_o; + default: n507_o = 1'b0; + endcase + /* upi41_core.vhd:394:3 */ + assign n508_o = n443_o[3:1]; + /* upi41_core.vhd:394:3 */ + assign n509_o = n446_o[3:1]; + /* upi41_core.vhd:394:3 */ + assign n510_o = n449_o[3:1]; + /* upi41_core.vhd:394:3 */ + assign n511_o = n452_o[3:1]; + /* upi41_core.vhd:394:3 */ + assign n512_o = n456_o[3:1]; + /* upi41_core.vhd:394:3 */ + assign n514_o = n461_o[2:0]; + /* upi41_core.vhd:394:3 */ + assign n515_o = n467_o[3:1]; + /* upi41_core.vhd:394:3 */ + assign n516_o = n473_o[3:1]; + /* upi41_core.vhd:394:3 */ + assign n517_o = n477_o[3:1]; + /* upi41_core.vhd:394:3 */ + assign n518_o = n480_o[3:1]; + /* upi41_core.vhd:394:3 */ + assign n519_o = n485_o[3:1]; + /* upi41_core.vhd:394:3 */ + assign n520_o = in_a_s[3:1]; + /* alu.vhd:200:5 */ + always @* + case (n490_o) + 13'b1000000000000: n522_o = n520_o; + 13'b0100000000000: n522_o = n519_o; + 13'b0010000000000: n522_o = n518_o; + 13'b0001000000000: n522_o = n517_o; + 13'b0000100000000: n522_o = n516_o; + 13'b0000010000000: n522_o = n515_o; + 13'b0000001000000: n522_o = n514_o; + 13'b0000000100000: n522_o = 3'b000; + 13'b0000000010000: n522_o = n512_o; + 13'b0000000001000: n522_o = n511_o; + 13'b0000000000100: n522_o = n510_o; + 13'b0000000000010: n522_o = n509_o; + 13'b0000000000001: n522_o = n508_o; + default: n522_o = 3'b000; + endcase + /* upi41_core.vhd:394:3 */ + assign n523_o = n443_o[6:4]; + /* upi41_core.vhd:394:3 */ + assign n524_o = n446_o[6:4]; + /* upi41_core.vhd:394:3 */ + assign n525_o = n449_o[6:4]; + /* upi41_core.vhd:394:3 */ + assign n526_o = n452_o[6:4]; + /* upi41_core.vhd:394:3 */ + assign n527_o = n456_o[6:4]; + /* upi41_core.vhd:394:3 */ + assign n529_o = n461_o[5:3]; + /* upi41_core.vhd:394:3 */ + assign n530_o = n467_o[6:4]; + /* upi41_core.vhd:394:3 */ + assign n531_o = n474_o[2:0]; + /* upi41_core.vhd:394:3 */ + assign n532_o = n477_o[6:4]; + /* upi41_core.vhd:394:3 */ + assign n533_o = n480_o[6:4]; + /* upi41_core.vhd:394:3 */ + assign n534_o = n485_o[6:4]; + /* upi41_core.vhd:394:3 */ + assign n535_o = in_a_s[6:4]; + /* alu.vhd:200:5 */ + always @* + case (n490_o) + 13'b1000000000000: n537_o = n535_o; + 13'b0100000000000: n537_o = n534_o; + 13'b0010000000000: n537_o = n533_o; + 13'b0001000000000: n537_o = n532_o; + 13'b0000100000000: n537_o = n531_o; + 13'b0000010000000: n537_o = n530_o; + 13'b0000001000000: n537_o = n529_o; + 13'b0000000100000: n537_o = 3'b000; + 13'b0000000010000: n537_o = n527_o; + 13'b0000000001000: n537_o = n526_o; + 13'b0000000000100: n537_o = n525_o; + 13'b0000000000010: n537_o = n524_o; + 13'b0000000000001: n537_o = n523_o; + default: n537_o = 3'b000; + endcase + /* upi41_core.vhd:394:3 */ + assign n538_o = n443_o[7]; + /* upi41_core.vhd:394:3 */ + assign n539_o = n446_o[7]; + /* upi41_core.vhd:394:3 */ + assign n540_o = n449_o[7]; + /* upi41_core.vhd:394:3 */ + assign n541_o = n452_o[7]; + /* upi41_core.vhd:394:3 */ + assign n542_o = n456_o[7]; + /* upi41_core.vhd:394:3 */ + assign n544_o = n461_o[6]; + /* upi41_core.vhd:394:3 */ + assign n545_o = n474_o[3]; + /* upi41_core.vhd:394:3 */ + assign n546_o = n477_o[7]; + /* upi41_core.vhd:394:3 */ + assign n547_o = n480_o[7]; + /* upi41_core.vhd:394:3 */ + assign n548_o = n485_o[7]; + /* upi41_core.vhd:394:3 */ + assign n549_o = in_a_s[7]; + /* alu.vhd:200:5 */ + always @* + case (n490_o) + 13'b1000000000000: n551_o = n549_o; + 13'b0100000000000: n551_o = n548_o; + 13'b0010000000000: n551_o = n547_o; + 13'b0001000000000: n551_o = n546_o; + 13'b0000100000000: n551_o = n545_o; + 13'b0000010000000: n551_o = n470_o; + 13'b0000001000000: n551_o = n544_o; + 13'b0000000100000: n551_o = 1'b0; + 13'b0000000010000: n551_o = n542_o; + 13'b0000000001000: n551_o = n541_o; + 13'b0000000000100: n551_o = n540_o; + 13'b0000000000010: n551_o = n539_o; + 13'b0000000000001: n551_o = n538_o; + default: n551_o = 1'b0; + endcase + /* alu.vhd:307:20 */ + assign n563_o = use_carry_i & carry_i; + /* alu.vhd:307:5 */ + assign n566_o = n563_o ? 1'b1 : 1'b0; + /* upi41_core.vhd:380:25 */ + assign n568_o = n567_o[8:1]; + /* alu.vhd:313:20 */ + assign n570_o = {1'b0, in_a_s}; + /* alu.vhd:314:20 */ + assign n572_o = {1'b0, in_b_s}; + /* upi41_core.vhd:356:5 */ + assign n575_o = n574_o[8:1]; + /* alu.vhd:317:7 */ + assign n577_o = alu_op_i == 4'b1001; + /* alu.vhd:320:7 */ + assign n579_o = alu_op_i == 4'b1000; + /* upi41_core.vhd:356:5 */ + assign n580_o = {n579_o, n577_o}; + /* upi41_core.vhd:356:5 */ + assign n582_o = n572_o[0]; + /* alu.vhd:316:5 */ + always @* + case (n580_o) + 2'b10: n583_o = 1'b1; + 2'b01: n583_o = 1'b1; + default: n583_o = n582_o; + endcase + /* upi41_core.vhd:356:5 */ + assign n585_o = n572_o[8:1]; + /* alu.vhd:316:5 */ + always @* + case (n580_o) + 2'b10: n586_o = 8'b11111111; + 2'b01: n586_o = n575_o; + default: n586_o = n585_o; + endcase + /* upi41_core.vhd:335:3 */ + assign n588_o = {n586_o, n583_o}; + /* alu.vhd:327:35 */ + assign n589_o = n570_o + n588_o; + /* upi41_core.vhd:328:25 */ + assign n590_o = {n568_o, n566_o}; + /* alu.vhd:328:35 */ + assign n591_o = n589_o + n590_o; + /* alu.vhd:334:32 */ + assign n592_o = in_a_s[4]; + /* alu.vhd:334:44 */ + assign n593_o = in_b_s[4]; + /* alu.vhd:334:36 */ + assign n594_o = {n592_o, n593_o}; + /* alu.vhd:339:20 */ + assign n595_o = n591_o[4]; + /* alu.vhd:339:9 */ + assign n598_o = n595_o ? 1'b1 : 1'b0; + /* alu.vhd:338:7 */ + assign n600_o = n594_o == 2'b00; + /* alu.vhd:338:17 */ + assign n602_o = n594_o == 2'b11; + /* alu.vhd:338:17 */ + assign n603_o = n600_o | n602_o; + /* alu.vhd:344:20 */ + assign n604_o = n591_o[4]; + /* alu.vhd:344:24 */ + assign n605_o = ~n604_o; + /* alu.vhd:344:9 */ + assign n608_o = n605_o ? 1'b1 : 1'b0; + /* alu.vhd:343:7 */ + assign n610_o = n594_o == 2'b01; + /* alu.vhd:343:17 */ + assign n612_o = n594_o == 2'b10; + /* alu.vhd:343:17 */ + assign n613_o = n610_o | n612_o; + /* upi41_core.vhd:94:5 */ + assign n614_o = {n613_o, n603_o}; + /* alu.vhd:337:5 */ + always @* + case (n614_o) + 2'b10: n616_o = n608_o; + 2'b01: n616_o = n598_o; + default: n616_o = 1'b0; + endcase + /* alu.vhd:389:35 */ + assign n623_o = accu_shadow_q[7:4]; + /* alu.vhd:391:35 */ + assign n624_o = accu_shadow_q[3:0]; + /* alu.vhd:388:5 */ + assign n625_o = da_high_i ? n623_o : n624_o; + /* alu.vhd:373:9 */ + assign n633_o = n625_o == 4'b1010; + /* alu.vhd:373:21 */ + assign n635_o = n625_o == 4'b1011; + /* alu.vhd:373:21 */ + assign n636_o = n633_o | n635_o; + /* alu.vhd:374:21 */ + assign n638_o = n625_o == 4'b1100; + /* alu.vhd:374:21 */ + assign n639_o = n636_o | n638_o; + /* alu.vhd:375:21 */ + assign n641_o = n625_o == 4'b1101; + /* alu.vhd:375:21 */ + assign n642_o = n639_o | n641_o; + /* alu.vhd:376:21 */ + assign n644_o = n625_o == 4'b1110; + /* alu.vhd:376:21 */ + assign n645_o = n642_o | n644_o; + /* alu.vhd:377:21 */ + assign n647_o = n625_o == 4'b1111; + /* alu.vhd:377:21 */ + assign n648_o = n645_o | n647_o; + /* alu.vhd:372:7 */ + always @* + case (n648_o) + 1'b1: n651_o = 1'b1; + default: n651_o = 1'b0; + endcase + /* alu.vhd:412:13 */ + assign n654_o = read_alu_i ? data_s : 8'b11111111; + /* alu.vhd:127:5 */ + assign n656_o = n429_o ? n421_o : accumulator_q; + /* alu.vhd:127:5 */ + always @(posedge clk_i or posedge n413_o) + if (n413_o) + n657_q <= 8'b00000000; + else + n657_q <= n656_o; + /* alu.vhd:127:5 */ + assign n658_o = en_clk_i ? n423_o : accu_shadow_q; + /* alu.vhd:127:5 */ + always @(posedge clk_i or posedge n413_o) + if (n413_o) + n659_q <= 8'b00000000; + else + n659_q <= n658_o; + /* alu.vhd:127:5 */ + assign n660_o = en_clk_i ? n428_o : temp_req_q; + /* alu.vhd:127:5 */ + always @(posedge clk_i or posedge n413_o) + if (n413_o) + n661_q <= 8'b00000000; + else + n661_q <= n660_o; + /* alu.vhd:122:5 */ + assign n662_o = {n551_o, n537_o, n522_o, n507_o}; +endmodule + +module upi41_core + (input xtal_i, + input xtal_en_i, + input reset_i, + input t0_i, + input cs_n_i, + input rd_n_i, + input a0_i, + input wr_n_i, + input [7:0] db_i, + input t1_i, + input [7:0] p2_i, + input [7:0] p1_i, + input clk_i, + input en_clk_i, + input [7:0] dmem_data_i, + input [7:0] pmem_data_i, + output sync_o, + output [7:0] db_o, + output db_dir_o, + output [7:0] p2_o, + output p2l_low_imp_o, + output p2h_low_imp_o, + output [7:0] p1_o, + output p1_low_imp_o, + output prog_n_o, + output xtal3_o, + output [7:0] dmem_addr_o, + output dmem_we_o, + output [7:0] dmem_data_o, + output [10:0] pmem_addr_o); + wire [7:0] t48_data_s; + wire xtal_en_s; + wire en_clk_s; + wire t0_s; + wire t1_s; + wire [7:0] alu_data_s; + wire alu_write_accu_s; + wire alu_write_shadow_s; + wire alu_write_temp_reg_s; + wire alu_read_alu_s; + wire alu_carry_s; + wire alu_aux_carry_s; + wire [3:0] alu_op_s; + wire alu_use_carry_s; + wire alu_da_high_s; + wire alu_da_overflow_s; + wire alu_accu_low_s; + wire alu_p06_temp_reg_s; + wire alu_p60_temp_reg_s; + wire bus_write_bus_s; + wire bus_read_bus_s; + wire [7:0] bus_data_s; + wire bus_ibf_s; + wire bus_obf_s; + wire bus_int_n_s; + wire bus_set_f1_s; + wire bus_clear_f1_s; + wire bus_ibf_int_s; + wire bus_en_dma_s; + wire bus_en_flags_s; + wire bus_write_sts_s; + wire bus_mint_ibf_n_s; + wire bus_mint_obf_s; + wire bus_dma_s; + wire bus_drq_s; + wire clk_multi_cycle_s; + wire clk_assert_psen_s; + wire clk_assert_prog_s; + wire clk_assert_rd_s; + wire clk_assert_wr_s; + wire [2:0] clk_mstate_s; + wire clk_second_cycle_s; + wire prog_s; + wire ale_s; + wire xtal3_s; + wire cnd_compute_take_s; + wire [3:0] cnd_branch_cond_s; + wire cnd_take_branch_s; + wire [2:0] cnd_comp_value_s; + wire cnd_f1_s; + wire cnd_tf_s; + wire dm_write_dmem_addr_s; + wire dm_write_dmem_s; + wire dm_read_dmem_s; + wire [1:0] dm_addr_type_s; + wire [7:0] dm_data_s; + wire [7:0] dec_data_s; + wire p1_write_p1_s; + wire p1_read_p1_s; + wire p1_read_reg_s; + wire [7:0] p1_data_s; + wire [7:0] p2_s; + wire p26_s; + wire p2_write_p2_s; + wire p2_write_exp_s; + wire p2_read_p2_s; + wire p2_read_reg_s; + wire p2_read_exp_s; + wire p2_output_pch_s; + wire [7:0] p2_data_s; + wire pm_write_pcl_s; + wire pm_read_pcl_s; + wire pm_write_pch_s; + wire pm_read_pch_s; + wire pm_read_pmem_s; + wire pm_inc_pc_s; + wire pm_write_pmem_addr_s; + wire [7:0] pm_data_s; + wire [1:0] pm_addr_type_s; + wire [11:0] pmem_addr_s; + wire psw_read_psw_s; + wire psw_read_sp_s; + wire psw_write_psw_s; + wire psw_write_sp_s; + wire psw_carry_s; + wire psw_aux_carry_s; + wire psw_f0_s; + wire psw_bs_s; + wire psw_special_data_s; + wire psw_inc_stackp_s; + wire psw_dec_stackp_s; + wire psw_write_carry_s; + wire psw_write_aux_carry_s; + wire psw_write_f0_s; + wire psw_write_bs_s; + wire [7:0] psw_data_s; + wire tim_overflow_s; + wire tim_of_s; + wire tim_read_timer_s; + wire tim_write_timer_s; + wire tim_start_t_s; + wire tim_start_cnt_s; + wire tim_stop_tcnt_s; + wire [7:0] tim_data_s; + wire gnd_s; + localparam n14_o = 1'b0; + wire n23_o; + wire n31_o; + wire [7:0] alu_b_n32; + wire alu_b_n33; + wire alu_b_n34; + wire alu_b_n35; + wire [7:0] alu_b_data_o; + wire alu_b_carry_o; + wire alu_b_aux_carry_o; + wire alu_b_da_overflow_o; + wire [7:0] bus_mux_b_n44; + wire [7:0] bus_mux_b_data_o; + wire clock_ctrl_b_n47; + wire [2:0] clock_ctrl_b_n49; + wire clock_ctrl_b_n50; + wire clock_ctrl_b_n51; + wire clock_ctrl_b_n53; + wire clock_ctrl_b_xtal3_o; + wire clock_ctrl_b_t0_o; + wire [2:0] clock_ctrl_b_mstate_o; + wire clock_ctrl_b_second_cycle_o; + wire clock_ctrl_b_ale_o; + wire clock_ctrl_b_psen_o; + wire clock_ctrl_b_prog_o; + wire clock_ctrl_b_rd_o; + wire clock_ctrl_b_wr_o; + wire cond_branch_b_n70; + wire cond_branch_b_take_branch_o; + wire [7:0] db_bus_b_n73; + wire db_bus_b_n74; + wire db_bus_b_n75; + wire db_bus_b_n76; + wire db_bus_b_n77; + wire db_bus_b_n78; + wire db_bus_b_n79; + wire db_bus_b_n80; + wire db_bus_b_n81; + wire db_bus_b_n82; + wire n83_o; + wire [7:0] db_bus_b_n84; + wire db_bus_b_n85; + wire [7:0] db_bus_b_data_o; + wire db_bus_b_set_f1_o; + wire db_bus_b_clear_f1_o; + wire db_bus_b_ibf_o; + wire db_bus_b_obf_o; + wire db_bus_b_int_n_o; + wire db_bus_b_mint_ibf_n_o; + wire db_bus_b_mint_obf_o; + wire db_bus_b_dma_o; + wire db_bus_b_drq_o; + wire [7:0] db_bus_b_db_o; + wire db_bus_b_db_dir_o; + wire [7:0] decoder_b_n111; + wire decoder_b_n112; + wire decoder_b_n113; + wire decoder_b_n114; + wire decoder_b_n115; + wire decoder_b_n116; + wire decoder_b_n117; + wire decoder_b_n118; + wire decoder_b_n119; + wire decoder_b_n120; + wire decoder_b_n121; + wire decoder_b_n122; + wire decoder_b_n123; + wire decoder_b_n124; + wire decoder_b_n125; + wire decoder_b_n126; + wire decoder_b_n127; + wire decoder_b_n128; + wire decoder_b_n129; + wire decoder_b_n130; + wire decoder_b_n131; + wire decoder_b_n132; + wire decoder_b_n133; + wire decoder_b_n134; + wire decoder_b_n135; + wire decoder_b_n136; + wire decoder_b_n137; + wire decoder_b_n138; + wire [3:0] decoder_b_n139; + wire decoder_b_n140; + wire decoder_b_n141; + wire decoder_b_n142; + wire decoder_b_n143; + wire decoder_b_n144; + wire decoder_b_n147; + wire decoder_b_n148; + wire decoder_b_n149; + wire decoder_b_n150; + wire decoder_b_n151; + wire decoder_b_n152; + wire [3:0] decoder_b_n153; + wire [2:0] decoder_b_n154; + wire decoder_b_n155; + wire decoder_b_n156; + wire [1:0] decoder_b_n157; + wire decoder_b_n158; + wire decoder_b_n159; + wire decoder_b_n160; + wire decoder_b_n161; + wire decoder_b_n162; + wire decoder_b_n163; + wire decoder_b_n164; + wire decoder_b_n165; + wire decoder_b_n166; + wire decoder_b_n167; + wire decoder_b_n168; + wire [1:0] decoder_b_n169; + wire decoder_b_n170; + wire decoder_b_n171; + wire decoder_b_n172; + wire decoder_b_n173; + wire decoder_b_n174; + wire decoder_b_n175; + wire decoder_b_n176; + wire decoder_b_t0_dir_o; + wire [7:0] decoder_b_data_o; + wire decoder_b_alu_write_accu_o; + wire decoder_b_alu_write_shadow_o; + wire decoder_b_alu_write_temp_reg_o; + wire decoder_b_alu_read_alu_o; + wire decoder_b_bus_write_bus_o; + wire decoder_b_bus_read_bus_o; + wire decoder_b_bus_ibf_int_o; + wire decoder_b_bus_en_dma_o; + wire decoder_b_bus_en_flags_o; + wire decoder_b_bus_write_sts_o; + wire decoder_b_dm_write_dmem_addr_o; + wire decoder_b_dm_write_dmem_o; + wire decoder_b_dm_read_dmem_o; + wire decoder_b_p1_write_p1_o; + wire decoder_b_p1_read_p1_o; + wire decoder_b_p2_write_p2_o; + wire decoder_b_p2_write_exp_o; + wire decoder_b_p2_read_p2_o; + wire decoder_b_p2_read_exp_o; + wire decoder_b_pm_write_pcl_o; + wire decoder_b_pm_read_pcl_o; + wire decoder_b_pm_write_pch_o; + wire decoder_b_pm_read_pch_o; + wire decoder_b_pm_read_pmem_o; + wire decoder_b_psw_read_psw_o; + wire decoder_b_psw_read_sp_o; + wire decoder_b_psw_write_psw_o; + wire decoder_b_psw_write_sp_o; + wire [3:0] decoder_b_alu_op_o; + wire decoder_b_alu_use_carry_o; + wire decoder_b_alu_da_high_o; + wire decoder_b_alu_accu_low_o; + wire decoder_b_alu_p06_temp_reg_o; + wire decoder_b_alu_p60_temp_reg_o; + wire decoder_b_bus_output_pcl_o; + wire decoder_b_bus_bidir_bus_o; + wire decoder_b_clk_multi_cycle_o; + wire decoder_b_clk_assert_psen_o; + wire decoder_b_clk_assert_prog_o; + wire decoder_b_clk_assert_rd_o; + wire decoder_b_clk_assert_wr_o; + wire decoder_b_cnd_compute_take_o; + wire [3:0] decoder_b_cnd_branch_cond_o; + wire [2:0] decoder_b_cnd_comp_value_o; + wire decoder_b_cnd_f1_o; + wire decoder_b_cnd_tf_o; + wire [1:0] decoder_b_dm_addr_type_o; + wire decoder_b_p1_read_reg_o; + wire decoder_b_p2_read_reg_o; + wire decoder_b_p2_output_pch_o; + wire decoder_b_pm_inc_pc_o; + wire decoder_b_pm_write_pmem_addr_o; + wire [1:0] decoder_b_pm_addr_type_o; + wire decoder_b_psw_special_data_o; + wire decoder_b_psw_inc_stackp_o; + wire decoder_b_psw_dec_stackp_o; + wire decoder_b_psw_write_carry_o; + wire decoder_b_psw_write_aux_carry_o; + wire decoder_b_psw_write_f0_o; + wire decoder_b_psw_write_bs_o; + wire decoder_b_tim_read_timer_o; + wire decoder_b_tim_write_timer_o; + wire decoder_b_tim_start_t_o; + wire decoder_b_tim_start_cnt_o; + wire decoder_b_tim_stop_tcnt_o; + wire [7:0] dmem_ctrl_b_n308; + wire [7:0] dmem_ctrl_b_n309; + wire dmem_ctrl_b_n310; + wire [7:0] dmem_ctrl_b_n311; + wire [7:0] dmem_ctrl_b_data_o; + wire [7:0] dmem_ctrl_b_dmem_addr_o; + wire dmem_ctrl_b_dmem_we_o; + wire [7:0] dmem_ctrl_b_dmem_data_o; + wire [7:0] timer_b_n320; + wire timer_b_n321; + wire [7:0] timer_b_data_o; + wire timer_b_overflow_o; + wire n333_o; + wire [7:0] p1_b_n334; + wire [7:0] p1_b_n335; + wire p1_b_n336; + wire [7:0] p1_b_data_o; + wire [7:0] p1_b_p1_o; + wire p1_b_p1_low_imp_o; + wire [7:0] p2_b_n343; + wire [3:0] n344_o; + wire [7:0] p2_b_n345; + wire p2_b_n346; + wire p2_b_n347; + wire [7:0] p2_b_data_o; + wire [7:0] p2_b_p2_o; + wire p2_b_p2l_low_imp_o; + wire p2_b_p2h_low_imp_o; + wire n356_o; + wire n357_o; + wire n358_o; + wire n359_o; + wire [1:0] n360_o; + wire n361_o; + wire n362_o; + wire [2:0] n363_o; + wire n364_o; + wire n365_o; + wire [3:0] n366_o; + wire [3:0] n367_o; + wire [7:0] n368_o; + wire [7:0] pmem_ctrl_b_n369; + wire [11:0] pmem_ctrl_b_n370; + wire [7:0] pmem_ctrl_b_data_o; + wire [11:0] pmem_ctrl_b_pmem_addr_o; + wire [7:0] psw_b_n375; + wire psw_b_n376; + wire psw_b_n377; + wire psw_b_n378; + wire psw_b_n379; + wire [7:0] psw_b_data_o; + wire psw_b_carry_o; + wire psw_b_aux_carry_o; + wire psw_b_f0_o; + wire psw_b_bs_o; + wire n391_o; + wire n398_o; + wire n406_o; + wire [10:0] n407_o; + assign sync_o = n14_o; + assign db_o = db_bus_b_n84; + assign db_dir_o = db_bus_b_n85; + assign p2_o = n368_o; + assign p2l_low_imp_o = p2_b_n346; + assign p2h_low_imp_o = p2_b_n347; + assign p1_o = p1_b_n335; + assign p1_low_imp_o = p1_b_n336; + assign prog_n_o = n398_o; + assign xtal3_o = n406_o; + assign dmem_addr_o = dmem_ctrl_b_n309; + assign dmem_we_o = dmem_ctrl_b_n310; + assign dmem_data_o = dmem_ctrl_b_n311; + assign pmem_addr_o = n407_o; + /* upi41_core.vhd:125:10 */ + assign t48_data_s = bus_mux_b_n44; // (signal) + /* upi41_core.vhd:127:10 */ + assign xtal_en_s = n23_o; // (signal) + /* upi41_core.vhd:128:10 */ + assign en_clk_s = n31_o; // (signal) + /* upi41_core.vhd:130:10 */ + assign t0_s = t0_i; // (signal) + /* upi41_core.vhd:130:16 */ + assign t1_s = t1_i; // (signal) + /* upi41_core.vhd:133:10 */ + assign alu_data_s = alu_b_n32; // (signal) + /* upi41_core.vhd:134:10 */ + assign alu_write_accu_s = decoder_b_n112; // (signal) + /* upi41_core.vhd:135:10 */ + assign alu_write_shadow_s = decoder_b_n113; // (signal) + /* upi41_core.vhd:136:10 */ + assign alu_write_temp_reg_s = decoder_b_n114; // (signal) + /* upi41_core.vhd:137:10 */ + assign alu_read_alu_s = decoder_b_n115; // (signal) + /* upi41_core.vhd:138:10 */ + assign alu_carry_s = alu_b_n33; // (signal) + /* upi41_core.vhd:139:10 */ + assign alu_aux_carry_s = alu_b_n34; // (signal) + /* upi41_core.vhd:140:10 */ + assign alu_op_s = decoder_b_n139; // (signal) + /* upi41_core.vhd:141:10 */ + assign alu_use_carry_s = decoder_b_n144; // (signal) + /* upi41_core.vhd:142:10 */ + assign alu_da_high_s = decoder_b_n140; // (signal) + /* upi41_core.vhd:143:10 */ + assign alu_da_overflow_s = alu_b_n35; // (signal) + /* upi41_core.vhd:144:10 */ + assign alu_accu_low_s = decoder_b_n141; // (signal) + /* upi41_core.vhd:145:10 */ + assign alu_p06_temp_reg_s = decoder_b_n142; // (signal) + /* upi41_core.vhd:146:10 */ + assign alu_p60_temp_reg_s = decoder_b_n143; // (signal) + /* upi41_core.vhd:149:10 */ + assign bus_write_bus_s = decoder_b_n116; // (signal) + /* upi41_core.vhd:150:10 */ + assign bus_read_bus_s = decoder_b_n117; // (signal) + /* upi41_core.vhd:151:10 */ + assign bus_data_s = db_bus_b_n73; // (signal) + /* upi41_core.vhd:153:10 */ + assign bus_ibf_s = db_bus_b_n76; // (signal) + /* upi41_core.vhd:154:10 */ + assign bus_obf_s = db_bus_b_n77; // (signal) + /* upi41_core.vhd:155:10 */ + assign bus_int_n_s = db_bus_b_n78; // (signal) + /* upi41_core.vhd:156:10 */ + assign bus_set_f1_s = db_bus_b_n74; // (signal) + /* upi41_core.vhd:157:10 */ + assign bus_clear_f1_s = db_bus_b_n75; // (signal) + /* upi41_core.vhd:158:10 */ + assign bus_ibf_int_s = decoder_b_n118; // (signal) + /* upi41_core.vhd:159:10 */ + assign bus_en_dma_s = decoder_b_n119; // (signal) + /* upi41_core.vhd:160:10 */ + assign bus_en_flags_s = decoder_b_n120; // (signal) + /* upi41_core.vhd:161:10 */ + assign bus_write_sts_s = decoder_b_n121; // (signal) + /* upi41_core.vhd:162:10 */ + assign bus_mint_ibf_n_s = db_bus_b_n79; // (signal) + /* upi41_core.vhd:163:10 */ + assign bus_mint_obf_s = db_bus_b_n80; // (signal) + /* upi41_core.vhd:164:10 */ + assign bus_dma_s = db_bus_b_n81; // (signal) + /* upi41_core.vhd:165:10 */ + assign bus_drq_s = db_bus_b_n82; // (signal) + /* upi41_core.vhd:168:10 */ + assign clk_multi_cycle_s = decoder_b_n147; // (signal) + /* upi41_core.vhd:169:10 */ + assign clk_assert_psen_s = decoder_b_n148; // (signal) + /* upi41_core.vhd:170:10 */ + assign clk_assert_prog_s = decoder_b_n149; // (signal) + /* upi41_core.vhd:171:10 */ + assign clk_assert_rd_s = decoder_b_n150; // (signal) + /* upi41_core.vhd:172:10 */ + assign clk_assert_wr_s = decoder_b_n151; // (signal) + /* upi41_core.vhd:173:10 */ + assign clk_mstate_s = clock_ctrl_b_n49; // (signal) + /* upi41_core.vhd:174:10 */ + assign clk_second_cycle_s = clock_ctrl_b_n50; // (signal) + /* upi41_core.vhd:175:10 */ + assign prog_s = clock_ctrl_b_n53; // (signal) + /* upi41_core.vhd:176:10 */ + assign ale_s = clock_ctrl_b_n51; // (signal) + /* upi41_core.vhd:177:10 */ + assign xtal3_s = clock_ctrl_b_n47; // (signal) + /* upi41_core.vhd:180:10 */ + assign cnd_compute_take_s = decoder_b_n152; // (signal) + /* upi41_core.vhd:181:10 */ + assign cnd_branch_cond_s = decoder_b_n153; // (signal) + /* upi41_core.vhd:182:10 */ + assign cnd_take_branch_s = cond_branch_b_n70; // (signal) + /* upi41_core.vhd:183:10 */ + assign cnd_comp_value_s = decoder_b_n154; // (signal) + /* upi41_core.vhd:184:10 */ + assign cnd_f1_s = decoder_b_n155; // (signal) + /* upi41_core.vhd:185:10 */ + assign cnd_tf_s = decoder_b_n156; // (signal) + /* upi41_core.vhd:188:10 */ + assign dm_write_dmem_addr_s = decoder_b_n122; // (signal) + /* upi41_core.vhd:189:10 */ + assign dm_write_dmem_s = decoder_b_n123; // (signal) + /* upi41_core.vhd:190:10 */ + assign dm_read_dmem_s = decoder_b_n124; // (signal) + /* upi41_core.vhd:191:10 */ + assign dm_addr_type_s = decoder_b_n157; // (signal) + /* upi41_core.vhd:192:10 */ + assign dm_data_s = dmem_ctrl_b_n308; // (signal) + /* upi41_core.vhd:195:10 */ + assign dec_data_s = decoder_b_n111; // (signal) + /* upi41_core.vhd:198:10 */ + assign p1_write_p1_s = decoder_b_n125; // (signal) + /* upi41_core.vhd:199:10 */ + assign p1_read_p1_s = decoder_b_n126; // (signal) + /* upi41_core.vhd:200:10 */ + assign p1_read_reg_s = decoder_b_n163; // (signal) + /* upi41_core.vhd:201:10 */ + assign p1_data_s = p1_b_n334; // (signal) + /* upi41_core.vhd:204:10 */ + assign p2_s = p2_b_n345; // (signal) + /* upi41_core.vhd:205:10 */ + assign p26_s = n358_o; // (signal) + /* upi41_core.vhd:206:10 */ + assign p2_write_p2_s = decoder_b_n127; // (signal) + /* upi41_core.vhd:207:10 */ + assign p2_write_exp_s = decoder_b_n128; // (signal) + /* upi41_core.vhd:208:10 */ + assign p2_read_p2_s = decoder_b_n129; // (signal) + /* upi41_core.vhd:209:10 */ + assign p2_read_reg_s = decoder_b_n164; // (signal) + /* upi41_core.vhd:210:10 */ + assign p2_read_exp_s = decoder_b_n165; // (signal) + /* upi41_core.vhd:211:10 */ + assign p2_output_pch_s = decoder_b_n166; // (signal) + /* upi41_core.vhd:212:10 */ + assign p2_data_s = p2_b_n343; // (signal) + /* upi41_core.vhd:215:10 */ + assign pm_write_pcl_s = decoder_b_n130; // (signal) + /* upi41_core.vhd:216:10 */ + assign pm_read_pcl_s = decoder_b_n131; // (signal) + /* upi41_core.vhd:217:10 */ + assign pm_write_pch_s = decoder_b_n132; // (signal) + /* upi41_core.vhd:218:10 */ + assign pm_read_pch_s = decoder_b_n133; // (signal) + /* upi41_core.vhd:219:10 */ + assign pm_read_pmem_s = decoder_b_n134; // (signal) + /* upi41_core.vhd:220:10 */ + assign pm_inc_pc_s = decoder_b_n167; // (signal) + /* upi41_core.vhd:221:10 */ + assign pm_write_pmem_addr_s = decoder_b_n168; // (signal) + /* upi41_core.vhd:222:10 */ + assign pm_data_s = pmem_ctrl_b_n369; // (signal) + /* upi41_core.vhd:223:10 */ + assign pm_addr_type_s = decoder_b_n169; // (signal) + /* upi41_core.vhd:224:10 */ + assign pmem_addr_s = pmem_ctrl_b_n370; // (signal) + /* upi41_core.vhd:227:10 */ + assign psw_read_psw_s = decoder_b_n135; // (signal) + /* upi41_core.vhd:228:10 */ + assign psw_read_sp_s = decoder_b_n136; // (signal) + /* upi41_core.vhd:229:10 */ + assign psw_write_psw_s = decoder_b_n137; // (signal) + /* upi41_core.vhd:230:10 */ + assign psw_write_sp_s = decoder_b_n138; // (signal) + /* upi41_core.vhd:231:10 */ + assign psw_carry_s = psw_b_n376; // (signal) + /* upi41_core.vhd:232:10 */ + assign psw_aux_carry_s = psw_b_n377; // (signal) + /* upi41_core.vhd:233:10 */ + assign psw_f0_s = psw_b_n378; // (signal) + /* upi41_core.vhd:234:10 */ + assign psw_bs_s = psw_b_n379; // (signal) + /* upi41_core.vhd:235:10 */ + assign psw_special_data_s = decoder_b_n170; // (signal) + /* upi41_core.vhd:236:10 */ + assign psw_inc_stackp_s = decoder_b_n171; // (signal) + /* upi41_core.vhd:237:10 */ + assign psw_dec_stackp_s = decoder_b_n172; // (signal) + /* upi41_core.vhd:238:10 */ + assign psw_write_carry_s = decoder_b_n173; // (signal) + /* upi41_core.vhd:239:10 */ + assign psw_write_aux_carry_s = decoder_b_n174; // (signal) + /* upi41_core.vhd:240:10 */ + assign psw_write_f0_s = decoder_b_n175; // (signal) + /* upi41_core.vhd:241:10 */ + assign psw_write_bs_s = decoder_b_n176; // (signal) + /* upi41_core.vhd:242:10 */ + assign psw_data_s = psw_b_n375; // (signal) + /* upi41_core.vhd:245:10 */ + assign tim_overflow_s = n333_o; // (signal) + /* upi41_core.vhd:246:10 */ + assign tim_of_s = timer_b_n321; // (signal) + /* upi41_core.vhd:247:10 */ + assign tim_read_timer_s = decoder_b_n158; // (signal) + /* upi41_core.vhd:248:10 */ + assign tim_write_timer_s = decoder_b_n159; // (signal) + /* upi41_core.vhd:249:10 */ + assign tim_start_t_s = decoder_b_n160; // (signal) + /* upi41_core.vhd:250:10 */ + assign tim_start_cnt_s = decoder_b_n161; // (signal) + /* upi41_core.vhd:251:10 */ + assign tim_stop_tcnt_s = decoder_b_n162; // (signal) + /* upi41_core.vhd:252:10 */ + assign tim_data_s = timer_b_n320; // (signal) + /* upi41_core.vhd:254:10 */ + assign gnd_s = 1'b0; // (signal) + /* t48_pack-p.vhd:75:5 */ + assign n23_o = xtal_en_i ? 1'b1 : 1'b0; + /* t48_pack-p.vhd:75:5 */ + assign n31_o = en_clk_i ? 1'b1 : 1'b0; + /* upi41_core.vhd:278:29 */ + assign alu_b_n32 = alu_b_data_o; // (signal) + /* upi41_core.vhd:284:29 */ + assign alu_b_n33 = alu_b_carry_o; // (signal) + /* upi41_core.vhd:285:29 */ + assign alu_b_n34 = alu_b_aux_carry_o; // (signal) + /* upi41_core.vhd:289:29 */ + assign alu_b_n35 = alu_b_da_overflow_o; // (signal) + /* upi41_core.vhd:272:3 */ + t48_alu alu_b ( + .clk_i(clk_i), + .res_i(reset_i), + .en_clk_i(en_clk_s), + .data_i(t48_data_s), + .write_accu_i(alu_write_accu_s), + .write_shadow_i(alu_write_shadow_s), + .write_temp_reg_i(alu_write_temp_reg_s), + .read_alu_i(alu_read_alu_s), + .carry_i(psw_carry_s), + .alu_op_i(alu_op_s), + .use_carry_i(alu_use_carry_s), + .da_high_i(alu_da_high_s), + .accu_low_i(alu_accu_low_s), + .p06_temp_reg_i(alu_p06_temp_reg_s), + .p60_temp_reg_i(alu_p60_temp_reg_s), + .data_o(alu_b_data_o), + .carry_o(alu_b_carry_o), + .aux_carry_o(alu_b_aux_carry_o), + .da_overflow_o(alu_b_da_overflow_o)); + /* upi41_core.vhd:306:21 */ + assign bus_mux_b_n44 = bus_mux_b_data_o; // (signal) + /* upi41_core.vhd:295:3 */ + t48_bus_mux bus_mux_b ( + .alu_data_i(alu_data_s), + .bus_data_i(bus_data_s), + .dec_data_i(dec_data_s), + .dm_data_i(dm_data_s), + .pm_data_i(pm_data_s), + .p1_data_i(p1_data_s), + .p2_data_i(p2_data_s), + .psw_data_i(psw_data_s), + .tim_data_i(tim_data_s), + .data_o(bus_mux_b_data_o)); + /* upi41_core.vhd:319:25 */ + assign clock_ctrl_b_n47 = clock_ctrl_b_xtal3_o; // (signal) + /* upi41_core.vhd:326:25 */ + assign clock_ctrl_b_n49 = clock_ctrl_b_mstate_o; // (signal) + /* upi41_core.vhd:327:25 */ + assign clock_ctrl_b_n50 = clock_ctrl_b_second_cycle_o; // (signal) + /* upi41_core.vhd:328:25 */ + assign clock_ctrl_b_n51 = clock_ctrl_b_ale_o; // (signal) + /* upi41_core.vhd:330:25 */ + assign clock_ctrl_b_n53 = clock_ctrl_b_prog_o; // (signal) + /* upi41_core.vhd:309:3 */ + t48_clock_ctrl_1 clock_ctrl_b ( + .clk_i(clk_i), + .xtal_i(xtal_i), + .xtal_en_i(xtal_en_s), + .res_i(reset_i), + .en_clk_i(en_clk_s), + .multi_cycle_i(clk_multi_cycle_s), + .assert_psen_i(clk_assert_psen_s), + .assert_prog_i(clk_assert_prog_s), + .assert_rd_i(clk_assert_rd_s), + .assert_wr_i(clk_assert_wr_s), + .xtal3_o(clock_ctrl_b_xtal3_o), + .t0_o(), + .mstate_o(clock_ctrl_b_mstate_o), + .second_cycle_o(clock_ctrl_b_second_cycle_o), + .ale_o(clock_ctrl_b_ale_o), + .psen_o(), + .prog_o(clock_ctrl_b_prog_o), + .rd_o(), + .wr_o()); + /* upi41_core.vhd:342:25 */ + assign cond_branch_b_n70 = cond_branch_b_take_branch_o; // (signal) + /* upi41_core.vhd:335:3 */ + t48_cond_branch cond_branch_b ( + .clk_i(clk_i), + .res_i(reset_i), + .en_clk_i(en_clk_s), + .compute_take_i(cnd_compute_take_s), + .branch_cond_i(cnd_branch_cond_s), + .accu_i(alu_data_s), + .t0_i(t0_s), + .t1_i(t1_s), + .int_n_i(bus_int_n_s), + .f0_i(psw_f0_s), + .f1_i(cnd_f1_s), + .tf_i(cnd_tf_s), + .carry_i(psw_carry_s), + .ibf_i(bus_ibf_s), + .obf_i(bus_obf_s), + .comp_value_i(cnd_comp_value_s), + .take_branch_o(cond_branch_b_take_branch_o)); + /* upi41_core.vhd:365:25 */ + assign db_bus_b_n73 = db_bus_b_data_o; // (signal) + /* upi41_core.vhd:369:25 */ + assign db_bus_b_n74 = db_bus_b_set_f1_o; // (signal) + /* upi41_core.vhd:370:25 */ + assign db_bus_b_n75 = db_bus_b_clear_f1_o; // (signal) + /* upi41_core.vhd:373:25 */ + assign db_bus_b_n76 = db_bus_b_ibf_o; // (signal) + /* upi41_core.vhd:374:25 */ + assign db_bus_b_n77 = db_bus_b_obf_o; // (signal) + /* upi41_core.vhd:375:25 */ + assign db_bus_b_n78 = db_bus_b_int_n_o; // (signal) + /* upi41_core.vhd:380:25 */ + assign db_bus_b_n79 = db_bus_b_mint_ibf_n_o; // (signal) + /* upi41_core.vhd:381:25 */ + assign db_bus_b_n80 = db_bus_b_mint_obf_o; // (signal) + /* upi41_core.vhd:382:25 */ + assign db_bus_b_n81 = db_bus_b_dma_o; // (signal) + /* upi41_core.vhd:383:25 */ + assign db_bus_b_n82 = db_bus_b_drq_o; // (signal) + /* upi41_core.vhd:384:29 */ + assign n83_o = p2_i[7]; + /* upi41_core.vhd:390:25 */ + assign db_bus_b_n84 = db_bus_b_db_o; // (signal) + /* upi41_core.vhd:391:25 */ + assign db_bus_b_n85 = db_bus_b_db_dir_o; // (signal) + /* upi41_core.vhd:356:5 */ + upi41_db_bus_1 db_bus_b ( + .clk_i(clk_i), + .res_i(reset_i), + .en_clk_i(en_clk_s), + .data_i(t48_data_s), + .write_bus_i(bus_write_bus_s), + .read_bus_i(bus_read_bus_s), + .write_sts_i(bus_write_sts_s), + .f0_i(psw_f0_s), + .f1_i(cnd_f1_s), + .ibf_int_i(bus_ibf_int_s), + .en_dma_i(bus_en_dma_s), + .en_flags_i(bus_en_flags_s), + .write_p2_i(p2_write_p2_s), + .dack_n_i(n83_o), + .a0_i(a0_i), + .cs_n_i(cs_n_i), + .rd_n_i(rd_n_i), + .wr_n_i(wr_n_i), + .db_i(db_i), + .data_o(db_bus_b_data_o), + .set_f1_o(db_bus_b_set_f1_o), + .clear_f1_o(db_bus_b_clear_f1_o), + .ibf_o(db_bus_b_ibf_o), + .obf_o(db_bus_b_obf_o), + .int_n_o(db_bus_b_int_n_o), + .mint_ibf_n_o(db_bus_b_mint_ibf_n_o), + .mint_obf_o(db_bus_b_mint_obf_o), + .dma_o(db_bus_b_dma_o), + .drq_o(db_bus_b_drq_o), + .db_o(db_bus_b_db_o), + .db_dir_o(db_bus_b_db_dir_o)); + /* upi41_core.vhd:411:33 */ + assign decoder_b_n111 = decoder_b_data_o; // (signal) + /* upi41_core.vhd:412:33 */ + assign decoder_b_n112 = decoder_b_alu_write_accu_o; // (signal) + /* upi41_core.vhd:413:33 */ + assign decoder_b_n113 = decoder_b_alu_write_shadow_o; // (signal) + /* upi41_core.vhd:414:33 */ + assign decoder_b_n114 = decoder_b_alu_write_temp_reg_o; // (signal) + /* upi41_core.vhd:415:33 */ + assign decoder_b_n115 = decoder_b_alu_read_alu_o; // (signal) + /* upi41_core.vhd:416:33 */ + assign decoder_b_n116 = decoder_b_bus_write_bus_o; // (signal) + /* upi41_core.vhd:417:33 */ + assign decoder_b_n117 = decoder_b_bus_read_bus_o; // (signal) + /* upi41_core.vhd:420:33 */ + assign decoder_b_n118 = decoder_b_bus_ibf_int_o; // (signal) + /* upi41_core.vhd:421:33 */ + assign decoder_b_n119 = decoder_b_bus_en_dma_o; // (signal) + /* upi41_core.vhd:422:33 */ + assign decoder_b_n120 = decoder_b_bus_en_flags_o; // (signal) + /* upi41_core.vhd:423:33 */ + assign decoder_b_n121 = decoder_b_bus_write_sts_o; // (signal) + /* upi41_core.vhd:424:33 */ + assign decoder_b_n122 = decoder_b_dm_write_dmem_addr_o; // (signal) + /* upi41_core.vhd:425:33 */ + assign decoder_b_n123 = decoder_b_dm_write_dmem_o; // (signal) + /* upi41_core.vhd:426:33 */ + assign decoder_b_n124 = decoder_b_dm_read_dmem_o; // (signal) + /* upi41_core.vhd:427:33 */ + assign decoder_b_n125 = decoder_b_p1_write_p1_o; // (signal) + /* upi41_core.vhd:428:33 */ + assign decoder_b_n126 = decoder_b_p1_read_p1_o; // (signal) + /* upi41_core.vhd:430:33 */ + assign decoder_b_n127 = decoder_b_p2_write_p2_o; // (signal) + /* upi41_core.vhd:431:33 */ + assign decoder_b_n128 = decoder_b_p2_write_exp_o; // (signal) + /* upi41_core.vhd:432:33 */ + assign decoder_b_n129 = decoder_b_p2_read_p2_o; // (signal) + /* upi41_core.vhd:429:33 */ + assign decoder_b_n130 = decoder_b_pm_write_pcl_o; // (signal) + /* upi41_core.vhd:433:33 */ + assign decoder_b_n131 = decoder_b_pm_read_pcl_o; // (signal) + /* upi41_core.vhd:434:33 */ + assign decoder_b_n132 = decoder_b_pm_write_pch_o; // (signal) + /* upi41_core.vhd:435:33 */ + assign decoder_b_n133 = decoder_b_pm_read_pch_o; // (signal) + /* upi41_core.vhd:436:33 */ + assign decoder_b_n134 = decoder_b_pm_read_pmem_o; // (signal) + /* upi41_core.vhd:437:33 */ + assign decoder_b_n135 = decoder_b_psw_read_psw_o; // (signal) + /* upi41_core.vhd:438:33 */ + assign decoder_b_n136 = decoder_b_psw_read_sp_o; // (signal) + /* upi41_core.vhd:439:33 */ + assign decoder_b_n137 = decoder_b_psw_write_psw_o; // (signal) + /* upi41_core.vhd:440:33 */ + assign decoder_b_n138 = decoder_b_psw_write_sp_o; // (signal) + /* upi41_core.vhd:442:33 */ + assign decoder_b_n139 = decoder_b_alu_op_o; // (signal) + /* upi41_core.vhd:444:33 */ + assign decoder_b_n140 = decoder_b_alu_da_high_o; // (signal) + /* upi41_core.vhd:446:33 */ + assign decoder_b_n141 = decoder_b_alu_accu_low_o; // (signal) + /* upi41_core.vhd:447:33 */ + assign decoder_b_n142 = decoder_b_alu_p06_temp_reg_o; // (signal) + /* upi41_core.vhd:448:33 */ + assign decoder_b_n143 = decoder_b_alu_p60_temp_reg_o; // (signal) + /* upi41_core.vhd:443:33 */ + assign decoder_b_n144 = decoder_b_alu_use_carry_o; // (signal) + /* upi41_core.vhd:451:33 */ + assign decoder_b_n147 = decoder_b_clk_multi_cycle_o; // (signal) + /* upi41_core.vhd:452:33 */ + assign decoder_b_n148 = decoder_b_clk_assert_psen_o; // (signal) + /* upi41_core.vhd:453:33 */ + assign decoder_b_n149 = decoder_b_clk_assert_prog_o; // (signal) + /* upi41_core.vhd:454:33 */ + assign decoder_b_n150 = decoder_b_clk_assert_rd_o; // (signal) + /* upi41_core.vhd:455:33 */ + assign decoder_b_n151 = decoder_b_clk_assert_wr_o; // (signal) + /* upi41_core.vhd:458:33 */ + assign decoder_b_n152 = decoder_b_cnd_compute_take_o; // (signal) + /* upi41_core.vhd:459:33 */ + assign decoder_b_n153 = decoder_b_cnd_branch_cond_o; // (signal) + /* upi41_core.vhd:461:33 */ + assign decoder_b_n154 = decoder_b_cnd_comp_value_o; // (signal) + /* upi41_core.vhd:462:33 */ + assign decoder_b_n155 = decoder_b_cnd_f1_o; // (signal) + /* upi41_core.vhd:463:33 */ + assign decoder_b_n156 = decoder_b_cnd_tf_o; // (signal) + /* upi41_core.vhd:464:33 */ + assign decoder_b_n157 = decoder_b_dm_addr_type_o; // (signal) + /* upi41_core.vhd:465:33 */ + assign decoder_b_n158 = decoder_b_tim_read_timer_o; // (signal) + /* upi41_core.vhd:466:33 */ + assign decoder_b_n159 = decoder_b_tim_write_timer_o; // (signal) + /* upi41_core.vhd:467:33 */ + assign decoder_b_n160 = decoder_b_tim_start_t_o; // (signal) + /* upi41_core.vhd:468:33 */ + assign decoder_b_n161 = decoder_b_tim_start_cnt_o; // (signal) + /* upi41_core.vhd:469:33 */ + assign decoder_b_n162 = decoder_b_tim_stop_tcnt_o; // (signal) + /* upi41_core.vhd:470:33 */ + assign decoder_b_n163 = decoder_b_p1_read_reg_o; // (signal) + /* upi41_core.vhd:471:33 */ + assign decoder_b_n164 = decoder_b_p2_read_reg_o; // (signal) + /* upi41_core.vhd:472:33 */ + assign decoder_b_n165 = decoder_b_p2_read_exp_o; // (signal) + /* upi41_core.vhd:473:33 */ + assign decoder_b_n166 = decoder_b_p2_output_pch_o; // (signal) + /* upi41_core.vhd:474:33 */ + assign decoder_b_n167 = decoder_b_pm_inc_pc_o; // (signal) + /* upi41_core.vhd:475:33 */ + assign decoder_b_n168 = decoder_b_pm_write_pmem_addr_o; // (signal) + /* upi41_core.vhd:476:33 */ + assign decoder_b_n169 = decoder_b_pm_addr_type_o; // (signal) + /* upi41_core.vhd:477:33 */ + assign decoder_b_n170 = decoder_b_psw_special_data_o; // (signal) + /* upi41_core.vhd:481:33 */ + assign decoder_b_n171 = decoder_b_psw_inc_stackp_o; // (signal) + /* upi41_core.vhd:482:33 */ + assign decoder_b_n172 = decoder_b_psw_dec_stackp_o; // (signal) + /* upi41_core.vhd:483:33 */ + assign decoder_b_n173 = decoder_b_psw_write_carry_o; // (signal) + /* upi41_core.vhd:484:33 */ + assign decoder_b_n174 = decoder_b_psw_write_aux_carry_o; // (signal) + /* upi41_core.vhd:485:33 */ + assign decoder_b_n175 = decoder_b_psw_write_f0_o; // (signal) + /* upi41_core.vhd:486:33 */ + assign decoder_b_n176 = decoder_b_psw_write_bs_o; // (signal) + /* upi41_core.vhd:394:3 */ + t48_decoder_1_1_1 decoder_b ( + .clk_i(clk_i), + .res_i(reset_i), + .en_clk_i(en_clk_s), + .xtal_i(xtal_i), + .xtal_en_i(xtal_en_s), + .ea_i(gnd_s), + .ale_i(ale_s), + .int_n_i(bus_int_n_s), + .data_i(t48_data_s), + .bus_set_f1_i(bus_set_f1_s), + .bus_clear_f1_i(bus_clear_f1_s), + .alu_carry_i(alu_carry_s), + .alu_da_overflow_i(alu_da_overflow_s), + .clk_mstate_i(clk_mstate_s), + .clk_second_cycle_i(clk_second_cycle_s), + .cnd_take_branch_i(cnd_take_branch_s), + .psw_carry_i(psw_carry_s), + .psw_aux_carry_i(psw_aux_carry_s), + .psw_f0_i(psw_f0_s), + .tim_overflow_i(tim_overflow_s), + .t0_dir_o(), + .data_o(decoder_b_data_o), + .alu_write_accu_o(decoder_b_alu_write_accu_o), + .alu_write_shadow_o(decoder_b_alu_write_shadow_o), + .alu_write_temp_reg_o(decoder_b_alu_write_temp_reg_o), + .alu_read_alu_o(decoder_b_alu_read_alu_o), + .bus_write_bus_o(decoder_b_bus_write_bus_o), + .bus_read_bus_o(decoder_b_bus_read_bus_o), + .bus_ibf_int_o(decoder_b_bus_ibf_int_o), + .bus_en_dma_o(decoder_b_bus_en_dma_o), + .bus_en_flags_o(decoder_b_bus_en_flags_o), + .bus_write_sts_o(decoder_b_bus_write_sts_o), + .dm_write_dmem_addr_o(decoder_b_dm_write_dmem_addr_o), + .dm_write_dmem_o(decoder_b_dm_write_dmem_o), + .dm_read_dmem_o(decoder_b_dm_read_dmem_o), + .p1_write_p1_o(decoder_b_p1_write_p1_o), + .p1_read_p1_o(decoder_b_p1_read_p1_o), + .p2_write_p2_o(decoder_b_p2_write_p2_o), + .p2_write_exp_o(decoder_b_p2_write_exp_o), + .p2_read_p2_o(decoder_b_p2_read_p2_o), + .p2_read_exp_o(decoder_b_p2_read_exp_o), + .pm_write_pcl_o(decoder_b_pm_write_pcl_o), + .pm_read_pcl_o(decoder_b_pm_read_pcl_o), + .pm_write_pch_o(decoder_b_pm_write_pch_o), + .pm_read_pch_o(decoder_b_pm_read_pch_o), + .pm_read_pmem_o(decoder_b_pm_read_pmem_o), + .psw_read_psw_o(decoder_b_psw_read_psw_o), + .psw_read_sp_o(decoder_b_psw_read_sp_o), + .psw_write_psw_o(decoder_b_psw_write_psw_o), + .psw_write_sp_o(decoder_b_psw_write_sp_o), + .alu_op_o(decoder_b_alu_op_o), + .alu_use_carry_o(decoder_b_alu_use_carry_o), + .alu_da_high_o(decoder_b_alu_da_high_o), + .alu_accu_low_o(decoder_b_alu_accu_low_o), + .alu_p06_temp_reg_o(decoder_b_alu_p06_temp_reg_o), + .alu_p60_temp_reg_o(decoder_b_alu_p60_temp_reg_o), + .bus_output_pcl_o(), + .bus_bidir_bus_o(), + .clk_multi_cycle_o(decoder_b_clk_multi_cycle_o), + .clk_assert_psen_o(decoder_b_clk_assert_psen_o), + .clk_assert_prog_o(decoder_b_clk_assert_prog_o), + .clk_assert_rd_o(decoder_b_clk_assert_rd_o), + .clk_assert_wr_o(decoder_b_clk_assert_wr_o), + .cnd_compute_take_o(decoder_b_cnd_compute_take_o), + .cnd_branch_cond_o(decoder_b_cnd_branch_cond_o), + .cnd_comp_value_o(decoder_b_cnd_comp_value_o), + .cnd_f1_o(decoder_b_cnd_f1_o), + .cnd_tf_o(decoder_b_cnd_tf_o), + .dm_addr_type_o(decoder_b_dm_addr_type_o), + .p1_read_reg_o(decoder_b_p1_read_reg_o), + .p2_read_reg_o(decoder_b_p2_read_reg_o), + .p2_output_pch_o(decoder_b_p2_output_pch_o), + .pm_inc_pc_o(decoder_b_pm_inc_pc_o), + .pm_write_pmem_addr_o(decoder_b_pm_write_pmem_addr_o), + .pm_addr_type_o(decoder_b_pm_addr_type_o), + .psw_special_data_o(decoder_b_psw_special_data_o), + .psw_inc_stackp_o(decoder_b_psw_inc_stackp_o), + .psw_dec_stackp_o(decoder_b_psw_dec_stackp_o), + .psw_write_carry_o(decoder_b_psw_write_carry_o), + .psw_write_aux_carry_o(decoder_b_psw_write_aux_carry_o), + .psw_write_f0_o(decoder_b_psw_write_f0_o), + .psw_write_bs_o(decoder_b_psw_write_bs_o), + .tim_read_timer_o(decoder_b_tim_read_timer_o), + .tim_write_timer_o(decoder_b_tim_write_timer_o), + .tim_start_t_o(decoder_b_tim_start_t_o), + .tim_start_cnt_o(decoder_b_tim_start_cnt_o), + .tim_stop_tcnt_o(decoder_b_tim_stop_tcnt_o)); + /* upi41_core.vhd:501:28 */ + assign dmem_ctrl_b_n308 = dmem_ctrl_b_data_o; // (signal) + /* upi41_core.vhd:503:28 */ + assign dmem_ctrl_b_n309 = dmem_ctrl_b_dmem_addr_o; // (signal) + /* upi41_core.vhd:504:28 */ + assign dmem_ctrl_b_n310 = dmem_ctrl_b_dmem_we_o; // (signal) + /* upi41_core.vhd:505:28 */ + assign dmem_ctrl_b_n311 = dmem_ctrl_b_dmem_data_o; // (signal) + /* upi41_core.vhd:490:3 */ + t48_dmem_ctrl dmem_ctrl_b ( + .clk_i(clk_i), + .res_i(reset_i), + .en_clk_i(en_clk_s), + .data_i(t48_data_s), + .write_dmem_addr_i(dm_write_dmem_addr_s), + .write_dmem_i(dm_write_dmem_s), + .read_dmem_i(dm_read_dmem_s), + .addr_type_i(dm_addr_type_s), + .bank_select_i(psw_bs_s), + .dmem_data_i(dmem_data_i), + .data_o(dmem_ctrl_b_data_o), + .dmem_addr_o(dmem_ctrl_b_dmem_addr_o), + .dmem_we_o(dmem_ctrl_b_dmem_we_o), + .dmem_data_o(dmem_ctrl_b_dmem_data_o)); + /* upi41_core.vhd:519:24 */ + assign timer_b_n320 = timer_b_data_o; // (signal) + /* upi41_core.vhd:525:24 */ + assign timer_b_n321 = timer_b_overflow_o; // (signal) + /* upi41_core.vhd:508:3 */ + t48_timer_4 timer_b ( + .clk_i(clk_i), + .res_i(reset_i), + .en_clk_i(en_clk_s), + .t1_i(t1_s), + .clk_mstate_i(clk_mstate_s), + .data_i(t48_data_s), + .read_timer_i(tim_read_timer_s), + .write_timer_i(tim_write_timer_s), + .start_t_i(tim_start_t_s), + .start_cnt_i(tim_start_cnt_s), + .stop_tcnt_i(tim_stop_tcnt_s), + .data_o(timer_b_data_o), + .overflow_o(timer_b_overflow_o)); + /* t48_pack-p.vhd:75:5 */ + assign n333_o = tim_of_s ? 1'b1 : 1'b0; + /* upi41_core.vhd:536:23 */ + assign p1_b_n334 = p1_b_data_o; // (signal) + /* upi41_core.vhd:541:23 */ + assign p1_b_n335 = p1_b_p1_o; // (signal) + /* upi41_core.vhd:542:23 */ + assign p1_b_n336 = p1_b_p1_low_imp_o; // (signal) + /* upi41_core.vhd:530:3 */ + t48_p1 p1_b ( + .clk_i(clk_i), + .res_i(reset_i), + .en_clk_i(en_clk_s), + .data_i(t48_data_s), + .write_p1_i(p1_write_p1_s), + .read_p1_i(p1_read_p1_s), + .read_reg_i(p1_read_reg_s), + .p1_i(p1_i), + .data_o(p1_b_data_o), + .p1_o(p1_b_p1_o), + .p1_low_imp_o(p1_b_p1_low_imp_o)); + /* upi41_core.vhd:553:24 */ + assign p2_b_n343 = p2_b_data_o; // (signal) + /* upi41_core.vhd:560:35 */ + assign n344_o = pmem_addr_s[11:8]; + /* upi41_core.vhd:562:24 */ + assign p2_b_n345 = p2_b_p2_o; // (signal) + /* upi41_core.vhd:563:24 */ + assign p2_b_n346 = p2_b_p2l_low_imp_o; // (signal) + /* upi41_core.vhd:564:24 */ + assign p2_b_n347 = p2_b_p2h_low_imp_o; // (signal) + /* upi41_core.vhd:545:3 */ + t48_p2 p2_b ( + .clk_i(clk_i), + .res_i(reset_i), + .en_clk_i(en_clk_s), + .xtal_i(xtal_i), + .xtal_en_i(xtal_en_s), + .data_i(t48_data_s), + .write_p2_i(p2_write_p2_s), + .write_exp_i(p2_write_exp_s), + .read_p2_i(p2_read_p2_s), + .read_reg_i(p2_read_reg_s), + .read_exp_i(p2_read_exp_s), + .output_pch_i(p2_output_pch_s), + .pch_i(n344_o), + .p2_i(p2_i), + .data_o(p2_b_data_o), + .p2_o(p2_b_p2_o), + .p2l_low_imp_o(p2_b_p2l_low_imp_o), + .p2h_low_imp_o(p2_b_p2h_low_imp_o)); + /* upi41_core.vhd:567:16 */ + assign n356_o = p2_s[6]; + /* upi41_core.vhd:567:25 */ + assign n357_o = ~bus_dma_s; + /* upi41_core.vhd:567:20 */ + assign n358_o = n357_o ? n356_o : bus_drq_s; + /* upi41_core.vhd:568:17 */ + assign n359_o = p2_s[7]; + /* upi41_core.vhd:569:11 */ + assign n360_o = {n359_o, p26_s}; + /* upi41_core.vhd:570:18 */ + assign n361_o = p2_s[5]; + /* upi41_core.vhd:570:22 */ + assign n362_o = n361_o & bus_mint_ibf_n_s; + /* upi41_core.vhd:570:11 */ + assign n363_o = {n360_o, n362_o}; + /* upi41_core.vhd:571:18 */ + assign n364_o = p2_s[4]; + /* upi41_core.vhd:571:22 */ + assign n365_o = n364_o & bus_mint_obf_s; + /* upi41_core.vhd:571:11 */ + assign n366_o = {n363_o, n365_o}; + /* upi41_core.vhd:572:17 */ + assign n367_o = p2_s[3:0]; + /* upi41_core.vhd:572:11 */ + assign n368_o = {n366_o, n367_o}; + /* upi41_core.vhd:580:28 */ + assign pmem_ctrl_b_n369 = pmem_ctrl_b_data_o; // (signal) + /* upi41_core.vhd:589:28 */ + assign pmem_ctrl_b_n370 = pmem_ctrl_b_pmem_addr_o; // (signal) + /* upi41_core.vhd:574:3 */ + t48_pmem_ctrl pmem_ctrl_b ( + .clk_i(clk_i), + .res_i(reset_i), + .en_clk_i(en_clk_s), + .data_i(t48_data_s), + .write_pcl_i(pm_write_pcl_s), + .read_pcl_i(pm_read_pcl_s), + .write_pch_i(pm_write_pch_s), + .read_pch_i(pm_read_pch_s), + .inc_pc_i(pm_inc_pc_s), + .write_pmem_addr_i(pm_write_pmem_addr_s), + .addr_type_i(pm_addr_type_s), + .read_pmem_i(pm_read_pmem_s), + .pmem_data_i(pmem_data_i), + .data_o(pmem_ctrl_b_data_o), + .pmem_addr_o(pmem_ctrl_b_pmem_addr_o)); + /* upi41_core.vhd:599:29 */ + assign psw_b_n375 = psw_b_data_o; // (signal) + /* upi41_core.vhd:611:29 */ + assign psw_b_n376 = psw_b_carry_o; // (signal) + /* upi41_core.vhd:613:29 */ + assign psw_b_n377 = psw_b_aux_carry_o; // (signal) + /* upi41_core.vhd:614:29 */ + assign psw_b_n378 = psw_b_f0_o; // (signal) + /* upi41_core.vhd:615:29 */ + assign psw_b_n379 = psw_b_bs_o; // (signal) + /* upi41_core.vhd:593:3 */ + t48_psw psw_b ( + .clk_i(clk_i), + .res_i(reset_i), + .en_clk_i(en_clk_s), + .data_i(t48_data_s), + .read_psw_i(psw_read_psw_s), + .read_sp_i(psw_read_sp_s), + .write_psw_i(psw_write_psw_s), + .write_sp_i(psw_write_sp_s), + .special_data_i(psw_special_data_s), + .inc_stackp_i(psw_inc_stackp_s), + .dec_stackp_i(psw_dec_stackp_s), + .write_carry_i(psw_write_carry_s), + .write_aux_carry_i(psw_write_aux_carry_s), + .write_f0_i(psw_write_f0_s), + .write_bs_i(psw_write_bs_s), + .aux_carry_i(alu_aux_carry_s), + .data_o(psw_b_data_o), + .carry_o(psw_b_carry_o), + .aux_carry_o(psw_b_aux_carry_o), + .f0_o(psw_b_f0_o), + .bs_o(psw_b_bs_o)); + /* upi41_core.vhd:622:30 */ + assign n391_o = ~prog_s; + /* t48_pack-p.vhd:66:5 */ + assign n398_o = n391_o ? 1'b1 : 1'b0; + /* t48_pack-p.vhd:66:5 */ + assign n406_o = xtal3_s ? 1'b1 : 1'b0; + /* upi41_core.vhd:624:29 */ + assign n407_o = pmem_addr_s[10:0]; +endmodule + diff --git a/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/t48/upi41_core.vhd b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/t48/upi41_core.vhd new file mode 100644 index 0000000000000000000000000000000000000000..e6532502bf97f729421da1b695d18ee7294bd799 --- /dev/null +++ b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/t48/upi41_core.vhd @@ -0,0 +1,624 @@ +------------------------------------------------------------------------------- +-- +-- UPI-41 Microcontroller Core +-- +-- Copyright (c) 2004-2022, Arnim Laeuger (arniml@opencores.org) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.opencores.org/cvsweb.shtml/t48/ +-- +-- Limitations : +-- ============= +-- +-- Compared to the original MCS-48 architecture, the following limitations +-- apply: +-- +-- * Single-step mode not implemented. +-- Not selected for future implementation. +-- +-- * Reading of internal Program Memory not implemented. +-- Not selected for future implementation. +-- +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; + +entity upi41_core is + + generic ( + -- divide XTAL1 by 3 to derive Clock States + xtal_div_3_g : integer := 1; + -- store mnemonic in flip-flops (registered-out) + register_mnemonic_g : integer := 1; + -- state in which T1 is sampled (3 or 4) + sample_t1_state_g : integer := 4; + -- UPI41 type a + is_upi_type_a_g : integer := 1 + ); + + port ( + -- UPI41 Interface -------------------------------------------------------- + xtal_i : in std_logic; + xtal_en_i : in std_logic; + reset_i : in std_logic; + t0_i : in std_logic; + cs_n_i : in std_logic; + rd_n_i : in std_logic; + a0_i : in std_logic; + wr_n_i : in std_logic; + sync_o : out std_logic; + db_i : in std_logic_vector( 7 downto 0); + db_o : out std_logic_vector( 7 downto 0); + db_dir_o : out std_logic; + t1_i : in std_logic; + p2_i : in std_logic_vector( 7 downto 0); + p2_o : out std_logic_vector( 7 downto 0); + p2l_low_imp_o : out std_logic; + p2h_low_imp_o : out std_logic; + p1_i : in std_logic_vector( 7 downto 0); + p1_o : out std_logic_vector( 7 downto 0); + p1_low_imp_o : out std_logic; + prog_n_o : out std_logic; + -- Core Interface --------------------------------------------------------- + clk_i : in std_logic; + en_clk_i : in std_logic; + xtal3_o : out std_logic; + dmem_addr_o : out std_logic_vector( 7 downto 0); + dmem_we_o : out std_logic; + dmem_data_i : in std_logic_vector( 7 downto 0); + dmem_data_o : out std_logic_vector( 7 downto 0); + pmem_addr_o : out std_logic_vector(10 downto 0); + pmem_data_i : in std_logic_vector( 7 downto 0) + ); + +end upi41_core; + + +use work.t48_alu_pack.alu_op_t; +use work.t48_cond_branch_pack.branch_conditions_t; +use work.t48_cond_branch_pack.comp_value_t; +use work.t48_dmem_ctrl_pack.dmem_addr_ident_t; +use work.t48_pmem_ctrl_pack.pmem_addr_ident_t; +use work.t48_comp_pack.all; +use work.t48_pack.bus_idle_level_c; +use work.t48_pack.word_t; +use work.t48_pack.pmem_addr_t; +use work.t48_pack.mstate_t; +use work.t48_pack.to_stdLogic; +use work.t48_pack.to_boolean; + +architecture struct of upi41_core is + + signal t48_data_s : word_t; + + signal xtal_en_s : boolean; + signal en_clk_s : boolean; + + signal t0_s, t1_s : std_logic; + + -- ALU signals + signal alu_data_s : word_t; + signal alu_write_accu_s : boolean; + signal alu_write_shadow_s : boolean; + signal alu_write_temp_reg_s : boolean; + signal alu_read_alu_s : boolean; + signal alu_carry_s : std_logic; + signal alu_aux_carry_s : std_logic; + signal alu_op_s : alu_op_t; + signal alu_use_carry_s : boolean; + signal alu_da_high_s : boolean; + signal alu_da_overflow_s : boolean; + signal alu_accu_low_s : boolean; + signal alu_p06_temp_reg_s : boolean; + signal alu_p60_temp_reg_s : boolean; + + -- BUS signals + signal bus_write_bus_s : boolean; + signal bus_read_bus_s : boolean; + signal bus_data_s : word_t; + -- UPI41 + signal bus_ibf_s : std_logic; + signal bus_obf_s : std_logic; + signal bus_int_n_s : std_logic; + signal bus_set_f1_s : boolean; + signal bus_clear_f1_s : boolean; + signal bus_ibf_int_s : boolean; + signal bus_en_dma_s : boolean; + signal bus_en_flags_s : boolean; + signal bus_write_sts_s : boolean; + signal bus_mint_ibf_n_s : std_logic; + signal bus_mint_obf_s : std_logic; + signal bus_dma_s : boolean; + signal bus_drq_s : std_logic; + + -- Clock Controller signals + signal clk_multi_cycle_s : boolean; + signal clk_assert_psen_s : boolean; + signal clk_assert_prog_s : boolean; + signal clk_assert_rd_s : boolean; + signal clk_assert_wr_s : boolean; + signal clk_mstate_s : mstate_t; + signal clk_second_cycle_s : boolean; + signal prog_s : boolean; + signal ale_s : boolean; + signal xtal3_s : boolean; + + -- Conditional Branch Logic signals + signal cnd_compute_take_s : boolean; + signal cnd_branch_cond_s : branch_conditions_t; + signal cnd_take_branch_s : boolean; + signal cnd_comp_value_s : comp_value_t; + signal cnd_f1_s : std_logic; + signal cnd_tf_s : std_logic; + + -- Data Memory Controller signals + signal dm_write_dmem_addr_s : boolean; + signal dm_write_dmem_s : boolean; + signal dm_read_dmem_s : boolean; + signal dm_addr_type_s : dmem_addr_ident_t; + signal dm_data_s : word_t; + + -- Decoder signals + signal dec_data_s : word_t; + + -- Port 1 signals + signal p1_write_p1_s : boolean; + signal p1_read_p1_s : boolean; + signal p1_read_reg_s : boolean; + signal p1_data_s : word_t; + + -- Port 2 signals + signal p2_s : word_t; + signal p26_s : std_logic; + signal p2_write_p2_s : boolean; + signal p2_write_exp_s : boolean; + signal p2_read_p2_s : boolean; + signal p2_read_reg_s : boolean; + signal p2_read_exp_s : boolean; + signal p2_output_pch_s : boolean; + signal p2_data_s : word_t; + + -- Program Memory Controller signals + signal pm_write_pcl_s : boolean; + signal pm_read_pcl_s : boolean; + signal pm_write_pch_s : boolean; + signal pm_read_pch_s : boolean; + signal pm_read_pmem_s : boolean; + signal pm_inc_pc_s : boolean; + signal pm_write_pmem_addr_s : boolean; + signal pm_data_s : word_t; + signal pm_addr_type_s : pmem_addr_ident_t; + signal pmem_addr_s : pmem_addr_t; + + -- PSW signals + signal psw_read_psw_s : boolean; + signal psw_read_sp_s : boolean; + signal psw_write_psw_s : boolean; + signal psw_write_sp_s : boolean; + signal psw_carry_s : std_logic; + signal psw_aux_carry_s : std_logic; + signal psw_f0_s : std_logic; + signal psw_bs_s : std_logic; + signal psw_special_data_s : std_logic; + signal psw_inc_stackp_s : boolean; + signal psw_dec_stackp_s : boolean; + signal psw_write_carry_s : boolean; + signal psw_write_aux_carry_s : boolean; + signal psw_write_f0_s : boolean; + signal psw_write_bs_s : boolean; + signal psw_data_s : word_t; + + -- Timer signals + signal tim_overflow_s : boolean; + signal tim_of_s : std_logic; + signal tim_read_timer_s : boolean; + signal tim_write_timer_s : boolean; + signal tim_start_t_s : boolean; + signal tim_start_cnt_s : boolean; + signal tim_stop_tcnt_s : boolean; + signal tim_data_s : word_t; + + signal gnd_s : std_logic; + +begin + + -- TODO + sync_o <= '0'; + + gnd_s <= '0'; + + + xtal_en_s <= to_boolean(xtal_en_i); + en_clk_s <= to_boolean(en_clk_i); + + t0_s <= To_X01Z(t0_i); + t1_s <= To_X01Z(t1_i); + + alu_b : t48_alu + port map ( + clk_i => clk_i, + res_i => reset_i, + en_clk_i => en_clk_s, + data_i => t48_data_s, + data_o => alu_data_s, + write_accu_i => alu_write_accu_s, + write_shadow_i => alu_write_shadow_s, + write_temp_reg_i => alu_write_temp_reg_s, + read_alu_i => alu_read_alu_s, + carry_i => psw_carry_s, + carry_o => alu_carry_s, + aux_carry_o => alu_aux_carry_s, + alu_op_i => alu_op_s, + use_carry_i => alu_use_carry_s, + da_high_i => alu_da_high_s, + da_overflow_o => alu_da_overflow_s, + accu_low_i => alu_accu_low_s, + p06_temp_reg_i => alu_p06_temp_reg_s, + p60_temp_reg_i => alu_p60_temp_reg_s + ); + + bus_mux_b : t48_bus_mux + port map ( + alu_data_i => alu_data_s, + bus_data_i => bus_data_s, + dec_data_i => dec_data_s, + dm_data_i => dm_data_s, + pm_data_i => pm_data_s, + p1_data_i => p1_data_s, + p2_data_i => p2_data_s, + psw_data_i => psw_data_s, + tim_data_i => tim_data_s, + data_o => t48_data_s + ); + + clock_ctrl_b : t48_clock_ctrl + generic map ( + xtal_div_3_g => xtal_div_3_g + ) + port map ( + clk_i => clk_i, + xtal_i => xtal_i, + xtal_en_i => xtal_en_s, + res_i => reset_i, + en_clk_i => en_clk_s, + xtal3_o => xtal3_s, + t0_o => open, + multi_cycle_i => clk_multi_cycle_s, + assert_psen_i => clk_assert_psen_s, + assert_prog_i => clk_assert_prog_s, + assert_rd_i => clk_assert_rd_s, + assert_wr_i => clk_assert_wr_s, + mstate_o => clk_mstate_s, + second_cycle_o => clk_second_cycle_s, + ale_o => ale_s, + psen_o => open, + prog_o => prog_s, + rd_o => open, + wr_o => open + ); + + cond_branch_b : t48_cond_branch + port map ( + clk_i => clk_i, + res_i => reset_i, + en_clk_i => en_clk_s, + compute_take_i => cnd_compute_take_s, + branch_cond_i => cnd_branch_cond_s, + take_branch_o => cnd_take_branch_s, + accu_i => alu_data_s, + t0_i => t0_s, + t1_i => t1_s, + int_n_i => bus_int_n_s, + f0_i => psw_f0_s, + f1_i => cnd_f1_s, + tf_i => cnd_tf_s, + carry_i => psw_carry_s, + ibf_i => bus_ibf_s, + obf_i => bus_obf_s, + comp_value_i => cnd_comp_value_s + ); + + db_bus_b : upi41_db_bus + generic map ( + is_type_a_g => 1 + ) + port map ( + clk_i => clk_i, + res_i => reset_i, + en_clk_i => en_clk_s, + data_i => t48_data_s, + data_o => bus_data_s, + write_bus_i => bus_write_bus_s, + read_bus_i => bus_read_bus_s, + write_sts_i => bus_write_sts_s, + set_f1_o => bus_set_f1_s, + clear_f1_o => bus_clear_f1_s, + f0_i => psw_f0_s, + f1_i => cnd_f1_s, + ibf_o => bus_ibf_s, + obf_o => bus_obf_s, + int_n_o => bus_int_n_s, + ibf_int_i => bus_ibf_int_s, + en_dma_i => bus_en_dma_s, + en_flags_i => bus_en_flags_s, + write_p2_i => p2_write_p2_s, + mint_ibf_n_o => bus_mint_ibf_n_s, + mint_obf_o => bus_mint_obf_s, + dma_o => bus_dma_s, + drq_o => bus_drq_s, + dack_n_i => p2_i(7), + a0_i => a0_i, + cs_n_i => cs_n_i, + rd_n_i => rd_n_i, + wr_n_i => wr_n_i, + db_i => db_i, + db_o => db_o, + db_dir_o => db_dir_o + ); + + decoder_b : t48_decoder + generic map ( + register_mnemonic_g => register_mnemonic_g, + is_upi_g => 1, + is_upi_type_a_g => is_upi_type_a_g + ) + port map ( + clk_i => clk_i, + res_i => reset_i, + en_clk_i => en_clk_s, + xtal_i => xtal_i, + xtal_en_i => xtal_en_s, + ea_i => gnd_s, + ale_i => ale_s, + int_n_i => bus_int_n_s, + t0_dir_o => open, + data_i => t48_data_s, + data_o => dec_data_s, + alu_write_accu_o => alu_write_accu_s, + alu_write_shadow_o => alu_write_shadow_s, + alu_write_temp_reg_o => alu_write_temp_reg_s, + alu_read_alu_o => alu_read_alu_s, + bus_write_bus_o => bus_write_bus_s, + bus_read_bus_o => bus_read_bus_s, + bus_set_f1_i => bus_set_f1_s, -- UPI41 + bus_clear_f1_i => bus_clear_f1_s, -- UPI41 + bus_ibf_int_o => bus_ibf_int_s, -- UPI41 + bus_en_dma_o => bus_en_dma_s, -- UPI41A + bus_en_flags_o => bus_en_flags_s, -- UPI41A + bus_write_sts_o => bus_write_sts_s, -- UPI41A + dm_write_dmem_addr_o => dm_write_dmem_addr_s, + dm_write_dmem_o => dm_write_dmem_s, + dm_read_dmem_o => dm_read_dmem_s, + p1_write_p1_o => p1_write_p1_s, + p1_read_p1_o => p1_read_p1_s, + pm_write_pcl_o => pm_write_pcl_s, + p2_write_p2_o => p2_write_p2_s, + p2_write_exp_o => p2_write_exp_s, + p2_read_p2_o => p2_read_p2_s, + pm_read_pcl_o => pm_read_pcl_s, + pm_write_pch_o => pm_write_pch_s, + pm_read_pch_o => pm_read_pch_s, + pm_read_pmem_o => pm_read_pmem_s, + psw_read_psw_o => psw_read_psw_s, + psw_read_sp_o => psw_read_sp_s, + psw_write_psw_o => psw_write_psw_s, + psw_write_sp_o => psw_write_sp_s, + alu_carry_i => alu_carry_s, + alu_op_o => alu_op_s, + alu_use_carry_o => alu_use_carry_s, + alu_da_high_o => alu_da_high_s, + alu_da_overflow_i => alu_da_overflow_s, + alu_accu_low_o => alu_accu_low_s, + alu_p06_temp_reg_o => alu_p06_temp_reg_s, + alu_p60_temp_reg_o => alu_p60_temp_reg_s, + bus_output_pcl_o => open, + bus_bidir_bus_o => open, + clk_multi_cycle_o => clk_multi_cycle_s, + clk_assert_psen_o => clk_assert_psen_s, + clk_assert_prog_o => clk_assert_prog_s, + clk_assert_rd_o => clk_assert_rd_s, + clk_assert_wr_o => clk_assert_wr_s, + clk_mstate_i => clk_mstate_s, + clk_second_cycle_i => clk_second_cycle_s, + cnd_compute_take_o => cnd_compute_take_s, + cnd_branch_cond_o => cnd_branch_cond_s, + cnd_take_branch_i => cnd_take_branch_s, + cnd_comp_value_o => cnd_comp_value_s, + cnd_f1_o => cnd_f1_s, + cnd_tf_o => cnd_tf_s, + dm_addr_type_o => dm_addr_type_s, + tim_read_timer_o => tim_read_timer_s, + tim_write_timer_o => tim_write_timer_s, + tim_start_t_o => tim_start_t_s, + tim_start_cnt_o => tim_start_cnt_s, + tim_stop_tcnt_o => tim_stop_tcnt_s, + p1_read_reg_o => p1_read_reg_s, + p2_read_reg_o => p2_read_reg_s, + p2_read_exp_o => p2_read_exp_s, + p2_output_pch_o => p2_output_pch_s, + pm_inc_pc_o => pm_inc_pc_s, + pm_write_pmem_addr_o => pm_write_pmem_addr_s, + pm_addr_type_o => pm_addr_type_s, + psw_special_data_o => psw_special_data_s, + psw_carry_i => psw_carry_s, + psw_aux_carry_i => psw_aux_carry_s, + psw_f0_i => psw_f0_s, + psw_inc_stackp_o => psw_inc_stackp_s, + psw_dec_stackp_o => psw_dec_stackp_s, + psw_write_carry_o => psw_write_carry_s, + psw_write_aux_carry_o => psw_write_aux_carry_s, + psw_write_f0_o => psw_write_f0_s, + psw_write_bs_o => psw_write_bs_s, + tim_overflow_i => tim_overflow_s + ); + + dmem_ctrl_b : t48_dmem_ctrl + port map ( + clk_i => clk_i, + res_i => reset_i, + en_clk_i => en_clk_s, + data_i => t48_data_s, + write_dmem_addr_i => dm_write_dmem_addr_s, + write_dmem_i => dm_write_dmem_s, + read_dmem_i => dm_read_dmem_s, + addr_type_i => dm_addr_type_s, + bank_select_i => psw_bs_s, + data_o => dm_data_s, + dmem_data_i => dmem_data_i, + dmem_addr_o => dmem_addr_o, + dmem_we_o => dmem_we_o, + dmem_data_o => dmem_data_o + ); + + timer_b : t48_timer + generic map ( + sample_t1_state_g => sample_t1_state_g + ) + port map ( + clk_i => clk_i, + res_i => reset_i, + en_clk_i => en_clk_s, + t1_i => t1_s, + clk_mstate_i => clk_mstate_s, + data_i => t48_data_s, + data_o => tim_data_s, + read_timer_i => tim_read_timer_s, + write_timer_i => tim_write_timer_s, + start_t_i => tim_start_t_s, + start_cnt_i => tim_start_cnt_s, + stop_tcnt_i => tim_stop_tcnt_s, + overflow_o => tim_of_s + ); + + tim_overflow_s <= to_boolean(tim_of_s); + + p1_b : t48_p1 + port map ( + clk_i => clk_i, + res_i => reset_i, + en_clk_i => en_clk_s, + data_i => t48_data_s, + data_o => p1_data_s, + write_p1_i => p1_write_p1_s, + read_p1_i => p1_read_p1_s, + read_reg_i => p1_read_reg_s, + p1_i => p1_i, + p1_o => p1_o, + p1_low_imp_o => p1_low_imp_o + ); + + p2_b : t48_p2 + port map ( + clk_i => clk_i, + res_i => reset_i, + en_clk_i => en_clk_s, + xtal_i => xtal_i, + xtal_en_i => xtal_en_s, + data_i => t48_data_s, + data_o => p2_data_s, + write_p2_i => p2_write_p2_s, + write_exp_i => p2_write_exp_s, + read_p2_i => p2_read_p2_s, + read_reg_i => p2_read_reg_s, + read_exp_i => p2_read_exp_s, + output_pch_i => p2_output_pch_s, + pch_i => pmem_addr_s(11 downto 8), + p2_i => p2_i, + p2_o => p2_s, + p2l_low_imp_o => p2l_low_imp_o, + p2h_low_imp_o => p2h_low_imp_o + ); + + p26_s <= p2_s(6) when not bus_dma_s else bus_drq_s; + p2_o <= p2_s(7) + & p26_s + & (p2_s(5) and bus_mint_ibf_n_s) + & (p2_s(4) and bus_mint_obf_s) + & p2_s(3 downto 0); + + pmem_ctrl_b : t48_pmem_ctrl + port map ( + clk_i => clk_i, + res_i => reset_i, + en_clk_i => en_clk_s, + data_i => t48_data_s, + data_o => pm_data_s, + write_pcl_i => pm_write_pcl_s, + read_pcl_i => pm_read_pcl_s, + write_pch_i => pm_write_pch_s, + read_pch_i => pm_read_pch_s, + inc_pc_i => pm_inc_pc_s, + write_pmem_addr_i => pm_write_pmem_addr_s, + addr_type_i => pm_addr_type_s, + read_pmem_i => pm_read_pmem_s, + pmem_addr_o => pmem_addr_s, + pmem_data_i => pmem_data_i + ); + + psw_b : t48_psw + port map ( + clk_i => clk_i, + res_i => reset_i, + en_clk_i => en_clk_s, + data_i => t48_data_s, + data_o => psw_data_s, + read_psw_i => psw_read_psw_s, + read_sp_i => psw_read_sp_s, + write_psw_i => psw_write_psw_s, + write_sp_i => psw_write_sp_s, + special_data_i => psw_special_data_s, + inc_stackp_i => psw_inc_stackp_s, + dec_stackp_i => psw_dec_stackp_s, + write_carry_i => psw_write_carry_s, + write_aux_carry_i => psw_write_aux_carry_s, + write_f0_i => psw_write_f0_s, + write_bs_i => psw_write_bs_s, + carry_o => psw_carry_s, + aux_carry_i => alu_aux_carry_s, + aux_carry_o => psw_aux_carry_s, + f0_o => psw_f0_s, + bs_o => psw_bs_s + ); + + + ----------------------------------------------------------------------------- + -- Output Mapping. + ----------------------------------------------------------------------------- + prog_n_o <= to_stdLogic(not prog_s); + xtal3_o <= to_stdLogic(xtal3_s); + pmem_addr_o <= pmem_addr_s(10 downto 0); + +end struct; diff --git a/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/t48/upi41_db_bus-c.vhd b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/t48/upi41_db_bus-c.vhd new file mode 100644 index 0000000000000000000000000000000000000000..e76fb49896dd07b83d3c8af5e22ed2a0c527bca0 --- /dev/null +++ b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/t48/upi41_db_bus-c.vhd @@ -0,0 +1,17 @@ +------------------------------------------------------------------------------- +-- +-- The UPI-41 BUS unit. +-- Implements the BUS port logic. +-- +-- Copyright (c) 2004-2022, Arnim Laeuger (arniml@opencores.org) +-- +-- All rights reserved +-- +------------------------------------------------------------------------------- + +configuration upi41_db_bus_rtl_c0 of upi41_db_bus is + + for rtl + end for; + +end upi41_db_bus_rtl_c0; diff --git a/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/t48/upi41_db_bus.vhd b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/t48/upi41_db_bus.vhd new file mode 100644 index 0000000000000000000000000000000000000000..34676b90ba9fe402aa8819e97c6a6b539895fe60 --- /dev/null +++ b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/t48/upi41_db_bus.vhd @@ -0,0 +1,267 @@ +------------------------------------------------------------------------------- +-- +-- The UPI-41 BUS unit. +-- Implements the BUS port logic. +-- +-- Copyright (c) 2004-2022, Arnim Laeuger (arniml@opencores.org) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.opencores.org/cvsweb.shtml/t48/ +-- +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; + +use work.t48_pack.word_t; + +entity upi41_db_bus is + + generic ( + is_type_a_g : integer := 1 + ); + port ( + -- Global Interface ------------------------------------------------------- + clk_i : in std_logic; + res_i : in std_logic; + en_clk_i : in boolean; + -- UPI41 Bus Interface ---------------------------------------------------- + data_i : in word_t; + data_o : out word_t; + write_bus_i : in boolean; + read_bus_i : in boolean; + write_sts_i : in boolean; + set_f1_o : out boolean; + clear_f1_o : out boolean; + f0_i : in std_logic; + f1_i : in std_logic; + ibf_o : out std_logic; + obf_o : out std_logic; + int_n_o : out std_logic; + ibf_int_i : in boolean; + en_dma_i : in boolean; + en_flags_i : in boolean; + -- P2 interface ----------------------------------------------------------- + write_p2_i : in boolean; + mint_ibf_n_o : out std_logic; + mint_obf_o : out std_logic; + dma_o : out boolean; + drq_o : out std_logic; + dack_n_i : in std_logic; + -- BUS Interface ---------------------------------------------------------- + a0_i : in std_logic; + cs_n_i : in std_logic; + rd_n_i : in std_logic; + wr_n_i : in std_logic; + db_i : in word_t; + db_o : out word_t; + db_dir_o : out std_logic + ); + +end upi41_db_bus; + + +use work.t48_pack.clk_active_c; +use work.t48_pack.res_active_c; +use work.t48_pack.bus_idle_level_c; +use work.t48_pack.to_stdLogic; + +architecture rtl of upi41_db_bus is + + signal read_s, read_q, + read_hold_q, + write_s, write_q, + read_pulse_s, write_pulse_s : boolean; + + signal a0_q : std_logic; + + signal ibf_q, obf_q : std_logic; + + -- the BUS output register + signal dbbin_q, + dbbout_q : word_t; + -- the BUS status register + signal sts_q : std_logic_vector(7 downto 4); + + signal dma_q, + flags_q : boolean; + + signal ext_acc_s : boolean; + signal dack_s : boolean; + +begin + + -- pragma translate_off + + -- UPI41 configuration ------------------------------------------------------ + assert (is_type_a_g = 0) or (is_type_a_g = 1) + report "is_type_a_g must be either 1 or 0!" + severity failure; + + -- pragma translate_on + + + ----------------------------------------------------------------------------- + -- Process master_access + -- + -- Purpose: + -- Generate read and write pulses based on master access. + -- + dack_s <= dack_n_i = '0' and dma_q; + ext_acc_s <= cs_n_i = '0' or dack_s; + read_s <= ext_acc_s and rd_n_i = '0'; + write_s <= ext_acc_s and wr_n_i = '0'; + -- + master_access: process (res_i, clk_i) + begin + if res_i = res_active_c then + read_q <= false; + read_hold_q <= false; + write_q <= false; + a0_q <= '0'; + + elsif clk_i'event and clk_i = clk_active_c then + read_q <= read_s; + write_q <= write_s; + + if read_s then + read_hold_q <= true; + elsif ext_acc_s then + read_hold_q <= false; + end if; + + if dack_s then + a0_q <= '0'; + elsif read_s or write_s then + a0_q <= a0_i; + end if; + + end if; + end process master_access; + -- + read_pulse_s <= read_q and not read_s; + write_pulse_s <= write_q and not write_s; + + ----------------------------------------------------------------------------- + -- Process bus_regs + -- + -- Purpose: + -- Implements the BUS output register. + -- + bus_regs: process (res_i, clk_i) + begin + if res_i = res_active_c then + dbbin_q <= (others => '0'); + dbbout_q <= (others => '0'); + sts_q <= (others => '0'); + ibf_q <= '0'; + obf_q <= '0'; + int_n_o <= '1'; + dma_q <= false; + drq_o <= '0'; + flags_q <= false; + + elsif clk_i'event and clk_i = clk_active_c then + -- master access + if read_pulse_s and a0_q = '0' then + obf_q <= '0'; + elsif write_pulse_s then + dbbin_q <= db_i; + ibf_q <= '1'; + int_n_o <= '0'; + end if; + + if dack_s and (read_s or write_s) then + drq_o <= '0'; + end if; + + if en_clk_i then + if write_bus_i then + dbbout_q <= data_i; + obf_q <= '1'; + elsif read_bus_i then + ibf_q <= '0'; + elsif write_sts_i then + sts_q <= data_i(7 downto 4); + end if; + + if ibf_int_i then + int_n_o <= '1'; + end if; + + if is_type_a_g = 1 then + if en_dma_i then + dma_q <= true; + drq_o <= '0'; + end if; + if en_flags_i then + flags_q <= true; + end if; + + if dma_q and write_p2_i and data_i(6) = '1' then + drq_o <= '1'; + end if; + end if; + + end if; + + end if; + + end process bus_regs; + -- + ----------------------------------------------------------------------------- + + + ----------------------------------------------------------------------------- + -- Output Mapping. + ----------------------------------------------------------------------------- + set_f1_o <= write_pulse_s and a0_q = '1'; + clear_f1_o <= write_pulse_s and a0_q = '0'; + ibf_o <= ibf_q; + obf_o <= obf_q; + db_o <= dbbout_q when a0_q = '0' else + sts_q & f1_i & f0_i & ibf_q & obf_q when is_type_a_g = 1 else + "0000" & f1_i & f0_i & ibf_q & obf_q; + db_dir_o <= '1' when ext_acc_s and read_hold_q else '0'; + data_o <= dbbin_q + when read_bus_i else + (others => bus_idle_level_c); + + mint_ibf_n_o <= '0' when flags_q and ibf_q = '1' else '1'; + mint_obf_o <= '0' when flags_q and obf_q = '0' else '1'; + + dma_o <= dma_q; + +end rtl; diff --git a/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/t65/T65.vhd b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/t65/T65.vhd new file mode 100644 index 0000000000000000000000000000000000000000..09253fe021c1936ad242d87841d5d1f60bea14cf --- /dev/null +++ b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/t65/T65.vhd @@ -0,0 +1,564 @@ +-- **** +-- T65(b) core. In an effort to merge and maintain bug fixes .... +-- +-- +-- Ver 301 more merging +-- Ver 300 Bugfixes by ehenciak added, started tidyup *bust* +-- MikeJ March 2005 +-- Latest version from www.fpgaarcade.com (original www.opencores.org) +-- +-- **** +-- +-- 65xx compatible microprocessor core +-- +-- Version : 0246 +-- +-- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.opencores.org/cvsweb.shtml/t65/ +-- +-- Limitations : +-- +-- 65C02 and 65C816 modes are incomplete +-- Undocumented instructions are not supported +-- Some interface signals behaves incorrect +-- +-- File history : +-- +-- 0246 : First release +-- + +library IEEE; + use IEEE.std_logic_1164.all; + use IEEE.numeric_std.all; + use work.T65_Pack.all; + +-- ehenciak 2-23-2005 : Added the enable signal so that one doesn't have to use +-- the ready signal to limit the CPU. +entity T65 is + port( + Mode : in std_logic_vector(1 downto 0); -- "00" => 6502, "01" => 65C02, "10" => 65C816 + Res_n : in std_logic; + Enable : in std_logic; + Clk : in std_logic; + Rdy : in std_logic; + Abort_n : in std_logic; + IRQ_n : in std_logic; + NMI_n : in std_logic; + SO_n : in std_logic; + R_W_n : out std_logic; + Sync : out std_logic; + EF : out std_logic; + MF : out std_logic; + XF : out std_logic; + ML_n : out std_logic; + VP_n : out std_logic; + VDA : out std_logic; + VPA : out std_logic; + A : out std_logic_vector(23 downto 0); + DI : in std_logic_vector(7 downto 0); + DO : out std_logic_vector(7 downto 0) + ); +end T65; + +architecture rtl of T65 is + + -- Registers + signal ABC, X, Y, D : std_logic_vector(15 downto 0); + signal P, AD, DL : std_logic_vector(7 downto 0) := x"00"; + signal BAH : std_logic_vector(7 downto 0); + signal BAL : std_logic_vector(8 downto 0); + signal PBR : std_logic_vector(7 downto 0); + signal DBR : std_logic_vector(7 downto 0); + signal PC : unsigned(15 downto 0); + signal S : unsigned(15 downto 0); + signal EF_i : std_logic; + signal MF_i : std_logic; + signal XF_i : std_logic; + + signal IR : std_logic_vector(7 downto 0); + signal MCycle : std_logic_vector(2 downto 0); + + signal Mode_r : std_logic_vector(1 downto 0); + signal ALU_Op_r : std_logic_vector(3 downto 0); + signal Write_Data_r : std_logic_vector(2 downto 0); + signal Set_Addr_To_r : std_logic_vector(1 downto 0); + signal PCAdder : unsigned(8 downto 0); + + signal RstCycle : std_logic; + signal IRQCycle : std_logic; + signal NMICycle : std_logic; + + signal B_o : std_logic; + signal SO_n_o : std_logic; + signal IRQ_n_o : std_logic; + signal NMI_n_o : std_logic; + signal NMIAct : std_logic; + + signal Break : std_logic; + + -- ALU signals + signal BusA : std_logic_vector(7 downto 0); + signal BusA_r : std_logic_vector(7 downto 0); + signal BusB : std_logic_vector(7 downto 0); + signal ALU_Q : std_logic_vector(7 downto 0); + signal P_Out : std_logic_vector(7 downto 0); + + -- Micro code outputs + signal LCycle : std_logic_vector(2 downto 0); + signal ALU_Op : std_logic_vector(3 downto 0); + signal Set_BusA_To : std_logic_vector(2 downto 0); + signal Set_Addr_To : std_logic_vector(1 downto 0); + signal Write_Data : std_logic_vector(2 downto 0); + signal Jump : std_logic_vector(1 downto 0); + signal BAAdd : std_logic_vector(1 downto 0); + signal BreakAtNA : std_logic; + signal ADAdd : std_logic; + signal AddY : std_logic; + signal PCAdd : std_logic; + signal Inc_S : std_logic; + signal Dec_S : std_logic; + signal LDA : std_logic; + signal LDP : std_logic; + signal LDX : std_logic; + signal LDY : std_logic; + signal LDS : std_logic; + signal LDDI : std_logic; + signal LDALU : std_logic; + signal LDAD : std_logic; + signal LDBAL : std_logic; + signal LDBAH : std_logic; + signal SaveP : std_logic; + signal Write : std_logic; + + signal really_rdy : std_logic; + signal R_W_n_i : std_logic; + +begin + -- ehenciak : gate Rdy with read/write to make an "OK, it's + -- really OK to stop the processor now if Rdy is + -- deasserted" signal + really_rdy <= Rdy or not(R_W_n_i); + + -- ehenciak : Drive R_W_n_i off chip. + R_W_n <= R_W_n_i; + + Sync <= '1' when MCycle = "000" else '0'; + EF <= EF_i; + MF <= MF_i; + XF <= XF_i; + ML_n <= '0' when IR(7 downto 6) /= "10" and IR(2 downto 1) = "11" and MCycle(2 downto 1) /= "00" else '1'; + VP_n <= '0' when IRQCycle = '1' and (MCycle = "101" or MCycle = "110") else '1'; + VDA <= '1' when Set_Addr_To_r /= "00" else '0'; -- Incorrect !!!!!!!!!!!! + VPA <= '1' when Jump(1) = '0' else '0'; -- Incorrect !!!!!!!!!!!! + + mcode : T65_MCode + port map( + Mode => Mode_r, + IR => IR, + MCycle => MCycle, + P => P, + LCycle => LCycle, + ALU_Op => ALU_Op, + Set_BusA_To => Set_BusA_To, + Set_Addr_To => Set_Addr_To, + Write_Data => Write_Data, + Jump => Jump, + BAAdd => BAAdd, + BreakAtNA => BreakAtNA, + ADAdd => ADAdd, + AddY => AddY, + PCAdd => PCAdd, + Inc_S => Inc_S, + Dec_S => Dec_S, + LDA => LDA, + LDP => LDP, + LDX => LDX, + LDY => LDY, + LDS => LDS, + LDDI => LDDI, + LDALU => LDALU, + LDAD => LDAD, + LDBAL => LDBAL, + LDBAH => LDBAH, + SaveP => SaveP, + Write => Write + ); + + alu : T65_ALU + port map( + Mode => Mode_r, + Op => ALU_Op_r, + BusA => BusA_r, + BusB => BusB, + P_In => P, + P_Out => P_Out, + Q => ALU_Q + ); + + process (Res_n, Clk) + begin + if Res_n = '0' then + PC <= (others => '0'); -- Program Counter + IR <= "00000000"; + S <= (others => '0'); -- Dummy !!!!!!!!!!!!!!!!!!!!! + D <= (others => '0'); + PBR <= (others => '0'); + DBR <= (others => '0'); + + Mode_r <= (others => '0'); + ALU_Op_r <= "1100"; + Write_Data_r <= "000"; + Set_Addr_To_r <= "00"; + + R_W_n_i <= '1'; + EF_i <= '1'; + MF_i <= '1'; + XF_i <= '1'; + + elsif Clk'event and Clk = '1' then + if (Enable = '1') then + if (really_rdy = '1') then + R_W_n_i <= not Write or RstCycle; + + D <= (others => '1'); -- Dummy + PBR <= (others => '1'); -- Dummy + DBR <= (others => '1'); -- Dummy + EF_i <= '0'; -- Dummy + MF_i <= '0'; -- Dummy + XF_i <= '0'; -- Dummy + + if MCycle = "000" then + Mode_r <= Mode; + + if IRQCycle = '0' and NMICycle = '0' then + PC <= PC + 1; + end if; + + if IRQCycle = '1' or NMICycle = '1' then + IR <= "00000000"; + else + IR <= DI; + end if; + end if; + + ALU_Op_r <= ALU_Op; + Write_Data_r <= Write_Data; + if Break = '1' then + Set_Addr_To_r <= "00"; + else + Set_Addr_To_r <= Set_Addr_To; + end if; + + if Inc_S = '1' then + S <= S + 1; + end if; + if Dec_S = '1' and RstCycle = '0' then + S <= S - 1; + end if; + if LDS = '1' then + S(7 downto 0) <= unsigned(ALU_Q); + end if; + + if IR = "00000000" and MCycle = "001" and IRQCycle = '0' and NMICycle = '0' then + PC <= PC + 1; + end if; + -- + -- jump control logic + -- + case Jump is + when "01" => + PC <= PC + 1; + + when "10" => + PC <= unsigned(DI & DL); + + when "11" => + if PCAdder(8) = '1' then + if DL(7) = '0' then + PC(15 downto 8) <= PC(15 downto 8) + 1; + else + PC(15 downto 8) <= PC(15 downto 8) - 1; + end if; + end if; + PC(7 downto 0) <= PCAdder(7 downto 0); + + when others => null; + end case; + end if; + end if; + end if; + end process; + + PCAdder <= resize(PC(7 downto 0),9) + resize(unsigned(DL(7) & DL),9) when PCAdd = '1' + else "0" & PC(7 downto 0); + + process (Clk) + begin + if Clk'event and Clk = '1' then + if (Enable = '1') then + if (really_rdy = '1') then + if MCycle = "000" then + if LDA = '1' then + ABC(7 downto 0) <= ALU_Q; + end if; + if LDX = '1' then + X(7 downto 0) <= ALU_Q; + end if; + if LDY = '1' then + Y(7 downto 0) <= ALU_Q; + end if; + if (LDA or LDX or LDY) = '1' then + P <= P_Out; + end if; + end if; + if SaveP = '1' then + P <= P_Out; + end if; + if LDP = '1' then + P <= ALU_Q; + end if; + if IR(4 downto 0) = "11000" then + case IR(7 downto 5) is + when "000" => + P(Flag_C) <= '0'; + when "001" => + P(Flag_C) <= '1'; + when "010" => + P(Flag_I) <= '0'; + when "011" => + P(Flag_I) <= '1'; + when "101" => + P(Flag_V) <= '0'; + when "110" => + P(Flag_D) <= '0'; + when "111" => + P(Flag_D) <= '1'; + when others => + end case; + end if; + + --if IR = "00000000" and MCycle = "011" and RstCycle = '0' and NMICycle = '0' and IRQCycle = '0' then + -- P(Flag_B) <= '1'; + --end if; + --if IR = "00000000" and MCycle = "100" and RstCycle = '0' and (NMICycle = '1' or IRQCycle = '1') then + -- P(Flag_I) <= '1'; + -- P(Flag_B) <= B_o; + --end if; + + -- B=1 always on the 6502 + P(Flag_B) <= '1'; + if IR = "00000000" and RstCycle = '0' and (NMICycle = '1' or IRQCycle = '1') then + if MCycle = "011" then + -- B=0 in *copy* of P pushed onto the stack + P(Flag_B) <= '0'; + elsif MCycle = "100" then + P(Flag_I) <= '1'; + end if; + end if; + + if SO_n_o = '1' and SO_n = '0' then + P(Flag_V) <= '1'; + end if; + if RstCycle = '1' and Mode_r /= "00" then + P(Flag_1) <= '1'; + P(Flag_D) <= '0'; + P(Flag_I) <= '1'; + end if; + P(Flag_1) <= '1'; + + B_o <= P(Flag_B); + SO_n_o <= SO_n; + IRQ_n_o <= IRQ_n; + NMI_n_o <= NMI_n; + end if; + end if; + end if; + end process; + +--------------------------------------------------------------------------- +-- +-- Buses +-- +--------------------------------------------------------------------------- + + process (Res_n, Clk) + begin + if Res_n = '0' then + BusA_r <= (others => '0'); + BusB <= (others => '0'); + AD <= (others => '0'); + BAL <= (others => '0'); + BAH <= (others => '0'); + DL <= (others => '0'); + elsif Clk'event and Clk = '1' then + if (Enable = '1') then + if (Rdy = '1') then + BusA_r <= BusA; + BusB <= DI; + + case BAAdd is + when "01" => + -- BA Inc + AD <= std_logic_vector(unsigned(AD) + 1); + BAL <= std_logic_vector(unsigned(BAL) + 1); + when "10" => + -- BA Add + BAL <= std_logic_vector(resize(unsigned(BAL(7 downto 0)),9) + resize(unsigned(BusA),9)); + when "11" => + -- BA Adj + if BAL(8) = '1' then + BAH <= std_logic_vector(unsigned(BAH) + 1); + end if; + when others => + end case; + + -- ehenciak : modified to use Y register as well (bugfix) + if ADAdd = '1' then + if (AddY = '1') then + AD <= std_logic_vector(unsigned(AD) + unsigned(Y(7 downto 0))); + else + AD <= std_logic_vector(unsigned(AD) + unsigned(X(7 downto 0))); + end if; + end if; + + if IR = "00000000" then + BAL <= (others => '1'); + BAH <= (others => '1'); + if RstCycle = '1' then + BAL(2 downto 0) <= "100"; + elsif NMICycle = '1' then + BAL(2 downto 0) <= "010"; + else + BAL(2 downto 0) <= "110"; + end if; + if Set_addr_To_r = "11" then + BAL(0) <= '1'; + end if; + end if; + + + if LDDI = '1' then + DL <= DI; + end if; + if LDALU = '1' then + DL <= ALU_Q; + end if; + if LDAD = '1' then + AD <= DI; + end if; + if LDBAL = '1' then + BAL(7 downto 0) <= DI; + end if; + if LDBAH = '1' then + BAH <= DI; + end if; + end if; + end if; + end if; + end process; + + Break <= (BreakAtNA and not BAL(8)) or (PCAdd and not PCAdder(8)); + + + with Set_BusA_To select + BusA <= DI when "000", + ABC(7 downto 0) when "001", + X(7 downto 0) when "010", + Y(7 downto 0) when "011", + std_logic_vector(S(7 downto 0)) when "100", + P when "101", + (others => '-') when others; + + with Set_Addr_To_r select + A <= "0000000000000001" & std_logic_vector(S(7 downto 0)) when "01", + DBR & "00000000" & AD when "10", + "00000000" & BAH & BAL(7 downto 0) when "11", + PBR & std_logic_vector(PC(15 downto 8)) & std_logic_vector(PCAdder(7 downto 0)) when others; + + with Write_Data_r select + DO <= DL when "000", + ABC(7 downto 0) when "001", + X(7 downto 0) when "010", + Y(7 downto 0) when "011", + std_logic_vector(S(7 downto 0)) when "100", + P when "101", + std_logic_vector(PC(7 downto 0)) when "110", + std_logic_vector(PC(15 downto 8)) when others; + +------------------------------------------------------------------------- +-- +-- Main state machine +-- +------------------------------------------------------------------------- + + process (Res_n, Clk) + begin + if Res_n = '0' then + MCycle <= "001"; + RstCycle <= '1'; + IRQCycle <= '0'; + NMICycle <= '0'; + NMIAct <= '0'; + elsif Clk'event and Clk = '1' then + if (Enable = '1') then + if (really_rdy = '1') then + if MCycle = LCycle or Break = '1' then + MCycle <= "000"; + RstCycle <= '0'; + IRQCycle <= '0'; + NMICycle <= '0'; + if NMIAct = '1' then + NMICycle <= '1'; + elsif IRQ_n_o = '0' and P(Flag_I) = '0' then + IRQCycle <= '1'; + end if; + else + MCycle <= std_logic_vector(unsigned(MCycle) + 1); + end if; + + if NMICycle = '1' then + NMIAct <= '0'; + end if; + if NMI_n_o = '1' and NMI_n = '0' then + NMIAct <= '1'; + end if; + end if; + end if; + end if; + end process; + +end; diff --git a/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/t65/T65_ALU.vhd b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/t65/T65_ALU.vhd new file mode 100644 index 0000000000000000000000000000000000000000..b1f6d63239587f48374ca8b04a66f7810d3a8998 --- /dev/null +++ b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/t65/T65_ALU.vhd @@ -0,0 +1,260 @@ +-- **** +-- T65(b) core. In an effort to merge and maintain bug fixes .... +-- +-- +-- Ver 300 Bugfixes by ehenciak added +-- MikeJ March 2005 +-- Latest version from www.fpgaarcade.com (original www.opencores.org) +-- +-- **** +-- +-- 6502 compatible microprocessor core +-- +-- Version : 0245 +-- +-- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.opencores.org/cvsweb.shtml/t65/ +-- +-- Limitations : +-- +-- File history : +-- +-- 0245 : First version +-- + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; +use work.T65_Pack.all; + +entity T65_ALU is + port( + Mode : in std_logic_vector(1 downto 0); -- "00" => 6502, "01" => 65C02, "10" => 65816 + Op : in std_logic_vector(3 downto 0); + BusA : in std_logic_vector(7 downto 0); + BusB : in std_logic_vector(7 downto 0); + P_In : in std_logic_vector(7 downto 0); + P_Out : out std_logic_vector(7 downto 0); + Q : out std_logic_vector(7 downto 0) + ); +end T65_ALU; + +architecture rtl of T65_ALU is + + -- AddSub variables (temporary signals) + signal ADC_Z : std_logic; + signal ADC_C : std_logic; + signal ADC_V : std_logic; + signal ADC_N : std_logic; + signal ADC_Q : std_logic_vector(7 downto 0); + signal SBC_Z : std_logic; + signal SBC_C : std_logic; + signal SBC_V : std_logic; + signal SBC_N : std_logic; + signal SBC_Q : std_logic_vector(7 downto 0); + +begin + + process (P_In, BusA, BusB) + variable AL : unsigned(6 downto 0); + variable AH : unsigned(6 downto 0); + variable C : std_logic; + begin + AL := resize(unsigned(BusA(3 downto 0) & P_In(Flag_C)), 7) + resize(unsigned(BusB(3 downto 0) & "1"), 7); + AH := resize(unsigned(BusA(7 downto 4) & AL(5)), 7) + resize(unsigned(BusB(7 downto 4) & "1"), 7); + +-- pragma translate_off + if is_x(std_logic_vector(AL)) then AL := "0000000"; end if; + if is_x(std_logic_vector(AH)) then AH := "0000000"; end if; +-- pragma translate_on + + if AL(4 downto 1) = 0 and AH(4 downto 1) = 0 then + ADC_Z <= '1'; + else + ADC_Z <= '0'; + end if; + + if AL(5 downto 1) > 9 and P_In(Flag_D) = '1' then + AL(6 downto 1) := AL(6 downto 1) + 6; + end if; + + C := AL(6) or AL(5); + AH := resize(unsigned(BusA(7 downto 4) & C), 7) + resize(unsigned(BusB(7 downto 4) & "1"), 7); + + ADC_N <= AH(4); + ADC_V <= (AH(4) xor BusA(7)) and not (BusA(7) xor BusB(7)); + +-- pragma translate_off + if is_x(std_logic_vector(AH)) then AH := "0000000"; end if; +-- pragma translate_on + + if AH(5 downto 1) > 9 and P_In(Flag_D) = '1' then + AH(6 downto 1) := AH(6 downto 1) + 6; + end if; + + ADC_C <= AH(6) or AH(5); + + ADC_Q <= std_logic_vector(AH(4 downto 1) & AL(4 downto 1)); + end process; + + process (Op, P_In, BusA, BusB) + variable AL : unsigned(6 downto 0); + variable AH : unsigned(5 downto 0); + variable C : std_logic; + begin + C := P_In(Flag_C) or not Op(0); + AL := resize(unsigned(BusA(3 downto 0) & C), 7) - resize(unsigned(BusB(3 downto 0) & "1"), 6); + AH := resize(unsigned(BusA(7 downto 4) & "0"), 6) - resize(unsigned(BusB(7 downto 4) & AL(5)), 6); + +-- pragma translate_off + if is_x(std_logic_vector(AL)) then AL := "0000000"; end if; + if is_x(std_logic_vector(AH)) then AH := "000000"; end if; +-- pragma translate_on + + if AL(4 downto 1) = 0 and AH(4 downto 1) = 0 then + SBC_Z <= '1'; + else + SBC_Z <= '0'; + end if; + + SBC_C <= not AH(5); + SBC_V <= (AH(4) xor BusA(7)) and (BusA(7) xor BusB(7)); + SBC_N <= AH(4); + + if P_In(Flag_D) = '1' then + if AL(5) = '1' then + AL(5 downto 1) := AL(5 downto 1) - 6; + end if; + AH := resize(unsigned(BusA(7 downto 4) & "0"), 6) - resize(unsigned(BusB(7 downto 4) & AL(6)), 6); + if AH(5) = '1' then + AH(5 downto 1) := AH(5 downto 1) - 6; + end if; + end if; + + SBC_Q <= std_logic_vector(AH(4 downto 1) & AL(4 downto 1)); + end process; + + process (Op, P_In, BusA, BusB, + ADC_Z, ADC_C, ADC_V, ADC_N, ADC_Q, + SBC_Z, SBC_C, SBC_V, SBC_N, SBC_Q) + variable Q_t : std_logic_vector(7 downto 0); + begin + -- ORA, AND, EOR, ADC, NOP, LD, CMP, SBC + -- ASL, ROL, LSR, ROR, BIT, LD, DEC, INC + P_Out <= P_In; + Q_t := BusA; + case Op(3 downto 0) is + when "0000" => + -- ORA + Q_t := BusA or BusB; + when "0001" => + -- AND + Q_t := BusA and BusB; + when "0010" => + -- EOR + Q_t := BusA xor BusB; + when "0011" => + -- ADC + P_Out(Flag_V) <= ADC_V; + P_Out(Flag_C) <= ADC_C; + Q_t := ADC_Q; + when "0101" | "1101" => + -- LDA + when "0110" => + -- CMP + P_Out(Flag_C) <= SBC_C; + when "0111" => + -- SBC + P_Out(Flag_V) <= SBC_V; + P_Out(Flag_C) <= SBC_C; + Q_t := SBC_Q; + when "1000" => + -- ASL + Q_t := BusA(6 downto 0) & "0"; + P_Out(Flag_C) <= BusA(7); + when "1001" => + -- ROL + Q_t := BusA(6 downto 0) & P_In(Flag_C); + P_Out(Flag_C) <= BusA(7); + when "1010" => + -- LSR + Q_t := "0" & BusA(7 downto 1); + P_Out(Flag_C) <= BusA(0); + when "1011" => + -- ROR + Q_t := P_In(Flag_C) & BusA(7 downto 1); + P_Out(Flag_C) <= BusA(0); + when "1100" => + -- BIT + P_Out(Flag_V) <= BusB(6); + when "1110" => + -- DEC + Q_t := std_logic_vector(unsigned(BusA) - 1); + when "1111" => + -- INC + Q_t := std_logic_vector(unsigned(BusA) + 1); + when others => + end case; + + case Op(3 downto 0) is + when "0011" => + P_Out(Flag_N) <= ADC_N; + P_Out(Flag_Z) <= ADC_Z; + when "0110" | "0111" => + P_Out(Flag_N) <= SBC_N; + P_Out(Flag_Z) <= SBC_Z; + when "0100" => + when "1100" => + P_Out(Flag_N) <= BusB(7); + if (BusA and BusB) = "00000000" then + P_Out(Flag_Z) <= '1'; + else + P_Out(Flag_Z) <= '0'; + end if; + when others => + P_Out(Flag_N) <= Q_t(7); + if Q_t = "00000000" then + P_Out(Flag_Z) <= '1'; + else + P_Out(Flag_Z) <= '0'; + end if; + end case; + + Q <= Q_t; + end process; + +end; diff --git a/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/t65/T65_MCode.vhd b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/t65/T65_MCode.vhd new file mode 100644 index 0000000000000000000000000000000000000000..6c6c864a42932722a2295f600393342614ac4c12 --- /dev/null +++ b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/t65/T65_MCode.vhd @@ -0,0 +1,1052 @@ +-- **** +-- T65(b) core. In an effort to merge and maintain bug fixes .... +-- +-- +-- Ver 302 minor timing fixes +-- Ver 301 Jump timing fixed +-- Ver 300 Bugfixes by ehenciak added +-- MikeJ March 2005 +-- Latest version from www.fpgaarcade.com (original www.opencores.org) +-- +-- **** +-- +-- 65xx compatible microprocessor core +-- +-- Version : 0246 + fix +-- +-- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.opencores.org/cvsweb.shtml/t65/ +-- +-- Limitations : +-- +-- 65C02 +-- supported : inc, dec, phx, plx, phy, ply +-- missing : bra, ora, lda, cmp, sbc, tsb*2, trb*2, stz*2, bit*2, wai, stp, jmp, bbr*8, bbs*8 +-- +-- File history : +-- +-- 0246 : First release +-- + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; +use work.T65_Pack.all; + +entity T65_MCode is + port( + Mode : in std_logic_vector(1 downto 0); -- "00" => 6502, "01" => 65C02, "10" => 65816 + IR : in std_logic_vector(7 downto 0); + MCycle : in std_logic_vector(2 downto 0); + P : in std_logic_vector(7 downto 0); + LCycle : out std_logic_vector(2 downto 0); + ALU_Op : out std_logic_vector(3 downto 0); + Set_BusA_To : out std_logic_vector(2 downto 0); -- DI,A,X,Y,S,P + Set_Addr_To : out std_logic_vector(1 downto 0); -- PC Adder,S,AD,BA + Write_Data : out std_logic_vector(2 downto 0); -- DL,A,X,Y,S,P,PCL,PCH + Jump : out std_logic_vector(1 downto 0); -- PC,++,DIDL,Rel + BAAdd : out std_logic_vector(1 downto 0); -- None,DB Inc,BA Add,BA Adj + BreakAtNA : out std_logic; + ADAdd : out std_logic; + AddY : out std_logic; + PCAdd : out std_logic; + Inc_S : out std_logic; + Dec_S : out std_logic; + LDA : out std_logic; + LDP : out std_logic; + LDX : out std_logic; + LDY : out std_logic; + LDS : out std_logic; + LDDI : out std_logic; + LDALU : out std_logic; + LDAD : out std_logic; + LDBAL : out std_logic; + LDBAH : out std_logic; + SaveP : out std_logic; + Write : out std_logic + ); +end T65_MCode; + +architecture rtl of T65_MCode is + + signal Branch : std_logic; + +begin + + with IR(7 downto 5) select + Branch <= not P(Flag_N) when "000", + P(Flag_N) when "001", + not P(Flag_V) when "010", + P(Flag_V) when "011", + not P(Flag_C) when "100", + P(Flag_C) when "101", + not P(Flag_Z) when "110", + P(Flag_Z) when others; + + process (IR, MCycle, P, Branch, Mode) + begin + LCycle <= "001"; + Set_BusA_To <= "001"; -- A + Set_Addr_To <= (others => '0'); + Write_Data <= (others => '0'); + Jump <= (others => '0'); + BAAdd <= "00"; + BreakAtNA <= '0'; + ADAdd <= '0'; + PCAdd <= '0'; + Inc_S <= '0'; + Dec_S <= '0'; + LDA <= '0'; + LDP <= '0'; + LDX <= '0'; + LDY <= '0'; + LDS <= '0'; + LDDI <= '0'; + LDALU <= '0'; + LDAD <= '0'; + LDBAL <= '0'; + LDBAH <= '0'; + SaveP <= '0'; + Write <= '0'; + AddY <= '0'; + + case IR(7 downto 5) is + when "100" => + --{{{ + case IR(1 downto 0) is + when "00" => + Set_BusA_To <= "011"; -- Y + Write_Data <= "011"; -- Y + when "10" => + Set_BusA_To <= "010"; -- X + Write_Data <= "010"; -- X + when others => + Write_Data <= "001"; -- A + end case; + --}}} + when "101" => + --{{{ + case IR(1 downto 0) is + when "00" => + if IR(4) /= '1' or IR(2) /= '0' then + LDY <= '1'; + end if; + when "10" => + LDX <= '1'; + when others => + LDA <= '1'; + end case; + Set_BusA_To <= "000"; -- DI + --}}} + when "110" => + --{{{ + case IR(1 downto 0) is + when "00" => + if IR(4) = '0' then + LDY <= '1'; + end if; + Set_BusA_To <= "011"; -- Y + when others => + Set_BusA_To <= "001"; -- A + end case; + --}}} + when "111" => + --{{{ + case IR(1 downto 0) is + when "00" => + if IR(4) = '0' then + LDX <= '1'; + end if; + Set_BusA_To <= "010"; -- X + when others => + Set_BusA_To <= "001"; -- A + end case; + --}}} + when others => + end case; + + if IR(7 downto 6) /= "10" and IR(1 downto 0) = "10" then + Set_BusA_To <= "000"; -- DI + end if; + + case IR(4 downto 0) is + when "00000" | "01000" | "01010" | "11000" | "11010" => + --{{{ + -- Implied + case IR is + when "00000000" => + -- BRK + LCycle <= "110"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= "01"; -- S + Write_Data <= "111"; -- PCH + Write <= '1'; + when 2 => + Dec_S <= '1'; + Set_Addr_To <= "01"; -- S + Write_Data <= "110"; -- PCL + Write <= '1'; + when 3 => + Dec_S <= '1'; + Set_Addr_To <= "01"; -- S + Write_Data <= "101"; -- P + Write <= '1'; + when 4 => + Dec_S <= '1'; + Set_Addr_To <= "11"; -- BA + when 5 => + LDDI <= '1'; + Set_Addr_To <= "11"; -- BA + when 6 => + Jump <= "10"; -- DIDL + when others => + end case; + when "00100000" => + -- JSR + LCycle <= "101"; + case to_integer(unsigned(MCycle)) is + when 1 => + Jump <= "01"; + LDDI <= '1'; + Set_Addr_To <= "01"; -- S + when 2 => + Set_Addr_To <= "01"; -- S + Write_Data <= "111"; -- PCH + Write <= '1'; + when 3 => + Dec_S <= '1'; + Set_Addr_To <= "01"; -- S + Write_Data <= "110"; -- PCL + Write <= '1'; + when 4 => + Dec_S <= '1'; + when 5 => + Jump <= "10"; -- DIDL + when others => + end case; + when "01000000" => + -- RTI + LCycle <= "101"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= "01"; -- S + when 2 => + Inc_S <= '1'; + Set_Addr_To <= "01"; -- S + when 3 => + Inc_S <= '1'; + Set_Addr_To <= "01"; -- S + Set_BusA_To <= "000"; -- DI + when 4 => + LDP <= '1'; + Inc_S <= '1'; + LDDI <= '1'; + Set_Addr_To <= "01"; -- S + when 5 => + Jump <= "10"; -- DIDL + when others => + end case; + when "01100000" => + -- RTS + LCycle <= "101"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= "01"; -- S + when 2 => + Inc_S <= '1'; + Set_Addr_To <= "01"; -- S + when 3 => + Inc_S <= '1'; + LDDI <= '1'; + Set_Addr_To <= "01"; -- S + when 4 => + Jump <= "10"; -- DIDL + when 5 => + Jump <= "01"; + when others => + end case; + when "00001000" | "01001000" | "01011010" | "11011010" => + -- PHP, PHA, PHY*, PHX* + LCycle <= "010"; + if Mode = "00" and IR(1) = '1' then + LCycle <= "001"; + end if; + case to_integer(unsigned(MCycle)) is + when 1 => + case IR(7 downto 4) is + when "0000" => + Write_Data <= "101"; -- P + when "0100" => + Write_Data <= "001"; -- A + when "0101" => + Write_Data <= "011"; -- Y + when "1101" => + Write_Data <= "010"; -- X + when others => + end case; + Write <= '1'; + Set_Addr_To <= "01"; -- S + when 2 => + Dec_S <= '1'; + when others => + end case; + when "00101000" | "01101000" | "01111010" | "11111010" => + -- PLP, PLA, PLY*, PLX* + LCycle <= "011"; + if Mode = "00" and IR(1) = '1' then + LCycle <= "001"; + end if; + case IR(7 downto 4) is + when "0010" => + LDP <= '1'; + when "0110" => + LDA <= '1'; + when "0111" => + if Mode /= "00" then + LDY <= '1'; + end if; + when "1111" => + if Mode /= "00" then + LDX <= '1'; + end if; + when others => + end case; + case to_integer(unsigned(MCycle)) is + when 0 => + SaveP <= '1'; + when 1 => + Set_Addr_To <= "01"; -- S + when 2 => + Inc_S <= '1'; + Set_Addr_To <= "01"; -- S + when 3 => + Set_BusA_To <= "000"; -- DI + when others => + end case; + when "10100000" | "11000000" | "11100000" => + -- LDY, CPY, CPX + -- Immediate + case to_integer(unsigned(MCycle)) is + when 0 => + when 1 => + Jump <= "01"; + when others => + end case; + when "10001000" => + -- DEY + LDY <= '1'; + case to_integer(unsigned(MCycle)) is + when 0 => + when 1 => + Set_BusA_To <= "011"; -- Y + when others => + end case; + when "11001010" => + -- DEX + LDX <= '1'; + case to_integer(unsigned(MCycle)) is + when 0 => + when 1 => + Set_BusA_To <= "010"; -- X + when others => + end case; + when "00011010" | "00111010" => + -- INC*, DEC* + if Mode /= "00" then + LDA <= '1'; -- A + end if; + case to_integer(unsigned(MCycle)) is + when 0 => + when 1 => + Set_BusA_To <= "100"; -- S + when others => + end case; + when "00001010" | "00101010" | "01001010" | "01101010" => + -- ASL, ROL, LSR, ROR + LDA <= '1'; -- A + Set_BusA_To <= "001"; -- A + case to_integer(unsigned(MCycle)) is + when 0 => + when 1 => + when others => + end case; + when "10001010" | "10011000" => + -- TYA, TXA + LDA <= '1'; -- A + case to_integer(unsigned(MCycle)) is + when 0 => + when 1 => + when others => + end case; + when "10101010" | "10101000" => + -- TAX, TAY + case to_integer(unsigned(MCycle)) is + when 0 => + when 1 => + Set_BusA_To <= "001"; -- A + when others => + end case; + when "10011010" => + -- TXS + case to_integer(unsigned(MCycle)) is + when 0 => + LDS <= '1'; + when 1 => + when others => + end case; + when "10111010" => + -- TSX + LDX <= '1'; + case to_integer(unsigned(MCycle)) is + when 0 => + when 1 => + Set_BusA_To <= "100"; -- S + when others => + end case; + + -- when "00011000" | "00111000" | "01011000" | "01111000" | "10111000" | "11011000" | "11111000" | "11001000" | "11101000" => + -- -- CLC, SEC, CLI, SEI, CLV, CLD, SED, INY, INX + -- case to_integer(unsigned(MCycle)) is + -- when 1 => + -- when others => + -- end case; + when others => + case to_integer(unsigned(MCycle)) is + when 0 => + when others => + end case; + end case; + --}}} + + when "00001" | "00011" => + --{{{ + -- Zero Page Indexed Indirect (d,x) + LCycle <= "101"; + if IR(7 downto 6) /= "10" then + LDA <= '1'; + end if; + case to_integer(unsigned(MCycle)) is + when 0 => + when 1 => + Jump <= "01"; + LDAD <= '1'; + Set_Addr_To <= "10"; -- AD + when 2 => + ADAdd <= '1'; + Set_Addr_To <= "10"; -- AD + when 3 => + BAAdd <= "01"; -- DB Inc + LDBAL <= '1'; + Set_Addr_To <= "10"; -- AD + when 4 => + LDBAH <= '1'; + if IR(7 downto 5) = "100" then + Write <= '1'; + end if; + Set_Addr_To <= "11"; -- BA + when 5 => + when others => + end case; + --}}} + + when "01001" | "01011" => + --{{{ + -- Immediate + LDA <= '1'; + case to_integer(unsigned(MCycle)) is + when 0 => + when 1 => + Jump <= "01"; + when others => + end case; + + --}}} + + when "00010" | "10010" => + --{{{ + -- Immediate, KIL + LDX <= '1'; + case to_integer(unsigned(MCycle)) is + when 0 => + when 1 => + if IR = "10100010" then + -- LDX + Jump <= "01"; + else + -- KIL !!!!!!!!!!!!!!!!!!!!!!!!!!!!! + end if; + when others => + end case; + --}}} + + when "00100" => + --{{{ + -- Zero Page + LCycle <= "010"; + case to_integer(unsigned(MCycle)) is + when 0 => + if IR(7 downto 5) = "001" then + SaveP <= '1'; + end if; + when 1 => + Jump <= "01"; + LDAD <= '1'; + if IR(7 downto 5) = "100" then + Write <= '1'; + end if; + Set_Addr_To <= "10"; -- AD + when 2 => + when others => + end case; + --}}} + + when "00101" | "00110" | "00111" => + --{{{ + -- Zero Page + if IR(7 downto 6) /= "10" and IR(1 downto 0) = "10" then + -- Read-Modify-Write + LCycle <= "100"; + case to_integer(unsigned(MCycle)) is + when 1 => + Jump <= "01"; + LDAD <= '1'; + Set_Addr_To <= "10"; -- AD + when 2 => + LDDI <= '1'; + Write <= '1'; + Set_Addr_To <= "10"; -- AD + when 3 => + LDALU <= '1'; + SaveP <= '1'; + Write <= '1'; + Set_Addr_To <= "10"; -- AD + when 4 => + when others => + end case; + else + LCycle <= "010"; + if IR(7 downto 6) /= "10" then + LDA <= '1'; + end if; + case to_integer(unsigned(MCycle)) is + when 0 => + when 1 => + Jump <= "01"; + LDAD <= '1'; + if IR(7 downto 5) = "100" then + Write <= '1'; + end if; + Set_Addr_To <= "10"; -- AD + when 2 => + when others => + end case; + end if; + --}}} + + when "01100" => + --{{{ + -- Absolute + if IR(7 downto 6) = "01" and IR(4 downto 0) = "01100" then + -- JMP + if IR(5) = '0' then + --LCycle <= "011"; + LCycle <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Jump <= "01"; + LDDI <= '1'; + when 2 => + Jump <= "10"; -- DIDL + when others => + end case; + else + --LCycle <= "101"; + LCycle <= "100"; -- mikej + case to_integer(unsigned(MCycle)) is + when 1 => + Jump <= "01"; + LDDI <= '1'; + LDBAL <= '1'; + when 2 => + LDBAH <= '1'; + if Mode /= "00" then + Jump <= "10"; -- DIDL + end if; + if Mode = "00" then + Set_Addr_To <= "11"; -- BA + end if; + when 3 => + LDDI <= '1'; + if Mode = "00" then + Set_Addr_To <= "11"; -- BA + BAAdd <= "01"; -- DB Inc + else + Jump <= "01"; + end if; + when 4 => + Jump <= "10"; -- DIDL + when others => + end case; + end if; + else + LCycle <= "011"; + case to_integer(unsigned(MCycle)) is + when 0 => + if IR(7 downto 5) = "001" then + SaveP <= '1'; + end if; + when 1 => + Jump <= "01"; + LDBAL <= '1'; + when 2 => + Jump <= "01"; + LDBAH <= '1'; + if IR(7 downto 5) = "100" then + Write <= '1'; + end if; + Set_Addr_To <= "11"; -- BA + when 3 => + when others => + end case; + end if; + --}}} + + when "01101" | "01110" | "01111" => + --{{{ + -- Absolute + if IR(7 downto 6) /= "10" and IR(1 downto 0) = "10" then + -- Read-Modify-Write + LCycle <= "101"; + case to_integer(unsigned(MCycle)) is + when 1 => + Jump <= "01"; + LDBAL <= '1'; + when 2 => + Jump <= "01"; + LDBAH <= '1'; + Set_Addr_To <= "11"; -- BA + when 3 => + LDDI <= '1'; + Write <= '1'; + Set_Addr_To <= "11"; -- BA + when 4 => + Write <= '1'; + LDALU <= '1'; + SaveP <= '1'; + Set_Addr_To <= "11"; -- BA + when 5 => + SaveP <= '0'; -- MIKEJ was 1 + when others => + end case; + else + LCycle <= "011"; + if IR(7 downto 6) /= "10" then + LDA <= '1'; + end if; + case to_integer(unsigned(MCycle)) is + when 0 => + when 1 => + Jump <= "01"; + LDBAL <= '1'; + when 2 => + Jump <= "01"; + LDBAH <= '1'; + if IR(7 downto 5) = "100" then + Write <= '1'; + end if; + Set_Addr_To <= "11"; -- BA + when 3 => + when others => + end case; + end if; + --}}} + + when "10000" => + --{{{ + -- Relative + + -- This circuit dictates when the last + -- microcycle occurs for the branch depending on + -- whether or not the branch is taken and if a page + -- is crossed... + if (Branch = '1') then + + LCycle <= "011"; -- We're done @ T3 if branching...upper + -- level logic will stop at T2 if no page cross + -- (See the Break signal) + else + + LCycle <= "001"; + + end if; + + -- This decodes the current microcycle and takes the + -- proper course of action... + case to_integer(unsigned(MCycle)) is + + -- On the T1 microcycle, increment the program counter + -- and instruct the upper level logic to fetch the offset + -- from the Din bus and store it in the data latches. This + -- will be the last microcycle if the branch isn't taken. + when 1 => + + Jump <= "01"; -- Increments the PC by one (PC will now be PC+2) + -- from microcycle T0. + + LDDI <= '1'; -- Tells logic in top level (T65.vhd) to route + -- the Din bus to the memory data latch (DL) + -- so that the branch offset is fetched. + + -- In microcycle T2, tell the logic in the top level to + -- add the offset. If the most significant byte of the + -- program counter (i.e. the current "page") does not need + -- updating, we are done here...the Break signal at the + -- T65.vhd level takes care of that... + when 2 => + + Jump <= "11"; -- Tell the PC Jump logic to use relative mode. + + PCAdd <= '1'; -- This tells the PC adder to update itself with + -- the current offset recently fetched from + -- memory. + + -- The following is microcycle T3 : + -- The program counter should be completely updated + -- on this cycle after the page cross is detected. + -- We don't need to do anything here... + when 3 => + + + when others => null; -- Do nothing. + + end case; + --}}} + + when "10001" | "10011" => + --{{{ + -- Zero Page Indirect Indexed (d),y + LCycle <= "101"; + if IR(7 downto 6) /= "10" then + LDA <= '1'; + end if; + case to_integer(unsigned(MCycle)) is + when 0 => + when 1 => + Jump <= "01"; + LDAD <= '1'; + Set_Addr_To <= "10"; -- AD + when 2 => + LDBAL <= '1'; + BAAdd <= "01"; -- DB Inc + Set_Addr_To <= "10"; -- AD + when 3 => + Set_BusA_To <= "011"; -- Y + BAAdd <= "10"; -- BA Add + LDBAH <= '1'; + Set_Addr_To <= "11"; -- BA + when 4 => + BAAdd <= "11"; -- BA Adj + if IR(7 downto 5) = "100" then + Write <= '1'; + else + BreakAtNA <= '1'; + end if; + Set_Addr_To <= "11"; -- BA + when 5 => + when others => + end case; + --}}} + + when "10100" | "10101" | "10110" | "10111" => + --{{{ + -- Zero Page, X + if IR(7 downto 6) /= "10" and IR(1 downto 0) = "10" then + -- Read-Modify-Write + LCycle <= "101"; + case to_integer(unsigned(MCycle)) is + when 1 => + Jump <= "01"; + LDAD <= '1'; + Set_Addr_To <= "10"; -- AD + when 2 => + ADAdd <= '1'; + Set_Addr_To <= "10"; -- AD + when 3 => + LDDI <= '1'; + Write <= '1'; + Set_Addr_To <= "10"; -- AD + when 4 => + LDALU <= '1'; + SaveP <= '1'; + Write <= '1'; + Set_Addr_To <= "10"; -- AD + when 5 => + when others => + end case; + else + LCycle <= "011"; + if IR(7 downto 6) /= "10" then + LDA <= '1'; + end if; + case to_integer(unsigned(MCycle)) is + when 0 => + when 1 => + Jump <= "01"; + LDAD <= '1'; + Set_Addr_To <= "10"; -- AD + when 2 => + ADAdd <= '1'; + -- Added this check for Y reg. use... + if (IR(3 downto 0) = "0110") then + AddY <= '1'; + end if; + + if IR(7 downto 5) = "100" then + Write <= '1'; + end if; + Set_Addr_To <= "10"; -- AD + when 3 => null; + when others => + end case; + end if; + --}}} + + when "11001" | "11011" => + --{{{ + -- Absolute Y + LCycle <= "100"; + if IR(7 downto 6) /= "10" then + LDA <= '1'; + end if; + case to_integer(unsigned(MCycle)) is + when 0 => + when 1 => + Jump <= "01"; + LDBAL <= '1'; + when 2 => + Jump <= "01"; + Set_BusA_To <= "011"; -- Y + BAAdd <= "10"; -- BA Add + LDBAH <= '1'; + Set_Addr_To <= "11"; -- BA + when 3 => + BAAdd <= "11"; -- BA adj + if IR(7 downto 5) = "100" then + Write <= '1'; + else + BreakAtNA <= '1'; + end if; + Set_Addr_To <= "11"; -- BA + when 4 => + when others => + end case; + --}}} + + when "11100" | "11101" | "11110" | "11111" => + --{{{ + -- Absolute X + + if IR(7 downto 6) /= "10" and IR(1 downto 0) = "10" then + -- Read-Modify-Write + LCycle <= "110"; + case to_integer(unsigned(MCycle)) is + when 1 => + Jump <= "01"; + LDBAL <= '1'; + when 2 => + Jump <= "01"; + Set_BusA_To <= "010"; -- X + BAAdd <= "10"; -- BA Add + LDBAH <= '1'; + Set_Addr_To <= "11"; -- BA + when 3 => + BAAdd <= "11"; -- BA adj + Set_Addr_To <= "11"; -- BA + when 4 => + LDDI <= '1'; + Write <= '1'; + Set_Addr_To <= "11"; -- BA + when 5 => + LDALU <= '1'; + SaveP <= '1'; + Write <= '1'; + Set_Addr_To <= "11"; -- BA + when 6 => + when others => + end case; + else + LCycle <= "100"; + if IR(7 downto 6) /= "10" then + LDA <= '1'; + end if; + case to_integer(unsigned(MCycle)) is + when 0 => + when 1 => + Jump <= "01"; + LDBAL <= '1'; + when 2 => + Jump <= "01"; + -- mikej + -- special case 0xBE which uses Y reg as index!! + if (IR = "10111110") then + Set_BusA_To <= "011"; -- Y + else + Set_BusA_To <= "010"; -- X + end if; + BAAdd <= "10"; -- BA Add + LDBAH <= '1'; + Set_Addr_To <= "11"; -- BA + when 3 => + BAAdd <= "11"; -- BA adj + if IR(7 downto 5) = "100" then + Write <= '1'; + else + BreakAtNA <= '1'; + end if; + Set_Addr_To <= "11"; -- BA + when 4 => + when others => + end case; + end if; + --}}} + when others => + end case; + end process; + + process (IR, MCycle) + begin + -- ORA, AND, EOR, ADC, NOP, LD, CMP, SBC + -- ASL, ROL, LSR, ROR, BIT, LD, DEC, INC + case IR(1 downto 0) is + when "00" => + --{{{ + case IR(4 downto 2) is + when "000" | "001" | "011" => + case IR(7 downto 5) is + when "110" | "111" => + -- CP + ALU_Op <= "0110"; + when "101" => + -- LD + ALU_Op <= "0101"; + when "001" => + -- BIT + ALU_Op <= "1100"; + when others => + -- NOP/ST + ALU_Op <= "0100"; + end case; + when "010" => + case IR(7 downto 5) is + when "111" | "110" => + -- IN + ALU_Op <= "1111"; + when "100" => + -- DEY + ALU_Op <= "1110"; + when others => + -- LD + ALU_Op <= "1101"; + end case; + when "110" => + case IR(7 downto 5) is + when "100" => + -- TYA + ALU_Op <= "1101"; + when others => + ALU_Op <= "----"; + end case; + when others => + case IR(7 downto 5) is + when "101" => + -- LD + ALU_Op <= "1101"; + when others => + ALU_Op <= "0100"; + end case; + end case; + --}}} + when "01" => -- OR + --{{{ + ALU_Op(3) <= '0'; + ALU_Op(2 downto 0) <= IR(7 downto 5); + --}}} + when "10" => + --{{{ + ALU_Op(3) <= '1'; + ALU_Op(2 downto 0) <= IR(7 downto 5); + case IR(7 downto 5) is + when "000" => + if IR(4 downto 2) = "110" then + -- INC + ALU_Op <= "1111"; + end if; + when "001" => + if IR(4 downto 2) = "110" then + -- DEC + ALU_Op <= "1110"; + end if; + when "100" => + if IR(4 downto 2) = "010" then + -- TXA + ALU_Op <= "0101"; + else + ALU_Op <= "0100"; + end if; + when others => + end case; + --}}} + when others => + --{{{ + case IR(7 downto 5) is + when "100" => + ALU_Op <= "0100"; + when others => + if MCycle = "000" then + ALU_Op(3) <= '0'; + ALU_Op(2 downto 0) <= IR(7 downto 5); + else + ALU_Op(3) <= '1'; + ALU_Op(2 downto 0) <= IR(7 downto 5); + end if; + end case; + --}}} + end case; + end process; + +end; diff --git a/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/t65/T65_Pack.vhd b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/t65/T65_Pack.vhd new file mode 100644 index 0000000000000000000000000000000000000000..e025e1bff71fc4acd32fcd68917e1a1091668220 --- /dev/null +++ b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/t65/T65_Pack.vhd @@ -0,0 +1,117 @@ +-- **** +-- T65(b) core. In an effort to merge and maintain bug fixes .... +-- +-- +-- Ver 300 Bugfixes by ehenciak added +-- MikeJ March 2005 +-- Latest version from www.fpgaarcade.com (original www.opencores.org) +-- +-- **** +-- +-- 65xx compatible microprocessor core +-- +-- Version : 0246 +-- +-- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.opencores.org/cvsweb.shtml/t65/ +-- +-- Limitations : +-- +-- File history : +-- + +library IEEE; +use IEEE.std_logic_1164.all; + +package T65_Pack is + + constant Flag_C : integer := 0; + constant Flag_Z : integer := 1; + constant Flag_I : integer := 2; + constant Flag_D : integer := 3; + constant Flag_B : integer := 4; + constant Flag_1 : integer := 5; + constant Flag_V : integer := 6; + constant Flag_N : integer := 7; + + component T65_MCode + port( + Mode : in std_logic_vector(1 downto 0); -- "00" => 6502, "01" => 65C02, "10" => 65816 + IR : in std_logic_vector(7 downto 0); + MCycle : in std_logic_vector(2 downto 0); + P : in std_logic_vector(7 downto 0); + LCycle : out std_logic_vector(2 downto 0); + ALU_Op : out std_logic_vector(3 downto 0); + Set_BusA_To : out std_logic_vector(2 downto 0); -- DI,A,X,Y,S,P + Set_Addr_To : out std_logic_vector(1 downto 0); -- PC Adder,S,AD,BA + Write_Data : out std_logic_vector(2 downto 0); -- DL,A,X,Y,S,P,PCL,PCH + Jump : out std_logic_vector(1 downto 0); -- PC,++,DIDL,Rel + BAAdd : out std_logic_vector(1 downto 0); -- None,DB Inc,BA Add,BA Adj + BreakAtNA : out std_logic; + ADAdd : out std_logic; + AddY : out std_logic; + PCAdd : out std_logic; + Inc_S : out std_logic; + Dec_S : out std_logic; + LDA : out std_logic; + LDP : out std_logic; + LDX : out std_logic; + LDY : out std_logic; + LDS : out std_logic; + LDDI : out std_logic; + LDALU : out std_logic; + LDAD : out std_logic; + LDBAL : out std_logic; + LDBAH : out std_logic; + SaveP : out std_logic; + Write : out std_logic + ); + end component; + + component T65_ALU + port( + Mode : in std_logic_vector(1 downto 0); -- "00" => 6502, "01" => 65C02, "10" => 65C816 + Op : in std_logic_vector(3 downto 0); + BusA : in std_logic_vector(7 downto 0); + BusB : in std_logic_vector(7 downto 0); + P_In : in std_logic_vector(7 downto 0); + P_Out : out std_logic_vector(7 downto 0); + Q : out std_logic_vector(7 downto 0) + ); + end component; + +end; diff --git a/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/t65/t65.v b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/t65/t65.v new file mode 100644 index 0000000000000000000000000000000000000000..9c032c95d3e3561a191f7c4457f3e3e55d4c17ec --- /dev/null +++ b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/t65/t65.v @@ -0,0 +1,6827 @@ +// Converted from T65 VHDL code using GHDL 3.0.0-dev (v2.0.0-1267-gd82550423) [Dunoon edition] +module t65_alu + (input [1:0] mode, + input [3:0] op, + input [7:0] busa, + input [7:0] busb, + input [7:0] p_in, + output [7:0] p_out, + output [7:0] q); + wire adc_z; + wire adc_c; + wire adc_v; + wire adc_n; + wire [7:0] adc_q; + wire sbc_z; + wire sbc_c; + wire sbc_v; + wire sbc_n; + wire [7:0] sbc_q; + wire [3:0] n2531_o; + wire n2532_o; + wire [4:0] n2533_o; + wire [6:0] n2534_o; + wire [3:0] n2535_o; + wire [4:0] n2537_o; + wire [6:0] n2538_o; + wire [6:0] n2539_o; + wire [3:0] n2540_o; + wire n2541_o; + wire [4:0] n2542_o; + wire [6:0] n2543_o; + wire [3:0] n2544_o; + wire [4:0] n2546_o; + wire [6:0] n2547_o; + wire [6:0] n2548_o; + wire [3:0] n2549_o; + wire n2551_o; + wire [3:0] n2552_o; + wire n2554_o; + wire n2555_o; + wire n2558_o; + wire [4:0] n2559_o; + wire n2561_o; + wire n2562_o; + wire n2563_o; + wire [5:0] n2564_o; + wire [5:0] n2566_o; + wire [5:0] n2567_o; + wire [5:0] n2568_o; + wire n2569_o; + wire [6:0] n2570_o; + wire n2571_o; + wire [6:0] n2572_o; + wire n2573_o; + wire n2574_o; + wire [3:0] n2575_o; + wire [4:0] n2576_o; + wire [6:0] n2577_o; + wire [3:0] n2578_o; + wire [4:0] n2580_o; + wire [6:0] n2581_o; + wire [6:0] n2582_o; + wire n2583_o; + wire n2584_o; + wire n2585_o; + wire n2586_o; + wire n2587_o; + wire n2588_o; + wire n2589_o; + wire n2590_o; + wire n2591_o; + wire [4:0] n2592_o; + wire n2594_o; + wire n2595_o; + wire n2596_o; + wire [5:0] n2597_o; + wire [5:0] n2599_o; + wire [5:0] n2600_o; + wire [5:0] n2601_o; + wire n2602_o; + wire [6:0] n2603_o; + wire n2604_o; + wire [6:0] n2605_o; + wire n2606_o; + wire n2607_o; + wire [6:0] n2608_o; + wire [3:0] n2609_o; + wire [6:0] n2610_o; + wire [3:0] n2611_o; + wire [7:0] n2612_o; + wire n2621_o; + wire n2622_o; + wire n2623_o; + wire n2624_o; + wire [3:0] n2625_o; + wire [4:0] n2626_o; + wire [6:0] n2627_o; + wire [3:0] n2628_o; + wire [4:0] n2630_o; + wire [5:0] n2631_o; + wire [6:0] n2632_o; + wire [6:0] n2633_o; + wire [3:0] n2634_o; + wire [4:0] n2636_o; + wire [5:0] n2637_o; + wire [3:0] n2638_o; + wire n2639_o; + wire [4:0] n2640_o; + wire [5:0] n2641_o; + wire [5:0] n2642_o; + wire [3:0] n2643_o; + wire n2645_o; + wire [3:0] n2646_o; + wire n2648_o; + wire n2649_o; + wire n2652_o; + wire n2653_o; + wire n2654_o; + wire n2655_o; + wire n2656_o; + wire n2657_o; + wire n2658_o; + wire n2659_o; + wire n2660_o; + wire n2661_o; + wire n2662_o; + wire n2663_o; + wire n2664_o; + wire [4:0] n2665_o; + wire [4:0] n2667_o; + wire [4:0] n2668_o; + wire [4:0] n2669_o; + wire [3:0] n2670_o; + wire [4:0] n2672_o; + wire [5:0] n2673_o; + wire [3:0] n2674_o; + wire n2675_o; + wire n2676_o; + wire [6:0] n2677_o; + wire n2678_o; + wire [4:0] n2679_o; + wire [5:0] n2680_o; + wire [5:0] n2681_o; + wire n2682_o; + wire [4:0] n2683_o; + wire [4:0] n2685_o; + wire [4:0] n2686_o; + wire [4:0] n2687_o; + wire n2688_o; + wire [4:0] n2689_o; + wire [4:0] n2690_o; + wire n2691_o; + wire n2692_o; + wire [5:0] n2693_o; + wire [5:0] n2694_o; + wire [3:0] n2695_o; + wire [6:0] n2696_o; + wire [3:0] n2697_o; + wire [7:0] n2698_o; + wire [7:0] n2704_o; + wire n2706_o; + wire [7:0] n2707_o; + wire n2709_o; + wire [7:0] n2710_o; + wire n2712_o; + wire n2714_o; + wire n2716_o; + wire n2718_o; + wire n2719_o; + wire n2721_o; + wire n2723_o; + wire [6:0] n2724_o; + wire [7:0] n2726_o; + wire n2727_o; + wire n2729_o; + wire [6:0] n2730_o; + wire n2731_o; + wire [7:0] n2732_o; + wire n2733_o; + wire n2735_o; + wire [6:0] n2736_o; + wire [7:0] n2738_o; + wire n2739_o; + wire n2741_o; + wire n2742_o; + wire [6:0] n2743_o; + wire [7:0] n2744_o; + wire n2745_o; + wire n2747_o; + wire n2748_o; + wire n2750_o; + wire [7:0] n2752_o; + wire n2754_o; + wire [7:0] n2756_o; + wire n2758_o; + wire [13:0] n2759_o; + wire n2760_o; + reg n2761_o; + wire n2762_o; + reg n2763_o; + wire n2765_o; + reg [7:0] n2767_o; + wire n2769_o; + wire n2771_o; + wire n2773_o; + wire n2774_o; + wire n2776_o; + wire n2777_o; + wire [7:0] n2778_o; + wire n2780_o; + wire n2783_o; + wire n2785_o; + wire n2786_o; + wire n2788_o; + wire n2791_o; + wire [3:0] n2792_o; + wire n2793_o; + reg n2794_o; + reg n2795_o; + wire [3:0] n2796_o; + wire [7:0] n2798_o; + assign p_out = n2798_o; + assign q = n2767_o; + /* T65_ALU.vhd:79:21 */ + assign adc_z = n2558_o; // (signal) + /* T65_ALU.vhd:80:21 */ + assign adc_c = n2607_o; // (signal) + /* T65_ALU.vhd:81:21 */ + assign adc_v = n2591_o; // (signal) + /* T65_ALU.vhd:82:21 */ + assign adc_n = n2583_o; // (signal) + /* T65_ALU.vhd:83:21 */ + assign adc_q = n2612_o; // (signal) + /* T65_ALU.vhd:84:21 */ + assign sbc_z = n2652_o; // (signal) + /* T65_ALU.vhd:85:21 */ + assign sbc_c = n2654_o; // (signal) + /* T65_ALU.vhd:86:21 */ + assign sbc_v = n2661_o; // (signal) + /* T65_ALU.vhd:87:21 */ + assign sbc_n = n2662_o; // (signal) + /* T65_ALU.vhd:88:21 */ + assign sbc_q = n2698_o; // (signal) + /* T65_ALU.vhd:97:43 */ + assign n2531_o = busa[3:0]; + /* T65_ALU.vhd:97:62 */ + assign n2532_o = p_in[0]; + /* T65_ALU.vhd:97:56 */ + assign n2533_o = {n2531_o, n2532_o}; + /* T65_ALU.vhd:97:23 */ + assign n2534_o = {2'b0, n2533_o}; // uext + /* T65_ALU.vhd:97:98 */ + assign n2535_o = busb[3:0]; + /* T65_ALU.vhd:97:111 */ + assign n2537_o = {n2535_o, 1'b1}; + /* T65_ALU.vhd:97:78 */ + assign n2538_o = {2'b0, n2537_o}; // uext + /* T65_ALU.vhd:97:76 */ + assign n2539_o = n2534_o + n2538_o; + /* T65_ALU.vhd:98:43 */ + assign n2540_o = busa[7:4]; + /* T65_ALU.vhd:98:60 */ + assign n2541_o = n2539_o[5]; + /* T65_ALU.vhd:98:56 */ + assign n2542_o = {n2540_o, n2541_o}; + /* T65_ALU.vhd:98:23 */ + assign n2543_o = {2'b0, n2542_o}; // uext + /* T65_ALU.vhd:98:91 */ + assign n2544_o = busb[7:4]; + /* T65_ALU.vhd:98:104 */ + assign n2546_o = {n2544_o, 1'b1}; + /* T65_ALU.vhd:98:71 */ + assign n2547_o = {2'b0, n2546_o}; // uext + /* T65_ALU.vhd:98:69 */ + assign n2548_o = n2543_o + n2547_o; + /* T65_ALU.vhd:105:22 */ + assign n2549_o = n2539_o[4:1]; + /* T65_ALU.vhd:105:35 */ + assign n2551_o = n2549_o == 4'b0000; + /* T65_ALU.vhd:105:45 */ + assign n2552_o = n2548_o[4:1]; + /* T65_ALU.vhd:105:58 */ + assign n2554_o = n2552_o == 4'b0000; + /* T65_ALU.vhd:105:39 */ + assign n2555_o = n2551_o & n2554_o; + /* T65_ALU.vhd:105:17 */ + assign n2558_o = n2555_o ? 1'b1 : 1'b0; + /* T65_ALU.vhd:111:22 */ + assign n2559_o = n2539_o[5:1]; + /* T65_ALU.vhd:111:35 */ + assign n2561_o = $unsigned(n2559_o) > $unsigned(5'b01001); + /* T65_ALU.vhd:111:47 */ + assign n2562_o = p_in[3]; + /* T65_ALU.vhd:111:39 */ + assign n2563_o = n2561_o & n2562_o; + /* T65_ALU.vhd:112:45 */ + assign n2564_o = n2539_o[6:1]; + /* T65_ALU.vhd:112:58 */ + assign n2566_o = n2564_o + 6'b000110; + assign n2567_o = n2539_o[6:1]; + /* T65_ALU.vhd:111:17 */ + assign n2568_o = n2563_o ? n2566_o : n2567_o; + assign n2569_o = n2539_o[0]; + /* T65_MCode.vhd:404:33 */ + assign n2570_o = {n2568_o, n2569_o}; + /* T65_ALU.vhd:115:24 */ + assign n2571_o = n2570_o[6]; + /* T65_MCode.vhd:403:38 */ + assign n2572_o = {n2568_o, n2569_o}; + /* T65_ALU.vhd:115:33 */ + assign n2573_o = n2572_o[5]; + /* T65_ALU.vhd:115:28 */ + assign n2574_o = n2571_o | n2573_o; + /* T65_ALU.vhd:116:43 */ + assign n2575_o = busa[7:4]; + /* T65_ALU.vhd:116:56 */ + assign n2576_o = {n2575_o, n2574_o}; + /* T65_ALU.vhd:116:23 */ + assign n2577_o = {2'b0, n2576_o}; // uext + /* T65_ALU.vhd:116:87 */ + assign n2578_o = busb[7:4]; + /* T65_ALU.vhd:116:100 */ + assign n2580_o = {n2578_o, 1'b1}; + /* T65_ALU.vhd:116:67 */ + assign n2581_o = {2'b0, n2580_o}; // uext + /* T65_ALU.vhd:116:65 */ + assign n2582_o = n2577_o + n2581_o; + /* T65_ALU.vhd:118:28 */ + assign n2583_o = n2582_o[4]; + /* T65_ALU.vhd:119:29 */ + assign n2584_o = n2582_o[4]; + /* T65_ALU.vhd:119:41 */ + assign n2585_o = busa[7]; + /* T65_ALU.vhd:119:33 */ + assign n2586_o = n2584_o ^ n2585_o; + /* T65_ALU.vhd:119:59 */ + assign n2587_o = busa[7]; + /* T65_ALU.vhd:119:71 */ + assign n2588_o = busb[7]; + /* T65_ALU.vhd:119:63 */ + assign n2589_o = n2587_o ^ n2588_o; + /* T65_ALU.vhd:119:50 */ + assign n2590_o = ~n2589_o; + /* T65_ALU.vhd:119:46 */ + assign n2591_o = n2586_o & n2590_o; + /* T65_ALU.vhd:125:22 */ + assign n2592_o = n2582_o[5:1]; + /* T65_ALU.vhd:125:35 */ + assign n2594_o = $unsigned(n2592_o) > $unsigned(5'b01001); + /* T65_ALU.vhd:125:47 */ + assign n2595_o = p_in[3]; + /* T65_ALU.vhd:125:39 */ + assign n2596_o = n2594_o & n2595_o; + /* T65_ALU.vhd:126:45 */ + assign n2597_o = n2582_o[6:1]; + /* T65_ALU.vhd:126:58 */ + assign n2599_o = n2597_o + 6'b000110; + assign n2600_o = n2582_o[6:1]; + /* T65_ALU.vhd:125:17 */ + assign n2601_o = n2596_o ? n2599_o : n2600_o; + assign n2602_o = n2582_o[0]; + assign n2603_o = {n2601_o, n2602_o}; + /* T65_ALU.vhd:129:28 */ + assign n2604_o = n2603_o[6]; + assign n2605_o = {n2601_o, n2602_o}; + /* T65_ALU.vhd:129:37 */ + assign n2606_o = n2605_o[5]; + /* T65_ALU.vhd:129:32 */ + assign n2607_o = n2604_o | n2606_o; + assign n2608_o = {n2601_o, n2602_o}; + /* T65_ALU.vhd:131:45 */ + assign n2609_o = n2608_o[4:1]; + assign n2610_o = {n2568_o, n2569_o}; + /* T65_ALU.vhd:131:62 */ + assign n2611_o = n2610_o[4:1]; + /* T65_ALU.vhd:131:58 */ + assign n2612_o = {n2609_o, n2611_o}; + /* T65_ALU.vhd:139:26 */ + assign n2621_o = p_in[0]; + /* T65_ALU.vhd:139:44 */ + assign n2622_o = op[0]; + /* T65_ALU.vhd:139:38 */ + assign n2623_o = ~n2622_o; + /* T65_ALU.vhd:139:35 */ + assign n2624_o = n2621_o | n2623_o; + /* T65_ALU.vhd:140:43 */ + assign n2625_o = busa[3:0]; + /* T65_ALU.vhd:140:56 */ + assign n2626_o = {n2625_o, n2624_o}; + /* T65_ALU.vhd:140:23 */ + assign n2627_o = {2'b0, n2626_o}; // uext + /* T65_ALU.vhd:140:87 */ + assign n2628_o = busb[3:0]; + /* T65_ALU.vhd:140:100 */ + assign n2630_o = {n2628_o, 1'b1}; + /* T65_ALU.vhd:140:67 */ + assign n2631_o = {1'b0, n2630_o}; // uext + /* T65_ALU.vhd:140:65 */ + assign n2632_o = {1'b0, n2631_o}; // uext + /* T65_ALU.vhd:140:65 */ + assign n2633_o = n2627_o - n2632_o; + /* T65_ALU.vhd:141:43 */ + assign n2634_o = busa[7:4]; + /* T65_ALU.vhd:141:56 */ + assign n2636_o = {n2634_o, 1'b0}; + /* T65_ALU.vhd:141:23 */ + assign n2637_o = {1'b0, n2636_o}; // uext + /* T65_ALU.vhd:141:89 */ + assign n2638_o = busb[7:4]; + /* T65_ALU.vhd:141:106 */ + assign n2639_o = n2633_o[5]; + /* T65_ALU.vhd:141:102 */ + assign n2640_o = {n2638_o, n2639_o}; + /* T65_ALU.vhd:141:69 */ + assign n2641_o = {1'b0, n2640_o}; // uext + /* T65_ALU.vhd:141:67 */ + assign n2642_o = n2637_o - n2641_o; + /* T65_ALU.vhd:148:22 */ + assign n2643_o = n2633_o[4:1]; + /* T65_ALU.vhd:148:35 */ + assign n2645_o = n2643_o == 4'b0000; + /* T65_ALU.vhd:148:45 */ + assign n2646_o = n2642_o[4:1]; + /* T65_ALU.vhd:148:58 */ + assign n2648_o = n2646_o == 4'b0000; + /* T65_ALU.vhd:148:39 */ + assign n2649_o = n2645_o & n2648_o; + /* T65_ALU.vhd:148:17 */ + assign n2652_o = n2649_o ? 1'b1 : 1'b0; + /* T65_ALU.vhd:154:32 */ + assign n2653_o = n2642_o[5]; + /* T65_ALU.vhd:154:26 */ + assign n2654_o = ~n2653_o; + /* T65_ALU.vhd:155:29 */ + assign n2655_o = n2642_o[4]; + /* T65_ALU.vhd:155:41 */ + assign n2656_o = busa[7]; + /* T65_ALU.vhd:155:33 */ + assign n2657_o = n2655_o ^ n2656_o; + /* T65_ALU.vhd:155:55 */ + assign n2658_o = busa[7]; + /* T65_ALU.vhd:155:67 */ + assign n2659_o = busb[7]; + /* T65_ALU.vhd:155:59 */ + assign n2660_o = n2658_o ^ n2659_o; + /* T65_ALU.vhd:155:46 */ + assign n2661_o = n2657_o & n2660_o; + /* T65_ALU.vhd:156:28 */ + assign n2662_o = n2642_o[4]; + /* T65_ALU.vhd:158:24 */ + assign n2663_o = p_in[3]; + /* T65_ALU.vhd:159:30 */ + assign n2664_o = n2633_o[5]; + /* T65_ALU.vhd:160:53 */ + assign n2665_o = n2633_o[5:1]; + /* T65_ALU.vhd:160:66 */ + assign n2667_o = n2665_o - 5'b00110; + assign n2668_o = n2633_o[5:1]; + /* T65_ALU.vhd:159:25 */ + assign n2669_o = n2664_o ? n2667_o : n2668_o; + /* T65_ALU.vhd:162:51 */ + assign n2670_o = busa[7:4]; + /* T65_ALU.vhd:162:64 */ + assign n2672_o = {n2670_o, 1'b0}; + /* T65_ALU.vhd:162:31 */ + assign n2673_o = {1'b0, n2672_o}; // uext + /* T65_ALU.vhd:162:97 */ + assign n2674_o = busb[7:4]; + assign n2675_o = n2633_o[0]; + assign n2676_o = n2633_o[6]; + assign n2677_o = {n2676_o, n2669_o, n2675_o}; + /* T65_ALU.vhd:162:114 */ + assign n2678_o = n2677_o[6]; + /* T65_ALU.vhd:162:110 */ + assign n2679_o = {n2674_o, n2678_o}; + /* T65_ALU.vhd:162:77 */ + assign n2680_o = {1'b0, n2679_o}; // uext + /* T65_ALU.vhd:162:75 */ + assign n2681_o = n2673_o - n2680_o; + /* T65_ALU.vhd:163:30 */ + assign n2682_o = n2681_o[5]; + /* T65_ALU.vhd:164:53 */ + assign n2683_o = n2681_o[5:1]; + /* T65_ALU.vhd:164:66 */ + assign n2685_o = n2683_o - 5'b00110; + assign n2686_o = n2681_o[5:1]; + /* T65_ALU.vhd:163:25 */ + assign n2687_o = n2682_o ? n2685_o : n2686_o; + assign n2688_o = n2681_o[0]; + assign n2689_o = n2633_o[5:1]; + /* T65_ALU.vhd:158:17 */ + assign n2690_o = n2663_o ? n2669_o : n2689_o; + assign n2691_o = n2633_o[6]; + assign n2692_o = n2633_o[0]; + assign n2693_o = {n2687_o, n2688_o}; + /* T65_ALU.vhd:158:17 */ + assign n2694_o = n2663_o ? n2693_o : n2642_o; + /* T65_ALU.vhd:168:45 */ + assign n2695_o = n2694_o[4:1]; + assign n2696_o = {n2691_o, n2690_o, n2692_o}; + /* T65_ALU.vhd:168:62 */ + assign n2697_o = n2696_o[4:1]; + /* T65_ALU.vhd:168:58 */ + assign n2698_o = {n2695_o, n2697_o}; + /* T65_ALU.vhd:183:37 */ + assign n2704_o = busa | busb; + /* T65_ALU.vhd:181:17 */ + assign n2706_o = op == 4'b0000; + /* T65_ALU.vhd:186:37 */ + assign n2707_o = busa & busb; + /* T65_ALU.vhd:184:17 */ + assign n2709_o = op == 4'b0001; + /* T65_ALU.vhd:189:37 */ + assign n2710_o = busa ^ busb; + /* T65_ALU.vhd:187:17 */ + assign n2712_o = op == 4'b0010; + /* T65_ALU.vhd:190:17 */ + assign n2714_o = op == 4'b0011; + /* T65_ALU.vhd:195:17 */ + assign n2716_o = op == 4'b0101; + /* T65_ALU.vhd:195:29 */ + assign n2718_o = op == 4'b1101; + /* T65_ALU.vhd:195:29 */ + assign n2719_o = n2716_o | n2718_o; + /* T65_ALU.vhd:197:17 */ + assign n2721_o = op == 4'b0110; + /* T65_ALU.vhd:200:17 */ + assign n2723_o = op == 4'b0111; + /* T65_ALU.vhd:207:36 */ + assign n2724_o = busa[6:0]; + /* T65_ALU.vhd:207:49 */ + assign n2726_o = {n2724_o, 1'b0}; + /* T65_ALU.vhd:208:46 */ + assign n2727_o = busa[7]; + /* T65_ALU.vhd:205:17 */ + assign n2729_o = op == 4'b1000; + /* T65_ALU.vhd:211:36 */ + assign n2730_o = busa[6:0]; + /* T65_ALU.vhd:211:55 */ + assign n2731_o = p_in[0]; + /* T65_ALU.vhd:211:49 */ + assign n2732_o = {n2730_o, n2731_o}; + /* T65_ALU.vhd:212:46 */ + assign n2733_o = busa[7]; + /* T65_ALU.vhd:209:17 */ + assign n2735_o = op == 4'b1001; + /* T65_ALU.vhd:215:42 */ + assign n2736_o = busa[7:1]; + /* T65_ALU.vhd:215:36 */ + assign n2738_o = {1'b0, n2736_o}; + /* T65_ALU.vhd:216:46 */ + assign n2739_o = busa[0]; + /* T65_ALU.vhd:213:17 */ + assign n2741_o = op == 4'b1010; + /* T65_ALU.vhd:219:36 */ + assign n2742_o = p_in[0]; + /* T65_ALU.vhd:219:51 */ + assign n2743_o = busa[7:1]; + /* T65_ALU.vhd:219:45 */ + assign n2744_o = {n2742_o, n2743_o}; + /* T65_ALU.vhd:220:46 */ + assign n2745_o = busa[0]; + /* T65_ALU.vhd:217:17 */ + assign n2747_o = op == 4'b1011; + /* T65_ALU.vhd:223:46 */ + assign n2748_o = busb[6]; + /* T65_ALU.vhd:221:17 */ + assign n2750_o = op == 4'b1100; + /* T65_ALU.vhd:226:64 */ + assign n2752_o = busa - 8'b00000001; + /* T65_ALU.vhd:224:17 */ + assign n2754_o = op == 4'b1110; + /* T65_ALU.vhd:229:64 */ + assign n2756_o = busa + 8'b00000001; + /* T65_ALU.vhd:227:17 */ + assign n2758_o = op == 4'b1111; + assign n2759_o = {n2758_o, n2754_o, n2750_o, n2747_o, n2741_o, n2735_o, n2729_o, n2723_o, n2721_o, n2719_o, n2714_o, n2712_o, n2709_o, n2706_o}; + assign n2760_o = p_in[0]; + /* T65_ALU.vhd:180:17 */ + always @* + case (n2759_o) + 14'b10000000000000: n2761_o = n2760_o; + 14'b01000000000000: n2761_o = n2760_o; + 14'b00100000000000: n2761_o = n2760_o; + 14'b00010000000000: n2761_o = n2745_o; + 14'b00001000000000: n2761_o = n2739_o; + 14'b00000100000000: n2761_o = n2733_o; + 14'b00000010000000: n2761_o = n2727_o; + 14'b00000001000000: n2761_o = sbc_c; + 14'b00000000100000: n2761_o = sbc_c; + 14'b00000000010000: n2761_o = n2760_o; + 14'b00000000001000: n2761_o = adc_c; + 14'b00000000000100: n2761_o = n2760_o; + 14'b00000000000010: n2761_o = n2760_o; + 14'b00000000000001: n2761_o = n2760_o; + default: n2761_o = n2760_o; + endcase + assign n2762_o = p_in[6]; + /* T65_ALU.vhd:180:17 */ + always @* + case (n2759_o) + 14'b10000000000000: n2763_o = n2762_o; + 14'b01000000000000: n2763_o = n2762_o; + 14'b00100000000000: n2763_o = n2748_o; + 14'b00010000000000: n2763_o = n2762_o; + 14'b00001000000000: n2763_o = n2762_o; + 14'b00000100000000: n2763_o = n2762_o; + 14'b00000010000000: n2763_o = n2762_o; + 14'b00000001000000: n2763_o = sbc_v; + 14'b00000000100000: n2763_o = n2762_o; + 14'b00000000010000: n2763_o = n2762_o; + 14'b00000000001000: n2763_o = adc_v; + 14'b00000000000100: n2763_o = n2762_o; + 14'b00000000000010: n2763_o = n2762_o; + 14'b00000000000001: n2763_o = n2762_o; + default: n2763_o = n2762_o; + endcase + assign n2765_o = p_in[7]; + /* T65_ALU.vhd:180:17 */ + always @* + case (n2759_o) + 14'b10000000000000: n2767_o = n2756_o; + 14'b01000000000000: n2767_o = n2752_o; + 14'b00100000000000: n2767_o = busa; + 14'b00010000000000: n2767_o = n2744_o; + 14'b00001000000000: n2767_o = n2738_o; + 14'b00000100000000: n2767_o = n2732_o; + 14'b00000010000000: n2767_o = n2726_o; + 14'b00000001000000: n2767_o = sbc_q; + 14'b00000000100000: n2767_o = busa; + 14'b00000000010000: n2767_o = busa; + 14'b00000000001000: n2767_o = adc_q; + 14'b00000000000100: n2767_o = n2710_o; + 14'b00000000000010: n2767_o = n2707_o; + 14'b00000000000001: n2767_o = n2704_o; + default: n2767_o = busa; + endcase + /* T65_ALU.vhd:234:17 */ + assign n2769_o = op == 4'b0011; + /* T65_ALU.vhd:237:17 */ + assign n2771_o = op == 4'b0110; + /* T65_ALU.vhd:237:29 */ + assign n2773_o = op == 4'b0111; + /* T65_ALU.vhd:237:29 */ + assign n2774_o = n2771_o | n2773_o; + /* T65_ALU.vhd:240:17 */ + assign n2776_o = op == 4'b0100; + /* T65_ALU.vhd:242:46 */ + assign n2777_o = busb[7]; + /* T65_ALU.vhd:243:34 */ + assign n2778_o = busa & busb; + /* T65_ALU.vhd:243:44 */ + assign n2780_o = n2778_o == 8'b00000000; + /* T65_ALU.vhd:243:25 */ + assign n2783_o = n2780_o ? 1'b1 : 1'b0; + /* T65_ALU.vhd:241:17 */ + assign n2785_o = op == 4'b1100; + /* T65_ALU.vhd:249:45 */ + assign n2786_o = n2767_o[7]; + /* T65_ALU.vhd:250:32 */ + assign n2788_o = n2767_o == 8'b00000000; + /* T65_ALU.vhd:250:25 */ + assign n2791_o = n2788_o ? 1'b1 : 1'b0; + assign n2792_o = {n2785_o, n2776_o, n2774_o, n2769_o}; + assign n2793_o = p_in[1]; + /* T65_ALU.vhd:233:17 */ + always @* + case (n2792_o) + 4'b1000: n2794_o = n2783_o; + 4'b0100: n2794_o = n2793_o; + 4'b0010: n2794_o = sbc_z; + 4'b0001: n2794_o = adc_z; + default: n2794_o = n2791_o; + endcase + /* T65_ALU.vhd:233:17 */ + always @* + case (n2792_o) + 4'b1000: n2795_o = n2777_o; + 4'b0100: n2795_o = n2765_o; + 4'b0010: n2795_o = sbc_n; + 4'b0001: n2795_o = adc_n; + default: n2795_o = n2786_o; + endcase + assign n2796_o = p_in[5:2]; + assign n2798_o = {n2795_o, n2763_o, n2796_o, n2794_o, n2761_o}; +endmodule + +module t65_mcode + (input [1:0] mode, + input [7:0] ir, + input [2:0] mcycle, + input [7:0] p, + output [2:0] lcycle, + output [3:0] alu_op, + output [2:0] set_busa_to, + output [1:0] set_addr_to, + output [2:0] write_data, + output [1:0] jump, + output [1:0] baadd, + output breakatna, + output adadd, + output addy, + output pcadd, + output inc_s, + output dec_s, + output lda, + output ldp, + output ldx, + output ldy, + output lds, + output lddi, + output ldalu, + output ldad, + output ldbal, + output ldbah, + output savep, + output write); + wire branch; + wire [2:0] n909_o; + wire n910_o; + wire n911_o; + wire n913_o; + wire n914_o; + wire n916_o; + wire n917_o; + wire n918_o; + wire n920_o; + wire n921_o; + wire n923_o; + wire n924_o; + wire n925_o; + wire n927_o; + wire n928_o; + wire n930_o; + wire n931_o; + wire n932_o; + wire n934_o; + wire n935_o; + wire [6:0] n936_o; + reg n937_o; + wire [2:0] n940_o; + wire [1:0] n941_o; + wire n943_o; + wire n945_o; + wire [1:0] n946_o; + reg [2:0] n950_o; + reg [2:0] n954_o; + wire n956_o; + wire [1:0] n957_o; + wire n958_o; + wire n960_o; + wire n961_o; + wire n963_o; + wire n964_o; + wire n967_o; + wire n969_o; + wire n971_o; + wire [1:0] n972_o; + reg n975_o; + reg n978_o; + reg n980_o; + wire n982_o; + wire [1:0] n983_o; + wire n984_o; + wire n985_o; + wire n988_o; + wire n990_o; + reg [2:0] n993_o; + reg n995_o; + wire n997_o; + wire [1:0] n998_o; + wire n999_o; + wire n1000_o; + wire n1003_o; + wire n1005_o; + reg [2:0] n1008_o; + reg n1010_o; + wire n1012_o; + wire [3:0] n1013_o; + reg [2:0] n1016_o; + reg [2:0] n1019_o; + reg n1022_o; + reg n1025_o; + reg n1028_o; + wire [1:0] n1030_o; + wire n1032_o; + wire [1:0] n1033_o; + wire n1035_o; + wire n1036_o; + wire [2:0] n1038_o; + wire [4:0] n1039_o; + wire [30:0] n1040_o; + wire n1042_o; + wire n1044_o; + wire n1046_o; + wire n1048_o; + wire n1050_o; + wire n1052_o; + wire [5:0] n1053_o; + reg [1:0] n1060_o; + reg [2:0] n1064_o; + reg [1:0] n1067_o; + reg n1072_o; + reg n1075_o; + reg n1080_o; + wire n1082_o; + wire [30:0] n1083_o; + wire n1085_o; + wire n1087_o; + wire n1089_o; + wire n1091_o; + wire n1093_o; + wire [4:0] n1094_o; + reg [1:0] n1099_o; + reg [2:0] n1102_o; + reg [1:0] n1106_o; + reg n1110_o; + reg n1113_o; + reg n1117_o; + wire n1119_o; + wire [30:0] n1120_o; + wire n1122_o; + wire n1124_o; + wire n1126_o; + wire n1128_o; + wire n1130_o; + wire [4:0] n1131_o; + reg [2:0] n1133_o; + reg [1:0] n1139_o; + reg [1:0] n1142_o; + reg n1147_o; + reg n1150_o; + reg n1153_o; + wire n1155_o; + wire [30:0] n1156_o; + wire n1158_o; + wire n1160_o; + wire n1162_o; + wire n1164_o; + wire n1166_o; + wire [4:0] n1167_o; + reg [1:0] n1172_o; + reg [1:0] n1176_o; + reg n1180_o; + reg n1183_o; + wire n1185_o; + wire n1187_o; + wire n1188_o; + wire n1189_o; + wire [2:0] n1192_o; + wire [30:0] n1194_o; + wire [3:0] n1195_o; + wire n1197_o; + wire n1199_o; + wire n1201_o; + wire n1203_o; + wire [3:0] n1204_o; + reg [2:0] n1209_o; + wire n1211_o; + wire n1213_o; + wire [1:0] n1214_o; + reg [1:0] n1217_o; + reg [2:0] n1218_o; + reg n1221_o; + reg n1224_o; + wire n1226_o; + wire n1228_o; + wire n1229_o; + wire n1231_o; + wire n1232_o; + wire n1234_o; + wire n1235_o; + wire n1237_o; + wire n1238_o; + wire n1239_o; + wire [2:0] n1242_o; + wire [3:0] n1244_o; + wire n1246_o; + wire n1248_o; + wire n1250_o; + wire n1252_o; + wire n1254_o; + wire n1256_o; + wire n1258_o; + wire n1260_o; + wire [3:0] n1261_o; + reg n1263_o; + reg n1266_o; + reg n1267_o; + reg n1268_o; + wire [30:0] n1269_o; + wire n1271_o; + wire n1273_o; + wire n1275_o; + wire n1277_o; + wire [3:0] n1278_o; + reg [2:0] n1280_o; + reg [1:0] n1284_o; + reg n1287_o; + reg n1290_o; + wire n1292_o; + wire n1294_o; + wire n1295_o; + wire n1297_o; + wire n1298_o; + wire n1300_o; + wire n1301_o; + wire [30:0] n1302_o; + wire n1304_o; + wire n1306_o; + wire [1:0] n1307_o; + reg [1:0] n1310_o; + wire n1312_o; + wire n1314_o; + wire n1315_o; + wire n1317_o; + wire n1318_o; + wire [30:0] n1319_o; + wire n1321_o; + wire n1323_o; + wire [1:0] n1324_o; + reg [2:0] n1326_o; + wire n1328_o; + wire [30:0] n1329_o; + wire n1331_o; + wire n1333_o; + wire [1:0] n1334_o; + reg [2:0] n1336_o; + wire n1338_o; + wire n1340_o; + wire n1342_o; + wire [30:0] n1343_o; + wire n1345_o; + wire n1347_o; + wire [1:0] n1348_o; + reg [2:0] n1350_o; + wire n1352_o; + wire n1354_o; + wire n1355_o; + wire n1363_o; + wire n1365_o; + wire n1366_o; + wire n1368_o; + wire n1369_o; + wire n1371_o; + wire n1372_o; + wire n1380_o; + wire n1382_o; + wire n1383_o; + wire [30:0] n1384_o; + wire n1386_o; + wire n1388_o; + wire [1:0] n1389_o; + reg [2:0] n1391_o; + wire n1393_o; + wire n1395_o; + wire n1396_o; + wire [30:0] n1397_o; + wire n1399_o; + wire n1401_o; + wire [1:0] n1402_o; + reg n1405_o; + wire n1407_o; + wire [30:0] n1408_o; + wire n1410_o; + wire n1412_o; + wire [1:0] n1413_o; + reg [2:0] n1415_o; + wire n1417_o; + wire [14:0] n1421_o; + reg [2:0] n1427_o; + reg [2:0] n1429_o; + reg [1:0] n1431_o; + reg [2:0] n1432_o; + reg [1:0] n1434_o; + reg n1436_o; + reg n1438_o; + reg n1441_o; + reg n1443_o; + reg n1446_o; + reg n1448_o; + reg n1450_o; + reg n1452_o; + reg n1454_o; + reg n1456_o; + wire n1458_o; + wire n1460_o; + wire n1461_o; + wire n1463_o; + wire n1464_o; + wire n1466_o; + wire n1467_o; + wire n1469_o; + wire n1470_o; + wire [1:0] n1471_o; + wire n1473_o; + wire n1475_o; + wire [30:0] n1476_o; + wire n1478_o; + wire n1480_o; + wire n1482_o; + wire n1484_o; + wire [2:0] n1485_o; + wire n1487_o; + wire n1490_o; + wire n1492_o; + wire n1494_o; + wire [5:0] n1495_o; + reg [1:0] n1501_o; + reg [1:0] n1504_o; + reg [1:0] n1507_o; + reg n1510_o; + reg n1513_o; + reg n1516_o; + reg n1519_o; + reg n1521_o; + wire n1523_o; + wire n1525_o; + wire n1526_o; + wire [30:0] n1527_o; + wire n1529_o; + wire n1531_o; + wire [1:0] n1532_o; + reg [1:0] n1535_o; + wire n1537_o; + wire n1539_o; + wire n1540_o; + wire [30:0] n1541_o; + wire n1543_o; + wire n1545_o; + wire [1:0] n1548_o; + wire n1550_o; + wire [1:0] n1551_o; + reg [1:0] n1553_o; + wire n1555_o; + wire n1557_o; + wire n1558_o; + wire [30:0] n1559_o; + wire [2:0] n1560_o; + wire n1562_o; + wire n1565_o; + wire n1567_o; + wire [2:0] n1568_o; + wire n1570_o; + wire n1573_o; + wire n1575_o; + wire n1577_o; + wire [2:0] n1578_o; + reg [1:0] n1581_o; + reg [1:0] n1584_o; + reg n1587_o; + reg n1589_o; + reg n1591_o; + wire n1593_o; + wire [1:0] n1594_o; + wire n1596_o; + wire [1:0] n1597_o; + wire n1599_o; + wire n1600_o; + wire [30:0] n1601_o; + wire n1603_o; + wire n1605_o; + wire n1607_o; + wire n1609_o; + wire [3:0] n1610_o; + reg [1:0] n1615_o; + reg [1:0] n1618_o; + reg n1621_o; + reg n1624_o; + reg n1627_o; + reg n1630_o; + reg n1634_o; + wire [1:0] n1635_o; + wire n1637_o; + wire n1639_o; + wire [30:0] n1640_o; + wire n1642_o; + wire [2:0] n1643_o; + wire n1645_o; + wire n1648_o; + wire n1650_o; + wire n1652_o; + wire [2:0] n1653_o; + reg [1:0] n1656_o; + reg [1:0] n1659_o; + reg n1662_o; + reg n1664_o; + wire [2:0] n1667_o; + wire [1:0] n1668_o; + wire [1:0] n1669_o; + wire n1670_o; + wire n1672_o; + wire n1674_o; + wire n1675_o; + wire n1677_o; + wire n1678_o; + wire n1680_o; + wire n1682_o; + wire n1683_o; + wire n1685_o; + wire n1686_o; + wire [1:0] n1687_o; + wire n1689_o; + wire [4:0] n1690_o; + wire n1692_o; + wire n1693_o; + wire n1694_o; + wire n1695_o; + wire [30:0] n1696_o; + wire n1698_o; + wire n1700_o; + wire [1:0] n1701_o; + reg [1:0] n1705_o; + reg n1708_o; + wire [30:0] n1709_o; + wire n1711_o; + wire n1713_o; + wire [1:0] n1716_o; + wire n1718_o; + wire [1:0] n1721_o; + wire n1723_o; + wire n1725_o; + wire [1:0] n1728_o; + wire [1:0] n1731_o; + wire [1:0] n1734_o; + wire n1736_o; + wire n1738_o; + wire [3:0] n1739_o; + reg [1:0] n1741_o; + reg [1:0] n1745_o; + reg [1:0] n1747_o; + reg n1751_o; + reg n1754_o; + reg n1757_o; + wire [2:0] n1760_o; + wire [1:0] n1762_o; + wire [1:0] n1763_o; + wire [1:0] n1765_o; + wire n1766_o; + wire n1768_o; + wire n1770_o; + wire [30:0] n1771_o; + wire [2:0] n1772_o; + wire n1774_o; + wire n1777_o; + wire n1779_o; + wire n1781_o; + wire [2:0] n1782_o; + wire n1784_o; + wire n1787_o; + wire n1789_o; + wire n1791_o; + wire [3:0] n1792_o; + reg [1:0] n1795_o; + reg [1:0] n1799_o; + reg n1802_o; + reg n1805_o; + reg n1807_o; + reg n1809_o; + wire [2:0] n1811_o; + wire [1:0] n1812_o; + wire [1:0] n1813_o; + wire [1:0] n1815_o; + wire n1817_o; + wire n1818_o; + wire n1819_o; + wire n1821_o; + wire n1823_o; + wire n1825_o; + wire [1:0] n1826_o; + wire n1828_o; + wire [1:0] n1829_o; + wire n1831_o; + wire n1832_o; + wire [30:0] n1833_o; + wire n1835_o; + wire n1837_o; + wire n1839_o; + wire n1841_o; + wire n1843_o; + wire [4:0] n1844_o; + reg [1:0] n1849_o; + reg [1:0] n1853_o; + reg n1856_o; + reg n1859_o; + reg n1862_o; + reg n1865_o; + reg n1869_o; + reg n1873_o; + wire [1:0] n1874_o; + wire n1876_o; + wire n1878_o; + wire [30:0] n1879_o; + wire n1881_o; + wire n1883_o; + wire [2:0] n1884_o; + wire n1886_o; + wire n1889_o; + wire n1891_o; + wire n1893_o; + wire [3:0] n1894_o; + reg [1:0] n1897_o; + reg [1:0] n1901_o; + reg n1904_o; + reg n1907_o; + reg n1909_o; + wire [2:0] n1912_o; + wire [1:0] n1913_o; + wire [1:0] n1914_o; + wire n1915_o; + wire n1917_o; + wire n1919_o; + wire n1920_o; + wire n1921_o; + wire n1923_o; + wire n1924_o; + wire n1926_o; + wire n1928_o; + wire n1929_o; + wire n1931_o; + wire n1932_o; + wire [2:0] n1935_o; + wire [30:0] n1936_o; + wire n1938_o; + wire n1940_o; + wire n1942_o; + wire [2:0] n1943_o; + reg [1:0] n1947_o; + reg n1950_o; + reg n1953_o; + wire n1955_o; + wire [1:0] n1956_o; + wire n1958_o; + wire n1960_o; + wire [30:0] n1961_o; + wire n1963_o; + wire n1965_o; + wire n1967_o; + wire n1969_o; + wire [2:0] n1970_o; + wire n1972_o; + wire n1975_o; + wire n1978_o; + wire n1980_o; + wire n1982_o; + wire [5:0] n1983_o; + reg [2:0] n1985_o; + reg [1:0] n1991_o; + reg [1:0] n1994_o; + reg [1:0] n1999_o; + reg n2001_o; + reg n2004_o; + reg n2007_o; + reg n2010_o; + reg n2012_o; + wire n2014_o; + wire n2016_o; + wire n2017_o; + wire [1:0] n2018_o; + wire n2020_o; + wire [1:0] n2021_o; + wire n2023_o; + wire n2024_o; + wire [30:0] n2025_o; + wire n2027_o; + wire n2029_o; + wire n2031_o; + wire n2033_o; + wire n2035_o; + wire [4:0] n2036_o; + reg [1:0] n2042_o; + reg [1:0] n2045_o; + reg n2048_o; + reg n2051_o; + reg n2054_o; + reg n2057_o; + reg n2060_o; + reg n2064_o; + wire [1:0] n2065_o; + wire n2067_o; + wire n2069_o; + wire [30:0] n2070_o; + wire n2072_o; + wire n2074_o; + wire [3:0] n2075_o; + wire n2077_o; + wire n2080_o; + wire [2:0] n2081_o; + wire n2083_o; + wire n2086_o; + wire n2088_o; + wire n2090_o; + wire [3:0] n2091_o; + reg [1:0] n2095_o; + reg [1:0] n2098_o; + reg n2101_o; + reg n2103_o; + reg n2106_o; + reg n2108_o; + wire [2:0] n2111_o; + wire [1:0] n2112_o; + wire [1:0] n2113_o; + wire n2114_o; + wire n2116_o; + wire n2117_o; + wire n2119_o; + wire n2121_o; + wire n2122_o; + wire n2124_o; + wire n2125_o; + wire n2127_o; + wire n2129_o; + wire n2130_o; + wire n2132_o; + wire n2133_o; + wire n2135_o; + wire n2136_o; + wire [1:0] n2137_o; + wire n2139_o; + wire n2141_o; + wire [30:0] n2142_o; + wire n2144_o; + wire n2146_o; + wire n2148_o; + wire [2:0] n2149_o; + wire n2151_o; + wire n2154_o; + wire n2157_o; + wire n2159_o; + wire n2161_o; + wire [4:0] n2162_o; + reg [2:0] n2164_o; + reg [1:0] n2168_o; + reg [1:0] n2172_o; + reg [1:0] n2176_o; + reg n2178_o; + reg n2181_o; + reg n2184_o; + reg n2186_o; + wire n2188_o; + wire n2190_o; + wire n2191_o; + wire [1:0] n2192_o; + wire n2194_o; + wire [1:0] n2195_o; + wire n2197_o; + wire n2198_o; + wire [30:0] n2199_o; + wire n2201_o; + wire n2203_o; + wire n2205_o; + wire n2207_o; + wire n2209_o; + wire n2211_o; + wire [5:0] n2212_o; + reg [2:0] n2214_o; + reg [1:0] n2220_o; + reg [1:0] n2224_o; + reg [1:0] n2228_o; + reg n2231_o; + reg n2234_o; + reg n2237_o; + reg n2240_o; + reg n2243_o; + reg n2247_o; + wire [1:0] n2248_o; + wire n2250_o; + wire n2252_o; + wire [30:0] n2253_o; + wire n2255_o; + wire n2257_o; + wire n2259_o; + wire [2:0] n2262_o; + wire n2264_o; + wire [2:0] n2265_o; + wire n2267_o; + wire n2270_o; + wire n2273_o; + wire n2275_o; + wire n2277_o; + wire [4:0] n2278_o; + reg [2:0] n2279_o; + reg [1:0] n2283_o; + reg [1:0] n2287_o; + reg [1:0] n2291_o; + reg n2293_o; + reg n2296_o; + reg n2299_o; + reg n2301_o; + wire [2:0] n2304_o; + wire [2:0] n2305_o; + wire [1:0] n2306_o; + wire [1:0] n2307_o; + wire [1:0] n2308_o; + wire n2310_o; + wire n2311_o; + wire n2313_o; + wire n2315_o; + wire n2316_o; + wire n2317_o; + wire n2319_o; + wire n2320_o; + wire n2322_o; + wire n2324_o; + wire n2325_o; + wire n2327_o; + wire n2328_o; + wire n2330_o; + wire n2331_o; + wire [12:0] n2332_o; + reg [2:0] n2338_o; + reg [2:0] n2340_o; + reg [1:0] n2342_o; + reg [2:0] n2344_o; + reg [1:0] n2346_o; + reg [1:0] n2349_o; + reg n2352_o; + reg n2355_o; + reg n2358_o; + reg n2361_o; + reg n2364_o; + reg n2367_o; + reg n2370_o; + reg n2372_o; + reg n2375_o; + reg n2376_o; + reg n2378_o; + reg n2381_o; + reg n2384_o; + reg n2387_o; + reg n2390_o; + reg n2393_o; + reg n2396_o; + reg n2399_o; + wire [1:0] n2404_o; + wire [2:0] n2405_o; + wire [2:0] n2406_o; + wire n2408_o; + wire n2410_o; + wire n2411_o; + wire n2413_o; + wire n2415_o; + wire [2:0] n2416_o; + reg [3:0] n2421_o; + wire n2423_o; + wire n2425_o; + wire n2426_o; + wire n2428_o; + wire n2429_o; + wire [2:0] n2430_o; + wire n2432_o; + wire n2434_o; + wire n2435_o; + wire n2437_o; + wire [1:0] n2438_o; + reg [3:0] n2442_o; + wire n2444_o; + wire [2:0] n2445_o; + wire n2447_o; + reg [3:0] n2450_o; + wire n2452_o; + wire [2:0] n2453_o; + wire n2455_o; + reg [3:0] n2458_o; + wire [2:0] n2459_o; + reg [3:0] n2460_o; + wire n2462_o; + wire [2:0] n2464_o; + wire n2466_o; + wire [2:0] n2468_o; + wire [2:0] n2469_o; + wire [2:0] n2470_o; + wire n2472_o; + wire [3:0] n2474_o; + wire [3:0] n2475_o; + wire n2477_o; + wire [2:0] n2478_o; + wire n2480_o; + wire [3:0] n2482_o; + wire [3:0] n2483_o; + wire n2485_o; + wire [2:0] n2486_o; + wire n2488_o; + wire [3:0] n2491_o; + wire n2493_o; + wire [2:0] n2494_o; + wire [3:0] n2495_o; + reg [3:0] n2496_o; + wire n2498_o; + wire [2:0] n2499_o; + wire n2501_o; + wire n2503_o; + wire [2:0] n2505_o; + wire [2:0] n2507_o; + wire [3:0] n2508_o; + wire [3:0] n2509_o; + wire [3:0] n2510_o; + reg [3:0] n2512_o; + wire [2:0] n2513_o; + wire [2:0] n2514_o; + wire [2:0] n2515_o; + wire [2:0] n2516_o; + reg [2:0] n2517_o; + wire n2518_o; + wire n2519_o; + wire n2520_o; + reg n2521_o; + wire [3:0] n2523_o; + assign lcycle = n2338_o; + assign alu_op = n2523_o; + assign set_busa_to = n2340_o; + assign set_addr_to = n2342_o; + assign write_data = n2344_o; + assign jump = n2346_o; + assign baadd = n2349_o; + assign breakatna = n2352_o; + assign adadd = n2355_o; + assign addy = n2358_o; + assign pcadd = n2361_o; + assign inc_s = n2364_o; + assign dec_s = n2367_o; + assign lda = n2370_o; + assign ldp = n2372_o; + assign ldx = n2375_o; + assign ldy = n2376_o; + assign lds = n2378_o; + assign lddi = n2381_o; + assign ldalu = n2384_o; + assign ldad = n2387_o; + assign ldbal = n2390_o; + assign ldbah = n2393_o; + assign savep = n2396_o; + assign write = n2399_o; + /* T65_MCode.vhd:106:16 */ + assign branch = n937_o; // (signal) + /* T65_MCode.vhd:110:16 */ + assign n909_o = ir[7:5]; + /* T65_MCode.vhd:111:32 */ + assign n910_o = p[7]; + /* T65_MCode.vhd:111:27 */ + assign n911_o = ~n910_o; + /* T65_MCode.vhd:111:41 */ + assign n913_o = n909_o == 3'b000; + /* T65_MCode.vhd:112:44 */ + assign n914_o = p[7]; + /* T65_MCode.vhd:112:53 */ + assign n916_o = n909_o == 3'b001; + /* T65_MCode.vhd:113:40 */ + assign n917_o = p[6]; + /* T65_MCode.vhd:113:35 */ + assign n918_o = ~n917_o; + /* T65_MCode.vhd:113:49 */ + assign n920_o = n909_o == 3'b010; + /* T65_MCode.vhd:114:44 */ + assign n921_o = p[6]; + /* T65_MCode.vhd:114:53 */ + assign n923_o = n909_o == 3'b011; + /* T65_MCode.vhd:115:40 */ + assign n924_o = p[0]; + /* T65_MCode.vhd:115:35 */ + assign n925_o = ~n924_o; + /* T65_MCode.vhd:115:49 */ + assign n927_o = n909_o == 3'b100; + /* T65_MCode.vhd:116:44 */ + assign n928_o = p[0]; + /* T65_MCode.vhd:116:53 */ + assign n930_o = n909_o == 3'b101; + /* T65_MCode.vhd:117:40 */ + assign n931_o = p[1]; + /* T65_MCode.vhd:117:35 */ + assign n932_o = ~n931_o; + /* T65_MCode.vhd:117:49 */ + assign n934_o = n909_o == 3'b110; + /* T65_MCode.vhd:118:44 */ + assign n935_o = p[1]; + /* T65.vhd:93:17 */ + assign n936_o = {n934_o, n930_o, n927_o, n923_o, n920_o, n916_o, n913_o}; + /* T65_MCode.vhd:110:9 */ + always @* + case (n936_o) + 7'b1000000: n937_o = n932_o; + 7'b0100000: n937_o = n928_o; + 7'b0010000: n937_o = n925_o; + 7'b0001000: n937_o = n921_o; + 7'b0000100: n937_o = n918_o; + 7'b0000010: n937_o = n914_o; + 7'b0000001: n937_o = n911_o; + default: n937_o = n935_o; + endcase + /* T65_MCode.vhd:147:24 */ + assign n940_o = ir[7:5]; + /* T65_MCode.vhd:150:32 */ + assign n941_o = ir[1:0]; + /* T65_MCode.vhd:151:25 */ + assign n943_o = n941_o == 2'b00; + /* T65_MCode.vhd:154:25 */ + assign n945_o = n941_o == 2'b10; + /* T65.vhd:83:17 */ + assign n946_o = {n945_o, n943_o}; + /* T65_MCode.vhd:150:25 */ + always @* + case (n946_o) + 2'b10: n950_o = 3'b010; + 2'b01: n950_o = 3'b011; + default: n950_o = 3'b001; + endcase + /* T65_MCode.vhd:150:25 */ + always @* + case (n946_o) + 2'b10: n954_o = 3'b010; + 2'b01: n954_o = 3'b011; + default: n954_o = 3'b001; + endcase + /* T65_MCode.vhd:148:17 */ + assign n956_o = n940_o == 3'b100; + /* T65_MCode.vhd:163:32 */ + assign n957_o = ir[1:0]; + /* T65_MCode.vhd:165:38 */ + assign n958_o = ir[4]; + /* T65_MCode.vhd:165:42 */ + assign n960_o = n958_o != 1'b1; + /* T65_MCode.vhd:165:54 */ + assign n961_o = ir[2]; + /* T65_MCode.vhd:165:58 */ + assign n963_o = n961_o != 1'b0; + /* T65_MCode.vhd:165:49 */ + assign n964_o = n960_o | n963_o; + /* T65_MCode.vhd:165:33 */ + assign n967_o = n964_o ? 1'b1 : 1'b0; + /* T65_MCode.vhd:164:25 */ + assign n969_o = n957_o == 2'b00; + /* T65_MCode.vhd:168:25 */ + assign n971_o = n957_o == 2'b10; + assign n972_o = {n971_o, n969_o}; + /* T65_MCode.vhd:163:25 */ + always @* + case (n972_o) + 2'b10: n975_o = 1'b0; + 2'b01: n975_o = 1'b0; + default: n975_o = 1'b1; + endcase + /* T65_MCode.vhd:163:25 */ + always @* + case (n972_o) + 2'b10: n978_o = 1'b1; + 2'b01: n978_o = 1'b0; + default: n978_o = 1'b0; + endcase + /* T65_MCode.vhd:163:25 */ + always @* + case (n972_o) + 2'b10: n980_o = 1'b0; + 2'b01: n980_o = n967_o; + default: n980_o = 1'b0; + endcase + /* T65_MCode.vhd:161:17 */ + assign n982_o = n940_o == 3'b101; + /* T65_MCode.vhd:177:32 */ + assign n983_o = ir[1:0]; + /* T65_MCode.vhd:179:38 */ + assign n984_o = ir[4]; + /* T65_MCode.vhd:179:42 */ + assign n985_o = ~n984_o; + /* T65_MCode.vhd:179:33 */ + assign n988_o = n985_o ? 1'b1 : 1'b0; + /* T65_MCode.vhd:178:25 */ + assign n990_o = n983_o == 2'b00; + /* T65_MCode.vhd:177:25 */ + always @* + case (n990_o) + 1'b1: n993_o = 3'b011; + default: n993_o = 3'b001; + endcase + /* T65_MCode.vhd:177:25 */ + always @* + case (n990_o) + 1'b1: n995_o = n988_o; + default: n995_o = 1'b0; + endcase + /* T65_MCode.vhd:175:17 */ + assign n997_o = n940_o == 3'b110; + /* T65_MCode.vhd:189:32 */ + assign n998_o = ir[1:0]; + /* T65_MCode.vhd:191:38 */ + assign n999_o = ir[4]; + /* T65_MCode.vhd:191:42 */ + assign n1000_o = ~n999_o; + /* T65_MCode.vhd:191:33 */ + assign n1003_o = n1000_o ? 1'b1 : 1'b0; + /* T65_MCode.vhd:190:25 */ + assign n1005_o = n998_o == 2'b00; + /* T65_MCode.vhd:189:25 */ + always @* + case (n1005_o) + 1'b1: n1008_o = 3'b010; + default: n1008_o = 3'b001; + endcase + /* T65_MCode.vhd:189:25 */ + always @* + case (n1005_o) + 1'b1: n1010_o = n1003_o; + default: n1010_o = 1'b0; + endcase + /* T65_MCode.vhd:187:17 */ + assign n1012_o = n940_o == 3'b111; + assign n1013_o = {n1012_o, n997_o, n982_o, n956_o}; + /* T65_MCode.vhd:147:17 */ + always @* + case (n1013_o) + 4'b1000: n1016_o = n1008_o; + 4'b0100: n1016_o = n993_o; + 4'b0010: n1016_o = 3'b000; + 4'b0001: n1016_o = n950_o; + default: n1016_o = 3'b001; + endcase + /* T65_MCode.vhd:147:17 */ + always @* + case (n1013_o) + 4'b1000: n1019_o = 3'b000; + 4'b0100: n1019_o = 3'b000; + 4'b0010: n1019_o = 3'b000; + 4'b0001: n1019_o = n954_o; + default: n1019_o = 3'b000; + endcase + /* T65_MCode.vhd:147:17 */ + always @* + case (n1013_o) + 4'b1000: n1022_o = 1'b0; + 4'b0100: n1022_o = 1'b0; + 4'b0010: n1022_o = n975_o; + 4'b0001: n1022_o = 1'b0; + default: n1022_o = 1'b0; + endcase + /* T65_MCode.vhd:147:17 */ + always @* + case (n1013_o) + 4'b1000: n1025_o = n1010_o; + 4'b0100: n1025_o = 1'b0; + 4'b0010: n1025_o = n978_o; + 4'b0001: n1025_o = 1'b0; + default: n1025_o = 1'b0; + endcase + /* T65_MCode.vhd:147:17 */ + always @* + case (n1013_o) + 4'b1000: n1028_o = 1'b0; + 4'b0100: n1028_o = n995_o; + 4'b0010: n1028_o = n980_o; + 4'b0001: n1028_o = 1'b0; + default: n1028_o = 1'b0; + endcase + /* T65_MCode.vhd:202:22 */ + assign n1030_o = ir[7:6]; + /* T65_MCode.vhd:202:35 */ + assign n1032_o = n1030_o != 2'b10; + /* T65_MCode.vhd:202:49 */ + assign n1033_o = ir[1:0]; + /* T65_MCode.vhd:202:62 */ + assign n1035_o = n1033_o == 2'b10; + /* T65_MCode.vhd:202:43 */ + assign n1036_o = n1032_o & n1035_o; + /* T65_MCode.vhd:202:17 */ + assign n1038_o = n1036_o ? 3'b000 : n1016_o; + /* T65_MCode.vhd:206:24 */ + assign n1039_o = ir[4:0]; + /* T65_MCode.vhd:214:38 */ + assign n1040_o = {28'b0, mcycle}; // uext + /* T65_MCode.vhd:215:33 */ + assign n1042_o = n1040_o == 31'b0000000000000000000000000000001; + /* T65_MCode.vhd:219:33 */ + assign n1044_o = n1040_o == 31'b0000000000000000000000000000010; + /* T65_MCode.vhd:224:33 */ + assign n1046_o = n1040_o == 31'b0000000000000000000000000000011; + /* T65_MCode.vhd:229:33 */ + assign n1048_o = n1040_o == 31'b0000000000000000000000000000100; + /* T65_MCode.vhd:232:33 */ + assign n1050_o = n1040_o == 31'b0000000000000000000000000000101; + /* T65_MCode.vhd:235:33 */ + assign n1052_o = n1040_o == 31'b0000000000000000000000000000110; + /* T65.vhd:252:17 */ + assign n1053_o = {n1052_o, n1050_o, n1048_o, n1046_o, n1044_o, n1042_o}; + /* T65_MCode.vhd:214:33 */ + always @* + case (n1053_o) + 6'b100000: n1060_o = 2'b00; + 6'b010000: n1060_o = 2'b11; + 6'b001000: n1060_o = 2'b11; + 6'b000100: n1060_o = 2'b01; + 6'b000010: n1060_o = 2'b01; + 6'b000001: n1060_o = 2'b01; + default: n1060_o = 2'b00; + endcase + /* T65_MCode.vhd:214:33 */ + always @* + case (n1053_o) + 6'b100000: n1064_o = n1019_o; + 6'b010000: n1064_o = n1019_o; + 6'b001000: n1064_o = n1019_o; + 6'b000100: n1064_o = 3'b101; + 6'b000010: n1064_o = 3'b110; + 6'b000001: n1064_o = 3'b111; + default: n1064_o = n1019_o; + endcase + /* T65_MCode.vhd:214:33 */ + always @* + case (n1053_o) + 6'b100000: n1067_o = 2'b10; + 6'b010000: n1067_o = 2'b00; + 6'b001000: n1067_o = 2'b00; + 6'b000100: n1067_o = 2'b00; + 6'b000010: n1067_o = 2'b00; + 6'b000001: n1067_o = 2'b00; + default: n1067_o = 2'b00; + endcase + /* T65_MCode.vhd:214:33 */ + always @* + case (n1053_o) + 6'b100000: n1072_o = 1'b0; + 6'b010000: n1072_o = 1'b0; + 6'b001000: n1072_o = 1'b1; + 6'b000100: n1072_o = 1'b1; + 6'b000010: n1072_o = 1'b1; + 6'b000001: n1072_o = 1'b0; + default: n1072_o = 1'b0; + endcase + /* T65_MCode.vhd:214:33 */ + always @* + case (n1053_o) + 6'b100000: n1075_o = 1'b0; + 6'b010000: n1075_o = 1'b1; + 6'b001000: n1075_o = 1'b0; + 6'b000100: n1075_o = 1'b0; + 6'b000010: n1075_o = 1'b0; + 6'b000001: n1075_o = 1'b0; + default: n1075_o = 1'b0; + endcase + /* T65_MCode.vhd:214:33 */ + always @* + case (n1053_o) + 6'b100000: n1080_o = 1'b0; + 6'b010000: n1080_o = 1'b0; + 6'b001000: n1080_o = 1'b0; + 6'b000100: n1080_o = 1'b1; + 6'b000010: n1080_o = 1'b1; + 6'b000001: n1080_o = 1'b1; + default: n1080_o = 1'b0; + endcase + /* T65_MCode.vhd:211:25 */ + assign n1082_o = ir == 8'b00000000; + /* T65_MCode.vhd:242:38 */ + assign n1083_o = {28'b0, mcycle}; // uext + /* T65_MCode.vhd:243:33 */ + assign n1085_o = n1083_o == 31'b0000000000000000000000000000001; + /* T65_MCode.vhd:247:33 */ + assign n1087_o = n1083_o == 31'b0000000000000000000000000000010; + /* T65_MCode.vhd:251:33 */ + assign n1089_o = n1083_o == 31'b0000000000000000000000000000011; + /* T65_MCode.vhd:256:33 */ + assign n1091_o = n1083_o == 31'b0000000000000000000000000000100; + /* T65_MCode.vhd:258:33 */ + assign n1093_o = n1083_o == 31'b0000000000000000000000000000101; + assign n1094_o = {n1093_o, n1091_o, n1089_o, n1087_o, n1085_o}; + /* T65_MCode.vhd:242:33 */ + always @* + case (n1094_o) + 5'b10000: n1099_o = 2'b00; + 5'b01000: n1099_o = 2'b00; + 5'b00100: n1099_o = 2'b01; + 5'b00010: n1099_o = 2'b01; + 5'b00001: n1099_o = 2'b01; + default: n1099_o = 2'b00; + endcase + /* T65_MCode.vhd:242:33 */ + always @* + case (n1094_o) + 5'b10000: n1102_o = n1019_o; + 5'b01000: n1102_o = n1019_o; + 5'b00100: n1102_o = 3'b110; + 5'b00010: n1102_o = 3'b111; + 5'b00001: n1102_o = n1019_o; + default: n1102_o = n1019_o; + endcase + /* T65_MCode.vhd:242:33 */ + always @* + case (n1094_o) + 5'b10000: n1106_o = 2'b10; + 5'b01000: n1106_o = 2'b00; + 5'b00100: n1106_o = 2'b00; + 5'b00010: n1106_o = 2'b00; + 5'b00001: n1106_o = 2'b01; + default: n1106_o = 2'b00; + endcase + /* T65_MCode.vhd:242:33 */ + always @* + case (n1094_o) + 5'b10000: n1110_o = 1'b0; + 5'b01000: n1110_o = 1'b1; + 5'b00100: n1110_o = 1'b1; + 5'b00010: n1110_o = 1'b0; + 5'b00001: n1110_o = 1'b0; + default: n1110_o = 1'b0; + endcase + /* T65_MCode.vhd:242:33 */ + always @* + case (n1094_o) + 5'b10000: n1113_o = 1'b0; + 5'b01000: n1113_o = 1'b0; + 5'b00100: n1113_o = 1'b0; + 5'b00010: n1113_o = 1'b0; + 5'b00001: n1113_o = 1'b1; + default: n1113_o = 1'b0; + endcase + /* T65_MCode.vhd:242:33 */ + always @* + case (n1094_o) + 5'b10000: n1117_o = 1'b0; + 5'b01000: n1117_o = 1'b0; + 5'b00100: n1117_o = 1'b1; + 5'b00010: n1117_o = 1'b1; + 5'b00001: n1117_o = 1'b0; + default: n1117_o = 1'b0; + endcase + /* T65_MCode.vhd:239:25 */ + assign n1119_o = ir == 8'b00100000; + /* T65_MCode.vhd:265:38 */ + assign n1120_o = {28'b0, mcycle}; // uext + /* T65_MCode.vhd:266:33 */ + assign n1122_o = n1120_o == 31'b0000000000000000000000000000001; + /* T65_MCode.vhd:268:33 */ + assign n1124_o = n1120_o == 31'b0000000000000000000000000000010; + /* T65_MCode.vhd:271:33 */ + assign n1126_o = n1120_o == 31'b0000000000000000000000000000011; + /* T65_MCode.vhd:275:33 */ + assign n1128_o = n1120_o == 31'b0000000000000000000000000000100; + /* T65_MCode.vhd:280:33 */ + assign n1130_o = n1120_o == 31'b0000000000000000000000000000101; + assign n1131_o = {n1130_o, n1128_o, n1126_o, n1124_o, n1122_o}; + /* T65_MCode.vhd:265:33 */ + always @* + case (n1131_o) + 5'b10000: n1133_o = n1038_o; + 5'b01000: n1133_o = n1038_o; + 5'b00100: n1133_o = 3'b000; + 5'b00010: n1133_o = n1038_o; + 5'b00001: n1133_o = n1038_o; + default: n1133_o = n1038_o; + endcase + /* T65_MCode.vhd:265:33 */ + always @* + case (n1131_o) + 5'b10000: n1139_o = 2'b00; + 5'b01000: n1139_o = 2'b01; + 5'b00100: n1139_o = 2'b01; + 5'b00010: n1139_o = 2'b01; + 5'b00001: n1139_o = 2'b01; + default: n1139_o = 2'b00; + endcase + /* T65_MCode.vhd:265:33 */ + always @* + case (n1131_o) + 5'b10000: n1142_o = 2'b10; + 5'b01000: n1142_o = 2'b00; + 5'b00100: n1142_o = 2'b00; + 5'b00010: n1142_o = 2'b00; + 5'b00001: n1142_o = 2'b00; + default: n1142_o = 2'b00; + endcase + /* T65_MCode.vhd:265:33 */ + always @* + case (n1131_o) + 5'b10000: n1147_o = 1'b0; + 5'b01000: n1147_o = 1'b1; + 5'b00100: n1147_o = 1'b1; + 5'b00010: n1147_o = 1'b1; + 5'b00001: n1147_o = 1'b0; + default: n1147_o = 1'b0; + endcase + /* T65_MCode.vhd:265:33 */ + always @* + case (n1131_o) + 5'b10000: n1150_o = 1'b0; + 5'b01000: n1150_o = 1'b1; + 5'b00100: n1150_o = 1'b0; + 5'b00010: n1150_o = 1'b0; + 5'b00001: n1150_o = 1'b0; + default: n1150_o = 1'b0; + endcase + /* T65_MCode.vhd:265:33 */ + always @* + case (n1131_o) + 5'b10000: n1153_o = 1'b0; + 5'b01000: n1153_o = 1'b1; + 5'b00100: n1153_o = 1'b0; + 5'b00010: n1153_o = 1'b0; + 5'b00001: n1153_o = 1'b0; + default: n1153_o = 1'b0; + endcase + /* T65_MCode.vhd:262:25 */ + assign n1155_o = ir == 8'b01000000; + /* T65_MCode.vhd:287:38 */ + assign n1156_o = {28'b0, mcycle}; // uext + /* T65_MCode.vhd:288:33 */ + assign n1158_o = n1156_o == 31'b0000000000000000000000000000001; + /* T65_MCode.vhd:290:33 */ + assign n1160_o = n1156_o == 31'b0000000000000000000000000000010; + /* T65_MCode.vhd:293:33 */ + assign n1162_o = n1156_o == 31'b0000000000000000000000000000011; + /* T65_MCode.vhd:297:33 */ + assign n1164_o = n1156_o == 31'b0000000000000000000000000000100; + /* T65_MCode.vhd:299:33 */ + assign n1166_o = n1156_o == 31'b0000000000000000000000000000101; + assign n1167_o = {n1166_o, n1164_o, n1162_o, n1160_o, n1158_o}; + /* T65_MCode.vhd:287:33 */ + always @* + case (n1167_o) + 5'b10000: n1172_o = 2'b00; + 5'b01000: n1172_o = 2'b00; + 5'b00100: n1172_o = 2'b01; + 5'b00010: n1172_o = 2'b01; + 5'b00001: n1172_o = 2'b01; + default: n1172_o = 2'b00; + endcase + /* T65_MCode.vhd:287:33 */ + always @* + case (n1167_o) + 5'b10000: n1176_o = 2'b01; + 5'b01000: n1176_o = 2'b10; + 5'b00100: n1176_o = 2'b00; + 5'b00010: n1176_o = 2'b00; + 5'b00001: n1176_o = 2'b00; + default: n1176_o = 2'b00; + endcase + /* T65_MCode.vhd:287:33 */ + always @* + case (n1167_o) + 5'b10000: n1180_o = 1'b0; + 5'b01000: n1180_o = 1'b0; + 5'b00100: n1180_o = 1'b1; + 5'b00010: n1180_o = 1'b1; + 5'b00001: n1180_o = 1'b0; + default: n1180_o = 1'b0; + endcase + /* T65_MCode.vhd:287:33 */ + always @* + case (n1167_o) + 5'b10000: n1183_o = 1'b0; + 5'b01000: n1183_o = 1'b0; + 5'b00100: n1183_o = 1'b1; + 5'b00010: n1183_o = 1'b0; + 5'b00001: n1183_o = 1'b0; + default: n1183_o = 1'b0; + endcase + /* T65_MCode.vhd:284:25 */ + assign n1185_o = ir == 8'b01100000; + /* T65_MCode.vhd:306:41 */ + assign n1187_o = mode == 2'b00; + /* T65_MCode.vhd:306:54 */ + assign n1188_o = ir[1]; + /* T65_MCode.vhd:306:48 */ + assign n1189_o = n1187_o & n1188_o; + /* T65_MCode.vhd:306:33 */ + assign n1192_o = n1189_o ? 3'b001 : 3'b010; + /* T65_MCode.vhd:309:38 */ + assign n1194_o = {28'b0, mcycle}; // uext + /* T65_MCode.vhd:311:48 */ + assign n1195_o = ir[7:4]; + /* T65_MCode.vhd:312:41 */ + assign n1197_o = n1195_o == 4'b0000; + /* T65_MCode.vhd:314:41 */ + assign n1199_o = n1195_o == 4'b0100; + /* T65_MCode.vhd:316:41 */ + assign n1201_o = n1195_o == 4'b0101; + /* T65_MCode.vhd:318:41 */ + assign n1203_o = n1195_o == 4'b1101; + assign n1204_o = {n1203_o, n1201_o, n1199_o, n1197_o}; + /* T65_MCode.vhd:311:41 */ + always @* + case (n1204_o) + 4'b1000: n1209_o = 3'b010; + 4'b0100: n1209_o = 3'b011; + 4'b0010: n1209_o = 3'b001; + 4'b0001: n1209_o = 3'b101; + default: n1209_o = n1019_o; + endcase + /* T65_MCode.vhd:310:33 */ + assign n1211_o = n1194_o == 31'b0000000000000000000000000000001; + /* T65_MCode.vhd:324:33 */ + assign n1213_o = n1194_o == 31'b0000000000000000000000000000010; + assign n1214_o = {n1213_o, n1211_o}; + /* T65_MCode.vhd:309:33 */ + always @* + case (n1214_o) + 2'b10: n1217_o = 2'b00; + 2'b01: n1217_o = 2'b01; + default: n1217_o = 2'b00; + endcase + /* T65_MCode.vhd:309:33 */ + always @* + case (n1214_o) + 2'b10: n1218_o = n1019_o; + 2'b01: n1218_o = n1209_o; + default: n1218_o = n1019_o; + endcase + /* T65_MCode.vhd:309:33 */ + always @* + case (n1214_o) + 2'b10: n1221_o = 1'b1; + 2'b01: n1221_o = 1'b0; + default: n1221_o = 1'b0; + endcase + /* T65_MCode.vhd:309:33 */ + always @* + case (n1214_o) + 2'b10: n1224_o = 1'b0; + 2'b01: n1224_o = 1'b1; + default: n1224_o = 1'b0; + endcase + /* T65_MCode.vhd:303:25 */ + assign n1226_o = ir == 8'b00001000; + /* T65_MCode.vhd:303:41 */ + assign n1228_o = ir == 8'b01001000; + /* T65_MCode.vhd:303:41 */ + assign n1229_o = n1226_o | n1228_o; + /* T65_MCode.vhd:303:54 */ + assign n1231_o = ir == 8'b01011010; + /* T65_MCode.vhd:303:54 */ + assign n1232_o = n1229_o | n1231_o; + /* T65_MCode.vhd:303:67 */ + assign n1234_o = ir == 8'b11011010; + /* T65_MCode.vhd:303:67 */ + assign n1235_o = n1232_o | n1234_o; + /* T65_MCode.vhd:331:41 */ + assign n1237_o = mode == 2'b00; + /* T65_MCode.vhd:331:54 */ + assign n1238_o = ir[1]; + /* T65_MCode.vhd:331:48 */ + assign n1239_o = n1237_o & n1238_o; + /* T65_MCode.vhd:331:33 */ + assign n1242_o = n1239_o ? 3'b001 : 3'b011; + /* T65_MCode.vhd:334:40 */ + assign n1244_o = ir[7:4]; + /* T65_MCode.vhd:335:33 */ + assign n1246_o = n1244_o == 4'b0010; + /* T65_MCode.vhd:337:33 */ + assign n1248_o = n1244_o == 4'b0110; + /* T65_MCode.vhd:340:49 */ + assign n1250_o = mode != 2'b00; + /* T65_MCode.vhd:340:41 */ + assign n1252_o = n1250_o ? 1'b1 : n1028_o; + /* T65_MCode.vhd:339:33 */ + assign n1254_o = n1244_o == 4'b0111; + /* T65_MCode.vhd:344:49 */ + assign n1256_o = mode != 2'b00; + /* T65_MCode.vhd:344:41 */ + assign n1258_o = n1256_o ? 1'b1 : n1025_o; + /* T65_MCode.vhd:343:33 */ + assign n1260_o = n1244_o == 4'b1111; + assign n1261_o = {n1260_o, n1254_o, n1248_o, n1246_o}; + /* T65_MCode.vhd:334:33 */ + always @* + case (n1261_o) + 4'b1000: n1263_o = n1022_o; + 4'b0100: n1263_o = n1022_o; + 4'b0010: n1263_o = 1'b1; + 4'b0001: n1263_o = n1022_o; + default: n1263_o = n1022_o; + endcase + /* T65_MCode.vhd:334:33 */ + always @* + case (n1261_o) + 4'b1000: n1266_o = 1'b0; + 4'b0100: n1266_o = 1'b0; + 4'b0010: n1266_o = 1'b0; + 4'b0001: n1266_o = 1'b1; + default: n1266_o = 1'b0; + endcase + /* T65_MCode.vhd:334:33 */ + always @* + case (n1261_o) + 4'b1000: n1267_o = n1258_o; + 4'b0100: n1267_o = n1025_o; + 4'b0010: n1267_o = n1025_o; + 4'b0001: n1267_o = n1025_o; + default: n1267_o = n1025_o; + endcase + /* T65_MCode.vhd:334:33 */ + always @* + case (n1261_o) + 4'b1000: n1268_o = n1028_o; + 4'b0100: n1268_o = n1252_o; + 4'b0010: n1268_o = n1028_o; + 4'b0001: n1268_o = n1028_o; + default: n1268_o = n1028_o; + endcase + /* T65_MCode.vhd:349:38 */ + assign n1269_o = {28'b0, mcycle}; // uext + /* T65_MCode.vhd:350:33 */ + assign n1271_o = n1269_o == 31'b0000000000000000000000000000000; + /* T65_MCode.vhd:352:33 */ + assign n1273_o = n1269_o == 31'b0000000000000000000000000000001; + /* T65_MCode.vhd:354:33 */ + assign n1275_o = n1269_o == 31'b0000000000000000000000000000010; + /* T65_MCode.vhd:357:33 */ + assign n1277_o = n1269_o == 31'b0000000000000000000000000000011; + assign n1278_o = {n1277_o, n1275_o, n1273_o, n1271_o}; + /* T65_MCode.vhd:349:33 */ + always @* + case (n1278_o) + 4'b1000: n1280_o = 3'b000; + 4'b0100: n1280_o = n1038_o; + 4'b0010: n1280_o = n1038_o; + 4'b0001: n1280_o = n1038_o; + default: n1280_o = n1038_o; + endcase + /* T65_MCode.vhd:349:33 */ + always @* + case (n1278_o) + 4'b1000: n1284_o = 2'b00; + 4'b0100: n1284_o = 2'b01; + 4'b0010: n1284_o = 2'b01; + 4'b0001: n1284_o = 2'b00; + default: n1284_o = 2'b00; + endcase + /* T65_MCode.vhd:349:33 */ + always @* + case (n1278_o) + 4'b1000: n1287_o = 1'b0; + 4'b0100: n1287_o = 1'b1; + 4'b0010: n1287_o = 1'b0; + 4'b0001: n1287_o = 1'b0; + default: n1287_o = 1'b0; + endcase + /* T65_MCode.vhd:349:33 */ + always @* + case (n1278_o) + 4'b1000: n1290_o = 1'b0; + 4'b0100: n1290_o = 1'b0; + 4'b0010: n1290_o = 1'b0; + 4'b0001: n1290_o = 1'b1; + default: n1290_o = 1'b0; + endcase + /* T65_MCode.vhd:328:25 */ + assign n1292_o = ir == 8'b00101000; + /* T65_MCode.vhd:328:41 */ + assign n1294_o = ir == 8'b01101000; + /* T65_MCode.vhd:328:41 */ + assign n1295_o = n1292_o | n1294_o; + /* T65_MCode.vhd:328:54 */ + assign n1297_o = ir == 8'b01111010; + /* T65_MCode.vhd:328:54 */ + assign n1298_o = n1295_o | n1297_o; + /* T65_MCode.vhd:328:67 */ + assign n1300_o = ir == 8'b11111010; + /* T65_MCode.vhd:328:67 */ + assign n1301_o = n1298_o | n1300_o; + /* T65_MCode.vhd:364:38 */ + assign n1302_o = {28'b0, mcycle}; // uext + /* T65_MCode.vhd:365:33 */ + assign n1304_o = n1302_o == 31'b0000000000000000000000000000000; + /* T65_MCode.vhd:366:33 */ + assign n1306_o = n1302_o == 31'b0000000000000000000000000000001; + assign n1307_o = {n1306_o, n1304_o}; + /* T65_MCode.vhd:364:33 */ + always @* + case (n1307_o) + 2'b10: n1310_o = 2'b01; + 2'b01: n1310_o = 2'b00; + default: n1310_o = 2'b00; + endcase + /* T65_MCode.vhd:361:25 */ + assign n1312_o = ir == 8'b10100000; + /* T65_MCode.vhd:361:41 */ + assign n1314_o = ir == 8'b11000000; + /* T65_MCode.vhd:361:41 */ + assign n1315_o = n1312_o | n1314_o; + /* T65_MCode.vhd:361:54 */ + assign n1317_o = ir == 8'b11100000; + /* T65_MCode.vhd:361:54 */ + assign n1318_o = n1315_o | n1317_o; + /* T65_MCode.vhd:373:38 */ + assign n1319_o = {28'b0, mcycle}; // uext + /* T65_MCode.vhd:374:33 */ + assign n1321_o = n1319_o == 31'b0000000000000000000000000000000; + /* T65_MCode.vhd:375:33 */ + assign n1323_o = n1319_o == 31'b0000000000000000000000000000001; + assign n1324_o = {n1323_o, n1321_o}; + /* T65_MCode.vhd:373:33 */ + always @* + case (n1324_o) + 2'b10: n1326_o = 3'b011; + 2'b01: n1326_o = n1038_o; + default: n1326_o = n1038_o; + endcase + /* T65_MCode.vhd:370:25 */ + assign n1328_o = ir == 8'b10001000; + /* T65_MCode.vhd:382:38 */ + assign n1329_o = {28'b0, mcycle}; // uext + /* T65_MCode.vhd:383:33 */ + assign n1331_o = n1329_o == 31'b0000000000000000000000000000000; + /* T65_MCode.vhd:384:33 */ + assign n1333_o = n1329_o == 31'b0000000000000000000000000000001; + assign n1334_o = {n1333_o, n1331_o}; + /* T65_MCode.vhd:382:33 */ + always @* + case (n1334_o) + 2'b10: n1336_o = 3'b010; + 2'b01: n1336_o = n1038_o; + default: n1336_o = n1038_o; + endcase + /* T65_MCode.vhd:379:25 */ + assign n1338_o = ir == 8'b11001010; + /* T65_MCode.vhd:390:41 */ + assign n1340_o = mode != 2'b00; + /* T65_MCode.vhd:390:33 */ + assign n1342_o = n1340_o ? 1'b1 : n1022_o; + /* T65_MCode.vhd:393:38 */ + assign n1343_o = {28'b0, mcycle}; // uext + /* T65_MCode.vhd:394:33 */ + assign n1345_o = n1343_o == 31'b0000000000000000000000000000000; + /* T65_MCode.vhd:395:33 */ + assign n1347_o = n1343_o == 31'b0000000000000000000000000000001; + assign n1348_o = {n1347_o, n1345_o}; + /* T65_MCode.vhd:393:33 */ + always @* + case (n1348_o) + 2'b10: n1350_o = 3'b100; + 2'b01: n1350_o = n1038_o; + default: n1350_o = n1038_o; + endcase + /* T65_MCode.vhd:388:25 */ + assign n1352_o = ir == 8'b00011010; + /* T65_MCode.vhd:388:41 */ + assign n1354_o = ir == 8'b00111010; + /* T65_MCode.vhd:388:41 */ + assign n1355_o = n1352_o | n1354_o; + /* T65_MCode.vhd:399:25 */ + assign n1363_o = ir == 8'b00001010; + /* T65_MCode.vhd:399:41 */ + assign n1365_o = ir == 8'b00101010; + /* T65_MCode.vhd:399:41 */ + assign n1366_o = n1363_o | n1365_o; + /* T65_MCode.vhd:399:54 */ + assign n1368_o = ir == 8'b01001010; + /* T65_MCode.vhd:399:54 */ + assign n1369_o = n1366_o | n1368_o; + /* T65_MCode.vhd:399:67 */ + assign n1371_o = ir == 8'b01101010; + /* T65_MCode.vhd:399:67 */ + assign n1372_o = n1369_o | n1371_o; + /* T65_MCode.vhd:408:25 */ + assign n1380_o = ir == 8'b10001010; + /* T65_MCode.vhd:408:41 */ + assign n1382_o = ir == 8'b10011000; + /* T65_MCode.vhd:408:41 */ + assign n1383_o = n1380_o | n1382_o; + /* T65_MCode.vhd:418:38 */ + assign n1384_o = {28'b0, mcycle}; // uext + /* T65_MCode.vhd:419:33 */ + assign n1386_o = n1384_o == 31'b0000000000000000000000000000000; + /* T65_MCode.vhd:420:33 */ + assign n1388_o = n1384_o == 31'b0000000000000000000000000000001; + assign n1389_o = {n1388_o, n1386_o}; + /* T65_MCode.vhd:418:33 */ + always @* + case (n1389_o) + 2'b10: n1391_o = 3'b001; + 2'b01: n1391_o = n1038_o; + default: n1391_o = n1038_o; + endcase + /* T65_MCode.vhd:416:25 */ + assign n1393_o = ir == 8'b10101010; + /* T65_MCode.vhd:416:41 */ + assign n1395_o = ir == 8'b10101000; + /* T65_MCode.vhd:416:41 */ + assign n1396_o = n1393_o | n1395_o; + /* T65_MCode.vhd:426:38 */ + assign n1397_o = {28'b0, mcycle}; // uext + /* T65_MCode.vhd:427:33 */ + assign n1399_o = n1397_o == 31'b0000000000000000000000000000000; + /* T65_MCode.vhd:429:33 */ + assign n1401_o = n1397_o == 31'b0000000000000000000000000000001; + assign n1402_o = {n1401_o, n1399_o}; + /* T65_MCode.vhd:426:33 */ + always @* + case (n1402_o) + 2'b10: n1405_o = 1'b0; + 2'b01: n1405_o = 1'b1; + default: n1405_o = 1'b0; + endcase + /* T65_MCode.vhd:424:25 */ + assign n1407_o = ir == 8'b10011010; + /* T65_MCode.vhd:435:38 */ + assign n1408_o = {28'b0, mcycle}; // uext + /* T65_MCode.vhd:436:33 */ + assign n1410_o = n1408_o == 31'b0000000000000000000000000000000; + /* T65_MCode.vhd:437:33 */ + assign n1412_o = n1408_o == 31'b0000000000000000000000000000001; + assign n1413_o = {n1412_o, n1410_o}; + /* T65_MCode.vhd:435:33 */ + always @* + case (n1413_o) + 2'b10: n1415_o = 3'b100; + 2'b01: n1415_o = n1038_o; + default: n1415_o = n1038_o; + endcase + /* T65_MCode.vhd:432:25 */ + assign n1417_o = ir == 8'b10111010; + assign n1421_o = {n1417_o, n1407_o, n1396_o, n1383_o, n1372_o, n1355_o, n1338_o, n1328_o, n1318_o, n1301_o, n1235_o, n1185_o, n1155_o, n1119_o, n1082_o}; + /* T65_MCode.vhd:210:25 */ + always @* + case (n1421_o) + 15'b100000000000000: n1427_o = 3'b001; + 15'b010000000000000: n1427_o = 3'b001; + 15'b001000000000000: n1427_o = 3'b001; + 15'b000100000000000: n1427_o = 3'b001; + 15'b000010000000000: n1427_o = 3'b001; + 15'b000001000000000: n1427_o = 3'b001; + 15'b000000100000000: n1427_o = 3'b001; + 15'b000000010000000: n1427_o = 3'b001; + 15'b000000001000000: n1427_o = 3'b001; + 15'b000000000100000: n1427_o = n1242_o; + 15'b000000000010000: n1427_o = n1192_o; + 15'b000000000001000: n1427_o = 3'b101; + 15'b000000000000100: n1427_o = 3'b101; + 15'b000000000000010: n1427_o = 3'b101; + 15'b000000000000001: n1427_o = 3'b110; + default: n1427_o = 3'b001; + endcase + /* T65_MCode.vhd:210:25 */ + always @* + case (n1421_o) + 15'b100000000000000: n1429_o = n1415_o; + 15'b010000000000000: n1429_o = n1038_o; + 15'b001000000000000: n1429_o = n1391_o; + 15'b000100000000000: n1429_o = n1038_o; + 15'b000010000000000: n1429_o = 3'b001; + 15'b000001000000000: n1429_o = n1350_o; + 15'b000000100000000: n1429_o = n1336_o; + 15'b000000010000000: n1429_o = n1326_o; + 15'b000000001000000: n1429_o = n1038_o; + 15'b000000000100000: n1429_o = n1280_o; + 15'b000000000010000: n1429_o = n1038_o; + 15'b000000000001000: n1429_o = n1038_o; + 15'b000000000000100: n1429_o = n1133_o; + 15'b000000000000010: n1429_o = n1038_o; + 15'b000000000000001: n1429_o = n1038_o; + default: n1429_o = n1038_o; + endcase + /* T65_MCode.vhd:210:25 */ + always @* + case (n1421_o) + 15'b100000000000000: n1431_o = 2'b00; + 15'b010000000000000: n1431_o = 2'b00; + 15'b001000000000000: n1431_o = 2'b00; + 15'b000100000000000: n1431_o = 2'b00; + 15'b000010000000000: n1431_o = 2'b00; + 15'b000001000000000: n1431_o = 2'b00; + 15'b000000100000000: n1431_o = 2'b00; + 15'b000000010000000: n1431_o = 2'b00; + 15'b000000001000000: n1431_o = 2'b00; + 15'b000000000100000: n1431_o = n1284_o; + 15'b000000000010000: n1431_o = n1217_o; + 15'b000000000001000: n1431_o = n1172_o; + 15'b000000000000100: n1431_o = n1139_o; + 15'b000000000000010: n1431_o = n1099_o; + 15'b000000000000001: n1431_o = n1060_o; + default: n1431_o = 2'b00; + endcase + /* T65_MCode.vhd:210:25 */ + always @* + case (n1421_o) + 15'b100000000000000: n1432_o = n1019_o; + 15'b010000000000000: n1432_o = n1019_o; + 15'b001000000000000: n1432_o = n1019_o; + 15'b000100000000000: n1432_o = n1019_o; + 15'b000010000000000: n1432_o = n1019_o; + 15'b000001000000000: n1432_o = n1019_o; + 15'b000000100000000: n1432_o = n1019_o; + 15'b000000010000000: n1432_o = n1019_o; + 15'b000000001000000: n1432_o = n1019_o; + 15'b000000000100000: n1432_o = n1019_o; + 15'b000000000010000: n1432_o = n1218_o; + 15'b000000000001000: n1432_o = n1019_o; + 15'b000000000000100: n1432_o = n1019_o; + 15'b000000000000010: n1432_o = n1102_o; + 15'b000000000000001: n1432_o = n1064_o; + default: n1432_o = n1019_o; + endcase + /* T65_MCode.vhd:210:25 */ + always @* + case (n1421_o) + 15'b100000000000000: n1434_o = 2'b00; + 15'b010000000000000: n1434_o = 2'b00; + 15'b001000000000000: n1434_o = 2'b00; + 15'b000100000000000: n1434_o = 2'b00; + 15'b000010000000000: n1434_o = 2'b00; + 15'b000001000000000: n1434_o = 2'b00; + 15'b000000100000000: n1434_o = 2'b00; + 15'b000000010000000: n1434_o = 2'b00; + 15'b000000001000000: n1434_o = n1310_o; + 15'b000000000100000: n1434_o = 2'b00; + 15'b000000000010000: n1434_o = 2'b00; + 15'b000000000001000: n1434_o = n1176_o; + 15'b000000000000100: n1434_o = n1142_o; + 15'b000000000000010: n1434_o = n1106_o; + 15'b000000000000001: n1434_o = n1067_o; + default: n1434_o = 2'b00; + endcase + /* T65_MCode.vhd:210:25 */ + always @* + case (n1421_o) + 15'b100000000000000: n1436_o = 1'b0; + 15'b010000000000000: n1436_o = 1'b0; + 15'b001000000000000: n1436_o = 1'b0; + 15'b000100000000000: n1436_o = 1'b0; + 15'b000010000000000: n1436_o = 1'b0; + 15'b000001000000000: n1436_o = 1'b0; + 15'b000000100000000: n1436_o = 1'b0; + 15'b000000010000000: n1436_o = 1'b0; + 15'b000000001000000: n1436_o = 1'b0; + 15'b000000000100000: n1436_o = n1287_o; + 15'b000000000010000: n1436_o = 1'b0; + 15'b000000000001000: n1436_o = n1180_o; + 15'b000000000000100: n1436_o = n1147_o; + 15'b000000000000010: n1436_o = 1'b0; + 15'b000000000000001: n1436_o = 1'b0; + default: n1436_o = 1'b0; + endcase + /* T65_MCode.vhd:210:25 */ + always @* + case (n1421_o) + 15'b100000000000000: n1438_o = 1'b0; + 15'b010000000000000: n1438_o = 1'b0; + 15'b001000000000000: n1438_o = 1'b0; + 15'b000100000000000: n1438_o = 1'b0; + 15'b000010000000000: n1438_o = 1'b0; + 15'b000001000000000: n1438_o = 1'b0; + 15'b000000100000000: n1438_o = 1'b0; + 15'b000000010000000: n1438_o = 1'b0; + 15'b000000001000000: n1438_o = 1'b0; + 15'b000000000100000: n1438_o = 1'b0; + 15'b000000000010000: n1438_o = n1221_o; + 15'b000000000001000: n1438_o = 1'b0; + 15'b000000000000100: n1438_o = 1'b0; + 15'b000000000000010: n1438_o = n1110_o; + 15'b000000000000001: n1438_o = n1072_o; + default: n1438_o = 1'b0; + endcase + /* T65_MCode.vhd:210:25 */ + always @* + case (n1421_o) + 15'b100000000000000: n1441_o = n1022_o; + 15'b010000000000000: n1441_o = n1022_o; + 15'b001000000000000: n1441_o = n1022_o; + 15'b000100000000000: n1441_o = 1'b1; + 15'b000010000000000: n1441_o = 1'b1; + 15'b000001000000000: n1441_o = n1342_o; + 15'b000000100000000: n1441_o = n1022_o; + 15'b000000010000000: n1441_o = n1022_o; + 15'b000000001000000: n1441_o = n1022_o; + 15'b000000000100000: n1441_o = n1263_o; + 15'b000000000010000: n1441_o = n1022_o; + 15'b000000000001000: n1441_o = n1022_o; + 15'b000000000000100: n1441_o = n1022_o; + 15'b000000000000010: n1441_o = n1022_o; + 15'b000000000000001: n1441_o = n1022_o; + default: n1441_o = n1022_o; + endcase + /* T65_MCode.vhd:210:25 */ + always @* + case (n1421_o) + 15'b100000000000000: n1443_o = 1'b0; + 15'b010000000000000: n1443_o = 1'b0; + 15'b001000000000000: n1443_o = 1'b0; + 15'b000100000000000: n1443_o = 1'b0; + 15'b000010000000000: n1443_o = 1'b0; + 15'b000001000000000: n1443_o = 1'b0; + 15'b000000100000000: n1443_o = 1'b0; + 15'b000000010000000: n1443_o = 1'b0; + 15'b000000001000000: n1443_o = 1'b0; + 15'b000000000100000: n1443_o = n1266_o; + 15'b000000000010000: n1443_o = 1'b0; + 15'b000000000001000: n1443_o = 1'b0; + 15'b000000000000100: n1443_o = n1150_o; + 15'b000000000000010: n1443_o = 1'b0; + 15'b000000000000001: n1443_o = 1'b0; + default: n1443_o = 1'b0; + endcase + /* T65_MCode.vhd:210:25 */ + always @* + case (n1421_o) + 15'b100000000000000: n1446_o = 1'b1; + 15'b010000000000000: n1446_o = n1025_o; + 15'b001000000000000: n1446_o = n1025_o; + 15'b000100000000000: n1446_o = n1025_o; + 15'b000010000000000: n1446_o = n1025_o; + 15'b000001000000000: n1446_o = n1025_o; + 15'b000000100000000: n1446_o = 1'b1; + 15'b000000010000000: n1446_o = n1025_o; + 15'b000000001000000: n1446_o = n1025_o; + 15'b000000000100000: n1446_o = n1267_o; + 15'b000000000010000: n1446_o = n1025_o; + 15'b000000000001000: n1446_o = n1025_o; + 15'b000000000000100: n1446_o = n1025_o; + 15'b000000000000010: n1446_o = n1025_o; + 15'b000000000000001: n1446_o = n1025_o; + default: n1446_o = n1025_o; + endcase + /* T65_MCode.vhd:210:25 */ + always @* + case (n1421_o) + 15'b100000000000000: n1448_o = n1028_o; + 15'b010000000000000: n1448_o = n1028_o; + 15'b001000000000000: n1448_o = n1028_o; + 15'b000100000000000: n1448_o = n1028_o; + 15'b000010000000000: n1448_o = n1028_o; + 15'b000001000000000: n1448_o = n1028_o; + 15'b000000100000000: n1448_o = n1028_o; + 15'b000000010000000: n1448_o = 1'b1; + 15'b000000001000000: n1448_o = n1028_o; + 15'b000000000100000: n1448_o = n1268_o; + 15'b000000000010000: n1448_o = n1028_o; + 15'b000000000001000: n1448_o = n1028_o; + 15'b000000000000100: n1448_o = n1028_o; + 15'b000000000000010: n1448_o = n1028_o; + 15'b000000000000001: n1448_o = n1028_o; + default: n1448_o = n1028_o; + endcase + /* T65_MCode.vhd:210:25 */ + always @* + case (n1421_o) + 15'b100000000000000: n1450_o = 1'b0; + 15'b010000000000000: n1450_o = n1405_o; + 15'b001000000000000: n1450_o = 1'b0; + 15'b000100000000000: n1450_o = 1'b0; + 15'b000010000000000: n1450_o = 1'b0; + 15'b000001000000000: n1450_o = 1'b0; + 15'b000000100000000: n1450_o = 1'b0; + 15'b000000010000000: n1450_o = 1'b0; + 15'b000000001000000: n1450_o = 1'b0; + 15'b000000000100000: n1450_o = 1'b0; + 15'b000000000010000: n1450_o = 1'b0; + 15'b000000000001000: n1450_o = 1'b0; + 15'b000000000000100: n1450_o = 1'b0; + 15'b000000000000010: n1450_o = 1'b0; + 15'b000000000000001: n1450_o = 1'b0; + default: n1450_o = 1'b0; + endcase + /* T65_MCode.vhd:210:25 */ + always @* + case (n1421_o) + 15'b100000000000000: n1452_o = 1'b0; + 15'b010000000000000: n1452_o = 1'b0; + 15'b001000000000000: n1452_o = 1'b0; + 15'b000100000000000: n1452_o = 1'b0; + 15'b000010000000000: n1452_o = 1'b0; + 15'b000001000000000: n1452_o = 1'b0; + 15'b000000100000000: n1452_o = 1'b0; + 15'b000000010000000: n1452_o = 1'b0; + 15'b000000001000000: n1452_o = 1'b0; + 15'b000000000100000: n1452_o = 1'b0; + 15'b000000000010000: n1452_o = 1'b0; + 15'b000000000001000: n1452_o = n1183_o; + 15'b000000000000100: n1452_o = n1153_o; + 15'b000000000000010: n1452_o = n1113_o; + 15'b000000000000001: n1452_o = n1075_o; + default: n1452_o = 1'b0; + endcase + /* T65_MCode.vhd:210:25 */ + always @* + case (n1421_o) + 15'b100000000000000: n1454_o = 1'b0; + 15'b010000000000000: n1454_o = 1'b0; + 15'b001000000000000: n1454_o = 1'b0; + 15'b000100000000000: n1454_o = 1'b0; + 15'b000010000000000: n1454_o = 1'b0; + 15'b000001000000000: n1454_o = 1'b0; + 15'b000000100000000: n1454_o = 1'b0; + 15'b000000010000000: n1454_o = 1'b0; + 15'b000000001000000: n1454_o = 1'b0; + 15'b000000000100000: n1454_o = n1290_o; + 15'b000000000010000: n1454_o = 1'b0; + 15'b000000000001000: n1454_o = 1'b0; + 15'b000000000000100: n1454_o = 1'b0; + 15'b000000000000010: n1454_o = 1'b0; + 15'b000000000000001: n1454_o = 1'b0; + default: n1454_o = 1'b0; + endcase + /* T65_MCode.vhd:210:25 */ + always @* + case (n1421_o) + 15'b100000000000000: n1456_o = 1'b0; + 15'b010000000000000: n1456_o = 1'b0; + 15'b001000000000000: n1456_o = 1'b0; + 15'b000100000000000: n1456_o = 1'b0; + 15'b000010000000000: n1456_o = 1'b0; + 15'b000001000000000: n1456_o = 1'b0; + 15'b000000100000000: n1456_o = 1'b0; + 15'b000000010000000: n1456_o = 1'b0; + 15'b000000001000000: n1456_o = 1'b0; + 15'b000000000100000: n1456_o = 1'b0; + 15'b000000000010000: n1456_o = n1224_o; + 15'b000000000001000: n1456_o = 1'b0; + 15'b000000000000100: n1456_o = 1'b0; + 15'b000000000000010: n1456_o = n1117_o; + 15'b000000000000001: n1456_o = n1080_o; + default: n1456_o = 1'b0; + endcase + /* T65_MCode.vhd:207:17 */ + assign n1458_o = n1039_o == 5'b00000; + /* T65_MCode.vhd:207:30 */ + assign n1460_o = n1039_o == 5'b01000; + /* T65_MCode.vhd:207:30 */ + assign n1461_o = n1458_o | n1460_o; + /* T65_MCode.vhd:207:40 */ + assign n1463_o = n1039_o == 5'b01010; + /* T65_MCode.vhd:207:40 */ + assign n1464_o = n1461_o | n1463_o; + /* T65_MCode.vhd:207:50 */ + assign n1466_o = n1039_o == 5'b11000; + /* T65_MCode.vhd:207:50 */ + assign n1467_o = n1464_o | n1466_o; + /* T65_MCode.vhd:207:60 */ + assign n1469_o = n1039_o == 5'b11010; + /* T65_MCode.vhd:207:60 */ + assign n1470_o = n1467_o | n1469_o; + /* T65_MCode.vhd:460:30 */ + assign n1471_o = ir[7:6]; + /* T65_MCode.vhd:460:43 */ + assign n1473_o = n1471_o != 2'b10; + /* T65_MCode.vhd:460:25 */ + assign n1475_o = n1473_o ? 1'b1 : n1022_o; + /* T65_MCode.vhd:463:30 */ + assign n1476_o = {28'b0, mcycle}; // uext + /* T65_MCode.vhd:464:25 */ + assign n1478_o = n1476_o == 31'b0000000000000000000000000000000; + /* T65_MCode.vhd:465:25 */ + assign n1480_o = n1476_o == 31'b0000000000000000000000000000001; + /* T65_MCode.vhd:469:25 */ + assign n1482_o = n1476_o == 31'b0000000000000000000000000000010; + /* T65_MCode.vhd:472:25 */ + assign n1484_o = n1476_o == 31'b0000000000000000000000000000011; + /* T65_MCode.vhd:478:38 */ + assign n1485_o = ir[7:5]; + /* T65_MCode.vhd:478:51 */ + assign n1487_o = n1485_o == 3'b100; + /* T65_MCode.vhd:478:33 */ + assign n1490_o = n1487_o ? 1'b1 : 1'b0; + /* T65_MCode.vhd:476:25 */ + assign n1492_o = n1476_o == 31'b0000000000000000000000000000100; + /* T65_MCode.vhd:482:25 */ + assign n1494_o = n1476_o == 31'b0000000000000000000000000000101; + assign n1495_o = {n1494_o, n1492_o, n1484_o, n1482_o, n1480_o, n1478_o}; + /* T65_MCode.vhd:463:25 */ + always @* + case (n1495_o) + 6'b100000: n1501_o = 2'b00; + 6'b010000: n1501_o = 2'b11; + 6'b001000: n1501_o = 2'b10; + 6'b000100: n1501_o = 2'b10; + 6'b000010: n1501_o = 2'b10; + 6'b000001: n1501_o = 2'b00; + default: n1501_o = 2'b00; + endcase + /* T65_MCode.vhd:463:25 */ + always @* + case (n1495_o) + 6'b100000: n1504_o = 2'b00; + 6'b010000: n1504_o = 2'b00; + 6'b001000: n1504_o = 2'b00; + 6'b000100: n1504_o = 2'b00; + 6'b000010: n1504_o = 2'b01; + 6'b000001: n1504_o = 2'b00; + default: n1504_o = 2'b00; + endcase + /* T65_MCode.vhd:463:25 */ + always @* + case (n1495_o) + 6'b100000: n1507_o = 2'b00; + 6'b010000: n1507_o = 2'b00; + 6'b001000: n1507_o = 2'b01; + 6'b000100: n1507_o = 2'b00; + 6'b000010: n1507_o = 2'b00; + 6'b000001: n1507_o = 2'b00; + default: n1507_o = 2'b00; + endcase + /* T65_MCode.vhd:463:25 */ + always @* + case (n1495_o) + 6'b100000: n1510_o = 1'b0; + 6'b010000: n1510_o = 1'b0; + 6'b001000: n1510_o = 1'b0; + 6'b000100: n1510_o = 1'b1; + 6'b000010: n1510_o = 1'b0; + 6'b000001: n1510_o = 1'b0; + default: n1510_o = 1'b0; + endcase + /* T65_MCode.vhd:463:25 */ + always @* + case (n1495_o) + 6'b100000: n1513_o = 1'b0; + 6'b010000: n1513_o = 1'b0; + 6'b001000: n1513_o = 1'b0; + 6'b000100: n1513_o = 1'b0; + 6'b000010: n1513_o = 1'b1; + 6'b000001: n1513_o = 1'b0; + default: n1513_o = 1'b0; + endcase + /* T65_MCode.vhd:463:25 */ + always @* + case (n1495_o) + 6'b100000: n1516_o = 1'b0; + 6'b010000: n1516_o = 1'b0; + 6'b001000: n1516_o = 1'b1; + 6'b000100: n1516_o = 1'b0; + 6'b000010: n1516_o = 1'b0; + 6'b000001: n1516_o = 1'b0; + default: n1516_o = 1'b0; + endcase + /* T65_MCode.vhd:463:25 */ + always @* + case (n1495_o) + 6'b100000: n1519_o = 1'b0; + 6'b010000: n1519_o = 1'b1; + 6'b001000: n1519_o = 1'b0; + 6'b000100: n1519_o = 1'b0; + 6'b000010: n1519_o = 1'b0; + 6'b000001: n1519_o = 1'b0; + default: n1519_o = 1'b0; + endcase + /* T65_MCode.vhd:463:25 */ + always @* + case (n1495_o) + 6'b100000: n1521_o = 1'b0; + 6'b010000: n1521_o = n1490_o; + 6'b001000: n1521_o = 1'b0; + 6'b000100: n1521_o = 1'b0; + 6'b000010: n1521_o = 1'b0; + 6'b000001: n1521_o = 1'b0; + default: n1521_o = 1'b0; + endcase + /* T65_MCode.vhd:456:17 */ + assign n1523_o = n1039_o == 5'b00001; + /* T65_MCode.vhd:456:30 */ + assign n1525_o = n1039_o == 5'b00011; + /* T65_MCode.vhd:456:30 */ + assign n1526_o = n1523_o | n1525_o; + /* T65_MCode.vhd:491:30 */ + assign n1527_o = {28'b0, mcycle}; // uext + /* T65_MCode.vhd:492:25 */ + assign n1529_o = n1527_o == 31'b0000000000000000000000000000000; + /* T65_MCode.vhd:493:25 */ + assign n1531_o = n1527_o == 31'b0000000000000000000000000000001; + assign n1532_o = {n1531_o, n1529_o}; + /* T65_MCode.vhd:491:25 */ + always @* + case (n1532_o) + 2'b10: n1535_o = 2'b01; + 2'b01: n1535_o = 2'b00; + default: n1535_o = 2'b00; + endcase + /* T65_MCode.vhd:487:17 */ + assign n1537_o = n1039_o == 5'b01001; + /* T65_MCode.vhd:487:30 */ + assign n1539_o = n1039_o == 5'b01011; + /* T65_MCode.vhd:487:30 */ + assign n1540_o = n1537_o | n1539_o; + /* T65_MCode.vhd:504:30 */ + assign n1541_o = {28'b0, mcycle}; // uext + /* T65_MCode.vhd:505:25 */ + assign n1543_o = n1541_o == 31'b0000000000000000000000000000000; + /* T65_MCode.vhd:507:39 */ + assign n1545_o = ir == 8'b10100010; + /* T65_MCode.vhd:507:33 */ + assign n1548_o = n1545_o ? 2'b01 : 2'b00; + /* T65_MCode.vhd:506:25 */ + assign n1550_o = n1541_o == 31'b0000000000000000000000000000001; + assign n1551_o = {n1550_o, n1543_o}; + /* T65_MCode.vhd:504:25 */ + always @* + case (n1551_o) + 2'b10: n1553_o = n1548_o; + 2'b01: n1553_o = 2'b00; + default: n1553_o = 2'b00; + endcase + /* T65_MCode.vhd:500:17 */ + assign n1555_o = n1039_o == 5'b00010; + /* T65_MCode.vhd:500:30 */ + assign n1557_o = n1039_o == 5'b10010; + /* T65_MCode.vhd:500:30 */ + assign n1558_o = n1555_o | n1557_o; + /* T65_MCode.vhd:521:30 */ + assign n1559_o = {28'b0, mcycle}; // uext + /* T65_MCode.vhd:523:38 */ + assign n1560_o = ir[7:5]; + /* T65_MCode.vhd:523:51 */ + assign n1562_o = n1560_o == 3'b001; + /* T65_MCode.vhd:523:33 */ + assign n1565_o = n1562_o ? 1'b1 : 1'b0; + /* T65_MCode.vhd:522:25 */ + assign n1567_o = n1559_o == 31'b0000000000000000000000000000000; + /* T65_MCode.vhd:529:38 */ + assign n1568_o = ir[7:5]; + /* T65_MCode.vhd:529:51 */ + assign n1570_o = n1568_o == 3'b100; + /* T65_MCode.vhd:529:33 */ + assign n1573_o = n1570_o ? 1'b1 : 1'b0; + /* T65_MCode.vhd:526:25 */ + assign n1575_o = n1559_o == 31'b0000000000000000000000000000001; + /* T65_MCode.vhd:533:25 */ + assign n1577_o = n1559_o == 31'b0000000000000000000000000000010; + assign n1578_o = {n1577_o, n1575_o, n1567_o}; + /* T65_MCode.vhd:521:25 */ + always @* + case (n1578_o) + 3'b100: n1581_o = 2'b00; + 3'b010: n1581_o = 2'b10; + 3'b001: n1581_o = 2'b00; + default: n1581_o = 2'b00; + endcase + /* T65_MCode.vhd:521:25 */ + always @* + case (n1578_o) + 3'b100: n1584_o = 2'b00; + 3'b010: n1584_o = 2'b01; + 3'b001: n1584_o = 2'b00; + default: n1584_o = 2'b00; + endcase + /* T65_MCode.vhd:521:25 */ + always @* + case (n1578_o) + 3'b100: n1587_o = 1'b0; + 3'b010: n1587_o = 1'b1; + 3'b001: n1587_o = 1'b0; + default: n1587_o = 1'b0; + endcase + /* T65_MCode.vhd:521:25 */ + always @* + case (n1578_o) + 3'b100: n1589_o = 1'b0; + 3'b010: n1589_o = 1'b0; + 3'b001: n1589_o = n1565_o; + default: n1589_o = 1'b0; + endcase + /* T65_MCode.vhd:521:25 */ + always @* + case (n1578_o) + 3'b100: n1591_o = 1'b0; + 3'b010: n1591_o = n1573_o; + 3'b001: n1591_o = 1'b0; + default: n1591_o = 1'b0; + endcase + /* T65_MCode.vhd:517:17 */ + assign n1593_o = n1039_o == 5'b00100; + /* T65_MCode.vhd:541:30 */ + assign n1594_o = ir[7:6]; + /* T65_MCode.vhd:541:43 */ + assign n1596_o = n1594_o != 2'b10; + /* T65_MCode.vhd:541:57 */ + assign n1597_o = ir[1:0]; + /* T65_MCode.vhd:541:70 */ + assign n1599_o = n1597_o == 2'b10; + /* T65_MCode.vhd:541:51 */ + assign n1600_o = n1596_o & n1599_o; + /* T65_MCode.vhd:544:38 */ + assign n1601_o = {28'b0, mcycle}; // uext + /* T65_MCode.vhd:545:33 */ + assign n1603_o = n1601_o == 31'b0000000000000000000000000000001; + /* T65_MCode.vhd:549:33 */ + assign n1605_o = n1601_o == 31'b0000000000000000000000000000010; + /* T65_MCode.vhd:553:33 */ + assign n1607_o = n1601_o == 31'b0000000000000000000000000000011; + /* T65_MCode.vhd:558:33 */ + assign n1609_o = n1601_o == 31'b0000000000000000000000000000100; + assign n1610_o = {n1609_o, n1607_o, n1605_o, n1603_o}; + /* T65_MCode.vhd:544:33 */ + always @* + case (n1610_o) + 4'b1000: n1615_o = 2'b00; + 4'b0100: n1615_o = 2'b10; + 4'b0010: n1615_o = 2'b10; + 4'b0001: n1615_o = 2'b10; + default: n1615_o = 2'b00; + endcase + /* T65_MCode.vhd:544:33 */ + always @* + case (n1610_o) + 4'b1000: n1618_o = 2'b00; + 4'b0100: n1618_o = 2'b00; + 4'b0010: n1618_o = 2'b00; + 4'b0001: n1618_o = 2'b01; + default: n1618_o = 2'b00; + endcase + /* T65_MCode.vhd:544:33 */ + always @* + case (n1610_o) + 4'b1000: n1621_o = 1'b0; + 4'b0100: n1621_o = 1'b0; + 4'b0010: n1621_o = 1'b1; + 4'b0001: n1621_o = 1'b0; + default: n1621_o = 1'b0; + endcase + /* T65_MCode.vhd:544:33 */ + always @* + case (n1610_o) + 4'b1000: n1624_o = 1'b0; + 4'b0100: n1624_o = 1'b1; + 4'b0010: n1624_o = 1'b0; + 4'b0001: n1624_o = 1'b0; + default: n1624_o = 1'b0; + endcase + /* T65_MCode.vhd:544:33 */ + always @* + case (n1610_o) + 4'b1000: n1627_o = 1'b0; + 4'b0100: n1627_o = 1'b0; + 4'b0010: n1627_o = 1'b0; + 4'b0001: n1627_o = 1'b1; + default: n1627_o = 1'b0; + endcase + /* T65_MCode.vhd:544:33 */ + always @* + case (n1610_o) + 4'b1000: n1630_o = 1'b0; + 4'b0100: n1630_o = 1'b1; + 4'b0010: n1630_o = 1'b0; + 4'b0001: n1630_o = 1'b0; + default: n1630_o = 1'b0; + endcase + /* T65_MCode.vhd:544:33 */ + always @* + case (n1610_o) + 4'b1000: n1634_o = 1'b0; + 4'b0100: n1634_o = 1'b1; + 4'b0010: n1634_o = 1'b1; + 4'b0001: n1634_o = 1'b0; + default: n1634_o = 1'b0; + endcase + /* T65_MCode.vhd:563:38 */ + assign n1635_o = ir[7:6]; + /* T65_MCode.vhd:563:51 */ + assign n1637_o = n1635_o != 2'b10; + /* T65_MCode.vhd:563:33 */ + assign n1639_o = n1637_o ? 1'b1 : n1022_o; + /* T65_MCode.vhd:566:38 */ + assign n1640_o = {28'b0, mcycle}; // uext + /* T65_MCode.vhd:567:33 */ + assign n1642_o = n1640_o == 31'b0000000000000000000000000000000; + /* T65_MCode.vhd:571:46 */ + assign n1643_o = ir[7:5]; + /* T65_MCode.vhd:571:59 */ + assign n1645_o = n1643_o == 3'b100; + /* T65_MCode.vhd:571:41 */ + assign n1648_o = n1645_o ? 1'b1 : 1'b0; + /* T65_MCode.vhd:568:33 */ + assign n1650_o = n1640_o == 31'b0000000000000000000000000000001; + /* T65_MCode.vhd:575:33 */ + assign n1652_o = n1640_o == 31'b0000000000000000000000000000010; + assign n1653_o = {n1652_o, n1650_o, n1642_o}; + /* T65_MCode.vhd:566:33 */ + always @* + case (n1653_o) + 3'b100: n1656_o = 2'b00; + 3'b010: n1656_o = 2'b10; + 3'b001: n1656_o = 2'b00; + default: n1656_o = 2'b00; + endcase + /* T65_MCode.vhd:566:33 */ + always @* + case (n1653_o) + 3'b100: n1659_o = 2'b00; + 3'b010: n1659_o = 2'b01; + 3'b001: n1659_o = 2'b00; + default: n1659_o = 2'b00; + endcase + /* T65_MCode.vhd:566:33 */ + always @* + case (n1653_o) + 3'b100: n1662_o = 1'b0; + 3'b010: n1662_o = 1'b1; + 3'b001: n1662_o = 1'b0; + default: n1662_o = 1'b0; + endcase + /* T65_MCode.vhd:566:33 */ + always @* + case (n1653_o) + 3'b100: n1664_o = 1'b0; + 3'b010: n1664_o = n1648_o; + 3'b001: n1664_o = 1'b0; + default: n1664_o = 1'b0; + endcase + /* T65_MCode.vhd:541:25 */ + assign n1667_o = n1600_o ? 3'b100 : 3'b010; + /* T65_MCode.vhd:541:25 */ + assign n1668_o = n1600_o ? n1615_o : n1656_o; + /* T65_MCode.vhd:541:25 */ + assign n1669_o = n1600_o ? n1618_o : n1659_o; + /* T65_MCode.vhd:541:25 */ + assign n1670_o = n1600_o ? n1022_o : n1639_o; + /* T65_MCode.vhd:541:25 */ + assign n1672_o = n1600_o ? n1621_o : 1'b0; + /* T65_MCode.vhd:541:25 */ + assign n1674_o = n1600_o ? n1624_o : 1'b0; + /* T65_MCode.vhd:541:25 */ + assign n1675_o = n1600_o ? n1627_o : n1662_o; + /* T65_MCode.vhd:541:25 */ + assign n1677_o = n1600_o ? n1630_o : 1'b0; + /* T65_MCode.vhd:541:25 */ + assign n1678_o = n1600_o ? n1634_o : n1664_o; + /* T65_MCode.vhd:538:17 */ + assign n1680_o = n1039_o == 5'b00101; + /* T65_MCode.vhd:538:30 */ + assign n1682_o = n1039_o == 5'b00110; + /* T65_MCode.vhd:538:30 */ + assign n1683_o = n1680_o | n1682_o; + /* T65_MCode.vhd:538:40 */ + assign n1685_o = n1039_o == 5'b00111; + /* T65_MCode.vhd:538:40 */ + assign n1686_o = n1683_o | n1685_o; + /* T65_MCode.vhd:584:30 */ + assign n1687_o = ir[7:6]; + /* T65_MCode.vhd:584:43 */ + assign n1689_o = n1687_o == 2'b01; + /* T65_MCode.vhd:584:56 */ + assign n1690_o = ir[4:0]; + /* T65_MCode.vhd:584:69 */ + assign n1692_o = n1690_o == 5'b01100; + /* T65_MCode.vhd:584:50 */ + assign n1693_o = n1689_o & n1692_o; + /* T65_MCode.vhd:586:38 */ + assign n1694_o = ir[5]; + /* T65_MCode.vhd:586:42 */ + assign n1695_o = ~n1694_o; + /* T65_MCode.vhd:589:46 */ + assign n1696_o = {28'b0, mcycle}; // uext + /* T65_MCode.vhd:590:41 */ + assign n1698_o = n1696_o == 31'b0000000000000000000000000000001; + /* T65_MCode.vhd:593:41 */ + assign n1700_o = n1696_o == 31'b0000000000000000000000000000010; + assign n1701_o = {n1700_o, n1698_o}; + /* T65_MCode.vhd:589:41 */ + always @* + case (n1701_o) + 2'b10: n1705_o = 2'b10; + 2'b01: n1705_o = 2'b01; + default: n1705_o = 2'b00; + endcase + /* T65_MCode.vhd:589:41 */ + always @* + case (n1701_o) + 2'b10: n1708_o = 1'b0; + 2'b01: n1708_o = 1'b1; + default: n1708_o = 1'b0; + endcase + /* T65_MCode.vhd:600:46 */ + assign n1709_o = {28'b0, mcycle}; // uext + /* T65_MCode.vhd:601:41 */ + assign n1711_o = n1709_o == 31'b0000000000000000000000000000001; + /* T65_MCode.vhd:607:57 */ + assign n1713_o = mode != 2'b00; + /* T65_MCode.vhd:607:49 */ + assign n1716_o = n1713_o ? 2'b10 : 2'b00; + /* T65_MCode.vhd:610:57 */ + assign n1718_o = mode == 2'b00; + /* T65_MCode.vhd:610:49 */ + assign n1721_o = n1718_o ? 2'b11 : 2'b00; + /* T65_MCode.vhd:605:41 */ + assign n1723_o = n1709_o == 31'b0000000000000000000000000000010; + /* T65_MCode.vhd:615:57 */ + assign n1725_o = mode == 2'b00; + /* T65_MCode.vhd:615:49 */ + assign n1728_o = n1725_o ? 2'b11 : 2'b00; + /* T65_MCode.vhd:615:49 */ + assign n1731_o = n1725_o ? 2'b00 : 2'b01; + /* T65_MCode.vhd:615:49 */ + assign n1734_o = n1725_o ? 2'b01 : 2'b00; + /* T65_MCode.vhd:613:41 */ + assign n1736_o = n1709_o == 31'b0000000000000000000000000000011; + /* T65_MCode.vhd:621:41 */ + assign n1738_o = n1709_o == 31'b0000000000000000000000000000100; + assign n1739_o = {n1738_o, n1736_o, n1723_o, n1711_o}; + /* T65_MCode.vhd:600:41 */ + always @* + case (n1739_o) + 4'b1000: n1741_o = 2'b00; + 4'b0100: n1741_o = n1728_o; + 4'b0010: n1741_o = n1721_o; + 4'b0001: n1741_o = 2'b00; + default: n1741_o = 2'b00; + endcase + /* T65_MCode.vhd:600:41 */ + always @* + case (n1739_o) + 4'b1000: n1745_o = 2'b10; + 4'b0100: n1745_o = n1731_o; + 4'b0010: n1745_o = n1716_o; + 4'b0001: n1745_o = 2'b01; + default: n1745_o = 2'b00; + endcase + /* T65_MCode.vhd:600:41 */ + always @* + case (n1739_o) + 4'b1000: n1747_o = 2'b00; + 4'b0100: n1747_o = n1734_o; + 4'b0010: n1747_o = 2'b00; + 4'b0001: n1747_o = 2'b00; + default: n1747_o = 2'b00; + endcase + /* T65_MCode.vhd:600:41 */ + always @* + case (n1739_o) + 4'b1000: n1751_o = 1'b0; + 4'b0100: n1751_o = 1'b1; + 4'b0010: n1751_o = 1'b0; + 4'b0001: n1751_o = 1'b1; + default: n1751_o = 1'b0; + endcase + /* T65_MCode.vhd:600:41 */ + always @* + case (n1739_o) + 4'b1000: n1754_o = 1'b0; + 4'b0100: n1754_o = 1'b0; + 4'b0010: n1754_o = 1'b0; + 4'b0001: n1754_o = 1'b1; + default: n1754_o = 1'b0; + endcase + /* T65_MCode.vhd:600:41 */ + always @* + case (n1739_o) + 4'b1000: n1757_o = 1'b0; + 4'b0100: n1757_o = 1'b0; + 4'b0010: n1757_o = 1'b1; + 4'b0001: n1757_o = 1'b0; + default: n1757_o = 1'b0; + endcase + /* T65_MCode.vhd:586:33 */ + assign n1760_o = n1695_o ? 3'b010 : 3'b100; + /* T65_MCode.vhd:586:33 */ + assign n1762_o = n1695_o ? 2'b00 : n1741_o; + /* T65_MCode.vhd:586:33 */ + assign n1763_o = n1695_o ? n1705_o : n1745_o; + /* T65_MCode.vhd:586:33 */ + assign n1765_o = n1695_o ? 2'b00 : n1747_o; + /* T65_MCode.vhd:586:33 */ + assign n1766_o = n1695_o ? n1708_o : n1751_o; + /* T65_MCode.vhd:586:33 */ + assign n1768_o = n1695_o ? 1'b0 : n1754_o; + /* T65_MCode.vhd:586:33 */ + assign n1770_o = n1695_o ? 1'b0 : n1757_o; + /* T65_MCode.vhd:628:38 */ + assign n1771_o = {28'b0, mcycle}; // uext + /* T65_MCode.vhd:630:46 */ + assign n1772_o = ir[7:5]; + /* T65_MCode.vhd:630:59 */ + assign n1774_o = n1772_o == 3'b001; + /* T65_MCode.vhd:630:41 */ + assign n1777_o = n1774_o ? 1'b1 : 1'b0; + /* T65_MCode.vhd:629:33 */ + assign n1779_o = n1771_o == 31'b0000000000000000000000000000000; + /* T65_MCode.vhd:633:33 */ + assign n1781_o = n1771_o == 31'b0000000000000000000000000000001; + /* T65_MCode.vhd:639:46 */ + assign n1782_o = ir[7:5]; + /* T65_MCode.vhd:639:59 */ + assign n1784_o = n1782_o == 3'b100; + /* T65_MCode.vhd:639:41 */ + assign n1787_o = n1784_o ? 1'b1 : 1'b0; + /* T65_MCode.vhd:636:33 */ + assign n1789_o = n1771_o == 31'b0000000000000000000000000000010; + /* T65_MCode.vhd:643:33 */ + assign n1791_o = n1771_o == 31'b0000000000000000000000000000011; + assign n1792_o = {n1791_o, n1789_o, n1781_o, n1779_o}; + /* T65_MCode.vhd:628:33 */ + always @* + case (n1792_o) + 4'b1000: n1795_o = 2'b00; + 4'b0100: n1795_o = 2'b11; + 4'b0010: n1795_o = 2'b00; + 4'b0001: n1795_o = 2'b00; + default: n1795_o = 2'b00; + endcase + /* T65_MCode.vhd:628:33 */ + always @* + case (n1792_o) + 4'b1000: n1799_o = 2'b00; + 4'b0100: n1799_o = 2'b01; + 4'b0010: n1799_o = 2'b01; + 4'b0001: n1799_o = 2'b00; + default: n1799_o = 2'b00; + endcase + /* T65_MCode.vhd:628:33 */ + always @* + case (n1792_o) + 4'b1000: n1802_o = 1'b0; + 4'b0100: n1802_o = 1'b0; + 4'b0010: n1802_o = 1'b1; + 4'b0001: n1802_o = 1'b0; + default: n1802_o = 1'b0; + endcase + /* T65_MCode.vhd:628:33 */ + always @* + case (n1792_o) + 4'b1000: n1805_o = 1'b0; + 4'b0100: n1805_o = 1'b1; + 4'b0010: n1805_o = 1'b0; + 4'b0001: n1805_o = 1'b0; + default: n1805_o = 1'b0; + endcase + /* T65_MCode.vhd:628:33 */ + always @* + case (n1792_o) + 4'b1000: n1807_o = 1'b0; + 4'b0100: n1807_o = 1'b0; + 4'b0010: n1807_o = 1'b0; + 4'b0001: n1807_o = n1777_o; + default: n1807_o = 1'b0; + endcase + /* T65_MCode.vhd:628:33 */ + always @* + case (n1792_o) + 4'b1000: n1809_o = 1'b0; + 4'b0100: n1809_o = n1787_o; + 4'b0010: n1809_o = 1'b0; + 4'b0001: n1809_o = 1'b0; + default: n1809_o = 1'b0; + endcase + /* T65_MCode.vhd:584:25 */ + assign n1811_o = n1693_o ? n1760_o : 3'b011; + /* T65_MCode.vhd:584:25 */ + assign n1812_o = n1693_o ? n1762_o : n1795_o; + /* T65_MCode.vhd:584:25 */ + assign n1813_o = n1693_o ? n1763_o : n1799_o; + /* T65_MCode.vhd:584:25 */ + assign n1815_o = n1693_o ? n1765_o : 2'b00; + /* T65_MCode.vhd:584:25 */ + assign n1817_o = n1693_o ? n1766_o : 1'b0; + /* T65_MCode.vhd:584:25 */ + assign n1818_o = n1693_o ? n1768_o : n1802_o; + /* T65_MCode.vhd:584:25 */ + assign n1819_o = n1693_o ? n1770_o : n1805_o; + /* T65_MCode.vhd:584:25 */ + assign n1821_o = n1693_o ? 1'b0 : n1807_o; + /* T65_MCode.vhd:584:25 */ + assign n1823_o = n1693_o ? 1'b0 : n1809_o; + /* T65_MCode.vhd:581:17 */ + assign n1825_o = n1039_o == 5'b01100; + /* T65_MCode.vhd:652:30 */ + assign n1826_o = ir[7:6]; + /* T65_MCode.vhd:652:43 */ + assign n1828_o = n1826_o != 2'b10; + /* T65_MCode.vhd:652:57 */ + assign n1829_o = ir[1:0]; + /* T65_MCode.vhd:652:70 */ + assign n1831_o = n1829_o == 2'b10; + /* T65_MCode.vhd:652:51 */ + assign n1832_o = n1828_o & n1831_o; + /* T65_MCode.vhd:655:38 */ + assign n1833_o = {28'b0, mcycle}; // uext + /* T65_MCode.vhd:656:33 */ + assign n1835_o = n1833_o == 31'b0000000000000000000000000000001; + /* T65_MCode.vhd:659:33 */ + assign n1837_o = n1833_o == 31'b0000000000000000000000000000010; + /* T65_MCode.vhd:663:33 */ + assign n1839_o = n1833_o == 31'b0000000000000000000000000000011; + /* T65_MCode.vhd:667:33 */ + assign n1841_o = n1833_o == 31'b0000000000000000000000000000100; + /* T65_MCode.vhd:672:33 */ + assign n1843_o = n1833_o == 31'b0000000000000000000000000000101; + assign n1844_o = {n1843_o, n1841_o, n1839_o, n1837_o, n1835_o}; + /* T65_MCode.vhd:655:33 */ + always @* + case (n1844_o) + 5'b10000: n1849_o = 2'b00; + 5'b01000: n1849_o = 2'b11; + 5'b00100: n1849_o = 2'b11; + 5'b00010: n1849_o = 2'b11; + 5'b00001: n1849_o = 2'b00; + default: n1849_o = 2'b00; + endcase + /* T65_MCode.vhd:655:33 */ + always @* + case (n1844_o) + 5'b10000: n1853_o = 2'b00; + 5'b01000: n1853_o = 2'b00; + 5'b00100: n1853_o = 2'b00; + 5'b00010: n1853_o = 2'b01; + 5'b00001: n1853_o = 2'b01; + default: n1853_o = 2'b00; + endcase + /* T65_MCode.vhd:655:33 */ + always @* + case (n1844_o) + 5'b10000: n1856_o = 1'b0; + 5'b01000: n1856_o = 1'b0; + 5'b00100: n1856_o = 1'b1; + 5'b00010: n1856_o = 1'b0; + 5'b00001: n1856_o = 1'b0; + default: n1856_o = 1'b0; + endcase + /* T65_MCode.vhd:655:33 */ + always @* + case (n1844_o) + 5'b10000: n1859_o = 1'b0; + 5'b01000: n1859_o = 1'b1; + 5'b00100: n1859_o = 1'b0; + 5'b00010: n1859_o = 1'b0; + 5'b00001: n1859_o = 1'b0; + default: n1859_o = 1'b0; + endcase + /* T65_MCode.vhd:655:33 */ + always @* + case (n1844_o) + 5'b10000: n1862_o = 1'b0; + 5'b01000: n1862_o = 1'b0; + 5'b00100: n1862_o = 1'b0; + 5'b00010: n1862_o = 1'b0; + 5'b00001: n1862_o = 1'b1; + default: n1862_o = 1'b0; + endcase + /* T65_MCode.vhd:655:33 */ + always @* + case (n1844_o) + 5'b10000: n1865_o = 1'b0; + 5'b01000: n1865_o = 1'b0; + 5'b00100: n1865_o = 1'b0; + 5'b00010: n1865_o = 1'b1; + 5'b00001: n1865_o = 1'b0; + default: n1865_o = 1'b0; + endcase + /* T65_MCode.vhd:655:33 */ + always @* + case (n1844_o) + 5'b10000: n1869_o = 1'b0; + 5'b01000: n1869_o = 1'b1; + 5'b00100: n1869_o = 1'b0; + 5'b00010: n1869_o = 1'b0; + 5'b00001: n1869_o = 1'b0; + default: n1869_o = 1'b0; + endcase + /* T65_MCode.vhd:655:33 */ + always @* + case (n1844_o) + 5'b10000: n1873_o = 1'b0; + 5'b01000: n1873_o = 1'b1; + 5'b00100: n1873_o = 1'b1; + 5'b00010: n1873_o = 1'b0; + 5'b00001: n1873_o = 1'b0; + default: n1873_o = 1'b0; + endcase + /* T65_MCode.vhd:678:38 */ + assign n1874_o = ir[7:6]; + /* T65_MCode.vhd:678:51 */ + assign n1876_o = n1874_o != 2'b10; + /* T65_MCode.vhd:678:33 */ + assign n1878_o = n1876_o ? 1'b1 : n1022_o; + /* T65_MCode.vhd:681:38 */ + assign n1879_o = {28'b0, mcycle}; // uext + /* T65_MCode.vhd:682:33 */ + assign n1881_o = n1879_o == 31'b0000000000000000000000000000000; + /* T65_MCode.vhd:683:33 */ + assign n1883_o = n1879_o == 31'b0000000000000000000000000000001; + /* T65_MCode.vhd:689:46 */ + assign n1884_o = ir[7:5]; + /* T65_MCode.vhd:689:59 */ + assign n1886_o = n1884_o == 3'b100; + /* T65_MCode.vhd:689:41 */ + assign n1889_o = n1886_o ? 1'b1 : 1'b0; + /* T65_MCode.vhd:686:33 */ + assign n1891_o = n1879_o == 31'b0000000000000000000000000000010; + /* T65_MCode.vhd:693:33 */ + assign n1893_o = n1879_o == 31'b0000000000000000000000000000011; + assign n1894_o = {n1893_o, n1891_o, n1883_o, n1881_o}; + /* T65_MCode.vhd:681:33 */ + always @* + case (n1894_o) + 4'b1000: n1897_o = 2'b00; + 4'b0100: n1897_o = 2'b11; + 4'b0010: n1897_o = 2'b00; + 4'b0001: n1897_o = 2'b00; + default: n1897_o = 2'b00; + endcase + /* T65_MCode.vhd:681:33 */ + always @* + case (n1894_o) + 4'b1000: n1901_o = 2'b00; + 4'b0100: n1901_o = 2'b01; + 4'b0010: n1901_o = 2'b01; + 4'b0001: n1901_o = 2'b00; + default: n1901_o = 2'b00; + endcase + /* T65_MCode.vhd:681:33 */ + always @* + case (n1894_o) + 4'b1000: n1904_o = 1'b0; + 4'b0100: n1904_o = 1'b0; + 4'b0010: n1904_o = 1'b1; + 4'b0001: n1904_o = 1'b0; + default: n1904_o = 1'b0; + endcase + /* T65_MCode.vhd:681:33 */ + always @* + case (n1894_o) + 4'b1000: n1907_o = 1'b0; + 4'b0100: n1907_o = 1'b1; + 4'b0010: n1907_o = 1'b0; + 4'b0001: n1907_o = 1'b0; + default: n1907_o = 1'b0; + endcase + /* T65_MCode.vhd:681:33 */ + always @* + case (n1894_o) + 4'b1000: n1909_o = 1'b0; + 4'b0100: n1909_o = n1889_o; + 4'b0010: n1909_o = 1'b0; + 4'b0001: n1909_o = 1'b0; + default: n1909_o = 1'b0; + endcase + /* T65_MCode.vhd:652:25 */ + assign n1912_o = n1832_o ? 3'b101 : 3'b011; + /* T65_MCode.vhd:652:25 */ + assign n1913_o = n1832_o ? n1849_o : n1897_o; + /* T65_MCode.vhd:652:25 */ + assign n1914_o = n1832_o ? n1853_o : n1901_o; + /* T65_MCode.vhd:652:25 */ + assign n1915_o = n1832_o ? n1022_o : n1878_o; + /* T65_MCode.vhd:652:25 */ + assign n1917_o = n1832_o ? n1856_o : 1'b0; + /* T65_MCode.vhd:652:25 */ + assign n1919_o = n1832_o ? n1859_o : 1'b0; + /* T65_MCode.vhd:652:25 */ + assign n1920_o = n1832_o ? n1862_o : n1904_o; + /* T65_MCode.vhd:652:25 */ + assign n1921_o = n1832_o ? n1865_o : n1907_o; + /* T65_MCode.vhd:652:25 */ + assign n1923_o = n1832_o ? n1869_o : 1'b0; + /* T65_MCode.vhd:652:25 */ + assign n1924_o = n1832_o ? n1873_o : n1909_o; + /* T65_MCode.vhd:649:17 */ + assign n1926_o = n1039_o == 5'b01101; + /* T65_MCode.vhd:649:30 */ + assign n1928_o = n1039_o == 5'b01110; + /* T65_MCode.vhd:649:30 */ + assign n1929_o = n1926_o | n1928_o; + /* T65_MCode.vhd:649:40 */ + assign n1931_o = n1039_o == 5'b01111; + /* T65_MCode.vhd:649:40 */ + assign n1932_o = n1929_o | n1931_o; + /* T65_MCode.vhd:707:25 */ + assign n1935_o = branch ? 3'b011 : 3'b001; + /* T65_MCode.vhd:720:30 */ + assign n1936_o = {28'b0, mcycle}; // uext + /* T65_MCode.vhd:726:33 */ + assign n1938_o = n1936_o == 31'b0000000000000000000000000000001; + /* T65_MCode.vhd:740:33 */ + assign n1940_o = n1936_o == 31'b0000000000000000000000000000010; + /* T65_MCode.vhd:752:33 */ + assign n1942_o = n1936_o == 31'b0000000000000000000000000000011; + assign n1943_o = {n1942_o, n1940_o, n1938_o}; + /* T65_MCode.vhd:720:25 */ + always @* + case (n1943_o) + 3'b100: n1947_o = 2'b00; + 3'b010: n1947_o = 2'b11; + 3'b001: n1947_o = 2'b01; + default: n1947_o = 2'b00; + endcase + /* T65_MCode.vhd:720:25 */ + always @* + case (n1943_o) + 3'b100: n1950_o = 1'b0; + 3'b010: n1950_o = 1'b1; + 3'b001: n1950_o = 1'b0; + default: n1950_o = 1'b0; + endcase + /* T65_MCode.vhd:720:25 */ + always @* + case (n1943_o) + 3'b100: n1953_o = 1'b0; + 3'b010: n1953_o = 1'b0; + 3'b001: n1953_o = 1'b1; + default: n1953_o = 1'b0; + endcase + /* T65_MCode.vhd:699:17 */ + assign n1955_o = n1039_o == 5'b10000; + /* T65_MCode.vhd:764:30 */ + assign n1956_o = ir[7:6]; + /* T65_MCode.vhd:764:43 */ + assign n1958_o = n1956_o != 2'b10; + /* T65_MCode.vhd:764:25 */ + assign n1960_o = n1958_o ? 1'b1 : n1022_o; + /* T65_MCode.vhd:767:30 */ + assign n1961_o = {28'b0, mcycle}; // uext + /* T65_MCode.vhd:768:25 */ + assign n1963_o = n1961_o == 31'b0000000000000000000000000000000; + /* T65_MCode.vhd:769:25 */ + assign n1965_o = n1961_o == 31'b0000000000000000000000000000001; + /* T65_MCode.vhd:773:25 */ + assign n1967_o = n1961_o == 31'b0000000000000000000000000000010; + /* T65_MCode.vhd:777:25 */ + assign n1969_o = n1961_o == 31'b0000000000000000000000000000011; + /* T65_MCode.vhd:784:38 */ + assign n1970_o = ir[7:5]; + /* T65_MCode.vhd:784:51 */ + assign n1972_o = n1970_o == 3'b100; + /* T65_MCode.vhd:784:33 */ + assign n1975_o = n1972_o ? 1'b0 : 1'b1; + /* T65_MCode.vhd:784:33 */ + assign n1978_o = n1972_o ? 1'b1 : 1'b0; + /* T65_MCode.vhd:782:25 */ + assign n1980_o = n1961_o == 31'b0000000000000000000000000000100; + /* T65_MCode.vhd:790:25 */ + assign n1982_o = n1961_o == 31'b0000000000000000000000000000101; + assign n1983_o = {n1982_o, n1980_o, n1969_o, n1967_o, n1965_o, n1963_o}; + /* T65_MCode.vhd:767:25 */ + always @* + case (n1983_o) + 6'b100000: n1985_o = n1038_o; + 6'b010000: n1985_o = n1038_o; + 6'b001000: n1985_o = 3'b011; + 6'b000100: n1985_o = n1038_o; + 6'b000010: n1985_o = n1038_o; + 6'b000001: n1985_o = n1038_o; + default: n1985_o = n1038_o; + endcase + /* T65_MCode.vhd:767:25 */ + always @* + case (n1983_o) + 6'b100000: n1991_o = 2'b00; + 6'b010000: n1991_o = 2'b11; + 6'b001000: n1991_o = 2'b11; + 6'b000100: n1991_o = 2'b10; + 6'b000010: n1991_o = 2'b10; + 6'b000001: n1991_o = 2'b00; + default: n1991_o = 2'b00; + endcase + /* T65_MCode.vhd:767:25 */ + always @* + case (n1983_o) + 6'b100000: n1994_o = 2'b00; + 6'b010000: n1994_o = 2'b00; + 6'b001000: n1994_o = 2'b00; + 6'b000100: n1994_o = 2'b00; + 6'b000010: n1994_o = 2'b01; + 6'b000001: n1994_o = 2'b00; + default: n1994_o = 2'b00; + endcase + /* T65_MCode.vhd:767:25 */ + always @* + case (n1983_o) + 6'b100000: n1999_o = 2'b00; + 6'b010000: n1999_o = 2'b11; + 6'b001000: n1999_o = 2'b10; + 6'b000100: n1999_o = 2'b01; + 6'b000010: n1999_o = 2'b00; + 6'b000001: n1999_o = 2'b00; + default: n1999_o = 2'b00; + endcase + /* T65_MCode.vhd:767:25 */ + always @* + case (n1983_o) + 6'b100000: n2001_o = 1'b0; + 6'b010000: n2001_o = n1975_o; + 6'b001000: n2001_o = 1'b0; + 6'b000100: n2001_o = 1'b0; + 6'b000010: n2001_o = 1'b0; + 6'b000001: n2001_o = 1'b0; + default: n2001_o = 1'b0; + endcase + /* T65_MCode.vhd:767:25 */ + always @* + case (n1983_o) + 6'b100000: n2004_o = 1'b0; + 6'b010000: n2004_o = 1'b0; + 6'b001000: n2004_o = 1'b0; + 6'b000100: n2004_o = 1'b0; + 6'b000010: n2004_o = 1'b1; + 6'b000001: n2004_o = 1'b0; + default: n2004_o = 1'b0; + endcase + /* T65_MCode.vhd:767:25 */ + always @* + case (n1983_o) + 6'b100000: n2007_o = 1'b0; + 6'b010000: n2007_o = 1'b0; + 6'b001000: n2007_o = 1'b0; + 6'b000100: n2007_o = 1'b1; + 6'b000010: n2007_o = 1'b0; + 6'b000001: n2007_o = 1'b0; + default: n2007_o = 1'b0; + endcase + /* T65_MCode.vhd:767:25 */ + always @* + case (n1983_o) + 6'b100000: n2010_o = 1'b0; + 6'b010000: n2010_o = 1'b0; + 6'b001000: n2010_o = 1'b1; + 6'b000100: n2010_o = 1'b0; + 6'b000010: n2010_o = 1'b0; + 6'b000001: n2010_o = 1'b0; + default: n2010_o = 1'b0; + endcase + /* T65_MCode.vhd:767:25 */ + always @* + case (n1983_o) + 6'b100000: n2012_o = 1'b0; + 6'b010000: n2012_o = n1978_o; + 6'b001000: n2012_o = 1'b0; + 6'b000100: n2012_o = 1'b0; + 6'b000010: n2012_o = 1'b0; + 6'b000001: n2012_o = 1'b0; + default: n2012_o = 1'b0; + endcase + /* T65_MCode.vhd:760:17 */ + assign n2014_o = n1039_o == 5'b10001; + /* T65_MCode.vhd:760:30 */ + assign n2016_o = n1039_o == 5'b10011; + /* T65_MCode.vhd:760:30 */ + assign n2017_o = n2014_o | n2016_o; + /* T65_MCode.vhd:798:30 */ + assign n2018_o = ir[7:6]; + /* T65_MCode.vhd:798:43 */ + assign n2020_o = n2018_o != 2'b10; + /* T65_MCode.vhd:798:57 */ + assign n2021_o = ir[1:0]; + /* T65_MCode.vhd:798:70 */ + assign n2023_o = n2021_o == 2'b10; + /* T65_MCode.vhd:798:51 */ + assign n2024_o = n2020_o & n2023_o; + /* T65_MCode.vhd:801:38 */ + assign n2025_o = {28'b0, mcycle}; // uext + /* T65_MCode.vhd:802:33 */ + assign n2027_o = n2025_o == 31'b0000000000000000000000000000001; + /* T65_MCode.vhd:806:33 */ + assign n2029_o = n2025_o == 31'b0000000000000000000000000000010; + /* T65_MCode.vhd:809:33 */ + assign n2031_o = n2025_o == 31'b0000000000000000000000000000011; + /* T65_MCode.vhd:813:33 */ + assign n2033_o = n2025_o == 31'b0000000000000000000000000000100; + /* T65_MCode.vhd:818:33 */ + assign n2035_o = n2025_o == 31'b0000000000000000000000000000101; + assign n2036_o = {n2035_o, n2033_o, n2031_o, n2029_o, n2027_o}; + /* T65_MCode.vhd:801:33 */ + always @* + case (n2036_o) + 5'b10000: n2042_o = 2'b00; + 5'b01000: n2042_o = 2'b10; + 5'b00100: n2042_o = 2'b10; + 5'b00010: n2042_o = 2'b10; + 5'b00001: n2042_o = 2'b10; + default: n2042_o = 2'b00; + endcase + /* T65_MCode.vhd:801:33 */ + always @* + case (n2036_o) + 5'b10000: n2045_o = 2'b00; + 5'b01000: n2045_o = 2'b00; + 5'b00100: n2045_o = 2'b00; + 5'b00010: n2045_o = 2'b00; + 5'b00001: n2045_o = 2'b01; + default: n2045_o = 2'b00; + endcase + /* T65_MCode.vhd:801:33 */ + always @* + case (n2036_o) + 5'b10000: n2048_o = 1'b0; + 5'b01000: n2048_o = 1'b0; + 5'b00100: n2048_o = 1'b0; + 5'b00010: n2048_o = 1'b1; + 5'b00001: n2048_o = 1'b0; + default: n2048_o = 1'b0; + endcase + /* T65_MCode.vhd:801:33 */ + always @* + case (n2036_o) + 5'b10000: n2051_o = 1'b0; + 5'b01000: n2051_o = 1'b0; + 5'b00100: n2051_o = 1'b1; + 5'b00010: n2051_o = 1'b0; + 5'b00001: n2051_o = 1'b0; + default: n2051_o = 1'b0; + endcase + /* T65_MCode.vhd:801:33 */ + always @* + case (n2036_o) + 5'b10000: n2054_o = 1'b0; + 5'b01000: n2054_o = 1'b1; + 5'b00100: n2054_o = 1'b0; + 5'b00010: n2054_o = 1'b0; + 5'b00001: n2054_o = 1'b0; + default: n2054_o = 1'b0; + endcase + /* T65_MCode.vhd:801:33 */ + always @* + case (n2036_o) + 5'b10000: n2057_o = 1'b0; + 5'b01000: n2057_o = 1'b0; + 5'b00100: n2057_o = 1'b0; + 5'b00010: n2057_o = 1'b0; + 5'b00001: n2057_o = 1'b1; + default: n2057_o = 1'b0; + endcase + /* T65_MCode.vhd:801:33 */ + always @* + case (n2036_o) + 5'b10000: n2060_o = 1'b0; + 5'b01000: n2060_o = 1'b1; + 5'b00100: n2060_o = 1'b0; + 5'b00010: n2060_o = 1'b0; + 5'b00001: n2060_o = 1'b0; + default: n2060_o = 1'b0; + endcase + /* T65_MCode.vhd:801:33 */ + always @* + case (n2036_o) + 5'b10000: n2064_o = 1'b0; + 5'b01000: n2064_o = 1'b1; + 5'b00100: n2064_o = 1'b1; + 5'b00010: n2064_o = 1'b0; + 5'b00001: n2064_o = 1'b0; + default: n2064_o = 1'b0; + endcase + /* T65_MCode.vhd:823:38 */ + assign n2065_o = ir[7:6]; + /* T65_MCode.vhd:823:51 */ + assign n2067_o = n2065_o != 2'b10; + /* T65_MCode.vhd:823:33 */ + assign n2069_o = n2067_o ? 1'b1 : n1022_o; + /* T65_MCode.vhd:826:38 */ + assign n2070_o = {28'b0, mcycle}; // uext + /* T65_MCode.vhd:827:33 */ + assign n2072_o = n2070_o == 31'b0000000000000000000000000000000; + /* T65_MCode.vhd:828:33 */ + assign n2074_o = n2070_o == 31'b0000000000000000000000000000001; + /* T65_MCode.vhd:835:47 */ + assign n2075_o = ir[3:0]; + /* T65_MCode.vhd:835:60 */ + assign n2077_o = n2075_o == 4'b0110; + /* T65_MCode.vhd:835:41 */ + assign n2080_o = n2077_o ? 1'b1 : 1'b0; + /* T65_MCode.vhd:839:46 */ + assign n2081_o = ir[7:5]; + /* T65_MCode.vhd:839:59 */ + assign n2083_o = n2081_o == 3'b100; + /* T65_MCode.vhd:839:41 */ + assign n2086_o = n2083_o ? 1'b1 : 1'b0; + /* T65_MCode.vhd:832:33 */ + assign n2088_o = n2070_o == 31'b0000000000000000000000000000010; + /* T65_MCode.vhd:843:33 */ + assign n2090_o = n2070_o == 31'b0000000000000000000000000000011; + assign n2091_o = {n2090_o, n2088_o, n2074_o, n2072_o}; + /* T65_MCode.vhd:826:33 */ + always @* + case (n2091_o) + 4'b1000: n2095_o = 2'b00; + 4'b0100: n2095_o = 2'b10; + 4'b0010: n2095_o = 2'b10; + 4'b0001: n2095_o = 2'b00; + default: n2095_o = 2'b00; + endcase + /* T65_MCode.vhd:826:33 */ + always @* + case (n2091_o) + 4'b1000: n2098_o = 2'b00; + 4'b0100: n2098_o = 2'b00; + 4'b0010: n2098_o = 2'b01; + 4'b0001: n2098_o = 2'b00; + default: n2098_o = 2'b00; + endcase + /* T65_MCode.vhd:826:33 */ + always @* + case (n2091_o) + 4'b1000: n2101_o = 1'b0; + 4'b0100: n2101_o = 1'b1; + 4'b0010: n2101_o = 1'b0; + 4'b0001: n2101_o = 1'b0; + default: n2101_o = 1'b0; + endcase + /* T65_MCode.vhd:826:33 */ + always @* + case (n2091_o) + 4'b1000: n2103_o = 1'b0; + 4'b0100: n2103_o = n2080_o; + 4'b0010: n2103_o = 1'b0; + 4'b0001: n2103_o = 1'b0; + default: n2103_o = 1'b0; + endcase + /* T65_MCode.vhd:826:33 */ + always @* + case (n2091_o) + 4'b1000: n2106_o = 1'b0; + 4'b0100: n2106_o = 1'b0; + 4'b0010: n2106_o = 1'b1; + 4'b0001: n2106_o = 1'b0; + default: n2106_o = 1'b0; + endcase + /* T65_MCode.vhd:826:33 */ + always @* + case (n2091_o) + 4'b1000: n2108_o = 1'b0; + 4'b0100: n2108_o = n2086_o; + 4'b0010: n2108_o = 1'b0; + 4'b0001: n2108_o = 1'b0; + default: n2108_o = 1'b0; + endcase + /* T65_MCode.vhd:798:25 */ + assign n2111_o = n2024_o ? 3'b101 : 3'b011; + /* T65_MCode.vhd:798:25 */ + assign n2112_o = n2024_o ? n2042_o : n2095_o; + /* T65_MCode.vhd:798:25 */ + assign n2113_o = n2024_o ? n2045_o : n2098_o; + /* T65_MCode.vhd:798:25 */ + assign n2114_o = n2024_o ? n2048_o : n2101_o; + /* T65_MCode.vhd:798:25 */ + assign n2116_o = n2024_o ? 1'b0 : n2103_o; + /* T65_MCode.vhd:798:25 */ + assign n2117_o = n2024_o ? n1022_o : n2069_o; + /* T65_MCode.vhd:798:25 */ + assign n2119_o = n2024_o ? n2051_o : 1'b0; + /* T65_MCode.vhd:798:25 */ + assign n2121_o = n2024_o ? n2054_o : 1'b0; + /* T65_MCode.vhd:798:25 */ + assign n2122_o = n2024_o ? n2057_o : n2106_o; + /* T65_MCode.vhd:798:25 */ + assign n2124_o = n2024_o ? n2060_o : 1'b0; + /* T65_MCode.vhd:798:25 */ + assign n2125_o = n2024_o ? n2064_o : n2108_o; + /* T65_MCode.vhd:795:17 */ + assign n2127_o = n1039_o == 5'b10100; + /* T65_MCode.vhd:795:30 */ + assign n2129_o = n1039_o == 5'b10101; + /* T65_MCode.vhd:795:30 */ + assign n2130_o = n2127_o | n2129_o; + /* T65_MCode.vhd:795:40 */ + assign n2132_o = n1039_o == 5'b10110; + /* T65_MCode.vhd:795:40 */ + assign n2133_o = n2130_o | n2132_o; + /* T65_MCode.vhd:795:50 */ + assign n2135_o = n1039_o == 5'b10111; + /* T65_MCode.vhd:795:50 */ + assign n2136_o = n2133_o | n2135_o; + /* T65_MCode.vhd:853:30 */ + assign n2137_o = ir[7:6]; + /* T65_MCode.vhd:853:43 */ + assign n2139_o = n2137_o != 2'b10; + /* T65_MCode.vhd:853:25 */ + assign n2141_o = n2139_o ? 1'b1 : n1022_o; + /* T65_MCode.vhd:856:30 */ + assign n2142_o = {28'b0, mcycle}; // uext + /* T65_MCode.vhd:857:25 */ + assign n2144_o = n2142_o == 31'b0000000000000000000000000000000; + /* T65_MCode.vhd:858:25 */ + assign n2146_o = n2142_o == 31'b0000000000000000000000000000001; + /* T65_MCode.vhd:861:25 */ + assign n2148_o = n2142_o == 31'b0000000000000000000000000000010; + /* T65_MCode.vhd:869:38 */ + assign n2149_o = ir[7:5]; + /* T65_MCode.vhd:869:51 */ + assign n2151_o = n2149_o == 3'b100; + /* T65_MCode.vhd:869:33 */ + assign n2154_o = n2151_o ? 1'b0 : 1'b1; + /* T65_MCode.vhd:869:33 */ + assign n2157_o = n2151_o ? 1'b1 : 1'b0; + /* T65_MCode.vhd:867:25 */ + assign n2159_o = n2142_o == 31'b0000000000000000000000000000011; + /* T65_MCode.vhd:875:25 */ + assign n2161_o = n2142_o == 31'b0000000000000000000000000000100; + assign n2162_o = {n2161_o, n2159_o, n2148_o, n2146_o, n2144_o}; + /* T65_MCode.vhd:856:25 */ + always @* + case (n2162_o) + 5'b10000: n2164_o = n1038_o; + 5'b01000: n2164_o = n1038_o; + 5'b00100: n2164_o = 3'b011; + 5'b00010: n2164_o = n1038_o; + 5'b00001: n2164_o = n1038_o; + default: n2164_o = n1038_o; + endcase + /* T65_MCode.vhd:856:25 */ + always @* + case (n2162_o) + 5'b10000: n2168_o = 2'b00; + 5'b01000: n2168_o = 2'b11; + 5'b00100: n2168_o = 2'b11; + 5'b00010: n2168_o = 2'b00; + 5'b00001: n2168_o = 2'b00; + default: n2168_o = 2'b00; + endcase + /* T65_MCode.vhd:856:25 */ + always @* + case (n2162_o) + 5'b10000: n2172_o = 2'b00; + 5'b01000: n2172_o = 2'b00; + 5'b00100: n2172_o = 2'b01; + 5'b00010: n2172_o = 2'b01; + 5'b00001: n2172_o = 2'b00; + default: n2172_o = 2'b00; + endcase + /* T65_MCode.vhd:856:25 */ + always @* + case (n2162_o) + 5'b10000: n2176_o = 2'b00; + 5'b01000: n2176_o = 2'b11; + 5'b00100: n2176_o = 2'b10; + 5'b00010: n2176_o = 2'b00; + 5'b00001: n2176_o = 2'b00; + default: n2176_o = 2'b00; + endcase + /* T65_MCode.vhd:856:25 */ + always @* + case (n2162_o) + 5'b10000: n2178_o = 1'b0; + 5'b01000: n2178_o = n2154_o; + 5'b00100: n2178_o = 1'b0; + 5'b00010: n2178_o = 1'b0; + 5'b00001: n2178_o = 1'b0; + default: n2178_o = 1'b0; + endcase + /* T65_MCode.vhd:856:25 */ + always @* + case (n2162_o) + 5'b10000: n2181_o = 1'b0; + 5'b01000: n2181_o = 1'b0; + 5'b00100: n2181_o = 1'b0; + 5'b00010: n2181_o = 1'b1; + 5'b00001: n2181_o = 1'b0; + default: n2181_o = 1'b0; + endcase + /* T65_MCode.vhd:856:25 */ + always @* + case (n2162_o) + 5'b10000: n2184_o = 1'b0; + 5'b01000: n2184_o = 1'b0; + 5'b00100: n2184_o = 1'b1; + 5'b00010: n2184_o = 1'b0; + 5'b00001: n2184_o = 1'b0; + default: n2184_o = 1'b0; + endcase + /* T65_MCode.vhd:856:25 */ + always @* + case (n2162_o) + 5'b10000: n2186_o = 1'b0; + 5'b01000: n2186_o = n2157_o; + 5'b00100: n2186_o = 1'b0; + 5'b00010: n2186_o = 1'b0; + 5'b00001: n2186_o = 1'b0; + default: n2186_o = 1'b0; + endcase + /* T65_MCode.vhd:849:17 */ + assign n2188_o = n1039_o == 5'b11001; + /* T65_MCode.vhd:849:30 */ + assign n2190_o = n1039_o == 5'b11011; + /* T65_MCode.vhd:849:30 */ + assign n2191_o = n2188_o | n2190_o; + /* T65_MCode.vhd:884:30 */ + assign n2192_o = ir[7:6]; + /* T65_MCode.vhd:884:43 */ + assign n2194_o = n2192_o != 2'b10; + /* T65_MCode.vhd:884:57 */ + assign n2195_o = ir[1:0]; + /* T65_MCode.vhd:884:70 */ + assign n2197_o = n2195_o == 2'b10; + /* T65_MCode.vhd:884:51 */ + assign n2198_o = n2194_o & n2197_o; + /* T65_MCode.vhd:887:38 */ + assign n2199_o = {28'b0, mcycle}; // uext + /* T65_MCode.vhd:888:33 */ + assign n2201_o = n2199_o == 31'b0000000000000000000000000000001; + /* T65_MCode.vhd:891:33 */ + assign n2203_o = n2199_o == 31'b0000000000000000000000000000010; + /* T65_MCode.vhd:897:33 */ + assign n2205_o = n2199_o == 31'b0000000000000000000000000000011; + /* T65_MCode.vhd:900:33 */ + assign n2207_o = n2199_o == 31'b0000000000000000000000000000100; + /* T65_MCode.vhd:904:33 */ + assign n2209_o = n2199_o == 31'b0000000000000000000000000000101; + /* T65_MCode.vhd:909:33 */ + assign n2211_o = n2199_o == 31'b0000000000000000000000000000110; + assign n2212_o = {n2211_o, n2209_o, n2207_o, n2205_o, n2203_o, n2201_o}; + /* T65_MCode.vhd:887:33 */ + always @* + case (n2212_o) + 6'b100000: n2214_o = n1038_o; + 6'b010000: n2214_o = n1038_o; + 6'b001000: n2214_o = n1038_o; + 6'b000100: n2214_o = n1038_o; + 6'b000010: n2214_o = 3'b010; + 6'b000001: n2214_o = n1038_o; + default: n2214_o = n1038_o; + endcase + /* T65_MCode.vhd:887:33 */ + always @* + case (n2212_o) + 6'b100000: n2220_o = 2'b00; + 6'b010000: n2220_o = 2'b11; + 6'b001000: n2220_o = 2'b11; + 6'b000100: n2220_o = 2'b11; + 6'b000010: n2220_o = 2'b11; + 6'b000001: n2220_o = 2'b00; + default: n2220_o = 2'b00; + endcase + /* T65_MCode.vhd:887:33 */ + always @* + case (n2212_o) + 6'b100000: n2224_o = 2'b00; + 6'b010000: n2224_o = 2'b00; + 6'b001000: n2224_o = 2'b00; + 6'b000100: n2224_o = 2'b00; + 6'b000010: n2224_o = 2'b01; + 6'b000001: n2224_o = 2'b01; + default: n2224_o = 2'b00; + endcase + /* T65_MCode.vhd:887:33 */ + always @* + case (n2212_o) + 6'b100000: n2228_o = 2'b00; + 6'b010000: n2228_o = 2'b00; + 6'b001000: n2228_o = 2'b00; + 6'b000100: n2228_o = 2'b11; + 6'b000010: n2228_o = 2'b10; + 6'b000001: n2228_o = 2'b00; + default: n2228_o = 2'b00; + endcase + /* T65_MCode.vhd:887:33 */ + always @* + case (n2212_o) + 6'b100000: n2231_o = 1'b0; + 6'b010000: n2231_o = 1'b0; + 6'b001000: n2231_o = 1'b1; + 6'b000100: n2231_o = 1'b0; + 6'b000010: n2231_o = 1'b0; + 6'b000001: n2231_o = 1'b0; + default: n2231_o = 1'b0; + endcase + /* T65_MCode.vhd:887:33 */ + always @* + case (n2212_o) + 6'b100000: n2234_o = 1'b0; + 6'b010000: n2234_o = 1'b1; + 6'b001000: n2234_o = 1'b0; + 6'b000100: n2234_o = 1'b0; + 6'b000010: n2234_o = 1'b0; + 6'b000001: n2234_o = 1'b0; + default: n2234_o = 1'b0; + endcase + /* T65_MCode.vhd:887:33 */ + always @* + case (n2212_o) + 6'b100000: n2237_o = 1'b0; + 6'b010000: n2237_o = 1'b0; + 6'b001000: n2237_o = 1'b0; + 6'b000100: n2237_o = 1'b0; + 6'b000010: n2237_o = 1'b0; + 6'b000001: n2237_o = 1'b1; + default: n2237_o = 1'b0; + endcase + /* T65_MCode.vhd:887:33 */ + always @* + case (n2212_o) + 6'b100000: n2240_o = 1'b0; + 6'b010000: n2240_o = 1'b0; + 6'b001000: n2240_o = 1'b0; + 6'b000100: n2240_o = 1'b0; + 6'b000010: n2240_o = 1'b1; + 6'b000001: n2240_o = 1'b0; + default: n2240_o = 1'b0; + endcase + /* T65_MCode.vhd:887:33 */ + always @* + case (n2212_o) + 6'b100000: n2243_o = 1'b0; + 6'b010000: n2243_o = 1'b1; + 6'b001000: n2243_o = 1'b0; + 6'b000100: n2243_o = 1'b0; + 6'b000010: n2243_o = 1'b0; + 6'b000001: n2243_o = 1'b0; + default: n2243_o = 1'b0; + endcase + /* T65_MCode.vhd:887:33 */ + always @* + case (n2212_o) + 6'b100000: n2247_o = 1'b0; + 6'b010000: n2247_o = 1'b1; + 6'b001000: n2247_o = 1'b1; + 6'b000100: n2247_o = 1'b0; + 6'b000010: n2247_o = 1'b0; + 6'b000001: n2247_o = 1'b0; + default: n2247_o = 1'b0; + endcase + /* T65_MCode.vhd:914:38 */ + assign n2248_o = ir[7:6]; + /* T65_MCode.vhd:914:51 */ + assign n2250_o = n2248_o != 2'b10; + /* T65_MCode.vhd:914:33 */ + assign n2252_o = n2250_o ? 1'b1 : n1022_o; + /* T65_MCode.vhd:917:38 */ + assign n2253_o = {28'b0, mcycle}; // uext + /* T65_MCode.vhd:918:33 */ + assign n2255_o = n2253_o == 31'b0000000000000000000000000000000; + /* T65_MCode.vhd:919:33 */ + assign n2257_o = n2253_o == 31'b0000000000000000000000000000001; + /* T65_MCode.vhd:926:48 */ + assign n2259_o = ir == 8'b10111110; + /* T65_MCode.vhd:926:41 */ + assign n2262_o = n2259_o ? 3'b011 : 3'b010; + /* T65_MCode.vhd:922:33 */ + assign n2264_o = n2253_o == 31'b0000000000000000000000000000010; + /* T65_MCode.vhd:936:46 */ + assign n2265_o = ir[7:5]; + /* T65_MCode.vhd:936:59 */ + assign n2267_o = n2265_o == 3'b100; + /* T65_MCode.vhd:936:41 */ + assign n2270_o = n2267_o ? 1'b0 : 1'b1; + /* T65_MCode.vhd:936:41 */ + assign n2273_o = n2267_o ? 1'b1 : 1'b0; + /* T65_MCode.vhd:934:33 */ + assign n2275_o = n2253_o == 31'b0000000000000000000000000000011; + /* T65_MCode.vhd:942:33 */ + assign n2277_o = n2253_o == 31'b0000000000000000000000000000100; + assign n2278_o = {n2277_o, n2275_o, n2264_o, n2257_o, n2255_o}; + /* T65_MCode.vhd:917:33 */ + always @* + case (n2278_o) + 5'b10000: n2279_o = n1038_o; + 5'b01000: n2279_o = n1038_o; + 5'b00100: n2279_o = n2262_o; + 5'b00010: n2279_o = n1038_o; + 5'b00001: n2279_o = n1038_o; + default: n2279_o = n1038_o; + endcase + /* T65_MCode.vhd:917:33 */ + always @* + case (n2278_o) + 5'b10000: n2283_o = 2'b00; + 5'b01000: n2283_o = 2'b11; + 5'b00100: n2283_o = 2'b11; + 5'b00010: n2283_o = 2'b00; + 5'b00001: n2283_o = 2'b00; + default: n2283_o = 2'b00; + endcase + /* T65_MCode.vhd:917:33 */ + always @* + case (n2278_o) + 5'b10000: n2287_o = 2'b00; + 5'b01000: n2287_o = 2'b00; + 5'b00100: n2287_o = 2'b01; + 5'b00010: n2287_o = 2'b01; + 5'b00001: n2287_o = 2'b00; + default: n2287_o = 2'b00; + endcase + /* T65_MCode.vhd:917:33 */ + always @* + case (n2278_o) + 5'b10000: n2291_o = 2'b00; + 5'b01000: n2291_o = 2'b11; + 5'b00100: n2291_o = 2'b10; + 5'b00010: n2291_o = 2'b00; + 5'b00001: n2291_o = 2'b00; + default: n2291_o = 2'b00; + endcase + /* T65_MCode.vhd:917:33 */ + always @* + case (n2278_o) + 5'b10000: n2293_o = 1'b0; + 5'b01000: n2293_o = n2270_o; + 5'b00100: n2293_o = 1'b0; + 5'b00010: n2293_o = 1'b0; + 5'b00001: n2293_o = 1'b0; + default: n2293_o = 1'b0; + endcase + /* T65_MCode.vhd:917:33 */ + always @* + case (n2278_o) + 5'b10000: n2296_o = 1'b0; + 5'b01000: n2296_o = 1'b0; + 5'b00100: n2296_o = 1'b0; + 5'b00010: n2296_o = 1'b1; + 5'b00001: n2296_o = 1'b0; + default: n2296_o = 1'b0; + endcase + /* T65_MCode.vhd:917:33 */ + always @* + case (n2278_o) + 5'b10000: n2299_o = 1'b0; + 5'b01000: n2299_o = 1'b0; + 5'b00100: n2299_o = 1'b1; + 5'b00010: n2299_o = 1'b0; + 5'b00001: n2299_o = 1'b0; + default: n2299_o = 1'b0; + endcase + /* T65_MCode.vhd:917:33 */ + always @* + case (n2278_o) + 5'b10000: n2301_o = 1'b0; + 5'b01000: n2301_o = n2273_o; + 5'b00100: n2301_o = 1'b0; + 5'b00010: n2301_o = 1'b0; + 5'b00001: n2301_o = 1'b0; + default: n2301_o = 1'b0; + endcase + /* T65_MCode.vhd:884:25 */ + assign n2304_o = n2198_o ? 3'b110 : 3'b100; + /* T65_MCode.vhd:884:25 */ + assign n2305_o = n2198_o ? n2214_o : n2279_o; + /* T65_MCode.vhd:884:25 */ + assign n2306_o = n2198_o ? n2220_o : n2283_o; + /* T65_MCode.vhd:884:25 */ + assign n2307_o = n2198_o ? n2224_o : n2287_o; + /* T65_MCode.vhd:884:25 */ + assign n2308_o = n2198_o ? n2228_o : n2291_o; + /* T65_MCode.vhd:884:25 */ + assign n2310_o = n2198_o ? 1'b0 : n2293_o; + /* T65_MCode.vhd:884:25 */ + assign n2311_o = n2198_o ? n1022_o : n2252_o; + /* T65_MCode.vhd:884:25 */ + assign n2313_o = n2198_o ? n2231_o : 1'b0; + /* T65_MCode.vhd:884:25 */ + assign n2315_o = n2198_o ? n2234_o : 1'b0; + /* T65_MCode.vhd:884:25 */ + assign n2316_o = n2198_o ? n2237_o : n2296_o; + /* T65_MCode.vhd:884:25 */ + assign n2317_o = n2198_o ? n2240_o : n2299_o; + /* T65_MCode.vhd:884:25 */ + assign n2319_o = n2198_o ? n2243_o : 1'b0; + /* T65_MCode.vhd:884:25 */ + assign n2320_o = n2198_o ? n2247_o : n2301_o; + /* T65_MCode.vhd:880:17 */ + assign n2322_o = n1039_o == 5'b11100; + /* T65_MCode.vhd:880:30 */ + assign n2324_o = n1039_o == 5'b11101; + /* T65_MCode.vhd:880:30 */ + assign n2325_o = n2322_o | n2324_o; + /* T65_MCode.vhd:880:40 */ + assign n2327_o = n1039_o == 5'b11110; + /* T65_MCode.vhd:880:40 */ + assign n2328_o = n2325_o | n2327_o; + /* T65_MCode.vhd:880:50 */ + assign n2330_o = n1039_o == 5'b11111; + /* T65_MCode.vhd:880:50 */ + assign n2331_o = n2328_o | n2330_o; + assign n2332_o = {n2331_o, n2191_o, n2136_o, n2017_o, n1955_o, n1932_o, n1825_o, n1686_o, n1593_o, n1558_o, n1540_o, n1526_o, n1470_o}; + /* T65_MCode.vhd:206:17 */ + always @* + case (n2332_o) + 13'b1000000000000: n2338_o = n2304_o; + 13'b0100000000000: n2338_o = 3'b100; + 13'b0010000000000: n2338_o = n2111_o; + 13'b0001000000000: n2338_o = 3'b101; + 13'b0000100000000: n2338_o = n1935_o; + 13'b0000010000000: n2338_o = n1912_o; + 13'b0000001000000: n2338_o = n1811_o; + 13'b0000000100000: n2338_o = n1667_o; + 13'b0000000010000: n2338_o = 3'b010; + 13'b0000000001000: n2338_o = 3'b001; + 13'b0000000000100: n2338_o = 3'b001; + 13'b0000000000010: n2338_o = 3'b101; + 13'b0000000000001: n2338_o = n1427_o; + default: n2338_o = 3'b001; + endcase + /* T65_MCode.vhd:206:17 */ + always @* + case (n2332_o) + 13'b1000000000000: n2340_o = n2305_o; + 13'b0100000000000: n2340_o = n2164_o; + 13'b0010000000000: n2340_o = n1038_o; + 13'b0001000000000: n2340_o = n1985_o; + 13'b0000100000000: n2340_o = n1038_o; + 13'b0000010000000: n2340_o = n1038_o; + 13'b0000001000000: n2340_o = n1038_o; + 13'b0000000100000: n2340_o = n1038_o; + 13'b0000000010000: n2340_o = n1038_o; + 13'b0000000001000: n2340_o = n1038_o; + 13'b0000000000100: n2340_o = n1038_o; + 13'b0000000000010: n2340_o = n1038_o; + 13'b0000000000001: n2340_o = n1429_o; + default: n2340_o = n1038_o; + endcase + /* T65_MCode.vhd:206:17 */ + always @* + case (n2332_o) + 13'b1000000000000: n2342_o = n2306_o; + 13'b0100000000000: n2342_o = n2168_o; + 13'b0010000000000: n2342_o = n2112_o; + 13'b0001000000000: n2342_o = n1991_o; + 13'b0000100000000: n2342_o = 2'b00; + 13'b0000010000000: n2342_o = n1913_o; + 13'b0000001000000: n2342_o = n1812_o; + 13'b0000000100000: n2342_o = n1668_o; + 13'b0000000010000: n2342_o = n1581_o; + 13'b0000000001000: n2342_o = 2'b00; + 13'b0000000000100: n2342_o = 2'b00; + 13'b0000000000010: n2342_o = n1501_o; + 13'b0000000000001: n2342_o = n1431_o; + default: n2342_o = 2'b00; + endcase + /* T65_MCode.vhd:206:17 */ + always @* + case (n2332_o) + 13'b1000000000000: n2344_o = n1019_o; + 13'b0100000000000: n2344_o = n1019_o; + 13'b0010000000000: n2344_o = n1019_o; + 13'b0001000000000: n2344_o = n1019_o; + 13'b0000100000000: n2344_o = n1019_o; + 13'b0000010000000: n2344_o = n1019_o; + 13'b0000001000000: n2344_o = n1019_o; + 13'b0000000100000: n2344_o = n1019_o; + 13'b0000000010000: n2344_o = n1019_o; + 13'b0000000001000: n2344_o = n1019_o; + 13'b0000000000100: n2344_o = n1019_o; + 13'b0000000000010: n2344_o = n1019_o; + 13'b0000000000001: n2344_o = n1432_o; + default: n2344_o = n1019_o; + endcase + /* T65_MCode.vhd:206:17 */ + always @* + case (n2332_o) + 13'b1000000000000: n2346_o = n2307_o; + 13'b0100000000000: n2346_o = n2172_o; + 13'b0010000000000: n2346_o = n2113_o; + 13'b0001000000000: n2346_o = n1994_o; + 13'b0000100000000: n2346_o = n1947_o; + 13'b0000010000000: n2346_o = n1914_o; + 13'b0000001000000: n2346_o = n1813_o; + 13'b0000000100000: n2346_o = n1669_o; + 13'b0000000010000: n2346_o = n1584_o; + 13'b0000000001000: n2346_o = n1553_o; + 13'b0000000000100: n2346_o = n1535_o; + 13'b0000000000010: n2346_o = n1504_o; + 13'b0000000000001: n2346_o = n1434_o; + default: n2346_o = 2'b00; + endcase + /* T65_MCode.vhd:206:17 */ + always @* + case (n2332_o) + 13'b1000000000000: n2349_o = n2308_o; + 13'b0100000000000: n2349_o = n2176_o; + 13'b0010000000000: n2349_o = 2'b00; + 13'b0001000000000: n2349_o = n1999_o; + 13'b0000100000000: n2349_o = 2'b00; + 13'b0000010000000: n2349_o = 2'b00; + 13'b0000001000000: n2349_o = n1815_o; + 13'b0000000100000: n2349_o = 2'b00; + 13'b0000000010000: n2349_o = 2'b00; + 13'b0000000001000: n2349_o = 2'b00; + 13'b0000000000100: n2349_o = 2'b00; + 13'b0000000000010: n2349_o = n1507_o; + 13'b0000000000001: n2349_o = 2'b00; + default: n2349_o = 2'b00; + endcase + /* T65_MCode.vhd:206:17 */ + always @* + case (n2332_o) + 13'b1000000000000: n2352_o = n2310_o; + 13'b0100000000000: n2352_o = n2178_o; + 13'b0010000000000: n2352_o = 1'b0; + 13'b0001000000000: n2352_o = n2001_o; + 13'b0000100000000: n2352_o = 1'b0; + 13'b0000010000000: n2352_o = 1'b0; + 13'b0000001000000: n2352_o = 1'b0; + 13'b0000000100000: n2352_o = 1'b0; + 13'b0000000010000: n2352_o = 1'b0; + 13'b0000000001000: n2352_o = 1'b0; + 13'b0000000000100: n2352_o = 1'b0; + 13'b0000000000010: n2352_o = 1'b0; + 13'b0000000000001: n2352_o = 1'b0; + default: n2352_o = 1'b0; + endcase + /* T65_MCode.vhd:206:17 */ + always @* + case (n2332_o) + 13'b1000000000000: n2355_o = 1'b0; + 13'b0100000000000: n2355_o = 1'b0; + 13'b0010000000000: n2355_o = n2114_o; + 13'b0001000000000: n2355_o = 1'b0; + 13'b0000100000000: n2355_o = 1'b0; + 13'b0000010000000: n2355_o = 1'b0; + 13'b0000001000000: n2355_o = 1'b0; + 13'b0000000100000: n2355_o = 1'b0; + 13'b0000000010000: n2355_o = 1'b0; + 13'b0000000001000: n2355_o = 1'b0; + 13'b0000000000100: n2355_o = 1'b0; + 13'b0000000000010: n2355_o = n1510_o; + 13'b0000000000001: n2355_o = 1'b0; + default: n2355_o = 1'b0; + endcase + /* T65_MCode.vhd:206:17 */ + always @* + case (n2332_o) + 13'b1000000000000: n2358_o = 1'b0; + 13'b0100000000000: n2358_o = 1'b0; + 13'b0010000000000: n2358_o = n2116_o; + 13'b0001000000000: n2358_o = 1'b0; + 13'b0000100000000: n2358_o = 1'b0; + 13'b0000010000000: n2358_o = 1'b0; + 13'b0000001000000: n2358_o = 1'b0; + 13'b0000000100000: n2358_o = 1'b0; + 13'b0000000010000: n2358_o = 1'b0; + 13'b0000000001000: n2358_o = 1'b0; + 13'b0000000000100: n2358_o = 1'b0; + 13'b0000000000010: n2358_o = 1'b0; + 13'b0000000000001: n2358_o = 1'b0; + default: n2358_o = 1'b0; + endcase + /* T65_MCode.vhd:206:17 */ + always @* + case (n2332_o) + 13'b1000000000000: n2361_o = 1'b0; + 13'b0100000000000: n2361_o = 1'b0; + 13'b0010000000000: n2361_o = 1'b0; + 13'b0001000000000: n2361_o = 1'b0; + 13'b0000100000000: n2361_o = n1950_o; + 13'b0000010000000: n2361_o = 1'b0; + 13'b0000001000000: n2361_o = 1'b0; + 13'b0000000100000: n2361_o = 1'b0; + 13'b0000000010000: n2361_o = 1'b0; + 13'b0000000001000: n2361_o = 1'b0; + 13'b0000000000100: n2361_o = 1'b0; + 13'b0000000000010: n2361_o = 1'b0; + 13'b0000000000001: n2361_o = 1'b0; + default: n2361_o = 1'b0; + endcase + /* T65_MCode.vhd:206:17 */ + always @* + case (n2332_o) + 13'b1000000000000: n2364_o = 1'b0; + 13'b0100000000000: n2364_o = 1'b0; + 13'b0010000000000: n2364_o = 1'b0; + 13'b0001000000000: n2364_o = 1'b0; + 13'b0000100000000: n2364_o = 1'b0; + 13'b0000010000000: n2364_o = 1'b0; + 13'b0000001000000: n2364_o = 1'b0; + 13'b0000000100000: n2364_o = 1'b0; + 13'b0000000010000: n2364_o = 1'b0; + 13'b0000000001000: n2364_o = 1'b0; + 13'b0000000000100: n2364_o = 1'b0; + 13'b0000000000010: n2364_o = 1'b0; + 13'b0000000000001: n2364_o = n1436_o; + default: n2364_o = 1'b0; + endcase + /* T65_MCode.vhd:206:17 */ + always @* + case (n2332_o) + 13'b1000000000000: n2367_o = 1'b0; + 13'b0100000000000: n2367_o = 1'b0; + 13'b0010000000000: n2367_o = 1'b0; + 13'b0001000000000: n2367_o = 1'b0; + 13'b0000100000000: n2367_o = 1'b0; + 13'b0000010000000: n2367_o = 1'b0; + 13'b0000001000000: n2367_o = 1'b0; + 13'b0000000100000: n2367_o = 1'b0; + 13'b0000000010000: n2367_o = 1'b0; + 13'b0000000001000: n2367_o = 1'b0; + 13'b0000000000100: n2367_o = 1'b0; + 13'b0000000000010: n2367_o = 1'b0; + 13'b0000000000001: n2367_o = n1438_o; + default: n2367_o = 1'b0; + endcase + /* T65_MCode.vhd:206:17 */ + always @* + case (n2332_o) + 13'b1000000000000: n2370_o = n2311_o; + 13'b0100000000000: n2370_o = n2141_o; + 13'b0010000000000: n2370_o = n2117_o; + 13'b0001000000000: n2370_o = n1960_o; + 13'b0000100000000: n2370_o = n1022_o; + 13'b0000010000000: n2370_o = n1915_o; + 13'b0000001000000: n2370_o = n1022_o; + 13'b0000000100000: n2370_o = n1670_o; + 13'b0000000010000: n2370_o = n1022_o; + 13'b0000000001000: n2370_o = n1022_o; + 13'b0000000000100: n2370_o = 1'b1; + 13'b0000000000010: n2370_o = n1475_o; + 13'b0000000000001: n2370_o = n1441_o; + default: n2370_o = n1022_o; + endcase + /* T65_MCode.vhd:206:17 */ + always @* + case (n2332_o) + 13'b1000000000000: n2372_o = 1'b0; + 13'b0100000000000: n2372_o = 1'b0; + 13'b0010000000000: n2372_o = 1'b0; + 13'b0001000000000: n2372_o = 1'b0; + 13'b0000100000000: n2372_o = 1'b0; + 13'b0000010000000: n2372_o = 1'b0; + 13'b0000001000000: n2372_o = 1'b0; + 13'b0000000100000: n2372_o = 1'b0; + 13'b0000000010000: n2372_o = 1'b0; + 13'b0000000001000: n2372_o = 1'b0; + 13'b0000000000100: n2372_o = 1'b0; + 13'b0000000000010: n2372_o = 1'b0; + 13'b0000000000001: n2372_o = n1443_o; + default: n2372_o = 1'b0; + endcase + /* T65_MCode.vhd:206:17 */ + always @* + case (n2332_o) + 13'b1000000000000: n2375_o = n1025_o; + 13'b0100000000000: n2375_o = n1025_o; + 13'b0010000000000: n2375_o = n1025_o; + 13'b0001000000000: n2375_o = n1025_o; + 13'b0000100000000: n2375_o = n1025_o; + 13'b0000010000000: n2375_o = n1025_o; + 13'b0000001000000: n2375_o = n1025_o; + 13'b0000000100000: n2375_o = n1025_o; + 13'b0000000010000: n2375_o = n1025_o; + 13'b0000000001000: n2375_o = 1'b1; + 13'b0000000000100: n2375_o = n1025_o; + 13'b0000000000010: n2375_o = n1025_o; + 13'b0000000000001: n2375_o = n1446_o; + default: n2375_o = n1025_o; + endcase + /* T65_MCode.vhd:206:17 */ + always @* + case (n2332_o) + 13'b1000000000000: n2376_o = n1028_o; + 13'b0100000000000: n2376_o = n1028_o; + 13'b0010000000000: n2376_o = n1028_o; + 13'b0001000000000: n2376_o = n1028_o; + 13'b0000100000000: n2376_o = n1028_o; + 13'b0000010000000: n2376_o = n1028_o; + 13'b0000001000000: n2376_o = n1028_o; + 13'b0000000100000: n2376_o = n1028_o; + 13'b0000000010000: n2376_o = n1028_o; + 13'b0000000001000: n2376_o = n1028_o; + 13'b0000000000100: n2376_o = n1028_o; + 13'b0000000000010: n2376_o = n1028_o; + 13'b0000000000001: n2376_o = n1448_o; + default: n2376_o = n1028_o; + endcase + /* T65_MCode.vhd:206:17 */ + always @* + case (n2332_o) + 13'b1000000000000: n2378_o = 1'b0; + 13'b0100000000000: n2378_o = 1'b0; + 13'b0010000000000: n2378_o = 1'b0; + 13'b0001000000000: n2378_o = 1'b0; + 13'b0000100000000: n2378_o = 1'b0; + 13'b0000010000000: n2378_o = 1'b0; + 13'b0000001000000: n2378_o = 1'b0; + 13'b0000000100000: n2378_o = 1'b0; + 13'b0000000010000: n2378_o = 1'b0; + 13'b0000000001000: n2378_o = 1'b0; + 13'b0000000000100: n2378_o = 1'b0; + 13'b0000000000010: n2378_o = 1'b0; + 13'b0000000000001: n2378_o = n1450_o; + default: n2378_o = 1'b0; + endcase + /* T65_MCode.vhd:206:17 */ + always @* + case (n2332_o) + 13'b1000000000000: n2381_o = n2313_o; + 13'b0100000000000: n2381_o = 1'b0; + 13'b0010000000000: n2381_o = n2119_o; + 13'b0001000000000: n2381_o = 1'b0; + 13'b0000100000000: n2381_o = n1953_o; + 13'b0000010000000: n2381_o = n1917_o; + 13'b0000001000000: n2381_o = n1817_o; + 13'b0000000100000: n2381_o = n1672_o; + 13'b0000000010000: n2381_o = 1'b0; + 13'b0000000001000: n2381_o = 1'b0; + 13'b0000000000100: n2381_o = 1'b0; + 13'b0000000000010: n2381_o = 1'b0; + 13'b0000000000001: n2381_o = n1452_o; + default: n2381_o = 1'b0; + endcase + /* T65_MCode.vhd:206:17 */ + always @* + case (n2332_o) + 13'b1000000000000: n2384_o = n2315_o; + 13'b0100000000000: n2384_o = 1'b0; + 13'b0010000000000: n2384_o = n2121_o; + 13'b0001000000000: n2384_o = 1'b0; + 13'b0000100000000: n2384_o = 1'b0; + 13'b0000010000000: n2384_o = n1919_o; + 13'b0000001000000: n2384_o = 1'b0; + 13'b0000000100000: n2384_o = n1674_o; + 13'b0000000010000: n2384_o = 1'b0; + 13'b0000000001000: n2384_o = 1'b0; + 13'b0000000000100: n2384_o = 1'b0; + 13'b0000000000010: n2384_o = 1'b0; + 13'b0000000000001: n2384_o = 1'b0; + default: n2384_o = 1'b0; + endcase + /* T65_MCode.vhd:206:17 */ + always @* + case (n2332_o) + 13'b1000000000000: n2387_o = 1'b0; + 13'b0100000000000: n2387_o = 1'b0; + 13'b0010000000000: n2387_o = n2122_o; + 13'b0001000000000: n2387_o = n2004_o; + 13'b0000100000000: n2387_o = 1'b0; + 13'b0000010000000: n2387_o = 1'b0; + 13'b0000001000000: n2387_o = 1'b0; + 13'b0000000100000: n2387_o = n1675_o; + 13'b0000000010000: n2387_o = n1587_o; + 13'b0000000001000: n2387_o = 1'b0; + 13'b0000000000100: n2387_o = 1'b0; + 13'b0000000000010: n2387_o = n1513_o; + 13'b0000000000001: n2387_o = 1'b0; + default: n2387_o = 1'b0; + endcase + /* T65_MCode.vhd:206:17 */ + always @* + case (n2332_o) + 13'b1000000000000: n2390_o = n2316_o; + 13'b0100000000000: n2390_o = n2181_o; + 13'b0010000000000: n2390_o = 1'b0; + 13'b0001000000000: n2390_o = n2007_o; + 13'b0000100000000: n2390_o = 1'b0; + 13'b0000010000000: n2390_o = n1920_o; + 13'b0000001000000: n2390_o = n1818_o; + 13'b0000000100000: n2390_o = 1'b0; + 13'b0000000010000: n2390_o = 1'b0; + 13'b0000000001000: n2390_o = 1'b0; + 13'b0000000000100: n2390_o = 1'b0; + 13'b0000000000010: n2390_o = n1516_o; + 13'b0000000000001: n2390_o = 1'b0; + default: n2390_o = 1'b0; + endcase + /* T65_MCode.vhd:206:17 */ + always @* + case (n2332_o) + 13'b1000000000000: n2393_o = n2317_o; + 13'b0100000000000: n2393_o = n2184_o; + 13'b0010000000000: n2393_o = 1'b0; + 13'b0001000000000: n2393_o = n2010_o; + 13'b0000100000000: n2393_o = 1'b0; + 13'b0000010000000: n2393_o = n1921_o; + 13'b0000001000000: n2393_o = n1819_o; + 13'b0000000100000: n2393_o = 1'b0; + 13'b0000000010000: n2393_o = 1'b0; + 13'b0000000001000: n2393_o = 1'b0; + 13'b0000000000100: n2393_o = 1'b0; + 13'b0000000000010: n2393_o = n1519_o; + 13'b0000000000001: n2393_o = 1'b0; + default: n2393_o = 1'b0; + endcase + /* T65_MCode.vhd:206:17 */ + always @* + case (n2332_o) + 13'b1000000000000: n2396_o = n2319_o; + 13'b0100000000000: n2396_o = 1'b0; + 13'b0010000000000: n2396_o = n2124_o; + 13'b0001000000000: n2396_o = 1'b0; + 13'b0000100000000: n2396_o = 1'b0; + 13'b0000010000000: n2396_o = n1923_o; + 13'b0000001000000: n2396_o = n1821_o; + 13'b0000000100000: n2396_o = n1677_o; + 13'b0000000010000: n2396_o = n1589_o; + 13'b0000000001000: n2396_o = 1'b0; + 13'b0000000000100: n2396_o = 1'b0; + 13'b0000000000010: n2396_o = 1'b0; + 13'b0000000000001: n2396_o = n1454_o; + default: n2396_o = 1'b0; + endcase + /* T65_MCode.vhd:206:17 */ + always @* + case (n2332_o) + 13'b1000000000000: n2399_o = n2320_o; + 13'b0100000000000: n2399_o = n2186_o; + 13'b0010000000000: n2399_o = n2125_o; + 13'b0001000000000: n2399_o = n2012_o; + 13'b0000100000000: n2399_o = 1'b0; + 13'b0000010000000: n2399_o = n1924_o; + 13'b0000001000000: n2399_o = n1823_o; + 13'b0000000100000: n2399_o = n1678_o; + 13'b0000000010000: n2399_o = n1591_o; + 13'b0000000001000: n2399_o = 1'b0; + 13'b0000000000100: n2399_o = 1'b0; + 13'b0000000000010: n2399_o = n1521_o; + 13'b0000000000001: n2399_o = n1456_o; + default: n2399_o = 1'b0; + endcase + /* T65_MCode.vhd:955:24 */ + assign n2404_o = ir[1:0]; + /* T65_MCode.vhd:958:32 */ + assign n2405_o = ir[4:2]; + /* T65_MCode.vhd:960:40 */ + assign n2406_o = ir[7:5]; + /* T65_MCode.vhd:961:33 */ + assign n2408_o = n2406_o == 3'b110; + /* T65_MCode.vhd:961:44 */ + assign n2410_o = n2406_o == 3'b111; + /* T65_MCode.vhd:961:44 */ + assign n2411_o = n2408_o | n2410_o; + /* T65_MCode.vhd:964:33 */ + assign n2413_o = n2406_o == 3'b101; + /* T65_MCode.vhd:967:33 */ + assign n2415_o = n2406_o == 3'b001; + assign n2416_o = {n2415_o, n2413_o, n2411_o}; + /* T65_MCode.vhd:960:33 */ + always @* + case (n2416_o) + 3'b100: n2421_o = 4'b1100; + 3'b010: n2421_o = 4'b0101; + 3'b001: n2421_o = 4'b0110; + default: n2421_o = 4'b0100; + endcase + /* T65_MCode.vhd:959:25 */ + assign n2423_o = n2405_o == 3'b000; + /* T65_MCode.vhd:959:36 */ + assign n2425_o = n2405_o == 3'b001; + /* T65_MCode.vhd:959:36 */ + assign n2426_o = n2423_o | n2425_o; + /* T65_MCode.vhd:959:44 */ + assign n2428_o = n2405_o == 3'b011; + /* T65_MCode.vhd:959:44 */ + assign n2429_o = n2426_o | n2428_o; + /* T65_MCode.vhd:975:40 */ + assign n2430_o = ir[7:5]; + /* T65_MCode.vhd:976:33 */ + assign n2432_o = n2430_o == 3'b111; + /* T65_MCode.vhd:976:44 */ + assign n2434_o = n2430_o == 3'b110; + /* T65_MCode.vhd:976:44 */ + assign n2435_o = n2432_o | n2434_o; + /* T65_MCode.vhd:979:33 */ + assign n2437_o = n2430_o == 3'b100; + assign n2438_o = {n2437_o, n2435_o}; + /* T65_MCode.vhd:975:33 */ + always @* + case (n2438_o) + 2'b10: n2442_o = 4'b1110; + 2'b01: n2442_o = 4'b1111; + default: n2442_o = 4'b1101; + endcase + /* T65_MCode.vhd:974:25 */ + assign n2444_o = n2405_o == 3'b010; + /* T65_MCode.vhd:987:40 */ + assign n2445_o = ir[7:5]; + /* T65_MCode.vhd:988:33 */ + assign n2447_o = n2445_o == 3'b100; + /* T65_MCode.vhd:987:33 */ + always @* + case (n2447_o) + 1'b1: n2450_o = 4'b1101; + default: n2450_o = 4'bX; + endcase + /* T65_MCode.vhd:986:25 */ + assign n2452_o = n2405_o == 3'b110; + /* T65_MCode.vhd:995:40 */ + assign n2453_o = ir[7:5]; + /* T65_MCode.vhd:996:33 */ + assign n2455_o = n2453_o == 3'b101; + /* T65_MCode.vhd:995:33 */ + always @* + case (n2455_o) + 1'b1: n2458_o = 4'b1101; + default: n2458_o = 4'b0100; + endcase + assign n2459_o = {n2452_o, n2444_o, n2429_o}; + /* T65_MCode.vhd:958:25 */ + always @* + case (n2459_o) + 3'b100: n2460_o = n2450_o; + 3'b010: n2460_o = n2442_o; + 3'b001: n2460_o = n2421_o; + default: n2460_o = n2458_o; + endcase + /* T65_MCode.vhd:956:17 */ + assign n2462_o = n2404_o == 2'b00; + /* T65_MCode.vhd:1007:49 */ + assign n2464_o = ir[7:5]; + /* T65_MCode.vhd:1004:17 */ + assign n2466_o = n2404_o == 2'b01; + /* T65_MCode.vhd:1012:49 */ + assign n2468_o = ir[7:5]; + /* T65_MCode.vhd:1013:32 */ + assign n2469_o = ir[7:5]; + /* T65_MCode.vhd:1015:38 */ + assign n2470_o = ir[4:2]; + /* T65_MCode.vhd:1015:51 */ + assign n2472_o = n2470_o == 3'b110; + assign n2474_o = {1'b1, n2468_o}; + /* T65_MCode.vhd:1015:33 */ + assign n2475_o = n2472_o ? 4'b1111 : n2474_o; + /* T65_MCode.vhd:1014:25 */ + assign n2477_o = n2469_o == 3'b000; + /* T65_MCode.vhd:1020:38 */ + assign n2478_o = ir[4:2]; + /* T65_MCode.vhd:1020:51 */ + assign n2480_o = n2478_o == 3'b110; + assign n2482_o = {1'b1, n2468_o}; + /* T65_MCode.vhd:1020:33 */ + assign n2483_o = n2480_o ? 4'b1110 : n2482_o; + /* T65_MCode.vhd:1019:25 */ + assign n2485_o = n2469_o == 3'b001; + /* T65_MCode.vhd:1025:38 */ + assign n2486_o = ir[4:2]; + /* T65_MCode.vhd:1025:51 */ + assign n2488_o = n2486_o == 3'b010; + /* T65_MCode.vhd:1025:33 */ + assign n2491_o = n2488_o ? 4'b0101 : 4'b0100; + /* T65_MCode.vhd:1024:25 */ + assign n2493_o = n2469_o == 3'b100; + assign n2494_o = {n2493_o, n2485_o, n2477_o}; + assign n2495_o = {1'b1, n2468_o}; + /* T65_MCode.vhd:1013:25 */ + always @* + case (n2494_o) + 3'b100: n2496_o = n2491_o; + 3'b010: n2496_o = n2483_o; + 3'b001: n2496_o = n2475_o; + default: n2496_o = n2495_o; + endcase + /* T65_MCode.vhd:1009:17 */ + assign n2498_o = n2404_o == 2'b10; + /* T65_MCode.vhd:1036:32 */ + assign n2499_o = ir[7:5]; + /* T65_MCode.vhd:1037:25 */ + assign n2501_o = n2499_o == 3'b100; + /* T65_MCode.vhd:1040:43 */ + assign n2503_o = mcycle == 3'b000; + /* T65_MCode.vhd:1042:65 */ + assign n2505_o = ir[7:5]; + /* T65_MCode.vhd:1045:65 */ + assign n2507_o = ir[7:5]; + assign n2508_o = {1'b1, n2507_o}; + assign n2509_o = {1'b0, n2505_o}; + /* T65_MCode.vhd:1040:33 */ + assign n2510_o = n2503_o ? n2509_o : n2508_o; + /* T65_MCode.vhd:1036:25 */ + always @* + case (n2501_o) + 1'b1: n2512_o = 4'b0100; + default: n2512_o = n2510_o; + endcase + assign n2513_o = {n2498_o, n2466_o, n2462_o}; + assign n2514_o = n2460_o[2:0]; + assign n2515_o = n2496_o[2:0]; + assign n2516_o = n2512_o[2:0]; + /* T65_MCode.vhd:955:17 */ + always @* + case (n2513_o) + 3'b100: n2517_o = n2515_o; + 3'b010: n2517_o = n2464_o; + 3'b001: n2517_o = n2514_o; + default: n2517_o = n2516_o; + endcase + assign n2518_o = n2460_o[3]; + assign n2519_o = n2496_o[3]; + assign n2520_o = n2512_o[3]; + /* T65_MCode.vhd:955:17 */ + always @* + case (n2513_o) + 3'b100: n2521_o = n2519_o; + 3'b010: n2521_o = 1'b0; + 3'b001: n2521_o = n2518_o; + default: n2521_o = n2520_o; + endcase + assign n2523_o = {n2521_o, n2517_o}; +endmodule + +module T65 + (input [1:0] Mode, + input Res_n, + input Enable, + input Clk, + input Rdy, + input Abort_n, + input IRQ_n, + input NMI_n, + input SO_n, + input [7:0] DI, + output R_W_n, + output Sync, + output EF, + output MF, + output XF, + output ML_n, + output VP_n, + output VDA, + output VPA, + output [23:0] A, + output [7:0] DO); + wire [15:0] abc; + wire [15:0] x; + wire [15:0] y; + reg [7:0] p; + reg [7:0] ad; + reg [7:0] dl; + wire [7:0] bah; + wire [8:0] bal; + wire [7:0] pbr; + wire [7:0] dbr; + wire [15:0] pc; + wire [15:0] s; + wire ef_i; + wire mf_i; + wire xf_i; + wire [7:0] ir; + wire [2:0] mcycle; + wire [1:0] mode_r; + wire [3:0] alu_op_r; + wire [2:0] write_data_r; + wire [1:0] set_addr_to_r; + wire [8:0] pcadder; + wire rstcycle; + wire irqcycle; + wire nmicycle; + wire so_n_o; + wire irq_n_o; + wire nmi_n_o; + wire nmiact; + wire brk; + wire [7:0] busa; + wire [7:0] busa_r; + wire [7:0] busb; + wire [7:0] alu_q; + wire [7:0] p_out; + wire [2:0] lcycle; + wire [3:0] alu_op; + wire [2:0] set_busa_to; + wire [1:0] set_addr_to; + wire [2:0] write_data; + wire [1:0] jump; + wire [1:0] baadd; + wire breakatna; + wire adadd; + wire addy; + wire pcadd; + wire inc_s; + wire dec_s; + wire lda; + wire ldp; + wire ldx; + wire ldy; + wire lds; + wire lddi; + wire ldalu; + wire ldad; + wire ldbal; + wire ldbah; + wire savep; + wire write; + wire really_rdy; + wire r_w_n_i; + wire n14_o; + wire n15_o; + wire n18_o; + wire n19_o; + wire [1:0] n22_o; + wire n24_o; + wire [1:0] n25_o; + wire n27_o; + wire n28_o; + wire [1:0] n29_o; + wire n31_o; + wire n32_o; + wire n33_o; + wire n37_o; + wire n39_o; + wire n40_o; + wire n41_o; + wire n42_o; + wire n46_o; + wire n47_o; + wire n50_o; + wire n51_o; + wire n52_o; + wire [2:0] mcode_n54; + wire [3:0] mcode_n55; + wire [2:0] mcode_n56; + wire [1:0] mcode_n57; + wire [2:0] mcode_n58; + wire [1:0] mcode_n59; + wire [1:0] mcode_n60; + wire mcode_n61; + wire mcode_n62; + wire mcode_n63; + wire mcode_n64; + wire mcode_n65; + wire mcode_n66; + wire mcode_n67; + wire mcode_n68; + wire mcode_n69; + wire mcode_n70; + wire mcode_n71; + wire mcode_n72; + wire mcode_n73; + wire mcode_n74; + wire mcode_n75; + wire mcode_n76; + wire mcode_n77; + wire mcode_n78; + wire [2:0] mcode_lcycle; + wire [3:0] mcode_alu_op; + wire [2:0] mcode_set_busa_to; + wire [1:0] mcode_set_addr_to; + wire [2:0] mcode_write_data; + wire [1:0] mcode_jump; + wire [1:0] mcode_baadd; + wire mcode_breakatna; + wire mcode_adadd; + wire mcode_addy; + wire mcode_pcadd; + wire mcode_inc_s; + wire mcode_dec_s; + wire mcode_lda; + wire mcode_ldp; + wire mcode_ldx; + wire mcode_ldy; + wire mcode_lds; + wire mcode_lddi; + wire mcode_ldalu; + wire mcode_ldad; + wire mcode_ldbal; + wire mcode_ldbah; + wire mcode_savep; + wire mcode_write; + wire [7:0] alu_n129; + wire [7:0] alu_p_out; + wire n137_o; + wire n139_o; + wire n140_o; + wire n142_o; + wire n143_o; + wire n144_o; + wire n145_o; + wire [15:0] n147_o; + wire n149_o; + wire [7:0] n151_o; + wire n152_o; + wire [1:0] n156_o; + wire [15:0] n158_o; + wire n160_o; + wire n161_o; + wire [15:0] n163_o; + wire [7:0] n165_o; + wire [7:0] n166_o; + wire [7:0] n167_o; + wire [7:0] n168_o; + wire [7:0] n169_o; + wire [7:0] n170_o; + wire [7:0] n171_o; + wire [7:0] n172_o; + wire [7:0] n173_o; + wire [7:0] n174_o; + wire [7:0] n175_o; + wire n177_o; + wire n179_o; + wire n180_o; + wire n181_o; + wire n182_o; + wire n183_o; + wire n184_o; + wire [15:0] n186_o; + wire [15:0] n189_o; + wire n191_o; + wire [15:0] n192_o; + wire n194_o; + wire n195_o; + wire n196_o; + wire n197_o; + wire [7:0] n198_o; + wire [7:0] n200_o; + wire [7:0] n201_o; + wire [7:0] n203_o; + wire [7:0] n204_o; + wire [7:0] n205_o; + wire [7:0] n206_o; + wire [7:0] n207_o; + wire [7:0] n208_o; + wire [7:0] n209_o; + wire [7:0] n210_o; + wire [7:0] n211_o; + wire n213_o; + wire [2:0] n214_o; + wire [7:0] n215_o; + wire [7:0] n216_o; + wire [7:0] n217_o; + wire [7:0] n218_o; + wire [7:0] n219_o; + wire [7:0] n220_o; + wire [7:0] n221_o; + reg [7:0] n222_o; + wire [7:0] n223_o; + wire [7:0] n224_o; + wire [7:0] n225_o; + wire [7:0] n226_o; + wire [7:0] n227_o; + wire [7:0] n228_o; + wire [7:0] n229_o; + reg [7:0] n230_o; + wire [15:0] n242_o; + wire [15:0] n244_o; + wire n252_o; + wire n253_o; + wire n259_o; + wire n260_o; + wire n261_o; + wire n262_o; + wire n263_o; + wire n264_o; + wire n265_o; + wire n266_o; + wire n267_o; + wire n268_o; + wire n269_o; + wire n270_o; + wire n271_o; + wire [7:0] n315_o; + wire [8:0] n316_o; + wire n317_o; + wire [8:0] n318_o; + wire [8:0] n319_o; + wire [8:0] n320_o; + wire [7:0] n321_o; + wire [8:0] n323_o; + wire n328_o; + wire n335_o; + wire n336_o; + wire n339_o; + wire n341_o; + wire n343_o; + wire n344_o; + wire [4:0] n347_o; + wire n349_o; + wire [2:0] n350_o; + wire n353_o; + wire n356_o; + wire n359_o; + wire n362_o; + wire n365_o; + wire n368_o; + wire n371_o; + wire [6:0] n372_o; + wire n373_o; + wire n374_o; + wire n375_o; + wire n376_o; + wire n377_o; + wire n378_o; + wire n379_o; + reg n380_o; + wire n381_o; + wire n382_o; + wire n383_o; + wire n384_o; + wire n385_o; + wire n386_o; + wire n387_o; + reg n388_o; + wire n389_o; + wire n390_o; + wire n391_o; + wire n392_o; + wire n393_o; + wire n394_o; + wire n395_o; + reg n396_o; + wire n397_o; + wire n398_o; + wire n399_o; + wire n400_o; + wire n401_o; + wire n402_o; + wire n403_o; + reg n404_o; + wire [1:0] n405_o; + wire n406_o; + wire n407_o; + wire n408_o; + wire n409_o; + wire n410_o; + wire n411_o; + wire n412_o; + wire n413_o; + wire n422_o; + wire n423_o; + wire n424_o; + wire n425_o; + wire n426_o; + wire n427_o; + wire n428_o; + wire n429_o; + wire n444_o; + wire n445_o; + wire n446_o; + wire n447_o; + wire n448_o; + wire n449_o; + wire n450_o; + wire n451_o; + wire n452_o; + wire n453_o; + wire n454_o; + wire n455_o; + wire n456_o; + wire n457_o; + wire n474_o; + wire n475_o; + wire n476_o; + wire n477_o; + wire n478_o; + wire n480_o; + wire n483_o; + wire n485_o; + wire n486_o; + wire n487_o; + wire n488_o; + wire n489_o; + wire n490_o; + wire n491_o; + wire n492_o; + wire n493_o; + wire n494_o; + wire n495_o; + wire n496_o; + wire n497_o; + wire n498_o; + wire n499_o; + wire n500_o; + wire n501_o; + wire n502_o; + wire n503_o; + wire n504_o; + wire n505_o; + wire n506_o; + wire n507_o; + wire n508_o; + wire n509_o; + wire n510_o; + wire n511_o; + wire n512_o; + wire n513_o; + wire n514_o; + wire n515_o; + wire n516_o; + wire n517_o; + wire n518_o; + wire n519_o; + wire n520_o; + wire n521_o; + wire n522_o; + wire n523_o; + wire n524_o; + wire n525_o; + wire n526_o; + wire n527_o; + wire n529_o; + wire n531_o; + wire n532_o; + wire [1:0] n536_o; + wire [1:0] n537_o; + wire [1:0] n538_o; + wire n543_o; + wire n545_o; + wire n547_o; + wire [7:0] n548_o; + wire n555_o; + wire n557_o; + wire n559_o; + wire n560_o; + wire n562_o; + wire n563_o; + wire n564_o; + wire n579_o; + wire [7:0] n582_o; + wire [8:0] n584_o; + wire n586_o; + wire [7:0] n587_o; + wire [8:0] n588_o; + wire [8:0] n589_o; + wire [8:0] n590_o; + wire n592_o; + wire n593_o; + wire [7:0] n595_o; + wire [7:0] n596_o; + wire n598_o; + wire [2:0] n599_o; + reg [7:0] n600_o; + reg [7:0] n601_o; + reg [8:0] n602_o; + wire [7:0] n603_o; + wire [7:0] n604_o; + wire [7:0] n605_o; + wire [7:0] n606_o; + wire [7:0] n607_o; + wire [7:0] n608_o; + wire n610_o; + localparam [2:0] n611_o = 3'b100; + localparam [2:0] n612_o = 3'b010; + localparam [2:0] n613_o = 3'b110; + localparam [8:0] n616_o = 9'b111111111; + wire [5:0] n617_o; + wire n619_o; + wire n621_o; + wire n622_o; + wire n623_o; + wire n624_o; + wire n625_o; + wire n626_o; + wire [1:0] n627_o; + wire [1:0] n628_o; + wire [1:0] n629_o; + wire [1:0] n630_o; + wire [1:0] n631_o; + wire [7:0] n633_o; + wire [8:0] n634_o; + wire [7:0] n636_o; + wire [7:0] n637_o; + wire [7:0] n638_o; + wire [7:0] n639_o; + wire [7:0] n640_o; + wire [7:0] n641_o; + wire [7:0] n642_o; + wire n643_o; + wire n644_o; + wire n645_o; + wire [7:0] n646_o; + wire [8:0] n650_o; + wire n654_o; + wire n655_o; + wire n656_o; + wire n657_o; + wire n658_o; + wire n659_o; + wire n679_o; + wire n680_o; + wire n681_o; + wire n682_o; + wire n683_o; + wire n684_o; + wire n685_o; + wire n687_o; + wire [7:0] n688_o; + wire n690_o; + wire [7:0] n691_o; + wire n693_o; + wire [7:0] n694_o; + wire n696_o; + wire [7:0] n697_o; + wire n699_o; + wire n701_o; + wire [5:0] n703_o; + reg [7:0] n704_o; + wire [7:0] n705_o; + wire [23:0] n707_o; + wire n709_o; + wire [15:0] n711_o; + wire [23:0] n712_o; + wire n714_o; + wire [15:0] n716_o; + wire [7:0] n717_o; + wire [23:0] n718_o; + wire n720_o; + wire [7:0] n721_o; + wire [15:0] n722_o; + wire [7:0] n723_o; + wire [23:0] n724_o; + wire [2:0] n725_o; + reg [23:0] n726_o; + wire n728_o; + wire [7:0] n729_o; + wire n731_o; + wire [7:0] n732_o; + wire n734_o; + wire [7:0] n735_o; + wire n737_o; + wire [7:0] n738_o; + wire n740_o; + wire n742_o; + wire [7:0] n743_o; + wire n745_o; + wire [7:0] n746_o; + wire [6:0] n747_o; + reg [7:0] n748_o; + wire n751_o; + wire n753_o; + wire n754_o; + wire n755_o; + wire n756_o; + wire n757_o; + wire n758_o; + wire n761_o; + wire n763_o; + wire n767_o; + wire [2:0] n770_o; + wire [2:0] n772_o; + wire n778_o; + wire n779_o; + wire n780_o; + wire n782_o; + wire n784_o; + wire n785_o; + wire n786_o; + wire n788_o; + wire n789_o; + wire n790_o; + wire n791_o; + wire n792_o; + wire [7:0] n809_o; + wire [7:0] n810_o; + reg [7:0] n811_q; + wire [15:0] n813_o; + wire [7:0] n814_o; + wire [7:0] n815_o; + reg [7:0] n816_q; + wire [15:0] n818_o; + wire [7:0] n819_o; + wire [7:0] n820_o; + reg [7:0] n821_q; + wire [15:0] n823_o; + wire [7:0] n826_o; + reg [7:0] n827_q; + wire [7:0] n828_o; + reg [7:0] n829_q; + wire [7:0] n830_o; + reg [7:0] n831_q; + wire [7:0] n832_o; + reg [7:0] n833_q; + wire [8:0] n834_o; + reg [8:0] n835_q; + wire [7:0] n836_o; + reg [7:0] n837_q; + wire [7:0] n838_o; + reg [7:0] n839_q; + wire [15:0] n840_o; + reg [15:0] n841_q; + wire [15:0] n842_o; + reg [15:0] n843_q; + wire n844_o; + reg n845_q; + wire n846_o; + reg n847_q; + wire n848_o; + reg n849_q; + wire [7:0] n850_o; + reg [7:0] n851_q; + wire [2:0] n852_o; + reg [2:0] n853_q; + wire [1:0] n854_o; + reg [1:0] n855_q; + wire [3:0] n856_o; + reg [3:0] n857_q; + wire [2:0] n858_o; + reg [2:0] n859_q; + wire [1:0] n860_o; + reg [1:0] n861_q; + wire n862_o; + reg n863_q; + wire n864_o; + reg n865_q; + wire n866_o; + reg n867_q; + wire n870_o; + reg n871_q; + wire n872_o; + reg n873_q; + wire n874_o; + reg n875_q; + wire n876_o; + reg n877_q; + wire [7:0] n878_o; + reg [7:0] n879_q; + wire [7:0] n880_o; + reg [7:0] n881_q; + wire n882_o; + reg n883_q; + assign R_W_n = r_w_n_i; + assign Sync = n19_o; + assign EF = ef_i; + assign MF = mf_i; + assign XF = xf_i; + assign ML_n = n33_o; + assign VP_n = n42_o; + assign VDA = n47_o; + assign VPA = n52_o; + assign A = n726_o; + assign DO = n748_o; + /* T65.vhd:100:16 */ + assign abc = n813_o; // (signal) + /* T65.vhd:100:21 */ + assign x = n818_o; // (signal) + /* T65.vhd:100:24 */ + assign y = n823_o; // (signal) + /* T65.vhd:101:16 */ + always @* + p = n827_q; // (isignal) + initial + p = 8'b00000000; + /* T65.vhd:101:19 */ + always @* + ad = n829_q; // (isignal) + initial + ad = 8'b00000000; + /* T65.vhd:101:23 */ + always @* + dl = n831_q; // (isignal) + initial + dl = 8'b00000000; + /* T65.vhd:102:16 */ + assign bah = n833_q; // (signal) + /* T65.vhd:103:16 */ + assign bal = n835_q; // (signal) + /* T65.vhd:104:16 */ + assign pbr = n837_q; // (signal) + /* T65.vhd:105:16 */ + assign dbr = n839_q; // (signal) + /* T65.vhd:106:16 */ + assign pc = n841_q; // (signal) + /* T65.vhd:107:16 */ + assign s = n843_q; // (signal) + /* T65.vhd:108:16 */ + assign ef_i = n845_q; // (signal) + /* T65.vhd:109:16 */ + assign mf_i = n847_q; // (signal) + /* T65.vhd:110:16 */ + assign xf_i = n849_q; // (signal) + /* T65.vhd:112:16 */ + assign ir = n851_q; // (signal) + /* T65.vhd:113:16 */ + assign mcycle = n853_q; // (signal) + /* T65.vhd:115:16 */ + assign mode_r = n855_q; // (signal) + /* T65.vhd:116:16 */ + assign alu_op_r = n857_q; // (signal) + /* T65.vhd:117:16 */ + assign write_data_r = n859_q; // (signal) + /* T65.vhd:118:16 */ + assign set_addr_to_r = n861_q; // (signal) + /* T65.vhd:119:16 */ + assign pcadder = n320_o; // (signal) + /* T65.vhd:121:16 */ + assign rstcycle = n863_q; // (signal) + /* T65.vhd:122:16 */ + assign irqcycle = n865_q; // (signal) + /* T65.vhd:123:16 */ + assign nmicycle = n867_q; // (signal) + /* T65.vhd:126:16 */ + assign so_n_o = n871_q; // (signal) + /* T65.vhd:127:16 */ + assign irq_n_o = n873_q; // (signal) + /* T65.vhd:128:16 */ + assign nmi_n_o = n875_q; // (signal) + /* T65.vhd:129:16 */ + assign nmiact = n877_q; // (signal) + /* T65.vhd:131:16 */ + assign brk = n685_o; // (signal) + /* T65.vhd:134:16 */ + assign busa = n704_o; // (signal) + /* T65.vhd:135:16 */ + assign busa_r = n879_q; // (signal) + /* T65.vhd:136:16 */ + assign busb = n881_q; // (signal) + /* T65.vhd:138:16 */ + assign p_out = alu_n129; // (signal) + /* T65.vhd:141:16 */ + assign lcycle = mcode_n54; // (signal) + /* T65.vhd:142:16 */ + assign alu_op = mcode_n55; // (signal) + /* T65.vhd:143:16 */ + assign set_busa_to = mcode_n56; // (signal) + /* T65.vhd:144:16 */ + assign set_addr_to = mcode_n57; // (signal) + /* T65.vhd:145:16 */ + assign write_data = mcode_n58; // (signal) + /* T65.vhd:146:16 */ + assign jump = mcode_n59; // (signal) + /* T65.vhd:147:16 */ + assign baadd = mcode_n60; // (signal) + /* T65.vhd:148:16 */ + assign breakatna = mcode_n61; // (signal) + /* T65.vhd:149:16 */ + assign adadd = mcode_n62; // (signal) + /* T65.vhd:150:16 */ + assign addy = mcode_n63; // (signal) + /* T65.vhd:151:16 */ + assign pcadd = mcode_n64; // (signal) + /* T65.vhd:152:16 */ + assign inc_s = mcode_n65; // (signal) + /* T65.vhd:153:16 */ + assign dec_s = mcode_n66; // (signal) + /* T65.vhd:154:16 */ + assign lda = mcode_n67; // (signal) + /* T65.vhd:155:16 */ + assign ldp = mcode_n68; // (signal) + /* T65.vhd:156:16 */ + assign ldx = mcode_n69; // (signal) + /* T65.vhd:157:16 */ + assign ldy = mcode_n70; // (signal) + /* T65.vhd:158:16 */ + assign lds = mcode_n71; // (signal) + /* T65.vhd:159:16 */ + assign lddi = mcode_n72; // (signal) + /* T65.vhd:160:16 */ + assign ldalu = mcode_n73; // (signal) + /* T65.vhd:161:16 */ + assign ldad = mcode_n74; // (signal) + /* T65.vhd:162:16 */ + assign ldbal = mcode_n75; // (signal) + /* T65.vhd:163:16 */ + assign ldbah = mcode_n76; // (signal) + /* T65.vhd:164:16 */ + assign savep = mcode_n77; // (signal) + /* T65.vhd:165:16 */ + assign write = mcode_n78; // (signal) + /* T65.vhd:167:16 */ + assign really_rdy = n15_o; // (signal) + /* T65.vhd:168:16 */ + assign r_w_n_i = n883_q; // (signal) + /* T65.vhd:174:30 */ + assign n14_o = ~r_w_n_i; + /* T65.vhd:174:27 */ + assign n15_o = Rdy | n14_o; + /* T65.vhd:179:33 */ + assign n18_o = mcycle == 3'b000; + /* T65.vhd:179:21 */ + assign n19_o = n18_o ? 1'b1 : 1'b0; + /* T65.vhd:183:28 */ + assign n22_o = ir[7:6]; + /* T65.vhd:183:41 */ + assign n24_o = n22_o != 2'b10; + /* T65.vhd:183:55 */ + assign n25_o = ir[2:1]; + /* T65.vhd:183:68 */ + assign n27_o = n25_o == 2'b11; + /* T65.vhd:183:49 */ + assign n28_o = n24_o & n27_o; + /* T65.vhd:183:85 */ + assign n29_o = mcycle[2:1]; + /* T65.vhd:183:98 */ + assign n31_o = n29_o != 2'b00; + /* T65.vhd:183:75 */ + assign n32_o = n28_o & n31_o; + /* T65.vhd:183:21 */ + assign n33_o = n32_o ? 1'b0 : 1'b1; + /* T65.vhd:184:53 */ + assign n37_o = mcycle == 3'b101; + /* T65.vhd:184:71 */ + assign n39_o = mcycle == 3'b110; + /* T65.vhd:184:61 */ + assign n40_o = n37_o | n39_o; + /* T65.vhd:184:41 */ + assign n41_o = irqcycle & n40_o; + /* T65.vhd:184:21 */ + assign n42_o = n41_o ? 1'b0 : 1'b1; + /* T65.vhd:185:39 */ + assign n46_o = set_addr_to_r != 2'b00; + /* T65.vhd:185:20 */ + assign n47_o = n46_o ? 1'b1 : 1'b0; + /* T65.vhd:186:29 */ + assign n50_o = jump[1]; + /* T65.vhd:186:33 */ + assign n51_o = ~n50_o; + /* T65.vhd:186:20 */ + assign n52_o = n51_o ? 1'b1 : 1'b0; + /* T65.vhd:194:40 */ + assign mcode_n54 = mcode_lcycle; // (signal) + /* T65.vhd:195:40 */ + assign mcode_n55 = mcode_alu_op; // (signal) + /* T65.vhd:196:40 */ + assign mcode_n56 = mcode_set_busa_to; // (signal) + /* T65.vhd:197:40 */ + assign mcode_n57 = mcode_set_addr_to; // (signal) + /* T65.vhd:198:40 */ + assign mcode_n58 = mcode_write_data; // (signal) + /* T65.vhd:199:40 */ + assign mcode_n59 = mcode_jump; // (signal) + /* T65.vhd:200:40 */ + assign mcode_n60 = mcode_baadd; // (signal) + /* T65.vhd:201:40 */ + assign mcode_n61 = mcode_breakatna; // (signal) + /* T65.vhd:202:40 */ + assign mcode_n62 = mcode_adadd; // (signal) + /* T65.vhd:203:40 */ + assign mcode_n63 = mcode_addy; // (signal) + /* T65.vhd:204:40 */ + assign mcode_n64 = mcode_pcadd; // (signal) + /* T65.vhd:205:40 */ + assign mcode_n65 = mcode_inc_s; // (signal) + /* T65.vhd:206:40 */ + assign mcode_n66 = mcode_dec_s; // (signal) + /* T65.vhd:207:40 */ + assign mcode_n67 = mcode_lda; // (signal) + /* T65.vhd:208:40 */ + assign mcode_n68 = mcode_ldp; // (signal) + /* T65.vhd:209:40 */ + assign mcode_n69 = mcode_ldx; // (signal) + /* T65.vhd:210:40 */ + assign mcode_n70 = mcode_ldy; // (signal) + /* T65.vhd:211:40 */ + assign mcode_n71 = mcode_lds; // (signal) + /* T65.vhd:212:40 */ + assign mcode_n72 = mcode_lddi; // (signal) + /* T65.vhd:213:40 */ + assign mcode_n73 = mcode_ldalu; // (signal) + /* T65.vhd:214:40 */ + assign mcode_n74 = mcode_ldad; // (signal) + /* T65.vhd:215:40 */ + assign mcode_n75 = mcode_ldbal; // (signal) + /* T65.vhd:216:40 */ + assign mcode_n76 = mcode_ldbah; // (signal) + /* T65.vhd:217:40 */ + assign mcode_n77 = mcode_savep; // (signal) + /* T65.vhd:218:40 */ + assign mcode_n78 = mcode_write; // (signal) + /* T65.vhd:188:9 */ + t65_mcode mcode ( + .mode(mode_r), + .ir(ir), + .mcycle(mcycle), + .p(p), + .lcycle(mcode_lcycle), + .alu_op(mcode_alu_op), + .set_busa_to(mcode_set_busa_to), + .set_addr_to(mcode_set_addr_to), + .write_data(mcode_write_data), + .jump(mcode_jump), + .baadd(mcode_baadd), + .breakatna(mcode_breakatna), + .adadd(mcode_adadd), + .addy(mcode_addy), + .pcadd(mcode_pcadd), + .inc_s(mcode_inc_s), + .dec_s(mcode_dec_s), + .lda(mcode_lda), + .ldp(mcode_ldp), + .ldx(mcode_ldx), + .ldy(mcode_ldy), + .lds(mcode_lds), + .lddi(mcode_lddi), + .ldalu(mcode_ldalu), + .ldad(mcode_ldad), + .ldbal(mcode_ldbal), + .ldbah(mcode_ldbah), + .savep(mcode_savep), + .write(mcode_write)); + /* T65.vhd:228:34 */ + assign alu_n129 = alu_p_out; // (signal) + /* T65.vhd:221:9 */ + t65_alu alu ( + .mode(mode_r), + .op(alu_op_r), + .busa(busa_r), + .busb(busb), + .p_in(p), + .p_out(alu_p_out), + .q(alu_q)); + /* T65.vhd:234:26 */ + assign n137_o = ~Res_n; + /* T65.vhd:255:44 */ + assign n139_o = ~write; + /* T65.vhd:255:54 */ + assign n140_o = n139_o | rstcycle; + /* T65.vhd:264:44 */ + assign n142_o = mcycle == 3'b000; + /* T65.vhd:267:53 */ + assign n143_o = ~irqcycle; + /* T65.vhd:267:72 */ + assign n144_o = ~nmicycle; + /* T65.vhd:267:59 */ + assign n145_o = n143_o & n144_o; + /* T65.vhd:268:58 */ + assign n147_o = pc + 16'b0000000000000001; + /* T65.vhd:271:59 */ + assign n149_o = irqcycle | nmicycle; + /* T65.vhd:271:41 */ + assign n151_o = n149_o ? 8'b00000000 : DI; + /* T65.vhd:264:33 */ + assign n152_o = n142_o & n145_o; + /* T65.vhd:280:33 */ + assign n156_o = brk ? 2'b00 : set_addr_to; + /* T65.vhd:287:48 */ + assign n158_o = s + 16'b0000000000000001; + /* T65.vhd:289:61 */ + assign n160_o = ~rstcycle; + /* T65.vhd:289:48 */ + assign n161_o = dec_s & n160_o; + /* T65.vhd:290:48 */ + assign n163_o = s - 16'b0000000000000001; + assign n165_o = n163_o[7:0]; + assign n166_o = n158_o[7:0]; + assign n167_o = s[7:0]; + /* T65.vhd:286:33 */ + assign n168_o = inc_s ? n166_o : n167_o; + /* T65.vhd:289:33 */ + assign n169_o = n161_o ? n165_o : n168_o; + /* T65.vhd:292:33 */ + assign n170_o = lds ? alu_q : n169_o; + assign n171_o = n163_o[15:8]; + assign n172_o = n158_o[15:8]; + assign n173_o = s[15:8]; + /* T65.vhd:286:33 */ + assign n174_o = inc_s ? n172_o : n173_o; + /* T65.vhd:289:33 */ + assign n175_o = n161_o ? n171_o : n174_o; + /* T65.vhd:296:39 */ + assign n177_o = ir == 8'b00000000; + /* T65.vhd:296:63 */ + assign n179_o = mcycle == 3'b001; + /* T65.vhd:296:52 */ + assign n180_o = n177_o & n179_o; + /* T65.vhd:296:84 */ + assign n181_o = ~irqcycle; + /* T65.vhd:296:71 */ + assign n182_o = n180_o & n181_o; + /* T65.vhd:296:103 */ + assign n183_o = ~nmicycle; + /* T65.vhd:296:90 */ + assign n184_o = n182_o & n183_o; + /* T65.vhd:297:50 */ + assign n186_o = pc + 16'b0000000000000001; + /* T65.vhd:304:52 */ + assign n189_o = pc + 16'b0000000000000001; + /* T65.vhd:303:35 */ + assign n191_o = jump == 2'b01; + /* T65.vhd:307:61 */ + assign n192_o = {DI, dl}; + /* T65.vhd:306:35 */ + assign n194_o = jump == 2'b10; + /* T65.vhd:310:53 */ + assign n195_o = pcadder[8]; + /* T65.vhd:311:56 */ + assign n196_o = dl[7]; + /* T65.vhd:311:60 */ + assign n197_o = ~n196_o; + /* T65.vhd:312:80 */ + assign n198_o = pc[15:8]; + /* T65.vhd:312:94 */ + assign n200_o = n198_o + 8'b00000001; + /* T65.vhd:314:80 */ + assign n201_o = pc[15:8]; + /* T65.vhd:314:94 */ + assign n203_o = n201_o - 8'b00000001; + /* T65.vhd:311:51 */ + assign n204_o = n197_o ? n200_o : n203_o; + assign n205_o = n186_o[15:8]; + assign n206_o = n147_o[15:8]; + assign n207_o = pc[15:8]; + /* T65.vhd:264:33 */ + assign n208_o = n152_o ? n206_o : n207_o; + /* T65.vhd:296:33 */ + assign n209_o = n184_o ? n205_o : n208_o; + /* T65.vhd:310:43 */ + assign n210_o = n195_o ? n204_o : n209_o; + /* T65.vhd:317:68 */ + assign n211_o = pcadder[7:0]; + /* T65.vhd:309:35 */ + assign n213_o = jump == 2'b11; + assign n214_o = {n213_o, n194_o, n191_o}; + assign n215_o = n189_o[7:0]; + assign n216_o = n192_o[7:0]; + assign n217_o = n186_o[7:0]; + assign n218_o = n147_o[7:0]; + assign n219_o = pc[7:0]; + /* T65.vhd:264:33 */ + assign n220_o = n152_o ? n218_o : n219_o; + /* T65.vhd:296:33 */ + assign n221_o = n184_o ? n217_o : n220_o; + /* T65.vhd:302:33 */ + always @* + case (n214_o) + 3'b100: n222_o = n211_o; + 3'b010: n222_o = n216_o; + 3'b001: n222_o = n215_o; + default: n222_o = n221_o; + endcase + assign n223_o = n189_o[15:8]; + assign n224_o = n192_o[15:8]; + assign n225_o = n186_o[15:8]; + assign n226_o = n147_o[15:8]; + assign n227_o = pc[15:8]; + /* T65.vhd:264:33 */ + assign n228_o = n152_o ? n226_o : n227_o; + /* T65.vhd:296:33 */ + assign n229_o = n184_o ? n225_o : n228_o; + /* T65.vhd:302:33 */ + always @* + case (n214_o) + 3'b100: n230_o = n210_o; + 3'b010: n230_o = n224_o; + 3'b001: n230_o = n223_o; + default: n230_o = n229_o; + endcase + assign n242_o = {n230_o, n222_o}; + assign n244_o = {n175_o, n170_o}; + /* T65.vhd:254:25 */ + assign n252_o = really_rdy & n142_o; + /* T65.vhd:254:25 */ + assign n253_o = really_rdy & n142_o; + /* T65.vhd:253:19 */ + assign n259_o = Enable & really_rdy; + /* T65.vhd:253:19 */ + assign n260_o = Enable & really_rdy; + /* T65.vhd:253:19 */ + assign n261_o = Enable & really_rdy; + /* T65.vhd:253:19 */ + assign n262_o = Enable & really_rdy; + /* T65.vhd:253:19 */ + assign n263_o = Enable & really_rdy; + /* T65.vhd:253:19 */ + assign n264_o = Enable & really_rdy; + /* T65.vhd:253:19 */ + assign n265_o = Enable & really_rdy; + /* T65.vhd:253:19 */ + assign n266_o = Enable & n252_o; + /* T65.vhd:253:19 */ + assign n267_o = Enable & n253_o; + /* T65.vhd:253:19 */ + assign n268_o = Enable & really_rdy; + /* T65.vhd:253:19 */ + assign n269_o = Enable & really_rdy; + /* T65.vhd:253:19 */ + assign n270_o = Enable & really_rdy; + /* T65.vhd:253:19 */ + assign n271_o = Enable & really_rdy; + /* T65.vhd:326:29 */ + assign n315_o = pc[7:0]; + /* T65.vhd:326:20 */ + assign n316_o = {1'b0, n315_o}; // uext + /* T65.vhd:326:65 */ + assign n317_o = dl[7]; + /* T65.vhd:326:69 */ + assign n318_o = {n317_o, dl}; + /* T65.vhd:326:45 */ + assign n319_o = n316_o + n318_o; + /* T65.vhd:326:78 */ + assign n320_o = pcadd ? n319_o : n323_o; + /* T65.vhd:327:41 */ + assign n321_o = pc[7:0]; + /* T65.vhd:327:37 */ + assign n323_o = {1'b0, n321_o}; + /* T65.vhd:334:43 */ + assign n328_o = mcycle == 3'b000; + /* T65.vhd:344:49 */ + assign n335_o = lda | ldx; + /* T65.vhd:344:56 */ + assign n336_o = n335_o | ldy; + /* T65.vhd:334:33 */ + assign n339_o = n328_o & lda; + /* T65.vhd:334:33 */ + assign n341_o = n328_o & ldx; + /* T65.vhd:334:33 */ + assign n343_o = n328_o & ldy; + /* T65.vhd:334:33 */ + assign n344_o = n328_o & n336_o; + /* T65.vhd:354:38 */ + assign n347_o = ir[4:0]; + /* T65.vhd:354:51 */ + assign n349_o = n347_o == 5'b11000; + /* T65.vhd:355:48 */ + assign n350_o = ir[7:5]; + /* T65.vhd:356:41 */ + assign n353_o = n350_o == 3'b000; + /* T65.vhd:358:41 */ + assign n356_o = n350_o == 3'b001; + /* T65.vhd:360:41 */ + assign n359_o = n350_o == 3'b010; + /* T65.vhd:362:41 */ + assign n362_o = n350_o == 3'b011; + /* T65.vhd:364:41 */ + assign n365_o = n350_o == 3'b101; + /* T65.vhd:366:41 */ + assign n368_o = n350_o == 3'b110; + /* T65.vhd:368:41 */ + assign n371_o = n350_o == 3'b111; + assign n372_o = {n371_o, n368_o, n365_o, n362_o, n359_o, n356_o, n353_o}; + assign n373_o = alu_q[0]; + assign n374_o = p_out[0]; + assign n375_o = p_out[0]; + assign n376_o = p[0]; + /* T65.vhd:334:33 */ + assign n377_o = n344_o ? n375_o : n376_o; + /* T65.vhd:348:33 */ + assign n378_o = savep ? n374_o : n377_o; + /* T65.vhd:351:33 */ + assign n379_o = ldp ? n373_o : n378_o; + /* T65.vhd:355:41 */ + always @* + case (n372_o) + 7'b1000000: n380_o = n379_o; + 7'b0100000: n380_o = n379_o; + 7'b0010000: n380_o = n379_o; + 7'b0001000: n380_o = n379_o; + 7'b0000100: n380_o = n379_o; + 7'b0000010: n380_o = 1'b1; + 7'b0000001: n380_o = 1'b0; + default: n380_o = n379_o; + endcase + assign n381_o = alu_q[2]; + assign n382_o = p_out[2]; + assign n383_o = p_out[2]; + assign n384_o = p[2]; + /* T65.vhd:334:33 */ + assign n385_o = n344_o ? n383_o : n384_o; + /* T65.vhd:348:33 */ + assign n386_o = savep ? n382_o : n385_o; + /* T65.vhd:351:33 */ + assign n387_o = ldp ? n381_o : n386_o; + /* T65.vhd:355:41 */ + always @* + case (n372_o) + 7'b1000000: n388_o = n387_o; + 7'b0100000: n388_o = n387_o; + 7'b0010000: n388_o = n387_o; + 7'b0001000: n388_o = 1'b1; + 7'b0000100: n388_o = 1'b0; + 7'b0000010: n388_o = n387_o; + 7'b0000001: n388_o = n387_o; + default: n388_o = n387_o; + endcase + assign n389_o = alu_q[3]; + assign n390_o = p_out[3]; + assign n391_o = p_out[3]; + assign n392_o = p[3]; + /* T65.vhd:334:33 */ + assign n393_o = n344_o ? n391_o : n392_o; + /* T65.vhd:348:33 */ + assign n394_o = savep ? n390_o : n393_o; + /* T65.vhd:351:33 */ + assign n395_o = ldp ? n389_o : n394_o; + /* T65.vhd:355:41 */ + always @* + case (n372_o) + 7'b1000000: n396_o = 1'b1; + 7'b0100000: n396_o = 1'b0; + 7'b0010000: n396_o = n395_o; + 7'b0001000: n396_o = n395_o; + 7'b0000100: n396_o = n395_o; + 7'b0000010: n396_o = n395_o; + 7'b0000001: n396_o = n395_o; + default: n396_o = n395_o; + endcase + assign n397_o = alu_q[6]; + assign n398_o = p_out[6]; + assign n399_o = p_out[6]; + assign n400_o = p[6]; + /* T65.vhd:334:33 */ + assign n401_o = n344_o ? n399_o : n400_o; + /* T65.vhd:348:33 */ + assign n402_o = savep ? n398_o : n401_o; + /* T65.vhd:351:33 */ + assign n403_o = ldp ? n397_o : n402_o; + /* T65.vhd:355:41 */ + always @* + case (n372_o) + 7'b1000000: n404_o = n403_o; + 7'b0100000: n404_o = n403_o; + 7'b0010000: n404_o = 1'b0; + 7'b0001000: n404_o = n403_o; + 7'b0000100: n404_o = n403_o; + 7'b0000010: n404_o = n403_o; + 7'b0000001: n404_o = n403_o; + default: n404_o = n403_o; + endcase + assign n405_o = {n396_o, n388_o}; + assign n406_o = alu_q[0]; + assign n407_o = p_out[0]; + assign n408_o = p_out[0]; + assign n409_o = p[0]; + /* T65.vhd:334:33 */ + assign n410_o = n344_o ? n408_o : n409_o; + /* T65.vhd:348:33 */ + assign n411_o = savep ? n407_o : n410_o; + /* T65.vhd:351:33 */ + assign n412_o = ldp ? n406_o : n411_o; + /* T65.vhd:354:33 */ + assign n413_o = n349_o ? n380_o : n412_o; + assign n422_o = alu_q[6]; + assign n423_o = p_out[6]; + assign n424_o = p_out[6]; + assign n425_o = p[6]; + /* T65.vhd:334:33 */ + assign n426_o = n344_o ? n424_o : n425_o; + /* T65.vhd:348:33 */ + assign n427_o = savep ? n423_o : n426_o; + /* T65.vhd:351:33 */ + assign n428_o = ldp ? n422_o : n427_o; + /* T65.vhd:354:33 */ + assign n429_o = n349_o ? n404_o : n428_o; + assign n444_o = alu_q[1]; + assign n445_o = p_out[1]; + assign n446_o = p_out[1]; + assign n447_o = p[1]; + /* T65.vhd:334:33 */ + assign n448_o = n344_o ? n446_o : n447_o; + /* T65.vhd:348:33 */ + assign n449_o = savep ? n445_o : n448_o; + /* T65.vhd:351:33 */ + assign n450_o = ldp ? n444_o : n449_o; + assign n451_o = alu_q[7]; + assign n452_o = p_out[7]; + assign n453_o = p_out[7]; + assign n454_o = p[7]; + /* T65.vhd:334:33 */ + assign n455_o = n344_o ? n453_o : n454_o; + /* T65.vhd:348:33 */ + assign n456_o = savep ? n452_o : n455_o; + /* T65.vhd:351:33 */ + assign n457_o = ldp ? n451_o : n456_o; + /* T65.vhd:384:39 */ + assign n474_o = ir == 8'b00000000; + /* T65.vhd:384:65 */ + assign n475_o = ~rstcycle; + /* T65.vhd:384:52 */ + assign n476_o = n474_o & n475_o; + /* T65.vhd:384:91 */ + assign n477_o = nmicycle | irqcycle; + /* T65.vhd:384:71 */ + assign n478_o = n476_o & n477_o; + /* T65.vhd:385:21 */ + assign n480_o = mcycle == 3'b011; + /* T65.vhd:388:24 */ + assign n483_o = mcycle == 3'b100; + assign n485_o = n405_o[0]; + assign n486_o = alu_q[2]; + assign n487_o = p_out[2]; + assign n488_o = p_out[2]; + assign n489_o = p[2]; + /* T65.vhd:334:33 */ + assign n490_o = n344_o ? n488_o : n489_o; + /* T65.vhd:348:33 */ + assign n491_o = savep ? n487_o : n490_o; + /* T65.vhd:351:33 */ + assign n492_o = ldp ? n486_o : n491_o; + /* T65.vhd:354:33 */ + assign n493_o = n349_o ? n485_o : n492_o; + /* T65.vhd:388:11 */ + assign n494_o = n483_o ? 1'b1 : n493_o; + assign n495_o = n405_o[0]; + assign n496_o = alu_q[2]; + assign n497_o = p_out[2]; + assign n498_o = p_out[2]; + assign n499_o = p[2]; + /* T65.vhd:334:33 */ + assign n500_o = n344_o ? n498_o : n499_o; + /* T65.vhd:348:33 */ + assign n501_o = savep ? n497_o : n500_o; + /* T65.vhd:351:33 */ + assign n502_o = ldp ? n496_o : n501_o; + /* T65.vhd:354:33 */ + assign n503_o = n349_o ? n495_o : n502_o; + /* T65.vhd:385:11 */ + assign n504_o = n480_o ? n503_o : n494_o; + /* T65.vhd:384:33 */ + assign n505_o = n516_o ? 1'b0 : 1'b1; + assign n506_o = n405_o[0]; + assign n507_o = alu_q[2]; + assign n508_o = p_out[2]; + assign n509_o = p_out[2]; + assign n510_o = p[2]; + /* T65.vhd:334:33 */ + assign n511_o = n344_o ? n509_o : n510_o; + /* T65.vhd:348:33 */ + assign n512_o = savep ? n508_o : n511_o; + /* T65.vhd:351:33 */ + assign n513_o = ldp ? n507_o : n512_o; + /* T65.vhd:354:33 */ + assign n514_o = n349_o ? n506_o : n513_o; + /* T65.vhd:384:33 */ + assign n515_o = n478_o ? n504_o : n514_o; + /* T65.vhd:384:33 */ + assign n516_o = n478_o & n480_o; + assign n517_o = n405_o[1]; + assign n518_o = alu_q[3]; + assign n519_o = p_out[3]; + assign n520_o = p_out[3]; + assign n521_o = p[3]; + /* T65.vhd:334:33 */ + assign n522_o = n344_o ? n520_o : n521_o; + /* T65.vhd:348:33 */ + assign n523_o = savep ? n519_o : n522_o; + /* T65.vhd:351:33 */ + assign n524_o = ldp ? n518_o : n523_o; + /* T65.vhd:354:33 */ + assign n525_o = n349_o ? n517_o : n524_o; + /* T65.vhd:393:58 */ + assign n526_o = ~SO_n; + /* T65.vhd:393:49 */ + assign n527_o = so_n_o & n526_o; + /* T65.vhd:393:33 */ + assign n529_o = n527_o ? 1'b1 : n429_o; + /* T65.vhd:396:62 */ + assign n531_o = mode_r != 2'b00; + /* T65.vhd:396:51 */ + assign n532_o = rstcycle & n531_o; + assign n536_o = {1'b0, 1'b1}; + assign n537_o = {n525_o, n515_o}; + /* T65.vhd:396:33 */ + assign n538_o = n532_o ? n536_o : n537_o; + /* T65.vhd:333:25 */ + assign n543_o = really_rdy & n339_o; + /* T65.vhd:333:25 */ + assign n545_o = really_rdy & n341_o; + /* T65.vhd:333:25 */ + assign n547_o = really_rdy & n343_o; + assign n548_o = {n457_o, n529_o, 1'b1, n505_o, n538_o, n450_o, n413_o}; + /* T65.vhd:332:19 */ + assign n555_o = Enable & n543_o; + /* T65.vhd:332:19 */ + assign n557_o = Enable & n545_o; + /* T65.vhd:332:19 */ + assign n559_o = Enable & n547_o; + /* T65.vhd:332:19 */ + assign n560_o = Enable & really_rdy; + /* T65.vhd:332:19 */ + assign n562_o = Enable & really_rdy; + /* T65.vhd:332:19 */ + assign n563_o = Enable & really_rdy; + /* T65.vhd:332:19 */ + assign n564_o = Enable & really_rdy; + /* T65.vhd:420:26 */ + assign n579_o = ~Res_n; + /* T65.vhd:436:77 */ + assign n582_o = ad + 8'b00000001; + /* T65.vhd:437:79 */ + assign n584_o = bal + 9'b000000001; + /* T65.vhd:434:33 */ + assign n586_o = baadd == 2'b01; + /* T65.vhd:440:84 */ + assign n587_o = bal[7:0]; + /* T65.vhd:440:65 */ + assign n588_o = {1'b0, n587_o}; // uext + /* T65.vhd:440:103 */ + assign n589_o = {1'b0, busa}; // uext + /* T65.vhd:440:101 */ + assign n590_o = n588_o + n589_o; + /* T65.vhd:438:33 */ + assign n592_o = baadd == 2'b10; + /* T65.vhd:443:47 */ + assign n593_o = bal[8]; + /* T65.vhd:444:87 */ + assign n595_o = bah + 8'b00000001; + /* T65.vhd:443:41 */ + assign n596_o = n593_o ? n595_o : bah; + /* T65.vhd:441:33 */ + assign n598_o = baadd == 2'b11; + assign n599_o = {n598_o, n592_o, n586_o}; + /* T65.vhd:433:33 */ + always @* + case (n599_o) + 3'b100: n600_o = ad; + 3'b010: n600_o = ad; + 3'b001: n600_o = n582_o; + default: n600_o = ad; + endcase + /* T65.vhd:433:33 */ + always @* + case (n599_o) + 3'b100: n601_o = n596_o; + 3'b010: n601_o = bah; + 3'b001: n601_o = bah; + default: n601_o = bah; + endcase + /* T65.vhd:433:33 */ + always @* + case (n599_o) + 3'b100: n602_o = bal; + 3'b010: n602_o = n590_o; + 3'b001: n602_o = n584_o; + default: n602_o = bal; + endcase + /* T65.vhd:452:89 */ + assign n603_o = y[7:0]; + /* T65.vhd:452:77 */ + assign n604_o = ad + n603_o; + /* T65.vhd:454:89 */ + assign n605_o = x[7:0]; + /* T65.vhd:454:77 */ + assign n606_o = ad + n605_o; + /* T65.vhd:451:35 */ + assign n607_o = addy ? n604_o : n606_o; + /* T65.vhd:450:33 */ + assign n608_o = adadd ? n607_o : n600_o; + /* T65.vhd:458:39 */ + assign n610_o = ir == 8'b00000000; + assign n617_o = n616_o[8:3]; + /* T65.vhd:468:58 */ + assign n619_o = set_addr_to_r == 2'b11; + assign n621_o = n611_o[0]; + assign n622_o = n612_o[0]; + assign n623_o = n613_o[0]; + /* T65.vhd:463:41 */ + assign n624_o = nmicycle ? n622_o : n623_o; + /* T65.vhd:461:41 */ + assign n625_o = rstcycle ? n621_o : n624_o; + /* T65.vhd:468:41 */ + assign n626_o = n619_o ? 1'b1 : n625_o; + assign n627_o = n611_o[2:1]; + assign n628_o = n612_o[2:1]; + assign n629_o = n613_o[2:1]; + /* T65.vhd:463:41 */ + assign n630_o = nmicycle ? n628_o : n629_o; + /* T65.vhd:461:41 */ + assign n631_o = rstcycle ? n627_o : n630_o; + /* T65.vhd:458:33 */ + assign n633_o = n610_o ? 8'b11111111 : n601_o; + assign n634_o = {n617_o, n631_o, n626_o}; + /* T65.vhd:474:33 */ + assign n636_o = lddi ? DI : dl; + /* T65.vhd:477:33 */ + assign n637_o = ldalu ? alu_q : n636_o; + /* T65.vhd:480:33 */ + assign n638_o = ldad ? DI : n608_o; + assign n639_o = n634_o[7:0]; + assign n640_o = n602_o[7:0]; + /* T65.vhd:458:33 */ + assign n641_o = n610_o ? n639_o : n640_o; + /* T65.vhd:483:33 */ + assign n642_o = ldbal ? DI : n641_o; + assign n643_o = n634_o[8]; + assign n644_o = n602_o[8]; + /* T65.vhd:458:33 */ + assign n645_o = n610_o ? n643_o : n644_o; + /* T65.vhd:486:33 */ + assign n646_o = ldbah ? DI : n633_o; + assign n650_o = {n645_o, n642_o}; + /* T65.vhd:428:19 */ + assign n654_o = Enable & Rdy; + /* T65.vhd:428:19 */ + assign n655_o = Enable & Rdy; + /* T65.vhd:428:19 */ + assign n656_o = Enable & Rdy; + /* T65.vhd:428:19 */ + assign n657_o = Enable & Rdy; + /* T65.vhd:428:19 */ + assign n658_o = Enable & Rdy; + /* T65.vhd:428:19 */ + assign n659_o = Enable & Rdy; + /* T65.vhd:494:40 */ + assign n679_o = bal[8]; + /* T65.vhd:494:33 */ + assign n680_o = ~n679_o; + /* T65.vhd:494:29 */ + assign n681_o = breakatna & n680_o; + /* T65.vhd:494:70 */ + assign n682_o = pcadder[8]; + /* T65.vhd:494:59 */ + assign n683_o = ~n682_o; + /* T65.vhd:494:55 */ + assign n684_o = pcadd & n683_o; + /* T65.vhd:494:45 */ + assign n685_o = n681_o | n684_o; + /* T65.vhd:498:28 */ + assign n687_o = set_busa_to == 3'b000; + /* T65.vhd:499:28 */ + assign n688_o = abc[7:0]; + /* T65.vhd:499:41 */ + assign n690_o = set_busa_to == 3'b001; + /* T65.vhd:500:26 */ + assign n691_o = x[7:0]; + /* T65.vhd:500:39 */ + assign n693_o = set_busa_to == 3'b010; + /* T65.vhd:501:26 */ + assign n694_o = y[7:0]; + /* T65.vhd:501:39 */ + assign n696_o = set_busa_to == 3'b011; + /* T65.vhd:502:43 */ + assign n697_o = s[7:0]; + /* T65.vhd:502:57 */ + assign n699_o = set_busa_to == 3'b100; + /* T65.vhd:503:27 */ + assign n701_o = set_busa_to == 3'b101; + assign n703_o = {n701_o, n699_o, n696_o, n693_o, n690_o, n687_o}; + /* T65.vhd:497:9 */ + always @* + case (n703_o) + 6'b100000: n704_o = p; + 6'b010000: n704_o = n697_o; + 6'b001000: n704_o = n694_o; + 6'b000100: n704_o = n691_o; + 6'b000010: n704_o = n688_o; + 6'b000001: n704_o = DI; + default: n704_o = 8'bX; + endcase + /* T65.vhd:507:61 */ + assign n705_o = s[7:0]; + /* T65.vhd:507:41 */ + assign n707_o = {16'b0000000000000001, n705_o}; + /* T65.vhd:507:75 */ + assign n709_o = set_addr_to_r == 2'b01; + /* T65.vhd:508:29 */ + assign n711_o = {dbr, 8'b00000000}; + /* T65.vhd:508:42 */ + assign n712_o = {n711_o, ad}; + /* T65.vhd:508:47 */ + assign n714_o = set_addr_to_r == 2'b10; + /* T65.vhd:509:36 */ + assign n716_o = {8'b00000000, bah}; + /* T65.vhd:509:47 */ + assign n717_o = bal[7:0]; + /* T65.vhd:509:42 */ + assign n718_o = {n716_o, n717_o}; + /* T65.vhd:509:60 */ + assign n720_o = set_addr_to_r == 2'b11; + /* T65.vhd:510:50 */ + assign n721_o = pc[15:8]; + /* T65.vhd:510:29 */ + assign n722_o = {pbr, n721_o}; + /* T65.vhd:510:91 */ + assign n723_o = pcadder[7:0]; + /* T65.vhd:510:65 */ + assign n724_o = {n722_o, n723_o}; + assign n725_o = {n720_o, n714_o, n709_o}; + /* T65.vhd:506:9 */ + always @* + case (n725_o) + 3'b100: n726_o = n718_o; + 3'b010: n726_o = n712_o; + 3'b001: n726_o = n707_o; + default: n726_o = n724_o; + endcase + /* T65.vhd:513:26 */ + assign n728_o = write_data_r == 3'b000; + /* T65.vhd:514:28 */ + assign n729_o = abc[7:0]; + /* T65.vhd:514:41 */ + assign n731_o = write_data_r == 3'b001; + /* T65.vhd:515:26 */ + assign n732_o = x[7:0]; + /* T65.vhd:515:39 */ + assign n734_o = write_data_r == 3'b010; + /* T65.vhd:516:26 */ + assign n735_o = y[7:0]; + /* T65.vhd:516:39 */ + assign n737_o = write_data_r == 3'b011; + /* T65.vhd:517:43 */ + assign n738_o = s[7:0]; + /* T65.vhd:517:57 */ + assign n740_o = write_data_r == 3'b100; + /* T65.vhd:518:27 */ + assign n742_o = write_data_r == 3'b101; + /* T65.vhd:519:44 */ + assign n743_o = pc[7:0]; + /* T65.vhd:519:58 */ + assign n745_o = write_data_r == 3'b110; + /* T65.vhd:520:44 */ + assign n746_o = pc[15:8]; + assign n747_o = {n745_o, n742_o, n740_o, n737_o, n734_o, n731_o, n728_o}; + /* T65.vhd:512:9 */ + always @* + case (n747_o) + 7'b1000000: n748_o = n743_o; + 7'b0100000: n748_o = p; + 7'b0010000: n748_o = n738_o; + 7'b0001000: n748_o = n735_o; + 7'b0000100: n748_o = n732_o; + 7'b0000010: n748_o = n729_o; + 7'b0000001: n748_o = dl; + default: n748_o = n746_o; + endcase + /* T65.vhd:530:26 */ + assign n751_o = ~Res_n; + /* T65.vhd:539:43 */ + assign n753_o = mcycle == lcycle; + /* T65.vhd:539:52 */ + assign n754_o = n753_o | brk; + /* T65.vhd:546:55 */ + assign n755_o = ~irq_n_o; + /* T65.vhd:546:66 */ + assign n756_o = p[2]; + /* T65.vhd:546:75 */ + assign n757_o = ~n756_o; + /* T65.vhd:546:61 */ + assign n758_o = n755_o & n757_o; + /* T65.vhd:546:41 */ + assign n761_o = n758_o ? 1'b1 : 1'b0; + /* T65.vhd:544:41 */ + assign n763_o = nmiact ? 1'b0 : n761_o; + /* T65.vhd:544:41 */ + assign n767_o = nmiact ? 1'b1 : 1'b0; + /* T65.vhd:550:85 */ + assign n770_o = mcycle + 3'b001; + /* T65.vhd:539:33 */ + assign n772_o = n754_o ? 3'b000 : n770_o; + /* T65.vhd:553:33 */ + assign n778_o = nmicycle ? 1'b0 : nmiact; + /* T65.vhd:556:60 */ + assign n779_o = ~NMI_n; + /* T65.vhd:556:50 */ + assign n780_o = nmi_n_o & n779_o; + /* T65.vhd:556:33 */ + assign n782_o = n780_o ? 1'b1 : n778_o; + /* T65.vhd:538:25 */ + assign n784_o = really_rdy & n754_o; + /* T65.vhd:538:25 */ + assign n785_o = really_rdy & n754_o; + /* T65.vhd:538:25 */ + assign n786_o = really_rdy & n754_o; + /* T65.vhd:537:19 */ + assign n788_o = Enable & really_rdy; + /* T65.vhd:537:19 */ + assign n789_o = Enable & n784_o; + /* T65.vhd:537:19 */ + assign n790_o = Enable & n785_o; + /* T65.vhd:537:19 */ + assign n791_o = Enable & n786_o; + /* T65.vhd:537:19 */ + assign n792_o = Enable & really_rdy; + assign n809_o = abc[7:0]; + /* T65.vhd:331:17 */ + assign n810_o = n555_o ? alu_q : n809_o; + /* T65.vhd:331:17 */ + always @(posedge Clk) + n811_q <= n810_o; + assign n813_o = {8'bZ, n811_q}; + assign n814_o = x[7:0]; + /* T65.vhd:331:17 */ + assign n815_o = n557_o ? alu_q : n814_o; + /* T65.vhd:331:17 */ + always @(posedge Clk) + n816_q <= n815_o; + assign n818_o = {8'bZ, n816_q}; + assign n819_o = y[7:0]; + /* T65.vhd:331:17 */ + assign n820_o = n559_o ? alu_q : n819_o; + /* T65.vhd:331:17 */ + always @(posedge Clk) + n821_q <= n820_o; + assign n823_o = {8'bZ, n821_q}; + /* T65.vhd:331:17 */ + assign n826_o = n560_o ? n548_o : p; + /* T65.vhd:331:17 */ + always @(posedge Clk) + n827_q <= n826_o; + initial + n827_q = 8'b00000000; + /* T65.vhd:427:17 */ + assign n828_o = n654_o ? n638_o : ad; + /* T65.vhd:427:17 */ + always @(posedge Clk or posedge n579_o) + if (n579_o) + n829_q <= 8'b00000000; + else + n829_q <= n828_o; + /* T65.vhd:427:17 */ + assign n830_o = n655_o ? n637_o : dl; + /* T65.vhd:427:17 */ + always @(posedge Clk or posedge n579_o) + if (n579_o) + n831_q <= 8'b00000000; + else + n831_q <= n830_o; + /* T65.vhd:427:17 */ + assign n832_o = n656_o ? n646_o : bah; + /* T65.vhd:427:17 */ + always @(posedge Clk or posedge n579_o) + if (n579_o) + n833_q <= 8'b00000000; + else + n833_q <= n832_o; + /* T65.vhd:427:17 */ + assign n834_o = n657_o ? n650_o : bal; + /* T65.vhd:427:17 */ + always @(posedge Clk or posedge n579_o) + if (n579_o) + n835_q <= 9'b000000000; + else + n835_q <= n834_o; + /* T65.vhd:252:17 */ + assign n836_o = n259_o ? 8'b11111111 : pbr; + /* T65.vhd:252:17 */ + always @(posedge Clk or posedge n137_o) + if (n137_o) + n837_q <= 8'b00000000; + else + n837_q <= n836_o; + /* T65.vhd:252:17 */ + assign n838_o = n260_o ? 8'b11111111 : dbr; + /* T65.vhd:252:17 */ + always @(posedge Clk or posedge n137_o) + if (n137_o) + n839_q <= 8'b00000000; + else + n839_q <= n838_o; + /* T65.vhd:252:17 */ + assign n840_o = n261_o ? n242_o : pc; + /* T65.vhd:252:17 */ + always @(posedge Clk or posedge n137_o) + if (n137_o) + n841_q <= 16'b0000000000000000; + else + n841_q <= n840_o; + /* T65.vhd:252:17 */ + assign n842_o = n262_o ? n244_o : s; + /* T65.vhd:252:17 */ + always @(posedge Clk or posedge n137_o) + if (n137_o) + n843_q <= 16'b0000000000000000; + else + n843_q <= n842_o; + /* T65.vhd:252:17 */ + assign n844_o = n263_o ? 1'b0 : ef_i; + /* T65.vhd:252:17 */ + always @(posedge Clk or posedge n137_o) + if (n137_o) + n845_q <= 1'b1; + else + n845_q <= n844_o; + /* T65.vhd:252:17 */ + assign n846_o = n264_o ? 1'b0 : mf_i; + /* T65.vhd:252:17 */ + always @(posedge Clk or posedge n137_o) + if (n137_o) + n847_q <= 1'b1; + else + n847_q <= n846_o; + /* T65.vhd:252:17 */ + assign n848_o = n265_o ? 1'b0 : xf_i; + /* T65.vhd:252:17 */ + always @(posedge Clk or posedge n137_o) + if (n137_o) + n849_q <= 1'b1; + else + n849_q <= n848_o; + /* T65.vhd:252:17 */ + assign n850_o = n266_o ? n151_o : ir; + /* T65.vhd:252:17 */ + always @(posedge Clk or posedge n137_o) + if (n137_o) + n851_q <= 8'b00000000; + else + n851_q <= n850_o; + /* T65.vhd:536:17 */ + assign n852_o = n788_o ? n772_o : mcycle; + /* T65.vhd:536:17 */ + always @(posedge Clk or posedge n751_o) + if (n751_o) + n853_q <= 3'b001; + else + n853_q <= n852_o; + /* T65.vhd:252:17 */ + assign n854_o = n267_o ? Mode : mode_r; + /* T65.vhd:252:17 */ + always @(posedge Clk or posedge n137_o) + if (n137_o) + n855_q <= 2'b00; + else + n855_q <= n854_o; + /* T65.vhd:252:17 */ + assign n856_o = n268_o ? alu_op : alu_op_r; + /* T65.vhd:252:17 */ + always @(posedge Clk or posedge n137_o) + if (n137_o) + n857_q <= 4'b1100; + else + n857_q <= n856_o; + /* T65.vhd:252:17 */ + assign n858_o = n269_o ? write_data : write_data_r; + /* T65.vhd:252:17 */ + always @(posedge Clk or posedge n137_o) + if (n137_o) + n859_q <= 3'b000; + else + n859_q <= n858_o; + /* T65.vhd:252:17 */ + assign n860_o = n270_o ? n156_o : set_addr_to_r; + /* T65.vhd:252:17 */ + always @(posedge Clk or posedge n137_o) + if (n137_o) + n861_q <= 2'b00; + else + n861_q <= n860_o; + /* T65.vhd:536:17 */ + assign n862_o = n789_o ? 1'b0 : rstcycle; + /* T65.vhd:536:17 */ + always @(posedge Clk or posedge n751_o) + if (n751_o) + n863_q <= 1'b1; + else + n863_q <= n862_o; + /* T65.vhd:536:17 */ + assign n864_o = n790_o ? n763_o : irqcycle; + /* T65.vhd:536:17 */ + always @(posedge Clk or posedge n751_o) + if (n751_o) + n865_q <= 1'b0; + else + n865_q <= n864_o; + /* T65.vhd:536:17 */ + assign n866_o = n791_o ? n767_o : nmicycle; + /* T65.vhd:536:17 */ + always @(posedge Clk or posedge n751_o) + if (n751_o) + n867_q <= 1'b0; + else + n867_q <= n866_o; + /* T65.vhd:331:17 */ + assign n870_o = n562_o ? SO_n : so_n_o; + /* T65.vhd:331:17 */ + always @(posedge Clk) + n871_q <= n870_o; + /* T65.vhd:331:17 */ + assign n872_o = n563_o ? IRQ_n : irq_n_o; + /* T65.vhd:331:17 */ + always @(posedge Clk) + n873_q <= n872_o; + /* T65.vhd:331:17 */ + assign n874_o = n564_o ? NMI_n : nmi_n_o; + /* T65.vhd:331:17 */ + always @(posedge Clk) + n875_q <= n874_o; + /* T65.vhd:536:17 */ + assign n876_o = n792_o ? n782_o : nmiact; + /* T65.vhd:536:17 */ + always @(posedge Clk or posedge n751_o) + if (n751_o) + n877_q <= 1'b0; + else + n877_q <= n876_o; + /* T65.vhd:427:17 */ + assign n878_o = n658_o ? busa : busa_r; + /* T65.vhd:427:17 */ + always @(posedge Clk or posedge n579_o) + if (n579_o) + n879_q <= 8'b00000000; + else + n879_q <= n878_o; + /* T65.vhd:427:17 */ + assign n880_o = n659_o ? DI : busb; + /* T65.vhd:427:17 */ + always @(posedge Clk or posedge n579_o) + if (n579_o) + n881_q <= 8'b00000000; + else + n881_q <= n880_o; + /* T65.vhd:252:17 */ + assign n882_o = n271_o ? n140_o : r_w_n_i; + /* T65.vhd:252:17 */ + always @(posedge Clk or posedge n137_o) + if (n137_o) + n883_q <= 1'b1; + else + n883_q <= n882_o; +endmodule + diff --git a/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/t80/T80.vhd b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/t80/T80.vhd new file mode 100644 index 0000000000000000000000000000000000000000..293bc43d69600ddc3f063a910febbd21fe2ee7f6 --- /dev/null +++ b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/t80/T80.vhd @@ -0,0 +1,1298 @@ +-------------------------------------------------------------------------------- +-- **** +-- T80(c) core. Attempt to finish all undocumented features and provide +-- accurate timings. +-- Version 350. +-- Copyright (c) 2018 Sorgelig +-- Test passed: ZEXDOC, ZEXALL, Z80Full(*), Z80memptr +-- (*) Currently only SCF and CCF instructions aren't passed X/Y flags check as +-- correct implementation is still unclear. +-- +-- **** +-- T80(b) core. In an effort to merge and maintain bug fixes .... +-- +-- Ver 303 add undocumented DDCB and FDCB opcodes by TobiFlex 20.04.2010 +-- Ver 301 parity flag is just parity for 8080, also overflow for Z80, by Sean Riddle +-- Ver 300 started tidyup. +-- +-- MikeJ March 2005 +-- Latest version from www.fpgaarcade.com (original www.opencores.org) +-- +-- **** +-- Z80 compatible microprocessor core +-- +-- Version : 0247 +-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.opencores.org/cvsweb.shtml/t80/ +-- +-- Limitations : +-- +-- File history : +-- +-- 0208 : First complete release +-- 0210 : Fixed wait and halt +-- 0211 : Fixed Refresh addition and IM 1 +-- 0214 : Fixed mostly flags, only the block instructions now fail the zex regression test +-- 0232 : Removed refresh address output for Mode > 1 and added DJNZ M1_n fix by Mike Johnson +-- 0235 : Added clock enable and IM 2 fix by Mike Johnson +-- 0237 : Changed 8080 I/O address output, added IntE output +-- 0238 : Fixed (IX/IY+d) timing and 16 bit ADC and SBC zero flag +-- 0240 : Added interrupt ack fix by Mike Johnson, changed (IX/IY+d) timing and changed flags in GB mode +-- 0242 : Added I/O wait, fixed refresh address, moved some registers to RAM +-- 0247 : Fixed bus req/ack cycle +-- + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; +use IEEE.STD_LOGIC_UNSIGNED.all; + +use work.all; + +entity T80 is + generic( + Mode : integer := 0; -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB + IOWait : integer := 0; -- 0 => Single cycle I/O, 1 => Std I/O cycle + Flag_C : integer := 0; + Flag_N : integer := 1; + Flag_P : integer := 2; + Flag_X : integer := 3; + Flag_H : integer := 4; + Flag_Y : integer := 5; + Flag_Z : integer := 6; + Flag_S : integer := 7 + ); + port( + RESET_n : in std_logic; + CLK_n : in std_logic; + CEN : in std_logic; + WAIT_n : in std_logic; + INT_n : in std_logic; + NMI_n : in std_logic; + BUSRQ_n : in std_logic; + M1_n : out std_logic; + IORQ : out std_logic; + NoRead : out std_logic; + Write : out std_logic; + RFSH_n : out std_logic; + HALT_n : out std_logic; + BUSAK_n : out std_logic; + A : out std_logic_vector(15 downto 0); + DInst : in std_logic_vector(7 downto 0); + DI : in std_logic_vector(7 downto 0); + DOUT : out std_logic_vector(7 downto 0); + MC : out std_logic_vector(2 downto 0); + TS : out std_logic_vector(2 downto 0); + IntCycle_n : out std_logic; + IntE : out std_logic; + Stop : out std_logic; + out0 : in std_logic := '0'; -- 0 => OUT(C),0, 1 => OUT(C),255 + REGS : out std_logic_vector(211 downto 0); -- IFF2, IFF1, IM, IY, HL', DE', BC', IX, HL, DE, BC, PC, SP, R, I, F', A', F, A + + DIRSet : in std_logic := '0'; + DIR : in std_logic_vector(211 downto 0) := (others => '0') -- IFF2, IFF1, IM, IY, HL', DE', BC', IX, HL, DE, BC, PC, SP, R, I, F', A', F, A + ); +end T80; + +architecture rtl of T80 is + component T80_MCode + generic( + Mode : integer := 0; + Flag_C : integer := 0; + Flag_N : integer := 1; + Flag_P : integer := 2; + Flag_X : integer := 3; + Flag_H : integer := 4; + Flag_Y : integer := 5; + Flag_Z : integer := 6; + Flag_S : integer := 7 + ); + port( + IR : in std_logic_vector(7 downto 0); + ISet : in std_logic_vector(1 downto 0); + MCycle : in std_logic_vector(2 downto 0); + F : in std_logic_vector(7 downto 0); + NMICycle : in std_logic; + IntCycle : in std_logic; + XY_State : in std_logic_vector(1 downto 0); + MCycles : out std_logic_vector(2 downto 0); + TStates : out std_logic_vector(2 downto 0); + Prefix : out std_logic_vector(1 downto 0); -- None,CB,ED,DD/FD + Inc_PC : out std_logic; + Inc_WZ : out std_logic; + IncDec_16 : out std_logic_vector(3 downto 0); -- BC,DE,HL,SP 0 is inc + Read_To_Reg : out std_logic; + Read_To_Acc : out std_logic; + Set_BusA_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI/DB,A,SP(L),SP(M),0,F + Set_BusB_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI,A,SP(L),SP(M),1,F,PC(L),PC(M),0 + ALU_Op : out std_logic_vector(3 downto 0); + -- ADD, ADC, SUB, SBC, AND, XOR, OR, CP, ROT, BIT, SET, RES, DAA, RLD, RRD, None + Save_ALU : out std_logic; + PreserveC : out std_logic; + Arith16 : out std_logic; + Set_Addr_To : out std_logic_vector(2 downto 0); -- aNone,aXY,aIOA,aSP,aBC,aDE,aZI + IORQ : out std_logic; + Jump : out std_logic; + JumpE : out std_logic; + JumpXY : out std_logic; + Call : out std_logic; + RstP : out std_logic; + LDZ : out std_logic; + LDW : out std_logic; + LDSPHL : out std_logic; + Special_LD : out std_logic_vector(2 downto 0); -- A,I;A,R;I,A;R,A;None + ExchangeDH : out std_logic; + ExchangeRp : out std_logic; + ExchangeAF : out std_logic; + ExchangeRS : out std_logic; + I_DJNZ : out std_logic; + I_CPL : out std_logic; + I_CCF : out std_logic; + I_SCF : out std_logic; + I_RETN : out std_logic; + I_BT : out std_logic; + I_BC : out std_logic; + I_BTR : out std_logic; + I_RLD : out std_logic; + I_RRD : out std_logic; + I_INRC : out std_logic; + SetWZ : out std_logic_vector(1 downto 0); + SetDI : out std_logic; + SetEI : out std_logic; + IMode : out std_logic_vector(1 downto 0); + Halt : out std_logic; + NoRead : out std_logic; + Write : out std_logic; + XYbit_undoc : out std_logic + ); + end component; + + component T80_ALU + generic( + Mode : integer := 0; + Flag_C : integer := 0; + Flag_N : integer := 1; + Flag_P : integer := 2; + Flag_X : integer := 3; + Flag_H : integer := 4; + Flag_Y : integer := 5; + Flag_Z : integer := 6; + Flag_S : integer := 7 + ); + port( + Arith16 : in std_logic; + Z16 : in std_logic; + WZ : in std_logic_vector(15 downto 0); + XY_State : in std_logic_vector(1 downto 0); + ALU_Op : in std_logic_vector(3 downto 0); + IR : in std_logic_vector(5 downto 0); + ISet : in std_logic_vector(1 downto 0); + BusA : in std_logic_vector(7 downto 0); + BusB : in std_logic_vector(7 downto 0); + F_In : in std_logic_vector(7 downto 0); + Q : out std_logic_vector(7 downto 0); + F_Out : out std_logic_vector(7 downto 0) + ); + end component; + + component T80_Reg + port( + Clk : in std_logic; + CEN : in std_logic; + WEH : in std_logic; + WEL : in std_logic; + AddrA : in std_logic_vector(2 downto 0); + AddrB : in std_logic_vector(2 downto 0); + AddrC : in std_logic_vector(2 downto 0); + DIH : in std_logic_vector(7 downto 0); + DIL : in std_logic_vector(7 downto 0); + DOAH : out std_logic_vector(7 downto 0); + DOAL : out std_logic_vector(7 downto 0); + DOBH : out std_logic_vector(7 downto 0); + DOBL : out std_logic_vector(7 downto 0); + DOCH : out std_logic_vector(7 downto 0); + DOCL : out std_logic_vector(7 downto 0); + DOR : out std_logic_vector(127 downto 0); + DIRSet : in std_logic; + DIR : in std_logic_vector(127 downto 0) + ); + end component; + + constant aNone : std_logic_vector(2 downto 0) := "111"; + constant aBC : std_logic_vector(2 downto 0) := "000"; + constant aDE : std_logic_vector(2 downto 0) := "001"; + constant aXY : std_logic_vector(2 downto 0) := "010"; + constant aIOA : std_logic_vector(2 downto 0) := "100"; + constant aSP : std_logic_vector(2 downto 0) := "101"; + constant aZI : std_logic_vector(2 downto 0) := "110"; + + -- Registers + signal ACC, F : std_logic_vector(7 downto 0); + signal Ap, Fp : std_logic_vector(7 downto 0); + signal I : std_logic_vector(7 downto 0); + signal R : unsigned(7 downto 0); + signal SP, PC : unsigned(15 downto 0); + + signal RegDIH : std_logic_vector(7 downto 0); + signal RegDIL : std_logic_vector(7 downto 0); + signal RegBusA : std_logic_vector(15 downto 0); + signal RegBusB : std_logic_vector(15 downto 0); + signal RegBusC : std_logic_vector(15 downto 0); + signal RegAddrA_r : std_logic_vector(2 downto 0); + signal RegAddrA : std_logic_vector(2 downto 0); + signal RegAddrB_r : std_logic_vector(2 downto 0); + signal RegAddrB : std_logic_vector(2 downto 0); + signal RegAddrC : std_logic_vector(2 downto 0); + signal RegWEH : std_logic; + signal RegWEL : std_logic; + signal Alternate : std_logic; + + -- Help Registers + signal WZ : std_logic_vector(15 downto 0); -- MEMPTR register + signal IR : std_logic_vector(7 downto 0); -- Instruction register + signal ISet : std_logic_vector(1 downto 0); -- Instruction set selector + signal RegBusA_r : std_logic_vector(15 downto 0); + + signal ID16 : signed(15 downto 0); + signal Save_Mux : std_logic_vector(7 downto 0); + + signal TState : unsigned(2 downto 0); + signal MCycle : std_logic_vector(2 downto 0); + signal IntE_FF1 : std_logic; + signal IntE_FF2 : std_logic; + signal Halt_FF : std_logic; + signal BusReq_s : std_logic; + signal BusAck : std_logic; + signal ClkEn : std_logic; + signal NMI_s : std_logic; + signal IStatus : std_logic_vector(1 downto 0); + + signal DI_Reg : std_logic_vector(7 downto 0); + signal T_Res : std_logic; + signal XY_State : std_logic_vector(1 downto 0); + signal Pre_XY_F_M : std_logic_vector(2 downto 0); + signal NextIs_XY_Fetch : std_logic; + signal XY_Ind : std_logic; + signal No_BTR : std_logic; + signal BTR_r : std_logic; + signal Auto_Wait : std_logic; + signal Auto_Wait_t1 : std_logic; + signal Auto_Wait_t2 : std_logic; + signal IncDecZ : std_logic; + + -- ALU signals + signal BusB : std_logic_vector(7 downto 0); + signal BusA : std_logic_vector(7 downto 0); + signal ALU_Q : std_logic_vector(7 downto 0); + signal F_Out : std_logic_vector(7 downto 0); + + -- Registered micro code outputs + signal Read_To_Reg_r : std_logic_vector(4 downto 0); + signal Arith16_r : std_logic; + signal Z16_r : std_logic; + signal ALU_Op_r : std_logic_vector(3 downto 0); + signal Save_ALU_r : std_logic; + signal PreserveC_r : std_logic; + signal MCycles : std_logic_vector(2 downto 0); + + -- Micro code outputs + signal MCycles_d : std_logic_vector(2 downto 0); + signal TStates : std_logic_vector(2 downto 0); + signal IntCycle : std_logic; + signal NMICycle : std_logic; + signal Inc_PC : std_logic; + signal Inc_WZ : std_logic; + signal IncDec_16 : std_logic_vector(3 downto 0); + signal Prefix : std_logic_vector(1 downto 0); + signal Read_To_Acc : std_logic; + signal Read_To_Reg : std_logic; + signal Set_BusB_To : std_logic_vector(3 downto 0); + signal Set_BusA_To : std_logic_vector(3 downto 0); + signal ALU_Op : std_logic_vector(3 downto 0); + signal Save_ALU : std_logic; + signal PreserveC : std_logic; + signal Arith16 : std_logic; + signal Set_Addr_To : std_logic_vector(2 downto 0); + signal Jump : std_logic; + signal JumpE : std_logic; + signal JumpXY : std_logic; + signal Call : std_logic; + signal RstP : std_logic; + signal LDZ : std_logic; + signal LDW : std_logic; + signal LDSPHL : std_logic; + signal IORQ_i : std_logic; + signal Special_LD : std_logic_vector(2 downto 0); + signal ExchangeDH : std_logic; + signal ExchangeRp : std_logic; + signal ExchangeAF : std_logic; + signal ExchangeRS : std_logic; + signal I_DJNZ : std_logic; + signal I_CPL : std_logic; + signal I_CCF : std_logic; + signal I_SCF : std_logic; + signal I_RETN : std_logic; + signal I_BT : std_logic; + signal I_BC : std_logic; + signal I_BTR : std_logic; + signal I_RLD : std_logic; + signal I_RRD : std_logic; + signal I_RXDD : std_logic; + signal I_INRC : std_logic; + signal SetWZ : std_logic_vector(1 downto 0); + signal SetDI : std_logic; + signal SetEI : std_logic; + signal IMode : std_logic_vector(1 downto 0); + signal Halt : std_logic; + signal XYbit_undoc : std_logic; + signal DOR : std_logic_vector(127 downto 0); + +begin + + REGS <= IntE_FF2 & IntE_FF1 & IStatus & DOR & std_logic_vector(PC) & std_logic_vector(SP) & std_logic_vector(R) & I & Fp & Ap & F & ACC when Alternate = '0' + else IntE_FF2 & IntE_FF1 & IStatus & DOR(127 downto 112) & DOR(47 downto 0) & DOR(63 downto 48) & DOR(111 downto 64) & + std_logic_vector(PC) & std_logic_vector(SP) & std_logic_vector(R) & I & Fp & Ap & F & ACC; + + mcode : T80_MCode + generic map( + Mode => Mode, + Flag_C => Flag_C, + Flag_N => Flag_N, + Flag_P => Flag_P, + Flag_X => Flag_X, + Flag_H => Flag_H, + Flag_Y => Flag_Y, + Flag_Z => Flag_Z, + Flag_S => Flag_S) + port map( + IR => IR, + ISet => ISet, + MCycle => MCycle, + F => F, + NMICycle => NMICycle, + IntCycle => IntCycle, + XY_State => XY_State, + MCycles => MCycles_d, + TStates => TStates, + Prefix => Prefix, + Inc_PC => Inc_PC, + Inc_WZ => Inc_WZ, + IncDec_16 => IncDec_16, + Read_To_Acc => Read_To_Acc, + Read_To_Reg => Read_To_Reg, + Set_BusB_To => Set_BusB_To, + Set_BusA_To => Set_BusA_To, + ALU_Op => ALU_Op, + Save_ALU => Save_ALU, + PreserveC => PreserveC, + Arith16 => Arith16, + Set_Addr_To => Set_Addr_To, + IORQ => IORQ_i, + Jump => Jump, + JumpE => JumpE, + JumpXY => JumpXY, + Call => Call, + RstP => RstP, + LDZ => LDZ, + LDW => LDW, + LDSPHL => LDSPHL, + Special_LD => Special_LD, + ExchangeDH => ExchangeDH, + ExchangeRp => ExchangeRp, + ExchangeAF => ExchangeAF, + ExchangeRS => ExchangeRS, + I_DJNZ => I_DJNZ, + I_CPL => I_CPL, + I_CCF => I_CCF, + I_SCF => I_SCF, + I_RETN => I_RETN, + I_BT => I_BT, + I_BC => I_BC, + I_BTR => I_BTR, + I_RLD => I_RLD, + I_RRD => I_RRD, + I_INRC => I_INRC, + SetWZ => SetWZ, + SetDI => SetDI, + SetEI => SetEI, + IMode => IMode, + Halt => Halt, + NoRead => NoRead, + Write => Write, + XYbit_undoc => XYbit_undoc); + + u_alu : T80_ALU + generic map( + Mode => Mode, + Flag_C => Flag_C, + Flag_N => Flag_N, + Flag_P => Flag_P, + Flag_X => Flag_X, + Flag_H => Flag_H, + Flag_Y => Flag_Y, + Flag_Z => Flag_Z, + Flag_S => Flag_S) + port map( + Arith16 => Arith16_r, + Z16 => Z16_r, + WZ => WZ, + XY_State=> XY_State, + ALU_Op => ALU_Op_r, + IR => IR(5 downto 0), + ISet => ISet, + BusA => BusA, + BusB => BusB, + F_In => F, + Q => ALU_Q, + F_Out => F_Out); + + ClkEn <= CEN and not BusAck; + + T_Res <= '1' when TState = unsigned(TStates) else '0'; + + NextIs_XY_Fetch <= '1' when XY_State /= "00" and XY_Ind = '0' and + ((Set_Addr_To = aXY) or + (MCycle = "001" and IR = "11001011") or + (MCycle = "001" and IR = "00110110")) else '0'; + + Save_Mux <= BusB when ExchangeRp = '1' else + DI_Reg when Save_ALU_r = '0' else + ALU_Q; + + process (RESET_n, CLK_n) + variable n : std_logic_vector(7 downto 0); + variable ioq : std_logic_vector(8 downto 0); + begin + if RESET_n = '0' then + PC <= (others => '0'); -- Program Counter + A <= (others => '0'); + WZ <= (others => '0'); + IR <= "00000000"; + ISet <= "00"; + XY_State <= "00"; + IStatus <= "00"; + MCycles <= "000"; + DOUT <= "00000000"; + + ACC <= (others => '1'); + F <= (others => '1'); + Ap <= (others => '1'); + Fp <= (others => '1'); + I <= (others => '0'); + R <= (others => '0'); + SP <= (others => '1'); + Alternate <= '0'; + + Read_To_Reg_r <= "00000"; + Arith16_r <= '0'; + BTR_r <= '0'; + Z16_r <= '0'; + ALU_Op_r <= "0000"; + Save_ALU_r <= '0'; + PreserveC_r <= '0'; + XY_Ind <= '0'; + I_RXDD <= '0'; + + elsif rising_edge(CLK_n) then + + if DIRSet = '1' then + ACC <= DIR( 7 downto 0); + F <= DIR(15 downto 8); + Ap <= DIR(23 downto 16); + Fp <= DIR(31 downto 24); + I <= DIR(39 downto 32); + R <= unsigned(DIR(47 downto 40)); + SP <= unsigned(DIR(63 downto 48)); + PC <= unsigned(DIR(79 downto 64)); + A <= DIR(79 downto 64); + IStatus <= DIR(209 downto 208); + + elsif ClkEn = '1' then + ALU_Op_r <= "0000"; + Save_ALU_r <= '0'; + Read_To_Reg_r <= "00000"; + + MCycles <= MCycles_d; + + if IMode /= "11" then + IStatus <= IMode; + end if; + + Arith16_r <= Arith16; + PreserveC_r <= PreserveC; + if ISet = "10" and ALU_OP(2) = '0' and ALU_OP(0) = '1' and MCycle = "011" then + Z16_r <= '1'; + else + Z16_r <= '0'; + end if; + + if MCycle = "001" and TState(2) = '0' then + -- MCycle = 1 and TState = 1, 2, or 3 + + if TState = 2 and Wait_n = '1' then + if Mode < 2 then + A(7 downto 0) <= std_logic_vector(R); + A(15 downto 8) <= I; + R(6 downto 0) <= R(6 downto 0) + 1; + end if; + + if Jump = '0' and Call = '0' and NMICycle = '0' and IntCycle = '0' and not (Halt_FF = '1' or Halt = '1') then + PC <= PC + 1; + end if; + + if IntCycle = '1' and IStatus = "01" then + IR <= "11111111"; + elsif Halt_FF = '1' or (IntCycle = '1' and IStatus = "10") or NMICycle = '1' then + IR <= "00000000"; + else + IR <= DInst; + end if; + + ISet <= "00"; + if Prefix /= "00" then + if Prefix = "11" then + if IR(5) = '1' then + XY_State <= "10"; + else + XY_State <= "01"; + end if; + else + if Prefix = "10" then + XY_State <= "00"; + XY_Ind <= '0'; + end if; + ISet <= Prefix; + end if; + else + XY_State <= "00"; + XY_Ind <= '0'; + end if; + end if; + + else + -- either (MCycle > 1) OR (MCycle = 1 AND TState > 3) + + if MCycle = "110" then + XY_Ind <= '1'; + if Prefix = "01" then + ISet <= "01"; + end if; + end if; + + if T_Res = '1' then + BTR_r <= (I_BT or I_BC or I_BTR) and not No_BTR; + if Jump = '1' then + A(15 downto 8) <= DI_Reg; + A(7 downto 0) <= WZ(7 downto 0); + PC(15 downto 8) <= unsigned(DI_Reg); + PC(7 downto 0) <= unsigned(WZ(7 downto 0)); + elsif JumpXY = '1' then + A <= RegBusC; + PC <= unsigned(RegBusC); + elsif Call = '1' or RstP = '1' then + A <= WZ; + PC <= unsigned(WZ); + elsif MCycle = MCycles and NMICycle = '1' then + A <= "0000000001100110"; + PC <= "0000000001100110"; + elsif MCycle = "011" and IntCycle = '1' and IStatus = "10" then + A(15 downto 8) <= I; + A(7 downto 0) <= WZ(7 downto 0); + PC(15 downto 8) <= unsigned(I); + PC(7 downto 0) <= unsigned(WZ(7 downto 0)); + else + case Set_Addr_To is + when aXY => + if XY_State = "00" then + A <= RegBusC; + else + if NextIs_XY_Fetch = '1' then + A <= std_logic_vector(PC); + else + A <= WZ; + end if; + end if; + when aIOA => + if Mode = 3 then + -- Memory map I/O on GBZ80 + A(15 downto 8) <= (others => '1'); + elsif Mode = 2 then + -- Duplicate I/O address on 8080 + A(15 downto 8) <= DI_Reg; + else + A(15 downto 8) <= ACC; + end if; + A(7 downto 0) <= DI_Reg; + WZ <= (ACC & DI_Reg) + "1"; + when aSP => + A <= std_logic_vector(SP); + when aBC => + if Mode = 3 and IORQ_i = '1' then + -- Memory map I/O on GBZ80 + A(15 downto 8) <= (others => '1'); + A(7 downto 0) <= RegBusC(7 downto 0); + else + A <= RegBusC; + if SetWZ = "01" then + WZ <= RegBusC + "1"; + end if; + if SetWZ = "10" then + WZ(7 downto 0) <= RegBusC(7 downto 0) + "1"; + WZ(15 downto 8) <= ACC; + end if; + end if; + when aDE => + A <= RegBusC; + if SetWZ = "10" then + WZ(7 downto 0) <= RegBusC(7 downto 0) + "1"; + WZ(15 downto 8) <= ACC; + end if; + when aZI => + if Inc_WZ = '1' then + A <= std_logic_vector(unsigned(WZ) + 1); + else + A(15 downto 8) <= DI_Reg; + A(7 downto 0) <= WZ(7 downto 0); + if SetWZ = "10" then + WZ(7 downto 0) <= WZ(7 downto 0) + "1"; + WZ(15 downto 8) <= ACC; + end if; + end if; + when others => + A <= std_logic_vector(PC); + end case; + end if; + + if SetWZ = "11" then + WZ <= std_logic_vector(ID16); + end if; + + Save_ALU_r <= Save_ALU; + ALU_Op_r <= ALU_Op; + + if I_CPL = '1' then + -- CPL + ACC <= not ACC; + F(Flag_Y) <= not ACC(5); + F(Flag_H) <= '1'; + F(Flag_X) <= not ACC(3); + F(Flag_N) <= '1'; + end if; + if I_CCF = '1' then + -- CCF + F(Flag_C) <= not F(Flag_C); + F(Flag_Y) <= ACC(5); + F(Flag_H) <= F(Flag_C); + F(Flag_X) <= ACC(3); + F(Flag_N) <= '0'; + end if; + if I_SCF = '1' then + -- SCF + F(Flag_C) <= '1'; + F(Flag_Y) <= ACC(5); + F(Flag_H) <= '0'; + F(Flag_X) <= ACC(3); + F(Flag_N) <= '0'; + end if; + end if; + + if (TState = 2 and I_BTR = '1' and IR(0) = '1') or (TState = 1 and I_BTR = '1' and IR(0) = '0') then + ioq := ('0' & DI_Reg) + ('0' & std_logic_vector(ID16(7 downto 0))); + F(Flag_N) <= DI_Reg(7); + F(Flag_C) <= ioq(8); + F(Flag_H) <= ioq(8); + ioq := (ioq and ('0' & x"07")) xor ('0'&BusA); + F(Flag_P) <= not (ioq(0) xor ioq(1) xor ioq(2) xor ioq(3) xor ioq(4) xor ioq(5) xor ioq(6) xor ioq(7)); + end if; + + if TState = 2 and Wait_n = '1' then + if ISet = "01" and MCycle = "111" then + IR <= DInst; + end if; + if JumpE = '1' then + PC <= unsigned(signed(PC) + signed(DI_Reg)); + WZ <= std_logic_vector(signed(PC) + signed(DI_Reg)); + elsif Inc_PC = '1' then + PC <= PC + 1; + end if; + if BTR_r = '1' then + PC <= PC - 2; + end if; + if RstP = '1' then + WZ <= (others =>'0'); + WZ(5 downto 3) <= IR(5 downto 3); + end if; + end if; + if TState = 3 and MCycle = "110" then + WZ <= std_logic_vector(signed(RegBusC) + signed(DI_Reg)); + end if; + + if MCycle = "011" and TState = 4 and No_BTR = '0' then + if I_BT = '1' or I_BC = '1' then + WZ <= std_logic_vector(PC)-"1"; + end if; + end if; + + if (TState = 2 and Wait_n = '1') or (TState = 4 and MCycle = "001") then + if IncDec_16(2 downto 0) = "111" then + if IncDec_16(3) = '1' then + SP <= SP - 1; + else + SP <= SP + 1; + end if; + end if; + end if; + + if LDSPHL = '1' then + SP <= unsigned(RegBusC); + end if; + if ExchangeAF = '1' then + Ap <= ACC; + ACC <= Ap; + Fp <= F; + F <= Fp; + end if; + if ExchangeRS = '1' then + Alternate <= not Alternate; + end if; + end if; + + if TState = 3 then + if LDZ = '1' then + WZ(7 downto 0) <= DI_Reg; + end if; + if LDW = '1' then + WZ(15 downto 8) <= DI_Reg; + end if; + + if Special_LD(2) = '1' then + case Special_LD(1 downto 0) is + when "00" => + ACC <= I; + F(Flag_P) <= IntE_FF2; + F(Flag_S) <= I(7); + + if I = x"00" then + F(Flag_Z) <= '1'; + else + F(Flag_Z) <= '0'; + end if; + + F(Flag_Y) <= I(5); + F(Flag_H) <= '0'; + F(Flag_X) <= I(3); + F(Flag_N) <= '0'; + + + when "01" => + ACC <= std_logic_vector(R); + F(Flag_P) <= IntE_FF2; + F(Flag_S) <= R(7); + + if R = x"00" then + F(Flag_Z) <= '1'; + else + F(Flag_Z) <= '0'; + end if; + + F(Flag_Y) <= R(5); + F(Flag_H) <= '0'; + F(Flag_X) <= R(3); + F(Flag_N) <= '0'; + + when "10" => + I <= ACC; + when others => + R <= unsigned(ACC); + end case; + end if; + end if; + + if (I_DJNZ = '0' and Save_ALU_r = '1') or ALU_Op_r = "1001" then + if Mode = 3 then + F(6) <= F_Out(6); + F(5) <= F_Out(5); + F(7) <= F_Out(7); + if PreserveC_r = '0' then + F(4) <= F_Out(4); + end if; + else + F(7 downto 1) <= F_Out(7 downto 1); + if PreserveC_r = '0' then + F(Flag_C) <= F_Out(0); + end if; + end if; + end if; + if T_Res = '1' and I_INRC = '1' then + F(Flag_H) <= '0'; + F(Flag_N) <= '0'; + F(Flag_X) <= DI_Reg(3); + F(Flag_Y) <= DI_Reg(5); + if DI_Reg(7 downto 0) = "00000000" then + F(Flag_Z) <= '1'; + else + F(Flag_Z) <= '0'; + end if; + F(Flag_S) <= DI_Reg(7); + F(Flag_P) <= not (DI_Reg(0) xor DI_Reg(1) xor DI_Reg(2) xor DI_Reg(3) xor + DI_Reg(4) xor DI_Reg(5) xor DI_Reg(6) xor DI_Reg(7)); + end if; + + if TState = 1 and Auto_Wait_t1 = '0' then + -- Keep D0 from M3 for RLD/RRD (Sorgelig) + I_RXDD <= I_RLD or I_RRD; + if I_RXDD='0' then + DOUT <= BusB; + end if; + if I_RLD = '1' then + DOUT(3 downto 0) <= BusA(3 downto 0); + DOUT(7 downto 4) <= BusB(3 downto 0); + end if; + if I_RRD = '1' then + DOUT(3 downto 0) <= BusB(7 downto 4); + DOUT(7 downto 4) <= BusA(3 downto 0); + end if; + end if; + + if T_Res = '1' then + Read_To_Reg_r(3 downto 0) <= Set_BusA_To; + Read_To_Reg_r(4) <= Read_To_Reg; + if Read_To_Acc = '1' then + Read_To_Reg_r(3 downto 0) <= "0111"; + Read_To_Reg_r(4) <= '1'; + end if; + end if; + + if TState = 1 and I_BT = '1' then + F(Flag_X) <= ALU_Q(3); + F(Flag_Y) <= ALU_Q(1); + F(Flag_H) <= '0'; + F(Flag_N) <= '0'; + end if; + if TState = 1 and I_BC = '1' then + n := ALU_Q - ("0000000" & F_Out(Flag_H)); + F(Flag_X) <= n(3); + F(Flag_Y) <= n(1); + end if; + if I_BC = '1' or I_BT = '1' then + F(Flag_P) <= IncDecZ; + end if; + + if (TState = 1 and Save_ALU_r = '0' and Auto_Wait_t1 = '0') or + (Save_ALU_r = '1' and ALU_OP_r /= "0111") then + case Read_To_Reg_r is + when "10111" => + ACC <= Save_Mux; + when "10110" => + DOUT <= Save_Mux; + when "11000" => + SP(7 downto 0) <= unsigned(Save_Mux); + when "11001" => + SP(15 downto 8) <= unsigned(Save_Mux); + when "11011" => + F <= Save_Mux; + when others => + end case; + if XYbit_undoc='1' then + DOUT <= ALU_Q; + end if; + end if; + end if; + end if; + end process; + +--------------------------------------------------------------------------- +-- +-- BC('), DE('), HL('), IX and IY +-- +--------------------------------------------------------------------------- + process (CLK_n) + begin + if rising_edge(CLK_n) then + if ClkEn = '1' then + -- Bus A / Write + RegAddrA_r <= Alternate & Set_BusA_To(2 downto 1); + if XY_Ind = '0' and XY_State /= "00" and Set_BusA_To(2 downto 1) = "10" then + RegAddrA_r <= XY_State(1) & "11"; + end if; + + -- Bus B + RegAddrB_r <= Alternate & Set_BusB_To(2 downto 1); + if XY_Ind = '0' and XY_State /= "00" and Set_BusB_To(2 downto 1) = "10" then + RegAddrB_r <= XY_State(1) & "11"; + end if; + + -- Address from register + RegAddrC <= Alternate & Set_Addr_To(1 downto 0); + -- Jump (HL), LD SP,HL + if (JumpXY = '1' or LDSPHL = '1') then + RegAddrC <= Alternate & "10"; + end if; + if ((JumpXY = '1' or LDSPHL = '1') and XY_State /= "00") or (MCycle = "110") then + RegAddrC <= XY_State(1) & "11"; + end if; + + if I_DJNZ = '1' and Save_ALU_r = '1' and Mode < 2 then + IncDecZ <= F_Out(Flag_Z); + end if; + if (TState = 2 or (TState = 3 and MCycle = "001")) and IncDec_16(2 downto 0) = "100" then + if ID16 = 0 then + IncDecZ <= '0'; + else + IncDecZ <= '1'; + end if; + end if; + + RegBusA_r <= RegBusA; + end if; + end if; + end process; + + RegAddrA <= + -- 16 bit increment/decrement + Alternate & IncDec_16(1 downto 0) when (TState = 2 or + (TState = 3 and MCycle = "001" and IncDec_16(2) = '1')) and XY_State = "00" else + XY_State(1) & "11" when (TState = 2 or + (TState = 3 and MCycle = "001" and IncDec_16(2) = '1')) and IncDec_16(1 downto 0) = "10" else + -- EX HL,DL + Alternate & "10" when ExchangeDH = '1' and TState = 3 else + Alternate & "01" when ExchangeDH = '1' and TState = 4 else + -- Bus A / Write + RegAddrA_r; + + RegAddrB <= + -- EX HL,DL + Alternate & "01" when ExchangeDH = '1' and TState = 3 else + -- Bus B + RegAddrB_r; + + ID16 <= signed(RegBusA) - 1 when IncDec_16(3) = '1' else + signed(RegBusA) + 1; + + process (Save_ALU_r, Auto_Wait_t1, ALU_OP_r, Read_To_Reg_r, + ExchangeDH, IncDec_16, MCycle, TState, Wait_n) + begin + RegWEH <= '0'; + RegWEL <= '0'; + if (TState = 1 and Save_ALU_r = '0' and Auto_Wait_t1 = '0') or + (Save_ALU_r = '1' and ALU_OP_r /= "0111") then + case Read_To_Reg_r is + when "10000" | "10001" | "10010" | "10011" | "10100" | "10101" => + RegWEH <= not Read_To_Reg_r(0); + RegWEL <= Read_To_Reg_r(0); + when others => + end case; + end if; + + if ExchangeDH = '1' and (TState = 3 or TState = 4) then + RegWEH <= '1'; + RegWEL <= '1'; + end if; + + if IncDec_16(2) = '1' and ((TState = 2 and Wait_n = '1' and MCycle /= "001") or (TState = 3 and MCycle = "001")) then + case IncDec_16(1 downto 0) is + when "00" | "01" | "10" => + RegWEH <= '1'; + RegWEL <= '1'; + when others => + end case; + end if; + end process; + + process (Save_Mux, RegBusB, RegBusA_r, ID16, + ExchangeDH, IncDec_16, MCycle, TState, Wait_n) + begin + RegDIH <= Save_Mux; + RegDIL <= Save_Mux; + + if ExchangeDH = '1' and TState = 3 then + RegDIH <= RegBusB(15 downto 8); + RegDIL <= RegBusB(7 downto 0); + end if; + if ExchangeDH = '1' and TState = 4 then + RegDIH <= RegBusA_r(15 downto 8); + RegDIL <= RegBusA_r(7 downto 0); + end if; + + if IncDec_16(2) = '1' and ((TState = 2 and MCycle /= "001") or (TState = 3 and MCycle = "001")) then + RegDIH <= std_logic_vector(ID16(15 downto 8)); + RegDIL <= std_logic_vector(ID16(7 downto 0)); + end if; + end process; + + u_Regs : T80_Reg + port map( + Clk => CLK_n, + CEN => ClkEn, + WEH => RegWEH, + WEL => RegWEL, + AddrA => RegAddrA, + AddrB => RegAddrB, + AddrC => RegAddrC, + DIH => RegDIH, + DIL => RegDIL, + DOAH => RegBusA(15 downto 8), + DOAL => RegBusA(7 downto 0), + DOBH => RegBusB(15 downto 8), + DOBL => RegBusB(7 downto 0), + DOCH => RegBusC(15 downto 8), + DOCL => RegBusC(7 downto 0), + DOR => DOR, + DIRSet => DIRSet, + DIR => DIR(207 downto 80)); + +--------------------------------------------------------------------------- +-- +-- Buses +-- +--------------------------------------------------------------------------- + process (CLK_n) + begin + if rising_edge(CLK_n) then + if ClkEn = '1' then + case Set_BusB_To is + when "0111" => + BusB <= ACC; + when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" => + if Set_BusB_To(0) = '1' then + BusB <= RegBusB(7 downto 0); + else + BusB <= RegBusB(15 downto 8); + end if; + when "0110" => + BusB <= DI_Reg; + when "1000" => + BusB <= std_logic_vector(SP(7 downto 0)); + when "1001" => + BusB <= std_logic_vector(SP(15 downto 8)); + when "1010" => + BusB <= "00000001"; + when "1011" => + BusB <= F; + when "1100" => + BusB <= std_logic_vector(PC(7 downto 0)); + when "1101" => + BusB <= std_logic_vector(PC(15 downto 8)); + when "1110" => + if IR = x"71" and out0 = '1' then + BusB <= "11111111"; + else + BusB <= "00000000"; + end if; + when others => + BusB <= "--------"; + end case; + + case Set_BusA_To is + when "0111" => + BusA <= ACC; + when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" => + if Set_BusA_To(0) = '1' then + BusA <= RegBusA(7 downto 0); + else + BusA <= RegBusA(15 downto 8); + end if; + when "0110" => + BusA <= DI_Reg; + when "1000" => + BusA <= std_logic_vector(SP(7 downto 0)); + when "1001" => + BusA <= std_logic_vector(SP(15 downto 8)); + when "1010" => + BusA <= "00000000"; + when others => + BusA <= "--------"; + end case; + if XYbit_undoc='1' then + BusA <= DI_Reg; + BusB <= DI_Reg; + end if; + end if; + end if; + end process; + +--------------------------------------------------------------------------- +-- +-- Generate external control signals +-- +--------------------------------------------------------------------------- + process (RESET_n,CLK_n) + begin + if RESET_n = '0' then + RFSH_n <= '1'; + elsif rising_edge(CLK_n) then + if DIRSet = '0' and CEN = '1' then + if MCycle = "001" and ((TState = 2 and Wait_n = '1') or TState = 3) then + RFSH_n <= '0'; + else + RFSH_n <= '1'; + end if; + end if; + end if; + end process; + + MC <= std_logic_vector(MCycle); + TS <= std_logic_vector(TState); + DI_Reg <= DI; + HALT_n <= not Halt_FF; + BUSAK_n <= not BusAck; + IntCycle_n <= not IntCycle; + IntE <= IntE_FF1; + IORQ <= IORQ_i; + Stop <= I_DJNZ; + +------------------------------------------------------------------------- +-- +-- Main state machine +-- +------------------------------------------------------------------------- + process (RESET_n, CLK_n) + variable OldNMI_n : std_logic; + begin + if RESET_n = '0' then + MCycle <= "001"; + TState <= "000"; + Pre_XY_F_M <= "000"; + Halt_FF <= '0'; + BusAck <= '0'; + NMICycle <= '0'; + IntCycle <= '0'; + IntE_FF1 <= '0'; + IntE_FF2 <= '0'; + No_BTR <= '0'; + Auto_Wait_t1 <= '0'; + Auto_Wait_t2 <= '0'; + M1_n <= '1'; + BusReq_s <= '0'; + NMI_s <= '0'; + elsif rising_edge(CLK_n) then + + if DIRSet = '1' then + IntE_FF2 <= DIR(211); + IntE_FF1 <= DIR(210); + else + if NMI_n = '0' and OldNMI_n = '1' then + NMI_s <= '1'; + end if; + OldNMI_n := NMI_n; + + if CEN = '1' then + BusReq_s <= not BUSRQ_n; + Auto_Wait_t2 <= Auto_Wait_t1; + if T_Res = '1' then + Auto_Wait_t1 <= '0'; + Auto_Wait_t2 <= '0'; + else + Auto_Wait_t1 <= Auto_Wait or IORQ_i; + end if; + No_BTR <= (I_BT and (not IR(4) or not F(Flag_P))) or + (I_BC and (not IR(4) or F(Flag_Z) or not F(Flag_P))) or + (I_BTR and (not IR(4) or F(Flag_Z))); + if TState = 2 then + if SetEI = '1' then + IntE_FF1 <= '1'; + IntE_FF2 <= '1'; + end if; + if I_RETN = '1' then + IntE_FF1 <= IntE_FF2; + end if; + end if; + if TState = 3 then + if SetDI = '1' then + IntE_FF1 <= '0'; + IntE_FF2 <= '0'; + end if; + end if; + if IntCycle = '1' or NMICycle = '1' then + Halt_FF <= '0'; + end if; + if MCycle = "001" and TState = 2 and Wait_n = '1' then + M1_n <= '1'; + end if; + if not ( BusReq_s = '1' and BusAck = '1' ) then + BusAck <= '0'; + if TState = 2 and Wait_n = '0' then + elsif T_Res = '1' then + if Halt = '1' then + Halt_FF <= '1'; + end if; + if BusReq_s = '1' then + BusAck <= '1'; + else + TState <= "001"; + if NextIs_XY_Fetch = '1' then + MCycle <= "110"; + Pre_XY_F_M <= MCycle; + if IR = "00110110" and Mode = 0 then + Pre_XY_F_M <= "010"; + end if; + elsif (MCycle = "111") or (MCycle = "110" and Mode = 1 and ISet /= "01") then + MCycle <= std_logic_vector(unsigned(Pre_XY_F_M) + 1); + elsif (MCycle = MCycles) or No_BTR = '1' or (MCycle = "010" and I_DJNZ = '1' and IncDecZ = '1') then + M1_n <= '0'; + MCycle <= "001"; + IntCycle <= '0'; + NMICycle <= '0'; + if NMI_s = '1' and Prefix = "00" then + NMI_s <= '0'; + NMICycle <= '1'; + IntE_FF1 <= '0'; + elsif IntE_FF1 = '1' and INT_n='0' and Prefix = "00" and SetEI = '0' then + IntCycle <= '1'; + IntE_FF1 <= '0'; + IntE_FF2 <= '0'; + end if; + else + MCycle <= std_logic_vector(unsigned(MCycle) + 1); + end if; + end if; + else + if (Auto_Wait = '1' and Auto_Wait_t2 = '0') nor + (IOWait = 1 and IORQ_i = '1' and Auto_Wait_t1 = '0') then + TState <= TState + 1; + end if; + end if; + end if; + if TState = 0 then + M1_n <= '0'; + end if; + end if; + end if; + end if; + end process; + + Auto_Wait <= '1' when IntCycle = '1' and MCycle = "001" else '0'; +end; diff --git a/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/t80/T80_ALU.vhd b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/t80/T80_ALU.vhd new file mode 100644 index 0000000000000000000000000000000000000000..a9438aedb99ba365c9051c38c41bb89a50bbe245 --- /dev/null +++ b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/t80/T80_ALU.vhd @@ -0,0 +1,376 @@ +-------------------------------------------------------------------------------- +-- **** +-- T80(c) core. Attempt to finish all undocumented features and provide +-- accurate timings. +-- Version 350. +-- Copyright (c) 2018 Sorgelig +-- Test passed: ZEXDOC, ZEXALL, Z80Full(*), Z80memptr +-- (*) Currently only SCF and CCF instructions aren't passed X/Y flags check as +-- correct implementation is still unclear. +-- +-- **** +-- T80(b) core. In an effort to merge and maintain bug fixes .... +-- +-- Ver 301 parity flag is just parity for 8080, also overflow for Z80, by Sean Riddle +-- Ver 300 started tidyup +-- MikeJ March 2005 +-- Latest version from www.fpgaarcade.com (original www.opencores.org) +-- +-- **** +-- Z80 compatible microprocessor core +-- +-- Version : 0247 +-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.opencores.org/cvsweb.shtml/t80/ +-- +-- Limitations : +-- +-- File history : +-- +-- 0214 : Fixed mostly flags, only the block instructions now fail the zex regression test +-- 0238 : Fixed zero flag for 16 bit SBC and ADC +-- 0240 : Added GB operations +-- 0242 : Cleanup +-- 0247 : Cleanup +-- + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; + +entity T80_ALU is + generic( + Mode : integer := 0; + Flag_C : integer := 0; + Flag_N : integer := 1; + Flag_P : integer := 2; + Flag_X : integer := 3; + Flag_H : integer := 4; + Flag_Y : integer := 5; + Flag_Z : integer := 6; + Flag_S : integer := 7 + ); + port( + Arith16 : in std_logic; + Z16 : in std_logic; + WZ : in std_logic_vector(15 downto 0); + XY_State : in std_logic_vector(1 downto 0); + ALU_Op : in std_logic_vector(3 downto 0); + IR : in std_logic_vector(5 downto 0); + ISet : in std_logic_vector(1 downto 0); + BusA : in std_logic_vector(7 downto 0); + BusB : in std_logic_vector(7 downto 0); + F_In : in std_logic_vector(7 downto 0); + Q : out std_logic_vector(7 downto 0); + F_Out : out std_logic_vector(7 downto 0) + ); +end T80_ALU; + +architecture rtl of T80_ALU is + + procedure AddSub(A : std_logic_vector; + B : std_logic_vector; + Sub : std_logic; + Carry_In : std_logic; + signal Res : out std_logic_vector; + signal Carry : out std_logic) is + + variable B_i : unsigned(A'length - 1 downto 0); + variable Res_i : unsigned(A'length + 1 downto 0); + begin + if Sub = '1' then + B_i := not unsigned(B); + else + B_i := unsigned(B); + end if; + + Res_i := unsigned("0" & A & Carry_In) + unsigned("0" & B_i & "1"); + Carry <= Res_i(A'length + 1); + Res <= std_logic_vector(Res_i(A'length downto 1)); + end; + + -- AddSub variables (temporary signals) + signal UseCarry : std_logic; + signal Carry7_v : std_logic; + signal Overflow_v : std_logic; + signal HalfCarry_v : std_logic; + signal Carry_v : std_logic; + signal Q_v : std_logic_vector(7 downto 0); + + signal BitMask : std_logic_vector(7 downto 0); + +begin + + with IR(5 downto 3) select BitMask <= "00000001" when "000", + "00000010" when "001", + "00000100" when "010", + "00001000" when "011", + "00010000" when "100", + "00100000" when "101", + "01000000" when "110", + "10000000" when others; + + UseCarry <= not ALU_Op(2) and ALU_Op(0); + AddSub(BusA(3 downto 0), BusB(3 downto 0), ALU_Op(1), ALU_Op(1) xor (UseCarry and F_In(Flag_C)), Q_v(3 downto 0), HalfCarry_v); + AddSub(BusA(6 downto 4), BusB(6 downto 4), ALU_Op(1), HalfCarry_v, Q_v(6 downto 4), Carry7_v); + AddSub(BusA(7 downto 7), BusB(7 downto 7), ALU_Op(1), Carry7_v, Q_v(7 downto 7), Carry_v); + + -- bug fix - parity flag is just parity for 8080, also overflow for Z80 + process (Carry_v, Carry7_v, Q_v) + begin + if(Mode=2) then + OverFlow_v <= not (Q_v(0) xor Q_v(1) xor Q_v(2) xor Q_v(3) xor + Q_v(4) xor Q_v(5) xor Q_v(6) xor Q_v(7)); else + OverFlow_v <= Carry_v xor Carry7_v; + end if; + end process; + + process (Arith16, ALU_OP, F_In, BusA, BusB, IR, Q_v, Carry_v, HalfCarry_v, OverFlow_v, BitMask, ISet, Z16, WZ, XY_State) + variable Q_t : std_logic_vector(7 downto 0); + variable DAA_Q : unsigned(8 downto 0); + begin + Q_t := "--------"; + F_Out <= F_In; + DAA_Q := "---------"; + case ALU_Op is + when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" | "0110" | "0111" => + F_Out(Flag_N) <= '0'; + F_Out(Flag_C) <= '0'; + case ALU_OP(2 downto 0) is + when "000" | "001" => -- ADD, ADC + Q_t := Q_v; + F_Out(Flag_C) <= Carry_v; + F_Out(Flag_H) <= HalfCarry_v; + F_Out(Flag_P) <= OverFlow_v; + when "010" | "011" | "111" => -- SUB, SBC, CP + Q_t := Q_v; + F_Out(Flag_N) <= '1'; + F_Out(Flag_C) <= not Carry_v; + F_Out(Flag_H) <= not HalfCarry_v; + F_Out(Flag_P) <= OverFlow_v; + when "100" => -- AND + Q_t(7 downto 0) := BusA and BusB; + F_Out(Flag_H) <= '1'; + when "101" => -- XOR + Q_t(7 downto 0) := BusA xor BusB; + F_Out(Flag_H) <= '0'; + when others => -- OR "110" + Q_t(7 downto 0) := BusA or BusB; + F_Out(Flag_H) <= '0'; + end case; + if ALU_Op(2 downto 0) = "111" then -- CP + F_Out(Flag_X) <= BusB(3); + F_Out(Flag_Y) <= BusB(5); + else + F_Out(Flag_X) <= Q_t(3); + F_Out(Flag_Y) <= Q_t(5); + end if; + if Q_t(7 downto 0) = "00000000" then + F_Out(Flag_Z) <= '1'; + if Z16 = '1' then + F_Out(Flag_Z) <= F_In(Flag_Z); -- 16 bit ADC,SBC + end if; + else + F_Out(Flag_Z) <= '0'; + end if; + F_Out(Flag_S) <= Q_t(7); + case ALU_Op(2 downto 0) is + when "000" | "001" | "010" | "011" | "111" => -- ADD, ADC, SUB, SBC, CP + when others => + F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor + Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7)); + end case; + if Arith16 = '1' then + F_Out(Flag_S) <= F_In(Flag_S); + F_Out(Flag_Z) <= F_In(Flag_Z); + F_Out(Flag_P) <= F_In(Flag_P); + end if; + when "1100" => + -- DAA + F_Out(Flag_H) <= F_In(Flag_H); + F_Out(Flag_C) <= F_In(Flag_C); + DAA_Q(7 downto 0) := unsigned(BusA); + DAA_Q(8) := '0'; + if F_In(Flag_N) = '0' then + -- After addition + -- Alow > 9 or H = 1 + if DAA_Q(3 downto 0) > 9 or F_In(Flag_H) = '1' then + if (DAA_Q(3 downto 0) > 9) then + F_Out(Flag_H) <= '1'; + else + F_Out(Flag_H) <= '0'; + end if; + DAA_Q := DAA_Q + 6; + end if; + -- new Ahigh > 9 or C = 1 + if DAA_Q(8 downto 4) > 9 or F_In(Flag_C) = '1' then + DAA_Q := DAA_Q + 96; -- 0x60 + end if; + else + -- After subtraction + if DAA_Q(3 downto 0) > 9 or F_In(Flag_H) = '1' then + if DAA_Q(3 downto 0) > 5 then + F_Out(Flag_H) <= '0'; + end if; + DAA_Q(7 downto 0) := DAA_Q(7 downto 0) - 6; + end if; + if unsigned(BusA) > 153 or F_In(Flag_C) = '1' then + DAA_Q := DAA_Q - 352; -- 0x160 + end if; + end if; + F_Out(Flag_X) <= DAA_Q(3); + F_Out(Flag_Y) <= DAA_Q(5); + F_Out(Flag_C) <= F_In(Flag_C) or DAA_Q(8); + Q_t := std_logic_vector(DAA_Q(7 downto 0)); + if DAA_Q(7 downto 0) = "00000000" then + F_Out(Flag_Z) <= '1'; + else + F_Out(Flag_Z) <= '0'; + end if; + F_Out(Flag_S) <= DAA_Q(7); + F_Out(Flag_P) <= not (DAA_Q(0) xor DAA_Q(1) xor DAA_Q(2) xor DAA_Q(3) xor + DAA_Q(4) xor DAA_Q(5) xor DAA_Q(6) xor DAA_Q(7)); + when "1101" | "1110" => + -- RLD, RRD + Q_t(7 downto 4) := BusA(7 downto 4); + if ALU_Op(0) = '1' then + Q_t(3 downto 0) := BusB(7 downto 4); + else + Q_t(3 downto 0) := BusB(3 downto 0); + end if; + F_Out(Flag_H) <= '0'; + F_Out(Flag_N) <= '0'; + F_Out(Flag_X) <= Q_t(3); + F_Out(Flag_Y) <= Q_t(5); + if Q_t(7 downto 0) = "00000000" then + F_Out(Flag_Z) <= '1'; + else + F_Out(Flag_Z) <= '0'; + end if; + F_Out(Flag_S) <= Q_t(7); + F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor + Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7)); + when "1001" => + -- BIT + Q_t(7 downto 0) := BusB and BitMask; + F_Out(Flag_S) <= Q_t(7); + if Q_t(7 downto 0) = "00000000" then + F_Out(Flag_Z) <= '1'; + F_Out(Flag_P) <= '1'; + else + F_Out(Flag_Z) <= '0'; + F_Out(Flag_P) <= '0'; + end if; + F_Out(Flag_H) <= '1'; + F_Out(Flag_N) <= '0'; + if IR(2 downto 0) = "110" or XY_State /= "00" then + F_Out(Flag_X) <= WZ(11); + F_Out(Flag_Y) <= WZ(13); + else + F_Out(Flag_X) <= BusB(3); + F_Out(Flag_Y) <= BusB(5); + end if; + when "1010" => + -- SET + Q_t(7 downto 0) := BusB or BitMask; + when "1011" => + -- RES + Q_t(7 downto 0) := BusB and not BitMask; + when "1000" => + -- ROT + case IR(5 downto 3) is + when "000" => -- RLC + Q_t(7 downto 1) := BusA(6 downto 0); + Q_t(0) := BusA(7); + F_Out(Flag_C) <= BusA(7); + when "010" => -- RL + Q_t(7 downto 1) := BusA(6 downto 0); + Q_t(0) := F_In(Flag_C); + F_Out(Flag_C) <= BusA(7); + when "001" => -- RRC + Q_t(6 downto 0) := BusA(7 downto 1); + Q_t(7) := BusA(0); + F_Out(Flag_C) <= BusA(0); + when "011" => -- RR + Q_t(6 downto 0) := BusA(7 downto 1); + Q_t(7) := F_In(Flag_C); + F_Out(Flag_C) <= BusA(0); + when "100" => -- SLA + Q_t(7 downto 1) := BusA(6 downto 0); + Q_t(0) := '0'; + F_Out(Flag_C) <= BusA(7); + when "110" => -- SLL (Undocumented) / SWAP + if Mode = 3 then + Q_t(7 downto 4) := BusA(3 downto 0); + Q_t(3 downto 0) := BusA(7 downto 4); + F_Out(Flag_C) <= '0'; + else + Q_t(7 downto 1) := BusA(6 downto 0); + Q_t(0) := '1'; + F_Out(Flag_C) <= BusA(7); + end if; + when "101" => -- SRA + Q_t(6 downto 0) := BusA(7 downto 1); + Q_t(7) := BusA(7); + F_Out(Flag_C) <= BusA(0); + when others => -- SRL + Q_t(6 downto 0) := BusA(7 downto 1); + Q_t(7) := '0'; + F_Out(Flag_C) <= BusA(0); + end case; + F_Out(Flag_H) <= '0'; + F_Out(Flag_N) <= '0'; + F_Out(Flag_X) <= Q_t(3); + F_Out(Flag_Y) <= Q_t(5); + F_Out(Flag_S) <= Q_t(7); + if Q_t(7 downto 0) = "00000000" then + F_Out(Flag_Z) <= '1'; + else + F_Out(Flag_Z) <= '0'; + end if; + F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor + Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7)); + if ISet = "00" then + F_Out(Flag_P) <= F_In(Flag_P); + F_Out(Flag_S) <= F_In(Flag_S); + F_Out(Flag_Z) <= F_In(Flag_Z); + end if; + when others => + null; + end case; + Q <= Q_t; + end process; +end; diff --git a/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/t80/T80_MCode.vhd b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/t80/T80_MCode.vhd new file mode 100644 index 0000000000000000000000000000000000000000..f5312bd65bf55d80bf965ef7b24e28cbd0086cdc --- /dev/null +++ b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/t80/T80_MCode.vhd @@ -0,0 +1,2035 @@ +-------------------------------------------------------------------------------- +-- **** +-- T80(c) core. Attempt to finish all undocumented features and provide +-- accurate timings. +-- Version 350. +-- Copyright (c) 2018 Sorgelig +-- Test passed: ZEXDOC, ZEXALL, Z80Full(*), Z80memptr +-- (*) Currently only SCF and CCF instructions aren't passed X/Y flags check as +-- correct implementation is still unclear. +-- +-- **** +-- T80(b) core. In an effort to merge and maintain bug fixes .... +-- +-- Ver 303 add undocumented DDCB and FDCB opcodes by TobiFlex 20.04.2010 +-- Ver 300 started tidyup +-- MikeJ March 2005 +-- Latest version from www.fpgaarcade.com (original www.opencores.org) +-- +-- **** +-- Z80 compatible microprocessor core +-- +-- Version : 0242 +-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.opencores.org/cvsweb.shtml/t80/ +-- +-- Limitations : +-- +-- File history : +-- +-- 0208 : First complete release +-- 0211 : Fixed IM 1 +-- 0214 : Fixed mostly flags, only the block instructions now fail the zex regression test +-- 0235 : Added IM 2 fix by Mike Johnson +-- 0238 : Added NoRead signal +-- 0238b: Fixed instruction timing for POP and DJNZ +-- 0240 : Added (IX/IY+d) states, removed op-codes from mode 2 and added all remaining mode 3 op-codes +-- 0240mj1 fix for HL inc/dec for INI, IND, INIR, INDR, OUTI, OUTD, OTIR, OTDR +-- 0242 : Fixed I/O instruction timing, cleanup +-- + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; + +entity T80_MCode is + generic( + Mode : integer := 0; + Flag_C : integer := 0; + Flag_N : integer := 1; + Flag_P : integer := 2; + Flag_X : integer := 3; + Flag_H : integer := 4; + Flag_Y : integer := 5; + Flag_Z : integer := 6; + Flag_S : integer := 7 + ); + port( + IR : in std_logic_vector(7 downto 0); + ISet : in std_logic_vector(1 downto 0); + MCycle : in std_logic_vector(2 downto 0); + F : in std_logic_vector(7 downto 0); + NMICycle : in std_logic; + IntCycle : in std_logic; + XY_State : in std_logic_vector(1 downto 0); + MCycles : out std_logic_vector(2 downto 0); + TStates : out std_logic_vector(2 downto 0); + Prefix : out std_logic_vector(1 downto 0); -- None,CB,ED,DD/FD + Inc_PC : out std_logic; + Inc_WZ : out std_logic; + IncDec_16 : out std_logic_vector(3 downto 0); -- BC,DE,HL,SP 0 is inc + Read_To_Reg : out std_logic; + Read_To_Acc : out std_logic; + Set_BusA_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI/DB,A,SP(L),SP(M),0,F + Set_BusB_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI,A,SP(L),SP(M),1,F,PC(L),PC(M),0 + ALU_Op : out std_logic_vector(3 downto 0); + -- ADD, ADC, SUB, SBC, AND, XOR, OR, CP, ROT, BIT, SET, RES, DAA, RLD, RRD, None + Save_ALU : out std_logic; + PreserveC : out std_logic; + Arith16 : out std_logic; + Set_Addr_To : out std_logic_vector(2 downto 0); -- aNone,aXY,aIOA,aSP,aBC,aDE,aZI + IORQ : out std_logic; + Jump : out std_logic; + JumpE : out std_logic; + JumpXY : out std_logic; + Call : out std_logic; + RstP : out std_logic; + LDZ : out std_logic; + LDW : out std_logic; + LDSPHL : out std_logic; + Special_LD : out std_logic_vector(2 downto 0); -- A,I;A,R;I,A;R,A;None + ExchangeDH : out std_logic; + ExchangeRp : out std_logic; + ExchangeAF : out std_logic; + ExchangeRS : out std_logic; + I_DJNZ : out std_logic; + I_CPL : out std_logic; + I_CCF : out std_logic; + I_SCF : out std_logic; + I_RETN : out std_logic; + I_BT : out std_logic; + I_BC : out std_logic; + I_BTR : out std_logic; + I_RLD : out std_logic; + I_RRD : out std_logic; + I_INRC : out std_logic; + SetWZ : out std_logic_vector(1 downto 0); + SetDI : out std_logic; + SetEI : out std_logic; + IMode : out std_logic_vector(1 downto 0); + Halt : out std_logic; + NoRead : out std_logic; + Write : out std_logic; + XYbit_undoc : out std_logic + ); +end T80_MCode; + +architecture rtl of T80_MCode is + + constant aNone : std_logic_vector(2 downto 0) := "111"; + constant aBC : std_logic_vector(2 downto 0) := "000"; + constant aDE : std_logic_vector(2 downto 0) := "001"; + constant aXY : std_logic_vector(2 downto 0) := "010"; + constant aIOA : std_logic_vector(2 downto 0) := "100"; + constant aSP : std_logic_vector(2 downto 0) := "101"; + constant aZI : std_logic_vector(2 downto 0) := "110"; + + function is_cc_true( + F : std_logic_vector(7 downto 0); + cc : bit_vector(2 downto 0) + ) return boolean is + begin + if Mode = 3 then + case cc is + when "000" => return F(Flag_S) = '0'; -- NZ + when "001" => return F(Flag_S) = '1'; -- Z + when "010" => return F(Flag_H) = '0'; -- NC + when "011" => return F(Flag_H) = '1'; -- C + when "100" => return false; + when "101" => return false; + when "110" => return false; + when "111" => return false; + end case; + else + case cc is + when "000" => return F(Flag_Z) = '0'; -- NZ + when "001" => return F(Flag_Z) = '1'; -- Z + when "010" => return F(Flag_C) = '0'; -- NC + when "011" => return F(Flag_C) = '1'; -- C + when "100" => return F(Flag_P) = '0'; -- PO + when "101" => return F(Flag_P) = '1'; -- PE + when "110" => return F(Flag_S) = '0'; -- P + when "111" => return F(Flag_S) = '1'; -- M + end case; + end if; + end; + +begin + + process (IR, ISet, MCycle, F, NMICycle, IntCycle, XY_State) + variable DDD : std_logic_vector(2 downto 0); + variable SSS : std_logic_vector(2 downto 0); + variable DPair : std_logic_vector(1 downto 0); + variable IRB : bit_vector(7 downto 0); + begin + DDD := IR(5 downto 3); + SSS := IR(2 downto 0); + DPair := IR(5 downto 4); + IRB := to_bitvector(IR); + + MCycles <= "001"; + if MCycle = "001" then + TStates <= "100"; + else + TStates <= "011"; + end if; + Prefix <= "00"; + Inc_PC <= '0'; + Inc_WZ <= '0'; + IncDec_16 <= "0000"; + Read_To_Acc <= '0'; + Read_To_Reg <= '0'; + Set_BusB_To <= "0000"; + Set_BusA_To <= "0000"; + ALU_Op <= "0" & IR(5 downto 3); + Save_ALU <= '0'; + PreserveC <= '0'; + Arith16 <= '0'; + IORQ <= '0'; + Set_Addr_To <= aNone; + Jump <= '0'; + JumpE <= '0'; + JumpXY <= '0'; + Call <= '0'; + RstP <= '0'; + LDZ <= '0'; + LDW <= '0'; + LDSPHL <= '0'; + Special_LD <= "000"; + ExchangeDH <= '0'; + ExchangeRp <= '0'; + ExchangeAF <= '0'; + ExchangeRS <= '0'; + I_DJNZ <= '0'; + I_CPL <= '0'; + I_CCF <= '0'; + I_SCF <= '0'; + I_RETN <= '0'; + I_BT <= '0'; + I_BC <= '0'; + I_BTR <= '0'; + I_RLD <= '0'; + I_RRD <= '0'; + I_INRC <= '0'; + SetDI <= '0'; + SetEI <= '0'; + IMode <= "11"; + Halt <= '0'; + NoRead <= '0'; + Write <= '0'; + XYbit_undoc <= '0'; + SetWZ <= "00"; + + case ISet is + when "00" => + +------------------------------------------------------------------------------ +-- +-- Unprefixed instructions +-- +------------------------------------------------------------------------------ + + case IRB is +-- 8 BIT LOAD GROUP + when "01000000"|"01000001"|"01000010"|"01000011"|"01000100"|"01000101"|"01000111" + |"01001000"|"01001001"|"01001010"|"01001011"|"01001100"|"01001101"|"01001111" + |"01010000"|"01010001"|"01010010"|"01010011"|"01010100"|"01010101"|"01010111" + |"01011000"|"01011001"|"01011010"|"01011011"|"01011100"|"01011101"|"01011111" + |"01100000"|"01100001"|"01100010"|"01100011"|"01100100"|"01100101"|"01100111" + |"01101000"|"01101001"|"01101010"|"01101011"|"01101100"|"01101101"|"01101111" + |"01111000"|"01111001"|"01111010"|"01111011"|"01111100"|"01111101"|"01111111" => + -- LD r,r' + Set_BusB_To(2 downto 0) <= SSS; + ExchangeRp <= '1'; + Set_BusA_To(2 downto 0) <= DDD; + Read_To_Reg <= '1'; + when "00000110"|"00001110"|"00010110"|"00011110"|"00100110"|"00101110"|"00111110" => + -- LD r,n + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + Set_BusA_To(2 downto 0) <= DDD; + Read_To_Reg <= '1'; + when others => null; + end case; + when "01000110"|"01001110"|"01010110"|"01011110"|"01100110"|"01101110"|"01111110" => + -- LD r,(HL) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + when 2 => + Set_BusA_To(2 downto 0) <= DDD; + Read_To_Reg <= '1'; + when others => null; + end case; + when "01110000"|"01110001"|"01110010"|"01110011"|"01110100"|"01110101"|"01110111" => + -- LD (HL),r + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + Set_BusB_To(2 downto 0) <= SSS; + Set_BusB_To(3) <= '0'; + when 2 => + Write <= '1'; + when others => null; + end case; + when "00110110" => + -- LD (HL),n + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + Set_Addr_To <= aXY; + Set_BusB_To(2 downto 0) <= SSS; + Set_BusB_To(3) <= '0'; + when 3 => + Write <= '1'; + when others => null; + end case; + when "00001010" => + -- LD A,(BC) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aBC; + when 2 => + Read_To_Acc <= '1'; + when others => null; + end case; + when "00011010" => + -- LD A,(DE) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aDE; + when 2 => + Read_To_Acc <= '1'; + when others => null; + end case; + when "00111010" => + if Mode = 3 then + -- LDD A,(HL) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + when 2 => + Read_To_Acc <= '1'; + IncDec_16 <= "1110"; + when others => null; + end case; + else + -- LD A,(nn) + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + when 4 => + Read_To_Acc <= '1'; + when others => null; + end case; + end if; + when "00000010" => + -- LD (BC),A + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aBC; + Set_BusB_To <= "0111"; + SetWZ <= "10"; + when 2 => + Write <= '1'; + when others => null; + end case; + when "00010010" => + -- LD (DE),A + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aDE; + Set_BusB_To <= "0111"; + SetWZ <= "10"; + when 2 => + Write <= '1'; + when others => null; + end case; + when "00110010" => + if Mode = 3 then + -- LDD (HL),A + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + Set_BusB_To <= "0111"; + when 2 => + Write <= '1'; + IncDec_16 <= "1110"; + when others => null; + end case; + else + -- LD (nn),A + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + SetWZ <= "10"; + Inc_PC <= '1'; + Set_BusB_To <= "0111"; + when 4 => + Write <= '1'; + when others => null; + end case; + end if; + +-- 16 BIT LOAD GROUP + when "00000001"|"00010001"|"00100001"|"00110001" => + -- LD dd,nn + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + Read_To_Reg <= '1'; + if DPAIR = "11" then + Set_BusA_To(3 downto 0) <= "1000"; + else + Set_BusA_To(2 downto 1) <= DPAIR; + Set_BusA_To(0) <= '1'; + end if; + when 3 => + Inc_PC <= '1'; + Read_To_Reg <= '1'; + if DPAIR = "11" then + Set_BusA_To(3 downto 0) <= "1001"; + else + Set_BusA_To(2 downto 1) <= DPAIR; + Set_BusA_To(0) <= '0'; + end if; + when others => null; + end case; + when "00101010" => + if Mode = 3 then + -- LDI A,(HL) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + when 2 => + Read_To_Acc <= '1'; + IncDec_16 <= "0110"; + when others => null; + end case; + else + -- LD HL,(nn) + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + LDW <= '1'; + when 4 => + Set_BusA_To(2 downto 0) <= "101"; -- L + Read_To_Reg <= '1'; + Inc_WZ <= '1'; + Set_Addr_To <= aZI; + when 5 => + Set_BusA_To(2 downto 0) <= "100"; -- H + Read_To_Reg <= '1'; + when others => null; + end case; + end if; + when "00100010" => + if Mode = 3 then + -- LDI (HL),A + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + Set_BusB_To <= "0111"; + when 2 => + Write <= '1'; + IncDec_16 <= "0110"; + when others => null; + end case; + else + -- LD (nn),HL + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + LDW <= '1'; + Set_BusB_To <= "0101"; -- L + when 4 => + Inc_WZ <= '1'; + Set_Addr_To <= aZI; + Write <= '1'; + Set_BusB_To <= "0100"; -- H + when 5 => + Write <= '1'; + when others => null; + end case; + end if; + when "11111001" => + -- LD SP,HL + TStates <= "110"; + LDSPHL <= '1'; + when "11000101"|"11010101"|"11100101"|"11110101" => + -- PUSH qq + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + TStates <= "101"; + IncDec_16 <= "1111"; + Set_Addr_TO <= aSP; + if DPAIR = "11" then + Set_BusB_To <= "0111"; + else + Set_BusB_To(2 downto 1) <= DPAIR; + Set_BusB_To(0) <= '0'; + Set_BusB_To(3) <= '0'; + end if; + when 2 => + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + if DPAIR = "11" then + Set_BusB_To <= "1011"; + else + Set_BusB_To(2 downto 1) <= DPAIR; + Set_BusB_To(0) <= '1'; + Set_BusB_To(3) <= '0'; + end if; + Write <= '1'; + when 3 => + Write <= '1'; + when others => null; + end case; + when "11000001"|"11010001"|"11100001"|"11110001" => + -- POP qq + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aSP; + when 2 => + IncDec_16 <= "0111"; + Set_Addr_To <= aSP; + Read_To_Reg <= '1'; + if DPAIR = "11" then + Set_BusA_To(3 downto 0) <= "1011"; + else + Set_BusA_To(2 downto 1) <= DPAIR; + Set_BusA_To(0) <= '1'; + end if; + when 3 => + IncDec_16 <= "0111"; + Read_To_Reg <= '1'; + if DPAIR = "11" then + Set_BusA_To(3 downto 0) <= "0111"; + else + Set_BusA_To(2 downto 1) <= DPAIR; + Set_BusA_To(0) <= '0'; + end if; + when others => null; + end case; + +-- EXCHANGE, BLOCK TRANSFER AND SEARCH GROUP + when "11101011" => + if Mode /= 3 then + -- EX DE,HL + ExchangeDH <= '1'; + end if; + when "00001000" => + if Mode = 3 then + -- LD (nn),SP + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + LDW <= '1'; + Set_BusB_To <= "1000"; + when 4 => + Inc_WZ <= '1'; + Set_Addr_To <= aZI; + Write <= '1'; + Set_BusB_To <= "1001"; + when 5 => + Write <= '1'; + when others => null; + end case; + elsif Mode < 2 then + -- EX AF,AF' + ExchangeAF <= '1'; + end if; + when "11011001" => + if Mode = 3 then + -- RETI + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_TO <= aSP; + when 2 => + IncDec_16 <= "0111"; + Set_Addr_To <= aSP; + LDZ <= '1'; + when 3 => + Jump <= '1'; + IncDec_16 <= "0111"; + I_RETN <= '1'; + SetEI <= '1'; + when others => null; + end case; + elsif Mode < 2 then + -- EXX + ExchangeRS <= '1'; + end if; + when "11100011" => + if Mode /= 3 then + -- EX (SP),HL + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aSP; + when 2 => + Read_To_Reg <= '1'; + Set_BusA_To <= "0101"; + Set_BusB_To <= "0101"; + Set_Addr_To <= aSP; + LDZ <= '1'; + when 3 => + IncDec_16 <= "0111"; + Set_Addr_To <= aSP; + TStates <= "100"; + Write <= '1'; + when 4 => + Read_To_Reg <= '1'; + Set_BusA_To <= "0100"; + Set_BusB_To <= "0100"; + Set_Addr_To <= aSP; + LDW <= '1'; + when 5 => + IncDec_16 <= "1111"; + TStates <= "101"; + Write <= '1'; + when others => null; + end case; + end if; + +-- 8 BIT ARITHMETIC AND LOGICAL GROUP + when "10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000111" + |"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001111" + |"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010111" + |"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011111" + |"10100000"|"10100001"|"10100010"|"10100011"|"10100100"|"10100101"|"10100111" + |"10101000"|"10101001"|"10101010"|"10101011"|"10101100"|"10101101"|"10101111" + |"10110000"|"10110001"|"10110010"|"10110011"|"10110100"|"10110101"|"10110111" + |"10111000"|"10111001"|"10111010"|"10111011"|"10111100"|"10111101"|"10111111" => + -- ADD A,r + -- ADC A,r + -- SUB A,r + -- SBC A,r + -- AND A,r + -- OR A,r + -- XOR A,r + -- CP A,r + Set_BusB_To(2 downto 0) <= SSS; + Set_BusA_To(2 downto 0) <= "111"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + when "10000110"|"10001110"|"10010110"|"10011110"|"10100110"|"10101110"|"10110110"|"10111110" => + -- ADD A,(HL) + -- ADC A,(HL) + -- SUB A,(HL) + -- SBC A,(HL) + -- AND A,(HL) + -- OR A,(HL) + -- XOR A,(HL) + -- CP A,(HL) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + when 2 => + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_BusB_To(2 downto 0) <= SSS; + Set_BusA_To(2 downto 0) <= "111"; + when others => null; + end case; + when "11000110"|"11001110"|"11010110"|"11011110"|"11100110"|"11101110"|"11110110"|"11111110" => + -- ADD A,n + -- ADC A,n + -- SUB A,n + -- SBC A,n + -- AND A,n + -- OR A,n + -- XOR A,n + -- CP A,n + MCycles <= "010"; + if MCycle = "010" then + Inc_PC <= '1'; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_BusB_To(2 downto 0) <= SSS; + Set_BusA_To(2 downto 0) <= "111"; + end if; + when "00000100"|"00001100"|"00010100"|"00011100"|"00100100"|"00101100"|"00111100" => + -- INC r + Set_BusB_To <= "1010"; + Set_BusA_To(2 downto 0) <= DDD; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + PreserveC <= '1'; + ALU_Op <= "0000"; + when "00110100" => + -- INC (HL) + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + when 2 => + TStates <= "100"; + Set_Addr_To <= aXY; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + PreserveC <= '1'; + ALU_Op <= "0000"; + Set_BusB_To <= "1010"; + Set_BusA_To(2 downto 0) <= DDD; + when 3 => + Write <= '1'; + when others => null; + end case; + when "00000101"|"00001101"|"00010101"|"00011101"|"00100101"|"00101101"|"00111101" => + -- DEC r + Set_BusB_To <= "1010"; + Set_BusA_To(2 downto 0) <= DDD; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + PreserveC <= '1'; + ALU_Op <= "0010"; + when "00110101" => + -- DEC (HL) + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + when 2 => + TStates <= "100"; + Set_Addr_To <= aXY; + ALU_Op <= "0010"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + PreserveC <= '1'; + Set_BusB_To <= "1010"; + Set_BusA_To(2 downto 0) <= DDD; + when 3 => + Write <= '1'; + when others => null; + end case; + +-- GENERAL PURPOSE ARITHMETIC AND CPU CONTROL GROUPS + when "00100111" => + -- DAA + Set_BusA_To(2 downto 0) <= "111"; + Read_To_Reg <= '1'; + ALU_Op <= "1100"; + Save_ALU <= '1'; + when "00101111" => + -- CPL + I_CPL <= '1'; + when "00111111" => + -- CCF + I_CCF <= '1'; + when "00110111" => + -- SCF + I_SCF <= '1'; + when "00000000" => + if NMICycle = '1' then + -- NMI + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + TStates <= "101"; + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + Set_BusB_To <= "1101"; + when 2 => + Write <= '1'; + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + Set_BusB_To <= "1100"; + when 3 => + Write <= '1'; + when others => null; + end case; + elsif IntCycle = '1' then + -- INT (IM 2) + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 1 => + LDZ <= '1'; + TStates <= "101"; + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + Set_BusB_To <= "1101"; + when 2 => + --TStates <= "100"; + Write <= '1'; + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + Set_BusB_To <= "1100"; + when 3 => + --TStates <= "100"; + Write <= '1'; + when 4 => + Inc_PC <= '1'; + LDZ <= '1'; + when 5 => + Jump <= '1'; + when others => null; + end case; + else + -- NOP + end if; + when "01110110" => + -- HALT + Halt <= '1'; + when "11110011" => + -- DI + SetDI <= '1'; + when "11111011" => + -- EI + SetEI <= '1'; + +-- 16 BIT ARITHMETIC GROUP + when "00001001"|"00011001"|"00101001"|"00111001" => + -- ADD HL,ss + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + NoRead <= '1'; + ALU_Op <= "0000"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_BusA_To(2 downto 0) <= "101"; + case to_integer(unsigned(IR(5 downto 4))) is + when 0|1|2 => + Set_BusB_To(2 downto 1) <= IR(5 downto 4); + Set_BusB_To(0) <= '1'; + when others => + Set_BusB_To <= "1000"; + end case; + TStates <= "100"; + Arith16 <= '1'; + SetWZ <= "11"; + when 3 => + NoRead <= '1'; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + ALU_Op <= "0001"; + Set_BusA_To(2 downto 0) <= "100"; + case to_integer(unsigned(IR(5 downto 4))) is + when 0|1|2 => + Set_BusB_To(2 downto 1) <= IR(5 downto 4); + when others => + Set_BusB_To <= "1001"; + end case; + Arith16 <= '1'; + when others => + end case; + when "00000011"|"00010011"|"00100011"|"00110011" => + -- INC ss + TStates <= "110"; + IncDec_16(3 downto 2) <= "01"; + IncDec_16(1 downto 0) <= DPair; + when "00001011"|"00011011"|"00101011"|"00111011" => + -- DEC ss + TStates <= "110"; + IncDec_16(3 downto 2) <= "11"; + IncDec_16(1 downto 0) <= DPair; + +-- ROTATE AND SHIFT GROUP + when "00000111" + -- RLCA + |"00010111" + -- RLA + |"00001111" + -- RRCA + |"00011111" => + -- RRA + Set_BusA_To(2 downto 0) <= "111"; + ALU_Op <= "1000"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + +-- JUMP GROUP + when "11000011" => + -- JP nn + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Inc_PC <= '1'; + Jump <= '1'; + LDW <= '1'; + when others => null; + end case; + when "11000010"|"11001010"|"11010010"|"11011010"|"11100010"|"11101010"|"11110010"|"11111010" => + if IR(5) = '1' and Mode = 3 then + case IRB(4 downto 3) is + when "00" => + -- LD ($FF00+C),A + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aBC; + Set_BusB_To <= "0111"; + when 2 => + Write <= '1'; + IORQ <= '1'; + when others => + end case; + when "01" => + -- LD (nn),A + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + Set_BusB_To <= "0111"; + when 4 => + Write <= '1'; + when others => null; + end case; + when "10" => + -- LD A,($FF00+C) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aBC; + when 2 => + Read_To_Acc <= '1'; + IORQ <= '1'; + when others => + end case; + when "11" => + -- LD A,(nn) + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + when 4 => + Read_To_Acc <= '1'; + when others => null; + end case; + end case; + else + -- JP cc,nn + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + LDW <= '1'; + Inc_PC <= '1'; + if is_cc_true(F, to_bitvector(IR(5 downto 3))) then + Jump <= '1'; + end if; + when others => null; + end case; + end if; + when "00011000" => + if Mode /= 2 then + -- JR e + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + when 3 => + NoRead <= '1'; + JumpE <= '1'; + TStates <= "101"; + when others => null; + end case; + end if; + when "00111000" => + if Mode /= 2 then + -- JR C,e + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + if F(Flag_C) = '0' then + MCycles <= "010"; + end if; + when 3 => + NoRead <= '1'; + JumpE <= '1'; + TStates <= "101"; + when others => null; + end case; + end if; + when "00110000" => + if Mode /= 2 then + -- JR NC,e + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + if F(Flag_C) = '1' then + MCycles <= "010"; + end if; + when 3 => + NoRead <= '1'; + JumpE <= '1'; + TStates <= "101"; + when others => null; + end case; + end if; + when "00101000" => + if Mode /= 2 then + -- JR Z,e + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + if F(Flag_Z) = '0' then + MCycles <= "010"; + end if; + when 3 => + NoRead <= '1'; + JumpE <= '1'; + TStates <= "101"; + when others => null; + end case; + end if; + when "00100000" => + if Mode /= 2 then + -- JR NZ,e + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + if F(Flag_Z) = '1' then + MCycles <= "010"; + end if; + when 3 => + NoRead <= '1'; + JumpE <= '1'; + TStates <= "101"; + when others => null; + end case; + end if; + when "11101001" => + -- JP (HL) + JumpXY <= '1'; + when "00010000" => + if Mode = 3 then + I_DJNZ <= '1'; + elsif Mode < 2 then + -- DJNZ,e + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + TStates <= "101"; + I_DJNZ <= '1'; + Set_BusB_To <= "1010"; + Set_BusA_To(2 downto 0) <= "000"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + ALU_Op <= "0010"; + when 2 => + I_DJNZ <= '1'; + Inc_PC <= '1'; + when 3 => + NoRead <= '1'; + JumpE <= '1'; + TStates <= "101"; + when others => null; + end case; + end if; + +-- CALL AND RETURN GROUP + when "11001101" => + -- CALL nn + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + IncDec_16 <= "1111"; + Inc_PC <= '1'; + TStates <= "100"; + Set_Addr_To <= aSP; + LDW <= '1'; + Set_BusB_To <= "1101"; + when 4 => + Write <= '1'; + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + Set_BusB_To <= "1100"; + when 5 => + Write <= '1'; + Call <= '1'; + when others => null; + end case; + when "11000100"|"11001100"|"11010100"|"11011100"|"11100100"|"11101100"|"11110100"|"11111100" => + if IR(5) = '0' or Mode /= 3 then + -- CALL cc,nn + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Inc_PC <= '1'; + LDW <= '1'; + if is_cc_true(F, to_bitvector(IR(5 downto 3))) then + IncDec_16 <= "1111"; + Set_Addr_TO <= aSP; + TStates <= "100"; + Set_BusB_To <= "1101"; + else + MCycles <= "011"; + end if; + when 4 => + Write <= '1'; + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + Set_BusB_To <= "1100"; + when 5 => + Write <= '1'; + Call <= '1'; + when others => null; + end case; + end if; + when "11001001" => + -- RET + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + --TStates <= "101"; + Set_Addr_TO <= aSP; + when 2 => + IncDec_16 <= "0111"; + Set_Addr_To <= aSP; + LDZ <= '1'; + when 3 => + Jump <= '1'; + IncDec_16 <= "0111"; + when others => null; + end case; + when "11000000"|"11001000"|"11010000"|"11011000"|"11100000"|"11101000"|"11110000"|"11111000" => + if IR(5) = '1' and Mode = 3 then + case IRB(4 downto 3) is + when "00" => + -- LD ($FF00+nn),A + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + Set_Addr_To <= aIOA; + Set_BusB_To <= "0111"; + when 3 => + Write <= '1'; + when others => null; + end case; + when "01" => + -- ADD SP,n + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + ALU_Op <= "0000"; + Inc_PC <= '1'; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_BusA_To <= "1000"; + Set_BusB_To <= "0110"; + when 3 => + NoRead <= '1'; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + ALU_Op <= "0001"; + Set_BusA_To <= "1001"; + Set_BusB_To <= "1110"; -- Incorrect unsigned !!!!!!!!!!!!!!!!!!!!! + when others => + end case; + when "10" => + -- LD A,($FF00+nn) + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + Set_Addr_To <= aIOA; + when 3 => + Read_To_Acc <= '1'; + when others => null; + end case; + when "11" => + -- LD HL,SP+n -- Not correct !!!!!!!!!!!!!!!!!!! + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + LDW <= '1'; + when 4 => + Set_BusA_To(2 downto 0) <= "101"; -- L + Read_To_Reg <= '1'; + Inc_WZ <= '1'; + Set_Addr_To <= aZI; + when 5 => + Set_BusA_To(2 downto 0) <= "100"; -- H + Read_To_Reg <= '1'; + when others => null; + end case; + end case; + else + -- RET cc + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + if is_cc_true(F, to_bitvector(IR(5 downto 3))) then + Set_Addr_TO <= aSP; + else + MCycles <= "001"; + end if; + TStates <= "101"; + when 2 => + IncDec_16 <= "0111"; + Set_Addr_To <= aSP; + LDZ <= '1'; + when 3 => + Jump <= '1'; + IncDec_16 <= "0111"; + when others => null; + end case; + end if; + when "11000111"|"11001111"|"11010111"|"11011111"|"11100111"|"11101111"|"11110111"|"11111111" => + -- RST p + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + TStates <= "101"; + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + Set_BusB_To <= "1101"; + when 2 => + Write <= '1'; + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + Set_BusB_To <= "1100"; + when 3 => + Write <= '1'; + RstP <= '1'; + when others => null; + end case; + +-- INPUT AND OUTPUT GROUP + when "11011011" => + if Mode /= 3 then + -- IN A,(n) + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + Set_Addr_To <= aIOA; + when 3 => + Read_To_Acc <= '1'; + IORQ <= '1'; + when others => null; + end case; + end if; + when "11010011" => + if Mode /= 3 then + -- OUT (n),A + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + Set_Addr_To <= aIOA; + Set_BusB_To <= "0111"; + when 3 => + Write <= '1'; + IORQ <= '1'; + when others => null; + end case; + end if; + +------------------------------------------------------------------------------ +------------------------------------------------------------------------------ +-- MULTIBYTE INSTRUCTIONS +------------------------------------------------------------------------------ +------------------------------------------------------------------------------ + + when "11001011" => + if Mode /= 2 then + Prefix <= "01"; + end if; + + when "11101101" => + if Mode < 2 then + Prefix <= "10"; + end if; + + when "11011101"|"11111101" => + if Mode < 2 then + Prefix <= "11"; + end if; + + end case; + + when "01" => + +------------------------------------------------------------------------------ +-- +-- CB prefixed instructions +-- +------------------------------------------------------------------------------ + + Set_BusA_To(2 downto 0) <= IR(2 downto 0); + Set_BusB_To(2 downto 0) <= IR(2 downto 0); + + case IRB is + when "00000000"|"00000001"|"00000010"|"00000011"|"00000100"|"00000101"|"00000111" + |"00010000"|"00010001"|"00010010"|"00010011"|"00010100"|"00010101"|"00010111" + |"00001000"|"00001001"|"00001010"|"00001011"|"00001100"|"00001101"|"00001111" + |"00011000"|"00011001"|"00011010"|"00011011"|"00011100"|"00011101"|"00011111" + |"00100000"|"00100001"|"00100010"|"00100011"|"00100100"|"00100101"|"00100111" + |"00101000"|"00101001"|"00101010"|"00101011"|"00101100"|"00101101"|"00101111" + |"00110000"|"00110001"|"00110010"|"00110011"|"00110100"|"00110101"|"00110111" + |"00111000"|"00111001"|"00111010"|"00111011"|"00111100"|"00111101"|"00111111" => + -- RLC r + -- RL r + -- RRC r + -- RR r + -- SLA r + -- SRA r + -- SRL r + -- SLL r (Undocumented) / SWAP r + if XY_State="00" then + if MCycle = "001" then + ALU_Op <= "1000"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + end if; + else + -- R/S (IX+d),Reg, undocumented + MCycles <= "011"; + XYbit_undoc <= '1'; + case to_integer(unsigned(MCycle)) is + when 1 | 7=> + Set_Addr_To <= aXY; + when 2 => + ALU_Op <= "1000"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_Addr_To <= aXY; + TStates <= "100"; + when 3 => + Write <= '1'; + when others => null; + end case; + end if; + + when "00000110"|"00010110"|"00001110"|"00011110"|"00101110"|"00111110"|"00100110"|"00110110" => + -- RLC (HL) + -- RL (HL) + -- RRC (HL) + -- RR (HL) + -- SRA (HL) + -- SRL (HL) + -- SLA (HL) + -- SLL (HL) (Undocumented) / SWAP (HL) + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 | 7 => + Set_Addr_To <= aXY; + when 2 => + ALU_Op <= "1000"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_Addr_To <= aXY; + TStates <= "100"; + when 3 => + Write <= '1'; + when others => + end case; + when "01000000"|"01000001"|"01000010"|"01000011"|"01000100"|"01000101"|"01000111" + |"01001000"|"01001001"|"01001010"|"01001011"|"01001100"|"01001101"|"01001111" + |"01010000"|"01010001"|"01010010"|"01010011"|"01010100"|"01010101"|"01010111" + |"01011000"|"01011001"|"01011010"|"01011011"|"01011100"|"01011101"|"01011111" + |"01100000"|"01100001"|"01100010"|"01100011"|"01100100"|"01100101"|"01100111" + |"01101000"|"01101001"|"01101010"|"01101011"|"01101100"|"01101101"|"01101111" + |"01110000"|"01110001"|"01110010"|"01110011"|"01110100"|"01110101"|"01110111" + |"01111000"|"01111001"|"01111010"|"01111011"|"01111100"|"01111101"|"01111111" => + -- BIT b,r + if XY_State="00" then + if MCycle = "001" then + Set_BusB_To(2 downto 0) <= IR(2 downto 0); + ALU_Op <= "1001"; + end if; + else + -- BIT b,(IX+d), undocumented + MCycles <= "010"; + XYbit_undoc <= '1'; + case to_integer(unsigned(MCycle)) is + when 1 | 7=> + Set_Addr_To <= aXY; + when 2 => + ALU_Op <= "1001"; + TStates <= "100"; + when others => null; + end case; + end if; + + when "01000110"|"01001110"|"01010110"|"01011110"|"01100110"|"01101110"|"01110110"|"01111110" => + -- BIT b,(HL) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 | 7 => + Set_Addr_To <= aXY; + when 2 => + ALU_Op <= "1001"; + TStates <= "100"; + when others => null; + end case; + when "11000000"|"11000001"|"11000010"|"11000011"|"11000100"|"11000101"|"11000111" + |"11001000"|"11001001"|"11001010"|"11001011"|"11001100"|"11001101"|"11001111" + |"11010000"|"11010001"|"11010010"|"11010011"|"11010100"|"11010101"|"11010111" + |"11011000"|"11011001"|"11011010"|"11011011"|"11011100"|"11011101"|"11011111" + |"11100000"|"11100001"|"11100010"|"11100011"|"11100100"|"11100101"|"11100111" + |"11101000"|"11101001"|"11101010"|"11101011"|"11101100"|"11101101"|"11101111" + |"11110000"|"11110001"|"11110010"|"11110011"|"11110100"|"11110101"|"11110111" + |"11111000"|"11111001"|"11111010"|"11111011"|"11111100"|"11111101"|"11111111" => + -- SET b,r + if XY_State="00" then + if MCycle = "001" then + ALU_Op <= "1010"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + end if; + else + -- SET b,(IX+d),Reg, undocumented + MCycles <= "011"; + XYbit_undoc <= '1'; + case to_integer(unsigned(MCycle)) is + when 1 | 7=> + Set_Addr_To <= aXY; + when 2 => + ALU_Op <= "1010"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_Addr_To <= aXY; + TStates <= "100"; + when 3 => + Write <= '1'; + when others => null; + end case; + end if; + + when "11000110"|"11001110"|"11010110"|"11011110"|"11100110"|"11101110"|"11110110"|"11111110" => + -- SET b,(HL) + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 | 7 => + Set_Addr_To <= aXY; + when 2 => + ALU_Op <= "1010"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_Addr_To <= aXY; + TStates <= "100"; + when 3 => + Write <= '1'; + when others => null; + end case; + when "10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000111" + |"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001111" + |"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010111" + |"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011111" + |"10100000"|"10100001"|"10100010"|"10100011"|"10100100"|"10100101"|"10100111" + |"10101000"|"10101001"|"10101010"|"10101011"|"10101100"|"10101101"|"10101111" + |"10110000"|"10110001"|"10110010"|"10110011"|"10110100"|"10110101"|"10110111" + |"10111000"|"10111001"|"10111010"|"10111011"|"10111100"|"10111101"|"10111111" => + -- RES b,r + if XY_State="00" then + if MCycle = "001" then + ALU_Op <= "1011"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + end if; + else + -- RES b,(IX+d),Reg, undocumented + MCycles <= "011"; + XYbit_undoc <= '1'; + case to_integer(unsigned(MCycle)) is + when 1 | 7=> + Set_Addr_To <= aXY; + when 2 => + ALU_Op <= "1011"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_Addr_To <= aXY; + TStates <= "100"; + when 3 => + Write <= '1'; + when others => null; + end case; + end if; + + when "10000110"|"10001110"|"10010110"|"10011110"|"10100110"|"10101110"|"10110110"|"10111110" => + -- RES b,(HL) + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 | 7 => + Set_Addr_To <= aXY; + when 2 => + ALU_Op <= "1011"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_Addr_To <= aXY; + TStates <= "100"; + when 3 => + Write <= '1'; + when others => null; + end case; + end case; + + when others => + +------------------------------------------------------------------------------ +-- +-- ED prefixed instructions +-- +------------------------------------------------------------------------------ + + case IRB is + when "00000000"|"00000001"|"00000010"|"00000011"|"00000100"|"00000101"|"00000110"|"00000111" + |"00001000"|"00001001"|"00001010"|"00001011"|"00001100"|"00001101"|"00001110"|"00001111" + |"00010000"|"00010001"|"00010010"|"00010011"|"00010100"|"00010101"|"00010110"|"00010111" + |"00011000"|"00011001"|"00011010"|"00011011"|"00011100"|"00011101"|"00011110"|"00011111" + |"00100000"|"00100001"|"00100010"|"00100011"|"00100100"|"00100101"|"00100110"|"00100111" + |"00101000"|"00101001"|"00101010"|"00101011"|"00101100"|"00101101"|"00101110"|"00101111" + |"00110000"|"00110001"|"00110010"|"00110011"|"00110100"|"00110101"|"00110110"|"00110111" + |"00111000"|"00111001"|"00111010"|"00111011"|"00111100"|"00111101"|"00111110"|"00111111" + + + |"10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000110"|"10000111" + |"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001110"|"10001111" + |"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010110"|"10010111" + |"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011110"|"10011111" + | "10100100"|"10100101"|"10100110"|"10100111" + | "10101100"|"10101101"|"10101110"|"10101111" + | "10110100"|"10110101"|"10110110"|"10110111" + | "10111100"|"10111101"|"10111110"|"10111111" + |"11000000"|"11000001"|"11000010"|"11000011"|"11000100"|"11000101"|"11000110"|"11000111" + |"11001000"|"11001001"|"11001010"|"11001011"|"11001100"|"11001101"|"11001110"|"11001111" + |"11010000"|"11010001"|"11010010"|"11010011"|"11010100"|"11010101"|"11010110"|"11010111" + |"11011000"|"11011001"|"11011010"|"11011011"|"11011100"|"11011101"|"11011110"|"11011111" + |"11100000"|"11100001"|"11100010"|"11100011"|"11100100"|"11100101"|"11100110"|"11100111" + |"11101000"|"11101001"|"11101010"|"11101011"|"11101100"|"11101101"|"11101110"|"11101111" + |"11110000"|"11110001"|"11110010"|"11110011"|"11110100"|"11110101"|"11110110"|"11110111" + |"11111000"|"11111001"|"11111010"|"11111011"|"11111100"|"11111101"|"11111110"|"11111111" => + null; -- NOP, undocumented + when "01111110"|"01111111" => + -- NOP, undocumented + null; +-- 8 BIT LOAD GROUP + when "01010111" => + -- LD A,I + Special_LD <= "100"; + TStates <= "101"; + when "01011111" => + -- LD A,R + Special_LD <= "101"; + TStates <= "101"; + when "01000111" => + -- LD I,A + Special_LD <= "110"; + TStates <= "101"; + when "01001111" => + -- LD R,A + Special_LD <= "111"; + TStates <= "101"; +-- 16 BIT LOAD GROUP + when "01001011"|"01011011"|"01101011"|"01111011" => + -- LD dd,(nn) + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + LDW <= '1'; + when 4 => + Read_To_Reg <= '1'; + if IR(5 downto 4) = "11" then + Set_BusA_To <= "1000"; + else + Set_BusA_To(2 downto 1) <= IR(5 downto 4); + Set_BusA_To(0) <= '1'; + end if; + Inc_WZ <= '1'; + Set_Addr_To <= aZI; + when 5 => + Read_To_Reg <= '1'; + if IR(5 downto 4) = "11" then + Set_BusA_To <= "1001"; + else + Set_BusA_To(2 downto 1) <= IR(5 downto 4); + Set_BusA_To(0) <= '0'; + end if; + when others => null; + end case; + when "01000011"|"01010011"|"01100011"|"01110011" => + -- LD (nn),dd + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + LDW <= '1'; + if IR(5 downto 4) = "11" then + Set_BusB_To <= "1000"; + else + Set_BusB_To(2 downto 1) <= IR(5 downto 4); + Set_BusB_To(0) <= '1'; + Set_BusB_To(3) <= '0'; + end if; + when 4 => + Inc_WZ <= '1'; + Set_Addr_To <= aZI; + Write <= '1'; + if IR(5 downto 4) = "11" then + Set_BusB_To <= "1001"; + else + Set_BusB_To(2 downto 1) <= IR(5 downto 4); + Set_BusB_To(0) <= '0'; + Set_BusB_To(3) <= '0'; + end if; + when 5 => + Write <= '1'; + when others => null; + end case; + when "10100000" | "10101000" | "10110000" | "10111000" => + -- LDI, LDD, LDIR, LDDR + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + IncDec_16 <= "1100"; -- BC + when 2 => + Set_BusB_To <= "0110"; + Set_BusA_To(2 downto 0) <= "111"; + ALU_Op <= "0000"; + Set_Addr_To <= aDE; + if IR(3) = '0' then + IncDec_16 <= "0110"; -- IX + else + IncDec_16 <= "1110"; + end if; + when 3 => + I_BT <= '1'; + TStates <= "101"; + Write <= '1'; + if IR(3) = '0' then + IncDec_16 <= "0101"; -- DE + else + IncDec_16 <= "1101"; + end if; + when 4 => + NoRead <= '1'; + TStates <= "101"; + when others => null; + end case; + when "10100001" | "10101001" | "10110001" | "10111001" => + -- CPI, CPD, CPIR, CPDR + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + IncDec_16 <= "1100"; -- BC + when 2 => + Set_BusB_To <= "0110"; + Set_BusA_To(2 downto 0) <= "111"; + ALU_Op <= "0111"; + Save_ALU <= '1'; + PreserveC <= '1'; + if IR(3) = '0' then + IncDec_16 <= "0110"; + else + IncDec_16 <= "1110"; + end if; + when 3 => + NoRead <= '1'; + I_BC <= '1'; + TStates <= "101"; + when 4 => + NoRead <= '1'; + TStates <= "101"; + when others => null; + end case; + when "01000100"|"01001100"|"01010100"|"01011100"|"01100100"|"01101100"|"01110100"|"01111100" => + -- NEG + Alu_OP <= "0010"; + Set_BusB_To <= "0111"; + Set_BusA_To <= "1010"; + Read_To_Acc <= '1'; + Save_ALU <= '1'; + when "01000110"|"01001110"|"01100110"|"01101110" => + -- IM 0 + IMode <= "00"; + when "01010110"|"01110110" => + -- IM 1 + IMode <= "01"; + when "01011110"|"01110111" => + -- IM 2 + IMode <= "10"; +-- 16 bit arithmetic + when "01001010"|"01011010"|"01101010"|"01111010" => + -- ADC HL,ss + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + NoRead <= '1'; + ALU_Op <= "0001"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_BusA_To(2 downto 0) <= "101"; + case to_integer(unsigned(IR(5 downto 4))) is + when 0|1|2 => + Set_BusB_To(2 downto 1) <= IR(5 downto 4); + Set_BusB_To(0) <= '1'; + when others => + Set_BusB_To <= "1000"; + end case; + TStates <= "100"; + SetWZ <= "11"; + when 3 => + NoRead <= '1'; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + ALU_Op <= "0001"; + Set_BusA_To(2 downto 0) <= "100"; + case to_integer(unsigned(IR(5 downto 4))) is + when 0|1|2 => + Set_BusB_To(2 downto 1) <= IR(5 downto 4); + Set_BusB_To(0) <= '0'; + when others => + Set_BusB_To <= "1001"; + end case; + when others => + end case; + when "01000010"|"01010010"|"01100010"|"01110010" => + -- SBC HL,ss + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + NoRead <= '1'; + ALU_Op <= "0011"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_BusA_To(2 downto 0) <= "101"; + case to_integer(unsigned(IR(5 downto 4))) is + when 0|1|2 => + Set_BusB_To(2 downto 1) <= IR(5 downto 4); + Set_BusB_To(0) <= '1'; + when others => + Set_BusB_To <= "1000"; + end case; + TStates <= "100"; + SetWZ <= "11"; + when 3 => + NoRead <= '1'; + ALU_Op <= "0011"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_BusA_To(2 downto 0) <= "100"; + case to_integer(unsigned(IR(5 downto 4))) is + when 0|1|2 => + Set_BusB_To(2 downto 1) <= IR(5 downto 4); + when others => + Set_BusB_To <= "1001"; + end case; + when others => + end case; + when "01101111" => + -- RLD -- Read in M2, not M3! fixed by Sorgelig + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + when 2 => + Read_To_Reg <= '1'; + Set_BusB_To(2 downto 0) <= "110"; + Set_BusA_To(2 downto 0) <= "111"; + ALU_Op <= "1101"; + Save_ALU <= '1'; + when 3 => + TStates <= "100"; + I_RLD <= '1'; + NoRead <= '1'; + Set_Addr_To <= aXY; + when 4 => + Write <= '1'; + when others => + end case; + when "01100111" => + -- RRD -- Read in M2, not M3! fixed by Sorgelig + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + when 2 => + Read_To_Reg <= '1'; + Set_BusB_To(2 downto 0) <= "110"; + Set_BusA_To(2 downto 0) <= "111"; + ALU_Op <= "1110"; + Save_ALU <= '1'; + when 3 => + TStates <= "100"; + I_RRD <= '1'; + NoRead <= '1'; + Set_Addr_To <= aXY; + when 4 => + Write <= '1'; + when others => + end case; + when "01000101"|"01001101"|"01010101"|"01011101"|"01100101"|"01101101"|"01110101"|"01111101" => + -- RETI/RETN + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_TO <= aSP; + when 2 => + IncDec_16 <= "0111"; + Set_Addr_To <= aSP; + LDZ <= '1'; + when 3 => + Jump <= '1'; + IncDec_16 <= "0111"; + LDW <= '1'; + I_RETN <= '1'; + when others => null; + end case; + when "01000000"|"01001000"|"01010000"|"01011000"|"01100000"|"01101000"|"01110000"|"01111000" => + -- IN r,(C) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aBC; + SetWZ <= "01"; + when 2 => + IORQ <= '1'; + if IR(5 downto 3) /= "110" then + Read_To_Reg <= '1'; + Set_BusA_To(2 downto 0) <= IR(5 downto 3); + end if; + I_INRC <= '1'; + when others => + end case; + when "01000001"|"01001001"|"01010001"|"01011001"|"01100001"|"01101001"|"01110001"|"01111001" => + -- OUT (C),r + -- OUT (C),0 + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aBC; + SetWZ <= "01"; + Set_BusB_To(2 downto 0) <= IR(5 downto 3); + if IR(5 downto 3) = "110" then + Set_BusB_To(3) <= '1'; + end if; + when 2 => + Write <= '1'; + IORQ <= '1'; + when others => + end case; + when "10100010" | "10101010" | "10110010" | "10111010" => + -- INI, IND, INIR, INDR + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 1 => + TStates <= "101"; + Set_Addr_To <= aBC; + Set_BusB_To <= "1010"; + Set_BusA_To <= "0000"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + ALU_Op <= "0010"; + SetWZ <= "11"; + IncDec_16(3) <= IR(3); + when 2 => + IORQ <= '1'; + Set_BusB_To <= "0110"; + Set_Addr_To <= aXY; + when 3 => + if IR(3) = '0' then + IncDec_16 <= "0110"; + else + IncDec_16 <= "1110"; + end if; + Write <= '1'; + I_BTR <= '1'; + when 4 => + NoRead <= '1'; + TStates <= "101"; + when others => null; + end case; + when "10100011" | "10101011" | "10110011" | "10111011" => + -- OUTI, OUTD, OTIR, OTDR + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 1 => + TStates <= "101"; + Set_Addr_To <= aXY; + Set_BusB_To <= "1010"; + Set_BusA_To <= "0000"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + ALU_Op <= "0010"; + when 2 => + Set_BusB_To <= "0110"; + Set_Addr_To <= aBC; + SetWZ <= "11"; + IncDec_16(3) <= IR(3); + when 3 => + if IR(3) = '0' then + IncDec_16 <= "0110"; + else + IncDec_16 <= "1110"; + end if; + IORQ <= '1'; + Write <= '1'; + I_BTR <= '1'; + when 4 => + NoRead <= '1'; + TStates <= "101"; + when others => null; + end case; + end case; + + end case; + + if Mode = 1 then + if MCycle = "001" then +-- TStates <= "100"; + else + TStates <= "011"; + end if; + end if; + + if Mode = 3 then + if MCycle = "001" then +-- TStates <= "100"; + else + TStates <= "100"; + end if; + end if; + + if Mode < 2 then + if MCycle = "110" then + Inc_PC <= '1'; + if Mode = 1 then + Set_Addr_To <= aXY; + TStates <= "100"; + Set_BusB_To(2 downto 0) <= SSS; + Set_BusB_To(3) <= '0'; + end if; + if IRB = "00110110" or IRB = "11001011" then + Set_Addr_To <= aNone; + end if; + end if; + if MCycle = "111" then + if Mode = 0 then + TStates <= "101"; + end if; + if ISet /= "01" then + Set_Addr_To <= aXY; + end if; + Set_BusB_To(2 downto 0) <= SSS; + Set_BusB_To(3) <= '0'; + if IRB = "00110110" or ISet = "01" then + -- LD (HL),n + Inc_PC <= '1'; + else + NoRead <= '1'; + end if; + end if; + end if; + + end process; + +end; diff --git a/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/t80/T80_Reg.vhd b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/t80/T80_Reg.vhd new file mode 100644 index 0000000000000000000000000000000000000000..e7e86454c36da39f42612d83c5759f7460f21db5 --- /dev/null +++ b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/t80/T80_Reg.vhd @@ -0,0 +1,152 @@ +-------------------------------------------------------------------------------- +-- **** +-- T80(c) core. Attempt to finish all undocumented features and provide +-- accurate timings. +-- Version 350. +-- Copyright (c) 2018 Sorgelig +-- Test passed: ZEXDOC, ZEXALL, Z80Full(*), Z80memptr +-- (*) Currently only SCF and CCF instructions aren't passed X/Y flags check as +-- correct implementation is still unclear. +-- +-- **** +-- T80(b) core. In an effort to merge and maintain bug fixes .... +-- +-- +-- Ver 300 started tidyup +-- MikeJ March 2005 +-- Latest version from www.fpgaarcade.com (original www.opencores.org) +-- +-- **** +-- +-- T80 Registers, technology independent +-- +-- Version : 0244 +-- +-- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.opencores.org/cvsweb.shtml/t51/ +-- +-- Limitations : +-- +-- File history : +-- +-- 0242 : Initial release +-- +-- 0244 : Changed to single register file +-- + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; + +entity T80_Reg is + port( + Clk : in std_logic; + CEN : in std_logic; + WEH : in std_logic; + WEL : in std_logic; + AddrA : in std_logic_vector(2 downto 0); + AddrB : in std_logic_vector(2 downto 0); + AddrC : in std_logic_vector(2 downto 0); + DIH : in std_logic_vector(7 downto 0); + DIL : in std_logic_vector(7 downto 0); + DOAH : out std_logic_vector(7 downto 0); + DOAL : out std_logic_vector(7 downto 0); + DOBH : out std_logic_vector(7 downto 0); + DOBL : out std_logic_vector(7 downto 0); + DOCH : out std_logic_vector(7 downto 0); + DOCL : out std_logic_vector(7 downto 0); + DOR : out std_logic_vector(127 downto 0); + DIRSet : in std_logic; + DIR : in std_logic_vector(127 downto 0) + ); +end T80_Reg; + +architecture rtl of T80_Reg is + + type Register_Image is array (natural range <>) of std_logic_vector(7 downto 0); + signal RegsH : Register_Image(0 to 7); + signal RegsL : Register_Image(0 to 7); + +begin + + process (Clk) + begin + if rising_edge(Clk) then + if DIRSet = '1' then + RegsL(0) <= DIR( 7 downto 0); + RegsH(0) <= DIR( 15 downto 8); + + RegsL(1) <= DIR( 23 downto 16); + RegsH(1) <= DIR( 31 downto 24); + + RegsL(2) <= DIR( 39 downto 32); + RegsH(2) <= DIR( 47 downto 40); + + RegsL(3) <= DIR( 55 downto 48); + RegsH(3) <= DIR( 63 downto 56); + + RegsL(4) <= DIR( 71 downto 64); + RegsH(4) <= DIR( 79 downto 72); + + RegsL(5) <= DIR( 87 downto 80); + RegsH(5) <= DIR( 95 downto 88); + + RegsL(6) <= DIR(103 downto 96); + RegsH(6) <= DIR(111 downto 104); + + RegsL(7) <= DIR(119 downto 112); + RegsH(7) <= DIR(127 downto 120); + elsif CEN = '1' then + if WEH = '1' then + RegsH(to_integer(unsigned(AddrA))) <= DIH; + end if; + if WEL = '1' then + RegsL(to_integer(unsigned(AddrA))) <= DIL; + end if; + end if; + end if; + end process; + + DOAH <= RegsH(to_integer(unsigned(AddrA))); + DOAL <= RegsL(to_integer(unsigned(AddrA))); + DOBH <= RegsH(to_integer(unsigned(AddrB))); + DOBL <= RegsL(to_integer(unsigned(AddrB))); + DOCH <= RegsH(to_integer(unsigned(AddrC))); + DOCL <= RegsL(to_integer(unsigned(AddrC))); + DOR <= RegsH(7) & RegsL(7) & RegsH(6) & RegsL(6) & RegsH(5) & RegsL(5) & RegsH(4) & RegsL(4) & RegsH(3) & RegsL(3) & RegsH(2) & RegsL(2) & RegsH(1) & RegsL(1) & RegsH(0) & RegsL(0); + +end; diff --git a/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/t80/T80pa.vhd b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/t80/T80pa.vhd new file mode 100644 index 0000000000000000000000000000000000000000..436dc4d67669e53a1ee6cc179e0936c89aa1c66b --- /dev/null +++ b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/t80/T80pa.vhd @@ -0,0 +1,259 @@ +-- +-- Z80 compatible microprocessor core, preudo-asynchronous top level (by Sorgelig) +-- +-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.opencores.org/cvsweb.shtml/t80/ +-- +-- File history : +-- +-- v1.0: convert to preudo-asynchronous model with original Z80 timings. +-- +-- v2.0: rewritten for more precise timings. +-- support for both CEN_n and CEN_p set to 1. Effective clock will be CLK/2. +-- +-- v2.1: Output Address 0 during non-bus MCycle (fix ZX contention) +-- +-- v2.2: Interrupt acknowledge cycle has been corrected +-- WAIT_n is broken in T80.vhd. Simulate correct WAIT_n locally. +-- +-- v2.3: Output last used Address during non-bus MCycle seems more correct. +-- + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; + +entity T80pa is + generic( + Mode : integer := 0 -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB + ); + port( + RESET_n : in std_logic; + CLK : in std_logic; + CEN_p : in std_logic := '1'; + CEN_n : in std_logic := '1'; + WAIT_n : in std_logic := '1'; + INT_n : in std_logic := '1'; + NMI_n : in std_logic := '1'; + BUSRQ_n : in std_logic := '1'; + M1_n : out std_logic; + MREQ_n : out std_logic; + IORQ_n : out std_logic; + RD_n : out std_logic; + WR_n : out std_logic; + RFSH_n : out std_logic; + HALT_n : out std_logic; + BUSAK_n : out std_logic; + OUT0 : in std_logic := '0'; -- 0 => OUT(C),0, 1 => OUT(C),255 + A : out std_logic_vector(15 downto 0); + DI : in std_logic_vector(7 downto 0); + DO : out std_logic_vector(7 downto 0); + REG : out std_logic_vector(211 downto 0); -- IFF2, IFF1, IM, IY, HL', DE', BC', IX, HL, DE, BC, PC, SP, R, I, F', A', F, A + DIRSet : in std_logic := '0'; + DIR : in std_logic_vector(211 downto 0) := (others => '0') -- IFF2, IFF1, IM, IY, HL', DE', BC', IX, HL, DE, BC, PC, SP, R, I, F', A', F, A + ); +end T80pa; + +architecture rtl of T80pa is + component T80 + generic( + Mode : integer := 0; -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB + IOWait : integer := 0; -- 0 => Single cycle I/O, 1 => Std I/O cycle + Flag_C : integer := 0; + Flag_N : integer := 1; + Flag_P : integer := 2; + Flag_X : integer := 3; + Flag_H : integer := 4; + Flag_Y : integer := 5; + Flag_Z : integer := 6; + Flag_S : integer := 7 + ); + port( + RESET_n : in std_logic; + CLK_n : in std_logic; + CEN : in std_logic; + WAIT_n : in std_logic; + INT_n : in std_logic; + NMI_n : in std_logic; + BUSRQ_n : in std_logic; + M1_n : out std_logic; + IORQ : out std_logic; + NoRead : out std_logic; + Write : out std_logic; + RFSH_n : out std_logic; + HALT_n : out std_logic; + BUSAK_n : out std_logic; + A : out std_logic_vector(15 downto 0); + DInst : in std_logic_vector(7 downto 0); + DI : in std_logic_vector(7 downto 0); + DO : out std_logic_vector(7 downto 0); + MC : out std_logic_vector(2 downto 0); + TS : out std_logic_vector(2 downto 0); + IntCycle_n : out std_logic; + IntE : out std_logic; + Stop : out std_logic; + out0 : in std_logic := '0'; -- 0 => OUT(C),0, 1 => OUT(C),255 + REG : out std_logic_vector(211 downto 0); -- IFF2, IFF1, IM, IY, HL', DE', BC', IX, HL, DE, BC, PC, SP, R, I, F', A', F, A + + DIRSet : in std_logic := '0'; + DIR : in std_logic_vector(211 downto 0) := (others => '0') -- IFF2, IFF1, IM, IY, HL', DE', BC', IX, HL, DE, BC, PC, SP, R, I, F', A', F, A + ); + end component; + signal IntCycle_n : std_logic; + signal IntCycleD_n : std_logic_vector(1 downto 0); + signal IORQ : std_logic; + signal NoRead : std_logic; + signal Write : std_logic; + signal BUSAK : std_logic; + signal DI_Reg : std_logic_vector (7 downto 0); -- Input synchroniser + signal MCycle : std_logic_vector(2 downto 0); + signal TState : std_logic_vector(2 downto 0); + signal CEN_pol : std_logic; + signal A_int : std_logic_vector(15 downto 0); + signal A_last : std_logic_vector(15 downto 0); + signal CEN : std_logic; +begin + + A <= A_int when NoRead = '0' or Write = '1' else A_last; + CEN <= CEN_p and not CEN_pol; + BUSAK_n <= BUSAK; + + u0 : T80 + generic map( + Mode => Mode, + IOWait => 1 + ) + port map( + CEN => CEN, + M1_n => M1_n, + IORQ => IORQ, + NoRead => NoRead, + Write => Write, + RFSH_n => RFSH_n, + HALT_n => HALT_n, + WAIT_n => '1', + INT_n => INT_n, + NMI_n => NMI_n, + RESET_n => RESET_n, + BUSRQ_n => BUSRQ_n, + BUSAK_n => BUSAK, + CLK_n => CLK, + A => A_int, + DInst => DI, -- valid at beginning of T3 + DI => DI_Reg, -- latched at middle of T3 + DO => DO, + REG => REG, + MC => MCycle, + TS => TState, + OUT0 => OUT0, + IntCycle_n => IntCycle_n, + DIRSet => DIRSet, + DIR => DIR + ); + + process(CLK) + begin + if rising_edge(CLK) then + if RESET_n = '0' then + WR_n <= '1'; + RD_n <= '1'; + IORQ_n <= '1'; + MREQ_n <= '1'; + DI_Reg <= "00000000"; + CEN_pol <= '0'; + elsif CEN_p = '1' and CEN_pol = '0' then + CEN_pol <= '1'; + if MCycle = "001" then + if TState = "010" then + IORQ_n <= '1'; + MREQ_n <= '1'; + RD_n <= '1'; + end if; + else + if TState = "001" and IORQ = '1' then + WR_n <= not Write; + RD_n <= Write; + IORQ_n <= '0'; + end if; + end if; + elsif CEN_n = '1' and CEN_pol = '1' then + if TState = "010" then + CEN_pol <= not WAIT_n; + else + CEN_pol <= '0'; + end if; + if TState = "011" and BUSAK = '1' then + DI_Reg <= DI; + end if; + if MCycle = "001" then + if TState = "001" then + IntCycleD_n <= IntCycleD_n(0) & IntCycle_n; + RD_n <= not IntCycle_n; + MREQ_n <= not IntCycle_n; + IORQ_n <= IntCycleD_n(1); + A_last <= A_int; + end if; + if TState = "011" then + IntCycleD_n <= "11"; + RD_n <= '1'; + MREQ_n <= '0'; + end if; + if TState = "100" then + MREQ_n <= '1'; + end if; + else + if NoRead = '0' and IORQ = '0' then + if TState = "001" then + RD_n <= Write; + MREQ_n <= '0'; + A_last <= A_int; + end if; + end if; + if TState = "010" then + WR_n <= not Write; + end if; + if TState = "011" then + WR_n <= '1'; + RD_n <= '1'; + IORQ_n <= '1'; + MREQ_n <= '1'; + end if; + end if; + end if; + end if; + end process; +end; diff --git a/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/t80/T80s.v b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/t80/T80s.v new file mode 100644 index 0000000000000000000000000000000000000000..da81ea10b5232a5ed4a7e11df0ce098a542e39ad --- /dev/null +++ b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/t80/T80s.v @@ -0,0 +1,21311 @@ +// look below for +// Register assignments for debugging. +/* verilator coverage_off */ +module t80_reg + (input clk, + input cen, + input weh, + input wel, + input [2:0] addra, + input [2:0] addrb, + input [2:0] addrc, + input [7:0] dih, + input [7:0] dil, + input dirset, + input [127:0] dir, + output [7:0] doah, + output [7:0] doal, + output [7:0] dobh, + output [7:0] dobl, + output [7:0] doch, + output [7:0] docl, + output [127:0] dor); + wire [63:0] regsh; + wire [63:0] regsl; + wire [7:0] n7804_o; + wire [7:0] n7805_o; + wire [7:0] n7806_o; + wire [7:0] n7807_o; + wire [7:0] n7808_o; + wire [7:0] n7809_o; + wire [7:0] n7810_o; + wire [7:0] n7811_o; + wire [7:0] n7812_o; + wire [7:0] n7813_o; + wire [7:0] n7814_o; + wire [7:0] n7815_o; + wire [7:0] n7816_o; + wire [7:0] n7817_o; + wire [7:0] n7818_o; + wire [7:0] n7819_o; + wire [2:0] n7822_o; + wire [63:0] n7825_o; + wire [2:0] n7828_o; + wire [63:0] n7831_o; + wire n7832_o; + wire n7833_o; + wire [63:0] n7834_o; + wire [63:0] n7835_o; + wire [63:0] n7836_o; + wire [63:0] n7837_o; + wire [2:0] n7843_o; + wire [2:0] n7848_o; + wire [2:0] n7853_o; + wire [2:0] n7858_o; + wire [2:0] n7863_o; + wire [2:0] n7868_o; + wire [7:0] n7871_o; + wire [7:0] n7872_o; + wire [15:0] n7873_o; + wire [7:0] n7874_o; + wire [23:0] n7875_o; + wire [7:0] n7876_o; + wire [31:0] n7877_o; + wire [7:0] n7878_o; + wire [39:0] n7879_o; + wire [7:0] n7880_o; + wire [47:0] n7881_o; + wire [7:0] n7882_o; + wire [55:0] n7883_o; + wire [7:0] n7884_o; + wire [63:0] n7885_o; + wire [7:0] n7886_o; + wire [71:0] n7887_o; + wire [7:0] n7888_o; + wire [79:0] n7889_o; + wire [7:0] n7890_o; + wire [87:0] n7891_o; + wire [7:0] n7892_o; + wire [95:0] n7893_o; + wire [7:0] n7894_o; + wire [103:0] n7895_o; + wire [7:0] n7896_o; + wire [111:0] n7897_o; + wire [7:0] n7898_o; + wire [119:0] n7899_o; + wire [7:0] n7900_o; + wire [127:0] n7901_o; + reg [63:0] n7902_q; + reg [63:0] n7903_q; + wire n7904_o; + wire n7905_o; + wire n7906_o; + wire n7907_o; + wire n7908_o; + wire n7909_o; + wire n7910_o; + wire n7911_o; + wire n7912_o; + wire n7913_o; + wire n7914_o; + wire n7915_o; + wire n7916_o; + wire n7917_o; + wire n7918_o; + wire n7919_o; + wire n7920_o; + wire n7921_o; + wire [7:0] n7922_o; + wire [7:0] n7923_o; + wire [7:0] n7924_o; + wire [7:0] n7925_o; + wire [7:0] n7926_o; + wire [7:0] n7927_o; + wire [7:0] n7928_o; + wire [7:0] n7929_o; + wire [7:0] n7930_o; + wire [7:0] n7931_o; + wire [7:0] n7932_o; + wire [7:0] n7933_o; + wire [7:0] n7934_o; + wire [7:0] n7935_o; + wire [7:0] n7936_o; + wire [7:0] n7937_o; + wire [63:0] n7938_o; + wire n7939_o; + wire n7940_o; + wire n7941_o; + wire n7942_o; + wire n7943_o; + wire n7944_o; + wire n7945_o; + wire n7946_o; + wire n7947_o; + wire n7948_o; + wire n7949_o; + wire n7950_o; + wire n7951_o; + wire n7952_o; + wire n7953_o; + wire n7954_o; + wire n7955_o; + wire n7956_o; + wire [7:0] n7957_o; + wire [7:0] n7958_o; + wire [7:0] n7959_o; + wire [7:0] n7960_o; + wire [7:0] n7961_o; + wire [7:0] n7962_o; + wire [7:0] n7963_o; + wire [7:0] n7964_o; + wire [7:0] n7965_o; + wire [7:0] n7966_o; + wire [7:0] n7967_o; + wire [7:0] n7968_o; + wire [7:0] n7969_o; + wire [7:0] n7970_o; + wire [7:0] n7971_o; + wire [7:0] n7972_o; + wire [63:0] n7973_o; + wire [7:0] n7974_o; + wire [7:0] n7975_o; + wire [7:0] n7976_o; + wire [7:0] n7977_o; + wire [7:0] n7978_o; + wire [7:0] n7979_o; + wire [7:0] n7980_o; + wire [7:0] n7981_o; + wire [1:0] n7982_o; + reg [7:0] n7983_o; + wire [1:0] n7984_o; + reg [7:0] n7985_o; + wire n7986_o; + wire [7:0] n7987_o; + wire [7:0] n7988_o; + wire [7:0] n7989_o; + wire [7:0] n7990_o; + wire [7:0] n7991_o; + wire [7:0] n7992_o; + wire [7:0] n7993_o; + wire [7:0] n7994_o; + wire [7:0] n7995_o; + wire [1:0] n7996_o; + reg [7:0] n7997_o; + wire [1:0] n7998_o; + reg [7:0] n7999_o; + wire n8000_o; + wire [7:0] n8001_o; + wire [7:0] n8002_o; + wire [7:0] n8003_o; + wire [7:0] n8004_o; + wire [7:0] n8005_o; + wire [7:0] n8006_o; + wire [7:0] n8007_o; + wire [7:0] n8008_o; + wire [7:0] n8009_o; + wire [1:0] n8010_o; + reg [7:0] n8011_o; + wire [1:0] n8012_o; + reg [7:0] n8013_o; + wire n8014_o; + wire [7:0] n8015_o; + wire [7:0] n8016_o; + wire [7:0] n8017_o; + wire [7:0] n8018_o; + wire [7:0] n8019_o; + wire [7:0] n8020_o; + wire [7:0] n8021_o; + wire [7:0] n8022_o; + wire [7:0] n8023_o; + wire [1:0] n8024_o; + reg [7:0] n8025_o; + wire [1:0] n8026_o; + reg [7:0] n8027_o; + wire n8028_o; + wire [7:0] n8029_o; + wire [7:0] n8030_o; + wire [7:0] n8031_o; + wire [7:0] n8032_o; + wire [7:0] n8033_o; + wire [7:0] n8034_o; + wire [7:0] n8035_o; + wire [7:0] n8036_o; + wire [7:0] n8037_o; + wire [1:0] n8038_o; + reg [7:0] n8039_o; + wire [1:0] n8040_o; + reg [7:0] n8041_o; + wire n8042_o; + wire [7:0] n8043_o; + wire [7:0] n8044_o; + wire [7:0] n8045_o; + wire [7:0] n8046_o; + wire [7:0] n8047_o; + wire [7:0] n8048_o; + wire [7:0] n8049_o; + wire [7:0] n8050_o; + wire [7:0] n8051_o; + wire [1:0] n8052_o; + reg [7:0] n8053_o; + wire [1:0] n8054_o; + reg [7:0] n8055_o; + wire n8056_o; + wire [7:0] n8057_o; + + assign doah = n7987_o; + assign doal = n8001_o; + assign dobh = n8015_o; + assign dobl = n8029_o; + assign doch = n8043_o; + assign docl = n8057_o; + assign dor = n7901_o; + /* T80_Reg.vhd:101:16 */ + assign regsh = n7902_q; // (signal) + /* T80_Reg.vhd:102:16 */ + assign regsl = n7903_q; // (signal) + /* T80_Reg.vhd:110:48 */ + assign n7804_o = dir[7:0]; + /* T80_Reg.vhd:111:48 */ + assign n7805_o = dir[15:8]; + /* T80_Reg.vhd:113:48 */ + assign n7806_o = dir[23:16]; + /* T80_Reg.vhd:114:48 */ + assign n7807_o = dir[31:24]; + /* T80_Reg.vhd:116:48 */ + assign n7808_o = dir[39:32]; + /* T80_Reg.vhd:117:48 */ + assign n7809_o = dir[47:40]; + /* T80_Reg.vhd:119:48 */ + assign n7810_o = dir[55:48]; + /* T80_Reg.vhd:120:48 */ + assign n7811_o = dir[63:56]; + /* T80_Reg.vhd:122:48 */ + assign n7812_o = dir[71:64]; + /* T80_Reg.vhd:123:48 */ + assign n7813_o = dir[79:72]; + /* T80_Reg.vhd:125:48 */ + assign n7814_o = dir[87:80]; + /* T80_Reg.vhd:126:48 */ + assign n7815_o = dir[95:88]; + /* T80_Reg.vhd:128:48 */ + assign n7816_o = dir[103:96]; + /* T80_Reg.vhd:129:48 */ + assign n7817_o = dir[111:104]; + /* T80_Reg.vhd:131:48 */ + assign n7818_o = dir[119:112]; + /* T80_Reg.vhd:132:48 */ + assign n7819_o = dir[127:120]; + /* T80_Reg.vhd:135:47 */ + assign n7822_o = 3'b111 - addra; + /* T80_Reg.vhd:133:25 */ + assign n7825_o = n7832_o ? n7938_o : regsh; + /* T80_Reg.vhd:138:47 */ + assign n7828_o = 3'b111 - addra; + /* T80_Reg.vhd:133:25 */ + assign n7831_o = n7833_o ? n7973_o : regsl; + /* T80_Reg.vhd:133:25 */ + assign n7832_o = cen & weh; + /* T80_Reg.vhd:133:25 */ + assign n7833_o = cen & wel; + assign n7834_o = {n7805_o, n7807_o, n7809_o, n7811_o, n7813_o, n7815_o, n7817_o, n7819_o}; + /* T80_Reg.vhd:109:25 */ + assign n7835_o = dirset ? n7834_o : n7825_o; + /* T80_ALU.vhd:112:26 */ + assign n7836_o = {n7804_o, n7806_o, n7808_o, n7810_o, n7812_o, n7814_o, n7816_o, n7818_o}; + /* T80_Reg.vhd:109:25 */ + assign n7837_o = dirset ? n7836_o : n7831_o; + /* T80_Reg.vhd:144:23 */ + assign n7843_o = 3'b111 - addra; + /* T80_Reg.vhd:145:23 */ + assign n7848_o = 3'b111 - addra; + /* T80_Reg.vhd:146:23 */ + assign n7853_o = 3'b111 - addrb; + /* T80_Reg.vhd:147:23 */ + assign n7858_o = 3'b111 - addrb; + /* T80_Reg.vhd:148:23 */ + assign n7863_o = 3'b111 - addrc; + /* T80_Reg.vhd:149:23 */ + assign n7868_o = 3'b111 - addrc; + /* T80_Reg.vhd:150:22 */ + assign n7871_o = regsh[7:0]; + /* T80_Reg.vhd:150:33 */ + assign n7872_o = regsl[7:0]; + /* T80_Reg.vhd:150:26 */ + assign n7873_o = {n7871_o, n7872_o}; + /* T80_Reg.vhd:150:44 */ + assign n7874_o = regsh[15:8]; + /* T80_Reg.vhd:150:37 */ + assign n7875_o = {n7873_o, n7874_o}; + /* T80_Reg.vhd:150:55 */ + assign n7876_o = regsl[15:8]; + /* T80_Reg.vhd:150:48 */ + assign n7877_o = {n7875_o, n7876_o}; + /* T80_Reg.vhd:150:66 */ + assign n7878_o = regsh[23:16]; + /* T80_Reg.vhd:150:59 */ + assign n7879_o = {n7877_o, n7878_o}; + /* T80_Reg.vhd:150:77 */ + assign n7880_o = regsl[23:16]; + /* T80_Reg.vhd:150:70 */ + assign n7881_o = {n7879_o, n7880_o}; + /* T80_Reg.vhd:150:88 */ + assign n7882_o = regsh[31:24]; + /* T80_Reg.vhd:150:81 */ + assign n7883_o = {n7881_o, n7882_o}; + /* T80_Reg.vhd:150:99 */ + assign n7884_o = regsl[31:24]; + /* T80_Reg.vhd:150:92 */ + assign n7885_o = {n7883_o, n7884_o}; + /* T80_Reg.vhd:150:110 */ + assign n7886_o = regsh[39:32]; + /* T80_Reg.vhd:150:103 */ + assign n7887_o = {n7885_o, n7886_o}; + /* T80_Reg.vhd:150:121 */ + assign n7888_o = regsl[39:32]; + /* T80_Reg.vhd:150:114 */ + assign n7889_o = {n7887_o, n7888_o}; + /* T80_Reg.vhd:150:132 */ + assign n7890_o = regsh[47:40]; + /* T80_Reg.vhd:150:125 */ + assign n7891_o = {n7889_o, n7890_o}; + /* T80_Reg.vhd:150:143 */ + assign n7892_o = regsl[47:40]; + /* T80_Reg.vhd:150:136 */ + assign n7893_o = {n7891_o, n7892_o}; + /* T80_Reg.vhd:150:154 */ + assign n7894_o = regsh[55:48]; + /* T80_Reg.vhd:150:147 */ + assign n7895_o = {n7893_o, n7894_o}; + /* T80_Reg.vhd:150:165 */ + assign n7896_o = regsl[55:48]; + /* T80_Reg.vhd:150:158 */ + assign n7897_o = {n7895_o, n7896_o}; + /* T80_Reg.vhd:150:176 */ + assign n7898_o = regsh[63:56]; + /* T80_Reg.vhd:150:169 */ + assign n7899_o = {n7897_o, n7898_o}; + /* T80_Reg.vhd:150:187 */ + assign n7900_o = regsl[63:56]; + /* T80_Reg.vhd:150:180 */ + assign n7901_o = {n7899_o, n7900_o}; + /* T80_Reg.vhd:108:17 */ + always @(posedge clk) + n7902_q <= n7835_o; + /* T80_Reg.vhd:108:17 */ + always @(posedge clk) + n7903_q <= n7837_o; + /* T80_Reg.vhd:135:41 */ + assign n7904_o = n7822_o[2]; + /* T80_Reg.vhd:135:41 */ + assign n7905_o = ~n7904_o; + /* T80_Reg.vhd:135:41 */ + assign n7906_o = n7822_o[1]; + /* T80_Reg.vhd:135:41 */ + assign n7907_o = ~n7906_o; + /* T80_Reg.vhd:135:41 */ + assign n7908_o = n7905_o & n7907_o; + /* T80_Reg.vhd:135:41 */ + assign n7909_o = n7905_o & n7906_o; + /* T80_Reg.vhd:135:41 */ + assign n7910_o = n7904_o & n7907_o; + /* T80_Reg.vhd:135:41 */ + assign n7911_o = n7904_o & n7906_o; + /* T80_Reg.vhd:135:41 */ + assign n7912_o = n7822_o[0]; + /* T80_Reg.vhd:135:41 */ + assign n7913_o = ~n7912_o; + /* T80_Reg.vhd:135:41 */ + assign n7914_o = n7908_o & n7913_o; + /* T80_Reg.vhd:135:41 */ + assign n7915_o = n7908_o & n7912_o; + /* T80_Reg.vhd:135:41 */ + assign n7916_o = n7909_o & n7913_o; + /* T80_Reg.vhd:135:41 */ + assign n7917_o = n7909_o & n7912_o; + /* T80_Reg.vhd:135:41 */ + assign n7918_o = n7910_o & n7913_o; + /* T80_Reg.vhd:135:41 */ + assign n7919_o = n7910_o & n7912_o; + /* T80_Reg.vhd:135:41 */ + assign n7920_o = n7911_o & n7913_o; + /* T80_Reg.vhd:135:41 */ + assign n7921_o = n7911_o & n7912_o; + assign n7922_o = regsh[7:0]; + /* T80_Reg.vhd:135:41 */ + assign n7923_o = n7914_o ? dih : n7922_o; + assign n7924_o = regsh[15:8]; + /* T80_Reg.vhd:135:41 */ + assign n7925_o = n7915_o ? dih : n7924_o; + assign n7926_o = regsh[23:16]; + /* T80_Reg.vhd:135:41 */ + assign n7927_o = n7916_o ? dih : n7926_o; + assign n7928_o = regsh[31:24]; + /* T80_Reg.vhd:135:41 */ + assign n7929_o = n7917_o ? dih : n7928_o; + assign n7930_o = regsh[39:32]; + /* T80_Reg.vhd:135:41 */ + assign n7931_o = n7918_o ? dih : n7930_o; + assign n7932_o = regsh[47:40]; + /* T80_Reg.vhd:135:41 */ + assign n7933_o = n7919_o ? dih : n7932_o; + assign n7934_o = regsh[55:48]; + /* T80_Reg.vhd:135:41 */ + assign n7935_o = n7920_o ? dih : n7934_o; + assign n7936_o = regsh[63:56]; + /* T80_Reg.vhd:135:41 */ + assign n7937_o = n7921_o ? dih : n7936_o; + assign n7938_o = {n7937_o, n7935_o, n7933_o, n7931_o, n7929_o, n7927_o, n7925_o, n7923_o}; + /* T80_Reg.vhd:138:41 */ + assign n7939_o = n7828_o[2]; + /* T80_Reg.vhd:138:41 */ + assign n7940_o = ~n7939_o; + /* T80_Reg.vhd:138:41 */ + assign n7941_o = n7828_o[1]; + /* T80_Reg.vhd:138:41 */ + assign n7942_o = ~n7941_o; + /* T80_Reg.vhd:138:41 */ + assign n7943_o = n7940_o & n7942_o; + /* T80_Reg.vhd:138:41 */ + assign n7944_o = n7940_o & n7941_o; + /* T80_Reg.vhd:138:41 */ + assign n7945_o = n7939_o & n7942_o; + /* T80_Reg.vhd:138:41 */ + assign n7946_o = n7939_o & n7941_o; + /* T80_Reg.vhd:138:41 */ + assign n7947_o = n7828_o[0]; + /* T80_Reg.vhd:138:41 */ + assign n7948_o = ~n7947_o; + /* T80_Reg.vhd:138:41 */ + assign n7949_o = n7943_o & n7948_o; + /* T80_Reg.vhd:138:41 */ + assign n7950_o = n7943_o & n7947_o; + /* T80_Reg.vhd:138:41 */ + assign n7951_o = n7944_o & n7948_o; + /* T80_Reg.vhd:138:41 */ + assign n7952_o = n7944_o & n7947_o; + /* T80_Reg.vhd:138:41 */ + assign n7953_o = n7945_o & n7948_o; + /* T80_Reg.vhd:138:41 */ + assign n7954_o = n7945_o & n7947_o; + /* T80_Reg.vhd:138:41 */ + assign n7955_o = n7946_o & n7948_o; + /* T80_Reg.vhd:138:41 */ + assign n7956_o = n7946_o & n7947_o; + assign n7957_o = regsl[7:0]; + /* T80_Reg.vhd:138:41 */ + assign n7958_o = n7949_o ? dil : n7957_o; + assign n7959_o = regsl[15:8]; + /* T80_Reg.vhd:138:41 */ + assign n7960_o = n7950_o ? dil : n7959_o; + assign n7961_o = regsl[23:16]; + /* T80_Reg.vhd:138:41 */ + assign n7962_o = n7951_o ? dil : n7961_o; + assign n7963_o = regsl[31:24]; + /* T80_Reg.vhd:138:41 */ + assign n7964_o = n7952_o ? dil : n7963_o; + assign n7965_o = regsl[39:32]; + /* T80_Reg.vhd:138:41 */ + assign n7966_o = n7953_o ? dil : n7965_o; + assign n7967_o = regsl[47:40]; + /* T80_Reg.vhd:138:41 */ + assign n7968_o = n7954_o ? dil : n7967_o; + assign n7969_o = regsl[55:48]; + /* T80_Reg.vhd:138:41 */ + assign n7970_o = n7955_o ? dil : n7969_o; + assign n7971_o = regsl[63:56]; + /* T80_Reg.vhd:138:41 */ + assign n7972_o = n7956_o ? dil : n7971_o; + assign n7973_o = {n7972_o, n7970_o, n7968_o, n7966_o, n7964_o, n7962_o, n7960_o, n7958_o}; + /* T80_Reg.vhd:138:47 */ + assign n7974_o = regsh[7:0]; + /* T80_Reg.vhd:138:41 */ + assign n7975_o = regsh[15:8]; + assign n7976_o = regsh[23:16]; + assign n7977_o = regsh[31:24]; + assign n7978_o = regsh[39:32]; + assign n7979_o = regsh[47:40]; + assign n7980_o = regsh[55:48]; + assign n7981_o = regsh[63:56]; + /* T80_Reg.vhd:144:22 */ + assign n7982_o = n7843_o[1:0]; + /* T80_Reg.vhd:144:22 */ + always @* + case (n7982_o) + 2'b00: n7983_o = n7974_o; + 2'b01: n7983_o = n7975_o; + 2'b10: n7983_o = n7976_o; + 2'b11: n7983_o = n7977_o; + endcase + /* T80_Reg.vhd:144:22 */ + assign n7984_o = n7843_o[1:0]; + /* T80_Reg.vhd:144:22 */ + always @* + case (n7984_o) + 2'b00: n7985_o = n7978_o; + 2'b01: n7985_o = n7979_o; + 2'b10: n7985_o = n7980_o; + 2'b11: n7985_o = n7981_o; + endcase + /* T80_Reg.vhd:144:22 */ + assign n7986_o = n7843_o[2]; + /* T80_Reg.vhd:144:22 */ + assign n7987_o = n7986_o ? n7985_o : n7983_o; + /* T80_Reg.vhd:144:22 */ + assign n7988_o = regsl[7:0]; + /* T80_Reg.vhd:144:23 */ + assign n7989_o = regsl[15:8]; + assign n7990_o = regsl[23:16]; + assign n7991_o = regsl[31:24]; + assign n7992_o = regsl[39:32]; + assign n7993_o = regsl[47:40]; + assign n7994_o = regsl[55:48]; + assign n7995_o = regsl[63:56]; + /* T80_Reg.vhd:145:22 */ + assign n7996_o = n7848_o[1:0]; + /* T80_Reg.vhd:145:22 */ + always @* + case (n7996_o) + 2'b00: n7997_o = n7988_o; + 2'b01: n7997_o = n7989_o; + 2'b10: n7997_o = n7990_o; + 2'b11: n7997_o = n7991_o; + endcase + /* T80_Reg.vhd:145:22 */ + assign n7998_o = n7848_o[1:0]; + /* T80_Reg.vhd:145:22 */ + always @* + case (n7998_o) + 2'b00: n7999_o = n7992_o; + 2'b01: n7999_o = n7993_o; + 2'b10: n7999_o = n7994_o; + 2'b11: n7999_o = n7995_o; + endcase + /* T80_Reg.vhd:145:22 */ + assign n8000_o = n7848_o[2]; + /* T80_Reg.vhd:145:22 */ + assign n8001_o = n8000_o ? n7999_o : n7997_o; + /* T80_Reg.vhd:145:22 */ + assign n8002_o = regsh[7:0]; + /* T80_Reg.vhd:145:23 */ + assign n8003_o = regsh[15:8]; + assign n8004_o = regsh[23:16]; + assign n8005_o = regsh[31:24]; + assign n8006_o = regsh[39:32]; + assign n8007_o = regsh[47:40]; + assign n8008_o = regsh[55:48]; + assign n8009_o = regsh[63:56]; + /* T80_Reg.vhd:146:22 */ + assign n8010_o = n7853_o[1:0]; + /* T80_Reg.vhd:146:22 */ + always @* + case (n8010_o) + 2'b00: n8011_o = n8002_o; + 2'b01: n8011_o = n8003_o; + 2'b10: n8011_o = n8004_o; + 2'b11: n8011_o = n8005_o; + endcase + /* T80_Reg.vhd:146:22 */ + assign n8012_o = n7853_o[1:0]; + /* T80_Reg.vhd:146:22 */ + always @* + case (n8012_o) + 2'b00: n8013_o = n8006_o; + 2'b01: n8013_o = n8007_o; + 2'b10: n8013_o = n8008_o; + 2'b11: n8013_o = n8009_o; + endcase + /* T80_Reg.vhd:146:22 */ + assign n8014_o = n7853_o[2]; + /* T80_Reg.vhd:146:22 */ + assign n8015_o = n8014_o ? n8013_o : n8011_o; + /* T80_Reg.vhd:146:22 */ + assign n8016_o = regsl[7:0]; + /* T80_Reg.vhd:146:23 */ + assign n8017_o = regsl[15:8]; + assign n8018_o = regsl[23:16]; + assign n8019_o = regsl[31:24]; + assign n8020_o = regsl[39:32]; + assign n8021_o = regsl[47:40]; + assign n8022_o = regsl[55:48]; + assign n8023_o = regsl[63:56]; + /* T80_Reg.vhd:147:22 */ + assign n8024_o = n7858_o[1:0]; + /* T80_Reg.vhd:147:22 */ + always @* + case (n8024_o) + 2'b00: n8025_o = n8016_o; + 2'b01: n8025_o = n8017_o; + 2'b10: n8025_o = n8018_o; + 2'b11: n8025_o = n8019_o; + endcase + /* T80_Reg.vhd:147:22 */ + assign n8026_o = n7858_o[1:0]; + /* T80_Reg.vhd:147:22 */ + always @* + case (n8026_o) + 2'b00: n8027_o = n8020_o; + 2'b01: n8027_o = n8021_o; + 2'b10: n8027_o = n8022_o; + 2'b11: n8027_o = n8023_o; + endcase + /* T80_Reg.vhd:147:22 */ + assign n8028_o = n7858_o[2]; + /* T80_Reg.vhd:147:22 */ + assign n8029_o = n8028_o ? n8027_o : n8025_o; + /* T80_Reg.vhd:147:22 */ + assign n8030_o = regsh[7:0]; + /* T80_Reg.vhd:147:23 */ + assign n8031_o = regsh[15:8]; + assign n8032_o = regsh[23:16]; + assign n8033_o = regsh[31:24]; + assign n8034_o = regsh[39:32]; + assign n8035_o = regsh[47:40]; + assign n8036_o = regsh[55:48]; + assign n8037_o = regsh[63:56]; + /* T80_Reg.vhd:148:22 */ + assign n8038_o = n7863_o[1:0]; + /* T80_Reg.vhd:148:22 */ + always @* + case (n8038_o) + 2'b00: n8039_o = n8030_o; + 2'b01: n8039_o = n8031_o; + 2'b10: n8039_o = n8032_o; + 2'b11: n8039_o = n8033_o; + endcase + /* T80_Reg.vhd:148:22 */ + assign n8040_o = n7863_o[1:0]; + /* T80_Reg.vhd:148:22 */ + always @* + case (n8040_o) + 2'b00: n8041_o = n8034_o; + 2'b01: n8041_o = n8035_o; + 2'b10: n8041_o = n8036_o; + 2'b11: n8041_o = n8037_o; + endcase + /* T80_Reg.vhd:148:22 */ + assign n8042_o = n7863_o[2]; + /* T80_Reg.vhd:148:22 */ + assign n8043_o = n8042_o ? n8041_o : n8039_o; + /* T80_Reg.vhd:148:22 */ + assign n8044_o = regsl[7:0]; + /* T80_Reg.vhd:148:23 */ + assign n8045_o = regsl[15:8]; + assign n8046_o = regsl[23:16]; + assign n8047_o = regsl[31:24]; + assign n8048_o = regsl[39:32]; + assign n8049_o = regsl[47:40]; + assign n8050_o = regsl[55:48]; + assign n8051_o = regsl[63:56]; + /* T80_Reg.vhd:149:22 */ + assign n8052_o = n7868_o[1:0]; + /* T80_Reg.vhd:149:22 */ + always @* + case (n8052_o) + 2'b00: n8053_o = n8044_o; + 2'b01: n8053_o = n8045_o; + 2'b10: n8053_o = n8046_o; + 2'b11: n8053_o = n8047_o; + endcase + /* T80_Reg.vhd:149:22 */ + assign n8054_o = n7868_o[1:0]; + /* T80_Reg.vhd:149:22 */ + always @* + case (n8054_o) + 2'b00: n8055_o = n8048_o; + 2'b01: n8055_o = n8049_o; + 2'b10: n8055_o = n8050_o; + 2'b11: n8055_o = n8051_o; + endcase + /* T80_Reg.vhd:149:22 */ + assign n8056_o = n7868_o[2]; + /* T80_Reg.vhd:149:22 */ + assign n8057_o = n8056_o ? n8055_o : n8053_o; +endmodule + +module t80_alu_0_0_1_2_3_4_5_6_7 + (input arith16, + input z16, + input [15:0] wz, + input [1:0] xy_state, + input [3:0] alu_op, + input [5:0] ir, + input [1:0] iset, + input [7:0] busa, + input [7:0] busb, + input [7:0] f_in, + output [7:0] q, + output [7:0] f_out); + wire usecarry; + wire carry7_v; + wire overflow_v; + wire halfcarry_v; + wire carry_v; + wire [7:0] q_v; + wire [7:0] bitmask; + wire [2:0] n7216_o; + wire n7219_o; + wire n7222_o; + wire n7225_o; + wire n7228_o; + wire n7231_o; + wire n7234_o; + wire n7237_o; + wire [6:0] n7239_o; + reg [7:0] n7240_o; + wire n7241_o; + wire n7242_o; + wire n7243_o; + wire n7244_o; + wire [3:0] n7246_o; + wire [3:0] n7247_o; + wire n7248_o; + wire n7249_o; + wire n7250_o; + wire n7251_o; + wire n7252_o; + wire [3:0] n7257_o; + wire [3:0] n7258_o; + wire [4:0] n7261_o; + wire [5:0] n7262_o; + wire [4:0] n7264_o; + wire [5:0] n7266_o; + wire [5:0] n7267_o; + wire n7269_o; + wire [3:0] n7270_o; + wire [2:0] n7272_o; + wire [2:0] n7273_o; + wire n7274_o; + wire [2:0] n7279_o; + wire [2:0] n7280_o; + wire [3:0] n7283_o; + wire [4:0] n7284_o; + wire [3:0] n7286_o; + wire [4:0] n7288_o; + wire [4:0] n7289_o; + wire n7291_o; + wire [2:0] n7292_o; + wire n7294_o; + wire n7295_o; + wire n7296_o; + wire n7301_o; + wire n7302_o; + wire [1:0] n7305_o; + wire [2:0] n7306_o; + wire [1:0] n7308_o; + wire [2:0] n7310_o; + wire [2:0] n7311_o; + wire n7313_o; + wire n7314_o; + wire n7317_o; + wire [2:0] n7325_o; + wire n7327_o; + wire n7329_o; + wire n7330_o; + wire n7332_o; + wire n7333_o; + wire n7335_o; + wire n7337_o; + wire n7338_o; + wire n7340_o; + wire n7341_o; + wire [7:0] n7342_o; + wire n7345_o; + wire [7:0] n7346_o; + wire n7349_o; + wire [7:0] n7350_o; + wire [3:0] n7352_o; + reg n7353_o; + reg n7354_o; + wire n7355_o; + reg n7356_o; + reg n7357_o; + reg [7:0] n7358_o; + wire [2:0] n7359_o; + wire n7361_o; + wire n7362_o; + wire n7363_o; + wire n7364_o; + wire n7365_o; + wire n7366_o; + wire n7367_o; + wire n7369_o; + wire n7371_o; + wire n7372_o; + wire n7374_o; + wire n7375_o; + wire [2:0] n7376_o; + wire n7378_o; + wire n7380_o; + wire n7381_o; + wire n7383_o; + wire n7384_o; + wire n7386_o; + wire n7387_o; + wire n7389_o; + wire n7390_o; + wire n7391_o; + wire n7392_o; + wire n7393_o; + wire n7394_o; + wire n7395_o; + wire n7396_o; + wire n7397_o; + wire n7398_o; + wire n7399_o; + wire n7400_o; + wire n7401_o; + wire n7402_o; + wire n7403_o; + wire n7404_o; + wire n7405_o; + wire n7406_o; + reg n7407_o; + wire n7408_o; + wire n7409_o; + wire n7410_o; + wire [1:0] n7411_o; + wire n7412_o; + wire [1:0] n7413_o; + wire [1:0] n7414_o; + wire n7416_o; + wire n7418_o; + wire n7419_o; + wire n7421_o; + wire n7422_o; + wire n7424_o; + wire n7425_o; + wire n7427_o; + wire n7428_o; + wire n7430_o; + wire n7431_o; + wire n7433_o; + wire n7434_o; + wire n7436_o; + wire n7437_o; + wire n7438_o; + wire n7441_o; + wire n7442_o; + wire [8:0] n7443_o; + wire [3:0] n7444_o; + wire n7446_o; + wire n7447_o; + wire n7448_o; + wire [8:0] n7449_o; + wire [3:0] n7450_o; + wire n7452_o; + wire n7455_o; + wire [8:0] n7456_o; + wire [8:0] n7458_o; + wire n7459_o; + wire [8:0] n7460_o; + wire [8:0] n7461_o; + wire [4:0] n7462_o; + wire n7464_o; + wire n7465_o; + wire n7466_o; + wire [8:0] n7468_o; + wire [8:0] n7469_o; + wire [8:0] n7470_o; + wire [3:0] n7471_o; + wire n7473_o; + wire n7474_o; + wire n7475_o; + wire [8:0] n7476_o; + wire [3:0] n7477_o; + wire n7479_o; + wire n7481_o; + wire [8:0] n7482_o; + wire [7:0] n7483_o; + wire [7:0] n7485_o; + wire n7486_o; + wire [7:0] n7487_o; + wire n7489_o; + wire n7490_o; + wire n7491_o; + wire [8:0] n7492_o; + wire [8:0] n7494_o; + wire [8:0] n7495_o; + wire [8:0] n7496_o; + wire n7497_o; + wire [8:0] n7498_o; + wire n7499_o; + wire n7500_o; + wire n7501_o; + wire n7502_o; + wire n7503_o; + wire [7:0] n7504_o; + wire [7:0] n7505_o; + wire n7507_o; + wire n7510_o; + wire n7511_o; + wire n7512_o; + wire n7513_o; + wire n7514_o; + wire n7515_o; + wire n7516_o; + wire n7517_o; + wire n7518_o; + wire n7519_o; + wire n7520_o; + wire n7521_o; + wire n7522_o; + wire n7523_o; + wire n7524_o; + wire n7525_o; + wire n7526_o; + wire n7527_o; + wire n7529_o; + wire [3:0] n7530_o; + wire n7531_o; + wire [3:0] n7532_o; + wire [3:0] n7533_o; + wire [3:0] n7534_o; + wire [7:0] n7537_o; + wire n7538_o; + wire [7:0] n7539_o; + wire n7540_o; + wire [7:0] n7541_o; + wire n7543_o; + wire n7546_o; + wire [7:0] n7547_o; + wire n7548_o; + wire [7:0] n7549_o; + wire n7550_o; + wire [7:0] n7551_o; + wire n7552_o; + wire n7553_o; + wire [7:0] n7554_o; + wire n7555_o; + wire n7556_o; + wire [7:0] n7557_o; + wire n7558_o; + wire n7559_o; + wire [7:0] n7560_o; + wire n7561_o; + wire n7562_o; + wire [7:0] n7563_o; + wire n7564_o; + wire n7565_o; + wire [7:0] n7566_o; + wire n7567_o; + wire n7568_o; + wire [7:0] n7569_o; + wire n7570_o; + wire n7571_o; + wire n7572_o; + wire n7574_o; + wire n7576_o; + wire n7577_o; + wire [7:0] n7578_o; + wire n7579_o; + wire n7581_o; + wire n7586_o; + wire n7587_o; + wire [2:0] n7590_o; + wire n7592_o; + wire n7594_o; + wire n7595_o; + wire n7596_o; + wire n7597_o; + wire n7598_o; + wire n7599_o; + wire n7600_o; + wire n7601_o; + wire n7603_o; + wire [7:0] n7604_o; + wire n7606_o; + wire [7:0] n7607_o; + wire [7:0] n7608_o; + wire n7610_o; + wire [2:0] n7611_o; + wire [6:0] n7612_o; + wire n7613_o; + wire n7614_o; + wire n7616_o; + wire [6:0] n7617_o; + wire n7618_o; + wire n7619_o; + wire n7621_o; + wire [6:0] n7622_o; + wire n7623_o; + wire n7624_o; + wire n7626_o; + wire [6:0] n7627_o; + wire n7628_o; + wire n7629_o; + wire n7631_o; + wire [6:0] n7632_o; + wire n7634_o; + wire n7636_o; + wire [6:0] n7637_o; + wire n7639_o; + wire n7641_o; + wire [6:0] n7642_o; + wire n7643_o; + wire n7644_o; + wire n7646_o; + wire [6:0] n7647_o; + wire n7649_o; + wire [6:0] n7650_o; + reg n7651_o; + wire n7652_o; + wire n7653_o; + wire n7654_o; + wire n7655_o; + reg n7656_o; + wire [5:0] n7657_o; + wire [5:0] n7658_o; + wire [5:0] n7659_o; + wire [5:0] n7660_o; + wire [5:0] n7661_o; + wire [5:0] n7662_o; + wire [5:0] n7663_o; + wire [5:0] n7664_o; + reg [5:0] n7665_o; + wire n7666_o; + wire n7667_o; + wire n7668_o; + wire n7669_o; + reg n7670_o; + wire [7:0] n7673_o; + wire n7674_o; + wire [7:0] n7675_o; + wire n7676_o; + wire [7:0] n7677_o; + wire n7678_o; + wire [7:0] n7679_o; + wire n7681_o; + wire n7684_o; + wire [7:0] n7685_o; + wire n7686_o; + wire [7:0] n7687_o; + wire n7688_o; + wire n7689_o; + wire [7:0] n7690_o; + wire n7691_o; + wire n7692_o; + wire [7:0] n7693_o; + wire n7694_o; + wire n7695_o; + wire [7:0] n7696_o; + wire n7697_o; + wire n7698_o; + wire [7:0] n7699_o; + wire n7700_o; + wire n7701_o; + wire [7:0] n7702_o; + wire n7703_o; + wire n7704_o; + wire [7:0] n7705_o; + wire n7706_o; + wire n7707_o; + wire n7708_o; + wire n7710_o; + wire n7711_o; + wire n7712_o; + wire n7713_o; + wire [1:0] n7714_o; + wire n7715_o; + wire [1:0] n7716_o; + wire [1:0] n7717_o; + wire n7719_o; + wire [6:0] n7720_o; + wire n7721_o; + reg n7722_o; + wire n7723_o; + reg n7724_o; + wire n7725_o; + reg n7726_o; + wire n7727_o; + reg n7728_o; + wire n7729_o; + reg n7730_o; + wire n7731_o; + reg n7732_o; + wire n7733_o; + wire n7734_o; + wire n7735_o; + reg n7736_o; + wire n7737_o; + wire n7738_o; + wire n7739_o; + reg n7740_o; + wire n7748_o; + wire n7749_o; + wire n7750_o; + wire n7751_o; + wire n7752_o; + wire n7753_o; + reg n7755_o; + wire [2:0] n7756_o; + wire [2:0] n7757_o; + wire [2:0] n7758_o; + wire [2:0] n7759_o; + wire [2:0] n7760_o; + wire [2:0] n7761_o; + wire [2:0] n7762_o; + reg [2:0] n7764_o; + wire [2:0] n7765_o; + wire [2:0] n7766_o; + wire [2:0] n7767_o; + wire [2:0] n7768_o; + wire [2:0] n7769_o; + wire [2:0] n7770_o; + wire [2:0] n7771_o; + reg [2:0] n7773_o; + wire n7774_o; + wire n7775_o; + wire n7776_o; + wire n7777_o; + wire n7778_o; + wire n7779_o; + reg n7781_o; + wire [7:0] n7789_o; + wire [7:0] n7792_o; + wire [7:0] n7793_o; + assign q = n7789_o; + assign f_out = n7793_o; + /* T80_ALU.vhd:126:16 */ + assign usecarry = n7244_o; // (signal) + /* T80_ALU.vhd:127:16 */ + assign carry7_v = n7291_o; // (signal) + /* T80_ALU.vhd:128:16 */ + assign overflow_v = n7317_o; // (signal) + /* T80_ALU.vhd:129:16 */ + assign halfcarry_v = n7269_o; // (signal) + /* T80_ALU.vhd:130:16 */ + assign carry_v = n7313_o; // (signal) + /* T80_ALU.vhd:131:16 */ + assign q_v = n7792_o; // (signal) + /* T80_ALU.vhd:133:16 */ + assign bitmask = n7240_o; // (signal) + /* T80_ALU.vhd:137:16 */ + assign n7216_o = ir[5:3]; + /* T80_ALU.vhd:137:58 */ + assign n7219_o = n7216_o == 3'b000; + /* T80_ALU.vhd:138:94 */ + assign n7222_o = n7216_o == 3'b001; + /* T80_ALU.vhd:139:94 */ + assign n7225_o = n7216_o == 3'b010; + /* T80_ALU.vhd:140:94 */ + assign n7228_o = n7216_o == 3'b011; + /* T80_ALU.vhd:141:94 */ + assign n7231_o = n7216_o == 3'b100; + /* T80_ALU.vhd:142:94 */ + assign n7234_o = n7216_o == 3'b101; + /* T80_ALU.vhd:143:94 */ + assign n7237_o = n7216_o == 3'b110; + /* T80_MCode.vhd:113:7 */ + assign n7239_o = {n7237_o, n7234_o, n7231_o, n7228_o, n7225_o, n7222_o, n7219_o}; + /* T80_ALU.vhd:137:9 */ + always @* + case (n7239_o) + 7'b1000000: n7240_o = 8'b01000000; + 7'b0100000: n7240_o = 8'b00100000; + 7'b0010000: n7240_o = 8'b00010000; + 7'b0001000: n7240_o = 8'b00001000; + 7'b0000100: n7240_o = 8'b00000100; + 7'b0000010: n7240_o = 8'b00000010; + 7'b0000001: n7240_o = 8'b00000001; + default: n7240_o = 8'b10000000; + endcase + /* T80_ALU.vhd:146:31 */ + assign n7241_o = alu_op[2]; + /* T80_ALU.vhd:146:21 */ + assign n7242_o = ~n7241_o; + /* T80_ALU.vhd:146:45 */ + assign n7243_o = alu_op[0]; + /* T80_ALU.vhd:146:35 */ + assign n7244_o = n7242_o & n7243_o; + /* T80_ALU.vhd:147:20 */ + assign n7246_o = busa[3:0]; + /* T80_ALU.vhd:147:38 */ + assign n7247_o = busb[3:0]; + /* T80_ALU.vhd:147:58 */ + assign n7248_o = alu_op[1]; + /* T80_ALU.vhd:147:69 */ + assign n7249_o = alu_op[1]; + /* T80_ALU.vhd:147:95 */ + assign n7250_o = f_in[0]; + /* T80_ALU.vhd:147:87 */ + assign n7251_o = usecarry & n7250_o; + /* T80_ALU.vhd:147:73 */ + assign n7252_o = n7249_o ^ n7251_o; + /* T80_ALU.vhd:115:32 */ + assign n7257_o = ~n7247_o; + /* T80_ALU.vhd:114:17 */ + assign n7258_o = n7248_o ? n7257_o : n7247_o; + /* T80_ALU.vhd:120:39 */ + assign n7261_o = {1'b0, n7246_o}; + /* T80_ALU.vhd:120:43 */ + assign n7262_o = {n7261_o, n7252_o}; + /* T80_ALU.vhd:120:70 */ + assign n7264_o = {1'b0, n7258_o}; + /* T80_ALU.vhd:120:76 */ + assign n7266_o = {n7264_o, 1'b1}; + /* T80_ALU.vhd:120:55 */ + assign n7267_o = n7262_o + n7266_o; + /* T80_ALU.vhd:121:31 */ + assign n7269_o = n7267_o[5]; + /* T80_ALU.vhd:122:46 */ + assign n7270_o = n7267_o[4:1]; + /* T80_ALU.vhd:148:20 */ + assign n7272_o = busa[6:4]; + /* T80_ALU.vhd:148:38 */ + assign n7273_o = busb[6:4]; + /* T80_ALU.vhd:148:58 */ + assign n7274_o = alu_op[1]; + /* T80_ALU.vhd:115:32 */ + assign n7279_o = ~n7273_o; + /* T80_ALU.vhd:114:17 */ + assign n7280_o = n7274_o ? n7279_o : n7273_o; + /* T80_ALU.vhd:120:39 */ + assign n7283_o = {1'b0, n7272_o}; + /* T80_ALU.vhd:120:43 */ + assign n7284_o = {n7283_o, halfcarry_v}; + /* T80_ALU.vhd:120:70 */ + assign n7286_o = {1'b0, n7280_o}; + /* T80_ALU.vhd:120:76 */ + assign n7288_o = {n7286_o, 1'b1}; + /* T80_ALU.vhd:120:55 */ + assign n7289_o = n7284_o + n7288_o; + /* T80_ALU.vhd:121:31 */ + assign n7291_o = n7289_o[4]; + /* T80_ALU.vhd:122:46 */ + assign n7292_o = n7289_o[3:1]; + /* T80_ALU.vhd:149:20 */ + assign n7294_o = busa[7]; + /* T80_ALU.vhd:149:38 */ + assign n7295_o = busb[7]; + /* T80_ALU.vhd:149:58 */ + assign n7296_o = alu_op[1]; + /* T80_ALU.vhd:115:32 */ + assign n7301_o = ~n7295_o; + /* T80_ALU.vhd:114:17 */ + assign n7302_o = n7296_o ? n7301_o : n7295_o; + /* T80_ALU.vhd:120:39 */ + assign n7305_o = {1'b0, n7294_o}; + /* T80_ALU.vhd:120:43 */ + assign n7306_o = {n7305_o, carry7_v}; + /* T80_ALU.vhd:120:70 */ + assign n7308_o = {1'b0, n7302_o}; + /* T80_ALU.vhd:120:76 */ + assign n7310_o = {n7308_o, 1'b1}; + /* T80_ALU.vhd:120:55 */ + assign n7311_o = n7306_o + n7310_o; + /* T80_ALU.vhd:121:31 */ + assign n7313_o = n7311_o[2]; + /* T80_ALU.vhd:122:46 */ + assign n7314_o = n7311_o[1]; + /* T80_ALU.vhd:157:47 */ + assign n7317_o = carry_v ^ carry7_v; + /* T80_ALU.vhd:172:36 */ + assign n7325_o = alu_op[2:0]; + /* T80_ALU.vhd:173:25 */ + assign n7327_o = n7325_o == 3'b000; + /* T80_ALU.vhd:173:36 */ + assign n7329_o = n7325_o == 3'b001; + /* T80_ALU.vhd:173:36 */ + assign n7330_o = n7327_o | n7329_o; + /* T80_ALU.vhd:181:50 */ + assign n7332_o = ~carry_v; + /* T80_ALU.vhd:182:50 */ + assign n7333_o = ~halfcarry_v; + /* T80_ALU.vhd:178:25 */ + assign n7335_o = n7325_o == 3'b010; + /* T80_ALU.vhd:178:36 */ + assign n7337_o = n7325_o == 3'b011; + /* T80_ALU.vhd:178:36 */ + assign n7338_o = n7335_o | n7337_o; + /* T80_ALU.vhd:178:44 */ + assign n7340_o = n7325_o == 3'b111; + /* T80_ALU.vhd:178:44 */ + assign n7341_o = n7338_o | n7340_o; + /* T80_ALU.vhd:185:57 */ + assign n7342_o = busa & busb; + /* T80_ALU.vhd:184:25 */ + assign n7345_o = n7325_o == 3'b100; + /* T80_ALU.vhd:188:57 */ + assign n7346_o = busa ^ busb; + /* T80_ALU.vhd:187:25 */ + assign n7349_o = n7325_o == 3'b101; + /* T80_ALU.vhd:191:57 */ + assign n7350_o = busa | busb; + assign n7352_o = {n7349_o, n7345_o, n7341_o, n7330_o}; + /* T80_ALU.vhd:172:25 */ + always @* + case (n7352_o) + 4'b1000: n7353_o = 1'b0; + 4'b0100: n7353_o = 1'b0; + 4'b0010: n7353_o = n7332_o; + 4'b0001: n7353_o = carry_v; + default: n7353_o = 1'b0; + endcase + /* T80_ALU.vhd:172:25 */ + always @* + case (n7352_o) + 4'b1000: n7354_o = 1'b0; + 4'b0100: n7354_o = 1'b0; + 4'b0010: n7354_o = 1'b1; + 4'b0001: n7354_o = 1'b0; + default: n7354_o = 1'b0; + endcase + assign n7355_o = f_in[2]; + /* T80_ALU.vhd:172:25 */ + always @* + case (n7352_o) + 4'b1000: n7356_o = n7355_o; + 4'b0100: n7356_o = n7355_o; + 4'b0010: n7356_o = overflow_v; + 4'b0001: n7356_o = overflow_v; + default: n7356_o = n7355_o; + endcase + /* T80_ALU.vhd:172:25 */ + always @* + case (n7352_o) + 4'b1000: n7357_o = 1'b0; + 4'b0100: n7357_o = 1'b1; + 4'b0010: n7357_o = n7333_o; + 4'b0001: n7357_o = halfcarry_v; + default: n7357_o = 1'b0; + endcase + /* T80_ALU.vhd:201:31 */ + always @* + case (n7352_o) + 4'b1000: n7358_o = n7346_o; + 4'b0100: n7358_o = n7342_o; + 4'b0010: n7358_o = q_v; + 4'b0001: n7358_o = q_v; + default: n7358_o = n7350_o; + endcase + /* T80_ALU.vhd:194:34 */ + assign n7359_o = alu_op[2:0]; + /* T80_ALU.vhd:194:47 */ + assign n7361_o = n7359_o == 3'b111; + /* T80_ALU.vhd:195:54 */ + assign n7362_o = busb[3]; + /* T80_ALU.vhd:196:54 */ + assign n7363_o = busb[5]; + /* T80_ALU.vhd:198:53 */ + assign n7364_o = n7358_o[3]; + /* T80_ALU.vhd:199:53 */ + assign n7365_o = n7358_o[5]; + /* T80_ALU.vhd:194:25 */ + assign n7366_o = n7361_o ? n7362_o : n7364_o; + /* T80_ALU.vhd:194:25 */ + assign n7367_o = n7361_o ? n7363_o : n7365_o; + /* T80_ALU.vhd:201:44 */ + assign n7369_o = n7358_o == 8'b00000000; + /* T80_ALU.vhd:204:62 */ + assign n7371_o = f_in[6]; + /* T80_ALU.vhd:203:33 */ + assign n7372_o = z16 ? n7371_o : 1'b1; + /* T80_ALU.vhd:201:25 */ + assign n7374_o = n7369_o ? n7372_o : 1'b0; + /* T80_ALU.vhd:209:45 */ + assign n7375_o = n7358_o[7]; + /* T80_ALU.vhd:210:36 */ + assign n7376_o = alu_op[2:0]; + /* T80_ALU.vhd:211:25 */ + assign n7378_o = n7376_o == 3'b000; + /* T80_ALU.vhd:211:36 */ + assign n7380_o = n7376_o == 3'b001; + /* T80_ALU.vhd:211:36 */ + assign n7381_o = n7378_o | n7380_o; + /* T80_ALU.vhd:211:44 */ + assign n7383_o = n7376_o == 3'b010; + /* T80_ALU.vhd:211:44 */ + assign n7384_o = n7381_o | n7383_o; + /* T80_ALU.vhd:211:52 */ + assign n7386_o = n7376_o == 3'b011; + /* T80_ALU.vhd:211:52 */ + assign n7387_o = n7384_o | n7386_o; + /* T80_ALU.vhd:211:60 */ + assign n7389_o = n7376_o == 3'b111; + /* T80_ALU.vhd:211:60 */ + assign n7390_o = n7387_o | n7389_o; + /* T80_ALU.vhd:213:58 */ + assign n7391_o = n7358_o[0]; + /* T80_ALU.vhd:213:69 */ + assign n7392_o = n7358_o[1]; + /* T80_ALU.vhd:213:62 */ + assign n7393_o = n7391_o ^ n7392_o; + /* T80_ALU.vhd:213:80 */ + assign n7394_o = n7358_o[2]; + /* T80_ALU.vhd:213:73 */ + assign n7395_o = n7393_o ^ n7394_o; + /* T80_ALU.vhd:213:91 */ + assign n7396_o = n7358_o[3]; + /* T80_ALU.vhd:213:84 */ + assign n7397_o = n7395_o ^ n7396_o; + /* T80_ALU.vhd:214:44 */ + assign n7398_o = n7358_o[4]; + /* T80_ALU.vhd:213:95 */ + assign n7399_o = n7397_o ^ n7398_o; + /* T80_ALU.vhd:214:55 */ + assign n7400_o = n7358_o[5]; + /* T80_ALU.vhd:214:48 */ + assign n7401_o = n7399_o ^ n7400_o; + /* T80_ALU.vhd:214:66 */ + assign n7402_o = n7358_o[6]; + /* T80_ALU.vhd:214:59 */ + assign n7403_o = n7401_o ^ n7402_o; + /* T80_ALU.vhd:214:77 */ + assign n7404_o = n7358_o[7]; + /* T80_ALU.vhd:214:70 */ + assign n7405_o = n7403_o ^ n7404_o; + /* T80_ALU.vhd:213:50 */ + assign n7406_o = ~n7405_o; + /* T80_ALU.vhd:210:25 */ + always @* + case (n7390_o) + 1'b1: n7407_o = n7356_o; + default: n7407_o = n7406_o; + endcase + /* T80_ALU.vhd:217:54 */ + assign n7408_o = f_in[7]; + /* T80_ALU.vhd:218:54 */ + assign n7409_o = f_in[6]; + /* T80_ALU.vhd:219:54 */ + assign n7410_o = f_in[2]; + assign n7411_o = {n7408_o, n7409_o}; + /* T80_ALU.vhd:216:25 */ + assign n7412_o = arith16 ? n7410_o : n7407_o; + assign n7413_o = {n7375_o, n7374_o}; + /* T80_ALU.vhd:216:25 */ + assign n7414_o = arith16 ? n7411_o : n7413_o; + /* T80_ALU.vhd:169:17 */ + assign n7416_o = alu_op == 4'b0000; + /* T80_ALU.vhd:169:29 */ + assign n7418_o = alu_op == 4'b0001; + /* T80_ALU.vhd:169:29 */ + assign n7419_o = n7416_o | n7418_o; + /* T80_ALU.vhd:169:38 */ + assign n7421_o = alu_op == 4'b0010; + /* T80_ALU.vhd:169:38 */ + assign n7422_o = n7419_o | n7421_o; + /* T80_ALU.vhd:169:48 */ + assign n7424_o = alu_op == 4'b0011; + /* T80_ALU.vhd:169:48 */ + assign n7425_o = n7422_o | n7424_o; + /* T80_ALU.vhd:169:57 */ + assign n7427_o = alu_op == 4'b0100; + /* T80_ALU.vhd:169:57 */ + assign n7428_o = n7425_o | n7427_o; + /* T80_ALU.vhd:169:66 */ + assign n7430_o = alu_op == 4'b0101; + /* T80_ALU.vhd:169:66 */ + assign n7431_o = n7428_o | n7430_o; + /* T80_ALU.vhd:169:75 */ + assign n7433_o = alu_op == 4'b0110; + /* T80_ALU.vhd:169:75 */ + assign n7434_o = n7431_o | n7433_o; + /* T80_ALU.vhd:169:84 */ + assign n7436_o = alu_op == 4'b0111; + /* T80_ALU.vhd:169:84 */ + assign n7437_o = n7434_o | n7436_o; + /* T80_ALU.vhd:223:46 */ + assign n7438_o = f_in[4]; + /* T80_ALU.vhd:227:32 */ + assign n7441_o = f_in[1]; + /* T80_ALU.vhd:227:41 */ + assign n7442_o = ~n7441_o; + assign n7443_o = {1'b0, busa}; + /* T80_ALU.vhd:230:41 */ + assign n7444_o = n7443_o[3:0]; + /* T80_ALU.vhd:230:54 */ + assign n7446_o = $unsigned(n7444_o) > $unsigned(4'b1001); + /* T80_ALU.vhd:230:65 */ + assign n7447_o = f_in[4]; + /* T80_ALU.vhd:230:58 */ + assign n7448_o = n7446_o | n7447_o; + assign n7449_o = {1'b0, busa}; + /* T80_ALU.vhd:231:50 */ + assign n7450_o = n7449_o[3:0]; + /* T80_ALU.vhd:231:63 */ + assign n7452_o = $unsigned(n7450_o) > $unsigned(4'b1001); + /* T80_ALU.vhd:231:41 */ + assign n7455_o = n7452_o ? 1'b1 : 1'b0; + assign n7456_o = {1'b0, busa}; + /* T80_ALU.vhd:236:56 */ + assign n7458_o = n7456_o + 9'b000000110; + /* T80_ALU.vhd:230:33 */ + assign n7459_o = n7448_o ? n7455_o : n7438_o; + assign n7460_o = {1'b0, busa}; + /* T80_ALU.vhd:230:33 */ + assign n7461_o = n7448_o ? n7458_o : n7460_o; + /* T80_ALU.vhd:239:41 */ + assign n7462_o = n7461_o[8:4]; + /* T80_ALU.vhd:239:54 */ + assign n7464_o = $unsigned(n7462_o) > $unsigned(5'b01001); + /* T80_ALU.vhd:239:65 */ + assign n7465_o = f_in[0]; + /* T80_ALU.vhd:239:58 */ + assign n7466_o = n7464_o | n7465_o; + /* T80_ALU.vhd:240:56 */ + assign n7468_o = n7461_o + 9'b001100000; + /* T80_ALU.vhd:239:33 */ + assign n7469_o = n7466_o ? n7468_o : n7461_o; + assign n7470_o = {1'b0, busa}; + /* T80_ALU.vhd:244:41 */ + assign n7471_o = n7470_o[3:0]; + /* T80_ALU.vhd:244:54 */ + assign n7473_o = $unsigned(n7471_o) > $unsigned(4'b1001); + /* T80_ALU.vhd:244:65 */ + assign n7474_o = f_in[4]; + /* T80_ALU.vhd:244:58 */ + assign n7475_o = n7473_o | n7474_o; + assign n7476_o = {1'b0, busa}; + /* T80_ALU.vhd:245:49 */ + assign n7477_o = n7476_o[3:0]; + /* T80_ALU.vhd:245:62 */ + assign n7479_o = $unsigned(n7477_o) > $unsigned(4'b0101); + /* T80_ALU.vhd:244:33 */ + assign n7481_o = n7486_o ? 1'b0 : n7438_o; + assign n7482_o = {1'b0, busa}; + /* T80_ALU.vhd:248:67 */ + assign n7483_o = n7482_o[7:0]; + /* T80_ALU.vhd:248:80 */ + assign n7485_o = n7483_o - 8'b00000110; + /* T80_ALU.vhd:244:33 */ + assign n7486_o = n7475_o & n7479_o; + /* T80_ALU.vhd:244:33 */ + assign n7487_o = n7475_o ? n7485_o : busa; + /* T80_ALU.vhd:250:51 */ + assign n7489_o = $unsigned(busa) > $unsigned(8'b10011001); + /* T80_ALU.vhd:250:64 */ + assign n7490_o = f_in[0]; + /* T80_ALU.vhd:250:57 */ + assign n7491_o = n7489_o | n7490_o; + assign n7492_o = {1'b0, n7487_o}; + /* T80_ALU.vhd:251:56 */ + assign n7494_o = n7492_o - 9'b101100000; + assign n7495_o = {1'b0, n7487_o}; + /* T80_ALU.vhd:250:33 */ + assign n7496_o = n7491_o ? n7494_o : n7495_o; + /* T80_ALU.vhd:227:25 */ + assign n7497_o = n7442_o ? n7459_o : n7481_o; + /* T80_ALU.vhd:227:25 */ + assign n7498_o = n7442_o ? n7469_o : n7496_o; + /* T80_ALU.vhd:254:47 */ + assign n7499_o = n7498_o[3]; + /* T80_ALU.vhd:255:47 */ + assign n7500_o = n7498_o[5]; + /* T80_ALU.vhd:256:46 */ + assign n7501_o = f_in[0]; + /* T80_ALU.vhd:256:63 */ + assign n7502_o = n7498_o[8]; + /* T80_ALU.vhd:256:55 */ + assign n7503_o = n7501_o | n7502_o; + /* T80_ALU.vhd:257:54 */ + assign n7504_o = n7498_o[7:0]; + /* T80_ALU.vhd:258:33 */ + assign n7505_o = n7498_o[7:0]; + /* T80_ALU.vhd:258:46 */ + assign n7507_o = n7505_o == 8'b00000000; + /* T80_ALU.vhd:258:25 */ + assign n7510_o = n7507_o ? 1'b1 : 1'b0; + /* T80_ALU.vhd:263:47 */ + assign n7511_o = n7498_o[7]; + /* T80_ALU.vhd:264:52 */ + assign n7512_o = n7498_o[0]; + /* T80_ALU.vhd:264:65 */ + assign n7513_o = n7498_o[1]; + /* T80_ALU.vhd:264:56 */ + assign n7514_o = n7512_o ^ n7513_o; + /* T80_ALU.vhd:264:78 */ + assign n7515_o = n7498_o[2]; + /* T80_ALU.vhd:264:69 */ + assign n7516_o = n7514_o ^ n7515_o; + /* T80_ALU.vhd:264:91 */ + assign n7517_o = n7498_o[3]; + /* T80_ALU.vhd:264:82 */ + assign n7518_o = n7516_o ^ n7517_o; + /* T80_ALU.vhd:265:38 */ + assign n7519_o = n7498_o[4]; + /* T80_ALU.vhd:264:95 */ + assign n7520_o = n7518_o ^ n7519_o; + /* T80_ALU.vhd:265:51 */ + assign n7521_o = n7498_o[5]; + /* T80_ALU.vhd:265:42 */ + assign n7522_o = n7520_o ^ n7521_o; + /* T80_ALU.vhd:265:64 */ + assign n7523_o = n7498_o[6]; + /* T80_ALU.vhd:265:55 */ + assign n7524_o = n7522_o ^ n7523_o; + /* T80_ALU.vhd:265:77 */ + assign n7525_o = n7498_o[7]; + /* T80_ALU.vhd:265:68 */ + assign n7526_o = n7524_o ^ n7525_o; + /* T80_ALU.vhd:264:42 */ + assign n7527_o = ~n7526_o; + /* T80_ALU.vhd:221:17 */ + assign n7529_o = alu_op == 4'b1100; + /* T80_ALU.vhd:268:48 */ + assign n7530_o = busa[7:4]; + /* T80_ALU.vhd:269:34 */ + assign n7531_o = alu_op[0]; + /* T80_ALU.vhd:270:56 */ + assign n7532_o = busb[7:4]; + /* T80_ALU.vhd:272:56 */ + assign n7533_o = busb[3:0]; + /* T80_ALU.vhd:269:25 */ + assign n7534_o = n7531_o ? n7532_o : n7533_o; + assign n7537_o = {n7530_o, n7534_o}; + /* T80_ALU.vhd:276:45 */ + assign n7538_o = n7537_o[3]; + assign n7539_o = {n7530_o, n7534_o}; + /* T80_ALU.vhd:277:45 */ + assign n7540_o = n7539_o[5]; + /* T80_ALU.vhd:278:31 */ + assign n7541_o = {n7530_o, n7534_o}; + /* T80_ALU.vhd:278:44 */ + assign n7543_o = n7541_o == 8'b00000000; + /* T80_ALU.vhd:278:25 */ + assign n7546_o = n7543_o ? 1'b1 : 1'b0; + assign n7547_o = {n7530_o, n7534_o}; + /* T80_ALU.vhd:283:45 */ + assign n7548_o = n7547_o[7]; + assign n7549_o = {n7530_o, n7534_o}; + /* T80_ALU.vhd:284:50 */ + assign n7550_o = n7549_o[0]; + assign n7551_o = {n7530_o, n7534_o}; + /* T80_ALU.vhd:284:61 */ + assign n7552_o = n7551_o[1]; + /* T80_ALU.vhd:284:54 */ + assign n7553_o = n7550_o ^ n7552_o; + assign n7554_o = {n7530_o, n7534_o}; + /* T80_ALU.vhd:284:72 */ + assign n7555_o = n7554_o[2]; + /* T80_ALU.vhd:284:65 */ + assign n7556_o = n7553_o ^ n7555_o; + assign n7557_o = {n7530_o, n7534_o}; + /* T80_ALU.vhd:284:83 */ + assign n7558_o = n7557_o[3]; + /* T80_ALU.vhd:284:76 */ + assign n7559_o = n7556_o ^ n7558_o; + assign n7560_o = {n7530_o, n7534_o}; + /* T80_ALU.vhd:285:36 */ + assign n7561_o = n7560_o[4]; + /* T80_ALU.vhd:284:87 */ + assign n7562_o = n7559_o ^ n7561_o; + assign n7563_o = {n7530_o, n7534_o}; + /* T80_ALU.vhd:285:47 */ + assign n7564_o = n7563_o[5]; + /* T80_ALU.vhd:285:40 */ + assign n7565_o = n7562_o ^ n7564_o; + assign n7566_o = {n7530_o, n7534_o}; + /* T80_ALU.vhd:285:58 */ + assign n7567_o = n7566_o[6]; + /* T80_ALU.vhd:285:51 */ + assign n7568_o = n7565_o ^ n7567_o; + assign n7569_o = {n7530_o, n7534_o}; + /* T80_ALU.vhd:285:69 */ + assign n7570_o = n7569_o[7]; + /* T80_ALU.vhd:285:62 */ + assign n7571_o = n7568_o ^ n7570_o; + /* T80_ALU.vhd:284:42 */ + assign n7572_o = ~n7571_o; + /* T80_ALU.vhd:266:17 */ + assign n7574_o = alu_op == 4'b1101; + /* T80_ALU.vhd:266:29 */ + assign n7576_o = alu_op == 4'b1110; + /* T80_ALU.vhd:266:29 */ + assign n7577_o = n7574_o | n7576_o; + /* T80_ALU.vhd:290:31 */ + assign n7578_o = busb & bitmask; + /* T80_ALU.vhd:289:45 */ + assign n7579_o = n7578_o[7]; + /* T80_ALU.vhd:290:44 */ + assign n7581_o = n7578_o == 8'b00000000; + /* T80_ALU.vhd:290:25 */ + assign n7586_o = n7581_o ? 1'b1 : 1'b0; + /* T80_ALU.vhd:290:25 */ + assign n7587_o = n7581_o ? 1'b1 : 1'b0; + /* T80_ALU.vhd:299:30 */ + assign n7590_o = ir[2:0]; + /* T80_ALU.vhd:299:43 */ + assign n7592_o = n7590_o == 3'b110; + /* T80_ALU.vhd:299:63 */ + assign n7594_o = xy_state != 2'b00; + /* T80_ALU.vhd:299:51 */ + assign n7595_o = n7592_o | n7594_o; + /* T80_ALU.vhd:300:52 */ + assign n7596_o = wz[11]; + /* T80_ALU.vhd:301:52 */ + assign n7597_o = wz[13]; + /* T80_ALU.vhd:303:54 */ + assign n7598_o = busb[3]; + /* T80_ALU.vhd:304:54 */ + assign n7599_o = busb[5]; + /* T80_ALU.vhd:299:25 */ + assign n7600_o = n7595_o ? n7596_o : n7598_o; + /* T80_ALU.vhd:299:25 */ + assign n7601_o = n7595_o ? n7597_o : n7599_o; + /* T80_ALU.vhd:286:17 */ + assign n7603_o = alu_op == 4'b1001; + /* T80_ALU.vhd:308:49 */ + assign n7604_o = busb | bitmask; + /* T80_ALU.vhd:306:17 */ + assign n7606_o = alu_op == 4'b1010; + /* T80_ALU.vhd:311:53 */ + assign n7607_o = ~bitmask; + /* T80_ALU.vhd:311:49 */ + assign n7608_o = busb & n7607_o; + /* T80_ALU.vhd:309:17 */ + assign n7610_o = alu_op == 4'b1011; + /* T80_ALU.vhd:314:32 */ + assign n7611_o = ir[5:3]; + /* T80_ALU.vhd:316:56 */ + assign n7612_o = busa[6:0]; + /* T80_ALU.vhd:317:47 */ + assign n7613_o = busa[7]; + /* T80_ALU.vhd:318:54 */ + assign n7614_o = busa[7]; + /* T80_ALU.vhd:315:25 */ + assign n7616_o = n7611_o == 3'b000; + /* T80_ALU.vhd:320:56 */ + assign n7617_o = busa[6:0]; + /* T80_ALU.vhd:321:47 */ + assign n7618_o = f_in[0]; + /* T80_ALU.vhd:322:54 */ + assign n7619_o = busa[7]; + /* T80_ALU.vhd:319:25 */ + assign n7621_o = n7611_o == 3'b010; + /* T80_ALU.vhd:324:56 */ + assign n7622_o = busa[7:1]; + /* T80_ALU.vhd:325:47 */ + assign n7623_o = busa[0]; + /* T80_ALU.vhd:326:54 */ + assign n7624_o = busa[0]; + /* T80_ALU.vhd:323:25 */ + assign n7626_o = n7611_o == 3'b001; + /* T80_ALU.vhd:328:56 */ + assign n7627_o = busa[7:1]; + /* T80_ALU.vhd:329:47 */ + assign n7628_o = f_in[0]; + /* T80_ALU.vhd:330:54 */ + assign n7629_o = busa[0]; + /* T80_ALU.vhd:327:25 */ + assign n7631_o = n7611_o == 3'b011; + /* T80_ALU.vhd:332:56 */ + assign n7632_o = busa[6:0]; + /* T80_ALU.vhd:334:54 */ + assign n7634_o = busa[7]; + /* T80_ALU.vhd:331:25 */ + assign n7636_o = n7611_o == 3'b100; + /* T80_ALU.vhd:341:64 */ + assign n7637_o = busa[6:0]; + /* T80_ALU.vhd:343:62 */ + assign n7639_o = busa[7]; + /* T80_ALU.vhd:335:25 */ + assign n7641_o = n7611_o == 3'b110; + /* T80_ALU.vhd:346:56 */ + assign n7642_o = busa[7:1]; + /* T80_ALU.vhd:347:47 */ + assign n7643_o = busa[7]; + /* T80_ALU.vhd:348:54 */ + assign n7644_o = busa[0]; + /* T80_ALU.vhd:345:25 */ + assign n7646_o = n7611_o == 3'b101; + /* T80_ALU.vhd:350:56 */ + assign n7647_o = busa[7:1]; + /* T80_ALU.vhd:352:54 */ + assign n7649_o = busa[0]; + assign n7650_o = {n7646_o, n7641_o, n7636_o, n7631_o, n7626_o, n7621_o, n7616_o}; + /* T80_ALU.vhd:314:25 */ + always @* + case (n7650_o) + 7'b1000000: n7651_o = n7644_o; + 7'b0100000: n7651_o = n7639_o; + 7'b0010000: n7651_o = n7634_o; + 7'b0001000: n7651_o = n7629_o; + 7'b0000100: n7651_o = n7624_o; + 7'b0000010: n7651_o = n7619_o; + 7'b0000001: n7651_o = n7614_o; + default: n7651_o = n7649_o; + endcase + assign n7652_o = n7622_o[0]; + assign n7653_o = n7627_o[0]; + assign n7654_o = n7642_o[0]; + assign n7655_o = n7647_o[0]; + /* T80_ALU.vhd:314:25 */ + always @* + case (n7650_o) + 7'b1000000: n7656_o = n7654_o; + 7'b0100000: n7656_o = 1'b1; + 7'b0010000: n7656_o = 1'b0; + 7'b0001000: n7656_o = n7653_o; + 7'b0000100: n7656_o = n7652_o; + 7'b0000010: n7656_o = n7618_o; + 7'b0000001: n7656_o = n7613_o; + default: n7656_o = n7655_o; + endcase + assign n7657_o = n7612_o[5:0]; + assign n7658_o = n7617_o[5:0]; + assign n7659_o = n7622_o[6:1]; + assign n7660_o = n7627_o[6:1]; + assign n7661_o = n7632_o[5:0]; + assign n7662_o = n7637_o[5:0]; + assign n7663_o = n7642_o[6:1]; + assign n7664_o = n7647_o[6:1]; + /* T80_ALU.vhd:314:25 */ + always @* + case (n7650_o) + 7'b1000000: n7665_o = n7663_o; + 7'b0100000: n7665_o = n7662_o; + 7'b0010000: n7665_o = n7661_o; + 7'b0001000: n7665_o = n7660_o; + 7'b0000100: n7665_o = n7659_o; + 7'b0000010: n7665_o = n7658_o; + 7'b0000001: n7665_o = n7657_o; + default: n7665_o = n7664_o; + endcase + assign n7666_o = n7612_o[6]; + assign n7667_o = n7617_o[6]; + assign n7668_o = n7632_o[6]; + assign n7669_o = n7637_o[6]; + /* T80_ALU.vhd:314:25 */ + always @* + case (n7650_o) + 7'b1000000: n7670_o = n7643_o; + 7'b0100000: n7670_o = n7669_o; + 7'b0010000: n7670_o = n7668_o; + 7'b0001000: n7670_o = n7628_o; + 7'b0000100: n7670_o = n7623_o; + 7'b0000010: n7670_o = n7667_o; + 7'b0000001: n7670_o = n7666_o; + default: n7670_o = 1'b0; + endcase + assign n7673_o = {n7670_o, n7665_o, n7656_o}; + /* T80_ALU.vhd:356:45 */ + assign n7674_o = n7673_o[3]; + assign n7675_o = {n7670_o, n7665_o, n7656_o}; + /* T80_ALU.vhd:357:45 */ + assign n7676_o = n7675_o[5]; + assign n7677_o = {n7670_o, n7665_o, n7656_o}; + /* T80_ALU.vhd:358:45 */ + assign n7678_o = n7677_o[7]; + /* T80_ALU.vhd:359:31 */ + assign n7679_o = {n7670_o, n7665_o, n7656_o}; + /* T80_ALU.vhd:359:44 */ + assign n7681_o = n7679_o == 8'b00000000; + /* T80_ALU.vhd:359:25 */ + assign n7684_o = n7681_o ? 1'b1 : 1'b0; + assign n7685_o = {n7670_o, n7665_o, n7656_o}; + /* T80_ALU.vhd:364:50 */ + assign n7686_o = n7685_o[0]; + assign n7687_o = {n7670_o, n7665_o, n7656_o}; + /* T80_ALU.vhd:364:61 */ + assign n7688_o = n7687_o[1]; + /* T80_ALU.vhd:364:54 */ + assign n7689_o = n7686_o ^ n7688_o; + assign n7690_o = {n7670_o, n7665_o, n7656_o}; + /* T80_ALU.vhd:364:72 */ + assign n7691_o = n7690_o[2]; + /* T80_ALU.vhd:364:65 */ + assign n7692_o = n7689_o ^ n7691_o; + assign n7693_o = {n7670_o, n7665_o, n7656_o}; + /* T80_ALU.vhd:364:83 */ + assign n7694_o = n7693_o[3]; + /* T80_ALU.vhd:364:76 */ + assign n7695_o = n7692_o ^ n7694_o; + assign n7696_o = {n7670_o, n7665_o, n7656_o}; + /* T80_ALU.vhd:365:36 */ + assign n7697_o = n7696_o[4]; + /* T80_ALU.vhd:364:87 */ + assign n7698_o = n7695_o ^ n7697_o; + assign n7699_o = {n7670_o, n7665_o, n7656_o}; + /* T80_ALU.vhd:365:47 */ + assign n7700_o = n7699_o[5]; + /* T80_ALU.vhd:365:40 */ + assign n7701_o = n7698_o ^ n7700_o; + assign n7702_o = {n7670_o, n7665_o, n7656_o}; + /* T80_ALU.vhd:365:58 */ + assign n7703_o = n7702_o[6]; + /* T80_ALU.vhd:365:51 */ + assign n7704_o = n7701_o ^ n7703_o; + assign n7705_o = {n7670_o, n7665_o, n7656_o}; + /* T80_ALU.vhd:365:69 */ + assign n7706_o = n7705_o[7]; + /* T80_ALU.vhd:365:62 */ + assign n7707_o = n7704_o ^ n7706_o; + /* T80_ALU.vhd:364:42 */ + assign n7708_o = ~n7707_o; + /* T80_ALU.vhd:366:33 */ + assign n7710_o = iset == 2'b00; + /* T80_ALU.vhd:367:54 */ + assign n7711_o = f_in[2]; + /* T80_ALU.vhd:368:54 */ + assign n7712_o = f_in[7]; + /* T80_ALU.vhd:369:54 */ + assign n7713_o = f_in[6]; + assign n7714_o = {n7712_o, n7713_o}; + /* T80_ALU.vhd:366:25 */ + assign n7715_o = n7710_o ? n7711_o : n7708_o; + assign n7716_o = {n7678_o, n7684_o}; + /* T80_ALU.vhd:366:25 */ + assign n7717_o = n7710_o ? n7714_o : n7716_o; + /* T80_ALU.vhd:312:17 */ + assign n7719_o = alu_op == 4'b1000; + assign n7720_o = {n7719_o, n7610_o, n7606_o, n7603_o, n7577_o, n7529_o, n7437_o}; + assign n7721_o = f_in[0]; + /* T80_ALU.vhd:168:17 */ + always @* + case (n7720_o) + 7'b1000000: n7722_o = n7651_o; + 7'b0100000: n7722_o = n7721_o; + 7'b0010000: n7722_o = n7721_o; + 7'b0001000: n7722_o = n7721_o; + 7'b0000100: n7722_o = n7721_o; + 7'b0000010: n7722_o = n7503_o; + 7'b0000001: n7722_o = n7353_o; + default: n7722_o = n7721_o; + endcase + assign n7723_o = f_in[1]; + /* T80_ALU.vhd:168:17 */ + always @* + case (n7720_o) + 7'b1000000: n7724_o = 1'b0; + 7'b0100000: n7724_o = n7723_o; + 7'b0010000: n7724_o = n7723_o; + 7'b0001000: n7724_o = 1'b0; + 7'b0000100: n7724_o = 1'b0; + 7'b0000010: n7724_o = n7723_o; + 7'b0000001: n7724_o = n7354_o; + default: n7724_o = n7723_o; + endcase + assign n7725_o = f_in[2]; + /* T80_ALU.vhd:168:17 */ + always @* + case (n7720_o) + 7'b1000000: n7726_o = n7715_o; + 7'b0100000: n7726_o = n7725_o; + 7'b0010000: n7726_o = n7725_o; + 7'b0001000: n7726_o = n7586_o; + 7'b0000100: n7726_o = n7572_o; + 7'b0000010: n7726_o = n7527_o; + 7'b0000001: n7726_o = n7412_o; + default: n7726_o = n7725_o; + endcase + assign n7727_o = f_in[3]; + /* T80_ALU.vhd:168:17 */ + always @* + case (n7720_o) + 7'b1000000: n7728_o = n7674_o; + 7'b0100000: n7728_o = n7727_o; + 7'b0010000: n7728_o = n7727_o; + 7'b0001000: n7728_o = n7600_o; + 7'b0000100: n7728_o = n7538_o; + 7'b0000010: n7728_o = n7499_o; + 7'b0000001: n7728_o = n7366_o; + default: n7728_o = n7727_o; + endcase + assign n7729_o = f_in[4]; + /* T80_ALU.vhd:168:17 */ + always @* + case (n7720_o) + 7'b1000000: n7730_o = 1'b0; + 7'b0100000: n7730_o = n7729_o; + 7'b0010000: n7730_o = n7729_o; + 7'b0001000: n7730_o = 1'b1; + 7'b0000100: n7730_o = 1'b0; + 7'b0000010: n7730_o = n7497_o; + 7'b0000001: n7730_o = n7357_o; + default: n7730_o = n7729_o; + endcase + assign n7731_o = f_in[5]; + /* T80_ALU.vhd:168:17 */ + always @* + case (n7720_o) + 7'b1000000: n7732_o = n7676_o; + 7'b0100000: n7732_o = n7731_o; + 7'b0010000: n7732_o = n7731_o; + 7'b0001000: n7732_o = n7601_o; + 7'b0000100: n7732_o = n7540_o; + 7'b0000010: n7732_o = n7500_o; + 7'b0000001: n7732_o = n7367_o; + default: n7732_o = n7731_o; + endcase + assign n7733_o = n7414_o[0]; + assign n7734_o = n7717_o[0]; + assign n7735_o = f_in[6]; + /* T80_ALU.vhd:168:17 */ + always @* + case (n7720_o) + 7'b1000000: n7736_o = n7734_o; + 7'b0100000: n7736_o = n7735_o; + 7'b0010000: n7736_o = n7735_o; + 7'b0001000: n7736_o = n7587_o; + 7'b0000100: n7736_o = n7546_o; + 7'b0000010: n7736_o = n7510_o; + 7'b0000001: n7736_o = n7733_o; + default: n7736_o = n7735_o; + endcase + assign n7737_o = n7414_o[1]; + assign n7738_o = n7717_o[1]; + assign n7739_o = f_in[7]; + /* T80_ALU.vhd:168:17 */ + always @* + case (n7720_o) + 7'b1000000: n7740_o = n7738_o; + 7'b0100000: n7740_o = n7739_o; + 7'b0010000: n7740_o = n7739_o; + 7'b0001000: n7740_o = n7579_o; + 7'b0000100: n7740_o = n7548_o; + 7'b0000010: n7740_o = n7511_o; + 7'b0000001: n7740_o = n7737_o; + default: n7740_o = n7739_o; + endcase + assign n7748_o = n7358_o[0]; + assign n7749_o = n7504_o[0]; + assign n7750_o = n7534_o[0]; + assign n7751_o = n7578_o[0]; + assign n7752_o = n7604_o[0]; + assign n7753_o = n7608_o[0]; + /* T80_ALU.vhd:168:17 */ + always @* + case (n7720_o) + 7'b1000000: n7755_o = n7656_o; + 7'b0100000: n7755_o = n7753_o; + 7'b0010000: n7755_o = n7752_o; + 7'b0001000: n7755_o = n7751_o; + 7'b0000100: n7755_o = n7750_o; + 7'b0000010: n7755_o = n7749_o; + 7'b0000001: n7755_o = n7748_o; + default: n7755_o = 1'bX; + endcase + assign n7756_o = n7358_o[3:1]; + assign n7757_o = n7504_o[3:1]; + assign n7758_o = n7534_o[3:1]; + assign n7759_o = n7578_o[3:1]; + assign n7760_o = n7604_o[3:1]; + assign n7761_o = n7608_o[3:1]; + assign n7762_o = n7665_o[2:0]; + /* T80_ALU.vhd:168:17 */ + always @* + case (n7720_o) + 7'b1000000: n7764_o = n7762_o; + 7'b0100000: n7764_o = n7761_o; + 7'b0010000: n7764_o = n7760_o; + 7'b0001000: n7764_o = n7759_o; + 7'b0000100: n7764_o = n7758_o; + 7'b0000010: n7764_o = n7757_o; + 7'b0000001: n7764_o = n7756_o; + default: n7764_o = 3'bX; + endcase + assign n7765_o = n7358_o[6:4]; + assign n7766_o = n7504_o[6:4]; + assign n7767_o = n7530_o[2:0]; + assign n7768_o = n7578_o[6:4]; + assign n7769_o = n7604_o[6:4]; + assign n7770_o = n7608_o[6:4]; + assign n7771_o = n7665_o[5:3]; + /* T80_ALU.vhd:168:17 */ + always @* + case (n7720_o) + 7'b1000000: n7773_o = n7771_o; + 7'b0100000: n7773_o = n7770_o; + 7'b0010000: n7773_o = n7769_o; + 7'b0001000: n7773_o = n7768_o; + 7'b0000100: n7773_o = n7767_o; + 7'b0000010: n7773_o = n7766_o; + 7'b0000001: n7773_o = n7765_o; + default: n7773_o = 3'bX; + endcase + assign n7774_o = n7358_o[7]; + assign n7775_o = n7504_o[7]; + assign n7776_o = n7530_o[3]; + assign n7777_o = n7578_o[7]; + assign n7778_o = n7604_o[7]; + assign n7779_o = n7608_o[7]; + /* T80_ALU.vhd:168:17 */ + always @* + case (n7720_o) + 7'b1000000: n7781_o = n7670_o; + 7'b0100000: n7781_o = n7779_o; + 7'b0010000: n7781_o = n7778_o; + 7'b0001000: n7781_o = n7777_o; + 7'b0000100: n7781_o = n7776_o; + 7'b0000010: n7781_o = n7775_o; + 7'b0000001: n7781_o = n7774_o; + default: n7781_o = 1'bX; + endcase + assign n7789_o = {n7781_o, n7773_o, n7764_o, n7755_o}; + assign n7792_o = {n7314_o, n7292_o, n7270_o}; + assign n7793_o = {n7740_o, n7736_o, n7732_o, n7730_o, n7728_o, n7726_o, n7724_o, n7722_o}; +endmodule + +module t80_mcode_0_0_1_2_3_4_5_6_7 + (input [7:0] ir, + input [1:0] iset, + input [2:0] mcycle, + input [7:0] f, + input nmicycle, + input intcycle, + input [1:0] xy_state, + output [2:0] mcycles, + output [2:0] tstates, + output [1:0] prefix, + output inc_pc, + output inc_wz, + output [3:0] incdec_16, + output read_to_reg, + output read_to_acc, + output [3:0] set_busa_to, + output [3:0] set_busb_to, + output [3:0] alu_op, + output save_alu, + output preservec, + output arith16, + output [2:0] set_addr_to, + output iorq, + output jump, + output jumpe, + output jumpxy, + output call, + output rstp, + output ldz, + output ldw, + output ldsphl, + output [2:0] special_ld, + output exchangedh, + output exchangerp, + output exchangeaf, + output exchangers, + output i_djnz, + output i_cpl, + output i_ccf, + output i_scf, + output i_retn, + output i_bt, + output i_bc, + output i_btr, + output i_rld, + output i_rrd, + output i_inrc, + output [1:0] setwz, + output setdi, + output setei, + output [1:0] imode, + output halt, + output noread, + output write, + output xybit_undoc); + wire [2:0] n2193_o; + wire [2:0] n2194_o; + wire [1:0] n2195_o; + wire n2197_o; + wire [2:0] n2200_o; + wire [2:0] n2201_o; + wire [3:0] n2203_o; + wire n2205_o; + wire n2207_o; + wire n2208_o; + wire n2210_o; + wire n2211_o; + wire n2213_o; + wire n2214_o; + wire n2216_o; + wire n2217_o; + wire n2219_o; + wire n2220_o; + wire n2222_o; + wire n2223_o; + wire n2225_o; + wire n2226_o; + wire n2228_o; + wire n2229_o; + wire n2231_o; + wire n2232_o; + wire n2234_o; + wire n2235_o; + wire n2237_o; + wire n2238_o; + wire n2240_o; + wire n2241_o; + wire n2243_o; + wire n2244_o; + wire n2246_o; + wire n2247_o; + wire n2249_o; + wire n2250_o; + wire n2252_o; + wire n2253_o; + wire n2255_o; + wire n2256_o; + wire n2258_o; + wire n2259_o; + wire n2261_o; + wire n2262_o; + wire n2264_o; + wire n2265_o; + wire n2267_o; + wire n2268_o; + wire n2270_o; + wire n2271_o; + wire n2273_o; + wire n2274_o; + wire n2276_o; + wire n2277_o; + wire n2279_o; + wire n2280_o; + wire n2282_o; + wire n2283_o; + wire n2285_o; + wire n2286_o; + wire n2288_o; + wire n2289_o; + wire n2291_o; + wire n2292_o; + wire n2294_o; + wire n2295_o; + wire n2297_o; + wire n2298_o; + wire n2300_o; + wire n2301_o; + wire n2303_o; + wire n2304_o; + wire n2306_o; + wire n2307_o; + wire n2309_o; + wire n2310_o; + wire n2312_o; + wire n2313_o; + wire n2315_o; + wire n2316_o; + wire n2318_o; + wire n2319_o; + wire n2321_o; + wire n2322_o; + wire n2324_o; + wire n2325_o; + wire n2327_o; + wire n2328_o; + wire n2330_o; + wire n2331_o; + wire n2333_o; + wire n2334_o; + wire n2336_o; + wire n2337_o; + wire n2339_o; + wire n2340_o; + wire n2342_o; + wire n2343_o; + wire n2345_o; + wire n2346_o; + wire n2348_o; + wire n2349_o; + wire [30:0] n2350_o; + wire n2352_o; + reg n2355_o; + reg n2358_o; + reg [2:0] n2360_o; + wire n2362_o; + wire n2364_o; + wire n2365_o; + wire n2367_o; + wire n2368_o; + wire n2370_o; + wire n2371_o; + wire n2373_o; + wire n2374_o; + wire n2376_o; + wire n2377_o; + wire n2379_o; + wire n2380_o; + wire [30:0] n2381_o; + wire n2383_o; + wire n2385_o; + wire [1:0] n2386_o; + reg n2389_o; + reg [2:0] n2391_o; + reg [2:0] n2394_o; + wire n2396_o; + wire n2398_o; + wire n2399_o; + wire n2401_o; + wire n2402_o; + wire n2404_o; + wire n2405_o; + wire n2407_o; + wire n2408_o; + wire n2410_o; + wire n2411_o; + wire n2413_o; + wire n2414_o; + wire [30:0] n2415_o; + wire n2418_o; + wire n2420_o; + wire [1:0] n2421_o; + reg [2:0] n2423_o; + reg n2425_o; + reg [2:0] n2428_o; + reg n2431_o; + wire n2433_o; + wire n2435_o; + wire n2436_o; + wire n2438_o; + wire n2439_o; + wire n2441_o; + wire n2442_o; + wire n2444_o; + wire n2445_o; + wire n2447_o; + wire n2448_o; + wire n2450_o; + wire n2451_o; + wire [30:0] n2452_o; + wire n2455_o; + wire n2457_o; + wire [1:0] n2458_o; + reg n2461_o; + reg [2:0] n2463_o; + reg n2465_o; + reg [2:0] n2468_o; + reg n2471_o; + wire n2473_o; + wire [30:0] n2474_o; + wire n2476_o; + wire n2478_o; + wire [1:0] n2479_o; + reg n2482_o; + reg [2:0] n2485_o; + wire n2487_o; + wire [30:0] n2488_o; + wire n2490_o; + wire n2492_o; + wire [1:0] n2493_o; + reg n2496_o; + reg [2:0] n2499_o; + wire n2501_o; + wire [30:0] n2502_o; + wire n2504_o; + wire n2506_o; + wire n2508_o; + wire [2:0] n2509_o; + reg n2513_o; + reg n2516_o; + reg [2:0] n2519_o; + reg n2522_o; + wire n2524_o; + wire [30:0] n2525_o; + wire n2527_o; + wire n2529_o; + wire [1:0] n2530_o; + reg [3:0] n2533_o; + reg [2:0] n2536_o; + reg [1:0] n2539_o; + reg n2542_o; + wire n2544_o; + wire [30:0] n2545_o; + wire n2547_o; + wire n2549_o; + wire [1:0] n2550_o; + reg [3:0] n2553_o; + reg [2:0] n2556_o; + reg [1:0] n2559_o; + reg n2562_o; + wire n2564_o; + wire [30:0] n2565_o; + wire n2567_o; + wire n2569_o; + wire n2571_o; + wire [2:0] n2572_o; + reg n2576_o; + reg [3:0] n2579_o; + reg [2:0] n2582_o; + reg n2585_o; + reg [1:0] n2588_o; + reg n2591_o; + wire n2593_o; + wire [30:0] n2594_o; + wire n2596_o; + wire [2:0] n2598_o; + wire [2:0] n2600_o; + wire n2603_o; + wire n2605_o; + wire n2607_o; + wire [2:0] n2609_o; + wire [2:0] n2611_o; + wire n2614_o; + wire n2616_o; + wire [1:0] n2617_o; + reg n2621_o; + reg n2625_o; + reg [2:0] n2627_o; + reg n2629_o; + wire n2631_o; + wire n2633_o; + wire n2634_o; + wire n2636_o; + wire n2637_o; + wire n2639_o; + wire n2640_o; + wire [30:0] n2641_o; + wire n2643_o; + wire n2645_o; + wire n2648_o; + wire n2651_o; + wire [3:0] n2652_o; + reg n2656_o; + reg n2659_o; + reg n2663_o; + reg [2:0] n2665_o; + reg [2:0] n2669_o; + reg n2672_o; + reg n2675_o; + wire n2677_o; + wire [30:0] n2678_o; + wire n2680_o; + wire n2682_o; + wire n2684_o; + wire n2686_o; + wire [3:0] n2687_o; + reg n2691_o; + reg n2694_o; + reg [3:0] n2698_o; + reg [2:0] n2702_o; + reg n2705_o; + reg n2708_o; + reg n2712_o; + wire n2714_o; + wire n2716_o; + wire [30:0] n2717_o; + wire n2719_o; + wire [3:0] n2722_o; + wire [3:0] n2724_o; + wire n2726_o; + wire n2728_o; + wire [3:0] n2731_o; + wire [3:0] n2733_o; + wire n2735_o; + wire n2737_o; + wire [2:0] n2738_o; + reg [2:0] n2740_o; + reg [3:0] n2744_o; + reg [3:0] n2746_o; + reg [2:0] n2750_o; + reg n2754_o; + wire n2756_o; + wire n2758_o; + wire n2759_o; + wire n2761_o; + wire n2762_o; + wire n2764_o; + wire n2765_o; + wire [30:0] n2766_o; + wire n2768_o; + wire n2770_o; + wire [2:0] n2772_o; + wire [2:0] n2774_o; + wire n2777_o; + wire n2779_o; + wire n2781_o; + wire [2:0] n2783_o; + wire [2:0] n2785_o; + wire n2788_o; + wire n2790_o; + wire [2:0] n2791_o; + reg [3:0] n2795_o; + reg n2799_o; + reg [2:0] n2801_o; + reg n2803_o; + reg [2:0] n2807_o; + wire n2809_o; + wire n2811_o; + wire n2812_o; + wire n2814_o; + wire n2815_o; + wire n2817_o; + wire n2818_o; + wire n2820_o; + wire n2822_o; + wire n2824_o; + wire [30:0] n2825_o; + wire n2827_o; + wire n2829_o; + wire n2831_o; + wire n2833_o; + wire n2835_o; + wire [4:0] n2836_o; + reg [2:0] n2839_o; + reg [3:0] n2843_o; + reg n2847_o; + reg [3:0] n2851_o; + reg [3:0] n2855_o; + reg [2:0] n2861_o; + reg n2864_o; + reg n2867_o; + reg n2871_o; + wire n2873_o; + wire n2876_o; + wire n2878_o; + wire n2879_o; + wire n2881_o; + wire n2882_o; + wire n2884_o; + wire n2885_o; + wire n2887_o; + wire n2888_o; + wire n2890_o; + wire n2891_o; + wire n2893_o; + wire n2894_o; + wire n2896_o; + wire n2897_o; + wire n2899_o; + wire n2900_o; + wire n2902_o; + wire n2903_o; + wire n2905_o; + wire n2906_o; + wire n2908_o; + wire n2909_o; + wire n2911_o; + wire n2912_o; + wire n2914_o; + wire n2915_o; + wire n2917_o; + wire n2918_o; + wire n2920_o; + wire n2921_o; + wire n2923_o; + wire n2924_o; + wire n2926_o; + wire n2927_o; + wire n2929_o; + wire n2930_o; + wire n2932_o; + wire n2933_o; + wire n2935_o; + wire n2936_o; + wire n2938_o; + wire n2939_o; + wire n2941_o; + wire n2942_o; + wire n2944_o; + wire n2945_o; + wire n2947_o; + wire n2948_o; + wire n2950_o; + wire n2951_o; + wire n2953_o; + wire n2954_o; + wire n2956_o; + wire n2957_o; + wire n2959_o; + wire n2960_o; + wire n2962_o; + wire n2963_o; + wire n2965_o; + wire n2966_o; + wire n2968_o; + wire n2969_o; + wire n2971_o; + wire n2972_o; + wire n2974_o; + wire n2975_o; + wire n2977_o; + wire n2978_o; + wire n2980_o; + wire n2981_o; + wire n2983_o; + wire n2984_o; + wire n2986_o; + wire n2987_o; + wire n2989_o; + wire n2990_o; + wire n2992_o; + wire n2993_o; + wire n2995_o; + wire n2996_o; + wire n2998_o; + wire n2999_o; + wire n3001_o; + wire n3002_o; + wire n3004_o; + wire n3005_o; + wire n3007_o; + wire n3008_o; + wire n3010_o; + wire n3011_o; + wire n3013_o; + wire n3014_o; + wire n3016_o; + wire n3017_o; + wire n3019_o; + wire n3020_o; + wire n3022_o; + wire n3023_o; + wire n3025_o; + wire n3026_o; + wire n3028_o; + wire n3029_o; + wire n3031_o; + wire n3032_o; + wire n3034_o; + wire n3035_o; + wire n3037_o; + wire n3038_o; + wire n3040_o; + wire n3041_o; + wire [30:0] n3042_o; + wire n3044_o; + wire n3047_o; + wire [1:0] n3048_o; + reg n3051_o; + reg [2:0] n3053_o; + reg [2:0] n3055_o; + reg n3058_o; + reg [2:0] n3061_o; + wire n3063_o; + wire n3065_o; + wire n3066_o; + wire n3068_o; + wire n3069_o; + wire n3071_o; + wire n3072_o; + wire n3074_o; + wire n3075_o; + wire n3077_o; + wire n3078_o; + wire n3080_o; + wire n3081_o; + wire n3083_o; + wire n3084_o; + wire n3086_o; + wire n3090_o; + wire n3093_o; + wire [2:0] n3095_o; + wire [2:0] n3097_o; + wire n3100_o; + wire n3102_o; + wire n3104_o; + wire n3105_o; + wire n3107_o; + wire n3108_o; + wire n3110_o; + wire n3111_o; + wire n3113_o; + wire n3114_o; + wire n3116_o; + wire n3117_o; + wire n3119_o; + wire n3120_o; + wire n3122_o; + wire n3123_o; + wire n3125_o; + wire n3127_o; + wire n3128_o; + wire n3130_o; + wire n3131_o; + wire n3133_o; + wire n3134_o; + wire n3136_o; + wire n3137_o; + wire n3139_o; + wire n3140_o; + wire n3142_o; + wire n3143_o; + wire [30:0] n3144_o; + wire n3146_o; + wire n3148_o; + wire n3150_o; + wire [2:0] n3151_o; + reg [2:0] n3153_o; + reg n3156_o; + reg [2:0] n3158_o; + reg [3:0] n3161_o; + reg [3:0] n3163_o; + reg n3166_o; + reg n3169_o; + reg [2:0] n3173_o; + reg n3176_o; + wire n3178_o; + wire n3180_o; + wire n3182_o; + wire n3183_o; + wire n3185_o; + wire n3186_o; + wire n3188_o; + wire n3189_o; + wire n3191_o; + wire n3192_o; + wire n3194_o; + wire n3195_o; + wire n3197_o; + wire n3198_o; + wire [30:0] n3199_o; + wire n3201_o; + wire n3203_o; + wire n3205_o; + wire [2:0] n3206_o; + reg [2:0] n3208_o; + reg n3211_o; + reg [2:0] n3213_o; + reg [3:0] n3216_o; + reg [3:0] n3218_o; + reg n3221_o; + reg n3224_o; + reg [2:0] n3228_o; + reg n3231_o; + wire n3233_o; + wire n3236_o; + wire n3238_o; + wire n3240_o; + wire n3242_o; + wire [30:0] n3243_o; + wire n3245_o; + wire n3247_o; + wire n3249_o; + wire [2:0] n3250_o; + reg [2:0] n3252_o; + reg [3:0] n3256_o; + reg [3:0] n3260_o; + reg [2:0] n3264_o; + reg n3268_o; + wire [30:0] n3269_o; + wire n3271_o; + wire n3273_o; + wire n3275_o; + wire n3277_o; + wire n3279_o; + wire [4:0] n3280_o; + reg [2:0] n3282_o; + reg n3285_o; + reg [3:0] n3289_o; + reg [3:0] n3293_o; + reg [2:0] n3297_o; + reg n3300_o; + reg n3304_o; + reg n3308_o; + wire [2:0] n3311_o; + wire [2:0] n3312_o; + wire n3314_o; + wire [3:0] n3316_o; + wire [3:0] n3318_o; + wire [2:0] n3320_o; + wire n3322_o; + wire n3324_o; + wire n3326_o; + wire [2:0] n3328_o; + wire [2:0] n3329_o; + wire n3331_o; + wire [3:0] n3332_o; + wire [3:0] n3333_o; + wire [2:0] n3334_o; + wire n3336_o; + wire n3338_o; + wire n3339_o; + wire n3341_o; + wire n3343_o; + wire n3345_o; + wire n3347_o; + wire [30:0] n3348_o; + wire [1:0] n3350_o; + wire [30:0] n3351_o; + wire [1:0] n3352_o; + wire n3355_o; + wire n3357_o; + wire n3358_o; + wire n3360_o; + wire n3361_o; + reg n3363_o; + reg [1:0] n3365_o; + reg n3368_o; + wire n3370_o; + wire [1:0] n3372_o; + wire [30:0] n3373_o; + wire [1:0] n3374_o; + wire n3376_o; + wire n3378_o; + wire n3379_o; + wire n3381_o; + wire n3382_o; + reg n3385_o; + reg [1:0] n3387_o; + reg n3390_o; + wire n3392_o; + wire [1:0] n3393_o; + reg [2:0] n3395_o; + reg n3399_o; + reg [2:0] n3401_o; + reg n3403_o; + reg [1:0] n3405_o; + reg n3407_o; + reg [3:0] n3410_o; + reg n3414_o; + reg n3418_o; + reg [1:0] n3421_o; + reg n3425_o; + wire n3427_o; + wire n3429_o; + wire n3430_o; + wire n3432_o; + wire n3433_o; + wire n3435_o; + wire n3436_o; + wire n3439_o; + wire n3441_o; + wire n3442_o; + wire n3444_o; + wire n3445_o; + wire n3447_o; + wire n3448_o; + wire n3451_o; + wire n3453_o; + wire n3454_o; + wire n3456_o; + wire n3457_o; + wire n3459_o; + wire n3460_o; + wire n3463_o; + wire n3465_o; + wire n3466_o; + wire n3468_o; + wire n3469_o; + wire n3471_o; + wire n3472_o; + wire [30:0] n3473_o; + wire n3475_o; + wire n3477_o; + wire [1:0] n3478_o; + reg n3482_o; + reg n3485_o; + reg n3488_o; + reg n3491_o; + wire n3493_o; + wire [30:0] n3495_o; + wire n3497_o; + wire [2:0] n3499_o; + wire n3504_o; + wire n3505_o; + wire n3507_o; + wire n3508_o; + wire n3510_o; + wire n3511_o; + wire n3512_o; + wire n3514_o; + wire n3515_o; + wire n3517_o; + wire n3518_o; + wire n3519_o; + wire n3521_o; + wire n3522_o; + wire n3524_o; + wire n3525_o; + wire n3526_o; + wire n3528_o; + wire n3529_o; + wire n3531_o; + wire [7:0] n3532_o; + reg n3534_o; + wire n3537_o; + wire n3539_o; + wire [1:0] n3540_o; + reg n3544_o; + reg n3546_o; + reg n3549_o; + reg n3552_o; + wire n3554_o; + wire n3556_o; + wire n3557_o; + wire n3559_o; + wire n3560_o; + wire n3562_o; + wire n3563_o; + wire n3565_o; + wire n3566_o; + wire n3568_o; + wire n3569_o; + wire n3571_o; + wire n3572_o; + wire n3574_o; + wire n3575_o; + wire [30:0] n3576_o; + wire n3578_o; + wire n3580_o; + wire [1:0] n3581_o; + reg [2:0] n3583_o; + reg n3586_o; + reg n3589_o; + reg n3592_o; + wire n3594_o; + wire [30:0] n3595_o; + wire n3596_o; + wire n3597_o; + wire [2:0] n3600_o; + wire n3602_o; + wire n3604_o; + wire [1:0] n3605_o; + reg [2:0] n3607_o; + reg [2:0] n3610_o; + reg n3613_o; + reg n3616_o; + reg n3619_o; + wire n3621_o; + wire [30:0] n3622_o; + wire n3623_o; + wire [2:0] n3626_o; + wire n3628_o; + wire n3630_o; + wire [1:0] n3631_o; + reg [2:0] n3633_o; + reg [2:0] n3636_o; + reg n3639_o; + reg n3642_o; + reg n3645_o; + wire n3647_o; + wire [30:0] n3648_o; + wire n3649_o; + wire n3650_o; + wire [2:0] n3653_o; + wire n3655_o; + wire n3657_o; + wire [1:0] n3658_o; + reg [2:0] n3660_o; + reg [2:0] n3663_o; + reg n3666_o; + reg n3669_o; + reg n3672_o; + wire n3674_o; + wire [30:0] n3675_o; + wire n3676_o; + wire [2:0] n3679_o; + wire n3681_o; + wire n3683_o; + wire [1:0] n3684_o; + reg [2:0] n3686_o; + reg [2:0] n3689_o; + reg n3692_o; + reg n3695_o; + reg n3698_o; + wire n3700_o; + wire n3702_o; + wire [30:0] n3703_o; + wire n3706_o; + wire n3708_o; + wire n3710_o; + wire [2:0] n3711_o; + reg [2:0] n3714_o; + reg n3717_o; + reg n3720_o; + reg [2:0] n3722_o; + reg [3:0] n3725_o; + reg [3:0] n3727_o; + reg n3730_o; + reg n3733_o; + reg n3737_o; + reg n3740_o; + wire n3742_o; + wire [30:0] n3743_o; + wire n3745_o; + wire n3747_o; + wire n3749_o; + wire n3751_o; + wire [3:0] n3752_o; + reg [2:0] n3754_o; + reg n3758_o; + reg [3:0] n3762_o; + reg [3:0] n3766_o; + reg [2:0] n3770_o; + reg n3773_o; + reg n3776_o; + reg n3779_o; + reg n3783_o; + wire n3785_o, stack_busy; // imperfect busy signal, but it catches some instances + assign stack_busy=n3785_o; + wire [30:0] n3788_o; + wire n3790_o; + wire [2:0] n3792_o; + wire n3797_o; + wire n3798_o; + wire n3800_o; + wire n3801_o; + wire n3803_o; + wire n3804_o; + wire n3805_o; + wire n3807_o; + wire n3808_o; + wire n3810_o; + wire n3811_o; + wire n3812_o; + wire n3814_o; + wire n3815_o; + wire n3817_o; + wire n3818_o; + wire n3819_o; + wire n3821_o; + wire n3822_o; + wire n3824_o; + wire [7:0] n3825_o; + reg n3827_o; + wire [2:0] n3830_o; + wire [2:0] n3832_o; + wire [3:0] n3835_o; + wire [3:0] n3838_o; + wire [2:0] n3841_o; + wire n3843_o; + wire n3845_o; + wire n3847_o; + wire [3:0] n3848_o; + reg [2:0] n3850_o; + reg [2:0] n3852_o; + reg n3856_o; + reg [3:0] n3859_o; + reg [3:0] n3862_o; + reg [2:0] n3865_o; + reg n3868_o; + reg n3871_o; + reg n3874_o; + reg n3878_o; + wire n3880_o; + wire n3882_o; + wire n3883_o; + wire n3885_o; + wire n3886_o; + wire n3888_o; + wire n3889_o; + wire n3891_o; + wire n3892_o; + wire n3894_o; + wire n3895_o; + wire n3897_o; + wire n3898_o; + wire n3900_o; + wire n3901_o; + wire [30:0] n3902_o; + wire n3904_o; + wire n3906_o; + wire n3908_o; + wire [2:0] n3909_o; + reg [3:0] n3913_o; + reg [2:0] n3917_o; + reg n3920_o; + reg n3923_o; + wire n3925_o; + wire [30:0] n3927_o; + wire [2:0] n3929_o; + wire n3934_o; + wire n3935_o; + wire n3937_o; + wire n3938_o; + wire n3940_o; + wire n3941_o; + wire n3942_o; + wire n3944_o; + wire n3945_o; + wire n3947_o; + wire n3948_o; + wire n3949_o; + wire n3951_o; + wire n3952_o; + wire n3954_o; + wire n3955_o; + wire n3956_o; + wire n3958_o; + wire n3959_o; + wire n3961_o; + wire [7:0] n3962_o; + reg n3964_o; + wire [2:0] n3967_o; + wire [2:0] n3970_o; + wire n3972_o; + wire n3974_o; + wire n3976_o; + wire [2:0] n3977_o; + reg [2:0] n3979_o; + reg [2:0] n3982_o; + reg [3:0] n3986_o; + reg [2:0] n3989_o; + reg n3992_o; + reg n3995_o; + wire n3997_o; + wire n3999_o; + wire n4000_o; + wire n4002_o; + wire n4003_o; + wire n4005_o; + wire n4006_o; + wire n4008_o; + wire n4009_o; + wire n4011_o; + wire n4012_o; + wire n4014_o; + wire n4015_o; + wire n4017_o; + wire n4018_o; + wire [30:0] n4019_o; + wire n4021_o; + wire n4023_o; + wire n4025_o; + wire [2:0] n4026_o; + reg [2:0] n4028_o; + reg [3:0] n4032_o; + reg [3:0] n4036_o; + reg [2:0] n4040_o; + reg n4043_o; + reg n4047_o; + wire n4049_o; + wire n4051_o; + wire n4052_o; + wire n4054_o; + wire n4055_o; + wire n4057_o; + wire n4058_o; + wire n4060_o; + wire n4061_o; + wire n4063_o; + wire n4064_o; + wire n4066_o; + wire n4067_o; + wire n4069_o; + wire n4070_o; + wire [30:0] n4071_o; + wire n4073_o; + wire n4075_o; + wire [1:0] n4076_o; + reg n4079_o; + reg n4082_o; + reg [2:0] n4085_o; + reg n4088_o; + wire n4090_o; + wire [30:0] n4091_o; + wire n4093_o; + wire n4095_o; + wire [1:0] n4096_o; + reg n4099_o; + reg [3:0] n4102_o; + reg [2:0] n4105_o; + reg n4108_o; + reg n4111_o; + wire n4113_o; + wire n4115_o; + wire n4117_o; + wire n4119_o; + wire n4121_o; + wire n4122_o; + wire [58:0] n4123_o; + reg [2:0] n4156_o; + reg [2:0] n4161_o; + reg [1:0] n4167_o; + reg n4170_o; + reg n4173_o; + wire [1:0] n4174_o; + wire [1:0] n4175_o; + wire [1:0] n4176_o; + wire [1:0] n4177_o; + wire [1:0] n4178_o; + wire [1:0] n4179_o; + wire [1:0] n4180_o; + wire [1:0] n4181_o; + wire [1:0] n4182_o; + reg [1:0] n4185_o; + wire [1:0] n4186_o; + wire [1:0] n4187_o; + wire [1:0] n4188_o; + wire [1:0] n4189_o; + wire [1:0] n4190_o; + wire [1:0] n4191_o; + wire [1:0] n4192_o; + wire [1:0] n4193_o; + wire [1:0] n4194_o; + reg [1:0] n4197_o; + reg n4206_o; + reg n4209_o; + wire [2:0] n4210_o; + reg [2:0] n4213_o; + wire n4214_o; + reg n4217_o; + wire n4218_o; + wire n4219_o; + wire n4220_o; + wire n4221_o; + wire n4222_o; + wire n4223_o; + wire n4224_o; + wire n4225_o; + wire n4226_o; + wire n4227_o; + wire n4228_o; + wire n4229_o; + wire n4231_o; + wire n4233_o; + wire n4234_o; + wire n4235_o; + wire n4236_o; + wire n4237_o; + wire n4238_o; + wire n4239_o; + reg n4242_o; + wire [1:0] n4243_o; + wire [1:0] n4244_o; + wire [1:0] n4245_o; + wire [1:0] n4246_o; + wire [1:0] n4247_o; + wire [1:0] n4248_o; + wire [1:0] n4249_o; + wire [1:0] n4250_o; + wire [1:0] n4251_o; + wire [1:0] n4252_o; + wire [1:0] n4253_o; + wire [1:0] n4254_o; + wire [1:0] n4256_o; + wire [1:0] n4258_o; + wire [1:0] n4259_o; + wire [1:0] n4260_o; + wire [1:0] n4261_o; + wire [1:0] n4262_o; + wire [1:0] n4263_o; + wire [1:0] n4264_o; + reg [1:0] n4267_o; + wire n4268_o; + wire n4269_o; + wire n4270_o; + wire n4271_o; + wire n4272_o; + wire n4273_o; + wire n4275_o; + wire n4277_o; + wire n4278_o; + wire n4279_o; + wire n4280_o; + wire n4281_o; + wire n4282_o; + wire n4283_o; + reg n4286_o; + reg [3:0] n4292_o; + reg n4300_o; + reg n4305_o; + reg n4308_o; + reg [2:0] n4311_o; + reg n4314_o; + reg n4317_o; + reg n4320_o; + reg n4324_o; + reg n4327_o; + reg n4330_o; + reg n4333_o; + reg n4336_o; + reg n4340_o; + reg n4344_o; + reg n4348_o; + reg n4352_o; + reg n4356_o; + reg n4359_o; + reg n4363_o; + reg n4367_o; + reg n4371_o; + reg [1:0] n4374_o; + reg n4378_o; + reg n4382_o; + reg n4386_o; + reg n4389_o; + reg n4392_o; + wire n4394_o; + wire [2:0] n4395_o; + wire [2:0] n4396_o; + wire n4398_o; + wire n4400_o; + wire n4403_o; + wire [3:0] n4405_o; + wire n4408_o; + wire [30:0] n4409_o; + wire n4411_o; + wire n4413_o; + wire n4414_o; + wire n4416_o; + wire n4418_o; + wire [2:0] n4419_o; + reg [2:0] n4421_o; + reg n4424_o; + reg [3:0] n4426_o; + reg n4429_o; + reg [2:0] n4433_o; + reg n4436_o; + wire [2:0] n4439_o; + wire [2:0] n4440_o; + wire n4441_o; + wire [3:0] n4442_o; + wire n4443_o; + wire [2:0] n4445_o; + wire n4447_o; + wire n4450_o; + wire n4452_o; + wire n4454_o; + wire n4455_o; + wire n4457_o; + wire n4458_o; + wire n4460_o; + wire n4461_o; + wire n4463_o; + wire n4464_o; + wire n4466_o; + wire n4467_o; + wire n4469_o; + wire n4470_o; + wire n4472_o; + wire n4473_o; + wire n4475_o; + wire n4476_o; + wire n4478_o; + wire n4479_o; + wire n4481_o; + wire n4482_o; + wire n4484_o; + wire n4485_o; + wire n4487_o; + wire n4488_o; + wire n4490_o; + wire n4491_o; + wire n4493_o; + wire n4494_o; + wire n4496_o; + wire n4497_o; + wire n4499_o; + wire n4500_o; + wire n4502_o; + wire n4503_o; + wire n4505_o; + wire n4506_o; + wire n4508_o; + wire n4509_o; + wire n4511_o; + wire n4512_o; + wire n4514_o; + wire n4515_o; + wire n4517_o; + wire n4518_o; + wire n4520_o; + wire n4521_o; + wire n4523_o; + wire n4524_o; + wire n4526_o; + wire n4527_o; + wire n4529_o; + wire n4530_o; + wire n4532_o; + wire n4533_o; + wire n4535_o; + wire n4536_o; + wire n4538_o; + wire n4539_o; + wire n4541_o; + wire n4542_o; + wire n4544_o; + wire n4545_o; + wire n4547_o; + wire n4548_o; + wire n4550_o; + wire n4551_o; + wire n4553_o; + wire n4554_o; + wire n4556_o; + wire n4557_o; + wire n4559_o; + wire n4560_o; + wire n4562_o; + wire n4563_o; + wire n4565_o; + wire n4566_o; + wire n4568_o; + wire n4569_o; + wire n4571_o; + wire n4572_o; + wire n4574_o; + wire n4575_o; + wire n4577_o; + wire n4578_o; + wire n4580_o; + wire n4581_o; + wire n4583_o; + wire n4584_o; + wire n4586_o; + wire n4587_o; + wire n4589_o; + wire n4590_o; + wire n4592_o; + wire n4593_o; + wire n4595_o; + wire n4596_o; + wire n4598_o; + wire n4599_o; + wire n4601_o; + wire n4602_o; + wire n4604_o; + wire n4605_o; + wire n4607_o; + wire n4608_o; + wire n4610_o; + wire n4611_o; + wire n4613_o; + wire n4614_o; + wire n4616_o; + wire n4617_o; + wire [30:0] n4618_o; + wire n4620_o; + wire n4622_o; + wire n4623_o; + wire n4625_o; + wire n4627_o; + wire [2:0] n4628_o; + reg [2:0] n4630_o; + reg n4633_o; + reg [3:0] n4635_o; + reg n4638_o; + reg [2:0] n4642_o; + reg n4645_o; + wire n4647_o; + wire n4649_o; + wire n4650_o; + wire n4652_o; + wire n4653_o; + wire n4655_o; + wire n4656_o; + wire n4658_o; + wire n4659_o; + wire n4661_o; + wire n4662_o; + wire n4664_o; + wire n4665_o; + wire n4667_o; + wire n4668_o; + wire n4670_o; + wire n4672_o; + wire [2:0] n4673_o; + wire [2:0] n4674_o; + wire [3:0] n4676_o; + wire [30:0] n4677_o; + wire n4679_o; + wire n4681_o; + wire n4682_o; + wire n4684_o; + wire [1:0] n4685_o; + reg [2:0] n4687_o; + reg [3:0] n4689_o; + reg [2:0] n4692_o; + wire [2:0] n4695_o; + wire [2:0] n4696_o; + wire n4697_o; + wire [3:0] n4698_o; + wire [2:0] n4700_o; + wire n4703_o; + wire n4705_o; + wire n4707_o; + wire n4708_o; + wire n4710_o; + wire n4711_o; + wire n4713_o; + wire n4714_o; + wire n4716_o; + wire n4717_o; + wire n4719_o; + wire n4720_o; + wire n4722_o; + wire n4723_o; + wire n4725_o; + wire n4726_o; + wire n4728_o; + wire n4729_o; + wire n4731_o; + wire n4732_o; + wire n4734_o; + wire n4735_o; + wire n4737_o; + wire n4738_o; + wire n4740_o; + wire n4741_o; + wire n4743_o; + wire n4744_o; + wire n4746_o; + wire n4747_o; + wire n4749_o; + wire n4750_o; + wire n4752_o; + wire n4753_o; + wire n4755_o; + wire n4756_o; + wire n4758_o; + wire n4759_o; + wire n4761_o; + wire n4762_o; + wire n4764_o; + wire n4765_o; + wire n4767_o; + wire n4768_o; + wire n4770_o; + wire n4771_o; + wire n4773_o; + wire n4774_o; + wire n4776_o; + wire n4777_o; + wire n4779_o; + wire n4780_o; + wire n4782_o; + wire n4783_o; + wire n4785_o; + wire n4786_o; + wire n4788_o; + wire n4789_o; + wire n4791_o; + wire n4792_o; + wire n4794_o; + wire n4795_o; + wire n4797_o; + wire n4798_o; + wire n4800_o; + wire n4801_o; + wire n4803_o; + wire n4804_o; + wire n4806_o; + wire n4807_o; + wire n4809_o; + wire n4810_o; + wire n4812_o; + wire n4813_o; + wire n4815_o; + wire n4816_o; + wire n4818_o; + wire n4819_o; + wire n4821_o; + wire n4822_o; + wire n4824_o; + wire n4825_o; + wire n4827_o; + wire n4828_o; + wire n4830_o; + wire n4831_o; + wire n4833_o; + wire n4834_o; + wire n4836_o; + wire n4837_o; + wire n4839_o; + wire n4840_o; + wire n4842_o; + wire n4843_o; + wire n4845_o; + wire n4846_o; + wire n4848_o; + wire n4849_o; + wire n4851_o; + wire n4852_o; + wire n4854_o; + wire n4855_o; + wire n4857_o; + wire n4858_o; + wire n4860_o; + wire n4861_o; + wire n4863_o; + wire n4864_o; + wire n4866_o; + wire n4867_o; + wire n4869_o; + wire n4870_o; + wire [30:0] n4871_o; + wire n4873_o; + wire n4875_o; + wire n4876_o; + wire n4878_o; + wire [1:0] n4879_o; + reg [2:0] n4881_o; + reg [3:0] n4883_o; + reg [2:0] n4886_o; + wire n4888_o; + wire n4890_o; + wire n4891_o; + wire n4893_o; + wire n4894_o; + wire n4896_o; + wire n4897_o; + wire n4899_o; + wire n4900_o; + wire n4902_o; + wire n4903_o; + wire n4905_o; + wire n4906_o; + wire n4908_o; + wire n4909_o; + wire n4911_o; + wire n4913_o; + wire n4916_o; + wire [3:0] n4918_o; + wire n4921_o; + wire [30:0] n4922_o; + wire n4924_o; + wire n4926_o; + wire n4927_o; + wire n4929_o; + wire n4931_o; + wire [2:0] n4932_o; + reg [2:0] n4934_o; + reg n4937_o; + reg [3:0] n4939_o; + reg n4942_o; + reg [2:0] n4946_o; + reg n4949_o; + wire [2:0] n4952_o; + wire [2:0] n4953_o; + wire n4954_o; + wire [3:0] n4955_o; + wire n4956_o; + wire [2:0] n4958_o; + wire n4960_o; + wire n4963_o; + wire n4965_o; + wire n4967_o; + wire n4968_o; + wire n4970_o; + wire n4971_o; + wire n4973_o; + wire n4974_o; + wire n4976_o; + wire n4977_o; + wire n4979_o; + wire n4980_o; + wire n4982_o; + wire n4983_o; + wire n4985_o; + wire n4986_o; + wire n4988_o; + wire n4989_o; + wire n4991_o; + wire n4992_o; + wire n4994_o; + wire n4995_o; + wire n4997_o; + wire n4998_o; + wire n5000_o; + wire n5001_o; + wire n5003_o; + wire n5004_o; + wire n5006_o; + wire n5007_o; + wire n5009_o; + wire n5010_o; + wire n5012_o; + wire n5013_o; + wire n5015_o; + wire n5016_o; + wire n5018_o; + wire n5019_o; + wire n5021_o; + wire n5022_o; + wire n5024_o; + wire n5025_o; + wire n5027_o; + wire n5028_o; + wire n5030_o; + wire n5031_o; + wire n5033_o; + wire n5034_o; + wire n5036_o; + wire n5037_o; + wire n5039_o; + wire n5040_o; + wire n5042_o; + wire n5043_o; + wire n5045_o; + wire n5046_o; + wire n5048_o; + wire n5049_o; + wire n5051_o; + wire n5052_o; + wire n5054_o; + wire n5055_o; + wire n5057_o; + wire n5058_o; + wire n5060_o; + wire n5061_o; + wire n5063_o; + wire n5064_o; + wire n5066_o; + wire n5067_o; + wire n5069_o; + wire n5070_o; + wire n5072_o; + wire n5073_o; + wire n5075_o; + wire n5076_o; + wire n5078_o; + wire n5079_o; + wire n5081_o; + wire n5082_o; + wire n5084_o; + wire n5085_o; + wire n5087_o; + wire n5088_o; + wire n5090_o; + wire n5091_o; + wire n5093_o; + wire n5094_o; + wire n5096_o; + wire n5097_o; + wire n5099_o; + wire n5100_o; + wire n5102_o; + wire n5103_o; + wire n5105_o; + wire n5106_o; + wire n5108_o; + wire n5109_o; + wire n5111_o; + wire n5112_o; + wire n5114_o; + wire n5115_o; + wire n5117_o; + wire n5118_o; + wire n5120_o; + wire n5121_o; + wire n5123_o; + wire n5124_o; + wire n5126_o; + wire n5127_o; + wire n5129_o; + wire n5130_o; + wire [30:0] n5131_o; + wire n5133_o; + wire n5135_o; + wire n5136_o; + wire n5138_o; + wire n5140_o; + wire [2:0] n5141_o; + reg [2:0] n5143_o; + reg n5146_o; + reg [3:0] n5148_o; + reg n5151_o; + reg [2:0] n5155_o; + reg n5158_o; + wire n5160_o; + wire n5162_o; + wire n5163_o; + wire n5165_o; + wire n5166_o; + wire n5168_o; + wire n5169_o; + wire n5171_o; + wire n5172_o; + wire n5174_o; + wire n5175_o; + wire n5177_o; + wire n5178_o; + wire n5180_o; + wire n5181_o; + wire n5183_o; + wire n5185_o; + wire n5188_o; + wire [3:0] n5190_o; + wire n5193_o; + wire [30:0] n5194_o; + wire n5196_o; + wire n5198_o; + wire n5199_o; + wire n5201_o; + wire n5203_o; + wire [2:0] n5204_o; + reg [2:0] n5206_o; + reg n5209_o; + reg [3:0] n5211_o; + reg n5214_o; + reg [2:0] n5218_o; + reg n5221_o; + wire [2:0] n5224_o; + wire [2:0] n5225_o; + wire n5226_o; + wire [3:0] n5227_o; + wire n5228_o; + wire [2:0] n5230_o; + wire n5232_o; + wire n5235_o; + wire n5237_o; + wire n5239_o; + wire n5240_o; + wire n5242_o; + wire n5243_o; + wire n5245_o; + wire n5246_o; + wire n5248_o; + wire n5249_o; + wire n5251_o; + wire n5252_o; + wire n5254_o; + wire n5255_o; + wire n5257_o; + wire n5258_o; + wire n5260_o; + wire n5261_o; + wire n5263_o; + wire n5264_o; + wire n5266_o; + wire n5267_o; + wire n5269_o; + wire n5270_o; + wire n5272_o; + wire n5273_o; + wire n5275_o; + wire n5276_o; + wire n5278_o; + wire n5279_o; + wire n5281_o; + wire n5282_o; + wire n5284_o; + wire n5285_o; + wire n5287_o; + wire n5288_o; + wire n5290_o; + wire n5291_o; + wire n5293_o; + wire n5294_o; + wire n5296_o; + wire n5297_o; + wire n5299_o; + wire n5300_o; + wire n5302_o; + wire n5303_o; + wire n5305_o; + wire n5306_o; + wire n5308_o; + wire n5309_o; + wire n5311_o; + wire n5312_o; + wire n5314_o; + wire n5315_o; + wire n5317_o; + wire n5318_o; + wire n5320_o; + wire n5321_o; + wire n5323_o; + wire n5324_o; + wire n5326_o; + wire n5327_o; + wire n5329_o; + wire n5330_o; + wire n5332_o; + wire n5333_o; + wire n5335_o; + wire n5336_o; + wire n5338_o; + wire n5339_o; + wire n5341_o; + wire n5342_o; + wire n5344_o; + wire n5345_o; + wire n5347_o; + wire n5348_o; + wire n5350_o; + wire n5351_o; + wire n5353_o; + wire n5354_o; + wire n5356_o; + wire n5357_o; + wire n5359_o; + wire n5360_o; + wire n5362_o; + wire n5363_o; + wire n5365_o; + wire n5366_o; + wire n5368_o; + wire n5369_o; + wire n5371_o; + wire n5372_o; + wire n5374_o; + wire n5375_o; + wire n5377_o; + wire n5378_o; + wire n5380_o; + wire n5381_o; + wire n5383_o; + wire n5384_o; + wire n5386_o; + wire n5387_o; + wire n5389_o; + wire n5390_o; + wire n5392_o; + wire n5393_o; + wire n5395_o; + wire n5396_o; + wire n5398_o; + wire n5399_o; + wire n5401_o; + wire n5402_o; + wire [30:0] n5403_o; + wire n5405_o; + wire n5407_o; + wire n5408_o; + wire n5410_o; + wire n5412_o; + wire [2:0] n5413_o; + reg [2:0] n5415_o; + reg n5418_o; + reg [3:0] n5420_o; + reg n5423_o; + reg [2:0] n5427_o; + reg n5430_o; + wire n5432_o; + wire n5434_o; + wire n5435_o; + wire n5437_o; + wire n5438_o; + wire n5440_o; + wire n5441_o; + wire n5443_o; + wire n5444_o; + wire n5446_o; + wire n5447_o; + wire n5449_o; + wire n5450_o; + wire n5452_o; + wire n5453_o; + wire [7:0] n5454_o; + reg [2:0] n5460_o; + reg [2:0] n5462_o; + reg n5465_o; + reg [2:0] n5467_o; + reg [3:0] n5469_o; + reg n5472_o; + reg [2:0] n5474_o; + reg n5477_o; + reg n5480_o; + wire n5482_o; + wire n5484_o; + wire n5486_o; + wire n5487_o; + wire n5489_o; + wire n5490_o; + wire n5492_o; + wire n5493_o; + wire n5495_o; + wire n5496_o; + wire n5498_o; + wire n5499_o; + wire n5501_o; + wire n5502_o; + wire n5504_o; + wire n5505_o; + wire n5507_o; + wire n5508_o; + wire n5510_o; + wire n5511_o; + wire n5513_o; + wire n5514_o; + wire n5516_o; + wire n5517_o; + wire n5519_o; + wire n5520_o; + wire n5522_o; + wire n5523_o; + wire n5525_o; + wire n5526_o; + wire n5528_o; + wire n5529_o; + wire n5531_o; + wire n5532_o; + wire n5534_o; + wire n5535_o; + wire n5537_o; + wire n5538_o; + wire n5540_o; + wire n5541_o; + wire n5543_o; + wire n5544_o; + wire n5546_o; + wire n5547_o; + wire n5549_o; + wire n5550_o; + wire n5552_o; + wire n5553_o; + wire n5555_o; + wire n5556_o; + wire n5558_o; + wire n5559_o; + wire n5561_o; + wire n5562_o; + wire n5564_o; + wire n5565_o; + wire n5567_o; + wire n5568_o; + wire n5570_o; + wire n5571_o; + wire n5573_o; + wire n5574_o; + wire n5576_o; + wire n5577_o; + wire n5579_o; + wire n5580_o; + wire n5582_o; + wire n5583_o; + wire n5585_o; + wire n5586_o; + wire n5588_o; + wire n5589_o; + wire n5591_o; + wire n5592_o; + wire n5594_o; + wire n5595_o; + wire n5597_o; + wire n5598_o; + wire n5600_o; + wire n5601_o; + wire n5603_o; + wire n5604_o; + wire n5606_o; + wire n5607_o; + wire n5609_o; + wire n5610_o; + wire n5612_o; + wire n5613_o; + wire n5615_o; + wire n5616_o; + wire n5618_o; + wire n5619_o; + wire n5621_o; + wire n5622_o; + wire n5624_o; + wire n5625_o; + wire n5627_o; + wire n5628_o; + wire n5630_o; + wire n5631_o; + wire n5633_o; + wire n5634_o; + wire n5636_o; + wire n5637_o; + wire n5639_o; + wire n5640_o; + wire n5642_o; + wire n5643_o; + wire n5645_o; + wire n5646_o; + wire n5648_o; + wire n5649_o; + wire n5651_o; + wire n5652_o; + wire n5654_o; + wire n5655_o; + wire n5657_o; + wire n5658_o; + wire n5660_o; + wire n5661_o; + wire n5663_o; + wire n5664_o; + wire n5666_o; + wire n5667_o; + wire n5669_o; + wire n5670_o; + wire n5672_o; + wire n5673_o; + wire n5675_o; + wire n5676_o; + wire n5678_o; + wire n5679_o; + wire n5681_o; + wire n5682_o; + wire n5684_o; + wire n5685_o; + wire n5687_o; + wire n5688_o; + wire n5690_o; + wire n5691_o; + wire n5693_o; + wire n5694_o; + wire n5696_o; + wire n5697_o; + wire n5699_o; + wire n5700_o; + wire n5702_o; + wire n5703_o; + wire n5705_o; + wire n5706_o; + wire n5708_o; + wire n5709_o; + wire n5711_o; + wire n5712_o; + wire n5714_o; + wire n5715_o; + wire n5717_o; + wire n5718_o; + wire n5720_o; + wire n5721_o; + wire n5723_o; + wire n5724_o; + wire n5726_o; + wire n5727_o; + wire n5729_o; + wire n5730_o; + wire n5732_o; + wire n5733_o; + wire n5735_o; + wire n5736_o; + wire n5738_o; + wire n5739_o; + wire n5741_o; + wire n5742_o; + wire n5744_o; + wire n5745_o; + wire n5747_o; + wire n5748_o; + wire n5750_o; + wire n5751_o; + wire n5753_o; + wire n5754_o; + wire n5756_o; + wire n5757_o; + wire n5759_o; + wire n5760_o; + wire n5762_o; + wire n5763_o; + wire n5765_o; + wire n5766_o; + wire n5768_o; + wire n5769_o; + wire n5771_o; + wire n5772_o; + wire n5774_o; + wire n5775_o; + wire n5777_o; + wire n5778_o; + wire n5780_o; + wire n5781_o; + wire n5783_o; + wire n5784_o; + wire n5786_o; + wire n5787_o; + wire n5789_o; + wire n5790_o; + wire n5792_o; + wire n5793_o; + wire n5795_o; + wire n5796_o; + wire n5798_o; + wire n5799_o; + wire n5801_o; + wire n5802_o; + wire n5804_o; + wire n5805_o; + wire n5807_o; + wire n5808_o; + wire n5810_o; + wire n5811_o; + wire n5813_o; + wire n5814_o; + wire n5816_o; + wire n5817_o; + wire n5819_o; + wire n5820_o; + wire n5822_o; + wire n5823_o; + wire n5825_o; + wire n5826_o; + wire n5828_o; + wire n5829_o; + wire n5831_o; + wire n5832_o; + wire n5834_o; + wire n5835_o; + wire n5837_o; + wire n5838_o; + wire n5840_o; + wire n5841_o; + wire n5843_o; + wire n5844_o; + wire n5846_o; + wire n5847_o; + wire n5849_o; + wire n5850_o; + wire n5852_o; + wire n5853_o; + wire n5855_o; + wire n5856_o; + wire n5858_o; + wire n5859_o; + wire n5861_o; + wire n5862_o; + wire n5864_o; + wire n5865_o; + wire n5867_o; + wire n5868_o; + wire n5870_o; + wire n5871_o; + wire n5873_o; + wire n5874_o; + wire n5876_o; + wire n5877_o; + wire n5879_o; + wire n5880_o; + wire n5882_o; + wire n5883_o; + wire n5885_o; + wire n5886_o; + wire n5888_o; + wire n5889_o; + wire n5891_o; + wire n5892_o; + wire n5894_o; + wire n5895_o; + wire n5897_o; + wire n5898_o; + wire n5900_o; + wire n5901_o; + wire n5903_o; + wire n5904_o; + wire n5906_o; + wire n5907_o; + wire n5909_o; + wire n5910_o; + wire n5912_o; + wire n5913_o; + wire n5915_o; + wire n5916_o; + wire n5918_o; + wire n5919_o; + wire n5921_o; + wire n5922_o; + wire n5924_o; + wire n5925_o; + wire n5927_o; + wire n5928_o; + wire n5930_o; + wire n5931_o; + wire n5933_o; + wire n5934_o; + wire n5936_o; + wire n5937_o; + wire n5939_o; + wire n5940_o; + wire n5942_o; + wire n5943_o; + wire n5945_o; + wire n5946_o; + wire n5948_o; + wire n5949_o; + wire n5951_o; + wire n5952_o; + wire n5954_o; + wire n5955_o; + wire n5957_o; + wire n5958_o; + wire n5960_o; + wire n5961_o; + wire n5963_o; + wire n5964_o; + wire n5966_o; + wire n5967_o; + wire n5969_o; + wire n5970_o; + wire n5972_o; + wire n5973_o; + wire n5975_o; + wire n5976_o; + wire n5978_o; + wire n5979_o; + wire n5981_o; + wire n5982_o; + wire n5984_o; + wire n5985_o; + wire n5987_o; + wire n5988_o; + wire n5990_o; + wire n5991_o; + wire n5993_o; + wire n5994_o; + wire n5996_o; + wire n5997_o; + wire n5999_o; + wire n6000_o; + wire n6002_o; + wire n6003_o; + wire n6005_o; + wire n6006_o; + wire n6008_o; + wire n6009_o; + wire n6011_o; + wire n6013_o; + wire n6014_o; + wire n6016_o; + wire n6018_o; + wire n6020_o; + wire n6022_o; + wire [30:0] n6023_o; + wire n6025_o; + wire n6027_o; + wire [1:0] n6028_o; + wire n6030_o; + wire [1:0] n6031_o; + wire [2:0] n6033_o; + wire [2:0] n6035_o; + wire n6038_o; + wire n6040_o; + wire [1:0] n6041_o; + wire n6043_o; + wire [1:0] n6044_o; + wire [2:0] n6046_o; + wire [2:0] n6048_o; + wire n6051_o; + wire n6053_o; + wire [3:0] n6054_o; + reg n6058_o; + reg n6061_o; + reg n6065_o; + reg [2:0] n6067_o; + reg n6069_o; + reg [2:0] n6073_o; + reg n6076_o; + reg n6079_o; + wire n6081_o; + wire n6083_o; + wire n6084_o; + wire n6086_o; + wire n6087_o; + wire n6089_o; + wire n6090_o; + wire [30:0] n6091_o; + wire n6093_o; + wire [1:0] n6094_o; + wire n6096_o; + wire [1:0] n6097_o; + wire [3:0] n6100_o; + wire [3:0] n6102_o; + wire n6104_o; + wire [1:0] n6105_o; + wire n6107_o; + wire [1:0] n6108_o; + wire [3:0] n6111_o; + wire [3:0] n6113_o; + wire n6115_o; + wire n6117_o; + wire [3:0] n6118_o; + reg n6122_o; + reg n6125_o; + reg [3:0] n6127_o; + reg [2:0] n6131_o; + reg n6134_o; + reg n6137_o; + reg n6141_o; + wire n6143_o; + wire n6145_o; + wire n6146_o; + wire n6148_o; + wire n6149_o; + wire n6151_o; + wire n6152_o; + wire [30:0] n6153_o; + wire n6155_o; + wire n6157_o; + wire n6158_o; + wire [3:0] n6161_o; + wire n6163_o; + wire n6164_o; + wire n6165_o; + wire [3:0] n6168_o; + wire n6170_o; + wire n6172_o; + wire [3:0] n6173_o; + reg [2:0] n6176_o; + reg [3:0] n6179_o; + reg [2:0] n6181_o; + reg [3:0] n6184_o; + reg [3:0] n6186_o; + reg [2:0] n6190_o; + reg n6193_o; + reg n6196_o; + reg n6199_o; + wire n6201_o; + wire n6203_o; + wire n6204_o; + wire n6206_o; + wire n6207_o; + wire n6209_o; + wire n6210_o; + wire [30:0] n6211_o; + wire n6213_o; + wire n6215_o; + wire n6216_o; + wire [3:0] n6219_o; + wire n6221_o; + wire n6223_o; + wire n6225_o; + wire [3:0] n6226_o; + reg [2:0] n6229_o; + reg [3:0] n6232_o; + reg [2:0] n6234_o; + reg [3:0] n6237_o; + reg [3:0] n6239_o; + reg n6242_o; + reg n6245_o; + reg [2:0] n6248_o; + reg n6251_o; + reg n6255_o; + wire n6257_o; + wire n6259_o; + wire n6260_o; + wire n6262_o; + wire n6263_o; + wire n6265_o; + wire n6266_o; + wire n6268_o; + wire n6270_o; + wire n6271_o; + wire n6273_o; + wire n6274_o; + wire n6276_o; + wire n6277_o; + wire n6279_o; + wire n6280_o; + wire n6282_o; + wire n6283_o; + wire n6285_o; + wire n6286_o; + wire n6288_o; + wire n6289_o; + wire n6291_o; + wire n6293_o; + wire n6294_o; + wire n6296_o; + wire n6297_o; + wire n6299_o; + wire n6300_o; + wire n6302_o; + wire n6304_o; + wire n6305_o; + wire n6307_o; + wire n6309_o; + wire n6310_o; + wire [30:0] n6311_o; + wire [1:0] n6313_o; + wire [30:0] n6314_o; + wire [1:0] n6315_o; + wire n6318_o; + wire n6320_o; + wire n6321_o; + wire n6323_o; + wire n6324_o; + reg n6326_o; + reg [1:0] n6328_o; + reg n6331_o; + wire n6333_o; + wire [1:0] n6335_o; + wire [30:0] n6336_o; + wire [1:0] n6337_o; + wire n6340_o; + wire n6342_o; + wire n6343_o; + wire n6345_o; + wire n6346_o; + reg n6348_o; + reg [1:0] n6350_o; + reg n6353_o; + wire n6355_o; + wire [1:0] n6356_o; + reg [2:0] n6358_o; + reg n6362_o; + reg [2:0] n6364_o; + reg n6366_o; + reg [1:0] n6368_o; + reg n6370_o; + reg [3:0] n6373_o; + reg n6377_o; + reg [1:0] n6380_o; + reg n6384_o; + wire n6386_o; + wire n6388_o; + wire n6389_o; + wire n6391_o; + wire n6392_o; + wire n6394_o; + wire n6395_o; + wire [30:0] n6396_o; + wire [1:0] n6398_o; + wire [30:0] n6399_o; + wire [1:0] n6400_o; + wire n6403_o; + wire n6405_o; + wire n6406_o; + wire n6408_o; + wire n6409_o; + reg n6411_o; + reg [1:0] n6413_o; + reg n6416_o; + wire n6418_o; + wire [1:0] n6420_o; + wire [30:0] n6421_o; + wire [1:0] n6422_o; + wire n6424_o; + wire n6426_o; + wire n6427_o; + wire n6429_o; + wire n6430_o; + reg n6433_o; + reg [1:0] n6435_o; + reg n6438_o; + wire n6440_o; + wire [1:0] n6441_o; + reg [2:0] n6443_o; + reg n6447_o; + reg [2:0] n6449_o; + reg n6451_o; + reg [1:0] n6453_o; + reg n6455_o; + reg [3:0] n6458_o; + reg n6462_o; + reg [1:0] n6465_o; + reg n6469_o; + wire n6471_o; + wire n6473_o; + wire n6474_o; + wire n6476_o; + wire n6477_o; + wire n6479_o; + wire n6480_o; + wire [30:0] n6481_o; + wire n6483_o; + wire n6487_o; + wire n6489_o; + wire n6491_o; + wire [3:0] n6492_o; + reg [2:0] n6494_o; + reg n6497_o; + reg [2:0] n6499_o; + reg [2:0] n6501_o; + reg [3:0] n6503_o; + reg n6506_o; + reg [2:0] n6510_o; + reg n6513_o; + reg n6516_o; + reg n6519_o; + wire n6521_o; + wire [30:0] n6522_o; + wire n6524_o; + wire n6528_o; + wire n6530_o; + wire n6532_o; + wire [3:0] n6533_o; + reg [2:0] n6535_o; + reg n6538_o; + reg [2:0] n6540_o; + reg [2:0] n6542_o; + reg [3:0] n6544_o; + reg n6547_o; + reg [2:0] n6551_o; + reg n6554_o; + reg n6557_o; + reg n6560_o; + wire n6562_o; + wire [30:0] n6563_o; + wire n6565_o; + wire n6567_o; + wire n6569_o; + wire [2:0] n6570_o; + reg [3:0] n6574_o; + reg [2:0] n6578_o; + reg n6581_o; + reg n6584_o; + reg n6587_o; + reg n6590_o; + wire n6592_o; + wire n6594_o; + wire n6595_o; + wire n6597_o; + wire n6598_o; + wire n6600_o; + wire n6601_o; + wire n6603_o; + wire n6604_o; + wire n6606_o; + wire n6607_o; + wire n6609_o; + wire n6610_o; + wire n6612_o; + wire n6613_o; + wire [30:0] n6614_o; + wire n6616_o; + wire [2:0] n6617_o; + wire n6619_o; + wire [2:0] n6620_o; + wire n6623_o; + wire [2:0] n6625_o; + wire n6627_o; + wire [1:0] n6628_o; + reg n6630_o; + reg [2:0] n6632_o; + reg [2:0] n6635_o; + reg n6638_o; + reg n6641_o; + reg [1:0] n6644_o; + wire n6646_o; + wire n6648_o; + wire n6649_o; + wire n6651_o; + wire n6652_o; + wire n6654_o; + wire n6655_o; + wire n6657_o; + wire n6658_o; + wire n6660_o; + wire n6661_o; + wire n6663_o; + wire n6664_o; + wire n6666_o; + wire n6667_o; + wire [30:0] n6668_o; + wire [2:0] n6669_o; + wire [2:0] n6670_o; + wire n6672_o; + wire n6675_o; + wire n6677_o; + wire n6679_o; + wire [1:0] n6680_o; + reg [2:0] n6682_o; + reg n6684_o; + reg [2:0] n6687_o; + reg n6690_o; + reg [1:0] n6693_o; + reg n6696_o; + wire n6698_o; + wire n6700_o; + wire n6701_o; + wire n6703_o; + wire n6704_o; + wire n6706_o; + wire n6707_o; + wire n6709_o; + wire n6710_o; + wire n6712_o; + wire n6713_o; + wire n6715_o; + wire n6716_o; + wire n6718_o; + wire n6719_o; + wire [30:0] n6720_o; + wire n6721_o; + wire n6723_o; + wire n6725_o; + wire n6726_o; + wire n6727_o; + wire [3:0] n6730_o; + wire n6732_o; + wire n6734_o; + wire [3:0] n6735_o; + reg [2:0] n6738_o; + wire [2:0] n6739_o; + reg [2:0] n6741_o; + wire n6742_o; + reg n6744_o; + reg n6747_o; + reg [3:0] n6750_o; + reg [3:0] n6754_o; + reg [3:0] n6756_o; + reg n6759_o; + reg [2:0] n6763_o; + reg n6766_o; + reg n6769_o; + reg [1:0] n6772_o; + reg n6775_o; + reg n6778_o; + wire n6780_o; + wire n6782_o; + wire n6783_o; + wire n6785_o; + wire n6786_o; + wire n6788_o; + wire n6789_o; + wire [30:0] n6790_o; + wire n6792_o; + wire n6793_o; + wire n6795_o; + wire n6796_o; + wire n6797_o; + wire [3:0] n6800_o; + wire n6802_o; + wire n6804_o; + wire [3:0] n6805_o; + reg [2:0] n6808_o; + wire [2:0] n6809_o; + reg [2:0] n6811_o; + wire n6812_o; + reg n6814_o; + reg n6817_o; + reg [3:0] n6820_o; + reg [3:0] n6824_o; + reg [3:0] n6826_o; + reg n6829_o; + reg [2:0] n6833_o; + reg n6836_o; + reg n6839_o; + reg [1:0] n6842_o; + reg n6845_o; + reg n6848_o; + wire n6850_o; + wire n6852_o; + wire n6853_o; + wire n6855_o; + wire n6856_o; + wire n6858_o; + wire n6859_o; + wire [22:0] n6860_o; + reg [2:0] n6876_o; + reg [2:0] n6882_o; + reg n6885_o; + reg n6888_o; + wire [2:0] n6889_o; + wire [2:0] n6890_o; + wire [2:0] n6891_o; + reg [2:0] n6894_o; + wire n6895_o; + wire n6896_o; + wire n6897_o; + reg n6900_o; + reg n6903_o; + reg n6907_o; + wire [2:0] n6909_o; + wire [2:0] n6910_o; + reg [2:0] n6913_o; + wire n6915_o; + wire n6916_o; + reg n6919_o; + wire n6920_o; + wire n6921_o; + wire n6922_o; + wire n6924_o; + wire n6925_o; + wire n6926_o; + wire n6927_o; + wire n6928_o; + reg n6931_o; + wire [1:0] n6932_o; + wire [1:0] n6933_o; + wire [1:0] n6934_o; + wire [1:0] n6936_o; + wire [1:0] n6937_o; + wire [1:0] n6938_o; + wire [1:0] n6939_o; + wire [1:0] n6940_o; + reg [1:0] n6943_o; + wire n6944_o; + wire n6945_o; + wire n6946_o; + wire n6948_o; + wire n6949_o; + reg n6952_o; + reg [3:0] n6955_o; + reg n6959_o; + reg n6962_o; + reg [2:0] n6965_o; + reg n6968_o; + reg n6971_o; + reg n6974_o; + reg n6977_o; + reg [2:0] n6984_o; + reg n6987_o; + reg n6990_o; + reg n6993_o; + reg n6996_o; + reg n6999_o; + reg n7002_o; + reg n7005_o; + reg [1:0] n7008_o; + reg [1:0] n7014_o; + reg n7017_o; + reg n7020_o; + wire [1:0] n7021_o; + reg [2:0] n7022_o; + reg [2:0] n7024_o; + reg [1:0] n7026_o; + reg n7029_o; + reg n7032_o; + wire [1:0] n7034_o; + reg [1:0] n7036_o; + wire n7037_o; + wire n7038_o; + reg n7040_o; + wire n7041_o; + reg n7043_o; + reg n7047_o; + reg n7050_o; + reg [2:0] n7052_o; + reg n7054_o; + wire n7057_o; + reg n7058_o; + wire [1:0] n7059_o; + reg [1:0] n7060_o; + reg n7062_o; + reg [3:0] n7066_o; + reg n7067_o; + reg n7070_o; + reg n7073_o; + reg [2:0] n7075_o; + reg n7078_o; + reg n7081_o; + reg n7084_o; + reg n7087_o; + reg n7090_o; + reg n7093_o; + reg n7096_o; + reg n7099_o; + reg n7102_o; + reg [2:0] n7105_o; + reg n7108_o; + reg n7111_o; + reg n7114_o; + reg n7117_o; + reg n7120_o; + reg n7123_o; + reg n7126_o; + reg n7129_o; + reg n7132_o; + reg n7135_o; + reg n7138_o; + reg n7141_o; + reg n7144_o; + reg n7147_o; + reg n7150_o; + reg [1:0] n7153_o; + reg n7156_o; + reg n7159_o; + reg [1:0] n7162_o; + reg n7165_o; + reg n7168_o; + reg n7170_o; + reg n7173_o; + wire n7176_o; + wire n7178_o; + wire n7180_o; + wire n7181_o; + wire [2:0] n7183_o; + wire n7185_o; + wire n7186_o; + wire n7188_o; + wire n7190_o; + wire [2:0] n7192_o; + wire n7195_o; + wire n7197_o; + wire n7198_o; + wire n7200_o; + wire n7202_o; + wire [2:0] n7204_o; + wire n7205_o; + wire [3:0] n7206_o; + wire [3:0] n7207_o; + wire [3:0] n7208_o; + wire n7209_o; + wire n7210_o; + wire [3:0] n7212_o; + wire [3:0] n7213_o; + assign mcycles = n7022_o; + assign tstates = n7204_o; + assign prefix = n7026_o; + assign inc_pc = n7200_o; + assign inc_wz = n7032_o; + assign incdec_16 = n7212_o; + assign read_to_reg = n7047_o; + assign read_to_acc = n7050_o; + assign set_busa_to = n7213_o; + assign set_busb_to = n7208_o; + assign alu_op = n7066_o; + assign save_alu = n7067_o; + assign preservec = n7070_o; + assign arith16 = n7073_o; + assign set_addr_to = n7192_o; + assign iorq = n7078_o; + assign jump = n7081_o; + assign jumpe = n7084_o; + assign jumpxy = n7087_o; + assign call = n7090_o; + assign rstp = n7093_o; + assign ldz = n7096_o; + assign ldw = n7099_o; + assign ldsphl = n7102_o; + assign special_ld = n7105_o; + assign exchangedh = n7108_o; + assign exchangerp = n7111_o; + assign exchangeaf = n7114_o; + assign exchangers = n7117_o; + assign i_djnz = n7120_o; + assign i_cpl = n7123_o; + assign i_ccf = n7126_o; + assign i_scf = n7129_o; + assign i_retn = n7132_o; + assign i_bt = n7135_o; + assign i_bc = n7138_o; + assign i_btr = n7141_o; + assign i_rld = n7144_o; + assign i_rrd = n7147_o; + assign i_inrc = n7150_o; + assign setwz = n7153_o; + assign setdi = n7156_o; + assign setei = n7159_o; + assign imode = n7162_o; + assign halt = n7165_o; + assign noread = n7210_o; + assign write = n7170_o; + assign xybit_undoc = n7173_o; + /* T80_MCode.vhd:198:26 */ + assign n2193_o = ir[5:3]; + /* T80_MCode.vhd:199:26 */ + assign n2194_o = ir[2:0]; + /* T80_MCode.vhd:200:28 */ + assign n2195_o = ir[5:4]; + /* T80_MCode.vhd:204:27 */ + assign n2197_o = mcycle == 3'b001; + /* T80_MCode.vhd:204:17 */ + assign n2200_o = n2197_o ? 3'b100 : 3'b011; + /* T80_MCode.vhd:217:35 */ + assign n2201_o = ir[5:3]; + /* T80_MCode.vhd:217:31 */ + assign n2203_o = {1'b0, n2201_o}; + /* T80_MCode.vhd:267:17 */ + assign n2205_o = ir == 8'b01000000; + /* T80_MCode.vhd:267:32 */ + assign n2207_o = ir == 8'b01000001; + /* T80_MCode.vhd:267:32 */ + assign n2208_o = n2205_o | n2207_o; + /* T80_MCode.vhd:267:43 */ + assign n2210_o = ir == 8'b01000010; + /* T80_MCode.vhd:267:43 */ + assign n2211_o = n2208_o | n2210_o; + /* T80_MCode.vhd:267:54 */ + assign n2213_o = ir == 8'b01000011; + /* T80_MCode.vhd:267:54 */ + assign n2214_o = n2211_o | n2213_o; + /* T80_MCode.vhd:267:65 */ + assign n2216_o = ir == 8'b01000100; + /* T80_MCode.vhd:267:65 */ + assign n2217_o = n2214_o | n2216_o; + /* T80_MCode.vhd:267:76 */ + assign n2219_o = ir == 8'b01000101; + /* T80_MCode.vhd:267:76 */ + assign n2220_o = n2217_o | n2219_o; + /* T80_MCode.vhd:267:87 */ + assign n2222_o = ir == 8'b01000111; + /* T80_MCode.vhd:267:87 */ + assign n2223_o = n2220_o | n2222_o; + /* T80_MCode.vhd:268:25 */ + assign n2225_o = ir == 8'b01001000; + /* T80_MCode.vhd:268:25 */ + assign n2226_o = n2223_o | n2225_o; + /* T80_MCode.vhd:268:36 */ + assign n2228_o = ir == 8'b01001001; + /* T80_MCode.vhd:268:36 */ + assign n2229_o = n2226_o | n2228_o; + /* T80_MCode.vhd:268:47 */ + assign n2231_o = ir == 8'b01001010; + /* T80_MCode.vhd:268:47 */ + assign n2232_o = n2229_o | n2231_o; + /* T80_MCode.vhd:268:58 */ + assign n2234_o = ir == 8'b01001011; + /* T80_MCode.vhd:268:58 */ + assign n2235_o = n2232_o | n2234_o; + /* T80_MCode.vhd:268:69 */ + assign n2237_o = ir == 8'b01001100; + /* T80_MCode.vhd:268:69 */ + assign n2238_o = n2235_o | n2237_o; + /* T80_MCode.vhd:268:80 */ + assign n2240_o = ir == 8'b01001101; + /* T80_MCode.vhd:268:80 */ + assign n2241_o = n2238_o | n2240_o; + /* T80_MCode.vhd:268:91 */ + assign n2243_o = ir == 8'b01001111; + /* T80_MCode.vhd:268:91 */ + assign n2244_o = n2241_o | n2243_o; + /* T80_MCode.vhd:269:25 */ + assign n2246_o = ir == 8'b01010000; + /* T80_MCode.vhd:269:25 */ + assign n2247_o = n2244_o | n2246_o; + /* T80_MCode.vhd:269:36 */ + assign n2249_o = ir == 8'b01010001; + /* T80_MCode.vhd:269:36 */ + assign n2250_o = n2247_o | n2249_o; + /* T80_MCode.vhd:269:47 */ + assign n2252_o = ir == 8'b01010010; + /* T80_MCode.vhd:269:47 */ + assign n2253_o = n2250_o | n2252_o; + /* T80_MCode.vhd:269:58 */ + assign n2255_o = ir == 8'b01010011; + /* T80_MCode.vhd:269:58 */ + assign n2256_o = n2253_o | n2255_o; + /* T80_MCode.vhd:269:69 */ + assign n2258_o = ir == 8'b01010100; + /* T80_MCode.vhd:269:69 */ + assign n2259_o = n2256_o | n2258_o; + /* T80_MCode.vhd:269:80 */ + assign n2261_o = ir == 8'b01010101; + /* T80_MCode.vhd:269:80 */ + assign n2262_o = n2259_o | n2261_o; + /* T80_MCode.vhd:269:91 */ + assign n2264_o = ir == 8'b01010111; + /* T80_MCode.vhd:269:91 */ + assign n2265_o = n2262_o | n2264_o; + /* T80_MCode.vhd:270:25 */ + assign n2267_o = ir == 8'b01011000; + /* T80_MCode.vhd:270:25 */ + assign n2268_o = n2265_o | n2267_o; + /* T80_MCode.vhd:270:36 */ + assign n2270_o = ir == 8'b01011001; + /* T80_MCode.vhd:270:36 */ + assign n2271_o = n2268_o | n2270_o; + /* T80_MCode.vhd:270:47 */ + assign n2273_o = ir == 8'b01011010; + /* T80_MCode.vhd:270:47 */ + assign n2274_o = n2271_o | n2273_o; + /* T80_MCode.vhd:270:58 */ + assign n2276_o = ir == 8'b01011011; + /* T80_MCode.vhd:270:58 */ + assign n2277_o = n2274_o | n2276_o; + /* T80_MCode.vhd:270:69 */ + assign n2279_o = ir == 8'b01011100; + /* T80_MCode.vhd:270:69 */ + assign n2280_o = n2277_o | n2279_o; + /* T80_MCode.vhd:270:80 */ + assign n2282_o = ir == 8'b01011101; + /* T80_MCode.vhd:270:80 */ + assign n2283_o = n2280_o | n2282_o; + /* T80_MCode.vhd:270:91 */ + assign n2285_o = ir == 8'b01011111; + /* T80_MCode.vhd:270:91 */ + assign n2286_o = n2283_o | n2285_o; + /* T80_MCode.vhd:271:25 */ + assign n2288_o = ir == 8'b01100000; + /* T80_MCode.vhd:271:25 */ + assign n2289_o = n2286_o | n2288_o; + /* T80_MCode.vhd:271:36 */ + assign n2291_o = ir == 8'b01100001; + /* T80_MCode.vhd:271:36 */ + assign n2292_o = n2289_o | n2291_o; + /* T80_MCode.vhd:271:47 */ + assign n2294_o = ir == 8'b01100010; + /* T80_MCode.vhd:271:47 */ + assign n2295_o = n2292_o | n2294_o; + /* T80_MCode.vhd:271:58 */ + assign n2297_o = ir == 8'b01100011; + /* T80_MCode.vhd:271:58 */ + assign n2298_o = n2295_o | n2297_o; + /* T80_MCode.vhd:271:69 */ + assign n2300_o = ir == 8'b01100100; + /* T80_MCode.vhd:271:69 */ + assign n2301_o = n2298_o | n2300_o; + /* T80_MCode.vhd:271:80 */ + assign n2303_o = ir == 8'b01100101; + /* T80_MCode.vhd:271:80 */ + assign n2304_o = n2301_o | n2303_o; + /* T80_MCode.vhd:271:91 */ + assign n2306_o = ir == 8'b01100111; + /* T80_MCode.vhd:271:91 */ + assign n2307_o = n2304_o | n2306_o; + /* T80_MCode.vhd:272:25 */ + assign n2309_o = ir == 8'b01101000; + /* T80_MCode.vhd:272:25 */ + assign n2310_o = n2307_o | n2309_o; + /* T80_MCode.vhd:272:36 */ + assign n2312_o = ir == 8'b01101001; + /* T80_MCode.vhd:272:36 */ + assign n2313_o = n2310_o | n2312_o; + /* T80_MCode.vhd:272:47 */ + assign n2315_o = ir == 8'b01101010; + /* T80_MCode.vhd:272:47 */ + assign n2316_o = n2313_o | n2315_o; + /* T80_MCode.vhd:272:58 */ + assign n2318_o = ir == 8'b01101011; + /* T80_MCode.vhd:272:58 */ + assign n2319_o = n2316_o | n2318_o; + /* T80_MCode.vhd:272:69 */ + assign n2321_o = ir == 8'b01101100; + /* T80_MCode.vhd:272:69 */ + assign n2322_o = n2319_o | n2321_o; + /* T80_MCode.vhd:272:80 */ + assign n2324_o = ir == 8'b01101101; + /* T80_MCode.vhd:272:80 */ + assign n2325_o = n2322_o | n2324_o; + /* T80_MCode.vhd:272:91 */ + assign n2327_o = ir == 8'b01101111; + /* T80_MCode.vhd:272:91 */ + assign n2328_o = n2325_o | n2327_o; + /* T80_MCode.vhd:273:25 */ + assign n2330_o = ir == 8'b01111000; + /* T80_MCode.vhd:273:25 */ + assign n2331_o = n2328_o | n2330_o; + /* T80_MCode.vhd:273:36 */ + assign n2333_o = ir == 8'b01111001; + /* T80_MCode.vhd:273:36 */ + assign n2334_o = n2331_o | n2333_o; + /* T80_MCode.vhd:273:47 */ + assign n2336_o = ir == 8'b01111010; + /* T80_MCode.vhd:273:47 */ + assign n2337_o = n2334_o | n2336_o; + /* T80_MCode.vhd:273:58 */ + assign n2339_o = ir == 8'b01111011; + /* T80_MCode.vhd:273:58 */ + assign n2340_o = n2337_o | n2339_o; + /* T80_MCode.vhd:273:69 */ + assign n2342_o = ir == 8'b01111100; + /* T80_MCode.vhd:273:69 */ + assign n2343_o = n2340_o | n2342_o; + /* T80_MCode.vhd:273:80 */ + assign n2345_o = ir == 8'b01111101; + /* T80_MCode.vhd:273:80 */ + assign n2346_o = n2343_o | n2345_o; + /* T80_MCode.vhd:273:91 */ + assign n2348_o = ir == 8'b01111111; + /* T80_MCode.vhd:273:91 */ + assign n2349_o = n2346_o | n2348_o; + /* T80_MCode.vhd:282:30 */ + assign n2350_o = {28'b0, mcycle}; // uext + /* T80_MCode.vhd:283:25 */ + assign n2352_o = n2350_o == 31'b0000000000000000000000000000010; + /* T80_MCode.vhd:282:25 */ + always @* + case (n2352_o) + 1'b1: n2355_o = 1'b1; + default: n2355_o = 1'b0; + endcase + /* T80_MCode.vhd:282:25 */ + always @* + case (n2352_o) + 1'b1: n2358_o = 1'b1; + default: n2358_o = 1'b0; + endcase + /* T80_MCode.vhd:282:25 */ + always @* + case (n2352_o) + 1'b1: n2360_o = n2193_o; + default: n2360_o = 3'b000; + endcase + /* T80_MCode.vhd:279:17 */ + assign n2362_o = ir == 8'b00000110; + /* T80_MCode.vhd:279:32 */ + assign n2364_o = ir == 8'b00001110; + /* T80_MCode.vhd:279:32 */ + assign n2365_o = n2362_o | n2364_o; + /* T80_MCode.vhd:279:43 */ + assign n2367_o = ir == 8'b00010110; + /* T80_MCode.vhd:279:43 */ + assign n2368_o = n2365_o | n2367_o; + /* T80_MCode.vhd:279:54 */ + assign n2370_o = ir == 8'b00011110; + /* T80_MCode.vhd:279:54 */ + assign n2371_o = n2368_o | n2370_o; + /* T80_MCode.vhd:279:65 */ + assign n2373_o = ir == 8'b00100110; + /* T80_MCode.vhd:279:65 */ + assign n2374_o = n2371_o | n2373_o; + /* T80_MCode.vhd:279:76 */ + assign n2376_o = ir == 8'b00101110; + /* T80_MCode.vhd:279:76 */ + assign n2377_o = n2374_o | n2376_o; + /* T80_MCode.vhd:279:87 */ + assign n2379_o = ir == 8'b00111110; + /* T80_MCode.vhd:279:87 */ + assign n2380_o = n2377_o | n2379_o; + /* T80_MCode.vhd:292:30 */ + assign n2381_o = {28'b0, mcycle}; // uext + /* T80_MCode.vhd:293:25 */ + assign n2383_o = n2381_o == 31'b0000000000000000000000000000001; + /* T80_MCode.vhd:295:25 */ + assign n2385_o = n2381_o == 31'b0000000000000000000000000000010; + assign n2386_o = {n2385_o, n2383_o}; + /* T80_MCode.vhd:292:25 */ + always @* + case (n2386_o) + 2'b10: n2389_o = 1'b1; + 2'b01: n2389_o = 1'b0; + default: n2389_o = 1'b0; + endcase + /* T80_MCode.vhd:292:25 */ + always @* + case (n2386_o) + 2'b10: n2391_o = n2193_o; + 2'b01: n2391_o = 3'b000; + default: n2391_o = 3'b000; + endcase + /* T80_MCode.vhd:292:25 */ + always @* + case (n2386_o) + 2'b10: n2394_o = 3'b111; + 2'b01: n2394_o = 3'b010; + default: n2394_o = 3'b111; + endcase + /* T80_MCode.vhd:289:17 */ + assign n2396_o = ir == 8'b01000110; + /* T80_MCode.vhd:289:32 */ + assign n2398_o = ir == 8'b01001110; + /* T80_MCode.vhd:289:32 */ + assign n2399_o = n2396_o | n2398_o; + /* T80_MCode.vhd:289:43 */ + assign n2401_o = ir == 8'b01010110; + /* T80_MCode.vhd:289:43 */ + assign n2402_o = n2399_o | n2401_o; + /* T80_MCode.vhd:289:54 */ + assign n2404_o = ir == 8'b01011110; + /* T80_MCode.vhd:289:54 */ + assign n2405_o = n2402_o | n2404_o; + /* T80_MCode.vhd:289:65 */ + assign n2407_o = ir == 8'b01100110; + /* T80_MCode.vhd:289:65 */ + assign n2408_o = n2405_o | n2407_o; + /* T80_MCode.vhd:289:76 */ + assign n2410_o = ir == 8'b01101110; + /* T80_MCode.vhd:289:76 */ + assign n2411_o = n2408_o | n2410_o; + /* T80_MCode.vhd:289:87 */ + assign n2413_o = ir == 8'b01111110; + /* T80_MCode.vhd:289:87 */ + assign n2414_o = n2411_o | n2413_o; + /* T80_MCode.vhd:303:30 */ + assign n2415_o = {28'b0, mcycle}; // uext + /* T80_MCode.vhd:304:25 */ + assign n2418_o = n2415_o == 31'b0000000000000000000000000000001; + /* T80_MCode.vhd:308:25 */ + assign n2420_o = n2415_o == 31'b0000000000000000000000000000010; + assign n2421_o = {n2420_o, n2418_o}; + /* T80_MCode.vhd:303:25 */ + always @* + case (n2421_o) + 2'b10: n2423_o = 3'b000; + 2'b01: n2423_o = n2194_o; + default: n2423_o = 3'b000; + endcase + /* T80_MCode.vhd:303:25 */ + always @* + case (n2421_o) + 2'b10: n2425_o = 1'b0; + 2'b01: n2425_o = 1'b0; + default: n2425_o = 1'b0; + endcase + /* T80_MCode.vhd:303:25 */ + always @* + case (n2421_o) + 2'b10: n2428_o = 3'b111; + 2'b01: n2428_o = 3'b010; + default: n2428_o = 3'b111; + endcase + /* T80_MCode.vhd:303:25 */ + always @* + case (n2421_o) + 2'b10: n2431_o = 1'b1; + 2'b01: n2431_o = 1'b0; + default: n2431_o = 1'b0; + endcase + /* T80_MCode.vhd:300:17 */ + assign n2433_o = ir == 8'b01110000; + /* T80_MCode.vhd:300:32 */ + assign n2435_o = ir == 8'b01110001; + /* T80_MCode.vhd:300:32 */ + assign n2436_o = n2433_o | n2435_o; + /* T80_MCode.vhd:300:43 */ + assign n2438_o = ir == 8'b01110010; + /* T80_MCode.vhd:300:43 */ + assign n2439_o = n2436_o | n2438_o; + /* T80_MCode.vhd:300:54 */ + assign n2441_o = ir == 8'b01110011; + /* T80_MCode.vhd:300:54 */ + assign n2442_o = n2439_o | n2441_o; + /* T80_MCode.vhd:300:65 */ + assign n2444_o = ir == 8'b01110100; + /* T80_MCode.vhd:300:65 */ + assign n2445_o = n2442_o | n2444_o; + /* T80_MCode.vhd:300:76 */ + assign n2447_o = ir == 8'b01110101; + /* T80_MCode.vhd:300:76 */ + assign n2448_o = n2445_o | n2447_o; + /* T80_MCode.vhd:300:87 */ + assign n2450_o = ir == 8'b01110111; + /* T80_MCode.vhd:300:87 */ + assign n2451_o = n2448_o | n2450_o; + /* T80_MCode.vhd:315:30 */ + assign n2452_o = {28'b0, mcycle}; // uext + /* T80_MCode.vhd:316:25 */ + assign n2455_o = n2452_o == 31'b0000000000000000000000000000010; + /* T80_MCode.vhd:321:25 */ + assign n2457_o = n2452_o == 31'b0000000000000000000000000000011; + assign n2458_o = {n2457_o, n2455_o}; + /* T80_MCode.vhd:315:25 */ + always @* + case (n2458_o) + 2'b10: n2461_o = 1'b0; + 2'b01: n2461_o = 1'b1; + default: n2461_o = 1'b0; + endcase + /* T80_MCode.vhd:315:25 */ + always @* + case (n2458_o) + 2'b10: n2463_o = 3'b000; + 2'b01: n2463_o = n2194_o; + default: n2463_o = 3'b000; + endcase + /* T80_MCode.vhd:315:25 */ + always @* + case (n2458_o) + 2'b10: n2465_o = 1'b0; + 2'b01: n2465_o = 1'b0; + default: n2465_o = 1'b0; + endcase + /* T80_MCode.vhd:315:25 */ + always @* + case (n2458_o) + 2'b10: n2468_o = 3'b111; + 2'b01: n2468_o = 3'b010; + default: n2468_o = 3'b111; + endcase + /* T80_MCode.vhd:315:25 */ + always @* + case (n2458_o) + 2'b10: n2471_o = 1'b1; + 2'b01: n2471_o = 1'b0; + default: n2471_o = 1'b0; + endcase + /* T80_MCode.vhd:312:17 */ + assign n2473_o = ir == 8'b00110110; + /* T80_MCode.vhd:328:30 */ + assign n2474_o = {28'b0, mcycle}; // uext + /* T80_MCode.vhd:329:25 */ + assign n2476_o = n2474_o == 31'b0000000000000000000000000000001; + /* T80_MCode.vhd:331:25 */ + assign n2478_o = n2474_o == 31'b0000000000000000000000000000010; + assign n2479_o = {n2478_o, n2476_o}; + /* T80_MCode.vhd:328:25 */ + always @* + case (n2479_o) + 2'b10: n2482_o = 1'b1; + 2'b01: n2482_o = 1'b0; + default: n2482_o = 1'b0; + endcase + /* T80_MCode.vhd:328:25 */ + always @* + case (n2479_o) + 2'b10: n2485_o = 3'b111; + 2'b01: n2485_o = 3'b000; + default: n2485_o = 3'b111; + endcase + /* T80_MCode.vhd:325:17 */ + assign n2487_o = ir == 8'b00001010; + /* T80_MCode.vhd:338:30 */ + assign n2488_o = {28'b0, mcycle}; // uext + /* T80_MCode.vhd:339:25 */ + assign n2490_o = n2488_o == 31'b0000000000000000000000000000001; + /* T80_MCode.vhd:341:25 */ + assign n2492_o = n2488_o == 31'b0000000000000000000000000000010; + assign n2493_o = {n2492_o, n2490_o}; + /* T80_MCode.vhd:338:25 */ + always @* + case (n2493_o) + 2'b10: n2496_o = 1'b1; + 2'b01: n2496_o = 1'b0; + default: n2496_o = 1'b0; + endcase + /* T80_MCode.vhd:338:25 */ + always @* + case (n2493_o) + 2'b10: n2499_o = 3'b111; + 2'b01: n2499_o = 3'b001; + default: n2499_o = 3'b111; + endcase + /* T80_MCode.vhd:335:17 */ + assign n2501_o = ir == 8'b00011010; + /* T80_MCode.vhd:360:38 */ + assign n2502_o = {28'b0, mcycle}; // uext + /* T80_MCode.vhd:361:33 */ + assign n2504_o = n2502_o == 31'b0000000000000000000000000000010; + /* T80_MCode.vhd:364:33 */ + assign n2506_o = n2502_o == 31'b0000000000000000000000000000011; + /* T80_MCode.vhd:367:33 */ + assign n2508_o = n2502_o == 31'b0000000000000000000000000000100; + assign n2509_o = {n2508_o, n2506_o, n2504_o}; + /* T80_MCode.vhd:360:33 */ + always @* + case (n2509_o) + 3'b100: n2513_o = 1'b0; + 3'b010: n2513_o = 1'b1; + 3'b001: n2513_o = 1'b1; + default: n2513_o = 1'b0; + endcase + /* T80_MCode.vhd:360:33 */ + always @* + case (n2509_o) + 3'b100: n2516_o = 1'b1; + 3'b010: n2516_o = 1'b0; + 3'b001: n2516_o = 1'b0; + default: n2516_o = 1'b0; + endcase + /* T80_MCode.vhd:360:33 */ + always @* + case (n2509_o) + 3'b100: n2519_o = 3'b111; + 3'b010: n2519_o = 3'b110; + 3'b001: n2519_o = 3'b111; + default: n2519_o = 3'b111; + endcase + /* T80_MCode.vhd:360:33 */ + always @* + case (n2509_o) + 3'b100: n2522_o = 1'b0; + 3'b010: n2522_o = 1'b0; + 3'b001: n2522_o = 1'b1; + default: n2522_o = 1'b0; + endcase + /* T80_MCode.vhd:345:17 */ + assign n2524_o = ir == 8'b00111010; + /* T80_MCode.vhd:375:30 */ + assign n2525_o = {28'b0, mcycle}; // uext + /* T80_MCode.vhd:376:25 */ + assign n2527_o = n2525_o == 31'b0000000000000000000000000000001; + /* T80_MCode.vhd:380:25 */ + assign n2529_o = n2525_o == 31'b0000000000000000000000000000010; + assign n2530_o = {n2529_o, n2527_o}; + /* T80_MCode.vhd:375:25 */ + always @* + case (n2530_o) + 2'b10: n2533_o = 4'b0000; + 2'b01: n2533_o = 4'b0111; + default: n2533_o = 4'b0000; + endcase + /* T80_MCode.vhd:375:25 */ + always @* + case (n2530_o) + 2'b10: n2536_o = 3'b111; + 2'b01: n2536_o = 3'b000; + default: n2536_o = 3'b111; + endcase + /* T80_MCode.vhd:375:25 */ + always @* + case (n2530_o) + 2'b10: n2539_o = 2'b00; + 2'b01: n2539_o = 2'b10; + default: n2539_o = 2'b00; + endcase + /* T80_MCode.vhd:375:25 */ + always @* + case (n2530_o) + 2'b10: n2542_o = 1'b1; + 2'b01: n2542_o = 1'b0; + default: n2542_o = 1'b0; + endcase + /* T80_MCode.vhd:372:17 */ + assign n2544_o = ir == 8'b00000010; + /* T80_MCode.vhd:387:30 */ + assign n2545_o = {28'b0, mcycle}; // uext + /* T80_MCode.vhd:388:25 */ + assign n2547_o = n2545_o == 31'b0000000000000000000000000000001; + /* T80_MCode.vhd:392:25 */ + assign n2549_o = n2545_o == 31'b0000000000000000000000000000010; + assign n2550_o = {n2549_o, n2547_o}; + /* T80_MCode.vhd:387:25 */ + always @* + case (n2550_o) + 2'b10: n2553_o = 4'b0000; + 2'b01: n2553_o = 4'b0111; + default: n2553_o = 4'b0000; + endcase + /* T80_MCode.vhd:387:25 */ + always @* + case (n2550_o) + 2'b10: n2556_o = 3'b111; + 2'b01: n2556_o = 3'b001; + default: n2556_o = 3'b111; + endcase + /* T80_MCode.vhd:387:25 */ + always @* + case (n2550_o) + 2'b10: n2559_o = 2'b00; + 2'b01: n2559_o = 2'b10; + default: n2559_o = 2'b00; + endcase + /* T80_MCode.vhd:387:25 */ + always @* + case (n2550_o) + 2'b10: n2562_o = 1'b1; + 2'b01: n2562_o = 1'b0; + default: n2562_o = 1'b0; + endcase + /* T80_MCode.vhd:384:17 */ + assign n2564_o = ir == 8'b00010010; + /* T80_MCode.vhd:412:38 */ + assign n2565_o = {28'b0, mcycle}; // uext + /* T80_MCode.vhd:413:33 */ + assign n2567_o = n2565_o == 31'b0000000000000000000000000000010; + /* T80_MCode.vhd:416:33 */ + assign n2569_o = n2565_o == 31'b0000000000000000000000000000011; + /* T80_MCode.vhd:421:33 */ + assign n2571_o = n2565_o == 31'b0000000000000000000000000000100; + assign n2572_o = {n2571_o, n2569_o, n2567_o}; + /* T80_MCode.vhd:412:33 */ + always @* + case (n2572_o) + 3'b100: n2576_o = 1'b0; + 3'b010: n2576_o = 1'b1; + 3'b001: n2576_o = 1'b1; + default: n2576_o = 1'b0; + endcase + /* T80_MCode.vhd:412:33 */ + always @* + case (n2572_o) + 3'b100: n2579_o = 4'b0000; + 3'b010: n2579_o = 4'b0111; + 3'b001: n2579_o = 4'b0000; + default: n2579_o = 4'b0000; + endcase + /* T80_MCode.vhd:412:33 */ + always @* + case (n2572_o) + 3'b100: n2582_o = 3'b111; + 3'b010: n2582_o = 3'b110; + 3'b001: n2582_o = 3'b111; + default: n2582_o = 3'b111; + endcase + /* T80_MCode.vhd:412:33 */ + always @* + case (n2572_o) + 3'b100: n2585_o = 1'b0; + 3'b010: n2585_o = 1'b0; + 3'b001: n2585_o = 1'b1; + default: n2585_o = 1'b0; + endcase + /* T80_MCode.vhd:412:33 */ + always @* + case (n2572_o) + 3'b100: n2588_o = 2'b00; + 3'b010: n2588_o = 2'b10; + 3'b001: n2588_o = 2'b00; + default: n2588_o = 2'b00; + endcase + /* T80_MCode.vhd:412:33 */ + always @* + case (n2572_o) + 3'b100: n2591_o = 1'b1; + 3'b010: n2591_o = 1'b0; + 3'b001: n2591_o = 1'b0; + default: n2591_o = 1'b0; + endcase + /* T80_MCode.vhd:396:17 */ + assign n2593_o = ir == 8'b00110010; + /* T80_MCode.vhd:431:30 */ + assign n2594_o = {28'b0, mcycle}; // uext + /* T80_MCode.vhd:435:42 */ + assign n2596_o = n2195_o == 2'b11; + assign n2598_o = {n2195_o, 1'b1}; + /* T80_MCode.vhd:435:33 */ + assign n2600_o = n2596_o ? 3'b000 : n2598_o; + /* T80_MCode.vhd:435:33 */ + assign n2603_o = n2596_o ? 1'b1 : 1'b0; + /* T80_MCode.vhd:432:25 */ + assign n2605_o = n2594_o == 31'b0000000000000000000000000000010; + /* T80_MCode.vhd:444:42 */ + assign n2607_o = n2195_o == 2'b11; + assign n2609_o = {n2195_o, 1'b0}; + /* T80_MCode.vhd:444:33 */ + assign n2611_o = n2607_o ? 3'b001 : n2609_o; + /* T80_MCode.vhd:444:33 */ + assign n2614_o = n2607_o ? 1'b1 : 1'b0; + /* T80_MCode.vhd:441:25 */ + assign n2616_o = n2594_o == 31'b0000000000000000000000000000011; + assign n2617_o = {n2616_o, n2605_o}; + /* T80_MCode.vhd:431:25 */ + always @* + case (n2617_o) + 2'b10: n2621_o = 1'b1; + 2'b01: n2621_o = 1'b1; + default: n2621_o = 1'b0; + endcase + /* T80_MCode.vhd:431:25 */ + always @* + case (n2617_o) + 2'b10: n2625_o = 1'b1; + 2'b01: n2625_o = 1'b1; + default: n2625_o = 1'b0; + endcase + /* T80_MCode.vhd:431:25 */ + always @* + case (n2617_o) + 2'b10: n2627_o = n2611_o; + 2'b01: n2627_o = n2600_o; + default: n2627_o = 3'b000; + endcase + /* T80_MCode.vhd:431:25 */ + always @* + case (n2617_o) + 2'b10: n2629_o = n2614_o; + 2'b01: n2629_o = n2603_o; + default: n2629_o = 1'b0; + endcase + /* T80_MCode.vhd:428:17 */ + assign n2631_o = ir == 8'b00000001; + /* T80_MCode.vhd:428:32 */ + assign n2633_o = ir == 8'b00010001; + /* T80_MCode.vhd:428:32 */ + assign n2634_o = n2631_o | n2633_o; + /* T80_MCode.vhd:428:43 */ + assign n2636_o = ir == 8'b00100001; + /* T80_MCode.vhd:428:43 */ + assign n2637_o = n2634_o | n2636_o; + /* T80_MCode.vhd:428:54 */ + assign n2639_o = ir == 8'b00110001; + /* T80_MCode.vhd:428:54 */ + assign n2640_o = n2637_o | n2639_o; + /* T80_MCode.vhd:467:38 */ + assign n2641_o = {28'b0, mcycle}; // uext + /* T80_MCode.vhd:468:33 */ + assign n2643_o = n2641_o == 31'b0000000000000000000000000000010; + /* T80_MCode.vhd:471:33 */ + assign n2645_o = n2641_o == 31'b0000000000000000000000000000011; + /* T80_MCode.vhd:475:33 */ + assign n2648_o = n2641_o == 31'b0000000000000000000000000000100; + /* T80_MCode.vhd:480:33 */ + assign n2651_o = n2641_o == 31'b0000000000000000000000000000101; + assign n2652_o = {n2651_o, n2648_o, n2645_o, n2643_o}; + /* T80_MCode.vhd:467:33 */ + always @* + case (n2652_o) + 4'b1000: n2656_o = 1'b0; + 4'b0100: n2656_o = 1'b0; + 4'b0010: n2656_o = 1'b1; + 4'b0001: n2656_o = 1'b1; + default: n2656_o = 1'b0; + endcase + /* T80_MCode.vhd:467:33 */ + always @* + case (n2652_o) + 4'b1000: n2659_o = 1'b0; + 4'b0100: n2659_o = 1'b1; + 4'b0010: n2659_o = 1'b0; + 4'b0001: n2659_o = 1'b0; + default: n2659_o = 1'b0; + endcase + /* T80_MCode.vhd:467:33 */ + always @* + case (n2652_o) + 4'b1000: n2663_o = 1'b1; + 4'b0100: n2663_o = 1'b1; + 4'b0010: n2663_o = 1'b0; + 4'b0001: n2663_o = 1'b0; + default: n2663_o = 1'b0; + endcase + /* T80_MCode.vhd:467:33 */ + always @* + case (n2652_o) + 4'b1000: n2665_o = 3'b100; + 4'b0100: n2665_o = 3'b101; + 4'b0010: n2665_o = 3'b000; + 4'b0001: n2665_o = 3'b000; + default: n2665_o = 3'b000; + endcase + /* T80_MCode.vhd:467:33 */ + always @* + case (n2652_o) + 4'b1000: n2669_o = 3'b111; + 4'b0100: n2669_o = 3'b110; + 4'b0010: n2669_o = 3'b110; + 4'b0001: n2669_o = 3'b111; + default: n2669_o = 3'b111; + endcase + /* T80_MCode.vhd:467:33 */ + always @* + case (n2652_o) + 4'b1000: n2672_o = 1'b0; + 4'b0100: n2672_o = 1'b0; + 4'b0010: n2672_o = 1'b0; + 4'b0001: n2672_o = 1'b1; + default: n2672_o = 1'b0; + endcase + /* T80_MCode.vhd:467:33 */ + always @* + case (n2652_o) + 4'b1000: n2675_o = 1'b0; + 4'b0100: n2675_o = 1'b0; + 4'b0010: n2675_o = 1'b1; + 4'b0001: n2675_o = 1'b0; + default: n2675_o = 1'b0; + endcase + /* T80_MCode.vhd:452:17 */ + assign n2677_o = ir == 8'b00101010; + /* T80_MCode.vhd:502:38 */ + assign n2678_o = {28'b0, mcycle}; // uext + /* T80_MCode.vhd:503:33 */ + assign n2680_o = n2678_o == 31'b0000000000000000000000000000010; + /* T80_MCode.vhd:506:33 */ + assign n2682_o = n2678_o == 31'b0000000000000000000000000000011; + /* T80_MCode.vhd:511:33 */ + assign n2684_o = n2678_o == 31'b0000000000000000000000000000100; + /* T80_MCode.vhd:516:33 */ + assign n2686_o = n2678_o == 31'b0000000000000000000000000000101; + assign n2687_o = {n2686_o, n2684_o, n2682_o, n2680_o}; + /* T80_MCode.vhd:502:33 */ + always @* + case (n2687_o) + 4'b1000: n2691_o = 1'b0; + 4'b0100: n2691_o = 1'b0; + 4'b0010: n2691_o = 1'b1; + 4'b0001: n2691_o = 1'b1; + default: n2691_o = 1'b0; + endcase + /* T80_MCode.vhd:502:33 */ + always @* + case (n2687_o) + 4'b1000: n2694_o = 1'b0; + 4'b0100: n2694_o = 1'b1; + 4'b0010: n2694_o = 1'b0; + 4'b0001: n2694_o = 1'b0; + default: n2694_o = 1'b0; + endcase + /* T80_MCode.vhd:502:33 */ + always @* + case (n2687_o) + 4'b1000: n2698_o = 4'b0000; + 4'b0100: n2698_o = 4'b0100; + 4'b0010: n2698_o = 4'b0101; + 4'b0001: n2698_o = 4'b0000; + default: n2698_o = 4'b0000; + endcase + /* T80_MCode.vhd:502:33 */ + always @* + case (n2687_o) + 4'b1000: n2702_o = 3'b111; + 4'b0100: n2702_o = 3'b110; + 4'b0010: n2702_o = 3'b110; + 4'b0001: n2702_o = 3'b111; + default: n2702_o = 3'b111; + endcase + /* T80_MCode.vhd:502:33 */ + always @* + case (n2687_o) + 4'b1000: n2705_o = 1'b0; + 4'b0100: n2705_o = 1'b0; + 4'b0010: n2705_o = 1'b0; + 4'b0001: n2705_o = 1'b1; + default: n2705_o = 1'b0; + endcase + /* T80_MCode.vhd:502:33 */ + always @* + case (n2687_o) + 4'b1000: n2708_o = 1'b0; + 4'b0100: n2708_o = 1'b0; + 4'b0010: n2708_o = 1'b1; + 4'b0001: n2708_o = 1'b0; + default: n2708_o = 1'b0; + endcase + /* T80_MCode.vhd:502:33 */ + always @* + case (n2687_o) + 4'b1000: n2712_o = 1'b1; + 4'b0100: n2712_o = 1'b1; + 4'b0010: n2712_o = 1'b0; + 4'b0001: n2712_o = 1'b0; + default: n2712_o = 1'b0; + endcase + /* T80_MCode.vhd:486:17 */ + assign n2714_o = ir == 8'b00100010; + /* T80_MCode.vhd:521:17 */ + assign n2716_o = ir == 8'b11111001; + /* T80_MCode.vhd:528:30 */ + assign n2717_o = {28'b0, mcycle}; // uext + /* T80_MCode.vhd:533:42 */ + assign n2719_o = n2195_o == 2'b11; + assign n2722_o = {1'b0, n2195_o, 1'b0}; + /* T80_MCode.vhd:533:33 */ + assign n2724_o = n2719_o ? 4'b0111 : n2722_o; + /* T80_MCode.vhd:529:25 */ + assign n2726_o = n2717_o == 31'b0000000000000000000000000000001; + /* T80_MCode.vhd:543:42 */ + assign n2728_o = n2195_o == 2'b11; + assign n2731_o = {1'b0, n2195_o, 1'b1}; + /* T80_MCode.vhd:543:33 */ + assign n2733_o = n2728_o ? 4'b1011 : n2731_o; + /* T80_MCode.vhd:540:25 */ + assign n2735_o = n2717_o == 31'b0000000000000000000000000000010; + /* T80_MCode.vhd:551:25 */ + assign n2737_o = n2717_o == 31'b0000000000000000000000000000011; + assign n2738_o = {n2737_o, n2735_o, n2726_o}; + /* T80_MCode.vhd:528:25 */ + always @* + case (n2738_o) + 3'b100: n2740_o = n2200_o; + 3'b010: n2740_o = n2200_o; + 3'b001: n2740_o = 3'b101; + default: n2740_o = n2200_o; + endcase + /* T80_MCode.vhd:528:25 */ + always @* + case (n2738_o) + 3'b100: n2744_o = 4'b0000; + 3'b010: n2744_o = 4'b1111; + 3'b001: n2744_o = 4'b1111; + default: n2744_o = 4'b0000; + endcase + /* T80_MCode.vhd:528:25 */ + always @* + case (n2738_o) + 3'b100: n2746_o = 4'b0000; + 3'b010: n2746_o = n2733_o; + 3'b001: n2746_o = n2724_o; + default: n2746_o = 4'b0000; + endcase + /* T80_MCode.vhd:528:25 */ + always @* + case (n2738_o) + 3'b100: n2750_o = 3'b111; + 3'b010: n2750_o = 3'b101; + 3'b001: n2750_o = 3'b101; + default: n2750_o = 3'b111; + endcase + /* T80_MCode.vhd:528:25 */ + always @* + case (n2738_o) + 3'b100: n2754_o = 1'b1; + 3'b010: n2754_o = 1'b1; + 3'b001: n2754_o = 1'b0; + default: n2754_o = 1'b0; + endcase + /* T80_MCode.vhd:525:17 */ + assign n2756_o = ir == 8'b11000101; + /* T80_MCode.vhd:525:32 */ + assign n2758_o = ir == 8'b11010101; + /* T80_MCode.vhd:525:32 */ + assign n2759_o = n2756_o | n2758_o; + /* T80_MCode.vhd:525:43 */ + assign n2761_o = ir == 8'b11100101; + /* T80_MCode.vhd:525:43 */ + assign n2762_o = n2759_o | n2761_o; + /* T80_MCode.vhd:525:54 */ + assign n2764_o = ir == 8'b11110101; + /* T80_MCode.vhd:525:54 */ + assign n2765_o = n2762_o | n2764_o; + /* T80_MCode.vhd:558:30 */ + assign n2766_o = {28'b0, mcycle}; // uext + /* T80_MCode.vhd:559:25 */ + assign n2768_o = n2766_o == 31'b0000000000000000000000000000001; + /* T80_MCode.vhd:565:42 */ + assign n2770_o = n2195_o == 2'b11; + assign n2772_o = {n2195_o, 1'b1}; + /* T80_MCode.vhd:565:33 */ + assign n2774_o = n2770_o ? 3'b011 : n2772_o; + /* T80_MCode.vhd:565:33 */ + assign n2777_o = n2770_o ? 1'b1 : 1'b0; + /* T80_MCode.vhd:561:25 */ + assign n2779_o = n2766_o == 31'b0000000000000000000000000000010; + /* T80_MCode.vhd:574:42 */ + assign n2781_o = n2195_o == 2'b11; + assign n2783_o = {n2195_o, 1'b0}; + /* T80_MCode.vhd:574:33 */ + assign n2785_o = n2781_o ? 3'b111 : n2783_o; + /* T80_MCode.vhd:574:33 */ + assign n2788_o = n2781_o ? 1'b0 : 1'b0; + /* T80_MCode.vhd:571:25 */ + assign n2790_o = n2766_o == 31'b0000000000000000000000000000011; + assign n2791_o = {n2790_o, n2779_o, n2768_o}; + /* T80_MCode.vhd:558:25 */ + always @* + case (n2791_o) + 3'b100: n2795_o = 4'b0111; + 3'b010: n2795_o = 4'b0111; + 3'b001: n2795_o = 4'b0000; + default: n2795_o = 4'b0000; + endcase + /* T80_MCode.vhd:558:25 */ + always @* + case (n2791_o) + 3'b100: n2799_o = 1'b1; + 3'b010: n2799_o = 1'b1; + 3'b001: n2799_o = 1'b0; + default: n2799_o = 1'b0; + endcase + /* T80_MCode.vhd:558:25 */ + always @* + case (n2791_o) + 3'b100: n2801_o = n2785_o; + 3'b010: n2801_o = n2774_o; + 3'b001: n2801_o = 3'b000; + default: n2801_o = 3'b000; + endcase + /* T80_MCode.vhd:558:25 */ + always @* + case (n2791_o) + 3'b100: n2803_o = n2788_o; + 3'b010: n2803_o = n2777_o; + 3'b001: n2803_o = 1'b0; + default: n2803_o = 1'b0; + endcase + /* T80_MCode.vhd:558:25 */ + always @* + case (n2791_o) + 3'b100: n2807_o = 3'b111; + 3'b010: n2807_o = 3'b101; + 3'b001: n2807_o = 3'b101; + default: n2807_o = 3'b111; + endcase + /* T80_MCode.vhd:555:17 */ + assign n2809_o = ir == 8'b11000001; + /* T80_MCode.vhd:555:32 */ + assign n2811_o = ir == 8'b11010001; + /* T80_MCode.vhd:555:32 */ + assign n2812_o = n2809_o | n2811_o; + /* T80_MCode.vhd:555:43 */ + assign n2814_o = ir == 8'b11100001; + /* T80_MCode.vhd:555:43 */ + assign n2815_o = n2812_o | n2814_o; + /* T80_MCode.vhd:555:54 */ + assign n2817_o = ir == 8'b11110001; + /* T80_MCode.vhd:555:54 */ + assign n2818_o = n2815_o | n2817_o; + /* T80_MCode.vhd:584:17 */ + assign n2820_o = ir == 8'b11101011; + /* T80_MCode.vhd:589:17 */ + assign n2822_o = ir == 8'b00001000; + /* T80_MCode.vhd:615:17 */ + assign n2824_o = ir == 8'b11011001; + /* T80_MCode.vhd:641:38 */ + assign n2825_o = {28'b0, mcycle}; // uext + /* T80_MCode.vhd:642:33 */ + assign n2827_o = n2825_o == 31'b0000000000000000000000000000001; + /* T80_MCode.vhd:644:33 */ + assign n2829_o = n2825_o == 31'b0000000000000000000000000000010; + /* T80_MCode.vhd:650:33 */ + assign n2831_o = n2825_o == 31'b0000000000000000000000000000011; + /* T80_MCode.vhd:655:33 */ + assign n2833_o = n2825_o == 31'b0000000000000000000000000000100; + /* T80_MCode.vhd:661:33 */ + assign n2835_o = n2825_o == 31'b0000000000000000000000000000101; + assign n2836_o = {n2835_o, n2833_o, n2831_o, n2829_o, n2827_o}; + /* T80_MCode.vhd:641:33 */ + always @* + case (n2836_o) + 5'b10000: n2839_o = 3'b101; + 5'b01000: n2839_o = n2200_o; + 5'b00100: n2839_o = 3'b100; + 5'b00010: n2839_o = n2200_o; + 5'b00001: n2839_o = n2200_o; + default: n2839_o = n2200_o; + endcase + /* T80_MCode.vhd:641:33 */ + always @* + case (n2836_o) + 5'b10000: n2843_o = 4'b1111; + 5'b01000: n2843_o = 4'b0000; + 5'b00100: n2843_o = 4'b0111; + 5'b00010: n2843_o = 4'b0000; + 5'b00001: n2843_o = 4'b0000; + default: n2843_o = 4'b0000; + endcase + /* T80_MCode.vhd:641:33 */ + always @* + case (n2836_o) + 5'b10000: n2847_o = 1'b0; + 5'b01000: n2847_o = 1'b1; + 5'b00100: n2847_o = 1'b0; + 5'b00010: n2847_o = 1'b1; + 5'b00001: n2847_o = 1'b0; + default: n2847_o = 1'b0; + endcase + /* T80_MCode.vhd:641:33 */ + always @* + case (n2836_o) + 5'b10000: n2851_o = 4'b0000; + 5'b01000: n2851_o = 4'b0100; + 5'b00100: n2851_o = 4'b0000; + 5'b00010: n2851_o = 4'b0101; + 5'b00001: n2851_o = 4'b0000; + default: n2851_o = 4'b0000; + endcase + /* T80_MCode.vhd:641:33 */ + always @* + case (n2836_o) + 5'b10000: n2855_o = 4'b0000; + 5'b01000: n2855_o = 4'b0100; + 5'b00100: n2855_o = 4'b0000; + 5'b00010: n2855_o = 4'b0101; + 5'b00001: n2855_o = 4'b0000; + default: n2855_o = 4'b0000; + endcase + /* T80_MCode.vhd:641:33 */ + always @* + case (n2836_o) + 5'b10000: n2861_o = 3'b111; + 5'b01000: n2861_o = 3'b101; + 5'b00100: n2861_o = 3'b101; + 5'b00010: n2861_o = 3'b101; + 5'b00001: n2861_o = 3'b101; + default: n2861_o = 3'b111; + endcase + /* T80_MCode.vhd:641:33 */ + always @* + case (n2836_o) + 5'b10000: n2864_o = 1'b0; + 5'b01000: n2864_o = 1'b0; + 5'b00100: n2864_o = 1'b0; + 5'b00010: n2864_o = 1'b1; + 5'b00001: n2864_o = 1'b0; + default: n2864_o = 1'b0; + endcase + /* T80_MCode.vhd:641:33 */ + always @* + case (n2836_o) + 5'b10000: n2867_o = 1'b0; + 5'b01000: n2867_o = 1'b1; + 5'b00100: n2867_o = 1'b0; + 5'b00010: n2867_o = 1'b0; + 5'b00001: n2867_o = 1'b0; + default: n2867_o = 1'b0; + endcase + /* T80_MCode.vhd:641:33 */ + always @* + case (n2836_o) + 5'b10000: n2871_o = 1'b1; + 5'b01000: n2871_o = 1'b0; + 5'b00100: n2871_o = 1'b1; + 5'b00010: n2871_o = 1'b0; + 5'b00001: n2871_o = 1'b0; + default: n2871_o = 1'b0; + endcase + /* T80_MCode.vhd:637:17 */ + assign n2873_o = ir == 8'b11100011; + /* T80_MCode.vhd:670:17 */ + assign n2876_o = ir == 8'b10000000; + /* T80_MCode.vhd:670:32 */ + assign n2878_o = ir == 8'b10000001; + /* T80_MCode.vhd:670:32 */ + assign n2879_o = n2876_o | n2878_o; + /* T80_MCode.vhd:670:43 */ + assign n2881_o = ir == 8'b10000010; + /* T80_MCode.vhd:670:43 */ + assign n2882_o = n2879_o | n2881_o; + /* T80_MCode.vhd:670:54 */ + assign n2884_o = ir == 8'b10000011; + /* T80_MCode.vhd:670:54 */ + assign n2885_o = n2882_o | n2884_o; + /* T80_MCode.vhd:670:65 */ + assign n2887_o = ir == 8'b10000100; + /* T80_MCode.vhd:670:65 */ + assign n2888_o = n2885_o | n2887_o; + /* T80_MCode.vhd:670:76 */ + assign n2890_o = ir == 8'b10000101; + /* T80_MCode.vhd:670:76 */ + assign n2891_o = n2888_o | n2890_o; + /* T80_MCode.vhd:670:87 */ + assign n2893_o = ir == 8'b10000111; + /* T80_MCode.vhd:670:87 */ + assign n2894_o = n2891_o | n2893_o; + /* T80_MCode.vhd:671:25 */ + assign n2896_o = ir == 8'b10001000; + /* T80_MCode.vhd:671:25 */ + assign n2897_o = n2894_o | n2896_o; + /* T80_MCode.vhd:671:36 */ + assign n2899_o = ir == 8'b10001001; + /* T80_MCode.vhd:671:36 */ + assign n2900_o = n2897_o | n2899_o; + /* T80_MCode.vhd:671:47 */ + assign n2902_o = ir == 8'b10001010; + /* T80_MCode.vhd:671:47 */ + assign n2903_o = n2900_o | n2902_o; + /* T80_MCode.vhd:671:58 */ + assign n2905_o = ir == 8'b10001011; + /* T80_MCode.vhd:671:58 */ + assign n2906_o = n2903_o | n2905_o; + /* T80_MCode.vhd:671:69 */ + assign n2908_o = ir == 8'b10001100; + /* T80_MCode.vhd:671:69 */ + assign n2909_o = n2906_o | n2908_o; + /* T80_MCode.vhd:671:80 */ + assign n2911_o = ir == 8'b10001101; + /* T80_MCode.vhd:671:80 */ + assign n2912_o = n2909_o | n2911_o; + /* T80_MCode.vhd:671:91 */ + assign n2914_o = ir == 8'b10001111; + /* T80_MCode.vhd:671:91 */ + assign n2915_o = n2912_o | n2914_o; + /* T80_MCode.vhd:672:25 */ + assign n2917_o = ir == 8'b10010000; + /* T80_MCode.vhd:672:25 */ + assign n2918_o = n2915_o | n2917_o; + /* T80_MCode.vhd:672:36 */ + assign n2920_o = ir == 8'b10010001; + /* T80_MCode.vhd:672:36 */ + assign n2921_o = n2918_o | n2920_o; + /* T80_MCode.vhd:672:47 */ + assign n2923_o = ir == 8'b10010010; + /* T80_MCode.vhd:672:47 */ + assign n2924_o = n2921_o | n2923_o; + /* T80_MCode.vhd:672:58 */ + assign n2926_o = ir == 8'b10010011; + /* T80_MCode.vhd:672:58 */ + assign n2927_o = n2924_o | n2926_o; + /* T80_MCode.vhd:672:69 */ + assign n2929_o = ir == 8'b10010100; + /* T80_MCode.vhd:672:69 */ + assign n2930_o = n2927_o | n2929_o; + /* T80_MCode.vhd:672:80 */ + assign n2932_o = ir == 8'b10010101; + /* T80_MCode.vhd:672:80 */ + assign n2933_o = n2930_o | n2932_o; + /* T80_MCode.vhd:672:91 */ + assign n2935_o = ir == 8'b10010111; + /* T80_MCode.vhd:672:91 */ + assign n2936_o = n2933_o | n2935_o; + /* T80_MCode.vhd:673:25 */ + assign n2938_o = ir == 8'b10011000; + /* T80_MCode.vhd:673:25 */ + assign n2939_o = n2936_o | n2938_o; + /* T80_MCode.vhd:673:36 */ + assign n2941_o = ir == 8'b10011001; + /* T80_MCode.vhd:673:36 */ + assign n2942_o = n2939_o | n2941_o; + /* T80_MCode.vhd:673:47 */ + assign n2944_o = ir == 8'b10011010; + /* T80_MCode.vhd:673:47 */ + assign n2945_o = n2942_o | n2944_o; + /* T80_MCode.vhd:673:58 */ + assign n2947_o = ir == 8'b10011011; + /* T80_MCode.vhd:673:58 */ + assign n2948_o = n2945_o | n2947_o; + /* T80_MCode.vhd:673:69 */ + assign n2950_o = ir == 8'b10011100; + /* T80_MCode.vhd:673:69 */ + assign n2951_o = n2948_o | n2950_o; + /* T80_MCode.vhd:673:80 */ + assign n2953_o = ir == 8'b10011101; + /* T80_MCode.vhd:673:80 */ + assign n2954_o = n2951_o | n2953_o; + /* T80_MCode.vhd:673:91 */ + assign n2956_o = ir == 8'b10011111; + /* T80_MCode.vhd:673:91 */ + assign n2957_o = n2954_o | n2956_o; + /* T80_MCode.vhd:674:25 */ + assign n2959_o = ir == 8'b10100000; + /* T80_MCode.vhd:674:25 */ + assign n2960_o = n2957_o | n2959_o; + /* T80_MCode.vhd:674:36 */ + assign n2962_o = ir == 8'b10100001; + /* T80_MCode.vhd:674:36 */ + assign n2963_o = n2960_o | n2962_o; + /* T80_MCode.vhd:674:47 */ + assign n2965_o = ir == 8'b10100010; + /* T80_MCode.vhd:674:47 */ + assign n2966_o = n2963_o | n2965_o; + /* T80_MCode.vhd:674:58 */ + assign n2968_o = ir == 8'b10100011; + /* T80_MCode.vhd:674:58 */ + assign n2969_o = n2966_o | n2968_o; + /* T80_MCode.vhd:674:69 */ + assign n2971_o = ir == 8'b10100100; + /* T80_MCode.vhd:674:69 */ + assign n2972_o = n2969_o | n2971_o; + /* T80_MCode.vhd:674:80 */ + assign n2974_o = ir == 8'b10100101; + /* T80_MCode.vhd:674:80 */ + assign n2975_o = n2972_o | n2974_o; + /* T80_MCode.vhd:674:91 */ + assign n2977_o = ir == 8'b10100111; + /* T80_MCode.vhd:674:91 */ + assign n2978_o = n2975_o | n2977_o; + /* T80_MCode.vhd:675:25 */ + assign n2980_o = ir == 8'b10101000; + /* T80_MCode.vhd:675:25 */ + assign n2981_o = n2978_o | n2980_o; + /* T80_MCode.vhd:675:36 */ + assign n2983_o = ir == 8'b10101001; + /* T80_MCode.vhd:675:36 */ + assign n2984_o = n2981_o | n2983_o; + /* T80_MCode.vhd:675:47 */ + assign n2986_o = ir == 8'b10101010; + /* T80_MCode.vhd:675:47 */ + assign n2987_o = n2984_o | n2986_o; + /* T80_MCode.vhd:675:58 */ + assign n2989_o = ir == 8'b10101011; + /* T80_MCode.vhd:675:58 */ + assign n2990_o = n2987_o | n2989_o; + /* T80_MCode.vhd:675:69 */ + assign n2992_o = ir == 8'b10101100; + /* T80_MCode.vhd:675:69 */ + assign n2993_o = n2990_o | n2992_o; + /* T80_MCode.vhd:675:80 */ + assign n2995_o = ir == 8'b10101101; + /* T80_MCode.vhd:675:80 */ + assign n2996_o = n2993_o | n2995_o; + /* T80_MCode.vhd:675:91 */ + assign n2998_o = ir == 8'b10101111; + /* T80_MCode.vhd:675:91 */ + assign n2999_o = n2996_o | n2998_o; + /* T80_MCode.vhd:676:25 */ + assign n3001_o = ir == 8'b10110000; + /* T80_MCode.vhd:676:25 */ + assign n3002_o = n2999_o | n3001_o; + /* T80_MCode.vhd:676:36 */ + assign n3004_o = ir == 8'b10110001; + /* T80_MCode.vhd:676:36 */ + assign n3005_o = n3002_o | n3004_o; + /* T80_MCode.vhd:676:47 */ + assign n3007_o = ir == 8'b10110010; + /* T80_MCode.vhd:676:47 */ + assign n3008_o = n3005_o | n3007_o; + /* T80_MCode.vhd:676:58 */ + assign n3010_o = ir == 8'b10110011; + /* T80_MCode.vhd:676:58 */ + assign n3011_o = n3008_o | n3010_o; + /* T80_MCode.vhd:676:69 */ + assign n3013_o = ir == 8'b10110100; + /* T80_MCode.vhd:676:69 */ + assign n3014_o = n3011_o | n3013_o; + /* T80_MCode.vhd:676:80 */ + assign n3016_o = ir == 8'b10110101; + /* T80_MCode.vhd:676:80 */ + assign n3017_o = n3014_o | n3016_o; + /* T80_MCode.vhd:676:91 */ + assign n3019_o = ir == 8'b10110111; + /* T80_MCode.vhd:676:91 */ + assign n3020_o = n3017_o | n3019_o; + /* T80_MCode.vhd:677:25 */ + assign n3022_o = ir == 8'b10111000; + /* T80_MCode.vhd:677:25 */ + assign n3023_o = n3020_o | n3022_o; + /* T80_MCode.vhd:677:36 */ + assign n3025_o = ir == 8'b10111001; + /* T80_MCode.vhd:677:36 */ + assign n3026_o = n3023_o | n3025_o; + /* T80_MCode.vhd:677:47 */ + assign n3028_o = ir == 8'b10111010; + /* T80_MCode.vhd:677:47 */ + assign n3029_o = n3026_o | n3028_o; + /* T80_MCode.vhd:677:58 */ + assign n3031_o = ir == 8'b10111011; + /* T80_MCode.vhd:677:58 */ + assign n3032_o = n3029_o | n3031_o; + /* T80_MCode.vhd:677:69 */ + assign n3034_o = ir == 8'b10111100; + /* T80_MCode.vhd:677:69 */ + assign n3035_o = n3032_o | n3034_o; + /* T80_MCode.vhd:677:80 */ + assign n3037_o = ir == 8'b10111101; + /* T80_MCode.vhd:677:80 */ + assign n3038_o = n3035_o | n3037_o; + /* T80_MCode.vhd:677:91 */ + assign n3040_o = ir == 8'b10111111; + /* T80_MCode.vhd:677:91 */ + assign n3041_o = n3038_o | n3040_o; + /* T80_MCode.vhd:700:30 */ + assign n3042_o = {28'b0, mcycle}; // uext + /* T80_MCode.vhd:701:25 */ + assign n3044_o = n3042_o == 31'b0000000000000000000000000000001; + /* T80_MCode.vhd:703:25 */ + assign n3047_o = n3042_o == 31'b0000000000000000000000000000010; + assign n3048_o = {n3047_o, n3044_o}; + /* T80_MCode.vhd:700:25 */ + always @* + case (n3048_o) + 2'b10: n3051_o = 1'b1; + 2'b01: n3051_o = 1'b0; + default: n3051_o = 1'b0; + endcase + /* T80_MCode.vhd:700:25 */ + always @* + case (n3048_o) + 2'b10: n3053_o = 3'b111; + 2'b01: n3053_o = 3'b000; + default: n3053_o = 3'b000; + endcase + /* T80_MCode.vhd:700:25 */ + always @* + case (n3048_o) + 2'b10: n3055_o = n2194_o; + 2'b01: n3055_o = 3'b000; + default: n3055_o = 3'b000; + endcase + /* T80_MCode.vhd:700:25 */ + always @* + case (n3048_o) + 2'b10: n3058_o = 1'b1; + 2'b01: n3058_o = 1'b0; + default: n3058_o = 1'b0; + endcase + /* T80_MCode.vhd:700:25 */ + always @* + case (n3048_o) + 2'b10: n3061_o = 3'b111; + 2'b01: n3061_o = 3'b010; + default: n3061_o = 3'b111; + endcase + /* T80_MCode.vhd:690:17 */ + assign n3063_o = ir == 8'b10000110; + /* T80_MCode.vhd:690:32 */ + assign n3065_o = ir == 8'b10001110; + /* T80_MCode.vhd:690:32 */ + assign n3066_o = n3063_o | n3065_o; + /* T80_MCode.vhd:690:43 */ + assign n3068_o = ir == 8'b10010110; + /* T80_MCode.vhd:690:43 */ + assign n3069_o = n3066_o | n3068_o; + /* T80_MCode.vhd:690:54 */ + assign n3071_o = ir == 8'b10011110; + /* T80_MCode.vhd:690:54 */ + assign n3072_o = n3069_o | n3071_o; + /* T80_MCode.vhd:690:65 */ + assign n3074_o = ir == 8'b10100110; + /* T80_MCode.vhd:690:65 */ + assign n3075_o = n3072_o | n3074_o; + /* T80_MCode.vhd:690:76 */ + assign n3077_o = ir == 8'b10101110; + /* T80_MCode.vhd:690:76 */ + assign n3078_o = n3075_o | n3077_o; + /* T80_MCode.vhd:690:87 */ + assign n3080_o = ir == 8'b10110110; + /* T80_MCode.vhd:690:87 */ + assign n3081_o = n3078_o | n3080_o; + /* T80_MCode.vhd:690:98 */ + assign n3083_o = ir == 8'b10111110; + /* T80_MCode.vhd:690:98 */ + assign n3084_o = n3081_o | n3083_o; + /* T80_MCode.vhd:720:35 */ + assign n3086_o = mcycle == 3'b010; + /* T80_MCode.vhd:720:25 */ + assign n3090_o = n3086_o ? 1'b1 : 1'b0; + /* T80_MCode.vhd:720:25 */ + assign n3093_o = n3086_o ? 1'b1 : 1'b0; + /* T80_MCode.vhd:720:25 */ + assign n3095_o = n3086_o ? 3'b111 : 3'b000; + /* T80_MCode.vhd:720:25 */ + assign n3097_o = n3086_o ? n2194_o : 3'b000; + /* T80_MCode.vhd:720:25 */ + assign n3100_o = n3086_o ? 1'b1 : 1'b0; + /* T80_MCode.vhd:710:17 */ + assign n3102_o = ir == 8'b11000110; + /* T80_MCode.vhd:710:32 */ + assign n3104_o = ir == 8'b11001110; + /* T80_MCode.vhd:710:32 */ + assign n3105_o = n3102_o | n3104_o; + /* T80_MCode.vhd:710:43 */ + assign n3107_o = ir == 8'b11010110; + /* T80_MCode.vhd:710:43 */ + assign n3108_o = n3105_o | n3107_o; + /* T80_MCode.vhd:710:54 */ + assign n3110_o = ir == 8'b11011110; + /* T80_MCode.vhd:710:54 */ + assign n3111_o = n3108_o | n3110_o; + /* T80_MCode.vhd:710:65 */ + assign n3113_o = ir == 8'b11100110; + /* T80_MCode.vhd:710:65 */ + assign n3114_o = n3111_o | n3113_o; + /* T80_MCode.vhd:710:76 */ + assign n3116_o = ir == 8'b11101110; + /* T80_MCode.vhd:710:76 */ + assign n3117_o = n3114_o | n3116_o; + /* T80_MCode.vhd:710:87 */ + assign n3119_o = ir == 8'b11110110; + /* T80_MCode.vhd:710:87 */ + assign n3120_o = n3117_o | n3119_o; + /* T80_MCode.vhd:710:98 */ + assign n3122_o = ir == 8'b11111110; + /* T80_MCode.vhd:710:98 */ + assign n3123_o = n3120_o | n3122_o; + /* T80_MCode.vhd:727:17 */ + assign n3125_o = ir == 8'b00000100; + /* T80_MCode.vhd:727:32 */ + assign n3127_o = ir == 8'b00001100; + /* T80_MCode.vhd:727:32 */ + assign n3128_o = n3125_o | n3127_o; + /* T80_MCode.vhd:727:43 */ + assign n3130_o = ir == 8'b00010100; + /* T80_MCode.vhd:727:43 */ + assign n3131_o = n3128_o | n3130_o; + /* T80_MCode.vhd:727:54 */ + assign n3133_o = ir == 8'b00011100; + /* T80_MCode.vhd:727:54 */ + assign n3134_o = n3131_o | n3133_o; + /* T80_MCode.vhd:727:65 */ + assign n3136_o = ir == 8'b00100100; + /* T80_MCode.vhd:727:65 */ + assign n3137_o = n3134_o | n3136_o; + /* T80_MCode.vhd:727:76 */ + assign n3139_o = ir == 8'b00101100; + /* T80_MCode.vhd:727:76 */ + assign n3140_o = n3137_o | n3139_o; + /* T80_MCode.vhd:727:87 */ + assign n3142_o = ir == 8'b00111100; + /* T80_MCode.vhd:727:87 */ + assign n3143_o = n3140_o | n3142_o; + /* T80_MCode.vhd:738:30 */ + assign n3144_o = {28'b0, mcycle}; // uext + /* T80_MCode.vhd:739:25 */ + assign n3146_o = n3144_o == 31'b0000000000000000000000000000001; + /* T80_MCode.vhd:741:25 */ + assign n3148_o = n3144_o == 31'b0000000000000000000000000000010; + /* T80_MCode.vhd:750:25 */ + assign n3150_o = n3144_o == 31'b0000000000000000000000000000011; + assign n3151_o = {n3150_o, n3148_o, n3146_o}; + /* T80_MCode.vhd:738:25 */ + always @* + case (n3151_o) + 3'b100: n3153_o = n2200_o; + 3'b010: n3153_o = 3'b100; + 3'b001: n3153_o = n2200_o; + default: n3153_o = n2200_o; + endcase + /* T80_MCode.vhd:738:25 */ + always @* + case (n3151_o) + 3'b100: n3156_o = 1'b0; + 3'b010: n3156_o = 1'b1; + 3'b001: n3156_o = 1'b0; + default: n3156_o = 1'b0; + endcase + /* T80_MCode.vhd:738:25 */ + always @* + case (n3151_o) + 3'b100: n3158_o = 3'b000; + 3'b010: n3158_o = n2193_o; + 3'b001: n3158_o = 3'b000; + default: n3158_o = 3'b000; + endcase + /* T80_MCode.vhd:738:25 */ + always @* + case (n3151_o) + 3'b100: n3161_o = 4'b0000; + 3'b010: n3161_o = 4'b1010; + 3'b001: n3161_o = 4'b0000; + default: n3161_o = 4'b0000; + endcase + /* T80_MCode.vhd:738:25 */ + always @* + case (n3151_o) + 3'b100: n3163_o = n2203_o; + 3'b010: n3163_o = 4'b0000; + 3'b001: n3163_o = n2203_o; + default: n3163_o = n2203_o; + endcase + /* T80_MCode.vhd:738:25 */ + always @* + case (n3151_o) + 3'b100: n3166_o = 1'b0; + 3'b010: n3166_o = 1'b1; + 3'b001: n3166_o = 1'b0; + default: n3166_o = 1'b0; + endcase + /* T80_MCode.vhd:738:25 */ + always @* + case (n3151_o) + 3'b100: n3169_o = 1'b0; + 3'b010: n3169_o = 1'b1; + 3'b001: n3169_o = 1'b0; + default: n3169_o = 1'b0; + endcase + /* T80_MCode.vhd:738:25 */ + always @* + case (n3151_o) + 3'b100: n3173_o = 3'b111; + 3'b010: n3173_o = 3'b010; + 3'b001: n3173_o = 3'b010; + default: n3173_o = 3'b111; + endcase + /* T80_MCode.vhd:738:25 */ + always @* + case (n3151_o) + 3'b100: n3176_o = 1'b1; + 3'b010: n3176_o = 1'b0; + 3'b001: n3176_o = 1'b0; + default: n3176_o = 1'b0; + endcase + /* T80_MCode.vhd:735:17 */ + assign n3178_o = ir == 8'b00110100; + /* T80_MCode.vhd:754:17 */ + assign n3180_o = ir == 8'b00000101; + /* T80_MCode.vhd:754:32 */ + assign n3182_o = ir == 8'b00001101; + /* T80_MCode.vhd:754:32 */ + assign n3183_o = n3180_o | n3182_o; + /* T80_MCode.vhd:754:43 */ + assign n3185_o = ir == 8'b00010101; + /* T80_MCode.vhd:754:43 */ + assign n3186_o = n3183_o | n3185_o; + /* T80_MCode.vhd:754:54 */ + assign n3188_o = ir == 8'b00011101; + /* T80_MCode.vhd:754:54 */ + assign n3189_o = n3186_o | n3188_o; + /* T80_MCode.vhd:754:65 */ + assign n3191_o = ir == 8'b00100101; + /* T80_MCode.vhd:754:65 */ + assign n3192_o = n3189_o | n3191_o; + /* T80_MCode.vhd:754:76 */ + assign n3194_o = ir == 8'b00101101; + /* T80_MCode.vhd:754:76 */ + assign n3195_o = n3192_o | n3194_o; + /* T80_MCode.vhd:754:87 */ + assign n3197_o = ir == 8'b00111101; + /* T80_MCode.vhd:754:87 */ + assign n3198_o = n3195_o | n3197_o; + /* T80_MCode.vhd:765:30 */ + assign n3199_o = {28'b0, mcycle}; // uext + /* T80_MCode.vhd:766:25 */ + assign n3201_o = n3199_o == 31'b0000000000000000000000000000001; + /* T80_MCode.vhd:768:25 */ + assign n3203_o = n3199_o == 31'b0000000000000000000000000000010; + /* T80_MCode.vhd:777:25 */ + assign n3205_o = n3199_o == 31'b0000000000000000000000000000011; + assign n3206_o = {n3205_o, n3203_o, n3201_o}; + /* T80_MCode.vhd:765:25 */ + always @* + case (n3206_o) + 3'b100: n3208_o = n2200_o; + 3'b010: n3208_o = 3'b100; + 3'b001: n3208_o = n2200_o; + default: n3208_o = n2200_o; + endcase + /* T80_MCode.vhd:765:25 */ + always @* + case (n3206_o) + 3'b100: n3211_o = 1'b0; + 3'b010: n3211_o = 1'b1; + 3'b001: n3211_o = 1'b0; + default: n3211_o = 1'b0; + endcase + /* T80_MCode.vhd:765:25 */ + always @* + case (n3206_o) + 3'b100: n3213_o = 3'b000; + 3'b010: n3213_o = n2193_o; + 3'b001: n3213_o = 3'b000; + default: n3213_o = 3'b000; + endcase + /* T80_MCode.vhd:765:25 */ + always @* + case (n3206_o) + 3'b100: n3216_o = 4'b0000; + 3'b010: n3216_o = 4'b1010; + 3'b001: n3216_o = 4'b0000; + default: n3216_o = 4'b0000; + endcase + /* T80_MCode.vhd:765:25 */ + always @* + case (n3206_o) + 3'b100: n3218_o = n2203_o; + 3'b010: n3218_o = 4'b0010; + 3'b001: n3218_o = n2203_o; + default: n3218_o = n2203_o; + endcase + /* T80_MCode.vhd:765:25 */ + always @* + case (n3206_o) + 3'b100: n3221_o = 1'b0; + 3'b010: n3221_o = 1'b1; + 3'b001: n3221_o = 1'b0; + default: n3221_o = 1'b0; + endcase + /* T80_MCode.vhd:765:25 */ + always @* + case (n3206_o) + 3'b100: n3224_o = 1'b0; + 3'b010: n3224_o = 1'b1; + 3'b001: n3224_o = 1'b0; + default: n3224_o = 1'b0; + endcase + /* T80_MCode.vhd:765:25 */ + always @* + case (n3206_o) + 3'b100: n3228_o = 3'b111; + 3'b010: n3228_o = 3'b010; + 3'b001: n3228_o = 3'b010; + default: n3228_o = 3'b111; + endcase + /* T80_MCode.vhd:765:25 */ + always @* + case (n3206_o) + 3'b100: n3231_o = 1'b1; + 3'b010: n3231_o = 1'b0; + 3'b001: n3231_o = 1'b0; + default: n3231_o = 1'b0; + endcase + /* T80_MCode.vhd:762:17 */ + assign n3233_o = ir == 8'b00110101; + /* T80_MCode.vhd:783:17 */ + assign n3236_o = ir == 8'b00100111; + /* T80_MCode.vhd:789:17 */ + assign n3238_o = ir == 8'b00101111; + /* T80_MCode.vhd:792:17 */ + assign n3240_o = ir == 8'b00111111; + /* T80_MCode.vhd:795:17 */ + assign n3242_o = ir == 8'b00110111; + /* T80_MCode.vhd:802:38 */ + assign n3243_o = {28'b0, mcycle}; // uext + /* T80_MCode.vhd:803:33 */ + assign n3245_o = n3243_o == 31'b0000000000000000000000000000001; + /* T80_MCode.vhd:808:33 */ + assign n3247_o = n3243_o == 31'b0000000000000000000000000000010; + /* T80_MCode.vhd:813:33 */ + assign n3249_o = n3243_o == 31'b0000000000000000000000000000011; + assign n3250_o = {n3249_o, n3247_o, n3245_o}; + /* T80_MCode.vhd:802:33 */ + always @* + case (n3250_o) + 3'b100: n3252_o = n2200_o; + 3'b010: n3252_o = n2200_o; + 3'b001: n3252_o = 3'b101; + default: n3252_o = n2200_o; + endcase + /* T80_MCode.vhd:802:33 */ + always @* + case (n3250_o) + 3'b100: n3256_o = 4'b0000; + 3'b010: n3256_o = 4'b1111; + 3'b001: n3256_o = 4'b1111; + default: n3256_o = 4'b0000; + endcase + /* T80_MCode.vhd:802:33 */ + always @* + case (n3250_o) + 3'b100: n3260_o = 4'b0000; + 3'b010: n3260_o = 4'b1100; + 3'b001: n3260_o = 4'b1101; + default: n3260_o = 4'b0000; + endcase + /* T80_MCode.vhd:802:33 */ + always @* + case (n3250_o) + 3'b100: n3264_o = 3'b111; + 3'b010: n3264_o = 3'b101; + 3'b001: n3264_o = 3'b101; + default: n3264_o = 3'b111; + endcase + /* T80_MCode.vhd:802:33 */ + always @* + case (n3250_o) + 3'b100: n3268_o = 1'b1; + 3'b010: n3268_o = 1'b1; + 3'b001: n3268_o = 1'b0; + default: n3268_o = 1'b0; + endcase + /* T80_MCode.vhd:820:38 */ + assign n3269_o = {28'b0, mcycle}; // uext + /* T80_MCode.vhd:821:33 */ + assign n3271_o = n3269_o == 31'b0000000000000000000000000000001; + /* T80_MCode.vhd:827:33 */ + assign n3273_o = n3269_o == 31'b0000000000000000000000000000010; + /* T80_MCode.vhd:833:33 */ + assign n3275_o = n3269_o == 31'b0000000000000000000000000000011; + /* T80_MCode.vhd:836:33 */ + assign n3277_o = n3269_o == 31'b0000000000000000000000000000100; + /* T80_MCode.vhd:839:33 */ + assign n3279_o = n3269_o == 31'b0000000000000000000000000000101; + assign n3280_o = {n3279_o, n3277_o, n3275_o, n3273_o, n3271_o}; + /* T80_MCode.vhd:820:33 */ + always @* + case (n3280_o) + 5'b10000: n3282_o = n2200_o; + 5'b01000: n3282_o = n2200_o; + 5'b00100: n3282_o = n2200_o; + 5'b00010: n3282_o = n2200_o; + 5'b00001: n3282_o = 3'b101; + default: n3282_o = n2200_o; + endcase + /* T80_MCode.vhd:820:33 */ + always @* + case (n3280_o) + 5'b10000: n3285_o = 1'b0; + 5'b01000: n3285_o = 1'b1; + 5'b00100: n3285_o = 1'b0; + 5'b00010: n3285_o = 1'b0; + 5'b00001: n3285_o = 1'b0; + default: n3285_o = 1'b0; + endcase + /* T80_MCode.vhd:820:33 */ + always @* + case (n3280_o) + 5'b10000: n3289_o = 4'b0000; + 5'b01000: n3289_o = 4'b0000; + 5'b00100: n3289_o = 4'b0000; + 5'b00010: n3289_o = 4'b1111; + 5'b00001: n3289_o = 4'b1111; + default: n3289_o = 4'b0000; + endcase + /* T80_MCode.vhd:820:33 */ + always @* + case (n3280_o) + 5'b10000: n3293_o = 4'b0000; + 5'b01000: n3293_o = 4'b0000; + 5'b00100: n3293_o = 4'b0000; + 5'b00010: n3293_o = 4'b1100; + 5'b00001: n3293_o = 4'b1101; + default: n3293_o = 4'b0000; + endcase + /* T80_MCode.vhd:820:33 */ + always @* + case (n3280_o) + 5'b10000: n3297_o = 3'b111; + 5'b01000: n3297_o = 3'b111; + 5'b00100: n3297_o = 3'b111; + 5'b00010: n3297_o = 3'b101; + 5'b00001: n3297_o = 3'b101; + default: n3297_o = 3'b111; + endcase + /* T80_MCode.vhd:820:33 */ + always @* + case (n3280_o) + 5'b10000: n3300_o = 1'b1; + 5'b01000: n3300_o = 1'b0; + 5'b00100: n3300_o = 1'b0; + 5'b00010: n3300_o = 1'b0; + 5'b00001: n3300_o = 1'b0; + default: n3300_o = 1'b0; + endcase + /* T80_MCode.vhd:820:33 */ + always @* + case (n3280_o) + 5'b10000: n3304_o = 1'b0; + 5'b01000: n3304_o = 1'b1; + 5'b00100: n3304_o = 1'b0; + 5'b00010: n3304_o = 1'b0; + 5'b00001: n3304_o = 1'b1; + default: n3304_o = 1'b0; + endcase + /* T80_MCode.vhd:820:33 */ + always @* + case (n3280_o) + 5'b10000: n3308_o = 1'b0; + 5'b01000: n3308_o = 1'b0; + 5'b00100: n3308_o = 1'b1; + 5'b00010: n3308_o = 1'b1; + 5'b00001: n3308_o = 1'b0; + default: n3308_o = 1'b0; + endcase + /* T80_MCode.vhd:817:25 */ + assign n3311_o = intcycle ? 3'b101 : 3'b001; + /* T80_MCode.vhd:817:25 */ + assign n3312_o = intcycle ? n3282_o : n2200_o; + /* T80_MCode.vhd:817:25 */ + assign n3314_o = intcycle ? n3285_o : 1'b0; + /* T80_MCode.vhd:817:25 */ + assign n3316_o = intcycle ? n3289_o : 4'b0000; + /* T80_MCode.vhd:817:25 */ + assign n3318_o = intcycle ? n3293_o : 4'b0000; + /* T80_MCode.vhd:817:25 */ + assign n3320_o = intcycle ? n3297_o : 3'b111; + /* T80_MCode.vhd:817:25 */ + assign n3322_o = intcycle ? n3300_o : 1'b0; + /* T80_MCode.vhd:817:25 */ + assign n3324_o = intcycle ? n3304_o : 1'b0; + /* T80_MCode.vhd:817:25 */ + assign n3326_o = intcycle ? n3308_o : 1'b0; + /* T80_MCode.vhd:799:25 */ + assign n3328_o = nmicycle ? 3'b011 : n3311_o; + /* T80_MCode.vhd:799:25 */ + assign n3329_o = nmicycle ? n3252_o : n3312_o; + /* T80_MCode.vhd:799:25 */ + assign n3331_o = nmicycle ? 1'b0 : n3314_o; + /* T80_MCode.vhd:799:25 */ + assign n3332_o = nmicycle ? n3256_o : n3316_o; + /* T80_MCode.vhd:799:25 */ + assign n3333_o = nmicycle ? n3260_o : n3318_o; + /* T80_MCode.vhd:799:25 */ + assign n3334_o = nmicycle ? n3264_o : n3320_o; + /* T80_MCode.vhd:799:25 */ + assign n3336_o = nmicycle ? 1'b0 : n3322_o; + /* T80_MCode.vhd:799:25 */ + assign n3338_o = nmicycle ? 1'b0 : n3324_o; + /* T80_MCode.vhd:799:25 */ + assign n3339_o = nmicycle ? n3268_o : n3326_o; + /* T80_MCode.vhd:798:17 */ + assign n3341_o = ir == 8'b00000000; + /* T80_MCode.vhd:846:17 */ + assign n3343_o = ir == 8'b01110110; + /* T80_MCode.vhd:849:17 */ + assign n3345_o = ir == 8'b11110011; + /* T80_MCode.vhd:852:17 */ + assign n3347_o = ir == 8'b11111011; + /* T80_MCode.vhd:860:30 */ + assign n3348_o = {28'b0, mcycle}; // uext + /* T80_MCode.vhd:867:60 */ + assign n3350_o = ir[5:4]; + /* T80_MCode.vhd:867:38 */ + assign n3351_o = {29'b0, n3350_o}; // uext + /* T80_MCode.vhd:869:70 */ + assign n3352_o = ir[5:4]; + /* T80_MCode.vhd:868:33 */ + assign n3355_o = n3351_o == 31'b0000000000000000000000000000000; + /* T80_MCode.vhd:868:39 */ + assign n3357_o = n3351_o == 31'b0000000000000000000000000000001; + /* T80_MCode.vhd:868:39 */ + assign n3358_o = n3355_o | n3357_o; + /* T80_MCode.vhd:868:41 */ + assign n3360_o = n3351_o == 31'b0000000000000000000000000000010; + /* T80_MCode.vhd:868:41 */ + assign n3361_o = n3358_o | n3360_o; + /* T80_MCode.vhd:867:33 */ + always @* + case (n3361_o) + 1'b1: n3363_o = 1'b1; + default: n3363_o = 1'b0; + endcase + /* T80_MCode.vhd:867:33 */ + always @* + case (n3361_o) + 1'b1: n3365_o = n3352_o; + default: n3365_o = 2'b00; + endcase + /* T80_MCode.vhd:867:33 */ + always @* + case (n3361_o) + 1'b1: n3368_o = 1'b0; + default: n3368_o = 1'b1; + endcase + /* T80_MCode.vhd:861:25 */ + assign n3370_o = n3348_o == 31'b0000000000000000000000000000010; + /* T80_MCode.vhd:883:60 */ + assign n3372_o = ir[5:4]; + /* T80_MCode.vhd:883:38 */ + assign n3373_o = {29'b0, n3372_o}; // uext + /* T80_MCode.vhd:885:70 */ + assign n3374_o = ir[5:4]; + /* T80_MCode.vhd:884:33 */ + assign n3376_o = n3373_o == 31'b0000000000000000000000000000000; + /* T80_MCode.vhd:884:39 */ + assign n3378_o = n3373_o == 31'b0000000000000000000000000000001; + /* T80_MCode.vhd:884:39 */ + assign n3379_o = n3376_o | n3378_o; + /* T80_MCode.vhd:884:41 */ + assign n3381_o = n3373_o == 31'b0000000000000000000000000000010; + /* T80_MCode.vhd:884:41 */ + assign n3382_o = n3379_o | n3381_o; + /* T80_MCode.vhd:883:33 */ + always @* + case (n3382_o) + 1'b1: n3385_o = 1'b0; + default: n3385_o = 1'b1; + endcase + /* T80_MCode.vhd:883:33 */ + always @* + case (n3382_o) + 1'b1: n3387_o = n3374_o; + default: n3387_o = 2'b00; + endcase + /* T80_MCode.vhd:883:33 */ + always @* + case (n3382_o) + 1'b1: n3390_o = 1'b0; + default: n3390_o = 1'b1; + endcase + /* T80_MCode.vhd:877:25 */ + assign n3392_o = n3348_o == 31'b0000000000000000000000000000011; + assign n3393_o = {n3392_o, n3370_o}; + /* T80_MCode.vhd:860:25 */ + always @* + case (n3393_o) + 2'b10: n3395_o = n2200_o; + 2'b01: n3395_o = 3'b100; + default: n3395_o = n2200_o; + endcase + /* T80_MCode.vhd:860:25 */ + always @* + case (n3393_o) + 2'b10: n3399_o = 1'b1; + 2'b01: n3399_o = 1'b1; + default: n3399_o = 1'b0; + endcase + /* T80_MCode.vhd:860:25 */ + always @* + case (n3393_o) + 2'b10: n3401_o = 3'b100; + 2'b01: n3401_o = 3'b101; + default: n3401_o = 3'b000; + endcase + /* T80_MCode.vhd:860:25 */ + always @* + case (n3393_o) + 2'b10: n3403_o = n3385_o; + 2'b01: n3403_o = n3363_o; + default: n3403_o = 1'b0; + endcase + /* T80_MCode.vhd:860:25 */ + always @* + case (n3393_o) + 2'b10: n3405_o = n3387_o; + 2'b01: n3405_o = n3365_o; + default: n3405_o = 2'b00; + endcase + /* T80_MCode.vhd:860:25 */ + always @* + case (n3393_o) + 2'b10: n3407_o = n3390_o; + 2'b01: n3407_o = n3368_o; + default: n3407_o = 1'b0; + endcase + /* T80_MCode.vhd:860:25 */ + always @* + case (n3393_o) + 2'b10: n3410_o = 4'b0001; + 2'b01: n3410_o = 4'b0000; + default: n3410_o = n2203_o; + endcase + /* T80_MCode.vhd:860:25 */ + always @* + case (n3393_o) + 2'b10: n3414_o = 1'b1; + 2'b01: n3414_o = 1'b1; + default: n3414_o = 1'b0; + endcase + /* T80_MCode.vhd:860:25 */ + always @* + case (n3393_o) + 2'b10: n3418_o = 1'b1; + 2'b01: n3418_o = 1'b1; + default: n3418_o = 1'b0; + endcase + /* T80_MCode.vhd:860:25 */ + always @* + case (n3393_o) + 2'b10: n3421_o = 2'b00; + 2'b01: n3421_o = 2'b11; + default: n3421_o = 2'b00; + endcase + /* T80_MCode.vhd:860:25 */ + always @* + case (n3393_o) + 2'b10: n3425_o = 1'b1; + 2'b01: n3425_o = 1'b1; + default: n3425_o = 1'b0; + endcase + /* T80_MCode.vhd:857:17 */ + assign n3427_o = ir == 8'b00001001; + /* T80_MCode.vhd:857:32 */ + assign n3429_o = ir == 8'b00011001; + /* T80_MCode.vhd:857:32 */ + assign n3430_o = n3427_o | n3429_o; + /* T80_MCode.vhd:857:43 */ + assign n3432_o = ir == 8'b00101001; + /* T80_MCode.vhd:857:43 */ + assign n3433_o = n3430_o | n3432_o; + /* T80_MCode.vhd:857:54 */ + assign n3435_o = ir == 8'b00111001; + /* T80_MCode.vhd:857:54 */ + assign n3436_o = n3433_o | n3435_o; + /* T80_MCode.vhd:892:17 */ + assign n3439_o = ir == 8'b00000011; + /* T80_MCode.vhd:892:32 */ + assign n3441_o = ir == 8'b00010011; + /* T80_MCode.vhd:892:32 */ + assign n3442_o = n3439_o | n3441_o; + /* T80_MCode.vhd:892:43 */ + assign n3444_o = ir == 8'b00100011; + /* T80_MCode.vhd:892:43 */ + assign n3445_o = n3442_o | n3444_o; + /* T80_MCode.vhd:892:54 */ + assign n3447_o = ir == 8'b00110011; + /* T80_MCode.vhd:892:54 */ + assign n3448_o = n3445_o | n3447_o; + /* T80_MCode.vhd:897:17 */ + assign n3451_o = ir == 8'b00001011; + /* T80_MCode.vhd:897:32 */ + assign n3453_o = ir == 8'b00011011; + /* T80_MCode.vhd:897:32 */ + assign n3454_o = n3451_o | n3453_o; + /* T80_MCode.vhd:897:43 */ + assign n3456_o = ir == 8'b00101011; + /* T80_MCode.vhd:897:43 */ + assign n3457_o = n3454_o | n3456_o; + /* T80_MCode.vhd:897:54 */ + assign n3459_o = ir == 8'b00111011; + /* T80_MCode.vhd:897:54 */ + assign n3460_o = n3457_o | n3459_o; + /* T80_MCode.vhd:904:17 */ + assign n3463_o = ir == 8'b00000111; + /* T80_MCode.vhd:906:25 */ + assign n3465_o = ir == 8'b00010111; + /* T80_MCode.vhd:906:25 */ + assign n3466_o = n3463_o | n3465_o; + /* T80_MCode.vhd:908:25 */ + assign n3468_o = ir == 8'b00001111; + /* T80_MCode.vhd:908:25 */ + assign n3469_o = n3466_o | n3468_o; + /* T80_MCode.vhd:910:25 */ + assign n3471_o = ir == 8'b00011111; + /* T80_MCode.vhd:910:25 */ + assign n3472_o = n3469_o | n3471_o; + /* T80_MCode.vhd:921:30 */ + assign n3473_o = {28'b0, mcycle}; // uext + /* T80_MCode.vhd:922:25 */ + assign n3475_o = n3473_o == 31'b0000000000000000000000000000010; + /* T80_MCode.vhd:925:25 */ + assign n3477_o = n3473_o == 31'b0000000000000000000000000000011; + assign n3478_o = {n3477_o, n3475_o}; + /* T80_MCode.vhd:921:25 */ + always @* + case (n3478_o) + 2'b10: n3482_o = 1'b1; + 2'b01: n3482_o = 1'b1; + default: n3482_o = 1'b0; + endcase + /* T80_MCode.vhd:921:25 */ + always @* + case (n3478_o) + 2'b10: n3485_o = 1'b1; + 2'b01: n3485_o = 1'b0; + default: n3485_o = 1'b0; + endcase + /* T80_MCode.vhd:921:25 */ + always @* + case (n3478_o) + 2'b10: n3488_o = 1'b0; + 2'b01: n3488_o = 1'b1; + default: n3488_o = 1'b0; + endcase + /* T80_MCode.vhd:921:25 */ + always @* + case (n3478_o) + 2'b10: n3491_o = 1'b1; + 2'b01: n3491_o = 1'b0; + default: n3491_o = 1'b0; + endcase + /* T80_MCode.vhd:918:17 */ + assign n3493_o = ir == 8'b11000011; + /* T80_MCode.vhd:990:38 */ + assign n3495_o = {28'b0, mcycle}; // uext + /* T80_MCode.vhd:991:33 */ + assign n3497_o = n3495_o == 31'b0000000000000000000000000000010; + /* T80_MCode.vhd:997:73 */ + assign n3499_o = ir[5:3]; + /* T80_MCode.vhd:178:47 */ + assign n3504_o = f[6]; + /* T80_MCode.vhd:178:56 */ + assign n3505_o = ~n3504_o; + /* T80_MCode.vhd:178:25 */ + assign n3507_o = n3499_o == 3'b000; + /* T80_MCode.vhd:179:47 */ + assign n3508_o = f[6]; + /* T80_MCode.vhd:179:25 */ + assign n3510_o = n3499_o == 3'b001; + /* T80_MCode.vhd:180:47 */ + assign n3511_o = f[0]; + /* T80_MCode.vhd:180:56 */ + assign n3512_o = ~n3511_o; + /* T80_MCode.vhd:180:25 */ + assign n3514_o = n3499_o == 3'b010; + /* T80_MCode.vhd:181:47 */ + assign n3515_o = f[0]; + /* T80_MCode.vhd:181:25 */ + assign n3517_o = n3499_o == 3'b011; + /* T80_MCode.vhd:182:47 */ + assign n3518_o = f[2]; + /* T80_MCode.vhd:182:56 */ + assign n3519_o = ~n3518_o; + /* T80_MCode.vhd:182:25 */ + assign n3521_o = n3499_o == 3'b100; + /* T80_MCode.vhd:183:47 */ + assign n3522_o = f[2]; + /* T80_MCode.vhd:183:25 */ + assign n3524_o = n3499_o == 3'b101; + /* T80_MCode.vhd:184:47 */ + assign n3525_o = f[7]; + /* T80_MCode.vhd:184:56 */ + assign n3526_o = ~n3525_o; + /* T80_MCode.vhd:184:25 */ + assign n3528_o = n3499_o == 3'b110; + /* T80_MCode.vhd:185:47 */ + assign n3529_o = f[7]; + /* T80_MCode.vhd:185:25 */ + assign n3531_o = n3499_o == 3'b111; + assign n3532_o = {n3531_o, n3528_o, n3524_o, n3521_o, n3517_o, n3514_o, n3510_o, n3507_o}; + /* T80_MCode.vhd:177:25 */ + always @* + case (n3532_o) + 8'b10000000: n3534_o = n3529_o; + 8'b01000000: n3534_o = n3526_o; + 8'b00100000: n3534_o = n3522_o; + 8'b00010000: n3534_o = n3519_o; + 8'b00001000: n3534_o = n3515_o; + 8'b00000100: n3534_o = n3512_o; + 8'b00000010: n3534_o = n3508_o; + 8'b00000001: n3534_o = n3505_o; + default: n3534_o = 1'bX; + endcase + /* T80_MCode.vhd:997:41 */ + assign n3537_o = n3534_o ? 1'b1 : 1'b0; + /* T80_MCode.vhd:994:33 */ + assign n3539_o = n3495_o == 31'b0000000000000000000000000000011; + assign n3540_o = {n3539_o, n3497_o}; + /* T80_MCode.vhd:990:33 */ + always @* + case (n3540_o) + 2'b10: n3544_o = 1'b1; + 2'b01: n3544_o = 1'b1; + default: n3544_o = 1'b0; + endcase + /* T80_MCode.vhd:990:33 */ + always @* + case (n3540_o) + 2'b10: n3546_o = n3537_o; + 2'b01: n3546_o = 1'b0; + default: n3546_o = 1'b0; + endcase + /* T80_MCode.vhd:990:33 */ + always @* + case (n3540_o) + 2'b10: n3549_o = 1'b0; + 2'b01: n3549_o = 1'b1; + default: n3549_o = 1'b0; + endcase + /* T80_MCode.vhd:990:33 */ + always @* + case (n3540_o) + 2'b10: n3552_o = 1'b1; + 2'b01: n3552_o = 1'b0; + default: n3552_o = 1'b0; + endcase + /* T80_MCode.vhd:931:17 */ + assign n3554_o = ir == 8'b11000010; + /* T80_MCode.vhd:931:32 */ + assign n3556_o = ir == 8'b11001010; + /* T80_MCode.vhd:931:32 */ + assign n3557_o = n3554_o | n3556_o; + /* T80_MCode.vhd:931:43 */ + assign n3559_o = ir == 8'b11010010; + /* T80_MCode.vhd:931:43 */ + assign n3560_o = n3557_o | n3559_o; + /* T80_MCode.vhd:931:54 */ + assign n3562_o = ir == 8'b11011010; + /* T80_MCode.vhd:931:54 */ + assign n3563_o = n3560_o | n3562_o; + /* T80_MCode.vhd:931:65 */ + assign n3565_o = ir == 8'b11100010; + /* T80_MCode.vhd:931:65 */ + assign n3566_o = n3563_o | n3565_o; + /* T80_MCode.vhd:931:76 */ + assign n3568_o = ir == 8'b11101010; + /* T80_MCode.vhd:931:76 */ + assign n3569_o = n3566_o | n3568_o; + /* T80_MCode.vhd:931:87 */ + assign n3571_o = ir == 8'b11110010; + /* T80_MCode.vhd:931:87 */ + assign n3572_o = n3569_o | n3571_o; + /* T80_MCode.vhd:931:98 */ + assign n3574_o = ir == 8'b11111010; + /* T80_MCode.vhd:931:98 */ + assign n3575_o = n3572_o | n3574_o; + /* T80_MCode.vhd:1007:38 */ + assign n3576_o = {28'b0, mcycle}; // uext + /* T80_MCode.vhd:1008:33 */ + assign n3578_o = n3576_o == 31'b0000000000000000000000000000010; + /* T80_MCode.vhd:1010:33 */ + assign n3580_o = n3576_o == 31'b0000000000000000000000000000011; + assign n3581_o = {n3580_o, n3578_o}; + /* T80_MCode.vhd:1007:33 */ + always @* + case (n3581_o) + 2'b10: n3583_o = 3'b101; + 2'b01: n3583_o = n2200_o; + default: n3583_o = n2200_o; + endcase + /* T80_MCode.vhd:1007:33 */ + always @* + case (n3581_o) + 2'b10: n3586_o = 1'b0; + 2'b01: n3586_o = 1'b1; + default: n3586_o = 1'b0; + endcase + /* T80_MCode.vhd:1007:33 */ + always @* + case (n3581_o) + 2'b10: n3589_o = 1'b1; + 2'b01: n3589_o = 1'b0; + default: n3589_o = 1'b0; + endcase + /* T80_MCode.vhd:1007:33 */ + always @* + case (n3581_o) + 2'b10: n3592_o = 1'b1; + 2'b01: n3592_o = 1'b0; + default: n3592_o = 1'b0; + endcase + /* T80_MCode.vhd:1003:17 */ + assign n3594_o = ir == 8'b00011000; + /* T80_MCode.vhd:1021:38 */ + assign n3595_o = {28'b0, mcycle}; // uext + /* T80_MCode.vhd:1024:45 */ + assign n3596_o = f[0]; + /* T80_MCode.vhd:1024:54 */ + assign n3597_o = ~n3596_o; + /* T80_MCode.vhd:1024:41 */ + assign n3600_o = n3597_o ? 3'b010 : 3'b011; + /* T80_MCode.vhd:1022:33 */ + assign n3602_o = n3595_o == 31'b0000000000000000000000000000010; + /* T80_MCode.vhd:1027:33 */ + assign n3604_o = n3595_o == 31'b0000000000000000000000000000011; + assign n3605_o = {n3604_o, n3602_o}; + /* T80_MCode.vhd:1021:33 */ + always @* + case (n3605_o) + 2'b10: n3607_o = 3'b011; + 2'b01: n3607_o = n3600_o; + default: n3607_o = 3'b011; + endcase + /* T80_MCode.vhd:1021:33 */ + always @* + case (n3605_o) + 2'b10: n3610_o = 3'b101; + 2'b01: n3610_o = n2200_o; + default: n3610_o = n2200_o; + endcase + /* T80_MCode.vhd:1021:33 */ + always @* + case (n3605_o) + 2'b10: n3613_o = 1'b0; + 2'b01: n3613_o = 1'b1; + default: n3613_o = 1'b0; + endcase + /* T80_MCode.vhd:1021:33 */ + always @* + case (n3605_o) + 2'b10: n3616_o = 1'b1; + 2'b01: n3616_o = 1'b0; + default: n3616_o = 1'b0; + endcase + /* T80_MCode.vhd:1021:33 */ + always @* + case (n3605_o) + 2'b10: n3619_o = 1'b1; + 2'b01: n3619_o = 1'b0; + default: n3619_o = 1'b0; + endcase + /* T80_MCode.vhd:1017:17 */ + assign n3621_o = ir == 8'b00111000; + /* T80_MCode.vhd:1038:38 */ + assign n3622_o = {28'b0, mcycle}; // uext + /* T80_MCode.vhd:1041:45 */ + assign n3623_o = f[0]; + /* T80_MCode.vhd:1041:41 */ + assign n3626_o = n3623_o ? 3'b010 : 3'b011; + /* T80_MCode.vhd:1039:33 */ + assign n3628_o = n3622_o == 31'b0000000000000000000000000000010; + /* T80_MCode.vhd:1044:33 */ + assign n3630_o = n3622_o == 31'b0000000000000000000000000000011; + assign n3631_o = {n3630_o, n3628_o}; + /* T80_MCode.vhd:1038:33 */ + always @* + case (n3631_o) + 2'b10: n3633_o = 3'b011; + 2'b01: n3633_o = n3626_o; + default: n3633_o = 3'b011; + endcase + /* T80_MCode.vhd:1038:33 */ + always @* + case (n3631_o) + 2'b10: n3636_o = 3'b101; + 2'b01: n3636_o = n2200_o; + default: n3636_o = n2200_o; + endcase + /* T80_MCode.vhd:1038:33 */ + always @* + case (n3631_o) + 2'b10: n3639_o = 1'b0; + 2'b01: n3639_o = 1'b1; + default: n3639_o = 1'b0; + endcase + /* T80_MCode.vhd:1038:33 */ + always @* + case (n3631_o) + 2'b10: n3642_o = 1'b1; + 2'b01: n3642_o = 1'b0; + default: n3642_o = 1'b0; + endcase + /* T80_MCode.vhd:1038:33 */ + always @* + case (n3631_o) + 2'b10: n3645_o = 1'b1; + 2'b01: n3645_o = 1'b0; + default: n3645_o = 1'b0; + endcase + /* T80_MCode.vhd:1034:17 */ + assign n3647_o = ir == 8'b00110000; + /* T80_MCode.vhd:1055:38 */ + assign n3648_o = {28'b0, mcycle}; // uext + /* T80_MCode.vhd:1058:45 */ + assign n3649_o = f[6]; + /* T80_MCode.vhd:1058:54 */ + assign n3650_o = ~n3649_o; + /* T80_MCode.vhd:1058:41 */ + assign n3653_o = n3650_o ? 3'b010 : 3'b011; + /* T80_MCode.vhd:1056:33 */ + assign n3655_o = n3648_o == 31'b0000000000000000000000000000010; + /* T80_MCode.vhd:1061:33 */ + assign n3657_o = n3648_o == 31'b0000000000000000000000000000011; + assign n3658_o = {n3657_o, n3655_o}; + /* T80_MCode.vhd:1055:33 */ + always @* + case (n3658_o) + 2'b10: n3660_o = 3'b011; + 2'b01: n3660_o = n3653_o; + default: n3660_o = 3'b011; + endcase + /* T80_MCode.vhd:1055:33 */ + always @* + case (n3658_o) + 2'b10: n3663_o = 3'b101; + 2'b01: n3663_o = n2200_o; + default: n3663_o = n2200_o; + endcase + /* T80_MCode.vhd:1055:33 */ + always @* + case (n3658_o) + 2'b10: n3666_o = 1'b0; + 2'b01: n3666_o = 1'b1; + default: n3666_o = 1'b0; + endcase + /* T80_MCode.vhd:1055:33 */ + always @* + case (n3658_o) + 2'b10: n3669_o = 1'b1; + 2'b01: n3669_o = 1'b0; + default: n3669_o = 1'b0; + endcase + /* T80_MCode.vhd:1055:33 */ + always @* + case (n3658_o) + 2'b10: n3672_o = 1'b1; + 2'b01: n3672_o = 1'b0; + default: n3672_o = 1'b0; + endcase + /* T80_MCode.vhd:1051:17 */ + assign n3674_o = ir == 8'b00101000; + /* T80_MCode.vhd:1072:38 */ + assign n3675_o = {28'b0, mcycle}; // uext + /* T80_MCode.vhd:1075:45 */ + assign n3676_o = f[6]; + /* T80_MCode.vhd:1075:41 */ + assign n3679_o = n3676_o ? 3'b010 : 3'b011; + /* T80_MCode.vhd:1073:33 */ + assign n3681_o = n3675_o == 31'b0000000000000000000000000000010; + /* T80_MCode.vhd:1078:33 */ + assign n3683_o = n3675_o == 31'b0000000000000000000000000000011; + assign n3684_o = {n3683_o, n3681_o}; + /* T80_MCode.vhd:1072:33 */ + always @* + case (n3684_o) + 2'b10: n3686_o = 3'b011; + 2'b01: n3686_o = n3679_o; + default: n3686_o = 3'b011; + endcase + /* T80_MCode.vhd:1072:33 */ + always @* + case (n3684_o) + 2'b10: n3689_o = 3'b101; + 2'b01: n3689_o = n2200_o; + default: n3689_o = n2200_o; + endcase + /* T80_MCode.vhd:1072:33 */ + always @* + case (n3684_o) + 2'b10: n3692_o = 1'b0; + 2'b01: n3692_o = 1'b1; + default: n3692_o = 1'b0; + endcase + /* T80_MCode.vhd:1072:33 */ + always @* + case (n3684_o) + 2'b10: n3695_o = 1'b1; + 2'b01: n3695_o = 1'b0; + default: n3695_o = 1'b0; + endcase + /* T80_MCode.vhd:1072:33 */ + always @* + case (n3684_o) + 2'b10: n3698_o = 1'b1; + 2'b01: n3698_o = 1'b0; + default: n3698_o = 1'b0; + endcase + /* T80_MCode.vhd:1068:17 */ + assign n3700_o = ir == 8'b00100000; + /* T80_MCode.vhd:1085:17 */ + assign n3702_o = ir == 8'b11101001; + /* T80_MCode.vhd:1094:38 */ + assign n3703_o = {28'b0, mcycle}; // uext + /* T80_MCode.vhd:1095:33 */ + assign n3706_o = n3703_o == 31'b0000000000000000000000000000001; + /* T80_MCode.vhd:1103:33 */ + assign n3708_o = n3703_o == 31'b0000000000000000000000000000010; + /* T80_MCode.vhd:1106:33 */ + assign n3710_o = n3703_o == 31'b0000000000000000000000000000011; + assign n3711_o = {n3710_o, n3708_o, n3706_o}; + /* T80_MCode.vhd:1094:33 */ + always @* + case (n3711_o) + 3'b100: n3714_o = 3'b101; + 3'b010: n3714_o = n2200_o; + 3'b001: n3714_o = 3'b101; + default: n3714_o = n2200_o; + endcase + /* T80_MCode.vhd:1094:33 */ + always @* + case (n3711_o) + 3'b100: n3717_o = 1'b0; + 3'b010: n3717_o = 1'b1; + 3'b001: n3717_o = 1'b0; + default: n3717_o = 1'b0; + endcase + /* T80_MCode.vhd:1094:33 */ + always @* + case (n3711_o) + 3'b100: n3720_o = 1'b0; + 3'b010: n3720_o = 1'b0; + 3'b001: n3720_o = 1'b1; + default: n3720_o = 1'b0; + endcase + /* T80_MCode.vhd:1094:33 */ + always @* + case (n3711_o) + 3'b100: n3722_o = 3'b000; + 3'b010: n3722_o = 3'b000; + 3'b001: n3722_o = 3'b000; + default: n3722_o = 3'b000; + endcase + /* T80_MCode.vhd:1094:33 */ + always @* + case (n3711_o) + 3'b100: n3725_o = 4'b0000; + 3'b010: n3725_o = 4'b0000; + 3'b001: n3725_o = 4'b1010; + default: n3725_o = 4'b0000; + endcase + /* T80_MCode.vhd:1094:33 */ + always @* + case (n3711_o) + 3'b100: n3727_o = n2203_o; + 3'b010: n3727_o = n2203_o; + 3'b001: n3727_o = 4'b0010; + default: n3727_o = n2203_o; + endcase + /* T80_MCode.vhd:1094:33 */ + always @* + case (n3711_o) + 3'b100: n3730_o = 1'b0; + 3'b010: n3730_o = 1'b0; + 3'b001: n3730_o = 1'b1; + default: n3730_o = 1'b0; + endcase + /* T80_MCode.vhd:1094:33 */ + always @* + case (n3711_o) + 3'b100: n3733_o = 1'b1; + 3'b010: n3733_o = 1'b0; + 3'b001: n3733_o = 1'b0; + default: n3733_o = 1'b0; + endcase + /* T80_MCode.vhd:1094:33 */ + always @* + case (n3711_o) + 3'b100: n3737_o = 1'b0; + 3'b010: n3737_o = 1'b1; + 3'b001: n3737_o = 1'b1; + default: n3737_o = 1'b0; + endcase + /* T80_MCode.vhd:1094:33 */ + always @* + case (n3711_o) + 3'b100: n3740_o = 1'b1; + 3'b010: n3740_o = 1'b0; + 3'b001: n3740_o = 1'b0; + default: n3740_o = 1'b0; + endcase + /* T80_MCode.vhd:1088:17 */ + assign n3742_o = ir == 8'b00010000; + /* T80_MCode.vhd:1118:30 */ + assign n3743_o = {28'b0, mcycle}; // uext + /* T80_MCode.vhd:1119:25 */ + assign n3745_o = n3743_o == 31'b0000000000000000000000000000010; + /* T80_MCode.vhd:1122:25 */ + assign n3747_o = n3743_o == 31'b0000000000000000000000000000011; + /* T80_MCode.vhd:1129:25 */ + assign n3749_o = n3743_o == 31'b0000000000000000000000000000100; + /* T80_MCode.vhd:1134:25 */ + assign n3751_o = n3743_o == 31'b0000000000000000000000000000101; + assign n3752_o = {n3751_o, n3749_o, n3747_o, n3745_o}; + /* T80_MCode.vhd:1118:25 */ + always @* + case (n3752_o) + 4'b1000: n3754_o = n2200_o; + 4'b0100: n3754_o = n2200_o; + 4'b0010: n3754_o = 3'b100; + 4'b0001: n3754_o = n2200_o; + default: n3754_o = n2200_o; + endcase + /* T80_MCode.vhd:1118:25 */ + always @* + case (n3752_o) + 4'b1000: n3758_o = 1'b0; + 4'b0100: n3758_o = 1'b0; + 4'b0010: n3758_o = 1'b1; + 4'b0001: n3758_o = 1'b1; + default: n3758_o = 1'b0; + endcase + /* T80_MCode.vhd:1118:25 */ + always @* + case (n3752_o) + 4'b1000: n3762_o = 4'b0000; + 4'b0100: n3762_o = 4'b1111; + 4'b0010: n3762_o = 4'b1111; + 4'b0001: n3762_o = 4'b0000; + default: n3762_o = 4'b0000; + endcase + /* T80_MCode.vhd:1118:25 */ + always @* + case (n3752_o) + 4'b1000: n3766_o = 4'b0000; + 4'b0100: n3766_o = 4'b1100; + 4'b0010: n3766_o = 4'b1101; + 4'b0001: n3766_o = 4'b0000; + default: n3766_o = 4'b0000; + endcase + /* T80_MCode.vhd:1118:25 */ + always @* + case (n3752_o) + 4'b1000: n3770_o = 3'b111; + 4'b0100: n3770_o = 3'b101; + 4'b0010: n3770_o = 3'b101; + 4'b0001: n3770_o = 3'b111; + default: n3770_o = 3'b111; + endcase + /* T80_MCode.vhd:1118:25 */ + always @* + case (n3752_o) + 4'b1000: n3773_o = 1'b1; + 4'b0100: n3773_o = 1'b0; + 4'b0010: n3773_o = 1'b0; + 4'b0001: n3773_o = 1'b0; + default: n3773_o = 1'b0; + endcase + /* T80_MCode.vhd:1118:25 */ + always @* + case (n3752_o) + 4'b1000: n3776_o = 1'b0; + 4'b0100: n3776_o = 1'b0; + 4'b0010: n3776_o = 1'b0; + 4'b0001: n3776_o = 1'b1; + default: n3776_o = 1'b0; + endcase + /* T80_MCode.vhd:1118:25 */ + always @* + case (n3752_o) + 4'b1000: n3779_o = 1'b0; + 4'b0100: n3779_o = 1'b0; + 4'b0010: n3779_o = 1'b1; + 4'b0001: n3779_o = 1'b0; + default: n3779_o = 1'b0; + endcase + /* T80_MCode.vhd:1118:25 */ + always @* + case (n3752_o) + 4'b1000: n3783_o = 1'b1; + 4'b0100: n3783_o = 1'b1; + 4'b0010: n3783_o = 1'b0; + 4'b0001: n3783_o = 1'b0; + default: n3783_o = 1'b0; + endcase + /* T80_MCode.vhd:1115:17 */ + assign n3785_o = ir == 8'b11001101; + /* T80_MCode.vhd:1143:38 */ + assign n3788_o = {28'b0, mcycle}; // uext + /* T80_MCode.vhd:1144:33 */ + assign n3790_o = n3788_o == 31'b0000000000000000000000000000010; + /* T80_MCode.vhd:1150:73 */ + assign n3792_o = ir[5:3]; + /* T80_MCode.vhd:178:47 */ + assign n3797_o = f[6]; + /* T80_MCode.vhd:178:56 */ + assign n3798_o = ~n3797_o; + /* T80_MCode.vhd:178:25 */ + assign n3800_o = n3792_o == 3'b000; + /* T80_MCode.vhd:179:47 */ + assign n3801_o = f[6]; + /* T80_MCode.vhd:179:25 */ + assign n3803_o = n3792_o == 3'b001; + /* T80_MCode.vhd:180:47 */ + assign n3804_o = f[0]; + /* T80_MCode.vhd:180:56 */ + assign n3805_o = ~n3804_o; + /* T80_MCode.vhd:180:25 */ + assign n3807_o = n3792_o == 3'b010; + /* T80_MCode.vhd:181:47 */ + assign n3808_o = f[0]; + /* T80_MCode.vhd:181:25 */ + assign n3810_o = n3792_o == 3'b011; + /* T80_MCode.vhd:182:47 */ + assign n3811_o = f[2]; + /* T80_MCode.vhd:182:56 */ + assign n3812_o = ~n3811_o; + /* T80_MCode.vhd:182:25 */ + assign n3814_o = n3792_o == 3'b100; + /* T80_MCode.vhd:183:47 */ + assign n3815_o = f[2]; + /* T80_MCode.vhd:183:25 */ + assign n3817_o = n3792_o == 3'b101; + /* T80_MCode.vhd:184:47 */ + assign n3818_o = f[7]; + /* T80_MCode.vhd:184:56 */ + assign n3819_o = ~n3818_o; + /* T80_MCode.vhd:184:25 */ + assign n3821_o = n3792_o == 3'b110; + /* T80_MCode.vhd:185:47 */ + assign n3822_o = f[7]; + /* T80_MCode.vhd:185:25 */ + assign n3824_o = n3792_o == 3'b111; + assign n3825_o = {n3824_o, n3821_o, n3817_o, n3814_o, n3810_o, n3807_o, n3803_o, n3800_o}; + /* T80_MCode.vhd:177:25 */ + always @* + case (n3825_o) + 8'b10000000: n3827_o = n3822_o; + 8'b01000000: n3827_o = n3819_o; + 8'b00100000: n3827_o = n3815_o; + 8'b00010000: n3827_o = n3812_o; + 8'b00001000: n3827_o = n3808_o; + 8'b00000100: n3827_o = n3805_o; + 8'b00000010: n3827_o = n3801_o; + 8'b00000001: n3827_o = n3798_o; + default: n3827_o = 1'bX; + endcase + /* T80_MCode.vhd:1150:41 */ + assign n3830_o = n3827_o ? 3'b101 : 3'b011; + /* T80_MCode.vhd:1150:41 */ + assign n3832_o = n3827_o ? 3'b100 : n2200_o; + /* T80_MCode.vhd:1150:41 */ + assign n3835_o = n3827_o ? 4'b1111 : 4'b0000; + /* T80_MCode.vhd:1150:41 */ + assign n3838_o = n3827_o ? 4'b1101 : 4'b0000; + /* T80_MCode.vhd:1150:41 */ + assign n3841_o = n3827_o ? 3'b101 : 3'b111; + /* T80_MCode.vhd:1147:33 */ + assign n3843_o = n3788_o == 31'b0000000000000000000000000000011; + /* T80_MCode.vhd:1158:33 */ + assign n3845_o = n3788_o == 31'b0000000000000000000000000000100; + /* T80_MCode.vhd:1163:33 */ + assign n3847_o = n3788_o == 31'b0000000000000000000000000000101; + assign n3848_o = {n3847_o, n3845_o, n3843_o, n3790_o}; + /* T80_MCode.vhd:1143:33 */ + always @* + case (n3848_o) + 4'b1000: n3850_o = 3'b101; + 4'b0100: n3850_o = 3'b101; + 4'b0010: n3850_o = n3830_o; + 4'b0001: n3850_o = 3'b101; + default: n3850_o = 3'b101; + endcase + /* T80_MCode.vhd:1143:33 */ + always @* + case (n3848_o) + 4'b1000: n3852_o = n2200_o; + 4'b0100: n3852_o = n2200_o; + 4'b0010: n3852_o = n3832_o; + 4'b0001: n3852_o = n2200_o; + default: n3852_o = n2200_o; + endcase + /* T80_MCode.vhd:1143:33 */ + always @* + case (n3848_o) + 4'b1000: n3856_o = 1'b0; + 4'b0100: n3856_o = 1'b0; + 4'b0010: n3856_o = 1'b1; + 4'b0001: n3856_o = 1'b1; + default: n3856_o = 1'b0; + endcase + /* T80_MCode.vhd:1143:33 */ + always @* + case (n3848_o) + 4'b1000: n3859_o = 4'b0000; + 4'b0100: n3859_o = 4'b1111; + 4'b0010: n3859_o = n3835_o; + 4'b0001: n3859_o = 4'b0000; + default: n3859_o = 4'b0000; + endcase + /* T80_MCode.vhd:1143:33 */ + always @* + case (n3848_o) + 4'b1000: n3862_o = 4'b0000; + 4'b0100: n3862_o = 4'b1100; + 4'b0010: n3862_o = n3838_o; + 4'b0001: n3862_o = 4'b0000; + default: n3862_o = 4'b0000; + endcase + /* T80_MCode.vhd:1143:33 */ + always @* + case (n3848_o) + 4'b1000: n3865_o = 3'b111; + 4'b0100: n3865_o = 3'b101; + 4'b0010: n3865_o = n3841_o; + 4'b0001: n3865_o = 3'b111; + default: n3865_o = 3'b111; + endcase + /* T80_MCode.vhd:1143:33 */ + always @* + case (n3848_o) + 4'b1000: n3868_o = 1'b1; + 4'b0100: n3868_o = 1'b0; + 4'b0010: n3868_o = 1'b0; + 4'b0001: n3868_o = 1'b0; + default: n3868_o = 1'b0; + endcase + /* T80_MCode.vhd:1143:33 */ + always @* + case (n3848_o) + 4'b1000: n3871_o = 1'b0; + 4'b0100: n3871_o = 1'b0; + 4'b0010: n3871_o = 1'b0; + 4'b0001: n3871_o = 1'b1; + default: n3871_o = 1'b0; + endcase + /* T80_MCode.vhd:1143:33 */ + always @* + case (n3848_o) + 4'b1000: n3874_o = 1'b0; + 4'b0100: n3874_o = 1'b0; + 4'b0010: n3874_o = 1'b1; + 4'b0001: n3874_o = 1'b0; + default: n3874_o = 1'b0; + endcase + /* T80_MCode.vhd:1143:33 */ + always @* + case (n3848_o) + 4'b1000: n3878_o = 1'b1; + 4'b0100: n3878_o = 1'b1; + 4'b0010: n3878_o = 1'b0; + 4'b0001: n3878_o = 1'b0; + default: n3878_o = 1'b0; + endcase + /* T80_MCode.vhd:1139:17 */ + assign n3880_o = ir == 8'b11000100; + /* T80_MCode.vhd:1139:32 */ + assign n3882_o = ir == 8'b11001100; + /* T80_MCode.vhd:1139:32 */ + assign n3883_o = n3880_o | n3882_o; + /* T80_MCode.vhd:1139:43 */ + assign n3885_o = ir == 8'b11010100; + /* T80_MCode.vhd:1139:43 */ + assign n3886_o = n3883_o | n3885_o; + /* T80_MCode.vhd:1139:54 */ + assign n3888_o = ir == 8'b11011100; + /* T80_MCode.vhd:1139:54 */ + assign n3889_o = n3886_o | n3888_o; + /* T80_MCode.vhd:1139:65 */ + assign n3891_o = ir == 8'b11100100; + /* T80_MCode.vhd:1139:65 */ + assign n3892_o = n3889_o | n3891_o; + /* T80_MCode.vhd:1139:76 */ + assign n3894_o = ir == 8'b11101100; + /* T80_MCode.vhd:1139:76 */ + assign n3895_o = n3892_o | n3894_o; + /* T80_MCode.vhd:1139:87 */ + assign n3897_o = ir == 8'b11110100; + /* T80_MCode.vhd:1139:87 */ + assign n3898_o = n3895_o | n3897_o; + /* T80_MCode.vhd:1139:98 */ + assign n3900_o = ir == 8'b11111100; + /* T80_MCode.vhd:1139:98 */ + assign n3901_o = n3898_o | n3900_o; + /* T80_MCode.vhd:1172:30 */ + assign n3902_o = {28'b0, mcycle}; // uext + /* T80_MCode.vhd:1173:25 */ + assign n3904_o = n3902_o == 31'b0000000000000000000000000000001; + /* T80_MCode.vhd:1176:25 */ + assign n3906_o = n3902_o == 31'b0000000000000000000000000000010; + /* T80_MCode.vhd:1180:25 */ + assign n3908_o = n3902_o == 31'b0000000000000000000000000000011; + assign n3909_o = {n3908_o, n3906_o, n3904_o}; + /* T80_MCode.vhd:1172:25 */ + always @* + case (n3909_o) + 3'b100: n3913_o = 4'b0111; + 3'b010: n3913_o = 4'b0111; + 3'b001: n3913_o = 4'b0000; + default: n3913_o = 4'b0000; + endcase + /* T80_MCode.vhd:1172:25 */ + always @* + case (n3909_o) + 3'b100: n3917_o = 3'b111; + 3'b010: n3917_o = 3'b101; + 3'b001: n3917_o = 3'b101; + default: n3917_o = 3'b111; + endcase + /* T80_MCode.vhd:1172:25 */ + always @* + case (n3909_o) + 3'b100: n3920_o = 1'b1; + 3'b010: n3920_o = 1'b0; + 3'b001: n3920_o = 1'b0; + default: n3920_o = 1'b0; + endcase + /* T80_MCode.vhd:1172:25 */ + always @* + case (n3909_o) + 3'b100: n3923_o = 1'b0; + 3'b010: n3923_o = 1'b1; + 3'b001: n3923_o = 1'b0; + default: n3923_o = 1'b0; + endcase + /* T80_MCode.vhd:1169:17 */ + assign n3925_o = ir == 8'b11001001; + /* T80_MCode.vhd:1256:38 */ + assign n3927_o = {28'b0, mcycle}; // uext + /* T80_MCode.vhd:1258:73 */ + assign n3929_o = ir[5:3]; + /* T80_MCode.vhd:178:47 */ + assign n3934_o = f[6]; + /* T80_MCode.vhd:178:56 */ + assign n3935_o = ~n3934_o; + /* T80_MCode.vhd:178:25 */ + assign n3937_o = n3929_o == 3'b000; + /* T80_MCode.vhd:179:47 */ + assign n3938_o = f[6]; + /* T80_MCode.vhd:179:25 */ + assign n3940_o = n3929_o == 3'b001; + /* T80_MCode.vhd:180:47 */ + assign n3941_o = f[0]; + /* T80_MCode.vhd:180:56 */ + assign n3942_o = ~n3941_o; + /* T80_MCode.vhd:180:25 */ + assign n3944_o = n3929_o == 3'b010; + /* T80_MCode.vhd:181:47 */ + assign n3945_o = f[0]; + /* T80_MCode.vhd:181:25 */ + assign n3947_o = n3929_o == 3'b011; + /* T80_MCode.vhd:182:47 */ + assign n3948_o = f[2]; + /* T80_MCode.vhd:182:56 */ + assign n3949_o = ~n3948_o; + /* T80_MCode.vhd:182:25 */ + assign n3951_o = n3929_o == 3'b100; + /* T80_MCode.vhd:183:47 */ + assign n3952_o = f[2]; + /* T80_MCode.vhd:183:25 */ + assign n3954_o = n3929_o == 3'b101; + /* T80_MCode.vhd:184:47 */ + assign n3955_o = f[7]; + /* T80_MCode.vhd:184:56 */ + assign n3956_o = ~n3955_o; + /* T80_MCode.vhd:184:25 */ + assign n3958_o = n3929_o == 3'b110; + /* T80_MCode.vhd:185:47 */ + assign n3959_o = f[7]; + /* T80_MCode.vhd:185:25 */ + assign n3961_o = n3929_o == 3'b111; + assign n3962_o = {n3961_o, n3958_o, n3954_o, n3951_o, n3947_o, n3944_o, n3940_o, n3937_o}; + /* T80_MCode.vhd:177:25 */ + always @* + case (n3962_o) + 8'b10000000: n3964_o = n3959_o; + 8'b01000000: n3964_o = n3956_o; + 8'b00100000: n3964_o = n3952_o; + 8'b00010000: n3964_o = n3949_o; + 8'b00001000: n3964_o = n3945_o; + 8'b00000100: n3964_o = n3942_o; + 8'b00000010: n3964_o = n3938_o; + 8'b00000001: n3964_o = n3935_o; + default: n3964_o = 1'bX; + endcase + /* T80_MCode.vhd:1258:41 */ + assign n3967_o = n3964_o ? 3'b011 : 3'b001; + /* T80_MCode.vhd:1258:41 */ + assign n3970_o = n3964_o ? 3'b101 : 3'b111; + /* T80_MCode.vhd:1257:33 */ + assign n3972_o = n3927_o == 31'b0000000000000000000000000000001; + /* T80_MCode.vhd:1264:33 */ + assign n3974_o = n3927_o == 31'b0000000000000000000000000000010; + /* T80_MCode.vhd:1268:33 */ + assign n3976_o = n3927_o == 31'b0000000000000000000000000000011; + assign n3977_o = {n3976_o, n3974_o, n3972_o}; + /* T80_MCode.vhd:1256:33 */ + always @* + case (n3977_o) + 3'b100: n3979_o = 3'b011; + 3'b010: n3979_o = 3'b011; + 3'b001: n3979_o = n3967_o; + default: n3979_o = 3'b011; + endcase + /* T80_MCode.vhd:1256:33 */ + always @* + case (n3977_o) + 3'b100: n3982_o = n2200_o; + 3'b010: n3982_o = n2200_o; + 3'b001: n3982_o = 3'b101; + default: n3982_o = n2200_o; + endcase + /* T80_MCode.vhd:1256:33 */ + always @* + case (n3977_o) + 3'b100: n3986_o = 4'b0111; + 3'b010: n3986_o = 4'b0111; + 3'b001: n3986_o = 4'b0000; + default: n3986_o = 4'b0000; + endcase + /* T80_MCode.vhd:1256:33 */ + always @* + case (n3977_o) + 3'b100: n3989_o = 3'b111; + 3'b010: n3989_o = 3'b101; + 3'b001: n3989_o = n3970_o; + default: n3989_o = 3'b111; + endcase + /* T80_MCode.vhd:1256:33 */ + always @* + case (n3977_o) + 3'b100: n3992_o = 1'b1; + 3'b010: n3992_o = 1'b0; + 3'b001: n3992_o = 1'b0; + default: n3992_o = 1'b0; + endcase + /* T80_MCode.vhd:1256:33 */ + always @* + case (n3977_o) + 3'b100: n3995_o = 1'b0; + 3'b010: n3995_o = 1'b1; + 3'b001: n3995_o = 1'b0; + default: n3995_o = 1'b0; + endcase + /* T80_MCode.vhd:1185:17 */ + assign n3997_o = ir == 8'b11000000; + /* T80_MCode.vhd:1185:32 */ + assign n3999_o = ir == 8'b11001000; + /* T80_MCode.vhd:1185:32 */ + assign n4000_o = n3997_o | n3999_o; + /* T80_MCode.vhd:1185:43 */ + assign n4002_o = ir == 8'b11010000; + /* T80_MCode.vhd:1185:43 */ + assign n4003_o = n4000_o | n4002_o; + /* T80_MCode.vhd:1185:54 */ + assign n4005_o = ir == 8'b11011000; + /* T80_MCode.vhd:1185:54 */ + assign n4006_o = n4003_o | n4005_o; + /* T80_MCode.vhd:1185:65 */ + assign n4008_o = ir == 8'b11100000; + /* T80_MCode.vhd:1185:65 */ + assign n4009_o = n4006_o | n4008_o; + /* T80_MCode.vhd:1185:76 */ + assign n4011_o = ir == 8'b11101000; + /* T80_MCode.vhd:1185:76 */ + assign n4012_o = n4009_o | n4011_o; + /* T80_MCode.vhd:1185:87 */ + assign n4014_o = ir == 8'b11110000; + /* T80_MCode.vhd:1185:87 */ + assign n4015_o = n4012_o | n4014_o; + /* T80_MCode.vhd:1185:98 */ + assign n4017_o = ir == 8'b11111000; + /* T80_MCode.vhd:1185:98 */ + assign n4018_o = n4015_o | n4017_o; + /* T80_MCode.vhd:1277:30 */ + assign n4019_o = {28'b0, mcycle}; // uext + /* T80_MCode.vhd:1278:25 */ + assign n4021_o = n4019_o == 31'b0000000000000000000000000000001; + /* T80_MCode.vhd:1283:25 */ + assign n4023_o = n4019_o == 31'b0000000000000000000000000000010; + /* T80_MCode.vhd:1288:25 */ + assign n4025_o = n4019_o == 31'b0000000000000000000000000000011; + assign n4026_o = {n4025_o, n4023_o, n4021_o}; + /* T80_MCode.vhd:1277:25 */ + always @* + case (n4026_o) + 3'b100: n4028_o = n2200_o; + 3'b010: n4028_o = n2200_o; + 3'b001: n4028_o = 3'b101; + default: n4028_o = n2200_o; + endcase + /* T80_MCode.vhd:1277:25 */ + always @* + case (n4026_o) + 3'b100: n4032_o = 4'b0000; + 3'b010: n4032_o = 4'b1111; + 3'b001: n4032_o = 4'b1111; + default: n4032_o = 4'b0000; + endcase + /* T80_MCode.vhd:1277:25 */ + always @* + case (n4026_o) + 3'b100: n4036_o = 4'b0000; + 3'b010: n4036_o = 4'b1100; + 3'b001: n4036_o = 4'b1101; + default: n4036_o = 4'b0000; + endcase + /* T80_MCode.vhd:1277:25 */ + always @* + case (n4026_o) + 3'b100: n4040_o = 3'b111; + 3'b010: n4040_o = 3'b101; + 3'b001: n4040_o = 3'b101; + default: n4040_o = 3'b111; + endcase + /* T80_MCode.vhd:1277:25 */ + always @* + case (n4026_o) + 3'b100: n4043_o = 1'b1; + 3'b010: n4043_o = 1'b0; + 3'b001: n4043_o = 1'b0; + default: n4043_o = 1'b0; + endcase + /* T80_MCode.vhd:1277:25 */ + always @* + case (n4026_o) + 3'b100: n4047_o = 1'b1; + 3'b010: n4047_o = 1'b1; + 3'b001: n4047_o = 1'b0; + default: n4047_o = 1'b0; + endcase + /* T80_MCode.vhd:1274:17 */ + assign n4049_o = ir == 8'b11000111; + /* T80_MCode.vhd:1274:32 */ + assign n4051_o = ir == 8'b11001111; + /* T80_MCode.vhd:1274:32 */ + assign n4052_o = n4049_o | n4051_o; + /* T80_MCode.vhd:1274:43 */ + assign n4054_o = ir == 8'b11010111; + /* T80_MCode.vhd:1274:43 */ + assign n4055_o = n4052_o | n4054_o; + /* T80_MCode.vhd:1274:54 */ + assign n4057_o = ir == 8'b11011111; + /* T80_MCode.vhd:1274:54 */ + assign n4058_o = n4055_o | n4057_o; + /* T80_MCode.vhd:1274:65 */ + assign n4060_o = ir == 8'b11100111; + /* T80_MCode.vhd:1274:65 */ + assign n4061_o = n4058_o | n4060_o; + /* T80_MCode.vhd:1274:76 */ + assign n4063_o = ir == 8'b11101111; + /* T80_MCode.vhd:1274:76 */ + assign n4064_o = n4061_o | n4063_o; + /* T80_MCode.vhd:1274:87 */ + assign n4066_o = ir == 8'b11110111; + /* T80_MCode.vhd:1274:87 */ + assign n4067_o = n4064_o | n4066_o; + /* T80_MCode.vhd:1274:98 */ + assign n4069_o = ir == 8'b11111111; + /* T80_MCode.vhd:1274:98 */ + assign n4070_o = n4067_o | n4069_o; + /* T80_MCode.vhd:1299:38 */ + assign n4071_o = {28'b0, mcycle}; // uext + /* T80_MCode.vhd:1300:33 */ + assign n4073_o = n4071_o == 31'b0000000000000000000000000000010; + /* T80_MCode.vhd:1303:33 */ + assign n4075_o = n4071_o == 31'b0000000000000000000000000000011; + assign n4076_o = {n4075_o, n4073_o}; + /* T80_MCode.vhd:1299:33 */ + always @* + case (n4076_o) + 2'b10: n4079_o = 1'b0; + 2'b01: n4079_o = 1'b1; + default: n4079_o = 1'b0; + endcase + /* T80_MCode.vhd:1299:33 */ + always @* + case (n4076_o) + 2'b10: n4082_o = 1'b1; + 2'b01: n4082_o = 1'b0; + default: n4082_o = 1'b0; + endcase + /* T80_MCode.vhd:1299:33 */ + always @* + case (n4076_o) + 2'b10: n4085_o = 3'b111; + 2'b01: n4085_o = 3'b100; + default: n4085_o = 3'b111; + endcase + /* T80_MCode.vhd:1299:33 */ + always @* + case (n4076_o) + 2'b10: n4088_o = 1'b1; + 2'b01: n4088_o = 1'b0; + default: n4088_o = 1'b0; + endcase + /* T80_MCode.vhd:1295:17 */ + assign n4090_o = ir == 8'b11011011; + /* T80_MCode.vhd:1313:38 */ + assign n4091_o = {28'b0, mcycle}; // uext + /* T80_MCode.vhd:1314:33 */ + assign n4093_o = n4091_o == 31'b0000000000000000000000000000010; + /* T80_MCode.vhd:1318:33 */ + assign n4095_o = n4091_o == 31'b0000000000000000000000000000011; + assign n4096_o = {n4095_o, n4093_o}; + /* T80_MCode.vhd:1313:33 */ + always @* + case (n4096_o) + 2'b10: n4099_o = 1'b0; + 2'b01: n4099_o = 1'b1; + default: n4099_o = 1'b0; + endcase + /* T80_MCode.vhd:1313:33 */ + always @* + case (n4096_o) + 2'b10: n4102_o = 4'b0000; + 2'b01: n4102_o = 4'b0111; + default: n4102_o = 4'b0000; + endcase + /* T80_MCode.vhd:1313:33 */ + always @* + case (n4096_o) + 2'b10: n4105_o = 3'b111; + 2'b01: n4105_o = 3'b100; + default: n4105_o = 3'b111; + endcase + /* T80_MCode.vhd:1313:33 */ + always @* + case (n4096_o) + 2'b10: n4108_o = 1'b1; + 2'b01: n4108_o = 1'b0; + default: n4108_o = 1'b0; + endcase + /* T80_MCode.vhd:1313:33 */ + always @* + case (n4096_o) + 2'b10: n4111_o = 1'b1; + 2'b01: n4111_o = 1'b0; + default: n4111_o = 1'b0; + endcase + /* T80_MCode.vhd:1309:17 */ + assign n4113_o = ir == 8'b11010011; + /* T80_MCode.vhd:1331:17 */ + assign n4115_o = ir == 8'b11001011; + /* T80_MCode.vhd:1336:17 */ + assign n4117_o = ir == 8'b11101101; + /* T80_MCode.vhd:1341:17 */ + assign n4119_o = ir == 8'b11011101; + /* T80_MCode.vhd:1341:32 */ + assign n4121_o = ir == 8'b11111101; + /* T80_MCode.vhd:1341:32 */ + assign n4122_o = n4119_o | n4121_o; + assign n4123_o = {n4122_o, n4117_o, n4115_o, n4113_o, n4090_o, n4070_o, n4018_o, n3925_o, n3901_o, n3785_o, n3742_o, n3702_o, n3700_o, n3674_o, n3647_o, n3621_o, n3594_o, n3575_o, n3493_o, n3472_o, n3460_o, n3448_o, n3436_o, n3347_o, n3345_o, n3343_o, n3341_o, n3242_o, n3240_o, n3238_o, n3236_o, n3233_o, n3198_o, n3178_o, n3143_o, n3123_o, n3084_o, n3041_o, n2873_o, n2824_o, n2822_o, n2820_o, n2818_o, n2765_o, n2716_o, n2714_o, n2677_o, n2640_o, n2593_o, n2564_o, n2544_o, n2524_o, n2501_o, n2487_o, n2473_o, n2451_o, n2414_o, n2380_o, n2349_o}; + /* T80_MCode.vhd:265:17 */ + always @* + case (n4123_o) + 59'b10000000000000000000000000000000000000000000000000000000000: n4156_o = 3'b001; + 59'b01000000000000000000000000000000000000000000000000000000000: n4156_o = 3'b001; + 59'b00100000000000000000000000000000000000000000000000000000000: n4156_o = 3'b001; + 59'b00010000000000000000000000000000000000000000000000000000000: n4156_o = 3'b011; + 59'b00001000000000000000000000000000000000000000000000000000000: n4156_o = 3'b011; + 59'b00000100000000000000000000000000000000000000000000000000000: n4156_o = 3'b011; + 59'b00000010000000000000000000000000000000000000000000000000000: n4156_o = n3979_o; + 59'b00000001000000000000000000000000000000000000000000000000000: n4156_o = 3'b011; + 59'b00000000100000000000000000000000000000000000000000000000000: n4156_o = n3850_o; + 59'b00000000010000000000000000000000000000000000000000000000000: n4156_o = 3'b101; + 59'b00000000001000000000000000000000000000000000000000000000000: n4156_o = 3'b011; + 59'b00000000000100000000000000000000000000000000000000000000000: n4156_o = 3'b001; + 59'b00000000000010000000000000000000000000000000000000000000000: n4156_o = n3686_o; + 59'b00000000000001000000000000000000000000000000000000000000000: n4156_o = n3660_o; + 59'b00000000000000100000000000000000000000000000000000000000000: n4156_o = n3633_o; + 59'b00000000000000010000000000000000000000000000000000000000000: n4156_o = n3607_o; + 59'b00000000000000001000000000000000000000000000000000000000000: n4156_o = 3'b011; + 59'b00000000000000000100000000000000000000000000000000000000000: n4156_o = 3'b011; + 59'b00000000000000000010000000000000000000000000000000000000000: n4156_o = 3'b011; + 59'b00000000000000000001000000000000000000000000000000000000000: n4156_o = 3'b001; + 59'b00000000000000000000100000000000000000000000000000000000000: n4156_o = 3'b001; + 59'b00000000000000000000010000000000000000000000000000000000000: n4156_o = 3'b001; + 59'b00000000000000000000001000000000000000000000000000000000000: n4156_o = 3'b011; + 59'b00000000000000000000000100000000000000000000000000000000000: n4156_o = 3'b001; + 59'b00000000000000000000000010000000000000000000000000000000000: n4156_o = 3'b001; + 59'b00000000000000000000000001000000000000000000000000000000000: n4156_o = 3'b001; + 59'b00000000000000000000000000100000000000000000000000000000000: n4156_o = n3328_o; + 59'b00000000000000000000000000010000000000000000000000000000000: n4156_o = 3'b001; + 59'b00000000000000000000000000001000000000000000000000000000000: n4156_o = 3'b001; + 59'b00000000000000000000000000000100000000000000000000000000000: n4156_o = 3'b001; + 59'b00000000000000000000000000000010000000000000000000000000000: n4156_o = 3'b001; + 59'b00000000000000000000000000000001000000000000000000000000000: n4156_o = 3'b011; + 59'b00000000000000000000000000000000100000000000000000000000000: n4156_o = 3'b001; + 59'b00000000000000000000000000000000010000000000000000000000000: n4156_o = 3'b011; + 59'b00000000000000000000000000000000001000000000000000000000000: n4156_o = 3'b001; + 59'b00000000000000000000000000000000000100000000000000000000000: n4156_o = 3'b010; + 59'b00000000000000000000000000000000000010000000000000000000000: n4156_o = 3'b010; + 59'b00000000000000000000000000000000000001000000000000000000000: n4156_o = 3'b001; + 59'b00000000000000000000000000000000000000100000000000000000000: n4156_o = 3'b101; + 59'b00000000000000000000000000000000000000010000000000000000000: n4156_o = 3'b001; + 59'b00000000000000000000000000000000000000001000000000000000000: n4156_o = 3'b001; + 59'b00000000000000000000000000000000000000000100000000000000000: n4156_o = 3'b001; + 59'b00000000000000000000000000000000000000000010000000000000000: n4156_o = 3'b011; + 59'b00000000000000000000000000000000000000000001000000000000000: n4156_o = 3'b011; + 59'b00000000000000000000000000000000000000000000100000000000000: n4156_o = 3'b001; + 59'b00000000000000000000000000000000000000000000010000000000000: n4156_o = 3'b101; + 59'b00000000000000000000000000000000000000000000001000000000000: n4156_o = 3'b101; + 59'b00000000000000000000000000000000000000000000000100000000000: n4156_o = 3'b011; + 59'b00000000000000000000000000000000000000000000000010000000000: n4156_o = 3'b100; + 59'b00000000000000000000000000000000000000000000000001000000000: n4156_o = 3'b010; + 59'b00000000000000000000000000000000000000000000000000100000000: n4156_o = 3'b010; + 59'b00000000000000000000000000000000000000000000000000010000000: n4156_o = 3'b100; + 59'b00000000000000000000000000000000000000000000000000001000000: n4156_o = 3'b010; + 59'b00000000000000000000000000000000000000000000000000000100000: n4156_o = 3'b010; + 59'b00000000000000000000000000000000000000000000000000000010000: n4156_o = 3'b011; + 59'b00000000000000000000000000000000000000000000000000000001000: n4156_o = 3'b010; + 59'b00000000000000000000000000000000000000000000000000000000100: n4156_o = 3'b010; + 59'b00000000000000000000000000000000000000000000000000000000010: n4156_o = 3'b010; + 59'b00000000000000000000000000000000000000000000000000000000001: n4156_o = 3'b001; + default: n4156_o = 3'bX; + endcase + /* T80_MCode.vhd:265:17 */ + always @* + case (n4123_o) + 59'b10000000000000000000000000000000000000000000000000000000000: n4161_o = n2200_o; + 59'b01000000000000000000000000000000000000000000000000000000000: n4161_o = n2200_o; + 59'b00100000000000000000000000000000000000000000000000000000000: n4161_o = n2200_o; + 59'b00010000000000000000000000000000000000000000000000000000000: n4161_o = n2200_o; + 59'b00001000000000000000000000000000000000000000000000000000000: n4161_o = n2200_o; + 59'b00000100000000000000000000000000000000000000000000000000000: n4161_o = n4028_o; + 59'b00000010000000000000000000000000000000000000000000000000000: n4161_o = n3982_o; + 59'b00000001000000000000000000000000000000000000000000000000000: n4161_o = n2200_o; + 59'b00000000100000000000000000000000000000000000000000000000000: n4161_o = n3852_o; + 59'b00000000010000000000000000000000000000000000000000000000000: n4161_o = n3754_o; + 59'b00000000001000000000000000000000000000000000000000000000000: n4161_o = n3714_o; + 59'b00000000000100000000000000000000000000000000000000000000000: n4161_o = n2200_o; + 59'b00000000000010000000000000000000000000000000000000000000000: n4161_o = n3689_o; + 59'b00000000000001000000000000000000000000000000000000000000000: n4161_o = n3663_o; + 59'b00000000000000100000000000000000000000000000000000000000000: n4161_o = n3636_o; + 59'b00000000000000010000000000000000000000000000000000000000000: n4161_o = n3610_o; + 59'b00000000000000001000000000000000000000000000000000000000000: n4161_o = n3583_o; + 59'b00000000000000000100000000000000000000000000000000000000000: n4161_o = n2200_o; + 59'b00000000000000000010000000000000000000000000000000000000000: n4161_o = n2200_o; + 59'b00000000000000000001000000000000000000000000000000000000000: n4161_o = n2200_o; + 59'b00000000000000000000100000000000000000000000000000000000000: n4161_o = 3'b110; + 59'b00000000000000000000010000000000000000000000000000000000000: n4161_o = 3'b110; + 59'b00000000000000000000001000000000000000000000000000000000000: n4161_o = n3395_o; + 59'b00000000000000000000000100000000000000000000000000000000000: n4161_o = n2200_o; + 59'b00000000000000000000000010000000000000000000000000000000000: n4161_o = n2200_o; + 59'b00000000000000000000000001000000000000000000000000000000000: n4161_o = n2200_o; + 59'b00000000000000000000000000100000000000000000000000000000000: n4161_o = n3329_o; + 59'b00000000000000000000000000010000000000000000000000000000000: n4161_o = n2200_o; + 59'b00000000000000000000000000001000000000000000000000000000000: n4161_o = n2200_o; + 59'b00000000000000000000000000000100000000000000000000000000000: n4161_o = n2200_o; + 59'b00000000000000000000000000000010000000000000000000000000000: n4161_o = n2200_o; + 59'b00000000000000000000000000000001000000000000000000000000000: n4161_o = n3208_o; + 59'b00000000000000000000000000000000100000000000000000000000000: n4161_o = n2200_o; + 59'b00000000000000000000000000000000010000000000000000000000000: n4161_o = n3153_o; + 59'b00000000000000000000000000000000001000000000000000000000000: n4161_o = n2200_o; + 59'b00000000000000000000000000000000000100000000000000000000000: n4161_o = n2200_o; + 59'b00000000000000000000000000000000000010000000000000000000000: n4161_o = n2200_o; + 59'b00000000000000000000000000000000000001000000000000000000000: n4161_o = n2200_o; + 59'b00000000000000000000000000000000000000100000000000000000000: n4161_o = n2839_o; + 59'b00000000000000000000000000000000000000010000000000000000000: n4161_o = n2200_o; + 59'b00000000000000000000000000000000000000001000000000000000000: n4161_o = n2200_o; + 59'b00000000000000000000000000000000000000000100000000000000000: n4161_o = n2200_o; + 59'b00000000000000000000000000000000000000000010000000000000000: n4161_o = n2200_o; + 59'b00000000000000000000000000000000000000000001000000000000000: n4161_o = n2740_o; + 59'b00000000000000000000000000000000000000000000100000000000000: n4161_o = 3'b110; + 59'b00000000000000000000000000000000000000000000010000000000000: n4161_o = n2200_o; + 59'b00000000000000000000000000000000000000000000001000000000000: n4161_o = n2200_o; + 59'b00000000000000000000000000000000000000000000000100000000000: n4161_o = n2200_o; + 59'b00000000000000000000000000000000000000000000000010000000000: n4161_o = n2200_o; + 59'b00000000000000000000000000000000000000000000000001000000000: n4161_o = n2200_o; + 59'b00000000000000000000000000000000000000000000000000100000000: n4161_o = n2200_o; + 59'b00000000000000000000000000000000000000000000000000010000000: n4161_o = n2200_o; + 59'b00000000000000000000000000000000000000000000000000001000000: n4161_o = n2200_o; + 59'b00000000000000000000000000000000000000000000000000000100000: n4161_o = n2200_o; + 59'b00000000000000000000000000000000000000000000000000000010000: n4161_o = n2200_o; + 59'b00000000000000000000000000000000000000000000000000000001000: n4161_o = n2200_o; + 59'b00000000000000000000000000000000000000000000000000000000100: n4161_o = n2200_o; + 59'b00000000000000000000000000000000000000000000000000000000010: n4161_o = n2200_o; + 59'b00000000000000000000000000000000000000000000000000000000001: n4161_o = n2200_o; + default: n4161_o = 3'bX; + endcase + /* T80_MCode.vhd:265:17 */ + always @* + case (n4123_o) + 59'b10000000000000000000000000000000000000000000000000000000000: n4167_o = 2'b11; + 59'b01000000000000000000000000000000000000000000000000000000000: n4167_o = 2'b10; + 59'b00100000000000000000000000000000000000000000000000000000000: n4167_o = 2'b01; + 59'b00010000000000000000000000000000000000000000000000000000000: n4167_o = 2'b00; + 59'b00001000000000000000000000000000000000000000000000000000000: n4167_o = 2'b00; + 59'b00000100000000000000000000000000000000000000000000000000000: n4167_o = 2'b00; + 59'b00000010000000000000000000000000000000000000000000000000000: n4167_o = 2'b00; + 59'b00000001000000000000000000000000000000000000000000000000000: n4167_o = 2'b00; + 59'b00000000100000000000000000000000000000000000000000000000000: n4167_o = 2'b00; + 59'b00000000010000000000000000000000000000000000000000000000000: n4167_o = 2'b00; + 59'b00000000001000000000000000000000000000000000000000000000000: n4167_o = 2'b00; + 59'b00000000000100000000000000000000000000000000000000000000000: n4167_o = 2'b00; + 59'b00000000000010000000000000000000000000000000000000000000000: n4167_o = 2'b00; + 59'b00000000000001000000000000000000000000000000000000000000000: n4167_o = 2'b00; + 59'b00000000000000100000000000000000000000000000000000000000000: n4167_o = 2'b00; + 59'b00000000000000010000000000000000000000000000000000000000000: n4167_o = 2'b00; + 59'b00000000000000001000000000000000000000000000000000000000000: n4167_o = 2'b00; + 59'b00000000000000000100000000000000000000000000000000000000000: n4167_o = 2'b00; + 59'b00000000000000000010000000000000000000000000000000000000000: n4167_o = 2'b00; + 59'b00000000000000000001000000000000000000000000000000000000000: n4167_o = 2'b00; + 59'b00000000000000000000100000000000000000000000000000000000000: n4167_o = 2'b00; + 59'b00000000000000000000010000000000000000000000000000000000000: n4167_o = 2'b00; + 59'b00000000000000000000001000000000000000000000000000000000000: n4167_o = 2'b00; + 59'b00000000000000000000000100000000000000000000000000000000000: n4167_o = 2'b00; + 59'b00000000000000000000000010000000000000000000000000000000000: n4167_o = 2'b00; + 59'b00000000000000000000000001000000000000000000000000000000000: n4167_o = 2'b00; + 59'b00000000000000000000000000100000000000000000000000000000000: n4167_o = 2'b00; + 59'b00000000000000000000000000010000000000000000000000000000000: n4167_o = 2'b00; + 59'b00000000000000000000000000001000000000000000000000000000000: n4167_o = 2'b00; + 59'b00000000000000000000000000000100000000000000000000000000000: n4167_o = 2'b00; + 59'b00000000000000000000000000000010000000000000000000000000000: n4167_o = 2'b00; + 59'b00000000000000000000000000000001000000000000000000000000000: n4167_o = 2'b00; + 59'b00000000000000000000000000000000100000000000000000000000000: n4167_o = 2'b00; + 59'b00000000000000000000000000000000010000000000000000000000000: n4167_o = 2'b00; + 59'b00000000000000000000000000000000001000000000000000000000000: n4167_o = 2'b00; + 59'b00000000000000000000000000000000000100000000000000000000000: n4167_o = 2'b00; + 59'b00000000000000000000000000000000000010000000000000000000000: n4167_o = 2'b00; + 59'b00000000000000000000000000000000000001000000000000000000000: n4167_o = 2'b00; + 59'b00000000000000000000000000000000000000100000000000000000000: n4167_o = 2'b00; + 59'b00000000000000000000000000000000000000010000000000000000000: n4167_o = 2'b00; + 59'b00000000000000000000000000000000000000001000000000000000000: n4167_o = 2'b00; + 59'b00000000000000000000000000000000000000000100000000000000000: n4167_o = 2'b00; + 59'b00000000000000000000000000000000000000000010000000000000000: n4167_o = 2'b00; + 59'b00000000000000000000000000000000000000000001000000000000000: n4167_o = 2'b00; + 59'b00000000000000000000000000000000000000000000100000000000000: n4167_o = 2'b00; + 59'b00000000000000000000000000000000000000000000010000000000000: n4167_o = 2'b00; + 59'b00000000000000000000000000000000000000000000001000000000000: n4167_o = 2'b00; + 59'b00000000000000000000000000000000000000000000000100000000000: n4167_o = 2'b00; + 59'b00000000000000000000000000000000000000000000000010000000000: n4167_o = 2'b00; + 59'b00000000000000000000000000000000000000000000000001000000000: n4167_o = 2'b00; + 59'b00000000000000000000000000000000000000000000000000100000000: n4167_o = 2'b00; + 59'b00000000000000000000000000000000000000000000000000010000000: n4167_o = 2'b00; + 59'b00000000000000000000000000000000000000000000000000001000000: n4167_o = 2'b00; + 59'b00000000000000000000000000000000000000000000000000000100000: n4167_o = 2'b00; + 59'b00000000000000000000000000000000000000000000000000000010000: n4167_o = 2'b00; + 59'b00000000000000000000000000000000000000000000000000000001000: n4167_o = 2'b00; + 59'b00000000000000000000000000000000000000000000000000000000100: n4167_o = 2'b00; + 59'b00000000000000000000000000000000000000000000000000000000010: n4167_o = 2'b00; + 59'b00000000000000000000000000000000000000000000000000000000001: n4167_o = 2'b00; + default: n4167_o = 2'bX; + endcase + /* T80_MCode.vhd:265:17 */ + always @* + case (n4123_o) + 59'b10000000000000000000000000000000000000000000000000000000000: n4170_o = 1'b0; + 59'b01000000000000000000000000000000000000000000000000000000000: n4170_o = 1'b0; + 59'b00100000000000000000000000000000000000000000000000000000000: n4170_o = 1'b0; + 59'b00010000000000000000000000000000000000000000000000000000000: n4170_o = n4099_o; + 59'b00001000000000000000000000000000000000000000000000000000000: n4170_o = n4079_o; + 59'b00000100000000000000000000000000000000000000000000000000000: n4170_o = 1'b0; + 59'b00000010000000000000000000000000000000000000000000000000000: n4170_o = 1'b0; + 59'b00000001000000000000000000000000000000000000000000000000000: n4170_o = 1'b0; + 59'b00000000100000000000000000000000000000000000000000000000000: n4170_o = n3856_o; + 59'b00000000010000000000000000000000000000000000000000000000000: n4170_o = n3758_o; + 59'b00000000001000000000000000000000000000000000000000000000000: n4170_o = n3717_o; + 59'b00000000000100000000000000000000000000000000000000000000000: n4170_o = 1'b0; + 59'b00000000000010000000000000000000000000000000000000000000000: n4170_o = n3692_o; + 59'b00000000000001000000000000000000000000000000000000000000000: n4170_o = n3666_o; + 59'b00000000000000100000000000000000000000000000000000000000000: n4170_o = n3639_o; + 59'b00000000000000010000000000000000000000000000000000000000000: n4170_o = n3613_o; + 59'b00000000000000001000000000000000000000000000000000000000000: n4170_o = n3586_o; + 59'b00000000000000000100000000000000000000000000000000000000000: n4170_o = n3544_o; + 59'b00000000000000000010000000000000000000000000000000000000000: n4170_o = n3482_o; + 59'b00000000000000000001000000000000000000000000000000000000000: n4170_o = 1'b0; + 59'b00000000000000000000100000000000000000000000000000000000000: n4170_o = 1'b0; + 59'b00000000000000000000010000000000000000000000000000000000000: n4170_o = 1'b0; + 59'b00000000000000000000001000000000000000000000000000000000000: n4170_o = 1'b0; + 59'b00000000000000000000000100000000000000000000000000000000000: n4170_o = 1'b0; + 59'b00000000000000000000000010000000000000000000000000000000000: n4170_o = 1'b0; + 59'b00000000000000000000000001000000000000000000000000000000000: n4170_o = 1'b0; + 59'b00000000000000000000000000100000000000000000000000000000000: n4170_o = n3331_o; + 59'b00000000000000000000000000010000000000000000000000000000000: n4170_o = 1'b0; + 59'b00000000000000000000000000001000000000000000000000000000000: n4170_o = 1'b0; + 59'b00000000000000000000000000000100000000000000000000000000000: n4170_o = 1'b0; + 59'b00000000000000000000000000000010000000000000000000000000000: n4170_o = 1'b0; + 59'b00000000000000000000000000000001000000000000000000000000000: n4170_o = 1'b0; + 59'b00000000000000000000000000000000100000000000000000000000000: n4170_o = 1'b0; + 59'b00000000000000000000000000000000010000000000000000000000000: n4170_o = 1'b0; + 59'b00000000000000000000000000000000001000000000000000000000000: n4170_o = 1'b0; + 59'b00000000000000000000000000000000000100000000000000000000000: n4170_o = n3090_o; + 59'b00000000000000000000000000000000000010000000000000000000000: n4170_o = 1'b0; + 59'b00000000000000000000000000000000000001000000000000000000000: n4170_o = 1'b0; + 59'b00000000000000000000000000000000000000100000000000000000000: n4170_o = 1'b0; + 59'b00000000000000000000000000000000000000010000000000000000000: n4170_o = 1'b0; + 59'b00000000000000000000000000000000000000001000000000000000000: n4170_o = 1'b0; + 59'b00000000000000000000000000000000000000000100000000000000000: n4170_o = 1'b0; + 59'b00000000000000000000000000000000000000000010000000000000000: n4170_o = 1'b0; + 59'b00000000000000000000000000000000000000000001000000000000000: n4170_o = 1'b0; + 59'b00000000000000000000000000000000000000000000100000000000000: n4170_o = 1'b0; + 59'b00000000000000000000000000000000000000000000010000000000000: n4170_o = n2691_o; + 59'b00000000000000000000000000000000000000000000001000000000000: n4170_o = n2656_o; + 59'b00000000000000000000000000000000000000000000000100000000000: n4170_o = n2621_o; + 59'b00000000000000000000000000000000000000000000000010000000000: n4170_o = n2576_o; + 59'b00000000000000000000000000000000000000000000000001000000000: n4170_o = 1'b0; + 59'b00000000000000000000000000000000000000000000000000100000000: n4170_o = 1'b0; + 59'b00000000000000000000000000000000000000000000000000010000000: n4170_o = n2513_o; + 59'b00000000000000000000000000000000000000000000000000001000000: n4170_o = 1'b0; + 59'b00000000000000000000000000000000000000000000000000000100000: n4170_o = 1'b0; + 59'b00000000000000000000000000000000000000000000000000000010000: n4170_o = n2461_o; + 59'b00000000000000000000000000000000000000000000000000000001000: n4170_o = 1'b0; + 59'b00000000000000000000000000000000000000000000000000000000100: n4170_o = 1'b0; + 59'b00000000000000000000000000000000000000000000000000000000010: n4170_o = n2355_o; + 59'b00000000000000000000000000000000000000000000000000000000001: n4170_o = 1'b0; + default: n4170_o = 1'bX; + endcase + /* T80_MCode.vhd:265:17 */ + always @* + case (n4123_o) + 59'b10000000000000000000000000000000000000000000000000000000000: n4173_o = 1'b0; + 59'b01000000000000000000000000000000000000000000000000000000000: n4173_o = 1'b0; + 59'b00100000000000000000000000000000000000000000000000000000000: n4173_o = 1'b0; + 59'b00010000000000000000000000000000000000000000000000000000000: n4173_o = 1'b0; + 59'b00001000000000000000000000000000000000000000000000000000000: n4173_o = 1'b0; + 59'b00000100000000000000000000000000000000000000000000000000000: n4173_o = 1'b0; + 59'b00000010000000000000000000000000000000000000000000000000000: n4173_o = 1'b0; + 59'b00000001000000000000000000000000000000000000000000000000000: n4173_o = 1'b0; + 59'b00000000100000000000000000000000000000000000000000000000000: n4173_o = 1'b0; + 59'b00000000010000000000000000000000000000000000000000000000000: n4173_o = 1'b0; + 59'b00000000001000000000000000000000000000000000000000000000000: n4173_o = 1'b0; + 59'b00000000000100000000000000000000000000000000000000000000000: n4173_o = 1'b0; + 59'b00000000000010000000000000000000000000000000000000000000000: n4173_o = 1'b0; + 59'b00000000000001000000000000000000000000000000000000000000000: n4173_o = 1'b0; + 59'b00000000000000100000000000000000000000000000000000000000000: n4173_o = 1'b0; + 59'b00000000000000010000000000000000000000000000000000000000000: n4173_o = 1'b0; + 59'b00000000000000001000000000000000000000000000000000000000000: n4173_o = 1'b0; + 59'b00000000000000000100000000000000000000000000000000000000000: n4173_o = 1'b0; + 59'b00000000000000000010000000000000000000000000000000000000000: n4173_o = 1'b0; + 59'b00000000000000000001000000000000000000000000000000000000000: n4173_o = 1'b0; + 59'b00000000000000000000100000000000000000000000000000000000000: n4173_o = 1'b0; + 59'b00000000000000000000010000000000000000000000000000000000000: n4173_o = 1'b0; + 59'b00000000000000000000001000000000000000000000000000000000000: n4173_o = 1'b0; + 59'b00000000000000000000000100000000000000000000000000000000000: n4173_o = 1'b0; + 59'b00000000000000000000000010000000000000000000000000000000000: n4173_o = 1'b0; + 59'b00000000000000000000000001000000000000000000000000000000000: n4173_o = 1'b0; + 59'b00000000000000000000000000100000000000000000000000000000000: n4173_o = 1'b0; + 59'b00000000000000000000000000010000000000000000000000000000000: n4173_o = 1'b0; + 59'b00000000000000000000000000001000000000000000000000000000000: n4173_o = 1'b0; + 59'b00000000000000000000000000000100000000000000000000000000000: n4173_o = 1'b0; + 59'b00000000000000000000000000000010000000000000000000000000000: n4173_o = 1'b0; + 59'b00000000000000000000000000000001000000000000000000000000000: n4173_o = 1'b0; + 59'b00000000000000000000000000000000100000000000000000000000000: n4173_o = 1'b0; + 59'b00000000000000000000000000000000010000000000000000000000000: n4173_o = 1'b0; + 59'b00000000000000000000000000000000001000000000000000000000000: n4173_o = 1'b0; + 59'b00000000000000000000000000000000000100000000000000000000000: n4173_o = 1'b0; + 59'b00000000000000000000000000000000000010000000000000000000000: n4173_o = 1'b0; + 59'b00000000000000000000000000000000000001000000000000000000000: n4173_o = 1'b0; + 59'b00000000000000000000000000000000000000100000000000000000000: n4173_o = 1'b0; + 59'b00000000000000000000000000000000000000010000000000000000000: n4173_o = 1'b0; + 59'b00000000000000000000000000000000000000001000000000000000000: n4173_o = 1'b0; + 59'b00000000000000000000000000000000000000000100000000000000000: n4173_o = 1'b0; + 59'b00000000000000000000000000000000000000000010000000000000000: n4173_o = 1'b0; + 59'b00000000000000000000000000000000000000000001000000000000000: n4173_o = 1'b0; + 59'b00000000000000000000000000000000000000000000100000000000000: n4173_o = 1'b0; + 59'b00000000000000000000000000000000000000000000010000000000000: n4173_o = n2694_o; + 59'b00000000000000000000000000000000000000000000001000000000000: n4173_o = n2659_o; + 59'b00000000000000000000000000000000000000000000000100000000000: n4173_o = 1'b0; + 59'b00000000000000000000000000000000000000000000000010000000000: n4173_o = 1'b0; + 59'b00000000000000000000000000000000000000000000000001000000000: n4173_o = 1'b0; + 59'b00000000000000000000000000000000000000000000000000100000000: n4173_o = 1'b0; + 59'b00000000000000000000000000000000000000000000000000010000000: n4173_o = 1'b0; + 59'b00000000000000000000000000000000000000000000000000001000000: n4173_o = 1'b0; + 59'b00000000000000000000000000000000000000000000000000000100000: n4173_o = 1'b0; + 59'b00000000000000000000000000000000000000000000000000000010000: n4173_o = 1'b0; + 59'b00000000000000000000000000000000000000000000000000000001000: n4173_o = 1'b0; + 59'b00000000000000000000000000000000000000000000000000000000100: n4173_o = 1'b0; + 59'b00000000000000000000000000000000000000000000000000000000010: n4173_o = 1'b0; + 59'b00000000000000000000000000000000000000000000000000000000001: n4173_o = 1'b0; + default: n4173_o = 1'bX; + endcase + assign n4174_o = n2744_o[1:0]; + assign n4175_o = n2795_o[1:0]; + assign n4176_o = n2843_o[1:0]; + assign n4177_o = n3332_o[1:0]; + assign n4178_o = n3762_o[1:0]; + assign n4179_o = n3859_o[1:0]; + assign n4180_o = n3913_o[1:0]; + assign n4181_o = n3986_o[1:0]; + assign n4182_o = n4032_o[1:0]; + /* T80_MCode.vhd:265:17 */ + always @* + case (n4123_o) + 59'b10000000000000000000000000000000000000000000000000000000000: n4185_o = 2'b00; + 59'b01000000000000000000000000000000000000000000000000000000000: n4185_o = 2'b00; + 59'b00100000000000000000000000000000000000000000000000000000000: n4185_o = 2'b00; + 59'b00010000000000000000000000000000000000000000000000000000000: n4185_o = 2'b00; + 59'b00001000000000000000000000000000000000000000000000000000000: n4185_o = 2'b00; + 59'b00000100000000000000000000000000000000000000000000000000000: n4185_o = n4182_o; + 59'b00000010000000000000000000000000000000000000000000000000000: n4185_o = n4181_o; + 59'b00000001000000000000000000000000000000000000000000000000000: n4185_o = n4180_o; + 59'b00000000100000000000000000000000000000000000000000000000000: n4185_o = n4179_o; + 59'b00000000010000000000000000000000000000000000000000000000000: n4185_o = n4178_o; + 59'b00000000001000000000000000000000000000000000000000000000000: n4185_o = 2'b00; + 59'b00000000000100000000000000000000000000000000000000000000000: n4185_o = 2'b00; + 59'b00000000000010000000000000000000000000000000000000000000000: n4185_o = 2'b00; + 59'b00000000000001000000000000000000000000000000000000000000000: n4185_o = 2'b00; + 59'b00000000000000100000000000000000000000000000000000000000000: n4185_o = 2'b00; + 59'b00000000000000010000000000000000000000000000000000000000000: n4185_o = 2'b00; + 59'b00000000000000001000000000000000000000000000000000000000000: n4185_o = 2'b00; + 59'b00000000000000000100000000000000000000000000000000000000000: n4185_o = 2'b00; + 59'b00000000000000000010000000000000000000000000000000000000000: n4185_o = 2'b00; + 59'b00000000000000000001000000000000000000000000000000000000000: n4185_o = 2'b00; + 59'b00000000000000000000100000000000000000000000000000000000000: n4185_o = n2195_o; + 59'b00000000000000000000010000000000000000000000000000000000000: n4185_o = n2195_o; + 59'b00000000000000000000001000000000000000000000000000000000000: n4185_o = 2'b00; + 59'b00000000000000000000000100000000000000000000000000000000000: n4185_o = 2'b00; + 59'b00000000000000000000000010000000000000000000000000000000000: n4185_o = 2'b00; + 59'b00000000000000000000000001000000000000000000000000000000000: n4185_o = 2'b00; + 59'b00000000000000000000000000100000000000000000000000000000000: n4185_o = n4177_o; + 59'b00000000000000000000000000010000000000000000000000000000000: n4185_o = 2'b00; + 59'b00000000000000000000000000001000000000000000000000000000000: n4185_o = 2'b00; + 59'b00000000000000000000000000000100000000000000000000000000000: n4185_o = 2'b00; + 59'b00000000000000000000000000000010000000000000000000000000000: n4185_o = 2'b00; + 59'b00000000000000000000000000000001000000000000000000000000000: n4185_o = 2'b00; + 59'b00000000000000000000000000000000100000000000000000000000000: n4185_o = 2'b00; + 59'b00000000000000000000000000000000010000000000000000000000000: n4185_o = 2'b00; + 59'b00000000000000000000000000000000001000000000000000000000000: n4185_o = 2'b00; + 59'b00000000000000000000000000000000000100000000000000000000000: n4185_o = 2'b00; + 59'b00000000000000000000000000000000000010000000000000000000000: n4185_o = 2'b00; + 59'b00000000000000000000000000000000000001000000000000000000000: n4185_o = 2'b00; + 59'b00000000000000000000000000000000000000100000000000000000000: n4185_o = n4176_o; + 59'b00000000000000000000000000000000000000010000000000000000000: n4185_o = 2'b00; + 59'b00000000000000000000000000000000000000001000000000000000000: n4185_o = 2'b00; + 59'b00000000000000000000000000000000000000000100000000000000000: n4185_o = 2'b00; + 59'b00000000000000000000000000000000000000000010000000000000000: n4185_o = n4175_o; + 59'b00000000000000000000000000000000000000000001000000000000000: n4185_o = n4174_o; + 59'b00000000000000000000000000000000000000000000100000000000000: n4185_o = 2'b00; + 59'b00000000000000000000000000000000000000000000010000000000000: n4185_o = 2'b00; + 59'b00000000000000000000000000000000000000000000001000000000000: n4185_o = 2'b00; + 59'b00000000000000000000000000000000000000000000000100000000000: n4185_o = 2'b00; + 59'b00000000000000000000000000000000000000000000000010000000000: n4185_o = 2'b00; + 59'b00000000000000000000000000000000000000000000000001000000000: n4185_o = 2'b00; + 59'b00000000000000000000000000000000000000000000000000100000000: n4185_o = 2'b00; + 59'b00000000000000000000000000000000000000000000000000010000000: n4185_o = 2'b00; + 59'b00000000000000000000000000000000000000000000000000001000000: n4185_o = 2'b00; + 59'b00000000000000000000000000000000000000000000000000000100000: n4185_o = 2'b00; + 59'b00000000000000000000000000000000000000000000000000000010000: n4185_o = 2'b00; + 59'b00000000000000000000000000000000000000000000000000000001000: n4185_o = 2'b00; + 59'b00000000000000000000000000000000000000000000000000000000100: n4185_o = 2'b00; + 59'b00000000000000000000000000000000000000000000000000000000010: n4185_o = 2'b00; + 59'b00000000000000000000000000000000000000000000000000000000001: n4185_o = 2'b00; + default: n4185_o = 2'bX; + endcase + assign n4186_o = n2744_o[3:2]; + assign n4187_o = n2795_o[3:2]; + assign n4188_o = n2843_o[3:2]; + assign n4189_o = n3332_o[3:2]; + assign n4190_o = n3762_o[3:2]; + assign n4191_o = n3859_o[3:2]; + assign n4192_o = n3913_o[3:2]; + assign n4193_o = n3986_o[3:2]; + assign n4194_o = n4032_o[3:2]; + /* T80_MCode.vhd:265:17 */ + always @* + case (n4123_o) + 59'b10000000000000000000000000000000000000000000000000000000000: n4197_o = 2'b00; + 59'b01000000000000000000000000000000000000000000000000000000000: n4197_o = 2'b00; + 59'b00100000000000000000000000000000000000000000000000000000000: n4197_o = 2'b00; + 59'b00010000000000000000000000000000000000000000000000000000000: n4197_o = 2'b00; + 59'b00001000000000000000000000000000000000000000000000000000000: n4197_o = 2'b00; + 59'b00000100000000000000000000000000000000000000000000000000000: n4197_o = n4194_o; + 59'b00000010000000000000000000000000000000000000000000000000000: n4197_o = n4193_o; + 59'b00000001000000000000000000000000000000000000000000000000000: n4197_o = n4192_o; + 59'b00000000100000000000000000000000000000000000000000000000000: n4197_o = n4191_o; + 59'b00000000010000000000000000000000000000000000000000000000000: n4197_o = n4190_o; + 59'b00000000001000000000000000000000000000000000000000000000000: n4197_o = 2'b00; + 59'b00000000000100000000000000000000000000000000000000000000000: n4197_o = 2'b00; + 59'b00000000000010000000000000000000000000000000000000000000000: n4197_o = 2'b00; + 59'b00000000000001000000000000000000000000000000000000000000000: n4197_o = 2'b00; + 59'b00000000000000100000000000000000000000000000000000000000000: n4197_o = 2'b00; + 59'b00000000000000010000000000000000000000000000000000000000000: n4197_o = 2'b00; + 59'b00000000000000001000000000000000000000000000000000000000000: n4197_o = 2'b00; + 59'b00000000000000000100000000000000000000000000000000000000000: n4197_o = 2'b00; + 59'b00000000000000000010000000000000000000000000000000000000000: n4197_o = 2'b00; + 59'b00000000000000000001000000000000000000000000000000000000000: n4197_o = 2'b00; + 59'b00000000000000000000100000000000000000000000000000000000000: n4197_o = 2'b11; + 59'b00000000000000000000010000000000000000000000000000000000000: n4197_o = 2'b01; + 59'b00000000000000000000001000000000000000000000000000000000000: n4197_o = 2'b00; + 59'b00000000000000000000000100000000000000000000000000000000000: n4197_o = 2'b00; + 59'b00000000000000000000000010000000000000000000000000000000000: n4197_o = 2'b00; + 59'b00000000000000000000000001000000000000000000000000000000000: n4197_o = 2'b00; + 59'b00000000000000000000000000100000000000000000000000000000000: n4197_o = n4189_o; + 59'b00000000000000000000000000010000000000000000000000000000000: n4197_o = 2'b00; + 59'b00000000000000000000000000001000000000000000000000000000000: n4197_o = 2'b00; + 59'b00000000000000000000000000000100000000000000000000000000000: n4197_o = 2'b00; + 59'b00000000000000000000000000000010000000000000000000000000000: n4197_o = 2'b00; + 59'b00000000000000000000000000000001000000000000000000000000000: n4197_o = 2'b00; + 59'b00000000000000000000000000000000100000000000000000000000000: n4197_o = 2'b00; + 59'b00000000000000000000000000000000010000000000000000000000000: n4197_o = 2'b00; + 59'b00000000000000000000000000000000001000000000000000000000000: n4197_o = 2'b00; + 59'b00000000000000000000000000000000000100000000000000000000000: n4197_o = 2'b00; + 59'b00000000000000000000000000000000000010000000000000000000000: n4197_o = 2'b00; + 59'b00000000000000000000000000000000000001000000000000000000000: n4197_o = 2'b00; + 59'b00000000000000000000000000000000000000100000000000000000000: n4197_o = n4188_o; + 59'b00000000000000000000000000000000000000010000000000000000000: n4197_o = 2'b00; + 59'b00000000000000000000000000000000000000001000000000000000000: n4197_o = 2'b00; + 59'b00000000000000000000000000000000000000000100000000000000000: n4197_o = 2'b00; + 59'b00000000000000000000000000000000000000000010000000000000000: n4197_o = n4187_o; + 59'b00000000000000000000000000000000000000000001000000000000000: n4197_o = n4186_o; + 59'b00000000000000000000000000000000000000000000100000000000000: n4197_o = 2'b00; + 59'b00000000000000000000000000000000000000000000010000000000000: n4197_o = 2'b00; + 59'b00000000000000000000000000000000000000000000001000000000000: n4197_o = 2'b00; + 59'b00000000000000000000000000000000000000000000000100000000000: n4197_o = 2'b00; + 59'b00000000000000000000000000000000000000000000000010000000000: n4197_o = 2'b00; + 59'b00000000000000000000000000000000000000000000000001000000000: n4197_o = 2'b00; + 59'b00000000000000000000000000000000000000000000000000100000000: n4197_o = 2'b00; + 59'b00000000000000000000000000000000000000000000000000010000000: n4197_o = 2'b00; + 59'b00000000000000000000000000000000000000000000000000001000000: n4197_o = 2'b00; + 59'b00000000000000000000000000000000000000000000000000000100000: n4197_o = 2'b00; + 59'b00000000000000000000000000000000000000000000000000000010000: n4197_o = 2'b00; + 59'b00000000000000000000000000000000000000000000000000000001000: n4197_o = 2'b00; + 59'b00000000000000000000000000000000000000000000000000000000100: n4197_o = 2'b00; + 59'b00000000000000000000000000000000000000000000000000000000010: n4197_o = 2'b00; + 59'b00000000000000000000000000000000000000000000000000000000001: n4197_o = 2'b00; + default: n4197_o = 2'bX; + endcase + /* T80_MCode.vhd:265:17 */ + always @* + case (n4123_o) + 59'b10000000000000000000000000000000000000000000000000000000000: n4206_o = 1'b0; + 59'b01000000000000000000000000000000000000000000000000000000000: n4206_o = 1'b0; + 59'b00100000000000000000000000000000000000000000000000000000000: n4206_o = 1'b0; + 59'b00010000000000000000000000000000000000000000000000000000000: n4206_o = 1'b0; + 59'b00001000000000000000000000000000000000000000000000000000000: n4206_o = 1'b0; + 59'b00000100000000000000000000000000000000000000000000000000000: n4206_o = 1'b0; + 59'b00000010000000000000000000000000000000000000000000000000000: n4206_o = 1'b0; + 59'b00000001000000000000000000000000000000000000000000000000000: n4206_o = 1'b0; + 59'b00000000100000000000000000000000000000000000000000000000000: n4206_o = 1'b0; + 59'b00000000010000000000000000000000000000000000000000000000000: n4206_o = 1'b0; + 59'b00000000001000000000000000000000000000000000000000000000000: n4206_o = n3720_o; + 59'b00000000000100000000000000000000000000000000000000000000000: n4206_o = 1'b0; + 59'b00000000000010000000000000000000000000000000000000000000000: n4206_o = 1'b0; + 59'b00000000000001000000000000000000000000000000000000000000000: n4206_o = 1'b0; + 59'b00000000000000100000000000000000000000000000000000000000000: n4206_o = 1'b0; + 59'b00000000000000010000000000000000000000000000000000000000000: n4206_o = 1'b0; + 59'b00000000000000001000000000000000000000000000000000000000000: n4206_o = 1'b0; + 59'b00000000000000000100000000000000000000000000000000000000000: n4206_o = 1'b0; + 59'b00000000000000000010000000000000000000000000000000000000000: n4206_o = 1'b0; + 59'b00000000000000000001000000000000000000000000000000000000000: n4206_o = 1'b1; + 59'b00000000000000000000100000000000000000000000000000000000000: n4206_o = 1'b0; + 59'b00000000000000000000010000000000000000000000000000000000000: n4206_o = 1'b0; + 59'b00000000000000000000001000000000000000000000000000000000000: n4206_o = n3399_o; + 59'b00000000000000000000000100000000000000000000000000000000000: n4206_o = 1'b0; + 59'b00000000000000000000000010000000000000000000000000000000000: n4206_o = 1'b0; + 59'b00000000000000000000000001000000000000000000000000000000000: n4206_o = 1'b0; + 59'b00000000000000000000000000100000000000000000000000000000000: n4206_o = 1'b0; + 59'b00000000000000000000000000010000000000000000000000000000000: n4206_o = 1'b0; + 59'b00000000000000000000000000001000000000000000000000000000000: n4206_o = 1'b0; + 59'b00000000000000000000000000000100000000000000000000000000000: n4206_o = 1'b0; + 59'b00000000000000000000000000000010000000000000000000000000000: n4206_o = 1'b1; + 59'b00000000000000000000000000000001000000000000000000000000000: n4206_o = n3211_o; + 59'b00000000000000000000000000000000100000000000000000000000000: n4206_o = 1'b1; + 59'b00000000000000000000000000000000010000000000000000000000000: n4206_o = n3156_o; + 59'b00000000000000000000000000000000001000000000000000000000000: n4206_o = 1'b1; + 59'b00000000000000000000000000000000000100000000000000000000000: n4206_o = n3093_o; + 59'b00000000000000000000000000000000000010000000000000000000000: n4206_o = n3051_o; + 59'b00000000000000000000000000000000000001000000000000000000000: n4206_o = 1'b1; + 59'b00000000000000000000000000000000000000100000000000000000000: n4206_o = n2847_o; + 59'b00000000000000000000000000000000000000010000000000000000000: n4206_o = 1'b0; + 59'b00000000000000000000000000000000000000001000000000000000000: n4206_o = 1'b0; + 59'b00000000000000000000000000000000000000000100000000000000000: n4206_o = 1'b0; + 59'b00000000000000000000000000000000000000000010000000000000000: n4206_o = n2799_o; + 59'b00000000000000000000000000000000000000000001000000000000000: n4206_o = 1'b0; + 59'b00000000000000000000000000000000000000000000100000000000000: n4206_o = 1'b0; + 59'b00000000000000000000000000000000000000000000010000000000000: n4206_o = 1'b0; + 59'b00000000000000000000000000000000000000000000001000000000000: n4206_o = n2663_o; + 59'b00000000000000000000000000000000000000000000000100000000000: n4206_o = n2625_o; + 59'b00000000000000000000000000000000000000000000000010000000000: n4206_o = 1'b0; + 59'b00000000000000000000000000000000000000000000000001000000000: n4206_o = 1'b0; + 59'b00000000000000000000000000000000000000000000000000100000000: n4206_o = 1'b0; + 59'b00000000000000000000000000000000000000000000000000010000000: n4206_o = 1'b0; + 59'b00000000000000000000000000000000000000000000000000001000000: n4206_o = 1'b0; + 59'b00000000000000000000000000000000000000000000000000000100000: n4206_o = 1'b0; + 59'b00000000000000000000000000000000000000000000000000000010000: n4206_o = 1'b0; + 59'b00000000000000000000000000000000000000000000000000000001000: n4206_o = 1'b0; + 59'b00000000000000000000000000000000000000000000000000000000100: n4206_o = n2389_o; + 59'b00000000000000000000000000000000000000000000000000000000010: n4206_o = n2358_o; + 59'b00000000000000000000000000000000000000000000000000000000001: n4206_o = 1'b1; + default: n4206_o = 1'bX; + endcase + /* T80_MCode.vhd:265:17 */ + always @* + case (n4123_o) + 59'b10000000000000000000000000000000000000000000000000000000000: n4209_o = 1'b0; + 59'b01000000000000000000000000000000000000000000000000000000000: n4209_o = 1'b0; + 59'b00100000000000000000000000000000000000000000000000000000000: n4209_o = 1'b0; + 59'b00010000000000000000000000000000000000000000000000000000000: n4209_o = 1'b0; + 59'b00001000000000000000000000000000000000000000000000000000000: n4209_o = n4082_o; + 59'b00000100000000000000000000000000000000000000000000000000000: n4209_o = 1'b0; + 59'b00000010000000000000000000000000000000000000000000000000000: n4209_o = 1'b0; + 59'b00000001000000000000000000000000000000000000000000000000000: n4209_o = 1'b0; + 59'b00000000100000000000000000000000000000000000000000000000000: n4209_o = 1'b0; + 59'b00000000010000000000000000000000000000000000000000000000000: n4209_o = 1'b0; + 59'b00000000001000000000000000000000000000000000000000000000000: n4209_o = 1'b0; + 59'b00000000000100000000000000000000000000000000000000000000000: n4209_o = 1'b0; + 59'b00000000000010000000000000000000000000000000000000000000000: n4209_o = 1'b0; + 59'b00000000000001000000000000000000000000000000000000000000000: n4209_o = 1'b0; + 59'b00000000000000100000000000000000000000000000000000000000000: n4209_o = 1'b0; + 59'b00000000000000010000000000000000000000000000000000000000000: n4209_o = 1'b0; + 59'b00000000000000001000000000000000000000000000000000000000000: n4209_o = 1'b0; + 59'b00000000000000000100000000000000000000000000000000000000000: n4209_o = 1'b0; + 59'b00000000000000000010000000000000000000000000000000000000000: n4209_o = 1'b0; + 59'b00000000000000000001000000000000000000000000000000000000000: n4209_o = 1'b0; + 59'b00000000000000000000100000000000000000000000000000000000000: n4209_o = 1'b0; + 59'b00000000000000000000010000000000000000000000000000000000000: n4209_o = 1'b0; + 59'b00000000000000000000001000000000000000000000000000000000000: n4209_o = 1'b0; + 59'b00000000000000000000000100000000000000000000000000000000000: n4209_o = 1'b0; + 59'b00000000000000000000000010000000000000000000000000000000000: n4209_o = 1'b0; + 59'b00000000000000000000000001000000000000000000000000000000000: n4209_o = 1'b0; + 59'b00000000000000000000000000100000000000000000000000000000000: n4209_o = 1'b0; + 59'b00000000000000000000000000010000000000000000000000000000000: n4209_o = 1'b0; + 59'b00000000000000000000000000001000000000000000000000000000000: n4209_o = 1'b0; + 59'b00000000000000000000000000000100000000000000000000000000000: n4209_o = 1'b0; + 59'b00000000000000000000000000000010000000000000000000000000000: n4209_o = 1'b0; + 59'b00000000000000000000000000000001000000000000000000000000000: n4209_o = 1'b0; + 59'b00000000000000000000000000000000100000000000000000000000000: n4209_o = 1'b0; + 59'b00000000000000000000000000000000010000000000000000000000000: n4209_o = 1'b0; + 59'b00000000000000000000000000000000001000000000000000000000000: n4209_o = 1'b0; + 59'b00000000000000000000000000000000000100000000000000000000000: n4209_o = 1'b0; + 59'b00000000000000000000000000000000000010000000000000000000000: n4209_o = 1'b0; + 59'b00000000000000000000000000000000000001000000000000000000000: n4209_o = 1'b0; + 59'b00000000000000000000000000000000000000100000000000000000000: n4209_o = 1'b0; + 59'b00000000000000000000000000000000000000010000000000000000000: n4209_o = 1'b0; + 59'b00000000000000000000000000000000000000001000000000000000000: n4209_o = 1'b0; + 59'b00000000000000000000000000000000000000000100000000000000000: n4209_o = 1'b0; + 59'b00000000000000000000000000000000000000000010000000000000000: n4209_o = 1'b0; + 59'b00000000000000000000000000000000000000000001000000000000000: n4209_o = 1'b0; + 59'b00000000000000000000000000000000000000000000100000000000000: n4209_o = 1'b0; + 59'b00000000000000000000000000000000000000000000010000000000000: n4209_o = 1'b0; + 59'b00000000000000000000000000000000000000000000001000000000000: n4209_o = 1'b0; + 59'b00000000000000000000000000000000000000000000000100000000000: n4209_o = 1'b0; + 59'b00000000000000000000000000000000000000000000000010000000000: n4209_o = 1'b0; + 59'b00000000000000000000000000000000000000000000000001000000000: n4209_o = 1'b0; + 59'b00000000000000000000000000000000000000000000000000100000000: n4209_o = 1'b0; + 59'b00000000000000000000000000000000000000000000000000010000000: n4209_o = n2516_o; + 59'b00000000000000000000000000000000000000000000000000001000000: n4209_o = n2496_o; + 59'b00000000000000000000000000000000000000000000000000000100000: n4209_o = n2482_o; + 59'b00000000000000000000000000000000000000000000000000000010000: n4209_o = 1'b0; + 59'b00000000000000000000000000000000000000000000000000000001000: n4209_o = 1'b0; + 59'b00000000000000000000000000000000000000000000000000000000100: n4209_o = 1'b0; + 59'b00000000000000000000000000000000000000000000000000000000010: n4209_o = 1'b0; + 59'b00000000000000000000000000000000000000000000000000000000001: n4209_o = 1'b0; + default: n4209_o = 1'bX; + endcase + assign n4210_o = n2851_o[2:0]; + /* T80_MCode.vhd:265:17 */ + always @* + case (n4123_o) + 59'b10000000000000000000000000000000000000000000000000000000000: n4213_o = 3'b000; + 59'b01000000000000000000000000000000000000000000000000000000000: n4213_o = 3'b000; + 59'b00100000000000000000000000000000000000000000000000000000000: n4213_o = 3'b000; + 59'b00010000000000000000000000000000000000000000000000000000000: n4213_o = 3'b000; + 59'b00001000000000000000000000000000000000000000000000000000000: n4213_o = 3'b000; + 59'b00000100000000000000000000000000000000000000000000000000000: n4213_o = 3'b000; + 59'b00000010000000000000000000000000000000000000000000000000000: n4213_o = 3'b000; + 59'b00000001000000000000000000000000000000000000000000000000000: n4213_o = 3'b000; + 59'b00000000100000000000000000000000000000000000000000000000000: n4213_o = 3'b000; + 59'b00000000010000000000000000000000000000000000000000000000000: n4213_o = 3'b000; + 59'b00000000001000000000000000000000000000000000000000000000000: n4213_o = n3722_o; + 59'b00000000000100000000000000000000000000000000000000000000000: n4213_o = 3'b000; + 59'b00000000000010000000000000000000000000000000000000000000000: n4213_o = 3'b000; + 59'b00000000000001000000000000000000000000000000000000000000000: n4213_o = 3'b000; + 59'b00000000000000100000000000000000000000000000000000000000000: n4213_o = 3'b000; + 59'b00000000000000010000000000000000000000000000000000000000000: n4213_o = 3'b000; + 59'b00000000000000001000000000000000000000000000000000000000000: n4213_o = 3'b000; + 59'b00000000000000000100000000000000000000000000000000000000000: n4213_o = 3'b000; + 59'b00000000000000000010000000000000000000000000000000000000000: n4213_o = 3'b000; + 59'b00000000000000000001000000000000000000000000000000000000000: n4213_o = 3'b111; + 59'b00000000000000000000100000000000000000000000000000000000000: n4213_o = 3'b000; + 59'b00000000000000000000010000000000000000000000000000000000000: n4213_o = 3'b000; + 59'b00000000000000000000001000000000000000000000000000000000000: n4213_o = n3401_o; + 59'b00000000000000000000000100000000000000000000000000000000000: n4213_o = 3'b000; + 59'b00000000000000000000000010000000000000000000000000000000000: n4213_o = 3'b000; + 59'b00000000000000000000000001000000000000000000000000000000000: n4213_o = 3'b000; + 59'b00000000000000000000000000100000000000000000000000000000000: n4213_o = 3'b000; + 59'b00000000000000000000000000010000000000000000000000000000000: n4213_o = 3'b000; + 59'b00000000000000000000000000001000000000000000000000000000000: n4213_o = 3'b000; + 59'b00000000000000000000000000000100000000000000000000000000000: n4213_o = 3'b000; + 59'b00000000000000000000000000000010000000000000000000000000000: n4213_o = 3'b111; + 59'b00000000000000000000000000000001000000000000000000000000000: n4213_o = n3213_o; + 59'b00000000000000000000000000000000100000000000000000000000000: n4213_o = n2193_o; + 59'b00000000000000000000000000000000010000000000000000000000000: n4213_o = n3158_o; + 59'b00000000000000000000000000000000001000000000000000000000000: n4213_o = n2193_o; + 59'b00000000000000000000000000000000000100000000000000000000000: n4213_o = n3095_o; + 59'b00000000000000000000000000000000000010000000000000000000000: n4213_o = n3053_o; + 59'b00000000000000000000000000000000000001000000000000000000000: n4213_o = 3'b111; + 59'b00000000000000000000000000000000000000100000000000000000000: n4213_o = n4210_o; + 59'b00000000000000000000000000000000000000010000000000000000000: n4213_o = 3'b000; + 59'b00000000000000000000000000000000000000001000000000000000000: n4213_o = 3'b000; + 59'b00000000000000000000000000000000000000000100000000000000000: n4213_o = 3'b000; + 59'b00000000000000000000000000000000000000000010000000000000000: n4213_o = n2801_o; + 59'b00000000000000000000000000000000000000000001000000000000000: n4213_o = 3'b000; + 59'b00000000000000000000000000000000000000000000100000000000000: n4213_o = 3'b000; + 59'b00000000000000000000000000000000000000000000010000000000000: n4213_o = 3'b000; + 59'b00000000000000000000000000000000000000000000001000000000000: n4213_o = n2665_o; + 59'b00000000000000000000000000000000000000000000000100000000000: n4213_o = n2627_o; + 59'b00000000000000000000000000000000000000000000000010000000000: n4213_o = 3'b000; + 59'b00000000000000000000000000000000000000000000000001000000000: n4213_o = 3'b000; + 59'b00000000000000000000000000000000000000000000000000100000000: n4213_o = 3'b000; + 59'b00000000000000000000000000000000000000000000000000010000000: n4213_o = 3'b000; + 59'b00000000000000000000000000000000000000000000000000001000000: n4213_o = 3'b000; + 59'b00000000000000000000000000000000000000000000000000000100000: n4213_o = 3'b000; + 59'b00000000000000000000000000000000000000000000000000000010000: n4213_o = 3'b000; + 59'b00000000000000000000000000000000000000000000000000000001000: n4213_o = 3'b000; + 59'b00000000000000000000000000000000000000000000000000000000100: n4213_o = n2391_o; + 59'b00000000000000000000000000000000000000000000000000000000010: n4213_o = n2360_o; + 59'b00000000000000000000000000000000000000000000000000000000001: n4213_o = n2193_o; + default: n4213_o = 3'bX; + endcase + assign n4214_o = n2851_o[3]; + /* T80_MCode.vhd:265:17 */ + always @* + case (n4123_o) + 59'b10000000000000000000000000000000000000000000000000000000000: n4217_o = 1'b0; + 59'b01000000000000000000000000000000000000000000000000000000000: n4217_o = 1'b0; + 59'b00100000000000000000000000000000000000000000000000000000000: n4217_o = 1'b0; + 59'b00010000000000000000000000000000000000000000000000000000000: n4217_o = 1'b0; + 59'b00001000000000000000000000000000000000000000000000000000000: n4217_o = 1'b0; + 59'b00000100000000000000000000000000000000000000000000000000000: n4217_o = 1'b0; + 59'b00000010000000000000000000000000000000000000000000000000000: n4217_o = 1'b0; + 59'b00000001000000000000000000000000000000000000000000000000000: n4217_o = 1'b0; + 59'b00000000100000000000000000000000000000000000000000000000000: n4217_o = 1'b0; + 59'b00000000010000000000000000000000000000000000000000000000000: n4217_o = 1'b0; + 59'b00000000001000000000000000000000000000000000000000000000000: n4217_o = 1'b0; + 59'b00000000000100000000000000000000000000000000000000000000000: n4217_o = 1'b0; + 59'b00000000000010000000000000000000000000000000000000000000000: n4217_o = 1'b0; + 59'b00000000000001000000000000000000000000000000000000000000000: n4217_o = 1'b0; + 59'b00000000000000100000000000000000000000000000000000000000000: n4217_o = 1'b0; + 59'b00000000000000010000000000000000000000000000000000000000000: n4217_o = 1'b0; + 59'b00000000000000001000000000000000000000000000000000000000000: n4217_o = 1'b0; + 59'b00000000000000000100000000000000000000000000000000000000000: n4217_o = 1'b0; + 59'b00000000000000000010000000000000000000000000000000000000000: n4217_o = 1'b0; + 59'b00000000000000000001000000000000000000000000000000000000000: n4217_o = 1'b0; + 59'b00000000000000000000100000000000000000000000000000000000000: n4217_o = 1'b0; + 59'b00000000000000000000010000000000000000000000000000000000000: n4217_o = 1'b0; + 59'b00000000000000000000001000000000000000000000000000000000000: n4217_o = 1'b0; + 59'b00000000000000000000000100000000000000000000000000000000000: n4217_o = 1'b0; + 59'b00000000000000000000000010000000000000000000000000000000000: n4217_o = 1'b0; + 59'b00000000000000000000000001000000000000000000000000000000000: n4217_o = 1'b0; + 59'b00000000000000000000000000100000000000000000000000000000000: n4217_o = 1'b0; + 59'b00000000000000000000000000010000000000000000000000000000000: n4217_o = 1'b0; + 59'b00000000000000000000000000001000000000000000000000000000000: n4217_o = 1'b0; + 59'b00000000000000000000000000000100000000000000000000000000000: n4217_o = 1'b0; + 59'b00000000000000000000000000000010000000000000000000000000000: n4217_o = 1'b0; + 59'b00000000000000000000000000000001000000000000000000000000000: n4217_o = 1'b0; + 59'b00000000000000000000000000000000100000000000000000000000000: n4217_o = 1'b0; + 59'b00000000000000000000000000000000010000000000000000000000000: n4217_o = 1'b0; + 59'b00000000000000000000000000000000001000000000000000000000000: n4217_o = 1'b0; + 59'b00000000000000000000000000000000000100000000000000000000000: n4217_o = 1'b0; + 59'b00000000000000000000000000000000000010000000000000000000000: n4217_o = 1'b0; + 59'b00000000000000000000000000000000000001000000000000000000000: n4217_o = 1'b0; + 59'b00000000000000000000000000000000000000100000000000000000000: n4217_o = n4214_o; + 59'b00000000000000000000000000000000000000010000000000000000000: n4217_o = 1'b0; + 59'b00000000000000000000000000000000000000001000000000000000000: n4217_o = 1'b0; + 59'b00000000000000000000000000000000000000000100000000000000000: n4217_o = 1'b0; + 59'b00000000000000000000000000000000000000000010000000000000000: n4217_o = n2803_o; + 59'b00000000000000000000000000000000000000000001000000000000000: n4217_o = 1'b0; + 59'b00000000000000000000000000000000000000000000100000000000000: n4217_o = 1'b0; + 59'b00000000000000000000000000000000000000000000010000000000000: n4217_o = 1'b0; + 59'b00000000000000000000000000000000000000000000001000000000000: n4217_o = 1'b0; + 59'b00000000000000000000000000000000000000000000000100000000000: n4217_o = n2629_o; + 59'b00000000000000000000000000000000000000000000000010000000000: n4217_o = 1'b0; + 59'b00000000000000000000000000000000000000000000000001000000000: n4217_o = 1'b0; + 59'b00000000000000000000000000000000000000000000000000100000000: n4217_o = 1'b0; + 59'b00000000000000000000000000000000000000000000000000010000000: n4217_o = 1'b0; + 59'b00000000000000000000000000000000000000000000000000001000000: n4217_o = 1'b0; + 59'b00000000000000000000000000000000000000000000000000000100000: n4217_o = 1'b0; + 59'b00000000000000000000000000000000000000000000000000000010000: n4217_o = 1'b0; + 59'b00000000000000000000000000000000000000000000000000000001000: n4217_o = 1'b0; + 59'b00000000000000000000000000000000000000000000000000000000100: n4217_o = 1'b0; + 59'b00000000000000000000000000000000000000000000000000000000010: n4217_o = 1'b0; + 59'b00000000000000000000000000000000000000000000000000000000001: n4217_o = 1'b0; + default: n4217_o = 1'bX; + endcase + assign n4218_o = n2194_o[0]; + assign n4219_o = n2423_o[0]; + assign n4220_o = n2463_o[0]; + assign n4221_o = n2533_o[0]; + assign n4222_o = n2553_o[0]; + assign n4223_o = n2579_o[0]; + assign n4224_o = n2698_o[0]; + assign n4225_o = n2746_o[0]; + assign n4226_o = n2855_o[0]; + assign n4227_o = n2194_o[0]; + assign n4228_o = n3055_o[0]; + assign n4229_o = n3097_o[0]; + assign n4231_o = n3161_o[0]; + assign n4233_o = n3216_o[0]; + assign n4234_o = n3333_o[0]; + assign n4235_o = n3725_o[0]; + assign n4236_o = n3766_o[0]; + assign n4237_o = n3862_o[0]; + assign n4238_o = n4036_o[0]; + assign n4239_o = n4102_o[0]; + /* T80_MCode.vhd:265:17 */ + always @* + case (n4123_o) + 59'b10000000000000000000000000000000000000000000000000000000000: n4242_o = 1'b0; + 59'b01000000000000000000000000000000000000000000000000000000000: n4242_o = 1'b0; + 59'b00100000000000000000000000000000000000000000000000000000000: n4242_o = 1'b0; + 59'b00010000000000000000000000000000000000000000000000000000000: n4242_o = n4239_o; + 59'b00001000000000000000000000000000000000000000000000000000000: n4242_o = 1'b0; + 59'b00000100000000000000000000000000000000000000000000000000000: n4242_o = n4238_o; + 59'b00000010000000000000000000000000000000000000000000000000000: n4242_o = 1'b0; + 59'b00000001000000000000000000000000000000000000000000000000000: n4242_o = 1'b0; + 59'b00000000100000000000000000000000000000000000000000000000000: n4242_o = n4237_o; + 59'b00000000010000000000000000000000000000000000000000000000000: n4242_o = n4236_o; + 59'b00000000001000000000000000000000000000000000000000000000000: n4242_o = n4235_o; + 59'b00000000000100000000000000000000000000000000000000000000000: n4242_o = 1'b0; + 59'b00000000000010000000000000000000000000000000000000000000000: n4242_o = 1'b0; + 59'b00000000000001000000000000000000000000000000000000000000000: n4242_o = 1'b0; + 59'b00000000000000100000000000000000000000000000000000000000000: n4242_o = 1'b0; + 59'b00000000000000010000000000000000000000000000000000000000000: n4242_o = 1'b0; + 59'b00000000000000001000000000000000000000000000000000000000000: n4242_o = 1'b0; + 59'b00000000000000000100000000000000000000000000000000000000000: n4242_o = 1'b0; + 59'b00000000000000000010000000000000000000000000000000000000000: n4242_o = 1'b0; + 59'b00000000000000000001000000000000000000000000000000000000000: n4242_o = 1'b0; + 59'b00000000000000000000100000000000000000000000000000000000000: n4242_o = 1'b0; + 59'b00000000000000000000010000000000000000000000000000000000000: n4242_o = 1'b0; + 59'b00000000000000000000001000000000000000000000000000000000000: n4242_o = n3403_o; + 59'b00000000000000000000000100000000000000000000000000000000000: n4242_o = 1'b0; + 59'b00000000000000000000000010000000000000000000000000000000000: n4242_o = 1'b0; + 59'b00000000000000000000000001000000000000000000000000000000000: n4242_o = 1'b0; + 59'b00000000000000000000000000100000000000000000000000000000000: n4242_o = n4234_o; + 59'b00000000000000000000000000010000000000000000000000000000000: n4242_o = 1'b0; + 59'b00000000000000000000000000001000000000000000000000000000000: n4242_o = 1'b0; + 59'b00000000000000000000000000000100000000000000000000000000000: n4242_o = 1'b0; + 59'b00000000000000000000000000000010000000000000000000000000000: n4242_o = 1'b0; + 59'b00000000000000000000000000000001000000000000000000000000000: n4242_o = n4233_o; + 59'b00000000000000000000000000000000100000000000000000000000000: n4242_o = 1'b0; + 59'b00000000000000000000000000000000010000000000000000000000000: n4242_o = n4231_o; + 59'b00000000000000000000000000000000001000000000000000000000000: n4242_o = 1'b0; + 59'b00000000000000000000000000000000000100000000000000000000000: n4242_o = n4229_o; + 59'b00000000000000000000000000000000000010000000000000000000000: n4242_o = n4228_o; + 59'b00000000000000000000000000000000000001000000000000000000000: n4242_o = n4227_o; + 59'b00000000000000000000000000000000000000100000000000000000000: n4242_o = n4226_o; + 59'b00000000000000000000000000000000000000010000000000000000000: n4242_o = 1'b0; + 59'b00000000000000000000000000000000000000001000000000000000000: n4242_o = 1'b0; + 59'b00000000000000000000000000000000000000000100000000000000000: n4242_o = 1'b0; + 59'b00000000000000000000000000000000000000000010000000000000000: n4242_o = 1'b0; + 59'b00000000000000000000000000000000000000000001000000000000000: n4242_o = n4225_o; + 59'b00000000000000000000000000000000000000000000100000000000000: n4242_o = 1'b0; + 59'b00000000000000000000000000000000000000000000010000000000000: n4242_o = n4224_o; + 59'b00000000000000000000000000000000000000000000001000000000000: n4242_o = 1'b0; + 59'b00000000000000000000000000000000000000000000000100000000000: n4242_o = 1'b0; + 59'b00000000000000000000000000000000000000000000000010000000000: n4242_o = n4223_o; + 59'b00000000000000000000000000000000000000000000000001000000000: n4242_o = n4222_o; + 59'b00000000000000000000000000000000000000000000000000100000000: n4242_o = n4221_o; + 59'b00000000000000000000000000000000000000000000000000010000000: n4242_o = 1'b0; + 59'b00000000000000000000000000000000000000000000000000001000000: n4242_o = 1'b0; + 59'b00000000000000000000000000000000000000000000000000000100000: n4242_o = 1'b0; + 59'b00000000000000000000000000000000000000000000000000000010000: n4242_o = n4220_o; + 59'b00000000000000000000000000000000000000000000000000000001000: n4242_o = n4219_o; + 59'b00000000000000000000000000000000000000000000000000000000100: n4242_o = 1'b0; + 59'b00000000000000000000000000000000000000000000000000000000010: n4242_o = 1'b0; + 59'b00000000000000000000000000000000000000000000000000000000001: n4242_o = n4218_o; + default: n4242_o = 1'bX; + endcase + assign n4243_o = n2194_o[2:1]; + assign n4244_o = n2423_o[2:1]; + assign n4245_o = n2463_o[2:1]; + assign n4246_o = n2533_o[2:1]; + assign n4247_o = n2553_o[2:1]; + assign n4248_o = n2579_o[2:1]; + assign n4249_o = n2698_o[2:1]; + assign n4250_o = n2746_o[2:1]; + assign n4251_o = n2855_o[2:1]; + assign n4252_o = n2194_o[2:1]; + assign n4253_o = n3055_o[2:1]; + assign n4254_o = n3097_o[2:1]; + assign n4256_o = n3161_o[2:1]; + assign n4258_o = n3216_o[2:1]; + assign n4259_o = n3333_o[2:1]; + assign n4260_o = n3725_o[2:1]; + assign n4261_o = n3766_o[2:1]; + assign n4262_o = n3862_o[2:1]; + assign n4263_o = n4036_o[2:1]; + assign n4264_o = n4102_o[2:1]; + /* T80_MCode.vhd:265:17 */ + always @* + case (n4123_o) + 59'b10000000000000000000000000000000000000000000000000000000000: n4267_o = 2'b00; + 59'b01000000000000000000000000000000000000000000000000000000000: n4267_o = 2'b00; + 59'b00100000000000000000000000000000000000000000000000000000000: n4267_o = 2'b00; + 59'b00010000000000000000000000000000000000000000000000000000000: n4267_o = n4264_o; + 59'b00001000000000000000000000000000000000000000000000000000000: n4267_o = 2'b00; + 59'b00000100000000000000000000000000000000000000000000000000000: n4267_o = n4263_o; + 59'b00000010000000000000000000000000000000000000000000000000000: n4267_o = 2'b00; + 59'b00000001000000000000000000000000000000000000000000000000000: n4267_o = 2'b00; + 59'b00000000100000000000000000000000000000000000000000000000000: n4267_o = n4262_o; + 59'b00000000010000000000000000000000000000000000000000000000000: n4267_o = n4261_o; + 59'b00000000001000000000000000000000000000000000000000000000000: n4267_o = n4260_o; + 59'b00000000000100000000000000000000000000000000000000000000000: n4267_o = 2'b00; + 59'b00000000000010000000000000000000000000000000000000000000000: n4267_o = 2'b00; + 59'b00000000000001000000000000000000000000000000000000000000000: n4267_o = 2'b00; + 59'b00000000000000100000000000000000000000000000000000000000000: n4267_o = 2'b00; + 59'b00000000000000010000000000000000000000000000000000000000000: n4267_o = 2'b00; + 59'b00000000000000001000000000000000000000000000000000000000000: n4267_o = 2'b00; + 59'b00000000000000000100000000000000000000000000000000000000000: n4267_o = 2'b00; + 59'b00000000000000000010000000000000000000000000000000000000000: n4267_o = 2'b00; + 59'b00000000000000000001000000000000000000000000000000000000000: n4267_o = 2'b00; + 59'b00000000000000000000100000000000000000000000000000000000000: n4267_o = 2'b00; + 59'b00000000000000000000010000000000000000000000000000000000000: n4267_o = 2'b00; + 59'b00000000000000000000001000000000000000000000000000000000000: n4267_o = n3405_o; + 59'b00000000000000000000000100000000000000000000000000000000000: n4267_o = 2'b00; + 59'b00000000000000000000000010000000000000000000000000000000000: n4267_o = 2'b00; + 59'b00000000000000000000000001000000000000000000000000000000000: n4267_o = 2'b00; + 59'b00000000000000000000000000100000000000000000000000000000000: n4267_o = n4259_o; + 59'b00000000000000000000000000010000000000000000000000000000000: n4267_o = 2'b00; + 59'b00000000000000000000000000001000000000000000000000000000000: n4267_o = 2'b00; + 59'b00000000000000000000000000000100000000000000000000000000000: n4267_o = 2'b00; + 59'b00000000000000000000000000000010000000000000000000000000000: n4267_o = 2'b00; + 59'b00000000000000000000000000000001000000000000000000000000000: n4267_o = n4258_o; + 59'b00000000000000000000000000000000100000000000000000000000000: n4267_o = 2'b01; + 59'b00000000000000000000000000000000010000000000000000000000000: n4267_o = n4256_o; + 59'b00000000000000000000000000000000001000000000000000000000000: n4267_o = 2'b01; + 59'b00000000000000000000000000000000000100000000000000000000000: n4267_o = n4254_o; + 59'b00000000000000000000000000000000000010000000000000000000000: n4267_o = n4253_o; + 59'b00000000000000000000000000000000000001000000000000000000000: n4267_o = n4252_o; + 59'b00000000000000000000000000000000000000100000000000000000000: n4267_o = n4251_o; + 59'b00000000000000000000000000000000000000010000000000000000000: n4267_o = 2'b00; + 59'b00000000000000000000000000000000000000001000000000000000000: n4267_o = 2'b00; + 59'b00000000000000000000000000000000000000000100000000000000000: n4267_o = 2'b00; + 59'b00000000000000000000000000000000000000000010000000000000000: n4267_o = 2'b00; + 59'b00000000000000000000000000000000000000000001000000000000000: n4267_o = n4250_o; + 59'b00000000000000000000000000000000000000000000100000000000000: n4267_o = 2'b00; + 59'b00000000000000000000000000000000000000000000010000000000000: n4267_o = n4249_o; + 59'b00000000000000000000000000000000000000000000001000000000000: n4267_o = 2'b00; + 59'b00000000000000000000000000000000000000000000000100000000000: n4267_o = 2'b00; + 59'b00000000000000000000000000000000000000000000000010000000000: n4267_o = n4248_o; + 59'b00000000000000000000000000000000000000000000000001000000000: n4267_o = n4247_o; + 59'b00000000000000000000000000000000000000000000000000100000000: n4267_o = n4246_o; + 59'b00000000000000000000000000000000000000000000000000010000000: n4267_o = 2'b00; + 59'b00000000000000000000000000000000000000000000000000001000000: n4267_o = 2'b00; + 59'b00000000000000000000000000000000000000000000000000000100000: n4267_o = 2'b00; + 59'b00000000000000000000000000000000000000000000000000000010000: n4267_o = n4245_o; + 59'b00000000000000000000000000000000000000000000000000000001000: n4267_o = n4244_o; + 59'b00000000000000000000000000000000000000000000000000000000100: n4267_o = 2'b00; + 59'b00000000000000000000000000000000000000000000000000000000010: n4267_o = 2'b00; + 59'b00000000000000000000000000000000000000000000000000000000001: n4267_o = n4243_o; + default: n4267_o = 2'bX; + endcase + assign n4268_o = n2533_o[3]; + assign n4269_o = n2553_o[3]; + assign n4270_o = n2579_o[3]; + assign n4271_o = n2698_o[3]; + assign n4272_o = n2746_o[3]; + assign n4273_o = n2855_o[3]; + assign n4275_o = n3161_o[3]; + assign n4277_o = n3216_o[3]; + assign n4278_o = n3333_o[3]; + assign n4279_o = n3725_o[3]; + assign n4280_o = n3766_o[3]; + assign n4281_o = n3862_o[3]; + assign n4282_o = n4036_o[3]; + assign n4283_o = n4102_o[3]; + /* T80_MCode.vhd:265:17 */ + always @* + case (n4123_o) + 59'b10000000000000000000000000000000000000000000000000000000000: n4286_o = 1'b0; + 59'b01000000000000000000000000000000000000000000000000000000000: n4286_o = 1'b0; + 59'b00100000000000000000000000000000000000000000000000000000000: n4286_o = 1'b0; + 59'b00010000000000000000000000000000000000000000000000000000000: n4286_o = n4283_o; + 59'b00001000000000000000000000000000000000000000000000000000000: n4286_o = 1'b0; + 59'b00000100000000000000000000000000000000000000000000000000000: n4286_o = n4282_o; + 59'b00000010000000000000000000000000000000000000000000000000000: n4286_o = 1'b0; + 59'b00000001000000000000000000000000000000000000000000000000000: n4286_o = 1'b0; + 59'b00000000100000000000000000000000000000000000000000000000000: n4286_o = n4281_o; + 59'b00000000010000000000000000000000000000000000000000000000000: n4286_o = n4280_o; + 59'b00000000001000000000000000000000000000000000000000000000000: n4286_o = n4279_o; + 59'b00000000000100000000000000000000000000000000000000000000000: n4286_o = 1'b0; + 59'b00000000000010000000000000000000000000000000000000000000000: n4286_o = 1'b0; + 59'b00000000000001000000000000000000000000000000000000000000000: n4286_o = 1'b0; + 59'b00000000000000100000000000000000000000000000000000000000000: n4286_o = 1'b0; + 59'b00000000000000010000000000000000000000000000000000000000000: n4286_o = 1'b0; + 59'b00000000000000001000000000000000000000000000000000000000000: n4286_o = 1'b0; + 59'b00000000000000000100000000000000000000000000000000000000000: n4286_o = 1'b0; + 59'b00000000000000000010000000000000000000000000000000000000000: n4286_o = 1'b0; + 59'b00000000000000000001000000000000000000000000000000000000000: n4286_o = 1'b0; + 59'b00000000000000000000100000000000000000000000000000000000000: n4286_o = 1'b0; + 59'b00000000000000000000010000000000000000000000000000000000000: n4286_o = 1'b0; + 59'b00000000000000000000001000000000000000000000000000000000000: n4286_o = n3407_o; + 59'b00000000000000000000000100000000000000000000000000000000000: n4286_o = 1'b0; + 59'b00000000000000000000000010000000000000000000000000000000000: n4286_o = 1'b0; + 59'b00000000000000000000000001000000000000000000000000000000000: n4286_o = 1'b0; + 59'b00000000000000000000000000100000000000000000000000000000000: n4286_o = n4278_o; + 59'b00000000000000000000000000010000000000000000000000000000000: n4286_o = 1'b0; + 59'b00000000000000000000000000001000000000000000000000000000000: n4286_o = 1'b0; + 59'b00000000000000000000000000000100000000000000000000000000000: n4286_o = 1'b0; + 59'b00000000000000000000000000000010000000000000000000000000000: n4286_o = 1'b0; + 59'b00000000000000000000000000000001000000000000000000000000000: n4286_o = n4277_o; + 59'b00000000000000000000000000000000100000000000000000000000000: n4286_o = 1'b1; + 59'b00000000000000000000000000000000010000000000000000000000000: n4286_o = n4275_o; + 59'b00000000000000000000000000000000001000000000000000000000000: n4286_o = 1'b1; + 59'b00000000000000000000000000000000000100000000000000000000000: n4286_o = 1'b0; + 59'b00000000000000000000000000000000000010000000000000000000000: n4286_o = 1'b0; + 59'b00000000000000000000000000000000000001000000000000000000000: n4286_o = 1'b0; + 59'b00000000000000000000000000000000000000100000000000000000000: n4286_o = n4273_o; + 59'b00000000000000000000000000000000000000010000000000000000000: n4286_o = 1'b0; + 59'b00000000000000000000000000000000000000001000000000000000000: n4286_o = 1'b0; + 59'b00000000000000000000000000000000000000000100000000000000000: n4286_o = 1'b0; + 59'b00000000000000000000000000000000000000000010000000000000000: n4286_o = 1'b0; + 59'b00000000000000000000000000000000000000000001000000000000000: n4286_o = n4272_o; + 59'b00000000000000000000000000000000000000000000100000000000000: n4286_o = 1'b0; + 59'b00000000000000000000000000000000000000000000010000000000000: n4286_o = n4271_o; + 59'b00000000000000000000000000000000000000000000001000000000000: n4286_o = 1'b0; + 59'b00000000000000000000000000000000000000000000000100000000000: n4286_o = 1'b0; + 59'b00000000000000000000000000000000000000000000000010000000000: n4286_o = n4270_o; + 59'b00000000000000000000000000000000000000000000000001000000000: n4286_o = n4269_o; + 59'b00000000000000000000000000000000000000000000000000100000000: n4286_o = n4268_o; + 59'b00000000000000000000000000000000000000000000000000010000000: n4286_o = 1'b0; + 59'b00000000000000000000000000000000000000000000000000001000000: n4286_o = 1'b0; + 59'b00000000000000000000000000000000000000000000000000000100000: n4286_o = 1'b0; + 59'b00000000000000000000000000000000000000000000000000000010000: n4286_o = n2465_o; + 59'b00000000000000000000000000000000000000000000000000000001000: n4286_o = n2425_o; + 59'b00000000000000000000000000000000000000000000000000000000100: n4286_o = 1'b0; + 59'b00000000000000000000000000000000000000000000000000000000010: n4286_o = 1'b0; + 59'b00000000000000000000000000000000000000000000000000000000001: n4286_o = 1'b0; + default: n4286_o = 1'bX; + endcase + /* T80_MCode.vhd:265:17 */ + always @* + case (n4123_o) + 59'b10000000000000000000000000000000000000000000000000000000000: n4292_o = n2203_o; + 59'b01000000000000000000000000000000000000000000000000000000000: n4292_o = n2203_o; + 59'b00100000000000000000000000000000000000000000000000000000000: n4292_o = n2203_o; + 59'b00010000000000000000000000000000000000000000000000000000000: n4292_o = n2203_o; + 59'b00001000000000000000000000000000000000000000000000000000000: n4292_o = n2203_o; + 59'b00000100000000000000000000000000000000000000000000000000000: n4292_o = n2203_o; + 59'b00000010000000000000000000000000000000000000000000000000000: n4292_o = n2203_o; + 59'b00000001000000000000000000000000000000000000000000000000000: n4292_o = n2203_o; + 59'b00000000100000000000000000000000000000000000000000000000000: n4292_o = n2203_o; + 59'b00000000010000000000000000000000000000000000000000000000000: n4292_o = n2203_o; + 59'b00000000001000000000000000000000000000000000000000000000000: n4292_o = n3727_o; + 59'b00000000000100000000000000000000000000000000000000000000000: n4292_o = n2203_o; + 59'b00000000000010000000000000000000000000000000000000000000000: n4292_o = n2203_o; + 59'b00000000000001000000000000000000000000000000000000000000000: n4292_o = n2203_o; + 59'b00000000000000100000000000000000000000000000000000000000000: n4292_o = n2203_o; + 59'b00000000000000010000000000000000000000000000000000000000000: n4292_o = n2203_o; + 59'b00000000000000001000000000000000000000000000000000000000000: n4292_o = n2203_o; + 59'b00000000000000000100000000000000000000000000000000000000000: n4292_o = n2203_o; + 59'b00000000000000000010000000000000000000000000000000000000000: n4292_o = n2203_o; + 59'b00000000000000000001000000000000000000000000000000000000000: n4292_o = 4'b1000; + 59'b00000000000000000000100000000000000000000000000000000000000: n4292_o = n2203_o; + 59'b00000000000000000000010000000000000000000000000000000000000: n4292_o = n2203_o; + 59'b00000000000000000000001000000000000000000000000000000000000: n4292_o = n3410_o; + 59'b00000000000000000000000100000000000000000000000000000000000: n4292_o = n2203_o; + 59'b00000000000000000000000010000000000000000000000000000000000: n4292_o = n2203_o; + 59'b00000000000000000000000001000000000000000000000000000000000: n4292_o = n2203_o; + 59'b00000000000000000000000000100000000000000000000000000000000: n4292_o = n2203_o; + 59'b00000000000000000000000000010000000000000000000000000000000: n4292_o = n2203_o; + 59'b00000000000000000000000000001000000000000000000000000000000: n4292_o = n2203_o; + 59'b00000000000000000000000000000100000000000000000000000000000: n4292_o = n2203_o; + 59'b00000000000000000000000000000010000000000000000000000000000: n4292_o = 4'b1100; + 59'b00000000000000000000000000000001000000000000000000000000000: n4292_o = n3218_o; + 59'b00000000000000000000000000000000100000000000000000000000000: n4292_o = 4'b0010; + 59'b00000000000000000000000000000000010000000000000000000000000: n4292_o = n3163_o; + 59'b00000000000000000000000000000000001000000000000000000000000: n4292_o = 4'b0000; + 59'b00000000000000000000000000000000000100000000000000000000000: n4292_o = n2203_o; + 59'b00000000000000000000000000000000000010000000000000000000000: n4292_o = n2203_o; + 59'b00000000000000000000000000000000000001000000000000000000000: n4292_o = n2203_o; + 59'b00000000000000000000000000000000000000100000000000000000000: n4292_o = n2203_o; + 59'b00000000000000000000000000000000000000010000000000000000000: n4292_o = n2203_o; + 59'b00000000000000000000000000000000000000001000000000000000000: n4292_o = n2203_o; + 59'b00000000000000000000000000000000000000000100000000000000000: n4292_o = n2203_o; + 59'b00000000000000000000000000000000000000000010000000000000000: n4292_o = n2203_o; + 59'b00000000000000000000000000000000000000000001000000000000000: n4292_o = n2203_o; + 59'b00000000000000000000000000000000000000000000100000000000000: n4292_o = n2203_o; + 59'b00000000000000000000000000000000000000000000010000000000000: n4292_o = n2203_o; + 59'b00000000000000000000000000000000000000000000001000000000000: n4292_o = n2203_o; + 59'b00000000000000000000000000000000000000000000000100000000000: n4292_o = n2203_o; + 59'b00000000000000000000000000000000000000000000000010000000000: n4292_o = n2203_o; + 59'b00000000000000000000000000000000000000000000000001000000000: n4292_o = n2203_o; + 59'b00000000000000000000000000000000000000000000000000100000000: n4292_o = n2203_o; + 59'b00000000000000000000000000000000000000000000000000010000000: n4292_o = n2203_o; + 59'b00000000000000000000000000000000000000000000000000001000000: n4292_o = n2203_o; + 59'b00000000000000000000000000000000000000000000000000000100000: n4292_o = n2203_o; + 59'b00000000000000000000000000000000000000000000000000000010000: n4292_o = n2203_o; + 59'b00000000000000000000000000000000000000000000000000000001000: n4292_o = n2203_o; + 59'b00000000000000000000000000000000000000000000000000000000100: n4292_o = n2203_o; + 59'b00000000000000000000000000000000000000000000000000000000010: n4292_o = n2203_o; + 59'b00000000000000000000000000000000000000000000000000000000001: n4292_o = n2203_o; + default: n4292_o = 4'bX; + endcase + /* T80_MCode.vhd:265:17 */ + always @* + case (n4123_o) + 59'b10000000000000000000000000000000000000000000000000000000000: n4300_o = 1'b0; + 59'b01000000000000000000000000000000000000000000000000000000000: n4300_o = 1'b0; + 59'b00100000000000000000000000000000000000000000000000000000000: n4300_o = 1'b0; + 59'b00010000000000000000000000000000000000000000000000000000000: n4300_o = 1'b0; + 59'b00001000000000000000000000000000000000000000000000000000000: n4300_o = 1'b0; + 59'b00000100000000000000000000000000000000000000000000000000000: n4300_o = 1'b0; + 59'b00000010000000000000000000000000000000000000000000000000000: n4300_o = 1'b0; + 59'b00000001000000000000000000000000000000000000000000000000000: n4300_o = 1'b0; + 59'b00000000100000000000000000000000000000000000000000000000000: n4300_o = 1'b0; + 59'b00000000010000000000000000000000000000000000000000000000000: n4300_o = 1'b0; + 59'b00000000001000000000000000000000000000000000000000000000000: n4300_o = n3730_o; + 59'b00000000000100000000000000000000000000000000000000000000000: n4300_o = 1'b0; + 59'b00000000000010000000000000000000000000000000000000000000000: n4300_o = 1'b0; + 59'b00000000000001000000000000000000000000000000000000000000000: n4300_o = 1'b0; + 59'b00000000000000100000000000000000000000000000000000000000000: n4300_o = 1'b0; + 59'b00000000000000010000000000000000000000000000000000000000000: n4300_o = 1'b0; + 59'b00000000000000001000000000000000000000000000000000000000000: n4300_o = 1'b0; + 59'b00000000000000000100000000000000000000000000000000000000000: n4300_o = 1'b0; + 59'b00000000000000000010000000000000000000000000000000000000000: n4300_o = 1'b0; + 59'b00000000000000000001000000000000000000000000000000000000000: n4300_o = 1'b1; + 59'b00000000000000000000100000000000000000000000000000000000000: n4300_o = 1'b0; + 59'b00000000000000000000010000000000000000000000000000000000000: n4300_o = 1'b0; + 59'b00000000000000000000001000000000000000000000000000000000000: n4300_o = n3414_o; + 59'b00000000000000000000000100000000000000000000000000000000000: n4300_o = 1'b0; + 59'b00000000000000000000000010000000000000000000000000000000000: n4300_o = 1'b0; + 59'b00000000000000000000000001000000000000000000000000000000000: n4300_o = 1'b0; + 59'b00000000000000000000000000100000000000000000000000000000000: n4300_o = 1'b0; + 59'b00000000000000000000000000010000000000000000000000000000000: n4300_o = 1'b0; + 59'b00000000000000000000000000001000000000000000000000000000000: n4300_o = 1'b0; + 59'b00000000000000000000000000000100000000000000000000000000000: n4300_o = 1'b0; + 59'b00000000000000000000000000000010000000000000000000000000000: n4300_o = 1'b1; + 59'b00000000000000000000000000000001000000000000000000000000000: n4300_o = n3221_o; + 59'b00000000000000000000000000000000100000000000000000000000000: n4300_o = 1'b1; + 59'b00000000000000000000000000000000010000000000000000000000000: n4300_o = n3166_o; + 59'b00000000000000000000000000000000001000000000000000000000000: n4300_o = 1'b1; + 59'b00000000000000000000000000000000000100000000000000000000000: n4300_o = n3100_o; + 59'b00000000000000000000000000000000000010000000000000000000000: n4300_o = n3058_o; + 59'b00000000000000000000000000000000000001000000000000000000000: n4300_o = 1'b1; + 59'b00000000000000000000000000000000000000100000000000000000000: n4300_o = 1'b0; + 59'b00000000000000000000000000000000000000010000000000000000000: n4300_o = 1'b0; + 59'b00000000000000000000000000000000000000001000000000000000000: n4300_o = 1'b0; + 59'b00000000000000000000000000000000000000000100000000000000000: n4300_o = 1'b0; + 59'b00000000000000000000000000000000000000000010000000000000000: n4300_o = 1'b0; + 59'b00000000000000000000000000000000000000000001000000000000000: n4300_o = 1'b0; + 59'b00000000000000000000000000000000000000000000100000000000000: n4300_o = 1'b0; + 59'b00000000000000000000000000000000000000000000010000000000000: n4300_o = 1'b0; + 59'b00000000000000000000000000000000000000000000001000000000000: n4300_o = 1'b0; + 59'b00000000000000000000000000000000000000000000000100000000000: n4300_o = 1'b0; + 59'b00000000000000000000000000000000000000000000000010000000000: n4300_o = 1'b0; + 59'b00000000000000000000000000000000000000000000000001000000000: n4300_o = 1'b0; + 59'b00000000000000000000000000000000000000000000000000100000000: n4300_o = 1'b0; + 59'b00000000000000000000000000000000000000000000000000010000000: n4300_o = 1'b0; + 59'b00000000000000000000000000000000000000000000000000001000000: n4300_o = 1'b0; + 59'b00000000000000000000000000000000000000000000000000000100000: n4300_o = 1'b0; + 59'b00000000000000000000000000000000000000000000000000000010000: n4300_o = 1'b0; + 59'b00000000000000000000000000000000000000000000000000000001000: n4300_o = 1'b0; + 59'b00000000000000000000000000000000000000000000000000000000100: n4300_o = 1'b0; + 59'b00000000000000000000000000000000000000000000000000000000010: n4300_o = 1'b0; + 59'b00000000000000000000000000000000000000000000000000000000001: n4300_o = 1'b0; + default: n4300_o = 1'bX; + endcase + /* T80_MCode.vhd:265:17 */ + always @* + case (n4123_o) + 59'b10000000000000000000000000000000000000000000000000000000000: n4305_o = 1'b0; + 59'b01000000000000000000000000000000000000000000000000000000000: n4305_o = 1'b0; + 59'b00100000000000000000000000000000000000000000000000000000000: n4305_o = 1'b0; + 59'b00010000000000000000000000000000000000000000000000000000000: n4305_o = 1'b0; + 59'b00001000000000000000000000000000000000000000000000000000000: n4305_o = 1'b0; + 59'b00000100000000000000000000000000000000000000000000000000000: n4305_o = 1'b0; + 59'b00000010000000000000000000000000000000000000000000000000000: n4305_o = 1'b0; + 59'b00000001000000000000000000000000000000000000000000000000000: n4305_o = 1'b0; + 59'b00000000100000000000000000000000000000000000000000000000000: n4305_o = 1'b0; + 59'b00000000010000000000000000000000000000000000000000000000000: n4305_o = 1'b0; + 59'b00000000001000000000000000000000000000000000000000000000000: n4305_o = 1'b0; + 59'b00000000000100000000000000000000000000000000000000000000000: n4305_o = 1'b0; + 59'b00000000000010000000000000000000000000000000000000000000000: n4305_o = 1'b0; + 59'b00000000000001000000000000000000000000000000000000000000000: n4305_o = 1'b0; + 59'b00000000000000100000000000000000000000000000000000000000000: n4305_o = 1'b0; + 59'b00000000000000010000000000000000000000000000000000000000000: n4305_o = 1'b0; + 59'b00000000000000001000000000000000000000000000000000000000000: n4305_o = 1'b0; + 59'b00000000000000000100000000000000000000000000000000000000000: n4305_o = 1'b0; + 59'b00000000000000000010000000000000000000000000000000000000000: n4305_o = 1'b0; + 59'b00000000000000000001000000000000000000000000000000000000000: n4305_o = 1'b0; + 59'b00000000000000000000100000000000000000000000000000000000000: n4305_o = 1'b0; + 59'b00000000000000000000010000000000000000000000000000000000000: n4305_o = 1'b0; + 59'b00000000000000000000001000000000000000000000000000000000000: n4305_o = 1'b0; + 59'b00000000000000000000000100000000000000000000000000000000000: n4305_o = 1'b0; + 59'b00000000000000000000000010000000000000000000000000000000000: n4305_o = 1'b0; + 59'b00000000000000000000000001000000000000000000000000000000000: n4305_o = 1'b0; + 59'b00000000000000000000000000100000000000000000000000000000000: n4305_o = 1'b0; + 59'b00000000000000000000000000010000000000000000000000000000000: n4305_o = 1'b0; + 59'b00000000000000000000000000001000000000000000000000000000000: n4305_o = 1'b0; + 59'b00000000000000000000000000000100000000000000000000000000000: n4305_o = 1'b0; + 59'b00000000000000000000000000000010000000000000000000000000000: n4305_o = 1'b0; + 59'b00000000000000000000000000000001000000000000000000000000000: n4305_o = n3224_o; + 59'b00000000000000000000000000000000100000000000000000000000000: n4305_o = 1'b1; + 59'b00000000000000000000000000000000010000000000000000000000000: n4305_o = n3169_o; + 59'b00000000000000000000000000000000001000000000000000000000000: n4305_o = 1'b1; + 59'b00000000000000000000000000000000000100000000000000000000000: n4305_o = 1'b0; + 59'b00000000000000000000000000000000000010000000000000000000000: n4305_o = 1'b0; + 59'b00000000000000000000000000000000000001000000000000000000000: n4305_o = 1'b0; + 59'b00000000000000000000000000000000000000100000000000000000000: n4305_o = 1'b0; + 59'b00000000000000000000000000000000000000010000000000000000000: n4305_o = 1'b0; + 59'b00000000000000000000000000000000000000001000000000000000000: n4305_o = 1'b0; + 59'b00000000000000000000000000000000000000000100000000000000000: n4305_o = 1'b0; + 59'b00000000000000000000000000000000000000000010000000000000000: n4305_o = 1'b0; + 59'b00000000000000000000000000000000000000000001000000000000000: n4305_o = 1'b0; + 59'b00000000000000000000000000000000000000000000100000000000000: n4305_o = 1'b0; + 59'b00000000000000000000000000000000000000000000010000000000000: n4305_o = 1'b0; + 59'b00000000000000000000000000000000000000000000001000000000000: n4305_o = 1'b0; + 59'b00000000000000000000000000000000000000000000000100000000000: n4305_o = 1'b0; + 59'b00000000000000000000000000000000000000000000000010000000000: n4305_o = 1'b0; + 59'b00000000000000000000000000000000000000000000000001000000000: n4305_o = 1'b0; + 59'b00000000000000000000000000000000000000000000000000100000000: n4305_o = 1'b0; + 59'b00000000000000000000000000000000000000000000000000010000000: n4305_o = 1'b0; + 59'b00000000000000000000000000000000000000000000000000001000000: n4305_o = 1'b0; + 59'b00000000000000000000000000000000000000000000000000000100000: n4305_o = 1'b0; + 59'b00000000000000000000000000000000000000000000000000000010000: n4305_o = 1'b0; + 59'b00000000000000000000000000000000000000000000000000000001000: n4305_o = 1'b0; + 59'b00000000000000000000000000000000000000000000000000000000100: n4305_o = 1'b0; + 59'b00000000000000000000000000000000000000000000000000000000010: n4305_o = 1'b0; + 59'b00000000000000000000000000000000000000000000000000000000001: n4305_o = 1'b0; + default: n4305_o = 1'bX; + endcase + /* T80_MCode.vhd:265:17 */ + always @* + case (n4123_o) + 59'b10000000000000000000000000000000000000000000000000000000000: n4308_o = 1'b0; + 59'b01000000000000000000000000000000000000000000000000000000000: n4308_o = 1'b0; + 59'b00100000000000000000000000000000000000000000000000000000000: n4308_o = 1'b0; + 59'b00010000000000000000000000000000000000000000000000000000000: n4308_o = 1'b0; + 59'b00001000000000000000000000000000000000000000000000000000000: n4308_o = 1'b0; + 59'b00000100000000000000000000000000000000000000000000000000000: n4308_o = 1'b0; + 59'b00000010000000000000000000000000000000000000000000000000000: n4308_o = 1'b0; + 59'b00000001000000000000000000000000000000000000000000000000000: n4308_o = 1'b0; + 59'b00000000100000000000000000000000000000000000000000000000000: n4308_o = 1'b0; + 59'b00000000010000000000000000000000000000000000000000000000000: n4308_o = 1'b0; + 59'b00000000001000000000000000000000000000000000000000000000000: n4308_o = 1'b0; + 59'b00000000000100000000000000000000000000000000000000000000000: n4308_o = 1'b0; + 59'b00000000000010000000000000000000000000000000000000000000000: n4308_o = 1'b0; + 59'b00000000000001000000000000000000000000000000000000000000000: n4308_o = 1'b0; + 59'b00000000000000100000000000000000000000000000000000000000000: n4308_o = 1'b0; + 59'b00000000000000010000000000000000000000000000000000000000000: n4308_o = 1'b0; + 59'b00000000000000001000000000000000000000000000000000000000000: n4308_o = 1'b0; + 59'b00000000000000000100000000000000000000000000000000000000000: n4308_o = 1'b0; + 59'b00000000000000000010000000000000000000000000000000000000000: n4308_o = 1'b0; + 59'b00000000000000000001000000000000000000000000000000000000000: n4308_o = 1'b0; + 59'b00000000000000000000100000000000000000000000000000000000000: n4308_o = 1'b0; + 59'b00000000000000000000010000000000000000000000000000000000000: n4308_o = 1'b0; + 59'b00000000000000000000001000000000000000000000000000000000000: n4308_o = n3418_o; + 59'b00000000000000000000000100000000000000000000000000000000000: n4308_o = 1'b0; + 59'b00000000000000000000000010000000000000000000000000000000000: n4308_o = 1'b0; + 59'b00000000000000000000000001000000000000000000000000000000000: n4308_o = 1'b0; + 59'b00000000000000000000000000100000000000000000000000000000000: n4308_o = 1'b0; + 59'b00000000000000000000000000010000000000000000000000000000000: n4308_o = 1'b0; + 59'b00000000000000000000000000001000000000000000000000000000000: n4308_o = 1'b0; + 59'b00000000000000000000000000000100000000000000000000000000000: n4308_o = 1'b0; + 59'b00000000000000000000000000000010000000000000000000000000000: n4308_o = 1'b0; + 59'b00000000000000000000000000000001000000000000000000000000000: n4308_o = 1'b0; + 59'b00000000000000000000000000000000100000000000000000000000000: n4308_o = 1'b0; + 59'b00000000000000000000000000000000010000000000000000000000000: n4308_o = 1'b0; + 59'b00000000000000000000000000000000001000000000000000000000000: n4308_o = 1'b0; + 59'b00000000000000000000000000000000000100000000000000000000000: n4308_o = 1'b0; + 59'b00000000000000000000000000000000000010000000000000000000000: n4308_o = 1'b0; + 59'b00000000000000000000000000000000000001000000000000000000000: n4308_o = 1'b0; + 59'b00000000000000000000000000000000000000100000000000000000000: n4308_o = 1'b0; + 59'b00000000000000000000000000000000000000010000000000000000000: n4308_o = 1'b0; + 59'b00000000000000000000000000000000000000001000000000000000000: n4308_o = 1'b0; + 59'b00000000000000000000000000000000000000000100000000000000000: n4308_o = 1'b0; + 59'b00000000000000000000000000000000000000000010000000000000000: n4308_o = 1'b0; + 59'b00000000000000000000000000000000000000000001000000000000000: n4308_o = 1'b0; + 59'b00000000000000000000000000000000000000000000100000000000000: n4308_o = 1'b0; + 59'b00000000000000000000000000000000000000000000010000000000000: n4308_o = 1'b0; + 59'b00000000000000000000000000000000000000000000001000000000000: n4308_o = 1'b0; + 59'b00000000000000000000000000000000000000000000000100000000000: n4308_o = 1'b0; + 59'b00000000000000000000000000000000000000000000000010000000000: n4308_o = 1'b0; + 59'b00000000000000000000000000000000000000000000000001000000000: n4308_o = 1'b0; + 59'b00000000000000000000000000000000000000000000000000100000000: n4308_o = 1'b0; + 59'b00000000000000000000000000000000000000000000000000010000000: n4308_o = 1'b0; + 59'b00000000000000000000000000000000000000000000000000001000000: n4308_o = 1'b0; + 59'b00000000000000000000000000000000000000000000000000000100000: n4308_o = 1'b0; + 59'b00000000000000000000000000000000000000000000000000000010000: n4308_o = 1'b0; + 59'b00000000000000000000000000000000000000000000000000000001000: n4308_o = 1'b0; + 59'b00000000000000000000000000000000000000000000000000000000100: n4308_o = 1'b0; + 59'b00000000000000000000000000000000000000000000000000000000010: n4308_o = 1'b0; + 59'b00000000000000000000000000000000000000000000000000000000001: n4308_o = 1'b0; + default: n4308_o = 1'bX; + endcase + /* T80_MCode.vhd:265:17 */ + always @* + case (n4123_o) + 59'b10000000000000000000000000000000000000000000000000000000000: n4311_o = 3'b111; + 59'b01000000000000000000000000000000000000000000000000000000000: n4311_o = 3'b111; + 59'b00100000000000000000000000000000000000000000000000000000000: n4311_o = 3'b111; + 59'b00010000000000000000000000000000000000000000000000000000000: n4311_o = n4105_o; + 59'b00001000000000000000000000000000000000000000000000000000000: n4311_o = n4085_o; + 59'b00000100000000000000000000000000000000000000000000000000000: n4311_o = n4040_o; + 59'b00000010000000000000000000000000000000000000000000000000000: n4311_o = n3989_o; + 59'b00000001000000000000000000000000000000000000000000000000000: n4311_o = n3917_o; + 59'b00000000100000000000000000000000000000000000000000000000000: n4311_o = n3865_o; + 59'b00000000010000000000000000000000000000000000000000000000000: n4311_o = n3770_o; + 59'b00000000001000000000000000000000000000000000000000000000000: n4311_o = 3'b111; + 59'b00000000000100000000000000000000000000000000000000000000000: n4311_o = 3'b111; + 59'b00000000000010000000000000000000000000000000000000000000000: n4311_o = 3'b111; + 59'b00000000000001000000000000000000000000000000000000000000000: n4311_o = 3'b111; + 59'b00000000000000100000000000000000000000000000000000000000000: n4311_o = 3'b111; + 59'b00000000000000010000000000000000000000000000000000000000000: n4311_o = 3'b111; + 59'b00000000000000001000000000000000000000000000000000000000000: n4311_o = 3'b111; + 59'b00000000000000000100000000000000000000000000000000000000000: n4311_o = 3'b111; + 59'b00000000000000000010000000000000000000000000000000000000000: n4311_o = 3'b111; + 59'b00000000000000000001000000000000000000000000000000000000000: n4311_o = 3'b111; + 59'b00000000000000000000100000000000000000000000000000000000000: n4311_o = 3'b111; + 59'b00000000000000000000010000000000000000000000000000000000000: n4311_o = 3'b111; + 59'b00000000000000000000001000000000000000000000000000000000000: n4311_o = 3'b111; + 59'b00000000000000000000000100000000000000000000000000000000000: n4311_o = 3'b111; + 59'b00000000000000000000000010000000000000000000000000000000000: n4311_o = 3'b111; + 59'b00000000000000000000000001000000000000000000000000000000000: n4311_o = 3'b111; + 59'b00000000000000000000000000100000000000000000000000000000000: n4311_o = n3334_o; + 59'b00000000000000000000000000010000000000000000000000000000000: n4311_o = 3'b111; + 59'b00000000000000000000000000001000000000000000000000000000000: n4311_o = 3'b111; + 59'b00000000000000000000000000000100000000000000000000000000000: n4311_o = 3'b111; + 59'b00000000000000000000000000000010000000000000000000000000000: n4311_o = 3'b111; + 59'b00000000000000000000000000000001000000000000000000000000000: n4311_o = n3228_o; + 59'b00000000000000000000000000000000100000000000000000000000000: n4311_o = 3'b111; + 59'b00000000000000000000000000000000010000000000000000000000000: n4311_o = n3173_o; + 59'b00000000000000000000000000000000001000000000000000000000000: n4311_o = 3'b111; + 59'b00000000000000000000000000000000000100000000000000000000000: n4311_o = 3'b111; + 59'b00000000000000000000000000000000000010000000000000000000000: n4311_o = n3061_o; + 59'b00000000000000000000000000000000000001000000000000000000000: n4311_o = 3'b111; + 59'b00000000000000000000000000000000000000100000000000000000000: n4311_o = n2861_o; + 59'b00000000000000000000000000000000000000010000000000000000000: n4311_o = 3'b111; + 59'b00000000000000000000000000000000000000001000000000000000000: n4311_o = 3'b111; + 59'b00000000000000000000000000000000000000000100000000000000000: n4311_o = 3'b111; + 59'b00000000000000000000000000000000000000000010000000000000000: n4311_o = n2807_o; + 59'b00000000000000000000000000000000000000000001000000000000000: n4311_o = n2750_o; + 59'b00000000000000000000000000000000000000000000100000000000000: n4311_o = 3'b111; + 59'b00000000000000000000000000000000000000000000010000000000000: n4311_o = n2702_o; + 59'b00000000000000000000000000000000000000000000001000000000000: n4311_o = n2669_o; + 59'b00000000000000000000000000000000000000000000000100000000000: n4311_o = 3'b111; + 59'b00000000000000000000000000000000000000000000000010000000000: n4311_o = n2582_o; + 59'b00000000000000000000000000000000000000000000000001000000000: n4311_o = n2556_o; + 59'b00000000000000000000000000000000000000000000000000100000000: n4311_o = n2536_o; + 59'b00000000000000000000000000000000000000000000000000010000000: n4311_o = n2519_o; + 59'b00000000000000000000000000000000000000000000000000001000000: n4311_o = n2499_o; + 59'b00000000000000000000000000000000000000000000000000000100000: n4311_o = n2485_o; + 59'b00000000000000000000000000000000000000000000000000000010000: n4311_o = n2468_o; + 59'b00000000000000000000000000000000000000000000000000000001000: n4311_o = n2428_o; + 59'b00000000000000000000000000000000000000000000000000000000100: n4311_o = n2394_o; + 59'b00000000000000000000000000000000000000000000000000000000010: n4311_o = 3'b111; + 59'b00000000000000000000000000000000000000000000000000000000001: n4311_o = 3'b111; + default: n4311_o = 3'bX; + endcase + /* T80_MCode.vhd:265:17 */ + always @* + case (n4123_o) + 59'b10000000000000000000000000000000000000000000000000000000000: n4314_o = 1'b0; + 59'b01000000000000000000000000000000000000000000000000000000000: n4314_o = 1'b0; + 59'b00100000000000000000000000000000000000000000000000000000000: n4314_o = 1'b0; + 59'b00010000000000000000000000000000000000000000000000000000000: n4314_o = n4108_o; + 59'b00001000000000000000000000000000000000000000000000000000000: n4314_o = n4088_o; + 59'b00000100000000000000000000000000000000000000000000000000000: n4314_o = 1'b0; + 59'b00000010000000000000000000000000000000000000000000000000000: n4314_o = 1'b0; + 59'b00000001000000000000000000000000000000000000000000000000000: n4314_o = 1'b0; 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+ 59'b00000000000000000000010000000000000000000000000000000000000: n4314_o = 1'b0; + 59'b00000000000000000000001000000000000000000000000000000000000: n4314_o = 1'b0; + 59'b00000000000000000000000100000000000000000000000000000000000: n4314_o = 1'b0; + 59'b00000000000000000000000010000000000000000000000000000000000: n4314_o = 1'b0; + 59'b00000000000000000000000001000000000000000000000000000000000: n4314_o = 1'b0; + 59'b00000000000000000000000000100000000000000000000000000000000: n4314_o = 1'b0; + 59'b00000000000000000000000000010000000000000000000000000000000: n4314_o = 1'b0; + 59'b00000000000000000000000000001000000000000000000000000000000: n4314_o = 1'b0; + 59'b00000000000000000000000000000100000000000000000000000000000: n4314_o = 1'b0; + 59'b00000000000000000000000000000010000000000000000000000000000: n4314_o = 1'b0; + 59'b00000000000000000000000000000001000000000000000000000000000: n4314_o = 1'b0; + 59'b00000000000000000000000000000000100000000000000000000000000: n4314_o = 1'b0; + 59'b00000000000000000000000000000000010000000000000000000000000: n4314_o = 1'b0; + 59'b00000000000000000000000000000000001000000000000000000000000: n4314_o = 1'b0; + 59'b00000000000000000000000000000000000100000000000000000000000: n4314_o = 1'b0; + 59'b00000000000000000000000000000000000010000000000000000000000: n4314_o = 1'b0; + 59'b00000000000000000000000000000000000001000000000000000000000: n4314_o = 1'b0; + 59'b00000000000000000000000000000000000000100000000000000000000: n4314_o = 1'b0; + 59'b00000000000000000000000000000000000000010000000000000000000: n4314_o = 1'b0; + 59'b00000000000000000000000000000000000000001000000000000000000: n4314_o = 1'b0; + 59'b00000000000000000000000000000000000000000100000000000000000: n4314_o = 1'b0; + 59'b00000000000000000000000000000000000000000010000000000000000: n4314_o = 1'b0; + 59'b00000000000000000000000000000000000000000001000000000000000: n4314_o = 1'b0; + 59'b00000000000000000000000000000000000000000000100000000000000: n4314_o = 1'b0; + 59'b00000000000000000000000000000000000000000000010000000000000: n4314_o = 1'b0; + 59'b00000000000000000000000000000000000000000000001000000000000: n4314_o = 1'b0; + 59'b00000000000000000000000000000000000000000000000100000000000: n4314_o = 1'b0; + 59'b00000000000000000000000000000000000000000000000010000000000: n4314_o = 1'b0; + 59'b00000000000000000000000000000000000000000000000001000000000: n4314_o = 1'b0; + 59'b00000000000000000000000000000000000000000000000000100000000: n4314_o = 1'b0; + 59'b00000000000000000000000000000000000000000000000000010000000: n4314_o = 1'b0; + 59'b00000000000000000000000000000000000000000000000000001000000: n4314_o = 1'b0; + 59'b00000000000000000000000000000000000000000000000000000100000: n4314_o = 1'b0; + 59'b00000000000000000000000000000000000000000000000000000010000: n4314_o = 1'b0; + 59'b00000000000000000000000000000000000000000000000000000001000: n4314_o = 1'b0; + 59'b00000000000000000000000000000000000000000000000000000000100: n4314_o = 1'b0; + 59'b00000000000000000000000000000000000000000000000000000000010: n4314_o = 1'b0; + 59'b00000000000000000000000000000000000000000000000000000000001: n4314_o = 1'b0; + default: n4314_o = 1'bX; + endcase + /* T80_MCode.vhd:265:17 */ + always @* + case (n4123_o) + 59'b10000000000000000000000000000000000000000000000000000000000: n4317_o = 1'b0; + 59'b01000000000000000000000000000000000000000000000000000000000: n4317_o = 1'b0; + 59'b00100000000000000000000000000000000000000000000000000000000: n4317_o = 1'b0; + 59'b00010000000000000000000000000000000000000000000000000000000: n4317_o = 1'b0; + 59'b00001000000000000000000000000000000000000000000000000000000: n4317_o = 1'b0; + 59'b00000100000000000000000000000000000000000000000000000000000: n4317_o = 1'b0; + 59'b00000010000000000000000000000000000000000000000000000000000: n4317_o = n3992_o; + 59'b00000001000000000000000000000000000000000000000000000000000: n4317_o = n3920_o; + 59'b00000000100000000000000000000000000000000000000000000000000: n4317_o = 1'b0; + 59'b00000000010000000000000000000000000000000000000000000000000: n4317_o = 1'b0; + 59'b00000000001000000000000000000000000000000000000000000000000: n4317_o = 1'b0; + 59'b00000000000100000000000000000000000000000000000000000000000: n4317_o = 1'b0; + 59'b00000000000010000000000000000000000000000000000000000000000: n4317_o = 1'b0; + 59'b00000000000001000000000000000000000000000000000000000000000: n4317_o = 1'b0; + 59'b00000000000000100000000000000000000000000000000000000000000: n4317_o = 1'b0; + 59'b00000000000000010000000000000000000000000000000000000000000: n4317_o = 1'b0; + 59'b00000000000000001000000000000000000000000000000000000000000: n4317_o = 1'b0; + 59'b00000000000000000100000000000000000000000000000000000000000: n4317_o = n3546_o; + 59'b00000000000000000010000000000000000000000000000000000000000: n4317_o = n3485_o; + 59'b00000000000000000001000000000000000000000000000000000000000: n4317_o = 1'b0; + 59'b00000000000000000000100000000000000000000000000000000000000: n4317_o = 1'b0; + 59'b00000000000000000000010000000000000000000000000000000000000: n4317_o = 1'b0; + 59'b00000000000000000000001000000000000000000000000000000000000: n4317_o = 1'b0; + 59'b00000000000000000000000100000000000000000000000000000000000: n4317_o = 1'b0; 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+ 59'b00000000000000000000000000000000000001000000000000000000000: n4317_o = 1'b0; + 59'b00000000000000000000000000000000000000100000000000000000000: n4317_o = 1'b0; + 59'b00000000000000000000000000000000000000010000000000000000000: n4317_o = 1'b0; + 59'b00000000000000000000000000000000000000001000000000000000000: n4317_o = 1'b0; + 59'b00000000000000000000000000000000000000000100000000000000000: n4317_o = 1'b0; + 59'b00000000000000000000000000000000000000000010000000000000000: n4317_o = 1'b0; + 59'b00000000000000000000000000000000000000000001000000000000000: n4317_o = 1'b0; + 59'b00000000000000000000000000000000000000000000100000000000000: n4317_o = 1'b0; + 59'b00000000000000000000000000000000000000000000010000000000000: n4317_o = 1'b0; + 59'b00000000000000000000000000000000000000000000001000000000000: n4317_o = 1'b0; + 59'b00000000000000000000000000000000000000000000000100000000000: n4317_o = 1'b0; + 59'b00000000000000000000000000000000000000000000000010000000000: n4317_o = 1'b0; + 59'b00000000000000000000000000000000000000000000000001000000000: n4317_o = 1'b0; + 59'b00000000000000000000000000000000000000000000000000100000000: n4317_o = 1'b0; + 59'b00000000000000000000000000000000000000000000000000010000000: n4317_o = 1'b0; + 59'b00000000000000000000000000000000000000000000000000001000000: n4317_o = 1'b0; + 59'b00000000000000000000000000000000000000000000000000000100000: n4317_o = 1'b0; + 59'b00000000000000000000000000000000000000000000000000000010000: n4317_o = 1'b0; + 59'b00000000000000000000000000000000000000000000000000000001000: n4317_o = 1'b0; + 59'b00000000000000000000000000000000000000000000000000000000100: n4317_o = 1'b0; + 59'b00000000000000000000000000000000000000000000000000000000010: n4317_o = 1'b0; + 59'b00000000000000000000000000000000000000000000000000000000001: n4317_o = 1'b0; + default: n4317_o = 1'bX; + endcase + /* T80_MCode.vhd:265:17 */ + always @* + case (n4123_o) + 59'b10000000000000000000000000000000000000000000000000000000000: n4320_o = 1'b0; + 59'b01000000000000000000000000000000000000000000000000000000000: n4320_o = 1'b0; + 59'b00100000000000000000000000000000000000000000000000000000000: n4320_o = 1'b0; + 59'b00010000000000000000000000000000000000000000000000000000000: n4320_o = 1'b0; + 59'b00001000000000000000000000000000000000000000000000000000000: n4320_o = 1'b0; + 59'b00000100000000000000000000000000000000000000000000000000000: n4320_o = 1'b0; + 59'b00000010000000000000000000000000000000000000000000000000000: n4320_o = 1'b0; + 59'b00000001000000000000000000000000000000000000000000000000000: n4320_o = 1'b0; + 59'b00000000100000000000000000000000000000000000000000000000000: n4320_o = 1'b0; + 59'b00000000010000000000000000000000000000000000000000000000000: n4320_o = 1'b0; + 59'b00000000001000000000000000000000000000000000000000000000000: n4320_o = n3733_o; + 59'b00000000000100000000000000000000000000000000000000000000000: n4320_o = 1'b0; + 59'b00000000000010000000000000000000000000000000000000000000000: n4320_o = n3695_o; + 59'b00000000000001000000000000000000000000000000000000000000000: n4320_o = n3669_o; + 59'b00000000000000100000000000000000000000000000000000000000000: n4320_o = n3642_o; + 59'b00000000000000010000000000000000000000000000000000000000000: n4320_o = n3616_o; + 59'b00000000000000001000000000000000000000000000000000000000000: n4320_o = n3589_o; + 59'b00000000000000000100000000000000000000000000000000000000000: n4320_o = 1'b0; + 59'b00000000000000000010000000000000000000000000000000000000000: n4320_o = 1'b0; + 59'b00000000000000000001000000000000000000000000000000000000000: n4320_o = 1'b0; + 59'b00000000000000000000100000000000000000000000000000000000000: n4320_o = 1'b0; + 59'b00000000000000000000010000000000000000000000000000000000000: n4320_o = 1'b0; + 59'b00000000000000000000001000000000000000000000000000000000000: n4320_o = 1'b0; + 59'b00000000000000000000000100000000000000000000000000000000000: n4320_o = 1'b0; + 59'b00000000000000000000000010000000000000000000000000000000000: n4320_o = 1'b0; + 59'b00000000000000000000000001000000000000000000000000000000000: n4320_o = 1'b0; + 59'b00000000000000000000000000100000000000000000000000000000000: n4320_o = 1'b0; + 59'b00000000000000000000000000010000000000000000000000000000000: n4320_o = 1'b0; + 59'b00000000000000000000000000001000000000000000000000000000000: n4320_o = 1'b0; + 59'b00000000000000000000000000000100000000000000000000000000000: n4320_o = 1'b0; + 59'b00000000000000000000000000000010000000000000000000000000000: n4320_o = 1'b0; + 59'b00000000000000000000000000000001000000000000000000000000000: n4320_o = 1'b0; + 59'b00000000000000000000000000000000100000000000000000000000000: n4320_o = 1'b0; + 59'b00000000000000000000000000000000010000000000000000000000000: n4320_o = 1'b0; + 59'b00000000000000000000000000000000001000000000000000000000000: n4320_o = 1'b0; + 59'b00000000000000000000000000000000000100000000000000000000000: n4320_o = 1'b0; + 59'b00000000000000000000000000000000000010000000000000000000000: n4320_o = 1'b0; + 59'b00000000000000000000000000000000000001000000000000000000000: n4320_o = 1'b0; + 59'b00000000000000000000000000000000000000100000000000000000000: n4320_o = 1'b0; + 59'b00000000000000000000000000000000000000010000000000000000000: n4320_o = 1'b0; + 59'b00000000000000000000000000000000000000001000000000000000000: n4320_o = 1'b0; + 59'b00000000000000000000000000000000000000000100000000000000000: n4320_o = 1'b0; + 59'b00000000000000000000000000000000000000000010000000000000000: n4320_o = 1'b0; + 59'b00000000000000000000000000000000000000000001000000000000000: n4320_o = 1'b0; + 59'b00000000000000000000000000000000000000000000100000000000000: n4320_o = 1'b0; + 59'b00000000000000000000000000000000000000000000010000000000000: n4320_o = 1'b0; + 59'b00000000000000000000000000000000000000000000001000000000000: n4320_o = 1'b0; + 59'b00000000000000000000000000000000000000000000000100000000000: n4320_o = 1'b0; + 59'b00000000000000000000000000000000000000000000000010000000000: n4320_o = 1'b0; + 59'b00000000000000000000000000000000000000000000000001000000000: n4320_o = 1'b0; + 59'b00000000000000000000000000000000000000000000000000100000000: n4320_o = 1'b0; + 59'b00000000000000000000000000000000000000000000000000010000000: n4320_o = 1'b0; + 59'b00000000000000000000000000000000000000000000000000001000000: n4320_o = 1'b0; + 59'b00000000000000000000000000000000000000000000000000000100000: n4320_o = 1'b0; + 59'b00000000000000000000000000000000000000000000000000000010000: n4320_o = 1'b0; + 59'b00000000000000000000000000000000000000000000000000000001000: n4320_o = 1'b0; + 59'b00000000000000000000000000000000000000000000000000000000100: n4320_o = 1'b0; + 59'b00000000000000000000000000000000000000000000000000000000010: n4320_o = 1'b0; + 59'b00000000000000000000000000000000000000000000000000000000001: n4320_o = 1'b0; + default: n4320_o = 1'bX; + endcase + /* T80_MCode.vhd:265:17 */ + always @* + case (n4123_o) + 59'b10000000000000000000000000000000000000000000000000000000000: n4324_o = 1'b0; + 59'b01000000000000000000000000000000000000000000000000000000000: n4324_o = 1'b0; + 59'b00100000000000000000000000000000000000000000000000000000000: n4324_o = 1'b0; + 59'b00010000000000000000000000000000000000000000000000000000000: n4324_o = 1'b0; + 59'b00001000000000000000000000000000000000000000000000000000000: n4324_o = 1'b0; + 59'b00000100000000000000000000000000000000000000000000000000000: n4324_o = 1'b0; + 59'b00000010000000000000000000000000000000000000000000000000000: n4324_o = 1'b0; + 59'b00000001000000000000000000000000000000000000000000000000000: n4324_o = 1'b0; + 59'b00000000100000000000000000000000000000000000000000000000000: n4324_o = 1'b0; + 59'b00000000010000000000000000000000000000000000000000000000000: n4324_o = 1'b0; + 59'b00000000001000000000000000000000000000000000000000000000000: n4324_o = 1'b0; + 59'b00000000000100000000000000000000000000000000000000000000000: n4324_o = 1'b1; + 59'b00000000000010000000000000000000000000000000000000000000000: n4324_o = 1'b0; + 59'b00000000000001000000000000000000000000000000000000000000000: n4324_o = 1'b0; + 59'b00000000000000100000000000000000000000000000000000000000000: n4324_o = 1'b0; + 59'b00000000000000010000000000000000000000000000000000000000000: n4324_o = 1'b0; + 59'b00000000000000001000000000000000000000000000000000000000000: n4324_o = 1'b0; + 59'b00000000000000000100000000000000000000000000000000000000000: n4324_o = 1'b0; + 59'b00000000000000000010000000000000000000000000000000000000000: n4324_o = 1'b0; + 59'b00000000000000000001000000000000000000000000000000000000000: n4324_o = 1'b0; + 59'b00000000000000000000100000000000000000000000000000000000000: n4324_o = 1'b0; + 59'b00000000000000000000010000000000000000000000000000000000000: n4324_o = 1'b0; + 59'b00000000000000000000001000000000000000000000000000000000000: n4324_o = 1'b0; + 59'b00000000000000000000000100000000000000000000000000000000000: n4324_o = 1'b0; + 59'b00000000000000000000000010000000000000000000000000000000000: n4324_o = 1'b0; + 59'b00000000000000000000000001000000000000000000000000000000000: n4324_o = 1'b0; + 59'b00000000000000000000000000100000000000000000000000000000000: n4324_o = 1'b0; + 59'b00000000000000000000000000010000000000000000000000000000000: n4324_o = 1'b0; + 59'b00000000000000000000000000001000000000000000000000000000000: n4324_o = 1'b0; + 59'b00000000000000000000000000000100000000000000000000000000000: n4324_o = 1'b0; + 59'b00000000000000000000000000000010000000000000000000000000000: n4324_o = 1'b0; + 59'b00000000000000000000000000000001000000000000000000000000000: n4324_o = 1'b0; + 59'b00000000000000000000000000000000100000000000000000000000000: n4324_o = 1'b0; + 59'b00000000000000000000000000000000010000000000000000000000000: n4324_o = 1'b0; + 59'b00000000000000000000000000000000001000000000000000000000000: n4324_o = 1'b0; + 59'b00000000000000000000000000000000000100000000000000000000000: n4324_o = 1'b0; + 59'b00000000000000000000000000000000000010000000000000000000000: n4324_o = 1'b0; + 59'b00000000000000000000000000000000000001000000000000000000000: n4324_o = 1'b0; + 59'b00000000000000000000000000000000000000100000000000000000000: n4324_o = 1'b0; + 59'b00000000000000000000000000000000000000010000000000000000000: n4324_o = 1'b0; + 59'b00000000000000000000000000000000000000001000000000000000000: n4324_o = 1'b0; + 59'b00000000000000000000000000000000000000000100000000000000000: n4324_o = 1'b0; + 59'b00000000000000000000000000000000000000000010000000000000000: n4324_o = 1'b0; + 59'b00000000000000000000000000000000000000000001000000000000000: n4324_o = 1'b0; + 59'b00000000000000000000000000000000000000000000100000000000000: n4324_o = 1'b0; + 59'b00000000000000000000000000000000000000000000010000000000000: n4324_o = 1'b0; + 59'b00000000000000000000000000000000000000000000001000000000000: n4324_o = 1'b0; + 59'b00000000000000000000000000000000000000000000000100000000000: n4324_o = 1'b0; + 59'b00000000000000000000000000000000000000000000000010000000000: n4324_o = 1'b0; + 59'b00000000000000000000000000000000000000000000000001000000000: n4324_o = 1'b0; + 59'b00000000000000000000000000000000000000000000000000100000000: n4324_o = 1'b0; + 59'b00000000000000000000000000000000000000000000000000010000000: n4324_o = 1'b0; + 59'b00000000000000000000000000000000000000000000000000001000000: n4324_o = 1'b0; + 59'b00000000000000000000000000000000000000000000000000000100000: n4324_o = 1'b0; + 59'b00000000000000000000000000000000000000000000000000000010000: n4324_o = 1'b0; + 59'b00000000000000000000000000000000000000000000000000000001000: n4324_o = 1'b0; + 59'b00000000000000000000000000000000000000000000000000000000100: n4324_o = 1'b0; + 59'b00000000000000000000000000000000000000000000000000000000010: n4324_o = 1'b0; + 59'b00000000000000000000000000000000000000000000000000000000001: n4324_o = 1'b0; + default: n4324_o = 1'bX; + endcase + /* T80_MCode.vhd:265:17 */ + always @* + case (n4123_o) + 59'b10000000000000000000000000000000000000000000000000000000000: n4327_o = 1'b0; + 59'b01000000000000000000000000000000000000000000000000000000000: n4327_o = 1'b0; + 59'b00100000000000000000000000000000000000000000000000000000000: n4327_o = 1'b0; + 59'b00010000000000000000000000000000000000000000000000000000000: n4327_o = 1'b0; + 59'b00001000000000000000000000000000000000000000000000000000000: n4327_o = 1'b0; + 59'b00000100000000000000000000000000000000000000000000000000000: n4327_o = 1'b0; + 59'b00000010000000000000000000000000000000000000000000000000000: n4327_o = 1'b0; + 59'b00000001000000000000000000000000000000000000000000000000000: n4327_o = 1'b0; + 59'b00000000100000000000000000000000000000000000000000000000000: n4327_o = n3868_o; + 59'b00000000010000000000000000000000000000000000000000000000000: n4327_o = n3773_o; + 59'b00000000001000000000000000000000000000000000000000000000000: n4327_o = 1'b0; + 59'b00000000000100000000000000000000000000000000000000000000000: n4327_o = 1'b0; + 59'b00000000000010000000000000000000000000000000000000000000000: n4327_o = 1'b0; + 59'b00000000000001000000000000000000000000000000000000000000000: n4327_o = 1'b0; + 59'b00000000000000100000000000000000000000000000000000000000000: n4327_o = 1'b0; + 59'b00000000000000010000000000000000000000000000000000000000000: n4327_o = 1'b0; + 59'b00000000000000001000000000000000000000000000000000000000000: n4327_o = 1'b0; + 59'b00000000000000000100000000000000000000000000000000000000000: n4327_o = 1'b0; + 59'b00000000000000000010000000000000000000000000000000000000000: n4327_o = 1'b0; + 59'b00000000000000000001000000000000000000000000000000000000000: n4327_o = 1'b0; + 59'b00000000000000000000100000000000000000000000000000000000000: n4327_o = 1'b0; + 59'b00000000000000000000010000000000000000000000000000000000000: n4327_o = 1'b0; + 59'b00000000000000000000001000000000000000000000000000000000000: n4327_o = 1'b0; + 59'b00000000000000000000000100000000000000000000000000000000000: n4327_o = 1'b0; + 59'b00000000000000000000000010000000000000000000000000000000000: n4327_o = 1'b0; + 59'b00000000000000000000000001000000000000000000000000000000000: n4327_o = 1'b0; + 59'b00000000000000000000000000100000000000000000000000000000000: n4327_o = 1'b0; + 59'b00000000000000000000000000010000000000000000000000000000000: n4327_o = 1'b0; + 59'b00000000000000000000000000001000000000000000000000000000000: n4327_o = 1'b0; + 59'b00000000000000000000000000000100000000000000000000000000000: n4327_o = 1'b0; + 59'b00000000000000000000000000000010000000000000000000000000000: n4327_o = 1'b0; + 59'b00000000000000000000000000000001000000000000000000000000000: n4327_o = 1'b0; + 59'b00000000000000000000000000000000100000000000000000000000000: n4327_o = 1'b0; + 59'b00000000000000000000000000000000010000000000000000000000000: n4327_o = 1'b0; + 59'b00000000000000000000000000000000001000000000000000000000000: n4327_o = 1'b0; + 59'b00000000000000000000000000000000000100000000000000000000000: n4327_o = 1'b0; + 59'b00000000000000000000000000000000000010000000000000000000000: n4327_o = 1'b0; + 59'b00000000000000000000000000000000000001000000000000000000000: n4327_o = 1'b0; + 59'b00000000000000000000000000000000000000100000000000000000000: n4327_o = 1'b0; + 59'b00000000000000000000000000000000000000010000000000000000000: n4327_o = 1'b0; + 59'b00000000000000000000000000000000000000001000000000000000000: n4327_o = 1'b0; + 59'b00000000000000000000000000000000000000000100000000000000000: n4327_o = 1'b0; + 59'b00000000000000000000000000000000000000000010000000000000000: n4327_o = 1'b0; + 59'b00000000000000000000000000000000000000000001000000000000000: n4327_o = 1'b0; + 59'b00000000000000000000000000000000000000000000100000000000000: n4327_o = 1'b0; + 59'b00000000000000000000000000000000000000000000010000000000000: n4327_o = 1'b0; + 59'b00000000000000000000000000000000000000000000001000000000000: n4327_o = 1'b0; + 59'b00000000000000000000000000000000000000000000000100000000000: n4327_o = 1'b0; + 59'b00000000000000000000000000000000000000000000000010000000000: n4327_o = 1'b0; + 59'b00000000000000000000000000000000000000000000000001000000000: n4327_o = 1'b0; + 59'b00000000000000000000000000000000000000000000000000100000000: n4327_o = 1'b0; + 59'b00000000000000000000000000000000000000000000000000010000000: n4327_o = 1'b0; + 59'b00000000000000000000000000000000000000000000000000001000000: n4327_o = 1'b0; + 59'b00000000000000000000000000000000000000000000000000000100000: n4327_o = 1'b0; + 59'b00000000000000000000000000000000000000000000000000000010000: n4327_o = 1'b0; + 59'b00000000000000000000000000000000000000000000000000000001000: n4327_o = 1'b0; + 59'b00000000000000000000000000000000000000000000000000000000100: n4327_o = 1'b0; + 59'b00000000000000000000000000000000000000000000000000000000010: n4327_o = 1'b0; + 59'b00000000000000000000000000000000000000000000000000000000001: n4327_o = 1'b0; + default: n4327_o = 1'bX; + endcase + /* T80_MCode.vhd:265:17 */ + always @* + case (n4123_o) + 59'b10000000000000000000000000000000000000000000000000000000000: n4330_o = 1'b0; + 59'b01000000000000000000000000000000000000000000000000000000000: n4330_o = 1'b0; + 59'b00100000000000000000000000000000000000000000000000000000000: n4330_o = 1'b0; + 59'b00010000000000000000000000000000000000000000000000000000000: n4330_o = 1'b0; + 59'b00001000000000000000000000000000000000000000000000000000000: n4330_o = 1'b0; + 59'b00000100000000000000000000000000000000000000000000000000000: n4330_o = n4043_o; + 59'b00000010000000000000000000000000000000000000000000000000000: n4330_o = 1'b0; + 59'b00000001000000000000000000000000000000000000000000000000000: n4330_o = 1'b0; + 59'b00000000100000000000000000000000000000000000000000000000000: n4330_o = 1'b0; + 59'b00000000010000000000000000000000000000000000000000000000000: n4330_o = 1'b0; + 59'b00000000001000000000000000000000000000000000000000000000000: n4330_o = 1'b0; + 59'b00000000000100000000000000000000000000000000000000000000000: n4330_o = 1'b0; + 59'b00000000000010000000000000000000000000000000000000000000000: n4330_o = 1'b0; + 59'b00000000000001000000000000000000000000000000000000000000000: n4330_o = 1'b0; + 59'b00000000000000100000000000000000000000000000000000000000000: n4330_o = 1'b0; + 59'b00000000000000010000000000000000000000000000000000000000000: n4330_o = 1'b0; + 59'b00000000000000001000000000000000000000000000000000000000000: n4330_o = 1'b0; + 59'b00000000000000000100000000000000000000000000000000000000000: n4330_o = 1'b0; + 59'b00000000000000000010000000000000000000000000000000000000000: n4330_o = 1'b0; + 59'b00000000000000000001000000000000000000000000000000000000000: n4330_o = 1'b0; + 59'b00000000000000000000100000000000000000000000000000000000000: n4330_o = 1'b0; + 59'b00000000000000000000010000000000000000000000000000000000000: n4330_o = 1'b0; + 59'b00000000000000000000001000000000000000000000000000000000000: n4330_o = 1'b0; + 59'b00000000000000000000000100000000000000000000000000000000000: n4330_o = 1'b0; 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+ 59'b00000000000000000000000000000000000001000000000000000000000: n4330_o = 1'b0; + 59'b00000000000000000000000000000000000000100000000000000000000: n4330_o = 1'b0; + 59'b00000000000000000000000000000000000000010000000000000000000: n4330_o = 1'b0; + 59'b00000000000000000000000000000000000000001000000000000000000: n4330_o = 1'b0; + 59'b00000000000000000000000000000000000000000100000000000000000: n4330_o = 1'b0; + 59'b00000000000000000000000000000000000000000010000000000000000: n4330_o = 1'b0; + 59'b00000000000000000000000000000000000000000001000000000000000: n4330_o = 1'b0; + 59'b00000000000000000000000000000000000000000000100000000000000: n4330_o = 1'b0; + 59'b00000000000000000000000000000000000000000000010000000000000: n4330_o = 1'b0; + 59'b00000000000000000000000000000000000000000000001000000000000: n4330_o = 1'b0; + 59'b00000000000000000000000000000000000000000000000100000000000: n4330_o = 1'b0; + 59'b00000000000000000000000000000000000000000000000010000000000: n4330_o = 1'b0; + 59'b00000000000000000000000000000000000000000000000001000000000: n4330_o = 1'b0; + 59'b00000000000000000000000000000000000000000000000000100000000: n4330_o = 1'b0; + 59'b00000000000000000000000000000000000000000000000000010000000: n4330_o = 1'b0; + 59'b00000000000000000000000000000000000000000000000000001000000: n4330_o = 1'b0; + 59'b00000000000000000000000000000000000000000000000000000100000: n4330_o = 1'b0; + 59'b00000000000000000000000000000000000000000000000000000010000: n4330_o = 1'b0; + 59'b00000000000000000000000000000000000000000000000000000001000: n4330_o = 1'b0; + 59'b00000000000000000000000000000000000000000000000000000000100: n4330_o = 1'b0; + 59'b00000000000000000000000000000000000000000000000000000000010: n4330_o = 1'b0; + 59'b00000000000000000000000000000000000000000000000000000000001: n4330_o = 1'b0; + default: n4330_o = 1'bX; + endcase + /* T80_MCode.vhd:265:17 */ + always @* + case (n4123_o) + 59'b10000000000000000000000000000000000000000000000000000000000: n4333_o = 1'b0; + 59'b01000000000000000000000000000000000000000000000000000000000: n4333_o = 1'b0; + 59'b00100000000000000000000000000000000000000000000000000000000: n4333_o = 1'b0; + 59'b00010000000000000000000000000000000000000000000000000000000: n4333_o = 1'b0; + 59'b00001000000000000000000000000000000000000000000000000000000: n4333_o = 1'b0; + 59'b00000100000000000000000000000000000000000000000000000000000: n4333_o = 1'b0; + 59'b00000010000000000000000000000000000000000000000000000000000: n4333_o = n3995_o; + 59'b00000001000000000000000000000000000000000000000000000000000: n4333_o = n3923_o; + 59'b00000000100000000000000000000000000000000000000000000000000: n4333_o = n3871_o; + 59'b00000000010000000000000000000000000000000000000000000000000: n4333_o = n3776_o; + 59'b00000000001000000000000000000000000000000000000000000000000: n4333_o = 1'b0; + 59'b00000000000100000000000000000000000000000000000000000000000: n4333_o = 1'b0; + 59'b00000000000010000000000000000000000000000000000000000000000: n4333_o = 1'b0; + 59'b00000000000001000000000000000000000000000000000000000000000: n4333_o = 1'b0; + 59'b00000000000000100000000000000000000000000000000000000000000: n4333_o = 1'b0; + 59'b00000000000000010000000000000000000000000000000000000000000: n4333_o = 1'b0; + 59'b00000000000000001000000000000000000000000000000000000000000: n4333_o = 1'b0; + 59'b00000000000000000100000000000000000000000000000000000000000: n4333_o = n3549_o; + 59'b00000000000000000010000000000000000000000000000000000000000: n4333_o = n3488_o; + 59'b00000000000000000001000000000000000000000000000000000000000: n4333_o = 1'b0; + 59'b00000000000000000000100000000000000000000000000000000000000: n4333_o = 1'b0; + 59'b00000000000000000000010000000000000000000000000000000000000: n4333_o = 1'b0; + 59'b00000000000000000000001000000000000000000000000000000000000: n4333_o = 1'b0; + 59'b00000000000000000000000100000000000000000000000000000000000: n4333_o = 1'b0; + 59'b00000000000000000000000010000000000000000000000000000000000: n4333_o = 1'b0; + 59'b00000000000000000000000001000000000000000000000000000000000: n4333_o = 1'b0; + 59'b00000000000000000000000000100000000000000000000000000000000: n4333_o = n3338_o; + 59'b00000000000000000000000000010000000000000000000000000000000: n4333_o = 1'b0; + 59'b00000000000000000000000000001000000000000000000000000000000: n4333_o = 1'b0; + 59'b00000000000000000000000000000100000000000000000000000000000: n4333_o = 1'b0; + 59'b00000000000000000000000000000010000000000000000000000000000: n4333_o = 1'b0; + 59'b00000000000000000000000000000001000000000000000000000000000: n4333_o = 1'b0; + 59'b00000000000000000000000000000000100000000000000000000000000: n4333_o = 1'b0; + 59'b00000000000000000000000000000000010000000000000000000000000: n4333_o = 1'b0; + 59'b00000000000000000000000000000000001000000000000000000000000: n4333_o = 1'b0; + 59'b00000000000000000000000000000000000100000000000000000000000: n4333_o = 1'b0; + 59'b00000000000000000000000000000000000010000000000000000000000: n4333_o = 1'b0; + 59'b00000000000000000000000000000000000001000000000000000000000: n4333_o = 1'b0; + 59'b00000000000000000000000000000000000000100000000000000000000: n4333_o = n2864_o; + 59'b00000000000000000000000000000000000000010000000000000000000: n4333_o = 1'b0; + 59'b00000000000000000000000000000000000000001000000000000000000: n4333_o = 1'b0; + 59'b00000000000000000000000000000000000000000100000000000000000: n4333_o = 1'b0; + 59'b00000000000000000000000000000000000000000010000000000000000: n4333_o = 1'b0; + 59'b00000000000000000000000000000000000000000001000000000000000: n4333_o = 1'b0; + 59'b00000000000000000000000000000000000000000000100000000000000: n4333_o = 1'b0; + 59'b00000000000000000000000000000000000000000000010000000000000: n4333_o = n2705_o; + 59'b00000000000000000000000000000000000000000000001000000000000: n4333_o = n2672_o; + 59'b00000000000000000000000000000000000000000000000100000000000: n4333_o = 1'b0; + 59'b00000000000000000000000000000000000000000000000010000000000: n4333_o = n2585_o; + 59'b00000000000000000000000000000000000000000000000001000000000: n4333_o = 1'b0; + 59'b00000000000000000000000000000000000000000000000000100000000: n4333_o = 1'b0; + 59'b00000000000000000000000000000000000000000000000000010000000: n4333_o = n2522_o; + 59'b00000000000000000000000000000000000000000000000000001000000: n4333_o = 1'b0; + 59'b00000000000000000000000000000000000000000000000000000100000: n4333_o = 1'b0; + 59'b00000000000000000000000000000000000000000000000000000010000: n4333_o = 1'b0; + 59'b00000000000000000000000000000000000000000000000000000001000: n4333_o = 1'b0; + 59'b00000000000000000000000000000000000000000000000000000000100: n4333_o = 1'b0; + 59'b00000000000000000000000000000000000000000000000000000000010: n4333_o = 1'b0; + 59'b00000000000000000000000000000000000000000000000000000000001: n4333_o = 1'b0; + default: n4333_o = 1'bX; + endcase + /* T80_MCode.vhd:265:17 */ + always @* + case (n4123_o) + 59'b10000000000000000000000000000000000000000000000000000000000: n4336_o = 1'b0; + 59'b01000000000000000000000000000000000000000000000000000000000: n4336_o = 1'b0; + 59'b00100000000000000000000000000000000000000000000000000000000: n4336_o = 1'b0; + 59'b00010000000000000000000000000000000000000000000000000000000: n4336_o = 1'b0; + 59'b00001000000000000000000000000000000000000000000000000000000: n4336_o = 1'b0; + 59'b00000100000000000000000000000000000000000000000000000000000: n4336_o = 1'b0; + 59'b00000010000000000000000000000000000000000000000000000000000: n4336_o = 1'b0; + 59'b00000001000000000000000000000000000000000000000000000000000: n4336_o = 1'b0; + 59'b00000000100000000000000000000000000000000000000000000000000: n4336_o = n3874_o; + 59'b00000000010000000000000000000000000000000000000000000000000: n4336_o = n3779_o; + 59'b00000000001000000000000000000000000000000000000000000000000: n4336_o = 1'b0; + 59'b00000000000100000000000000000000000000000000000000000000000: n4336_o = 1'b0; + 59'b00000000000010000000000000000000000000000000000000000000000: n4336_o = 1'b0; + 59'b00000000000001000000000000000000000000000000000000000000000: n4336_o = 1'b0; + 59'b00000000000000100000000000000000000000000000000000000000000: n4336_o = 1'b0; + 59'b00000000000000010000000000000000000000000000000000000000000: n4336_o = 1'b0; + 59'b00000000000000001000000000000000000000000000000000000000000: n4336_o = 1'b0; + 59'b00000000000000000100000000000000000000000000000000000000000: n4336_o = n3552_o; + 59'b00000000000000000010000000000000000000000000000000000000000: n4336_o = n3491_o; + 59'b00000000000000000001000000000000000000000000000000000000000: n4336_o = 1'b0; + 59'b00000000000000000000100000000000000000000000000000000000000: n4336_o = 1'b0; + 59'b00000000000000000000010000000000000000000000000000000000000: n4336_o = 1'b0; + 59'b00000000000000000000001000000000000000000000000000000000000: n4336_o = 1'b0; + 59'b00000000000000000000000100000000000000000000000000000000000: n4336_o = 1'b0; + 59'b00000000000000000000000010000000000000000000000000000000000: n4336_o = 1'b0; + 59'b00000000000000000000000001000000000000000000000000000000000: n4336_o = 1'b0; + 59'b00000000000000000000000000100000000000000000000000000000000: n4336_o = 1'b0; + 59'b00000000000000000000000000010000000000000000000000000000000: n4336_o = 1'b0; + 59'b00000000000000000000000000001000000000000000000000000000000: n4336_o = 1'b0; + 59'b00000000000000000000000000000100000000000000000000000000000: n4336_o = 1'b0; + 59'b00000000000000000000000000000010000000000000000000000000000: n4336_o = 1'b0; + 59'b00000000000000000000000000000001000000000000000000000000000: n4336_o = 1'b0; + 59'b00000000000000000000000000000000100000000000000000000000000: n4336_o = 1'b0; + 59'b00000000000000000000000000000000010000000000000000000000000: n4336_o = 1'b0; + 59'b00000000000000000000000000000000001000000000000000000000000: n4336_o = 1'b0; + 59'b00000000000000000000000000000000000100000000000000000000000: n4336_o = 1'b0; + 59'b00000000000000000000000000000000000010000000000000000000000: n4336_o = 1'b0; + 59'b00000000000000000000000000000000000001000000000000000000000: n4336_o = 1'b0; + 59'b00000000000000000000000000000000000000100000000000000000000: n4336_o = n2867_o; + 59'b00000000000000000000000000000000000000010000000000000000000: n4336_o = 1'b0; + 59'b00000000000000000000000000000000000000001000000000000000000: n4336_o = 1'b0; + 59'b00000000000000000000000000000000000000000100000000000000000: n4336_o = 1'b0; + 59'b00000000000000000000000000000000000000000010000000000000000: n4336_o = 1'b0; + 59'b00000000000000000000000000000000000000000001000000000000000: n4336_o = 1'b0; + 59'b00000000000000000000000000000000000000000000100000000000000: n4336_o = 1'b0; + 59'b00000000000000000000000000000000000000000000010000000000000: n4336_o = n2708_o; + 59'b00000000000000000000000000000000000000000000001000000000000: n4336_o = n2675_o; + 59'b00000000000000000000000000000000000000000000000100000000000: n4336_o = 1'b0; + 59'b00000000000000000000000000000000000000000000000010000000000: n4336_o = 1'b0; + 59'b00000000000000000000000000000000000000000000000001000000000: n4336_o = 1'b0; + 59'b00000000000000000000000000000000000000000000000000100000000: n4336_o = 1'b0; + 59'b00000000000000000000000000000000000000000000000000010000000: n4336_o = 1'b0; + 59'b00000000000000000000000000000000000000000000000000001000000: n4336_o = 1'b0; + 59'b00000000000000000000000000000000000000000000000000000100000: n4336_o = 1'b0; + 59'b00000000000000000000000000000000000000000000000000000010000: n4336_o = 1'b0; + 59'b00000000000000000000000000000000000000000000000000000001000: n4336_o = 1'b0; + 59'b00000000000000000000000000000000000000000000000000000000100: n4336_o = 1'b0; + 59'b00000000000000000000000000000000000000000000000000000000010: n4336_o = 1'b0; + 59'b00000000000000000000000000000000000000000000000000000000001: n4336_o = 1'b0; + default: n4336_o = 1'bX; + endcase + /* T80_MCode.vhd:265:17 */ + always @* + case (n4123_o) + 59'b10000000000000000000000000000000000000000000000000000000000: n4340_o = 1'b0; + 59'b01000000000000000000000000000000000000000000000000000000000: n4340_o = 1'b0; + 59'b00100000000000000000000000000000000000000000000000000000000: n4340_o = 1'b0; + 59'b00010000000000000000000000000000000000000000000000000000000: n4340_o = 1'b0; + 59'b00001000000000000000000000000000000000000000000000000000000: n4340_o = 1'b0; + 59'b00000100000000000000000000000000000000000000000000000000000: n4340_o = 1'b0; + 59'b00000010000000000000000000000000000000000000000000000000000: n4340_o = 1'b0; + 59'b00000001000000000000000000000000000000000000000000000000000: n4340_o = 1'b0; + 59'b00000000100000000000000000000000000000000000000000000000000: n4340_o = 1'b0; + 59'b00000000010000000000000000000000000000000000000000000000000: n4340_o = 1'b0; + 59'b00000000001000000000000000000000000000000000000000000000000: n4340_o = 1'b0; + 59'b00000000000100000000000000000000000000000000000000000000000: n4340_o = 1'b0; + 59'b00000000000010000000000000000000000000000000000000000000000: n4340_o = 1'b0; + 59'b00000000000001000000000000000000000000000000000000000000000: n4340_o = 1'b0; + 59'b00000000000000100000000000000000000000000000000000000000000: n4340_o = 1'b0; + 59'b00000000000000010000000000000000000000000000000000000000000: n4340_o = 1'b0; + 59'b00000000000000001000000000000000000000000000000000000000000: n4340_o = 1'b0; + 59'b00000000000000000100000000000000000000000000000000000000000: n4340_o = 1'b0; + 59'b00000000000000000010000000000000000000000000000000000000000: n4340_o = 1'b0; + 59'b00000000000000000001000000000000000000000000000000000000000: n4340_o = 1'b0; + 59'b00000000000000000000100000000000000000000000000000000000000: n4340_o = 1'b0; + 59'b00000000000000000000010000000000000000000000000000000000000: n4340_o = 1'b0; + 59'b00000000000000000000001000000000000000000000000000000000000: n4340_o = 1'b0; + 59'b00000000000000000000000100000000000000000000000000000000000: n4340_o = 1'b0; + 59'b00000000000000000000000010000000000000000000000000000000000: n4340_o = 1'b0; + 59'b00000000000000000000000001000000000000000000000000000000000: n4340_o = 1'b0; + 59'b00000000000000000000000000100000000000000000000000000000000: n4340_o = 1'b0; + 59'b00000000000000000000000000010000000000000000000000000000000: n4340_o = 1'b0; + 59'b00000000000000000000000000001000000000000000000000000000000: n4340_o = 1'b0; + 59'b00000000000000000000000000000100000000000000000000000000000: n4340_o = 1'b0; + 59'b00000000000000000000000000000010000000000000000000000000000: n4340_o = 1'b0; + 59'b00000000000000000000000000000001000000000000000000000000000: n4340_o = 1'b0; + 59'b00000000000000000000000000000000100000000000000000000000000: n4340_o = 1'b0; + 59'b00000000000000000000000000000000010000000000000000000000000: n4340_o = 1'b0; + 59'b00000000000000000000000000000000001000000000000000000000000: n4340_o = 1'b0; + 59'b00000000000000000000000000000000000100000000000000000000000: n4340_o = 1'b0; + 59'b00000000000000000000000000000000000010000000000000000000000: n4340_o = 1'b0; + 59'b00000000000000000000000000000000000001000000000000000000000: n4340_o = 1'b0; + 59'b00000000000000000000000000000000000000100000000000000000000: n4340_o = 1'b0; + 59'b00000000000000000000000000000000000000010000000000000000000: n4340_o = 1'b0; + 59'b00000000000000000000000000000000000000001000000000000000000: n4340_o = 1'b0; + 59'b00000000000000000000000000000000000000000100000000000000000: n4340_o = 1'b0; + 59'b00000000000000000000000000000000000000000010000000000000000: n4340_o = 1'b0; + 59'b00000000000000000000000000000000000000000001000000000000000: n4340_o = 1'b0; + 59'b00000000000000000000000000000000000000000000100000000000000: n4340_o = 1'b1; + 59'b00000000000000000000000000000000000000000000010000000000000: n4340_o = 1'b0; + 59'b00000000000000000000000000000000000000000000001000000000000: n4340_o = 1'b0; + 59'b00000000000000000000000000000000000000000000000100000000000: n4340_o = 1'b0; + 59'b00000000000000000000000000000000000000000000000010000000000: n4340_o = 1'b0; + 59'b00000000000000000000000000000000000000000000000001000000000: n4340_o = 1'b0; + 59'b00000000000000000000000000000000000000000000000000100000000: n4340_o = 1'b0; + 59'b00000000000000000000000000000000000000000000000000010000000: n4340_o = 1'b0; + 59'b00000000000000000000000000000000000000000000000000001000000: n4340_o = 1'b0; + 59'b00000000000000000000000000000000000000000000000000000100000: n4340_o = 1'b0; + 59'b00000000000000000000000000000000000000000000000000000010000: n4340_o = 1'b0; + 59'b00000000000000000000000000000000000000000000000000000001000: n4340_o = 1'b0; + 59'b00000000000000000000000000000000000000000000000000000000100: n4340_o = 1'b0; + 59'b00000000000000000000000000000000000000000000000000000000010: n4340_o = 1'b0; + 59'b00000000000000000000000000000000000000000000000000000000001: n4340_o = 1'b0; + default: n4340_o = 1'bX; + endcase + /* T80_MCode.vhd:265:17 */ + always @* + case (n4123_o) + 59'b10000000000000000000000000000000000000000000000000000000000: n4344_o = 1'b0; + 59'b01000000000000000000000000000000000000000000000000000000000: n4344_o = 1'b0; + 59'b00100000000000000000000000000000000000000000000000000000000: n4344_o = 1'b0; + 59'b00010000000000000000000000000000000000000000000000000000000: n4344_o = 1'b0; + 59'b00001000000000000000000000000000000000000000000000000000000: n4344_o = 1'b0; + 59'b00000100000000000000000000000000000000000000000000000000000: n4344_o = 1'b0; + 59'b00000010000000000000000000000000000000000000000000000000000: n4344_o = 1'b0; + 59'b00000001000000000000000000000000000000000000000000000000000: n4344_o = 1'b0; + 59'b00000000100000000000000000000000000000000000000000000000000: n4344_o = 1'b0; + 59'b00000000010000000000000000000000000000000000000000000000000: n4344_o = 1'b0; + 59'b00000000001000000000000000000000000000000000000000000000000: n4344_o = 1'b0; + 59'b00000000000100000000000000000000000000000000000000000000000: n4344_o = 1'b0; + 59'b00000000000010000000000000000000000000000000000000000000000: n4344_o = 1'b0; + 59'b00000000000001000000000000000000000000000000000000000000000: n4344_o = 1'b0; + 59'b00000000000000100000000000000000000000000000000000000000000: n4344_o = 1'b0; + 59'b00000000000000010000000000000000000000000000000000000000000: n4344_o = 1'b0; + 59'b00000000000000001000000000000000000000000000000000000000000: n4344_o = 1'b0; + 59'b00000000000000000100000000000000000000000000000000000000000: n4344_o = 1'b0; + 59'b00000000000000000010000000000000000000000000000000000000000: n4344_o = 1'b0; + 59'b00000000000000000001000000000000000000000000000000000000000: n4344_o = 1'b0; + 59'b00000000000000000000100000000000000000000000000000000000000: n4344_o = 1'b0; + 59'b00000000000000000000010000000000000000000000000000000000000: n4344_o = 1'b0; + 59'b00000000000000000000001000000000000000000000000000000000000: n4344_o = 1'b0; + 59'b00000000000000000000000100000000000000000000000000000000000: n4344_o = 1'b0; + 59'b00000000000000000000000010000000000000000000000000000000000: n4344_o = 1'b0; + 59'b00000000000000000000000001000000000000000000000000000000000: n4344_o = 1'b0; + 59'b00000000000000000000000000100000000000000000000000000000000: n4344_o = 1'b0; + 59'b00000000000000000000000000010000000000000000000000000000000: n4344_o = 1'b0; + 59'b00000000000000000000000000001000000000000000000000000000000: n4344_o = 1'b0; + 59'b00000000000000000000000000000100000000000000000000000000000: n4344_o = 1'b0; + 59'b00000000000000000000000000000010000000000000000000000000000: n4344_o = 1'b0; + 59'b00000000000000000000000000000001000000000000000000000000000: n4344_o = 1'b0; + 59'b00000000000000000000000000000000100000000000000000000000000: n4344_o = 1'b0; + 59'b00000000000000000000000000000000010000000000000000000000000: n4344_o = 1'b0; + 59'b00000000000000000000000000000000001000000000000000000000000: n4344_o = 1'b0; + 59'b00000000000000000000000000000000000100000000000000000000000: n4344_o = 1'b0; + 59'b00000000000000000000000000000000000010000000000000000000000: n4344_o = 1'b0; + 59'b00000000000000000000000000000000000001000000000000000000000: n4344_o = 1'b0; + 59'b00000000000000000000000000000000000000100000000000000000000: n4344_o = 1'b0; + 59'b00000000000000000000000000000000000000010000000000000000000: n4344_o = 1'b0; + 59'b00000000000000000000000000000000000000001000000000000000000: n4344_o = 1'b0; + 59'b00000000000000000000000000000000000000000100000000000000000: n4344_o = 1'b1; + 59'b00000000000000000000000000000000000000000010000000000000000: n4344_o = 1'b0; + 59'b00000000000000000000000000000000000000000001000000000000000: n4344_o = 1'b0; + 59'b00000000000000000000000000000000000000000000100000000000000: n4344_o = 1'b0; + 59'b00000000000000000000000000000000000000000000010000000000000: n4344_o = 1'b0; + 59'b00000000000000000000000000000000000000000000001000000000000: n4344_o = 1'b0; + 59'b00000000000000000000000000000000000000000000000100000000000: n4344_o = 1'b0; + 59'b00000000000000000000000000000000000000000000000010000000000: n4344_o = 1'b0; + 59'b00000000000000000000000000000000000000000000000001000000000: n4344_o = 1'b0; + 59'b00000000000000000000000000000000000000000000000000100000000: n4344_o = 1'b0; + 59'b00000000000000000000000000000000000000000000000000010000000: n4344_o = 1'b0; + 59'b00000000000000000000000000000000000000000000000000001000000: n4344_o = 1'b0; + 59'b00000000000000000000000000000000000000000000000000000100000: n4344_o = 1'b0; + 59'b00000000000000000000000000000000000000000000000000000010000: n4344_o = 1'b0; + 59'b00000000000000000000000000000000000000000000000000000001000: n4344_o = 1'b0; + 59'b00000000000000000000000000000000000000000000000000000000100: n4344_o = 1'b0; + 59'b00000000000000000000000000000000000000000000000000000000010: n4344_o = 1'b0; + 59'b00000000000000000000000000000000000000000000000000000000001: n4344_o = 1'b0; + default: n4344_o = 1'bX; + endcase + /* T80_MCode.vhd:265:17 */ + always @* + case (n4123_o) + 59'b10000000000000000000000000000000000000000000000000000000000: n4348_o = 1'b0; + 59'b01000000000000000000000000000000000000000000000000000000000: n4348_o = 1'b0; + 59'b00100000000000000000000000000000000000000000000000000000000: n4348_o = 1'b0; + 59'b00010000000000000000000000000000000000000000000000000000000: n4348_o = 1'b0; + 59'b00001000000000000000000000000000000000000000000000000000000: n4348_o = 1'b0; + 59'b00000100000000000000000000000000000000000000000000000000000: n4348_o = 1'b0; + 59'b00000010000000000000000000000000000000000000000000000000000: n4348_o = 1'b0; + 59'b00000001000000000000000000000000000000000000000000000000000: n4348_o = 1'b0; + 59'b00000000100000000000000000000000000000000000000000000000000: n4348_o = 1'b0; + 59'b00000000010000000000000000000000000000000000000000000000000: n4348_o = 1'b0; + 59'b00000000001000000000000000000000000000000000000000000000000: n4348_o = 1'b0; + 59'b00000000000100000000000000000000000000000000000000000000000: n4348_o = 1'b0; + 59'b00000000000010000000000000000000000000000000000000000000000: n4348_o = 1'b0; + 59'b00000000000001000000000000000000000000000000000000000000000: n4348_o = 1'b0; + 59'b00000000000000100000000000000000000000000000000000000000000: n4348_o = 1'b0; + 59'b00000000000000010000000000000000000000000000000000000000000: n4348_o = 1'b0; + 59'b00000000000000001000000000000000000000000000000000000000000: n4348_o = 1'b0; + 59'b00000000000000000100000000000000000000000000000000000000000: n4348_o = 1'b0; + 59'b00000000000000000010000000000000000000000000000000000000000: n4348_o = 1'b0; + 59'b00000000000000000001000000000000000000000000000000000000000: n4348_o = 1'b0; + 59'b00000000000000000000100000000000000000000000000000000000000: n4348_o = 1'b0; + 59'b00000000000000000000010000000000000000000000000000000000000: n4348_o = 1'b0; + 59'b00000000000000000000001000000000000000000000000000000000000: n4348_o = 1'b0; + 59'b00000000000000000000000100000000000000000000000000000000000: n4348_o = 1'b0; + 59'b00000000000000000000000010000000000000000000000000000000000: n4348_o = 1'b0; + 59'b00000000000000000000000001000000000000000000000000000000000: n4348_o = 1'b0; + 59'b00000000000000000000000000100000000000000000000000000000000: n4348_o = 1'b0; + 59'b00000000000000000000000000010000000000000000000000000000000: n4348_o = 1'b0; + 59'b00000000000000000000000000001000000000000000000000000000000: n4348_o = 1'b0; + 59'b00000000000000000000000000000100000000000000000000000000000: n4348_o = 1'b0; + 59'b00000000000000000000000000000010000000000000000000000000000: n4348_o = 1'b0; + 59'b00000000000000000000000000000001000000000000000000000000000: n4348_o = 1'b0; + 59'b00000000000000000000000000000000100000000000000000000000000: n4348_o = 1'b0; + 59'b00000000000000000000000000000000010000000000000000000000000: n4348_o = 1'b0; + 59'b00000000000000000000000000000000001000000000000000000000000: n4348_o = 1'b0; + 59'b00000000000000000000000000000000000100000000000000000000000: n4348_o = 1'b0; + 59'b00000000000000000000000000000000000010000000000000000000000: n4348_o = 1'b0; + 59'b00000000000000000000000000000000000001000000000000000000000: n4348_o = 1'b0; + 59'b00000000000000000000000000000000000000100000000000000000000: n4348_o = 1'b0; + 59'b00000000000000000000000000000000000000010000000000000000000: n4348_o = 1'b0; + 59'b00000000000000000000000000000000000000001000000000000000000: n4348_o = 1'b0; + 59'b00000000000000000000000000000000000000000100000000000000000: n4348_o = 1'b0; + 59'b00000000000000000000000000000000000000000010000000000000000: n4348_o = 1'b0; + 59'b00000000000000000000000000000000000000000001000000000000000: n4348_o = 1'b0; + 59'b00000000000000000000000000000000000000000000100000000000000: n4348_o = 1'b0; + 59'b00000000000000000000000000000000000000000000010000000000000: n4348_o = 1'b0; + 59'b00000000000000000000000000000000000000000000001000000000000: n4348_o = 1'b0; + 59'b00000000000000000000000000000000000000000000000100000000000: n4348_o = 1'b0; + 59'b00000000000000000000000000000000000000000000000010000000000: n4348_o = 1'b0; + 59'b00000000000000000000000000000000000000000000000001000000000: n4348_o = 1'b0; + 59'b00000000000000000000000000000000000000000000000000100000000: n4348_o = 1'b0; + 59'b00000000000000000000000000000000000000000000000000010000000: n4348_o = 1'b0; + 59'b00000000000000000000000000000000000000000000000000001000000: n4348_o = 1'b0; + 59'b00000000000000000000000000000000000000000000000000000100000: n4348_o = 1'b0; + 59'b00000000000000000000000000000000000000000000000000000010000: n4348_o = 1'b0; + 59'b00000000000000000000000000000000000000000000000000000001000: n4348_o = 1'b0; + 59'b00000000000000000000000000000000000000000000000000000000100: n4348_o = 1'b0; + 59'b00000000000000000000000000000000000000000000000000000000010: n4348_o = 1'b0; + 59'b00000000000000000000000000000000000000000000000000000000001: n4348_o = 1'b1; + default: n4348_o = 1'bX; + endcase + /* T80_MCode.vhd:265:17 */ + always @* + case (n4123_o) + 59'b10000000000000000000000000000000000000000000000000000000000: n4352_o = 1'b0; + 59'b01000000000000000000000000000000000000000000000000000000000: n4352_o = 1'b0; + 59'b00100000000000000000000000000000000000000000000000000000000: n4352_o = 1'b0; + 59'b00010000000000000000000000000000000000000000000000000000000: n4352_o = 1'b0; + 59'b00001000000000000000000000000000000000000000000000000000000: n4352_o = 1'b0; + 59'b00000100000000000000000000000000000000000000000000000000000: n4352_o = 1'b0; + 59'b00000010000000000000000000000000000000000000000000000000000: n4352_o = 1'b0; + 59'b00000001000000000000000000000000000000000000000000000000000: n4352_o = 1'b0; + 59'b00000000100000000000000000000000000000000000000000000000000: n4352_o = 1'b0; + 59'b00000000010000000000000000000000000000000000000000000000000: n4352_o = 1'b0; + 59'b00000000001000000000000000000000000000000000000000000000000: n4352_o = 1'b0; + 59'b00000000000100000000000000000000000000000000000000000000000: n4352_o = 1'b0; + 59'b00000000000010000000000000000000000000000000000000000000000: n4352_o = 1'b0; + 59'b00000000000001000000000000000000000000000000000000000000000: n4352_o = 1'b0; + 59'b00000000000000100000000000000000000000000000000000000000000: n4352_o = 1'b0; + 59'b00000000000000010000000000000000000000000000000000000000000: n4352_o = 1'b0; + 59'b00000000000000001000000000000000000000000000000000000000000: n4352_o = 1'b0; + 59'b00000000000000000100000000000000000000000000000000000000000: n4352_o = 1'b0; + 59'b00000000000000000010000000000000000000000000000000000000000: n4352_o = 1'b0; + 59'b00000000000000000001000000000000000000000000000000000000000: n4352_o = 1'b0; + 59'b00000000000000000000100000000000000000000000000000000000000: n4352_o = 1'b0; + 59'b00000000000000000000010000000000000000000000000000000000000: n4352_o = 1'b0; + 59'b00000000000000000000001000000000000000000000000000000000000: n4352_o = 1'b0; + 59'b00000000000000000000000100000000000000000000000000000000000: n4352_o = 1'b0; + 59'b00000000000000000000000010000000000000000000000000000000000: n4352_o = 1'b0; + 59'b00000000000000000000000001000000000000000000000000000000000: n4352_o = 1'b0; + 59'b00000000000000000000000000100000000000000000000000000000000: n4352_o = 1'b0; + 59'b00000000000000000000000000010000000000000000000000000000000: n4352_o = 1'b0; + 59'b00000000000000000000000000001000000000000000000000000000000: n4352_o = 1'b0; + 59'b00000000000000000000000000000100000000000000000000000000000: n4352_o = 1'b0; + 59'b00000000000000000000000000000010000000000000000000000000000: n4352_o = 1'b0; + 59'b00000000000000000000000000000001000000000000000000000000000: n4352_o = 1'b0; + 59'b00000000000000000000000000000000100000000000000000000000000: n4352_o = 1'b0; + 59'b00000000000000000000000000000000010000000000000000000000000: n4352_o = 1'b0; + 59'b00000000000000000000000000000000001000000000000000000000000: n4352_o = 1'b0; + 59'b00000000000000000000000000000000000100000000000000000000000: n4352_o = 1'b0; + 59'b00000000000000000000000000000000000010000000000000000000000: n4352_o = 1'b0; + 59'b00000000000000000000000000000000000001000000000000000000000: n4352_o = 1'b0; + 59'b00000000000000000000000000000000000000100000000000000000000: n4352_o = 1'b0; + 59'b00000000000000000000000000000000000000010000000000000000000: n4352_o = 1'b0; + 59'b00000000000000000000000000000000000000001000000000000000000: n4352_o = 1'b1; + 59'b00000000000000000000000000000000000000000100000000000000000: n4352_o = 1'b0; + 59'b00000000000000000000000000000000000000000010000000000000000: n4352_o = 1'b0; + 59'b00000000000000000000000000000000000000000001000000000000000: n4352_o = 1'b0; + 59'b00000000000000000000000000000000000000000000100000000000000: n4352_o = 1'b0; + 59'b00000000000000000000000000000000000000000000010000000000000: n4352_o = 1'b0; + 59'b00000000000000000000000000000000000000000000001000000000000: n4352_o = 1'b0; + 59'b00000000000000000000000000000000000000000000000100000000000: n4352_o = 1'b0; + 59'b00000000000000000000000000000000000000000000000010000000000: n4352_o = 1'b0; + 59'b00000000000000000000000000000000000000000000000001000000000: n4352_o = 1'b0; + 59'b00000000000000000000000000000000000000000000000000100000000: n4352_o = 1'b0; + 59'b00000000000000000000000000000000000000000000000000010000000: n4352_o = 1'b0; + 59'b00000000000000000000000000000000000000000000000000001000000: n4352_o = 1'b0; + 59'b00000000000000000000000000000000000000000000000000000100000: n4352_o = 1'b0; + 59'b00000000000000000000000000000000000000000000000000000010000: n4352_o = 1'b0; + 59'b00000000000000000000000000000000000000000000000000000001000: n4352_o = 1'b0; + 59'b00000000000000000000000000000000000000000000000000000000100: n4352_o = 1'b0; + 59'b00000000000000000000000000000000000000000000000000000000010: n4352_o = 1'b0; + 59'b00000000000000000000000000000000000000000000000000000000001: n4352_o = 1'b0; + default: n4352_o = 1'bX; + endcase + /* T80_MCode.vhd:265:17 */ + always @* + case (n4123_o) + 59'b10000000000000000000000000000000000000000000000000000000000: n4356_o = 1'b0; + 59'b01000000000000000000000000000000000000000000000000000000000: n4356_o = 1'b0; + 59'b00100000000000000000000000000000000000000000000000000000000: n4356_o = 1'b0; + 59'b00010000000000000000000000000000000000000000000000000000000: n4356_o = 1'b0; + 59'b00001000000000000000000000000000000000000000000000000000000: n4356_o = 1'b0; + 59'b00000100000000000000000000000000000000000000000000000000000: n4356_o = 1'b0; + 59'b00000010000000000000000000000000000000000000000000000000000: n4356_o = 1'b0; + 59'b00000001000000000000000000000000000000000000000000000000000: n4356_o = 1'b0; + 59'b00000000100000000000000000000000000000000000000000000000000: n4356_o = 1'b0; + 59'b00000000010000000000000000000000000000000000000000000000000: n4356_o = 1'b0; + 59'b00000000001000000000000000000000000000000000000000000000000: n4356_o = 1'b0; + 59'b00000000000100000000000000000000000000000000000000000000000: n4356_o = 1'b0; + 59'b00000000000010000000000000000000000000000000000000000000000: n4356_o = 1'b0; + 59'b00000000000001000000000000000000000000000000000000000000000: n4356_o = 1'b0; + 59'b00000000000000100000000000000000000000000000000000000000000: n4356_o = 1'b0; + 59'b00000000000000010000000000000000000000000000000000000000000: n4356_o = 1'b0; + 59'b00000000000000001000000000000000000000000000000000000000000: n4356_o = 1'b0; + 59'b00000000000000000100000000000000000000000000000000000000000: n4356_o = 1'b0; + 59'b00000000000000000010000000000000000000000000000000000000000: n4356_o = 1'b0; + 59'b00000000000000000001000000000000000000000000000000000000000: n4356_o = 1'b0; + 59'b00000000000000000000100000000000000000000000000000000000000: n4356_o = 1'b0; + 59'b00000000000000000000010000000000000000000000000000000000000: n4356_o = 1'b0; + 59'b00000000000000000000001000000000000000000000000000000000000: n4356_o = 1'b0; + 59'b00000000000000000000000100000000000000000000000000000000000: n4356_o = 1'b0; + 59'b00000000000000000000000010000000000000000000000000000000000: n4356_o = 1'b0; + 59'b00000000000000000000000001000000000000000000000000000000000: n4356_o = 1'b0; + 59'b00000000000000000000000000100000000000000000000000000000000: n4356_o = 1'b0; + 59'b00000000000000000000000000010000000000000000000000000000000: n4356_o = 1'b0; + 59'b00000000000000000000000000001000000000000000000000000000000: n4356_o = 1'b0; + 59'b00000000000000000000000000000100000000000000000000000000000: n4356_o = 1'b0; + 59'b00000000000000000000000000000010000000000000000000000000000: n4356_o = 1'b0; + 59'b00000000000000000000000000000001000000000000000000000000000: n4356_o = 1'b0; + 59'b00000000000000000000000000000000100000000000000000000000000: n4356_o = 1'b0; + 59'b00000000000000000000000000000000010000000000000000000000000: n4356_o = 1'b0; + 59'b00000000000000000000000000000000001000000000000000000000000: n4356_o = 1'b0; + 59'b00000000000000000000000000000000000100000000000000000000000: n4356_o = 1'b0; + 59'b00000000000000000000000000000000000010000000000000000000000: n4356_o = 1'b0; + 59'b00000000000000000000000000000000000001000000000000000000000: n4356_o = 1'b0; + 59'b00000000000000000000000000000000000000100000000000000000000: n4356_o = 1'b0; + 59'b00000000000000000000000000000000000000010000000000000000000: n4356_o = 1'b1; + 59'b00000000000000000000000000000000000000001000000000000000000: n4356_o = 1'b0; + 59'b00000000000000000000000000000000000000000100000000000000000: n4356_o = 1'b0; + 59'b00000000000000000000000000000000000000000010000000000000000: n4356_o = 1'b0; + 59'b00000000000000000000000000000000000000000001000000000000000: n4356_o = 1'b0; + 59'b00000000000000000000000000000000000000000000100000000000000: n4356_o = 1'b0; + 59'b00000000000000000000000000000000000000000000010000000000000: n4356_o = 1'b0; + 59'b00000000000000000000000000000000000000000000001000000000000: n4356_o = 1'b0; + 59'b00000000000000000000000000000000000000000000000100000000000: n4356_o = 1'b0; + 59'b00000000000000000000000000000000000000000000000010000000000: n4356_o = 1'b0; + 59'b00000000000000000000000000000000000000000000000001000000000: n4356_o = 1'b0; + 59'b00000000000000000000000000000000000000000000000000100000000: n4356_o = 1'b0; + 59'b00000000000000000000000000000000000000000000000000010000000: n4356_o = 1'b0; + 59'b00000000000000000000000000000000000000000000000000001000000: n4356_o = 1'b0; + 59'b00000000000000000000000000000000000000000000000000000100000: n4356_o = 1'b0; + 59'b00000000000000000000000000000000000000000000000000000010000: n4356_o = 1'b0; + 59'b00000000000000000000000000000000000000000000000000000001000: n4356_o = 1'b0; + 59'b00000000000000000000000000000000000000000000000000000000100: n4356_o = 1'b0; + 59'b00000000000000000000000000000000000000000000000000000000010: n4356_o = 1'b0; + 59'b00000000000000000000000000000000000000000000000000000000001: n4356_o = 1'b0; + default: n4356_o = 1'bX; + endcase + /* T80_MCode.vhd:265:17 */ + always @* + case (n4123_o) + 59'b10000000000000000000000000000000000000000000000000000000000: n4359_o = 1'b0; + 59'b01000000000000000000000000000000000000000000000000000000000: n4359_o = 1'b0; + 59'b00100000000000000000000000000000000000000000000000000000000: n4359_o = 1'b0; + 59'b00010000000000000000000000000000000000000000000000000000000: n4359_o = 1'b0; + 59'b00001000000000000000000000000000000000000000000000000000000: n4359_o = 1'b0; + 59'b00000100000000000000000000000000000000000000000000000000000: n4359_o = 1'b0; + 59'b00000010000000000000000000000000000000000000000000000000000: n4359_o = 1'b0; + 59'b00000001000000000000000000000000000000000000000000000000000: n4359_o = 1'b0; + 59'b00000000100000000000000000000000000000000000000000000000000: n4359_o = 1'b0; + 59'b00000000010000000000000000000000000000000000000000000000000: n4359_o = 1'b0; + 59'b00000000001000000000000000000000000000000000000000000000000: n4359_o = n3737_o; + 59'b00000000000100000000000000000000000000000000000000000000000: n4359_o = 1'b0; + 59'b00000000000010000000000000000000000000000000000000000000000: n4359_o = 1'b0; + 59'b00000000000001000000000000000000000000000000000000000000000: n4359_o = 1'b0; + 59'b00000000000000100000000000000000000000000000000000000000000: n4359_o = 1'b0; + 59'b00000000000000010000000000000000000000000000000000000000000: n4359_o = 1'b0; + 59'b00000000000000001000000000000000000000000000000000000000000: n4359_o = 1'b0; + 59'b00000000000000000100000000000000000000000000000000000000000: n4359_o = 1'b0; + 59'b00000000000000000010000000000000000000000000000000000000000: n4359_o = 1'b0; + 59'b00000000000000000001000000000000000000000000000000000000000: n4359_o = 1'b0; + 59'b00000000000000000000100000000000000000000000000000000000000: n4359_o = 1'b0; + 59'b00000000000000000000010000000000000000000000000000000000000: n4359_o = 1'b0; + 59'b00000000000000000000001000000000000000000000000000000000000: n4359_o = 1'b0; + 59'b00000000000000000000000100000000000000000000000000000000000: n4359_o = 1'b0; + 59'b00000000000000000000000010000000000000000000000000000000000: n4359_o = 1'b0; + 59'b00000000000000000000000001000000000000000000000000000000000: n4359_o = 1'b0; + 59'b00000000000000000000000000100000000000000000000000000000000: n4359_o = 1'b0; + 59'b00000000000000000000000000010000000000000000000000000000000: n4359_o = 1'b0; + 59'b00000000000000000000000000001000000000000000000000000000000: n4359_o = 1'b0; + 59'b00000000000000000000000000000100000000000000000000000000000: n4359_o = 1'b0; + 59'b00000000000000000000000000000010000000000000000000000000000: n4359_o = 1'b0; + 59'b00000000000000000000000000000001000000000000000000000000000: n4359_o = 1'b0; + 59'b00000000000000000000000000000000100000000000000000000000000: n4359_o = 1'b0; + 59'b00000000000000000000000000000000010000000000000000000000000: n4359_o = 1'b0; + 59'b00000000000000000000000000000000001000000000000000000000000: n4359_o = 1'b0; + 59'b00000000000000000000000000000000000100000000000000000000000: n4359_o = 1'b0; + 59'b00000000000000000000000000000000000010000000000000000000000: n4359_o = 1'b0; + 59'b00000000000000000000000000000000000001000000000000000000000: n4359_o = 1'b0; + 59'b00000000000000000000000000000000000000100000000000000000000: n4359_o = 1'b0; + 59'b00000000000000000000000000000000000000010000000000000000000: n4359_o = 1'b0; + 59'b00000000000000000000000000000000000000001000000000000000000: n4359_o = 1'b0; + 59'b00000000000000000000000000000000000000000100000000000000000: n4359_o = 1'b0; + 59'b00000000000000000000000000000000000000000010000000000000000: n4359_o = 1'b0; + 59'b00000000000000000000000000000000000000000001000000000000000: n4359_o = 1'b0; + 59'b00000000000000000000000000000000000000000000100000000000000: n4359_o = 1'b0; + 59'b00000000000000000000000000000000000000000000010000000000000: n4359_o = 1'b0; + 59'b00000000000000000000000000000000000000000000001000000000000: n4359_o = 1'b0; + 59'b00000000000000000000000000000000000000000000000100000000000: n4359_o = 1'b0; + 59'b00000000000000000000000000000000000000000000000010000000000: n4359_o = 1'b0; + 59'b00000000000000000000000000000000000000000000000001000000000: n4359_o = 1'b0; + 59'b00000000000000000000000000000000000000000000000000100000000: n4359_o = 1'b0; + 59'b00000000000000000000000000000000000000000000000000010000000: n4359_o = 1'b0; + 59'b00000000000000000000000000000000000000000000000000001000000: n4359_o = 1'b0; + 59'b00000000000000000000000000000000000000000000000000000100000: n4359_o = 1'b0; + 59'b00000000000000000000000000000000000000000000000000000010000: n4359_o = 1'b0; + 59'b00000000000000000000000000000000000000000000000000000001000: n4359_o = 1'b0; + 59'b00000000000000000000000000000000000000000000000000000000100: n4359_o = 1'b0; + 59'b00000000000000000000000000000000000000000000000000000000010: n4359_o = 1'b0; + 59'b00000000000000000000000000000000000000000000000000000000001: n4359_o = 1'b0; + default: n4359_o = 1'bX; + endcase + /* T80_MCode.vhd:265:17 */ + always @* + case (n4123_o) + 59'b10000000000000000000000000000000000000000000000000000000000: n4363_o = 1'b0; + 59'b01000000000000000000000000000000000000000000000000000000000: n4363_o = 1'b0; + 59'b00100000000000000000000000000000000000000000000000000000000: n4363_o = 1'b0; + 59'b00010000000000000000000000000000000000000000000000000000000: n4363_o = 1'b0; + 59'b00001000000000000000000000000000000000000000000000000000000: n4363_o = 1'b0; + 59'b00000100000000000000000000000000000000000000000000000000000: n4363_o = 1'b0; + 59'b00000010000000000000000000000000000000000000000000000000000: n4363_o = 1'b0; + 59'b00000001000000000000000000000000000000000000000000000000000: n4363_o = 1'b0; + 59'b00000000100000000000000000000000000000000000000000000000000: n4363_o = 1'b0; + 59'b00000000010000000000000000000000000000000000000000000000000: n4363_o = 1'b0; + 59'b00000000001000000000000000000000000000000000000000000000000: n4363_o = 1'b0; + 59'b00000000000100000000000000000000000000000000000000000000000: n4363_o = 1'b0; + 59'b00000000000010000000000000000000000000000000000000000000000: n4363_o = 1'b0; + 59'b00000000000001000000000000000000000000000000000000000000000: n4363_o = 1'b0; + 59'b00000000000000100000000000000000000000000000000000000000000: n4363_o = 1'b0; + 59'b00000000000000010000000000000000000000000000000000000000000: n4363_o = 1'b0; + 59'b00000000000000001000000000000000000000000000000000000000000: n4363_o = 1'b0; + 59'b00000000000000000100000000000000000000000000000000000000000: n4363_o = 1'b0; + 59'b00000000000000000010000000000000000000000000000000000000000: n4363_o = 1'b0; + 59'b00000000000000000001000000000000000000000000000000000000000: n4363_o = 1'b0; + 59'b00000000000000000000100000000000000000000000000000000000000: n4363_o = 1'b0; + 59'b00000000000000000000010000000000000000000000000000000000000: n4363_o = 1'b0; + 59'b00000000000000000000001000000000000000000000000000000000000: n4363_o = 1'b0; + 59'b00000000000000000000000100000000000000000000000000000000000: n4363_o = 1'b0; + 59'b00000000000000000000000010000000000000000000000000000000000: n4363_o = 1'b0; + 59'b00000000000000000000000001000000000000000000000000000000000: n4363_o = 1'b0; + 59'b00000000000000000000000000100000000000000000000000000000000: n4363_o = 1'b0; + 59'b00000000000000000000000000010000000000000000000000000000000: n4363_o = 1'b0; + 59'b00000000000000000000000000001000000000000000000000000000000: n4363_o = 1'b0; + 59'b00000000000000000000000000000100000000000000000000000000000: n4363_o = 1'b1; + 59'b00000000000000000000000000000010000000000000000000000000000: n4363_o = 1'b0; + 59'b00000000000000000000000000000001000000000000000000000000000: n4363_o = 1'b0; + 59'b00000000000000000000000000000000100000000000000000000000000: n4363_o = 1'b0; + 59'b00000000000000000000000000000000010000000000000000000000000: n4363_o = 1'b0; + 59'b00000000000000000000000000000000001000000000000000000000000: n4363_o = 1'b0; + 59'b00000000000000000000000000000000000100000000000000000000000: n4363_o = 1'b0; + 59'b00000000000000000000000000000000000010000000000000000000000: n4363_o = 1'b0; + 59'b00000000000000000000000000000000000001000000000000000000000: n4363_o = 1'b0; + 59'b00000000000000000000000000000000000000100000000000000000000: n4363_o = 1'b0; + 59'b00000000000000000000000000000000000000010000000000000000000: n4363_o = 1'b0; + 59'b00000000000000000000000000000000000000001000000000000000000: n4363_o = 1'b0; + 59'b00000000000000000000000000000000000000000100000000000000000: n4363_o = 1'b0; + 59'b00000000000000000000000000000000000000000010000000000000000: n4363_o = 1'b0; + 59'b00000000000000000000000000000000000000000001000000000000000: n4363_o = 1'b0; + 59'b00000000000000000000000000000000000000000000100000000000000: n4363_o = 1'b0; + 59'b00000000000000000000000000000000000000000000010000000000000: n4363_o = 1'b0; + 59'b00000000000000000000000000000000000000000000001000000000000: n4363_o = 1'b0; + 59'b00000000000000000000000000000000000000000000000100000000000: n4363_o = 1'b0; + 59'b00000000000000000000000000000000000000000000000010000000000: n4363_o = 1'b0; + 59'b00000000000000000000000000000000000000000000000001000000000: n4363_o = 1'b0; + 59'b00000000000000000000000000000000000000000000000000100000000: n4363_o = 1'b0; + 59'b00000000000000000000000000000000000000000000000000010000000: n4363_o = 1'b0; + 59'b00000000000000000000000000000000000000000000000000001000000: n4363_o = 1'b0; + 59'b00000000000000000000000000000000000000000000000000000100000: n4363_o = 1'b0; + 59'b00000000000000000000000000000000000000000000000000000010000: n4363_o = 1'b0; + 59'b00000000000000000000000000000000000000000000000000000001000: n4363_o = 1'b0; + 59'b00000000000000000000000000000000000000000000000000000000100: n4363_o = 1'b0; + 59'b00000000000000000000000000000000000000000000000000000000010: n4363_o = 1'b0; + 59'b00000000000000000000000000000000000000000000000000000000001: n4363_o = 1'b0; + default: n4363_o = 1'bX; + endcase + /* T80_MCode.vhd:265:17 */ + always @* + case (n4123_o) + 59'b10000000000000000000000000000000000000000000000000000000000: n4367_o = 1'b0; + 59'b01000000000000000000000000000000000000000000000000000000000: n4367_o = 1'b0; + 59'b00100000000000000000000000000000000000000000000000000000000: n4367_o = 1'b0; + 59'b00010000000000000000000000000000000000000000000000000000000: n4367_o = 1'b0; + 59'b00001000000000000000000000000000000000000000000000000000000: n4367_o = 1'b0; + 59'b00000100000000000000000000000000000000000000000000000000000: n4367_o = 1'b0; + 59'b00000010000000000000000000000000000000000000000000000000000: n4367_o = 1'b0; + 59'b00000001000000000000000000000000000000000000000000000000000: n4367_o = 1'b0; + 59'b00000000100000000000000000000000000000000000000000000000000: n4367_o = 1'b0; + 59'b00000000010000000000000000000000000000000000000000000000000: n4367_o = 1'b0; + 59'b00000000001000000000000000000000000000000000000000000000000: n4367_o = 1'b0; + 59'b00000000000100000000000000000000000000000000000000000000000: n4367_o = 1'b0; + 59'b00000000000010000000000000000000000000000000000000000000000: n4367_o = 1'b0; + 59'b00000000000001000000000000000000000000000000000000000000000: n4367_o = 1'b0; + 59'b00000000000000100000000000000000000000000000000000000000000: n4367_o = 1'b0; + 59'b00000000000000010000000000000000000000000000000000000000000: n4367_o = 1'b0; + 59'b00000000000000001000000000000000000000000000000000000000000: n4367_o = 1'b0; + 59'b00000000000000000100000000000000000000000000000000000000000: n4367_o = 1'b0; + 59'b00000000000000000010000000000000000000000000000000000000000: n4367_o = 1'b0; + 59'b00000000000000000001000000000000000000000000000000000000000: n4367_o = 1'b0; + 59'b00000000000000000000100000000000000000000000000000000000000: n4367_o = 1'b0; + 59'b00000000000000000000010000000000000000000000000000000000000: n4367_o = 1'b0; + 59'b00000000000000000000001000000000000000000000000000000000000: n4367_o = 1'b0; + 59'b00000000000000000000000100000000000000000000000000000000000: n4367_o = 1'b0; + 59'b00000000000000000000000010000000000000000000000000000000000: n4367_o = 1'b0; + 59'b00000000000000000000000001000000000000000000000000000000000: n4367_o = 1'b0; + 59'b00000000000000000000000000100000000000000000000000000000000: n4367_o = 1'b0; + 59'b00000000000000000000000000010000000000000000000000000000000: n4367_o = 1'b0; + 59'b00000000000000000000000000001000000000000000000000000000000: n4367_o = 1'b1; + 59'b00000000000000000000000000000100000000000000000000000000000: n4367_o = 1'b0; + 59'b00000000000000000000000000000010000000000000000000000000000: n4367_o = 1'b0; + 59'b00000000000000000000000000000001000000000000000000000000000: n4367_o = 1'b0; + 59'b00000000000000000000000000000000100000000000000000000000000: n4367_o = 1'b0; + 59'b00000000000000000000000000000000010000000000000000000000000: n4367_o = 1'b0; + 59'b00000000000000000000000000000000001000000000000000000000000: n4367_o = 1'b0; + 59'b00000000000000000000000000000000000100000000000000000000000: n4367_o = 1'b0; + 59'b00000000000000000000000000000000000010000000000000000000000: n4367_o = 1'b0; + 59'b00000000000000000000000000000000000001000000000000000000000: n4367_o = 1'b0; + 59'b00000000000000000000000000000000000000100000000000000000000: n4367_o = 1'b0; + 59'b00000000000000000000000000000000000000010000000000000000000: n4367_o = 1'b0; + 59'b00000000000000000000000000000000000000001000000000000000000: n4367_o = 1'b0; + 59'b00000000000000000000000000000000000000000100000000000000000: n4367_o = 1'b0; + 59'b00000000000000000000000000000000000000000010000000000000000: n4367_o = 1'b0; + 59'b00000000000000000000000000000000000000000001000000000000000: n4367_o = 1'b0; + 59'b00000000000000000000000000000000000000000000100000000000000: n4367_o = 1'b0; + 59'b00000000000000000000000000000000000000000000010000000000000: n4367_o = 1'b0; + 59'b00000000000000000000000000000000000000000000001000000000000: n4367_o = 1'b0; + 59'b00000000000000000000000000000000000000000000000100000000000: n4367_o = 1'b0; + 59'b00000000000000000000000000000000000000000000000010000000000: n4367_o = 1'b0; + 59'b00000000000000000000000000000000000000000000000001000000000: n4367_o = 1'b0; + 59'b00000000000000000000000000000000000000000000000000100000000: n4367_o = 1'b0; + 59'b00000000000000000000000000000000000000000000000000010000000: n4367_o = 1'b0; + 59'b00000000000000000000000000000000000000000000000000001000000: n4367_o = 1'b0; + 59'b00000000000000000000000000000000000000000000000000000100000: n4367_o = 1'b0; + 59'b00000000000000000000000000000000000000000000000000000010000: n4367_o = 1'b0; + 59'b00000000000000000000000000000000000000000000000000000001000: n4367_o = 1'b0; + 59'b00000000000000000000000000000000000000000000000000000000100: n4367_o = 1'b0; + 59'b00000000000000000000000000000000000000000000000000000000010: n4367_o = 1'b0; + 59'b00000000000000000000000000000000000000000000000000000000001: n4367_o = 1'b0; + default: n4367_o = 1'bX; + endcase + /* T80_MCode.vhd:265:17 */ + always @* + case (n4123_o) + 59'b10000000000000000000000000000000000000000000000000000000000: n4371_o = 1'b0; + 59'b01000000000000000000000000000000000000000000000000000000000: n4371_o = 1'b0; + 59'b00100000000000000000000000000000000000000000000000000000000: n4371_o = 1'b0; + 59'b00010000000000000000000000000000000000000000000000000000000: n4371_o = 1'b0; + 59'b00001000000000000000000000000000000000000000000000000000000: n4371_o = 1'b0; + 59'b00000100000000000000000000000000000000000000000000000000000: n4371_o = 1'b0; + 59'b00000010000000000000000000000000000000000000000000000000000: n4371_o = 1'b0; + 59'b00000001000000000000000000000000000000000000000000000000000: n4371_o = 1'b0; + 59'b00000000100000000000000000000000000000000000000000000000000: n4371_o = 1'b0; + 59'b00000000010000000000000000000000000000000000000000000000000: n4371_o = 1'b0; + 59'b00000000001000000000000000000000000000000000000000000000000: n4371_o = 1'b0; + 59'b00000000000100000000000000000000000000000000000000000000000: n4371_o = 1'b0; + 59'b00000000000010000000000000000000000000000000000000000000000: n4371_o = 1'b0; + 59'b00000000000001000000000000000000000000000000000000000000000: n4371_o = 1'b0; + 59'b00000000000000100000000000000000000000000000000000000000000: n4371_o = 1'b0; + 59'b00000000000000010000000000000000000000000000000000000000000: n4371_o = 1'b0; + 59'b00000000000000001000000000000000000000000000000000000000000: n4371_o = 1'b0; + 59'b00000000000000000100000000000000000000000000000000000000000: n4371_o = 1'b0; + 59'b00000000000000000010000000000000000000000000000000000000000: n4371_o = 1'b0; + 59'b00000000000000000001000000000000000000000000000000000000000: n4371_o = 1'b0; + 59'b00000000000000000000100000000000000000000000000000000000000: n4371_o = 1'b0; + 59'b00000000000000000000010000000000000000000000000000000000000: n4371_o = 1'b0; + 59'b00000000000000000000001000000000000000000000000000000000000: n4371_o = 1'b0; + 59'b00000000000000000000000100000000000000000000000000000000000: n4371_o = 1'b0; + 59'b00000000000000000000000010000000000000000000000000000000000: n4371_o = 1'b0; + 59'b00000000000000000000000001000000000000000000000000000000000: n4371_o = 1'b0; + 59'b00000000000000000000000000100000000000000000000000000000000: n4371_o = 1'b0; + 59'b00000000000000000000000000010000000000000000000000000000000: n4371_o = 1'b1; + 59'b00000000000000000000000000001000000000000000000000000000000: n4371_o = 1'b0; + 59'b00000000000000000000000000000100000000000000000000000000000: n4371_o = 1'b0; + 59'b00000000000000000000000000000010000000000000000000000000000: n4371_o = 1'b0; + 59'b00000000000000000000000000000001000000000000000000000000000: n4371_o = 1'b0; + 59'b00000000000000000000000000000000100000000000000000000000000: n4371_o = 1'b0; + 59'b00000000000000000000000000000000010000000000000000000000000: n4371_o = 1'b0; + 59'b00000000000000000000000000000000001000000000000000000000000: n4371_o = 1'b0; + 59'b00000000000000000000000000000000000100000000000000000000000: n4371_o = 1'b0; + 59'b00000000000000000000000000000000000010000000000000000000000: n4371_o = 1'b0; + 59'b00000000000000000000000000000000000001000000000000000000000: n4371_o = 1'b0; + 59'b00000000000000000000000000000000000000100000000000000000000: n4371_o = 1'b0; + 59'b00000000000000000000000000000000000000010000000000000000000: n4371_o = 1'b0; + 59'b00000000000000000000000000000000000000001000000000000000000: n4371_o = 1'b0; + 59'b00000000000000000000000000000000000000000100000000000000000: n4371_o = 1'b0; + 59'b00000000000000000000000000000000000000000010000000000000000: n4371_o = 1'b0; + 59'b00000000000000000000000000000000000000000001000000000000000: n4371_o = 1'b0; + 59'b00000000000000000000000000000000000000000000100000000000000: n4371_o = 1'b0; + 59'b00000000000000000000000000000000000000000000010000000000000: n4371_o = 1'b0; + 59'b00000000000000000000000000000000000000000000001000000000000: n4371_o = 1'b0; + 59'b00000000000000000000000000000000000000000000000100000000000: n4371_o = 1'b0; + 59'b00000000000000000000000000000000000000000000000010000000000: n4371_o = 1'b0; + 59'b00000000000000000000000000000000000000000000000001000000000: n4371_o = 1'b0; + 59'b00000000000000000000000000000000000000000000000000100000000: n4371_o = 1'b0; + 59'b00000000000000000000000000000000000000000000000000010000000: n4371_o = 1'b0; + 59'b00000000000000000000000000000000000000000000000000001000000: n4371_o = 1'b0; + 59'b00000000000000000000000000000000000000000000000000000100000: n4371_o = 1'b0; + 59'b00000000000000000000000000000000000000000000000000000010000: n4371_o = 1'b0; + 59'b00000000000000000000000000000000000000000000000000000001000: n4371_o = 1'b0; + 59'b00000000000000000000000000000000000000000000000000000000100: n4371_o = 1'b0; + 59'b00000000000000000000000000000000000000000000000000000000010: n4371_o = 1'b0; + 59'b00000000000000000000000000000000000000000000000000000000001: n4371_o = 1'b0; + default: n4371_o = 1'bX; + endcase + /* T80_MCode.vhd:265:17 */ + always @* + case (n4123_o) + 59'b10000000000000000000000000000000000000000000000000000000000: n4374_o = 2'b00; + 59'b01000000000000000000000000000000000000000000000000000000000: n4374_o = 2'b00; + 59'b00100000000000000000000000000000000000000000000000000000000: n4374_o = 2'b00; + 59'b00010000000000000000000000000000000000000000000000000000000: n4374_o = 2'b00; + 59'b00001000000000000000000000000000000000000000000000000000000: n4374_o = 2'b00; + 59'b00000100000000000000000000000000000000000000000000000000000: n4374_o = 2'b00; + 59'b00000010000000000000000000000000000000000000000000000000000: n4374_o = 2'b00; + 59'b00000001000000000000000000000000000000000000000000000000000: n4374_o = 2'b00; + 59'b00000000100000000000000000000000000000000000000000000000000: n4374_o = 2'b00; + 59'b00000000010000000000000000000000000000000000000000000000000: n4374_o = 2'b00; + 59'b00000000001000000000000000000000000000000000000000000000000: n4374_o = 2'b00; + 59'b00000000000100000000000000000000000000000000000000000000000: n4374_o = 2'b00; + 59'b00000000000010000000000000000000000000000000000000000000000: n4374_o = 2'b00; + 59'b00000000000001000000000000000000000000000000000000000000000: n4374_o = 2'b00; + 59'b00000000000000100000000000000000000000000000000000000000000: n4374_o = 2'b00; + 59'b00000000000000010000000000000000000000000000000000000000000: n4374_o = 2'b00; + 59'b00000000000000001000000000000000000000000000000000000000000: n4374_o = 2'b00; + 59'b00000000000000000100000000000000000000000000000000000000000: n4374_o = 2'b00; + 59'b00000000000000000010000000000000000000000000000000000000000: n4374_o = 2'b00; + 59'b00000000000000000001000000000000000000000000000000000000000: n4374_o = 2'b00; + 59'b00000000000000000000100000000000000000000000000000000000000: n4374_o = 2'b00; + 59'b00000000000000000000010000000000000000000000000000000000000: n4374_o = 2'b00; + 59'b00000000000000000000001000000000000000000000000000000000000: n4374_o = n3421_o; + 59'b00000000000000000000000100000000000000000000000000000000000: n4374_o = 2'b00; + 59'b00000000000000000000000010000000000000000000000000000000000: n4374_o = 2'b00; + 59'b00000000000000000000000001000000000000000000000000000000000: n4374_o = 2'b00; + 59'b00000000000000000000000000100000000000000000000000000000000: n4374_o = 2'b00; + 59'b00000000000000000000000000010000000000000000000000000000000: n4374_o = 2'b00; + 59'b00000000000000000000000000001000000000000000000000000000000: n4374_o = 2'b00; + 59'b00000000000000000000000000000100000000000000000000000000000: n4374_o = 2'b00; + 59'b00000000000000000000000000000010000000000000000000000000000: n4374_o = 2'b00; + 59'b00000000000000000000000000000001000000000000000000000000000: n4374_o = 2'b00; + 59'b00000000000000000000000000000000100000000000000000000000000: n4374_o = 2'b00; + 59'b00000000000000000000000000000000010000000000000000000000000: n4374_o = 2'b00; + 59'b00000000000000000000000000000000001000000000000000000000000: n4374_o = 2'b00; + 59'b00000000000000000000000000000000000100000000000000000000000: n4374_o = 2'b00; + 59'b00000000000000000000000000000000000010000000000000000000000: n4374_o = 2'b00; + 59'b00000000000000000000000000000000000001000000000000000000000: n4374_o = 2'b00; + 59'b00000000000000000000000000000000000000100000000000000000000: n4374_o = 2'b00; + 59'b00000000000000000000000000000000000000010000000000000000000: n4374_o = 2'b00; + 59'b00000000000000000000000000000000000000001000000000000000000: n4374_o = 2'b00; + 59'b00000000000000000000000000000000000000000100000000000000000: n4374_o = 2'b00; + 59'b00000000000000000000000000000000000000000010000000000000000: n4374_o = 2'b00; + 59'b00000000000000000000000000000000000000000001000000000000000: n4374_o = 2'b00; + 59'b00000000000000000000000000000000000000000000100000000000000: n4374_o = 2'b00; + 59'b00000000000000000000000000000000000000000000010000000000000: n4374_o = 2'b00; + 59'b00000000000000000000000000000000000000000000001000000000000: n4374_o = 2'b00; + 59'b00000000000000000000000000000000000000000000000100000000000: n4374_o = 2'b00; + 59'b00000000000000000000000000000000000000000000000010000000000: n4374_o = n2588_o; + 59'b00000000000000000000000000000000000000000000000001000000000: n4374_o = n2559_o; + 59'b00000000000000000000000000000000000000000000000000100000000: n4374_o = n2539_o; + 59'b00000000000000000000000000000000000000000000000000010000000: n4374_o = 2'b00; + 59'b00000000000000000000000000000000000000000000000000001000000: n4374_o = 2'b00; + 59'b00000000000000000000000000000000000000000000000000000100000: n4374_o = 2'b00; + 59'b00000000000000000000000000000000000000000000000000000010000: n4374_o = 2'b00; + 59'b00000000000000000000000000000000000000000000000000000001000: n4374_o = 2'b00; + 59'b00000000000000000000000000000000000000000000000000000000100: n4374_o = 2'b00; + 59'b00000000000000000000000000000000000000000000000000000000010: n4374_o = 2'b00; + 59'b00000000000000000000000000000000000000000000000000000000001: n4374_o = 2'b00; + default: n4374_o = 2'bX; + endcase + /* T80_MCode.vhd:265:17 */ + always @* + case (n4123_o) + 59'b10000000000000000000000000000000000000000000000000000000000: n4378_o = 1'b0; + 59'b01000000000000000000000000000000000000000000000000000000000: n4378_o = 1'b0; + 59'b00100000000000000000000000000000000000000000000000000000000: n4378_o = 1'b0; + 59'b00010000000000000000000000000000000000000000000000000000000: n4378_o = 1'b0; + 59'b00001000000000000000000000000000000000000000000000000000000: n4378_o = 1'b0; + 59'b00000100000000000000000000000000000000000000000000000000000: n4378_o = 1'b0; + 59'b00000010000000000000000000000000000000000000000000000000000: n4378_o = 1'b0; + 59'b00000001000000000000000000000000000000000000000000000000000: n4378_o = 1'b0; + 59'b00000000100000000000000000000000000000000000000000000000000: n4378_o = 1'b0; + 59'b00000000010000000000000000000000000000000000000000000000000: n4378_o = 1'b0; + 59'b00000000001000000000000000000000000000000000000000000000000: n4378_o = 1'b0; + 59'b00000000000100000000000000000000000000000000000000000000000: n4378_o = 1'b0; + 59'b00000000000010000000000000000000000000000000000000000000000: n4378_o = 1'b0; + 59'b00000000000001000000000000000000000000000000000000000000000: n4378_o = 1'b0; + 59'b00000000000000100000000000000000000000000000000000000000000: n4378_o = 1'b0; + 59'b00000000000000010000000000000000000000000000000000000000000: n4378_o = 1'b0; + 59'b00000000000000001000000000000000000000000000000000000000000: n4378_o = 1'b0; + 59'b00000000000000000100000000000000000000000000000000000000000: n4378_o = 1'b0; + 59'b00000000000000000010000000000000000000000000000000000000000: n4378_o = 1'b0; + 59'b00000000000000000001000000000000000000000000000000000000000: n4378_o = 1'b0; + 59'b00000000000000000000100000000000000000000000000000000000000: n4378_o = 1'b0; + 59'b00000000000000000000010000000000000000000000000000000000000: n4378_o = 1'b0; + 59'b00000000000000000000001000000000000000000000000000000000000: n4378_o = 1'b0; + 59'b00000000000000000000000100000000000000000000000000000000000: n4378_o = 1'b0; + 59'b00000000000000000000000010000000000000000000000000000000000: n4378_o = 1'b1; + 59'b00000000000000000000000001000000000000000000000000000000000: n4378_o = 1'b0; + 59'b00000000000000000000000000100000000000000000000000000000000: n4378_o = 1'b0; + 59'b00000000000000000000000000010000000000000000000000000000000: n4378_o = 1'b0; + 59'b00000000000000000000000000001000000000000000000000000000000: n4378_o = 1'b0; + 59'b00000000000000000000000000000100000000000000000000000000000: n4378_o = 1'b0; + 59'b00000000000000000000000000000010000000000000000000000000000: n4378_o = 1'b0; + 59'b00000000000000000000000000000001000000000000000000000000000: n4378_o = 1'b0; + 59'b00000000000000000000000000000000100000000000000000000000000: n4378_o = 1'b0; + 59'b00000000000000000000000000000000010000000000000000000000000: n4378_o = 1'b0; + 59'b00000000000000000000000000000000001000000000000000000000000: n4378_o = 1'b0; + 59'b00000000000000000000000000000000000100000000000000000000000: n4378_o = 1'b0; + 59'b00000000000000000000000000000000000010000000000000000000000: n4378_o = 1'b0; + 59'b00000000000000000000000000000000000001000000000000000000000: n4378_o = 1'b0; + 59'b00000000000000000000000000000000000000100000000000000000000: n4378_o = 1'b0; + 59'b00000000000000000000000000000000000000010000000000000000000: n4378_o = 1'b0; + 59'b00000000000000000000000000000000000000001000000000000000000: n4378_o = 1'b0; + 59'b00000000000000000000000000000000000000000100000000000000000: n4378_o = 1'b0; + 59'b00000000000000000000000000000000000000000010000000000000000: n4378_o = 1'b0; + 59'b00000000000000000000000000000000000000000001000000000000000: n4378_o = 1'b0; + 59'b00000000000000000000000000000000000000000000100000000000000: n4378_o = 1'b0; + 59'b00000000000000000000000000000000000000000000010000000000000: n4378_o = 1'b0; + 59'b00000000000000000000000000000000000000000000001000000000000: n4378_o = 1'b0; + 59'b00000000000000000000000000000000000000000000000100000000000: n4378_o = 1'b0; + 59'b00000000000000000000000000000000000000000000000010000000000: n4378_o = 1'b0; + 59'b00000000000000000000000000000000000000000000000001000000000: n4378_o = 1'b0; + 59'b00000000000000000000000000000000000000000000000000100000000: n4378_o = 1'b0; + 59'b00000000000000000000000000000000000000000000000000010000000: n4378_o = 1'b0; + 59'b00000000000000000000000000000000000000000000000000001000000: n4378_o = 1'b0; + 59'b00000000000000000000000000000000000000000000000000000100000: n4378_o = 1'b0; + 59'b00000000000000000000000000000000000000000000000000000010000: n4378_o = 1'b0; + 59'b00000000000000000000000000000000000000000000000000000001000: n4378_o = 1'b0; + 59'b00000000000000000000000000000000000000000000000000000000100: n4378_o = 1'b0; + 59'b00000000000000000000000000000000000000000000000000000000010: n4378_o = 1'b0; + 59'b00000000000000000000000000000000000000000000000000000000001: n4378_o = 1'b0; + default: n4378_o = 1'bX; + endcase + /* T80_MCode.vhd:265:17 */ + always @* + case (n4123_o) + 59'b10000000000000000000000000000000000000000000000000000000000: n4382_o = 1'b0; + 59'b01000000000000000000000000000000000000000000000000000000000: n4382_o = 1'b0; + 59'b00100000000000000000000000000000000000000000000000000000000: n4382_o = 1'b0; + 59'b00010000000000000000000000000000000000000000000000000000000: n4382_o = 1'b0; + 59'b00001000000000000000000000000000000000000000000000000000000: n4382_o = 1'b0; + 59'b00000100000000000000000000000000000000000000000000000000000: n4382_o = 1'b0; + 59'b00000010000000000000000000000000000000000000000000000000000: n4382_o = 1'b0; + 59'b00000001000000000000000000000000000000000000000000000000000: n4382_o = 1'b0; + 59'b00000000100000000000000000000000000000000000000000000000000: n4382_o = 1'b0; + 59'b00000000010000000000000000000000000000000000000000000000000: n4382_o = 1'b0; + 59'b00000000001000000000000000000000000000000000000000000000000: n4382_o = 1'b0; + 59'b00000000000100000000000000000000000000000000000000000000000: n4382_o = 1'b0; + 59'b00000000000010000000000000000000000000000000000000000000000: n4382_o = 1'b0; + 59'b00000000000001000000000000000000000000000000000000000000000: n4382_o = 1'b0; + 59'b00000000000000100000000000000000000000000000000000000000000: n4382_o = 1'b0; + 59'b00000000000000010000000000000000000000000000000000000000000: n4382_o = 1'b0; + 59'b00000000000000001000000000000000000000000000000000000000000: n4382_o = 1'b0; + 59'b00000000000000000100000000000000000000000000000000000000000: n4382_o = 1'b0; + 59'b00000000000000000010000000000000000000000000000000000000000: n4382_o = 1'b0; + 59'b00000000000000000001000000000000000000000000000000000000000: n4382_o = 1'b0; + 59'b00000000000000000000100000000000000000000000000000000000000: n4382_o = 1'b0; + 59'b00000000000000000000010000000000000000000000000000000000000: n4382_o = 1'b0; + 59'b00000000000000000000001000000000000000000000000000000000000: n4382_o = 1'b0; + 59'b00000000000000000000000100000000000000000000000000000000000: n4382_o = 1'b1; + 59'b00000000000000000000000010000000000000000000000000000000000: n4382_o = 1'b0; + 59'b00000000000000000000000001000000000000000000000000000000000: n4382_o = 1'b0; + 59'b00000000000000000000000000100000000000000000000000000000000: n4382_o = 1'b0; + 59'b00000000000000000000000000010000000000000000000000000000000: n4382_o = 1'b0; + 59'b00000000000000000000000000001000000000000000000000000000000: n4382_o = 1'b0; + 59'b00000000000000000000000000000100000000000000000000000000000: n4382_o = 1'b0; + 59'b00000000000000000000000000000010000000000000000000000000000: n4382_o = 1'b0; + 59'b00000000000000000000000000000001000000000000000000000000000: n4382_o = 1'b0; + 59'b00000000000000000000000000000000100000000000000000000000000: n4382_o = 1'b0; + 59'b00000000000000000000000000000000010000000000000000000000000: n4382_o = 1'b0; + 59'b00000000000000000000000000000000001000000000000000000000000: n4382_o = 1'b0; + 59'b00000000000000000000000000000000000100000000000000000000000: n4382_o = 1'b0; + 59'b00000000000000000000000000000000000010000000000000000000000: n4382_o = 1'b0; + 59'b00000000000000000000000000000000000001000000000000000000000: n4382_o = 1'b0; + 59'b00000000000000000000000000000000000000100000000000000000000: n4382_o = 1'b0; + 59'b00000000000000000000000000000000000000010000000000000000000: n4382_o = 1'b0; + 59'b00000000000000000000000000000000000000001000000000000000000: n4382_o = 1'b0; + 59'b00000000000000000000000000000000000000000100000000000000000: n4382_o = 1'b0; + 59'b00000000000000000000000000000000000000000010000000000000000: n4382_o = 1'b0; + 59'b00000000000000000000000000000000000000000001000000000000000: n4382_o = 1'b0; + 59'b00000000000000000000000000000000000000000000100000000000000: n4382_o = 1'b0; + 59'b00000000000000000000000000000000000000000000010000000000000: n4382_o = 1'b0; + 59'b00000000000000000000000000000000000000000000001000000000000: n4382_o = 1'b0; + 59'b00000000000000000000000000000000000000000000000100000000000: n4382_o = 1'b0; + 59'b00000000000000000000000000000000000000000000000010000000000: n4382_o = 1'b0; + 59'b00000000000000000000000000000000000000000000000001000000000: n4382_o = 1'b0; + 59'b00000000000000000000000000000000000000000000000000100000000: n4382_o = 1'b0; + 59'b00000000000000000000000000000000000000000000000000010000000: n4382_o = 1'b0; + 59'b00000000000000000000000000000000000000000000000000001000000: n4382_o = 1'b0; + 59'b00000000000000000000000000000000000000000000000000000100000: n4382_o = 1'b0; + 59'b00000000000000000000000000000000000000000000000000000010000: n4382_o = 1'b0; + 59'b00000000000000000000000000000000000000000000000000000001000: n4382_o = 1'b0; + 59'b00000000000000000000000000000000000000000000000000000000100: n4382_o = 1'b0; + 59'b00000000000000000000000000000000000000000000000000000000010: n4382_o = 1'b0; + 59'b00000000000000000000000000000000000000000000000000000000001: n4382_o = 1'b0; + default: n4382_o = 1'bX; + endcase + /* T80_MCode.vhd:265:17 */ + always @* + case (n4123_o) + 59'b10000000000000000000000000000000000000000000000000000000000: n4386_o = 1'b0; + 59'b01000000000000000000000000000000000000000000000000000000000: n4386_o = 1'b0; + 59'b00100000000000000000000000000000000000000000000000000000000: n4386_o = 1'b0; + 59'b00010000000000000000000000000000000000000000000000000000000: n4386_o = 1'b0; + 59'b00001000000000000000000000000000000000000000000000000000000: n4386_o = 1'b0; + 59'b00000100000000000000000000000000000000000000000000000000000: n4386_o = 1'b0; + 59'b00000010000000000000000000000000000000000000000000000000000: n4386_o = 1'b0; + 59'b00000001000000000000000000000000000000000000000000000000000: n4386_o = 1'b0; + 59'b00000000100000000000000000000000000000000000000000000000000: n4386_o = 1'b0; + 59'b00000000010000000000000000000000000000000000000000000000000: n4386_o = 1'b0; + 59'b00000000001000000000000000000000000000000000000000000000000: n4386_o = 1'b0; + 59'b00000000000100000000000000000000000000000000000000000000000: n4386_o = 1'b0; + 59'b00000000000010000000000000000000000000000000000000000000000: n4386_o = 1'b0; + 59'b00000000000001000000000000000000000000000000000000000000000: n4386_o = 1'b0; + 59'b00000000000000100000000000000000000000000000000000000000000: n4386_o = 1'b0; + 59'b00000000000000010000000000000000000000000000000000000000000: n4386_o = 1'b0; + 59'b00000000000000001000000000000000000000000000000000000000000: n4386_o = 1'b0; + 59'b00000000000000000100000000000000000000000000000000000000000: n4386_o = 1'b0; + 59'b00000000000000000010000000000000000000000000000000000000000: n4386_o = 1'b0; + 59'b00000000000000000001000000000000000000000000000000000000000: n4386_o = 1'b0; + 59'b00000000000000000000100000000000000000000000000000000000000: n4386_o = 1'b0; + 59'b00000000000000000000010000000000000000000000000000000000000: n4386_o = 1'b0; + 59'b00000000000000000000001000000000000000000000000000000000000: n4386_o = 1'b0; + 59'b00000000000000000000000100000000000000000000000000000000000: n4386_o = 1'b0; + 59'b00000000000000000000000010000000000000000000000000000000000: n4386_o = 1'b0; + 59'b00000000000000000000000001000000000000000000000000000000000: n4386_o = 1'b1; + 59'b00000000000000000000000000100000000000000000000000000000000: n4386_o = 1'b0; + 59'b00000000000000000000000000010000000000000000000000000000000: n4386_o = 1'b0; + 59'b00000000000000000000000000001000000000000000000000000000000: n4386_o = 1'b0; + 59'b00000000000000000000000000000100000000000000000000000000000: n4386_o = 1'b0; + 59'b00000000000000000000000000000010000000000000000000000000000: n4386_o = 1'b0; + 59'b00000000000000000000000000000001000000000000000000000000000: n4386_o = 1'b0; + 59'b00000000000000000000000000000000100000000000000000000000000: n4386_o = 1'b0; + 59'b00000000000000000000000000000000010000000000000000000000000: n4386_o = 1'b0; + 59'b00000000000000000000000000000000001000000000000000000000000: n4386_o = 1'b0; + 59'b00000000000000000000000000000000000100000000000000000000000: n4386_o = 1'b0; + 59'b00000000000000000000000000000000000010000000000000000000000: n4386_o = 1'b0; + 59'b00000000000000000000000000000000000001000000000000000000000: n4386_o = 1'b0; + 59'b00000000000000000000000000000000000000100000000000000000000: n4386_o = 1'b0; + 59'b00000000000000000000000000000000000000010000000000000000000: n4386_o = 1'b0; + 59'b00000000000000000000000000000000000000001000000000000000000: n4386_o = 1'b0; + 59'b00000000000000000000000000000000000000000100000000000000000: n4386_o = 1'b0; + 59'b00000000000000000000000000000000000000000010000000000000000: n4386_o = 1'b0; + 59'b00000000000000000000000000000000000000000001000000000000000: n4386_o = 1'b0; + 59'b00000000000000000000000000000000000000000000100000000000000: n4386_o = 1'b0; + 59'b00000000000000000000000000000000000000000000010000000000000: n4386_o = 1'b0; + 59'b00000000000000000000000000000000000000000000001000000000000: n4386_o = 1'b0; + 59'b00000000000000000000000000000000000000000000000100000000000: n4386_o = 1'b0; + 59'b00000000000000000000000000000000000000000000000010000000000: n4386_o = 1'b0; + 59'b00000000000000000000000000000000000000000000000001000000000: n4386_o = 1'b0; + 59'b00000000000000000000000000000000000000000000000000100000000: n4386_o = 1'b0; + 59'b00000000000000000000000000000000000000000000000000010000000: n4386_o = 1'b0; + 59'b00000000000000000000000000000000000000000000000000001000000: n4386_o = 1'b0; + 59'b00000000000000000000000000000000000000000000000000000100000: n4386_o = 1'b0; + 59'b00000000000000000000000000000000000000000000000000000010000: n4386_o = 1'b0; + 59'b00000000000000000000000000000000000000000000000000000001000: n4386_o = 1'b0; + 59'b00000000000000000000000000000000000000000000000000000000100: n4386_o = 1'b0; + 59'b00000000000000000000000000000000000000000000000000000000010: n4386_o = 1'b0; + 59'b00000000000000000000000000000000000000000000000000000000001: n4386_o = 1'b0; + default: n4386_o = 1'bX; + endcase + /* T80_MCode.vhd:265:17 */ + always @* + case (n4123_o) + 59'b10000000000000000000000000000000000000000000000000000000000: n4389_o = 1'b0; + 59'b01000000000000000000000000000000000000000000000000000000000: n4389_o = 1'b0; + 59'b00100000000000000000000000000000000000000000000000000000000: n4389_o = 1'b0; + 59'b00010000000000000000000000000000000000000000000000000000000: n4389_o = 1'b0; + 59'b00001000000000000000000000000000000000000000000000000000000: n4389_o = 1'b0; + 59'b00000100000000000000000000000000000000000000000000000000000: n4389_o = 1'b0; + 59'b00000010000000000000000000000000000000000000000000000000000: n4389_o = 1'b0; + 59'b00000001000000000000000000000000000000000000000000000000000: n4389_o = 1'b0; + 59'b00000000100000000000000000000000000000000000000000000000000: n4389_o = 1'b0; + 59'b00000000010000000000000000000000000000000000000000000000000: n4389_o = 1'b0; + 59'b00000000001000000000000000000000000000000000000000000000000: n4389_o = n3740_o; + 59'b00000000000100000000000000000000000000000000000000000000000: n4389_o = 1'b0; + 59'b00000000000010000000000000000000000000000000000000000000000: n4389_o = n3698_o; + 59'b00000000000001000000000000000000000000000000000000000000000: n4389_o = n3672_o; + 59'b00000000000000100000000000000000000000000000000000000000000: n4389_o = n3645_o; + 59'b00000000000000010000000000000000000000000000000000000000000: n4389_o = n3619_o; + 59'b00000000000000001000000000000000000000000000000000000000000: n4389_o = n3592_o; + 59'b00000000000000000100000000000000000000000000000000000000000: n4389_o = 1'b0; + 59'b00000000000000000010000000000000000000000000000000000000000: n4389_o = 1'b0; + 59'b00000000000000000001000000000000000000000000000000000000000: n4389_o = 1'b0; + 59'b00000000000000000000100000000000000000000000000000000000000: n4389_o = 1'b0; + 59'b00000000000000000000010000000000000000000000000000000000000: n4389_o = 1'b0; + 59'b00000000000000000000001000000000000000000000000000000000000: n4389_o = n3425_o; + 59'b00000000000000000000000100000000000000000000000000000000000: n4389_o = 1'b0; + 59'b00000000000000000000000010000000000000000000000000000000000: n4389_o = 1'b0; + 59'b00000000000000000000000001000000000000000000000000000000000: n4389_o = 1'b0; + 59'b00000000000000000000000000100000000000000000000000000000000: n4389_o = 1'b0; + 59'b00000000000000000000000000010000000000000000000000000000000: n4389_o = 1'b0; + 59'b00000000000000000000000000001000000000000000000000000000000: n4389_o = 1'b0; + 59'b00000000000000000000000000000100000000000000000000000000000: n4389_o = 1'b0; + 59'b00000000000000000000000000000010000000000000000000000000000: n4389_o = 1'b0; + 59'b00000000000000000000000000000001000000000000000000000000000: n4389_o = 1'b0; + 59'b00000000000000000000000000000000100000000000000000000000000: n4389_o = 1'b0; + 59'b00000000000000000000000000000000010000000000000000000000000: n4389_o = 1'b0; + 59'b00000000000000000000000000000000001000000000000000000000000: n4389_o = 1'b0; + 59'b00000000000000000000000000000000000100000000000000000000000: n4389_o = 1'b0; + 59'b00000000000000000000000000000000000010000000000000000000000: n4389_o = 1'b0; + 59'b00000000000000000000000000000000000001000000000000000000000: n4389_o = 1'b0; + 59'b00000000000000000000000000000000000000100000000000000000000: n4389_o = 1'b0; + 59'b00000000000000000000000000000000000000010000000000000000000: n4389_o = 1'b0; + 59'b00000000000000000000000000000000000000001000000000000000000: n4389_o = 1'b0; + 59'b00000000000000000000000000000000000000000100000000000000000: n4389_o = 1'b0; + 59'b00000000000000000000000000000000000000000010000000000000000: n4389_o = 1'b0; + 59'b00000000000000000000000000000000000000000001000000000000000: n4389_o = 1'b0; + 59'b00000000000000000000000000000000000000000000100000000000000: n4389_o = 1'b0; + 59'b00000000000000000000000000000000000000000000010000000000000: n4389_o = 1'b0; + 59'b00000000000000000000000000000000000000000000001000000000000: n4389_o = 1'b0; + 59'b00000000000000000000000000000000000000000000000100000000000: n4389_o = 1'b0; + 59'b00000000000000000000000000000000000000000000000010000000000: n4389_o = 1'b0; + 59'b00000000000000000000000000000000000000000000000001000000000: n4389_o = 1'b0; + 59'b00000000000000000000000000000000000000000000000000100000000: n4389_o = 1'b0; + 59'b00000000000000000000000000000000000000000000000000010000000: n4389_o = 1'b0; + 59'b00000000000000000000000000000000000000000000000000001000000: n4389_o = 1'b0; + 59'b00000000000000000000000000000000000000000000000000000100000: n4389_o = 1'b0; + 59'b00000000000000000000000000000000000000000000000000000010000: n4389_o = 1'b0; + 59'b00000000000000000000000000000000000000000000000000000001000: n4389_o = 1'b0; + 59'b00000000000000000000000000000000000000000000000000000000100: n4389_o = 1'b0; + 59'b00000000000000000000000000000000000000000000000000000000010: n4389_o = 1'b0; + 59'b00000000000000000000000000000000000000000000000000000000001: n4389_o = 1'b0; + default: n4389_o = 1'bX; + endcase + /* T80_MCode.vhd:265:17 */ + always @* + case (n4123_o) + 59'b10000000000000000000000000000000000000000000000000000000000: n4392_o = 1'b0; + 59'b01000000000000000000000000000000000000000000000000000000000: n4392_o = 1'b0; + 59'b00100000000000000000000000000000000000000000000000000000000: n4392_o = 1'b0; + 59'b00010000000000000000000000000000000000000000000000000000000: n4392_o = n4111_o; + 59'b00001000000000000000000000000000000000000000000000000000000: n4392_o = 1'b0; + 59'b00000100000000000000000000000000000000000000000000000000000: n4392_o = n4047_o; + 59'b00000010000000000000000000000000000000000000000000000000000: n4392_o = 1'b0; + 59'b00000001000000000000000000000000000000000000000000000000000: n4392_o = 1'b0; + 59'b00000000100000000000000000000000000000000000000000000000000: n4392_o = n3878_o; + 59'b00000000010000000000000000000000000000000000000000000000000: n4392_o = n3783_o; + 59'b00000000001000000000000000000000000000000000000000000000000: n4392_o = 1'b0; + 59'b00000000000100000000000000000000000000000000000000000000000: n4392_o = 1'b0; + 59'b00000000000010000000000000000000000000000000000000000000000: n4392_o = 1'b0; + 59'b00000000000001000000000000000000000000000000000000000000000: n4392_o = 1'b0; + 59'b00000000000000100000000000000000000000000000000000000000000: n4392_o = 1'b0; + 59'b00000000000000010000000000000000000000000000000000000000000: n4392_o = 1'b0; + 59'b00000000000000001000000000000000000000000000000000000000000: n4392_o = 1'b0; + 59'b00000000000000000100000000000000000000000000000000000000000: n4392_o = 1'b0; + 59'b00000000000000000010000000000000000000000000000000000000000: n4392_o = 1'b0; + 59'b00000000000000000001000000000000000000000000000000000000000: n4392_o = 1'b0; + 59'b00000000000000000000100000000000000000000000000000000000000: n4392_o = 1'b0; + 59'b00000000000000000000010000000000000000000000000000000000000: n4392_o = 1'b0; + 59'b00000000000000000000001000000000000000000000000000000000000: n4392_o = 1'b0; + 59'b00000000000000000000000100000000000000000000000000000000000: n4392_o = 1'b0; + 59'b00000000000000000000000010000000000000000000000000000000000: n4392_o = 1'b0; + 59'b00000000000000000000000001000000000000000000000000000000000: n4392_o = 1'b0; + 59'b00000000000000000000000000100000000000000000000000000000000: n4392_o = n3339_o; + 59'b00000000000000000000000000010000000000000000000000000000000: n4392_o = 1'b0; + 59'b00000000000000000000000000001000000000000000000000000000000: n4392_o = 1'b0; + 59'b00000000000000000000000000000100000000000000000000000000000: n4392_o = 1'b0; + 59'b00000000000000000000000000000010000000000000000000000000000: n4392_o = 1'b0; + 59'b00000000000000000000000000000001000000000000000000000000000: n4392_o = n3231_o; + 59'b00000000000000000000000000000000100000000000000000000000000: n4392_o = 1'b0; + 59'b00000000000000000000000000000000010000000000000000000000000: n4392_o = n3176_o; + 59'b00000000000000000000000000000000001000000000000000000000000: n4392_o = 1'b0; + 59'b00000000000000000000000000000000000100000000000000000000000: n4392_o = 1'b0; + 59'b00000000000000000000000000000000000010000000000000000000000: n4392_o = 1'b0; + 59'b00000000000000000000000000000000000001000000000000000000000: n4392_o = 1'b0; + 59'b00000000000000000000000000000000000000100000000000000000000: n4392_o = n2871_o; + 59'b00000000000000000000000000000000000000010000000000000000000: n4392_o = 1'b0; + 59'b00000000000000000000000000000000000000001000000000000000000: n4392_o = 1'b0; + 59'b00000000000000000000000000000000000000000100000000000000000: n4392_o = 1'b0; + 59'b00000000000000000000000000000000000000000010000000000000000: n4392_o = 1'b0; + 59'b00000000000000000000000000000000000000000001000000000000000: n4392_o = n2754_o; + 59'b00000000000000000000000000000000000000000000100000000000000: n4392_o = 1'b0; + 59'b00000000000000000000000000000000000000000000010000000000000: n4392_o = n2712_o; + 59'b00000000000000000000000000000000000000000000001000000000000: n4392_o = 1'b0; + 59'b00000000000000000000000000000000000000000000000100000000000: n4392_o = 1'b0; + 59'b00000000000000000000000000000000000000000000000010000000000: n4392_o = n2591_o; + 59'b00000000000000000000000000000000000000000000000001000000000: n4392_o = n2562_o; + 59'b00000000000000000000000000000000000000000000000000100000000: n4392_o = n2542_o; + 59'b00000000000000000000000000000000000000000000000000010000000: n4392_o = 1'b0; + 59'b00000000000000000000000000000000000000000000000000001000000: n4392_o = 1'b0; + 59'b00000000000000000000000000000000000000000000000000000100000: n4392_o = 1'b0; + 59'b00000000000000000000000000000000000000000000000000000010000: n4392_o = n2471_o; + 59'b00000000000000000000000000000000000000000000000000000001000: n4392_o = n2431_o; + 59'b00000000000000000000000000000000000000000000000000000000100: n4392_o = 1'b0; + 59'b00000000000000000000000000000000000000000000000000000000010: n4392_o = 1'b0; + 59'b00000000000000000000000000000000000000000000000000000000001: n4392_o = 1'b0; + default: n4392_o = 1'bX; + endcase + /* T80_MCode.vhd:257:17 */ + assign n4394_o = iset == 2'b00; + /* T80_MCode.vhd:1356:54 */ + assign n4395_o = ir[2:0]; + /* T80_MCode.vhd:1357:54 */ + assign n4396_o = ir[2:0]; + /* T80_MCode.vhd:1376:44 */ + assign n4398_o = xy_state == 2'b00; + /* T80_MCode.vhd:1377:51 */ + assign n4400_o = mcycle == 3'b001; + /* T80_MCode.vhd:1377:41 */ + assign n4403_o = n4400_o ? 1'b1 : 1'b0; + /* T80_MCode.vhd:1377:41 */ + assign n4405_o = n4400_o ? 4'b1000 : n2203_o; + /* T80_MCode.vhd:1377:41 */ + assign n4408_o = n4400_o ? 1'b1 : 1'b0; + /* T80_MCode.vhd:1386:46 */ + assign n4409_o = {28'b0, mcycle}; // uext + /* T80_MCode.vhd:1387:41 */ + assign n4411_o = n4409_o == 31'b0000000000000000000000000000001; + /* T80_MCode.vhd:1387:48 */ + assign n4413_o = n4409_o == 31'b0000000000000000000000000000111; + /* T80_MCode.vhd:1387:48 */ + assign n4414_o = n4411_o | n4413_o; + /* T80_MCode.vhd:1389:41 */ + assign n4416_o = n4409_o == 31'b0000000000000000000000000000010; + /* T80_MCode.vhd:1395:41 */ + assign n4418_o = n4409_o == 31'b0000000000000000000000000000011; + assign n4419_o = {n4418_o, n4416_o, n4414_o}; + /* T80_MCode.vhd:1386:41 */ + always @* + case (n4419_o) + 3'b100: n4421_o = n2200_o; + 3'b010: n4421_o = 3'b100; + 3'b001: n4421_o = n2200_o; + default: n4421_o = n2200_o; + endcase + /* T80_MCode.vhd:1386:41 */ + always @* + case (n4419_o) + 3'b100: n4424_o = 1'b0; + 3'b010: n4424_o = 1'b1; + 3'b001: n4424_o = 1'b0; + default: n4424_o = 1'b0; + endcase + /* T80_MCode.vhd:1386:41 */ + always @* + case (n4419_o) + 3'b100: n4426_o = n2203_o; + 3'b010: n4426_o = 4'b1000; + 3'b001: n4426_o = n2203_o; + default: n4426_o = n2203_o; + endcase + /* T80_MCode.vhd:1386:41 */ + always @* + case (n4419_o) + 3'b100: n4429_o = 1'b0; + 3'b010: n4429_o = 1'b1; + 3'b001: n4429_o = 1'b0; + default: n4429_o = 1'b0; + endcase + /* T80_MCode.vhd:1386:41 */ + always @* + case (n4419_o) + 3'b100: n4433_o = 3'b111; + 3'b010: n4433_o = 3'b010; + 3'b001: n4433_o = 3'b010; + default: n4433_o = 3'b111; + endcase + /* T80_MCode.vhd:1386:41 */ + always @* + case (n4419_o) + 3'b100: n4436_o = 1'b1; + 3'b010: n4436_o = 1'b0; + 3'b001: n4436_o = 1'b0; + default: n4436_o = 1'b0; + endcase + /* T80_MCode.vhd:1376:33 */ + assign n4439_o = n4398_o ? 3'b001 : 3'b011; + /* T80_MCode.vhd:1376:33 */ + assign n4440_o = n4398_o ? n2200_o : n4421_o; + /* T80_MCode.vhd:1376:33 */ + assign n4441_o = n4398_o ? n4403_o : n4424_o; + /* T80_MCode.vhd:1376:33 */ + assign n4442_o = n4398_o ? n4405_o : n4426_o; + /* T80_MCode.vhd:1376:33 */ + assign n4443_o = n4398_o ? n4408_o : n4429_o; + /* T80_MCode.vhd:1376:33 */ + assign n4445_o = n4398_o ? 3'b111 : n4433_o; + /* T80_MCode.vhd:1376:33 */ + assign n4447_o = n4398_o ? 1'b0 : n4436_o; + /* T80_MCode.vhd:1376:33 */ + assign n4450_o = n4398_o ? 1'b0 : 1'b1; + /* T80_MCode.vhd:1360:25 */ + assign n4452_o = ir == 8'b00000000; + /* T80_MCode.vhd:1360:40 */ + assign n4454_o = ir == 8'b00000001; + /* T80_MCode.vhd:1360:40 */ + assign n4455_o = n4452_o | n4454_o; + /* T80_MCode.vhd:1360:51 */ + assign n4457_o = ir == 8'b00000010; + /* T80_MCode.vhd:1360:51 */ + assign n4458_o = n4455_o | n4457_o; + /* T80_MCode.vhd:1360:62 */ + assign n4460_o = ir == 8'b00000011; + /* T80_MCode.vhd:1360:62 */ + assign n4461_o = n4458_o | n4460_o; + /* T80_MCode.vhd:1360:73 */ + assign n4463_o = ir == 8'b00000100; + /* T80_MCode.vhd:1360:73 */ + assign n4464_o = n4461_o | n4463_o; + /* T80_MCode.vhd:1360:84 */ + assign n4466_o = ir == 8'b00000101; + /* T80_MCode.vhd:1360:84 */ + assign n4467_o = n4464_o | n4466_o; + /* T80_MCode.vhd:1360:95 */ + assign n4469_o = ir == 8'b00000111; + /* T80_MCode.vhd:1360:95 */ + assign n4470_o = n4467_o | n4469_o; + /* T80_MCode.vhd:1361:33 */ + assign n4472_o = ir == 8'b00010000; + /* T80_MCode.vhd:1361:33 */ + assign n4473_o = n4470_o | n4472_o; + /* T80_MCode.vhd:1361:44 */ + assign n4475_o = ir == 8'b00010001; + /* T80_MCode.vhd:1361:44 */ + assign n4476_o = n4473_o | n4475_o; + /* T80_MCode.vhd:1361:55 */ + assign n4478_o = ir == 8'b00010010; + /* T80_MCode.vhd:1361:55 */ + assign n4479_o = n4476_o | n4478_o; + /* T80_MCode.vhd:1361:66 */ + assign n4481_o = ir == 8'b00010011; + /* T80_MCode.vhd:1361:66 */ + assign n4482_o = n4479_o | n4481_o; + /* T80_MCode.vhd:1361:77 */ + assign n4484_o = ir == 8'b00010100; + /* T80_MCode.vhd:1361:77 */ + assign n4485_o = n4482_o | n4484_o; + /* T80_MCode.vhd:1361:88 */ + assign n4487_o = ir == 8'b00010101; + /* T80_MCode.vhd:1361:88 */ + assign n4488_o = n4485_o | n4487_o; + /* T80_MCode.vhd:1361:99 */ + assign n4490_o = ir == 8'b00010111; + /* T80_MCode.vhd:1361:99 */ + assign n4491_o = n4488_o | n4490_o; + /* T80_MCode.vhd:1362:33 */ + assign n4493_o = ir == 8'b00001000; + /* T80_MCode.vhd:1362:33 */ + assign n4494_o = n4491_o | n4493_o; + /* T80_MCode.vhd:1362:44 */ + assign n4496_o = ir == 8'b00001001; + /* T80_MCode.vhd:1362:44 */ + assign n4497_o = n4494_o | n4496_o; + /* T80_MCode.vhd:1362:55 */ + assign n4499_o = ir == 8'b00001010; + /* T80_MCode.vhd:1362:55 */ + assign n4500_o = n4497_o | n4499_o; + /* T80_MCode.vhd:1362:66 */ + assign n4502_o = ir == 8'b00001011; + /* T80_MCode.vhd:1362:66 */ + assign n4503_o = n4500_o | n4502_o; + /* T80_MCode.vhd:1362:77 */ + assign n4505_o = ir == 8'b00001100; + /* T80_MCode.vhd:1362:77 */ + assign n4506_o = n4503_o | n4505_o; + /* T80_MCode.vhd:1362:88 */ + assign n4508_o = ir == 8'b00001101; + /* T80_MCode.vhd:1362:88 */ + assign n4509_o = n4506_o | n4508_o; + /* T80_MCode.vhd:1362:99 */ + assign n4511_o = ir == 8'b00001111; + /* T80_MCode.vhd:1362:99 */ + assign n4512_o = n4509_o | n4511_o; + /* T80_MCode.vhd:1363:33 */ + assign n4514_o = ir == 8'b00011000; + /* T80_MCode.vhd:1363:33 */ + assign n4515_o = n4512_o | n4514_o; + /* T80_MCode.vhd:1363:44 */ + assign n4517_o = ir == 8'b00011001; + /* T80_MCode.vhd:1363:44 */ + assign n4518_o = n4515_o | n4517_o; + /* T80_MCode.vhd:1363:55 */ + assign n4520_o = ir == 8'b00011010; + /* T80_MCode.vhd:1363:55 */ + assign n4521_o = n4518_o | n4520_o; + /* T80_MCode.vhd:1363:66 */ + assign n4523_o = ir == 8'b00011011; + /* T80_MCode.vhd:1363:66 */ + assign n4524_o = n4521_o | n4523_o; + /* T80_MCode.vhd:1363:77 */ + assign n4526_o = ir == 8'b00011100; + /* T80_MCode.vhd:1363:77 */ + assign n4527_o = n4524_o | n4526_o; + /* T80_MCode.vhd:1363:88 */ + assign n4529_o = ir == 8'b00011101; + /* T80_MCode.vhd:1363:88 */ + assign n4530_o = n4527_o | n4529_o; + /* T80_MCode.vhd:1363:99 */ + assign n4532_o = ir == 8'b00011111; + /* T80_MCode.vhd:1363:99 */ + assign n4533_o = n4530_o | n4532_o; + /* T80_MCode.vhd:1364:33 */ + assign n4535_o = ir == 8'b00100000; + /* T80_MCode.vhd:1364:33 */ + assign n4536_o = n4533_o | n4535_o; + /* T80_MCode.vhd:1364:44 */ + assign n4538_o = ir == 8'b00100001; + /* T80_MCode.vhd:1364:44 */ + assign n4539_o = n4536_o | n4538_o; + /* T80_MCode.vhd:1364:55 */ + assign n4541_o = ir == 8'b00100010; + /* T80_MCode.vhd:1364:55 */ + assign n4542_o = n4539_o | n4541_o; + /* T80_MCode.vhd:1364:66 */ + assign n4544_o = ir == 8'b00100011; + /* T80_MCode.vhd:1364:66 */ + assign n4545_o = n4542_o | n4544_o; + /* T80_MCode.vhd:1364:77 */ + assign n4547_o = ir == 8'b00100100; + /* T80_MCode.vhd:1364:77 */ + assign n4548_o = n4545_o | n4547_o; + /* T80_MCode.vhd:1364:88 */ + assign n4550_o = ir == 8'b00100101; + /* T80_MCode.vhd:1364:88 */ + assign n4551_o = n4548_o | n4550_o; + /* T80_MCode.vhd:1364:99 */ + assign n4553_o = ir == 8'b00100111; + /* T80_MCode.vhd:1364:99 */ + assign n4554_o = n4551_o | n4553_o; + /* T80_MCode.vhd:1365:33 */ + assign n4556_o = ir == 8'b00101000; + /* T80_MCode.vhd:1365:33 */ + assign n4557_o = n4554_o | n4556_o; + /* T80_MCode.vhd:1365:44 */ + assign n4559_o = ir == 8'b00101001; + /* T80_MCode.vhd:1365:44 */ + assign n4560_o = n4557_o | n4559_o; + /* T80_MCode.vhd:1365:55 */ + assign n4562_o = ir == 8'b00101010; + /* T80_MCode.vhd:1365:55 */ + assign n4563_o = n4560_o | n4562_o; + /* T80_MCode.vhd:1365:66 */ + assign n4565_o = ir == 8'b00101011; + /* T80_MCode.vhd:1365:66 */ + assign n4566_o = n4563_o | n4565_o; + /* T80_MCode.vhd:1365:77 */ + assign n4568_o = ir == 8'b00101100; + /* T80_MCode.vhd:1365:77 */ + assign n4569_o = n4566_o | n4568_o; + /* T80_MCode.vhd:1365:88 */ + assign n4571_o = ir == 8'b00101101; + /* T80_MCode.vhd:1365:88 */ + assign n4572_o = n4569_o | n4571_o; + /* T80_MCode.vhd:1365:99 */ + assign n4574_o = ir == 8'b00101111; + /* T80_MCode.vhd:1365:99 */ + assign n4575_o = n4572_o | n4574_o; + /* T80_MCode.vhd:1366:33 */ + assign n4577_o = ir == 8'b00110000; + /* T80_MCode.vhd:1366:33 */ + assign n4578_o = n4575_o | n4577_o; + /* T80_MCode.vhd:1366:44 */ + assign n4580_o = ir == 8'b00110001; + /* T80_MCode.vhd:1366:44 */ + assign n4581_o = n4578_o | n4580_o; + /* T80_MCode.vhd:1366:55 */ + assign n4583_o = ir == 8'b00110010; + /* T80_MCode.vhd:1366:55 */ + assign n4584_o = n4581_o | n4583_o; + /* T80_MCode.vhd:1366:66 */ + assign n4586_o = ir == 8'b00110011; + /* T80_MCode.vhd:1366:66 */ + assign n4587_o = n4584_o | n4586_o; + /* T80_MCode.vhd:1366:77 */ + assign n4589_o = ir == 8'b00110100; + /* T80_MCode.vhd:1366:77 */ + assign n4590_o = n4587_o | n4589_o; + /* T80_MCode.vhd:1366:88 */ + assign n4592_o = ir == 8'b00110101; + /* T80_MCode.vhd:1366:88 */ + assign n4593_o = n4590_o | n4592_o; + /* T80_MCode.vhd:1366:99 */ + assign n4595_o = ir == 8'b00110111; + /* T80_MCode.vhd:1366:99 */ + assign n4596_o = n4593_o | n4595_o; + /* T80_MCode.vhd:1367:33 */ + assign n4598_o = ir == 8'b00111000; + /* T80_MCode.vhd:1367:33 */ + assign n4599_o = n4596_o | n4598_o; + /* T80_MCode.vhd:1367:44 */ + assign n4601_o = ir == 8'b00111001; + /* T80_MCode.vhd:1367:44 */ + assign n4602_o = n4599_o | n4601_o; + /* T80_MCode.vhd:1367:55 */ + assign n4604_o = ir == 8'b00111010; + /* T80_MCode.vhd:1367:55 */ + assign n4605_o = n4602_o | n4604_o; + /* T80_MCode.vhd:1367:66 */ + assign n4607_o = ir == 8'b00111011; + /* T80_MCode.vhd:1367:66 */ + assign n4608_o = n4605_o | n4607_o; + /* T80_MCode.vhd:1367:77 */ + assign n4610_o = ir == 8'b00111100; + /* T80_MCode.vhd:1367:77 */ + assign n4611_o = n4608_o | n4610_o; + /* T80_MCode.vhd:1367:88 */ + assign n4613_o = ir == 8'b00111101; + /* T80_MCode.vhd:1367:88 */ + assign n4614_o = n4611_o | n4613_o; + /* T80_MCode.vhd:1367:99 */ + assign n4616_o = ir == 8'b00111111; + /* T80_MCode.vhd:1367:99 */ + assign n4617_o = n4614_o | n4616_o; + /* T80_MCode.vhd:1411:38 */ + assign n4618_o = {28'b0, mcycle}; // uext + /* T80_MCode.vhd:1412:33 */ + assign n4620_o = n4618_o == 31'b0000000000000000000000000000001; + /* T80_MCode.vhd:1412:40 */ + assign n4622_o = n4618_o == 31'b0000000000000000000000000000111; + /* T80_MCode.vhd:1412:40 */ + assign n4623_o = n4620_o | n4622_o; + /* T80_MCode.vhd:1414:33 */ + assign n4625_o = n4618_o == 31'b0000000000000000000000000000010; + /* T80_MCode.vhd:1420:33 */ + assign n4627_o = n4618_o == 31'b0000000000000000000000000000011; + assign n4628_o = {n4627_o, n4625_o, n4623_o}; + /* T80_MCode.vhd:1411:33 */ + always @* + case (n4628_o) + 3'b100: n4630_o = n2200_o; + 3'b010: n4630_o = 3'b100; + 3'b001: n4630_o = n2200_o; + default: n4630_o = n2200_o; + endcase + /* T80_MCode.vhd:1411:33 */ + always @* + case (n4628_o) + 3'b100: n4633_o = 1'b0; + 3'b010: n4633_o = 1'b1; + 3'b001: n4633_o = 1'b0; + default: n4633_o = 1'b0; + endcase + /* T80_MCode.vhd:1411:33 */ + always @* + case (n4628_o) + 3'b100: n4635_o = n2203_o; + 3'b010: n4635_o = 4'b1000; + 3'b001: n4635_o = n2203_o; + default: n4635_o = n2203_o; + endcase + /* T80_MCode.vhd:1411:33 */ + always @* + case (n4628_o) + 3'b100: n4638_o = 1'b0; + 3'b010: n4638_o = 1'b1; + 3'b001: n4638_o = 1'b0; + default: n4638_o = 1'b0; + endcase + /* T80_MCode.vhd:1411:33 */ + always @* + case (n4628_o) + 3'b100: n4642_o = 3'b111; + 3'b010: n4642_o = 3'b010; + 3'b001: n4642_o = 3'b010; + default: n4642_o = 3'b111; + endcase + /* T80_MCode.vhd:1411:33 */ + always @* + case (n4628_o) + 3'b100: n4645_o = 1'b1; + 3'b010: n4645_o = 1'b0; + 3'b001: n4645_o = 1'b0; + default: n4645_o = 1'b0; + endcase + /* T80_MCode.vhd:1401:25 */ + assign n4647_o = ir == 8'b00000110; + /* T80_MCode.vhd:1401:40 */ + assign n4649_o = ir == 8'b00010110; + /* T80_MCode.vhd:1401:40 */ + assign n4650_o = n4647_o | n4649_o; + /* T80_MCode.vhd:1401:51 */ + assign n4652_o = ir == 8'b00001110; + /* T80_MCode.vhd:1401:51 */ + assign n4653_o = n4650_o | n4652_o; + /* T80_MCode.vhd:1401:62 */ + assign n4655_o = ir == 8'b00011110; + /* T80_MCode.vhd:1401:62 */ + assign n4656_o = n4653_o | n4655_o; + /* T80_MCode.vhd:1401:73 */ + assign n4658_o = ir == 8'b00101110; + /* T80_MCode.vhd:1401:73 */ + assign n4659_o = n4656_o | n4658_o; + /* T80_MCode.vhd:1401:84 */ + assign n4661_o = ir == 8'b00111110; + /* T80_MCode.vhd:1401:84 */ + assign n4662_o = n4659_o | n4661_o; + /* T80_MCode.vhd:1401:95 */ + assign n4664_o = ir == 8'b00100110; + /* T80_MCode.vhd:1401:95 */ + assign n4665_o = n4662_o | n4664_o; + /* T80_MCode.vhd:1401:106 */ + assign n4667_o = ir == 8'b00110110; + /* T80_MCode.vhd:1401:106 */ + assign n4668_o = n4665_o | n4667_o; + /* T80_MCode.vhd:1433:44 */ + assign n4670_o = xy_state == 2'b00; + /* T80_MCode.vhd:1434:51 */ + assign n4672_o = mcycle == 3'b001; + /* T80_MCode.vhd:1435:72 */ + assign n4673_o = ir[2:0]; + /* T80_MCode.vhd:1433:33 */ + assign n4674_o = n4697_o ? n4673_o : n4396_o; + /* T80_MCode.vhd:1434:41 */ + assign n4676_o = n4672_o ? 4'b1001 : n2203_o; + /* T80_MCode.vhd:1442:46 */ + assign n4677_o = {28'b0, mcycle}; // uext + /* T80_MCode.vhd:1443:41 */ + assign n4679_o = n4677_o == 31'b0000000000000000000000000000001; + /* T80_MCode.vhd:1443:48 */ + assign n4681_o = n4677_o == 31'b0000000000000000000000000000111; + /* T80_MCode.vhd:1443:48 */ + assign n4682_o = n4679_o | n4681_o; + /* T80_MCode.vhd:1445:41 */ + assign n4684_o = n4677_o == 31'b0000000000000000000000000000010; + assign n4685_o = {n4684_o, n4682_o}; + /* T80_MCode.vhd:1442:41 */ + always @* + case (n4685_o) + 2'b10: n4687_o = 3'b100; + 2'b01: n4687_o = n2200_o; + default: n4687_o = n2200_o; + endcase + /* T80_MCode.vhd:1442:41 */ + always @* + case (n4685_o) + 2'b10: n4689_o = 4'b1001; + 2'b01: n4689_o = n2203_o; + default: n4689_o = n2203_o; + endcase + /* T80_MCode.vhd:1442:41 */ + always @* + case (n4685_o) + 2'b10: n4692_o = 3'b111; + 2'b01: n4692_o = 3'b010; + default: n4692_o = 3'b111; + endcase + /* T80_MCode.vhd:1433:33 */ + assign n4695_o = n4670_o ? 3'b001 : 3'b010; + /* T80_MCode.vhd:1433:33 */ + assign n4696_o = n4670_o ? n2200_o : n4687_o; + /* T80_MCode.vhd:1433:33 */ + assign n4697_o = n4670_o & n4672_o; + /* T80_MCode.vhd:1433:33 */ + assign n4698_o = n4670_o ? n4676_o : n4689_o; + /* T80_MCode.vhd:1433:33 */ + assign n4700_o = n4670_o ? 3'b111 : n4692_o; + /* T80_MCode.vhd:1433:33 */ + assign n4703_o = n4670_o ? 1'b0 : 1'b1; + /* T80_MCode.vhd:1424:25 */ + assign n4705_o = ir == 8'b01000000; + /* T80_MCode.vhd:1424:40 */ + assign n4707_o = ir == 8'b01000001; + /* T80_MCode.vhd:1424:40 */ + assign n4708_o = n4705_o | n4707_o; + /* T80_MCode.vhd:1424:51 */ + assign n4710_o = ir == 8'b01000010; + /* T80_MCode.vhd:1424:51 */ + assign n4711_o = n4708_o | n4710_o; + /* T80_MCode.vhd:1424:62 */ + assign n4713_o = ir == 8'b01000011; + /* T80_MCode.vhd:1424:62 */ + assign n4714_o = n4711_o | n4713_o; + /* T80_MCode.vhd:1424:73 */ + assign n4716_o = ir == 8'b01000100; + /* T80_MCode.vhd:1424:73 */ + assign n4717_o = n4714_o | n4716_o; + /* T80_MCode.vhd:1424:84 */ + assign n4719_o = ir == 8'b01000101; + /* T80_MCode.vhd:1424:84 */ + assign n4720_o = n4717_o | n4719_o; + /* T80_MCode.vhd:1424:95 */ + assign n4722_o = ir == 8'b01000111; + /* T80_MCode.vhd:1424:95 */ + assign n4723_o = n4720_o | n4722_o; + /* T80_MCode.vhd:1425:33 */ + assign n4725_o = ir == 8'b01001000; + /* T80_MCode.vhd:1425:33 */ + assign n4726_o = n4723_o | n4725_o; + /* T80_MCode.vhd:1425:44 */ + assign n4728_o = ir == 8'b01001001; + /* T80_MCode.vhd:1425:44 */ + assign n4729_o = n4726_o | n4728_o; + /* T80_MCode.vhd:1425:55 */ + assign n4731_o = ir == 8'b01001010; + /* T80_MCode.vhd:1425:55 */ + assign n4732_o = n4729_o | n4731_o; + /* T80_MCode.vhd:1425:66 */ + assign n4734_o = ir == 8'b01001011; + /* T80_MCode.vhd:1425:66 */ + assign n4735_o = n4732_o | n4734_o; + /* T80_MCode.vhd:1425:77 */ + assign n4737_o = ir == 8'b01001100; + /* T80_MCode.vhd:1425:77 */ + assign n4738_o = n4735_o | n4737_o; + /* T80_MCode.vhd:1425:88 */ + assign n4740_o = ir == 8'b01001101; + /* T80_MCode.vhd:1425:88 */ + assign n4741_o = n4738_o | n4740_o; + /* T80_MCode.vhd:1425:99 */ + assign n4743_o = ir == 8'b01001111; + /* T80_MCode.vhd:1425:99 */ + assign n4744_o = n4741_o | n4743_o; + /* T80_MCode.vhd:1426:33 */ + assign n4746_o = ir == 8'b01010000; + /* T80_MCode.vhd:1426:33 */ + assign n4747_o = n4744_o | n4746_o; + /* T80_MCode.vhd:1426:44 */ + assign n4749_o = ir == 8'b01010001; + /* T80_MCode.vhd:1426:44 */ + assign n4750_o = n4747_o | n4749_o; + /* T80_MCode.vhd:1426:55 */ + assign n4752_o = ir == 8'b01010010; + /* T80_MCode.vhd:1426:55 */ + assign n4753_o = n4750_o | n4752_o; + /* T80_MCode.vhd:1426:66 */ + assign n4755_o = ir == 8'b01010011; + /* T80_MCode.vhd:1426:66 */ + assign n4756_o = n4753_o | n4755_o; + /* T80_MCode.vhd:1426:77 */ + assign n4758_o = ir == 8'b01010100; + /* T80_MCode.vhd:1426:77 */ + assign n4759_o = n4756_o | n4758_o; + /* T80_MCode.vhd:1426:88 */ + assign n4761_o = ir == 8'b01010101; + /* T80_MCode.vhd:1426:88 */ + assign n4762_o = n4759_o | n4761_o; + /* T80_MCode.vhd:1426:99 */ + assign n4764_o = ir == 8'b01010111; + /* T80_MCode.vhd:1426:99 */ + assign n4765_o = n4762_o | n4764_o; + /* T80_MCode.vhd:1427:33 */ + assign n4767_o = ir == 8'b01011000; + /* T80_MCode.vhd:1427:33 */ + assign n4768_o = n4765_o | n4767_o; + /* T80_MCode.vhd:1427:44 */ + assign n4770_o = ir == 8'b01011001; + /* T80_MCode.vhd:1427:44 */ + assign n4771_o = n4768_o | n4770_o; + /* T80_MCode.vhd:1427:55 */ + assign n4773_o = ir == 8'b01011010; + /* T80_MCode.vhd:1427:55 */ + assign n4774_o = n4771_o | n4773_o; + /* T80_MCode.vhd:1427:66 */ + assign n4776_o = ir == 8'b01011011; + /* T80_MCode.vhd:1427:66 */ + assign n4777_o = n4774_o | n4776_o; + /* T80_MCode.vhd:1427:77 */ + assign n4779_o = ir == 8'b01011100; + /* T80_MCode.vhd:1427:77 */ + assign n4780_o = n4777_o | n4779_o; + /* T80_MCode.vhd:1427:88 */ + assign n4782_o = ir == 8'b01011101; + /* T80_MCode.vhd:1427:88 */ + assign n4783_o = n4780_o | n4782_o; + /* T80_MCode.vhd:1427:99 */ + assign n4785_o = ir == 8'b01011111; + /* T80_MCode.vhd:1427:99 */ + assign n4786_o = n4783_o | n4785_o; + /* T80_MCode.vhd:1428:33 */ + assign n4788_o = ir == 8'b01100000; + /* T80_MCode.vhd:1428:33 */ + assign n4789_o = n4786_o | n4788_o; + /* T80_MCode.vhd:1428:44 */ + assign n4791_o = ir == 8'b01100001; + /* T80_MCode.vhd:1428:44 */ + assign n4792_o = n4789_o | n4791_o; + /* T80_MCode.vhd:1428:55 */ + assign n4794_o = ir == 8'b01100010; + /* T80_MCode.vhd:1428:55 */ + assign n4795_o = n4792_o | n4794_o; + /* T80_MCode.vhd:1428:66 */ + assign n4797_o = ir == 8'b01100011; + /* T80_MCode.vhd:1428:66 */ + assign n4798_o = n4795_o | n4797_o; + /* T80_MCode.vhd:1428:77 */ + assign n4800_o = ir == 8'b01100100; + /* T80_MCode.vhd:1428:77 */ + assign n4801_o = n4798_o | n4800_o; + /* T80_MCode.vhd:1428:88 */ + assign n4803_o = ir == 8'b01100101; + /* T80_MCode.vhd:1428:88 */ + assign n4804_o = n4801_o | n4803_o; + /* T80_MCode.vhd:1428:99 */ + assign n4806_o = ir == 8'b01100111; + /* T80_MCode.vhd:1428:99 */ + assign n4807_o = n4804_o | n4806_o; + /* T80_MCode.vhd:1429:33 */ + assign n4809_o = ir == 8'b01101000; + /* T80_MCode.vhd:1429:33 */ + assign n4810_o = n4807_o | n4809_o; + /* T80_MCode.vhd:1429:44 */ + assign n4812_o = ir == 8'b01101001; + /* T80_MCode.vhd:1429:44 */ + assign n4813_o = n4810_o | n4812_o; + /* T80_MCode.vhd:1429:55 */ + assign n4815_o = ir == 8'b01101010; + /* T80_MCode.vhd:1429:55 */ + assign n4816_o = n4813_o | n4815_o; + /* T80_MCode.vhd:1429:66 */ + assign n4818_o = ir == 8'b01101011; + /* T80_MCode.vhd:1429:66 */ + assign n4819_o = n4816_o | n4818_o; + /* T80_MCode.vhd:1429:77 */ + assign n4821_o = ir == 8'b01101100; + /* T80_MCode.vhd:1429:77 */ + assign n4822_o = n4819_o | n4821_o; + /* T80_MCode.vhd:1429:88 */ + assign n4824_o = ir == 8'b01101101; + /* T80_MCode.vhd:1429:88 */ + assign n4825_o = n4822_o | n4824_o; + /* T80_MCode.vhd:1429:99 */ + assign n4827_o = ir == 8'b01101111; + /* T80_MCode.vhd:1429:99 */ + assign n4828_o = n4825_o | n4827_o; + /* T80_MCode.vhd:1430:33 */ + assign n4830_o = ir == 8'b01110000; + /* T80_MCode.vhd:1430:33 */ + assign n4831_o = n4828_o | n4830_o; + /* T80_MCode.vhd:1430:44 */ + assign n4833_o = ir == 8'b01110001; + /* T80_MCode.vhd:1430:44 */ + assign n4834_o = n4831_o | n4833_o; + /* T80_MCode.vhd:1430:55 */ + assign n4836_o = ir == 8'b01110010; + /* T80_MCode.vhd:1430:55 */ + assign n4837_o = n4834_o | n4836_o; + /* T80_MCode.vhd:1430:66 */ + assign n4839_o = ir == 8'b01110011; + /* T80_MCode.vhd:1430:66 */ + assign n4840_o = n4837_o | n4839_o; + /* T80_MCode.vhd:1430:77 */ + assign n4842_o = ir == 8'b01110100; + /* T80_MCode.vhd:1430:77 */ + assign n4843_o = n4840_o | n4842_o; + /* T80_MCode.vhd:1430:88 */ + assign n4845_o = ir == 8'b01110101; + /* T80_MCode.vhd:1430:88 */ + assign n4846_o = n4843_o | n4845_o; + /* T80_MCode.vhd:1430:99 */ + assign n4848_o = ir == 8'b01110111; + /* T80_MCode.vhd:1430:99 */ + assign n4849_o = n4846_o | n4848_o; + /* T80_MCode.vhd:1431:33 */ + assign n4851_o = ir == 8'b01111000; + /* T80_MCode.vhd:1431:33 */ + assign n4852_o = n4849_o | n4851_o; + /* T80_MCode.vhd:1431:44 */ + assign n4854_o = ir == 8'b01111001; + /* T80_MCode.vhd:1431:44 */ + assign n4855_o = n4852_o | n4854_o; + /* T80_MCode.vhd:1431:55 */ + assign n4857_o = ir == 8'b01111010; + /* T80_MCode.vhd:1431:55 */ + assign n4858_o = n4855_o | n4857_o; + /* T80_MCode.vhd:1431:66 */ + assign n4860_o = ir == 8'b01111011; + /* T80_MCode.vhd:1431:66 */ + assign n4861_o = n4858_o | n4860_o; + /* T80_MCode.vhd:1431:77 */ + assign n4863_o = ir == 8'b01111100; + /* T80_MCode.vhd:1431:77 */ + assign n4864_o = n4861_o | n4863_o; + /* T80_MCode.vhd:1431:88 */ + assign n4866_o = ir == 8'b01111101; + /* T80_MCode.vhd:1431:88 */ + assign n4867_o = n4864_o | n4866_o; + /* T80_MCode.vhd:1431:99 */ + assign n4869_o = ir == 8'b01111111; + /* T80_MCode.vhd:1431:99 */ + assign n4870_o = n4867_o | n4869_o; + /* T80_MCode.vhd:1455:38 */ + assign n4871_o = {28'b0, mcycle}; // uext + /* T80_MCode.vhd:1456:33 */ + assign n4873_o = n4871_o == 31'b0000000000000000000000000000001; + /* T80_MCode.vhd:1456:40 */ + assign n4875_o = n4871_o == 31'b0000000000000000000000000000111; + /* T80_MCode.vhd:1456:40 */ + assign n4876_o = n4873_o | n4875_o; + /* T80_MCode.vhd:1458:33 */ + assign n4878_o = n4871_o == 31'b0000000000000000000000000000010; + assign n4879_o = {n4878_o, n4876_o}; + /* T80_MCode.vhd:1455:33 */ + always @* + case (n4879_o) + 2'b10: n4881_o = 3'b100; + 2'b01: n4881_o = n2200_o; + default: n4881_o = n2200_o; + endcase + /* T80_MCode.vhd:1455:33 */ + always @* + case (n4879_o) + 2'b10: n4883_o = 4'b1001; + 2'b01: n4883_o = n2203_o; + default: n4883_o = n2203_o; + endcase + /* T80_MCode.vhd:1455:33 */ + always @* + case (n4879_o) + 2'b10: n4886_o = 3'b111; + 2'b01: n4886_o = 3'b010; + default: n4886_o = 3'b111; + endcase + /* T80_MCode.vhd:1452:25 */ + assign n4888_o = ir == 8'b01000110; + /* T80_MCode.vhd:1452:40 */ + assign n4890_o = ir == 8'b01001110; + /* T80_MCode.vhd:1452:40 */ + assign n4891_o = n4888_o | n4890_o; + /* T80_MCode.vhd:1452:51 */ + assign n4893_o = ir == 8'b01010110; + /* T80_MCode.vhd:1452:51 */ + assign n4894_o = n4891_o | n4893_o; + /* T80_MCode.vhd:1452:62 */ + assign n4896_o = ir == 8'b01011110; + /* T80_MCode.vhd:1452:62 */ + assign n4897_o = n4894_o | n4896_o; + /* T80_MCode.vhd:1452:73 */ + assign n4899_o = ir == 8'b01100110; + /* T80_MCode.vhd:1452:73 */ + assign n4900_o = n4897_o | n4899_o; + /* T80_MCode.vhd:1452:84 */ + assign n4902_o = ir == 8'b01101110; + /* T80_MCode.vhd:1452:84 */ + assign n4903_o = n4900_o | n4902_o; + /* T80_MCode.vhd:1452:95 */ + assign n4905_o = ir == 8'b01110110; + /* T80_MCode.vhd:1452:95 */ + assign n4906_o = n4903_o | n4905_o; + /* T80_MCode.vhd:1452:106 */ + assign n4908_o = ir == 8'b01111110; + /* T80_MCode.vhd:1452:106 */ + assign n4909_o = n4906_o | n4908_o; + /* T80_MCode.vhd:1472:44 */ + assign n4911_o = xy_state == 2'b00; + /* T80_MCode.vhd:1473:51 */ + assign n4913_o = mcycle == 3'b001; + /* T80_MCode.vhd:1473:41 */ + assign n4916_o = n4913_o ? 1'b1 : 1'b0; + /* T80_MCode.vhd:1473:41 */ + assign n4918_o = n4913_o ? 4'b1010 : n2203_o; + /* T80_MCode.vhd:1473:41 */ + assign n4921_o = n4913_o ? 1'b1 : 1'b0; + /* T80_MCode.vhd:1482:46 */ + assign n4922_o = {28'b0, mcycle}; // uext + /* T80_MCode.vhd:1483:41 */ + assign n4924_o = n4922_o == 31'b0000000000000000000000000000001; + /* T80_MCode.vhd:1483:48 */ + assign n4926_o = n4922_o == 31'b0000000000000000000000000000111; + /* T80_MCode.vhd:1483:48 */ + assign n4927_o = n4924_o | n4926_o; + /* T80_MCode.vhd:1485:41 */ + assign n4929_o = n4922_o == 31'b0000000000000000000000000000010; + /* T80_MCode.vhd:1491:41 */ + assign n4931_o = n4922_o == 31'b0000000000000000000000000000011; + assign n4932_o = {n4931_o, n4929_o, n4927_o}; + /* T80_MCode.vhd:1482:41 */ + always @* + case (n4932_o) + 3'b100: n4934_o = n2200_o; + 3'b010: n4934_o = 3'b100; + 3'b001: n4934_o = n2200_o; + default: n4934_o = n2200_o; + endcase + /* T80_MCode.vhd:1482:41 */ + always @* + case (n4932_o) + 3'b100: n4937_o = 1'b0; + 3'b010: n4937_o = 1'b1; + 3'b001: n4937_o = 1'b0; + default: n4937_o = 1'b0; + endcase + /* T80_MCode.vhd:1482:41 */ + always @* + case (n4932_o) + 3'b100: n4939_o = n2203_o; + 3'b010: n4939_o = 4'b1010; + 3'b001: n4939_o = n2203_o; + default: n4939_o = n2203_o; + endcase + /* T80_MCode.vhd:1482:41 */ + always @* + case (n4932_o) + 3'b100: n4942_o = 1'b0; + 3'b010: n4942_o = 1'b1; + 3'b001: n4942_o = 1'b0; + default: n4942_o = 1'b0; + endcase + /* T80_MCode.vhd:1482:41 */ + always @* + case (n4932_o) + 3'b100: n4946_o = 3'b111; + 3'b010: n4946_o = 3'b010; + 3'b001: n4946_o = 3'b010; + default: n4946_o = 3'b111; + endcase + /* T80_MCode.vhd:1482:41 */ + always @* + case (n4932_o) + 3'b100: n4949_o = 1'b1; + 3'b010: n4949_o = 1'b0; + 3'b001: n4949_o = 1'b0; + default: n4949_o = 1'b0; + endcase + /* T80_MCode.vhd:1472:33 */ + assign n4952_o = n4911_o ? 3'b001 : 3'b011; + /* T80_MCode.vhd:1472:33 */ + assign n4953_o = n4911_o ? n2200_o : n4934_o; + /* T80_MCode.vhd:1472:33 */ + assign n4954_o = n4911_o ? n4916_o : n4937_o; + /* T80_MCode.vhd:1472:33 */ + assign n4955_o = n4911_o ? n4918_o : n4939_o; + /* T80_MCode.vhd:1472:33 */ + assign n4956_o = n4911_o ? n4921_o : n4942_o; + /* T80_MCode.vhd:1472:33 */ + assign n4958_o = n4911_o ? 3'b111 : n4946_o; + /* T80_MCode.vhd:1472:33 */ + assign n4960_o = n4911_o ? 1'b0 : n4949_o; + /* T80_MCode.vhd:1472:33 */ + assign n4963_o = n4911_o ? 1'b0 : 1'b1; + /* T80_MCode.vhd:1463:25 */ + assign n4965_o = ir == 8'b11000000; + /* T80_MCode.vhd:1463:40 */ + assign n4967_o = ir == 8'b11000001; + /* T80_MCode.vhd:1463:40 */ + assign n4968_o = n4965_o | n4967_o; + /* T80_MCode.vhd:1463:51 */ + assign n4970_o = ir == 8'b11000010; + /* T80_MCode.vhd:1463:51 */ + assign n4971_o = n4968_o | n4970_o; + /* T80_MCode.vhd:1463:62 */ + assign n4973_o = ir == 8'b11000011; + /* T80_MCode.vhd:1463:62 */ + assign n4974_o = n4971_o | n4973_o; + /* T80_MCode.vhd:1463:73 */ + assign n4976_o = ir == 8'b11000100; + /* T80_MCode.vhd:1463:73 */ + assign n4977_o = n4974_o | n4976_o; + /* T80_MCode.vhd:1463:84 */ + assign n4979_o = ir == 8'b11000101; + /* T80_MCode.vhd:1463:84 */ + assign n4980_o = n4977_o | n4979_o; + /* T80_MCode.vhd:1463:95 */ + assign n4982_o = ir == 8'b11000111; + /* T80_MCode.vhd:1463:95 */ + assign n4983_o = n4980_o | n4982_o; + /* T80_MCode.vhd:1464:33 */ + assign n4985_o = ir == 8'b11001000; + /* T80_MCode.vhd:1464:33 */ + assign n4986_o = n4983_o | n4985_o; + /* T80_MCode.vhd:1464:44 */ + assign n4988_o = ir == 8'b11001001; + /* T80_MCode.vhd:1464:44 */ + assign n4989_o = n4986_o | n4988_o; + /* T80_MCode.vhd:1464:55 */ + assign n4991_o = ir == 8'b11001010; + /* T80_MCode.vhd:1464:55 */ + assign n4992_o = n4989_o | n4991_o; + /* T80_MCode.vhd:1464:66 */ + assign n4994_o = ir == 8'b11001011; + /* T80_MCode.vhd:1464:66 */ + assign n4995_o = n4992_o | n4994_o; + /* T80_MCode.vhd:1464:77 */ + assign n4997_o = ir == 8'b11001100; + /* T80_MCode.vhd:1464:77 */ + assign n4998_o = n4995_o | n4997_o; + /* T80_MCode.vhd:1464:88 */ + assign n5000_o = ir == 8'b11001101; + /* T80_MCode.vhd:1464:88 */ + assign n5001_o = n4998_o | n5000_o; + /* T80_MCode.vhd:1464:99 */ + assign n5003_o = ir == 8'b11001111; + /* T80_MCode.vhd:1464:99 */ + assign n5004_o = n5001_o | n5003_o; + /* T80_MCode.vhd:1465:33 */ + assign n5006_o = ir == 8'b11010000; + /* T80_MCode.vhd:1465:33 */ + assign n5007_o = n5004_o | n5006_o; + /* T80_MCode.vhd:1465:44 */ + assign n5009_o = ir == 8'b11010001; + /* T80_MCode.vhd:1465:44 */ + assign n5010_o = n5007_o | n5009_o; + /* T80_MCode.vhd:1465:55 */ + assign n5012_o = ir == 8'b11010010; + /* T80_MCode.vhd:1465:55 */ + assign n5013_o = n5010_o | n5012_o; + /* T80_MCode.vhd:1465:66 */ + assign n5015_o = ir == 8'b11010011; + /* T80_MCode.vhd:1465:66 */ + assign n5016_o = n5013_o | n5015_o; + /* T80_MCode.vhd:1465:77 */ + assign n5018_o = ir == 8'b11010100; + /* T80_MCode.vhd:1465:77 */ + assign n5019_o = n5016_o | n5018_o; + /* T80_MCode.vhd:1465:88 */ + assign n5021_o = ir == 8'b11010101; + /* T80_MCode.vhd:1465:88 */ + assign n5022_o = n5019_o | n5021_o; + /* T80_MCode.vhd:1465:99 */ + assign n5024_o = ir == 8'b11010111; + /* T80_MCode.vhd:1465:99 */ + assign n5025_o = n5022_o | n5024_o; + /* T80_MCode.vhd:1466:33 */ + assign n5027_o = ir == 8'b11011000; + /* T80_MCode.vhd:1466:33 */ + assign n5028_o = n5025_o | n5027_o; + /* T80_MCode.vhd:1466:44 */ + assign n5030_o = ir == 8'b11011001; + /* T80_MCode.vhd:1466:44 */ + assign n5031_o = n5028_o | n5030_o; + /* T80_MCode.vhd:1466:55 */ + assign n5033_o = ir == 8'b11011010; + /* T80_MCode.vhd:1466:55 */ + assign n5034_o = n5031_o | n5033_o; + /* T80_MCode.vhd:1466:66 */ + assign n5036_o = ir == 8'b11011011; + /* T80_MCode.vhd:1466:66 */ + assign n5037_o = n5034_o | n5036_o; + /* T80_MCode.vhd:1466:77 */ + assign n5039_o = ir == 8'b11011100; + /* T80_MCode.vhd:1466:77 */ + assign n5040_o = n5037_o | n5039_o; + /* T80_MCode.vhd:1466:88 */ + assign n5042_o = ir == 8'b11011101; + /* T80_MCode.vhd:1466:88 */ + assign n5043_o = n5040_o | n5042_o; + /* T80_MCode.vhd:1466:99 */ + assign n5045_o = ir == 8'b11011111; + /* T80_MCode.vhd:1466:99 */ + assign n5046_o = n5043_o | n5045_o; + /* T80_MCode.vhd:1467:33 */ + assign n5048_o = ir == 8'b11100000; + /* T80_MCode.vhd:1467:33 */ + assign n5049_o = n5046_o | n5048_o; + /* T80_MCode.vhd:1467:44 */ + assign n5051_o = ir == 8'b11100001; + /* T80_MCode.vhd:1467:44 */ + assign n5052_o = n5049_o | n5051_o; + /* T80_MCode.vhd:1467:55 */ + assign n5054_o = ir == 8'b11100010; + /* T80_MCode.vhd:1467:55 */ + assign n5055_o = n5052_o | n5054_o; + /* T80_MCode.vhd:1467:66 */ + assign n5057_o = ir == 8'b11100011; + /* T80_MCode.vhd:1467:66 */ + assign n5058_o = n5055_o | n5057_o; + /* T80_MCode.vhd:1467:77 */ + assign n5060_o = ir == 8'b11100100; + /* T80_MCode.vhd:1467:77 */ + assign n5061_o = n5058_o | n5060_o; + /* T80_MCode.vhd:1467:88 */ + assign n5063_o = ir == 8'b11100101; + /* T80_MCode.vhd:1467:88 */ + assign n5064_o = n5061_o | n5063_o; + /* T80_MCode.vhd:1467:99 */ + assign n5066_o = ir == 8'b11100111; + /* T80_MCode.vhd:1467:99 */ + assign n5067_o = n5064_o | n5066_o; + /* T80_MCode.vhd:1468:33 */ + assign n5069_o = ir == 8'b11101000; + /* T80_MCode.vhd:1468:33 */ + assign n5070_o = n5067_o | n5069_o; + /* T80_MCode.vhd:1468:44 */ + assign n5072_o = ir == 8'b11101001; + /* T80_MCode.vhd:1468:44 */ + assign n5073_o = n5070_o | n5072_o; + /* T80_MCode.vhd:1468:55 */ + assign n5075_o = ir == 8'b11101010; + /* T80_MCode.vhd:1468:55 */ + assign n5076_o = n5073_o | n5075_o; + /* T80_MCode.vhd:1468:66 */ + assign n5078_o = ir == 8'b11101011; + /* T80_MCode.vhd:1468:66 */ + assign n5079_o = n5076_o | n5078_o; + /* T80_MCode.vhd:1468:77 */ + assign n5081_o = ir == 8'b11101100; + /* T80_MCode.vhd:1468:77 */ + assign n5082_o = n5079_o | n5081_o; + /* T80_MCode.vhd:1468:88 */ + assign n5084_o = ir == 8'b11101101; + /* T80_MCode.vhd:1468:88 */ + assign n5085_o = n5082_o | n5084_o; + /* T80_MCode.vhd:1468:99 */ + assign n5087_o = ir == 8'b11101111; + /* T80_MCode.vhd:1468:99 */ + assign n5088_o = n5085_o | n5087_o; + /* T80_MCode.vhd:1469:33 */ + assign n5090_o = ir == 8'b11110000; + /* T80_MCode.vhd:1469:33 */ + assign n5091_o = n5088_o | n5090_o; + /* T80_MCode.vhd:1469:44 */ + assign n5093_o = ir == 8'b11110001; + /* T80_MCode.vhd:1469:44 */ + assign n5094_o = n5091_o | n5093_o; + /* T80_MCode.vhd:1469:55 */ + assign n5096_o = ir == 8'b11110010; + /* T80_MCode.vhd:1469:55 */ + assign n5097_o = n5094_o | n5096_o; + /* T80_MCode.vhd:1469:66 */ + assign n5099_o = ir == 8'b11110011; + /* T80_MCode.vhd:1469:66 */ + assign n5100_o = n5097_o | n5099_o; + /* T80_MCode.vhd:1469:77 */ + assign n5102_o = ir == 8'b11110100; + /* T80_MCode.vhd:1469:77 */ + assign n5103_o = n5100_o | n5102_o; + /* T80_MCode.vhd:1469:88 */ + assign n5105_o = ir == 8'b11110101; + /* T80_MCode.vhd:1469:88 */ + assign n5106_o = n5103_o | n5105_o; + /* T80_MCode.vhd:1469:99 */ + assign n5108_o = ir == 8'b11110111; + /* T80_MCode.vhd:1469:99 */ + assign n5109_o = n5106_o | n5108_o; + /* T80_MCode.vhd:1470:33 */ + assign n5111_o = ir == 8'b11111000; + /* T80_MCode.vhd:1470:33 */ + assign n5112_o = n5109_o | n5111_o; + /* T80_MCode.vhd:1470:44 */ + assign n5114_o = ir == 8'b11111001; + /* T80_MCode.vhd:1470:44 */ + assign n5115_o = n5112_o | n5114_o; + /* T80_MCode.vhd:1470:55 */ + assign n5117_o = ir == 8'b11111010; + /* T80_MCode.vhd:1470:55 */ + assign n5118_o = n5115_o | n5117_o; + /* T80_MCode.vhd:1470:66 */ + assign n5120_o = ir == 8'b11111011; + /* T80_MCode.vhd:1470:66 */ + assign n5121_o = n5118_o | n5120_o; + /* T80_MCode.vhd:1470:77 */ + assign n5123_o = ir == 8'b11111100; + /* T80_MCode.vhd:1470:77 */ + assign n5124_o = n5121_o | n5123_o; + /* T80_MCode.vhd:1470:88 */ + assign n5126_o = ir == 8'b11111101; + /* T80_MCode.vhd:1470:88 */ + assign n5127_o = n5124_o | n5126_o; + /* T80_MCode.vhd:1470:99 */ + assign n5129_o = ir == 8'b11111111; + /* T80_MCode.vhd:1470:99 */ + assign n5130_o = n5127_o | n5129_o; + /* T80_MCode.vhd:1500:38 */ + assign n5131_o = {28'b0, mcycle}; // uext + /* T80_MCode.vhd:1501:33 */ + assign n5133_o = n5131_o == 31'b0000000000000000000000000000001; + /* T80_MCode.vhd:1501:40 */ + assign n5135_o = n5131_o == 31'b0000000000000000000000000000111; + /* T80_MCode.vhd:1501:40 */ + assign n5136_o = n5133_o | n5135_o; + /* T80_MCode.vhd:1503:33 */ + assign n5138_o = n5131_o == 31'b0000000000000000000000000000010; + /* T80_MCode.vhd:1509:33 */ + assign n5140_o = n5131_o == 31'b0000000000000000000000000000011; + assign n5141_o = {n5140_o, n5138_o, n5136_o}; + /* T80_MCode.vhd:1500:33 */ + always @* + case (n5141_o) + 3'b100: n5143_o = n2200_o; + 3'b010: n5143_o = 3'b100; + 3'b001: n5143_o = n2200_o; + default: n5143_o = n2200_o; + endcase + /* T80_MCode.vhd:1500:33 */ + always @* + case (n5141_o) + 3'b100: n5146_o = 1'b0; + 3'b010: n5146_o = 1'b1; + 3'b001: n5146_o = 1'b0; + default: n5146_o = 1'b0; + endcase + /* T80_MCode.vhd:1500:33 */ + always @* + case (n5141_o) + 3'b100: n5148_o = n2203_o; + 3'b010: n5148_o = 4'b1010; + 3'b001: n5148_o = n2203_o; + default: n5148_o = n2203_o; + endcase + /* T80_MCode.vhd:1500:33 */ + always @* + case (n5141_o) + 3'b100: n5151_o = 1'b0; + 3'b010: n5151_o = 1'b1; + 3'b001: n5151_o = 1'b0; + default: n5151_o = 1'b0; + endcase + /* T80_MCode.vhd:1500:33 */ + always @* + case (n5141_o) + 3'b100: n5155_o = 3'b111; + 3'b010: n5155_o = 3'b010; + 3'b001: n5155_o = 3'b010; + default: n5155_o = 3'b111; + endcase + /* T80_MCode.vhd:1500:33 */ + always @* + case (n5141_o) + 3'b100: n5158_o = 1'b1; + 3'b010: n5158_o = 1'b0; + 3'b001: n5158_o = 1'b0; + default: n5158_o = 1'b0; + endcase + /* T80_MCode.vhd:1497:25 */ + assign n5160_o = ir == 8'b11000110; + /* T80_MCode.vhd:1497:40 */ + assign n5162_o = ir == 8'b11001110; + /* T80_MCode.vhd:1497:40 */ + assign n5163_o = n5160_o | n5162_o; + /* T80_MCode.vhd:1497:51 */ + assign n5165_o = ir == 8'b11010110; + /* T80_MCode.vhd:1497:51 */ + assign n5166_o = n5163_o | n5165_o; + /* T80_MCode.vhd:1497:62 */ + assign n5168_o = ir == 8'b11011110; + /* T80_MCode.vhd:1497:62 */ + assign n5169_o = n5166_o | n5168_o; + /* T80_MCode.vhd:1497:73 */ + assign n5171_o = ir == 8'b11100110; + /* T80_MCode.vhd:1497:73 */ + assign n5172_o = n5169_o | n5171_o; + /* T80_MCode.vhd:1497:84 */ + assign n5174_o = ir == 8'b11101110; + /* T80_MCode.vhd:1497:84 */ + assign n5175_o = n5172_o | n5174_o; + /* T80_MCode.vhd:1497:95 */ + assign n5177_o = ir == 8'b11110110; + /* T80_MCode.vhd:1497:95 */ + assign n5178_o = n5175_o | n5177_o; + /* T80_MCode.vhd:1497:106 */ + assign n5180_o = ir == 8'b11111110; + /* T80_MCode.vhd:1497:106 */ + assign n5181_o = n5178_o | n5180_o; + /* T80_MCode.vhd:1522:44 */ + assign n5183_o = xy_state == 2'b00; + /* T80_MCode.vhd:1523:51 */ + assign n5185_o = mcycle == 3'b001; + /* T80_MCode.vhd:1523:41 */ + assign n5188_o = n5185_o ? 1'b1 : 1'b0; + /* T80_MCode.vhd:1523:41 */ + assign n5190_o = n5185_o ? 4'b1011 : n2203_o; + /* T80_MCode.vhd:1523:41 */ + assign n5193_o = n5185_o ? 1'b1 : 1'b0; + /* T80_MCode.vhd:1532:46 */ + assign n5194_o = {28'b0, mcycle}; // uext + /* T80_MCode.vhd:1533:41 */ + assign n5196_o = n5194_o == 31'b0000000000000000000000000000001; + /* T80_MCode.vhd:1533:48 */ + assign n5198_o = n5194_o == 31'b0000000000000000000000000000111; + /* T80_MCode.vhd:1533:48 */ + assign n5199_o = n5196_o | n5198_o; + /* T80_MCode.vhd:1535:41 */ + assign n5201_o = n5194_o == 31'b0000000000000000000000000000010; + /* T80_MCode.vhd:1541:41 */ + assign n5203_o = n5194_o == 31'b0000000000000000000000000000011; + assign n5204_o = {n5203_o, n5201_o, n5199_o}; + /* T80_MCode.vhd:1532:41 */ + always @* + case (n5204_o) + 3'b100: n5206_o = n2200_o; + 3'b010: n5206_o = 3'b100; + 3'b001: n5206_o = n2200_o; + default: n5206_o = n2200_o; + endcase + /* T80_MCode.vhd:1532:41 */ + always @* + case (n5204_o) + 3'b100: n5209_o = 1'b0; + 3'b010: n5209_o = 1'b1; + 3'b001: n5209_o = 1'b0; + default: n5209_o = 1'b0; + endcase + /* T80_MCode.vhd:1532:41 */ + always @* + case (n5204_o) + 3'b100: n5211_o = n2203_o; + 3'b010: n5211_o = 4'b1011; + 3'b001: n5211_o = n2203_o; + default: n5211_o = n2203_o; + endcase + /* T80_MCode.vhd:1532:41 */ + always @* + case (n5204_o) + 3'b100: n5214_o = 1'b0; + 3'b010: n5214_o = 1'b1; + 3'b001: n5214_o = 1'b0; + default: n5214_o = 1'b0; + endcase + /* T80_MCode.vhd:1532:41 */ + always @* + case (n5204_o) + 3'b100: n5218_o = 3'b111; + 3'b010: n5218_o = 3'b010; + 3'b001: n5218_o = 3'b010; + default: n5218_o = 3'b111; + endcase + /* T80_MCode.vhd:1532:41 */ + always @* + case (n5204_o) + 3'b100: n5221_o = 1'b1; + 3'b010: n5221_o = 1'b0; + 3'b001: n5221_o = 1'b0; + default: n5221_o = 1'b0; + endcase + /* T80_MCode.vhd:1522:33 */ + assign n5224_o = n5183_o ? 3'b001 : 3'b011; + /* T80_MCode.vhd:1522:33 */ + assign n5225_o = n5183_o ? n2200_o : n5206_o; + /* T80_MCode.vhd:1522:33 */ + assign n5226_o = n5183_o ? n5188_o : n5209_o; + /* T80_MCode.vhd:1522:33 */ + assign n5227_o = n5183_o ? n5190_o : n5211_o; + /* T80_MCode.vhd:1522:33 */ + assign n5228_o = n5183_o ? n5193_o : n5214_o; + /* T80_MCode.vhd:1522:33 */ + assign n5230_o = n5183_o ? 3'b111 : n5218_o; + /* T80_MCode.vhd:1522:33 */ + assign n5232_o = n5183_o ? 1'b0 : n5221_o; + /* T80_MCode.vhd:1522:33 */ + assign n5235_o = n5183_o ? 1'b0 : 1'b1; + /* T80_MCode.vhd:1513:25 */ + assign n5237_o = ir == 8'b10000000; + /* T80_MCode.vhd:1513:40 */ + assign n5239_o = ir == 8'b10000001; + /* T80_MCode.vhd:1513:40 */ + assign n5240_o = n5237_o | n5239_o; + /* T80_MCode.vhd:1513:51 */ + assign n5242_o = ir == 8'b10000010; + /* T80_MCode.vhd:1513:51 */ + assign n5243_o = n5240_o | n5242_o; + /* T80_MCode.vhd:1513:62 */ + assign n5245_o = ir == 8'b10000011; + /* T80_MCode.vhd:1513:62 */ + assign n5246_o = n5243_o | n5245_o; + /* T80_MCode.vhd:1513:73 */ + assign n5248_o = ir == 8'b10000100; + /* T80_MCode.vhd:1513:73 */ + assign n5249_o = n5246_o | n5248_o; + /* T80_MCode.vhd:1513:84 */ + assign n5251_o = ir == 8'b10000101; + /* T80_MCode.vhd:1513:84 */ + assign n5252_o = n5249_o | n5251_o; + /* T80_MCode.vhd:1513:95 */ + assign n5254_o = ir == 8'b10000111; + /* T80_MCode.vhd:1513:95 */ + assign n5255_o = n5252_o | n5254_o; + /* T80_MCode.vhd:1514:33 */ + assign n5257_o = ir == 8'b10001000; + /* T80_MCode.vhd:1514:33 */ + assign n5258_o = n5255_o | n5257_o; + /* T80_MCode.vhd:1514:44 */ + assign n5260_o = ir == 8'b10001001; + /* T80_MCode.vhd:1514:44 */ + assign n5261_o = n5258_o | n5260_o; + /* T80_MCode.vhd:1514:55 */ + assign n5263_o = ir == 8'b10001010; + /* T80_MCode.vhd:1514:55 */ + assign n5264_o = n5261_o | n5263_o; + /* T80_MCode.vhd:1514:66 */ + assign n5266_o = ir == 8'b10001011; + /* T80_MCode.vhd:1514:66 */ + assign n5267_o = n5264_o | n5266_o; + /* T80_MCode.vhd:1514:77 */ + assign n5269_o = ir == 8'b10001100; + /* T80_MCode.vhd:1514:77 */ + assign n5270_o = n5267_o | n5269_o; + /* T80_MCode.vhd:1514:88 */ + assign n5272_o = ir == 8'b10001101; + /* T80_MCode.vhd:1514:88 */ + assign n5273_o = n5270_o | n5272_o; + /* T80_MCode.vhd:1514:99 */ + assign n5275_o = ir == 8'b10001111; + /* T80_MCode.vhd:1514:99 */ + assign n5276_o = n5273_o | n5275_o; + /* T80_MCode.vhd:1515:33 */ + assign n5278_o = ir == 8'b10010000; + /* T80_MCode.vhd:1515:33 */ + assign n5279_o = n5276_o | n5278_o; + /* T80_MCode.vhd:1515:44 */ + assign n5281_o = ir == 8'b10010001; + /* T80_MCode.vhd:1515:44 */ + assign n5282_o = n5279_o | n5281_o; + /* T80_MCode.vhd:1515:55 */ + assign n5284_o = ir == 8'b10010010; + /* T80_MCode.vhd:1515:55 */ + assign n5285_o = n5282_o | n5284_o; + /* T80_MCode.vhd:1515:66 */ + assign n5287_o = ir == 8'b10010011; + /* T80_MCode.vhd:1515:66 */ + assign n5288_o = n5285_o | n5287_o; + /* T80_MCode.vhd:1515:77 */ + assign n5290_o = ir == 8'b10010100; + /* T80_MCode.vhd:1515:77 */ + assign n5291_o = n5288_o | n5290_o; + /* T80_MCode.vhd:1515:88 */ + assign n5293_o = ir == 8'b10010101; + /* T80_MCode.vhd:1515:88 */ + assign n5294_o = n5291_o | n5293_o; + /* T80_MCode.vhd:1515:99 */ + assign n5296_o = ir == 8'b10010111; + /* T80_MCode.vhd:1515:99 */ + assign n5297_o = n5294_o | n5296_o; + /* T80_MCode.vhd:1516:33 */ + assign n5299_o = ir == 8'b10011000; + /* T80_MCode.vhd:1516:33 */ + assign n5300_o = n5297_o | n5299_o; + /* T80_MCode.vhd:1516:44 */ + assign n5302_o = ir == 8'b10011001; + /* T80_MCode.vhd:1516:44 */ + assign n5303_o = n5300_o | n5302_o; + /* T80_MCode.vhd:1516:55 */ + assign n5305_o = ir == 8'b10011010; + /* T80_MCode.vhd:1516:55 */ + assign n5306_o = n5303_o | n5305_o; + /* T80_MCode.vhd:1516:66 */ + assign n5308_o = ir == 8'b10011011; + /* T80_MCode.vhd:1516:66 */ + assign n5309_o = n5306_o | n5308_o; + /* T80_MCode.vhd:1516:77 */ + assign n5311_o = ir == 8'b10011100; + /* T80_MCode.vhd:1516:77 */ + assign n5312_o = n5309_o | n5311_o; + /* T80_MCode.vhd:1516:88 */ + assign n5314_o = ir == 8'b10011101; + /* T80_MCode.vhd:1516:88 */ + assign n5315_o = n5312_o | n5314_o; + /* T80_MCode.vhd:1516:99 */ + assign n5317_o = ir == 8'b10011111; + /* T80_MCode.vhd:1516:99 */ + assign n5318_o = n5315_o | n5317_o; + /* T80_MCode.vhd:1517:33 */ + assign n5320_o = ir == 8'b10100000; + /* T80_MCode.vhd:1517:33 */ + assign n5321_o = n5318_o | n5320_o; + /* T80_MCode.vhd:1517:44 */ + assign n5323_o = ir == 8'b10100001; + /* T80_MCode.vhd:1517:44 */ + assign n5324_o = n5321_o | n5323_o; + /* T80_MCode.vhd:1517:55 */ + assign n5326_o = ir == 8'b10100010; + /* T80_MCode.vhd:1517:55 */ + assign n5327_o = n5324_o | n5326_o; + /* T80_MCode.vhd:1517:66 */ + assign n5329_o = ir == 8'b10100011; + /* T80_MCode.vhd:1517:66 */ + assign n5330_o = n5327_o | n5329_o; + /* T80_MCode.vhd:1517:77 */ + assign n5332_o = ir == 8'b10100100; + /* T80_MCode.vhd:1517:77 */ + assign n5333_o = n5330_o | n5332_o; + /* T80_MCode.vhd:1517:88 */ + assign n5335_o = ir == 8'b10100101; + /* T80_MCode.vhd:1517:88 */ + assign n5336_o = n5333_o | n5335_o; + /* T80_MCode.vhd:1517:99 */ + assign n5338_o = ir == 8'b10100111; + /* T80_MCode.vhd:1517:99 */ + assign n5339_o = n5336_o | n5338_o; + /* T80_MCode.vhd:1518:33 */ + assign n5341_o = ir == 8'b10101000; + /* T80_MCode.vhd:1518:33 */ + assign n5342_o = n5339_o | n5341_o; + /* T80_MCode.vhd:1518:44 */ + assign n5344_o = ir == 8'b10101001; + /* T80_MCode.vhd:1518:44 */ + assign n5345_o = n5342_o | n5344_o; + /* T80_MCode.vhd:1518:55 */ + assign n5347_o = ir == 8'b10101010; + /* T80_MCode.vhd:1518:55 */ + assign n5348_o = n5345_o | n5347_o; + /* T80_MCode.vhd:1518:66 */ + assign n5350_o = ir == 8'b10101011; + /* T80_MCode.vhd:1518:66 */ + assign n5351_o = n5348_o | n5350_o; + /* T80_MCode.vhd:1518:77 */ + assign n5353_o = ir == 8'b10101100; + /* T80_MCode.vhd:1518:77 */ + assign n5354_o = n5351_o | n5353_o; + /* T80_MCode.vhd:1518:88 */ + assign n5356_o = ir == 8'b10101101; + /* T80_MCode.vhd:1518:88 */ + assign n5357_o = n5354_o | n5356_o; + /* T80_MCode.vhd:1518:99 */ + assign n5359_o = ir == 8'b10101111; + /* T80_MCode.vhd:1518:99 */ + assign n5360_o = n5357_o | n5359_o; + /* T80_MCode.vhd:1519:33 */ + assign n5362_o = ir == 8'b10110000; + /* T80_MCode.vhd:1519:33 */ + assign n5363_o = n5360_o | n5362_o; + /* T80_MCode.vhd:1519:44 */ + assign n5365_o = ir == 8'b10110001; + /* T80_MCode.vhd:1519:44 */ + assign n5366_o = n5363_o | n5365_o; + /* T80_MCode.vhd:1519:55 */ + assign n5368_o = ir == 8'b10110010; + /* T80_MCode.vhd:1519:55 */ + assign n5369_o = n5366_o | n5368_o; + /* T80_MCode.vhd:1519:66 */ + assign n5371_o = ir == 8'b10110011; + /* T80_MCode.vhd:1519:66 */ + assign n5372_o = n5369_o | n5371_o; + /* T80_MCode.vhd:1519:77 */ + assign n5374_o = ir == 8'b10110100; + /* T80_MCode.vhd:1519:77 */ + assign n5375_o = n5372_o | n5374_o; + /* T80_MCode.vhd:1519:88 */ + assign n5377_o = ir == 8'b10110101; + /* T80_MCode.vhd:1519:88 */ + assign n5378_o = n5375_o | n5377_o; + /* T80_MCode.vhd:1519:99 */ + assign n5380_o = ir == 8'b10110111; + /* T80_MCode.vhd:1519:99 */ + assign n5381_o = n5378_o | n5380_o; + /* T80_MCode.vhd:1520:33 */ + assign n5383_o = ir == 8'b10111000; + /* T80_MCode.vhd:1520:33 */ + assign n5384_o = n5381_o | n5383_o; + /* T80_MCode.vhd:1520:44 */ + assign n5386_o = ir == 8'b10111001; + /* T80_MCode.vhd:1520:44 */ + assign n5387_o = n5384_o | n5386_o; + /* T80_MCode.vhd:1520:55 */ + assign n5389_o = ir == 8'b10111010; + /* T80_MCode.vhd:1520:55 */ + assign n5390_o = n5387_o | n5389_o; + /* T80_MCode.vhd:1520:66 */ + assign n5392_o = ir == 8'b10111011; + /* T80_MCode.vhd:1520:66 */ + assign n5393_o = n5390_o | n5392_o; + /* T80_MCode.vhd:1520:77 */ + assign n5395_o = ir == 8'b10111100; + /* T80_MCode.vhd:1520:77 */ + assign n5396_o = n5393_o | n5395_o; + /* T80_MCode.vhd:1520:88 */ + assign n5398_o = ir == 8'b10111101; + /* T80_MCode.vhd:1520:88 */ + assign n5399_o = n5396_o | n5398_o; + /* T80_MCode.vhd:1520:99 */ + assign n5401_o = ir == 8'b10111111; + /* T80_MCode.vhd:1520:99 */ + assign n5402_o = n5399_o | n5401_o; + /* T80_MCode.vhd:1550:38 */ + assign n5403_o = {28'b0, mcycle}; // uext + /* T80_MCode.vhd:1551:33 */ + assign n5405_o = n5403_o == 31'b0000000000000000000000000000001; + /* T80_MCode.vhd:1551:40 */ + assign n5407_o = n5403_o == 31'b0000000000000000000000000000111; + /* T80_MCode.vhd:1551:40 */ + assign n5408_o = n5405_o | n5407_o; + /* T80_MCode.vhd:1553:33 */ + assign n5410_o = n5403_o == 31'b0000000000000000000000000000010; + /* T80_MCode.vhd:1559:33 */ + assign n5412_o = n5403_o == 31'b0000000000000000000000000000011; + assign n5413_o = {n5412_o, n5410_o, n5408_o}; + /* T80_MCode.vhd:1550:33 */ + always @* + case (n5413_o) + 3'b100: n5415_o = n2200_o; + 3'b010: n5415_o = 3'b100; + 3'b001: n5415_o = n2200_o; + default: n5415_o = n2200_o; + endcase + /* T80_MCode.vhd:1550:33 */ + always @* + case (n5413_o) + 3'b100: n5418_o = 1'b0; + 3'b010: n5418_o = 1'b1; + 3'b001: n5418_o = 1'b0; + default: n5418_o = 1'b0; + endcase + /* T80_MCode.vhd:1550:33 */ + always @* + case (n5413_o) + 3'b100: n5420_o = n2203_o; + 3'b010: n5420_o = 4'b1011; + 3'b001: n5420_o = n2203_o; + default: n5420_o = n2203_o; + endcase + /* T80_MCode.vhd:1550:33 */ + always @* + case (n5413_o) + 3'b100: n5423_o = 1'b0; + 3'b010: n5423_o = 1'b1; + 3'b001: n5423_o = 1'b0; + default: n5423_o = 1'b0; + endcase + /* T80_MCode.vhd:1550:33 */ + always @* + case (n5413_o) + 3'b100: n5427_o = 3'b111; + 3'b010: n5427_o = 3'b010; + 3'b001: n5427_o = 3'b010; + default: n5427_o = 3'b111; + endcase + /* T80_MCode.vhd:1550:33 */ + always @* + case (n5413_o) + 3'b100: n5430_o = 1'b1; + 3'b010: n5430_o = 1'b0; + 3'b001: n5430_o = 1'b0; + default: n5430_o = 1'b0; + endcase + /* T80_MCode.vhd:1547:25 */ + assign n5432_o = ir == 8'b10000110; + /* T80_MCode.vhd:1547:40 */ + assign n5434_o = ir == 8'b10001110; + /* T80_MCode.vhd:1547:40 */ + assign n5435_o = n5432_o | n5434_o; + /* T80_MCode.vhd:1547:51 */ + assign n5437_o = ir == 8'b10010110; + /* T80_MCode.vhd:1547:51 */ + assign n5438_o = n5435_o | n5437_o; + /* T80_MCode.vhd:1547:62 */ + assign n5440_o = ir == 8'b10011110; + /* T80_MCode.vhd:1547:62 */ + assign n5441_o = n5438_o | n5440_o; + /* T80_MCode.vhd:1547:73 */ + assign n5443_o = ir == 8'b10100110; + /* T80_MCode.vhd:1547:73 */ + assign n5444_o = n5441_o | n5443_o; + /* T80_MCode.vhd:1547:84 */ + assign n5446_o = ir == 8'b10101110; + /* T80_MCode.vhd:1547:84 */ + assign n5447_o = n5444_o | n5446_o; + /* T80_MCode.vhd:1547:95 */ + assign n5449_o = ir == 8'b10110110; + /* T80_MCode.vhd:1547:95 */ + assign n5450_o = n5447_o | n5449_o; + /* T80_MCode.vhd:1547:106 */ + assign n5452_o = ir == 8'b10111110; + /* T80_MCode.vhd:1547:106 */ + assign n5453_o = n5450_o | n5452_o; + assign n5454_o = {n5453_o, n5402_o, n5181_o, n5130_o, n4909_o, n4870_o, n4668_o, n4617_o}; + /* T80_MCode.vhd:1359:25 */ + always @* + case (n5454_o) + 8'b10000000: n5460_o = 3'b011; + 8'b01000000: n5460_o = n5224_o; + 8'b00100000: n5460_o = 3'b011; + 8'b00010000: n5460_o = n4952_o; + 8'b00001000: n5460_o = 3'b010; + 8'b00000100: n5460_o = n4695_o; + 8'b00000010: n5460_o = 3'b011; + 8'b00000001: n5460_o = n4439_o; + default: n5460_o = 3'bX; + endcase + /* T80_MCode.vhd:1359:25 */ + always @* + case (n5454_o) + 8'b10000000: n5462_o = n5415_o; + 8'b01000000: n5462_o = n5225_o; + 8'b00100000: n5462_o = n5143_o; + 8'b00010000: n5462_o = n4953_o; + 8'b00001000: n5462_o = n4881_o; + 8'b00000100: n5462_o = n4696_o; + 8'b00000010: n5462_o = n4630_o; + 8'b00000001: n5462_o = n4440_o; + default: n5462_o = 3'bX; + endcase + /* T80_MCode.vhd:1359:25 */ + always @* + case (n5454_o) + 8'b10000000: n5465_o = n5418_o; + 8'b01000000: n5465_o = n5226_o; + 8'b00100000: n5465_o = n5146_o; + 8'b00010000: n5465_o = n4954_o; + 8'b00001000: n5465_o = 1'b0; + 8'b00000100: n5465_o = 1'b0; + 8'b00000010: n5465_o = n4633_o; + 8'b00000001: n5465_o = n4441_o; + default: n5465_o = 1'bX; + endcase + /* T80_MCode.vhd:1359:25 */ + always @* + case (n5454_o) + 8'b10000000: n5467_o = n4396_o; + 8'b01000000: n5467_o = n4396_o; + 8'b00100000: n5467_o = n4396_o; + 8'b00010000: n5467_o = n4396_o; + 8'b00001000: n5467_o = n4396_o; + 8'b00000100: n5467_o = n4674_o; + 8'b00000010: n5467_o = n4396_o; + 8'b00000001: n5467_o = n4396_o; + default: n5467_o = 3'bX; + endcase + /* T80_MCode.vhd:1359:25 */ + always @* + case (n5454_o) + 8'b10000000: n5469_o = n5420_o; + 8'b01000000: n5469_o = n5227_o; + 8'b00100000: n5469_o = n5148_o; + 8'b00010000: n5469_o = n4955_o; + 8'b00001000: n5469_o = n4883_o; + 8'b00000100: n5469_o = n4698_o; + 8'b00000010: n5469_o = n4635_o; + 8'b00000001: n5469_o = n4442_o; + default: n5469_o = 4'bX; + endcase + /* T80_MCode.vhd:1359:25 */ + always @* + case (n5454_o) + 8'b10000000: n5472_o = n5423_o; + 8'b01000000: n5472_o = n5228_o; + 8'b00100000: n5472_o = n5151_o; + 8'b00010000: n5472_o = n4956_o; + 8'b00001000: n5472_o = 1'b0; + 8'b00000100: n5472_o = 1'b0; + 8'b00000010: n5472_o = n4638_o; + 8'b00000001: n5472_o = n4443_o; + default: n5472_o = 1'bX; + endcase + /* T80_MCode.vhd:1359:25 */ + always @* + case (n5454_o) + 8'b10000000: n5474_o = n5427_o; + 8'b01000000: n5474_o = n5230_o; + 8'b00100000: n5474_o = n5155_o; + 8'b00010000: n5474_o = n4958_o; + 8'b00001000: n5474_o = n4886_o; + 8'b00000100: n5474_o = n4700_o; + 8'b00000010: n5474_o = n4642_o; + 8'b00000001: n5474_o = n4445_o; + default: n5474_o = 3'bX; + endcase + /* T80_MCode.vhd:1359:25 */ + always @* + case (n5454_o) + 8'b10000000: n5477_o = n5430_o; + 8'b01000000: n5477_o = n5232_o; + 8'b00100000: n5477_o = n5158_o; + 8'b00010000: n5477_o = n4960_o; + 8'b00001000: n5477_o = 1'b0; + 8'b00000100: n5477_o = 1'b0; + 8'b00000010: n5477_o = n4645_o; + 8'b00000001: n5477_o = n4447_o; + default: n5477_o = 1'bX; + endcase + /* T80_MCode.vhd:1359:25 */ + always @* + case (n5454_o) + 8'b10000000: n5480_o = 1'b0; + 8'b01000000: n5480_o = n5235_o; + 8'b00100000: n5480_o = 1'b0; + 8'b00010000: n5480_o = n4963_o; + 8'b00001000: n5480_o = 1'b0; + 8'b00000100: n5480_o = n4703_o; + 8'b00000010: n5480_o = 1'b0; + 8'b00000001: n5480_o = n4450_o; + default: n5480_o = 1'bX; + endcase + /* T80_MCode.vhd:1348:17 */ + assign n5482_o = iset == 2'b01; + /* T80_MCode.vhd:1574:25 */ + assign n5484_o = ir == 8'b00000000; + /* T80_MCode.vhd:1574:40 */ + assign n5486_o = ir == 8'b00000001; + /* T80_MCode.vhd:1574:40 */ + assign n5487_o = n5484_o | n5486_o; + /* T80_MCode.vhd:1574:51 */ + assign n5489_o = ir == 8'b00000010; + /* T80_MCode.vhd:1574:51 */ + assign n5490_o = n5487_o | n5489_o; + /* T80_MCode.vhd:1574:62 */ + assign n5492_o = ir == 8'b00000011; + /* T80_MCode.vhd:1574:62 */ + assign n5493_o = n5490_o | n5492_o; + /* T80_MCode.vhd:1574:73 */ + assign n5495_o = ir == 8'b00000100; + /* T80_MCode.vhd:1574:73 */ + assign n5496_o = n5493_o | n5495_o; + /* T80_MCode.vhd:1574:84 */ + assign n5498_o = ir == 8'b00000101; + /* T80_MCode.vhd:1574:84 */ + assign n5499_o = n5496_o | n5498_o; + /* T80_MCode.vhd:1574:95 */ + assign n5501_o = ir == 8'b00000110; + /* T80_MCode.vhd:1574:95 */ + assign n5502_o = n5499_o | n5501_o; + /* T80_MCode.vhd:1574:106 */ + assign n5504_o = ir == 8'b00000111; + /* T80_MCode.vhd:1574:106 */ + assign n5505_o = n5502_o | n5504_o; + /* T80_MCode.vhd:1575:33 */ + assign n5507_o = ir == 8'b00001000; + /* T80_MCode.vhd:1575:33 */ + assign n5508_o = n5505_o | n5507_o; + /* T80_MCode.vhd:1575:44 */ + assign n5510_o = ir == 8'b00001001; + /* T80_MCode.vhd:1575:44 */ + assign n5511_o = n5508_o | n5510_o; + /* T80_MCode.vhd:1575:55 */ + assign n5513_o = ir == 8'b00001010; + /* T80_MCode.vhd:1575:55 */ + assign n5514_o = n5511_o | n5513_o; + /* T80_MCode.vhd:1575:66 */ + assign n5516_o = ir == 8'b00001011; + /* T80_MCode.vhd:1575:66 */ + assign n5517_o = n5514_o | n5516_o; + /* T80_MCode.vhd:1575:77 */ + assign n5519_o = ir == 8'b00001100; + /* T80_MCode.vhd:1575:77 */ + assign n5520_o = n5517_o | n5519_o; + /* T80_MCode.vhd:1575:88 */ + assign n5522_o = ir == 8'b00001101; + /* T80_MCode.vhd:1575:88 */ + assign n5523_o = n5520_o | n5522_o; + /* T80_MCode.vhd:1575:99 */ + assign n5525_o = ir == 8'b00001110; + /* T80_MCode.vhd:1575:99 */ + assign n5526_o = n5523_o | n5525_o; + /* T80_MCode.vhd:1575:110 */ + assign n5528_o = ir == 8'b00001111; + /* T80_MCode.vhd:1575:110 */ + assign n5529_o = n5526_o | n5528_o; + /* T80_MCode.vhd:1576:33 */ + assign n5531_o = ir == 8'b00010000; + /* T80_MCode.vhd:1576:33 */ + assign n5532_o = n5529_o | n5531_o; + /* T80_MCode.vhd:1576:44 */ + assign n5534_o = ir == 8'b00010001; + /* T80_MCode.vhd:1576:44 */ + assign n5535_o = n5532_o | n5534_o; + /* T80_MCode.vhd:1576:55 */ + assign n5537_o = ir == 8'b00010010; + /* T80_MCode.vhd:1576:55 */ + assign n5538_o = n5535_o | n5537_o; + /* T80_MCode.vhd:1576:66 */ + assign n5540_o = ir == 8'b00010011; + /* T80_MCode.vhd:1576:66 */ + assign n5541_o = n5538_o | n5540_o; + /* T80_MCode.vhd:1576:77 */ + assign n5543_o = ir == 8'b00010100; + /* T80_MCode.vhd:1576:77 */ + assign n5544_o = n5541_o | n5543_o; + /* T80_MCode.vhd:1576:88 */ + assign n5546_o = ir == 8'b00010101; + /* T80_MCode.vhd:1576:88 */ + assign n5547_o = n5544_o | n5546_o; + /* T80_MCode.vhd:1576:99 */ + assign n5549_o = ir == 8'b00010110; + /* T80_MCode.vhd:1576:99 */ + assign n5550_o = n5547_o | n5549_o; + /* T80_MCode.vhd:1576:110 */ + assign n5552_o = ir == 8'b00010111; + /* T80_MCode.vhd:1576:110 */ + assign n5553_o = n5550_o | n5552_o; + /* T80_MCode.vhd:1577:33 */ + assign n5555_o = ir == 8'b00011000; + /* T80_MCode.vhd:1577:33 */ + assign n5556_o = n5553_o | n5555_o; + /* T80_MCode.vhd:1577:44 */ + assign n5558_o = ir == 8'b00011001; + /* T80_MCode.vhd:1577:44 */ + assign n5559_o = n5556_o | n5558_o; + /* T80_MCode.vhd:1577:55 */ + assign n5561_o = ir == 8'b00011010; + /* T80_MCode.vhd:1577:55 */ + assign n5562_o = n5559_o | n5561_o; + /* T80_MCode.vhd:1577:66 */ + assign n5564_o = ir == 8'b00011011; + /* T80_MCode.vhd:1577:66 */ + assign n5565_o = n5562_o | n5564_o; + /* T80_MCode.vhd:1577:77 */ + assign n5567_o = ir == 8'b00011100; + /* T80_MCode.vhd:1577:77 */ + assign n5568_o = n5565_o | n5567_o; + /* T80_MCode.vhd:1577:88 */ + assign n5570_o = ir == 8'b00011101; + /* T80_MCode.vhd:1577:88 */ + assign n5571_o = n5568_o | n5570_o; + /* T80_MCode.vhd:1577:99 */ + assign n5573_o = ir == 8'b00011110; + /* T80_MCode.vhd:1577:99 */ + assign n5574_o = n5571_o | n5573_o; + /* T80_MCode.vhd:1577:110 */ + assign n5576_o = ir == 8'b00011111; + /* T80_MCode.vhd:1577:110 */ + assign n5577_o = n5574_o | n5576_o; + /* T80_MCode.vhd:1578:33 */ + assign n5579_o = ir == 8'b00100000; + /* T80_MCode.vhd:1578:33 */ + assign n5580_o = n5577_o | n5579_o; + /* T80_MCode.vhd:1578:44 */ + assign n5582_o = ir == 8'b00100001; + /* T80_MCode.vhd:1578:44 */ + assign n5583_o = n5580_o | n5582_o; + /* T80_MCode.vhd:1578:55 */ + assign n5585_o = ir == 8'b00100010; + /* T80_MCode.vhd:1578:55 */ + assign n5586_o = n5583_o | n5585_o; + /* T80_MCode.vhd:1578:66 */ + assign n5588_o = ir == 8'b00100011; + /* T80_MCode.vhd:1578:66 */ + assign n5589_o = n5586_o | n5588_o; + /* T80_MCode.vhd:1578:77 */ + assign n5591_o = ir == 8'b00100100; + /* T80_MCode.vhd:1578:77 */ + assign n5592_o = n5589_o | n5591_o; + /* T80_MCode.vhd:1578:88 */ + assign n5594_o = ir == 8'b00100101; + /* T80_MCode.vhd:1578:88 */ + assign n5595_o = n5592_o | n5594_o; + /* T80_MCode.vhd:1578:99 */ + assign n5597_o = ir == 8'b00100110; + /* T80_MCode.vhd:1578:99 */ + assign n5598_o = n5595_o | n5597_o; + /* T80_MCode.vhd:1578:110 */ + assign n5600_o = ir == 8'b00100111; + /* T80_MCode.vhd:1578:110 */ + assign n5601_o = n5598_o | n5600_o; + /* T80_MCode.vhd:1579:33 */ + assign n5603_o = ir == 8'b00101000; + /* T80_MCode.vhd:1579:33 */ + assign n5604_o = n5601_o | n5603_o; + /* T80_MCode.vhd:1579:44 */ + assign n5606_o = ir == 8'b00101001; + /* T80_MCode.vhd:1579:44 */ + assign n5607_o = n5604_o | n5606_o; + /* T80_MCode.vhd:1579:55 */ + assign n5609_o = ir == 8'b00101010; + /* T80_MCode.vhd:1579:55 */ + assign n5610_o = n5607_o | n5609_o; + /* T80_MCode.vhd:1579:66 */ + assign n5612_o = ir == 8'b00101011; + /* T80_MCode.vhd:1579:66 */ + assign n5613_o = n5610_o | n5612_o; + /* T80_MCode.vhd:1579:77 */ + assign n5615_o = ir == 8'b00101100; + /* T80_MCode.vhd:1579:77 */ + assign n5616_o = n5613_o | n5615_o; + /* T80_MCode.vhd:1579:88 */ + assign n5618_o = ir == 8'b00101101; + /* T80_MCode.vhd:1579:88 */ + assign n5619_o = n5616_o | n5618_o; + /* T80_MCode.vhd:1579:99 */ + assign n5621_o = ir == 8'b00101110; + /* T80_MCode.vhd:1579:99 */ + assign n5622_o = n5619_o | n5621_o; + /* T80_MCode.vhd:1579:110 */ + assign n5624_o = ir == 8'b00101111; + /* T80_MCode.vhd:1579:110 */ + assign n5625_o = n5622_o | n5624_o; + /* T80_MCode.vhd:1580:33 */ + assign n5627_o = ir == 8'b00110000; + /* T80_MCode.vhd:1580:33 */ + assign n5628_o = n5625_o | n5627_o; + /* T80_MCode.vhd:1580:44 */ + assign n5630_o = ir == 8'b00110001; + /* T80_MCode.vhd:1580:44 */ + assign n5631_o = n5628_o | n5630_o; + /* T80_MCode.vhd:1580:55 */ + assign n5633_o = ir == 8'b00110010; + /* T80_MCode.vhd:1580:55 */ + assign n5634_o = n5631_o | n5633_o; + /* T80_MCode.vhd:1580:66 */ + assign n5636_o = ir == 8'b00110011; + /* T80_MCode.vhd:1580:66 */ + assign n5637_o = n5634_o | n5636_o; + /* T80_MCode.vhd:1580:77 */ + assign n5639_o = ir == 8'b00110100; + /* T80_MCode.vhd:1580:77 */ + assign n5640_o = n5637_o | n5639_o; + /* T80_MCode.vhd:1580:88 */ + assign n5642_o = ir == 8'b00110101; + /* T80_MCode.vhd:1580:88 */ + assign n5643_o = n5640_o | n5642_o; + /* T80_MCode.vhd:1580:99 */ + assign n5645_o = ir == 8'b00110110; + /* T80_MCode.vhd:1580:99 */ + assign n5646_o = n5643_o | n5645_o; + /* T80_MCode.vhd:1580:110 */ + assign n5648_o = ir == 8'b00110111; + /* T80_MCode.vhd:1580:110 */ + assign n5649_o = n5646_o | n5648_o; + /* T80_MCode.vhd:1581:33 */ + assign n5651_o = ir == 8'b00111000; + /* T80_MCode.vhd:1581:33 */ + assign n5652_o = n5649_o | n5651_o; + /* T80_MCode.vhd:1581:44 */ + assign n5654_o = ir == 8'b00111001; + /* T80_MCode.vhd:1581:44 */ + assign n5655_o = n5652_o | n5654_o; + /* T80_MCode.vhd:1581:55 */ + assign n5657_o = ir == 8'b00111010; + /* T80_MCode.vhd:1581:55 */ + assign n5658_o = n5655_o | n5657_o; + /* T80_MCode.vhd:1581:66 */ + assign n5660_o = ir == 8'b00111011; + /* T80_MCode.vhd:1581:66 */ + assign n5661_o = n5658_o | n5660_o; + /* T80_MCode.vhd:1581:77 */ + assign n5663_o = ir == 8'b00111100; + /* T80_MCode.vhd:1581:77 */ + assign n5664_o = n5661_o | n5663_o; + /* T80_MCode.vhd:1581:88 */ + assign n5666_o = ir == 8'b00111101; + /* T80_MCode.vhd:1581:88 */ + assign n5667_o = n5664_o | n5666_o; + /* T80_MCode.vhd:1581:99 */ + assign n5669_o = ir == 8'b00111110; + /* T80_MCode.vhd:1581:99 */ + assign n5670_o = n5667_o | n5669_o; + /* T80_MCode.vhd:1581:110 */ + assign n5672_o = ir == 8'b00111111; + /* T80_MCode.vhd:1581:110 */ + assign n5673_o = n5670_o | n5672_o; + /* T80_MCode.vhd:1584:33 */ + assign n5675_o = ir == 8'b10000000; + /* T80_MCode.vhd:1584:33 */ + assign n5676_o = n5673_o | n5675_o; + /* T80_MCode.vhd:1584:44 */ + assign n5678_o = ir == 8'b10000001; + /* T80_MCode.vhd:1584:44 */ + assign n5679_o = n5676_o | n5678_o; + /* T80_MCode.vhd:1584:55 */ + assign n5681_o = ir == 8'b10000010; + /* T80_MCode.vhd:1584:55 */ + assign n5682_o = n5679_o | n5681_o; + /* T80_MCode.vhd:1584:66 */ + assign n5684_o = ir == 8'b10000011; + /* T80_MCode.vhd:1584:66 */ + assign n5685_o = n5682_o | n5684_o; + /* T80_MCode.vhd:1584:77 */ + assign n5687_o = ir == 8'b10000100; + /* T80_MCode.vhd:1584:77 */ + assign n5688_o = n5685_o | n5687_o; + /* T80_MCode.vhd:1584:88 */ + assign n5690_o = ir == 8'b10000101; + /* T80_MCode.vhd:1584:88 */ + assign n5691_o = n5688_o | n5690_o; + /* T80_MCode.vhd:1584:99 */ + assign n5693_o = ir == 8'b10000110; + /* T80_MCode.vhd:1584:99 */ + assign n5694_o = n5691_o | n5693_o; + /* T80_MCode.vhd:1584:110 */ + assign n5696_o = ir == 8'b10000111; + /* T80_MCode.vhd:1584:110 */ + assign n5697_o = n5694_o | n5696_o; + /* T80_MCode.vhd:1585:33 */ + assign n5699_o = ir == 8'b10001000; + /* T80_MCode.vhd:1585:33 */ + assign n5700_o = n5697_o | n5699_o; + /* T80_MCode.vhd:1585:44 */ + assign n5702_o = ir == 8'b10001001; + /* T80_MCode.vhd:1585:44 */ + assign n5703_o = n5700_o | n5702_o; + /* T80_MCode.vhd:1585:55 */ + assign n5705_o = ir == 8'b10001010; + /* T80_MCode.vhd:1585:55 */ + assign n5706_o = n5703_o | n5705_o; + /* T80_MCode.vhd:1585:66 */ + assign n5708_o = ir == 8'b10001011; + /* T80_MCode.vhd:1585:66 */ + assign n5709_o = n5706_o | n5708_o; + /* T80_MCode.vhd:1585:77 */ + assign n5711_o = ir == 8'b10001100; + /* T80_MCode.vhd:1585:77 */ + assign n5712_o = n5709_o | n5711_o; + /* T80_MCode.vhd:1585:88 */ + assign n5714_o = ir == 8'b10001101; + /* T80_MCode.vhd:1585:88 */ + assign n5715_o = n5712_o | n5714_o; + /* T80_MCode.vhd:1585:99 */ + assign n5717_o = ir == 8'b10001110; + /* T80_MCode.vhd:1585:99 */ + assign n5718_o = n5715_o | n5717_o; + /* T80_MCode.vhd:1585:110 */ + assign n5720_o = ir == 8'b10001111; + /* T80_MCode.vhd:1585:110 */ + assign n5721_o = n5718_o | n5720_o; + /* T80_MCode.vhd:1586:33 */ + assign n5723_o = ir == 8'b10010000; + /* T80_MCode.vhd:1586:33 */ + assign n5724_o = n5721_o | n5723_o; + /* T80_MCode.vhd:1586:44 */ + assign n5726_o = ir == 8'b10010001; + /* T80_MCode.vhd:1586:44 */ + assign n5727_o = n5724_o | n5726_o; + /* T80_MCode.vhd:1586:55 */ + assign n5729_o = ir == 8'b10010010; + /* T80_MCode.vhd:1586:55 */ + assign n5730_o = n5727_o | n5729_o; + /* T80_MCode.vhd:1586:66 */ + assign n5732_o = ir == 8'b10010011; + /* T80_MCode.vhd:1586:66 */ + assign n5733_o = n5730_o | n5732_o; + /* T80_MCode.vhd:1586:77 */ + assign n5735_o = ir == 8'b10010100; + /* T80_MCode.vhd:1586:77 */ + assign n5736_o = n5733_o | n5735_o; + /* T80_MCode.vhd:1586:88 */ + assign n5738_o = ir == 8'b10010101; + /* T80_MCode.vhd:1586:88 */ + assign n5739_o = n5736_o | n5738_o; + /* T80_MCode.vhd:1586:99 */ + assign n5741_o = ir == 8'b10010110; + /* T80_MCode.vhd:1586:99 */ + assign n5742_o = n5739_o | n5741_o; + /* T80_MCode.vhd:1586:110 */ + assign n5744_o = ir == 8'b10010111; + /* T80_MCode.vhd:1586:110 */ + assign n5745_o = n5742_o | n5744_o; + /* T80_MCode.vhd:1587:33 */ + assign n5747_o = ir == 8'b10011000; + /* T80_MCode.vhd:1587:33 */ + assign n5748_o = n5745_o | n5747_o; + /* T80_MCode.vhd:1587:44 */ + assign n5750_o = ir == 8'b10011001; + /* T80_MCode.vhd:1587:44 */ + assign n5751_o = n5748_o | n5750_o; + /* T80_MCode.vhd:1587:55 */ + assign n5753_o = ir == 8'b10011010; + /* T80_MCode.vhd:1587:55 */ + assign n5754_o = n5751_o | n5753_o; + /* T80_MCode.vhd:1587:66 */ + assign n5756_o = ir == 8'b10011011; + /* T80_MCode.vhd:1587:66 */ + assign n5757_o = n5754_o | n5756_o; + /* T80_MCode.vhd:1587:77 */ + assign n5759_o = ir == 8'b10011100; + /* T80_MCode.vhd:1587:77 */ + assign n5760_o = n5757_o | n5759_o; + /* T80_MCode.vhd:1587:88 */ + assign n5762_o = ir == 8'b10011101; + /* T80_MCode.vhd:1587:88 */ + assign n5763_o = n5760_o | n5762_o; + /* T80_MCode.vhd:1587:99 */ + assign n5765_o = ir == 8'b10011110; + /* T80_MCode.vhd:1587:99 */ + assign n5766_o = n5763_o | n5765_o; + /* T80_MCode.vhd:1587:110 */ + assign n5768_o = ir == 8'b10011111; + /* T80_MCode.vhd:1587:110 */ + assign n5769_o = n5766_o | n5768_o; + /* T80_MCode.vhd:1588:33 */ + assign n5771_o = ir == 8'b10100100; + /* T80_MCode.vhd:1588:33 */ + assign n5772_o = n5769_o | n5771_o; + /* T80_MCode.vhd:1588:88 */ + assign n5774_o = ir == 8'b10100101; + /* T80_MCode.vhd:1588:88 */ + assign n5775_o = n5772_o | n5774_o; + /* T80_MCode.vhd:1588:99 */ + assign n5777_o = ir == 8'b10100110; + /* T80_MCode.vhd:1588:99 */ + assign n5778_o = n5775_o | n5777_o; + /* T80_MCode.vhd:1588:110 */ + assign n5780_o = ir == 8'b10100111; + /* T80_MCode.vhd:1588:110 */ + assign n5781_o = n5778_o | n5780_o; + /* T80_MCode.vhd:1589:33 */ + assign n5783_o = ir == 8'b10101100; + /* T80_MCode.vhd:1589:33 */ + assign n5784_o = n5781_o | n5783_o; + /* T80_MCode.vhd:1589:88 */ + assign n5786_o = ir == 8'b10101101; + /* T80_MCode.vhd:1589:88 */ + assign n5787_o = n5784_o | n5786_o; + /* T80_MCode.vhd:1589:99 */ + assign n5789_o = ir == 8'b10101110; + /* T80_MCode.vhd:1589:99 */ + assign n5790_o = n5787_o | n5789_o; + /* T80_MCode.vhd:1589:110 */ + assign n5792_o = ir == 8'b10101111; + /* T80_MCode.vhd:1589:110 */ + assign n5793_o = n5790_o | n5792_o; + /* T80_MCode.vhd:1590:33 */ + assign n5795_o = ir == 8'b10110100; + /* T80_MCode.vhd:1590:33 */ + assign n5796_o = n5793_o | n5795_o; + /* T80_MCode.vhd:1590:88 */ + assign n5798_o = ir == 8'b10110101; + /* T80_MCode.vhd:1590:88 */ + assign n5799_o = n5796_o | n5798_o; + /* T80_MCode.vhd:1590:99 */ + assign n5801_o = ir == 8'b10110110; + /* T80_MCode.vhd:1590:99 */ + assign n5802_o = n5799_o | n5801_o; + /* T80_MCode.vhd:1590:110 */ + assign n5804_o = ir == 8'b10110111; + /* T80_MCode.vhd:1590:110 */ + assign n5805_o = n5802_o | n5804_o; + /* T80_MCode.vhd:1591:33 */ + assign n5807_o = ir == 8'b10111100; + /* T80_MCode.vhd:1591:33 */ + assign n5808_o = n5805_o | n5807_o; + /* T80_MCode.vhd:1591:88 */ + assign n5810_o = ir == 8'b10111101; + /* T80_MCode.vhd:1591:88 */ + assign n5811_o = n5808_o | n5810_o; + /* T80_MCode.vhd:1591:99 */ + assign n5813_o = ir == 8'b10111110; + /* T80_MCode.vhd:1591:99 */ + assign n5814_o = n5811_o | n5813_o; + /* T80_MCode.vhd:1591:110 */ + assign n5816_o = ir == 8'b10111111; + /* T80_MCode.vhd:1591:110 */ + assign n5817_o = n5814_o | n5816_o; + /* T80_MCode.vhd:1592:33 */ + assign n5819_o = ir == 8'b11000000; + /* T80_MCode.vhd:1592:33 */ + assign n5820_o = n5817_o | n5819_o; + /* T80_MCode.vhd:1592:44 */ + assign n5822_o = ir == 8'b11000001; + /* T80_MCode.vhd:1592:44 */ + assign n5823_o = n5820_o | n5822_o; + /* T80_MCode.vhd:1592:55 */ + assign n5825_o = ir == 8'b11000010; + /* T80_MCode.vhd:1592:55 */ + assign n5826_o = n5823_o | n5825_o; + /* T80_MCode.vhd:1592:66 */ + assign n5828_o = ir == 8'b11000011; + /* T80_MCode.vhd:1592:66 */ + assign n5829_o = n5826_o | n5828_o; + /* T80_MCode.vhd:1592:77 */ + assign n5831_o = ir == 8'b11000100; + /* T80_MCode.vhd:1592:77 */ + assign n5832_o = n5829_o | n5831_o; + /* T80_MCode.vhd:1592:88 */ + assign n5834_o = ir == 8'b11000101; + /* T80_MCode.vhd:1592:88 */ + assign n5835_o = n5832_o | n5834_o; + /* T80_MCode.vhd:1592:99 */ + assign n5837_o = ir == 8'b11000110; + /* T80_MCode.vhd:1592:99 */ + assign n5838_o = n5835_o | n5837_o; + /* T80_MCode.vhd:1592:110 */ + assign n5840_o = ir == 8'b11000111; + /* T80_MCode.vhd:1592:110 */ + assign n5841_o = n5838_o | n5840_o; + /* T80_MCode.vhd:1593:33 */ + assign n5843_o = ir == 8'b11001000; + /* T80_MCode.vhd:1593:33 */ + assign n5844_o = n5841_o | n5843_o; + /* T80_MCode.vhd:1593:44 */ + assign n5846_o = ir == 8'b11001001; + /* T80_MCode.vhd:1593:44 */ + assign n5847_o = n5844_o | n5846_o; + /* T80_MCode.vhd:1593:55 */ + assign n5849_o = ir == 8'b11001010; + /* T80_MCode.vhd:1593:55 */ + assign n5850_o = n5847_o | n5849_o; + /* T80_MCode.vhd:1593:66 */ + assign n5852_o = ir == 8'b11001011; + /* T80_MCode.vhd:1593:66 */ + assign n5853_o = n5850_o | n5852_o; + /* T80_MCode.vhd:1593:77 */ + assign n5855_o = ir == 8'b11001100; + /* T80_MCode.vhd:1593:77 */ + assign n5856_o = n5853_o | n5855_o; + /* T80_MCode.vhd:1593:88 */ + assign n5858_o = ir == 8'b11001101; + /* T80_MCode.vhd:1593:88 */ + assign n5859_o = n5856_o | n5858_o; + /* T80_MCode.vhd:1593:99 */ + assign n5861_o = ir == 8'b11001110; + /* T80_MCode.vhd:1593:99 */ + assign n5862_o = n5859_o | n5861_o; + /* T80_MCode.vhd:1593:110 */ + assign n5864_o = ir == 8'b11001111; + /* T80_MCode.vhd:1593:110 */ + assign n5865_o = n5862_o | n5864_o; + /* T80_MCode.vhd:1594:33 */ + assign n5867_o = ir == 8'b11010000; + /* T80_MCode.vhd:1594:33 */ + assign n5868_o = n5865_o | n5867_o; + /* T80_MCode.vhd:1594:44 */ + assign n5870_o = ir == 8'b11010001; + /* T80_MCode.vhd:1594:44 */ + assign n5871_o = n5868_o | n5870_o; + /* T80_MCode.vhd:1594:55 */ + assign n5873_o = ir == 8'b11010010; + /* T80_MCode.vhd:1594:55 */ + assign n5874_o = n5871_o | n5873_o; + /* T80_MCode.vhd:1594:66 */ + assign n5876_o = ir == 8'b11010011; + /* T80_MCode.vhd:1594:66 */ + assign n5877_o = n5874_o | n5876_o; + /* T80_MCode.vhd:1594:77 */ + assign n5879_o = ir == 8'b11010100; + /* T80_MCode.vhd:1594:77 */ + assign n5880_o = n5877_o | n5879_o; + /* T80_MCode.vhd:1594:88 */ + assign n5882_o = ir == 8'b11010101; + /* T80_MCode.vhd:1594:88 */ + assign n5883_o = n5880_o | n5882_o; + /* T80_MCode.vhd:1594:99 */ + assign n5885_o = ir == 8'b11010110; + /* T80_MCode.vhd:1594:99 */ + assign n5886_o = n5883_o | n5885_o; + /* T80_MCode.vhd:1594:110 */ + assign n5888_o = ir == 8'b11010111; + /* T80_MCode.vhd:1594:110 */ + assign n5889_o = n5886_o | n5888_o; + /* T80_MCode.vhd:1595:33 */ + assign n5891_o = ir == 8'b11011000; + /* T80_MCode.vhd:1595:33 */ + assign n5892_o = n5889_o | n5891_o; + /* T80_MCode.vhd:1595:44 */ + assign n5894_o = ir == 8'b11011001; + /* T80_MCode.vhd:1595:44 */ + assign n5895_o = n5892_o | n5894_o; + /* T80_MCode.vhd:1595:55 */ + assign n5897_o = ir == 8'b11011010; + /* T80_MCode.vhd:1595:55 */ + assign n5898_o = n5895_o | n5897_o; + /* T80_MCode.vhd:1595:66 */ + assign n5900_o = ir == 8'b11011011; + /* T80_MCode.vhd:1595:66 */ + assign n5901_o = n5898_o | n5900_o; + /* T80_MCode.vhd:1595:77 */ + assign n5903_o = ir == 8'b11011100; + /* T80_MCode.vhd:1595:77 */ + assign n5904_o = n5901_o | n5903_o; + /* T80_MCode.vhd:1595:88 */ + assign n5906_o = ir == 8'b11011101; + /* T80_MCode.vhd:1595:88 */ + assign n5907_o = n5904_o | n5906_o; + /* T80_MCode.vhd:1595:99 */ + assign n5909_o = ir == 8'b11011110; + /* T80_MCode.vhd:1595:99 */ + assign n5910_o = n5907_o | n5909_o; + /* T80_MCode.vhd:1595:110 */ + assign n5912_o = ir == 8'b11011111; + /* T80_MCode.vhd:1595:110 */ + assign n5913_o = n5910_o | n5912_o; + /* T80_MCode.vhd:1596:33 */ + assign n5915_o = ir == 8'b11100000; + /* T80_MCode.vhd:1596:33 */ + assign n5916_o = n5913_o | n5915_o; + /* T80_MCode.vhd:1596:44 */ + assign n5918_o = ir == 8'b11100001; + /* T80_MCode.vhd:1596:44 */ + assign n5919_o = n5916_o | n5918_o; + /* T80_MCode.vhd:1596:55 */ + assign n5921_o = ir == 8'b11100010; + /* T80_MCode.vhd:1596:55 */ + assign n5922_o = n5919_o | n5921_o; + /* T80_MCode.vhd:1596:66 */ + assign n5924_o = ir == 8'b11100011; + /* T80_MCode.vhd:1596:66 */ + assign n5925_o = n5922_o | n5924_o; + /* T80_MCode.vhd:1596:77 */ + assign n5927_o = ir == 8'b11100100; + /* T80_MCode.vhd:1596:77 */ + assign n5928_o = n5925_o | n5927_o; + /* T80_MCode.vhd:1596:88 */ + assign n5930_o = ir == 8'b11100101; + /* T80_MCode.vhd:1596:88 */ + assign n5931_o = n5928_o | n5930_o; + /* T80_MCode.vhd:1596:99 */ + assign n5933_o = ir == 8'b11100110; + /* T80_MCode.vhd:1596:99 */ + assign n5934_o = n5931_o | n5933_o; + /* T80_MCode.vhd:1596:110 */ + assign n5936_o = ir == 8'b11100111; + /* T80_MCode.vhd:1596:110 */ + assign n5937_o = n5934_o | n5936_o; + /* T80_MCode.vhd:1597:33 */ + assign n5939_o = ir == 8'b11101000; + /* T80_MCode.vhd:1597:33 */ + assign n5940_o = n5937_o | n5939_o; + /* T80_MCode.vhd:1597:44 */ + assign n5942_o = ir == 8'b11101001; + /* T80_MCode.vhd:1597:44 */ + assign n5943_o = n5940_o | n5942_o; + /* T80_MCode.vhd:1597:55 */ + assign n5945_o = ir == 8'b11101010; + /* T80_MCode.vhd:1597:55 */ + assign n5946_o = n5943_o | n5945_o; + /* T80_MCode.vhd:1597:66 */ + assign n5948_o = ir == 8'b11101011; + /* T80_MCode.vhd:1597:66 */ + assign n5949_o = n5946_o | n5948_o; + /* T80_MCode.vhd:1597:77 */ + assign n5951_o = ir == 8'b11101100; + /* T80_MCode.vhd:1597:77 */ + assign n5952_o = n5949_o | n5951_o; + /* T80_MCode.vhd:1597:88 */ + assign n5954_o = ir == 8'b11101101; + /* T80_MCode.vhd:1597:88 */ + assign n5955_o = n5952_o | n5954_o; + /* T80_MCode.vhd:1597:99 */ + assign n5957_o = ir == 8'b11101110; + /* T80_MCode.vhd:1597:99 */ + assign n5958_o = n5955_o | n5957_o; + /* T80_MCode.vhd:1597:110 */ + assign n5960_o = ir == 8'b11101111; + /* T80_MCode.vhd:1597:110 */ + assign n5961_o = n5958_o | n5960_o; + /* T80_MCode.vhd:1598:33 */ + assign n5963_o = ir == 8'b11110000; + /* T80_MCode.vhd:1598:33 */ + assign n5964_o = n5961_o | n5963_o; + /* T80_MCode.vhd:1598:44 */ + assign n5966_o = ir == 8'b11110001; + /* T80_MCode.vhd:1598:44 */ + assign n5967_o = n5964_o | n5966_o; + /* T80_MCode.vhd:1598:55 */ + assign n5969_o = ir == 8'b11110010; + /* T80_MCode.vhd:1598:55 */ + assign n5970_o = n5967_o | n5969_o; + /* T80_MCode.vhd:1598:66 */ + assign n5972_o = ir == 8'b11110011; + /* T80_MCode.vhd:1598:66 */ + assign n5973_o = n5970_o | n5972_o; + /* T80_MCode.vhd:1598:77 */ + assign n5975_o = ir == 8'b11110100; + /* T80_MCode.vhd:1598:77 */ + assign n5976_o = n5973_o | n5975_o; + /* T80_MCode.vhd:1598:88 */ + assign n5978_o = ir == 8'b11110101; + /* T80_MCode.vhd:1598:88 */ + assign n5979_o = n5976_o | n5978_o; + /* T80_MCode.vhd:1598:99 */ + assign n5981_o = ir == 8'b11110110; + /* T80_MCode.vhd:1598:99 */ + assign n5982_o = n5979_o | n5981_o; + /* T80_MCode.vhd:1598:110 */ + assign n5984_o = ir == 8'b11110111; + /* T80_MCode.vhd:1598:110 */ + assign n5985_o = n5982_o | n5984_o; + /* T80_MCode.vhd:1599:33 */ + assign n5987_o = ir == 8'b11111000; + /* T80_MCode.vhd:1599:33 */ + assign n5988_o = n5985_o | n5987_o; + /* T80_MCode.vhd:1599:44 */ + assign n5990_o = ir == 8'b11111001; + /* T80_MCode.vhd:1599:44 */ + assign n5991_o = n5988_o | n5990_o; + /* T80_MCode.vhd:1599:55 */ + assign n5993_o = ir == 8'b11111010; + /* T80_MCode.vhd:1599:55 */ + assign n5994_o = n5991_o | n5993_o; + /* T80_MCode.vhd:1599:66 */ + assign n5996_o = ir == 8'b11111011; + /* T80_MCode.vhd:1599:66 */ + assign n5997_o = n5994_o | n5996_o; + /* T80_MCode.vhd:1599:77 */ + assign n5999_o = ir == 8'b11111100; + /* T80_MCode.vhd:1599:77 */ + assign n6000_o = n5997_o | n5999_o; + /* T80_MCode.vhd:1599:88 */ + assign n6002_o = ir == 8'b11111101; + /* T80_MCode.vhd:1599:88 */ + assign n6003_o = n6000_o | n6002_o; + /* T80_MCode.vhd:1599:99 */ + assign n6005_o = ir == 8'b11111110; + /* T80_MCode.vhd:1599:99 */ + assign n6006_o = n6003_o | n6005_o; + /* T80_MCode.vhd:1599:110 */ + assign n6008_o = ir == 8'b11111111; + /* T80_MCode.vhd:1599:110 */ + assign n6009_o = n6006_o | n6008_o; + /* T80_MCode.vhd:1601:25 */ + assign n6011_o = ir == 8'b01111110; + /* T80_MCode.vhd:1601:40 */ + assign n6013_o = ir == 8'b01111111; + /* T80_MCode.vhd:1601:40 */ + assign n6014_o = n6011_o | n6013_o; + /* T80_MCode.vhd:1605:25 */ + assign n6016_o = ir == 8'b01010111; + /* T80_MCode.vhd:1609:25 */ + assign n6018_o = ir == 8'b01011111; + /* T80_MCode.vhd:1613:25 */ + assign n6020_o = ir == 8'b01000111; + /* T80_MCode.vhd:1617:25 */ + assign n6022_o = ir == 8'b01001111; + /* T80_MCode.vhd:1625:38 */ + assign n6023_o = {28'b0, mcycle}; // uext + /* T80_MCode.vhd:1626:33 */ + assign n6025_o = n6023_o == 31'b0000000000000000000000000000010; + /* T80_MCode.vhd:1629:33 */ + assign n6027_o = n6023_o == 31'b0000000000000000000000000000011; + /* T80_MCode.vhd:1635:46 */ + assign n6028_o = ir[5:4]; + /* T80_MCode.vhd:1635:59 */ + assign n6030_o = n6028_o == 2'b11; + /* T80_MCode.vhd:1638:78 */ + assign n6031_o = ir[5:4]; + assign n6033_o = {n6031_o, 1'b1}; + /* T80_MCode.vhd:1635:41 */ + assign n6035_o = n6030_o ? 3'b000 : n6033_o; + /* T80_MCode.vhd:1635:41 */ + assign n6038_o = n6030_o ? 1'b1 : 1'b0; + /* T80_MCode.vhd:1633:33 */ + assign n6040_o = n6023_o == 31'b0000000000000000000000000000100; + /* T80_MCode.vhd:1645:46 */ + assign n6041_o = ir[5:4]; + /* T80_MCode.vhd:1645:59 */ + assign n6043_o = n6041_o == 2'b11; + /* T80_MCode.vhd:1648:78 */ + assign n6044_o = ir[5:4]; + assign n6046_o = {n6044_o, 1'b0}; + /* T80_MCode.vhd:1645:41 */ + assign n6048_o = n6043_o ? 3'b001 : n6046_o; + /* T80_MCode.vhd:1645:41 */ + assign n6051_o = n6043_o ? 1'b1 : 1'b0; + /* T80_MCode.vhd:1643:33 */ + assign n6053_o = n6023_o == 31'b0000000000000000000000000000101; + assign n6054_o = {n6053_o, n6040_o, n6027_o, n6025_o}; + /* T80_MCode.vhd:1625:33 */ + always @* + case (n6054_o) + 4'b1000: n6058_o = 1'b0; + 4'b0100: n6058_o = 1'b0; + 4'b0010: n6058_o = 1'b1; + 4'b0001: n6058_o = 1'b1; + default: n6058_o = 1'b0; + endcase + /* T80_MCode.vhd:1625:33 */ + always @* + case (n6054_o) + 4'b1000: n6061_o = 1'b0; + 4'b0100: n6061_o = 1'b1; + 4'b0010: n6061_o = 1'b0; + 4'b0001: n6061_o = 1'b0; + default: n6061_o = 1'b0; + endcase + /* T80_MCode.vhd:1625:33 */ + always @* + case (n6054_o) + 4'b1000: n6065_o = 1'b1; + 4'b0100: n6065_o = 1'b1; + 4'b0010: n6065_o = 1'b0; + 4'b0001: n6065_o = 1'b0; + default: n6065_o = 1'b0; + endcase + /* T80_MCode.vhd:1625:33 */ + always @* + case (n6054_o) + 4'b1000: n6067_o = n6048_o; + 4'b0100: n6067_o = n6035_o; + 4'b0010: n6067_o = 3'b000; + 4'b0001: n6067_o = 3'b000; + default: n6067_o = 3'b000; + endcase + /* T80_MCode.vhd:1625:33 */ + always @* + case (n6054_o) + 4'b1000: n6069_o = n6051_o; + 4'b0100: n6069_o = n6038_o; + 4'b0010: n6069_o = 1'b0; + 4'b0001: n6069_o = 1'b0; + default: n6069_o = 1'b0; + endcase + /* T80_MCode.vhd:1625:33 */ + always @* + case (n6054_o) + 4'b1000: n6073_o = 3'b111; + 4'b0100: n6073_o = 3'b110; + 4'b0010: n6073_o = 3'b110; + 4'b0001: n6073_o = 3'b111; + default: n6073_o = 3'b111; + endcase + /* T80_MCode.vhd:1625:33 */ + always @* + case (n6054_o) + 4'b1000: n6076_o = 1'b0; + 4'b0100: n6076_o = 1'b0; + 4'b0010: n6076_o = 1'b0; + 4'b0001: n6076_o = 1'b1; + default: n6076_o = 1'b0; + endcase + /* T80_MCode.vhd:1625:33 */ + always @* + case (n6054_o) + 4'b1000: n6079_o = 1'b0; + 4'b0100: n6079_o = 1'b0; + 4'b0010: n6079_o = 1'b1; + 4'b0001: n6079_o = 1'b0; + default: n6079_o = 1'b0; + endcase + /* T80_MCode.vhd:1622:25 */ + assign n6081_o = ir == 8'b01001011; + /* T80_MCode.vhd:1622:40 */ + assign n6083_o = ir == 8'b01011011; + /* T80_MCode.vhd:1622:40 */ + assign n6084_o = n6081_o | n6083_o; + /* T80_MCode.vhd:1622:51 */ + assign n6086_o = ir == 8'b01101011; + /* T80_MCode.vhd:1622:51 */ + assign n6087_o = n6084_o | n6086_o; + /* T80_MCode.vhd:1622:62 */ + assign n6089_o = ir == 8'b01111011; + /* T80_MCode.vhd:1622:62 */ + assign n6090_o = n6087_o | n6089_o; + /* T80_MCode.vhd:1656:38 */ + assign n6091_o = {28'b0, mcycle}; // uext + /* T80_MCode.vhd:1657:33 */ + assign n6093_o = n6091_o == 31'b0000000000000000000000000000010; + /* T80_MCode.vhd:1664:46 */ + assign n6094_o = ir[5:4]; + /* T80_MCode.vhd:1664:59 */ + assign n6096_o = n6094_o == 2'b11; + /* T80_MCode.vhd:1667:78 */ + assign n6097_o = ir[5:4]; + assign n6100_o = {1'b0, n6097_o, 1'b1}; + /* T80_MCode.vhd:1664:41 */ + assign n6102_o = n6096_o ? 4'b1000 : n6100_o; + /* T80_MCode.vhd:1660:33 */ + assign n6104_o = n6091_o == 31'b0000000000000000000000000000011; + /* T80_MCode.vhd:1675:46 */ + assign n6105_o = ir[5:4]; + /* T80_MCode.vhd:1675:59 */ + assign n6107_o = n6105_o == 2'b11; + /* T80_MCode.vhd:1678:78 */ + assign n6108_o = ir[5:4]; + assign n6111_o = {1'b0, n6108_o, 1'b0}; + /* T80_MCode.vhd:1675:41 */ + assign n6113_o = n6107_o ? 4'b1001 : n6111_o; + /* T80_MCode.vhd:1671:33 */ + assign n6115_o = n6091_o == 31'b0000000000000000000000000000100; + /* T80_MCode.vhd:1682:33 */ + assign n6117_o = n6091_o == 31'b0000000000000000000000000000101; + assign n6118_o = {n6117_o, n6115_o, n6104_o, n6093_o}; + /* T80_MCode.vhd:1656:33 */ + always @* + case (n6118_o) + 4'b1000: n6122_o = 1'b0; + 4'b0100: n6122_o = 1'b0; + 4'b0010: n6122_o = 1'b1; + 4'b0001: n6122_o = 1'b1; + default: n6122_o = 1'b0; + endcase + /* T80_MCode.vhd:1656:33 */ + always @* + case (n6118_o) + 4'b1000: n6125_o = 1'b0; + 4'b0100: n6125_o = 1'b1; + 4'b0010: n6125_o = 1'b0; + 4'b0001: n6125_o = 1'b0; + default: n6125_o = 1'b0; + endcase + /* T80_MCode.vhd:1656:33 */ + always @* + case (n6118_o) + 4'b1000: n6127_o = 4'b0000; + 4'b0100: n6127_o = n6113_o; + 4'b0010: n6127_o = n6102_o; + 4'b0001: n6127_o = 4'b0000; + default: n6127_o = 4'b0000; + endcase + /* T80_MCode.vhd:1656:33 */ + always @* + case (n6118_o) + 4'b1000: n6131_o = 3'b111; + 4'b0100: n6131_o = 3'b110; + 4'b0010: n6131_o = 3'b110; + 4'b0001: n6131_o = 3'b111; + default: n6131_o = 3'b111; + endcase + /* T80_MCode.vhd:1656:33 */ + always @* + case (n6118_o) + 4'b1000: n6134_o = 1'b0; + 4'b0100: n6134_o = 1'b0; + 4'b0010: n6134_o = 1'b0; + 4'b0001: n6134_o = 1'b1; + default: n6134_o = 1'b0; + endcase + /* T80_MCode.vhd:1656:33 */ + always @* + case (n6118_o) + 4'b1000: n6137_o = 1'b0; + 4'b0100: n6137_o = 1'b0; + 4'b0010: n6137_o = 1'b1; + 4'b0001: n6137_o = 1'b0; + default: n6137_o = 1'b0; + endcase + /* T80_MCode.vhd:1656:33 */ + always @* + case (n6118_o) + 4'b1000: n6141_o = 1'b1; + 4'b0100: n6141_o = 1'b1; + 4'b0010: n6141_o = 1'b0; + 4'b0001: n6141_o = 1'b0; + default: n6141_o = 1'b0; + endcase + /* T80_MCode.vhd:1653:25 */ + assign n6143_o = ir == 8'b01000011; + /* T80_MCode.vhd:1653:40 */ + assign n6145_o = ir == 8'b01010011; + /* T80_MCode.vhd:1653:40 */ + assign n6146_o = n6143_o | n6145_o; + /* T80_MCode.vhd:1653:51 */ + assign n6148_o = ir == 8'b01100011; + /* T80_MCode.vhd:1653:51 */ + assign n6149_o = n6146_o | n6148_o; + /* T80_MCode.vhd:1653:62 */ + assign n6151_o = ir == 8'b01110011; + /* T80_MCode.vhd:1653:62 */ + assign n6152_o = n6149_o | n6151_o; + /* T80_MCode.vhd:1689:38 */ + assign n6153_o = {28'b0, mcycle}; // uext + /* T80_MCode.vhd:1690:33 */ + assign n6155_o = n6153_o == 31'b0000000000000000000000000000001; + /* T80_MCode.vhd:1698:46 */ + assign n6157_o = ir[3]; + /* T80_MCode.vhd:1698:50 */ + assign n6158_o = ~n6157_o; + /* T80_MCode.vhd:1698:41 */ + assign n6161_o = n6158_o ? 4'b0110 : 4'b1110; + /* T80_MCode.vhd:1693:33 */ + assign n6163_o = n6153_o == 31'b0000000000000000000000000000010; + /* T80_MCode.vhd:1707:46 */ + assign n6164_o = ir[3]; + /* T80_MCode.vhd:1707:50 */ + assign n6165_o = ~n6164_o; + /* T80_MCode.vhd:1707:41 */ + assign n6168_o = n6165_o ? 4'b0101 : 4'b1101; + /* T80_MCode.vhd:1703:33 */ + assign n6170_o = n6153_o == 31'b0000000000000000000000000000011; + /* T80_MCode.vhd:1712:33 */ + assign n6172_o = n6153_o == 31'b0000000000000000000000000000100; + assign n6173_o = {n6172_o, n6170_o, n6163_o, n6155_o}; + /* T80_MCode.vhd:1689:33 */ + always @* + case (n6173_o) + 4'b1000: n6176_o = 3'b101; + 4'b0100: n6176_o = 3'b101; + 4'b0010: n6176_o = n2200_o; + 4'b0001: n6176_o = n2200_o; + default: n6176_o = n2200_o; + endcase + /* T80_MCode.vhd:1689:33 */ + always @* + case (n6173_o) + 4'b1000: n6179_o = 4'b0000; + 4'b0100: n6179_o = n6168_o; + 4'b0010: n6179_o = n6161_o; + 4'b0001: n6179_o = 4'b1100; + default: n6179_o = 4'b0000; + endcase + /* T80_MCode.vhd:1689:33 */ + always @* + case (n6173_o) + 4'b1000: n6181_o = 3'b000; + 4'b0100: n6181_o = 3'b000; + 4'b0010: n6181_o = 3'b111; + 4'b0001: n6181_o = 3'b000; + default: n6181_o = 3'b000; + endcase + /* T80_MCode.vhd:1689:33 */ + always @* + case (n6173_o) + 4'b1000: n6184_o = 4'b0000; + 4'b0100: n6184_o = 4'b0000; + 4'b0010: n6184_o = 4'b0110; + 4'b0001: n6184_o = 4'b0000; + default: n6184_o = 4'b0000; + endcase + /* T80_MCode.vhd:1689:33 */ + always @* + case (n6173_o) + 4'b1000: n6186_o = n2203_o; + 4'b0100: n6186_o = n2203_o; + 4'b0010: n6186_o = 4'b0000; + 4'b0001: n6186_o = n2203_o; + default: n6186_o = n2203_o; + endcase + /* T80_MCode.vhd:1689:33 */ + always @* + case (n6173_o) + 4'b1000: n6190_o = 3'b111; + 4'b0100: n6190_o = 3'b111; + 4'b0010: n6190_o = 3'b001; + 4'b0001: n6190_o = 3'b010; + default: n6190_o = 3'b111; + endcase + /* T80_MCode.vhd:1689:33 */ + always @* + case (n6173_o) + 4'b1000: n6193_o = 1'b0; + 4'b0100: n6193_o = 1'b1; + 4'b0010: n6193_o = 1'b0; + 4'b0001: n6193_o = 1'b0; + default: n6193_o = 1'b0; + endcase + /* T80_MCode.vhd:1689:33 */ + always @* + case (n6173_o) + 4'b1000: n6196_o = 1'b1; + 4'b0100: n6196_o = 1'b0; + 4'b0010: n6196_o = 1'b0; + 4'b0001: n6196_o = 1'b0; + default: n6196_o = 1'b0; + endcase + /* T80_MCode.vhd:1689:33 */ + always @* + case (n6173_o) + 4'b1000: n6199_o = 1'b0; + 4'b0100: n6199_o = 1'b1; + 4'b0010: n6199_o = 1'b0; + 4'b0001: n6199_o = 1'b0; + default: n6199_o = 1'b0; + endcase + /* T80_MCode.vhd:1686:25 */ + assign n6201_o = ir == 8'b10100000; + /* T80_MCode.vhd:1686:41 */ + assign n6203_o = ir == 8'b10101000; + /* T80_MCode.vhd:1686:41 */ + assign n6204_o = n6201_o | n6203_o; + /* T80_MCode.vhd:1686:54 */ + assign n6206_o = ir == 8'b10110000; + /* T80_MCode.vhd:1686:54 */ + assign n6207_o = n6204_o | n6206_o; + /* T80_MCode.vhd:1686:67 */ + assign n6209_o = ir == 8'b10111000; + /* T80_MCode.vhd:1686:67 */ + assign n6210_o = n6207_o | n6209_o; + /* T80_MCode.vhd:1720:38 */ + assign n6211_o = {28'b0, mcycle}; // uext + /* T80_MCode.vhd:1721:33 */ + assign n6213_o = n6211_o == 31'b0000000000000000000000000000001; + /* T80_MCode.vhd:1730:46 */ + assign n6215_o = ir[3]; + /* T80_MCode.vhd:1730:50 */ + assign n6216_o = ~n6215_o; + /* T80_MCode.vhd:1730:41 */ + assign n6219_o = n6216_o ? 4'b0110 : 4'b1110; + /* T80_MCode.vhd:1724:33 */ + assign n6221_o = n6211_o == 31'b0000000000000000000000000000010; + /* T80_MCode.vhd:1735:33 */ + assign n6223_o = n6211_o == 31'b0000000000000000000000000000011; + /* T80_MCode.vhd:1739:33 */ + assign n6225_o = n6211_o == 31'b0000000000000000000000000000100; + assign n6226_o = {n6225_o, n6223_o, n6221_o, n6213_o}; + /* T80_MCode.vhd:1720:33 */ + always @* + case (n6226_o) + 4'b1000: n6229_o = 3'b101; + 4'b0100: n6229_o = 3'b101; + 4'b0010: n6229_o = n2200_o; + 4'b0001: n6229_o = n2200_o; + default: n6229_o = n2200_o; + endcase + /* T80_MCode.vhd:1720:33 */ + always @* + case (n6226_o) + 4'b1000: n6232_o = 4'b0000; + 4'b0100: n6232_o = 4'b0000; + 4'b0010: n6232_o = n6219_o; + 4'b0001: n6232_o = 4'b1100; + default: n6232_o = 4'b0000; + endcase + /* T80_MCode.vhd:1720:33 */ + always @* + case (n6226_o) + 4'b1000: n6234_o = 3'b000; + 4'b0100: n6234_o = 3'b000; + 4'b0010: n6234_o = 3'b111; + 4'b0001: n6234_o = 3'b000; + default: n6234_o = 3'b000; + endcase + /* T80_MCode.vhd:1720:33 */ + always @* + case (n6226_o) + 4'b1000: n6237_o = 4'b0000; + 4'b0100: n6237_o = 4'b0000; + 4'b0010: n6237_o = 4'b0110; + 4'b0001: n6237_o = 4'b0000; + default: n6237_o = 4'b0000; + endcase + /* T80_MCode.vhd:1720:33 */ + always @* + case (n6226_o) + 4'b1000: n6239_o = n2203_o; + 4'b0100: n6239_o = n2203_o; + 4'b0010: n6239_o = 4'b0111; + 4'b0001: n6239_o = n2203_o; + default: n6239_o = n2203_o; + endcase + /* T80_MCode.vhd:1720:33 */ + always @* + case (n6226_o) + 4'b1000: n6242_o = 1'b0; + 4'b0100: n6242_o = 1'b0; + 4'b0010: n6242_o = 1'b1; + 4'b0001: n6242_o = 1'b0; + default: n6242_o = 1'b0; + endcase + /* T80_MCode.vhd:1720:33 */ + always @* + case (n6226_o) + 4'b1000: n6245_o = 1'b0; + 4'b0100: n6245_o = 1'b0; + 4'b0010: n6245_o = 1'b1; + 4'b0001: n6245_o = 1'b0; + default: n6245_o = 1'b0; + endcase + /* T80_MCode.vhd:1720:33 */ + always @* + case (n6226_o) + 4'b1000: n6248_o = 3'b111; + 4'b0100: n6248_o = 3'b111; + 4'b0010: n6248_o = 3'b111; + 4'b0001: n6248_o = 3'b010; + default: n6248_o = 3'b111; + endcase + /* T80_MCode.vhd:1720:33 */ + always @* + case (n6226_o) + 4'b1000: n6251_o = 1'b0; + 4'b0100: n6251_o = 1'b1; + 4'b0010: n6251_o = 1'b0; + 4'b0001: n6251_o = 1'b0; + default: n6251_o = 1'b0; + endcase + /* T80_MCode.vhd:1720:33 */ + always @* + case (n6226_o) + 4'b1000: n6255_o = 1'b1; + 4'b0100: n6255_o = 1'b1; + 4'b0010: n6255_o = 1'b0; + 4'b0001: n6255_o = 1'b0; + default: n6255_o = 1'b0; + endcase + /* T80_MCode.vhd:1717:25 */ + assign n6257_o = ir == 8'b10100001; + /* T80_MCode.vhd:1717:41 */ + assign n6259_o = ir == 8'b10101001; + /* T80_MCode.vhd:1717:41 */ + assign n6260_o = n6257_o | n6259_o; + /* T80_MCode.vhd:1717:54 */ + assign n6262_o = ir == 8'b10110001; + /* T80_MCode.vhd:1717:54 */ + assign n6263_o = n6260_o | n6262_o; + /* T80_MCode.vhd:1717:67 */ + assign n6265_o = ir == 8'b10111001; + /* T80_MCode.vhd:1717:67 */ + assign n6266_o = n6263_o | n6265_o; + /* T80_MCode.vhd:1744:25 */ + assign n6268_o = ir == 8'b01000100; + /* T80_MCode.vhd:1744:40 */ + assign n6270_o = ir == 8'b01001100; + /* T80_MCode.vhd:1744:40 */ + assign n6271_o = n6268_o | n6270_o; + /* T80_MCode.vhd:1744:51 */ + assign n6273_o = ir == 8'b01010100; + /* T80_MCode.vhd:1744:51 */ + assign n6274_o = n6271_o | n6273_o; + /* T80_MCode.vhd:1744:62 */ + assign n6276_o = ir == 8'b01011100; + /* T80_MCode.vhd:1744:62 */ + assign n6277_o = n6274_o | n6276_o; + /* T80_MCode.vhd:1744:73 */ + assign n6279_o = ir == 8'b01100100; + /* T80_MCode.vhd:1744:73 */ + assign n6280_o = n6277_o | n6279_o; + /* T80_MCode.vhd:1744:84 */ + assign n6282_o = ir == 8'b01101100; + /* T80_MCode.vhd:1744:84 */ + assign n6283_o = n6280_o | n6282_o; + /* T80_MCode.vhd:1744:95 */ + assign n6285_o = ir == 8'b01110100; + /* T80_MCode.vhd:1744:95 */ + assign n6286_o = n6283_o | n6285_o; + /* T80_MCode.vhd:1744:106 */ + assign n6288_o = ir == 8'b01111100; + /* T80_MCode.vhd:1744:106 */ + assign n6289_o = n6286_o | n6288_o; + /* T80_MCode.vhd:1751:25 */ + assign n6291_o = ir == 8'b01000110; + /* T80_MCode.vhd:1751:40 */ + assign n6293_o = ir == 8'b01001110; + /* T80_MCode.vhd:1751:40 */ + assign n6294_o = n6291_o | n6293_o; + /* T80_MCode.vhd:1751:51 */ + assign n6296_o = ir == 8'b01100110; + /* T80_MCode.vhd:1751:51 */ + assign n6297_o = n6294_o | n6296_o; + /* T80_MCode.vhd:1751:62 */ + assign n6299_o = ir == 8'b01101110; + /* T80_MCode.vhd:1751:62 */ + assign n6300_o = n6297_o | n6299_o; + /* T80_MCode.vhd:1754:25 */ + assign n6302_o = ir == 8'b01010110; + /* T80_MCode.vhd:1754:40 */ + assign n6304_o = ir == 8'b01110110; + /* T80_MCode.vhd:1754:40 */ + assign n6305_o = n6302_o | n6304_o; + /* T80_MCode.vhd:1757:25 */ + assign n6307_o = ir == 8'b01011110; + /* T80_MCode.vhd:1757:40 */ + assign n6309_o = ir == 8'b01110111; + /* T80_MCode.vhd:1757:40 */ + assign n6310_o = n6307_o | n6309_o; + /* T80_MCode.vhd:1764:38 */ + assign n6311_o = {28'b0, mcycle}; // uext + /* T80_MCode.vhd:1771:68 */ + assign n6313_o = ir[5:4]; + /* T80_MCode.vhd:1771:46 */ + assign n6314_o = {29'b0, n6313_o}; // uext + /* T80_MCode.vhd:1773:78 */ + assign n6315_o = ir[5:4]; + /* T80_MCode.vhd:1772:41 */ + assign n6318_o = n6314_o == 31'b0000000000000000000000000000000; + /* T80_MCode.vhd:1772:47 */ + assign n6320_o = n6314_o == 31'b0000000000000000000000000000001; + /* T80_MCode.vhd:1772:47 */ + assign n6321_o = n6318_o | n6320_o; + /* T80_MCode.vhd:1772:49 */ + assign n6323_o = n6314_o == 31'b0000000000000000000000000000010; + /* T80_MCode.vhd:1772:49 */ + assign n6324_o = n6321_o | n6323_o; + /* T80_MCode.vhd:1771:41 */ + always @* + case (n6324_o) + 1'b1: n6326_o = 1'b1; + default: n6326_o = 1'b0; + endcase + /* T80_MCode.vhd:1771:41 */ + always @* + case (n6324_o) + 1'b1: n6328_o = n6315_o; + default: n6328_o = 2'b00; + endcase + /* T80_MCode.vhd:1771:41 */ + always @* + case (n6324_o) + 1'b1: n6331_o = 1'b0; + default: n6331_o = 1'b1; + endcase + /* T80_MCode.vhd:1765:33 */ + assign n6333_o = n6311_o == 31'b0000000000000000000000000000010; + /* T80_MCode.vhd:1786:68 */ + assign n6335_o = ir[5:4]; + /* T80_MCode.vhd:1786:46 */ + assign n6336_o = {29'b0, n6335_o}; // uext + /* T80_MCode.vhd:1788:78 */ + assign n6337_o = ir[5:4]; + /* T80_MCode.vhd:1787:41 */ + assign n6340_o = n6336_o == 31'b0000000000000000000000000000000; + /* T80_MCode.vhd:1787:47 */ + assign n6342_o = n6336_o == 31'b0000000000000000000000000000001; + /* T80_MCode.vhd:1787:47 */ + assign n6343_o = n6340_o | n6342_o; + /* T80_MCode.vhd:1787:49 */ + assign n6345_o = n6336_o == 31'b0000000000000000000000000000010; + /* T80_MCode.vhd:1787:49 */ + assign n6346_o = n6343_o | n6345_o; + /* T80_MCode.vhd:1786:41 */ + always @* + case (n6346_o) + 1'b1: n6348_o = 1'b0; + default: n6348_o = 1'b1; + endcase + /* T80_MCode.vhd:1786:41 */ + always @* + case (n6346_o) + 1'b1: n6350_o = n6337_o; + default: n6350_o = 2'b00; + endcase + /* T80_MCode.vhd:1786:41 */ + always @* + case (n6346_o) + 1'b1: n6353_o = 1'b0; + default: n6353_o = 1'b1; + endcase + /* T80_MCode.vhd:1780:33 */ + assign n6355_o = n6311_o == 31'b0000000000000000000000000000011; + assign n6356_o = {n6355_o, n6333_o}; + /* T80_MCode.vhd:1764:33 */ + always @* + case (n6356_o) + 2'b10: n6358_o = n2200_o; + 2'b01: n6358_o = 3'b100; + default: n6358_o = n2200_o; + endcase + /* T80_MCode.vhd:1764:33 */ + always @* + case (n6356_o) + 2'b10: n6362_o = 1'b1; + 2'b01: n6362_o = 1'b1; + default: n6362_o = 1'b0; + endcase + /* T80_MCode.vhd:1764:33 */ + always @* + case (n6356_o) + 2'b10: n6364_o = 3'b100; + 2'b01: n6364_o = 3'b101; + default: n6364_o = 3'b000; + endcase + /* T80_MCode.vhd:1764:33 */ + always @* + case (n6356_o) + 2'b10: n6366_o = n6348_o; + 2'b01: n6366_o = n6326_o; + default: n6366_o = 1'b0; + endcase + /* T80_MCode.vhd:1764:33 */ + always @* + case (n6356_o) + 2'b10: n6368_o = n6350_o; + 2'b01: n6368_o = n6328_o; + default: n6368_o = 2'b00; + endcase + /* T80_MCode.vhd:1764:33 */ + always @* + case (n6356_o) + 2'b10: n6370_o = n6353_o; + 2'b01: n6370_o = n6331_o; + default: n6370_o = 1'b0; + endcase + /* T80_MCode.vhd:1764:33 */ + always @* + case (n6356_o) + 2'b10: n6373_o = 4'b0001; + 2'b01: n6373_o = 4'b0001; + default: n6373_o = n2203_o; + endcase + /* T80_MCode.vhd:1764:33 */ + always @* + case (n6356_o) + 2'b10: n6377_o = 1'b1; + 2'b01: n6377_o = 1'b1; + default: n6377_o = 1'b0; + endcase + /* T80_MCode.vhd:1764:33 */ + always @* + case (n6356_o) + 2'b10: n6380_o = 2'b00; + 2'b01: n6380_o = 2'b11; + default: n6380_o = 2'b00; + endcase + /* T80_MCode.vhd:1764:33 */ + always @* + case (n6356_o) + 2'b10: n6384_o = 1'b1; + 2'b01: n6384_o = 1'b1; + default: n6384_o = 1'b0; + endcase + /* T80_MCode.vhd:1761:25 */ + assign n6386_o = ir == 8'b01001010; + /* T80_MCode.vhd:1761:40 */ + assign n6388_o = ir == 8'b01011010; + /* T80_MCode.vhd:1761:40 */ + assign n6389_o = n6386_o | n6388_o; + /* T80_MCode.vhd:1761:51 */ + assign n6391_o = ir == 8'b01101010; + /* T80_MCode.vhd:1761:51 */ + assign n6392_o = n6389_o | n6391_o; + /* T80_MCode.vhd:1761:62 */ + assign n6394_o = ir == 8'b01111010; + /* T80_MCode.vhd:1761:62 */ + assign n6395_o = n6392_o | n6394_o; + /* T80_MCode.vhd:1798:38 */ + assign n6396_o = {28'b0, mcycle}; // uext + /* T80_MCode.vhd:1805:68 */ + assign n6398_o = ir[5:4]; + /* T80_MCode.vhd:1805:46 */ + assign n6399_o = {29'b0, n6398_o}; // uext + /* T80_MCode.vhd:1807:78 */ + assign n6400_o = ir[5:4]; + /* T80_MCode.vhd:1806:41 */ + assign n6403_o = n6399_o == 31'b0000000000000000000000000000000; + /* T80_MCode.vhd:1806:47 */ + assign n6405_o = n6399_o == 31'b0000000000000000000000000000001; + /* T80_MCode.vhd:1806:47 */ + assign n6406_o = n6403_o | n6405_o; + /* T80_MCode.vhd:1806:49 */ + assign n6408_o = n6399_o == 31'b0000000000000000000000000000010; + /* T80_MCode.vhd:1806:49 */ + assign n6409_o = n6406_o | n6408_o; + /* T80_MCode.vhd:1805:41 */ + always @* + case (n6409_o) + 1'b1: n6411_o = 1'b1; + default: n6411_o = 1'b0; + endcase + /* T80_MCode.vhd:1805:41 */ + always @* + case (n6409_o) + 1'b1: n6413_o = n6400_o; + default: n6413_o = 2'b00; + endcase + /* T80_MCode.vhd:1805:41 */ + always @* + case (n6409_o) + 1'b1: n6416_o = 1'b0; + default: n6416_o = 1'b1; + endcase + /* T80_MCode.vhd:1799:33 */ + assign n6418_o = n6396_o == 31'b0000000000000000000000000000010; + /* T80_MCode.vhd:1820:68 */ + assign n6420_o = ir[5:4]; + /* T80_MCode.vhd:1820:46 */ + assign n6421_o = {29'b0, n6420_o}; // uext + /* T80_MCode.vhd:1822:78 */ + assign n6422_o = ir[5:4]; + /* T80_MCode.vhd:1821:41 */ + assign n6424_o = n6421_o == 31'b0000000000000000000000000000000; + /* T80_MCode.vhd:1821:47 */ + assign n6426_o = n6421_o == 31'b0000000000000000000000000000001; + /* T80_MCode.vhd:1821:47 */ + assign n6427_o = n6424_o | n6426_o; + /* T80_MCode.vhd:1821:49 */ + assign n6429_o = n6421_o == 31'b0000000000000000000000000000010; + /* T80_MCode.vhd:1821:49 */ + assign n6430_o = n6427_o | n6429_o; + /* T80_MCode.vhd:1820:41 */ + always @* + case (n6430_o) + 1'b1: n6433_o = 1'b0; + default: n6433_o = 1'b1; + endcase + /* T80_MCode.vhd:1820:41 */ + always @* + case (n6430_o) + 1'b1: n6435_o = n6422_o; + default: n6435_o = 2'b00; + endcase + /* T80_MCode.vhd:1820:41 */ + always @* + case (n6430_o) + 1'b1: n6438_o = 1'b0; + default: n6438_o = 1'b1; + endcase + /* T80_MCode.vhd:1814:33 */ + assign n6440_o = n6396_o == 31'b0000000000000000000000000000011; + assign n6441_o = {n6440_o, n6418_o}; + /* T80_MCode.vhd:1798:33 */ + always @* + case (n6441_o) + 2'b10: n6443_o = n2200_o; + 2'b01: n6443_o = 3'b100; + default: n6443_o = n2200_o; + endcase + /* T80_MCode.vhd:1798:33 */ + always @* + case (n6441_o) + 2'b10: n6447_o = 1'b1; + 2'b01: n6447_o = 1'b1; + default: n6447_o = 1'b0; + endcase + /* T80_MCode.vhd:1798:33 */ + always @* + case (n6441_o) + 2'b10: n6449_o = 3'b100; + 2'b01: n6449_o = 3'b101; + default: n6449_o = 3'b000; + endcase + /* T80_MCode.vhd:1798:33 */ + always @* + case (n6441_o) + 2'b10: n6451_o = n6433_o; + 2'b01: n6451_o = n6411_o; + default: n6451_o = 1'b0; + endcase + /* T80_MCode.vhd:1798:33 */ + always @* + case (n6441_o) + 2'b10: n6453_o = n6435_o; + 2'b01: n6453_o = n6413_o; + default: n6453_o = 2'b00; + endcase + /* T80_MCode.vhd:1798:33 */ + always @* + case (n6441_o) + 2'b10: n6455_o = n6438_o; + 2'b01: n6455_o = n6416_o; + default: n6455_o = 1'b0; + endcase + /* T80_MCode.vhd:1798:33 */ + always @* + case (n6441_o) + 2'b10: n6458_o = 4'b0011; + 2'b01: n6458_o = 4'b0011; + default: n6458_o = n2203_o; + endcase + /* T80_MCode.vhd:1798:33 */ + always @* + case (n6441_o) + 2'b10: n6462_o = 1'b1; + 2'b01: n6462_o = 1'b1; + default: n6462_o = 1'b0; + endcase + /* T80_MCode.vhd:1798:33 */ + always @* + case (n6441_o) + 2'b10: n6465_o = 2'b00; + 2'b01: n6465_o = 2'b11; + default: n6465_o = 2'b00; + endcase + /* T80_MCode.vhd:1798:33 */ + always @* + case (n6441_o) + 2'b10: n6469_o = 1'b1; + 2'b01: n6469_o = 1'b1; + default: n6469_o = 1'b0; + endcase + /* T80_MCode.vhd:1795:25 */ + assign n6471_o = ir == 8'b01000010; + /* T80_MCode.vhd:1795:40 */ + assign n6473_o = ir == 8'b01010010; + /* T80_MCode.vhd:1795:40 */ + assign n6474_o = n6471_o | n6473_o; + /* T80_MCode.vhd:1795:51 */ + assign n6476_o = ir == 8'b01100010; + /* T80_MCode.vhd:1795:51 */ + assign n6477_o = n6474_o | n6476_o; + /* T80_MCode.vhd:1795:62 */ + assign n6479_o = ir == 8'b01110010; + /* T80_MCode.vhd:1795:62 */ + assign n6480_o = n6477_o | n6479_o; + /* T80_MCode.vhd:1831:38 */ + assign n6481_o = {28'b0, mcycle}; // uext + /* T80_MCode.vhd:1832:33 */ + assign n6483_o = n6481_o == 31'b0000000000000000000000000000001; + /* T80_MCode.vhd:1834:33 */ + assign n6487_o = n6481_o == 31'b0000000000000000000000000000010; + /* T80_MCode.vhd:1840:33 */ + assign n6489_o = n6481_o == 31'b0000000000000000000000000000011; + /* T80_MCode.vhd:1845:33 */ + assign n6491_o = n6481_o == 31'b0000000000000000000000000000100; + assign n6492_o = {n6491_o, n6489_o, n6487_o, n6483_o}; + /* T80_MCode.vhd:1831:33 */ + always @* + case (n6492_o) + 4'b1000: n6494_o = n2200_o; + 4'b0100: n6494_o = 3'b100; + 4'b0010: n6494_o = n2200_o; + 4'b0001: n6494_o = n2200_o; + default: n6494_o = n2200_o; + endcase + /* T80_MCode.vhd:1831:33 */ + always @* + case (n6492_o) + 4'b1000: n6497_o = 1'b0; + 4'b0100: n6497_o = 1'b0; + 4'b0010: n6497_o = 1'b1; + 4'b0001: n6497_o = 1'b0; + default: n6497_o = 1'b0; + endcase + /* T80_MCode.vhd:1831:33 */ + always @* + case (n6492_o) + 4'b1000: n6499_o = 3'b000; + 4'b0100: n6499_o = 3'b000; + 4'b0010: n6499_o = 3'b111; + 4'b0001: n6499_o = 3'b000; + default: n6499_o = 3'b000; + endcase + /* T80_MCode.vhd:1831:33 */ + always @* + case (n6492_o) + 4'b1000: n6501_o = 3'b000; + 4'b0100: n6501_o = 3'b000; + 4'b0010: n6501_o = 3'b110; + 4'b0001: n6501_o = 3'b000; + default: n6501_o = 3'b000; + endcase + /* T80_MCode.vhd:1831:33 */ + always @* + case (n6492_o) + 4'b1000: n6503_o = n2203_o; + 4'b0100: n6503_o = n2203_o; + 4'b0010: n6503_o = 4'b1101; + 4'b0001: n6503_o = n2203_o; + default: n6503_o = n2203_o; + endcase + /* T80_MCode.vhd:1831:33 */ + always @* + case (n6492_o) + 4'b1000: n6506_o = 1'b0; + 4'b0100: n6506_o = 1'b0; + 4'b0010: n6506_o = 1'b1; + 4'b0001: n6506_o = 1'b0; + default: n6506_o = 1'b0; + endcase + /* T80_MCode.vhd:1831:33 */ + always @* + case (n6492_o) + 4'b1000: n6510_o = 3'b111; + 4'b0100: n6510_o = 3'b010; + 4'b0010: n6510_o = 3'b111; + 4'b0001: n6510_o = 3'b010; + default: n6510_o = 3'b111; + endcase + /* T80_MCode.vhd:1831:33 */ + always @* + case (n6492_o) + 4'b1000: n6513_o = 1'b0; + 4'b0100: n6513_o = 1'b1; + 4'b0010: n6513_o = 1'b0; + 4'b0001: n6513_o = 1'b0; + default: n6513_o = 1'b0; + endcase + /* T80_MCode.vhd:1831:33 */ + always @* + case (n6492_o) + 4'b1000: n6516_o = 1'b0; + 4'b0100: n6516_o = 1'b1; + 4'b0010: n6516_o = 1'b0; + 4'b0001: n6516_o = 1'b0; + default: n6516_o = 1'b0; + endcase + /* T80_MCode.vhd:1831:33 */ + always @* + case (n6492_o) + 4'b1000: n6519_o = 1'b1; + 4'b0100: n6519_o = 1'b0; + 4'b0010: n6519_o = 1'b0; + 4'b0001: n6519_o = 1'b0; + default: n6519_o = 1'b0; + endcase + /* T80_MCode.vhd:1828:25 */ + assign n6521_o = ir == 8'b01101111; + /* T80_MCode.vhd:1852:38 */ + assign n6522_o = {28'b0, mcycle}; // uext + /* T80_MCode.vhd:1853:33 */ + assign n6524_o = n6522_o == 31'b0000000000000000000000000000001; + /* T80_MCode.vhd:1855:33 */ + assign n6528_o = n6522_o == 31'b0000000000000000000000000000010; + /* T80_MCode.vhd:1861:33 */ + assign n6530_o = n6522_o == 31'b0000000000000000000000000000011; + /* T80_MCode.vhd:1866:33 */ + assign n6532_o = n6522_o == 31'b0000000000000000000000000000100; + assign n6533_o = {n6532_o, n6530_o, n6528_o, n6524_o}; + /* T80_MCode.vhd:1852:33 */ + always @* + case (n6533_o) + 4'b1000: n6535_o = n2200_o; + 4'b0100: n6535_o = 3'b100; + 4'b0010: n6535_o = n2200_o; + 4'b0001: n6535_o = n2200_o; + default: n6535_o = n2200_o; + endcase + /* T80_MCode.vhd:1852:33 */ + always @* + case (n6533_o) + 4'b1000: n6538_o = 1'b0; + 4'b0100: n6538_o = 1'b0; + 4'b0010: n6538_o = 1'b1; + 4'b0001: n6538_o = 1'b0; + default: n6538_o = 1'b0; + endcase + /* T80_MCode.vhd:1852:33 */ + always @* + case (n6533_o) + 4'b1000: n6540_o = 3'b000; + 4'b0100: n6540_o = 3'b000; + 4'b0010: n6540_o = 3'b111; + 4'b0001: n6540_o = 3'b000; + default: n6540_o = 3'b000; + endcase + /* T80_MCode.vhd:1852:33 */ + always @* + case (n6533_o) + 4'b1000: n6542_o = 3'b000; + 4'b0100: n6542_o = 3'b000; + 4'b0010: n6542_o = 3'b110; + 4'b0001: n6542_o = 3'b000; + default: n6542_o = 3'b000; + endcase + /* T80_MCode.vhd:1852:33 */ + always @* + case (n6533_o) + 4'b1000: n6544_o = n2203_o; + 4'b0100: n6544_o = n2203_o; + 4'b0010: n6544_o = 4'b1110; + 4'b0001: n6544_o = n2203_o; + default: n6544_o = n2203_o; + endcase + /* T80_MCode.vhd:1852:33 */ + always @* + case (n6533_o) + 4'b1000: n6547_o = 1'b0; + 4'b0100: n6547_o = 1'b0; + 4'b0010: n6547_o = 1'b1; + 4'b0001: n6547_o = 1'b0; + default: n6547_o = 1'b0; + endcase + /* T80_MCode.vhd:1852:33 */ + always @* + case (n6533_o) + 4'b1000: n6551_o = 3'b111; + 4'b0100: n6551_o = 3'b010; + 4'b0010: n6551_o = 3'b111; + 4'b0001: n6551_o = 3'b010; + default: n6551_o = 3'b111; + endcase + /* T80_MCode.vhd:1852:33 */ + always @* + case (n6533_o) + 4'b1000: n6554_o = 1'b0; + 4'b0100: n6554_o = 1'b1; + 4'b0010: n6554_o = 1'b0; + 4'b0001: n6554_o = 1'b0; + default: n6554_o = 1'b0; + endcase + /* T80_MCode.vhd:1852:33 */ + always @* + case (n6533_o) + 4'b1000: n6557_o = 1'b0; + 4'b0100: n6557_o = 1'b1; + 4'b0010: n6557_o = 1'b0; + 4'b0001: n6557_o = 1'b0; + default: n6557_o = 1'b0; + endcase + /* T80_MCode.vhd:1852:33 */ + always @* + case (n6533_o) + 4'b1000: n6560_o = 1'b1; + 4'b0100: n6560_o = 1'b0; + 4'b0010: n6560_o = 1'b0; + 4'b0001: n6560_o = 1'b0; + default: n6560_o = 1'b0; + endcase + /* T80_MCode.vhd:1849:25 */ + assign n6562_o = ir == 8'b01100111; + /* T80_MCode.vhd:1873:38 */ + assign n6563_o = {28'b0, mcycle}; // uext + /* T80_MCode.vhd:1874:33 */ + assign n6565_o = n6563_o == 31'b0000000000000000000000000000001; + /* T80_MCode.vhd:1876:33 */ + assign n6567_o = n6563_o == 31'b0000000000000000000000000000010; + /* T80_MCode.vhd:1880:33 */ + assign n6569_o = n6563_o == 31'b0000000000000000000000000000011; + assign n6570_o = {n6569_o, n6567_o, n6565_o}; + /* T80_MCode.vhd:1873:33 */ + always @* + case (n6570_o) + 3'b100: n6574_o = 4'b0111; + 3'b010: n6574_o = 4'b0111; + 3'b001: n6574_o = 4'b0000; + default: n6574_o = 4'b0000; + endcase + /* T80_MCode.vhd:1873:33 */ + always @* + case (n6570_o) + 3'b100: n6578_o = 3'b111; + 3'b010: n6578_o = 3'b101; + 3'b001: n6578_o = 3'b101; + default: n6578_o = 3'b111; + endcase + /* T80_MCode.vhd:1873:33 */ + always @* + case (n6570_o) + 3'b100: n6581_o = 1'b1; + 3'b010: n6581_o = 1'b0; + 3'b001: n6581_o = 1'b0; + default: n6581_o = 1'b0; + endcase + /* T80_MCode.vhd:1873:33 */ + always @* + case (n6570_o) + 3'b100: n6584_o = 1'b0; + 3'b010: n6584_o = 1'b1; + 3'b001: n6584_o = 1'b0; + default: n6584_o = 1'b0; + endcase + /* T80_MCode.vhd:1873:33 */ + always @* + case (n6570_o) + 3'b100: n6587_o = 1'b1; + 3'b010: n6587_o = 1'b0; + 3'b001: n6587_o = 1'b0; + default: n6587_o = 1'b0; + endcase + /* T80_MCode.vhd:1873:33 */ + always @* + case (n6570_o) + 3'b100: n6590_o = 1'b1; + 3'b010: n6590_o = 1'b0; + 3'b001: n6590_o = 1'b0; + default: n6590_o = 1'b0; + endcase + /* T80_MCode.vhd:1870:25 */ + assign n6592_o = ir == 8'b01000101; + /* T80_MCode.vhd:1870:40 */ + assign n6594_o = ir == 8'b01001101; + /* T80_MCode.vhd:1870:40 */ + assign n6595_o = n6592_o | n6594_o; + /* T80_MCode.vhd:1870:51 */ + assign n6597_o = ir == 8'b01010101; + /* T80_MCode.vhd:1870:51 */ + assign n6598_o = n6595_o | n6597_o; + /* T80_MCode.vhd:1870:62 */ + assign n6600_o = ir == 8'b01011101; + /* T80_MCode.vhd:1870:62 */ + assign n6601_o = n6598_o | n6600_o; + /* T80_MCode.vhd:1870:73 */ + assign n6603_o = ir == 8'b01100101; + /* T80_MCode.vhd:1870:73 */ + assign n6604_o = n6601_o | n6603_o; + /* T80_MCode.vhd:1870:84 */ + assign n6606_o = ir == 8'b01101101; + /* T80_MCode.vhd:1870:84 */ + assign n6607_o = n6604_o | n6606_o; + /* T80_MCode.vhd:1870:95 */ + assign n6609_o = ir == 8'b01110101; + /* T80_MCode.vhd:1870:95 */ + assign n6610_o = n6607_o | n6609_o; + /* T80_MCode.vhd:1870:106 */ + assign n6612_o = ir == 8'b01111101; + /* T80_MCode.vhd:1870:106 */ + assign n6613_o = n6610_o | n6612_o; + /* T80_MCode.vhd:1890:38 */ + assign n6614_o = {28'b0, mcycle}; // uext + /* T80_MCode.vhd:1891:33 */ + assign n6616_o = n6614_o == 31'b0000000000000000000000000000001; + /* T80_MCode.vhd:1896:46 */ + assign n6617_o = ir[5:3]; + /* T80_MCode.vhd:1896:59 */ + assign n6619_o = n6617_o != 3'b110; + /* T80_MCode.vhd:1898:78 */ + assign n6620_o = ir[5:3]; + /* T80_MCode.vhd:1896:41 */ + assign n6623_o = n6619_o ? 1'b1 : 1'b0; + /* T80_MCode.vhd:1896:41 */ + assign n6625_o = n6619_o ? n6620_o : 3'b000; + /* T80_MCode.vhd:1894:33 */ + assign n6627_o = n6614_o == 31'b0000000000000000000000000000010; + assign n6628_o = {n6627_o, n6616_o}; + /* T80_MCode.vhd:1890:33 */ + always @* + case (n6628_o) + 2'b10: n6630_o = n6623_o; + 2'b01: n6630_o = 1'b0; + default: n6630_o = 1'b0; + endcase + /* T80_MCode.vhd:1890:33 */ + always @* + case (n6628_o) + 2'b10: n6632_o = n6625_o; + 2'b01: n6632_o = 3'b000; + default: n6632_o = 3'b000; + endcase + /* T80_MCode.vhd:1890:33 */ + always @* + case (n6628_o) + 2'b10: n6635_o = 3'b111; + 2'b01: n6635_o = 3'b000; + default: n6635_o = 3'b111; + endcase + /* T80_MCode.vhd:1890:33 */ + always @* + case (n6628_o) + 2'b10: n6638_o = 1'b1; + 2'b01: n6638_o = 1'b0; + default: n6638_o = 1'b0; + endcase + /* T80_MCode.vhd:1890:33 */ + always @* + case (n6628_o) + 2'b10: n6641_o = 1'b1; + 2'b01: n6641_o = 1'b0; + default: n6641_o = 1'b0; + endcase + /* T80_MCode.vhd:1890:33 */ + always @* + case (n6628_o) + 2'b10: n6644_o = 2'b00; + 2'b01: n6644_o = 2'b01; + default: n6644_o = 2'b00; + endcase + /* T80_MCode.vhd:1887:25 */ + assign n6646_o = ir == 8'b01000000; + /* T80_MCode.vhd:1887:40 */ + assign n6648_o = ir == 8'b01001000; + /* T80_MCode.vhd:1887:40 */ + assign n6649_o = n6646_o | n6648_o; + /* T80_MCode.vhd:1887:51 */ + assign n6651_o = ir == 8'b01010000; + /* T80_MCode.vhd:1887:51 */ + assign n6652_o = n6649_o | n6651_o; + /* T80_MCode.vhd:1887:62 */ + assign n6654_o = ir == 8'b01011000; + /* T80_MCode.vhd:1887:62 */ + assign n6655_o = n6652_o | n6654_o; + /* T80_MCode.vhd:1887:73 */ + assign n6657_o = ir == 8'b01100000; + /* T80_MCode.vhd:1887:73 */ + assign n6658_o = n6655_o | n6657_o; + /* T80_MCode.vhd:1887:84 */ + assign n6660_o = ir == 8'b01101000; + /* T80_MCode.vhd:1887:84 */ + assign n6661_o = n6658_o | n6660_o; + /* T80_MCode.vhd:1887:95 */ + assign n6663_o = ir == 8'b01110000; + /* T80_MCode.vhd:1887:95 */ + assign n6664_o = n6661_o | n6663_o; + /* T80_MCode.vhd:1887:106 */ + assign n6666_o = ir == 8'b01111000; + /* T80_MCode.vhd:1887:106 */ + assign n6667_o = n6664_o | n6666_o; + /* T80_MCode.vhd:1907:38 */ + assign n6668_o = {28'b0, mcycle}; // uext + /* T80_MCode.vhd:1911:78 */ + assign n6669_o = ir[5:3]; + /* T80_MCode.vhd:1912:46 */ + assign n6670_o = ir[5:3]; + /* T80_MCode.vhd:1912:59 */ + assign n6672_o = n6670_o == 3'b110; + /* T80_MCode.vhd:1912:41 */ + assign n6675_o = n6672_o ? 1'b1 : 1'b0; + /* T80_MCode.vhd:1908:33 */ + assign n6677_o = n6668_o == 31'b0000000000000000000000000000001; + /* T80_MCode.vhd:1915:33 */ + assign n6679_o = n6668_o == 31'b0000000000000000000000000000010; + assign n6680_o = {n6679_o, n6677_o}; + /* T80_MCode.vhd:1907:33 */ + always @* + case (n6680_o) + 2'b10: n6682_o = 3'b000; + 2'b01: n6682_o = n6669_o; + default: n6682_o = 3'b000; + endcase + /* T80_MCode.vhd:1907:33 */ + always @* + case (n6680_o) + 2'b10: n6684_o = 1'b0; + 2'b01: n6684_o = n6675_o; + default: n6684_o = 1'b0; + endcase + /* T80_MCode.vhd:1907:33 */ + always @* + case (n6680_o) + 2'b10: n6687_o = 3'b111; + 2'b01: n6687_o = 3'b000; + default: n6687_o = 3'b111; + endcase + /* T80_MCode.vhd:1907:33 */ + always @* + case (n6680_o) + 2'b10: n6690_o = 1'b1; + 2'b01: n6690_o = 1'b0; + default: n6690_o = 1'b0; + endcase + /* T80_MCode.vhd:1907:33 */ + always @* + case (n6680_o) + 2'b10: n6693_o = 2'b00; + 2'b01: n6693_o = 2'b01; + default: n6693_o = 2'b00; + endcase + /* T80_MCode.vhd:1907:33 */ + always @* + case (n6680_o) + 2'b10: n6696_o = 1'b1; + 2'b01: n6696_o = 1'b0; + default: n6696_o = 1'b0; + endcase + /* T80_MCode.vhd:1903:25 */ + assign n6698_o = ir == 8'b01000001; + /* T80_MCode.vhd:1903:40 */ + assign n6700_o = ir == 8'b01001001; + /* T80_MCode.vhd:1903:40 */ + assign n6701_o = n6698_o | n6700_o; + /* T80_MCode.vhd:1903:51 */ + assign n6703_o = ir == 8'b01010001; + /* T80_MCode.vhd:1903:51 */ + assign n6704_o = n6701_o | n6703_o; + /* T80_MCode.vhd:1903:62 */ + assign n6706_o = ir == 8'b01011001; + /* T80_MCode.vhd:1903:62 */ + assign n6707_o = n6704_o | n6706_o; + /* T80_MCode.vhd:1903:73 */ + assign n6709_o = ir == 8'b01100001; + /* T80_MCode.vhd:1903:73 */ + assign n6710_o = n6707_o | n6709_o; + /* T80_MCode.vhd:1903:84 */ + assign n6712_o = ir == 8'b01101001; + /* T80_MCode.vhd:1903:84 */ + assign n6713_o = n6710_o | n6712_o; + /* T80_MCode.vhd:1903:95 */ + assign n6715_o = ir == 8'b01110001; + /* T80_MCode.vhd:1903:95 */ + assign n6716_o = n6713_o | n6715_o; + /* T80_MCode.vhd:1903:106 */ + assign n6718_o = ir == 8'b01111001; + /* T80_MCode.vhd:1903:106 */ + assign n6719_o = n6716_o | n6718_o; + /* T80_MCode.vhd:1923:38 */ + assign n6720_o = {28'b0, mcycle}; // uext + /* T80_MCode.vhd:1933:59 */ + assign n6721_o = ir[3]; + /* T80_MCode.vhd:1924:33 */ + assign n6723_o = n6720_o == 31'b0000000000000000000000000000001; + /* T80_MCode.vhd:1934:33 */ + assign n6725_o = n6720_o == 31'b0000000000000000000000000000010; + /* T80_MCode.vhd:1939:46 */ + assign n6726_o = ir[3]; + /* T80_MCode.vhd:1939:50 */ + assign n6727_o = ~n6726_o; + /* T80_MCode.vhd:1939:41 */ + assign n6730_o = n6727_o ? 4'b0110 : 4'b1110; + /* T80_MCode.vhd:1938:33 */ + assign n6732_o = n6720_o == 31'b0000000000000000000000000000011; + /* T80_MCode.vhd:1946:33 */ + assign n6734_o = n6720_o == 31'b0000000000000000000000000000100; + assign n6735_o = {n6734_o, n6732_o, n6725_o, n6723_o}; + /* T80_MCode.vhd:1923:33 */ + always @* + case (n6735_o) + 4'b1000: n6738_o = 3'b101; + 4'b0100: n6738_o = n2200_o; + 4'b0010: n6738_o = n2200_o; + 4'b0001: n6738_o = 3'b101; + default: n6738_o = n2200_o; + endcase + assign n6739_o = n6730_o[2:0]; + /* T80_MCode.vhd:1923:33 */ + always @* + case (n6735_o) + 4'b1000: n6741_o = 3'b000; + 4'b0100: n6741_o = n6739_o; + 4'b0010: n6741_o = 3'b000; + 4'b0001: n6741_o = 3'b000; + default: n6741_o = 3'b000; + endcase + assign n6742_o = n6730_o[3]; + /* T80_MCode.vhd:1923:33 */ + always @* + case (n6735_o) + 4'b1000: n6744_o = 1'b0; + 4'b0100: n6744_o = n6742_o; + 4'b0010: n6744_o = 1'b0; + 4'b0001: n6744_o = n6721_o; + default: n6744_o = 1'b0; + endcase + /* T80_MCode.vhd:1923:33 */ + always @* + case (n6735_o) + 4'b1000: n6747_o = 1'b0; + 4'b0100: n6747_o = 1'b0; + 4'b0010: n6747_o = 1'b0; + 4'b0001: n6747_o = 1'b1; + default: n6747_o = 1'b0; + endcase + /* T80_MCode.vhd:1923:33 */ + always @* + case (n6735_o) + 4'b1000: n6750_o = 4'b0000; + 4'b0100: n6750_o = 4'b0000; + 4'b0010: n6750_o = 4'b0000; + 4'b0001: n6750_o = 4'b0000; + default: n6750_o = 4'b0000; + endcase + /* T80_MCode.vhd:1923:33 */ + always @* + case (n6735_o) + 4'b1000: n6754_o = 4'b0000; + 4'b0100: n6754_o = 4'b0000; + 4'b0010: n6754_o = 4'b0110; + 4'b0001: n6754_o = 4'b1010; + default: n6754_o = 4'b0000; + endcase + /* T80_MCode.vhd:1923:33 */ + always @* + case (n6735_o) + 4'b1000: n6756_o = n2203_o; + 4'b0100: n6756_o = n2203_o; + 4'b0010: n6756_o = n2203_o; + 4'b0001: n6756_o = 4'b0010; + default: n6756_o = n2203_o; + endcase + /* T80_MCode.vhd:1923:33 */ + always @* + case (n6735_o) + 4'b1000: n6759_o = 1'b0; + 4'b0100: n6759_o = 1'b0; + 4'b0010: n6759_o = 1'b0; + 4'b0001: n6759_o = 1'b1; + default: n6759_o = 1'b0; + endcase + /* T80_MCode.vhd:1923:33 */ + always @* + case (n6735_o) + 4'b1000: n6763_o = 3'b111; + 4'b0100: n6763_o = 3'b111; + 4'b0010: n6763_o = 3'b010; + 4'b0001: n6763_o = 3'b000; + default: n6763_o = 3'b111; + endcase + /* T80_MCode.vhd:1923:33 */ + always @* + case (n6735_o) + 4'b1000: n6766_o = 1'b0; + 4'b0100: n6766_o = 1'b0; + 4'b0010: n6766_o = 1'b1; + 4'b0001: n6766_o = 1'b0; + default: n6766_o = 1'b0; + endcase + /* T80_MCode.vhd:1923:33 */ + always @* + case (n6735_o) + 4'b1000: n6769_o = 1'b0; + 4'b0100: n6769_o = 1'b1; + 4'b0010: n6769_o = 1'b0; + 4'b0001: n6769_o = 1'b0; + default: n6769_o = 1'b0; + endcase + /* T80_MCode.vhd:1923:33 */ + always @* + case (n6735_o) + 4'b1000: n6772_o = 2'b00; + 4'b0100: n6772_o = 2'b00; + 4'b0010: n6772_o = 2'b00; + 4'b0001: n6772_o = 2'b11; + default: n6772_o = 2'b00; + endcase + /* T80_MCode.vhd:1923:33 */ + always @* + case (n6735_o) + 4'b1000: n6775_o = 1'b1; + 4'b0100: n6775_o = 1'b0; + 4'b0010: n6775_o = 1'b0; + 4'b0001: n6775_o = 1'b0; + default: n6775_o = 1'b0; + endcase + /* T80_MCode.vhd:1923:33 */ + always @* + case (n6735_o) + 4'b1000: n6778_o = 1'b0; + 4'b0100: n6778_o = 1'b1; + 4'b0010: n6778_o = 1'b0; + 4'b0001: n6778_o = 1'b0; + default: n6778_o = 1'b0; + endcase + /* T80_MCode.vhd:1920:25 */ + assign n6780_o = ir == 8'b10100010; + /* T80_MCode.vhd:1920:41 */ + assign n6782_o = ir == 8'b10101010; + /* T80_MCode.vhd:1920:41 */ + assign n6783_o = n6780_o | n6782_o; + /* T80_MCode.vhd:1920:54 */ + assign n6785_o = ir == 8'b10110010; + /* T80_MCode.vhd:1920:54 */ + assign n6786_o = n6783_o | n6785_o; + /* T80_MCode.vhd:1920:67 */ + assign n6788_o = ir == 8'b10111010; + /* T80_MCode.vhd:1920:67 */ + assign n6789_o = n6786_o | n6788_o; + /* T80_MCode.vhd:1954:38 */ + assign n6790_o = {28'b0, mcycle}; // uext + /* T80_MCode.vhd:1955:33 */ + assign n6792_o = n6790_o == 31'b0000000000000000000000000000001; + /* T80_MCode.vhd:1967:59 */ + assign n6793_o = ir[3]; + /* T80_MCode.vhd:1963:33 */ + assign n6795_o = n6790_o == 31'b0000000000000000000000000000010; + /* T80_MCode.vhd:1969:46 */ + assign n6796_o = ir[3]; + /* T80_MCode.vhd:1969:50 */ + assign n6797_o = ~n6796_o; + /* T80_MCode.vhd:1969:41 */ + assign n6800_o = n6797_o ? 4'b0110 : 4'b1110; + /* T80_MCode.vhd:1968:33 */ + assign n6802_o = n6790_o == 31'b0000000000000000000000000000011; + /* T80_MCode.vhd:1977:33 */ + assign n6804_o = n6790_o == 31'b0000000000000000000000000000100; + assign n6805_o = {n6804_o, n6802_o, n6795_o, n6792_o}; + /* T80_MCode.vhd:1954:33 */ + always @* + case (n6805_o) + 4'b1000: n6808_o = 3'b101; + 4'b0100: n6808_o = n2200_o; + 4'b0010: n6808_o = n2200_o; + 4'b0001: n6808_o = 3'b101; + default: n6808_o = n2200_o; + endcase + assign n6809_o = n6800_o[2:0]; + /* T80_MCode.vhd:1954:33 */ + always @* + case (n6805_o) + 4'b1000: n6811_o = 3'b000; + 4'b0100: n6811_o = n6809_o; + 4'b0010: n6811_o = 3'b000; + 4'b0001: n6811_o = 3'b000; + default: n6811_o = 3'b000; + endcase + assign n6812_o = n6800_o[3]; + /* T80_MCode.vhd:1954:33 */ + always @* + case (n6805_o) + 4'b1000: n6814_o = 1'b0; + 4'b0100: n6814_o = n6812_o; + 4'b0010: n6814_o = n6793_o; + 4'b0001: n6814_o = 1'b0; + default: n6814_o = 1'b0; + endcase + /* T80_MCode.vhd:1954:33 */ + always @* + case (n6805_o) + 4'b1000: n6817_o = 1'b0; + 4'b0100: n6817_o = 1'b0; + 4'b0010: n6817_o = 1'b0; + 4'b0001: n6817_o = 1'b1; + default: n6817_o = 1'b0; + endcase + /* T80_MCode.vhd:1954:33 */ + always @* + case (n6805_o) + 4'b1000: n6820_o = 4'b0000; + 4'b0100: n6820_o = 4'b0000; + 4'b0010: n6820_o = 4'b0000; + 4'b0001: n6820_o = 4'b0000; + default: n6820_o = 4'b0000; + endcase + /* T80_MCode.vhd:1954:33 */ + always @* + case (n6805_o) + 4'b1000: n6824_o = 4'b0000; + 4'b0100: n6824_o = 4'b0000; + 4'b0010: n6824_o = 4'b0110; + 4'b0001: n6824_o = 4'b1010; + default: n6824_o = 4'b0000; + endcase + /* T80_MCode.vhd:1954:33 */ + always @* + case (n6805_o) + 4'b1000: n6826_o = n2203_o; + 4'b0100: n6826_o = n2203_o; + 4'b0010: n6826_o = n2203_o; + 4'b0001: n6826_o = 4'b0010; + default: n6826_o = n2203_o; + endcase + /* T80_MCode.vhd:1954:33 */ + always @* + case (n6805_o) + 4'b1000: n6829_o = 1'b0; + 4'b0100: n6829_o = 1'b0; + 4'b0010: n6829_o = 1'b0; + 4'b0001: n6829_o = 1'b1; + default: n6829_o = 1'b0; + endcase + /* T80_MCode.vhd:1954:33 */ + always @* + case (n6805_o) + 4'b1000: n6833_o = 3'b111; + 4'b0100: n6833_o = 3'b111; + 4'b0010: n6833_o = 3'b000; + 4'b0001: n6833_o = 3'b010; + default: n6833_o = 3'b111; + endcase + /* T80_MCode.vhd:1954:33 */ + always @* + case (n6805_o) + 4'b1000: n6836_o = 1'b0; + 4'b0100: n6836_o = 1'b1; + 4'b0010: n6836_o = 1'b0; + 4'b0001: n6836_o = 1'b0; + default: n6836_o = 1'b0; + endcase + /* T80_MCode.vhd:1954:33 */ + always @* + case (n6805_o) + 4'b1000: n6839_o = 1'b0; + 4'b0100: n6839_o = 1'b1; + 4'b0010: n6839_o = 1'b0; + 4'b0001: n6839_o = 1'b0; + default: n6839_o = 1'b0; + endcase + /* T80_MCode.vhd:1954:33 */ + always @* + case (n6805_o) + 4'b1000: n6842_o = 2'b00; + 4'b0100: n6842_o = 2'b00; + 4'b0010: n6842_o = 2'b11; + 4'b0001: n6842_o = 2'b00; + default: n6842_o = 2'b00; + endcase + /* T80_MCode.vhd:1954:33 */ + always @* + case (n6805_o) + 4'b1000: n6845_o = 1'b1; + 4'b0100: n6845_o = 1'b0; + 4'b0010: n6845_o = 1'b0; + 4'b0001: n6845_o = 1'b0; + default: n6845_o = 1'b0; + endcase + /* T80_MCode.vhd:1954:33 */ + always @* + case (n6805_o) + 4'b1000: n6848_o = 1'b0; + 4'b0100: n6848_o = 1'b1; + 4'b0010: n6848_o = 1'b0; + 4'b0001: n6848_o = 1'b0; + default: n6848_o = 1'b0; + endcase + /* T80_MCode.vhd:1951:25 */ + assign n6850_o = ir == 8'b10100011; + /* T80_MCode.vhd:1951:41 */ + assign n6852_o = ir == 8'b10101011; + /* T80_MCode.vhd:1951:41 */ + assign n6853_o = n6850_o | n6852_o; + /* T80_MCode.vhd:1951:54 */ + assign n6855_o = ir == 8'b10110011; + /* T80_MCode.vhd:1951:54 */ + assign n6856_o = n6853_o | n6855_o; + /* T80_MCode.vhd:1951:67 */ + assign n6858_o = ir == 8'b10111011; + /* T80_MCode.vhd:1951:67 */ + assign n6859_o = n6856_o | n6858_o; + assign n6860_o = {n6859_o, n6789_o, n6719_o, n6667_o, n6613_o, n6562_o, n6521_o, n6480_o, n6395_o, n6310_o, n6305_o, n6300_o, n6289_o, n6266_o, n6210_o, n6152_o, n6090_o, n6022_o, n6020_o, n6018_o, n6016_o, n6014_o, n6009_o}; + /* T80_MCode.vhd:1573:25 */ + always @* + case (n6860_o) + 23'b10000000000000000000000: n6876_o = 3'b100; + 23'b01000000000000000000000: n6876_o = 3'b100; + 23'b00100000000000000000000: n6876_o = 3'b010; + 23'b00010000000000000000000: n6876_o = 3'b010; + 23'b00001000000000000000000: n6876_o = 3'b011; + 23'b00000100000000000000000: n6876_o = 3'b100; + 23'b00000010000000000000000: n6876_o = 3'b100; + 23'b00000001000000000000000: n6876_o = 3'b011; + 23'b00000000100000000000000: n6876_o = 3'b011; + 23'b00000000010000000000000: n6876_o = 3'b001; + 23'b00000000001000000000000: n6876_o = 3'b001; + 23'b00000000000100000000000: n6876_o = 3'b001; + 23'b00000000000010000000000: n6876_o = 3'b001; + 23'b00000000000001000000000: n6876_o = 3'b100; + 23'b00000000000000100000000: n6876_o = 3'b100; + 23'b00000000000000010000000: n6876_o = 3'b101; + 23'b00000000000000001000000: n6876_o = 3'b101; + 23'b00000000000000000100000: n6876_o = 3'b001; + 23'b00000000000000000010000: n6876_o = 3'b001; + 23'b00000000000000000001000: n6876_o = 3'b001; + 23'b00000000000000000000100: n6876_o = 3'b001; + 23'b00000000000000000000010: n6876_o = 3'b001; + 23'b00000000000000000000001: n6876_o = 3'b001; + default: n6876_o = 3'bX; + endcase + /* T80_MCode.vhd:1573:25 */ + always @* + case (n6860_o) + 23'b10000000000000000000000: n6882_o = n6808_o; + 23'b01000000000000000000000: n6882_o = n6738_o; + 23'b00100000000000000000000: n6882_o = n2200_o; + 23'b00010000000000000000000: n6882_o = n2200_o; + 23'b00001000000000000000000: n6882_o = n2200_o; + 23'b00000100000000000000000: n6882_o = n6535_o; + 23'b00000010000000000000000: n6882_o = n6494_o; + 23'b00000001000000000000000: n6882_o = n6443_o; + 23'b00000000100000000000000: n6882_o = n6358_o; + 23'b00000000010000000000000: n6882_o = n2200_o; + 23'b00000000001000000000000: n6882_o = n2200_o; + 23'b00000000000100000000000: n6882_o = n2200_o; + 23'b00000000000010000000000: n6882_o = n2200_o; + 23'b00000000000001000000000: n6882_o = n6229_o; + 23'b00000000000000100000000: n6882_o = n6176_o; + 23'b00000000000000010000000: n6882_o = n2200_o; + 23'b00000000000000001000000: n6882_o = n2200_o; + 23'b00000000000000000100000: n6882_o = 3'b101; + 23'b00000000000000000010000: n6882_o = 3'b101; + 23'b00000000000000000001000: n6882_o = 3'b101; + 23'b00000000000000000000100: n6882_o = 3'b101; + 23'b00000000000000000000010: n6882_o = n2200_o; + 23'b00000000000000000000001: n6882_o = n2200_o; + default: n6882_o = 3'bX; + endcase + /* T80_MCode.vhd:1573:25 */ + always @* + case (n6860_o) + 23'b10000000000000000000000: n6885_o = 1'b0; + 23'b01000000000000000000000: n6885_o = 1'b0; + 23'b00100000000000000000000: n6885_o = 1'b0; + 23'b00010000000000000000000: n6885_o = 1'b0; + 23'b00001000000000000000000: n6885_o = 1'b0; + 23'b00000100000000000000000: n6885_o = 1'b0; + 23'b00000010000000000000000: n6885_o = 1'b0; + 23'b00000001000000000000000: n6885_o = 1'b0; + 23'b00000000100000000000000: n6885_o = 1'b0; + 23'b00000000010000000000000: n6885_o = 1'b0; + 23'b00000000001000000000000: n6885_o = 1'b0; + 23'b00000000000100000000000: n6885_o = 1'b0; + 23'b00000000000010000000000: n6885_o = 1'b0; + 23'b00000000000001000000000: n6885_o = 1'b0; + 23'b00000000000000100000000: n6885_o = 1'b0; + 23'b00000000000000010000000: n6885_o = n6122_o; + 23'b00000000000000001000000: n6885_o = n6058_o; + 23'b00000000000000000100000: n6885_o = 1'b0; + 23'b00000000000000000010000: n6885_o = 1'b0; + 23'b00000000000000000001000: n6885_o = 1'b0; + 23'b00000000000000000000100: n6885_o = 1'b0; + 23'b00000000000000000000010: n6885_o = 1'b0; + 23'b00000000000000000000001: n6885_o = 1'b0; + default: n6885_o = 1'bX; + endcase + /* T80_MCode.vhd:1573:25 */ + always @* + case (n6860_o) + 23'b10000000000000000000000: n6888_o = 1'b0; + 23'b01000000000000000000000: n6888_o = 1'b0; + 23'b00100000000000000000000: n6888_o = 1'b0; + 23'b00010000000000000000000: n6888_o = 1'b0; + 23'b00001000000000000000000: n6888_o = 1'b0; + 23'b00000100000000000000000: n6888_o = 1'b0; + 23'b00000010000000000000000: n6888_o = 1'b0; + 23'b00000001000000000000000: n6888_o = 1'b0; + 23'b00000000100000000000000: n6888_o = 1'b0; + 23'b00000000010000000000000: n6888_o = 1'b0; + 23'b00000000001000000000000: n6888_o = 1'b0; + 23'b00000000000100000000000: n6888_o = 1'b0; + 23'b00000000000010000000000: n6888_o = 1'b0; + 23'b00000000000001000000000: n6888_o = 1'b0; + 23'b00000000000000100000000: n6888_o = 1'b0; + 23'b00000000000000010000000: n6888_o = n6125_o; + 23'b00000000000000001000000: n6888_o = n6061_o; + 23'b00000000000000000100000: n6888_o = 1'b0; + 23'b00000000000000000010000: n6888_o = 1'b0; + 23'b00000000000000000001000: n6888_o = 1'b0; + 23'b00000000000000000000100: n6888_o = 1'b0; + 23'b00000000000000000000010: n6888_o = 1'b0; + 23'b00000000000000000000001: n6888_o = 1'b0; + default: n6888_o = 1'bX; + endcase + assign n6889_o = n6179_o[2:0]; + assign n6890_o = n6232_o[2:0]; + assign n6891_o = n6574_o[2:0]; + /* T80_MCode.vhd:1573:25 */ + always @* + case (n6860_o) + 23'b10000000000000000000000: n6894_o = n6811_o; + 23'b01000000000000000000000: n6894_o = n6741_o; + 23'b00100000000000000000000: n6894_o = 3'b000; + 23'b00010000000000000000000: n6894_o = 3'b000; + 23'b00001000000000000000000: n6894_o = n6891_o; + 23'b00000100000000000000000: n6894_o = 3'b000; + 23'b00000010000000000000000: n6894_o = 3'b000; + 23'b00000001000000000000000: n6894_o = 3'b000; + 23'b00000000100000000000000: n6894_o = 3'b000; + 23'b00000000010000000000000: n6894_o = 3'b000; + 23'b00000000001000000000000: n6894_o = 3'b000; + 23'b00000000000100000000000: n6894_o = 3'b000; + 23'b00000000000010000000000: n6894_o = 3'b000; + 23'b00000000000001000000000: n6894_o = n6890_o; + 23'b00000000000000100000000: n6894_o = n6889_o; + 23'b00000000000000010000000: n6894_o = 3'b000; + 23'b00000000000000001000000: n6894_o = 3'b000; + 23'b00000000000000000100000: n6894_o = 3'b000; + 23'b00000000000000000010000: n6894_o = 3'b000; + 23'b00000000000000000001000: n6894_o = 3'b000; + 23'b00000000000000000000100: n6894_o = 3'b000; + 23'b00000000000000000000010: n6894_o = 3'b000; + 23'b00000000000000000000001: n6894_o = 3'b000; + default: n6894_o = 3'bX; + endcase + assign n6895_o = n6179_o[3]; + assign n6896_o = n6232_o[3]; + assign n6897_o = n6574_o[3]; + /* T80_MCode.vhd:1573:25 */ + always @* + case (n6860_o) + 23'b10000000000000000000000: n6900_o = n6814_o; + 23'b01000000000000000000000: n6900_o = n6744_o; + 23'b00100000000000000000000: n6900_o = 1'b0; + 23'b00010000000000000000000: n6900_o = 1'b0; + 23'b00001000000000000000000: n6900_o = n6897_o; + 23'b00000100000000000000000: n6900_o = 1'b0; + 23'b00000010000000000000000: n6900_o = 1'b0; + 23'b00000001000000000000000: n6900_o = 1'b0; + 23'b00000000100000000000000: n6900_o = 1'b0; + 23'b00000000010000000000000: n6900_o = 1'b0; + 23'b00000000001000000000000: n6900_o = 1'b0; + 23'b00000000000100000000000: n6900_o = 1'b0; + 23'b00000000000010000000000: n6900_o = 1'b0; + 23'b00000000000001000000000: n6900_o = n6896_o; + 23'b00000000000000100000000: n6900_o = n6895_o; + 23'b00000000000000010000000: n6900_o = 1'b0; + 23'b00000000000000001000000: n6900_o = 1'b0; + 23'b00000000000000000100000: n6900_o = 1'b0; + 23'b00000000000000000010000: n6900_o = 1'b0; + 23'b00000000000000000001000: n6900_o = 1'b0; + 23'b00000000000000000000100: n6900_o = 1'b0; + 23'b00000000000000000000010: n6900_o = 1'b0; + 23'b00000000000000000000001: n6900_o = 1'b0; + default: n6900_o = 1'bX; + endcase + /* T80_MCode.vhd:1573:25 */ + always @* + case (n6860_o) + 23'b10000000000000000000000: n6903_o = n6817_o; + 23'b01000000000000000000000: n6903_o = n6747_o; + 23'b00100000000000000000000: n6903_o = 1'b0; + 23'b00010000000000000000000: n6903_o = n6630_o; + 23'b00001000000000000000000: n6903_o = 1'b0; + 23'b00000100000000000000000: n6903_o = n6538_o; + 23'b00000010000000000000000: n6903_o = n6497_o; + 23'b00000001000000000000000: n6903_o = n6447_o; + 23'b00000000100000000000000: n6903_o = n6362_o; + 23'b00000000010000000000000: n6903_o = 1'b0; + 23'b00000000001000000000000: n6903_o = 1'b0; + 23'b00000000000100000000000: n6903_o = 1'b0; + 23'b00000000000010000000000: n6903_o = 1'b0; + 23'b00000000000001000000000: n6903_o = 1'b0; + 23'b00000000000000100000000: n6903_o = 1'b0; + 23'b00000000000000010000000: n6903_o = 1'b0; + 23'b00000000000000001000000: n6903_o = n6065_o; + 23'b00000000000000000100000: n6903_o = 1'b0; + 23'b00000000000000000010000: n6903_o = 1'b0; + 23'b00000000000000000001000: n6903_o = 1'b0; + 23'b00000000000000000000100: n6903_o = 1'b0; + 23'b00000000000000000000010: n6903_o = 1'b0; + 23'b00000000000000000000001: n6903_o = 1'b0; + default: n6903_o = 1'bX; + endcase + /* T80_MCode.vhd:1573:25 */ + always @* + case (n6860_o) + 23'b10000000000000000000000: n6907_o = 1'b0; + 23'b01000000000000000000000: n6907_o = 1'b0; + 23'b00100000000000000000000: n6907_o = 1'b0; + 23'b00010000000000000000000: n6907_o = 1'b0; + 23'b00001000000000000000000: n6907_o = 1'b0; + 23'b00000100000000000000000: n6907_o = 1'b0; + 23'b00000010000000000000000: n6907_o = 1'b0; + 23'b00000001000000000000000: n6907_o = 1'b0; + 23'b00000000100000000000000: n6907_o = 1'b0; + 23'b00000000010000000000000: n6907_o = 1'b0; + 23'b00000000001000000000000: n6907_o = 1'b0; + 23'b00000000000100000000000: n6907_o = 1'b0; + 23'b00000000000010000000000: n6907_o = 1'b1; + 23'b00000000000001000000000: n6907_o = 1'b0; + 23'b00000000000000100000000: n6907_o = 1'b0; + 23'b00000000000000010000000: n6907_o = 1'b0; + 23'b00000000000000001000000: n6907_o = 1'b0; + 23'b00000000000000000100000: n6907_o = 1'b0; + 23'b00000000000000000010000: n6907_o = 1'b0; + 23'b00000000000000000001000: n6907_o = 1'b0; + 23'b00000000000000000000100: n6907_o = 1'b0; + 23'b00000000000000000000010: n6907_o = 1'b0; + 23'b00000000000000000000001: n6907_o = 1'b0; + default: n6907_o = 1'bX; + endcase + assign n6909_o = n6750_o[2:0]; + assign n6910_o = n6820_o[2:0]; + /* T80_MCode.vhd:1573:25 */ + always @* + case (n6860_o) + 23'b10000000000000000000000: n6913_o = n6910_o; + 23'b01000000000000000000000: n6913_o = n6909_o; + 23'b00100000000000000000000: n6913_o = 3'b000; + 23'b00010000000000000000000: n6913_o = n6632_o; + 23'b00001000000000000000000: n6913_o = 3'b000; + 23'b00000100000000000000000: n6913_o = n6540_o; + 23'b00000010000000000000000: n6913_o = n6499_o; + 23'b00000001000000000000000: n6913_o = n6449_o; + 23'b00000000100000000000000: n6913_o = n6364_o; + 23'b00000000010000000000000: n6913_o = 3'b000; + 23'b00000000001000000000000: n6913_o = 3'b000; + 23'b00000000000100000000000: n6913_o = 3'b000; + 23'b00000000000010000000000: n6913_o = 3'b010; + 23'b00000000000001000000000: n6913_o = n6234_o; + 23'b00000000000000100000000: n6913_o = n6181_o; + 23'b00000000000000010000000: n6913_o = 3'b000; + 23'b00000000000000001000000: n6913_o = n6067_o; + 23'b00000000000000000100000: n6913_o = 3'b000; + 23'b00000000000000000010000: n6913_o = 3'b000; + 23'b00000000000000000001000: n6913_o = 3'b000; + 23'b00000000000000000000100: n6913_o = 3'b000; + 23'b00000000000000000000010: n6913_o = 3'b000; + 23'b00000000000000000000001: n6913_o = 3'b000; + default: n6913_o = 3'bX; + endcase + assign n6915_o = n6750_o[3]; + assign n6916_o = n6820_o[3]; + /* T80_MCode.vhd:1573:25 */ + always @* + case (n6860_o) + 23'b10000000000000000000000: n6919_o = n6916_o; + 23'b01000000000000000000000: n6919_o = n6915_o; + 23'b00100000000000000000000: n6919_o = 1'b0; + 23'b00010000000000000000000: n6919_o = 1'b0; + 23'b00001000000000000000000: n6919_o = 1'b0; + 23'b00000100000000000000000: n6919_o = 1'b0; + 23'b00000010000000000000000: n6919_o = 1'b0; + 23'b00000001000000000000000: n6919_o = 1'b0; + 23'b00000000100000000000000: n6919_o = 1'b0; + 23'b00000000010000000000000: n6919_o = 1'b0; + 23'b00000000001000000000000: n6919_o = 1'b0; + 23'b00000000000100000000000: n6919_o = 1'b0; + 23'b00000000000010000000000: n6919_o = 1'b1; + 23'b00000000000001000000000: n6919_o = 1'b0; + 23'b00000000000000100000000: n6919_o = 1'b0; + 23'b00000000000000010000000: n6919_o = 1'b0; + 23'b00000000000000001000000: n6919_o = n6069_o; + 23'b00000000000000000100000: n6919_o = 1'b0; + 23'b00000000000000000010000: n6919_o = 1'b0; + 23'b00000000000000000001000: n6919_o = 1'b0; + 23'b00000000000000000000100: n6919_o = 1'b0; + 23'b00000000000000000000010: n6919_o = 1'b0; + 23'b00000000000000000000001: n6919_o = 1'b0; + default: n6919_o = 1'bX; + endcase + assign n6920_o = n6127_o[0]; + assign n6921_o = n6184_o[0]; + assign n6922_o = n6237_o[0]; + assign n6924_o = n6501_o[0]; + assign n6925_o = n6542_o[0]; + assign n6926_o = n6682_o[0]; + assign n6927_o = n6754_o[0]; + assign n6928_o = n6824_o[0]; + /* T80_MCode.vhd:1573:25 */ + always @* + case (n6860_o) + 23'b10000000000000000000000: n6931_o = n6928_o; + 23'b01000000000000000000000: n6931_o = n6927_o; + 23'b00100000000000000000000: n6931_o = n6926_o; + 23'b00010000000000000000000: n6931_o = 1'b0; + 23'b00001000000000000000000: n6931_o = 1'b0; + 23'b00000100000000000000000: n6931_o = n6925_o; + 23'b00000010000000000000000: n6931_o = n6924_o; + 23'b00000001000000000000000: n6931_o = n6451_o; + 23'b00000000100000000000000: n6931_o = n6366_o; + 23'b00000000010000000000000: n6931_o = 1'b0; + 23'b00000000001000000000000: n6931_o = 1'b0; + 23'b00000000000100000000000: n6931_o = 1'b0; + 23'b00000000000010000000000: n6931_o = 1'b1; + 23'b00000000000001000000000: n6931_o = n6922_o; + 23'b00000000000000100000000: n6931_o = n6921_o; + 23'b00000000000000010000000: n6931_o = n6920_o; + 23'b00000000000000001000000: n6931_o = 1'b0; + 23'b00000000000000000100000: n6931_o = 1'b0; + 23'b00000000000000000010000: n6931_o = 1'b0; + 23'b00000000000000000001000: n6931_o = 1'b0; + 23'b00000000000000000000100: n6931_o = 1'b0; + 23'b00000000000000000000010: n6931_o = 1'b0; + 23'b00000000000000000000001: n6931_o = 1'b0; + default: n6931_o = 1'bX; + endcase + assign n6932_o = n6127_o[2:1]; + assign n6933_o = n6184_o[2:1]; + assign n6934_o = n6237_o[2:1]; + assign n6936_o = n6501_o[2:1]; + assign n6937_o = n6542_o[2:1]; + assign n6938_o = n6682_o[2:1]; + assign n6939_o = n6754_o[2:1]; + assign n6940_o = n6824_o[2:1]; + /* T80_MCode.vhd:1573:25 */ + always @* + case (n6860_o) + 23'b10000000000000000000000: n6943_o = n6940_o; + 23'b01000000000000000000000: n6943_o = n6939_o; + 23'b00100000000000000000000: n6943_o = n6938_o; + 23'b00010000000000000000000: n6943_o = 2'b00; + 23'b00001000000000000000000: n6943_o = 2'b00; + 23'b00000100000000000000000: n6943_o = n6937_o; + 23'b00000010000000000000000: n6943_o = n6936_o; + 23'b00000001000000000000000: n6943_o = n6453_o; + 23'b00000000100000000000000: n6943_o = n6368_o; + 23'b00000000010000000000000: n6943_o = 2'b00; + 23'b00000000001000000000000: n6943_o = 2'b00; + 23'b00000000000100000000000: n6943_o = 2'b00; + 23'b00000000000010000000000: n6943_o = 2'b11; + 23'b00000000000001000000000: n6943_o = n6934_o; + 23'b00000000000000100000000: n6943_o = n6933_o; + 23'b00000000000000010000000: n6943_o = n6932_o; + 23'b00000000000000001000000: n6943_o = 2'b00; + 23'b00000000000000000100000: n6943_o = 2'b00; + 23'b00000000000000000010000: n6943_o = 2'b00; + 23'b00000000000000000001000: n6943_o = 2'b00; + 23'b00000000000000000000100: n6943_o = 2'b00; + 23'b00000000000000000000010: n6943_o = 2'b00; + 23'b00000000000000000000001: n6943_o = 2'b00; + default: n6943_o = 2'bX; + endcase + assign n6944_o = n6127_o[3]; + assign n6945_o = n6184_o[3]; + assign n6946_o = n6237_o[3]; + assign n6948_o = n6754_o[3]; + assign n6949_o = n6824_o[3]; + /* T80_MCode.vhd:1573:25 */ + always @* + case (n6860_o) + 23'b10000000000000000000000: n6952_o = n6949_o; + 23'b01000000000000000000000: n6952_o = n6948_o; + 23'b00100000000000000000000: n6952_o = n6684_o; + 23'b00010000000000000000000: n6952_o = 1'b0; + 23'b00001000000000000000000: n6952_o = 1'b0; + 23'b00000100000000000000000: n6952_o = 1'b0; + 23'b00000010000000000000000: n6952_o = 1'b0; + 23'b00000001000000000000000: n6952_o = n6455_o; + 23'b00000000100000000000000: n6952_o = n6370_o; + 23'b00000000010000000000000: n6952_o = 1'b0; + 23'b00000000001000000000000: n6952_o = 1'b0; + 23'b00000000000100000000000: n6952_o = 1'b0; + 23'b00000000000010000000000: n6952_o = 1'b0; + 23'b00000000000001000000000: n6952_o = n6946_o; + 23'b00000000000000100000000: n6952_o = n6945_o; + 23'b00000000000000010000000: n6952_o = n6944_o; + 23'b00000000000000001000000: n6952_o = 1'b0; + 23'b00000000000000000100000: n6952_o = 1'b0; + 23'b00000000000000000010000: n6952_o = 1'b0; + 23'b00000000000000000001000: n6952_o = 1'b0; + 23'b00000000000000000000100: n6952_o = 1'b0; + 23'b00000000000000000000010: n6952_o = 1'b0; + 23'b00000000000000000000001: n6952_o = 1'b0; + default: n6952_o = 1'bX; + endcase + /* T80_MCode.vhd:1573:25 */ + always @* + case (n6860_o) + 23'b10000000000000000000000: n6955_o = n6826_o; + 23'b01000000000000000000000: n6955_o = n6756_o; + 23'b00100000000000000000000: n6955_o = n2203_o; + 23'b00010000000000000000000: n6955_o = n2203_o; + 23'b00001000000000000000000: n6955_o = n2203_o; + 23'b00000100000000000000000: n6955_o = n6544_o; + 23'b00000010000000000000000: n6955_o = n6503_o; + 23'b00000001000000000000000: n6955_o = n6458_o; + 23'b00000000100000000000000: n6955_o = n6373_o; + 23'b00000000010000000000000: n6955_o = n2203_o; + 23'b00000000001000000000000: n6955_o = n2203_o; + 23'b00000000000100000000000: n6955_o = n2203_o; + 23'b00000000000010000000000: n6955_o = 4'b0010; + 23'b00000000000001000000000: n6955_o = n6239_o; + 23'b00000000000000100000000: n6955_o = n6186_o; + 23'b00000000000000010000000: n6955_o = n2203_o; + 23'b00000000000000001000000: n6955_o = n2203_o; + 23'b00000000000000000100000: n6955_o = n2203_o; + 23'b00000000000000000010000: n6955_o = n2203_o; + 23'b00000000000000000001000: n6955_o = n2203_o; + 23'b00000000000000000000100: n6955_o = n2203_o; + 23'b00000000000000000000010: n6955_o = n2203_o; + 23'b00000000000000000000001: n6955_o = n2203_o; + default: n6955_o = 4'bX; + endcase + /* T80_MCode.vhd:1573:25 */ + always @* + case (n6860_o) + 23'b10000000000000000000000: n6959_o = n6829_o; + 23'b01000000000000000000000: n6959_o = n6759_o; + 23'b00100000000000000000000: n6959_o = 1'b0; + 23'b00010000000000000000000: n6959_o = 1'b0; + 23'b00001000000000000000000: n6959_o = 1'b0; + 23'b00000100000000000000000: n6959_o = n6547_o; + 23'b00000010000000000000000: n6959_o = n6506_o; + 23'b00000001000000000000000: n6959_o = n6462_o; + 23'b00000000100000000000000: n6959_o = n6377_o; + 23'b00000000010000000000000: n6959_o = 1'b0; + 23'b00000000001000000000000: n6959_o = 1'b0; + 23'b00000000000100000000000: n6959_o = 1'b0; + 23'b00000000000010000000000: n6959_o = 1'b1; + 23'b00000000000001000000000: n6959_o = n6242_o; + 23'b00000000000000100000000: n6959_o = 1'b0; + 23'b00000000000000010000000: n6959_o = 1'b0; + 23'b00000000000000001000000: n6959_o = 1'b0; + 23'b00000000000000000100000: n6959_o = 1'b0; + 23'b00000000000000000010000: n6959_o = 1'b0; + 23'b00000000000000000001000: n6959_o = 1'b0; + 23'b00000000000000000000100: n6959_o = 1'b0; + 23'b00000000000000000000010: n6959_o = 1'b0; + 23'b00000000000000000000001: n6959_o = 1'b0; + default: n6959_o = 1'bX; + endcase + /* T80_MCode.vhd:1573:25 */ + always @* + case (n6860_o) + 23'b10000000000000000000000: n6962_o = 1'b0; + 23'b01000000000000000000000: n6962_o = 1'b0; + 23'b00100000000000000000000: n6962_o = 1'b0; + 23'b00010000000000000000000: n6962_o = 1'b0; + 23'b00001000000000000000000: n6962_o = 1'b0; + 23'b00000100000000000000000: n6962_o = 1'b0; + 23'b00000010000000000000000: n6962_o = 1'b0; + 23'b00000001000000000000000: n6962_o = 1'b0; + 23'b00000000100000000000000: n6962_o = 1'b0; + 23'b00000000010000000000000: n6962_o = 1'b0; + 23'b00000000001000000000000: n6962_o = 1'b0; + 23'b00000000000100000000000: n6962_o = 1'b0; + 23'b00000000000010000000000: n6962_o = 1'b0; + 23'b00000000000001000000000: n6962_o = n6245_o; + 23'b00000000000000100000000: n6962_o = 1'b0; + 23'b00000000000000010000000: n6962_o = 1'b0; + 23'b00000000000000001000000: n6962_o = 1'b0; + 23'b00000000000000000100000: n6962_o = 1'b0; + 23'b00000000000000000010000: n6962_o = 1'b0; + 23'b00000000000000000001000: n6962_o = 1'b0; + 23'b00000000000000000000100: n6962_o = 1'b0; + 23'b00000000000000000000010: n6962_o = 1'b0; + 23'b00000000000000000000001: n6962_o = 1'b0; + default: n6962_o = 1'bX; + endcase + /* T80_MCode.vhd:1573:25 */ + always @* + case (n6860_o) + 23'b10000000000000000000000: n6965_o = n6833_o; + 23'b01000000000000000000000: n6965_o = n6763_o; + 23'b00100000000000000000000: n6965_o = n6687_o; + 23'b00010000000000000000000: n6965_o = n6635_o; + 23'b00001000000000000000000: n6965_o = n6578_o; + 23'b00000100000000000000000: n6965_o = n6551_o; + 23'b00000010000000000000000: n6965_o = n6510_o; + 23'b00000001000000000000000: n6965_o = 3'b111; + 23'b00000000100000000000000: n6965_o = 3'b111; + 23'b00000000010000000000000: n6965_o = 3'b111; + 23'b00000000001000000000000: n6965_o = 3'b111; + 23'b00000000000100000000000: n6965_o = 3'b111; + 23'b00000000000010000000000: n6965_o = 3'b111; + 23'b00000000000001000000000: n6965_o = n6248_o; + 23'b00000000000000100000000: n6965_o = n6190_o; + 23'b00000000000000010000000: n6965_o = n6131_o; + 23'b00000000000000001000000: n6965_o = n6073_o; + 23'b00000000000000000100000: n6965_o = 3'b111; + 23'b00000000000000000010000: n6965_o = 3'b111; + 23'b00000000000000000001000: n6965_o = 3'b111; + 23'b00000000000000000000100: n6965_o = 3'b111; + 23'b00000000000000000000010: n6965_o = 3'b111; + 23'b00000000000000000000001: n6965_o = 3'b111; + default: n6965_o = 3'bX; + endcase + /* T80_MCode.vhd:1573:25 */ + always @* + case (n6860_o) + 23'b10000000000000000000000: n6968_o = n6836_o; + 23'b01000000000000000000000: n6968_o = n6766_o; + 23'b00100000000000000000000: n6968_o = n6690_o; + 23'b00010000000000000000000: n6968_o = n6638_o; + 23'b00001000000000000000000: n6968_o = 1'b0; + 23'b00000100000000000000000: n6968_o = 1'b0; + 23'b00000010000000000000000: n6968_o = 1'b0; + 23'b00000001000000000000000: n6968_o = 1'b0; + 23'b00000000100000000000000: n6968_o = 1'b0; + 23'b00000000010000000000000: n6968_o = 1'b0; + 23'b00000000001000000000000: n6968_o = 1'b0; + 23'b00000000000100000000000: n6968_o = 1'b0; + 23'b00000000000010000000000: n6968_o = 1'b0; + 23'b00000000000001000000000: n6968_o = 1'b0; + 23'b00000000000000100000000: n6968_o = 1'b0; + 23'b00000000000000010000000: n6968_o = 1'b0; + 23'b00000000000000001000000: n6968_o = 1'b0; + 23'b00000000000000000100000: n6968_o = 1'b0; + 23'b00000000000000000010000: n6968_o = 1'b0; + 23'b00000000000000000001000: n6968_o = 1'b0; + 23'b00000000000000000000100: n6968_o = 1'b0; + 23'b00000000000000000000010: n6968_o = 1'b0; + 23'b00000000000000000000001: n6968_o = 1'b0; + default: n6968_o = 1'bX; + endcase + /* T80_MCode.vhd:1573:25 */ + always @* + case (n6860_o) + 23'b10000000000000000000000: n6971_o = 1'b0; + 23'b01000000000000000000000: n6971_o = 1'b0; + 23'b00100000000000000000000: n6971_o = 1'b0; + 23'b00010000000000000000000: n6971_o = 1'b0; + 23'b00001000000000000000000: n6971_o = n6581_o; + 23'b00000100000000000000000: n6971_o = 1'b0; + 23'b00000010000000000000000: n6971_o = 1'b0; + 23'b00000001000000000000000: n6971_o = 1'b0; + 23'b00000000100000000000000: n6971_o = 1'b0; + 23'b00000000010000000000000: n6971_o = 1'b0; + 23'b00000000001000000000000: n6971_o = 1'b0; + 23'b00000000000100000000000: n6971_o = 1'b0; + 23'b00000000000010000000000: n6971_o = 1'b0; + 23'b00000000000001000000000: n6971_o = 1'b0; + 23'b00000000000000100000000: n6971_o = 1'b0; + 23'b00000000000000010000000: n6971_o = 1'b0; + 23'b00000000000000001000000: n6971_o = 1'b0; + 23'b00000000000000000100000: n6971_o = 1'b0; + 23'b00000000000000000010000: n6971_o = 1'b0; + 23'b00000000000000000001000: n6971_o = 1'b0; + 23'b00000000000000000000100: n6971_o = 1'b0; + 23'b00000000000000000000010: n6971_o = 1'b0; + 23'b00000000000000000000001: n6971_o = 1'b0; + default: n6971_o = 1'bX; + endcase + /* T80_MCode.vhd:1573:25 */ + always @* + case (n6860_o) + 23'b10000000000000000000000: n6974_o = 1'b0; + 23'b01000000000000000000000: n6974_o = 1'b0; + 23'b00100000000000000000000: n6974_o = 1'b0; + 23'b00010000000000000000000: n6974_o = 1'b0; + 23'b00001000000000000000000: n6974_o = n6584_o; + 23'b00000100000000000000000: n6974_o = 1'b0; + 23'b00000010000000000000000: n6974_o = 1'b0; + 23'b00000001000000000000000: n6974_o = 1'b0; + 23'b00000000100000000000000: n6974_o = 1'b0; + 23'b00000000010000000000000: n6974_o = 1'b0; + 23'b00000000001000000000000: n6974_o = 1'b0; + 23'b00000000000100000000000: n6974_o = 1'b0; + 23'b00000000000010000000000: n6974_o = 1'b0; + 23'b00000000000001000000000: n6974_o = 1'b0; + 23'b00000000000000100000000: n6974_o = 1'b0; + 23'b00000000000000010000000: n6974_o = n6134_o; + 23'b00000000000000001000000: n6974_o = n6076_o; + 23'b00000000000000000100000: n6974_o = 1'b0; + 23'b00000000000000000010000: n6974_o = 1'b0; + 23'b00000000000000000001000: n6974_o = 1'b0; + 23'b00000000000000000000100: n6974_o = 1'b0; + 23'b00000000000000000000010: n6974_o = 1'b0; + 23'b00000000000000000000001: n6974_o = 1'b0; + default: n6974_o = 1'bX; + endcase + /* T80_MCode.vhd:1573:25 */ + always @* + case (n6860_o) + 23'b10000000000000000000000: n6977_o = 1'b0; + 23'b01000000000000000000000: n6977_o = 1'b0; + 23'b00100000000000000000000: n6977_o = 1'b0; + 23'b00010000000000000000000: n6977_o = 1'b0; + 23'b00001000000000000000000: n6977_o = n6587_o; + 23'b00000100000000000000000: n6977_o = 1'b0; + 23'b00000010000000000000000: n6977_o = 1'b0; + 23'b00000001000000000000000: n6977_o = 1'b0; + 23'b00000000100000000000000: n6977_o = 1'b0; + 23'b00000000010000000000000: n6977_o = 1'b0; + 23'b00000000001000000000000: n6977_o = 1'b0; + 23'b00000000000100000000000: n6977_o = 1'b0; + 23'b00000000000010000000000: n6977_o = 1'b0; + 23'b00000000000001000000000: n6977_o = 1'b0; + 23'b00000000000000100000000: n6977_o = 1'b0; + 23'b00000000000000010000000: n6977_o = n6137_o; + 23'b00000000000000001000000: n6977_o = n6079_o; + 23'b00000000000000000100000: n6977_o = 1'b0; + 23'b00000000000000000010000: n6977_o = 1'b0; + 23'b00000000000000000001000: n6977_o = 1'b0; + 23'b00000000000000000000100: n6977_o = 1'b0; + 23'b00000000000000000000010: n6977_o = 1'b0; + 23'b00000000000000000000001: n6977_o = 1'b0; + default: n6977_o = 1'bX; + endcase + /* T80_MCode.vhd:1573:25 */ + always @* + case (n6860_o) + 23'b10000000000000000000000: n6984_o = 3'b000; + 23'b01000000000000000000000: n6984_o = 3'b000; + 23'b00100000000000000000000: n6984_o = 3'b000; + 23'b00010000000000000000000: n6984_o = 3'b000; + 23'b00001000000000000000000: n6984_o = 3'b000; + 23'b00000100000000000000000: n6984_o = 3'b000; + 23'b00000010000000000000000: n6984_o = 3'b000; + 23'b00000001000000000000000: n6984_o = 3'b000; + 23'b00000000100000000000000: n6984_o = 3'b000; + 23'b00000000010000000000000: n6984_o = 3'b000; + 23'b00000000001000000000000: n6984_o = 3'b000; + 23'b00000000000100000000000: n6984_o = 3'b000; + 23'b00000000000010000000000: n6984_o = 3'b000; + 23'b00000000000001000000000: n6984_o = 3'b000; + 23'b00000000000000100000000: n6984_o = 3'b000; + 23'b00000000000000010000000: n6984_o = 3'b000; + 23'b00000000000000001000000: n6984_o = 3'b000; + 23'b00000000000000000100000: n6984_o = 3'b111; + 23'b00000000000000000010000: n6984_o = 3'b110; + 23'b00000000000000000001000: n6984_o = 3'b101; + 23'b00000000000000000000100: n6984_o = 3'b100; + 23'b00000000000000000000010: n6984_o = 3'b000; + 23'b00000000000000000000001: n6984_o = 3'b000; + default: n6984_o = 3'bX; + endcase + /* T80_MCode.vhd:1573:25 */ + always @* + case (n6860_o) + 23'b10000000000000000000000: n6987_o = 1'b0; + 23'b01000000000000000000000: n6987_o = 1'b0; + 23'b00100000000000000000000: n6987_o = 1'b0; + 23'b00010000000000000000000: n6987_o = 1'b0; + 23'b00001000000000000000000: n6987_o = n6590_o; + 23'b00000100000000000000000: n6987_o = 1'b0; + 23'b00000010000000000000000: n6987_o = 1'b0; + 23'b00000001000000000000000: n6987_o = 1'b0; + 23'b00000000100000000000000: n6987_o = 1'b0; + 23'b00000000010000000000000: n6987_o = 1'b0; + 23'b00000000001000000000000: n6987_o = 1'b0; + 23'b00000000000100000000000: n6987_o = 1'b0; + 23'b00000000000010000000000: n6987_o = 1'b0; + 23'b00000000000001000000000: n6987_o = 1'b0; + 23'b00000000000000100000000: n6987_o = 1'b0; + 23'b00000000000000010000000: n6987_o = 1'b0; + 23'b00000000000000001000000: n6987_o = 1'b0; + 23'b00000000000000000100000: n6987_o = 1'b0; + 23'b00000000000000000010000: n6987_o = 1'b0; + 23'b00000000000000000001000: n6987_o = 1'b0; + 23'b00000000000000000000100: n6987_o = 1'b0; + 23'b00000000000000000000010: n6987_o = 1'b0; + 23'b00000000000000000000001: n6987_o = 1'b0; + default: n6987_o = 1'bX; + endcase + /* T80_MCode.vhd:1573:25 */ + always @* + case (n6860_o) + 23'b10000000000000000000000: n6990_o = 1'b0; + 23'b01000000000000000000000: n6990_o = 1'b0; + 23'b00100000000000000000000: n6990_o = 1'b0; + 23'b00010000000000000000000: n6990_o = 1'b0; + 23'b00001000000000000000000: n6990_o = 1'b0; + 23'b00000100000000000000000: n6990_o = 1'b0; + 23'b00000010000000000000000: n6990_o = 1'b0; + 23'b00000001000000000000000: n6990_o = 1'b0; + 23'b00000000100000000000000: n6990_o = 1'b0; + 23'b00000000010000000000000: n6990_o = 1'b0; + 23'b00000000001000000000000: n6990_o = 1'b0; + 23'b00000000000100000000000: n6990_o = 1'b0; + 23'b00000000000010000000000: n6990_o = 1'b0; + 23'b00000000000001000000000: n6990_o = 1'b0; + 23'b00000000000000100000000: n6990_o = n6193_o; + 23'b00000000000000010000000: n6990_o = 1'b0; + 23'b00000000000000001000000: n6990_o = 1'b0; + 23'b00000000000000000100000: n6990_o = 1'b0; + 23'b00000000000000000010000: n6990_o = 1'b0; + 23'b00000000000000000001000: n6990_o = 1'b0; + 23'b00000000000000000000100: n6990_o = 1'b0; + 23'b00000000000000000000010: n6990_o = 1'b0; + 23'b00000000000000000000001: n6990_o = 1'b0; + default: n6990_o = 1'bX; + endcase + /* T80_MCode.vhd:1573:25 */ + always @* + case (n6860_o) + 23'b10000000000000000000000: n6993_o = 1'b0; + 23'b01000000000000000000000: n6993_o = 1'b0; + 23'b00100000000000000000000: n6993_o = 1'b0; + 23'b00010000000000000000000: n6993_o = 1'b0; + 23'b00001000000000000000000: n6993_o = 1'b0; + 23'b00000100000000000000000: n6993_o = 1'b0; + 23'b00000010000000000000000: n6993_o = 1'b0; + 23'b00000001000000000000000: n6993_o = 1'b0; + 23'b00000000100000000000000: n6993_o = 1'b0; + 23'b00000000010000000000000: n6993_o = 1'b0; + 23'b00000000001000000000000: n6993_o = 1'b0; + 23'b00000000000100000000000: n6993_o = 1'b0; + 23'b00000000000010000000000: n6993_o = 1'b0; + 23'b00000000000001000000000: n6993_o = n6251_o; + 23'b00000000000000100000000: n6993_o = 1'b0; + 23'b00000000000000010000000: n6993_o = 1'b0; + 23'b00000000000000001000000: n6993_o = 1'b0; + 23'b00000000000000000100000: n6993_o = 1'b0; + 23'b00000000000000000010000: n6993_o = 1'b0; + 23'b00000000000000000001000: n6993_o = 1'b0; + 23'b00000000000000000000100: n6993_o = 1'b0; + 23'b00000000000000000000010: n6993_o = 1'b0; + 23'b00000000000000000000001: n6993_o = 1'b0; + default: n6993_o = 1'bX; + endcase + /* T80_MCode.vhd:1573:25 */ + always @* + case (n6860_o) + 23'b10000000000000000000000: n6996_o = n6839_o; + 23'b01000000000000000000000: n6996_o = n6769_o; + 23'b00100000000000000000000: n6996_o = 1'b0; + 23'b00010000000000000000000: n6996_o = 1'b0; + 23'b00001000000000000000000: n6996_o = 1'b0; + 23'b00000100000000000000000: n6996_o = 1'b0; + 23'b00000010000000000000000: n6996_o = 1'b0; + 23'b00000001000000000000000: n6996_o = 1'b0; + 23'b00000000100000000000000: n6996_o = 1'b0; + 23'b00000000010000000000000: n6996_o = 1'b0; + 23'b00000000001000000000000: n6996_o = 1'b0; + 23'b00000000000100000000000: n6996_o = 1'b0; + 23'b00000000000010000000000: n6996_o = 1'b0; + 23'b00000000000001000000000: n6996_o = 1'b0; + 23'b00000000000000100000000: n6996_o = 1'b0; + 23'b00000000000000010000000: n6996_o = 1'b0; + 23'b00000000000000001000000: n6996_o = 1'b0; + 23'b00000000000000000100000: n6996_o = 1'b0; + 23'b00000000000000000010000: n6996_o = 1'b0; + 23'b00000000000000000001000: n6996_o = 1'b0; + 23'b00000000000000000000100: n6996_o = 1'b0; + 23'b00000000000000000000010: n6996_o = 1'b0; + 23'b00000000000000000000001: n6996_o = 1'b0; + default: n6996_o = 1'bX; + endcase + /* T80_MCode.vhd:1573:25 */ + always @* + case (n6860_o) + 23'b10000000000000000000000: n6999_o = 1'b0; + 23'b01000000000000000000000: n6999_o = 1'b0; + 23'b00100000000000000000000: n6999_o = 1'b0; + 23'b00010000000000000000000: n6999_o = 1'b0; + 23'b00001000000000000000000: n6999_o = 1'b0; + 23'b00000100000000000000000: n6999_o = 1'b0; + 23'b00000010000000000000000: n6999_o = n6513_o; + 23'b00000001000000000000000: n6999_o = 1'b0; + 23'b00000000100000000000000: n6999_o = 1'b0; + 23'b00000000010000000000000: n6999_o = 1'b0; + 23'b00000000001000000000000: n6999_o = 1'b0; + 23'b00000000000100000000000: n6999_o = 1'b0; + 23'b00000000000010000000000: n6999_o = 1'b0; + 23'b00000000000001000000000: n6999_o = 1'b0; + 23'b00000000000000100000000: n6999_o = 1'b0; + 23'b00000000000000010000000: n6999_o = 1'b0; + 23'b00000000000000001000000: n6999_o = 1'b0; + 23'b00000000000000000100000: n6999_o = 1'b0; + 23'b00000000000000000010000: n6999_o = 1'b0; + 23'b00000000000000000001000: n6999_o = 1'b0; + 23'b00000000000000000000100: n6999_o = 1'b0; + 23'b00000000000000000000010: n6999_o = 1'b0; + 23'b00000000000000000000001: n6999_o = 1'b0; + default: n6999_o = 1'bX; + endcase + /* T80_MCode.vhd:1573:25 */ + always @* + case (n6860_o) + 23'b10000000000000000000000: n7002_o = 1'b0; + 23'b01000000000000000000000: n7002_o = 1'b0; + 23'b00100000000000000000000: n7002_o = 1'b0; + 23'b00010000000000000000000: n7002_o = 1'b0; + 23'b00001000000000000000000: n7002_o = 1'b0; + 23'b00000100000000000000000: n7002_o = n6554_o; + 23'b00000010000000000000000: n7002_o = 1'b0; + 23'b00000001000000000000000: n7002_o = 1'b0; + 23'b00000000100000000000000: n7002_o = 1'b0; + 23'b00000000010000000000000: n7002_o = 1'b0; + 23'b00000000001000000000000: n7002_o = 1'b0; + 23'b00000000000100000000000: n7002_o = 1'b0; + 23'b00000000000010000000000: n7002_o = 1'b0; + 23'b00000000000001000000000: n7002_o = 1'b0; + 23'b00000000000000100000000: n7002_o = 1'b0; + 23'b00000000000000010000000: n7002_o = 1'b0; + 23'b00000000000000001000000: n7002_o = 1'b0; + 23'b00000000000000000100000: n7002_o = 1'b0; + 23'b00000000000000000010000: n7002_o = 1'b0; + 23'b00000000000000000001000: n7002_o = 1'b0; + 23'b00000000000000000000100: n7002_o = 1'b0; + 23'b00000000000000000000010: n7002_o = 1'b0; + 23'b00000000000000000000001: n7002_o = 1'b0; + default: n7002_o = 1'bX; + endcase + /* T80_MCode.vhd:1573:25 */ + always @* + case (n6860_o) + 23'b10000000000000000000000: n7005_o = 1'b0; + 23'b01000000000000000000000: n7005_o = 1'b0; + 23'b00100000000000000000000: n7005_o = 1'b0; + 23'b00010000000000000000000: n7005_o = n6641_o; + 23'b00001000000000000000000: n7005_o = 1'b0; + 23'b00000100000000000000000: n7005_o = 1'b0; + 23'b00000010000000000000000: n7005_o = 1'b0; + 23'b00000001000000000000000: n7005_o = 1'b0; + 23'b00000000100000000000000: n7005_o = 1'b0; + 23'b00000000010000000000000: n7005_o = 1'b0; + 23'b00000000001000000000000: n7005_o = 1'b0; + 23'b00000000000100000000000: n7005_o = 1'b0; + 23'b00000000000010000000000: n7005_o = 1'b0; + 23'b00000000000001000000000: n7005_o = 1'b0; + 23'b00000000000000100000000: n7005_o = 1'b0; + 23'b00000000000000010000000: n7005_o = 1'b0; + 23'b00000000000000001000000: n7005_o = 1'b0; + 23'b00000000000000000100000: n7005_o = 1'b0; + 23'b00000000000000000010000: n7005_o = 1'b0; + 23'b00000000000000000001000: n7005_o = 1'b0; + 23'b00000000000000000000100: n7005_o = 1'b0; + 23'b00000000000000000000010: n7005_o = 1'b0; + 23'b00000000000000000000001: n7005_o = 1'b0; + default: n7005_o = 1'bX; + endcase + /* T80_MCode.vhd:1573:25 */ + always @* + case (n6860_o) + 23'b10000000000000000000000: n7008_o = n6842_o; + 23'b01000000000000000000000: n7008_o = n6772_o; + 23'b00100000000000000000000: n7008_o = n6693_o; + 23'b00010000000000000000000: n7008_o = n6644_o; + 23'b00001000000000000000000: n7008_o = 2'b00; + 23'b00000100000000000000000: n7008_o = 2'b00; + 23'b00000010000000000000000: n7008_o = 2'b00; + 23'b00000001000000000000000: n7008_o = n6465_o; + 23'b00000000100000000000000: n7008_o = n6380_o; + 23'b00000000010000000000000: n7008_o = 2'b00; + 23'b00000000001000000000000: n7008_o = 2'b00; + 23'b00000000000100000000000: n7008_o = 2'b00; + 23'b00000000000010000000000: n7008_o = 2'b00; + 23'b00000000000001000000000: n7008_o = 2'b00; + 23'b00000000000000100000000: n7008_o = 2'b00; + 23'b00000000000000010000000: n7008_o = 2'b00; + 23'b00000000000000001000000: n7008_o = 2'b00; + 23'b00000000000000000100000: n7008_o = 2'b00; + 23'b00000000000000000010000: n7008_o = 2'b00; + 23'b00000000000000000001000: n7008_o = 2'b00; + 23'b00000000000000000000100: n7008_o = 2'b00; + 23'b00000000000000000000010: n7008_o = 2'b00; + 23'b00000000000000000000001: n7008_o = 2'b00; + default: n7008_o = 2'bX; + endcase + /* T80_MCode.vhd:1573:25 */ + always @* + case (n6860_o) + 23'b10000000000000000000000: n7014_o = 2'b11; + 23'b01000000000000000000000: n7014_o = 2'b11; + 23'b00100000000000000000000: n7014_o = 2'b11; + 23'b00010000000000000000000: n7014_o = 2'b11; + 23'b00001000000000000000000: n7014_o = 2'b11; + 23'b00000100000000000000000: n7014_o = 2'b11; + 23'b00000010000000000000000: n7014_o = 2'b11; + 23'b00000001000000000000000: n7014_o = 2'b11; + 23'b00000000100000000000000: n7014_o = 2'b11; + 23'b00000000010000000000000: n7014_o = 2'b10; + 23'b00000000001000000000000: n7014_o = 2'b01; + 23'b00000000000100000000000: n7014_o = 2'b00; + 23'b00000000000010000000000: n7014_o = 2'b11; + 23'b00000000000001000000000: n7014_o = 2'b11; + 23'b00000000000000100000000: n7014_o = 2'b11; + 23'b00000000000000010000000: n7014_o = 2'b11; + 23'b00000000000000001000000: n7014_o = 2'b11; + 23'b00000000000000000100000: n7014_o = 2'b11; + 23'b00000000000000000010000: n7014_o = 2'b11; + 23'b00000000000000000001000: n7014_o = 2'b11; + 23'b00000000000000000000100: n7014_o = 2'b11; + 23'b00000000000000000000010: n7014_o = 2'b11; + 23'b00000000000000000000001: n7014_o = 2'b11; + default: n7014_o = 2'bX; + endcase + /* T80_MCode.vhd:1573:25 */ + always @* + case (n6860_o) + 23'b10000000000000000000000: n7017_o = n6845_o; + 23'b01000000000000000000000: n7017_o = n6775_o; + 23'b00100000000000000000000: n7017_o = 1'b0; + 23'b00010000000000000000000: n7017_o = 1'b0; + 23'b00001000000000000000000: n7017_o = 1'b0; + 23'b00000100000000000000000: n7017_o = n6557_o; + 23'b00000010000000000000000: n7017_o = n6516_o; + 23'b00000001000000000000000: n7017_o = n6469_o; + 23'b00000000100000000000000: n7017_o = n6384_o; + 23'b00000000010000000000000: n7017_o = 1'b0; + 23'b00000000001000000000000: n7017_o = 1'b0; + 23'b00000000000100000000000: n7017_o = 1'b0; + 23'b00000000000010000000000: n7017_o = 1'b0; + 23'b00000000000001000000000: n7017_o = n6255_o; + 23'b00000000000000100000000: n7017_o = n6196_o; + 23'b00000000000000010000000: n7017_o = 1'b0; + 23'b00000000000000001000000: n7017_o = 1'b0; + 23'b00000000000000000100000: n7017_o = 1'b0; + 23'b00000000000000000010000: n7017_o = 1'b0; + 23'b00000000000000000001000: n7017_o = 1'b0; + 23'b00000000000000000000100: n7017_o = 1'b0; + 23'b00000000000000000000010: n7017_o = 1'b0; + 23'b00000000000000000000001: n7017_o = 1'b0; + default: n7017_o = 1'bX; + endcase + /* T80_MCode.vhd:1573:25 */ + always @* + case (n6860_o) + 23'b10000000000000000000000: n7020_o = n6848_o; + 23'b01000000000000000000000: n7020_o = n6778_o; + 23'b00100000000000000000000: n7020_o = n6696_o; + 23'b00010000000000000000000: n7020_o = 1'b0; + 23'b00001000000000000000000: n7020_o = 1'b0; + 23'b00000100000000000000000: n7020_o = n6560_o; + 23'b00000010000000000000000: n7020_o = n6519_o; + 23'b00000001000000000000000: n7020_o = 1'b0; + 23'b00000000100000000000000: n7020_o = 1'b0; + 23'b00000000010000000000000: n7020_o = 1'b0; + 23'b00000000001000000000000: n7020_o = 1'b0; + 23'b00000000000100000000000: n7020_o = 1'b0; + 23'b00000000000010000000000: n7020_o = 1'b0; + 23'b00000000000001000000000: n7020_o = 1'b0; + 23'b00000000000000100000000: n7020_o = n6199_o; + 23'b00000000000000010000000: n7020_o = n6141_o; + 23'b00000000000000001000000: n7020_o = 1'b0; + 23'b00000000000000000100000: n7020_o = 1'b0; + 23'b00000000000000000010000: n7020_o = 1'b0; + 23'b00000000000000000001000: n7020_o = 1'b0; + 23'b00000000000000000000100: n7020_o = 1'b0; + 23'b00000000000000000000010: n7020_o = 1'b0; + 23'b00000000000000000000001: n7020_o = 1'b0; + default: n7020_o = 1'bX; + endcase + assign n7021_o = {n5482_o, n4394_o}; + /* T80_MCode.vhd:256:17 */ + always @* + case (n7021_o) + 2'b10: n7022_o = n5460_o; + 2'b01: n7022_o = n4156_o; + default: n7022_o = n6876_o; + endcase + /* T80_MCode.vhd:256:17 */ + always @* + case (n7021_o) + 2'b10: n7024_o = n5462_o; + 2'b01: n7024_o = n4161_o; + default: n7024_o = n6882_o; + endcase + /* T80_MCode.vhd:256:17 */ + always @* + case (n7021_o) + 2'b10: n7026_o = 2'b00; + 2'b01: n7026_o = n4167_o; + default: n7026_o = 2'b00; + endcase + /* T80_MCode.vhd:256:17 */ + always @* + case (n7021_o) + 2'b10: n7029_o = 1'b0; + 2'b01: n7029_o = n4170_o; + default: n7029_o = n6885_o; + endcase + /* T80_MCode.vhd:256:17 */ + always @* + case (n7021_o) + 2'b10: n7032_o = 1'b0; + 2'b01: n7032_o = n4173_o; + default: n7032_o = n6888_o; + endcase + assign n7034_o = n6894_o[1:0]; + /* T80_MCode.vhd:256:17 */ + always @* + case (n7021_o) + 2'b10: n7036_o = 2'b00; + 2'b01: n7036_o = n4185_o; + default: n7036_o = n7034_o; + endcase + assign n7037_o = n4197_o[0]; + assign n7038_o = n6894_o[2]; + /* T80_MCode.vhd:256:17 */ + always @* + case (n7021_o) + 2'b10: n7040_o = 1'b0; + 2'b01: n7040_o = n7037_o; + default: n7040_o = n7038_o; + endcase + assign n7041_o = n4197_o[1]; + /* T80_MCode.vhd:256:17 */ + always @* + case (n7021_o) + 2'b10: n7043_o = 1'b0; + 2'b01: n7043_o = n7041_o; + default: n7043_o = n6900_o; + endcase + /* T80_MCode.vhd:256:17 */ + always @* + case (n7021_o) + 2'b10: n7047_o = n5465_o; + 2'b01: n7047_o = n4206_o; + default: n7047_o = n6903_o; + endcase + /* T80_MCode.vhd:256:17 */ + always @* + case (n7021_o) + 2'b10: n7050_o = 1'b0; + 2'b01: n7050_o = n4209_o; + default: n7050_o = n6907_o; + endcase + /* T80_MCode.vhd:256:17 */ + always @* + case (n7021_o) + 2'b10: n7052_o = n4395_o; + 2'b01: n7052_o = n4213_o; + default: n7052_o = n6913_o; + endcase + /* T80_MCode.vhd:256:17 */ + always @* + case (n7021_o) + 2'b10: n7054_o = 1'b0; + 2'b01: n7054_o = n4217_o; + default: n7054_o = n6919_o; + endcase + assign n7057_o = n5467_o[0]; + /* T80_MCode.vhd:256:17 */ + always @* + case (n7021_o) + 2'b10: n7058_o = n7057_o; + 2'b01: n7058_o = n4242_o; + default: n7058_o = n6931_o; + endcase + assign n7059_o = n5467_o[2:1]; + /* T80_MCode.vhd:256:17 */ + always @* + case (n7021_o) + 2'b10: n7060_o = n7059_o; + 2'b01: n7060_o = n4267_o; + default: n7060_o = n6943_o; + endcase + /* T80_MCode.vhd:256:17 */ + always @* + case (n7021_o) + 2'b10: n7062_o = 1'b0; + 2'b01: n7062_o = n4286_o; + default: n7062_o = n6952_o; + endcase + /* T80_MCode.vhd:256:17 */ + always @* + case (n7021_o) + 2'b10: n7066_o = n5469_o; + 2'b01: n7066_o = n4292_o; + default: n7066_o = n6955_o; + endcase + /* T80_MCode.vhd:256:17 */ + always @* + case (n7021_o) + 2'b10: n7067_o = n5472_o; + 2'b01: n7067_o = n4300_o; + default: n7067_o = n6959_o; + endcase + /* T80_MCode.vhd:256:17 */ + always @* + case (n7021_o) + 2'b10: n7070_o = 1'b0; + 2'b01: n7070_o = n4305_o; + default: n7070_o = n6962_o; + endcase + /* T80_MCode.vhd:256:17 */ + always @* + case (n7021_o) + 2'b10: n7073_o = 1'b0; + 2'b01: n7073_o = n4308_o; + default: n7073_o = 1'b0; + endcase + /* T80_MCode.vhd:256:17 */ + always @* + case (n7021_o) + 2'b10: n7075_o = n5474_o; + 2'b01: n7075_o = n4311_o; + default: n7075_o = n6965_o; + endcase + /* T80_MCode.vhd:256:17 */ + always @* + case (n7021_o) + 2'b10: n7078_o = 1'b0; + 2'b01: n7078_o = n4314_o; + default: n7078_o = n6968_o; + endcase + /* T80_MCode.vhd:256:17 */ + always @* + case (n7021_o) + 2'b10: n7081_o = 1'b0; + 2'b01: n7081_o = n4317_o; + default: n7081_o = n6971_o; + endcase + /* T80_MCode.vhd:256:17 */ + always @* + case (n7021_o) + 2'b10: n7084_o = 1'b0; + 2'b01: n7084_o = n4320_o; + default: n7084_o = 1'b0; + endcase + /* T80_MCode.vhd:256:17 */ + always @* + case (n7021_o) + 2'b10: n7087_o = 1'b0; + 2'b01: n7087_o = n4324_o; + default: n7087_o = 1'b0; + endcase + /* T80_MCode.vhd:256:17 */ + always @* + case (n7021_o) + 2'b10: n7090_o = 1'b0; + 2'b01: n7090_o = n4327_o; + default: n7090_o = 1'b0; + endcase + /* T80_MCode.vhd:256:17 */ + always @* + case (n7021_o) + 2'b10: n7093_o = 1'b0; + 2'b01: n7093_o = n4330_o; + default: n7093_o = 1'b0; + endcase + /* T80_MCode.vhd:256:17 */ + always @* + case (n7021_o) + 2'b10: n7096_o = 1'b0; + 2'b01: n7096_o = n4333_o; + default: n7096_o = n6974_o; + endcase + /* T80_MCode.vhd:256:17 */ + always @* + case (n7021_o) + 2'b10: n7099_o = 1'b0; + 2'b01: n7099_o = n4336_o; + default: n7099_o = n6977_o; + endcase + /* T80_MCode.vhd:256:17 */ + always @* + case (n7021_o) + 2'b10: n7102_o = 1'b0; + 2'b01: n7102_o = n4340_o; + default: n7102_o = 1'b0; + endcase + /* T80_MCode.vhd:256:17 */ + always @* + case (n7021_o) + 2'b10: n7105_o = 3'b000; + 2'b01: n7105_o = 3'b000; + default: n7105_o = n6984_o; + endcase + /* T80_MCode.vhd:256:17 */ + always @* + case (n7021_o) + 2'b10: n7108_o = 1'b0; + 2'b01: n7108_o = n4344_o; + default: n7108_o = 1'b0; + endcase + /* T80_MCode.vhd:256:17 */ + always @* + case (n7021_o) + 2'b10: n7111_o = 1'b0; + 2'b01: n7111_o = n4348_o; + default: n7111_o = 1'b0; + endcase + /* T80_MCode.vhd:256:17 */ + always @* + case (n7021_o) + 2'b10: n7114_o = 1'b0; + 2'b01: n7114_o = n4352_o; + default: n7114_o = 1'b0; + endcase + /* T80_MCode.vhd:256:17 */ + always @* + case (n7021_o) + 2'b10: n7117_o = 1'b0; + 2'b01: n7117_o = n4356_o; + default: n7117_o = 1'b0; + endcase + /* T80_MCode.vhd:256:17 */ + always @* + case (n7021_o) + 2'b10: n7120_o = 1'b0; + 2'b01: n7120_o = n4359_o; + default: n7120_o = 1'b0; + endcase + /* T80_MCode.vhd:256:17 */ + always @* + case (n7021_o) + 2'b10: n7123_o = 1'b0; + 2'b01: n7123_o = n4363_o; + default: n7123_o = 1'b0; + endcase + /* T80_MCode.vhd:256:17 */ + always @* + case (n7021_o) + 2'b10: n7126_o = 1'b0; + 2'b01: n7126_o = n4367_o; + default: n7126_o = 1'b0; + endcase + /* T80_MCode.vhd:256:17 */ + always @* + case (n7021_o) + 2'b10: n7129_o = 1'b0; + 2'b01: n7129_o = n4371_o; + default: n7129_o = 1'b0; + endcase + /* T80_MCode.vhd:256:17 */ + always @* + case (n7021_o) + 2'b10: n7132_o = 1'b0; + 2'b01: n7132_o = 1'b0; + default: n7132_o = n6987_o; + endcase + /* T80_MCode.vhd:256:17 */ + always @* + case (n7021_o) + 2'b10: n7135_o = 1'b0; + 2'b01: n7135_o = 1'b0; + default: n7135_o = n6990_o; + endcase + /* T80_MCode.vhd:256:17 */ + always @* + case (n7021_o) + 2'b10: n7138_o = 1'b0; + 2'b01: n7138_o = 1'b0; + default: n7138_o = n6993_o; + endcase + /* T80_MCode.vhd:256:17 */ + always @* + case (n7021_o) + 2'b10: n7141_o = 1'b0; + 2'b01: n7141_o = 1'b0; + default: n7141_o = n6996_o; + endcase + /* T80_MCode.vhd:256:17 */ + always @* + case (n7021_o) + 2'b10: n7144_o = 1'b0; + 2'b01: n7144_o = 1'b0; + default: n7144_o = n6999_o; + endcase + /* T80_MCode.vhd:256:17 */ + always @* + case (n7021_o) + 2'b10: n7147_o = 1'b0; + 2'b01: n7147_o = 1'b0; + default: n7147_o = n7002_o; + endcase + /* T80_MCode.vhd:256:17 */ + always @* + case (n7021_o) + 2'b10: n7150_o = 1'b0; + 2'b01: n7150_o = 1'b0; + default: n7150_o = n7005_o; + endcase + /* T80_MCode.vhd:256:17 */ + always @* + case (n7021_o) + 2'b10: n7153_o = 2'b00; + 2'b01: n7153_o = n4374_o; + default: n7153_o = n7008_o; + endcase + /* T80_MCode.vhd:256:17 */ + always @* + case (n7021_o) + 2'b10: n7156_o = 1'b0; + 2'b01: n7156_o = n4378_o; + default: n7156_o = 1'b0; + endcase + /* T80_MCode.vhd:256:17 */ + always @* + case (n7021_o) + 2'b10: n7159_o = 1'b0; + 2'b01: n7159_o = n4382_o; + default: n7159_o = 1'b0; + endcase + /* T80_MCode.vhd:256:17 */ + always @* + case (n7021_o) + 2'b10: n7162_o = 2'b11; + 2'b01: n7162_o = 2'b11; + default: n7162_o = n7014_o; + endcase + /* T80_MCode.vhd:256:17 */ + always @* + case (n7021_o) + 2'b10: n7165_o = 1'b0; + 2'b01: n7165_o = n4386_o; + default: n7165_o = 1'b0; + endcase + /* T80_MCode.vhd:256:17 */ + always @* + case (n7021_o) + 2'b10: n7168_o = 1'b0; + 2'b01: n7168_o = n4389_o; + default: n7168_o = n7017_o; + endcase + /* T80_MCode.vhd:256:17 */ + always @* + case (n7021_o) + 2'b10: n7170_o = n5477_o; + 2'b01: n7170_o = n4392_o; + default: n7170_o = n7020_o; + endcase + /* T80_MCode.vhd:256:17 */ + always @* + case (n7021_o) + 2'b10: n7173_o = n5480_o; + 2'b01: n7173_o = 1'b0; + default: n7173_o = 1'b0; + endcase + /* T80_MCode.vhd:2003:35 */ + assign n7176_o = mcycle == 3'b110; + /* T80_MCode.vhd:2011:40 */ + assign n7178_o = ir == 8'b00110110; + /* T80_MCode.vhd:2011:60 */ + assign n7180_o = ir == 8'b11001011; + /* T80_MCode.vhd:2011:53 */ + assign n7181_o = n7178_o | n7180_o; + /* T80_MCode.vhd:2003:25 */ + assign n7183_o = n7186_o ? 3'b111 : n7075_o; + /* T80_MCode.vhd:2003:25 */ + assign n7185_o = n7176_o ? 1'b1 : n7029_o; + /* T80_MCode.vhd:2003:25 */ + assign n7186_o = n7176_o & n7181_o; + /* T80_MCode.vhd:2015:35 */ + assign n7188_o = mcycle == 3'b111; + /* T80_MCode.vhd:2019:41 */ + assign n7190_o = iset != 2'b01; + /* T80_MCode.vhd:2015:25 */ + assign n7192_o = n7209_o ? 3'b010 : n7183_o; + /* T80_MCode.vhd:2024:40 */ + assign n7195_o = ir == 8'b00110110; + /* T80_MCode.vhd:2024:61 */ + assign n7197_o = iset == 2'b01; + /* T80_MCode.vhd:2024:53 */ + assign n7198_o = n7195_o | n7197_o; + /* T80_MCode.vhd:2015:25 */ + assign n7200_o = n7205_o ? 1'b1 : n7185_o; + /* T80_MCode.vhd:2024:33 */ + assign n7202_o = n7198_o ? n7168_o : 1'b1; + /* T80_MCode.vhd:2015:25 */ + assign n7204_o = n7188_o ? 3'b101 : n7024_o; + /* T80_MCode.vhd:2015:25 */ + assign n7205_o = n7188_o & n7198_o; + assign n7206_o = {1'b0, n2194_o}; + assign n7207_o = {n7062_o, n7060_o, n7058_o}; + /* T80_MCode.vhd:2015:25 */ + assign n7208_o = n7188_o ? n7206_o : n7207_o; + /* T80_MCode.vhd:2015:25 */ + assign n7209_o = n7188_o & n7190_o; + /* T80_MCode.vhd:2015:25 */ + assign n7210_o = n7188_o ? n7202_o : n7168_o; + assign n7212_o = {n7043_o, n7040_o, n7036_o}; + assign n7213_o = {n7054_o, n7052_o}; +endmodule + +module t80_0_1_0_1_2_3_4_5_6_7 + (input reset_n, + input clk_n, + input cen, + input wait_n, + input int_n, + input nmi_n, + input busrq_n, + input [7:0] dinst, + input [7:0] di, + input out0, + input dirset, + input [211:0] dir, + output m1_n, + output iorq, + output noread, + output write, + output rfsh_n, + output halt_n, + output busak_n, + output [15:0] a, + output [7:0] dout, + output [2:0] mc, + output [2:0] ts, + output intcycle_n, + output inte, + output stop, + output [211:0] regs); + wire [7:0] acc; + wire [7:0] f; + wire [7:0] ap; + wire [7:0] fp; + wire [7:0] i; + wire [7:0] r; + wire [15:0] sp; + wire [15:0] pc; + wire [7:0] regdih; + wire [7:0] regdil; + wire [15:0] regbusa; + wire [15:0] regbusb; + wire [15:0] regbusc; + wire [2:0] regaddra_r; + wire [2:0] regaddra; + wire [2:0] regaddrb_r; + wire [2:0] regaddrb; + wire [2:0] regaddrc; + wire regweh; + wire regwel; + wire alternate; + wire [15:0] wz; + wire [7:0] ir; + wire [1:0] iset; + wire [15:0] regbusa_r; + wire [15:0] id16; + wire [7:0] save_mux; + wire [2:0] tstate; + wire [2:0] mcycle; + wire inte_ff1; + wire inte_ff2; + wire halt_ff; + wire busreq_s; + wire busack; + wire clken; + wire nmi_s; + wire [1:0] istatus; + wire [7:0] di_reg; + wire t_res; + wire [1:0] xy_state; + wire [2:0] pre_xy_f_m; + wire nextis_xy_fetch; + wire xy_ind; + wire no_btr; + wire btr_r; + wire auto_wait; + wire auto_wait_t1; + wire auto_wait_t2; + wire incdecz; + wire [7:0] busb; + wire [7:0] busa; + wire [7:0] alu_q; + wire [7:0] f_out; + wire [4:0] read_to_reg_r; + wire arith16_r; + wire z16_r; + wire [3:0] alu_op_r; + wire save_alu_r; + wire preservec_r; + wire [2:0] mcycles; + wire [2:0] mcycles_d; + wire [2:0] tstates; + wire intcycle; + wire nmicycle; + wire inc_pc; + wire inc_wz; + wire [3:0] incdec_16; + wire [1:0] prefix; + wire read_to_acc; + wire read_to_reg; + wire [3:0] set_busb_to; + wire [3:0] set_busa_to; + wire [3:0] alu_op; + wire save_alu; + wire preservec; + wire arith16; + wire [2:0] set_addr_to; + wire jump; + wire jumpe; + wire jumpxy; + wire call; + wire rstp; + wire ldz; + wire ldw; + wire ldsphl; + wire iorq_i; + wire [2:0] special_ld; + wire exchangedh; + wire exchangerp; + wire exchangeaf; + wire exchangers; + wire i_djnz; + wire i_cpl; + wire i_ccf; + wire i_scf; + wire i_retn; + wire i_bt; + wire i_bc; + wire i_btr; + wire i_rld; + wire i_rrd; + wire i_rxdd; + wire i_inrc; + wire [1:0] setwz; + wire setdi; + wire setei; + wire [1:0] imode; + wire halt; + wire xybit_undoc; + wire [127:0] dor; + wire [1:0] n171_o; + wire [3:0] n172_o; + wire [131:0] n173_o; + wire [147:0] n174_o; + wire [163:0] n175_o; + wire [171:0] n176_o; + wire [179:0] n177_o; + wire [187:0] n178_o; + wire [195:0] n179_o; + wire [203:0] n180_o; + wire [211:0] n181_o; + wire n182_o; + wire [211:0] n183_o; + wire [1:0] n184_o; + wire [3:0] n185_o; + wire [15:0] n186_o; + wire [19:0] n187_o; + wire [47:0] n188_o; + wire [67:0] n189_o; + wire [15:0] n190_o; + wire [83:0] n191_o; + wire [47:0] n192_o; + wire [131:0] n193_o; + wire [147:0] n194_o; + wire [163:0] n195_o; + wire [171:0] n196_o; + wire [179:0] n197_o; + wire [187:0] n198_o; + wire [195:0] n199_o; + wire [203:0] n200_o; + wire [211:0] n201_o; + wire [2:0] mcode_n202; + wire [2:0] mcode_n203; + wire [1:0] mcode_n204; + wire mcode_n205; + wire mcode_n206; + wire [3:0] mcode_n207; + wire mcode_n208; + wire mcode_n209; + wire [3:0] mcode_n210; + wire [3:0] mcode_n211; + wire [3:0] mcode_n212; + wire mcode_n213; + wire mcode_n214; + wire mcode_n215; + wire [2:0] mcode_n216; + wire mcode_n217; + wire mcode_n218; + wire mcode_n219; + wire mcode_n220; + wire mcode_n221; + wire mcode_n222; + wire mcode_n223; + wire mcode_n224; + wire mcode_n225; + wire [2:0] mcode_n226; + wire mcode_n227; + wire mcode_n228; + wire mcode_n229; + wire mcode_n230; + wire mcode_n231; + wire mcode_n232; + wire mcode_n233; + wire mcode_n234; + wire mcode_n235; + wire mcode_n236; + wire mcode_n237; + wire mcode_n238; + wire mcode_n239; + wire mcode_n240; + wire mcode_n241; + wire [1:0] mcode_n242; + wire mcode_n243; + wire mcode_n244; + wire [1:0] mcode_n245; + wire mcode_n246; + wire mcode_n247; + wire mcode_n248; + wire mcode_n249; + wire [2:0] mcode_mcycles; + wire [2:0] mcode_tstates; + wire [1:0] mcode_prefix; + wire mcode_inc_pc; + wire mcode_inc_wz; + wire [3:0] mcode_incdec_16; + wire mcode_read_to_reg; + wire mcode_read_to_acc; + wire [3:0] mcode_set_busa_to; + wire [3:0] mcode_set_busb_to; + wire [3:0] mcode_alu_op; + wire mcode_save_alu; + wire mcode_preservec; + wire mcode_arith16; + wire [2:0] mcode_set_addr_to; + wire mcode_iorq; + wire mcode_jump; + wire mcode_jumpe; + wire mcode_jumpxy; + wire mcode_call; + wire mcode_rstp; + wire mcode_ldz; + wire mcode_ldw; + wire mcode_ldsphl; + wire [2:0] mcode_special_ld; + wire mcode_exchangedh; + wire mcode_exchangerp; + wire mcode_exchangeaf; + wire mcode_exchangers; + wire mcode_i_djnz; + wire mcode_i_cpl; + wire mcode_i_ccf; + wire mcode_i_scf; + wire mcode_i_retn; + wire mcode_i_bt; + wire mcode_i_bc; + wire mcode_i_btr; + wire mcode_i_rld; + wire mcode_i_rrd; + wire mcode_i_inrc; + wire [1:0] mcode_setwz; + wire mcode_setdi; + wire mcode_setei; + wire [1:0] mcode_imode; + wire mcode_halt; + wire mcode_noread; + wire mcode_write; + wire mcode_xybit_undoc; + wire [5:0] n346_o; + wire [7:0] u_alu_n347; + wire [7:0] u_alu_n348; + wire [7:0] u_alu_q; + wire [7:0] u_alu_f_out; + wire n353_o; + wire n354_o; + wire n356_o; + wire n357_o; + wire n361_o; + wire n362_o; + wire n363_o; + wire n365_o; + wire n367_o; + wire n369_o; + wire n370_o; + wire n371_o; + wire n373_o; + wire n375_o; + wire n376_o; + wire n377_o; + wire n378_o; + wire n379_o; + wire [7:0] n381_o; + wire n382_o; + wire [7:0] n383_o; + wire n388_o; + wire [7:0] n390_o; + wire [7:0] n391_o; + wire [7:0] n392_o; + wire [7:0] n393_o; + wire [7:0] n394_o; + wire [7:0] n395_o; + wire [15:0] n396_o; + wire [15:0] n397_o; + wire [15:0] n398_o; + wire [1:0] n399_o; + wire n401_o; + wire [1:0] n402_o; + wire n404_o; + wire n405_o; + wire n406_o; + wire n407_o; + wire n408_o; + wire n409_o; + wire n411_o; + wire n412_o; + wire n415_o; + wire n417_o; + wire n418_o; + wire n419_o; + wire n420_o; + wire n422_o; + wire n423_o; + wire [6:0] n424_o; + wire [6:0] n426_o; + wire n427_o; + wire n428_o; + wire n429_o; + wire n430_o; + wire n431_o; + wire n432_o; + wire n433_o; + wire n434_o; + wire n435_o; + wire n436_o; + wire [15:0] n438_o; + wire [15:0] n439_o; + wire n441_o; + wire n442_o; + wire n444_o; + wire n445_o; + wire n446_o; + wire n447_o; + wire [7:0] n449_o; + wire [7:0] n451_o; + wire n453_o; + wire n455_o; + wire n456_o; + wire [1:0] n459_o; + wire n461_o; + wire [1:0] n463_o; + wire n465_o; + wire [1:0] n467_o; + wire [1:0] n468_o; + wire n469_o; + wire [1:0] n471_o; + wire [1:0] n474_o; + wire n476_o; + wire [15:0] n477_o; + wire [15:0] n478_o; + wire [6:0] n479_o; + wire [6:0] n480_o; + wire n481_o; + wire [7:0] n482_o; + wire [1:0] n483_o; + wire [1:0] n484_o; + wire n485_o; + wire n487_o; + wire n489_o; + wire [1:0] n491_o; + wire n492_o; + wire n494_o; + wire n495_o; + wire n496_o; + wire n497_o; + wire n498_o; + wire [7:0] n499_o; + wire [7:0] n500_o; + wire n501_o; + wire n502_o; + wire n503_o; + wire n505_o; + wire n506_o; + wire n508_o; + wire n509_o; + wire [7:0] n510_o; + wire [7:0] n511_o; + wire n513_o; + wire [15:0] n514_o; + wire [15:0] n515_o; + wire n517_o; + wire [15:0] n518_o; + wire [15:0] n521_o; + wire n523_o; + wire n525_o; + wire n527_o; + wire [15:0] n530_o; + wire [15:0] n531_o; + wire n533_o; + wire [7:0] n534_o; + wire [7:0] n537_o; + wire [15:0] n538_o; + wire [15:0] n539_o; + wire n541_o; + wire n543_o; + wire [7:0] n544_o; + wire [7:0] n547_o; + wire [15:0] n548_o; + wire [15:0] n549_o; + wire n551_o; + wire [15:0] n553_o; + wire [7:0] n554_o; + wire n556_o; + wire [7:0] n557_o; + wire [7:0] n560_o; + wire [15:0] n561_o; + wire [15:0] n562_o; + wire [15:0] n563_o; + wire [15:0] n564_o; + wire [15:0] n565_o; + wire n567_o; + wire [5:0] n568_o; + wire [7:0] n569_o; + wire [7:0] n570_o; + wire [7:0] n571_o; + wire [7:0] n572_o; + wire [7:0] n573_o; + wire [7:0] n574_o; + reg [7:0] n575_o; + wire [7:0] n576_o; + wire [7:0] n577_o; + wire [7:0] n578_o; + wire [7:0] n579_o; + wire [7:0] n580_o; + wire [7:0] n581_o; + reg [7:0] n582_o; + reg [15:0] n583_o; + wire [15:0] n584_o; + wire [15:0] n585_o; + wire [15:0] n586_o; + wire [15:0] n587_o; + wire [15:0] n588_o; + wire [15:0] n589_o; + wire [15:0] n591_o; + wire [15:0] n593_o; + wire [15:0] n594_o; + wire [15:0] n595_o; + wire [15:0] n596_o; + wire [15:0] n597_o; + wire [15:0] n598_o; + wire [15:0] n599_o; + wire [15:0] n600_o; + wire [15:0] n601_o; + wire [15:0] n602_o; + wire [15:0] n603_o; + wire [15:0] n604_o; + wire [15:0] n605_o; + wire n607_o; + wire [15:0] n608_o; + wire [7:0] n609_o; + wire n610_o; + wire n611_o; + wire n613_o; + wire n614_o; + wire [7:0] n616_o; + wire [2:0] n617_o; + wire n618_o; + wire n619_o; + wire n622_o; + wire n623_o; + wire n624_o; + wire n625_o; + wire n626_o; + wire [1:0] n628_o; + wire [2:0] n629_o; + wire n630_o; + wire [1:0] n631_o; + wire [1:0] n632_o; + wire n635_o; + wire n637_o; + wire [1:0] n639_o; + wire [2:0] n640_o; + wire [1:0] n641_o; + wire [15:0] n643_o; + wire n644_o; + wire [1:0] n645_o; + wire [1:0] n646_o; + wire [15:0] n649_o; + wire [15:0] n650_o; + wire n651_o; + wire [3:0] n653_o; + wire n655_o; + wire n657_o; + wire n658_o; + wire n659_o; + wire n660_o; + wire n662_o; + wire n663_o; + wire n664_o; + wire n665_o; + wire n666_o; + wire n667_o; + wire [8:0] n669_o; + wire [7:0] n670_o; + wire [8:0] n672_o; + wire [8:0] n673_o; + wire n674_o; + wire n675_o; + wire n676_o; + wire [8:0] n678_o; + wire [8:0] n680_o; + wire [8:0] n681_o; + wire n682_o; + wire n683_o; + wire n684_o; + wire n685_o; + wire n686_o; + wire n687_o; + wire n688_o; + wire n689_o; + wire n690_o; + wire n691_o; + wire n692_o; + wire n693_o; + wire n694_o; + wire n695_o; + wire n696_o; + wire n697_o; + wire [2:0] n698_o; + wire n699_o; + wire [2:0] n700_o; + wire [2:0] n701_o; + wire n702_o; + wire n703_o; + wire n704_o; + wire n705_o; + wire n706_o; + wire n707_o; + wire n708_o; + wire n709_o; + wire n710_o; + wire n711_o; + wire n712_o; + wire n713_o; + wire n714_o; + wire n715_o; + wire n716_o; + wire n717_o; + wire n718_o; + wire n719_o; + wire n720_o; + wire n721_o; + wire n722_o; + wire n723_o; + wire n724_o; + wire n725_o; + wire n726_o; + wire n727_o; + wire n728_o; + wire n729_o; + wire n732_o; + wire n733_o; + wire n735_o; + wire n737_o; + wire n738_o; + wire [7:0] n739_o; + wire [15:0] n740_o; + wire [15:0] n741_o; + wire [15:0] n742_o; + wire [15:0] n743_o; + wire [15:0] n745_o; + wire [15:0] n746_o; + wire [15:0] n747_o; + wire [15:0] n748_o; + wire [15:0] n750_o; + wire [15:0] n751_o; + wire [2:0] n752_o; + localparam [15:0] n753_o = 16'b0000000000000000; + wire [9:0] n754_o; + wire [2:0] n755_o; + wire [15:0] n756_o; + wire [15:0] n757_o; + wire [15:0] n758_o; + wire [15:0] n759_o; + wire n760_o; + wire n762_o; + wire n764_o; + wire n765_o; + wire [15:0] n766_o; + wire [15:0] n767_o; + wire [15:0] n768_o; + wire n770_o; + wire n772_o; + wire n773_o; + wire n774_o; + wire n775_o; + wire n776_o; + wire [15:0] n779_o; + wire [15:0] n780_o; + wire n781_o; + wire n783_o; + wire n784_o; + wire n786_o; + wire n788_o; + wire n789_o; + wire n790_o; + wire [2:0] n791_o; + wire n793_o; + wire n794_o; + wire [15:0] n796_o; + wire [15:0] n798_o; + wire [15:0] n799_o; + wire [15:0] n800_o; + wire n801_o; + wire [15:0] n802_o; + wire [7:0] n803_o; + wire [1:0] n804_o; + wire [7:0] n805_o; + wire [7:0] n807_o; + wire [7:0] n808_o; + wire n809_o; + wire n810_o; + wire [15:0] n811_o; + wire [7:0] n812_o; + wire [7:0] n814_o; + wire [7:0] n815_o; + wire n817_o; + wire [15:0] n818_o; + wire [15:0] n819_o; + wire n820_o; + wire [15:0] n821_o; + wire [7:0] n822_o; + wire [1:0] n823_o; + wire n824_o; + wire n825_o; + wire n826_o; + wire [3:0] n828_o; + wire n831_o; + wire n835_o; + wire [7:0] n836_o; + wire [7:0] n837_o; + wire [7:0] n838_o; + wire [7:0] n839_o; + wire [7:0] n840_o; + wire [7:0] n841_o; + wire [7:0] n842_o; + wire [7:0] n843_o; + wire [7:0] n844_o; + wire [7:0] n845_o; + wire [7:0] n846_o; + wire [7:0] n847_o; + wire [7:0] n848_o; + wire [7:0] n849_o; + wire [7:0] n850_o; + wire [7:0] n851_o; + wire [7:0] n852_o; + wire [7:0] n853_o; + wire [7:0] n854_o; + wire [7:0] n855_o; + wire [7:0] n856_o; + wire [7:0] n857_o; + wire [7:0] n858_o; + wire [7:0] n859_o; + wire [7:0] n860_o; + wire [7:0] n861_o; + wire [7:0] n862_o; + wire [7:0] n863_o; + wire [7:0] n864_o; + wire [7:0] n865_o; + wire [7:0] n866_o; + wire [7:0] n867_o; + wire [7:0] n868_o; + wire [7:0] n869_o; + wire [7:0] n870_o; + wire [7:0] n871_o; + wire [7:0] n872_o; + wire [7:0] n873_o; + wire [7:0] n874_o; + wire [7:0] n875_o; + wire [7:0] n876_o; + wire [7:0] n877_o; + wire [7:0] n878_o; + wire [7:0] n879_o; + wire [7:0] n880_o; + wire [7:0] n881_o; + wire [7:0] n882_o; + wire [7:0] n883_o; + wire [7:0] n884_o; + wire [7:0] n885_o; + wire [7:0] n886_o; + wire [7:0] n887_o; + wire [7:0] n888_o; + wire [7:0] n889_o; + wire [7:0] n890_o; + wire [7:0] n891_o; + wire [7:0] n892_o; + wire [7:0] n893_o; + wire [7:0] n894_o; + wire [7:0] n895_o; + wire [7:0] n896_o; + wire [7:0] n897_o; + wire [7:0] n898_o; + wire [7:0] n899_o; + wire [7:0] n900_o; + wire [7:0] n901_o; + wire [7:0] n902_o; + wire [7:0] n903_o; + wire [7:0] n904_o; + wire [7:0] n905_o; + wire [7:0] n906_o; + wire [7:0] n907_o; + wire [7:0] n908_o; + wire [7:0] n909_o; + wire [7:0] n910_o; + wire [7:0] n911_o; + wire [7:0] n912_o; + wire [7:0] n913_o; + wire [7:0] n914_o; + wire [7:0] n915_o; + wire [7:0] n916_o; + wire [7:0] n917_o; + wire [7:0] n918_o; + wire [7:0] n919_o; + wire n920_o; + wire [1:0] n921_o; + wire n922_o; + wire n924_o; + wire n927_o; + wire n928_o; + wire n930_o; + wire n933_o; + wire n934_o; + wire n936_o; + wire n939_o; + wire n940_o; + wire n942_o; + wire n945_o; + wire n947_o; + wire [2:0] n948_o; + reg [7:0] n949_o; + wire n950_o; + wire n951_o; + wire n952_o; + wire n953_o; + wire n954_o; + reg n955_o; + wire n956_o; + wire n957_o; + wire n958_o; + wire n959_o; + wire n960_o; + reg n961_o; + wire n962_o; + wire n963_o; + wire n964_o; + wire n965_o; + wire n966_o; + reg n967_o; + wire n968_o; + wire n969_o; + wire n970_o; + wire n971_o; + wire n972_o; + reg n973_o; + wire n974_o; + wire n975_o; + wire n976_o; + wire n977_o; + wire n978_o; + reg n979_o; + wire n980_o; + wire n981_o; + wire n982_o; + wire n983_o; + wire n984_o; + reg n985_o; + wire n986_o; + wire n987_o; + wire n988_o; + wire n989_o; + wire n990_o; + reg n991_o; + reg [7:0] n992_o; + wire n993_o; + wire [7:0] n994_o; + reg [7:0] n995_o; + wire [7:0] n996_o; + wire [6:0] n997_o; + wire [6:0] n998_o; + wire [6:0] n999_o; + wire [6:0] n1000_o; + wire [6:0] n1001_o; + wire [6:0] n1002_o; + wire [6:0] n1003_o; + wire [7:0] n1004_o; + wire n1005_o; + wire [7:0] n1006_o; + wire [7:0] n1007_o; + wire n1008_o; + wire [6:0] n1009_o; + wire [6:0] n1010_o; + wire [6:0] n1011_o; + wire [6:0] n1012_o; + wire [6:0] n1013_o; + wire [6:0] n1014_o; + wire n1015_o; + wire n1016_o; + wire n1017_o; + wire n1018_o; + wire n1019_o; + wire n1020_o; + wire n1021_o; + wire [7:0] n1022_o; + wire [7:0] n1023_o; + wire [15:0] n1024_o; + wire [15:0] n1025_o; + wire n1026_o; + wire n1027_o; + wire n1029_o; + wire n1030_o; + wire [6:0] n1031_o; + wire n1032_o; + wire n1033_o; + wire n1034_o; + wire [7:0] n1035_o; + wire [7:0] n1036_o; + wire n1038_o; + wire n1041_o; + wire n1042_o; + wire n1044_o; + wire n1047_o; + wire n1048_o; + wire n1049_o; + wire n1050_o; + wire n1051_o; + wire n1052_o; + wire n1053_o; + wire n1054_o; + wire n1055_o; + wire n1056_o; + wire n1057_o; + wire n1058_o; + wire n1059_o; + wire n1060_o; + wire n1061_o; + wire n1062_o; + wire n1063_o; + wire n1064_o; + wire [6:0] n1065_o; + wire n1070_o; + wire n1071_o; + wire n1072_o; + wire n1074_o; + wire n1075_o; + wire n1076_o; + wire n1077_o; + wire n1078_o; + wire [7:0] n1079_o; + wire [3:0] n1080_o; + wire [3:0] n1081_o; + wire [7:0] n1082_o; + wire [7:0] n1083_o; + wire [3:0] n1084_o; + wire [3:0] n1085_o; + wire [7:0] n1086_o; + wire [7:0] n1087_o; + wire [7:0] n1088_o; + wire n1089_o; + wire [4:0] n1092_o; + wire [4:0] n1093_o; + wire [4:0] n1094_o; + wire [4:0] n1096_o; + wire n1099_o; + wire n1100_o; + wire n1101_o; + wire n1102_o; + wire [2:0] n1105_o; + wire n1106_o; + wire n1107_o; + wire n1108_o; + wire n1109_o; + wire n1110_o; + wire n1111_o; + wire [1:0] n1123_o; + wire [1:0] n1124_o; + wire [1:0] n1125_o; + wire [1:0] n1126_o; + wire [1:0] n1127_o; + wire n1128_o; + wire n1129_o; + wire n1130_o; + wire n1131_o; + wire n1132_o; + wire n1134_o; + wire n1135_o; + wire n1136_o; + wire [7:0] n1138_o; + wire [7:0] n1139_o; + wire n1140_o; + wire n1141_o; + wire n1142_o; + wire n1143_o; + wire n1144_o; + wire n1145_o; + wire n1146_o; + wire n1147_o; + wire n1148_o; + wire n1149_o; + wire n1150_o; + wire n1151_o; + wire n1152_o; + wire n1153_o; + wire n1154_o; + wire n1155_o; + wire n1156_o; + wire n1157_o; + wire n1165_o; + wire n1166_o; + wire n1167_o; + wire n1168_o; + wire n1169_o; + wire n1170_o; + wire n1171_o; + wire n1173_o; + wire n1174_o; + wire n1176_o; + wire n1177_o; + wire n1178_o; + wire n1179_o; + wire n1180_o; + wire n1182_o; + wire n1183_o; + wire n1184_o; + wire n1186_o; + wire n1188_o; + wire n1190_o; + wire n1192_o; + wire n1194_o; + wire [4:0] n1195_o; + reg [7:0] n1196_o; + reg [7:0] n1197_o; + wire [7:0] n1198_o; + reg [7:0] n1199_o; + wire [7:0] n1200_o; + wire [7:0] n1201_o; + wire [7:0] n1202_o; + wire [7:0] n1203_o; + wire [7:0] n1204_o; + wire [7:0] n1205_o; + wire [7:0] n1206_o; + wire [7:0] n1207_o; + wire [7:0] n1208_o; + reg [7:0] n1209_o; + wire [7:0] n1210_o; + wire [7:0] n1211_o; + wire [7:0] n1212_o; + wire [7:0] n1213_o; + wire [7:0] n1214_o; + wire [7:0] n1215_o; + wire [7:0] n1216_o; + wire [7:0] n1217_o; + wire [7:0] n1218_o; + reg [7:0] n1219_o; + wire [7:0] n1220_o; + wire [7:0] n1221_o; + wire [7:0] n1222_o; + wire [7:0] n1223_o; + wire [7:0] n1224_o; + wire [15:0] n1225_o; + wire [15:0] n1226_o; + wire [15:0] n1227_o; + wire [7:0] n1228_o; + wire [7:0] n1229_o; + wire [7:0] n1230_o; + wire [7:0] n1231_o; + wire [7:0] n1232_o; + wire n1233_o; + wire [7:0] n1234_o; + wire [15:0] n1235_o; + wire [15:0] n1236_o; + wire n1237_o; + wire [15:0] n1238_o; + wire [7:0] n1239_o; + wire [1:0] n1240_o; + wire n1241_o; + wire n1242_o; + wire n1243_o; + wire n1244_o; + wire [4:0] n1245_o; + wire n1246_o; + wire n1247_o; + wire [3:0] n1248_o; + wire n1249_o; + wire n1250_o; + wire [2:0] n1251_o; + wire n1252_o; + wire [15:0] n1255_o; + wire [7:0] n1256_o; + wire [7:0] n1257_o; + wire [7:0] n1258_o; + wire [7:0] n1259_o; + wire [7:0] n1260_o; + wire [7:0] n1261_o; + wire [7:0] n1262_o; + wire [15:0] n1263_o; + wire [15:0] n1264_o; + wire n1265_o; + wire [15:0] n1266_o; + wire [7:0] n1267_o; + wire [1:0] n1268_o; + wire [1:0] n1269_o; + wire [1:0] n1270_o; + wire n1271_o; + wire n1272_o; + wire [4:0] n1273_o; + wire n1274_o; + wire n1275_o; + wire [3:0] n1276_o; + wire n1277_o; + wire n1278_o; + wire [2:0] n1279_o; + wire n1280_o; + wire [1:0] n1375_o; + wire [2:0] n1376_o; + wire n1377_o; + wire n1379_o; + wire n1380_o; + wire [1:0] n1381_o; + wire n1383_o; + wire n1384_o; + wire n1385_o; + wire [2:0] n1387_o; + wire [2:0] n1388_o; + wire [1:0] n1389_o; + wire [2:0] n1390_o; + wire n1391_o; + wire n1393_o; + wire n1394_o; + wire [1:0] n1395_o; + wire n1397_o; + wire n1398_o; + wire n1399_o; + wire [2:0] n1401_o; + wire [2:0] n1402_o; + wire [1:0] n1403_o; + wire [2:0] n1404_o; + wire n1405_o; + wire [2:0] n1407_o; + wire [2:0] n1408_o; + wire n1409_o; + wire n1411_o; + wire n1412_o; + wire n1414_o; + wire n1415_o; + wire n1416_o; + wire [2:0] n1418_o; + wire [2:0] n1419_o; + wire n1420_o; + wire n1422_o; + wire n1423_o; + wire n1424_o; + wire n1426_o; + wire n1428_o; + wire n1430_o; + wire n1431_o; + wire n1432_o; + wire [2:0] n1433_o; + wire n1435_o; + wire n1436_o; + wire n1438_o; + wire n1441_o; + wire n1442_o; + wire [1:0] n1454_o; + wire [2:0] n1455_o; + wire n1457_o; + wire n1459_o; + wire n1461_o; + wire n1462_o; + wire n1463_o; + wire n1464_o; + wire n1465_o; + wire n1467_o; + wire n1468_o; + wire [2:0] n1469_o; + wire n1470_o; + wire [2:0] n1472_o; + wire n1474_o; + wire n1476_o; + wire n1478_o; + wire n1479_o; + wire n1480_o; + wire n1481_o; + wire n1482_o; + wire [1:0] n1483_o; + wire n1485_o; + wire n1486_o; + wire [2:0] n1487_o; + wire [2:0] n1489_o; + wire n1491_o; + wire n1492_o; + wire [2:0] n1493_o; + wire [2:0] n1495_o; + wire n1497_o; + wire n1498_o; + wire [2:0] n1499_o; + wire [2:0] n1501_o; + wire n1503_o; + wire n1504_o; + wire [2:0] n1505_o; + wire [15:0] n1507_o; + wire n1508_o; + wire [15:0] n1509_o; + wire [15:0] n1511_o; + wire n1515_o; + wire n1516_o; + wire n1517_o; + wire n1518_o; + wire n1519_o; + wire n1521_o; + wire n1522_o; + wire n1523_o; + wire n1524_o; + wire n1525_o; + wire n1526_o; + wire n1528_o; + wire n1530_o; + wire n1531_o; + wire n1533_o; + wire n1534_o; + wire n1536_o; + wire n1537_o; + wire n1539_o; + wire n1540_o; + wire n1542_o; + wire n1543_o; + reg n1545_o; + reg n1547_o; + wire n1549_o; + wire n1552_o; + wire n1555_o; + wire n1557_o; + wire n1558_o; + wire n1559_o; + wire n1561_o; + wire n1563_o; + wire n1564_o; + wire n1566_o; + wire n1567_o; + wire n1569_o; + wire n1570_o; + wire n1572_o; + wire n1574_o; + wire n1575_o; + wire n1576_o; + wire n1577_o; + wire [1:0] n1578_o; + wire n1580_o; + wire n1582_o; + wire n1583_o; + wire n1585_o; + wire n1586_o; + reg n1588_o; + reg n1590_o; + wire n1591_o; + wire n1592_o; + wire n1597_o; + wire n1598_o; + wire [7:0] n1599_o; + wire [7:0] n1600_o; + wire [7:0] n1601_o; + wire [7:0] n1602_o; + wire n1604_o; + wire n1605_o; + wire [7:0] n1606_o; + wire [7:0] n1607_o; + wire [7:0] n1608_o; + wire [7:0] n1609_o; + wire n1610_o; + wire n1612_o; + wire n1614_o; + wire n1615_o; + wire n1617_o; + wire n1619_o; + wire n1620_o; + wire n1621_o; + wire n1622_o; + wire [7:0] n1623_o; + wire [7:0] n1624_o; + wire [7:0] n1625_o; + wire [7:0] n1626_o; + wire [7:0] u_regs_n1628; + wire [7:0] u_regs_n1629; + wire [7:0] u_regs_n1630; + wire [7:0] u_regs_n1631; + wire [7:0] u_regs_n1632; + wire [7:0] u_regs_n1633; + wire [127:0] u_regs_n1634; + wire [127:0] n1635_o; + wire [7:0] u_regs_doah; + wire [7:0] u_regs_doal; + wire [7:0] u_regs_dobh; + wire [7:0] u_regs_dobl; + wire [7:0] u_regs_doch; + wire [7:0] u_regs_docl; + wire [127:0] u_regs_dor; + wire n1654_o; + wire n1655_o; + wire [7:0] n1656_o; + wire [7:0] n1657_o; + wire [7:0] n1658_o; + wire n1660_o; + wire n1662_o; + wire n1663_o; + wire n1665_o; + wire n1666_o; + wire n1668_o; + wire n1669_o; + wire n1671_o; + wire n1672_o; + wire n1674_o; + wire n1675_o; + wire n1677_o; + wire [7:0] n1678_o; + wire n1680_o; + wire [7:0] n1681_o; + wire n1683_o; + wire n1685_o; + wire n1687_o; + wire [7:0] n1688_o; + wire n1690_o; + wire [7:0] n1691_o; + wire n1693_o; + wire n1695_o; + wire n1696_o; + wire [7:0] n1699_o; + wire n1701_o; + wire [9:0] n1702_o; + reg [7:0] n1705_o; + wire n1707_o; + wire n1708_o; + wire [7:0] n1709_o; + wire [7:0] n1710_o; + wire [7:0] n1711_o; + wire n1713_o; + wire n1715_o; + wire n1716_o; + wire n1718_o; + wire n1719_o; + wire n1721_o; + wire n1722_o; + wire n1724_o; + wire n1725_o; + wire n1727_o; + wire n1728_o; + wire n1730_o; + wire [7:0] n1731_o; + wire n1733_o; + wire [7:0] n1734_o; + wire n1736_o; + wire n1738_o; + wire [5:0] n1739_o; + reg [7:0] n1742_o; + wire [7:0] n1743_o; + wire [7:0] n1744_o; + wire n1752_o; + wire n1754_o; + wire n1755_o; + wire n1757_o; + wire n1759_o; + wire n1760_o; + wire n1762_o; + wire n1763_o; + wire n1764_o; + wire n1767_o; + wire n1773_o; + wire n1774_o; + wire n1775_o; + reg n1776_oldnmi_n; + wire n1779_o; + wire n1781_o; + wire n1782_o; + wire n1783_o; + wire n1784_o; + wire n1786_o; + wire n1787_o; + wire n1788_o; + wire n1790_o; + wire n1792_o; + wire n1793_o; + wire n1794_o; + wire n1795_o; + wire n1796_o; + wire n1797_o; + wire n1798_o; + wire n1799_o; + wire n1800_o; + wire n1801_o; + wire n1802_o; + wire n1803_o; + wire n1804_o; + wire n1805_o; + wire n1806_o; + wire n1807_o; + wire n1808_o; + wire n1809_o; + wire n1810_o; + wire n1811_o; + wire n1812_o; + wire n1813_o; + wire n1815_o; + wire n1817_o; + wire n1819_o; + wire n1820_o; + wire n1821_o; + wire n1822_o; + wire n1824_o; + wire n1826_o; + wire n1828_o; + wire n1829_o; + wire n1830_o; + wire n1831_o; + wire n1833_o; + wire n1835_o; + wire n1837_o; + wire n1838_o; + wire n1839_o; + wire n1841_o; + wire n1842_o; + wire n1843_o; + wire n1845_o; + wire n1846_o; + wire n1847_o; + wire n1849_o; + wire n1851_o; + wire n1853_o; + wire [2:0] n1855_o; + wire n1857_o; + wire n1861_o; + wire [2:0] n1863_o; + wire n1864_o; + wire n1865_o; + wire n1867_o; + wire n1868_o; + wire n1869_o; + wire n1870_o; + wire n1872_o; + wire n1873_o; + wire n1874_o; + wire n1875_o; + wire n1877_o; + wire n1878_o; + wire n1879_o; + wire n1880_o; + wire n1882_o; + wire n1884_o; + wire n1887_o; + wire n1889_o; + wire n1890_o; + wire n1892_o; + wire n1894_o; + wire n1898_o; + wire [2:0] n1901_o; + wire n1903_o; + wire [2:0] n1905_o; + wire n1906_o; + wire n1907_o; + wire n1908_o; + wire n1909_o; + wire n1910_o; + wire n1911_o; + wire [2:0] n1912_o; + wire n1913_o; + wire n1914_o; + wire n1915_o; + wire n1916_o; + wire n1917_o; + wire n1918_o; + wire [2:0] n1920_o; + wire n1921_o; + wire n1922_o; + wire n1923_o; + wire [2:0] n1924_o; + wire n1925_o; + wire n1926_o; + wire n1927_o; + wire [2:0] n1929_o; + wire [2:0] n1930_o; + wire n1931_o; + wire n1932_o; + wire n1935_o; + wire n1936_o; + wire [2:0] n1937_o; + wire n1938_o; + wire n1939_o; + wire n1940_o; + wire n1941_o; + wire n1943_o; + wire n1944_o; + wire n1945_o; + wire n1946_o; + wire n1947_o; + wire [2:0] n1949_o; + wire [2:0] n1950_o; + wire n1951_o; + wire [2:0] n1952_o; + wire [2:0] n1953_o; + wire n1954_o; + wire n1955_o; + wire n1956_o; + wire n1958_o; + wire n1959_o; + wire [2:0] n1960_o; + wire n1961_o; + wire n1962_o; + wire n1963_o; + wire [2:0] n1964_o; + wire [2:0] n1965_o; + wire n1966_o; + wire n1967_o; + wire n1968_o; + wire n1970_o; + wire n1972_o; + wire [2:0] n1973_o; + wire n1974_o; + wire n1975_o; + wire n1976_o; + wire [2:0] n1977_o; + wire [2:0] n1978_o; + wire n1979_o; + wire n1980_o; + wire n1981_o; + wire n1982_o; + wire n1983_o; + wire [2:0] n1984_o; + wire n1985_o; + wire n1986_o; + wire n1988_o; + wire n1990_o; + wire n1991_o; + wire n1992_o; + wire n1993_o; + wire n1994_o; + wire n1995_o; + wire n1996_o; + wire n1997_o; + wire n1998_o; + wire n1999_o; + wire n2000_o; + wire n2001_o; + wire n2002_o; + wire n2003_o; + wire n2004_o; + wire n2005_o; + wire n2006_o; + wire [2:0] n2007_o; + wire [2:0] n2008_o; + wire n2009_o; + wire n2010_o; + wire n2011_o; + wire n2012_o; + wire n2013_o; + wire n2014_o; + wire [2:0] n2015_o; + wire n2016_o; + wire n2017_o; + wire n2018_o; + wire n2019_o; + wire n2020_o; + wire n2021_o; + wire n2070_o; + wire n2071_o; + reg n2072_q; + wire n2075_o; + wire n2076_o; + wire n2077_o; + reg [7:0] n2079_q; + reg [7:0] n2080_q; + reg [7:0] n2081_q; + reg [7:0] n2082_q; + reg [7:0] n2083_q; + reg [7:0] n2084_q; + reg [15:0] n2085_q; + reg [15:0] n2086_q; + wire [15:0] n2087_o; + wire [15:0] n2088_o; + wire [15:0] n2089_o; + wire [2:0] n2090_o; + reg [2:0] n2091_q; + wire [2:0] n2092_o; + reg [2:0] n2093_q; + wire [2:0] n2094_o; + reg [2:0] n2095_q; + reg n2096_q; + reg [15:0] n2097_q; + reg [7:0] n2098_q; + reg [1:0] n2099_q; + wire [15:0] n2100_o; + reg [15:0] n2101_q; + reg [2:0] n2102_q; + reg [2:0] n2103_q; + reg n2104_q; + reg n2105_q; + reg n2106_q; + reg n2107_q; + reg n2108_q; + reg n2109_q; + reg [1:0] n2110_q; + reg [1:0] n2111_q; + reg [2:0] n2112_q; + reg n2113_q; + reg n2114_q; + reg n2115_q; + reg n2116_q; + reg n2117_q; + wire n2118_o; + reg n2119_q; + wire [7:0] n2120_o; + reg [7:0] n2121_q; + wire [7:0] n2122_o; + reg [7:0] n2123_q; + reg [4:0] n2124_q; + reg n2125_q; + reg n2126_q; + reg [3:0] n2127_q; + reg n2128_q; + reg n2129_q; + reg [2:0] n2130_q; + reg n2131_q; + reg n2132_q; + reg n2133_q; + reg n2134_q; + wire n2135_o; + reg n2136_q; + reg [15:0] n2137_q; + reg [7:0] n2138_q; + assign m1_n = n2134_q; + assign iorq = iorq_i; + assign noread = mcode_n247; + assign write = mcode_n248; + assign rfsh_n = n2136_q; + assign halt_n = n1773_o; + assign busak_n = n1774_o; + assign a = n2137_q; + assign dout = n2138_q; + assign mc = mcycle; + assign ts = tstate; + assign intcycle_n = n1775_o; + assign inte = inte_ff1; + assign stop = i_djnz; + assign regs = n183_o; + /* T80.vhd:263:16 */ + assign acc = n2079_q; // (signal) + /* T80.vhd:263:21 */ + assign f = n2080_q; // (signal) + /* T80.vhd:264:16 */ + assign ap = n2081_q; // (signal) + /* T80.vhd:264:20 */ + assign fp = n2082_q; // (signal) + /* T80.vhd:265:16 */ + assign i = n2083_q; // (signal) + /* T80.vhd:266:16 */ + assign r = n2084_q; // (signal) + /* T80.vhd:267:16 */ + assign sp = n2085_q; // (signal) + /* T80.vhd:267:20 */ + assign pc = n2086_q; // (signal) + /* T80.vhd:269:16 */ + assign regdih = n1625_o; // (signal) + /* T80.vhd:270:16 */ + assign regdil = n1626_o; // (signal) + /* T80.vhd:271:16 */ + assign regbusa = n2087_o; // (signal) + /* T80.vhd:272:16 */ + assign regbusb = n2088_o; // (signal) + /* T80.vhd:273:16 */ + assign regbusc = n2089_o; // (signal) + /* T80.vhd:274:16 */ + assign regaddra_r = n2091_q; // (signal) + /* T80.vhd:275:16 */ + assign regaddra = n1469_o; // (signal) + /* T80.vhd:276:16 */ + assign regaddrb_r = n2093_q; // (signal) + /* T80.vhd:277:16 */ + assign regaddrb = n1505_o; // (signal) + /* T80.vhd:278:16 */ + assign regaddrc = n2095_q; // (signal) + /* T80.vhd:279:16 */ + assign regweh = n1591_o; // (signal) + /* T80.vhd:280:16 */ + assign regwel = n1592_o; // (signal) + /* T80.vhd:281:16 */ + assign alternate = n2096_q; // (signal) + /* T80.vhd:284:16 */ + assign wz = n2097_q; // (signal) + /* T80.vhd:285:16 */ + assign ir = n2098_q; // (signal) + /* T80.vhd:286:16 */ + assign iset = n2099_q; // (signal) + /* T80.vhd:287:16 */ + assign regbusa_r = n2101_q; // (signal) + /* T80.vhd:289:16 */ + assign id16 = n1509_o; // (signal) + /* T80.vhd:290:16 */ + assign save_mux = n381_o; // (signal) + /* T80.vhd:292:16 */ + assign tstate = n2102_q; // (signal) + /* T80.vhd:293:16 */ + assign mcycle = n2103_q; // (signal) + /* T80.vhd:294:16 */ + assign inte_ff1 = n2104_q; // (signal) + /* T80.vhd:295:16 */ + assign inte_ff2 = n2105_q; // (signal) + /* T80.vhd:296:16 */ + assign halt_ff = n2106_q; // (signal) + /* T80.vhd:297:16 */ + assign busreq_s = n2107_q; // (signal) + /* T80.vhd:298:16 */ + assign busack = n2108_q; // (signal) + /* T80.vhd:299:16 */ + assign clken = n354_o; // (signal) + /* T80.vhd:300:16 */ + assign nmi_s = n2109_q; // (signal) + /* T80.vhd:301:16 */ + assign istatus = n2110_q; // (signal) + /* T80.vhd:864:50 */ + assign di_reg = di; // (signal) + /* T80.vhd:304:16 */ + assign t_res = n357_o; // (signal) + /* T80.vhd:305:16 */ + assign xy_state = n2111_q; // (signal) + /* T80.vhd:306:16 */ + assign pre_xy_f_m = n2112_q; // (signal) + /* T80.vhd:307:16 */ + assign nextis_xy_fetch = n379_o; // (signal) + /* T80.vhd:308:16 */ + assign xy_ind = n2113_q; // (signal) + /* T80.vhd:309:16 */ + assign no_btr = n2114_q; // (signal) + /* T80.vhd:310:16 */ + assign btr_r = n2115_q; // (signal) + /* T80.vhd:311:16 */ + assign auto_wait = n2077_o; // (signal) + /* T80.vhd:312:16 */ + assign auto_wait_t1 = n2116_q; // (signal) + /* T80.vhd:313:16 */ + assign auto_wait_t2 = n2117_q; // (signal) + /* T80.vhd:314:16 */ + assign incdecz = n2119_q; // (signal) + /* T80.vhd:317:16 */ + assign busb = n2121_q; // (signal) + /* T80.vhd:318:16 */ + assign busa = n2123_q; // (signal) + /* T80.vhd:319:16 */ + assign alu_q = u_alu_n347; // (signal) + /* T80.vhd:320:16 */ + assign f_out = u_alu_n348; // (signal) + /* T80.vhd:323:16 */ + assign read_to_reg_r = n2124_q; // (signal) + /* T80.vhd:324:16 */ + assign arith16_r = n2125_q; // (signal) + /* T80.vhd:325:16 */ + assign z16_r = n2126_q; // (signal) + /* T80.vhd:326:16 */ + assign alu_op_r = n2127_q; // (signal) + /* T80.vhd:327:16 */ + assign save_alu_r = n2128_q; // (signal) + /* T80.vhd:328:16 */ + assign preservec_r = n2129_q; // (signal) + /* T80.vhd:329:16 */ + assign mcycles = n2130_q; // (signal) + /* T80.vhd:332:16 */ + assign mcycles_d = mcode_n202; // (signal) + /* T80.vhd:333:16 */ + assign tstates = mcode_n203; // (signal) + /* T80.vhd:334:16 */ + assign intcycle = n2131_q; // (signal) + /* T80.vhd:335:16 */ + assign nmicycle = n2132_q; // (signal) + /* T80.vhd:336:16 */ + assign inc_pc = mcode_n205; // (signal) + /* T80.vhd:337:16 */ + assign inc_wz = mcode_n206; // (signal) + /* T80.vhd:338:16 */ + assign incdec_16 = mcode_n207; // (signal) + /* T80.vhd:339:16 */ + assign prefix = mcode_n204; // (signal) + /* T80.vhd:340:16 */ + assign read_to_acc = mcode_n209; // (signal) + /* T80.vhd:341:16 */ + assign read_to_reg = mcode_n208; // (signal) + /* T80.vhd:342:16 */ + assign set_busb_to = mcode_n211; // (signal) + /* T80.vhd:343:16 */ + assign set_busa_to = mcode_n210; // (signal) + /* T80.vhd:344:16 */ + assign alu_op = mcode_n212; // (signal) + /* T80.vhd:345:16 */ + assign save_alu = mcode_n213; // (signal) + /* T80.vhd:346:16 */ + assign preservec = mcode_n214; // (signal) + /* T80.vhd:347:16 */ + assign arith16 = mcode_n215; // (signal) + /* T80.vhd:348:16 */ + assign set_addr_to = mcode_n216; // (signal) + /* T80.vhd:349:16 */ + assign jump = mcode_n218; // (signal) + /* T80.vhd:350:16 */ + assign jumpe = mcode_n219; // (signal) + /* T80.vhd:351:16 */ + assign jumpxy = mcode_n220; // (signal) + /* T80.vhd:352:16 */ + assign call = mcode_n221; // (signal) + /* T80.vhd:353:16 */ + assign rstp = mcode_n222; // (signal) + /* T80.vhd:354:16 */ + assign ldz = mcode_n223; // (signal) + /* T80.vhd:355:16 */ + assign ldw = mcode_n224; // (signal) + /* T80.vhd:356:16 */ + assign ldsphl = mcode_n225; // (signal) + /* T80.vhd:357:16 */ + assign iorq_i = mcode_n217; // (signal) + /* T80.vhd:358:16 */ + assign special_ld = mcode_n226; // (signal) + /* T80.vhd:359:16 */ + assign exchangedh = mcode_n227; // (signal) + /* T80.vhd:360:16 */ + assign exchangerp = mcode_n228; // (signal) + /* T80.vhd:361:16 */ + assign exchangeaf = mcode_n229; // (signal) + /* T80.vhd:362:16 */ + assign exchangers = mcode_n230; // (signal) + /* T80.vhd:363:16 */ + assign i_djnz = mcode_n231; // (signal) + /* T80.vhd:364:16 */ + assign i_cpl = mcode_n232; // (signal) + /* T80.vhd:365:16 */ + assign i_ccf = mcode_n233; // (signal) + /* T80.vhd:366:16 */ + assign i_scf = mcode_n234; // (signal) + /* T80.vhd:367:16 */ + assign i_retn = mcode_n235; // (signal) + /* T80.vhd:368:16 */ + assign i_bt = mcode_n236; // (signal) + /* T80.vhd:369:16 */ + assign i_bc = mcode_n237; // (signal) + /* T80.vhd:370:16 */ + assign i_btr = mcode_n238; // (signal) + /* T80.vhd:371:16 */ + assign i_rld = mcode_n239; // (signal) + /* T80.vhd:372:16 */ + assign i_rrd = mcode_n240; // (signal) + /* T80.vhd:373:16 */ + assign i_rxdd = n2133_q; // (signal) + /* T80.vhd:374:16 */ + assign i_inrc = mcode_n241; // (signal) + /* T80.vhd:375:16 */ + assign setwz = mcode_n242; // (signal) + /* T80.vhd:376:16 */ + assign setdi = mcode_n243; // (signal) + /* T80.vhd:377:16 */ + assign setei = mcode_n244; // (signal) + /* T80.vhd:378:16 */ + assign imode = mcode_n245; // (signal) + /* T80.vhd:379:16 */ + assign halt = mcode_n246; // (signal) + /* T80.vhd:380:16 */ + assign xybit_undoc = mcode_n249; // (signal) + /* T80.vhd:381:16 */ + assign dor = u_regs_n1634; // (signal) + /* T80.vhd:385:26 */ + assign n171_o = {inte_ff2, inte_ff1}; + /* T80.vhd:385:37 */ + assign n172_o = {n171_o, istatus}; + /* T80.vhd:385:47 */ + assign n173_o = {n172_o, dor}; + /* T80.vhd:385:53 */ + assign n174_o = {n173_o, pc}; + /* T80.vhd:385:76 */ + assign n175_o = {n174_o, sp}; + /* T80.vhd:385:99 */ + assign n176_o = {n175_o, r}; + /* T80.vhd:385:121 */ + assign n177_o = {n176_o, i}; + /* T80.vhd:385:125 */ + assign n178_o = {n177_o, fp}; + /* T80.vhd:385:130 */ + assign n179_o = {n178_o, ap}; + /* T80.vhd:385:135 */ + assign n180_o = {n179_o, f}; + /* T80.vhd:385:139 */ + assign n181_o = {n180_o, acc}; + /* T80.vhd:385:160 */ + assign n182_o = ~alternate; + /* T80.vhd:385:145 */ + assign n183_o = n182_o ? n181_o : n201_o; + /* T80.vhd:386:40 */ + assign n184_o = {inte_ff2, inte_ff1}; + /* T80.vhd:386:51 */ + assign n185_o = {n184_o, istatus}; + /* T80.vhd:386:66 */ + assign n186_o = dor[127:112]; + /* T80.vhd:386:61 */ + assign n187_o = {n185_o, n186_o}; + /* T80.vhd:386:88 */ + assign n188_o = dor[47:0]; + /* T80.vhd:386:83 */ + assign n189_o = {n187_o, n188_o}; + /* T80.vhd:386:107 */ + assign n190_o = dor[63:48]; + /* T80.vhd:386:102 */ + assign n191_o = {n189_o, n190_o}; + /* T80.vhd:386:127 */ + assign n192_o = dor[111:64]; + /* T80.vhd:386:122 */ + assign n193_o = {n191_o, n192_o}; + /* T80.vhd:386:143 */ + assign n194_o = {n193_o, pc}; + /* T80.vhd:387:70 */ + assign n195_o = {n194_o, sp}; + /* T80.vhd:387:93 */ + assign n196_o = {n195_o, r}; + /* T80.vhd:387:115 */ + assign n197_o = {n196_o, i}; + /* T80.vhd:387:119 */ + assign n198_o = {n197_o, fp}; + /* T80.vhd:387:124 */ + assign n199_o = {n198_o, ap}; + /* T80.vhd:387:129 */ + assign n200_o = {n199_o, f}; + /* T80.vhd:387:133 */ + assign n201_o = {n200_o, acc}; + /* T80.vhd:408:40 */ + assign mcode_n202 = mcode_mcycles; // (signal) + /* T80.vhd:409:40 */ + assign mcode_n203 = mcode_tstates; // (signal) + /* T80.vhd:410:40 */ + assign mcode_n204 = mcode_prefix; // (signal) + /* T80.vhd:411:40 */ + assign mcode_n205 = mcode_inc_pc; // (signal) + /* T80.vhd:412:40 */ + assign mcode_n206 = mcode_inc_wz; // (signal) + /* T80.vhd:413:40 */ + assign mcode_n207 = mcode_incdec_16; // (signal) + /* T80.vhd:415:40 */ + assign mcode_n208 = mcode_read_to_reg; // (signal) + /* T80.vhd:414:40 */ + assign mcode_n209 = mcode_read_to_acc; // (signal) + /* T80.vhd:417:40 */ + assign mcode_n210 = mcode_set_busa_to; // (signal) + /* T80.vhd:416:40 */ + assign mcode_n211 = mcode_set_busb_to; // (signal) + /* T80.vhd:418:40 */ + assign mcode_n212 = mcode_alu_op; // (signal) + /* T80.vhd:419:40 */ + assign mcode_n213 = mcode_save_alu; // (signal) + /* T80.vhd:420:40 */ + assign mcode_n214 = mcode_preservec; // (signal) + /* T80.vhd:421:40 */ + assign mcode_n215 = mcode_arith16; // (signal) + /* T80.vhd:422:40 */ + assign mcode_n216 = mcode_set_addr_to; // (signal) + /* T80.vhd:423:40 */ + assign mcode_n217 = mcode_iorq; // (signal) + /* T80.vhd:424:40 */ + assign mcode_n218 = mcode_jump; // (signal) + /* T80.vhd:425:40 */ + assign mcode_n219 = mcode_jumpe; // (signal) + /* T80.vhd:426:40 */ + assign mcode_n220 = mcode_jumpxy; // (signal) + /* T80.vhd:427:40 */ + assign mcode_n221 = mcode_call; // (signal) + /* T80.vhd:428:40 */ + assign mcode_n222 = mcode_rstp; // (signal) + /* T80.vhd:429:40 */ + assign mcode_n223 = mcode_ldz; // (signal) + /* T80.vhd:430:40 */ + assign mcode_n224 = mcode_ldw; // (signal) + /* T80.vhd:431:40 */ + assign mcode_n225 = mcode_ldsphl; // (signal) + /* T80.vhd:432:40 */ + assign mcode_n226 = mcode_special_ld; // (signal) + /* T80.vhd:433:40 */ + assign mcode_n227 = mcode_exchangedh; // (signal) + /* T80.vhd:434:40 */ + assign mcode_n228 = mcode_exchangerp; // (signal) + /* T80.vhd:435:40 */ + assign mcode_n229 = mcode_exchangeaf; // (signal) + /* T80.vhd:436:40 */ + assign mcode_n230 = mcode_exchangers; // (signal) + /* T80.vhd:437:40 */ + assign mcode_n231 = mcode_i_djnz; // (signal) + /* T80.vhd:438:40 */ + assign mcode_n232 = mcode_i_cpl; // (signal) + /* T80.vhd:439:40 */ + assign mcode_n233 = mcode_i_ccf; // (signal) + /* T80.vhd:440:40 */ + assign mcode_n234 = mcode_i_scf; // (signal) + /* T80.vhd:441:40 */ + assign mcode_n235 = mcode_i_retn; // (signal) + /* T80.vhd:442:40 */ + assign mcode_n236 = mcode_i_bt; // (signal) + /* T80.vhd:443:40 */ + assign mcode_n237 = mcode_i_bc; // (signal) + /* T80.vhd:444:40 */ + assign mcode_n238 = mcode_i_btr; // (signal) + /* T80.vhd:445:40 */ + assign mcode_n239 = mcode_i_rld; // (signal) + /* T80.vhd:446:40 */ + assign mcode_n240 = mcode_i_rrd; // (signal) + /* T80.vhd:447:40 */ + assign mcode_n241 = mcode_i_inrc; // (signal) + /* T80.vhd:448:40 */ + assign mcode_n242 = mcode_setwz; // (signal) + /* T80.vhd:449:40 */ + assign mcode_n243 = mcode_setdi; // (signal) + /* T80.vhd:450:40 */ + assign mcode_n244 = mcode_setei; // (signal) + /* T80.vhd:451:40 */ + assign mcode_n245 = mcode_imode; // (signal) + /* T80.vhd:452:40 */ + assign mcode_n246 = mcode_halt; // (signal) + /* T80.vhd:453:40 */ + assign mcode_n247 = mcode_noread; // (signal) + /* T80.vhd:454:40 */ + assign mcode_n248 = mcode_write; // (signal) + /* T80.vhd:455:40 */ + assign mcode_n249 = mcode_xybit_undoc; // (signal) + /* T80.vhd:389:9 */ + t80_mcode_0_0_1_2_3_4_5_6_7 mcode ( + .ir(ir), + .iset(iset), + .mcycle(mcycle), + .f(f), + .nmicycle(nmicycle), + .intcycle(intcycle), + .xy_state(xy_state), + .mcycles(mcode_mcycles), + .tstates(mcode_tstates), + .prefix(mcode_prefix), + .inc_pc(mcode_inc_pc), + .inc_wz(mcode_inc_wz), + .incdec_16(mcode_incdec_16), + .read_to_reg(mcode_read_to_reg), + .read_to_acc(mcode_read_to_acc), + .set_busa_to(mcode_set_busa_to), + .set_busb_to(mcode_set_busb_to), + .alu_op(mcode_alu_op), + .save_alu(mcode_save_alu), + .preservec(mcode_preservec), + .arith16(mcode_arith16), + .set_addr_to(mcode_set_addr_to), + .iorq(mcode_iorq), + .jump(mcode_jump), + .jumpe(mcode_jumpe), + .jumpxy(mcode_jumpxy), + .call(mcode_call), + .rstp(mcode_rstp), + .ldz(mcode_ldz), + .ldw(mcode_ldw), + .ldsphl(mcode_ldsphl), + .special_ld(mcode_special_ld), + .exchangedh(mcode_exchangedh), + .exchangerp(mcode_exchangerp), + .exchangeaf(mcode_exchangeaf), + .exchangers(mcode_exchangers), + .i_djnz(mcode_i_djnz), + .i_cpl(mcode_i_cpl), + .i_ccf(mcode_i_ccf), + .i_scf(mcode_i_scf), + .i_retn(mcode_i_retn), + .i_bt(mcode_i_bt), + .i_bc(mcode_i_bc), + .i_btr(mcode_i_btr), + .i_rld(mcode_i_rld), + .i_rrd(mcode_i_rrd), + .i_inrc(mcode_i_inrc), + .setwz(mcode_setwz), + .setdi(mcode_setdi), + .setei(mcode_setei), + .imode(mcode_imode), + .halt(mcode_halt), + .noread(mcode_noread), + .write(mcode_write), + .xybit_undoc(mcode_xybit_undoc)); + /* T80.vhd:474:38 */ + assign n346_o = ir[5:0]; + /* T80.vhd:479:36 */ + assign u_alu_n347 = u_alu_q; // (signal) + /* T80.vhd:480:36 */ + assign u_alu_n348 = u_alu_f_out; // (signal) + /* T80.vhd:457:9 */ + t80_alu_0_0_1_2_3_4_5_6_7 u_alu ( + .arith16(arith16_r), + .z16(z16_r), + .wz(wz), + .xy_state(xy_state), + .alu_op(alu_op_r), + .ir(n346_o), + .iset(iset), + .busa(busa), + .busb(busb), + .f_in(f), + .q(u_alu_q), + .f_out(u_alu_f_out)); + /* T80.vhd:482:26 */ + assign n353_o = ~busack; + /* T80.vhd:482:22 */ + assign n354_o = cen & n353_o; + /* T80.vhd:484:34 */ + assign n356_o = tstate == tstates; + /* T80.vhd:484:22 */ + assign n357_o = n356_o ? 1'b1 : 1'b0; + /* T80.vhd:486:46 */ + assign n361_o = xy_state != 2'b00; + /* T80.vhd:486:65 */ + assign n362_o = ~xy_ind; + /* T80.vhd:486:54 */ + assign n363_o = n362_o & n361_o; + /* T80.vhd:487:71 */ + assign n365_o = set_addr_to == 3'b010; + /* T80.vhd:488:65 */ + assign n367_o = mcycle == 3'b001; + /* T80.vhd:488:80 */ + assign n369_o = ir == 8'b11001011; + /* T80.vhd:488:73 */ + assign n370_o = n369_o & n367_o; + /* T80.vhd:487:78 */ + assign n371_o = n365_o | n370_o; + /* T80.vhd:489:65 */ + assign n373_o = mcycle == 3'b001; + /* T80.vhd:489:80 */ + assign n375_o = ir == 8'b00110110; + /* T80.vhd:489:73 */ + assign n376_o = n375_o & n373_o; + /* T80.vhd:488:94 */ + assign n377_o = n371_o | n376_o; + /* T80.vhd:486:71 */ + assign n378_o = n377_o & n363_o; + /* T80.vhd:486:32 */ + assign n379_o = n378_o ? 1'b1 : 1'b0; + /* T80.vhd:491:26 */ + assign n381_o = exchangerp ? busb : n383_o; + /* T80.vhd:492:40 */ + assign n382_o = ~save_alu_r; + /* T80.vhd:491:48 */ + assign n383_o = n382_o ? di_reg : alu_q; + /* T80.vhd:499:28 */ + assign n388_o = ~reset_n; + /* T80.vhd:532:43 */ + assign n390_o = dir[7:0]; + /* T80.vhd:533:43 */ + assign n391_o = dir[15:8]; + /* T80.vhd:534:43 */ + assign n392_o = dir[23:16]; + /* T80.vhd:535:43 */ + assign n393_o = dir[31:24]; + /* T80.vhd:536:43 */ + assign n394_o = dir[39:32]; + /* T80.vhd:537:52 */ + assign n395_o = dir[47:40]; + /* T80.vhd:538:52 */ + assign n396_o = dir[63:48]; + /* T80.vhd:539:52 */ + assign n397_o = dir[79:64]; + /* T80.vhd:540:43 */ + assign n398_o = dir[79:64]; + /* T80.vhd:541:47 */ + assign n399_o = dir[209:208]; + /* T80.vhd:550:42 */ + assign n401_o = imode != 2'b11; + /* T80.vhd:543:25 */ + assign n402_o = n1241_o ? imode : istatus; + /* T80.vhd:556:41 */ + assign n404_o = iset == 2'b10; + /* T80.vhd:556:58 */ + assign n405_o = alu_op[2]; + /* T80.vhd:556:62 */ + assign n406_o = ~n405_o; + /* T80.vhd:556:48 */ + assign n407_o = n406_o & n404_o; + /* T80.vhd:556:78 */ + assign n408_o = alu_op[0]; + /* T80.vhd:556:68 */ + assign n409_o = n408_o & n407_o; + /* T80.vhd:556:99 */ + assign n411_o = mcycle == 3'b011; + /* T80.vhd:556:88 */ + assign n412_o = n411_o & n409_o; + /* T80.vhd:556:33 */ + assign n415_o = n412_o ? 1'b1 : 1'b0; + /* T80.vhd:562:44 */ + assign n417_o = mcycle == 3'b001; + /* T80.vhd:562:62 */ + assign n418_o = tstate[2]; + /* T80.vhd:562:66 */ + assign n419_o = ~n418_o; + /* T80.vhd:562:52 */ + assign n420_o = n419_o & n417_o; + /* T80.vhd:565:51 */ + assign n422_o = tstate == 3'b010; + /* T80.vhd:565:55 */ + assign n423_o = wait_n & n422_o; + /* T80.vhd:569:75 */ + assign n424_o = r[6:0]; + /* T80.vhd:569:88 */ + assign n426_o = n424_o + 7'b0000001; + /* T80.vhd:572:57 */ + assign n427_o = ~jump; + /* T80.vhd:572:72 */ + assign n428_o = ~call; + /* T80.vhd:572:63 */ + assign n429_o = n428_o & n427_o; + /* T80.vhd:572:91 */ + assign n430_o = ~nmicycle; + /* T80.vhd:572:78 */ + assign n431_o = n430_o & n429_o; + /* T80.vhd:572:110 */ + assign n432_o = ~intcycle; + /* T80.vhd:572:97 */ + assign n433_o = n432_o & n431_o; + /* T80.vhd:572:139 */ + assign n434_o = halt_ff | halt; + /* T80.vhd:572:120 */ + assign n435_o = ~n434_o; + /* T80.vhd:572:116 */ + assign n436_o = n435_o & n433_o; + /* T80.vhd:573:66 */ + assign n438_o = pc + 16'b0000000000000001; + /* T80.vhd:565:41 */ + assign n439_o = n481_o ? n438_o : pc; + /* T80.vhd:576:79 */ + assign n441_o = istatus == 2'b01; + /* T80.vhd:576:67 */ + assign n442_o = n441_o & intcycle; + /* T80.vhd:578:100 */ + assign n444_o = istatus == 2'b10; + /* T80.vhd:578:88 */ + assign n445_o = n444_o & intcycle; + /* T80.vhd:578:69 */ + assign n446_o = halt_ff | n445_o; + /* T80.vhd:578:108 */ + assign n447_o = n446_o | nmicycle; + /* T80.vhd:578:49 */ + assign n449_o = n447_o ? 8'b00000000 : dinst; + /* T80.vhd:576:49 */ + assign n451_o = n442_o ? 8'b11111111 : n449_o; + /* T80.vhd:585:59 */ + assign n453_o = prefix != 2'b00; + /* T80.vhd:586:67 */ + assign n455_o = prefix == 2'b11; + /* T80.vhd:587:70 */ + assign n456_o = ir[5]; + /* T80.vhd:587:65 */ + assign n459_o = n456_o ? 2'b10 : 2'b01; + /* T80.vhd:593:75 */ + assign n461_o = prefix == 2'b10; + /* T80.vhd:593:65 */ + assign n463_o = n461_o ? 2'b00 : xy_state; + /* T80.vhd:593:65 */ + assign n465_o = n461_o ? 1'b0 : xy_ind; + /* T80.vhd:586:57 */ + assign n467_o = n455_o ? 2'b00 : prefix; + /* T80.vhd:586:57 */ + assign n468_o = n455_o ? n459_o : n463_o; + /* T80.vhd:586:57 */ + assign n469_o = n455_o ? xy_ind : n465_o; + /* T80.vhd:585:49 */ + assign n471_o = n453_o ? n467_o : 2'b00; + /* T80.vhd:585:49 */ + assign n474_o = n453_o ? n468_o : 2'b00; + /* T80.vhd:585:49 */ + assign n476_o = n453_o ? n469_o : 1'b0; + assign n477_o = {i, r}; + /* T80.vhd:565:41 */ + assign n478_o = n423_o ? n477_o : n2137_q; + assign n479_o = r[6:0]; + /* T80.vhd:562:33 */ + assign n480_o = n817_o ? n426_o : n479_o; + /* T80.vhd:565:41 */ + assign n481_o = n423_o & n436_o; + /* T80.vhd:565:41 */ + assign n482_o = n423_o ? n451_o : ir; + /* T80.vhd:565:41 */ + assign n483_o = n423_o ? n471_o : iset; + /* T80.vhd:543:25 */ + assign n484_o = n1242_o ? n474_o : xy_state; + /* T80.vhd:565:41 */ + assign n485_o = n423_o ? n476_o : xy_ind; + /* T80.vhd:608:51 */ + assign n487_o = mcycle == 3'b110; + /* T80.vhd:610:59 */ + assign n489_o = prefix == 2'b01; + /* T80.vhd:608:41 */ + assign n491_o = n492_o ? 2'b01 : iset; + /* T80.vhd:608:41 */ + assign n492_o = n487_o & n489_o; + /* T80.vhd:608:41 */ + assign n494_o = n487_o ? 1'b1 : xy_ind; + /* T80.vhd:616:64 */ + assign n495_o = i_bt | i_bc; + /* T80.vhd:616:72 */ + assign n496_o = n495_o | i_btr; + /* T80.vhd:616:86 */ + assign n497_o = ~no_btr; + /* T80.vhd:616:82 */ + assign n498_o = n496_o & n497_o; + /* T80.vhd:619:76 */ + assign n499_o = wz[7:0]; + /* T80.vhd:621:86 */ + assign n500_o = wz[7:0]; + /* T80.vhd:625:66 */ + assign n501_o = call | rstp; + /* T80.vhd:628:62 */ + assign n502_o = mcycle == mcycles; + /* T80.vhd:628:72 */ + assign n503_o = nmicycle & n502_o; + /* T80.vhd:631:62 */ + assign n505_o = mcycle == 3'b011; + /* T80.vhd:631:70 */ + assign n506_o = intcycle & n505_o; + /* T80.vhd:631:101 */ + assign n508_o = istatus == 2'b10; + /* T80.vhd:631:89 */ + assign n509_o = n508_o & n506_o; + /* T80.vhd:633:76 */ + assign n510_o = wz[7:0]; + /* T80.vhd:635:86 */ + assign n511_o = wz[7:0]; + /* T80.vhd:639:77 */ + assign n513_o = xy_state == 2'b00; + /* T80.vhd:642:73 */ + assign n514_o = nextis_xy_fetch ? pc : wz; + /* T80.vhd:639:65 */ + assign n515_o = n513_o ? regbusc : n514_o; + /* T80.vhd:638:57 */ + assign n517_o = set_addr_to == 3'b010; + /* T80.vhd:659:76 */ + assign n518_o = {acc, di_reg}; + /* T80.vhd:659:86 */ + assign n521_o = n518_o + 16'b0000000000000001; + /* T80.vhd:648:57 */ + assign n523_o = set_addr_to == 3'b100; + /* T80.vhd:660:57 */ + assign n525_o = set_addr_to == 3'b101; + /* T80.vhd:669:82 */ + assign n527_o = setwz == 2'b01; + /* T80.vhd:670:95 */ + assign n530_o = regbusc + 16'b0000000000000001; + /* T80.vhd:669:73 */ + assign n531_o = n527_o ? n530_o : wz; + /* T80.vhd:672:82 */ + assign n533_o = setwz == 2'b10; + /* T80.vhd:673:106 */ + assign n534_o = regbusc[7:0]; + /* T80.vhd:673:119 */ + assign n537_o = n534_o + 8'b00000001; + assign n538_o = {acc, n537_o}; + /* T80.vhd:672:73 */ + assign n539_o = n533_o ? n538_o : n531_o; + /* T80.vhd:662:57 */ + assign n541_o = set_addr_to == 3'b000; + /* T80.vhd:679:74 */ + assign n543_o = setwz == 2'b10; + /* T80.vhd:680:98 */ + assign n544_o = regbusc[7:0]; + /* T80.vhd:680:111 */ + assign n547_o = n544_o + 8'b00000001; + assign n548_o = {acc, n547_o}; + /* T80.vhd:679:65 */ + assign n549_o = n543_o ? n548_o : wz; + /* T80.vhd:677:57 */ + assign n551_o = set_addr_to == 3'b001; + /* T80.vhd:685:108 */ + assign n553_o = wz + 16'b0000000000000001; + /* T80.vhd:688:92 */ + assign n554_o = wz[7:0]; + /* T80.vhd:689:82 */ + assign n556_o = setwz == 2'b10; + /* T80.vhd:690:101 */ + assign n557_o = wz[7:0]; + /* T80.vhd:690:114 */ + assign n560_o = n557_o + 8'b00000001; + assign n561_o = {acc, n560_o}; + /* T80.vhd:689:73 */ + assign n562_o = n556_o ? n561_o : wz; + assign n563_o = {di_reg, n554_o}; + /* T80.vhd:684:65 */ + assign n564_o = inc_wz ? n553_o : n563_o; + /* T80.vhd:684:65 */ + assign n565_o = inc_wz ? wz : n562_o; + /* T80.vhd:683:57 */ + assign n567_o = set_addr_to == 3'b110; + assign n568_o = {n567_o, n551_o, n541_o, n525_o, n523_o, n517_o}; + assign n569_o = n515_o[7:0]; + assign n570_o = sp[7:0]; + assign n571_o = regbusc[7:0]; + assign n572_o = regbusc[7:0]; + assign n573_o = n564_o[7:0]; + assign n574_o = pc[7:0]; + /* T80.vhd:637:57 */ + always @* + case (n568_o) + 6'b100000: n575_o = n573_o; + 6'b010000: n575_o = n572_o; + 6'b001000: n575_o = n571_o; + 6'b000100: n575_o = n570_o; + 6'b000010: n575_o = di_reg; + 6'b000001: n575_o = n569_o; + default: n575_o = n574_o; + endcase + assign n576_o = n515_o[15:8]; + assign n577_o = sp[15:8]; + assign n578_o = regbusc[15:8]; + assign n579_o = regbusc[15:8]; + assign n580_o = n564_o[15:8]; + assign n581_o = pc[15:8]; + /* T80.vhd:637:57 */ + always @* + case (n568_o) + 6'b100000: n582_o = n580_o; + 6'b010000: n582_o = n579_o; + 6'b001000: n582_o = n578_o; + 6'b000100: n582_o = n577_o; + 6'b000010: n582_o = acc; + 6'b000001: n582_o = n576_o; + default: n582_o = n581_o; + endcase + /* T80.vhd:637:57 */ + always @* + case (n568_o) + 6'b100000: n583_o = n565_o; + 6'b010000: n583_o = n549_o; + 6'b001000: n583_o = n539_o; + 6'b000100: n583_o = wz; + 6'b000010: n583_o = n521_o; + 6'b000001: n583_o = wz; + default: n583_o = wz; + endcase + assign n584_o = {n582_o, n575_o}; + assign n585_o = {i, n510_o}; + /* T80.vhd:631:49 */ + assign n586_o = n509_o ? n585_o : n584_o; + assign n587_o = {i, n511_o}; + /* T80.vhd:631:49 */ + assign n588_o = n509_o ? n587_o : pc; + /* T80.vhd:631:49 */ + assign n589_o = n509_o ? wz : n583_o; + /* T80.vhd:628:49 */ + assign n591_o = n503_o ? 16'b0000000001100110 : n586_o; + /* T80.vhd:628:49 */ + assign n593_o = n503_o ? 16'b0000000001100110 : n588_o; + /* T80.vhd:628:49 */ + assign n594_o = n503_o ? wz : n589_o; + /* T80.vhd:625:49 */ + assign n595_o = n501_o ? wz : n591_o; + /* T80.vhd:625:49 */ + assign n596_o = n501_o ? wz : n593_o; + /* T80.vhd:625:49 */ + assign n597_o = n501_o ? wz : n594_o; + /* T80.vhd:622:49 */ + assign n598_o = jumpxy ? regbusc : n595_o; + /* T80.vhd:622:49 */ + assign n599_o = jumpxy ? regbusc : n596_o; + /* T80.vhd:622:49 */ + assign n600_o = jumpxy ? wz : n597_o; + assign n601_o = {di_reg, n499_o}; + /* T80.vhd:617:49 */ + assign n602_o = jump ? n601_o : n598_o; + assign n603_o = {di_reg, n500_o}; + /* T80.vhd:617:49 */ + assign n604_o = jump ? n603_o : n599_o; + /* T80.vhd:617:49 */ + assign n605_o = jump ? wz : n600_o; + /* T80.vhd:699:58 */ + assign n607_o = setwz == 2'b11; + /* T80.vhd:699:49 */ + assign n608_o = n607_o ? id16 : n605_o; + /* T80.vhd:708:64 */ + assign n609_o = ~acc; + /* T80.vhd:709:77 */ + assign n610_o = acc[5]; + /* T80.vhd:709:70 */ + assign n611_o = ~n610_o; + /* T80.vhd:711:77 */ + assign n613_o = acc[3]; + /* T80.vhd:711:70 */ + assign n614_o = ~n613_o; + /* T80.vhd:615:41 */ + assign n616_o = n644_o ? n609_o : acc; + assign n617_o = {n611_o, 1'b1, n614_o}; + assign n618_o = f[1]; + /* T80.vhd:706:49 */ + assign n619_o = i_cpl ? 1'b1 : n618_o; + /* T80.vhd:716:75 */ + assign n622_o = f[0]; + /* T80.vhd:716:70 */ + assign n623_o = ~n622_o; + /* T80.vhd:717:73 */ + assign n624_o = acc[5]; + /* T80.vhd:718:71 */ + assign n625_o = f[0]; + /* T80.vhd:719:73 */ + assign n626_o = acc[3]; + assign n628_o = {1'b0, n623_o}; + assign n629_o = {n624_o, n625_o, n626_o}; + assign n630_o = f[0]; + assign n631_o = {n619_o, n630_o}; + /* T80.vhd:714:49 */ + assign n632_o = i_ccf ? n628_o : n631_o; + /* T80.vhd:725:73 */ + assign n635_o = acc[5]; + /* T80.vhd:727:73 */ + assign n637_o = acc[3]; + assign n639_o = {1'b0, 1'b1}; + assign n640_o = {n635_o, 1'b0, n637_o}; + /* T80.vhd:722:49 */ + assign n641_o = i_scf ? n639_o : n632_o; + /* T80.vhd:615:41 */ + assign n643_o = t_res ? n602_o : n2137_q; + /* T80.vhd:615:41 */ + assign n644_o = t_res & i_cpl; + assign n645_o = f[1:0]; + /* T80.vhd:615:41 */ + assign n646_o = t_res ? n641_o : n645_o; + /* T80.vhd:615:41 */ + assign n649_o = t_res ? n604_o : pc; + /* T80.vhd:615:41 */ + assign n650_o = t_res ? n608_o : wz; + /* T80.vhd:615:41 */ + assign n651_o = t_res ? n498_o : btr_r; + /* T80.vhd:615:41 */ + assign n653_o = t_res ? alu_op : 4'b0000; + /* T80.vhd:615:41 */ + assign n655_o = t_res ? save_alu : 1'b0; + /* T80.vhd:732:52 */ + assign n657_o = tstate == 3'b010; + /* T80.vhd:732:56 */ + assign n658_o = i_btr & n657_o; + /* T80.vhd:732:78 */ + assign n659_o = ir[0]; + /* T80.vhd:732:72 */ + assign n660_o = n659_o & n658_o; + /* T80.vhd:732:100 */ + assign n662_o = tstate == 3'b001; + /* T80.vhd:732:104 */ + assign n663_o = i_btr & n662_o; + /* T80.vhd:732:126 */ + assign n664_o = ir[0]; + /* T80.vhd:732:130 */ + assign n665_o = ~n664_o; + /* T80.vhd:732:120 */ + assign n666_o = n665_o & n663_o; + /* T80.vhd:732:89 */ + assign n667_o = n660_o | n666_o; + /* T80.vhd:733:61 */ + assign n669_o = {1'b0, di_reg}; + /* T80.vhd:733:101 */ + assign n670_o = id16[7:0]; + /* T80.vhd:733:78 */ + assign n672_o = {1'b0, n670_o}; + /* T80.vhd:733:71 */ + assign n673_o = n669_o + n672_o; + /* T80.vhd:734:68 */ + assign n674_o = di_reg[7]; + /* T80.vhd:735:65 */ + assign n675_o = n673_o[8]; + /* T80.vhd:736:65 */ + assign n676_o = n673_o[8]; + /* T80.vhd:737:61 */ + assign n678_o = n673_o & 9'b000000111; + /* T80.vhd:737:88 */ + assign n680_o = {1'b0, busa}; + /* T80.vhd:737:80 */ + assign n681_o = n678_o ^ n680_o; + /* T80.vhd:738:70 */ + assign n682_o = n681_o[0]; + /* T80.vhd:738:81 */ + assign n683_o = n681_o[1]; + /* T80.vhd:738:74 */ + assign n684_o = n682_o ^ n683_o; + /* T80.vhd:738:92 */ + assign n685_o = n681_o[2]; + /* T80.vhd:738:85 */ + assign n686_o = n684_o ^ n685_o; + /* T80.vhd:738:103 */ + assign n687_o = n681_o[3]; + /* T80.vhd:738:96 */ + assign n688_o = n686_o ^ n687_o; + /* T80.vhd:738:114 */ + assign n689_o = n681_o[4]; + /* T80.vhd:738:107 */ + assign n690_o = n688_o ^ n689_o; + /* T80.vhd:738:125 */ + assign n691_o = n681_o[5]; + /* T80.vhd:738:118 */ + assign n692_o = n690_o ^ n691_o; + /* T80.vhd:738:136 */ + assign n693_o = n681_o[6]; + /* T80.vhd:738:129 */ + assign n694_o = n692_o ^ n693_o; + /* T80.vhd:738:147 */ + assign n695_o = n681_o[7]; + /* T80.vhd:738:140 */ + assign n696_o = n694_o ^ n695_o; + /* T80.vhd:738:62 */ + assign n697_o = ~n696_o; + assign n698_o = {n697_o, n674_o, n675_o}; + assign n699_o = f[2]; + assign n700_o = {n699_o, n646_o}; + /* T80.vhd:732:41 */ + assign n701_o = n667_o ? n698_o : n700_o; + assign n702_o = n640_o[1]; + assign n703_o = n629_o[1]; + assign n704_o = n617_o[1]; + assign n705_o = f[4]; + /* T80.vhd:706:49 */ + assign n706_o = i_cpl ? n704_o : n705_o; + /* T80.vhd:714:49 */ + assign n707_o = i_ccf ? n703_o : n706_o; + /* T80.vhd:722:49 */ + assign n708_o = i_scf ? n702_o : n707_o; + assign n709_o = f[4]; + /* T80.vhd:615:41 */ + assign n710_o = t_res ? n708_o : n709_o; + /* T80.vhd:732:41 */ + assign n711_o = n667_o ? n676_o : n710_o; + assign n712_o = n640_o[2]; + assign n713_o = n629_o[2]; + assign n714_o = n617_o[2]; + assign n715_o = f[5]; + /* T80.vhd:706:49 */ + assign n716_o = i_cpl ? n714_o : n715_o; + /* T80.vhd:714:49 */ + assign n717_o = i_ccf ? n713_o : n716_o; + /* T80.vhd:722:49 */ + assign n718_o = i_scf ? n712_o : n717_o; + assign n719_o = f[5]; + /* T80.vhd:615:41 */ + assign n720_o = t_res ? n718_o : n719_o; + assign n721_o = n640_o[0]; + assign n722_o = n629_o[0]; + assign n723_o = n617_o[0]; + assign n724_o = f[3]; + /* T80.vhd:706:49 */ + assign n725_o = i_cpl ? n723_o : n724_o; + /* T80.vhd:714:49 */ + assign n726_o = i_ccf ? n722_o : n725_o; + /* T80.vhd:722:49 */ + assign n727_o = i_scf ? n721_o : n726_o; + assign n728_o = f[3]; + /* T80.vhd:615:41 */ + assign n729_o = t_res ? n727_o : n728_o; + /* T80.vhd:741:51 */ + assign n732_o = tstate == 3'b010; + /* T80.vhd:741:55 */ + assign n733_o = wait_n & n732_o; + /* T80.vhd:742:57 */ + assign n735_o = iset == 2'b01; + /* T80.vhd:742:75 */ + assign n737_o = mcycle == 3'b111; + /* T80.vhd:742:64 */ + assign n738_o = n737_o & n735_o; + /* T80.vhd:741:41 */ + assign n739_o = n760_o ? dinst : ir; + /* T80.vhd:746:83 */ + assign n740_o = {{8{di_reg[7]}}, di_reg}; // sext + /* T80.vhd:746:83 */ + assign n741_o = pc + n740_o; + /* T80.vhd:747:91 */ + assign n742_o = {{8{di_reg[7]}}, di_reg}; // sext + /* T80.vhd:747:91 */ + assign n743_o = pc + n742_o; + /* T80.vhd:749:66 */ + assign n745_o = pc + 16'b0000000000000001; + /* T80.vhd:748:49 */ + assign n746_o = inc_pc ? n745_o : n649_o; + /* T80.vhd:745:49 */ + assign n747_o = jumpe ? n741_o : n746_o; + /* T80.vhd:745:49 */ + assign n748_o = jumpe ? n743_o : n650_o; + /* T80.vhd:752:66 */ + assign n750_o = pc - 16'b0000000000000010; + /* T80.vhd:751:49 */ + assign n751_o = btr_r ? n750_o : n747_o; + /* T80.vhd:756:77 */ + assign n752_o = ir[5:3]; + assign n754_o = n753_o[15:6]; + assign n755_o = n753_o[2:0]; + assign n756_o = {n754_o, n752_o, n755_o}; + /* T80.vhd:754:49 */ + assign n757_o = rstp ? n756_o : n748_o; + /* T80.vhd:741:41 */ + assign n758_o = n733_o ? n751_o : n649_o; + /* T80.vhd:741:41 */ + assign n759_o = n733_o ? n757_o : n650_o; + /* T80.vhd:741:41 */ + assign n760_o = n733_o & n738_o; + /* T80.vhd:759:51 */ + assign n762_o = tstate == 3'b011; + /* T80.vhd:759:66 */ + assign n764_o = mcycle == 3'b110; + /* T80.vhd:759:55 */ + assign n765_o = n764_o & n762_o; + /* T80.vhd:760:88 */ + assign n766_o = {{8{di_reg[7]}}, di_reg}; // sext + /* T80.vhd:760:88 */ + assign n767_o = regbusc + n766_o; + /* T80.vhd:759:41 */ + assign n768_o = n765_o ? n767_o : n759_o; + /* T80.vhd:763:51 */ + assign n770_o = mcycle == 3'b011; + /* T80.vhd:763:70 */ + assign n772_o = tstate == 3'b100; + /* T80.vhd:763:59 */ + assign n773_o = n772_o & n770_o; + /* T80.vhd:763:85 */ + assign n774_o = ~no_btr; + /* T80.vhd:763:74 */ + assign n775_o = n774_o & n773_o; + /* T80.vhd:764:63 */ + assign n776_o = i_bt | i_bc; + /* T80.vhd:765:83 */ + assign n779_o = pc - 16'b0000000000000001; + /* T80.vhd:763:41 */ + assign n780_o = n781_o ? n779_o : n768_o; + /* T80.vhd:763:41 */ + assign n781_o = n775_o & n776_o; + /* T80.vhd:769:52 */ + assign n783_o = tstate == 3'b010; + /* T80.vhd:769:56 */ + assign n784_o = wait_n & n783_o; + /* T80.vhd:769:85 */ + assign n786_o = tstate == 3'b100; + /* T80.vhd:769:100 */ + assign n788_o = mcycle == 3'b001; + /* T80.vhd:769:89 */ + assign n789_o = n788_o & n786_o; + /* T80.vhd:769:74 */ + assign n790_o = n784_o | n789_o; + /* T80.vhd:770:61 */ + assign n791_o = incdec_16[2:0]; + /* T80.vhd:770:74 */ + assign n793_o = n791_o == 3'b111; + /* T80.vhd:771:69 */ + assign n794_o = incdec_16[3]; + /* T80.vhd:772:74 */ + assign n796_o = sp - 16'b0000000000000001; + /* T80.vhd:774:74 */ + assign n798_o = sp + 16'b0000000000000001; + /* T80.vhd:771:57 */ + assign n799_o = n794_o ? n796_o : n798_o; + /* T80.vhd:769:41 */ + assign n800_o = n801_o ? n799_o : sp; + /* T80.vhd:769:41 */ + assign n801_o = n790_o & n793_o; + /* T80.vhd:779:41 */ + assign n802_o = ldsphl ? regbusc : n800_o; + /* T80.vhd:782:41 */ + assign n803_o = exchangeaf ? ap : n616_o; + assign n804_o = f[7:6]; + assign n805_o = {n804_o, n720_o, n711_o, n729_o, n701_o}; + /* T80.vhd:782:41 */ + assign n807_o = exchangeaf ? acc : ap; + /* T80.vhd:782:41 */ + assign n808_o = exchangeaf ? f : fp; + /* T80.vhd:789:62 */ + assign n809_o = ~alternate; + /* T80.vhd:788:41 */ + assign n810_o = exchangers ? n809_o : alternate; + /* T80.vhd:562:33 */ + assign n811_o = n420_o ? n478_o : n643_o; + /* T80.vhd:562:33 */ + assign n812_o = n420_o ? acc : n803_o; + /* T80.vhd:562:33 */ + assign n814_o = n420_o ? ap : n807_o; + /* T80.vhd:562:33 */ + assign n815_o = n420_o ? fp : n808_o; + /* T80.vhd:562:33 */ + assign n817_o = n420_o & n423_o; + /* T80.vhd:562:33 */ + assign n818_o = n420_o ? sp : n802_o; + /* T80.vhd:562:33 */ + assign n819_o = n420_o ? n439_o : n758_o; + /* T80.vhd:562:33 */ + assign n820_o = n420_o ? alternate : n810_o; + /* T80.vhd:562:33 */ + assign n821_o = n420_o ? wz : n780_o; + /* T80.vhd:562:33 */ + assign n822_o = n420_o ? n482_o : n739_o; + /* T80.vhd:562:33 */ + assign n823_o = n420_o ? n483_o : n491_o; + /* T80.vhd:562:33 */ + assign n824_o = n420_o & n423_o; + /* T80.vhd:562:33 */ + assign n825_o = n420_o ? n485_o : n494_o; + /* T80.vhd:562:33 */ + assign n826_o = n420_o ? btr_r : n651_o; + /* T80.vhd:562:33 */ + assign n828_o = n420_o ? 4'b0000 : n653_o; + /* T80.vhd:562:33 */ + assign n831_o = n420_o ? 1'b0 : n655_o; + /* T80.vhd:793:43 */ + assign n835_o = tstate == 3'b011; + assign n836_o = wz[7:0]; + assign n837_o = n779_o[7:0]; + assign n838_o = n767_o[7:0]; + assign n839_o = n756_o[7:0]; + assign n840_o = n743_o[7:0]; + assign n841_o = id16[7:0]; + assign n842_o = wz[7:0]; + assign n843_o = wz[7:0]; + assign n844_o = wz[7:0]; + assign n845_o = wz[7:0]; + assign n846_o = wz[7:0]; + assign n847_o = n583_o[7:0]; + /* T80.vhd:631:49 */ + assign n848_o = n509_o ? n846_o : n847_o; + /* T80.vhd:628:49 */ + assign n849_o = n503_o ? n845_o : n848_o; + /* T80.vhd:625:49 */ + assign n850_o = n501_o ? n844_o : n849_o; + /* T80.vhd:622:49 */ + assign n851_o = jumpxy ? n843_o : n850_o; + /* T80.vhd:617:49 */ + assign n852_o = jump ? n842_o : n851_o; + /* T80.vhd:699:49 */ + assign n853_o = n607_o ? n841_o : n852_o; + assign n854_o = wz[7:0]; + /* T80.vhd:615:41 */ + assign n855_o = t_res ? n853_o : n854_o; + /* T80.vhd:745:49 */ + assign n856_o = jumpe ? n840_o : n855_o; + /* T80.vhd:754:49 */ + assign n857_o = rstp ? n839_o : n856_o; + assign n858_o = id16[7:0]; + assign n859_o = wz[7:0]; + assign n860_o = wz[7:0]; + assign n861_o = wz[7:0]; + assign n862_o = wz[7:0]; + assign n863_o = wz[7:0]; + assign n864_o = n583_o[7:0]; + /* T80.vhd:631:49 */ + assign n865_o = n509_o ? n863_o : n864_o; + /* T80.vhd:628:49 */ + assign n866_o = n503_o ? n862_o : n865_o; + /* T80.vhd:625:49 */ + assign n867_o = n501_o ? n861_o : n866_o; + /* T80.vhd:622:49 */ + assign n868_o = jumpxy ? n860_o : n867_o; + /* T80.vhd:617:49 */ + assign n869_o = jump ? n859_o : n868_o; + /* T80.vhd:699:49 */ + assign n870_o = n607_o ? n858_o : n869_o; + assign n871_o = wz[7:0]; + /* T80.vhd:615:41 */ + assign n872_o = t_res ? n870_o : n871_o; + /* T80.vhd:741:41 */ + assign n873_o = n733_o ? n857_o : n872_o; + /* T80.vhd:759:41 */ + assign n874_o = n765_o ? n838_o : n873_o; + /* T80.vhd:763:41 */ + assign n875_o = n781_o ? n837_o : n874_o; + /* T80.vhd:562:33 */ + assign n876_o = n420_o ? n836_o : n875_o; + /* T80.vhd:794:41 */ + assign n877_o = ldz ? di_reg : n876_o; + assign n878_o = wz[15:8]; + assign n879_o = n779_o[15:8]; + assign n880_o = n767_o[15:8]; + assign n881_o = n756_o[15:8]; + assign n882_o = n743_o[15:8]; + assign n883_o = id16[15:8]; + assign n884_o = wz[15:8]; + assign n885_o = wz[15:8]; + assign n886_o = wz[15:8]; + assign n887_o = wz[15:8]; + assign n888_o = wz[15:8]; + assign n889_o = n583_o[15:8]; + /* T80.vhd:631:49 */ + assign n890_o = n509_o ? n888_o : n889_o; + /* T80.vhd:628:49 */ + assign n891_o = n503_o ? n887_o : n890_o; + /* T80.vhd:625:49 */ + assign n892_o = n501_o ? n886_o : n891_o; + /* T80.vhd:622:49 */ + assign n893_o = jumpxy ? n885_o : n892_o; + /* T80.vhd:617:49 */ + assign n894_o = jump ? n884_o : n893_o; + /* T80.vhd:699:49 */ + assign n895_o = n607_o ? n883_o : n894_o; + assign n896_o = wz[15:8]; + /* T80.vhd:615:41 */ + assign n897_o = t_res ? n895_o : n896_o; + /* T80.vhd:745:49 */ + assign n898_o = jumpe ? n882_o : n897_o; + /* T80.vhd:754:49 */ + assign n899_o = rstp ? n881_o : n898_o; + assign n900_o = id16[15:8]; + assign n901_o = wz[15:8]; + assign n902_o = wz[15:8]; + assign n903_o = wz[15:8]; + assign n904_o = wz[15:8]; + assign n905_o = wz[15:8]; + assign n906_o = n583_o[15:8]; + /* T80.vhd:631:49 */ + assign n907_o = n509_o ? n905_o : n906_o; + /* T80.vhd:628:49 */ + assign n908_o = n503_o ? n904_o : n907_o; + /* T80.vhd:625:49 */ + assign n909_o = n501_o ? n903_o : n908_o; + /* T80.vhd:622:49 */ + assign n910_o = jumpxy ? n902_o : n909_o; + /* T80.vhd:617:49 */ + assign n911_o = jump ? n901_o : n910_o; + /* T80.vhd:699:49 */ + assign n912_o = n607_o ? n900_o : n911_o; + assign n913_o = wz[15:8]; + /* T80.vhd:615:41 */ + assign n914_o = t_res ? n912_o : n913_o; + /* T80.vhd:741:41 */ + assign n915_o = n733_o ? n899_o : n914_o; + /* T80.vhd:759:41 */ + assign n916_o = n765_o ? n880_o : n915_o; + /* T80.vhd:763:41 */ + assign n917_o = n781_o ? n879_o : n916_o; + /* T80.vhd:562:33 */ + assign n918_o = n420_o ? n878_o : n917_o; + /* T80.vhd:797:41 */ + assign n919_o = ldw ? di_reg : n918_o; + /* T80.vhd:801:54 */ + assign n920_o = special_ld[2]; + /* T80.vhd:802:64 */ + assign n921_o = special_ld[1:0]; + /* T80.vhd:806:71 */ + assign n922_o = i[7]; + /* T80.vhd:808:62 */ + assign n924_o = i == 8'b00000000; + /* T80.vhd:808:57 */ + assign n927_o = n924_o ? 1'b1 : 1'b0; + /* T80.vhd:814:71 */ + assign n928_o = i[5]; + /* T80.vhd:816:71 */ + assign n930_o = i[3]; + /* T80.vhd:803:49 */ + assign n933_o = n921_o == 2'b00; + /* T80.vhd:823:71 */ + assign n934_o = r[7]; + /* T80.vhd:825:62 */ + assign n936_o = r == 8'b00000000; + /* T80.vhd:825:57 */ + assign n939_o = n936_o ? 1'b1 : 1'b0; + /* T80.vhd:831:71 */ + assign n940_o = r[5]; + /* T80.vhd:833:71 */ + assign n942_o = r[3]; + /* T80.vhd:820:49 */ + assign n945_o = n921_o == 2'b01; + /* T80.vhd:836:49 */ + assign n947_o = n921_o == 2'b10; + assign n948_o = {n947_o, n945_o, n933_o}; + /* T80.vhd:802:49 */ + always @* + case (n948_o) + 3'b100: n949_o = n812_o; + 3'b010: n949_o = r; + 3'b001: n949_o = i; + default: n949_o = n812_o; + endcase + assign n950_o = f[1]; + assign n951_o = fp[1]; + assign n952_o = n805_o[1]; + /* T80.vhd:782:41 */ + assign n953_o = exchangeaf ? n951_o : n952_o; + /* T80.vhd:562:33 */ + assign n954_o = n420_o ? n950_o : n953_o; + /* T80.vhd:802:49 */ + always @* + case (n948_o) + 3'b100: n955_o = n954_o; + 3'b010: n955_o = 1'b0; + 3'b001: n955_o = 1'b0; + default: n955_o = n954_o; + endcase + assign n956_o = f[2]; + assign n957_o = fp[2]; + assign n958_o = n805_o[2]; + /* T80.vhd:782:41 */ + assign n959_o = exchangeaf ? n957_o : n958_o; + /* T80.vhd:562:33 */ + assign n960_o = n420_o ? n956_o : n959_o; + /* T80.vhd:802:49 */ + always @* + case (n948_o) + 3'b100: n961_o = n960_o; + 3'b010: n961_o = inte_ff2; + 3'b001: n961_o = inte_ff2; + default: n961_o = n960_o; + endcase + assign n962_o = f[3]; + assign n963_o = fp[3]; + assign n964_o = n805_o[3]; + /* T80.vhd:782:41 */ + assign n965_o = exchangeaf ? n963_o : n964_o; + /* T80.vhd:562:33 */ + assign n966_o = n420_o ? n962_o : n965_o; + /* T80.vhd:802:49 */ + always @* + case (n948_o) + 3'b100: n967_o = n966_o; + 3'b010: n967_o = n942_o; + 3'b001: n967_o = n930_o; + default: n967_o = n966_o; + endcase + assign n968_o = f[4]; + assign n969_o = fp[4]; + assign n970_o = n805_o[4]; + /* T80.vhd:782:41 */ + assign n971_o = exchangeaf ? n969_o : n970_o; + /* T80.vhd:562:33 */ + assign n972_o = n420_o ? n968_o : n971_o; + /* T80.vhd:802:49 */ + always @* + case (n948_o) + 3'b100: n973_o = n972_o; + 3'b010: n973_o = 1'b0; + 3'b001: n973_o = 1'b0; + default: n973_o = n972_o; + endcase + assign n974_o = f[5]; + assign n975_o = fp[5]; + assign n976_o = n805_o[5]; + /* T80.vhd:782:41 */ + assign n977_o = exchangeaf ? n975_o : n976_o; + /* T80.vhd:562:33 */ + assign n978_o = n420_o ? n974_o : n977_o; + /* T80.vhd:802:49 */ + always @* + case (n948_o) + 3'b100: n979_o = n978_o; + 3'b010: n979_o = n940_o; + 3'b001: n979_o = n928_o; + default: n979_o = n978_o; + endcase + assign n980_o = f[6]; + assign n981_o = fp[6]; + assign n982_o = n805_o[6]; + /* T80.vhd:782:41 */ + assign n983_o = exchangeaf ? n981_o : n982_o; + /* T80.vhd:562:33 */ + assign n984_o = n420_o ? n980_o : n983_o; + /* T80.vhd:802:49 */ + always @* + case (n948_o) + 3'b100: n985_o = n984_o; + 3'b010: n985_o = n939_o; + 3'b001: n985_o = n927_o; + default: n985_o = n984_o; + endcase + assign n986_o = f[7]; + assign n987_o = fp[7]; + assign n988_o = n805_o[7]; + /* T80.vhd:782:41 */ + assign n989_o = exchangeaf ? n987_o : n988_o; + /* T80.vhd:562:33 */ + assign n990_o = n420_o ? n986_o : n989_o; + /* T80.vhd:802:49 */ + always @* + case (n948_o) + 3'b100: n991_o = n990_o; + 3'b010: n991_o = n934_o; + 3'b001: n991_o = n922_o; + default: n991_o = n990_o; + endcase + /* T80.vhd:802:49 */ + always @* + case (n948_o) + 3'b100: n992_o = acc; + 3'b010: n992_o = i; + 3'b001: n992_o = i; + default: n992_o = i; + endcase + assign n993_o = r[7]; + assign n994_o = {n993_o, n480_o}; + /* T80.vhd:802:49 */ + always @* + case (n948_o) + 3'b100: n995_o = n994_o; + 3'b010: n995_o = n994_o; + 3'b001: n995_o = n994_o; + default: n995_o = acc; + endcase + /* T80.vhd:793:33 */ + assign n996_o = n1008_o ? n949_o : n812_o; + assign n997_o = {n991_o, n985_o, n979_o, n973_o, n967_o, n961_o, n955_o}; + assign n998_o = f[7:1]; + assign n999_o = fp[7:1]; + assign n1000_o = n805_o[7:1]; + /* T80.vhd:782:41 */ + assign n1001_o = exchangeaf ? n999_o : n1000_o; + /* T80.vhd:562:33 */ + assign n1002_o = n420_o ? n998_o : n1001_o; + /* T80.vhd:801:41 */ + assign n1003_o = n920_o ? n997_o : n1002_o; + /* T80.vhd:543:25 */ + assign n1004_o = n1233_o ? n992_o : i; + assign n1005_o = r[7]; + assign n1006_o = {n1005_o, n480_o}; + /* T80.vhd:801:41 */ + assign n1007_o = n920_o ? n995_o : n1006_o; + /* T80.vhd:793:33 */ + assign n1008_o = n835_o & n920_o; + assign n1009_o = f[7:1]; + assign n1010_o = fp[7:1]; + assign n1011_o = n805_o[7:1]; + /* T80.vhd:782:41 */ + assign n1012_o = exchangeaf ? n1010_o : n1011_o; + /* T80.vhd:562:33 */ + assign n1013_o = n420_o ? n1009_o : n1012_o; + /* T80.vhd:793:33 */ + assign n1014_o = n835_o ? n1003_o : n1013_o; + assign n1015_o = f[0]; + assign n1016_o = fp[0]; + assign n1017_o = n805_o[0]; + /* T80.vhd:782:41 */ + assign n1018_o = exchangeaf ? n1016_o : n1017_o; + /* T80.vhd:562:33 */ + assign n1019_o = n420_o ? n1015_o : n1018_o; + /* T80.vhd:793:33 */ + assign n1020_o = n835_o & n920_o; + assign n1021_o = r[7]; + assign n1022_o = {n1021_o, n480_o}; + /* T80.vhd:793:33 */ + assign n1023_o = n835_o ? n1007_o : n1022_o; + assign n1024_o = {n919_o, n877_o}; + /* T80.vhd:793:33 */ + assign n1025_o = n835_o ? n1024_o : n821_o; + /* T80.vhd:844:44 */ + assign n1026_o = ~i_djnz; + /* T80.vhd:844:50 */ + assign n1027_o = save_alu_r & n1026_o; + /* T80.vhd:844:84 */ + assign n1029_o = alu_op_r == 4'b1001; + /* T80.vhd:844:72 */ + assign n1030_o = n1027_o | n1029_o; + /* T80.vhd:853:71 */ + assign n1031_o = f_out[7:1]; + /* T80.vhd:854:64 */ + assign n1032_o = ~preservec_r; + /* T80.vhd:855:75 */ + assign n1033_o = f_out[0]; + /* T80.vhd:854:49 */ + assign n1034_o = n1032_o ? n1033_o : n1019_o; + assign n1035_o = {n1031_o, n1034_o}; + assign n1036_o = {n1014_o, n1019_o}; + /* T80.vhd:859:48 */ + assign n1038_o = i_inrc & t_res; + /* T80.vhd:862:60 */ + assign n1041_o = di_reg[3]; + /* T80.vhd:863:60 */ + assign n1042_o = di_reg[5]; + /* T80.vhd:864:63 */ + assign n1044_o = di_reg == 8'b00000000; + /* T80.vhd:864:41 */ + assign n1047_o = n1044_o ? 1'b1 : 1'b0; + /* T80.vhd:869:60 */ + assign n1048_o = di_reg[7]; + /* T80.vhd:870:65 */ + assign n1049_o = di_reg[0]; + /* T80.vhd:870:79 */ + assign n1050_o = di_reg[1]; + /* T80.vhd:870:69 */ + assign n1051_o = n1049_o ^ n1050_o; + /* T80.vhd:870:93 */ + assign n1052_o = di_reg[2]; + /* T80.vhd:870:83 */ + assign n1053_o = n1051_o ^ n1052_o; + /* T80.vhd:870:107 */ + assign n1054_o = di_reg[3]; + /* T80.vhd:870:97 */ + assign n1055_o = n1053_o ^ n1054_o; + /* T80.vhd:871:55 */ + assign n1056_o = di_reg[4]; + /* T80.vhd:870:111 */ + assign n1057_o = n1055_o ^ n1056_o; + /* T80.vhd:871:69 */ + assign n1058_o = di_reg[5]; + /* T80.vhd:871:59 */ + assign n1059_o = n1057_o ^ n1058_o; + /* T80.vhd:871:83 */ + assign n1060_o = di_reg[6]; + /* T80.vhd:871:73 */ + assign n1061_o = n1059_o ^ n1060_o; + /* T80.vhd:871:97 */ + assign n1062_o = di_reg[7]; + /* T80.vhd:871:87 */ + assign n1063_o = n1061_o ^ n1062_o; + /* T80.vhd:870:54 */ + assign n1064_o = ~n1063_o; + assign n1065_o = {n1048_o, n1047_o, n1042_o, 1'b0, n1041_o, n1064_o, 1'b0}; + assign n1070_o = n1035_o[0]; + assign n1071_o = n1036_o[0]; + /* T80.vhd:844:33 */ + assign n1072_o = n1030_o ? n1070_o : n1071_o; + /* T80.vhd:874:43 */ + assign n1074_o = tstate == 3'b001; + /* T80.vhd:874:64 */ + assign n1075_o = ~auto_wait_t1; + /* T80.vhd:874:47 */ + assign n1076_o = n1075_o & n1074_o; + /* T80.vhd:876:57 */ + assign n1077_o = i_rld | i_rrd; + /* T80.vhd:877:50 */ + assign n1078_o = ~i_rxdd; + /* T80.vhd:877:41 */ + assign n1079_o = n1078_o ? busb : n2138_q; + /* T80.vhd:881:73 */ + assign n1080_o = busa[3:0]; + /* T80.vhd:882:73 */ + assign n1081_o = busb[3:0]; + assign n1082_o = {n1081_o, n1080_o}; + /* T80.vhd:880:41 */ + assign n1083_o = i_rld ? n1082_o : n1079_o; + /* T80.vhd:885:73 */ + assign n1084_o = busb[7:4]; + /* T80.vhd:886:73 */ + assign n1085_o = busa[3:0]; + assign n1086_o = {n1085_o, n1084_o}; + /* T80.vhd:884:41 */ + assign n1087_o = i_rrd ? n1086_o : n1083_o; + /* T80.vhd:874:33 */ + assign n1088_o = n1076_o ? n1087_o : n2138_q; + /* T80.vhd:543:25 */ + assign n1089_o = n1252_o ? n1077_o : i_rxdd; + assign n1092_o = {1'b1, 4'b0111}; + assign n1093_o = {read_to_reg, set_busa_to}; + /* T80.vhd:893:41 */ + assign n1094_o = read_to_acc ? n1092_o : n1093_o; + /* T80.vhd:890:33 */ + assign n1096_o = t_res ? n1094_o : 5'b00000; + /* T80.vhd:899:43 */ + assign n1099_o = tstate == 3'b001; + /* T80.vhd:899:47 */ + assign n1100_o = i_bt & n1099_o; + /* T80.vhd:900:59 */ + assign n1101_o = alu_q[3]; + /* T80.vhd:901:59 */ + assign n1102_o = alu_q[1]; + assign n1105_o = {n1102_o, 1'b0, n1101_o}; + assign n1106_o = n1065_o[0]; + assign n1107_o = n1035_o[1]; + assign n1108_o = n1036_o[1]; + /* T80.vhd:844:33 */ + assign n1109_o = n1030_o ? n1107_o : n1108_o; + /* T80.vhd:859:33 */ + assign n1110_o = n1038_o ? n1106_o : n1109_o; + /* T80.vhd:899:33 */ + assign n1111_o = n1100_o ? 1'b0 : n1110_o; + assign n1123_o = n1065_o[6:5]; + assign n1124_o = n1035_o[7:6]; + assign n1125_o = n1036_o[7:6]; + /* T80.vhd:844:33 */ + assign n1126_o = n1030_o ? n1124_o : n1125_o; + /* T80.vhd:859:33 */ + assign n1127_o = n1038_o ? n1123_o : n1126_o; + assign n1128_o = n1065_o[1]; + assign n1129_o = n1035_o[2]; + assign n1130_o = n1036_o[2]; + /* T80.vhd:844:33 */ + assign n1131_o = n1030_o ? n1129_o : n1130_o; + /* T80.vhd:859:33 */ + assign n1132_o = n1038_o ? n1128_o : n1131_o; + /* T80.vhd:905:43 */ + assign n1134_o = tstate == 3'b001; + /* T80.vhd:905:47 */ + assign n1135_o = i_bc & n1134_o; + /* T80.vhd:906:72 */ + assign n1136_o = f_out[4]; + /* T80.vhd:906:65 */ + assign n1138_o = {7'b0000000, n1136_o}; + /* T80.vhd:906:52 */ + assign n1139_o = alu_q - n1138_o; + /* T80.vhd:907:55 */ + assign n1140_o = n1139_o[3]; + /* T80.vhd:908:55 */ + assign n1141_o = n1139_o[1]; + assign n1142_o = n1105_o[0]; + assign n1143_o = n1065_o[2]; + assign n1144_o = n1035_o[3]; + assign n1145_o = n1036_o[3]; + /* T80.vhd:844:33 */ + assign n1146_o = n1030_o ? n1144_o : n1145_o; + /* T80.vhd:859:33 */ + assign n1147_o = n1038_o ? n1143_o : n1146_o; + /* T80.vhd:899:33 */ + assign n1148_o = n1100_o ? n1142_o : n1147_o; + /* T80.vhd:905:33 */ + assign n1149_o = n1135_o ? n1140_o : n1148_o; + assign n1150_o = n1105_o[2]; + assign n1151_o = n1065_o[4]; + assign n1152_o = n1035_o[5]; + assign n1153_o = n1036_o[5]; + /* T80.vhd:844:33 */ + assign n1154_o = n1030_o ? n1152_o : n1153_o; + /* T80.vhd:859:33 */ + assign n1155_o = n1038_o ? n1151_o : n1154_o; + /* T80.vhd:899:33 */ + assign n1156_o = n1100_o ? n1150_o : n1155_o; + /* T80.vhd:905:33 */ + assign n1157_o = n1135_o ? n1141_o : n1156_o; + assign n1165_o = n1105_o[1]; + assign n1166_o = n1065_o[3]; + assign n1167_o = n1035_o[4]; + assign n1168_o = n1036_o[4]; + /* T80.vhd:844:33 */ + assign n1169_o = n1030_o ? n1167_o : n1168_o; + /* T80.vhd:859:33 */ + assign n1170_o = n1038_o ? n1166_o : n1169_o; + /* T80.vhd:899:33 */ + assign n1171_o = n1100_o ? n1165_o : n1170_o; + /* T80.vhd:910:47 */ + assign n1173_o = i_bc | i_bt; + /* T80.vhd:910:33 */ + assign n1174_o = n1173_o ? incdecz : n1132_o; + /* T80.vhd:914:44 */ + assign n1176_o = tstate == 3'b001; + /* T80.vhd:914:63 */ + assign n1177_o = ~save_alu_r; + /* T80.vhd:914:48 */ + assign n1178_o = n1177_o & n1176_o; + /* T80.vhd:914:86 */ + assign n1179_o = ~auto_wait_t1; + /* T80.vhd:914:69 */ + assign n1180_o = n1179_o & n1178_o; + /* T80.vhd:915:72 */ + assign n1182_o = alu_op_r != 4'b0111; + /* T80.vhd:915:59 */ + assign n1183_o = n1182_o & save_alu_r; + /* T80.vhd:914:93 */ + assign n1184_o = n1180_o | n1183_o; + /* T80.vhd:917:41 */ + assign n1186_o = read_to_reg_r == 5'b10111; + /* T80.vhd:919:41 */ + assign n1188_o = read_to_reg_r == 5'b10110; + /* T80.vhd:921:41 */ + assign n1190_o = read_to_reg_r == 5'b11000; + /* T80.vhd:923:41 */ + assign n1192_o = read_to_reg_r == 5'b11001; + /* T80.vhd:925:41 */ + assign n1194_o = read_to_reg_r == 5'b11011; + assign n1195_o = {n1194_o, n1192_o, n1190_o, n1188_o, n1186_o}; + /* T80.vhd:916:41 */ + always @* + case (n1195_o) + 5'b10000: n1196_o = n1088_o; + 5'b01000: n1196_o = n1088_o; + 5'b00100: n1196_o = n1088_o; + 5'b00010: n1196_o = save_mux; + 5'b00001: n1196_o = n1088_o; + default: n1196_o = n1088_o; + endcase + /* T80.vhd:916:41 */ + always @* + case (n1195_o) + 5'b10000: n1197_o = n996_o; + 5'b01000: n1197_o = n996_o; + 5'b00100: n1197_o = n996_o; + 5'b00010: n1197_o = n996_o; + 5'b00001: n1197_o = save_mux; + default: n1197_o = n996_o; + endcase + assign n1198_o = {n1127_o, n1157_o, n1171_o, n1149_o, n1174_o, n1111_o, n1072_o}; + /* T80.vhd:916:41 */ + always @* + case (n1195_o) + 5'b10000: n1199_o = save_mux; + 5'b01000: n1199_o = n1198_o; + 5'b00100: n1199_o = n1198_o; + 5'b00010: n1199_o = n1198_o; + 5'b00001: n1199_o = n1198_o; + default: n1199_o = n1198_o; + endcase + assign n1200_o = sp[7:0]; + assign n1201_o = regbusc[7:0]; + assign n1202_o = n796_o[7:0]; + assign n1203_o = n798_o[7:0]; + /* T80.vhd:771:57 */ + assign n1204_o = n794_o ? n1202_o : n1203_o; + assign n1205_o = sp[7:0]; + /* T80.vhd:769:41 */ + assign n1206_o = n801_o ? n1204_o : n1205_o; + /* T80.vhd:779:41 */ + assign n1207_o = ldsphl ? n1201_o : n1206_o; + /* T80.vhd:562:33 */ + assign n1208_o = n420_o ? n1200_o : n1207_o; + /* T80.vhd:916:41 */ + always @* + case (n1195_o) + 5'b10000: n1209_o = n1208_o; + 5'b01000: n1209_o = n1208_o; + 5'b00100: n1209_o = save_mux; + 5'b00010: n1209_o = n1208_o; + 5'b00001: n1209_o = n1208_o; + default: n1209_o = n1208_o; + endcase + assign n1210_o = sp[15:8]; + assign n1211_o = regbusc[15:8]; + assign n1212_o = n796_o[15:8]; + assign n1213_o = n798_o[15:8]; + /* T80.vhd:771:57 */ + assign n1214_o = n794_o ? n1212_o : n1213_o; + assign n1215_o = sp[15:8]; + /* T80.vhd:769:41 */ + assign n1216_o = n801_o ? n1214_o : n1215_o; + /* T80.vhd:779:41 */ + assign n1217_o = ldsphl ? n1211_o : n1216_o; + /* T80.vhd:562:33 */ + assign n1218_o = n420_o ? n1210_o : n1217_o; + /* T80.vhd:916:41 */ + always @* + case (n1195_o) + 5'b10000: n1219_o = n1218_o; + 5'b01000: n1219_o = save_mux; + 5'b00100: n1219_o = n1218_o; + 5'b00010: n1219_o = n1218_o; + 5'b00001: n1219_o = n1218_o; + default: n1219_o = n1218_o; + endcase + /* T80.vhd:929:41 */ + assign n1220_o = xybit_undoc ? alu_q : n1196_o; + /* T80.vhd:914:33 */ + assign n1221_o = n1184_o ? n1220_o : n1088_o; + /* T80.vhd:914:33 */ + assign n1222_o = n1184_o ? n1197_o : n996_o; + assign n1223_o = {n1127_o, n1157_o, n1171_o, n1149_o, n1174_o, n1111_o, n1072_o}; + /* T80.vhd:914:33 */ + assign n1224_o = n1184_o ? n1199_o : n1223_o; + assign n1225_o = {n1219_o, n1209_o}; + /* T80.vhd:914:33 */ + assign n1226_o = n1184_o ? n1225_o : n818_o; + /* T80.vhd:543:25 */ + assign n1227_o = clken ? n811_o : n2137_q; + /* T80.vhd:543:25 */ + assign n1228_o = clken ? n1221_o : n2138_q; + /* T80.vhd:543:25 */ + assign n1229_o = clken ? n1222_o : acc; + /* T80.vhd:543:25 */ + assign n1230_o = clken ? n1224_o : f; + /* T80.vhd:543:25 */ + assign n1231_o = clken ? n814_o : ap; + /* T80.vhd:543:25 */ + assign n1232_o = clken ? n815_o : fp; + /* T80.vhd:543:25 */ + assign n1233_o = clken & n1020_o; + /* T80.vhd:543:25 */ + assign n1234_o = clken ? n1023_o : r; + /* T80.vhd:543:25 */ + assign n1235_o = clken ? n1226_o : sp; + /* T80.vhd:543:25 */ + assign n1236_o = clken ? n819_o : pc; + /* T80.vhd:543:25 */ + assign n1237_o = clken ? n820_o : alternate; + /* T80.vhd:543:25 */ + assign n1238_o = clken ? n1025_o : wz; + /* T80.vhd:543:25 */ + assign n1239_o = clken ? n822_o : ir; + /* T80.vhd:543:25 */ + assign n1240_o = clken ? n823_o : iset; + /* T80.vhd:543:25 */ + assign n1241_o = clken & n401_o; + /* T80.vhd:543:25 */ + assign n1242_o = clken & n824_o; + /* T80.vhd:543:25 */ + assign n1243_o = clken ? n825_o : xy_ind; + /* T80.vhd:543:25 */ + assign n1244_o = clken ? n826_o : btr_r; + /* T80.vhd:543:25 */ + assign n1245_o = clken ? n1096_o : read_to_reg_r; + /* T80.vhd:543:25 */ + assign n1246_o = clken ? arith16 : arith16_r; + /* T80.vhd:543:25 */ + assign n1247_o = clken ? n415_o : z16_r; + /* T80.vhd:543:25 */ + assign n1248_o = clken ? n828_o : alu_op_r; + /* T80.vhd:543:25 */ + assign n1249_o = clken ? n831_o : save_alu_r; + /* T80.vhd:543:25 */ + assign n1250_o = clken ? preservec : preservec_r; + /* T80.vhd:543:25 */ + assign n1251_o = clken ? mcycles_d : mcycles; + /* T80.vhd:543:25 */ + assign n1252_o = clken & n1076_o; + /* T80.vhd:531:25 */ + assign n1255_o = dirset ? n398_o : n1227_o; + /* T80.vhd:531:25 */ + assign n1256_o = dirset ? n2138_q : n1228_o; + /* T80.vhd:531:25 */ + assign n1257_o = dirset ? n390_o : n1229_o; + /* T80.vhd:531:25 */ + assign n1258_o = dirset ? n391_o : n1230_o; + /* T80.vhd:531:25 */ + assign n1259_o = dirset ? n392_o : n1231_o; + /* T80.vhd:531:25 */ + assign n1260_o = dirset ? n393_o : n1232_o; + /* T80.vhd:531:25 */ + assign n1261_o = dirset ? n394_o : n1004_o; + /* T80.vhd:531:25 */ + assign n1262_o = dirset ? n395_o : n1234_o; + /* T80.vhd:531:25 */ + assign n1263_o = dirset ? n396_o : n1235_o; + /* T80.vhd:531:25 */ + assign n1264_o = dirset ? n397_o : n1236_o; + /* T80.vhd:531:25 */ + assign n1265_o = dirset ? alternate : n1237_o; + /* T80.vhd:531:25 */ + assign n1266_o = dirset ? wz : n1238_o; + /* T80.vhd:531:25 */ + assign n1267_o = dirset ? ir : n1239_o; + /* T80.vhd:531:25 */ + assign n1268_o = dirset ? iset : n1240_o; + /* T80.vhd:531:25 */ + assign n1269_o = dirset ? n399_o : n402_o; + /* T80.vhd:531:25 */ + assign n1270_o = dirset ? xy_state : n484_o; + /* T80.vhd:531:25 */ + assign n1271_o = dirset ? xy_ind : n1243_o; + /* T80.vhd:531:25 */ + assign n1272_o = dirset ? btr_r : n1244_o; + /* T80.vhd:531:25 */ + assign n1273_o = dirset ? read_to_reg_r : n1245_o; + /* T80.vhd:531:25 */ + assign n1274_o = dirset ? arith16_r : n1246_o; + /* T80.vhd:531:25 */ + assign n1275_o = dirset ? z16_r : n1247_o; + /* T80.vhd:531:25 */ + assign n1276_o = dirset ? alu_op_r : n1248_o; + /* T80.vhd:531:25 */ + assign n1277_o = dirset ? save_alu_r : n1249_o; + /* T80.vhd:531:25 */ + assign n1278_o = dirset ? preservec_r : n1250_o; + /* T80.vhd:531:25 */ + assign n1279_o = dirset ? mcycles : n1251_o; + /* T80.vhd:531:25 */ + assign n1280_o = dirset ? i_rxdd : n1089_o; + /* T80.vhd:947:70 */ + assign n1375_o = set_busa_to[2:1]; + /* T80.vhd:947:57 */ + assign n1376_o = {alternate, n1375_o}; + /* T80.vhd:948:43 */ + assign n1377_o = ~xy_ind; + /* T80.vhd:948:62 */ + assign n1379_o = xy_state != 2'b00; + /* T80.vhd:948:49 */ + assign n1380_o = n1379_o & n1377_o; + /* T80.vhd:948:85 */ + assign n1381_o = set_busa_to[2:1]; + /* T80.vhd:948:98 */ + assign n1383_o = n1381_o == 2'b10; + /* T80.vhd:948:70 */ + assign n1384_o = n1383_o & n1380_o; + /* T80.vhd:949:63 */ + assign n1385_o = xy_state[1]; + /* T80.vhd:949:67 */ + assign n1387_o = {n1385_o, 2'b11}; + /* T80.vhd:948:33 */ + assign n1388_o = n1384_o ? n1387_o : n1376_o; + /* T80.vhd:953:70 */ + assign n1389_o = set_busb_to[2:1]; + /* T80.vhd:953:57 */ + assign n1390_o = {alternate, n1389_o}; + /* T80.vhd:954:43 */ + assign n1391_o = ~xy_ind; + /* T80.vhd:954:62 */ + assign n1393_o = xy_state != 2'b00; + /* T80.vhd:954:49 */ + assign n1394_o = n1393_o & n1391_o; + /* T80.vhd:954:85 */ + assign n1395_o = set_busb_to[2:1]; + /* T80.vhd:954:98 */ + assign n1397_o = n1395_o == 2'b10; + /* T80.vhd:954:70 */ + assign n1398_o = n1397_o & n1394_o; + /* T80.vhd:955:63 */ + assign n1399_o = xy_state[1]; + /* T80.vhd:955:67 */ + assign n1401_o = {n1399_o, 2'b11}; + /* T80.vhd:954:33 */ + assign n1402_o = n1398_o ? n1401_o : n1390_o; + /* T80.vhd:959:68 */ + assign n1403_o = set_addr_to[1:0]; + /* T80.vhd:959:55 */ + assign n1404_o = {alternate, n1403_o}; + /* T80.vhd:961:50 */ + assign n1405_o = jumpxy | ldsphl; + /* T80.vhd:962:63 */ + assign n1407_o = {alternate, 2'b10}; + /* T80.vhd:961:33 */ + assign n1408_o = n1405_o ? n1407_o : n1404_o; + /* T80.vhd:964:51 */ + assign n1409_o = jumpxy | ldsphl; + /* T80.vhd:964:81 */ + assign n1411_o = xy_state != 2'b00; + /* T80.vhd:964:68 */ + assign n1412_o = n1411_o & n1409_o; + /* T80.vhd:964:101 */ + assign n1414_o = mcycle == 3'b110; + /* T80.vhd:964:90 */ + assign n1415_o = n1412_o | n1414_o; + /* T80.vhd:965:61 */ + assign n1416_o = xy_state[1]; + /* T80.vhd:965:65 */ + assign n1418_o = {n1416_o, 2'b11}; + /* T80.vhd:964:33 */ + assign n1419_o = n1415_o ? n1418_o : n1408_o; + /* T80.vhd:968:49 */ + assign n1420_o = save_alu_r & i_djnz; + /* T80.vhd:968:70 */ + assign n1422_o = 1'b1 & n1420_o; + /* T80.vhd:969:57 */ + assign n1423_o = f_out[6]; + /* T80.vhd:968:33 */ + assign n1424_o = n1422_o ? n1423_o : incdecz; + /* T80.vhd:971:44 */ + assign n1426_o = tstate == 3'b010; + /* T80.vhd:971:59 */ + assign n1428_o = tstate == 3'b011; + /* T80.vhd:971:74 */ + assign n1430_o = mcycle == 3'b001; + /* T80.vhd:971:63 */ + assign n1431_o = n1430_o & n1428_o; + /* T80.vhd:971:48 */ + assign n1432_o = n1426_o | n1431_o; + /* T80.vhd:971:97 */ + assign n1433_o = incdec_16[2:0]; + /* T80.vhd:971:110 */ + assign n1435_o = n1433_o == 3'b100; + /* T80.vhd:971:84 */ + assign n1436_o = n1435_o & n1432_o; + /* T80.vhd:972:49 */ + assign n1438_o = id16 == 16'b0000000000000000; + /* T80.vhd:972:41 */ + assign n1441_o = n1438_o ? 1'b0 : 1'b1; + /* T80.vhd:971:33 */ + assign n1442_o = n1436_o ? n1441_o : n1424_o; + /* T80.vhd:986:46 */ + assign n1454_o = incdec_16[1:0]; + /* T80.vhd:986:35 */ + assign n1455_o = {alternate, n1454_o}; + /* T80.vhd:986:72 */ + assign n1457_o = tstate == 3'b010; + /* T80.vhd:987:41 */ + assign n1459_o = tstate == 3'b011; + /* T80.vhd:987:56 */ + assign n1461_o = mcycle == 3'b001; + /* T80.vhd:987:45 */ + assign n1462_o = n1461_o & n1459_o; + /* T80.vhd:987:77 */ + assign n1463_o = incdec_16[2]; + /* T80.vhd:987:64 */ + assign n1464_o = n1463_o & n1462_o; + /* T80.vhd:986:76 */ + assign n1465_o = n1457_o | n1464_o; + /* T80.vhd:987:102 */ + assign n1467_o = xy_state == 2'b00; + /* T80.vhd:987:89 */ + assign n1468_o = n1467_o & n1465_o; + /* T80.vhd:986:59 */ + assign n1469_o = n1468_o ? n1455_o : n1487_o; + /* T80.vhd:988:33 */ + assign n1470_o = xy_state[1]; + /* T80.vhd:988:37 */ + assign n1472_o = {n1470_o, 2'b11}; + /* T80.vhd:988:57 */ + assign n1474_o = tstate == 3'b010; + /* T80.vhd:989:41 */ + assign n1476_o = tstate == 3'b011; + /* T80.vhd:989:56 */ + assign n1478_o = mcycle == 3'b001; + /* T80.vhd:989:45 */ + assign n1479_o = n1478_o & n1476_o; + /* T80.vhd:989:77 */ + assign n1480_o = incdec_16[2]; + /* T80.vhd:989:64 */ + assign n1481_o = n1480_o & n1479_o; + /* T80.vhd:988:61 */ + assign n1482_o = n1474_o | n1481_o; + /* T80.vhd:989:102 */ + assign n1483_o = incdec_16[1:0]; + /* T80.vhd:989:115 */ + assign n1485_o = n1483_o == 2'b10; + /* T80.vhd:989:89 */ + assign n1486_o = n1485_o & n1482_o; + /* T80.vhd:987:109 */ + assign n1487_o = n1486_o ? n1472_o : n1493_o; + /* T80.vhd:991:35 */ + assign n1489_o = {alternate, 2'b10}; + /* T80.vhd:991:75 */ + assign n1491_o = tstate == 3'b011; + /* T80.vhd:991:64 */ + assign n1492_o = n1491_o & exchangedh; + /* T80.vhd:989:122 */ + assign n1493_o = n1492_o ? n1489_o : n1499_o; + /* T80.vhd:992:35 */ + assign n1495_o = {alternate, 2'b01}; + /* T80.vhd:992:75 */ + assign n1497_o = tstate == 3'b100; + /* T80.vhd:992:64 */ + assign n1498_o = n1497_o & exchangedh; + /* T80.vhd:991:79 */ + assign n1499_o = n1498_o ? n1495_o : regaddra_r; + /* T80.vhd:998:35 */ + assign n1501_o = {alternate, 2'b01}; + /* T80.vhd:998:75 */ + assign n1503_o = tstate == 3'b011; + /* T80.vhd:998:64 */ + assign n1504_o = n1503_o & exchangedh; + /* T80.vhd:998:42 */ + assign n1505_o = n1504_o ? n1501_o : regaddrb_r; + /* T80.vhd:1002:33 */ + assign n1507_o = regbusa - 16'b0000000000000001; + /* T80.vhd:1002:51 */ + assign n1508_o = incdec_16[3]; + /* T80.vhd:1002:37 */ + assign n1509_o = n1508_o ? n1507_o : n1511_o; + /* T80.vhd:1003:41 */ + assign n1511_o = regbusa + 16'b0000000000000001; + /* T80.vhd:1010:28 */ + assign n1515_o = tstate == 3'b001; + /* T80.vhd:1010:47 */ + assign n1516_o = ~save_alu_r; + /* T80.vhd:1010:32 */ + assign n1517_o = n1516_o & n1515_o; + /* T80.vhd:1010:70 */ + assign n1518_o = ~auto_wait_t1; + /* T80.vhd:1010:53 */ + assign n1519_o = n1518_o & n1517_o; + /* T80.vhd:1011:56 */ + assign n1521_o = alu_op_r != 4'b0111; + /* T80.vhd:1011:43 */ + assign n1522_o = n1521_o & save_alu_r; + /* T80.vhd:1010:77 */ + assign n1523_o = n1519_o | n1522_o; + /* T80.vhd:1014:60 */ + assign n1524_o = read_to_reg_r[0]; + /* T80.vhd:1014:43 */ + assign n1525_o = ~n1524_o; + /* T80.vhd:1015:56 */ + assign n1526_o = read_to_reg_r[0]; + /* T80.vhd:1013:25 */ + assign n1528_o = read_to_reg_r == 5'b10000; + /* T80.vhd:1013:38 */ + assign n1530_o = read_to_reg_r == 5'b10001; + /* T80.vhd:1013:38 */ + assign n1531_o = n1528_o | n1530_o; + /* T80.vhd:1013:48 */ + assign n1533_o = read_to_reg_r == 5'b10010; + /* T80.vhd:1013:48 */ + assign n1534_o = n1531_o | n1533_o; + /* T80.vhd:1013:58 */ + assign n1536_o = read_to_reg_r == 5'b10011; + /* T80.vhd:1013:58 */ + assign n1537_o = n1534_o | n1536_o; + /* T80.vhd:1013:68 */ + assign n1539_o = read_to_reg_r == 5'b10100; + /* T80.vhd:1013:68 */ + assign n1540_o = n1537_o | n1539_o; + /* T80.vhd:1013:78 */ + assign n1542_o = read_to_reg_r == 5'b10101; + /* T80.vhd:1013:78 */ + assign n1543_o = n1540_o | n1542_o; + /* T80.vhd:1012:25 */ + always @* + case (n1543_o) + 1'b1: n1545_o = n1525_o; + default: n1545_o = 1'b0; + endcase + /* T80.vhd:1012:25 */ + always @* + case (n1543_o) + 1'b1: n1547_o = n1526_o; + default: n1547_o = 1'b0; + endcase + /* T80.vhd:1010:17 */ + assign n1549_o = n1523_o ? n1545_o : 1'b0; + /* T80.vhd:1010:17 */ + assign n1552_o = n1523_o ? n1547_o : 1'b0; + /* T80.vhd:1020:49 */ + assign n1555_o = tstate == 3'b011; + /* T80.vhd:1020:63 */ + assign n1557_o = tstate == 3'b100; + /* T80.vhd:1020:53 */ + assign n1558_o = n1555_o | n1557_o; + /* T80.vhd:1020:37 */ + assign n1559_o = n1558_o & exchangedh; + /* T80.vhd:1020:17 */ + assign n1561_o = n1559_o ? 1'b1 : n1549_o; + /* T80.vhd:1020:17 */ + assign n1563_o = n1559_o ? 1'b1 : n1552_o; + /* T80.vhd:1025:29 */ + assign n1564_o = incdec_16[2]; + /* T80.vhd:1025:52 */ + assign n1566_o = tstate == 3'b010; + /* T80.vhd:1025:56 */ + assign n1567_o = wait_n & n1566_o; + /* T80.vhd:1025:84 */ + assign n1569_o = mcycle != 3'b001; + /* T80.vhd:1025:73 */ + assign n1570_o = n1569_o & n1567_o; + /* T80.vhd:1025:105 */ + assign n1572_o = tstate == 3'b011; + /* T80.vhd:1025:120 */ + assign n1574_o = mcycle == 3'b001; + /* T80.vhd:1025:109 */ + assign n1575_o = n1574_o & n1572_o; + /* T80.vhd:1025:94 */ + assign n1576_o = n1570_o | n1575_o; + /* T80.vhd:1025:39 */ + assign n1577_o = n1576_o & n1564_o; + /* T80.vhd:1026:39 */ + assign n1578_o = incdec_16[1:0]; + /* T80.vhd:1027:25 */ + assign n1580_o = n1578_o == 2'b00; + /* T80.vhd:1027:35 */ + assign n1582_o = n1578_o == 2'b01; + /* T80.vhd:1027:35 */ + assign n1583_o = n1580_o | n1582_o; + /* T80.vhd:1027:42 */ + assign n1585_o = n1578_o == 2'b10; + /* T80.vhd:1027:42 */ + assign n1586_o = n1583_o | n1585_o; + /* T80.vhd:1026:25 */ + always @* + case (n1586_o) + 1'b1: n1588_o = 1'b1; + default: n1588_o = n1561_o; + endcase + /* T80.vhd:1026:25 */ + always @* + case (n1586_o) + 1'b1: n1590_o = 1'b1; + default: n1590_o = n1563_o; + endcase + /* T80.vhd:1025:17 */ + assign n1591_o = n1577_o ? n1588_o : n1561_o; + /* T80.vhd:1025:17 */ + assign n1592_o = n1577_o ? n1590_o : n1563_o; + /* T80.vhd:1041:48 */ + assign n1597_o = tstate == 3'b011; + /* T80.vhd:1041:37 */ + assign n1598_o = n1597_o & exchangedh; + /* T80.vhd:1042:42 */ + assign n1599_o = regbusb[15:8]; + /* T80.vhd:1043:42 */ + assign n1600_o = regbusb[7:0]; + /* T80.vhd:1041:17 */ + assign n1601_o = n1598_o ? n1599_o : save_mux; + /* T80.vhd:1041:17 */ + assign n1602_o = n1598_o ? n1600_o : save_mux; + /* T80.vhd:1045:48 */ + assign n1604_o = tstate == 3'b100; + /* T80.vhd:1045:37 */ + assign n1605_o = n1604_o & exchangedh; + /* T80.vhd:1046:44 */ + assign n1606_o = regbusa_r[15:8]; + /* T80.vhd:1047:44 */ + assign n1607_o = regbusa_r[7:0]; + /* T80.vhd:1045:17 */ + assign n1608_o = n1605_o ? n1606_o : n1601_o; + /* T80.vhd:1045:17 */ + assign n1609_o = n1605_o ? n1607_o : n1602_o; + /* T80.vhd:1050:29 */ + assign n1610_o = incdec_16[2]; + /* T80.vhd:1050:52 */ + assign n1612_o = tstate == 3'b010; + /* T80.vhd:1050:67 */ + assign n1614_o = mcycle != 3'b001; + /* T80.vhd:1050:56 */ + assign n1615_o = n1614_o & n1612_o; + /* T80.vhd:1050:88 */ + assign n1617_o = tstate == 3'b011; + /* T80.vhd:1050:103 */ + assign n1619_o = mcycle == 3'b001; + /* T80.vhd:1050:92 */ + assign n1620_o = n1619_o & n1617_o; + /* T80.vhd:1050:77 */ + assign n1621_o = n1615_o | n1620_o; + /* T80.vhd:1050:39 */ + assign n1622_o = n1621_o & n1610_o; + /* T80.vhd:1051:56 */ + assign n1623_o = id16[15:8]; + /* T80.vhd:1052:56 */ + assign n1624_o = id16[7:0]; + /* T80.vhd:1050:17 */ + assign n1625_o = n1622_o ? n1623_o : n1608_o; + /* T80.vhd:1050:17 */ + assign n1626_o = n1622_o ? n1624_o : n1609_o; + /* T80.vhd:1067:33 */ + assign u_regs_n1628 = u_regs_doah; // (signal) + /* T80.vhd:1068:33 */ + assign u_regs_n1629 = u_regs_doal; // (signal) + /* T80.vhd:1069:33 */ + assign u_regs_n1630 = u_regs_dobh; // (signal) + /* T80.vhd:1070:33 */ + assign u_regs_n1631 = u_regs_dobl; // (signal) + /* T80.vhd:1071:33 */ + assign u_regs_n1632 = u_regs_doch; // (signal) + /* T80.vhd:1072:33 */ + assign u_regs_n1633 = u_regs_docl; // (signal) + /* T80.vhd:1073:33 */ + assign u_regs_n1634 = u_regs_dor; // (signal) + /* T80.vhd:1075:36 */ + assign n1635_o = dir[207:80]; + /* T80.vhd:1056:9 */ + t80_reg u_regs ( + .clk(clk_n), + .cen(clken), + .weh(regweh), + .wel(regwel), + .addra(regaddra), + .addrb(regaddrb), + .addrc(regaddrc), + .dih(regdih), + .dil(regdil), + .dirset(dirset), + .dir(n1635_o), + .doah(u_regs_doah), + .doal(u_regs_doal), + .dobh(u_regs_dobh), + .dobl(u_regs_dobl), + .doch(u_regs_doch), + .docl(u_regs_docl), + .dor(u_regs_dor)); + /* T80.vhd:1087:33 */ + assign n1654_o = set_busb_to == 4'b0111; + /* T80.vhd:1090:55 */ + assign n1655_o = set_busb_to[0]; + /* T80.vhd:1091:64 */ + assign n1656_o = regbusb[7:0]; + /* T80.vhd:1093:64 */ + assign n1657_o = regbusb[15:8]; + /* T80.vhd:1090:41 */ + assign n1658_o = n1655_o ? n1656_o : n1657_o; + /* T80.vhd:1089:33 */ + assign n1660_o = set_busb_to == 4'b0000; + /* T80.vhd:1089:45 */ + assign n1662_o = set_busb_to == 4'b0001; + /* T80.vhd:1089:45 */ + assign n1663_o = n1660_o | n1662_o; + /* T80.vhd:1089:54 */ + assign n1665_o = set_busb_to == 4'b0010; + /* T80.vhd:1089:54 */ + assign n1666_o = n1663_o | n1665_o; + /* T80.vhd:1089:63 */ + assign n1668_o = set_busb_to == 4'b0011; + /* T80.vhd:1089:63 */ + assign n1669_o = n1666_o | n1668_o; + /* T80.vhd:1089:72 */ + assign n1671_o = set_busb_to == 4'b0100; + /* T80.vhd:1089:72 */ + assign n1672_o = n1669_o | n1671_o; + /* T80.vhd:1089:81 */ + assign n1674_o = set_busb_to == 4'b0101; + /* T80.vhd:1089:81 */ + assign n1675_o = n1672_o | n1674_o; + /* T80.vhd:1095:33 */ + assign n1677_o = set_busb_to == 4'b0110; + /* T80.vhd:1098:68 */ + assign n1678_o = sp[7:0]; + /* T80.vhd:1097:33 */ + assign n1680_o = set_busb_to == 4'b1000; + /* T80.vhd:1100:68 */ + assign n1681_o = sp[15:8]; + /* T80.vhd:1099:33 */ + assign n1683_o = set_busb_to == 4'b1001; + /* T80.vhd:1101:33 */ + assign n1685_o = set_busb_to == 4'b1010; + /* T80.vhd:1103:33 */ + assign n1687_o = set_busb_to == 4'b1011; + /* T80.vhd:1106:68 */ + assign n1688_o = pc[7:0]; + /* T80.vhd:1105:33 */ + assign n1690_o = set_busb_to == 4'b1100; + /* T80.vhd:1108:68 */ + assign n1691_o = pc[15:8]; + /* T80.vhd:1107:33 */ + assign n1693_o = set_busb_to == 4'b1101; + /* T80.vhd:1110:47 */ + assign n1695_o = ir == 8'b01110001; + /* T80.vhd:1110:55 */ + assign n1696_o = out0 & n1695_o; + /* T80.vhd:1110:41 */ + assign n1699_o = n1696_o ? 8'b11111111 : 8'b00000000; + /* T80.vhd:1109:33 */ + assign n1701_o = set_busb_to == 4'b1110; + assign n1702_o = {n1701_o, n1693_o, n1690_o, n1687_o, n1685_o, n1683_o, n1680_o, n1677_o, n1675_o, n1654_o}; + /* T80.vhd:1086:33 */ + always @* + case (n1702_o) + 10'b1000000000: n1705_o = n1699_o; + 10'b0100000000: n1705_o = n1691_o; + 10'b0010000000: n1705_o = n1688_o; + 10'b0001000000: n1705_o = f; + 10'b0000100000: n1705_o = 8'b00000001; + 10'b0000010000: n1705_o = n1681_o; + 10'b0000001000: n1705_o = n1678_o; + 10'b0000000100: n1705_o = di_reg; + 10'b0000000010: n1705_o = n1658_o; + 10'b0000000001: n1705_o = acc; + default: n1705_o = 8'bX; + endcase + /* T80.vhd:1120:33 */ + assign n1707_o = set_busa_to == 4'b0111; + /* T80.vhd:1123:55 */ + assign n1708_o = set_busa_to[0]; + /* T80.vhd:1124:64 */ + assign n1709_o = regbusa[7:0]; + /* T80.vhd:1126:64 */ + assign n1710_o = regbusa[15:8]; + /* T80.vhd:1123:41 */ + assign n1711_o = n1708_o ? n1709_o : n1710_o; + /* T80.vhd:1122:33 */ + assign n1713_o = set_busa_to == 4'b0000; + /* T80.vhd:1122:45 */ + assign n1715_o = set_busa_to == 4'b0001; + /* T80.vhd:1122:45 */ + assign n1716_o = n1713_o | n1715_o; + /* T80.vhd:1122:54 */ + assign n1718_o = set_busa_to == 4'b0010; + /* T80.vhd:1122:54 */ + assign n1719_o = n1716_o | n1718_o; + /* T80.vhd:1122:63 */ + assign n1721_o = set_busa_to == 4'b0011; + /* T80.vhd:1122:63 */ + assign n1722_o = n1719_o | n1721_o; + /* T80.vhd:1122:72 */ + assign n1724_o = set_busa_to == 4'b0100; + /* T80.vhd:1122:72 */ + assign n1725_o = n1722_o | n1724_o; + /* T80.vhd:1122:81 */ + assign n1727_o = set_busa_to == 4'b0101; + /* T80.vhd:1122:81 */ + assign n1728_o = n1725_o | n1727_o; + /* T80.vhd:1128:33 */ + assign n1730_o = set_busa_to == 4'b0110; + /* T80.vhd:1131:68 */ + assign n1731_o = sp[7:0]; + /* T80.vhd:1130:33 */ + assign n1733_o = set_busa_to == 4'b1000; + /* T80.vhd:1133:68 */ + assign n1734_o = sp[15:8]; + /* T80.vhd:1132:33 */ + assign n1736_o = set_busa_to == 4'b1001; + /* T80.vhd:1134:33 */ + assign n1738_o = set_busa_to == 4'b1010; + assign n1739_o = {n1738_o, n1736_o, n1733_o, n1730_o, n1728_o, n1707_o}; + /* T80.vhd:1119:33 */ + always @* + case (n1739_o) + 6'b100000: n1742_o = 8'b00000000; + 6'b010000: n1742_o = n1734_o; + 6'b001000: n1742_o = n1731_o; + 6'b000100: n1742_o = di_reg; + 6'b000010: n1742_o = n1711_o; + 6'b000001: n1742_o = acc; + default: n1742_o = 8'bX; + endcase + /* T80.vhd:1139:33 */ + assign n1743_o = xybit_undoc ? di_reg : n1705_o; + /* T80.vhd:1139:33 */ + assign n1744_o = xybit_undoc ? di_reg : n1742_o; + /* T80.vhd:1154:28 */ + assign n1752_o = ~reset_n; + /* T80.vhd:1157:35 */ + assign n1754_o = ~dirset; + /* T80.vhd:1157:41 */ + assign n1755_o = cen & n1754_o; + /* T80.vhd:1158:43 */ + assign n1757_o = mcycle == 3'b001; + /* T80.vhd:1158:64 */ + assign n1759_o = tstate == 3'b010; + /* T80.vhd:1158:69 */ + assign n1760_o = wait_n & n1759_o; + /* T80.vhd:1158:97 */ + assign n1762_o = tstate == 3'b011; + /* T80.vhd:1158:87 */ + assign n1763_o = n1760_o | n1762_o; + /* T80.vhd:1158:51 */ + assign n1764_o = n1763_o & n1757_o; + /* T80.vhd:1158:33 */ + assign n1767_o = n1764_o ? 1'b0 : 1'b1; + /* T80.vhd:1170:19 */ + assign n1773_o = ~halt_ff; + /* T80.vhd:1171:20 */ + assign n1774_o = ~busack; + /* T80.vhd:1172:23 */ + assign n1775_o = ~intcycle; + /* T80.vhd:1183:26 */ + always @* + n1776_oldnmi_n = n2072_q; // (isignal) + initial + n1776_oldnmi_n = 1'bX; + /* T80.vhd:1185:28 */ + assign n1779_o = ~reset_n; + /* T80.vhd:1204:48 */ + assign n1781_o = dir[211]; + /* T80.vhd:1205:48 */ + assign n1782_o = dir[210]; + /* T80.vhd:1207:42 */ + assign n1783_o = ~nmi_n; + /* T80.vhd:1207:48 */ + assign n1784_o = n1776_oldnmi_n & n1783_o; + /* T80.vhd:1207:33 */ + assign n1786_o = n1784_o ? 1'b1 : nmi_s; + /* T80.vhd:1213:53 */ + assign n1787_o = ~busrq_n; + /* T80.vhd:1219:75 */ + assign n1788_o = auto_wait | iorq_i; + /* T80.vhd:1215:41 */ + assign n1790_o = t_res ? 1'b0 : n1788_o; + /* T80.vhd:1215:41 */ + assign n1792_o = t_res ? 1'b0 : auto_wait_t1; + /* T80.vhd:1221:68 */ + assign n1793_o = ir[4]; + /* T80.vhd:1221:62 */ + assign n1794_o = ~n1793_o; + /* T80.vhd:1221:80 */ + assign n1795_o = f[2]; + /* T80.vhd:1221:75 */ + assign n1796_o = ~n1795_o; + /* T80.vhd:1221:72 */ + assign n1797_o = n1794_o | n1796_o; + /* T80.vhd:1221:57 */ + assign n1798_o = i_bt & n1797_o; + /* T80.vhd:1222:74 */ + assign n1799_o = ir[4]; + /* T80.vhd:1222:68 */ + assign n1800_o = ~n1799_o; + /* T80.vhd:1222:82 */ + assign n1801_o = f[6]; + /* T80.vhd:1222:78 */ + assign n1802_o = n1800_o | n1801_o; + /* T80.vhd:1222:99 */ + assign n1803_o = f[2]; + /* T80.vhd:1222:94 */ + assign n1804_o = ~n1803_o; + /* T80.vhd:1222:91 */ + assign n1805_o = n1802_o | n1804_o; + /* T80.vhd:1222:63 */ + assign n1806_o = i_bc & n1805_o; + /* T80.vhd:1221:91 */ + assign n1807_o = n1798_o | n1806_o; + /* T80.vhd:1223:75 */ + assign n1808_o = ir[4]; + /* T80.vhd:1223:69 */ + assign n1809_o = ~n1808_o; + /* T80.vhd:1223:83 */ + assign n1810_o = f[6]; + /* T80.vhd:1223:79 */ + assign n1811_o = n1809_o | n1810_o; + /* T80.vhd:1223:64 */ + assign n1812_o = i_btr & n1811_o; + /* T80.vhd:1222:110 */ + assign n1813_o = n1807_o | n1812_o; + /* T80.vhd:1224:51 */ + assign n1815_o = tstate == 3'b010; + /* T80.vhd:1225:49 */ + assign n1817_o = setei ? 1'b1 : inte_ff1; + /* T80.vhd:1224:41 */ + assign n1819_o = n1822_o ? 1'b1 : inte_ff2; + /* T80.vhd:1229:49 */ + assign n1820_o = i_retn ? inte_ff2 : n1817_o; + /* T80.vhd:1224:41 */ + assign n1821_o = n1815_o ? n1820_o : inte_ff1; + /* T80.vhd:1224:41 */ + assign n1822_o = n1815_o & setei; + /* T80.vhd:1233:51 */ + assign n1824_o = tstate == 3'b011; + /* T80.vhd:1233:41 */ + assign n1826_o = n1829_o ? 1'b0 : n1821_o; + /* T80.vhd:1233:41 */ + assign n1828_o = n1830_o ? 1'b0 : n1819_o; + /* T80.vhd:1233:41 */ + assign n1829_o = n1824_o & setdi; + /* T80.vhd:1233:41 */ + assign n1830_o = n1824_o & setdi; + /* T80.vhd:1239:59 */ + assign n1831_o = intcycle | nmicycle; + /* T80.vhd:1239:41 */ + assign n1833_o = n1831_o ? 1'b0 : halt_ff; + /* T80.vhd:1242:51 */ + assign n1835_o = mcycle == 3'b001; + /* T80.vhd:1242:70 */ + assign n1837_o = tstate == 3'b010; + /* T80.vhd:1242:59 */ + assign n1838_o = n1837_o & n1835_o; + /* T80.vhd:1242:74 */ + assign n1839_o = wait_n & n1838_o; + /* T80.vhd:1242:41 */ + assign n1841_o = n1839_o ? 1'b1 : n2134_q; + /* T80.vhd:1245:65 */ + assign n1842_o = busack & busreq_s; + /* T80.vhd:1245:44 */ + assign n1843_o = ~n1842_o; + /* T80.vhd:1247:59 */ + assign n1845_o = tstate == 3'b010; + /* T80.vhd:1247:74 */ + assign n1846_o = ~wait_n; + /* T80.vhd:1247:63 */ + assign n1847_o = n1846_o & n1845_o; + /* T80.vhd:1248:49 */ + assign n1849_o = n1956_o ? 1'b1 : n1833_o; + /* T80.vhd:1259:79 */ + assign n1851_o = ir == 8'b00110110; + /* T80.vhd:1259:92 */ + assign n1853_o = 1'b1 & n1851_o; + /* T80.vhd:1259:73 */ + assign n1855_o = n1853_o ? 3'b010 : mcycle; + /* T80.vhd:1262:79 */ + assign n1857_o = mcycle == 3'b111; + /* T80.vhd:1262:88 */ + assign n1861_o = n1857_o | 1'b0; + /* T80.vhd:1263:121 */ + assign n1863_o = pre_xy_f_m + 3'b001; + /* T80.vhd:1264:79 */ + assign n1864_o = mcycle == mcycles; + /* T80.vhd:1264:90 */ + assign n1865_o = n1864_o | no_btr; + /* T80.vhd:1264:117 */ + assign n1867_o = mcycle == 3'b010; + /* T80.vhd:1264:125 */ + assign n1868_o = i_djnz & n1867_o; + /* T80.vhd:1264:142 */ + assign n1869_o = incdecz & n1868_o; + /* T80.vhd:1264:106 */ + assign n1870_o = n1865_o | n1869_o; + /* T80.vhd:1269:99 */ + assign n1872_o = prefix == 2'b00; + /* T80.vhd:1269:88 */ + assign n1873_o = n1872_o & nmi_s; + /* T80.vhd:1273:103 */ + assign n1874_o = ~int_n; + /* T80.vhd:1273:94 */ + assign n1875_o = n1874_o & inte_ff1; + /* T80.vhd:1273:119 */ + assign n1877_o = prefix == 2'b00; + /* T80.vhd:1273:108 */ + assign n1878_o = n1877_o & n1875_o; + /* T80.vhd:1273:136 */ + assign n1879_o = ~setei; + /* T80.vhd:1273:126 */ + assign n1880_o = n1879_o & n1878_o; + /* T80.vhd:1273:73 */ + assign n1882_o = n1880_o ? 1'b0 : n1826_o; + /* T80.vhd:1273:73 */ + assign n1884_o = n1880_o ? 1'b0 : n1828_o; + /* T80.vhd:1273:73 */ + assign n1887_o = n1880_o ? 1'b1 : 1'b0; + /* T80.vhd:1269:73 */ + assign n1889_o = n1873_o ? 1'b0 : n1882_o; + /* T80.vhd:1269:73 */ + assign n1890_o = n1873_o ? n1828_o : n1884_o; + /* T80.vhd:1264:65 */ + assign n1892_o = n1908_o ? 1'b0 : n1786_o; + /* T80.vhd:1269:73 */ + assign n1894_o = n1873_o ? 1'b0 : n1887_o; + /* T80.vhd:1269:73 */ + assign n1898_o = n1873_o ? 1'b1 : 1'b0; + /* T80.vhd:1279:117 */ + assign n1901_o = mcycle + 3'b001; + /* T80.vhd:1264:65 */ + assign n1903_o = n1870_o ? 1'b0 : n1841_o; + /* T80.vhd:1264:65 */ + assign n1905_o = n1870_o ? 3'b001 : n1901_o; + /* T80.vhd:1264:65 */ + assign n1906_o = n1870_o ? n1889_o : n1826_o; + /* T80.vhd:1264:65 */ + assign n1907_o = n1870_o ? n1890_o : n1828_o; + /* T80.vhd:1264:65 */ + assign n1908_o = n1870_o & n1873_o; + /* T80.vhd:1264:65 */ + assign n1909_o = n1870_o ? n1894_o : intcycle; + /* T80.vhd:1264:65 */ + assign n1910_o = n1870_o ? n1898_o : nmicycle; + /* T80.vhd:1262:65 */ + assign n1911_o = n1861_o ? n1841_o : n1903_o; + /* T80.vhd:1262:65 */ + assign n1912_o = n1861_o ? n1863_o : n1905_o; + /* T80.vhd:1262:65 */ + assign n1913_o = n1861_o ? n1826_o : n1906_o; + /* T80.vhd:1262:65 */ + assign n1914_o = n1861_o ? n1828_o : n1907_o; + /* T80.vhd:1262:65 */ + assign n1915_o = n1861_o ? n1786_o : n1892_o; + /* T80.vhd:1262:65 */ + assign n1916_o = n1861_o ? intcycle : n1909_o; + /* T80.vhd:1262:65 */ + assign n1917_o = n1861_o ? nmicycle : n1910_o; + /* T80.vhd:1256:65 */ + assign n1918_o = nextis_xy_fetch ? n1841_o : n1911_o; + /* T80.vhd:1256:65 */ + assign n1920_o = nextis_xy_fetch ? 3'b110 : n1912_o; + /* T80.vhd:1256:65 */ + assign n1921_o = nextis_xy_fetch ? n1826_o : n1913_o; + /* T80.vhd:1256:65 */ + assign n1922_o = nextis_xy_fetch ? n1828_o : n1914_o; + /* T80.vhd:1256:65 */ + assign n1923_o = nextis_xy_fetch ? n1786_o : n1915_o; + /* T80.vhd:1256:65 */ + assign n1924_o = nextis_xy_fetch ? n1855_o : pre_xy_f_m; + /* T80.vhd:1256:65 */ + assign n1925_o = nextis_xy_fetch ? intcycle : n1916_o; + /* T80.vhd:1256:65 */ + assign n1926_o = nextis_xy_fetch ? nmicycle : n1917_o; + /* T80.vhd:1252:57 */ + assign n1927_o = busreq_s ? n1841_o : n1918_o; + /* T80.vhd:1252:57 */ + assign n1929_o = busreq_s ? tstate : 3'b001; + /* T80.vhd:1252:57 */ + assign n1930_o = busreq_s ? mcycle : n1920_o; + /* T80.vhd:1252:57 */ + assign n1931_o = busreq_s ? n1826_o : n1921_o; + /* T80.vhd:1252:57 */ + assign n1932_o = busreq_s ? n1828_o : n1922_o; + /* T80.vhd:1252:57 */ + assign n1935_o = busreq_s ? 1'b1 : 1'b0; + /* T80.vhd:1252:57 */ + assign n1936_o = busreq_s ? n1786_o : n1923_o; + /* T80.vhd:1252:57 */ + assign n1937_o = busreq_s ? pre_xy_f_m : n1924_o; + /* T80.vhd:1252:57 */ + assign n1938_o = busreq_s ? intcycle : n1925_o; + /* T80.vhd:1252:57 */ + assign n1939_o = busreq_s ? nmicycle : n1926_o; + /* T80.vhd:1283:94 */ + assign n1940_o = ~auto_wait_t2; + /* T80.vhd:1283:77 */ + assign n1941_o = n1940_o & auto_wait; + /* T80.vhd:1284:77 */ + assign n1943_o = iorq_i & 1'b1; + /* T80.vhd:1284:111 */ + assign n1944_o = ~auto_wait_t1; + /* T80.vhd:1284:94 */ + assign n1945_o = n1944_o & n1943_o; + /* T80.vhd:1283:101 */ + assign n1946_o = n1941_o | n1945_o; + /* T80.vhd:1283:101 */ + assign n1947_o = ~n1946_o; + /* T80.vhd:1285:82 */ + assign n1949_o = tstate + 3'b001; + /* T80.vhd:1283:57 */ + assign n1950_o = n1947_o ? n1949_o : tstate; + /* T80.vhd:1248:49 */ + assign n1951_o = t_res ? n1927_o : n1841_o; + /* T80.vhd:1248:49 */ + assign n1952_o = t_res ? n1929_o : n1950_o; + /* T80.vhd:1248:49 */ + assign n1953_o = t_res ? n1930_o : mcycle; + /* T80.vhd:1248:49 */ + assign n1954_o = t_res ? n1931_o : n1826_o; + /* T80.vhd:1248:49 */ + assign n1955_o = t_res ? n1932_o : n1828_o; + /* T80.vhd:1248:49 */ + assign n1956_o = t_res & halt; + /* T80.vhd:1248:49 */ + assign n1958_o = t_res ? n1935_o : 1'b0; + /* T80.vhd:1248:49 */ + assign n1959_o = t_res ? n1936_o : n1786_o; + /* T80.vhd:1248:49 */ + assign n1960_o = t_res ? n1937_o : pre_xy_f_m; + /* T80.vhd:1248:49 */ + assign n1961_o = t_res ? n1938_o : intcycle; + /* T80.vhd:1248:49 */ + assign n1962_o = t_res ? n1939_o : nmicycle; + /* T80.vhd:1247:49 */ + assign n1963_o = n1847_o ? n1841_o : n1951_o; + /* T80.vhd:1247:49 */ + assign n1964_o = n1847_o ? tstate : n1952_o; + /* T80.vhd:1247:49 */ + assign n1965_o = n1847_o ? mcycle : n1953_o; + /* T80.vhd:1247:49 */ + assign n1966_o = n1847_o ? n1826_o : n1954_o; + /* T80.vhd:1247:49 */ + assign n1967_o = n1847_o ? n1828_o : n1955_o; + /* T80.vhd:1247:49 */ + assign n1968_o = n1847_o ? n1833_o : n1849_o; + /* T80.vhd:1247:49 */ + assign n1970_o = n1847_o ? 1'b0 : n1958_o; + /* T80.vhd:1247:49 */ + assign n1972_o = n1847_o ? n1786_o : n1959_o; + /* T80.vhd:1247:49 */ + assign n1973_o = n1847_o ? pre_xy_f_m : n1960_o; + /* T80.vhd:1247:49 */ + assign n1974_o = n1847_o ? intcycle : n1961_o; + /* T80.vhd:1247:49 */ + assign n1975_o = n1847_o ? nmicycle : n1962_o; + /* T80.vhd:1245:41 */ + assign n1976_o = n1843_o ? n1963_o : n1841_o; + /* T80.vhd:1212:33 */ + assign n1977_o = n1992_o ? n1964_o : tstate; + /* T80.vhd:1212:33 */ + assign n1978_o = n1993_o ? n1965_o : mcycle; + /* T80.vhd:1245:41 */ + assign n1979_o = n1843_o ? n1966_o : n1826_o; + /* T80.vhd:1245:41 */ + assign n1980_o = n1843_o ? n1967_o : n1828_o; + /* T80.vhd:1245:41 */ + assign n1981_o = n1843_o ? n1968_o : n1833_o; + /* T80.vhd:1212:33 */ + assign n1982_o = n1998_o ? n1970_o : busack; + /* T80.vhd:1212:33 */ + assign n1983_o = n1999_o ? n1972_o : n1786_o; + /* T80.vhd:1212:33 */ + assign n1984_o = n2000_o ? n1973_o : pre_xy_f_m; + /* T80.vhd:1212:33 */ + assign n1985_o = n2004_o ? n1974_o : intcycle; + /* T80.vhd:1212:33 */ + assign n1986_o = n2005_o ? n1975_o : nmicycle; + /* T80.vhd:1289:51 */ + assign n1988_o = tstate == 3'b000; + /* T80.vhd:1289:41 */ + assign n1990_o = n1988_o ? 1'b0 : n1976_o; + /* T80.vhd:1212:33 */ + assign n1991_o = cen ? n1990_o : n2134_q; + /* T80.vhd:1212:33 */ + assign n1992_o = cen & n1843_o; + /* T80.vhd:1212:33 */ + assign n1993_o = cen & n1843_o; + /* T80.vhd:1212:33 */ + assign n1994_o = cen ? n1979_o : inte_ff1; + /* T80.vhd:1212:33 */ + assign n1995_o = cen ? n1980_o : inte_ff2; + /* T80.vhd:1212:33 */ + assign n1996_o = cen ? n1981_o : halt_ff; + /* T80.vhd:1212:33 */ + assign n1997_o = cen ? n1787_o : busreq_s; + /* T80.vhd:1212:33 */ + assign n1998_o = cen & n1843_o; + /* T80.vhd:1212:33 */ + assign n1999_o = cen & n1843_o; + /* T80.vhd:1212:33 */ + assign n2000_o = cen & n1843_o; + /* T80.vhd:1212:33 */ + assign n2001_o = cen ? n1813_o : no_btr; + /* T80.vhd:1212:33 */ + assign n2002_o = cen ? n1790_o : auto_wait_t1; + /* T80.vhd:1212:33 */ + assign n2003_o = cen ? n1792_o : auto_wait_t2; + /* T80.vhd:1212:33 */ + assign n2004_o = cen & n1843_o; + /* T80.vhd:1212:33 */ + assign n2005_o = cen & n1843_o; + /* T80.vhd:1203:25 */ + assign n2006_o = dirset ? n2134_q : n1991_o; + /* T80.vhd:1203:25 */ + assign n2007_o = dirset ? tstate : n1977_o; + /* T80.vhd:1203:25 */ + assign n2008_o = dirset ? mcycle : n1978_o; + /* T80.vhd:1203:25 */ + assign n2009_o = dirset ? n1782_o : n1994_o; + /* T80.vhd:1203:25 */ + assign n2010_o = dirset ? n1781_o : n1995_o; + /* T80.vhd:1203:25 */ + assign n2011_o = dirset ? halt_ff : n1996_o; + /* T80.vhd:1203:25 */ + assign n2012_o = dirset ? busreq_s : n1997_o; + /* T80.vhd:1203:25 */ + assign n2013_o = dirset ? busack : n1982_o; + /* T80.vhd:1203:25 */ + assign n2014_o = dirset ? nmi_s : n1983_o; + /* T80.vhd:1203:25 */ + assign n2015_o = dirset ? pre_xy_f_m : n1984_o; + /* T80.vhd:1203:25 */ + assign n2016_o = dirset ? no_btr : n2001_o; + /* T80.vhd:1203:25 */ + assign n2017_o = dirset ? auto_wait_t1 : n2002_o; + /* T80.vhd:1203:25 */ + assign n2018_o = dirset ? auto_wait_t2 : n2003_o; + /* T80.vhd:1203:25 */ + assign n2019_o = dirset ? intcycle : n1985_o; + /* T80.vhd:1203:25 */ + assign n2020_o = dirset ? nmicycle : n1986_o; + /* T80.vhd:1203:25 */ + assign n2021_o = dirset ? n1776_oldnmi_n : nmi_n; + /* T80.vhd:1182:9 */ + assign n2070_o = ~n1779_o; + /* T80.vhd:1201:17 */ + assign n2071_o = n2070_o ? n2021_o : n1776_oldnmi_n; + /* T80.vhd:1201:17 */ + always @(posedge clk_n) + n2072_q <= n2071_o; + /* T80.vhd:1297:57 */ + assign n2075_o = mcycle == 3'b001; + /* T80.vhd:1297:46 */ + assign n2076_o = n2075_o & intcycle; + /* T80.vhd:1297:26 */ + assign n2077_o = n2076_o ? 1'b1 : 1'b0; + /* T80.vhd:529:17 */ + always @(posedge clk_n or posedge n388_o) + if (n388_o) + n2079_q <= 8'b11111111; + else + n2079_q <= n1257_o; + /* T80.vhd:529:17 */ + always @(posedge clk_n or posedge n388_o) + if (n388_o) + n2080_q <= 8'b11111111; + else + n2080_q <= n1258_o; + /* T80.vhd:529:17 */ + always @(posedge clk_n or posedge n388_o) + if (n388_o) + n2081_q <= 8'b11111111; + else + n2081_q <= n1259_o; + /* T80.vhd:529:17 */ + always @(posedge clk_n or posedge n388_o) + if (n388_o) + n2082_q <= 8'b11111111; + else + n2082_q <= n1260_o; + /* T80.vhd:529:17 */ + always @(posedge clk_n or posedge n388_o) + if (n388_o) + n2083_q <= 8'b00000000; + else + n2083_q <= n1261_o; + /* T80.vhd:529:17 */ + always @(posedge clk_n or posedge n388_o) + if (n388_o) + n2084_q <= 8'b00000000; + else + n2084_q <= n1262_o; + /* T80.vhd:529:17 */ + always @(posedge clk_n or posedge n388_o) + if (n388_o) + n2085_q <= 16'b1111111111111111; + else + n2085_q <= n1263_o; + /* T80.vhd:529:17 */ + always @(posedge clk_n or posedge n388_o) + if (n388_o) + n2086_q <= 16'b0000000000000000; + else + n2086_q <= n1264_o; + /* T80.vhd:499:17 */ + assign n2087_o = {u_regs_n1628, u_regs_n1629}; + /* T80.vhd:499:17 */ + assign n2088_o = {u_regs_n1630, u_regs_n1631}; + /* T80.vhd:499:17 */ + assign n2089_o = {u_regs_n1632, u_regs_n1633}; + /* T80.vhd:944:17 */ + assign n2090_o = clken ? n1388_o : regaddra_r; + /* T80.vhd:944:17 */ + always @(posedge clk_n) + n2091_q <= n2090_o; + /* T80.vhd:944:17 */ + assign n2092_o = clken ? n1402_o : regaddrb_r; + /* T80.vhd:944:17 */ + always @(posedge clk_n) + n2093_q <= n2092_o; + /* T80.vhd:944:17 */ + assign n2094_o = clken ? n1419_o : regaddrc; + /* T80.vhd:944:17 */ + always @(posedge clk_n) + n2095_q <= n2094_o; + /* T80.vhd:529:17 */ + always @(posedge clk_n or posedge n388_o) + if (n388_o) + n2096_q <= 1'b0; + else + n2096_q <= n1265_o; + /* T80.vhd:529:17 */ + always @(posedge clk_n or posedge n388_o) + if (n388_o) + n2097_q <= 16'b0000000000000000; + else + n2097_q <= n1266_o; + /* T80.vhd:529:17 */ + always @(posedge clk_n or posedge n388_o) + if (n388_o) + n2098_q <= 8'b00000000; + else + n2098_q <= n1267_o; + /* T80.vhd:529:17 */ + always @(posedge clk_n or posedge n388_o) + if (n388_o) + n2099_q <= 2'b00; + else + n2099_q <= n1268_o; + /* T80.vhd:944:17 */ + assign n2100_o = clken ? regbusa : regbusa_r; + /* T80.vhd:944:17 */ + always @(posedge clk_n) + n2101_q <= n2100_o; + /* T80.vhd:1201:17 */ + always @(posedge clk_n or posedge n1779_o) + if (n1779_o) + n2102_q <= 3'b000; + else + n2102_q <= n2007_o; + /* T80.vhd:1201:17 */ + always @(posedge clk_n or posedge n1779_o) + if (n1779_o) + n2103_q <= 3'b001; + else + n2103_q <= n2008_o; + /* T80.vhd:1201:17 */ + always @(posedge clk_n or posedge n1779_o) + if (n1779_o) + n2104_q <= 1'b0; + else + n2104_q <= n2009_o; + /* T80.vhd:1201:17 */ + always @(posedge clk_n or posedge n1779_o) + if (n1779_o) + n2105_q <= 1'b0; + else + n2105_q <= n2010_o; + /* T80.vhd:1201:17 */ + always @(posedge clk_n or posedge n1779_o) + if (n1779_o) + n2106_q <= 1'b0; + else + n2106_q <= n2011_o; + /* T80.vhd:1201:17 */ + always @(posedge clk_n or posedge n1779_o) + if (n1779_o) + n2107_q <= 1'b0; + else + n2107_q <= n2012_o; + /* T80.vhd:1201:17 */ + always @(posedge clk_n or posedge n1779_o) + if (n1779_o) + n2108_q <= 1'b0; + else + n2108_q <= n2013_o; + /* T80.vhd:1201:17 */ + always @(posedge clk_n or posedge n1779_o) + if (n1779_o) + n2109_q <= 1'b0; + else + n2109_q <= n2014_o; + /* T80.vhd:529:17 */ + always @(posedge clk_n or posedge n388_o) + if (n388_o) + n2110_q <= 2'b00; + else + n2110_q <= n1269_o; + /* T80.vhd:529:17 */ + always @(posedge clk_n or posedge n388_o) + if (n388_o) + n2111_q <= 2'b00; + else + n2111_q <= n1270_o; + /* T80.vhd:1201:17 */ + always @(posedge clk_n or posedge n1779_o) + if (n1779_o) + n2112_q <= 3'b000; + else + n2112_q <= n2015_o; + /* T80.vhd:529:17 */ + always @(posedge clk_n or posedge n388_o) + if (n388_o) + n2113_q <= 1'b0; + else + n2113_q <= n1271_o; + /* T80.vhd:1201:17 */ + always @(posedge clk_n or posedge n1779_o) + if (n1779_o) + n2114_q <= 1'b0; + else + n2114_q <= n2016_o; + /* T80.vhd:529:17 */ + always @(posedge clk_n or posedge n388_o) + if (n388_o) + n2115_q <= 1'b0; + else + n2115_q <= n1272_o; + /* T80.vhd:1201:17 */ + always @(posedge clk_n or posedge n1779_o) + if (n1779_o) + n2116_q <= 1'b0; + else + n2116_q <= n2017_o; + /* T80.vhd:1201:17 */ + always @(posedge clk_n or posedge n1779_o) + if (n1779_o) + n2117_q <= 1'b0; + else + n2117_q <= n2018_o; + /* T80.vhd:944:17 */ + assign n2118_o = clken ? n1442_o : incdecz; + /* T80.vhd:944:17 */ + always @(posedge clk_n) + n2119_q <= n2118_o; + /* T80.vhd:1084:17 */ + assign n2120_o = clken ? n1743_o : busb; + /* T80.vhd:1084:17 */ + always @(posedge clk_n) + n2121_q <= n2120_o; + /* T80.vhd:1084:17 */ + assign n2122_o = clken ? n1744_o : busa; + /* T80.vhd:1084:17 */ + always @(posedge clk_n) + n2123_q <= n2122_o; + /* T80.vhd:529:17 */ + always @(posedge clk_n or posedge n388_o) + if (n388_o) + n2124_q <= 5'b00000; + else + n2124_q <= n1273_o; + /* T80.vhd:529:17 */ + always @(posedge clk_n or posedge n388_o) + if (n388_o) + n2125_q <= 1'b0; + else + n2125_q <= n1274_o; + /* T80.vhd:529:17 */ + always @(posedge clk_n or posedge n388_o) + if (n388_o) + n2126_q <= 1'b0; + else + n2126_q <= n1275_o; + /* T80.vhd:529:17 */ + always @(posedge clk_n or posedge n388_o) + if (n388_o) + n2127_q <= 4'b0000; + else + n2127_q <= n1276_o; + /* T80.vhd:529:17 */ + always @(posedge clk_n or posedge n388_o) + if (n388_o) + n2128_q <= 1'b0; + else + n2128_q <= n1277_o; + /* T80.vhd:529:17 */ + always @(posedge clk_n or posedge n388_o) + if (n388_o) + n2129_q <= 1'b0; + else + n2129_q <= n1278_o; + /* T80.vhd:529:17 */ + always @(posedge clk_n or posedge n388_o) + if (n388_o) + n2130_q <= 3'b000; + else + n2130_q <= n1279_o; + /* T80.vhd:1201:17 */ + always @(posedge clk_n or posedge n1779_o) + if (n1779_o) + n2131_q <= 1'b0; + else + n2131_q <= n2019_o; + /* T80.vhd:1201:17 */ + always @(posedge clk_n or posedge n1779_o) + if (n1779_o) + n2132_q <= 1'b0; + else + n2132_q <= n2020_o; + /* T80.vhd:529:17 */ + always @(posedge clk_n or posedge n388_o) + if (n388_o) + n2133_q <= 1'b0; + else + n2133_q <= n1280_o; + /* T80.vhd:1201:17 */ + always @(posedge clk_n or posedge n1779_o) + if (n1779_o) + n2134_q <= 1'b1; + else + n2134_q <= n2006_o; + /* T80.vhd:1156:17 */ + assign n2135_o = n1755_o ? n1767_o : n2136_q; + /* T80.vhd:1156:17 */ + always @(posedge clk_n or posedge n1752_o) + if (n1752_o) + n2136_q <= 1'b1; + else + n2136_q <= n2135_o; + /* T80.vhd:529:17 */ + always @(posedge clk_n or posedge n388_o) + if (n388_o) + n2137_q <= 16'b0000000000000000; + else + n2137_q <= n1255_o; + /* T80.vhd:529:17 */ + always @(posedge clk_n or posedge n388_o) + if (n388_o) + n2138_q <= 8'b00000000; + else + n2138_q <= n1256_o; +endmodule + +module T80s + (input RESET_n, + input CLK, + input CEN, + input WAIT_n, + input INT_n, + input NMI_n, + input BUSRQ_n, + input OUT0, + input [7:0] DI, + output M1_n, + output MREQ_n, + output IORQ_n, + output RD_n, + output WR_n, + output RFSH_n, + output HALT_n, + output BUSAK_n, + output [15:0] A, + output [7:0] DOUT); + wire intcycle_n; + wire noread; + wire write; + wire iorq; + wire [7:0] di_reg; + wire [2:0] mcycle; + wire [2:0] tstate; + wire u0_n10; + wire u0_n11; + wire u0_n12; + wire u0_n13; + wire u0_n14; + wire u0_n15; + wire u0_n16; + wire [15:0] u0_n17; + wire [7:0] u0_n18; + wire [2:0] u0_n19; + wire [2:0] u0_n20; + wire u0_n21; + localparam n25_o = 1'b0; + localparam [211:0] n26_o = 212'b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; + wire u0_m1_n; + wire u0_iorq; + wire u0_noread; + wire u0_write; + wire u0_rfsh_n; + wire u0_halt_n; + wire u0_busak_n; + wire [15:0] u0_a; + wire [7:0] u0_dout; + wire [2:0] u0_mc; + wire [2:0] u0_ts; + wire u0_intcycle_n; + wire u0_inte; + wire u0_stop; + wire [211:0] u0_regs; + wire n56_o; + wire n59_o; + wire n61_o; + wire n63_o; + wire n64_o; + wire n65_o; + wire n66_o; + wire n67_o; + wire n68_o; + wire n70_o; + wire n72_o; + wire n74_o; + wire n76_o; + wire n78_o; + wire n80_o; + wire n82_o; + wire n83_o; + wire n84_o; + wire n85_o; + wire n86_o; + wire n87_o; + wire n88_o; + wire n89_o; + wire n90_o; + wire n92_o; + wire n94_o; + wire n97_o; + wire n99_o; + wire n101_o; + wire n102_o; + wire n103_o; + wire n104_o; + wire n105_o; + wire n106_o; + wire n107_o; + wire n108_o; + wire n111_o; + wire n112_o; + wire n114_o; + wire n116_o; + wire n119_o; + wire n122_o; + wire n123_o; + wire n129_o; + wire [7:0] n146_o; + reg [7:0] n147_q; + wire n148_o; + reg n149_q; + wire n150_o; + reg n151_q; + wire n152_o; + reg n153_q; + wire n154_o; + reg n155_q; + assign M1_n = u0_n10; + assign MREQ_n = n149_q; + assign IORQ_n = n151_q; + assign RD_n = n153_q; + assign WR_n = n155_q; + assign RFSH_n = u0_n14; + assign HALT_n = u0_n15; + assign BUSAK_n = u0_n16; + assign A = u0_n17; + assign DOUT = u0_n18; + /* T80s.vhd:148:16 */ + assign intcycle_n = u0_n21; // (signal) + /* T80s.vhd:149:16 */ + assign noread = u0_n12; // (signal) + /* T80s.vhd:150:16 */ + assign write = u0_n13; // (signal) + /* T80s.vhd:151:16 */ + assign iorq = u0_n11; // (signal) + /* T80s.vhd:152:16 */ + assign di_reg = n147_q; // (signal) + /* T80s.vhd:153:16 */ + assign mcycle = u0_n19; // (signal) + /* T80s.vhd:154:16 */ + assign tstate = u0_n20; // (signal) + /* T80s.vhd:164:25 */ + assign u0_n10 = u0_m1_n; // (signal) + /* T80s.vhd:165:25 */ + assign u0_n11 = u0_iorq; // (signal) + /* T80s.vhd:166:27 */ + assign u0_n12 = u0_noread; // (signal) + /* T80s.vhd:167:26 */ + assign u0_n13 = u0_write; // (signal) + /* T80s.vhd:168:27 */ + assign u0_n14 = u0_rfsh_n; // (signal) + /* T80s.vhd:169:27 */ + assign u0_n15 = u0_halt_n; // (signal) + /* T80s.vhd:175:28 */ + assign u0_n16 = u0_busak_n; // (signal) + /* T80s.vhd:177:22 */ + assign u0_n17 = u0_a; // (signal) + /* T80s.vhd:180:25 */ + assign u0_n18 = u0_dout; // (signal) + /* T80s.vhd:181:23 */ + assign u0_n19 = u0_mc; // (signal) + /* T80s.vhd:182:23 */ + assign u0_n20 = u0_ts; // (signal) + /* T80s.vhd:184:31 */ + assign u0_n21 = u0_intcycle_n; // (signal) + /* T80s.vhd:158:9 */ + wire [211:0] regs; + // Register assignments for debugging. Names + // match MAME's debugger names +// IFF2, IFF1, IM, IY, HL', DE', BC', IX, HL, DE, BC, PC, SP, R, I, F', A', F, A +wire [15:0] AF, BC, DE, HL, AF2, BC2, DE2, HL2,IX,IY,PC,SP; +wire [ 7:0] I,R; +assign {IY,HL2,DE2,BC2,IX,HL,DE,BC,PC,SP,R,I,AF2[7:0],AF2[15:8],AF[7:0],AF[15:8]} = regs[0+:208]; + t80_0_1_0_1_2_3_4_5_6_7 u0 ( + .reset_n(RESET_n), + .clk_n(CLK), + .cen(CEN), + .wait_n(WAIT_n), + .int_n(INT_n), + .nmi_n(NMI_n), + .busrq_n(BUSRQ_n), + .dinst(DI), + .di(di_reg), + .out0(OUT0), + .dirset(n25_o), + .dir(n26_o), + .m1_n(u0_m1_n), + .iorq(u0_iorq), + .noread(u0_noread), + .write(u0_write), + .rfsh_n(u0_rfsh_n), + .halt_n(u0_halt_n), + .busak_n(u0_busak_n), + .a(u0_a), + .dout(u0_dout), + .mc(u0_mc), + .ts(u0_ts), + .intcycle_n(u0_intcycle_n), + .inte(), + .stop(), + .regs(regs)); + /* T80s.vhd:189:28 */ + assign n56_o = ~RESET_n; + /* T80s.vhd:201:43 */ + assign n59_o = mcycle == 3'b001; + /* T80s.vhd:202:51 */ + assign n61_o = tstate == 3'b001; + /* T80s.vhd:202:66 */ + assign n63_o = tstate == 3'b010; + /* T80s.vhd:202:81 */ + assign n64_o = ~WAIT_n; + /* T80s.vhd:202:70 */ + assign n65_o = n64_o & n63_o; + /* T80s.vhd:202:55 */ + assign n66_o = n61_o | n65_o; + /* T80s.vhd:203:57 */ + assign n67_o = ~intcycle_n; + /* T80s.vhd:204:59 */ + assign n68_o = ~intcycle_n; + /* T80s.vhd:202:41 */ + assign n70_o = n66_o ? n68_o : 1'b1; + /* T80s.vhd:202:41 */ + assign n72_o = n66_o ? intcycle_n : 1'b1; + /* T80s.vhd:202:41 */ + assign n74_o = n66_o ? n67_o : 1'b1; + /* T80s.vhd:207:51 */ + assign n76_o = tstate == 3'b011; + /* T80s.vhd:207:41 */ + assign n78_o = n76_o ? 1'b0 : n70_o; + /* T80s.vhd:211:52 */ + assign n80_o = tstate == 3'b001; + /* T80s.vhd:211:67 */ + assign n82_o = tstate == 3'b010; + /* T80s.vhd:211:82 */ + assign n83_o = ~WAIT_n; + /* T80s.vhd:211:71 */ + assign n84_o = n83_o & n82_o; + /* T80s.vhd:211:56 */ + assign n85_o = n80_o | n84_o; + /* T80s.vhd:211:101 */ + assign n86_o = ~noread; + /* T80s.vhd:211:90 */ + assign n87_o = n86_o & n85_o; + /* T80s.vhd:211:117 */ + assign n88_o = ~write; + /* T80s.vhd:211:107 */ + assign n89_o = n88_o & n87_o; + /* T80s.vhd:213:59 */ + assign n90_o = ~iorq; + /* T80s.vhd:211:41 */ + assign n92_o = n89_o ? iorq : 1'b1; + /* T80s.vhd:211:41 */ + assign n94_o = n89_o ? n90_o : 1'b1; + /* T80s.vhd:211:41 */ + assign n97_o = n89_o ? 1'b0 : 1'b1; + /* T80s.vhd:223:60 */ + assign n99_o = tstate == 3'b001; + /* T80s.vhd:223:75 */ + assign n101_o = tstate == 3'b010; + /* T80s.vhd:223:90 */ + assign n102_o = ~WAIT_n; + /* T80s.vhd:223:79 */ + assign n103_o = n102_o & n101_o; + /* T80s.vhd:223:64 */ + assign n104_o = n99_o | n103_o; + /* T80s.vhd:223:98 */ + assign n105_o = write & n104_o; + /* T80s.vhd:225:67 */ + assign n106_o = ~iorq; + /* T80s.vhd:223:49 */ + assign n107_o = n105_o ? iorq : n92_o; + /* T80s.vhd:223:49 */ + assign n108_o = n105_o ? n106_o : n94_o; + /* T80s.vhd:223:49 */ + assign n111_o = n105_o ? 1'b0 : 1'b1; + /* T80s.vhd:201:33 */ + assign n112_o = n59_o ? n78_o : n107_o; + /* T80s.vhd:201:33 */ + assign n114_o = n59_o ? n72_o : n108_o; + /* T80s.vhd:201:33 */ + assign n116_o = n59_o ? n74_o : n97_o; + /* T80s.vhd:201:33 */ + assign n119_o = n59_o ? 1'b1 : n111_o; + /* T80s.vhd:230:43 */ + assign n122_o = tstate == 3'b010; + /* T80s.vhd:230:47 */ + assign n123_o = WAIT_n & n122_o; + /* T80s.vhd:196:25 */ + assign n129_o = CEN & n123_o; + /* T80s.vhd:195:17 */ + assign n146_o = n129_o ? DI : di_reg; + /* T80s.vhd:195:17 */ + always @(posedge CLK or posedge n56_o) + if (n56_o) + n147_q <= 8'b00000000; + else + n147_q <= n146_o; + /* T80s.vhd:195:17 */ + assign n148_o = CEN ? n112_o : n149_q; + /* T80s.vhd:195:17 */ + always @(posedge CLK or posedge n56_o) + if (n56_o) + n149_q <= 1'b1; + else + n149_q <= n148_o; + /* T80s.vhd:195:17 */ + assign n150_o = CEN ? n114_o : n151_q; + /* T80s.vhd:195:17 */ + always @(posedge CLK or posedge n56_o) + if (n56_o) + n151_q <= 1'b1; + else + n151_q <= n150_o; + /* T80s.vhd:195:17 */ + assign n152_o = CEN ? n116_o : n153_q; + /* T80s.vhd:195:17 */ + always @(posedge CLK or posedge n56_o) + if (n56_o) + n153_q <= 1'b1; + else + n153_q <= n152_o; + /* T80s.vhd:195:17 */ + assign n154_o = CEN ? n119_o : n155_q; + /* T80s.vhd:195:17 */ + always @(posedge CLK or posedge n56_o) + if (n56_o) + n155_q <= 1'b1; + else + n155_q <= n154_o; +endmodule + diff --git a/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/t80/T80s.vhd b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/t80/T80s.vhd new file mode 100644 index 0000000000000000000000000000000000000000..0f5a1a5491225a7687cc6ede9093c70472bd18ac --- /dev/null +++ b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/t80/T80s.vhd @@ -0,0 +1,236 @@ +-- +-- Z80 compatible microprocessor core, synchronous top level +-- Different timing than the original z80 +-- Inputs needs to be synchronous and outputs may glitch +-- +-- Version : 0242 +-- +-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.opencores.org/cvsweb.shtml/t80/ +-- +-- Limitations : +-- +-- File history : +-- +-- 0208 : First complete release +-- +-- 0210 : Fixed read with wait +-- +-- 0211 : Fixed interrupt cycle +-- +-- 0235 : Updated for T80 interface change +-- +-- 0236 : Added T2Write generic +-- +-- 0237 : Fixed T2Write with wait state +-- +-- 0238 : Updated for T80 interface change +-- +-- 0240 : Updated for T80 interface change +-- +-- 0242 : Updated for T80 interface change +-- + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; +use IEEE.STD_LOGIC_UNSIGNED.all; + +entity T80s is + generic( + Mode : integer := 0; -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB + T2Write : integer := 1; -- 0 => WR_n active in T3, /=0 => WR_n active in T2 + IOWait : integer := 1 -- 0 => Single cycle I/O, 1 => Std I/O cycle + ); + port( + RESET_n : in std_logic; + CLK : in std_logic; + CEN : in std_logic := '1'; + WAIT_n : in std_logic := '1'; + INT_n : in std_logic := '1'; + NMI_n : in std_logic := '1'; + BUSRQ_n : in std_logic := '1'; + M1_n : out std_logic; + MREQ_n : out std_logic; + IORQ_n : out std_logic; + RD_n : out std_logic; + WR_n : out std_logic; + RFSH_n : out std_logic; + HALT_n : out std_logic; + BUSAK_n : out std_logic; + OUT0 : in std_logic := '0'; -- 0 => OUT(C),0, 1 => OUT(C),255 + A : out std_logic_vector(15 downto 0); + DI : in std_logic_vector(7 downto 0); + DOUT : out std_logic_vector(7 downto 0) + ); +end T80s; + +architecture rtl of T80s is + component T80 + generic( + Mode : integer := 0; -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB + IOWait : integer := 0; -- 0 => Single cycle I/O, 1 => Std I/O cycle + Flag_C : integer := 0; + Flag_N : integer := 1; + Flag_P : integer := 2; + Flag_X : integer := 3; + Flag_H : integer := 4; + Flag_Y : integer := 5; + Flag_Z : integer := 6; + Flag_S : integer := 7 + ); + port( + RESET_n : in std_logic; + CLK_n : in std_logic; + CEN : in std_logic; + WAIT_n : in std_logic; + INT_n : in std_logic; + NMI_n : in std_logic; + BUSRQ_n : in std_logic; + M1_n : out std_logic; + IORQ : out std_logic; + NoRead : out std_logic; + Write : out std_logic; + RFSH_n : out std_logic; + HALT_n : out std_logic; + BUSAK_n : out std_logic; + A : out std_logic_vector(15 downto 0); + DInst : in std_logic_vector(7 downto 0); + DI : in std_logic_vector(7 downto 0); + DOUT : out std_logic_vector(7 downto 0); + MC : out std_logic_vector(2 downto 0); + TS : out std_logic_vector(2 downto 0); + IntCycle_n : out std_logic; + IntE : out std_logic; + Stop : out std_logic; + out0 : in std_logic := '0'; -- 0 => OUT(C),0, 1 => OUT(C),255 + REGS : out std_logic_vector(211 downto 0); -- IFF2, IFF1, IM, IY, HL', DE', BC', IX, HL, DE, BC, PC, SP, R, I, F', A', F, A + + DIRSet : in std_logic := '0'; + DIR : in std_logic_vector(211 downto 0) := (others => '0') -- IFF2, IFF1, IM, IY, HL', DE', BC', IX, HL, DE, BC, PC, SP, R, I, F', A', F, A + ); + end component; + + signal IntCycle_n : std_logic; + signal NoRead : std_logic; + signal Write : std_logic; + signal IORQ : std_logic; + signal DI_Reg : std_logic_vector(7 downto 0); + signal MCycle : std_logic_vector(2 downto 0); + signal TState : std_logic_vector(2 downto 0); + +begin + + u0 : T80 + generic map( + Mode => Mode, + IOWait => IOWait) + port map( + CEN => CEN, + M1_n => M1_n, + IORQ => IORQ, + NoRead => NoRead, + Write => Write, + RFSH_n => RFSH_n, + HALT_n => HALT_n, + WAIT_n => Wait_n, + INT_n => INT_n, + NMI_n => NMI_n, + RESET_n => RESET_n, + BUSRQ_n => BUSRQ_n, + BUSAK_n => BUSAK_n, + CLK_n => CLK, + A => A, + DInst => DI, + DI => DI_Reg, + DOUT => DOUT, + MC => MCycle, + TS => TState, + OUT0 => OUT0, + IntCycle_n => IntCycle_n + ); + + process (RESET_n, CLK) + begin + if RESET_n = '0' then + RD_n <= '1'; + WR_n <= '1'; + IORQ_n <= '1'; + MREQ_n <= '1'; + DI_Reg <= "00000000"; + elsif rising_edge(CLK) then + if CEN = '1' then + RD_n <= '1'; + WR_n <= '1'; + IORQ_n <= '1'; + MREQ_n <= '1'; + if MCycle = 1 then + if TState = 1 or (TState = 2 and Wait_n = '0') then + RD_n <= not IntCycle_n; + MREQ_n <= not IntCycle_n; + IORQ_n <= IntCycle_n; + end if; + if TState = 3 then + MREQ_n <= '0'; + end if; + else + if (TState = 1 or (TState = 2 and Wait_n = '0')) and NoRead = '0' and Write = '0' then + RD_n <= '0'; + IORQ_n <= not IORQ; + MREQ_n <= IORQ; + end if; + if T2Write = 0 then + if TState = 2 and Write = '1' then + WR_n <= '0'; + IORQ_n <= not IORQ; + MREQ_n <= IORQ; + end if; + else + if (TState = 1 or (TState = 2 and Wait_n = '0')) and Write = '1' then + WR_n <= '0'; + IORQ_n <= not IORQ; + MREQ_n <= IORQ; + end if; + end if; + end if; + if TState = 2 and Wait_n = '1' then + DI_Reg <= DI; + end if; + end if; + end if; + end process; +end; diff --git a/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/t8243/t8243-c.vhd b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/t8243/t8243-c.vhd new file mode 100644 index 0000000000000000000000000000000000000000..8d010626dab211f89b6a3405f282d1756a9e13da --- /dev/null +++ b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/t8243/t8243-c.vhd @@ -0,0 +1,19 @@ +------------------------------------------------------------------------------- +-- +-- T8243 Core +-- +-- $Id: t8243-c.vhd 295 2009-04-01 19:32:48Z arniml $ +-- +------------------------------------------------------------------------------- + +configuration t8243_struct_c0 of t8243 is + + for struct + + for t8243_async_notri_b: t8243_async_notri + use configuration work.t8243_async_notri_struct_c0; + end for; + + end for; + +end t8243_struct_c0; diff --git a/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/t8243/t8243.vhd b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/t8243/t8243.vhd new file mode 100644 index 0000000000000000000000000000000000000000..8275a8310c3953a598331fb9435ae30cc87fdf76 --- /dev/null +++ b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/t8243/t8243.vhd @@ -0,0 +1,137 @@ +------------------------------------------------------------------------------- +-- +-- The T8243 asynchronous toplevel +-- +-- $Id: t8243.vhd 295 2009-04-01 19:32:48Z arniml $ +-- +-- Copyright (c) 2006, Arnim Laeuger (arniml@opencores.org) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.opencores.org/cvsweb.shtml/t48/ +-- +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; + +entity t8243 is + + port ( + -- Control Interface ------------------------------------------------------ + cs_n_i : in std_logic; + prog_n_i : in std_logic; + -- Port 2 Interface ------------------------------------------------------- + p2_b : inout std_logic_vector(3 downto 0); + -- Port 4 Interface ------------------------------------------------------- + p4_b : inout std_logic_vector(3 downto 0); + -- Port 5 Interface ------------------------------------------------------- + p5_b : inout std_logic_vector(3 downto 0); + -- Port 6 Interface ------------------------------------------------------- + p6_b : inout std_logic_vector(3 downto 0); + -- Port 7 Interface ------------------------------------------------------- + p7_b : inout std_logic_vector(3 downto 0) + ); + +end t8243; + + +use work.t8243_comp_pack.t8243_async_notri; + +architecture struct of t8243 is + + signal p2_s, + p4_s, + p5_s, + p6_s, + p7_s : std_logic_vector(3 downto 0); + signal p2_en_s, + p4_en_s, + p5_en_s, + p6_en_s, + p7_en_s : std_logic; + + signal vdd_s : std_logic; + +begin + + vdd_s <= '1'; + + + ----------------------------------------------------------------------------- + -- The asynchronous T8243 + ----------------------------------------------------------------------------- + t8243_async_notri_b : t8243_async_notri + port map ( + reset_n_i => vdd_s, -- or generate power-on reset + cs_n_i => cs_n_i, + prog_n_i => prog_n_i, + p2_i => p2_b, + p2_o => p2_s, + p2_en_o => p2_en_s, + p4_i => p4_b, + p4_o => p4_s, + p4_en_o => p4_en_s, + p5_i => p5_b, + p5_o => p5_s, + p5_en_o => p5_en_s, + p6_i => p6_b, + p6_o => p6_s, + p6_en_o => p6_en_s, + p7_i => p7_b, + p7_o => p7_s, + p7_en_o => p7_en_s + ); + + + ----------------------------------------------------------------------------- + -- Bidirectional pad structures + ----------------------------------------------------------------------------- + p2_b <= p2_s + when p2_en_s = '1' else + (others => 'Z'); + p4_b <= p4_s + when p4_en_s = '1' else + (others => 'Z'); + p5_b <= p5_s + when p5_en_s = '1' else + (others => 'Z'); + p6_b <= p6_s + when p6_en_s = '1' else + (others => 'Z'); + p7_b <= p7_s + when p7_en_s = '1' else + (others => 'Z'); + +end struct; diff --git a/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/t8243/t8243_comp_pack-p.vhd b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/t8243/t8243_comp_pack-p.vhd new file mode 100644 index 0000000000000000000000000000000000000000..a164229f953366b8f68abdb0f0f7a324c972621b --- /dev/null +++ b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/t8243/t8243_comp_pack-p.vhd @@ -0,0 +1,132 @@ +------------------------------------------------------------------------------- +-- +-- $Id: t8243_comp_pack-p.vhd 295 2009-04-01 19:32:48Z arniml $ +-- +-- Copyright (c) 2006, Arnim Laeuger (arniml@opencores.org) +-- +-- All rights reserved +-- +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; + +package t8243_comp_pack is + + component t8243_core + generic ( + clk_fall_level_g : integer := 0 + ); + port ( + -- System Interface ----------------------------------------------------- + clk_i : in std_logic; + clk_rise_en_i : in std_logic; + clk_fall_en_i : in std_logic; + reset_n_i : in std_logic; + -- Control Interface ---------------------------------------------------- + cs_n_i : in std_logic; + prog_n_i : in std_logic; + -- Port 2 Interface ----------------------------------------------------- + p2_i : in std_logic_vector(3 downto 0); + p2_o : out std_logic_vector(3 downto 0); + p2_en_o : out std_logic; + -- Port 4 Interface ----------------------------------------------------- + p4_i : in std_logic_vector(3 downto 0); + p4_o : out std_logic_vector(3 downto 0); + p4_en_o : out std_logic; + -- Port 5 Interface ----------------------------------------------------- + p5_i : in std_logic_vector(3 downto 0); + p5_o : out std_logic_vector(3 downto 0); + p5_en_o : out std_logic; + -- Port 6 Interface ----------------------------------------------------- + p6_i : in std_logic_vector(3 downto 0); + p6_o : out std_logic_vector(3 downto 0); + p6_en_o : out std_logic; + -- Port 7 Interface ----------------------------------------------------- + p7_i : in std_logic_vector(3 downto 0); + p7_o : out std_logic_vector(3 downto 0); + p7_en_o : out std_logic + ); + end component; + + component t8243_sync_notri + port ( + -- System Interface ----------------------------------------------------- + clk_i : in std_logic; + clk_en_i : in std_logic; + reset_n_i : in std_logic; + -- Control Interface ---------------------------------------------------- + cs_n_i : in std_logic; + prog_n_i : in std_logic; + -- Port 2 Interface ----------------------------------------------------- + p2_i : in std_logic_vector(3 downto 0); + p2_o : out std_logic_vector(3 downto 0); + p2_en_o : out std_logic; + -- Port 4 Interface ----------------------------------------------------- + p4_i : in std_logic_vector(3 downto 0); + p4_o : out std_logic_vector(3 downto 0); + p4_en_o : out std_logic; + -- Port 5 Interface ----------------------------------------------------- + p5_i : in std_logic_vector(3 downto 0); + p5_o : out std_logic_vector(3 downto 0); + p5_en_o : out std_logic; + -- Port 6 Interface ----------------------------------------------------- + p6_i : in std_logic_vector(3 downto 0); + p6_o : out std_logic_vector(3 downto 0); + p6_en_o : out std_logic; + -- Port 7 Interface ----------------------------------------------------- + p7_i : in std_logic_vector(3 downto 0); + p7_o : out std_logic_vector(3 downto 0); + p7_en_o : out std_logic + ); + end component; + + component t8243_async_notri + port ( + -- System Interface ----------------------------------------------------- + reset_n_i : in std_logic; + -- Control Interface ---------------------------------------------------- + cs_n_i : in std_logic; + prog_n_i : in std_logic; + -- Port 2 Interface ----------------------------------------------------- + p2_i : in std_logic_vector(3 downto 0); + p2_o : out std_logic_vector(3 downto 0); + p2_en_o : out std_logic; + -- Port 4 Interface ----------------------------------------------------- + p4_i : in std_logic_vector(3 downto 0); + p4_o : out std_logic_vector(3 downto 0); + p4_en_o : out std_logic; + -- Port 5 Interface ----------------------------------------------------- + p5_i : in std_logic_vector(3 downto 0); + p5_o : out std_logic_vector(3 downto 0); + p5_en_o : out std_logic; + -- Port 6 Interface ----------------------------------------------------- + p6_i : in std_logic_vector(3 downto 0); + p6_o : out std_logic_vector(3 downto 0); + p6_en_o : out std_logic; + -- Port 7 Interface ----------------------------------------------------- + p7_i : in std_logic_vector(3 downto 0); + p7_o : out std_logic_vector(3 downto 0); + p7_en_o : out std_logic + ); + end component; + + component t8243 + port ( + -- Control Interface ---------------------------------------------------- + cs_n_i : in std_logic; + prog_n_i : in std_logic; + -- Port 2 Interface ----------------------------------------------------- + p2_b : inout std_logic_vector(3 downto 0); + -- Port 4 Interface ----------------------------------------------------- + p4_b : inout std_logic_vector(3 downto 0); + -- Port 5 Interface ----------------------------------------------------- + p5_b : inout std_logic_vector(3 downto 0); + -- Port 6 Interface ----------------------------------------------------- + p6_b : inout std_logic_vector(3 downto 0); + -- Port 7 Interface ----------------------------------------------------- + p7_b : inout std_logic_vector(3 downto 0) + ); + end component; + +end; diff --git a/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/t8243/t8243_core-c.vhd b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/t8243/t8243_core-c.vhd new file mode 100644 index 0000000000000000000000000000000000000000..d2c6e9ceb65541c4be46464efc3d7e7bba11f06d --- /dev/null +++ b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/t8243/t8243_core-c.vhd @@ -0,0 +1,14 @@ +------------------------------------------------------------------------------- +-- +-- T8243 Core +-- +-- $Id: t8243_core-c.vhd 295 2009-04-01 19:32:48Z arniml $ +-- +------------------------------------------------------------------------------- + +configuration t8243_core_rtl_c0 of t8243_core is + + for rtl + end for; + +end t8243_core_rtl_c0; diff --git a/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/t8243/t8243_core.vhd b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/t8243/t8243_core.vhd new file mode 100644 index 0000000000000000000000000000000000000000..a9a5235f5961efd03d7c3593ffee54cce340e872 --- /dev/null +++ b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/t8243/t8243_core.vhd @@ -0,0 +1,291 @@ +------------------------------------------------------------------------------- +-- +-- The T8243 Core +-- This is the core module implementing all functionality of the +-- original 8243 chip. +-- +-- $Id: t8243_core.vhd 295 2009-04-01 19:32:48Z arniml $ +-- +-- Copyright (c) 2006, Arnim Laeuger (arniml@opencores.org) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.opencores.org/cvsweb.shtml/t48/ +-- +------------------------------------------------------------------------------- + +library ieee; +use ieee. std_logic_1164.all; + +entity t8243_core is + + generic ( + clk_fall_level_g : integer := 0 + ); + port ( + -- System Interface ------------------------------------------------------- + clk_i : in std_logic; + clk_rise_en_i : in std_logic; + clk_fall_en_i : in std_logic; + reset_n_i : in std_logic; + -- Control Interface ------------------------------------------------------ + cs_n_i : in std_logic; + prog_n_i : in std_logic; + -- Port 2 Interface ------------------------------------------------------- + p2_i : in std_logic_vector(3 downto 0); + p2_o : out std_logic_vector(3 downto 0); + p2_en_o : out std_logic; + -- Port 4 Interface ------------------------------------------------------- + p4_i : in std_logic_vector(3 downto 0); + p4_o : out std_logic_vector(3 downto 0); + p4_en_o : out std_logic; + -- Port 5 Interface ------------------------------------------------------- + p5_i : in std_logic_vector(3 downto 0); + p5_o : out std_logic_vector(3 downto 0); + p5_en_o : out std_logic; + -- Port 6 Interface ------------------------------------------------------- + p6_i : in std_logic_vector(3 downto 0); + p6_o : out std_logic_vector(3 downto 0); + p6_en_o : out std_logic; + -- Port 7 Interface ------------------------------------------------------- + p7_i : in std_logic_vector(3 downto 0); + p7_o : out std_logic_vector(3 downto 0); + p7_en_o : out std_logic + ); + +end t8243_core; + + +library ieee; +use ieee.numeric_std.all; + +architecture rtl of t8243_core is + + function int2stdlogic_f(level_i : in integer) return std_logic is + begin + if level_i = 0 then + return '0'; + else + return '1'; + end if; + end; + + constant clk_fall_level_c : std_logic := int2stdlogic_f(clk_fall_level_g); + + type instr_t is (INSTR_READ, INSTR_WRITE, INSTR_ORLD, INSTR_ANLD); + signal instr_q : instr_t; + + constant port_4_c : integer := 4; + constant port_5_c : integer := 5; + constant port_6_c : integer := 6; + constant port_7_c : integer := 7; + + subtype port_range_t is natural range port_7_c downto port_4_c; + signal px_sel_q : std_logic_vector(port_range_t); + + signal px_en_q : std_logic_vector(port_range_t); + signal p2_en_q : std_logic; + + subtype port_vector_t is std_logic_vector(3 downto 0); + type four_ports_t is array (port_range_t) of port_vector_t; + signal px_latch_q : four_ports_t; + + signal data_s : port_vector_t; + + signal p2_s, + p4_s, + p5_s, + p6_s, + p7_s : port_vector_t; + +begin + + -- get rid of H and L + p2_s <= to_X01(p2_i); + p4_s <= to_X01(p4_i); + p5_s <= to_X01(p5_i); + p6_s <= to_X01(p6_i); + p7_s <= to_X01(p7_i); + + ----------------------------------------------------------------------------- + -- Process ctrl_seq + -- + -- Purpose: + -- Implements the sequential elements that control the T8243 core. + -- * latch port number + -- * latch instruction + -- + ctrl_seq: process (clk_i, cs_n_i) + begin + if cs_n_i = '1' then + px_sel_q <= (others => '0'); + p2_en_q <= '0'; + instr_q <= INSTR_WRITE; + + elsif clk_i'event and clk_i = clk_fall_level_c then + if cs_n_i = '0' and clk_fall_en_i = '1' then + -- enable addressed port ---------------------------------------------- + px_sel_q <= (others => '0'); + px_sel_q(to_integer(unsigned(p2_s(1 downto 0))) + + port_range_t'low) <= '1'; + + p2_en_q <= '0'; + + -- decode instruction ------------------------------------------------- + case p2_s(3 downto 2) is + when "00" => + instr_q <= INSTR_READ; + p2_en_q <= '1'; + when "01" => + instr_q <= INSTR_WRITE; + when "10" => + instr_q <= INSTR_ORLD; + when "11" => + instr_q <= INSTR_ANLD; + when others => + null; + end case; + + end if; + + end if; + end process ctrl_seq; + -- + ----------------------------------------------------------------------------- + + + ----------------------------------------------------------------------------- + -- Process port_seq + -- + -- Purpose: + -- Implements the sequential elements of the four ports. + -- + port_seq: process (clk_i, reset_n_i) + begin + if reset_n_i = '0' then + px_en_q <= (others => '0'); + px_latch_q <= (others => (others => '0')); + + elsif rising_edge(clk_i) then + if cs_n_i = '0' and clk_rise_en_i = '1' then + for idx in port_range_t loop + if px_sel_q(idx) = '1' then + if instr_q = INSTR_READ then + -- port is being read from, switch off output enable + px_en_q(idx) <= '0'; + + else + -- port is being written to, enable output + px_en_q(idx) <= '1'; + -- and latch value + px_latch_q(idx) <= data_s; + end if; + end if; + end loop; + end if; + + end if; + end process port_seq; + -- + ----------------------------------------------------------------------------- + + + ----------------------------------------------------------------------------- + -- Process data_gen + -- + -- Purpose: + -- Generates the data for the four port latches. + -- * determines data inputs + -- * calculates result of instruction + -- + -- Multiplexes the read value for P2. + -- + data_gen: process (px_sel_q, + instr_q, + p2_s, + px_latch_q, + p4_s, p5_s, p6_s, p7_s) + variable port_v : port_vector_t; + begin + -- select addressed port + case px_sel_q is + when "0001" => + port_v := px_latch_q(port_4_c); + p2_o <= p4_s; + when "0010" => + port_v := px_latch_q(port_5_c); + p2_o <= p5_s; + when "0100" => + port_v := px_latch_q(port_6_c); + p2_o <= p6_s; + when "1000" => + port_v := px_latch_q(port_7_c); + p2_o <= p7_s; + when others => + port_v := (others => '-'); + p2_o <= (others => '-'); + end case; + + case instr_q is + when INSTR_WRITE => + data_s <= p2_s; + when INSTR_ORLD => + data_s <= p2_s or port_v; + when INSTR_ANLD => + data_s <= p2_s and port_v; + when others => + data_s <= (others => '-'); + end case; + + end process; + -- + ----------------------------------------------------------------------------- + + + ----------------------------------------------------------------------------- + -- Output mapping + ----------------------------------------------------------------------------- + p2_en_o <= '1' + when cs_n_i = '0' and prog_n_i = '0' and p2_en_q = '1' else + '0'; + p4_o <= px_latch_q(port_4_c); + p4_en_o <= px_en_q(port_4_c); + p5_o <= px_latch_q(port_5_c); + p5_en_o <= px_en_q(port_5_c); + p6_o <= px_latch_q(port_6_c); + p6_en_o <= px_en_q(port_6_c); + p7_o <= px_latch_q(port_7_c); + p7_en_o <= px_en_q(port_7_c); + +end rtl; diff --git a/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/t8243/t8243_sync_notri-c.vhd b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/t8243/t8243_sync_notri-c.vhd new file mode 100644 index 0000000000000000000000000000000000000000..d10b783997dca8a2b80da1cd828854e574e1995a --- /dev/null +++ b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/t8243/t8243_sync_notri-c.vhd @@ -0,0 +1,19 @@ +------------------------------------------------------------------------------- +-- +-- T8243 Core +-- +-- $Id: t8243_sync_notri-c.vhd 295 2009-04-01 19:32:48Z arniml $ +-- +------------------------------------------------------------------------------- + +configuration t8243_sync_notri_struct_c0 of t8243_sync_notri is + + for struct + + for t8243_core_b: t8243_core + use configuration work.t8243_core_rtl_c0; + end for; + + end for; + +end t8243_sync_notri_struct_c0; diff --git a/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/t8243/t8243_sync_notri.v b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/t8243/t8243_sync_notri.v new file mode 100644 index 0000000000000000000000000000000000000000..f7f93ea8ee00e4e8fe0ac66618a61c391e112a60 --- /dev/null +++ b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/t8243/t8243_sync_notri.v @@ -0,0 +1,584 @@ +module t8243_core_1 + (input clk_i, + input clk_rise_en_i, + input clk_fall_en_i, + input reset_n_i, + input cs_n_i, + input prog_n_i, + input [3:0] p2_i, + input [3:0] p4_i, + input [3:0] p5_i, + input [3:0] p6_i, + input [3:0] p7_i, + output [3:0] p2_o, + output p2_en_o, + output [3:0] p4_o, + output p4_en_o, + output [3:0] p5_o, + output p5_en_o, + output [3:0] p6_o, + output p6_en_o, + output [3:0] p7_o, + output p7_en_o); + wire [1:0] instr_q; + wire [3:0] px_sel_q; + wire [3:0] px_en_q; + wire p2_en_q; + wire [15:0] px_latch_q; + wire [3:0] data_s; + wire [3:0] p2_s; + wire [3:0] p4_s; + wire [3:0] p5_s; + wire [3:0] p6_s; + wire [3:0] p7_s; + wire n68_o; + wire n69_o; + wire [1:0] n70_o; + wire [30:0] n71_o; + wire [31:0] n72_o; + wire [31:0] n74_o; + wire [1:0] n75_o; + wire [1:0] n77_o; + localparam [3:0] n79_o = 4'b0000; + wire [1:0] n83_o; + wire n85_o; + wire n87_o; + wire n89_o; + wire n91_o; + wire [3:0] n92_o; + reg [1:0] n97_o; + reg n100_o; + wire n116_o; + wire n118_o; + wire n119_o; + wire n120_o; + wire n122_o; + wire n125_o; + wire [3:0] n126_o; + wire [3:0] n127_o; + wire n128_o; + wire n129_o; + wire [3:0] n130_o; + wire [3:0] n131_o; + wire n132_o; + wire n134_o; + wire n137_o; + wire [3:0] n138_o; + wire [3:0] n139_o; + wire n140_o; + wire n141_o; + wire [3:0] n142_o; + wire [3:0] n143_o; + wire n144_o; + wire n146_o; + wire n149_o; + wire [3:0] n150_o; + wire [3:0] n151_o; + wire n152_o; + wire n153_o; + wire [3:0] n154_o; + wire [3:0] n155_o; + wire n156_o; + wire n158_o; + wire n161_o; + wire [3:0] n162_o; + wire [3:0] n163_o; + wire n164_o; + wire n165_o; + wire [3:0] n166_o; + wire [3:0] n167_o; + wire [3:0] n168_o; + wire [15:0] n170_o; + wire [3:0] n181_o; + wire n183_o; + wire [3:0] n184_o; + wire n186_o; + wire [3:0] n187_o; + wire n189_o; + wire [3:0] n190_o; + wire n192_o; + wire [3:0] n193_o; + reg [3:0] n195_o; + reg [3:0] n197_o; + wire n199_o; + wire [3:0] n200_o; + wire n202_o; + wire [3:0] n203_o; + wire n205_o; + wire [2:0] n206_o; + reg [3:0] n208_o; + wire n211_o; + wire n212_o; + wire n213_o; + wire n214_o; + wire n215_o; + wire [3:0] n217_o; + wire n218_o; + wire [3:0] n219_o; + wire n220_o; + wire [3:0] n221_o; + wire n222_o; + wire [3:0] n223_o; + wire n224_o; + wire [1:0] n225_o; + reg [1:0] n226_q; + wire [3:0] n227_o; + reg [3:0] n228_q; + wire [3:0] n229_o; + reg [3:0] n230_q; + wire n231_o; + reg n232_q; + wire [15:0] n233_o; + reg [15:0] n234_q; + wire n235_o; + wire n236_o; + wire n237_o; + wire n238_o; + wire n239_o; + wire n240_o; + wire n241_o; + wire n242_o; + wire n243_o; + wire n244_o; + wire n245_o; + wire n246_o; + wire n247_o; + wire n248_o; + wire n249_o; + wire n250_o; + wire [3:0] n251_o; + assign p2_o = n195_o; + assign p2_en_o = n215_o; + assign p4_o = n217_o; + assign p4_en_o = n218_o; + assign p5_o = n219_o; + assign p5_en_o = n220_o; + assign p6_o = n221_o; + assign p6_en_o = n222_o; + assign p7_o = n223_o; + assign p7_en_o = n224_o; + /* t8243_core.vhd:107:12 */ + assign instr_q = n226_q; // (signal) + /* t8243_core.vhd:115:11 */ + assign px_sel_q = n228_q; // (signal) + /* t8243_core.vhd:117:11 */ + assign px_en_q = n230_q; // (signal) + /* t8243_core.vhd:118:11 */ + assign p2_en_q = n232_q; // (signal) + /* t8243_core.vhd:122:11 */ + assign px_latch_q = n234_q; // (signal) + /* t8243_core.vhd:124:11 */ + assign data_s = n208_o; // (signal) + /* t8243_core.vhd:126:11 */ + assign p2_s = p2_i; // (signal) + /* t8243_core.vhd:127:11 */ + assign p4_s = p4_i; // (signal) + /* t8243_core.vhd:128:11 */ + assign p5_s = p5_i; // (signal) + /* t8243_core.vhd:129:11 */ + assign p6_s = p6_i; // (signal) + /* t8243_core.vhd:130:11 */ + assign p7_s = p7_i; // (signal) + /* t8243_core.vhd:157:17 */ + assign n68_o = ~cs_n_i; + /* t8243_core.vhd:157:23 */ + assign n69_o = clk_fall_en_i & n68_o; + /* t8243_core.vhd:160:42 */ + assign n70_o = p2_s[1:0]; + /* t8243_core.vhd:160:18 */ + assign n71_o = {29'b0, n70_o}; // uext + /* t8243_core.vhd:160:57 */ + assign n72_o = {1'b0, n71_o}; // uext + /* t8243_core.vhd:160:57 */ + assign n74_o = n72_o + 32'b00000000000000000000000000000100; + /* t8243_core.vhd:160:57 */ + assign n75_o = n74_o[1:0]; // trunc + /* t8243_core.vhd:160:57 */ + assign n77_o = n75_o - 2'b00; + /* t8243_core.vhd:166:18 */ + assign n83_o = p2_s[3:2]; + /* t8243_core.vhd:167:11 */ + assign n85_o = n83_o == 2'b00; + /* t8243_core.vhd:170:11 */ + assign n87_o = n83_o == 2'b01; + /* t8243_core.vhd:172:11 */ + assign n89_o = n83_o == 2'b10; + /* t8243_core.vhd:174:11 */ + assign n91_o = n83_o == 2'b11; + assign n92_o = {n91_o, n89_o, n87_o, n85_o}; + /* t8243_core.vhd:166:9 */ + always @* + case (n92_o) + 4'b1000: n97_o = 2'b11; + 4'b0100: n97_o = 2'b10; + 4'b0010: n97_o = 2'b01; + 4'b0001: n97_o = 2'b00; + default: n97_o = instr_q; + endcase + /* t8243_core.vhd:166:9 */ + always @* + case (n92_o) + 4'b1000: n100_o = 1'b0; + 4'b0100: n100_o = 1'b0; + 4'b0010: n100_o = 1'b0; + 4'b0001: n100_o = 1'b1; + default: n100_o = 1'b0; + endcase + /* t8243_core.vhd:196:18 */ + assign n116_o = ~reset_n_i; + /* t8243_core.vhd:201:17 */ + assign n118_o = ~cs_n_i; + /* t8243_core.vhd:201:23 */ + assign n119_o = clk_rise_en_i & n118_o; + /* t8243_core.vhd:203:22 */ + assign n120_o = px_sel_q[3]; + /* t8243_core.vhd:204:24 */ + assign n122_o = instr_q == 2'b00; + /* t8243_core.vhd:204:13 */ + assign n125_o = n122_o ? 1'b0 : 1'b1; + assign n126_o = px_latch_q[15:12]; + /* t8243_core.vhd:204:13 */ + assign n127_o = n122_o ? n126_o : data_s; + assign n128_o = px_en_q[3]; + /* t8243_core.vhd:203:11 */ + assign n129_o = n120_o ? n125_o : n128_o; + assign n130_o = px_latch_q[15:12]; + /* t8243_core.vhd:203:11 */ + assign n131_o = n120_o ? n127_o : n130_o; + /* t8243_core.vhd:203:22 */ + assign n132_o = px_sel_q[2]; + /* t8243_core.vhd:204:24 */ + assign n134_o = instr_q == 2'b00; + /* t8243_core.vhd:204:13 */ + assign n137_o = n134_o ? 1'b0 : 1'b1; + assign n138_o = px_latch_q[11:8]; + /* t8243_core.vhd:204:13 */ + assign n139_o = n134_o ? n138_o : data_s; + assign n140_o = px_en_q[2]; + /* t8243_core.vhd:203:11 */ + assign n141_o = n132_o ? n137_o : n140_o; + assign n142_o = px_latch_q[11:8]; + /* t8243_core.vhd:203:11 */ + assign n143_o = n132_o ? n139_o : n142_o; + /* t8243_core.vhd:203:22 */ + assign n144_o = px_sel_q[1]; + /* t8243_core.vhd:204:24 */ + assign n146_o = instr_q == 2'b00; + /* t8243_core.vhd:204:13 */ + assign n149_o = n146_o ? 1'b0 : 1'b1; + assign n150_o = px_latch_q[7:4]; + /* t8243_core.vhd:204:13 */ + assign n151_o = n146_o ? n150_o : data_s; + assign n152_o = px_en_q[1]; + /* t8243_core.vhd:203:11 */ + assign n153_o = n144_o ? n149_o : n152_o; + assign n154_o = px_latch_q[7:4]; + /* t8243_core.vhd:203:11 */ + assign n155_o = n144_o ? n151_o : n154_o; + /* t8243_core.vhd:203:22 */ + assign n156_o = px_sel_q[0]; + /* t8243_core.vhd:204:24 */ + assign n158_o = instr_q == 2'b00; + /* t8243_core.vhd:204:13 */ + assign n161_o = n158_o ? 1'b0 : 1'b1; + assign n162_o = px_latch_q[3:0]; + /* t8243_core.vhd:204:13 */ + assign n163_o = n158_o ? n162_o : data_s; + assign n164_o = px_en_q[0]; + /* t8243_core.vhd:203:11 */ + assign n165_o = n156_o ? n161_o : n164_o; + assign n166_o = px_latch_q[3:0]; + /* t8243_core.vhd:203:11 */ + assign n167_o = n156_o ? n163_o : n166_o; + assign n168_o = {n129_o, n141_o, n153_o, n165_o}; + assign n170_o = {n131_o, n143_o, n155_o, n167_o}; + /* t8243_core.vhd:244:29 */ + assign n181_o = px_latch_q[3:0]; + /* t8243_core.vhd:243:7 */ + assign n183_o = px_sel_q == 4'b0001; + /* t8243_core.vhd:247:29 */ + assign n184_o = px_latch_q[7:4]; + /* t8243_core.vhd:246:7 */ + assign n186_o = px_sel_q == 4'b0010; + /* t8243_core.vhd:250:29 */ + assign n187_o = px_latch_q[11:8]; + /* t8243_core.vhd:249:7 */ + assign n189_o = px_sel_q == 4'b0100; + /* t8243_core.vhd:253:29 */ + assign n190_o = px_latch_q[15:12]; + /* t8243_core.vhd:252:7 */ + assign n192_o = px_sel_q == 4'b1000; + assign n193_o = {n192_o, n189_o, n186_o, n183_o}; + /* t8243_core.vhd:242:5 */ + always @* + case (n193_o) + 4'b1000: n195_o = p7_s; + 4'b0100: n195_o = p6_s; + 4'b0010: n195_o = p5_s; + 4'b0001: n195_o = p4_s; + default: n195_o = 4'bX; + endcase + /* t8243_core.vhd:242:5 */ + always @* + case (n193_o) + 4'b1000: n197_o = n190_o; + 4'b0100: n197_o = n187_o; + 4'b0010: n197_o = n184_o; + 4'b0001: n197_o = n181_o; + default: n197_o = 4'bX; + endcase + /* t8243_core.vhd:261:7 */ + assign n199_o = instr_q == 2'b01; + /* t8243_core.vhd:264:24 */ + assign n200_o = p2_s | n197_o; + /* t8243_core.vhd:263:7 */ + assign n202_o = instr_q == 2'b10; + /* t8243_core.vhd:266:24 */ + assign n203_o = p2_s & n197_o; + /* t8243_core.vhd:265:7 */ + assign n205_o = instr_q == 2'b11; + assign n206_o = {n205_o, n202_o, n199_o}; + /* t8243_core.vhd:260:5 */ + always @* + case (n206_o) + 3'b100: n208_o = n203_o; + 3'b010: n208_o = n200_o; + 3'b001: n208_o = p2_s; + default: n208_o = 4'bX; + endcase + /* t8243_core.vhd:280:26 */ + assign n211_o = ~cs_n_i; + /* t8243_core.vhd:280:45 */ + assign n212_o = ~prog_n_i; + /* t8243_core.vhd:280:32 */ + assign n213_o = n212_o & n211_o; + /* t8243_core.vhd:280:51 */ + assign n214_o = p2_en_q & n213_o; + /* t8243_core.vhd:280:14 */ + assign n215_o = n214_o ? 1'b1 : 1'b0; + /* t8243_core.vhd:282:24 */ + assign n217_o = px_latch_q[3:0]; + /* t8243_core.vhd:283:21 */ + assign n218_o = px_en_q[0]; + /* t8243_core.vhd:284:24 */ + assign n219_o = px_latch_q[7:4]; + /* t8243_core.vhd:285:21 */ + assign n220_o = px_en_q[1]; + /* t8243_core.vhd:286:24 */ + assign n221_o = px_latch_q[11:8]; + /* t8243_core.vhd:287:21 */ + assign n222_o = px_en_q[2]; + /* t8243_core.vhd:288:24 */ + assign n223_o = px_latch_q[15:12]; + /* t8243_core.vhd:289:21 */ + assign n224_o = px_en_q[3]; + /* t8243_core.vhd:156:5 */ + assign n225_o = n69_o ? n97_o : instr_q; + /* t8243_core.vhd:156:5 */ + always @(negedge clk_i or posedge cs_n_i) + if (cs_n_i) + n226_q <= 2'b01; + else + n226_q <= n225_o; + /* t8243_core.vhd:156:5 */ + assign n227_o = n69_o ? n251_o : px_sel_q; + /* t8243_core.vhd:156:5 */ + always @(negedge clk_i or posedge cs_n_i) + if (cs_n_i) + n228_q <= 4'b0000; + else + n228_q <= n227_o; + /* t8243_core.vhd:200:5 */ + assign n229_o = n119_o ? n168_o : px_en_q; + /* t8243_core.vhd:200:5 */ + always @(posedge clk_i or posedge n116_o) + if (n116_o) + n230_q <= 4'b0000; + else + n230_q <= n229_o; + /* t8243_core.vhd:156:5 */ + assign n231_o = n69_o ? n100_o : p2_en_q; + /* t8243_core.vhd:156:5 */ + always @(negedge clk_i or posedge cs_n_i) + if (cs_n_i) + n232_q <= 1'b0; + else + n232_q <= n231_o; + /* t8243_core.vhd:200:5 */ + assign n233_o = n119_o ? n170_o : px_latch_q; + /* t8243_core.vhd:200:5 */ + always @(posedge clk_i or posedge n116_o) + if (n116_o) + n234_q <= 16'b0000000000000000; + else + n234_q <= n233_o; + /* t8243_core.vhd:160:9 */ + assign n235_o = n77_o[1]; + /* t8243_core.vhd:160:9 */ + assign n236_o = ~n235_o; + /* t8243_core.vhd:160:9 */ + assign n237_o = n77_o[0]; + /* t8243_core.vhd:160:9 */ + assign n238_o = ~n237_o; + /* t8243_core.vhd:160:9 */ + assign n239_o = n236_o & n238_o; + /* t8243_core.vhd:160:9 */ + assign n240_o = n236_o & n237_o; + /* t8243_core.vhd:160:9 */ + assign n241_o = n235_o & n238_o; + /* t8243_core.vhd:160:9 */ + assign n242_o = n235_o & n237_o; + /* t8243_core.vhd:68:5 */ + assign n243_o = n79_o[0]; + /* t8243_core.vhd:160:9 */ + assign n244_o = n239_o ? 1'b1 : n243_o; + assign n245_o = n79_o[1]; + /* t8243_core.vhd:160:9 */ + assign n246_o = n240_o ? 1'b1 : n245_o; + /* t8243_core.vhd:239:14 */ + assign n247_o = n79_o[2]; + /* t8243_core.vhd:160:9 */ + assign n248_o = n241_o ? 1'b1 : n247_o; + assign n249_o = n79_o[3]; + /* t8243_core.vhd:160:9 */ + assign n250_o = n242_o ? 1'b1 : n249_o; + /* t8243_core.vhd:200:5 */ + assign n251_o = {n250_o, n248_o, n246_o, n244_o}; +endmodule + +module t8243_sync_notri + (input clk_i, + input clk_en_i, + input reset_n_i, + input cs_n_i, + input prog_n_i, + input [3:0] p2_i, + input [3:0] p4_i, + input [3:0] p5_i, + input [3:0] p6_i, + input [3:0] p7_i, + output [3:0] p2_o, + output p2_en_o, + output [3:0] p4_o, + output p4_en_o, + output [3:0] p5_o, + output p5_en_o, + output [3:0] p6_o, + output p6_en_o, + output [3:0] p7_o, + output p7_en_o); + wire prog_n_q; + wire clk_rise_en_s; + wire clk_fall_en_s; + wire n11_o; + wire n18_o; + wire n19_o; + wire n20_o; + wire n21_o; + wire n22_o; + wire n23_o; + wire [3:0] t8243_core_b_n24; + wire t8243_core_b_n25; + wire [3:0] t8243_core_b_n26; + wire t8243_core_b_n27; + wire [3:0] t8243_core_b_n28; + wire t8243_core_b_n29; + wire [3:0] t8243_core_b_n30; + wire t8243_core_b_n31; + wire [3:0] t8243_core_b_n32; + wire t8243_core_b_n33; + wire [3:0] t8243_core_b_p2_o; + wire t8243_core_b_p2_en_o; + wire [3:0] t8243_core_b_p4_o; + wire t8243_core_b_p4_en_o; + wire [3:0] t8243_core_b_p5_o; + wire t8243_core_b_p5_en_o; + wire [3:0] t8243_core_b_p6_o; + wire t8243_core_b_p6_en_o; + wire [3:0] t8243_core_b_p7_o; + wire t8243_core_b_p7_en_o; + wire n54_o; + reg n55_q; + assign p2_o = t8243_core_b_n24; + assign p2_en_o = t8243_core_b_n25; + assign p4_o = t8243_core_b_n26; + assign p4_en_o = t8243_core_b_n27; + assign p5_o = t8243_core_b_n28; + assign p5_en_o = t8243_core_b_n29; + assign p6_o = t8243_core_b_n30; + assign p6_en_o = t8243_core_b_n31; + assign p7_o = t8243_core_b_n32; + assign p7_en_o = t8243_core_b_n33; + /* t8243_sync_notri.vhd:88:10 */ + assign prog_n_q = n55_q; // (signal) + /* t8243_sync_notri.vhd:89:10 */ + assign clk_rise_en_s = n20_o; // (signal) + /* t8243_sync_notri.vhd:90:10 */ + assign clk_fall_en_s = n23_o; // (signal) + /* t8243_sync_notri.vhd:103:18 */ + assign n11_o = ~reset_n_i; + /* t8243_sync_notri.vhd:117:20 */ + assign n18_o = ~prog_n_q; + /* t8243_sync_notri.vhd:116:29 */ + assign n19_o = clk_en_i & n18_o; + /* t8243_sync_notri.vhd:117:33 */ + assign n20_o = n19_o & prog_n_i; + /* t8243_sync_notri.vhd:118:29 */ + assign n21_o = clk_en_i & prog_n_q; + /* t8243_sync_notri.vhd:119:33 */ + assign n22_o = ~prog_n_i; + /* t8243_sync_notri.vhd:119:29 */ + assign n23_o = n21_o & n22_o; + /* t8243_sync_notri.vhd:137:24 */ + assign t8243_core_b_n24 = t8243_core_b_p2_o; // (signal) + /* t8243_sync_notri.vhd:138:24 */ + assign t8243_core_b_n25 = t8243_core_b_p2_en_o; // (signal) + /* t8243_sync_notri.vhd:140:24 */ + assign t8243_core_b_n26 = t8243_core_b_p4_o; // (signal) + /* t8243_sync_notri.vhd:141:24 */ + assign t8243_core_b_n27 = t8243_core_b_p4_en_o; // (signal) + /* t8243_sync_notri.vhd:143:24 */ + assign t8243_core_b_n28 = t8243_core_b_p5_o; // (signal) + /* t8243_sync_notri.vhd:144:24 */ + assign t8243_core_b_n29 = t8243_core_b_p5_en_o; // (signal) + /* t8243_sync_notri.vhd:146:24 */ + assign t8243_core_b_n30 = t8243_core_b_p6_o; // (signal) + /* t8243_sync_notri.vhd:147:24 */ + assign t8243_core_b_n31 = t8243_core_b_p6_en_o; // (signal) + /* t8243_sync_notri.vhd:149:24 */ + assign t8243_core_b_n32 = t8243_core_b_p7_o; // (signal) + /* t8243_sync_notri.vhd:150:24 */ + assign t8243_core_b_n33 = t8243_core_b_p7_en_o; // (signal) + /* t8243_sync_notri.vhd:125:3 */ + t8243_core_1 t8243_core_b ( + .clk_i(clk_i), + .clk_rise_en_i(clk_rise_en_s), + .clk_fall_en_i(clk_fall_en_s), + .reset_n_i(reset_n_i), + .cs_n_i(cs_n_i), + .prog_n_i(prog_n_i), + .p2_i(p2_i), + .p4_i(p4_i), + .p5_i(p5_i), + .p6_i(p6_i), + .p7_i(p7_i), + .p2_o(t8243_core_b_p2_o), + .p2_en_o(t8243_core_b_p2_en_o), + .p4_o(t8243_core_b_p4_o), + .p4_en_o(t8243_core_b_p4_en_o), + .p5_o(t8243_core_b_p5_o), + .p5_en_o(t8243_core_b_p5_en_o), + .p6_o(t8243_core_b_p6_o), + .p6_en_o(t8243_core_b_p6_en_o), + .p7_o(t8243_core_b_p7_o), + .p7_en_o(t8243_core_b_p7_en_o)); + /* t8243_sync_notri.vhd:105:5 */ + assign n54_o = clk_en_i ? prog_n_i : prog_n_q; + /* t8243_sync_notri.vhd:105:5 */ + always @(posedge clk_i or posedge n11_o) + if (n11_o) + n55_q <= 1'b1; + else + n55_q <= n54_o; +endmodule + diff --git a/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/t8243/t8243_sync_notri.vhd b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/t8243/t8243_sync_notri.vhd new file mode 100644 index 0000000000000000000000000000000000000000..980b664dc0cb5c45e97f8343d3f7c41ca1dd3e64 --- /dev/null +++ b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/cpu/t8243/t8243_sync_notri.vhd @@ -0,0 +1,153 @@ +------------------------------------------------------------------------------- +-- +-- The T8243 synchronous toplevel without tri-state signals +-- +-- $Id: t8243_sync_notri.vhd 295 2009-04-01 19:32:48Z arniml $ +-- +-- Copyright (c) 2006, Arnim Laeuger (arniml@opencores.org) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.opencores.org/cvsweb.shtml/t48/ +-- +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; + +entity t8243_sync_notri is + + port ( + -- System Interface ------------------------------------------------------- + clk_i : in std_logic; + clk_en_i : in std_logic; + reset_n_i : in std_logic; + -- Control Interface ------------------------------------------------------ + cs_n_i : in std_logic; + prog_n_i : in std_logic; + -- Port 2 Interface ------------------------------------------------------- + p2_i : in std_logic_vector(3 downto 0); + p2_o : out std_logic_vector(3 downto 0); + p2_en_o : out std_logic; + -- Port 4 Interface ------------------------------------------------------- + p4_i : in std_logic_vector(3 downto 0); + p4_o : out std_logic_vector(3 downto 0); + p4_en_o : out std_logic; + -- Port 5 Interface ------------------------------------------------------- + p5_i : in std_logic_vector(3 downto 0); + p5_o : out std_logic_vector(3 downto 0); + p5_en_o : out std_logic; + -- Port 6 Interface ------------------------------------------------------- + p6_i : in std_logic_vector(3 downto 0); + p6_o : out std_logic_vector(3 downto 0); + p6_en_o : out std_logic; + -- Port 7 Interface ------------------------------------------------------- + p7_i : in std_logic_vector(3 downto 0); + p7_o : out std_logic_vector(3 downto 0); + p7_en_o : out std_logic + ); + +end t8243_sync_notri; + + +use work.t8243_comp_pack.t8243_core; + +architecture struct of t8243_sync_notri is + + signal prog_n_q : std_logic; + signal clk_rise_en_s, + clk_fall_en_s : std_logic; + +begin + + ----------------------------------------------------------------------------- + -- Process edge_detect + -- + -- Purpose: + -- Implements the sequential element required for edge detection + -- on the PROG input. + -- + edge_detect: process (clk_i, reset_n_i) + begin + if reset_n_i = '0' then + prog_n_q <= '1'; + elsif rising_edge(clk_i) then + if clk_en_i = '1' then + prog_n_q <= prog_n_i; + end if; + end if; + end process edge_detect; + -- + ----------------------------------------------------------------------------- + + + -- clock enables to detect rising and falling edges of PROG + clk_rise_en_s <= clk_en_i and + not prog_n_q and prog_n_i; + clk_fall_en_s <= clk_en_i and + prog_n_q and not prog_n_i; + + + ----------------------------------------------------------------------------- + -- The T8243 Core + ----------------------------------------------------------------------------- + t8243_core_b : t8243_core + generic map ( + clk_fall_level_g => 1 + ) + port map ( + clk_i => clk_i, + clk_rise_en_i => clk_rise_en_s, + clk_fall_en_i => clk_fall_en_s, + reset_n_i => reset_n_i, + cs_n_i => cs_n_i, + prog_n_i => prog_n_i, + p2_i => p2_i, + p2_o => p2_o, + p2_en_o => p2_en_o, + p4_i => p4_i, + p4_o => p4_o, + p4_en_o => p4_en_o, + p5_i => p5_i, + p5_o => p5_o, + p5_en_o => p5_en_o, + p6_i => p6_i, + p6_o => p6_o, + p6_en_o => p6_en_o, + p7_i => p7_i, + p7_o => p7_o, + p7_en_o => p7_en_o + ); + +end struct; diff --git a/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/lightgun/jtframe_lightgun.v b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/lightgun/jtframe_lightgun.v new file mode 100644 index 0000000000000000000000000000000000000000..3cf1104812629caf35814f006108543011bf9a2a --- /dev/null +++ b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/lightgun/jtframe_lightgun.v @@ -0,0 +1,114 @@ +/* This file is part of JTFRAME. + JTFRAME program is free software: you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation, either version 3 of the License, or + (at your option) any later version. + + JTFRAME program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with JTFRAME. If not, see . + + Author: Rafael Eduardo Paiva Feener. Copyright: Miki Saito + Version: 1.0 + Date: 25-02-2025 */ + +module jtframe_lightgun ( + input rst, + input clk, + input vs, + input [ 7:0] debug_bus, + input gun_crossh_en, + input [ 1:0] rotate, + input [ 1:0] sensty, + input [ 3:0] game_joy1, + input [ 3:0] game_joy2, + input [15:0] joyana1, + input [15:0] joyana2, + input [15:0] mouse_1p, + input [15:0] mouse_2p, + input [ 1:0] mouse_strobe, + output [ 8:0] gun_1p_x, + output [ 8:0] gun_1p_y, + output [ 8:0] gun_2p_x, + output [ 8:0] gun_2p_y, + output [ 8:0] cross1_x, + output [ 8:0] cross1_y, + output [ 8:0] cross2_x, + output [ 8:0] cross2_y, + output [ 1:0] cross_disable +); + +parameter WIDTH = 384, HEIGHT = 224, + XOFFSET= `ifdef JTFRAME_LIGHTGUN_XOFFSET `JTFRAME_LIGHTGUN_XOFFSET `else 0 `endif, + YOFFSET= `ifdef JTFRAME_LIGHTGUN_YOFFSET `JTFRAME_LIGHTGUN_YOFFSET `else 0 `endif; + +`ifdef JTFRAME_LIGHTGUN + +wire [1:0] strobe; +wire vs_edge; + +jtframe_lightgun_mux #(.W(WIDTH),.H(HEIGHT), + .XOFFSET(XOFFSET),.YOFFSET(YOFFSET) +) u_crosshair_left( + .rst ( rst ), + .clk ( clk ), + .vs_edge ( vs_edge ), + .debug_bus ( debug_bus ), + .gun_crossh_en( gun_crossh_en ), + .rotate ( rotate ), + .sensty ( sensty ), + .game_joy ( game_joy1 ), + .joyana ( joyana1 ), + .mouse ( mouse_1p ), + .mouse_strobe ( mouse_strobe[0] ), + .strobe ( strobe[0] ), + .gun_x ( gun_1p_x ), + .gun_y ( gun_1p_y ), + .cross_x ( cross1_x ), + .cross_y ( cross1_y ) +); + +jtframe_lightgun_mux #(.W(WIDTH),.H(HEIGHT), + .XOFFSET(XOFFSET),.YOFFSET(YOFFSET) +) u_crosshair_center( + .rst ( rst ), + .clk ( clk ), + .vs_edge ( vs_edge ), + .debug_bus ( debug_bus ), + .gun_crossh_en( gun_crossh_en ), + .rotate ( rotate ), + .sensty ( sensty ), + .game_joy ( game_joy2 ), + .joyana ( joyana2 ), + .mouse ( mouse_2p ), + .mouse_strobe ( mouse_strobe[1] ), + .strobe ( strobe[1] ), + .gun_x ( gun_2p_x ), + .gun_y ( gun_2p_y ), + .cross_x ( cross2_x ), + .cross_y ( cross2_y ) +); + + +jtframe_crosshair_disable u_crosshair_disable( + .rst ( rst ), + .clk ( clk ), + .vs ( vs ), + .strobe ( strobe ), + .pulse ( vs_edge ), + .en_b ( cross_disable ) +); + +`else +assign {gun_1p_x, gun_1p_y} = 18'b0; +assign {gun_2p_x, gun_2p_y} = 18'b0; +assign {cross1_x, cross1_y} = 18'b0; +assign {cross2_x, cross2_y} = 18'b0; +assign cross_disable = 2'd3; +`endif + +endmodule diff --git a/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/lightgun/jtframe_lightgun_joyemu.v b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/lightgun/jtframe_lightgun_joyemu.v new file mode 100644 index 0000000000000000000000000000000000000000..146bf6d00d0eadd988c49fd4d36ff83fc552022b --- /dev/null +++ b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/lightgun/jtframe_lightgun_joyemu.v @@ -0,0 +1,84 @@ +/* This file is part of JTFRAME. + JTFRAME program is free software: you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation, either version 3 of the License, or + (at your option) any later version. + + JTFRAME program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with JTFRAME. If not, see . + + Author: Rafael Eduardo Paiva Feener. Copyright: Miki Saito + Version: 1.0 + Date: 02-10-2025 */ + +module jtframe_lightgun_joyemu( + input clk, + input vs_edge, + output strobe, + input [1:0] rotate, + input [1:0] sensty, + input [3:0] game_joy, + input [7:0] debug_bus, + output [8:0] x, y +); + +parameter W = 384, H = 224; + +reg [7:0] dx_in, dy_in; +wire [7:0] dx, dy; +reg [6:0] base_val; +reg joystr; +wire joy_on; + +assign joy_on = |game_joy; + +always @(*) begin + base_val = 7'h7; + case (sensty) + 1: base_val = base_val + 7'h2; + 0: base_val = base_val + 7'h0; + 3: base_val = base_val - 7'h2; + 2: base_val = base_val - 7'h4; + default:; + endcase +end + +always @(posedge clk) begin + joystr <= 0; + if(vs_edge) begin + joystr <= joy_on; + {dx_in, dy_in} <= 0; + if(game_joy[0]) dx_in <= {1'b0, base_val}; + if(game_joy[1]) dx_in <= {1'b1,-base_val}; + if(game_joy[2]) dy_in <= {1'b1,-base_val}; + if(game_joy[3]) dy_in <= {1'b0, base_val}; + end +end + +jtframe_mouse_rotation u_rotation( + .clk ( clk ), + .strobe ( joystr ), + .strobe_dly ( strobe ), + .rotate ( rotate ), + .dx_in ( dx_in ), + .dy_in ( dy_in ), + .dx ( dx ), + .dy ( dy ) +); + +jtframe_mouse_abspos #(.W(W),.H(H) +) u_abspos( + .clk ( clk ), + .dx ( dx ), + .dy ( dy ), + .strobe ( strobe ), + .x ( x ), + .y ( y ) +); + +endmodule \ No newline at end of file diff --git a/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/lightgun/jtframe_lightgun_mux.v b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/lightgun/jtframe_lightgun_mux.v new file mode 100644 index 0000000000000000000000000000000000000000..71cc6b9142689b0c138f3cfa35957dca024f36f8 --- /dev/null +++ b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/lightgun/jtframe_lightgun_mux.v @@ -0,0 +1,110 @@ +/* This file is part of JTFRAME. + JTFRAME program is free software: you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation, either version 3 of the License, or + (at your option) any later version. + + JTFRAME program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with JTFRAME. If not, see . + + Author: Rafael Eduardo Paiva Feener. Copyright: Miki Saito + Version: 1.0 + Date: 14-03-2025 */ + +module jtframe_lightgun_mux( + input rst, + input clk, + input vs_edge, + input [ 7:0] debug_bus, + input gun_crossh_en, + input [ 1:0] rotate, + input [ 1:0] sensty, + input [ 3:0] game_joy, + input [15:0] joyana, + input [15:0] mouse, + input mouse_strobe, + output strobe, + output [ 8:0] gun_x, + output [ 8:0] gun_y, + output [ 8:0] cross_x, + output [ 8:0] cross_y +); + +parameter W = 384, H = 224, XOFFSET=0, YOFFSET=0; + +wire [8:0] mouse_x, mouse_y, joyana_x, joyana_y, + joy_x, joy_y; +wire [7:0] dx, dy; +wire a_strobe, mouse_strobe_dly, j_strobe; + +jtframe_mouse_rotation u_mouse_rotation( + .clk ( clk ), + .strobe ( mouse_strobe ), + .strobe_dly ( mouse_strobe_dly ), + .rotate ( rotate ), + .dx_in ( mouse[ 7: 0] ), + .dy_in ( mouse[15: 8] ), + .dx ( dx ), + .dy ( dy ) +); + +jtframe_mouse_abspos #(.W(W),.H(H) +) u_mouse_abspos( + .clk ( clk ), + .dx ( dx ), + .dy ( dy ), + .strobe ( mouse_strobe_dly ), + .x ( mouse_x ), + .y ( mouse_y ) +); + +jtframe_lightgun_scaler #(.W(W),.H(H) +) u_lightgun_scaler( + .clk ( clk ), + .joyana ( joyana ), + .strobe ( a_strobe ), + .x ( joyana_x ), + .y ( joyana_y ) +); + +jtframe_lightgun_joyemu #(.W(W),.H(H) +) u_lightgun_joy( + .clk ( clk ), + .vs_edge ( vs_edge ), + .strobe ( j_strobe ), + .rotate ( rotate ), + .sensty ( sensty ), + .game_joy ( game_joy ), + .debug_bus ( debug_bus ), + .x ( joy_x ), + .y ( joy_y ) +); + +jtframe_lightgun_position #( + .XOFFSET(XOFFSET),.YOFFSET(YOFFSET) +) u_lightgun_position( + .rst ( rst ), + .clk ( clk ), + .gun_crossh_en( gun_crossh_en ), + .m_x ( mouse_x ), + .m_y ( mouse_y ), + .m_strobe ( mouse_strobe ), + .a_x ( joyana_x ), + .a_y ( joyana_y ), + .a_strobe ( a_strobe ), + .j_x ( joy_x ), + .j_y ( joy_y ), + .j_strobe ( j_strobe ), + .x ( gun_x ), + .y ( gun_y ), + .x_abs ( cross_x ), + .y_abs ( cross_y ), + .strobe ( strobe ) +); + +endmodule \ No newline at end of file diff --git a/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/lightgun/jtframe_lightgun_position.v b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/lightgun/jtframe_lightgun_position.v new file mode 100644 index 0000000000000000000000000000000000000000..434ce9f1e7afcb9bb75b37e8035282061214ff54 --- /dev/null +++ b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/lightgun/jtframe_lightgun_position.v @@ -0,0 +1,63 @@ +/* This file is part of JTFRAME. + JTFRAME program is free software: you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation, either version 3 of the License, or + (at your option) any later version. + + JTFRAME program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with JTFRAME. If not, see . + + Author: Rafael Eduardo Paiva Feener. Copyright: Miki Saito + Version: 1.0 + Date: 14-03-2025 */ + +module jtframe_lightgun_position( + input rst, + input clk, + input gun_crossh_en, + input [ 8:0] m_x, m_y, // mouse + input m_strobe, + input [ 8:0] a_x, a_y, // analog stick + input a_strobe, + input [ 8:0] j_x, j_y, // dpad + input j_strobe, + output reg [ 8:0] x, + output reg [ 8:0] y, + output reg [ 8:0] x_abs, + output reg [ 8:0] y_abs, + output reg strobe +); + +parameter XOFFSET=0, YOFFSET=0; + +always @(posedge clk) strobe <= m_strobe | (a_strobe & gun_crossh_en) | j_strobe; + +always @(posedge clk) begin + if(rst) begin + x <= 0; y <= 0; + x_abs <= 0; y_abs <= 0; + end else begin + x <= x_abs + XOFFSET[8:0]; + y <= y_abs + YOFFSET[8:0]; + + if (j_strobe) begin + x_abs <= j_x; + y_abs <= j_y; + end + if (a_strobe) begin + x_abs <= a_x; + y_abs <= a_y; + end + if (m_strobe) begin + x_abs <= m_x; + y_abs <= m_y; + end + end +end + +endmodule diff --git a/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/lightgun/jtframe_lightgun_scaler.v b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/lightgun/jtframe_lightgun_scaler.v new file mode 100644 index 0000000000000000000000000000000000000000..da1c33891a689b972436f86ad568785600877f8f --- /dev/null +++ b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/lightgun/jtframe_lightgun_scaler.v @@ -0,0 +1,51 @@ +/* This file is part of JTFRAME. + JTFRAME program is free software: you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation, either version 3 of the License, or + (at your option) any later version. + + JTFRAME program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with JTFRAME. If not, see . + + Author: Rafael Eduardo Paiva Feener. Copyright: Miki Saito + Version: 1.0 + Date: 14-03-2025 */ + +module jtframe_lightgun_scaler( + input clk, + input [15:0] joyana, + output reg strobe, + output reg [ 8:0] x, + output reg [ 8:0] y +); + +parameter W = 384, H = 224; + +reg [15:0] joya_l; +wire [ 9:0] x_next, y_next; +wire [ 7:0] x_corr, y_corr; +reg [17:0] x_scaled, y_scaled; + +assign x_corr = joyana[ 7:0] + 8'h80; +assign y_corr = joyana[15:8] + 8'h80; +assign x_next = x_scaled[17:8]; +assign y_next = y_scaled[17:8]; + +always @(*) begin + x_scaled = x_corr[7:0] * W[8:0]; + y_scaled = y_corr[7:0] * H[8:0]; +end + +always @(posedge clk) begin + x <= x_next[8:0]; + y <= y_next[8:0]; + strobe <= |joyana; + if(strobe) strobe <= 0; +end + +endmodule diff --git a/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/lightgun/jtframe_mouse_abspos.v b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/lightgun/jtframe_mouse_abspos.v new file mode 100644 index 0000000000000000000000000000000000000000..69bf97f594e569b5b10280bfe6c3ef5cdf27a06b --- /dev/null +++ b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/lightgun/jtframe_mouse_abspos.v @@ -0,0 +1,52 @@ +/* This file is part of JTCORES. + JTCORES program is free software: you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation, either version 3 of the License, or + (at your option) any later version. + + JTCORES program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with JTCORES. If not, see . + + Author: Rafael Eduardo Paiva Feener. Copyright: Miki Saito +*/ + +module jtframe_mouse_abspos( + input clk, + input [7:0] dx, + input [7:0] dy, + input strobe, + output reg [8:0] x, + output reg [8:0] y +); + +parameter W = 384, H = 224; + +wire [9:0] x_next, y_next; + +assign x_next = {1'b0, x} + {{2{dx[7]}}, dx}; +assign y_next = {1'b0, y} - {{2{dy[7]}}, dy}; + +always @(posedge clk) begin + if (strobe) begin + if (x_next[9] && dx[7]) + x <= 0; + else if (x_next[8:0] > W[8:0]) + x <= W[8:0]; + else + x <= x_next[8:0]; + + if (y_next[9] && !dy[7]) + y <= 0; + else if (y_next[8:0] > H[8:0]) + y <= H[8:0]; + else + y <= y_next[8:0]; + end +end + +endmodule diff --git a/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/lightgun/jtframe_mouse_rotation.v b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/lightgun/jtframe_mouse_rotation.v new file mode 100644 index 0000000000000000000000000000000000000000..7e3ac75efe4b59e121e4e3ac123e291a9659076d --- /dev/null +++ b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/lightgun/jtframe_mouse_rotation.v @@ -0,0 +1,38 @@ +/* This file is part of JTFRAME. + JTFRAME program is free software: you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation, either version 3 of the License, or + (at your option) any later version. + + JTFRAME program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with JTFRAME. If not, see . + + Author: Rafael Eduardo Paiva Feener. Copyright: Miki Saito + Version: 1.0 + Date: 14-03-2025 */ + +module jtframe_mouse_rotation( + input clk, + input strobe, + output reg strobe_dly, + input [1:0] rotate, + input [7:0] dx_in, dy_in, + output reg [7:0] dx, dy +); + +always @(posedge clk) begin + dx <= dx_in; + dy <= dy_in; + strobe_dly <= strobe; + if(rotate[0]) begin + dx <= rotate[1] ? dy_in : -dy_in; + dy <= rotate[1] ? -dx_in : dx_in; + end +end + +endmodule \ No newline at end of file diff --git a/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/sound/Makefile b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/sound/Makefile new file mode 100644 index 0000000000000000000000000000000000000000..e471a6d2e4ec8096df3ff3f5cd8d9cffa348ad4c --- /dev/null +++ b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/sound/Makefile @@ -0,0 +1,22 @@ +all: uprate2.hex uprate3.hex firjt49.hex + +uprate2.hex: filter2 fir_coeff + fir_coeff filter2 > uprate2.hex + +uprate3.hex: filter3 fir_coeff + fir_coeff filter3 > uprate3.hex + +firjt49.hex: firjt49 fir_coeff + fir_coeff firjt49 > firjt49.hex + +filter2: jtframe_fir2.m + octave jtframe_fir2.m + +filter3: jtframe_fir3.m + octave jtframe_fir3.m + +firjt49: firjt49.m + octave firjt49.m + +fir_coeff: fir_coeff.c + gcc fir_coeff.c -o fir_coeff \ No newline at end of file diff --git a/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/sound/audio_mod.yaml b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/sound/audio_mod.yaml new file mode 100644 index 0000000000000000000000000000000000000000..d6e42dc0327c8f8d7ec21d6c6589e96901a2f137 --- /dev/null +++ b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/sound/audio_mod.yaml @@ -0,0 +1,82 @@ +# Default module definitions +# vpp is the normalized amplitude for a 5V supply +# i.e. YM3014 outputs from 1/4*VDD to 3/4*VDD, so its vpp is 0.5 +# MSM5205 outputs goes from 0 to 5V, so its vpp is 1.0 + +# jt49: 10 kOhm load resistor -> 2.25V -> vpp = 0.45 +# jt49: 1 kOhm load resistor -> 0.92V -> vpp = 0.18 +# using 1 kOhm for vpp, as it is more typical +# AY-3-8910 could have different VPP than YM2149 +# each channel is vpp: 0.2 but as jt49 merges the channel without +# saturation, it adds extra bits that will result in less gain in the +# jtframe mixer. For now, setting vpp to 0.6 (0.2*3 channels). Real +# circuit probably has a compressed output, and different profile depending +# on whether the channels are joined or not and the load resistor side. +# it must be measured at some point +# AY-3-8910 +jt49: { data_width: 10, unsigned: true, dcrm: true, vpp: 0.6 } +# MSM5232 - once outputs are combined +jt5232: { data_width: 16, unsigned: true, vpp: 1.0 } +# YM2203's PSG output stage seems to be a source follower, gm=3.95mS -> Rout=253 Ohm +# output is 1.2Vpp, rather than the AY's 1V +jt03_psg: { data_width: 10, unsigned: true, dcrm: true, vpp: 0.72, rout: 253 } +# jt007232: resistor DAC is external +jt007232: { data_width: 11, vpp: 1.0 } +jt007232_stereo: { data_width: 11, vpp: 1.0, stereo: true } +jt7759: { data_width: 9, vpp: 1.0 } + +# OKI compatible +# jt5205: 4, 6, 8kHz sampling rates +# vpp: 1 unloaded (0-5V), LM1558 opamp's Rin=0.3~1M Ohm (1MOhm typ) +# rout (100k) from data sheet +jt5205: { data_width: 12, vpp: 1.0, rout: 100k } +# jt6295: rout is a guess, should be confirmed +# vpp: 1.0 according to data sheet +# internal 12bit DAC, multiplexed for 4 channels, reduces +# gain by 4, equivalent to the extra 2 bits from jt6295's accumulator +jt6295: { data_width: 14, vpp: 1.0, rout: 100k } + +jt89: { data_width: 11, vpp: 0.66 } # vpp is a guess +vlm5030: { data_width: 10, vpp: 0.5, rout: 81.25 } +HUC6280: { data_width: 24, stereo: true } +# jt051649, vpp and rout are a guess, it uses an external DAC +# 051671 +jt051649: { data_width: 12, vpp: 0.5, rout: 100k } + +# Ricoh +# from S18, vpp is a guess assuming multiplexed DAC over 8 channels +jtpcm658: { data_width: 10, vpp: 0.125, stereo: true } + +# FM chips using Yamaha's DACs +# YM3012's output impedance is a guess +jt51: { data_width: 16, rout: 6.5k, vpp: 0.5, stereo: true } +jt053260: { data_width: 16, rout: 6.5k, vpp: 0.5, stereo: true } +jt054539: { data_width: 16, rout: 6.5k, vpp: 0.5, stereo: true } # Temptative values +ym3014: { data_width: 16, rout: 6.5k, vpp: 0.5 } +# FM chips connected to YM3014 DAC +jt03_fm: { data_width: 16, rout: 6.5k, vpp: 0.5 } # only FM, declare PSG part as jt03_psg +jtopl: { data_width: 16, rout: 6.5k, vpp: 0.5 } +jtopl2: { data_width: 16, rout: 6.5k, vpp: 0.5 } +jt2413: { data_width: 16, rout: 6.5k, vpp: 0.5 } +# FM chips with internal DAC +# jt12: is audio output rail to rail? Other YM DAC are 1/4VDD to 3/4 VDD +# the DAC is time multiplexed, so each channel maximum amplitude is 1/6 +# but jt12 uses 12 bits instead of 9, so it's already attenuating by 1/32 +# in order to compensate for it, 0.5*32/6=2.6 +jt12: { data_width: 16, rout: 6.5k, vpp: 2.6, stereo: true } + +# Namco +# data_width is probably too much, pre tries to compensate that a bit +# rout is a guess based on Pac-Mania schematics +# internal capacitance might not exist at all, and if it does it may be +# much lower than 0.4nF +# Pac-Mania schematics do not have a external filter for CUS30, but they +# have a very good filter for the crude PCM DACs. Is the output of CUS30 +# different from samples? Is it more like a wave table at high sampling rate? +# CUS30 goes into CUS99, which is the real DAC, should the module name here +# be CUS99 instead of CUS30? +jtcus30: { data_width: 13, rout: 47k, stereo: true, vpp: 2.0 } + +# SEGA +# place holder values +jtpcm568: { data_width: 10, rout: 100k, vpp: 1.0 } \ No newline at end of file diff --git a/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/sound/fir20k.hex b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/sound/fir20k.hex new file mode 100644 index 0000000000000000000000000000000000000000..49ed3e24318cc575175628c16aa9f4e64f808e3a --- /dev/null +++ b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/sound/fir20k.hex @@ -0,0 +1,512 @@ +000B +0000 +FFFF +0019 +FFFF +0022 +FFFF +0000 +0021 +FFFF +005B +FFFF +003E +0000 +FFFF +00A6 +FFFF +00D9 +FFFF +0000 +00B7 +FFFF +01D5 +FFFF +012C +0000 +FFFF +02FA +FFFF +03F5 +FFFF +0000 +03E8 +FFFF +0D5F +FFFF +1454 +6A9C +1454 +FFFF +0D5F +FFFF +03E8 +0000 +FFFF +03F5 +FFFF +02FA +FFFF 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0000000000000000000000000000000000000000..2ee73011b0afb1612f3b61b479acbb2ae1fa1848 --- /dev/null +++ b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/sound/fir2_69.hex @@ -0,0 +1,512 @@ +0013 +FFF1 +FFE7 +000F +0023 +FFF1 +FFCB +000E +004F +FFF9 +FF8E +FFF9 +009D +0022 +FF2F +FFB2 +010B +0090 +FEB6 +FF11 +018B +0173 +FE34 +FDD5 +020A +0331 +FDBF +FB46 +026F +0756 +FD6E +F2EB +02A8 +2892 +3D4F +2892 +02A8 +F2EB +FD6E +0756 +026F +FB46 +FDBF +0331 +020A +FDD5 +FE34 +0173 +018B +FF11 +FEB6 +0090 +010B +FFB2 +FF2F +0022 +009D +FFF9 +FF8E +FFF9 +004F +000E +FFCB +FFF1 +0023 +000F +FFE7 +FFF1 +0013 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 diff --git a/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/sound/fir_192k_13k.csv b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/sound/fir_192k_13k.csv new file mode 100644 index 0000000000000000000000000000000000000000..a56cdc965236c5d0ecab6012d444453d5a8b3f6a --- /dev/null +++ b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/sound/fir_192k_13k.csv @@ -0,0 +1,64 @@ +# Rectangular, 192kHz sampling rate, cutoff 13kHz, transition bandwidth 2800 +0.006193585795996958 +0.002143576670835962 +-0.002581061136253086 +-0.007166607957950215 +-0.010766898054846251 +-0.012650868699814201 +-0.012340044897941813 +-0.009711768274031134 +-0.005048330460843305 +0.000979942058971605 +0.007399320312808589 +0.013075587459209000 +0.016895655667288300 +0.017960812752822235 +0.015761018118809124 +0.010300885805819662 +0.002153948521701974 +-0.007568254229877957 +-0.017333184592923077 +-0.025378073500620879 +-0.029950168967431891 +-0.029563467817218067 +-0.023234889870750657 +-0.010664261711889418 +0.007670709347303303 +0.030521949479720263 +0.055984222066932765 +0.081702082398226725 +0.105144886627842410 +0.123913856017766333 +0.136039935528770806 +0.140231811083132041 +0.136039935528770806 +0.123913856017766333 +0.105144886627842410 +0.081702082398226725 +0.055984222066932765 +0.030521949479720263 +0.007670709347303303 +-0.010664261711889418 +-0.023234889870750657 +-0.029563467817218067 +-0.029950168967431891 +-0.025378073500620879 +-0.017333184592923077 +-0.007568254229877957 +0.002153948521701974 +0.010300885805819662 +0.015761018118809124 +0.017960812752822235 +0.016895655667288300 +0.013075587459209000 +0.007399320312808589 +0.000979942058971605 +-0.005048330460843305 +-0.009711768274031134 +-0.012340044897941813 +-0.012650868699814201 +-0.010766898054846251 +-0.007166607957950215 +-0.002581061136253086 +0.002143576670835962 +0.006193585795996958 diff --git a/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/sound/fir_192k_4k.csv b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/sound/fir_192k_4k.csv new file mode 100644 index 0000000000000000000000000000000000000000..3f92a51c26eacfb0f56160467d023dee2baf5faf --- /dev/null +++ b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/sound/fir_192k_4k.csv @@ -0,0 +1,64 @@ +# Hamming, 192kHz sampling rate, cutoff 4kHz, transition bandwidth 9600 +-0.000690371292048241 +-0.000654588615521039 +-0.000632926451727032 +-0.000608742288226165 +-0.000560512668004587 +-0.000462553136491582 +-0.000285997336862128 +0.000000000000000000 +0.000426883071923585 +0.001025194695803240 +0.001823019732286185 +0.002844440934133643 +0.004108077504583262 +0.005625775085483039 +0.007401511177699945 +0.009430572286831139 +0.011699048684168224 +0.014183680002694234 +0.016852070486730680 +0.019663277203784385 +0.022568758588404805 +0.025513655028047682 +0.028438358522693916 +0.031280315418657632 +0.033975995429890833 +0.036462952118422466 +0.038681895091040447 +0.040578692625830831 +0.042106225363912550 +0.043226017028054578 +0.043909576647523631 +0.044139398120559246 +0.043909576647523631 +0.043226017028054578 +0.042106225363912550 +0.040578692625830838 +0.038681895091040454 +0.036462952118422480 +0.033975995429890840 +0.031280315418657639 +0.028438358522693916 +0.025513655028047689 +0.022568758588404802 +0.019663277203784392 +0.016852070486730691 +0.014183680002694238 +0.011699048684168234 +0.009430572286831137 +0.007401511177699947 +0.005625775085483041 +0.004108077504583262 +0.002844440934133646 +0.001823019732286185 +0.001025194695803241 +0.000426883071923585 +0.000000000000000000 +-0.000285997336862128 +-0.000462553136491582 +-0.000560512668004587 +-0.000608742288226166 +-0.000632926451727033 +-0.000654588615521039 +-0.000690371292048241 \ No newline at end of file diff --git a/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/sound/fir_coeff.c b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/sound/fir_coeff.c new file mode 100644 index 0000000000000000000000000000000000000000..84fcfd317a233830c8c960f569c06aecca358631 --- /dev/null +++ b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/sound/fir_coeff.c @@ -0,0 +1,37 @@ +#include +#include + +int fill( char *fname, int*ram); + +int main(int argc, char *argv[]) { + int ram[512]; + char *fname_def = "filter"; + char *fname = argc>1 ? argv[1] : fname_def; + if( fill( fname, ram ) ) return 1; + for( int j=0; j<512; j++ ) + printf("%04X\n",ram[j]&0xffff); + return 0; +} + +int fill( char *fname, int*ram ) { + FILE *fin; + int j=0; + char buf[256]; + for( int k=0; k<512; k++ ) ram[k]=0; + fin = fopen( fname ,"r" ); + if( !fin ) { + printf("Cannot open file %s\n", fname ); + return 1; + } + do { + fgets( buf, 256, fin ); + }while( buf[0]=='#' ); + do{ + int n; + n = strtol(buf, NULL, 0); + ram[j++] = n; + fgets( buf, 256, fin ); + }while(!feof(fin) && j<256); + fclose(fin); + return 0; +} \ No newline at end of file diff --git a/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/sound/firjt49.hex b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/sound/firjt49.hex new file mode 100644 index 0000000000000000000000000000000000000000..b49e4780a25544ad119f37fb998908a5ca54578b --- /dev/null +++ b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/sound/firjt49.hex @@ -0,0 +1,512 @@ +FFF4 +FFF8 +FFFE +0004 +000B +0010 +0012 +0010 +000A +0001 +FFF5 +FFE9 +FFE0 +FFDD +FFE2 +FFF0 +0004 +001C +0032 +0040 +0041 +0033 +0015 +FFED +FFC2 +FF9E +FF8C +FF91 +FFB2 +FFEC +0033 +007A +00B0 +00C5 +00AE +006B +0004 +FF8D +FF1E +FED2 +FEC2 +FEFA +FF79 +002A +00EF +019B +0204 +0205 +018C +009F +FF5E +FE03 +FCD7 +FC29 +FC3F +FD48 +FF51 +0240 +05D2 +09A8 +0D4E +1050 +124B +12FB +124B +1050 +0D4E +09A8 +05D2 +0240 +FF51 +FD48 +FC3F +FC29 +FCD7 +FE03 +FF5E +009F +018C +0205 +0204 +019B +00EF +002A +FF79 +FEFA +FEC2 +FED2 +FF1E +FF8D +0004 +006B +00AE +00C5 +00B0 +007A +0033 +FFEC +FFB2 +FF91 +FF8C +FF9E +FFC2 +FFED +0015 +0033 +0041 +0040 +0032 +001C +0004 +FFF0 +FFE2 +FFDD +FFE0 +FFE9 +FFF5 +0001 +000A +0010 +0012 +0010 +000B +0004 +FFFE +FFF8 +FFF4 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 diff --git a/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/sound/firjt49.m b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/sound/firjt49.m new file mode 100644 index 0000000000000000000000000000000000000000..306e1bfb6271d30b8de90f45e2d408f0b4a29c72 --- /dev/null +++ b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/sound/firjt49.m @@ -0,0 +1,15 @@ +# FIR +pkg load signal + +Fs=1.5e6/16; +f1=14000/Fs; +f2=20000/Fs; +N=127 +hc=round(fir1(N-1,f1,'low')*2^15); +printf("Stopband attenuation %d dB\n", N*22*(f2-f1)) +hc_fft=abs(fft(hc)); +hdb=20*log10(hc_fft); +haux=hc'; +save firjt49 haux +printf("Gain at DC %d dB = %d \n", hdb(1), hc_fft(1)) +# use freqz(hc) to display the frequency response \ No newline at end of file diff --git a/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/sound/hifi_1bit_dac.v b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/sound/hifi_1bit_dac.v new file mode 100644 index 0000000000000000000000000000000000000000..88268f4cc387d6005d2a189c088aa7a965bb9b46 --- /dev/null +++ b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/sound/hifi_1bit_dac.v @@ -0,0 +1,101 @@ +// Sent by Frederic REQUIN, thanks! + +// This module is a third order delta/sigma modulator +// It uses no multiply only shifts by 1, 2 or 13 +// There are only 7 adders used, it takes around 110 LUTs +module hifi_1bit_dac +( + input reset, + input clk, + input clk_ena, + input [19:0] pcm_in, + output reg dac_out +); + +wire [23:0] w_data_in_p0; +wire [23:0] w_data_err_p0; +wire [23:0] w_data_int_p0; +reg [23:0] r_data_fwd_p1; +wire [23:0] w_data_fb1_p1; +wire [23:0] w_data_fb2_p1; +wire [23:0] w_data_lpf_p1; +reg [23:0] r_data_lpf_p2; +wire [23:0] w_data_fb3_p1; +wire [23:0] w_data_int_p1; +reg [23:0] r_data_fwd_p2; +wire [23:0] w_data_qt_p2; + +// ====================================== +// ============== Stage #1 ============== +// ====================================== + +// PCM input extended to 24 bits +assign w_data_in_p0 = { {4{pcm_in[19]}}, pcm_in }; + +// Error between the input and the quantizer output +assign w_data_err_p0 = w_data_in_p0 - w_data_qt_p2; + +// First integrator adder +assign w_data_int_p0 = { {3{w_data_err_p0[23]}}, w_data_err_p0[22:2] } // Divide by 4 + + r_data_fwd_p1; + +// First integrator forward delay +always @(posedge reset or posedge clk) + if (reset) + r_data_fwd_p1 <= 24'd0; + else if (clk_ena) + r_data_fwd_p1 <= w_data_int_p0; + +// ====================================== +// ============== Stage #2 ============== +// ====================================== + +// Feedback from the quantizer output +assign w_data_fb1_p1 = { {3{r_data_fwd_p1[23]}}, r_data_fwd_p1[22:2] } // Divide by 4 + - { {3{w_data_qt_p2[23]}}, w_data_qt_p2[22:2] }; // Divide by 4 + +// Feedback from the third stage +assign w_data_fb2_p1 = w_data_fb1_p1 + - { {14{r_data_fwd_p2[23]}}, r_data_fwd_p2[22:13] }; // Divide by 8192 + +// Low pass filter +assign w_data_lpf_p1 = w_data_fb2_p1 + r_data_lpf_p2; + +// Low pass filter feedback delay +always @(posedge reset or posedge clk) + if (reset) + r_data_lpf_p2 <= 24'd0; + else if (clk_ena) + r_data_lpf_p2 <= w_data_lpf_p1; + +// ====================================== +// ============== Stage #3 ============== +// ====================================== + +// Feedback from the quantizer output +assign w_data_fb3_p1 = { {2{w_data_lpf_p1[23]}}, w_data_lpf_p1[22:1] } // Divide by 2 + - { {2{w_data_qt_p2[23]}}, w_data_qt_p2[22:1] }; // Divide by 2 + +// Second integrator adder +assign w_data_int_p1 = w_data_fb3_p1 + r_data_fwd_p2; + +// Second integrator forward delay +always @(posedge reset or posedge clk) + if (reset) + r_data_fwd_p2 <= 24'd0; + else if (clk_ena) + r_data_fwd_p2 <= w_data_int_p1; + +// ===================================== +// ========== 1-bit quantizer ========== +// ===================================== + +assign w_data_qt_p2 = (r_data_fwd_p2[23]) ? 24'hF00000 : 24'h100000; + +always @(posedge reset or posedge clk) + if (reset) + dac_out <= 1'b0; + else if (clk_ena) + dac_out <= ~r_data_fwd_p2[23]; + +endmodule diff --git a/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/sound/hybrid_pwm_sd.v b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/sound/hybrid_pwm_sd.v new file mode 100644 index 0000000000000000000000000000000000000000..ec1d7ebdc5539e1460e97dfcd70ff6000c6e137d --- /dev/null +++ b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/sound/hybrid_pwm_sd.v @@ -0,0 +1,45 @@ +// Hybrid PWM / Sigma Delta converter +// +// Uses 5-bit PWM, wrapped within a 10-bit Sigma Delta, with the intention of +// increasing the pulse width, since narrower pulses seem to equate to more noise + +module hybrid_pwm_sd +( + input clk, + input clk_ena, + input reset, + input [15:0] pcm_in, + output dac_out +); + +reg [4:0] pwmcounter; +reg [4:0] pwmthreshold; +reg [33:0] scaledin; +reg [15:0] sigma; +reg out; + +assign dac_out=out; + +always @(posedge clk, posedge reset) begin + if(reset) begin + sigma<=16'b00000100_00000000; + pwmthreshold<=5'b10000; + end else if(clk_ena) begin + pwmcounter<=pwmcounter+1'b1; + + if(pwmcounter==pwmthreshold) + out<=1'b0; + + if(pwmcounter==5'b11111) // Update threshold when pwmcounter reaches zero + begin + // Pick a new PWM threshold using a Sigma Delta + scaledin<=33'd134217728 // (1<<(16-5))<<16, offset to keep centre aligned. + +({1'b0,pcm_in}*61440); // 30<<(16-5)-1; + sigma<=scaledin[31:16]+{4'b0,sigma[10:0]}; // Will use previous iteration's scaledin value + pwmthreshold<=sigma[15:11]; // Will lag 2 cycles behind, but shouldn't matter. + out<=1'b1; + end + end +end + +endmodule diff --git a/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/sound/jtframe_dcrm.v b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/sound/jtframe_dcrm.v new file mode 100644 index 0000000000000000000000000000000000000000..87874529d7900c2cfb9a31d329d2fa05adfa5a79 --- /dev/null +++ b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/sound/jtframe_dcrm.v @@ -0,0 +1,75 @@ +/* This file is part of JTFRAME. + + JTFRAME is free software: you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation, either version 3 of the License, or + (at your option) any later version. + + JTFRAME is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with JTFRAME. If not, see . + + Author: Jose Tejada Gomez. Twitter: @topapate + Version: 1.0 + Date: 25-11-2020 + + */ + +// This is pretty much a copy of jt49_dcrm2 +// DC removal filter +// input is unsigned +// output is signed + +/* verilator tracing_off */ +module jtframe_dcrm #(parameter + SW = 8, + SIGNED_INPUT = 0 +)( + input rst, + input clk, + input sample, + input [SW-1:0] din, + output reg signed [SW-1:0] dout +); + +localparam DW=10; // width of the decimal portion + +reg signed [SW+DW:0] integ, exact, error; +reg signed [SW :0] pre_dout, q; +reg samplel; + +always @(*) begin + exact = integ+error; + q = exact[SW+DW:DW]; + pre_dout = { SIGNED_INPUT ? din[SW-1] : 1'b0, din } - q; +end + +always @(posedge clk) begin + dout <= pre_dout[SW-1:0]; +end + +always @(posedge clk) begin + if( rst ) begin + samplel <= 0; + end else begin + samplel <= sample; + end +end + +always @(posedge clk, posedge rst) begin + if( rst ) begin + integ <= {SW+DW+1{1'b0}}; + error <= {SW+DW+1{1'b0}}; + end else if( sample & ~samplel ) begin + /* verilator lint_off WIDTH */ + integ <= integ + pre_dout; + /* verilator lint_on WIDTH */ + error <= exact-{q, {DW{1'b0}}}; + end +end + +endmodule \ No newline at end of file diff --git a/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/sound/jtframe_fir.v b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/sound/jtframe_fir.v new file mode 100644 index 0000000000000000000000000000000000000000..29b11a91881e1fd200a31739a629306c3ca6834c --- /dev/null +++ b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/sound/jtframe_fir.v @@ -0,0 +1,119 @@ +/* This file is part of JTFRAME. + + + JTFRAME program is free software: you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation, either version 3 of the License, or + (at your option) any later version. + + JTFRAME program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with JTFRAME. If not, see . + + Author: Jose Tejada Gomez. Twitter: @topapate + Version: 1.0 + Date: 22-11-2020 + +*/ + +// Generic FIR filter for stereo signals +// Max 127 coefficients + +// Parameters +// KMAX = number of coefficients (8 bit value) +// COEFFS = hex file with filter coefficients + +module jtframe_fir( + input rst, + input clk, + input sample, + input signed [15:0] l_in, + input signed [15:0] r_in, + output reg signed [15:0] l_out, + output reg signed [15:0] r_out +); + +parameter [7:0] KMAX = 8'd68; +parameter COEFFS = "filter.hex"; + +reg signed [15:0] ram[0:511]; // dual port RAM +reg [6:0] pt_wr, pt_rd; +reg [7:0] cnt; +reg st; +reg signed [35:0] acc_l, acc_r; +reg signed [15:0] coeff; +reg signed [31:0] p_l, p_r; +wire [ 8:0] ram_idx, ptr_l, ptr_r; // using a wire prevents a false warning from Quartus + +assign ram_idx = {2'd0, cnt[6:0]}; +assign ptr_l = {2'd1, pt_rd }; +assign ptr_r = {2'd2, pt_rd }; + +function signed [35:0] ext; + input signed [31:0] p; + ext = { {4{p[31]}}, p }; +endfunction + +function [6:0] loop_inc; + input [6:0] s; + loop_inc = s == KMAX[6:0]-7'd1 ? 7'd0 : s+7'd1; +endfunction + +function signed [15:0] sat; + input [35:0] a; + sat = a[35:32] == {4{a[31]}} ? a[31:16] : { a[35], {15{~a[35]}} }; +endfunction + +always@(posedge clk, posedge rst) begin + if( rst ) begin + l_out <= 0; + r_out <= 0; + pt_rd <= 0; + pt_wr <= 0; + cnt <= 0; + acc_l <= 0; + acc_r <= 0; + p_l <= 0; + p_r <= 0; + end else begin + if( sample ) begin + pt_rd <= pt_wr; + cnt <= 0; + ram[ { 2'd1, pt_wr } ] <= l_in; + ram[ { 2'd2, pt_wr } ] <= r_in; + pt_wr <= loop_inc( pt_wr ); + acc_l <= 0; + acc_r <= 0; + p_l <= 0; + p_r <= 0; + st <= 0; + end else begin + if( cnt < KMAX ) begin + st <= ~st; + if( st == 0 ) begin + coeff <= ram[ ram_idx ]; + end else begin + p_l <= ram[ ptr_l ] * coeff; + p_r <= ram[ ptr_r ] * coeff; + acc_l <= acc_l + ext(p_l); + acc_r <= acc_r + ext(p_r); + cnt <= cnt+8'd1; + pt_rd <= loop_inc( pt_rd ); + end + end else begin + l_out <= sat(acc_l); + r_out <= sat(acc_r); + end + end + end +end + +initial begin + $readmemh( COEFFS, ram ); +end +endmodule + diff --git a/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/sound/jtframe_fir2.m b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/sound/jtframe_fir2.m new file mode 100644 index 0000000000000000000000000000000000000000..5a27fa1047c636bfefa8b5c8fb6cbd289ca08395 --- /dev/null +++ b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/sound/jtframe_fir2.m @@ -0,0 +1,15 @@ +# FIR +pkg load signal + +f1=0.48; +f2=0.52; +N=127 +hc=round(fir1(N-1,f1,'low')*2^15); +printf("Stopband attenuation %d dB\n", N*22*(f2-f1)) +hc_fft=abs(fft(hc)); +hdb=20*log10(hc_fft); +haux=hc'; +save filter2 haux +printf("Gain at DC %d dB = %d. Reject at f2 = %.0f dB. BW=%.3f\n", hdb(1), hc_fft(1), hdb(round(N*f2))-hdb(1), bw ) +printf("Group delay=%d\n", grpdelay(hc)(10)) +# use freqz(hc) to display the frequency response \ No newline at end of file diff --git a/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/sound/jtframe_fir2.v b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/sound/jtframe_fir2.v new file mode 100644 index 0000000000000000000000000000000000000000..9f360476aeef5d4c08d3255b60fbde6b325f1c17 --- /dev/null +++ b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/sound/jtframe_fir2.v @@ -0,0 +1,101 @@ +/* This file is part of JTFRAME. + + + JTFRAME program is free software: you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation, either version 3 of the License, or + (at your option) any later version. + + JTFRAME program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with JTFRAME. If not, see . + + Author: Jose Tejada Gomez. Twitter: @topapate + Version: 1.0 + Date: 22-11-2020 + +*/ + +module jtframe_fir2( + input rst, + input clk, + input sample, + input signed [15:0] l_in, + input signed [15:0] r_in, + output reg signed [15:0] l_out, + output reg signed [15:0] r_out +); + +parameter [7:0] KMAX = 8'd68; + +reg signed [15:0] ram[0:511]; // dual port RAM +reg [6:0] pt_wr, pt_rd, cnt; +reg st; +reg signed [35:0] acc_l, acc_r; +reg signed [15:0] coeff; +reg signed [31:0] p_l, p_r; + +function signed [35:0] ext; + input signed [31:0] p; + ext = { {4{p[31]}}, p }; +endfunction + +function [6:0] loop_inc; + input [6:0] s; + loop_inc = s == KMAX ? 8'd0 : s+8'd1; +endfunction + +function signed [15:0] sat; + input [35:0] a; + sat = a[35:30] == {6{a[29]}} ? a[29:14] : { a[35], {15{~a[35]}} }; +endfunction + +always@(posedge clk, posedge rst) begin + if( rst ) begin + l_out <= 16'd0; + r_out <= 16'd0; + pt_rd <= 8'd0; + pt_wr <= 8'd0; + cnt <= 8'd0; + end else begin + if( sample ) begin + pt_rd <= pt_wr; + cnt <= KMAX; + ram[ { 2'd1, pt_wr } ] <= l_in; + ram[ { 2'd2, pt_wr } ] <= r_in; + pt_wr <= loop_inc( pt_wr ); + acc_l <= 36'd0; + acc_r <= 36'd0; + p_l <= 32'd0; + p_r <= 32'd0; + st <= 0; + end else begin + if( cnt != 8'd0 ) begin + st <= ~st; + if( st == 0 ) begin + coeff <= ram[ {2'd0, cnt } ]; + end else begin + p_l <= ram[ {2'd1, pt_rd } ] * coeff; + p_r <= ram[ {2'd2, pt_rd } ] * coeff; + acc_l <= acc_l + ext(p_l); + acc_r <= acc_r + ext(p_r); + cnt <= cnt-8'd1; + pt_rd <= loop_inc( pt_rd ); + end + end else begin + l_out <= sat(acc_l); + r_out <= sat(acc_r); + end + end + end +end + +initial begin + $readmemh( "fir2_69.hex", ram ); +end +endmodule + diff --git a/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/sound/jtframe_fir3.m b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/sound/jtframe_fir3.m new file mode 100644 index 0000000000000000000000000000000000000000..499bace80018dec56df5e731b20f42c381b1fc19 --- /dev/null +++ b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/sound/jtframe_fir3.m @@ -0,0 +1,10 @@ +# FIR +pkg load signal + +f1=0.31; +f2=0.34; +N=127 +hc=round(fir1(N-1,f1,'low')*2^15); +printf("Stopband attenuation %d dB\n", N*22*(f2-f1)) +haux=hc'; +save filter3 haux \ No newline at end of file diff --git a/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/sound/jtframe_fir4.m b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/sound/jtframe_fir4.m new file mode 100644 index 0000000000000000000000000000000000000000..d8128021725672a702c86118e064d15a93260679 --- /dev/null +++ b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/sound/jtframe_fir4.m @@ -0,0 +1,23 @@ +# FIR +pkg load signal + +f1=0.24; +f2=0.25; +N=69 +hc=round(fir1(N-1,f1,'low')*(2^15-1)); +hc_fft=abs(fft(hc)); +hdb=20*log10(hc_fft); +haux=hc'; +save filter4 haux +bw=0; +for i=1:N + if hdb(i) < hdb(1)-3 + bw=(i-1)/N*2; + break + endif +endfor +printf("Gain at DC %d dB = %d. Reject at f2 = %.0f dB. BW=%.3f\n", hdb(1), hc_fft(1), hdb(round(N*f2))-hdb(1), bw ) +printf("Group delay=%d\n", grpdelay(hc)(10)) +printf("Delay =%d ms (Fs=26000)\n", grpdelay(hc)(10)/26) +# use freqz(hc) to display the frequency response +freqz(hc) \ No newline at end of file diff --git a/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/sound/jtframe_fir_mono.v b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/sound/jtframe_fir_mono.v new file mode 100644 index 0000000000000000000000000000000000000000..1bad674c31120cfa8fe25f7aee86c478da60e58f --- /dev/null +++ b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/sound/jtframe_fir_mono.v @@ -0,0 +1,128 @@ +/* This file is part of JTFRAME. + + + JTFRAME program is free software: you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation, either version 3 of the License, or + (at your option) any later version. + + JTFRAME program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with JTFRAME. If not, see . + + Author: Jose Tejada Gomez. Twitter: @topapate + Version: 1.0 + Date: 12-1-2021 + +*/ + +// Generic FIR filter for mono signals +// Max 255 coefficients + +// Parameters +// KMAX = number of coefficients (8 bit value) +// COEFFS = hex file with filter coefficients + +module jtframe_fir_mono( + input rst, + input clk, + input sample, + input signed [15:0] din, + output reg signed [15:0] dout +); + +parameter [7:0] KMAX = 8'd68; +parameter COEFFS = "filter.hex"; + +reg [ 7:0] pt_wr, pt_rd, cnt; +reg [ 8:0] rd_addr; +reg st, wt_ram; +reg signed [35:0] acc; +reg signed [15:0] coeff; +reg signed [31:0] p; +wire signed [15:0] ram_dout; + +function signed [35:0] ext; + input signed [31:0] p; + ext = { {4{p[31]}}, p }; +endfunction + +function [7:0] loop_inc; + input [7:0] s; + loop_inc = s == KMAX-8'd1 ? 8'd0 : s+8'd1; +endfunction + +function signed [15:0] sat; + input [35:0] a; + sat = a[35:30] == {6{a[29]}} ? a[29:14] : { a[35], {15{~a[35]}} }; +endfunction + +always @(*) begin + rd_addr = st==0 ? {1'd0, cnt} : {1'd1, pt_rd}; +end + +// dual port RAM +// the first half contains the coefficients +// the second half, contains the signal + +jtframe_dual_ram #(.DW(16), .AW(9), .SYNFILE(COEFFS)) u_ram( + .clk0 ( clk ), + .clk1 ( clk ), + // Port 0: write + .data0 ( din ), + .addr0 ( {1'd1, pt_wr} ), + .we0 ( sample ), + .q0 ( ), + // Port 1: read + .data1 ( 16'd0 ), + .addr1 ( rd_addr ), + .we1 ( 1'd0 ), + .q1 ( ram_dout ) +); + +always@(posedge clk, posedge rst) begin + if( rst ) begin + dout <= 16'd0; + pt_rd <= 8'd0; + pt_wr <= 8'd0; + cnt <= 8'd0; + acc <= 36'd0; + p <= 32'd0; + coeff <= 16'd0; + end else begin + if( sample ) begin + pt_rd <= pt_wr; + cnt <= 0; + // ram[ { 1'd1, pt_wr } ] <= din; + pt_wr <= loop_inc( pt_wr ); + acc <= 36'd0; + p <= 32'd0; + st <= 0; + wt_ram<= 1; + end else begin + wt_ram <= ~wt_ram; + if( !wt_ram ) begin + if( cnt < KMAX ) begin + st <= ~st; + if( st == 0 ) begin + coeff <= ram_dout; + end else begin + p <= ram_dout * coeff; + acc <= acc + ext(p); + cnt <= cnt+7'd1; + pt_rd <= loop_inc( pt_rd ); + end + end else begin + dout <= sat(acc); + end + end + end + end +end + +endmodule + diff --git a/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/sound/jtframe_gainmux.v b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/sound/jtframe_gainmux.v new file mode 100644 index 0000000000000000000000000000000000000000..9d1402310a7576511217ac3becc56fd1b9ded8ab --- /dev/null +++ b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/sound/jtframe_gainmux.v @@ -0,0 +1,45 @@ +/* This file is part of JTFRAME. + + JTFRAME program is free software: you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation, either version 3 of the License, or + (at your option) any later version. + + JTFRAME program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with JTFRAME. If not, see . + + Author: Jose Tejada Gomez. Twitter: @topapate + Version: 1.0 + Date: 10-1-2025 +*/ + +module jtframe_gainmux( + input clk, + input [2:0] sel, + output reg [7:0] g0,g1,g2,g3,g4,g5 +); + +parameter CH=6; // do not change when instantiating +// gains for each sel code, all channels appear concatenated +parameter [CH*8-1:0] GAME0=0,GAME1=0,GAME2=0,GAME3=0, + GAME4=0,GAME5=0,GAME6=0,GAME7=0; + +always @(posedge clk) begin + case(sel) + 0: {g5,g4,g3,g2,g1,g0} <= GAME0; + 1: {g5,g4,g3,g2,g1,g0} <= GAME1; + 2: {g5,g4,g3,g2,g1,g0} <= GAME2; + 3: {g5,g4,g3,g2,g1,g0} <= GAME3; + 4: {g5,g4,g3,g2,g1,g0} <= GAME4; + 5: {g5,g4,g3,g2,g1,g0} <= GAME5; + 6: {g5,g4,g3,g2,g1,g0} <= GAME6; + 7: {g5,g4,g3,g2,g1,g0} <= GAME7; + endcase +end + +endmodule \ No newline at end of file diff --git a/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/sound/jtframe_hipass.v b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/sound/jtframe_hipass.v new file mode 100644 index 0000000000000000000000000000000000000000..4ff15e11ee9722806cc13a5175eae3f9415e7a4d --- /dev/null +++ b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/sound/jtframe_hipass.v @@ -0,0 +1,76 @@ +/* This file is part of JTFRAME. + + + JTFRAME program is free software: you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation, either version 3 of the License, or + (at your option) any later version. + + JTFRAME program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with JTFRAME. If not, see . + + Author: Jose Tejada Gomez. Twitter: @topapate + Version: 1.0 + Date: 13-1-2021 + +*/ + +// First order high-pass IIR filter +// y[k] = b * (x[k]-x[k-1]) - a * y[k-1] +// +// Ωc=tan(pi*fc/fs) +// b=1/(1+Ωc), a=abs((Ωc-1)/(Ωc+1)) +// fc = cut-off frequency, fs = sampling frequency + +module jtframe_hipass #(parameter + WS=16, // Assuming that the signal is fixed point + WA=WS/2 // WA is only the decimal part +)( + input rst, + input clk, + input sample, // cannot be a fixed 1 + input signed [WS-1:0] sin, + input [WA-1:0] a, // denominator coefficient, unsigned + input [WA-1:0] b, // numerator coefficient, unsigned + output reg signed [WS-1:0] sout +); + +reg signed [WS-1:0] factor, prod_l, fmux, sin_l, delta; +reg signed [WS :0] diff, sum; + +wire signed [ WS-1:0] aext = { {WS-WA{1'b0}}, a }; +wire signed [ WS-1:0] bext = { {WS-WA{1'b0}}, b }; +reg signed [ 2*WS-1:0] prod; +reg v, v2; + +always @(*) begin + diff = {sin[WS-1],sin}-{sin_l[WS-1],sin_l}; + v = diff[WS]!=diff[WS-1]; + delta = v ? {diff[WS],{WS-1{~diff[WS]}}} : diff[WS-1:0]; // prevent overflow + factor = sample ? bext : aext; + fmux = sample ? delta : sout; + prod = factor * fmux; + sum = {prod[WS+WA-1],prod[WS+WA-1:WA]}+{prod_l[WS-1],prod_l}; + v2 = sum[WS]!=sum[WS-1]; +end + +always @(posedge clk) begin + if( rst ) begin + sout <= 0; + prod_l <= 0; + end else begin + if(sample) begin + sin_l <= sin; + sout <= v2 ? {sum[WS],{WS-1{~sum[WS]}}} : sum[WS-1:0]; + end else begin // calculate (1-a)*y[k-1] + prod_l <= prod[WS+WA-1:WA]; + end + end +end + +endmodule \ No newline at end of file diff --git a/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/sound/jtframe_iir2.v b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/sound/jtframe_iir2.v new file mode 100644 index 0000000000000000000000000000000000000000..ea3f32bb707c9dd716f47fa95e1383a31d4099c1 --- /dev/null +++ b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/sound/jtframe_iir2.v @@ -0,0 +1,66 @@ +/* This file is part of JTFRAME. + + + JTFRAME program is free software: you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation, either version 3 of the License, or + (at your option) any later version. + + JTFRAME program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with JTFRAME. If not, see . + + Author: Jose Tejada Gomez. Twitter: @topapate + Version: 1.0 + Date: 13-1-2021 + +*/ + +// Second order IIR filter +module jtframe_iir2 #(parameter + WS=14, + G = 4 // Gain = 2^G, G>0 needed for unity gain depending on + // coefficient scaling +)( + input rst, + input clk, + input sample, + input signed [WS-1:0] sin, + input signed [WS-1:0] b0,b1,b2,a1,a2, // coefficients (a0=1) + output signed [WS-1:0] sout +); + +reg signed [WS-1:0] x1, x2, y0, y1, y2; // previous signals +wire signed [WS-1:0] x0; +reg signed [WS*2-1:0] xb0,xb1,xb2,ya1,ya2; +wire signed [WS*2-1:0] sum; + +assign x0 = sin; +assign sout= sum[(WS*2-1-G)-:WS]; +assign sum = xb0+xb1+xb2-ya1-ya2; + +always @(posedge clk, posedge rst) begin + if( rst ) begin + end else begin + if(sample) begin + x2 <= x1; + x1 <= x0; + y2 <= y1; + y1 <= y0; + // y0 <= ^sum[WC*2+3:WC*2-1] ? { sum[WC*2+3], {WC-1{~sum[WC*2+3]}}} : sum[(WC*2-1)-:WC]; + y0 <= sum[WS+:WS]; + end else begin + xb0 <= x0*b0; + xb1 <= x1*b1; + xb2 <= x2*b2; + ya1 <= y1*a1; + ya2 <= y2*a2; + end + end +end + +endmodule \ No newline at end of file diff --git a/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/sound/jtframe_jt49_filters.v b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/sound/jtframe_jt49_filters.v new file mode 100644 index 0000000000000000000000000000000000000000..2c16c35f3fe008a699167e981bea1dd539c0261e --- /dev/null +++ b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/sound/jtframe_jt49_filters.v @@ -0,0 +1,64 @@ +/* This file is part of JTFRAME. + + + JTFRAME program is free software: you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation, either version 3 of the License, or + (at your option) any later version. + + JTFRAME program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with JTFRAME. If not, see . + + Author: Jose Tejada Gomez. Twitter: @topapate + Version: 1.0 + Date: 25-11-2020 + +*/ + +module jtframe_jt49_filters( + input rst, + input clk, + input [ 9:0] din0, + input [ 9:0] din1, + input sample, + output signed [15:0] dout +); + +localparam W=11,WD=16-W; + +wire signed [W-1:0] dcrm_snd; +reg [W-1:0] base_snd; +wire signed [ 15:0] dcrm16 = { dcrm_snd, dcrm_snd[W-2:W-WD-1] }; + +always @(posedge clk, posedge rst ) begin + if( rst ) begin + base_snd <= {W{1'd0}}; + end else if(sample) begin + base_snd <= { {W-10{1'b0}}, din0} + { {W-10{1'b0}}, din1}; + end +end + +jtframe_dcrm #(.SW(W)) u_dcrm( + .rst ( rst ), + .clk ( clk ), + .sample ( sample ), + .din ( base_snd ), + .dout ( dcrm_snd ) +); + +jtframe_fir #(.KMAX(126),.COEFFS("firjt49.hex")) u_fir( + .rst ( rst ), + .clk ( clk ), + .sample ( sample ), + .l_in ( dcrm16 ), + .r_in ( 16'd0 ), + .l_out ( dout ), + .r_out ( ) +); + +endmodule \ No newline at end of file diff --git a/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/sound/jtframe_limmul.v b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/sound/jtframe_limmul.v new file mode 100644 index 0000000000000000000000000000000000000000..5e310489a371967235ddf78435bf9c63cc70273e --- /dev/null +++ b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/sound/jtframe_limmul.v @@ -0,0 +1,63 @@ +/* This file is part of JTFRAME. + + + JTFRAME program is free software: you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation, either version 3 of the License, or + (at your option) any later version. + + JTFRAME program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with JTFRAME. If not, see . + + Author: Jose Tejada Gomez. Twitter: @topapate + Version: 1.0 + Date: 8-5-2024 + +*/ + +// Limiting multiplier of signed input by an unsigned gain +// the gain is taken as fixed point +// if the result does not fit in W bits +// peak is set and the output is clipped +module jtframe_limmul #(parameter + WI = 16, + WO = WI, + WD = 7 // decimal part of the gain input (1.7=8 bits) +)( + input rst, + input clk, + input cen, + input signed [WI-1:0] sin, + input [ 7:0] gain, + input peaked, + + output reg signed [WO-1:0] mul, + output reg peak +); + +localparam FW=WI+9, MSB=FW-1-(10-WD); + +wire signed [FW-1:0] full; +wire signed [ 8:0] sgain; +wire [FW-1:MSB] signs = full[FW-1:MSB]; +wire v = |signs & ~&signs; // overflow + +assign sgain = {1'b0,gain}; +assign full = sin * sgain; + +always @(posedge clk, posedge rst) begin + if( rst ) begin + mul <= 0; + peak <= 0; + end else if(cen) begin + peak <= v | peaked; + mul <= v ? {full[FW-1],{WO-1{~full[FW-1]}}} : full[MSB-:WO]; + end +end + +endmodule \ No newline at end of file diff --git a/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/sound/jtframe_limsum.v b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/sound/jtframe_limsum.v new file mode 100644 index 0000000000000000000000000000000000000000..af04a7e7cf2930ef2b6ff1811b1789fc69ff477f --- /dev/null +++ b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/sound/jtframe_limsum.v @@ -0,0 +1,64 @@ +/* This file is part of JTFRAME. + + + JTFRAME program is free software: you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation, either version 3 of the License, or + (at your option) any later version. + + JTFRAME program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with JTFRAME. If not, see . + + Author: Jose Tejada Gomez. Twitter: @topapate + Version: 1.0 + Date: 8-3-2024 + +*/ + +// Limiting summer of signed inputs of equal bit width +// the output will be clipped (limited) if the sum does not fit in W bits +// peak is set when the output is clipped +module jtframe_limsum #(parameter + WI = 16, + WO = WI, + K = 5 // number of input signals +)( + input rst, + input clk, + input cen, + input [WI*K-1:0] parts, + input [K-1:0] en, + output reg signed [WO-1:0] sum, + output reg peak +); + +localparam WS = WI+$clog2(K)+1; +reg signed [WS-1:0] full; +wire [WS-WO:0] signs = full[WS-1:WO-1]; +wire v = |signs & ~&signs; // overflow + +function [WS-1:0] ext(input en, input [WI-1:0] a); + ext = en ? { {WS-WI{a[WI-1]}}, a } : {WS{1'b0}}; +endfunction + +integer k; +always @* begin + for(k=0;k. + + Author: Jose Tejada Gomez. Twitter: @topapate + Version: 1.0 + Date: 20-12-2019 + +*/ + +// Generic mixer: improves on the jt12_mixer in JT12 repository + +// Usage: +// Specify width of input signals and desired outputs +// Select gain for each signal + +module jtframe_mixer #(parameter W0=16,W1=16,W2=16,W3=16,WOUT=16)( + input rst, + input clk, + input cen, + // input signals + input signed [W0-1:0] ch0, + input signed [W1-1:0] ch1, + input signed [W2-1:0] ch2, + input signed [W3-1:0] ch3, + // gain for each channel in 4.4 fixed point format + input [7:0] gain0, + input [7:0] gain1, + input [7:0] gain2, + input [7:0] gain3, + output signed [WOUT-1:0] mixed, + output peak // overflow signal (time enlarged) +); + +localparam WM = 16, + WD = 4, // decimal part + WA = WM+8, // width for the amplification + WS = WA+2, // width for the sum + WI = WS-WD; // width of the integer part of the sum +localparam signed [WM+3:0] MAXPOS = { 5'b0, {WM-1{1'b1}}}; +localparam signed [WM+3:0] MAXNEG = { ~5'b0, {WM-1{1'b0}}}; + + +`ifdef SIMULATION +initial begin + if( WOUTWM || W1 > WM || W2>WM || W3>WM || WOUT>WM ) begin + $display("ERROR: %m parameters cannot be larger than %d bits",WM); + $finish; + end +end +`endif + +reg signed [WA-1:0] ch0_pre, ch1_pre, ch2_pre, ch3_pre; +reg signed [WS-1:0] pre_sum; // 4 extra bits for overflow guard +reg signed [WM-1:0] sum; +reg signed [WI-1:0] pre_int; // no fractional part +wire ov_pos, ov_neg; + +// rescale to WM +wire signed [WM-1:0] scaled0 = { ch0, {WM-W0{1'b0}} }; +wire signed [WM-1:0] scaled1 = { ch1, {WM-W1{1'b0}} }; +wire signed [WM-1:0] scaled2 = { ch2, {WM-W2{1'b0}} }; +wire signed [WM-1:0] scaled3 = { ch3, {WM-W3{1'b0}} }; + + +wire signed [8:0] + g0 = {1'b0, gain0}, + g1 = {1'b0, gain1}, + g2 = {1'b0, gain2}, + g3 = {1'b0, gain3}; + +always @(posedge clk) begin + ch0_pre <= g0 * scaled0; + ch1_pre <= g1 * scaled1; + ch2_pre <= g2 * scaled2; + ch3_pre <= g3 * scaled3; + pre_sum <= ext(ch0_pre) + ext(ch1_pre) + ext(ch2_pre) + ext(ch3_pre); +end + +assign mixed = sum[WM-1:WM-WOUT]; + +assign peak = pre_int[WI-1:WM] != {WI-WM{pre_int[WM-1]}}; +assign ov_pos = peak && !pre_int[WI-1]; +assign ov_neg = peak && pre_int[WI-1]; + +function [WS-1:0] ext; + input [WA-1:0] a; + ext = { {WS-WA{a[WA-1]}}, a }; +endfunction + +always @(*) begin + pre_int = pre_sum[WS-1:WD]; +end + +// Apply gain +always @(posedge clk) if(cen) begin + if( rst ) begin // synchronous + sum <= sum>>>1; + end else begin + sum <= ov_pos ? MAXPOS[WM-1:0] : ( + ov_neg ? MAXNEG[WM-1:0] : pre_int[WM-1:0] ); + end +end + +endmodule // jtframe_mixer + +module jtframe_limamp #(parameter WIN=16,WOUT=16)( + input rst, + input clk, + input cen, + // input signals + input signed [WIN-1:0] sndin, + // gain for each channel in 4.4 fixed point format + input [7:0] gain, + output signed [WOUT-1:0] sndout, + output peak +); + +jtframe_mixer #(.W0(WIN),.WOUT(WOUT)) u_amp( + .rst ( rst ), + .clk ( clk ), + .cen ( cen ), + .ch0 ( sndin ), + .ch1 ( 16'd0 ), + .ch2 ( 16'd0 ), + .ch3 ( 16'd0 ), + .gain0 ( gain ), + .gain1 ( 8'h0 ), + .gain2 ( 8'h0 ), + .gain3 ( 8'h0 ), + .mixed ( sndout ), + .peak ( peak ) +); + +endmodule \ No newline at end of file diff --git a/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/sound/jtframe_mixer_en.v b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/sound/jtframe_mixer_en.v new file mode 100644 index 0000000000000000000000000000000000000000..2b5605664693f319ca744565b20c7fd3fa2c7574 --- /dev/null +++ b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/sound/jtframe_mixer_en.v @@ -0,0 +1,82 @@ +/* This file is part of JTFRAME. + + + JTFRAME program is free software: you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation, either version 3 of the License, or + (at your option) any later version. + + JTFRAME program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with JTFRAME. If not, see . + + Author: Jose Tejada Gomez. Twitter: @topapate + Version: 1.0 + Date: 20-12-2019 + +*/ + +// Adds channel enable signals to jtframe_mixer + +module jtframe_mixer_en #(parameter W0=16,W1=16,W2=16,W3=16,WOUT=16)( + input rst, + input clk, + input cen, + // input signals + input signed [W0-1:0] ch0, + input signed [W1-1:0] ch1, + input signed [W2-1:0] ch2, + input signed [W3-1:0] ch3, + // gain for each channel in 4.4 fixed point format + input [7:0] gain0, + input [7:0] gain1, + input [7:0] gain2, + input [7:0] gain3, + input [3:0] ch_en, + output signed [WOUT-1:0] mixed, + output peak // overflow signal (time enlarged) +); + +reg [7:0] g0, g1, g2, g3; + +always @(posedge clk,posedge rst) begin + if( rst ) begin + g0 <= 0; + g1 <= 0; + g2 <= 0; + g3 <= 0; + end else begin + g0 <= ch_en[0] ? gain0 : 8'd0; + g1 <= ch_en[1] ? gain1 : 8'd0; + g2 <= ch_en[2] ? gain2 : 8'd0; + g3 <= ch_en[3] ? gain3 : 8'd0; + end +end + +jtframe_mixer #( + .W0 ( W0 ), + .W1 ( W1 ), + .W2 ( W2 ), + .W3 ( W3 ), + .WOUT ( WOUT ) +)u_mix( + .rst ( rst ), + .clk ( clk ), + .cen ( cen ), + .ch0 ( ch0 ), + .ch1 ( ch1 ), + .ch2 ( ch2 ), + .ch3 ( ch3 ), + .gain0 ( g0 ), + .gain1 ( g1 ), + .gain2 ( g2 ), + .gain3 ( g3 ), + .mixed ( mixed ), + .peak ( peak ) +); + +endmodule \ No newline at end of file diff --git a/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/sound/jtframe_pole.v b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/sound/jtframe_pole.v new file mode 100644 index 0000000000000000000000000000000000000000..d9ed362f1d808dcc6563721623aed0d3fd6c4d1d --- /dev/null +++ b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/sound/jtframe_pole.v @@ -0,0 +1,77 @@ +/* This file is part of JTFRAME. + + + JTFRAME program is free software: you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation, either version 3 of the License, or + (at your option) any later version. + + JTFRAME program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with JTFRAME. If not, see . + + Author: Jose Tejada Gomez. Twitter: @topapate + Version: 1.0 + Date: 13-1-2021 + +*/ + +// Single pole IIR filter +// y[k] = a * y[k-1] + (1-a) * x[k] +// +// where a = 1/(1+wc), a<1 +// wc = radian normalized frequency = 2*pi*fc/fs +// fc = cut-off frequency, fs = sampling frequency +// There is no overflow check + +module jtframe_pole #(parameter + WS=16, // Assuming that the signal is fixed point + WA=WS/2 // WA is only the decimal part +)( + input rst, + input clk, + input sample, + input signed [WS-1:0] sin, + input [WA-1:0] a, // coefficient, unsigned + output signed [WS-1:0] sout +); + +localparam [WS-1:0] ONE={ {WS-WA-1{1'b0}}, 1'b1, {WA{1'b0}}}; +reg signed [WS :0] insum, full_out, fmux; +reg signed [WS-1:0] sin_l, factor; + +wire signed [ WS-1:0] aext = { {WS-WA{1'b0}}, a }; +reg signed [ 2*WS-1:0] prod, last_prod, sum; + +assign sout = full_out[WS:1]; // drop LSB + +always @(*) begin + insum = {sin[WS-1],sin}+{sin_l[WS-1],sin_l}; + factor = sample ? (ONE-aext) : aext; + fmux = sample ? insum : full_out; + prod = factor * fmux; + sum = last_prod + prod; // using 2*WS for less rounding error +end + +always @(posedge clk) begin + if( rst ) begin + sin_l <= 0; + full_out <= 0; + last_prod <= 0; + end else begin + if(sample) begin + sin_l <= sin; + // a==0 comparison added for logic simplification in jtframe_rcmix + // when the filter is not used and a is constant + full_out <= a==0 ? {sin,1'b0} : sum[WS+WA:WA]; + end else begin + last_prod <= prod; + end + end +end + +endmodule \ No newline at end of file diff --git a/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/sound/jtframe_rcmix.v b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/sound/jtframe_rcmix.v new file mode 100644 index 0000000000000000000000000000000000000000..c64b7ee3bb58af4e50013240ac2e21e18ffdf791 --- /dev/null +++ b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/sound/jtframe_rcmix.v @@ -0,0 +1,223 @@ +/* This file is part of JTFRAME. + + JTFRAME program is free software: you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation, either version 3 of the License, or + (at your option) any later version. + + JTFRAME program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with JTFRAME. If not, see . + + Author: Jose Tejada Gomez. Twitter: @topapate + Version: 1.0 + Date: 4-3-2024 +*/ + +// Generic mixer: improves on the jt12_mixer in JT12 repository + +// Usage: +// Specify width of input signals and desired outputs +// Select gain for each signal + +module jtframe_rcmix #(parameter + W0=16,W1=16,W2=16,W3=16,W4=16,W5=16, + STEREO =1, // is the output stereo? + DCRM0=0,DCRM1=0,DCRM2=0,DCRM3=0,DCRM4=0,DCRM5=0, // dc removal + STEREO0=1,STEREO1=1,STEREO2=1,STEREO3=1,STEREO4=1,STEREO5=1, // are the input channels stereo? + // Path to FIR filter coefficient files. Enabling FIR will disable the 2-pole filters + FIR0="",FIR1="",FIR2="",FIR3="",FIR4="",FIR5="", + // Fractional divider + FRACW=12, FRACN = 1, FRACM=262, + // Do not set externally: + WOUT=16, + WC =15, // pole coefficient resolution + WMX=STEREO ==1?WOUT*2:WOUT, + WS0=STEREO0==1? W0*2:W0, + WS1=STEREO1==1? W1*2:W1, + WS2=STEREO2==1? W2*2:W2, + WS3=STEREO3==1? W3*2:W3, + WS4=STEREO4==1? W4*2:W4, + WS5=STEREO5==1? W5*2:W5 +)( + input rst, + input clk, + input mute, + // input signals + input signed [WS0-1:0] ch0, // for stereo signals, concatenate {left,right} + input signed [WS1-1:0] ch1, + input signed [WS2-1:0] ch2, + input signed [WS3-1:0] ch3, + input signed [WS4-1:0] ch4, + input signed [WS5-1:0] ch5, + input [5:0] ch_en, + // up to 2 pole coefficients per input (unsigned numbers, only decimal part) + input [WC*2-1:0] p0,p1,p2,p3,p4,p5, // concatenate the bits for each pole coefficient + input [WC -1:0] gpole, // allow for one global pole + // gain for each channel in 4.4 fixed point format + input [7:0] g0,g1,g2,g3,g4,g5, // concatenate all gains {gain4, gain3,..., gain0} + input [7:0] gain, // global gain + output sample, + output reg [5:0] vu, // "volume unit", signals channel activity + output reg signed [WMX-1:0] mixed, + output reg peak // overflow signal +); + +localparam SFREQ = 192, // sampling frequency in kHz + STEFF0 = STEREO0 && STEREO, + STEFF1 = STEREO1 && STEREO, + STEFF2 = STEREO2 && STEREO, + STEFF3 = STEREO3 && STEREO, + STEFF4 = STEREO4 && STEREO, + STEFF5 = STEREO5 && STEREO, + WE0 = STEFF0==1 ? 2*W0 : W0, + WE1 = STEFF1==1 ? 2*W1 : W1, + WE2 = STEFF2==1 ? 2*W2 : W2, + WE3 = STEFF3==1 ? 2*W3 : W3, + WE4 = STEFF4==1 ? 2*W4 : W4, + WE5 = STEFF5==1 ? 2*W5 : W5, + WO0 = STEFF0==1 ? 2*WOUT : WOUT, + WO1 = STEFF1==1 ? 2*WOUT : WOUT, + WO2 = STEFF2==1 ? 2*WOUT : WOUT, + WO3 = STEFF3==1 ? 2*WOUT : WOUT, + WO4 = STEFF4==1 ? 2*WOUT : WOUT, + WO5 = STEFF5==1 ? 2*WOUT : WOUT; + +wire signed [WE0-1:0] sm0; +wire signed [WE1-1:0] sm1; +wire signed [WE2-1:0] sm2; +wire signed [WE3-1:0] sm3; +wire signed [WE4-1:0] sm4; +wire signed [WE5-1:0] sm5; +wire signed [WO0-1:0] ft0; +wire signed [WO1-1:0] ft1; +wire signed [WO2-1:0] ft2; +wire signed [WO3-1:0] ft3; +wire signed [WO4-1:0] ft4; +wire signed [WO5-1:0] ft5; +wire [ 5:0] v; // overflow in sound chain +wire signed [15:0] left, right, mul_l, mul_r; +wire signed [16:0] pre_l, pre_r; // extra bit to allow reduction in the final gain stage +wire peak_l, peak_r, pks_l, pks_r; +wire cen; // sampling frequency + +assign sample=cen; + +wire nc; +jtframe_frac_cen #(.WC(FRACW)) u_cen( + .clk ( clk ), + .n ( FRACN ), + .m ( FRACM ), + .cen ({nc,cen} ), + .cenb ( ) +); + +always @(posedge clk) if(cen) begin + vu[0] <= ch0!=0; + vu[1] <= ch1!=0; + vu[2] <= ch2!=0; + vu[3] <= ch3!=0; + vu[4] <= ch4!=0; + vu[5] <= ch5!=0; +end + +// convert to mono if the system is mono, otherwise kept as stereo +jtframe_st2mono #(.W(W0),.STEREO_IN(STEREO0),.STEREO_OUT(STEREO)) u_st0(.sin(ch0),.sout(sm0)); +jtframe_st2mono #(.W(W1),.STEREO_IN(STEREO1),.STEREO_OUT(STEREO)) u_st1(.sin(ch1),.sout(sm1)); +jtframe_st2mono #(.W(W2),.STEREO_IN(STEREO2),.STEREO_OUT(STEREO)) u_st2(.sin(ch2),.sout(sm2)); +jtframe_st2mono #(.W(W3),.STEREO_IN(STEREO3),.STEREO_OUT(STEREO)) u_st3(.sin(ch3),.sout(sm3)); +jtframe_st2mono #(.W(W4),.STEREO_IN(STEREO4),.STEREO_OUT(STEREO)) u_st4(.sin(ch4),.sout(sm4)); +jtframe_st2mono #(.W(W5),.STEREO_IN(STEREO5),.STEREO_OUT(STEREO)) u_st5(.sin(ch5),.sout(sm5)); + +jtframe_sndchain #(.FILE("ch0.raw"),.W(W0),.WC(WC),.DCRM(DCRM0),.STEREO(STEFF0),.FIR(FIR0)) u_ch0(.rst(rst),.clk(clk),.cen(cen),.poles(p0),.gain(g0),.sin(sm0), .sout(ft0), .peak(v[0])); +jtframe_sndchain #(.FILE("ch1.raw"),.W(W1),.WC(WC),.DCRM(DCRM1),.STEREO(STEFF1),.FIR(FIR1)) u_ch1(.rst(rst),.clk(clk),.cen(cen),.poles(p1),.gain(g1),.sin(sm1), .sout(ft1), .peak(v[1])); +jtframe_sndchain #(.FILE("ch2.raw"),.W(W2),.WC(WC),.DCRM(DCRM2),.STEREO(STEFF2),.FIR(FIR2)) u_ch2(.rst(rst),.clk(clk),.cen(cen),.poles(p2),.gain(g2),.sin(sm2), .sout(ft2), .peak(v[2])); +jtframe_sndchain #(.FILE("ch3.raw"),.W(W3),.WC(WC),.DCRM(DCRM3),.STEREO(STEFF3),.FIR(FIR3)) u_ch3(.rst(rst),.clk(clk),.cen(cen),.poles(p3),.gain(g3),.sin(sm3), .sout(ft3), .peak(v[3])); +jtframe_sndchain #(.FILE("ch4.raw"),.W(W4),.WC(WC),.DCRM(DCRM4),.STEREO(STEFF4),.FIR(FIR4)) u_ch4(.rst(rst),.clk(clk),.cen(cen),.poles(p4),.gain(g4),.sin(sm4), .sout(ft4), .peak(v[4])); +jtframe_sndchain #(.FILE("ch5.raw"),.W(W5),.WC(WC),.DCRM(DCRM5),.STEREO(STEFF5),.FIR(FIR5)) u_ch5(.rst(rst),.clk(clk),.cen(cen),.poles(p5),.gain(g5),.sin(sm5), .sout(ft5), .peak(v[5])); + +jtframe_limsum #(.WI(WOUT),.WO(WOUT+1),.K(6)) u_right( + .rst ( rst ), + .clk ( clk ), + .cen ( cen ), + .en ( ch_en ), + .parts ( {ft5[WOUT-1:0], ft4[WOUT-1:0], ft3[WOUT-1:0], ft2[WOUT-1:0], ft1[WOUT-1:0], ft0[WOUT-1:0]} ), + .sum ( pre_r ), + .peak ( pks_r ) +); + +jtframe_limmul #(.WI(WOUT+1),.WO(WOUT)) u_gain( + .rst ( rst ), + .clk ( clk ), + .cen ( cen ), + .gain ( gain ), + .sin ( pre_r ), + .mul ( mul_r ), + .peaked ( pks_r ), + .peak ( peak_r) +); + +// Global RC +jtframe_pole #(.WS(16),.WA(WC)) u_pole1( + .rst ( rst ), + .clk ( clk ), + .sample ( cen ), + .a ( gpole ), + .sin ( mul_r ), + .sout ( right ) +); + +always @(posedge clk) mixed[WOUT-1:0] <= mute ? {WOUT{1'b0}} : right; + +generate + if( STEREO==1 ) begin : leftch + jtframe_limsum #(.WI(WOUT),.WO(WOUT+1),.K(6)) u_left( + .rst ( rst ), + .clk ( clk ), + .cen ( cen ), + .en ( ch_en ), + .parts ( {ft5[WO5-1-:WOUT], + ft4[WO4-1-:WOUT], + ft3[WO3-1-:WOUT], + ft2[WO2-1-:WOUT], + ft1[WO1-1-:WOUT], + ft0[WO0-1-:WOUT] } ), + .sum ( pre_l ), + .peak ( pks_l ) + ); + + jtframe_limmul #(.WI(WOUT+1),.WO(WOUT)) u_gain( + .rst ( rst ), + .clk ( clk ), + .cen ( cen ), + .gain ( gain ), + .sin ( pre_l ), + .mul ( mul_l ), + .peaked ( pks_l ), + .peak ( peak_l) + ); + + // Global RC + jtframe_pole #(.WS(16),.WA(WC)) u_pole1( + .rst ( rst ), + .clk ( clk ), + .sample ( cen ), + .a ( gpole ), + .sin ( mul_l ), + .sout ( left ) + ); + + always @(posedge clk) begin + mixed[WMX-1-:WOUT] <= mute ? {WOUT{1'b0}} : left; + peak <= | {peak_l, peak_r, v}; + end + end else begin + always @(posedge clk) peak <= | {peak_r, v}; + end +endgenerate + +endmodule diff --git a/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/sound/jtframe_sndchain.v b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/sound/jtframe_sndchain.v new file mode 100644 index 0000000000000000000000000000000000000000..f17632352f0160ad83562d39cf8b831df6aef62a --- /dev/null +++ b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/sound/jtframe_sndchain.v @@ -0,0 +1,191 @@ +/* This file is part of JTFRAME. + + + JTFRAME program is free software: you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation, either version 3 of the License, or + (at your option) any later version. + + JTFRAME program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with JTFRAME. If not, see . + + Author: Jose Tejada Gomez. Twitter: @topapate + Version: 1.0 + Date: 4-3-2024 + +*/ + +module jtframe_sndchain #(parameter + W=12, + DCRM=1, + FIR="", + STEREO=1, + WC=8, // width for each pole coefficient + FILE="ch0.raw", // dump raw audio to a file + // do not set + WS = STEREO==1?2*W :W, + WO = 16, + WOS = STEREO==1?2*WO:WO +)( + input rst, + input clk, + input cen, // sample frequency + input [WC*2-1:0] poles, // 8-bit coefficients for two poles + input [7:0] gain, // n.m fixed point format (see WD below) + input signed [ WS-1:0] sin, // for stereo input: { left, right } + output reg signed [WOS-1:0] sout, // for stereo output: { left, right } + output reg peak // overflow (signal clipped) +); + +localparam WM = WOS+9, + WD = 7; // decimal part + +reg signed [WOS-1:0] scld; +wire signed [WOS-1:0] dc, p1, p2; +wire signed [ WM-1:0] mul_l, mul_r; +wire signed [ 8:0] sgain; +wire [ WC-1:0] c1, c2; +wire over_r, over_l; + +initial begin + if( W>WO ) begin + $display("Maximum allowed signal width is %d\n",WO); + $finish; + end +end + +assign sgain = {1'b0,gain}; +assign mul_r = $signed(p2[ 0+:WO])*sgain; +assign mul_l = $signed(p2[WOS-1-:WO])*sgain; +assign over_r = over(mul_r[WM-1:WO+WD-1]), + over_l = over(mul_l[WM-1:WO+WD-1]); + +function over(input [WM-WO-WD:0]signs); + over = |signs & ~&signs; +endfunction + +always @* begin + scld[ 0+:WO]={sin[ 0+:W], {WO-W{1'b0}}}; + scld[WOS-1-:WO]={sin[WS-1-:W], {WO-W{1'b0}}}; +end + +always @(posedge clk, posedge rst) begin + if( rst ) begin + sout <= 0; + peak <= 0; + end else begin + sout[0+:WO] <= mul_r[WD+:WO]; + if(over_r) sout[0+:WO] <= { mul_r[WM-1], {WO-1{~mul_r[WM-1]}}}; + peak <= over_r; + if(STEREO==1) begin + sout[WOS-1-:WO] <= mul_l[WD+:WO]; + if(over_l) sout[WOS-1-:WO] <= { mul_l[WM-1], {WO-1{~mul_l[WM-1]}}}; + peak <= over_r | over_l; + end + end +end + +generate + if( DCRM==1 ) begin // Use the dc removal to convert from unsigned to signed + jtframe_dcrm #(.SW(WO),.SIGNED_INPUT(0)) u_dcrm( + .rst ( rst ), + .clk ( clk ), + .sample ( cen ), + .din ( scld[WO-1:0] ), + .dout ( dc[WO-1:0] ) + ); + if( STEREO==1 ) begin + jtframe_dcrm #(.SW(WO),.SIGNED_INPUT(0)) u_dcrm_l( + .rst ( rst ), + .clk ( clk ), + .sample ( cen ), + .din (scld[WOS-1-:WO]), + .dout ( dc[WOS-1-:WO] ) + ); + end + end else begin + assign dc = scld; + end +endgenerate + +generate + if( FIR=="" ) begin + assign c1 = poles[WC-1:0], + c2 = poles[WC+:WC]; + // 1st pole + jtframe_pole #(.WS(WO),.WA(WC)) u_pole1( + .rst ( rst ), + .clk ( clk ), + .sample ( cen ), + .a ( c1 ), + .sin ( dc[0+:WO] ), + .sout ( p1[0+:WO] ) + ); + jtframe_pole #(.WS(WO),.WA(WC)) u_pole2( + .rst ( rst ), + .clk ( clk ), + .sample ( cen ), + .a ( c2 ), + .sin ( p1[0+:WO] ), + .sout ( p2[0+:WO] ) + ); + if( STEREO==1 ) begin + jtframe_pole #(.WS(WO),.WA(WC)) u_pole1_l( + .rst ( rst ), + .clk ( clk ), + .sample ( cen ), + .a ( c1 ), + .sin (dc[(WOS-1)-:WO]), + .sout (p1[(WOS-1)-:WO]) + ); + jtframe_pole #(.WS(WO),.WA(WC)) u_pole2_l( + .rst ( rst ), + .clk ( clk ), + .sample ( cen ), + .a ( c2 ), + .sin (p1[(WOS-1)-:WO]), + .sout (p2[(WOS-1)-:WO]) + ); + end + end else begin + wire [WO-1:0] fir_l, fir_r; + jtframe_fir #(.COEFFS(FIR)) u_fir( + .rst ( rst ), + .clk ( clk ), + .sample ( cen ), + .l_in ( dc[0+:WO] ), + .r_in (dc[(WOS-1)-:WO]), + .l_out ( fir_l ), + .r_out ( fir_r ) + ); + assign p2[0+:WO] = fir_r; + if( STEREO==1 ) begin + assign p2[(WOS-1)-:WO] = fir_l; + end + end +endgenerate + +`ifdef DUMP + `define JTFRAME_SIM_CH_RAW +`endif + +`ifdef JTFRAME_SIM_CH_RAW +integer fsnd; +initial begin + fsnd=$fopen(FILE,"wb"); +end + +always @(posedge cen) begin + if(STEREO==1) + $fwrite(fsnd,"%u", sout ); + else + $fwrite(fsnd,"%u", {2{sout}} ); +end +`endif + +endmodule \ No newline at end of file diff --git a/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/sound/jtframe_sndrec.sv b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/sound/jtframe_sndrec.sv new file mode 100644 index 0000000000000000000000000000000000000000..d528f3784e0e308cc46d15a24ac1afe56a69f5d0 --- /dev/null +++ b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/sound/jtframe_sndrec.sv @@ -0,0 +1,105 @@ +/* This file is part of JT_FRAME. + JTFRAME program is free software: you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation, either version 3 of the License, or + (at your option) any later version. + + JTFRAME program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with JTFRAME. If not, see . + + Author: Jose Tejada Gomez. Twitter: @topapate + Version: 1.0 + Date: 28-6-2023 */ + +module jtframe_sndrec( + input rst, + input clk, + input v5, // 240 Hz + input we, + input [3:0] a, + input [7:0] din, + + output [7:0] ioctl_din +); + +localparam RECAW=13; + +/* Encoding + byte 0: + 00 -> EOF + 80 -> v5 pulse (once every 64 lines -rising edge of v5- ) + 1x -> write to address a + byte 1 + xx -> data written +*/ + +reg v5l, we_l, rec_we, do_data, rec_clrd, full; +reg [RECAW-1:0] reca; + +always @(posedge clk, posedge rst) begin + if( rst ) begin + reca <= 0; + rec_clrd <= 0; + recin <= 0; + rec_we <= 0; + do_data <= 0; + v5l <= 0; + we_l <= 0; + full <= 0; + end else begin + if( !rec_clrd ) begin + reca <= reca+1'd1; + recin <= 0; + rec_we <= 1; + if( &reca ) begin + rec_clrd <= 1; + rec_we <= 0; + end + end else if(!full) begin + v5l <= v5; + we_l <= we; + if( rec_we ) begin + reca <= reca + 1'd1; + rec_we <= 0; + end + if( v5 && !v5l ) do_v5 <= 1; + if( we && !we_l ) begin + recin <= {4'd1,a}; + do_data <= 1; + rec_we <= 1; + end else if( do_data ) begin + recin <= din; + do_data <= 0; + rec_we <= 1; + end else if( do_v5 ) begin + rec_din <= 8'h80; + rec_we <= 1; + end + if( &reca ) full <= 1; + end else begin // full + rec_we <= 0; + end + end +end + +jtframe_dual_ram #(.AW(RECAW) ) u_record( // 2kB, set in jtdef.go + // Port 0: record + .clk0 ( clk ), + .data0 ( recmux ), + .addr0 ( reca ), + .we0 ( rec_we ), + .q0 ( ), + // Port 1: readout + .clk1 ( clk ), + .data1 ( 8'd0 ), + .addr1 (ioctl_addr[RECAW-1:0]), + .we1 ( 1'b0 ), + .q1 ( ioctl_din ) +); + +endmodule \ No newline at end of file diff --git a/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/sound/jtframe_st2mono.v b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/sound/jtframe_st2mono.v new file mode 100644 index 0000000000000000000000000000000000000000..5eb0619b179472c484cf5b22329a98521d65c3f1 --- /dev/null +++ b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/sound/jtframe_st2mono.v @@ -0,0 +1,61 @@ +/* This file is part of JTFRAME. + + + JTFRAME program is free software: you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation, either version 3 of the License, or + (at your option) any later version. + + JTFRAME program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with JTFRAME. If not, see . + + Author: Jose Tejada Gomez. Twitter: @topapate + Version: 1.0 + Date: 4-3-2024 + +*/ + +// converts stereo to mono by a clipping adder +// or leaves the signal as stereo if the output can take stereo +module jtframe_st2mono #(parameter + W = 12, + STEREO_IN = 1, + STEREO_OUT = 1, + // Do not assign + EFF_OUT = STEREO_IN==1&&STEREO_OUT==1 ? 1 : 0, + WI = (STEREO_IN==1?2*W:W), + WO = EFF_OUT==1?2*W:W +)( + input [WI-1:0] sin, + output reg [WO-1:0] sout +); + +initial begin + if(STEREO_IN==0 && EFF_OUT==1) begin + $display("mono to stereo conversion is not supported"); + `ifdef SIMULATION + $stop; + `endif + end +end + +wire [W:0] raw = {sin[W-1],sin[0+:W]}+{sin[WI-1],sin[WI-1-:W]}; +reg [W-1:0] mono; +localparam [1:0] ST2MONO =2'b10, + STEREO =2'b11; + +always @* begin + mono = raw[W]!=raw[W-1] ? { raw[W], {W-1{~raw[W]}}} : raw[W-1:0]; + case( {STEREO_IN[0], EFF_OUT[0]} ) + STEREO: sout = sin[WO-1:0]; + ST2MONO: sout[W-1:0] = mono; + default: sout[W-1:0] = sin[W-1:0]; + endcase +end + +endmodule diff --git a/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/sound/jtframe_volume.v b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/sound/jtframe_volume.v new file mode 100644 index 0000000000000000000000000000000000000000..86ebfb0ed0e0c29b3aebc6e58fcca439ff5dfe40 --- /dev/null +++ b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/sound/jtframe_volume.v @@ -0,0 +1,64 @@ +/* This file is part of JTFRAME. + JTFRAME program is free software: you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation, either version 3 of the License, or + (at your option) any later version. + + JTFRAME program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with JTFRAME. If not, see . + + Author: Jose Tejada Gomez. Twitter: @topapate + Version: 1.0 + Date: 10-5-2021 */ + +module jtframe_volume( + input rst, + input clk, + input vs, + input peak, + input up, + input down, + input [7:0] game_vol, + output reg [7:0] vol +); + +localparam [7:0] UNSET=8'h0; + +reg lock, vs_l, peaked; +reg [ 7:0] knob; +reg [15:0] vol16; + +always @(posedge clk) begin + vol16 <= game_vol==UNSET ? {knob,8'd0} : knob*game_vol; + vol <= vol16[15] ? 8'hff : vol16[14-:8]; +end + +always @(posedge clk, posedge rst) begin + if( rst ) begin + knob <= 8'h80; // matching value in game_test.v + vs_l <= 0; + lock <= 0; + peaked <= 0; + end else begin + vs_l <= vs; + if( peak ) peaked <= 1; + if( !lock ) begin + if( ~&knob && up && !peaked ) begin + knob <= knob+8'd1; + end + if( |knob && down ) begin + knob <= knob-8'd1; + peaked <= 0; + end + lock <= 1; + end + if( vs && !vs_l ) lock <= 0; + end +end + +endmodule \ No newline at end of file diff --git a/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/sound/jtframe_vumeter.sv b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/sound/jtframe_vumeter.sv new file mode 100644 index 0000000000000000000000000000000000000000..636576eb39c10f85ea255ff6d824b8bfc0e8a00b --- /dev/null +++ b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/sound/jtframe_vumeter.sv @@ -0,0 +1,87 @@ +/* This file is part of JTFRAME. + + + JTFRAME program is free software: you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation, either version 3 of the License, or + (at your option) any later version. + + JTFRAME program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with JTFRAME. If not, see . + + Author: Jose Tejada Gomez. Twitter: @topapate + Version: 1.0 + Date: 5-4-2024 + +*/ + +// average sound power +module jtframe_vumeter( + input rst, + input clk, + input cen, // use 192 kHz + // input signals + input signed [15:0] l, r, + output reg [ 7:0] vu, // "volume unit", signals channel activity + output reg peak // overflow signal +); + +localparam W=28; + +reg signed [31:0] ml, mr; +reg [15:0] l2r2; // accumulator result is always possitive +reg [12:0] cnt; +reg [ 5:0] peak_cnt; +reg [ 1:0] cen_div=0; +reg cen48; +reg [W-1:0] acc; +wire [W-1:0] nx_acc; +wire over, v; + +assign over = &cnt; +assign {v, nx_acc} = ({1'b0,acc}>>over)+{ {W-16{1'b0}},l2r2}; + +always @(posedge clk) begin + cen_div <= cen_div+2'd1; + cen48 <= &cen_div; +end + +always @(posedge clk, posedge rst) begin + if( rst ) begin + + end else if(cen48) begin + ml <= l*l; + mr <= r*r; + l2r2 <= ml[31-:16]+mr[31-:16]; + acc <= v ? '1 : nx_acc; + cnt <= cnt+1; + if(over) casez(acc[W-1-:8]) + 8'b0000_0001: vu <= 8'h01; + 8'b0000_001?: vu <= 8'h03; + 8'b0000_01??: vu <= 8'h07; + 8'b0000_1???: vu <= 8'h0f; + 8'b0001_????: vu <= 8'h1f; + 8'b001?_????: vu <= 8'h3f; + 8'b01??_????: vu <= 8'h7f; + 8'b1???_????: vu <= 8'hff; + default: vu <= 0; + endcase + // peak + if( &peak_cnt ) begin + peak <= 0; + end else begin + peak_cnt <= peak_cnt+1'd1; + end + if( v ) begin + peak <= 1; + peak_cnt <= 0; + end + end +end + +endmodule \ No newline at end of file diff --git a/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/video/crosshair/jtframe_crosshair.v b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/video/crosshair/jtframe_crosshair.v new file mode 100644 index 0000000000000000000000000000000000000000..a30a5b81d9ce61bc1de48de65651f263d06920ba --- /dev/null +++ b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/video/crosshair/jtframe_crosshair.v @@ -0,0 +1,112 @@ +/* This file is part of JTFRAME. + JTFRAME program is free software: you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation, either version 3 of the License, or + (at your option) any later version. + + JTFRAME program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with JTFRAME. If not, see . + + Author: Rafael Eduardo Paiva Feener. Copyright: Miki Saito + Version: 1.0 + Date: 26-02-2025 */ + +module jtframe_crosshair #(parameter COLORW=4)( + input rst, + input clk, + input pxl_cen, + input flip, + input draw_en, + input [ 1:0] cross_disable, + input pre_lvbl, + input pre_lhbl, + input pre_hs, + input pre_vs, + output lvbl, + output lhbl, + output hs, + output vs, + input [ 8:0] gun_1p_x, + input [ 8:0] gun_1p_y, + input [ 8:0] gun_2p_x, + input [ 8:0] gun_2p_y, + input [COLORW-1:0] rin, + input [COLORW-1:0] gin, + input [COLORW-1:0] bin, + output [COLORW-1:0] rout, + output [COLORW-1:0] gout, + output [COLORW-1:0] bout +); + +`ifdef JTFRAME_LIGHTGUN +wire [3*COLORW-1:0] rgb_cross; +wire [ 8:0] hcnt, vcnt; +wire [ 3:0] crosshair; + +jtframe_crosshair_draw u_crosshair_left( + .clk ( clk ), + .hcnt ( hcnt ), + .vcnt ( vcnt ), + .x ( gun_1p_x ), + .y ( gun_1p_y ), + .crosshair ( crosshair[1:0] ) +); + +jtframe_crosshair_draw u_crosshair_center( + .clk ( clk ), + .hcnt ( hcnt ), + .vcnt ( vcnt ), + .x ( gun_2p_x ), + .y ( gun_2p_y ), + .crosshair ( crosshair[3:2] ) +); + +jtframe_video_counter u_vidcnt( + .rst ( rst ), + .clk ( clk ), + .pxl_cen ( pxl_cen ), + .flip ( 1'b0 ), + .lhbl ( pre_lhbl ), + .lvbl ( pre_lvbl ), + .v ( vcnt ), + .h ( hcnt ) +); + +jtframe_crosshair_color #(.COLORW(COLORW)) u_crosshair_color( + .clk ( clk ), + .draw_en ( draw_en ), + .hs_in ( pre_hs ), + .vs_in ( pre_vs ), + .hs_out ( hs ), + .vs_out ( vs ), + .cross_disable({1'b0,cross_disable}), + .crosshair ({2'b0,crosshair}), + .rin ( rin ), + .gin ( gin ), + .bin ( bin ), + .rgb_cross ( rgb_cross ) +); + +jtframe_blank #(.DLY(1),.DW(COLORW*3)) u_blank( + .clk ( clk ), + .pxl_cen ( pxl_cen ), + .preLHBL ( pre_lhbl ), + .preLVBL ( pre_lvbl ), + .LHBL ( lhbl ), + .LVBL ( lvbl ), + .preLBL ( ), + .rgb_in ( rgb_cross ), + .rgb_out ( {rout,gout,bout} ) +); +`else +assign {rout,gout,bout} = {rin,gin,bin}; +assign {lhbl,lvbl} = {pre_lhbl,pre_lvbl}; +assign {hs , vs } = {pre_hs, pre_vs }; +`endif + +endmodule \ No newline at end of file diff --git a/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/video/crosshair/jtframe_crosshair_color.v b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/video/crosshair/jtframe_crosshair_color.v new file mode 100644 index 0000000000000000000000000000000000000000..2f6766c6b0d5b5d02ae39d3bf168b77720820c2a --- /dev/null +++ b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/video/crosshair/jtframe_crosshair_color.v @@ -0,0 +1,54 @@ +/* This file is part of JTFRAME. + JTFRAME program is free software: you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation, either version 3 of the License, or + (at your option) any later version. + + JTFRAME program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with JTFRAME. If not, see . + + Author: Rafael Eduardo Paiva Feener. Copyright: Miki Saito + Version: 1.0 + Date: 27-02-2025 */ + +module jtframe_crosshair_color #(parameter COLORW=4)( + input clk, + input draw_en, + input hs_in, vs_in, + output reg hs_out, vs_out, + input [ 2:0] cross_disable, + input [ 5:0] crosshair, + input [ COLORW-1:0] rin, + input [ COLORW-1:0] gin, + input [ COLORW-1:0] bin, + output [3*COLORW-1:0] rgb_cross + ); + +reg [COLORW-1:0] r_cross, g_cross, b_cross; +wire [ 2:0] ch_col, ch_black; + +assign rgb_cross = {r_cross, g_cross, b_cross}; +assign ch_col = {crosshair[4],crosshair[2],crosshair[0]} & ~cross_disable; +assign ch_black = {crosshair[5],crosshair[3],crosshair[1]} & ~cross_disable; + +always @(posedge clk) begin + {hs_out, vs_out} <= {hs_in, vs_in}; + if(draw_en) begin + r_cross <= |ch_col ? {COLORW{ch_col[0]}} : rin; + g_cross <= |ch_col ? {COLORW{ch_col[1]}} : gin; + b_cross <= |ch_col ? {COLORW{ch_col[2]}} : bin; + if(ch_black!=0) + {r_cross, g_cross, b_cross} <= 0; + end else begin + r_cross <= rin; + g_cross <= gin; + b_cross <= bin; + end +end + +endmodule \ No newline at end of file diff --git a/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/video/crosshair/jtframe_crosshair_disable.v b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/video/crosshair/jtframe_crosshair_disable.v new file mode 100644 index 0000000000000000000000000000000000000000..69152f3da68977bf6762ae4221a3bc4d7288ad9e --- /dev/null +++ b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/video/crosshair/jtframe_crosshair_disable.v @@ -0,0 +1,52 @@ +/* This file is part of JTFRAME. + JTFRAME program is free software: you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation, either version 3 of the License, or + (at your option) any later version. + + JTFRAME program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with JTFRAME. If not, see . + + Author: Rafael Eduardo Paiva Feener. Copyright: Miki Saito + Version: 1.0 + Date: 28-02-2025 */ + +module jtframe_crosshair_disable #(parameter CNTW=8)( + input rst, + input clk, + input vs, + input [1:0] strobe, + output pulse, + output [1:0] en_b +); + +jtframe_countup #(.W(CNTW) +)crosshair_left( + .rst( strobe[0] ), + .clk( clk ), + .cen( pulse ), + .v ( en_b[0] ) +); + +jtframe_countup #(.W(CNTW) +)crosshair_rigth( + .rst( strobe[1] ), + .clk( clk ), + .cen( pulse ), + .v ( en_b[1] ) +); + +jtframe_edge cnt_pulse( + .rst ( rst ), + .clk ( clk ), + .edgeof( vs ), + .clr ( pulse ), + .q ( pulse ) +); + +endmodule \ No newline at end of file diff --git a/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/video/crosshair/jtframe_crosshair_draw.sv b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/video/crosshair/jtframe_crosshair_draw.sv new file mode 100644 index 0000000000000000000000000000000000000000..0b1d549063e8c34d571e87f018dee8962d473a6c --- /dev/null +++ b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/video/crosshair/jtframe_crosshair_draw.sv @@ -0,0 +1,57 @@ +/* This file is part of JTFRAME. + JTFRAME program is free software: you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation, either version 3 of the License, or + (at your option) any later version. + + JTFRAME program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with JTFRAME. If not, see . + + Author: Rafael Eduardo Paiva Feener. Copyright: Miki Saito + Version: 1.0 + Date: 28-02-2025 */ + +module jtframe_crosshair_draw( + input clk, + input [8:0] hcnt, + input [8:0] vcnt, + input [8:0] x, + input [8:0] y, + output reg [1:0] crosshair +); + +wire [8:0] x_diff, y_diff; +reg [5:0] cord; +reg [1:0] pxl [63:0]; +wire [1:0] cross_pre; +reg inzone; + +assign x_diff = hcnt - x; +assign y_diff = vcnt - y; +assign cross_pre = inzone ? pxl[cord] : 2'b0; + +always @(posedge clk) begin + inzone <= ( ( ~|x_diff[8:3] && ~&x_diff[2:1] ) || ( &x_diff[8:3] && |x_diff[2:1] ) ) && + ( ( ~|y_diff[8:3] && ~&y_diff[2:1] ) || ( &y_diff[8:3] && |y_diff[2:1] ) ); + cord <= { ~y_diff[2], y_diff[1:0], ~x_diff[2], x_diff[1:0] }; + crosshair <= cross_pre; +end + +initial pxl ='{ +// X 0 1 2 3 4 5 6 7 // Y + 0, 0, 3, 1, 1, 3, 0, 0, // 0 + 0, 0, 3, 1, 1, 3, 0, 0, // 1 + 3, 3, 3, 1, 1, 3, 3, 3, // 2 + 1, 1, 1, 3, 3, 1, 1, 1, // 3 + 1, 1, 1, 3, 3, 1, 1, 1, // 4 + 3, 3, 3, 1, 1, 3, 3, 3, // 5 + 0, 0, 3, 1, 1, 3, 0, 0, // 6 + 0, 0, 3, 1, 1, 3, 0, 0 // 7 +}; + +endmodule diff --git a/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/video/jtframe_avatar.v b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/video/jtframe_avatar.v new file mode 100644 index 0000000000000000000000000000000000000000..c705132788ad5f51c574e6cb6c287a924cfa6447 --- /dev/null +++ b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/video/jtframe_avatar.v @@ -0,0 +1,54 @@ +/* This file is part of JTFRAME. + JTFRAME program is free software: you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation, either version 3 of the License, or + (at your option) any later version. + + JTFRAME program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with JTFRAME. If not, see . + + Author: Jose Tejada Gomez. Twitter: @topapate + Version: 1.0 + Date: 20-2-2019 */ + + +module jtframe_avatar #(parameter AW=13)( + input rst, + input clk, + input pause, + input [AW-1:0] obj_addr, + input [15:0] obj_data, + input ok_in, + output reg ok_out, + output reg [15:0] obj_mux +); + +`ifdef JTFRAME_AVATARS + // Alternative Objects during pause for MiSTer + wire [15:0] avatar_data; + jtframe_ram #(.DW(16), .AW(AW), .SYNFILE("avatar.hex"),.CEN_RD(1)) u_avatars( + .clk ( clk ), + .cen ( pause ), // tiny power saving when not in pause + .data ( 16'd0 ), + .addr ( obj_addr ), + .we ( 1'b0 ), + .q ( avatar_data ) + ); + always @(posedge clk) begin + obj_mux <= pause ? avatar_data : obj_data; + ok_out <= ok_in; + end +`else + // Let the real data go through + always @(*) begin + obj_mux = obj_data; + ok_out = ok_in; + end +`endif + +endmodule \ No newline at end of file diff --git a/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/video/jtframe_blank.v b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/video/jtframe_blank.v new file mode 100644 index 0000000000000000000000000000000000000000..e7320b54c57934f1634037a93f9578cc22b1bb24 --- /dev/null +++ b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/video/jtframe_blank.v @@ -0,0 +1,61 @@ +/* This file is part of JTFRAME. + JTFRAME program is free software: you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation, either version 3 of the License, or + (at your option) any later version. + + JTFRAME program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with JTFRAME. If not, see . + + Author: Jose Tejada Gomez. Twitter: @topapate + Version: 1.0 + Date: 17-05-2020 */ + +module jtframe_blank #(parameter DLY=4,DW=12)( + input clk, + input pxl_cen, + input preLHBL, + input preLVBL, + output reg LHBL, + output reg LVBL, + output preLBL, + input [DW-1:0] rgb_in, + output reg [DW-1:0] rgb_out +); + +wire [1:0] predly; + +assign preLBL = predly==2'b11; + +generate + if( DLY>1 ) + jtframe_sh #(.W(2),.L(DLY-1)) u_dly( + .clk ( clk ), + .clk_en ( pxl_cen ), + .din ( {preLHBL, preLVBL} ), + .drop ( predly ) + ); + else + assign predly = {preLHBL, preLVBL}; +endgenerate + +generate + if( DLY > 0 ) begin : latch + always @(posedge clk) if(pxl_cen) begin + rgb_out <= predly==2'b11 ? rgb_in : {DW{1'b0}}; + {LHBL, LVBL} <= predly; + end + end else begin : comb // DLY==0 + always @(*) begin + rgb_out = predly==2'b11 ? rgb_in : {DW{1'b0}}; + {LHBL, LVBL} = predly; + end + end +endgenerate + +endmodule \ No newline at end of file diff --git a/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/video/jtframe_blank_length.v b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/video/jtframe_blank_length.v new file mode 100644 index 0000000000000000000000000000000000000000..25d68c63c3695dce74cb9fb3d3cb415731837da0 --- /dev/null +++ b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/video/jtframe_blank_length.v @@ -0,0 +1,158 @@ +/* This file is part of JTFRAME. + JTFRAME program is free software: you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation, either version 3 of the License, or + (at your option) any later version. + + JTFRAME program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with JTFRAME. If not, see . + + Author: Jose Tejada Gomez. Twitter: @topapate + Version: 1.0 + Date: 5-9-2025 */ + +module jtframe_blank_length( + input rst, + input clk, + input pxl_cen, + + input lhbl, lvbl, + input hs, vs, + + output rdy, // v*_len ready after two frames + + output [8:0] h_len, + output [8:0] v_len, + output [5:0] hbs_len, // H blank start to HS start + hsy_len, // HS length + hsa_len, // HS end to active video start + vbs_len, // V blank start to HS start + vsy_len, // VS length + vsa_len // VS end to active video start +); + + reg [2:0] rdy_sh; + reg lvbl_l, lhbl_l; + wire hbl_neg, vbl_neg; + + assign hbl_neg = !lhbl && lhbl_l; + assign vbl_neg = !lvbl && lvbl_l; + assign rdy = rdy_sh[1]; + + always @(posedge clk) begin : blank_edges + if( rst ) begin + lvbl_l <= 0; + lhbl_l <= 0; + end else if(pxl_cen) begin + lhbl_l <= lhbl; + if( hbl_neg ) begin + lvbl_l <= lvbl; + end + end + end + + always @(posedge clk) begin : frames_to_ready + if( rst ) begin + rdy_sh <= 0; + end else if(pxl_cen) begin + if( vbl_neg & hbl_neg ) rdy_sh <= {rdy_sh[1:0],1'b1}; + end + end + + jtframe_sync_blank_counter u_hcnt( + .rst ( rst ), + .clk ( clk ), + .pxl_cen ( pxl_cen ), + .cnt_cen ( 1'b1 ), + + .s ( hs ), + .lbl ( lhbl ), + + .total ( h_len ), + + .bs_len ( hbs_len ), + .sy_len ( hsy_len ), + .sa_len ( hsa_len ) + ); + + jtframe_sync_blank_counter u_vcnt( + .rst ( rst ), + .clk ( clk ), + .pxl_cen ( pxl_cen ), + .cnt_cen ( hbl_neg ), + + .s ( vs ), + .lbl ( lvbl ), + + .total ( v_len ), + + .bs_len ( vbs_len ), + .sy_len ( vsy_len ), + .sa_len ( vsa_len ) + ); + +endmodule + +////////////////////////////////////////////////////////// +module jtframe_sync_blank_counter( + input rst, clk, + s, lbl, + pxl_cen, + cnt_cen, + + output reg [8:0] total, + + output reg [5:0] bs_len, // blank start to S start + sy_len, // S length + sa_len // S end to active video start +); + + reg [8:0] cnt; + reg [5:0] aux; + reg s_l, lbl_l; + + always @(posedge clk) begin : blank_edges + if( rst ) begin + s_l <= 0; + lbl_l <= 0; + end else if(pxl_cen) begin + if( cnt_cen ) begin + s_l <= s; + lbl_l <= lbl; + end + end + end + + always @(posedge clk) begin : vertical_counter + if( rst ) begin + cnt <= 0; + aux <= 0; + bs_len <= 0; + sy_len <= 0; + sa_len <= 0; + total <= 0; + end else if(pxl_cen) begin + if (!lbl) begin + if( cnt_cen ) begin + aux <= aux + 1'd1; + if( s && !s_l) begin bs_len <= aux; aux <= 0; end + if(!s && s_l) begin sy_len <= aux; aux <= 0; end + end + end else if( cnt_cen ) begin + cnt <= cnt + 9'd1; + if(!lbl_l) begin + aux <= 0; + sa_len <= aux; + cnt <= 0; + total <= cnt; + end + end + end + end + +endmodule \ No newline at end of file diff --git a/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/video/jtframe_blink.v b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/video/jtframe_blink.v new file mode 100644 index 0000000000000000000000000000000000000000..acb2b1aeb2b08efb2c4eb4ee4a254fb9d70cb35a --- /dev/null +++ b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/video/jtframe_blink.v @@ -0,0 +1,36 @@ +/* This file is part of JTCORES. + JTCORES program is free software: you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation, either version 3 of the License, or + (at your option) any later version. + + JTCORES program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with JTCORES. If not, see . + + Author: Jose Tejada Gomez. Twitter: @topapate + Version: 1.0 + Date: 3-1-2025 */ + +// blink output toggles every frame as long as en==1 +// if en==0, blink=0 +module jtframe_blink( + input clk, + input vs, + input en, + output reg blink=0 +); + +reg vs_l=0, odd=0; + +always @(posedge clk) begin + vs_l <= vs; + if( vs & ~vs_l ) odd<=~odd; + blink <= !en || odd; +end + +endmodule \ No newline at end of file diff --git a/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/video/jtframe_center_logo.v b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/video/jtframe_center_logo.v new file mode 100644 index 0000000000000000000000000000000000000000..e217e3b26a8458f014311a653bdd805f286ccd31 --- /dev/null +++ b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/video/jtframe_center_logo.v @@ -0,0 +1,112 @@ +/* This file is part of JTFRAME. + JTFRAME program is free software: you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation, either version 3 of the License, or + (at your option) any later version. + + JTFRAME program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with JTFRAME. If not, see . + + Author: Jose Tejada Gomez. Twitter: @topapate + Version: 1.0 + Date: 11-8-2022 */ + +// shows the JT logo at the screen centre +module jtframe_center_logo #(parameter + COLORW = 4, + SHOWHEX = 1 +) ( + input rst, + input clk, + input pxl_cen, + input show_en, + // input [1:0] rotate, //[0] - rotate [1] - left or right + + // VGA signals coming from core + input [3*COLORW-1:0] rgb_in, + input hs, + input vs, + input lhbl, + input lvbl, + + // VGA signals going to video connector + output reg [3*COLORW-1:0] rgb_out, + + input [63:0] chipid, + + output reg hs_out, + output reg vs_out, + output reg lhbl_out, + output reg lvbl_out +); + +reg [ 8:0] hcnt=0,vcnt=0, + htot=9'd256, vtot=9'd256, + hover=0, vover=9'd100; +reg [ 9:0] hdiff, vdiff; +reg lhbl_l, lvbl_l; +wire idpxl, blank; +reg inzone; +wire [COLORW*3-1:0] logorgb, logo_id_mx, bg; + +assign logo_id_mx = inzone ? logorgb : {3*COLORW{idpxl & SHOWHEX[0] }}; +assign blank = logo_id_mx == 0; +assign bg = `ifdef BETA { {2*COLORW{1'b1}}, {COLORW{1'b0}}}; // yellowish + `else {COLORW{1'b0}}; `endif + +always @(posedge clk) if( pxl_cen ) begin + { hs_out, vs_out } <= { hs, vs }; + { lhbl_out, lvbl_out } <= { lhbl, lvbl }; + rgb_out <= !show_en ? rgb_in : // regular video + !blank ? logo_id_mx : // logo or chip ID + bg; // background color +end + +always @* begin + hdiff = {1'b0,hcnt} - {1'b0,hover}; + vdiff = {1'b0,vcnt} - {1'b0,vover}; + inzone = hdiff < 256 && !hdiff[9] && hdiff>8 && + vdiff < 128 && !vdiff[9]; +end + +// screen counter +always @(posedge clk) if( pxl_cen ) begin + lhbl_l <= lhbl; + lvbl_l <= lvbl; + hcnt <= lhbl ? hcnt + 9'd1 : 9'd0; + if( !lhbl && lhbl_l ) begin + htot <= hcnt; + vcnt <= lvbl ? vcnt+9'd1 : 9'd0; + end + if( !lvbl && lvbl_l ) begin + vtot <= vcnt; + hover <= htot<9'd256 ? 9'd0 : (htot-9'd256)>>1; + vover <= vtot<9'd128 ? 9'd0 : (vtot-9'd128)>>1; + end +end + +jtframe_logo #(.COLORW(COLORW)) u_logo( + .rst ( rst ), + .clk ( clk ), + .pxl_cen ( pxl_cen ), + + .vdump ( vdiff ), + .hdump ( hdiff ), + .rgb ( logorgb ) +); + +jtframe_hexdisplay #(.H0(64),.V0(192)) u_hexdisplay( + .clk ( clk ), + .pxl_cen ( pxl_cen ), + .hcnt ( hcnt ), + .vcnt ( vcnt ), + .data ( chipid ), + .pxl ( idpxl ) +); + +endmodule diff --git a/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/video/jtframe_charmsg.v b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/video/jtframe_charmsg.v new file mode 100644 index 0000000000000000000000000000000000000000..3982f5c84b8b632762224cc7e814f032a7e67ce1 --- /dev/null +++ b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/video/jtframe_charmsg.v @@ -0,0 +1,72 @@ +/* This file is part of JTFRAME. + JTFRAME program is free software: you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation, either version 3 of the License, or + (at your option) any later version. + + JTFRAME program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with JTFRAME. If not, see . + + Author: Jose Tejada Gomez. Twitter: @topapate + Version: 1.0 + Date: 18-2-2019 */ + +// Alternative memory for on-screen message generation +// SW = width of the memory address/scan vectors +// msg_width output is a fixed value equal to HVAL + +module jtframe_charmsg #(parameter SW=10, HVAL=8'd2, VERTICAL=1)( + input clk, + input pxl_cen, /* synthesis direct_enable = 1 */ + + input [3:0] avatar_idx, + input [SW-1:0] scan, + output reg [7:0] msg_low, + output [7:0] msg_high +); + +wire [7:0] mem_msg, mem_msg_av; + +jtframe_ram #(.AW(SW),.SYNFILE("msg.hex"),.SIMFILE("msg.bin")) u_char_msg( + .clk ( clk ), + .cen ( pxl_cen ), + .data ( 8'd0 ), + .addr ( scan ), + .we ( 1'b0 ), + .q ( mem_msg ) +); + +`ifdef JTFRAME_AVATARS +wire [4:0] av_sel0 = VERTICAL ? scan[9:5] : scan[4:0]; +wire [4:0] av_sel1 = VERTICAL ? scan[4:0] : scan[9:5]; +localparam [4:0] AVPOS = VERTICAL ? 5'd8 : 5'd22; + +wire [8:0] av_scan = { avatar_idx, av_sel0 }; + +jtframe_ram #(.AW(9),.SYNFILE("msg_av.hex")) u_ram_msg_av( + .clk ( clk ), + .cen ( pxl_cen ), + .data ( 8'd0 ), + .addr ( av_scan ), + .we ( 1'b0 ), + .q ( mem_msg_av ) +); + +reg av_col; + +always @(*) begin + av_col = av_sel1 == AVPOS; + msg_low = av_col ? mem_msg_av : mem_msg; +end +`else +always @(*) msg_low = mem_msg; +`endif + +assign msg_high = HVAL; + +endmodule \ No newline at end of file diff --git a/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/video/jtframe_credits.v b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/video/jtframe_credits.v new file mode 100644 index 0000000000000000000000000000000000000000..21453bdfd44f2db0ee86c91c0122357e937ebbfc --- /dev/null +++ b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/video/jtframe_credits.v @@ -0,0 +1,448 @@ +/* This file is part of JTFRAME. + JTFRAME program is free software: you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation, either version 3 of the License, or + (at your option) any later version. + + JTFRAME program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with JTFRAME. If not, see . + + Author: Jose Tejada Gomez. Twitter: @topapate + Version: 1.0 + Date: 14-3-2020 */ + +// 8x8 tiles + +module jtframe_credits #( + parameter PAGES = 1, + COLW = 4, // bits per pixel colour component + parameter [11:0] PAL0 = { 4'hf, 4'h0, 4'h0 }, // Red + parameter [11:0] PAL1 = { 4'h0, 4'hf, 4'h0 }, // Green + parameter [11:0] PAL2 = { 4'h3, 4'h3, 4'hf }, // Blue + parameter [11:0] PAL3 = { 4'hf, 4'hf, 4'hf }, // White + parameter BLKPOL = 1'b1, // Blanking polarity + parameter SPEED = 2 // scroll speed +) ( + input rst, + input clk, + + // input image + input pxl_cen, + input HB, + input VB, + input HS, + input VS, + input [COLW*3-1:0] rgb_in, + + // Optional VRAM control + input [7:0] vram_din, + input [9:0] vram_addr, + input vram_we, + output [7:0] vram_dout, + + // control + input enable, // shows the screen and resets the scroll counter + input toggle, // disables the screen. Only has an effect if enable is high + input [2:0] vram_ctrl, + input fast_scroll, + input [1:0] rotate, + + // output image + output reg HB_out, + output reg VB_out, + output reg HS_out, + output reg VS_out, + output reg [COLW*3-1:0] rgb_out +); + +localparam MSGW = PAGES == 1 ? 10 : + (PAGES == 2 ? 11 : + (PAGES > 2 && PAGES <=4 ? 12 : + (PAGES > 5 && PAGES <=8 ? 13 : 14 ))); // Support for upto 16 pages +localparam VPOSW = MSGW-2; +localparam HPOSW = 9; +localparam _MAXVISIBLE = PAGES*32*8-1; // workaround to avoid a warning +localparam [VPOSW-1:0] MAXVISIBLE = _MAXVISIBLE[VPOSW-1:0]; + +`ifndef JTFRAME_CREDITS_HSTART + localparam [HPOSW-1:0] HOFFSET=0; +`else + localparam [HPOSW-1:0] HOFFSET=`JTFRAME_CREDITS_HSTART; +`endif + +localparam [HPOSW-1:0] HSTART= 0, + HEND = 'h102; + +reg [HPOSW-1:0] hn; +wire [HPOSW-1:0] hscan; +reg [VPOSW-1:0] scrpos, vdump, vdump1; +reg [8:0] vrender; +wire [8:0] scan_data; +wire [7:0] font_data; +reg [MSGW-1:0] scan_addr; +wire [2:0] font_row = rotate==2'b11 ? (~vdump[2:0]+3'd1) : vdump[2:0]; +wire visible = vrender < MAXVISIBLE; +reg last_toggle, last_enable; +reg show, hide; +wire vram_mode = vram_ctrl[0]; +wire vram_nc; + +assign hscan = hn - HOFFSET; + +jtframe_dual_ram #(.DW(9), .AW(MSGW),.SYNFILE("msg.bin"),.ASCII_BIN(1)) u_msg( + .clk0 ( clk ), + .clk1 ( clk ), + // Port 0: optional write access + .data0 ( {1'b1, vram_din } ), + .addr0 ( { {MSGW-10{1'b0}}, vram_addr } ), + .we0 ( vram_we ), + .q0 ( { vram_nc, vram_dout } ), + // Port 1: video dump + .data1 ( 9'd0 ), + .addr1 ( scan_addr ), + .we1 ( 1'b0 ), + .q1 ( scan_data ) +); + +jtframe_font u_font( + .clk ( clk ), + .ascii ( scan_data[6:0] ), + .v ( font_row ), + .pxl ( font_data ) +); + +reg [1:0] pal; +reg [2:0] pxl; + +localparam MULTIPAGE = MSGW > 10; + +// hb and vb are always active high +wire hb = BLKPOL ? HB : ~HB; +wire vb = BLKPOL ? VB : ~VB; +reg [7:0] pxl_data; +wire tate = rotate[0], + tate_flip = rotate==2'b11; + +reg last_hb, last_vb; +reg [3:0] scr_base; + +wire hb_edge = hb && !last_hb; + +always @(posedge clk) if(pxl_cen) begin + if( tate || hb_edge ) begin + vdump1 <= scrpos + (tate ? hscan : vrender); + vdump <= vdump1; + end +end + +wire [VPOSW-1:3] vidx_flip = (~vdump[VPOSW-1:3])+1'd1; + +always @(posedge clk) begin + if( rst ) begin + hn <= HSTART; + scrpos <= {VPOSW{1'b0}}; + vrender <= 8'd0; + scr_base <= 4'd0; + end else if(pxl_cen) begin + last_hb <= hb; + last_vb <= vb; + if( hb_edge ) begin + vrender <= vrender + 8'd1; + end + hn <= hb ? HSTART : hn+9'd1; + // scrpos: scroll counter + // gets reset each time the pause button is pressed + if( enable && !last_enable ) begin + scrpos <= tate_flip ? MAXVISIBLE : {VPOSW{1'b0}}; + end else begin + if ( vb ) begin + vrender <= 0; + if( !last_vb && MULTIPAGE ) begin + // Scroll runs at max speed when the visible pages are over + // otherwise it runs at SPEED + if( scr_base == SPEED || scrpos>MAXVISIBLE || fast_scroll ) begin + scrpos <= tate_flip ? (scrpos-1'b1) : (scrpos + 1'b1); + scr_base <= 4'd0; + end else scr_base <= scr_base + 4'd1; + end + end + end + if( vram_mode ) scrpos <= 0; + //if( /*tate || hn[2:0]==3'd0 || hb || vb ) begin + scan_addr <= tate ? + { rotate[1] ? vidx_flip : vdump[VPOSW-1:3], vrender[7:3]^{5{~rotate[1]}} } : + { vdump[VPOSW-1:3], hscan[7:3] }; + //end + // Draw + if( tate ) begin + pxl <= { scan_data[8:7], font_data[ vrender[2:0] ^{3{rotate[1]}} ] }; + end else begin + pxl <= { pal, pxl_data[7] }; + if( hscan[2:0]==3'd1 ) begin + pal <= scan_data[8:7]; + pxl_data <= font_data; + end else begin + pxl_data <= pxl_data << 1; + end + end + end +end + +////////////////////////////////////////////////////////////////////////////// +// Object Generator + + +`ifdef JTFRAME_AVATARS +reg [ 7:0] buf_din; +reg buf_we0, buf_we1; +reg [ 7:0] buf_addr0; + +reg [11:0] lut_addr; +wire [ 7:0] lut_data; + +reg [12:0] obj_addr; +wire [15:0] obj_data; + +wire [ 7:0] pal_addr; +wire [11:0] pal_data; +reg [11:0] obj_pxl; +reg [ 7:0] obj_id, obj_x, obj_y; + +reg line = 1'b0; + +jtframe_dual_ram #(.DW(8), .AW(9)) u_linebuffer( + .clk0 ( clk ), + .clk1 ( clk ), + // Port 0: new data writes + .data0 ( buf_din ), + .addr0 ( { line, buf_addr0 } ), + .we0 ( buf_we0 ), + .q0 ( ), + // Port 1 + .data1 ( ~8'd0 ), + .addr1 ( { ~line, hscan[7:0] } ), + .we1 ( buf_we1 ), + .q1 ( pal_addr ) +); + +jtframe_ram #(.DW(8), .AW(12),.SYNFILE("lut.hex")) u_lut( + .clk ( clk ), + .cen ( 1'b1 ), + .data ( 8'd0 ), + .addr ( lut_addr ), + .we ( 1'b0 ), + .q ( lut_data ) +); + +jtframe_ram #(.DW(16), .AW(13),.SYNFILE("avatar.hex")) u_obj( + .clk ( clk ), + .cen ( 1'b1 ), + .data ( 16'd0 ), + .addr ( obj_addr ), + .we ( 1'b0 ), + .q ( obj_data ) +); + +jtframe_ram #(.DW(12), .AW(4+4),.SYNFILE("avatar_pal.hex")) u_pal( + .clk ( clk ), + .cen ( 1'b1 ), + .data ( 12'd0 ), + .addr ( pal_addr ), + .we ( 1'b0 ), + .q ( pal_data ) +); + +wire [VPOSW-1:0] vsub = vdump1 - { lut_data, 3'b0 }; +reg [3:0] obj_pal; +reg [3:0] x,y,z,w; + +reg [4:0] st; +reg first; + +reg last_hb2; // this is one is not gated by pxl_cen + +always @(posedge clk) begin + last_hb2 <= hb; + if( hb && !last_hb2 ) begin + lut_addr <= 12'd0; + first <= 1'b1; + st <= 0; + line <= ~line; + buf_we0 <= 1'b0; + buf_addr0<= 8'd0; + end else begin + st <= st+1; + case( st ) + 0: begin + if( lut_addr==12'd0 && !first ) st <= 0; + end + 1: begin + lut_addr <= lut_addr + 12'd1; + first <= 1'b0; + end + 2: begin + lut_addr <= lut_addr + 12'd1; + obj_id <= lut_data; + end + 3: begin + lut_addr <= lut_addr + 12'd1; + obj_x <= lut_data; + end + 4: begin + lut_addr <= lut_addr + 12'd1; + obj_y <= lut_data; + obj_addr <= { obj_id[6:0], vsub[3:0], 2'b0 }; // 7+4+2 = 13 + if( !({lut_data,3'b0} <= vdump1 && {lut_data,3'b0}+16 > vdump1) ) st <= 0; + if( obj_id==8'hff ) begin // end of LUT + lut_addr <= 12'd0; + st <= 0; + end + end + 5: obj_pal <= lut_data; + 6: begin + buf_addr0 <= { obj_x-8'd1, 3'b111 }; + {z,y,x,w} <= obj_data; + obj_addr[1:0] <= 2'b01; + end + 7,8,9,10, 12,13,14,15, + 17,18,19,20, 22,23,24,25: begin + buf_addr0 <= buf_addr0 + 1; + // xywz + // wxyz + // zyxw + // zywx + // zwyx + // zwxy + buf_din <= { obj_pal, z[3],y[3],x[3],w[3] }; + buf_we0 <= 1'b1; + obj_x <= obj_x + 1; + x <= x << 1; + y <= y << 1; + z <= z << 1; + w <= w << 1; + end + 11: begin + {z,y,x,w} <= obj_data; + obj_addr[1:0] <= 2'b10; + end + 16: begin + {z,y,x,w} <= obj_data; + obj_addr[1:0] <= 2'b11; + end + 21: {z,y,x,w} <= obj_data; + 26: begin + buf_we0<= 1'b0; + st <= 0; + end + endcase + end +end + +reg rd=1'b0; +reg [ 2:0] st2=3'd0; +reg obj_ok; + +always @(posedge clk ) begin + st2 <= st2+1; + case( st2 ) + 3: begin + obj_pxl <= pal_data; + obj_ok <= pal_addr[3:0] != 4'hf; // visible pixel + buf_we1 <= !hscan[8]; // do not empty the line buffer when + // scanning the left side of the screen + // This applies when JTFRAME_CREDITS_HSTART!=0 + end + 4: begin + buf_we1 <= 1'b0; + if( pxl_cen ) st2 <= 0; else st2 <= 4; + end + endcase +end + +`else +wire [11:0] obj_pxl = ~12'h0; +wire obj_ok = 1'b0; +`endif + +///////////////////////////////////////////////////////////////////////////// +// Colour Mixer +// Merge the new image with the old +localparam R1 = COLW*3-1; +localparam R0 = COLW*2; +localparam G1 = COLW*2-1; +localparam G0 = COLW; +localparam B1 = COLW-1; +localparam B0 = 0; + +wire [COLW*3-1:0] dim = { 1'b0, rgb_in[R1:R0+1], 1'b0, rgb_in[G1:G0+1], 1'b0, rgb_in[B1:B0+1] }; + +// COLW must be >= 4 +reg [7:0] b; + +function [COLW*3-1:0] extend; + input [11:0] rgb4; + begin + b = {2{rgb4[3:0]}}; + extend[COLW*3-1-:8] = {2{rgb4[11:8]}}; + extend[COLW*2-1-:8] = {2{rgb4[ 7:4]}}; + extend[COLW*1-1: 0] = b[7-:COLW]; + end +endfunction + +always @(posedge clk, posedge rst) begin + if( rst ) begin + show <= 0; + hide <= 0; + last_toggle <= 0; + last_enable <= 0; + end else begin + last_enable <= enable; + last_toggle <= toggle; + if( enable ) begin + if( vram_mode ) begin + show <= 1; + hide <= 0; + end else begin + show <= ~hide; + if( toggle && !last_toggle ) begin + hide <= ~hide; + end + end + end else show <= 0; + end +end + +always @(posedge clk) if(pxl_cen) begin + { HB_out, VB_out, HS_out, VS_out } <= { HB, VB, HS, VS }; + // if HOFFSET != 0 and the game is vertical, the full horizontal length + // of the screen is used. Otherwise, the credits will start at HOFFSET + // and last for 256 pixels + if( !show || ( HOFFSET!=0 && !tate && (hn=(HEND+HOFFSET))) ) + rgb_out <= rgb_in; + else begin + if( (!pxl[0] && (!obj_ok || vram_mode)) || !visible ) begin + if( vram_ctrl[0] ) begin + rgb_out <= (vdump[7] ? vram_ctrl[2] : vram_ctrl[1]) ? dim : rgb_in; + end else begin + rgb_out <= dim; + end + end else begin + if( pxl[0] || tate ) begin // CHAR, OBJ disabled for TATE + case( pxl[2:1] ) + 2'd0: rgb_out <= extend(PAL0); + 2'd1: rgb_out <= extend(PAL1); + 2'd2: rgb_out <= extend(PAL2); + 2'd3: rgb_out <= extend(PAL3); + endcase + end else rgb_out <= extend(obj_pxl); // OBJ + end + if( vb || hb ) rgb_out <= 0; + end +end + +endmodule \ No newline at end of file diff --git a/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/video/jtframe_draw.v b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/video/jtframe_draw.v new file mode 100644 index 0000000000000000000000000000000000000000..bd894d4100a87c7a78bbf09cb737edfd7fa0a234 --- /dev/null +++ b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/video/jtframe_draw.v @@ -0,0 +1,147 @@ +/* This file is part of JTFRAME. + JTFRAME program is free software: you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation, either version 3 of the License, or + (at your option) any later version. + + JTFRAME program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with JTFRAME. If not, see . + + Author: Jose Tejada Gomez. Twitter: @topapate + Version: 1.0 + Date: 18-12-2022 */ + +// Draws one line of a 16x16 tile +// It could be extended to 32x32 easily + +module jtframe_draw#( parameter + AW = 9, // Buffer with + CW = 12, // code width + PW = 8, // pixel width (lower four bits come from ROM) + ZW = 6, // zoom step width + ZI = ZW-1, // integer part of the zoom, use for enlarging. ZI=ZW-1=no enlarging + ZENLARGE = 0, // enable zoom enlarging + SWAPH = 0, // swaps the two horizontal halves of the tile + KEEP_OLD = 0 // slows down drawing to be compatible with jtframe_obj_buffer's KEEP_OLD parameter +)( + input rst, + input clk, + + input draw, + output reg busy, + input [CW-1:0] code, + input [AW-1:0] xpos, + input [ 3:0] ysub, + input [ 1:0] trunc, // 00=no trunc, 10 = 8 pixels, 11 = 4 pixels + + // optional zoom, keep at zero for no zoom + input [ZW-1:0] hzoom, + input hz_keep, // set to 0 on the first tile of a multi-tile + // sprite, 1 for the rest of the tiles + input hflip, + input vflip, + input [PW-5:0] pal, + + output [CW+6:2] rom_addr, // HVVVV format + output reg rom_cs, + input rom_ok, + input [31:0] rom_data, // leftmost pixel in LSB + // one plane per byte + + output reg [AW-1:0] buf_addr, + output buf_we, + output [PW-1:0] buf_din +); + +localparam [ZW-1:0] HZONE = { {ZW-1{1'b0}},1'b1} << ZI; + +reg [31:0] pxl_data; +reg rom_lsb; +reg [ 3:0] cnt; +wire [ 3:0] ysubf, pxl; +reg [ZW-1:0] hz_cnt, nx_hz; +wire [ZW-1:ZI] hzint; +reg cen=0, moveon, readon, no_zoom; + +assign ysubf = ysub^{4{vflip}}; +assign buf_din = { pal, pxl }; +assign pxl = hflip ? + { pxl_data[31], pxl_data[23], pxl_data[15], pxl_data[ 7] } : + { pxl_data[24], pxl_data[16], pxl_data[ 8], pxl_data[ 0] }; + +assign rom_addr = { code, rom_lsb^SWAPH[0], ysubf[3:0] }; +assign buf_we = busy & ~cnt[3]; +assign hzint = hz_cnt[ZW-1:ZI]; + +always @* begin + if( ZENLARGE==1 ) begin + readon = hzint >= 1; // tile pixels read (reduce) + moveon = hzint <= 1; // buffer moves (enlarge) + nx_hz = readon ? hz_cnt - HZONE : hz_cnt; + if( moveon ) nx_hz = nx_hz + hzoom; + if( no_zoom ) {moveon, readon} = 2'b11; + end else begin + readon = 1; + { moveon, nx_hz } = {1'b1, hz_cnt}-{1'b0,hzoom}; + end +end + +always @(posedge clk) cen <= ~cen; + +always @(posedge clk) begin + if( rst ) begin + rom_cs <= 0; + buf_addr <= 0; + pxl_data <= 0; + busy <= 0; + cnt <= 0; + hz_cnt <= 0; + no_zoom <= 0; + end else begin + if( !busy ) begin + if( draw ) begin + rom_lsb <= hflip; + rom_cs <= 1; + busy <= 1; + cnt <= 8; + no_zoom <= hzoom == HZONE || hzoom == 0; // zoom=0 is not valid. Makes counts keep going and busy stays forever. Check simpsons/scene 32 + if( !hz_keep ) begin + hz_cnt <= HZONE >> 1; + buf_addr <= xpos; + end + end + end else if(KEEP_OLD==0 || cen || cnt[3] ) begin + // cen is required when old buffer data must be preserved but it + // slows down the process. That wait is not needed while cnt[3] + // is high, so it can be used to gain back some time + if( rom_ok && rom_cs && cnt[3]) begin + pxl_data <= rom_data; + cnt[3] <= 0; + if( rom_lsb^hflip ) begin + rom_cs <= 0; + end else begin + rom_cs <= 1; + end + end + if( !cnt[3] ) begin + hz_cnt <= nx_hz; + if( readon ) begin + cnt <= cnt+1'd1; + pxl_data <= hflip ? pxl_data << 1 : pxl_data >> 1; + end + if( moveon ) buf_addr <= buf_addr+1'd1; + rom_lsb <= ~hflip; + if( cnt[2:0]==7 && !rom_cs && readon ) busy <= 0; // 16 pixels + if( cnt[2:0]==7 && trunc==2'b10 ) busy <= 0; // 8 pixels + if( cnt[1:0]==3 && trunc==2'b11 ) busy <= 0; // 4 pixels + end + end + end +end + +endmodule \ No newline at end of file diff --git a/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/video/jtframe_font.v b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/video/jtframe_font.v new file mode 100644 index 0000000000000000000000000000000000000000..181f34eba3ef44454b8e66ae3f5db4a2df8a199d --- /dev/null +++ b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/video/jtframe_font.v @@ -0,0 +1,37 @@ +/* This file is part of JTFRAME. + JTFRAME program is free software: you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation, either version 3 of the License, or + (at your option) any later version. + + JTFRAME program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with JTFRAME. If not, see . + + Author: Jose Tejada Gomez. Twitter: @topapate + Version: 1.0 + Date: 25-1-2025 */ + +module jtframe_font( + input clk, + input [6:0] ascii, + input [2:0] v, + output [7:0] pxl +); + +wire [9:0] addr = {ascii,v}; + +jtframe_ram #(.AW(10),.SYNFILE("font0.hex")) u_font( + .clk ( clk ), + .cen ( 1'b1 ), + .data ( 8'd0 ), + .addr ( addr ), + .we ( 1'b0 ), + .q ( pxl ) +); + +endmodule \ No newline at end of file diff --git a/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/video/jtframe_framebuf.v b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/video/jtframe_framebuf.v new file mode 100644 index 0000000000000000000000000000000000000000..28dbd5c2d955a87ecfd2ccc425998e4ff4302258 --- /dev/null +++ b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/video/jtframe_framebuf.v @@ -0,0 +1,72 @@ +/* This file is part of JTCORES. + JTCORES program is free software: you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation, either version 3 of the License, or + (at your option) any later version. + + JTCORES program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with JTCORES. If not, see . + + Author: Jose Tejada Gomez. Twitter: @topapate + Version: 1.0 + Date: 2-1-2025 */ + +// jtframe_framebuf copies the contents of a memory, normally an object LUT, +// at each vertical blank. It provides access to the data copied during the +// previous frame. +module jtframe_framebuf #(parameter AW=10,DW=8)( + input clk, + input lvbl, + output reg [AW-1:0] dma_addr, + input [DW-1:0] dma_data, + output reg busy=0, + + input [AW-1:0] rd_addr, + output [DW-1:0] rd_data +); + +reg lvbl_l=0, odd=0, even=0, cen=0; +wire [AW:0] nx_addr; +wire we; + +assign nx_addr = {1'b1,dma_addr}+1'd1; +assign we = busy & cen; + +always @(posedge clk) begin + cen <= ~cen; +end + +always @(posedge clk) if(cen) begin + lvbl_l <= lvbl; + if( !lvbl && lvbl_l ) begin + busy <= 1; + dma_addr <= 0; + odd <= ~odd; + even <= odd; + end + if( busy ) begin + {busy,dma_addr}<=nx_addr; + end +end + +jtframe_dual_ram #(.DW(DW),.AW(AW+1))u_buffer( + // Port 0 - writes + .clk0 ( clk ), + .data0 ( dma_data ), + .addr0 ({odd,dma_addr}), + .we0 ( we ), + .q0 ( ), + // Port 1 - reads + .clk1 ( clk ), + .data1 ( {DW{1'b0}}), + .addr1 ({even,rd_addr}), + .we1 ( 1'b0 ), + .q1 ( rd_data ) +); + +endmodule diff --git a/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/video/jtframe_hexdisplay.v b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/video/jtframe_hexdisplay.v new file mode 100644 index 0000000000000000000000000000000000000000..853997f7b46f827560d083cbb9b4fe5496844b05 --- /dev/null +++ b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/video/jtframe_hexdisplay.v @@ -0,0 +1,84 @@ +/* This file is part of JTFRAME. + JTFRAME program is free software: you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation, either version 3 of the License, or + (at your option) any later version. + + JTFRAME program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with JTFRAME. If not, see . + + Author: Jose Tejada Gomez. Twitter: @topapate + Version: 1.0 + Date: 8-5-2021 */ + +module jtframe_hexdisplay #( + parameter [8:0] LENBYTES=8, // Number of bytes to display + H0, // Display positions + V0 // only supports one row +) ( + input clk, + input pxl_cen, + input [8:0] hcnt, + input [8:0] vcnt, + input [(LENBYTES<<3)-1:0] data, + output reg pxl +); + +reg [19:0] font [0:15]; // 4x5 font +wire [ 3:0] display_nibble_bus, display_nibble_view; +reg [ 4:0] font_pixel; +wire [19:0] char; +wire [ 3:0] nibble; +wire inhzone, invzone; +reg [(LENBYTES<<3)-1:0] ser; + +localparam [8:0] HOVER = H0 + (LENBYTES<<4); + +assign nibble = ser[(LENBYTES<<3)-1-:4]; +assign char = font[ nibble ]; +assign inhzone = hcnt[8:3]= H0[8:3]; +assign invzone = vcnt[8:3]==V0[8:3] && vcnt[2:0]<5; + +// Inspired by TIC computer 6x6 font by nesbox +// https://fontstruct.com/fontstructions/show/1334143/tic-computer-6x6-font +initial begin + font[4'd00] = 20'b0110_1001_1001_1001_0110; // MSB is the bottom row + font[4'd01] = 20'b0111_0010_0010_0110_0010; + font[4'd02] = 20'b1111_1000_0110_0001_1110; + font[4'd03] = 20'b1110_0001_0110_0001_1111; + font[4'd04] = 20'b0010_1111_1010_1010_0010; + font[4'd05] = 20'b1110_0001_1110_1000_1111; + font[4'd06] = 20'b0110_1001_1110_1000_0110; + font[4'd07] = 20'b0100_0100_0010_0001_1111; + font[4'd08] = 20'b0110_1001_0110_1001_0110; + font[4'd09] = 20'b0110_0001_0111_1001_0110; + font[4'd10] = 20'b1001_1111_1001_1001_0110; + font[4'd11] = 20'b1110_1001_1110_1001_1110; + font[4'd12] = 20'b0111_1000_1000_1000_0111; + font[4'd13] = 20'b1110_1001_1001_1001_1110; + font[4'd14] = 20'b1111_1000_1110_1000_1111; + font[4'd15] = 20'b1000_1000_1110_1000_1111; +end + +always @(posedge clk) begin + font_pixel <= { vcnt[2:0], ~hcnt[1:0] }; + + if( !inhzone ) + ser <= data; + + if( pxl_cen ) begin + if( inhzone && invzone ) begin + pxl <= hcnt[2:0]< 4 ? char[ font_pixel ] : 1'b0; + if( &hcnt[2:0] ) ser <= ser<<4; // get next nibble ready + end else begin + pxl <= 0; + end + end +end + +endmodule \ No newline at end of file diff --git a/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/video/jtframe_hsize.v b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/video/jtframe_hsize.v new file mode 100644 index 0000000000000000000000000000000000000000..cb507239412b9162e9f784919be8751c7e461fd4 --- /dev/null +++ b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/video/jtframe_hsize.v @@ -0,0 +1,123 @@ +/* This file is part of JTFRAME. + JTFRAME program is free software: you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation, either version 3 of the License, or + (at your option) any later version. + + JTFRAME program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with JTFRAME. If not, see . + + Author: Jose Tejada Gomez. Twitter: @topapate + Version: 1.0 + Date: 1-8-2021 */ + +// Applies horizontal scaling to an analogue signal + +module jtframe_hsize #( parameter + COLORW =4 // bits per colour + //VIDEO_WIDTH=256 // screen pixel width (excluding blanking) +) ( + input clk, + input pxl_cen, + input pxl2_cen, + + input [3:0] scale, + input [4:0] offset, + input enable, + + input [COLORW-1:0] r_in, + input [COLORW-1:0] g_in, + input [COLORW-1:0] b_in, + input HS_in, + input VS_in, + input HB_in, + input VB_in, + // filtered video + output reg HS_out, + output reg VS_out, + output reg HB_out, + output reg VB_out, + output reg [COLORW-1:0] r_out, + output reg [COLORW-1:0] g_out, + output reg [COLORW-1:0] b_out +); + +//localparam VW = VIDEO_WIDTH <= 256 ? 9 : (VIDEO_WIDTH <= 512 ? 9 : 10); +localparam VW = 9; // Max 512 pixels including blanking +localparam SW = 8; + +wire [ VW+SW-2:0] summand; +wire [COLORW*3-1:0] rgb_out, rgb_in; +reg [ VW:0] rdcnt_l=0, rdcnt=0,rgbcnt_i=0; +reg [ SW-2:0] rdfrac=0,rgbfrac=0; +reg [ VW-1:0] hb0, hb1; +reg [ VW-1:0] wrcnt, rgbcnt, hmax; + +reg VSl, HSl, LHBl, LHBll, VBl, pass, over; + +assign rgb_in = {r_in, g_in, b_in}; +assign summand = {{VW{1'b0}},~scale[3],{SW-6{scale[3]}},scale}; + +always @(posedge clk) if(pxl_cen) begin + HSl <= HS_in; + LHBl <= ~HB_in; + LHBll <= LHBl; + HB_out <= HB_in; + HS_out <= HS_in; + VB_out <= VB_in; + + // VB must be adjusted to prevent the bottom line from being washed out + if( ~HB_in & ~LHBl ) {VB_out, VBl} <= {VBl, VB_in}; + if( HS_in & ~HSl ) begin + wrcnt <= 0; + hmax <= wrcnt; + VSl <= VS_in; + VS_out <= VSl; + end else begin + wrcnt <= wrcnt + 1'd1; + end + if( !enable) begin + VB_out <= VB_in; + VS_out <= VS_in; + end + // Register when HB toggles + if( LHBl & ~LHBll ) hb1 <= wrcnt; + if( HB_in & LHBl ) hb0 <= wrcnt; + // colour output + {r_out,g_out,b_out} <= enable ? (!HB_out && pass ? rgb_out : {3*COLORW{1'b0}}) : rgb_in; +end + +always @(posedge clk) if(pxl2_cen) begin + {rdcnt,rdfrac} <= {rdcnt,rdfrac} + {1'b0,summand}; + pass <= (rgbcnt <= hb0) && (rgbcnt >= hb1); + if( ~HS_in & HSl) over <= 1; + if( HS_in & ~HSl & over) begin + {rdcnt,rdfrac} <= { {VW-4{offset[4]}}, offset,{SW-1{1'b0}} }; + rdcnt_l <= rdcnt; + rgbcnt <= rgbcnt_i[VW-1:0]; + rgbfrac <= 0; + rgbcnt_i <= ({1'b0,hmax}-rdcnt_l)>>1; + over <= 0; //Avoids this step being done twice in the same HS + end else begin + {rgbcnt,rgbfrac} <= {rgbcnt,rgbfrac} + summand; + end +end + +jtframe_linebuf #(.DW(COLORW*3), .AW(VW)) u_line( + .clk ( clk ), + .LHBL (~HS_in ), + // Port 0: writes + .wr_data ( rgb_in ), + .wr_addr ( wrcnt ), + .we ( pxl_cen ), + // Port 1 + .rd_addr (rgbcnt), + .rd_gated ( ), + .rd_data ( rgb_out ) + ); +endmodule \ No newline at end of file diff --git a/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/video/jtframe_lfbuf_bram.v b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/video/jtframe_lfbuf_bram.v new file mode 100644 index 0000000000000000000000000000000000000000..79dafd223d0d4eb49dec1723cbb71971b4db38a3 --- /dev/null +++ b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/video/jtframe_lfbuf_bram.v @@ -0,0 +1,127 @@ +/* This file is part of JTFRAME. + JTFRAME program is free software: you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation, either version 3 of the License, or + (at your option) any later version. + + JTFRAME program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with JTFRAME. If not, see . + + Author: Jose Tejada Gomez. Twitter: @topapate + Version: 1.0 + Date: 30-10-2022 + + Adapted by @somhi for BRAM memory (tested in cyclone IV GX150 target) + Date: 23-12-2023 */ + +// Frame buffer built on top of two line buffers + +// This module is not fully tested yet +module jtframe_lfbuf_bram #(parameter + DW = 16, + VW = 8, + HW = 9 +)( + input rst, // hold in reset for >150 us + input clk, + input pxl_cen, + + // video status + input [VW-1:0] vrender, + input [HW-1:0] hdump, + input hs, + input vs, + input lhbl, + input lvbl, + + // core interface + input [HW-1:0] ln_addr, + input [DW-1:0] ln_data, + input ln_done, + input ln_we, + output ln_hs, ln_vs, ln_lvbl, + output [DW-1:0] ln_pxl, + output [VW-1:0] ln_v, + + // Status + input [7:0] st_addr, + output [7:0] st_dout +); + +wire frame, fb_clr, fb_done, line, scr_we; +wire [HW-1:0] fb_addr, rd_addr; +wire [ 15:0] fb_din, fb_dout; + +jtframe_lfbuf_bram_ctrl #(.HW(HW),.VW(VW)) u_ctrl ( + .rst ( rst ), + .clk ( clk ), + .pxl_cen ( pxl_cen ), + + .lhbl ( lhbl ), + .vs ( vs ), + .ln_done ( ln_done ), + .vrender ( vrender ), + .ln_v ( ln_v ), + // data written to external memory + .frame ( frame ), + .fb_blank ( fb_blank ), + .fb_addr ( fb_addr ), + .rd_addr ( rd_addr ), + .fb_din ( fb_din ), + .fb_dout ( fb_dout ), + .fb_clr ( fb_clr ), + .fb_done ( fb_done ), + + // data read from external memory to screen buffer + // during h blank + .line ( line ), + .scr_we ( scr_we ), + + .st_addr ( st_addr ), + .st_dout ( st_dout ) +); + +jtframe_lfbuf_line #(.DW(DW),.HW(HW),.VW(VW)) u_line( + .rst ( rst ), + .clk ( clk ), + .pxl_cen ( pxl_cen ), + + // video status + .vrender ( vrender ), + .hdump ( hdump ), + .hs ( hs ), + .vs ( vs ), // vertical sync, the buffer is swapped here + .lvbl ( lvbl ), // vertical blank, active low + + // core interface + .ln_hs ( ln_hs ), + .ln_v ( ln_v ), + .ln_vs ( ln_vs ), + .ln_lvbl ( ln_lvbl ), + .ln_addr ( ln_addr ), + .ln_data ( ln_data ), + .ln_we ( ln_we ), + .ln_pxl ( ln_pxl ), + + // data written to external memory + .frame ( frame ), + .fb_blank ( fb_blank ), + .fb_addr ( fb_addr ), + .rd_addr ( rd_addr ), + .fb_din ( fb_din ), + .fb_dout ( fb_dout ), + .fb_clr ( fb_clr ), + .fb_done ( fb_done ), + + // data read from external memory to screen buffer + // during h blank + .line ( line ), + .scr_we ( scr_we ) +); + +endmodule diff --git a/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/video/jtframe_lfbuf_bram_ctrl.v b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/video/jtframe_lfbuf_bram_ctrl.v new file mode 100644 index 0000000000000000000000000000000000000000..5789c3fa9a0041ce963950a65d10a9811b2207f3 --- /dev/null +++ b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/video/jtframe_lfbuf_bram_ctrl.v @@ -0,0 +1,196 @@ +/* This file is part of JTFRAME. + JTFRAME program is free software: you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation, either version 3 of the License, or + (at your option) any later version. + + JTFRAME program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with JTFRAME. If not, see . + + Author: Jose Tejada Gomez. Twitter: @topapate + Version: 1.0 + Date: 20-11-2022 + + Adapted by @somhi for BRAM memory (tested in cyclone IV GX150 target) + Date: 23-12-2023 */ + +module jtframe_lfbuf_bram_ctrl #(parameter + CLK96 = 0, // assume 48-ish MHz operation by default + VW = 8, + HW = 9 +)( + input rst, // hold in reset for >150 us + input clk, + input pxl_cen, + + input lhbl, + input ln_done, + input [VW-1:0] vrender, + input [VW-1:0] ln_v, + input vs, + // data written to external memory + input frame, + input fb_blank, + output reg [HW-1:0] fb_addr, + input [ 15:0] fb_din, + output reg fb_clr, + output reg fb_done, + + // data read from external memory to screen buffer + // during h blank + output [ 15:0] fb_dout, + output reg [HW-1:0] rd_addr, + output reg line, + output reg scr_we, + + // Status + input [7:0] st_addr, + output reg [7:0] st_dout +); + +localparam AW=HW+VW+1; +localparam [1:0] IDLE=0, READ=1, WRITE=2; + +reg vsl, lhbl_l, ln_done_l, do_wr; +reg [ 1:0] st; +reg [AW-1:0] act_addr; +wire [HW-1:0] nx_rd_addr; +reg [HW-1:0] hblen, hlim, hcnt; +wire fb_over; +reg bram_rd; + +reg [15:0] ram[(2**AW)-1:0]; +wire [20:0] bram_addr; +wire [15:0] bram_data; +reg [15:0] douta; +reg bram_we; + +always @(posedge clk) + if (~bram_we) + ram[bram_addr] <= bram_data; + else + douta <= ram[bram_addr]; + +assign fb_over = &fb_addr; +assign bram_addr = act_addr; +assign nx_rd_addr = rd_addr + 1'd1; +assign bram_data = bram_we ? 16'hzzzz : fb_din; +assign fb_dout = ~bram_we ? 16'd0 : douta; + +always @(posedge clk) begin + case( st_addr[3:0] ) + 0: st_dout <= { 2'd0, bram_we, bram_rd, 2'd0, st }; + 1: st_dout <= { 3'd0, frame, fb_done, 1'd0, 1'd0, line }; + 2: st_dout <= fb_din[7:0]; + 3: st_dout <= fb_din[15:8]; + 4: st_dout <= bram_data[7:0]; + 5: st_dout <= bram_data[15:8]; + 6: st_dout <= 0; + 7: st_dout <= 0; + 8: st_dout <= ln_v[7:0]; + 9: st_dout <= vrender[7:0]; + default: st_dout <= 0; + endcase +end + +always @( posedge clk ) begin + if( rst ) begin + hblen <= 0; + hlim <= 0; + hcnt <= 0; + lhbl_l <= 0; + vsl <= 0; + end else if(pxl_cen) begin + lhbl_l <= lhbl; + vsl <= vs; + hcnt <= hcnt+1'd1; + if( ~lhbl & lhbl_l ) begin // enters blanking + hcnt <= 0; + hlim <= hcnt - hblen; // H limit below which we allow do_wr events + end + if( lhbl & ~lhbl_l ) begin // leaves blanking + hblen <= hcnt; + end + end +end + +wire skip_blank_lines = do_wr && fb_blank; + +always @( posedge clk ) begin + if( rst ) begin + bram_we <= 1; + bram_rd <= 0; + fb_addr <= 0; + fb_clr <= 0; + fb_done <= 0; + act_addr <= 0; + rd_addr <= 0; + line <= 0; + scr_we <= 0; + ln_done_l<= 0; + do_wr <= 0; + st <= IDLE; + end else begin + fb_done <= 0; + ln_done_l <= ln_done; + if (ln_done && !ln_done_l ) do_wr <= 1; + if( fb_clr ) begin + // the line is cleared outside the state machine so a + // read operation can happen independently + fb_addr <= fb_addr + 1'd1; + if( fb_over ) begin + fb_clr <= 0; + end + end + case( st ) + IDLE: begin + bram_we <= 1; + bram_rd <= 0; + scr_we <= 0; + if( lhbl_l & ~lhbl ) begin + act_addr <= { ~frame, vrender, {HW{1'd0}} }; + bram_rd <= 1; + rd_addr <= 0; + scr_we <= 1; + st <= READ; + end else if( skip_blank_lines ) begin + fb_done <= 1; + do_wr <= 0; + end else if( do_wr && !fb_clr && + hcnt. + + Author: Jose Tejada Gomez. Twitter: @topapate + Version: 1.0 + Date: 30-10-2022 */ + +// Frame buffer built on top of two line buffers +// the frame is stored in two PSRAM chips + +// This module is not fully tested yet +module jtframe_lfbuf_cram #(parameter + DW = 16, + VW = 8, + HW = 9 +)( + input rst, // hold in reset for >150 us + input clk, + input pxl_cen, + + // video status + input [VW-1:0] vrender, + input [HW-1:0] hdump, + input hs, + input vs, + input lhbl, + input lvbl, + + // core interface + input [HW-1:0] ln_addr, + input [DW-1:0] ln_data, + input ln_done, + output ln_hs, ln_vs, ln_lvbl, + output [DW-1:0] ln_pxl, + output [VW-1:0] ln_v, + input ln_we, + + // PSRAM chip + output [ 21:16] cr_addr, + inout [ 15:0] cr_adq, + output cr_advn, + output [ 1:0] cr_cen, + output cr_clk, + output cr_cre, + output [ 1:0] cr_dsn, + output cr_oen, + input cr_wait, + output cr_wen +); + +wire frame, fb_clr, fb_done, line, scr_we, fb_blank; +wire [HW-1:0] fb_addr, rd_addr; +wire [ 15:0] fb_din, fb_dout; + +jtframe_lfbuf_ctrl #(.HW(HW),.VW(VW)) u_ctrl ( + .rst ( rst ), + .clk ( clk ), + .pxl_cen ( pxl_cen ), + + .lhbl ( lhbl ), + .vs ( vs ), + .ln_done ( ln_done ), + .vrender ( vrender ), + .ln_v ( ln_v ), + // data written to external memory + .frame ( frame ), + .fb_blank ( fb_blank ), + .fb_addr ( fb_addr ), + .rd_addr ( rd_addr ), + .fb_din ( fb_din ), + .fb_dout ( fb_dout ), + .fb_clr ( fb_clr ), + .fb_done ( fb_done ), + + // data read from external memory to screen buffer + // during h blank + .line ( line ), + .scr_we ( scr_we ), + + // cell RAM (PSRAM) signals + .cr_addr ( cr_addr ), + .cr_adq ( cr_adq ), + .cr_wait ( cr_wait ), + .cr_clk ( cr_clk ), + .cr_advn ( cr_advn ), + .cr_cre ( cr_cre ), + .cr_cen ( cr_cen ), + .cr_oen ( cr_oen ), + .cr_wen ( cr_wen ), + .cr_dsn ( cr_dsn ) +); + +jtframe_lfbuf_line #(.DW(DW),.HW(HW),.VW(VW)) u_line( + .rst ( rst ), + .clk ( clk ), + .pxl_cen ( pxl_cen ), + // video status + .vrender ( vrender ), + .hdump ( hdump ), + .hs ( hs ), + .vs ( vs ), // vertical sync, the buffer is swapped here + .lvbl ( lvbl ), // vertical blank, active low + + // core interface + .ln_hs ( ln_hs ), + .ln_v ( ln_v ), + .ln_vs ( ln_vs ), + .ln_lvbl ( ln_lvbl ), + .ln_addr ( ln_addr ), + .ln_data ( ln_data ), + .ln_we ( ln_we ), + .ln_pxl ( ln_pxl ), + + // data written to external memory + .frame ( frame ), + .fb_blank ( fb_blank ), + .fb_addr ( fb_addr ), + .rd_addr ( rd_addr ), + .fb_din ( fb_din ), + .fb_dout ( fb_dout ), + .fb_clr ( fb_clr ), + .fb_done ( fb_done ), + + // data read from external memory to screen buffer + // during h blank + .line ( line ), + .scr_we ( scr_we ) +); + +endmodule \ No newline at end of file diff --git a/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/video/jtframe_lfbuf_ctrl.v b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/video/jtframe_lfbuf_ctrl.v new file mode 100644 index 0000000000000000000000000000000000000000..bcc11b5e0538ec707b0a7bde85eab2d576aa8401 --- /dev/null +++ b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/video/jtframe_lfbuf_ctrl.v @@ -0,0 +1,288 @@ +/* This file is part of JTFRAME. + JTFRAME program is free software: you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation, either version 3 of the License, or + (at your option) any later version. + + JTFRAME program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with JTFRAME. If not, see . + + Author: Jose Tejada Gomez. Twitter: @topapate + Version: 1.0 + Date: 20-11-2022 */ + +module jtframe_lfbuf_ctrl #(parameter + CLK96 = 0, // assume 48-ish MHz operation by default + VW = 8, + HW = 9 +)( + input rst, // hold in reset for >150 us + input clk, + input pxl_cen, + + input lhbl, + input vs, + input ln_done, + input [VW-1:0] vrender, + input [VW-1:0] ln_v, + // data written to external memory + input frame, + input fb_blank, + output reg [HW-1:0] fb_addr, + input [ 15:0] fb_din, + output reg fb_clr, + output reg fb_done, + + // data read from external memory to screen buffer + // during h blank + output [ 15:0] fb_dout, + output reg [HW-1:0] rd_addr, + output reg line, + output scr_we, + + // cell RAM (PSRAM) signals + output reg [ 21:16] cr_addr, + inout [ 15:0] cr_adq, + input cr_wait, + output cr_clk, + output reg cr_advn, + output reg cr_cre, + output [ 1:0] cr_cen, // chip enable + output reg cr_oen, + output reg cr_wen, + output [ 1:0] cr_dsn +); + +localparam [3:0] INIT = { 3'd0, 1'd0 }, + IDLE = { 3'd1, 1'd0 }, + WRITE_ADDR = { 3'd2, 1'd0 }, + WRITEOUT = { 3'd2, 1'd1 }, + READ_ADDR = { 3'd4, 1'd0 }, + READIN = { 3'd4, 1'd1 }; + +localparam AW = HW+VW; + +localparam [21:0] BUS_CFG = { + 2'd0, // reserved + 2'd2, // bus configuration register + 2'd0, // reserved + 1'b0, // synchronous burst access + 1'b0, // variable latency + 3'd3, // default latency counter + 1'b0, // wait is active high + 1'b0, // reserved + 1'b0, // 1=wait set 1 clock ahead of data + 2'd0, // reserved + 2'd1, // drive strength (default) + 1'b1, // no burst wrap + 3'd7 // continuous burst +}, REF_CFG = { + 2'd0, // reserved + 2'd0, // refresh configuration register + 13'd0, // reserved + 1'b1, // deep power power down disabled + 1'd0, // reserved + 3'b100 // array not refreshed + // 1'b1, // use bottom half of the array (or all of it) + // AW == 21 ? 2'd0 : // full array (4096 x 16 bits = 64Mbit per chip half) + // AW == 20 ? 2'd1 : // half the array(2048 x 16 bits) + // AW == 19 ? 2'd2 : // 1/4 the array (1024 x 16 bits) + // 2'd3 // 1/8 the array (512k x 16 bits) +}; + +reg [ 3:0] st; +reg [ 4:0] cntup; // use a larger count to capture data using Signal Tap +wire [ 7:0] vram; // current row (v) being processed through the external RAM +reg [15:0] adq_reg; +reg [HW-1:0] hblen, hlim, hcnt, wr_addr; +reg lhbl_l, do_wr, wait1, adq_en, + csn, ln_done_l, vsl, startup; +wire fb_over; +wire wring; + +`ifdef SIMULATION +wire rding = st[3]; `endif +assign wring = st[2]; +assign cr_cen = { 1'b1, csn }; // I call it csn to avoid the confusion with the common cen (clock enable) signal +assign cr_dsn = 0; +assign fb_dout = cr_oen ? 16'd0 : cr_adq; +assign cr_adq =!cr_oen ? 16'hzzzz : adq_en ? adq_reg : fb_din; +assign cr_clk = clk; +assign fb_over =&fb_addr; +assign vram = lhbl ? ln_v : vrender; +assign scr_we = cr_wait & ~cr_oen; + +always @( posedge clk ) begin + if( rst ) begin + hblen <= 0; + hlim <= 0; + hcnt <= 0; + lhbl_l <= 0; + vsl <= 0; + cntup <= 0; + startup<= 0; + end else if(pxl_cen) begin + lhbl_l <= lhbl; + vsl <= vs; + hcnt <= hcnt+1'd1; + startup <= &cntup; + if( ~lhbl & lhbl_l ) begin // enters blanking + hcnt <= 0; + hlim <= hcnt - hblen; // H limit below which we allow do_wr events + end + if( lhbl & ~lhbl_l ) begin // leaves blanking + hblen <= hcnt; + end + if( vs & ~vsl & ~&cntup ) cntup <= cntup+1'd1; + end +end + +always @( posedge clk ) begin + if( rst ) begin + do_wr <= 0; + end else begin + ln_done_l <= ln_done; + if( ln_done & ~ln_done_l ) do_wr <= 1; + if( st==WRITEOUT && fb_over ) do_wr <= 0; + if( st==IDLE && skip_blank_lines ) do_wr <= 0; + end +end + +reg [4:0] init_seq[0:15]; +reg [4:0] init_cnt; + +initial begin + // cen, cre, advn, oen, wen + init_seq[ 0] = { 1'b1, 1'b1, 1'b1, 1'b1, 1'b1 }; + init_seq[ 1] = { 1'b0, 1'b1, 1'b0, 1'b1, 1'b1 }; // latch address + init_seq[ 2] = { 1'b0, 1'b0, 1'b1, 1'b1, 1'b1 }; + init_seq[ 3] = { 1'b0, 1'b0, 1'b1, 1'b1, 1'b0 }; // write starts + init_seq[ 4] = { 1'b0, 1'b0, 1'b1, 1'b1, 1'b0 }; + init_seq[ 5] = { 1'b0, 1'b0, 1'b1, 1'b1, 1'b0 }; // cfg written + // cen, cre, advn, oen, wen + init_seq[ 6] = { 1'b1, 1'b0, 1'b1, 1'b1, 1'b1 }; // read + init_seq[ 7] = { 1'b0, 1'b0, 1'b0, 1'b1, 1'b1 }; + init_seq[ 8] = { 1'b0, 1'b0, 1'b1, 1'b1, 1'b1 }; + init_seq[ 9] = { 1'b0, 1'b0, 1'b1, 1'b1, 1'b1 }; + init_seq[10] = { 1'b0, 1'b0, 1'b1, 1'b0, 1'b1 }; + init_seq[11] = { 1'b0, 1'b0, 1'b1, 1'b0, 1'b1 }; + init_seq[12] = { 1'b0, 1'b0, 1'b1, 1'b0, 1'b1 }; + init_seq[13] = { 1'b1, 1'b0, 1'b1, 1'b1, 1'b1 }; + // cen, cre, advn, oen, wen + init_seq[14] = { 1'b1, 1'b0, 1'b1, 1'b1, 1'b1 }; // idle + init_seq[15] = { 1'b1, 1'b0, 1'b1, 1'b1, 1'b1 }; +end + +wire skip_blank_lines = do_wr && fb_blank; + +always @( posedge clk ) begin + if( rst ) begin + st <= INIT; + cr_advn <= 0; + cr_oen <= 0; + cr_cre <= 0; + csn <= 0; + fb_addr <= 0; + fb_clr <= 0; + fb_done <= 0; + rd_addr <= 0; + line <= 0; + wait1 <= 0; + init_cnt <= 0; + adq_en <= 0; + end else begin + fb_done <= 0; + wait1 <= 0; + cr_advn <= 1; + if(!wait1) adq_en <= 0; + if( fb_clr ) begin + // the line is cleared outside the state machine so a + // read operation can happen independently + fb_addr <= fb_addr + 1'd1; + if( fb_over ) begin + fb_clr <= 0; + end + end + if( !startup ) begin + csn <= 1; + end else case( st ) + INIT: begin + case(init_cnt) + 1,2,7,8: adq_en <= 1; + default: adq_en <= 0; + endcase + if( init_cnt==0 ) { cr_addr, adq_reg } <= REF_CFG; + if( init_cnt==15 ) { cr_addr, adq_reg } <= BUS_CFG; + init_cnt <= init_cnt + 1'd1; + { csn, cr_cre, cr_advn, cr_oen, cr_wen } <= init_seq[init_cnt[3:0]]; + if( &init_cnt ) st <= IDLE; + end + // Wait for requests + IDLE: begin + csn <= 1; + cr_wen <= 1; + cr_cre <= 0; + adq_reg <= { vram[VW-6:0], {16+5-VW{1'b0}} }; + cr_addr <= { lhbl ^ frame, vram[VW-1-:5] }; + if( lhbl_l & ~lhbl ) begin + // it doesn't matter if vrender changes after the LHBL edge + // is set as it is latched in { cr_addr, adq_reg } + csn <= 0; + rd_addr <= 0; + cr_oen <= 1; + st <= READ_ADDR; + end else if( skip_blank_lines ) begin + fb_done <= 1; + end else if( do_wr && !fb_clr && + hcnt. + + Author: Jose Tejada Gomez. Twitter: @topapate + Version: 1.0 + Date: 30-10-2022 */ + +// Frame buffer built on top of two line buffers +/* verilator lint_off MODDUP */ +// This module is not fully tested yet +module jtframe_lfbuf_ddr #(parameter + DW = 16, + VW = 8, + HW = 9 +)( + input rst, // hold in reset for >150 us + input clk, + input pxl_cen, + + // video status + input [VW-1:0] vrender, + input [HW-1:0] hdump, + input hs, vs, + input lhbl, + input lvbl, + + // core interface + input [HW-1:0] ln_addr, + input [DW-1:0] ln_data, + input ln_done, + input ln_we, + output ln_hs, ln_vs, ln_lvbl, + output [DW-1:0] ln_pxl, + output [VW-1:0] ln_v, + + // DDR3 RAM + output ddram_clk, + input ddram_busy, + output [7:0] ddram_burstcnt, + output [28:0] ddram_addr, + input [63:0] ddram_dout, + input ddram_dout_ready, + output ddram_rd, + output [63:0] ddram_din, + output [7:0] ddram_be, + output ddram_we, + // Status + input [7:0] st_addr, + output [7:0] st_dout +); + +wire frame, fb_clr, fb_done, line, scr_we, fb_blank; +wire [HW-1:0] fb_addr, rd_addr; +wire [ 15:0] fb_din, fb_dout; + +jtframe_lfbuf_ddr_ctrl #(.HW(HW),.VW(VW)) u_ctrl ( + .rst ( rst ), + .clk ( clk ), + .pxl_cen ( pxl_cen ), + + .lhbl ( lhbl ), + .vs ( vs ), + .ln_done ( ln_done ), + .vrender ( vrender ), + .ln_v ( ln_v ), + // data written to external memory + .frame ( frame ), + .fb_blank ( fb_blank ), + .fb_addr ( fb_addr ), + .rd_addr ( rd_addr ), + .fb_din ( fb_din ), + .fb_dout ( fb_dout ), + .fb_clr ( fb_clr ), + .fb_done ( fb_done ), + + // data read from external memory to screen buffer + // during h blank + .line ( line ), + .scr_we ( scr_we ), + + .ddram_clk ( ddram_clk ), + .ddram_busy ( ddram_busy ), + .ddram_addr ( ddram_addr ), + .ddram_dout ( ddram_dout ), + .ddram_rd ( ddram_rd ), + .ddram_din ( ddram_din ), + .ddram_be ( ddram_be ), + .ddram_we ( ddram_we ), + .ddram_burstcnt ( ddram_burstcnt ), + .ddram_dout_ready( ddram_dout_ready ), + .st_addr ( st_addr ), + .st_dout ( st_dout ) +); + +jtframe_lfbuf_line #(.DW(DW),.HW(HW),.VW(VW)) u_line( + .rst ( rst ), + .clk ( clk ), + .pxl_cen ( pxl_cen ), + + // video status + .vrender ( vrender ), + .hdump ( hdump ), + .hs ( hs ), + .vs ( vs ), // vertical sync, the buffer is swapped here + .lvbl ( lvbl ), // vertical blank, active low + + // core interface + .ln_hs ( ln_hs ), + .ln_vs ( ln_vs ), + .ln_lvbl ( ln_lvbl ), + .ln_v ( ln_v ), + .ln_addr ( ln_addr ), + .ln_data ( ln_data ), + .ln_we ( ln_we ), + .ln_pxl ( ln_pxl ), + + // data written to external memory + .frame ( frame ), + .fb_addr ( fb_addr ), + .rd_addr ( rd_addr ), + .fb_din ( fb_din ), + .fb_dout ( fb_dout ), + .fb_clr ( fb_clr ), + .fb_done ( fb_done ), + .fb_blank ( fb_blank ), + + // data read from external memory to screen buffer + // during h blank + .line ( line ), + .scr_we ( scr_we ) +); + +endmodule \ No newline at end of file diff --git a/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/video/jtframe_lfbuf_ddr_ctrl.v b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/video/jtframe_lfbuf_ddr_ctrl.v new file mode 100644 index 0000000000000000000000000000000000000000..2282f90817333589822be32794d347f00b1488ad --- /dev/null +++ b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/video/jtframe_lfbuf_ddr_ctrl.v @@ -0,0 +1,199 @@ +/* This file is part of JTFRAME. + JTFRAME program is free software: you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation, either version 3 of the License, or + (at your option) any later version. + + JTFRAME program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with JTFRAME. If not, see . + + Author: Jose Tejada Gomez. Twitter: @topapate + Version: 1.0 + Date: 20-11-2022 */ +/* verilator lint_off MODDUP */ +module jtframe_lfbuf_ddr_ctrl #(parameter + CLK96 = 0, // assume 48-ish MHz operation by default + VW = 8, + HW = 9 +)( + input rst, // hold in reset for >150 us + input clk, + input pxl_cen, + + input lhbl, + input ln_done, + input [VW-1:0] vrender, + input [VW-1:0] ln_v, + input vs, + // data written to external memory + input frame, + input fb_blank, + output reg [HW-1:0] fb_addr, + input [ 15:0] fb_din, + output reg fb_clr, + output reg fb_done, + + // data read from external memory to screen buffer + // during h blank + output [ 15:0] fb_dout, + output reg [HW-1:0] rd_addr, + output reg line, + output reg scr_we, + + output ddram_clk, + input ddram_busy, + output [7:0] ddram_burstcnt, + output [31:3] ddram_addr, + input [63:0] ddram_dout, + input ddram_dout_ready, + output reg ddram_rd, + output [63:0] ddram_din, + output [7:0] ddram_be, + output reg ddram_we, + + // Status + input [7:0] st_addr, + output reg [7:0] st_dout +); + +localparam AW=HW+VW+1; +localparam [1:0] IDLE=0, READ=1, WRITE=2; + +reg lhbl_l, ln_done_l, do_wr; +reg [ 1:0] st; +reg [AW-1:0] act_addr; +wire [HW-1:0] nx_rd_addr; +reg [HW-1:0] hblen, hlim, hcnt; +wire fb_over; + +assign fb_over = &fb_addr; +assign ddram_clk = clk; +assign ddram_burstcnt = 8'h80; +assign ddram_addr = { 4'd3, {29-4-AW{1'd0}}, act_addr }; +assign ddram_din = { 48'd0, fb_din }; +assign ddram_be = 3; +assign nx_rd_addr = rd_addr + 1'd1; +assign fb_dout = ddram_dout[15:0]; + +always @(posedge clk) begin + case( st_addr[3:0] ) + 0: st_dout <= { 2'd0, ddram_we, ddram_rd, 2'd0, st }; + 1: st_dout <= { 3'd0, frame, fb_done, ddram_dout_ready, ddram_busy, line }; + 2: st_dout <= fb_din[7:0]; + 3: st_dout <= fb_din[15:8]; + 4: st_dout <= ddram_din[7:0]; + 5: st_dout <= ddram_din[15:8]; + 6: st_dout <= ddram_dout[7:0]; + 7: st_dout <= ddram_dout[15:8]; + 8: st_dout <= ln_v[7:0]; + 9: st_dout <= vrender[7:0]; + default: st_dout <= 0; + endcase +end + +always @( posedge clk ) begin + if( rst ) begin + hblen <= 0; + hlim <= 0; + hcnt <= 0; + lhbl_l <= 0; + end else if(pxl_cen) begin + lhbl_l <= lhbl; + hcnt <= hcnt+1'd1; + if( ~lhbl & lhbl_l ) begin // enters blanking + hcnt <= 0; + hlim <= hcnt - hblen; // H limit below which we allow do_wr events + end + if( lhbl & ~lhbl_l ) begin // leaves blanking + hblen <= hcnt; + end + end +end + +wire skip_blank_lines = do_wr && fb_blank; + +always @( posedge clk ) begin + if( rst ) begin + ddram_we <= 0; + ddram_rd <= 0; + fb_addr <= 0; + fb_clr <= 0; + fb_done <= 0; + act_addr <= 0; + rd_addr <= 0; + line <= 0; + scr_we <= 0; + ln_done_l<= 0; + do_wr <= 0; + st <= IDLE; + end else begin + fb_done <= 0; + ln_done_l <= ln_done; + if (ln_done && !ln_done_l) do_wr <= 1; + if( fb_clr ) begin + // the line is cleared outside the state machine so a + // read operation can happen independently + fb_addr <= fb_addr + 1'd1; + if( fb_over ) begin + fb_clr <= 0; + end + end + case( st ) + IDLE: begin + ddram_we <= 0; + ddram_rd <= 0; + scr_we <= 0; + if( lhbl_l & ~lhbl ) begin + act_addr <= { ~frame, vrender, {HW{1'd0}} }; + ddram_rd <= 1; + rd_addr <= 0; + scr_we <= 1; + st <= READ; + end else if( skip_blank_lines ) begin + fb_done <= 1; + do_wr <= 0; + end else if( do_wr && !fb_clr && + hcnt. + + Author: Jose Tejada Gomez. Twitter: @topapate + Version: 1.0 + Date: 30-10-2022 */ + +// Frame buffer built on top of two line buffers +// the frame buffer is assumed to be done on a 16-bit memory +// It uses 4x lines of internal BRAM. +// The idea is to use a regular object double line buffer to collect the line from the object processing unit +// at the same time, the previous line is dumped to the SDRAM +// in the mean time, one line is read from the SDRAM into another line buffer and +// the previous line is dumped from the same line buffer to the screen + +// This module is not fully tested yet +/* verilator lint_off MODDUP */ +module jtframe_lfbuf_line #(parameter + DW = 16, + VW = 8, + HW = 9 +)( + input rst, + input clk, + input pxl_cen, + // video status + input [VW-1:0] vrender, + input [HW-1:0] hdump, + input hs, + input vs, // vertical sync, the buffer is swapped here + input lvbl, // vertical blank, active low + + // core interface + output reg ln_hs, ln_vs, ln_lvbl, + output reg [VW-1:0] ln_v, + input [HW-1:0] ln_addr, + input [DW-1:0] ln_data, + input ln_we, + output reg [DW-1:0] ln_pxl, + + // data written to external memory + output reg frame, + input [HW-1:0] fb_addr, + input [HW-1:0] rd_addr, + output [ 15:0] fb_din, + input fb_clr, + input fb_done, + output fb_blank, + + // data read from external memory to screen buffer + // during h blank + input [ 15:0] fb_dout, + input line, + input scr_we +); + +reg vsl, lvbl_l, hs_l; +reg [ 5:0] porch; +reg [VW-1:0] vstart=0, vend=0; +wire [ 15:0] scr_pxl; +wire [ 5:0] vbs_len, vsy_len, vsa_len; +wire info_rdy; + +always @(posedge clk) if(pxl_cen) ln_pxl <= scr_pxl[DW-1:0]; + +`ifdef SIMULATION +initial begin + if( DW>16 ) begin + $display("jtframe_framebuf: cannot handle pixels of more than 16 bits"); + $finish; + end +end +`endif + +// Capture the vstart/vend values +always @(posedge clk) begin + hs_l <= hs; +end + +always @(posedge clk) begin + if( rst ) begin + lvbl_l <= 0; + end else begin + lvbl_l <= lvbl; + vsl <= vs; + if( !lvbl && lvbl_l ) begin + vend <= vrender; + end + if( lvbl && !lvbl_l ) begin + vstart <= vrender; + end + end +end + +jtframe_blank_length u_counter( + .rst ( rst ), + .clk ( clk ), + .pxl_cen ( pxl_cen ), + + .lhbl ( ~hs ), + .lvbl ( lvbl ), + .hs ( hs ), + .vs ( vs ), + + .v_len ( ), + .h_len ( ), + .hbs_len ( ), + .hsy_len ( ), + .hsa_len ( ), + .vbs_len ( vbs_len ), // V blank start to VS start + .vsy_len ( vsy_len ), // VS length + .vsa_len ( vsa_len ), // VS end to active video start + .rdy ( info_rdy ) // ready after two frames +); + +reg done; +wire active, // active video portion + vbs, // blank start to sync start + vsy, // sync start to end + vsa; // sync end to active start +reg [3:0] st; + +localparam [3:0] ACTIVE=4'b1_000, + VBTOSY=4'b0_001; + +`ifdef JTFRAME_LF_FULLV + assign {active,vsa,vsy,vbs} = st; + assign fb_blank = ~ln_lvbl; +`else + assign fb_blank = 0; + initial begin + ln_vs = 0; + ln_lvbl = 1; + end +`endif + +// count lines so objects get drawn in the line buffer +// and dumped from there to the SDRAM +always @(posedge clk, posedge rst) begin + if( rst ) begin + frame <= 0; + ln_hs <= 0; + ln_v <= 0; + done <= 0; + `ifdef JTFRAME_LF_FULLV + ln_vs <= 0; + ln_lvbl <= 0; + porch <= 0; + st <= 0; + `endif + end else if(info_rdy) begin + ln_hs <= 0; + if( vs && !vsl ) begin // object parsing starts during VB + frame <= ~frame; + ln_v <= vstart; + ln_hs <= 1; + done <= 0; + `ifdef JTFRAME_LF_FULLV + ln_lvbl <= 0; + porch <= vbs_len; + st <= VBTOSY; + `endif + end + if( fb_done && !done ) + `ifdef JTFRAME_LF_FULLV + if({vsa,vsy,vbs}!=0) begin + porch <= porch - 1'd1; + ln_hs <= 1; + if(porch==0) begin + porch <= vbs ? vsy_len : vsa_len; + ln_vs <= vbs; + ln_lvbl <= vsa; + st <= st<<1; + end + end else if(active) begin + ln_v <= ln_v + 1'd1; + if( ln_v == vend ) + done <= 1; + else + ln_hs <= 1; + end + `else begin + ln_v <= ln_v + 1'd1; + if( ln_v == vend ) + done <= 1; + else + ln_hs <= 1; + end + `endif + end +end + +localparam [15:0] LFBUF_CLR = `ifndef JTFRAME_LFBUF_CLR 0 `else `JTFRAME_LFBUF_CLR `endif ; + +// collect input data +jtframe_dual_ram #(.DW(16),.AW(HW+1)) u_linein( + // Write to big RAM and delete + .clk0 ( clk ), + .data0 ( LFBUF_CLR ), + .addr0 ( { line^fb_clr, fb_addr } ), + .we0 ( fb_clr ), + .q0 ( fb_din ), + // Get new pixels from core + .clk1 ( clk ), + .data1 ( { {16-DW{1'b0}}, ln_data } ), + .addr1 ( { line, ln_addr } ), + .we1 ( ln_we ), // the core should not send transparent pixels + .q1 ( ) +); + +jtframe_rpwp_ram #(.DW(16),.AW(HW)) u_lineout( + .clk ( clk ), + // Read from big RAM, write to line buffer + .din ( fb_dout ), + .wr_addr( rd_addr ), + .we ( scr_we ), + // Read from line buffer to screen + .rd_addr( hdump ), + .dout ( scr_pxl ) +); + +endmodule \ No newline at end of file diff --git a/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/video/jtframe_lfbuf_sdr.v b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/video/jtframe_lfbuf_sdr.v new file mode 100644 index 0000000000000000000000000000000000000000..08a578181358ec60615c881f9c9d49285cc412df --- /dev/null +++ b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/video/jtframe_lfbuf_sdr.v @@ -0,0 +1,150 @@ +/* This file is part of JTFRAME. + JTFRAME program is free software: you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation, either version 3 of the License, or + (at your option) any later version. + + JTFRAME program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with JTFRAME. If not, see . + + Author: Jose Tejada Gomez. Twitter: @topapate + Version: 1.0 + Date: 30-10-2022 */ + +// Frame buffer built on top of two line buffers + +// This module is not fully tested yet +/* verilator lint_off MODDUP */ +module jtframe_lfbuf_sdr #(parameter + DW = 16, + VW = 8, + HW = 9 +)( + input rst, // hold in reset for >150 us + input clk, + input pxl_cen, + + // video status + input [VW-1:0] vrender, + input [HW-1:0] hdump, + input hs, + input vs, + input lhbl, + input lvbl, + + // core interface + input [HW-1:0] ln_addr, + input [DW-1:0] ln_data, + input ln_done, + input ln_we, + output ln_hs, ln_vs, ln_lvbl, + output [DW-1:0] ln_pxl, + output [VW-1:0] ln_v, + + // SDR RAM + input init_n, + output [12:0] SDRAM_A, + inout [15:0] SDRAM_DQ, + output SDRAM_DQML, + output SDRAM_DQMH, + output SDRAM_nWE, + output SDRAM_nCAS, + output SDRAM_nRAS, + output SDRAM_nCS, + output [1:0] SDRAM_BA, + output SDRAM_CKE, + + // Status + input [7:0] st_addr, + output [7:0] st_dout +); + +wire frame, fb_clr, fb_done, line, scr_we, fb_blank; +wire [HW-1:0] fb_addr, rd_addr; +wire [ 15:0] fb_din, fb_dout; + +jtframe_lfbuf_sdr_ctrl #(.HW(HW),.VW(VW)) u_ctrl ( + .rst ( rst ), + .clk ( clk ), + .pxl_cen ( pxl_cen ), + + .lhbl ( lhbl ), + .vs ( vs ), + .ln_done ( ln_done ), + .vrender ( vrender ), + .ln_v ( ln_v ), + // data written to external memory + .frame ( frame ), + .fb_blank ( fb_blank ), + .fb_addr ( fb_addr ), + .rd_addr ( rd_addr ), + .fb_din ( fb_din ), + .fb_dout ( fb_dout ), + .fb_clr ( fb_clr ), + .fb_done ( fb_done ), + + // data read from external memory to screen buffer + // during h blank + .line ( line ), + .scr_we ( scr_we ), + + .init_n ( init_n ), + .SDRAM_A ( SDRAM_A ), + .SDRAM_DQ ( SDRAM_DQ ), + .SDRAM_DQML ( SDRAM_DQML ), + .SDRAM_DQMH ( SDRAM_DQMH ), + .SDRAM_nWE ( SDRAM_nWE ), + .SDRAM_nCAS ( SDRAM_nCAS ), + .SDRAM_nRAS ( SDRAM_nRAS ), + .SDRAM_nCS ( SDRAM_nCS ), + .SDRAM_BA ( SDRAM_BA ), + .SDRAM_CKE ( SDRAM_CKE ), + + .st_addr ( st_addr ), + .st_dout ( st_dout ) +); + +jtframe_lfbuf_line #(.DW(DW),.HW(HW),.VW(VW)) u_line( + .rst ( rst ), + .clk ( clk ), + .pxl_cen ( pxl_cen ), + + // video status + .vrender ( vrender ), + .hdump ( hdump ), + .hs ( hs ), + .vs ( vs ), // vertical sync, the buffer is swapped here + .lvbl ( lvbl ), // vertical blank, active low + + // core interface + .ln_hs ( ln_hs ), + .ln_v ( ln_v ), + .ln_vs ( ln_vs ), + .ln_lvbl ( ln_lvbl ), + .ln_addr ( ln_addr ), + .ln_data ( ln_data ), + .ln_we ( ln_we ), + .ln_pxl ( ln_pxl ), + + // data written to external memory + .frame ( frame ), + .fb_blank ( fb_blank ), + .fb_addr ( fb_addr ), + .rd_addr ( rd_addr ), + .fb_din ( fb_din ), + .fb_dout ( fb_dout ), + .fb_clr ( fb_clr ), + .fb_done ( fb_done ), + + // data read from external memory to screen buffer + // during h blank + .line ( line ), + .scr_we ( scr_we ) +); + +endmodule \ No newline at end of file diff --git a/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/video/jtframe_lfbuf_sdr_ctrl.v b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/video/jtframe_lfbuf_sdr_ctrl.v new file mode 100644 index 0000000000000000000000000000000000000000..7d64ba278f43fcca810bca7a5cce27a9b2fe6bed --- /dev/null +++ b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/video/jtframe_lfbuf_sdr_ctrl.v @@ -0,0 +1,290 @@ +/* This file is part of JTFRAME. + JTFRAME program is free software: you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation, either version 3 of the License, or + (at your option) any later version. + + JTFRAME program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with JTFRAME. If not, see . + + Author: Gyorgy Szombathelyi + Version: 1.0 + Date: 27-03-2024 */ + +/* + This module uses an SDRAM module for framebuffer. + Each row contain one line, and the row content is bursted out to line buffers. + As every used row is opened in every frame, there's no need to explicit refresh. +*/ +/* verilator lint_off MODDUP */ +module jtframe_lfbuf_sdr_ctrl #(parameter + CLK96 = 0, // assume 48-ish MHz operation by default + VW = 8, + HW = 9 +)( + input rst, // hold in reset for >150 us + input clk, + input pxl_cen, + + input lhbl, + input ln_done, + input [VW-1:0] vrender, + input [VW-1:0] ln_v, + input vs, + // data written to external memory + input frame, + input fb_blank, + output reg [HW-1:0] fb_addr, + input [ 15:0] fb_din, + output reg fb_clr, + output reg fb_done, + + // data read from external memory to screen buffer + // during h blank + output [ 15:0] fb_dout, + output reg [HW-1:0] rd_addr, + output reg line, + output reg scr_we, + + input init_n, + output reg [12:0] SDRAM_A, + inout [15:0] SDRAM_DQ, + output reg SDRAM_DQML, + output reg SDRAM_DQMH, + output SDRAM_nWE, + output SDRAM_nCAS, + output SDRAM_nRAS, + output SDRAM_nCS, + output [1:0] SDRAM_BA, + output SDRAM_CKE, + + // Status + input [7:0] st_addr, + output reg [7:0] st_dout +); + +localparam AW=HW+VW+1; +localparam [2:0] IDLE=0, READ1=1, WRITE1=2, READ=3, WRITE=4; + +localparam RASCAS_DELAY = 3'd2; // tRCD=20ns -> 2 cycles@<100MHz +localparam BURST_LENGTH = 3'b000; // 000=1, 001=2, 010=4, 011=8 +localparam ACCESS_TYPE = 1'b0; // 0=sequential, 1=interleaved +localparam CAS_LATENCY = 3'd2; // 2/3 allowed +localparam OP_MODE = 2'b00; // only 00 (standard operation) allowed +localparam NO_WRITE_BURST = 1'b1; // 0= write burst enabled, 1=only single access write + +localparam MODE = { 3'b000, NO_WRITE_BURST, OP_MODE, CAS_LATENCY, ACCESS_TYPE, BURST_LENGTH}; + +// all possible commands +localparam CMD_INHIBIT = 4'b1111; +localparam CMD_NOP = 4'b0111; +localparam CMD_ACTIVE = 4'b0011; +localparam CMD_READ = 4'b0101; +localparam CMD_WRITE = 4'b0100; +localparam CMD_BURST_TERMINATE = 4'b0110; +localparam CMD_PRECHARGE = 4'b0010; +localparam CMD_AUTO_REFRESH = 4'b0001; +localparam CMD_LOAD_MODE = 4'b0000; + +reg lhbl_l, ln_done_l, do_wr; +reg [ 2:0] st; +reg [HW-1:0] act_addr; +wire [HW-1:0] nx_rd_addr; +reg [HW-1:0] hblen, hlim, hcnt; +wire fb_over; +reg sdram_init = 1; +reg [6:0] sdram_init_st = 0; +reg [15:0] sdram_din; +reg [15:0] sdram_dout; +reg sdram_oe; +reg [3:0] sdram_cmd = CMD_NOP; +reg [1:0] sdram_del; +reg sdram_prechg; + +assign SDRAM_CKE = 1; +assign SDRAM_BA = 0; +assign SDRAM_DQ = sdram_oe ? sdram_din : 16'hZZZZ; +assign SDRAM_nCS = sdram_cmd[3]; +assign SDRAM_nRAS = sdram_cmd[2]; +assign SDRAM_nCAS = sdram_cmd[1]; +assign SDRAM_nWE = sdram_cmd[0]; + +assign fb_over = &fb_addr; +assign fb_dout = sdram_dout[15:0]; + +always @(posedge clk) begin + case( st_addr[3:0] ) + 0: st_dout <= { 2'd0, 1'b0, 2'd0, st }; + 1: st_dout <= { 3'd0, frame, fb_done, 1'b0, 1'b0, line }; + 2: st_dout <= fb_din[7:0]; + 3: st_dout <= fb_din[15:8]; + 4: st_dout <= sdram_din[7:0]; + 5: st_dout <= sdram_din[15:8]; + 6: st_dout <= sdram_dout[7:0]; + 7: st_dout <= sdram_dout[15:8]; + 8: st_dout <= ln_v[7:0]; + 9: st_dout <= vrender[7:0]; + default: st_dout <= 0; + endcase +end + +always @( posedge clk ) begin + if( rst ) begin + hblen <= 0; + hlim <= 0; + hcnt <= 0; + lhbl_l <= 0; + end else if(pxl_cen) begin + lhbl_l <= lhbl; + hcnt <= hcnt+1'd1; + if( ~lhbl & lhbl_l ) begin // enters blanking + hcnt <= 0; + hlim <= hcnt - hblen; // H limit below which we allow do_wr events + end + if( lhbl & ~lhbl_l ) begin // leaves blanking + hblen <= hcnt; + end + end +end + +wire skip_blank_lines = do_wr && fb_blank; + +always @( posedge clk ) begin + if( rst ) begin + fb_addr <= 0; + fb_clr <= 0; + fb_done <= 0; + act_addr <= 0; + rd_addr <= 0; + line <= 0; + scr_we <= 0; + ln_done_l<= 0; + do_wr <= 0; + st <= IDLE; + sdram_cmd <= CMD_NOP; + sdram_oe <= 0; + { SDRAM_DQML, SDRAM_DQMH } <= 2'b11; + sdram_init_st <= 0; + end else begin + sdram_dout <= SDRAM_DQ; + sdram_cmd <= CMD_NOP; + sdram_oe <= 0; + { SDRAM_DQML, SDRAM_DQMH } <= 2'b11; + + fb_done <= 0; + ln_done_l <= ln_done; + if (ln_done && !ln_done_l ) do_wr <= 1; + if( fb_clr ) begin + // the line is cleared outside the state machine so a + // read operation can happen independently + fb_addr <= fb_addr + 1'd1; + if( fb_over ) begin + fb_clr <= 0; + end + end + case( st ) + IDLE: begin + if (sdram_init) begin + sdram_init_st <= sdram_init_st + 1'd1; + if (sdram_init_st[2:0] == 0) begin + case (sdram_init_st[6:3]) + 0: begin + sdram_cmd <= CMD_PRECHARGE; + SDRAM_A[10] <= 1; + end + 5,7: begin + sdram_cmd <= CMD_AUTO_REFRESH; + end + 13: begin + sdram_cmd <= CMD_LOAD_MODE; + SDRAM_A <= MODE; + end + 15: sdram_init <= 0; + default: ; + endcase + end + end + else begin + scr_we <= 0; + sdram_prechg <= 0; + if( lhbl_l & ~lhbl ) begin + act_addr <= 0; + rd_addr <= 0; + SDRAM_A <= { ~frame, vrender }; + sdram_cmd<= CMD_ACTIVE; + sdram_del<= 3; + st <= READ1; + end else if( skip_blank_lines ) begin + fb_done <= 1; + do_wr <= 0; + end else if( do_wr && !fb_clr && + hcnt. + + Author: Jose Tejada Gomez. Twitter: @topapate + Version: 1.0 + Date: 30-10-2022 + + Adapted by @kyp069 & @somhi for SRAM memory (tested in NeptUNO target) + Date: 07-04-2023 */ + +// Frame buffer built on top of two line buffers + +// This module is not fully tested yet +module jtframe_lfbuf_sram #(parameter + DW = 16, + VW = 8, + HW = 9 +)( + input rst, // hold in reset for >150 us + input clk, + input pxl_cen, + + // video status + input [VW-1:0] vrender, + input [HW-1:0] hdump, + input hs, + input vs, + input lhbl, + input lvbl, + + // core interface + input [HW-1:0] ln_addr, + input [DW-1:0] ln_data, + input ln_done, + input ln_we, + output ln_hs, ln_vs, ln_lvbl, + output [DW-1:0] ln_pxl, + output [VW-1:0] ln_v, + + // SRAM + output [20:0] sram_addr, + inout [15:0] sram_data, + output sram_we, //negative logic + + // Status + input [7:0] st_addr, + output [7:0] st_dout +); + +wire frame, fb_clr, fb_done, line, scr_we, fb_blank; +wire [HW-1:0] fb_addr, rd_addr; +wire [ 15:0] fb_din, fb_dout; + +jtframe_lfbuf_sram_ctrl #(.HW(HW),.VW(VW)) u_ctrl ( + .rst ( rst ), + .clk ( clk ), + .pxl_cen ( pxl_cen ), + + .lhbl ( lhbl ), + .vs ( vs ), + .ln_done ( ln_done ), + .vrender ( vrender ), + .ln_v ( ln_v ), + // data written to external memory + .frame ( frame ), + .fb_blank ( fb_blank ), + .fb_addr ( fb_addr ), + .rd_addr ( rd_addr ), + .fb_din ( fb_din ), + .fb_dout ( fb_dout ), + .fb_clr ( fb_clr ), + .fb_done ( fb_done ), + + // data read from external memory to screen buffer + // during h blank + .line ( line ), + .scr_we ( scr_we ), + + .sram_addr ( sram_addr ), + .sram_data ( sram_data ), + .sram_we ( sram_we ), //negative logic + + .st_addr ( st_addr ), + .st_dout ( st_dout ) +); + +jtframe_lfbuf_line #(.DW(DW),.HW(HW),.VW(VW)) u_line( + .rst ( rst ), + .clk ( clk ), + .pxl_cen ( pxl_cen ), + + // video status + .vrender ( vrender ), + .hdump ( hdump ), + .hs ( hs ), + .vs ( vs ), // vertical sync, the buffer is swapped here + .lvbl ( lvbl ), // vertical blank, active low + + // core interface + .ln_hs ( ln_hs ), + .ln_v ( ln_v ), + .ln_vs ( ln_vs ), + .ln_lvbl ( ln_lvbl ), + .ln_addr ( ln_addr ), + .ln_data ( ln_data ), + .ln_we ( ln_we ), + .ln_pxl ( ln_pxl ), + + // data written to external memory + .frame ( frame ), + .fb_addr ( fb_addr ), + .rd_addr ( rd_addr ), + .fb_din ( fb_din ), + .fb_dout ( fb_dout ), + .fb_clr ( fb_clr ), + .fb_done ( fb_done ), + .fb_blank ( fb_blank ), + + // data read from external memory to screen buffer + // during h blank + .line ( line ), + .scr_we ( scr_we ) +); + +endmodule diff --git a/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/video/jtframe_lfbuf_sram_ctrl.v b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/video/jtframe_lfbuf_sram_ctrl.v new file mode 100644 index 0000000000000000000000000000000000000000..fef8a29df61d141d3cb5a984be9a75bb3398dd0c --- /dev/null +++ b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/video/jtframe_lfbuf_sram_ctrl.v @@ -0,0 +1,190 @@ +/* This file is part of JTFRAME. + JTFRAME program is free software: you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation, either version 3 of the License, or + (at your option) any later version. + + JTFRAME program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with JTFRAME. If not, see . + + Author: Jose Tejada Gomez. Twitter: @topapate + Version: 1.0 + Date: 20-11-2022 + + Adapted by @kyp069 & @somhi for SRAM memory (tested in NeptUNO target) + Date: 07-04-2023 */ + +module jtframe_lfbuf_sram_ctrl #(parameter + CLK96 = 0, // assume 48-ish MHz operation by default + VW = 8, + HW = 9 +)( + input rst, // hold in reset for >150 us + input clk, + input pxl_cen, + + input lhbl, + input ln_done, + input [VW-1:0] vrender, + input [VW-1:0] ln_v, + input vs, + // data written to external memory + input frame, + input fb_blank, + output reg [HW-1:0] fb_addr, + input [ 15:0] fb_din, + output reg fb_clr, + output reg fb_done, + + // data read from external memory to screen buffer + // during h blank + output [ 15:0] fb_dout, + output reg [HW-1:0] rd_addr, + output reg line, + output reg scr_we, + + // SRAM + output [20:0] sram_addr, + inout [15:0] sram_data, + output reg sram_we, //negative logic + + // Status + input [7:0] st_addr, + output reg [7:0] st_dout +); + +localparam AW=HW+VW+1; +localparam [1:0] IDLE=0, READ=1, WRITE=2; + +reg vsl, lhbl_l, ln_done_l, do_wr; +reg [ 1:0] st; +reg [AW-1:0] act_addr; +wire [HW-1:0] nx_rd_addr; +reg [HW-1:0] hblen, hlim, hcnt; +wire fb_over; +reg sram_rd; + +assign fb_over = &fb_addr; +assign sram_addr = { {21-AW{1'd0}}, act_addr }; +assign nx_rd_addr = rd_addr + 1'd1; +assign sram_data = sram_we ? 16'hzzzz : fb_din; +assign fb_dout = ~sram_we ? 16'd0 : sram_data; + + +always @(posedge clk) begin + case( st_addr[3:0] ) + 0: st_dout <= { 2'd0, sram_we, sram_rd, 2'd0, st }; + 1: st_dout <= { 3'd0, frame, fb_done, 1'd0, 1'd0, line }; + 2: st_dout <= fb_din[7:0]; + 3: st_dout <= fb_din[15:8]; + 4: st_dout <= sram_data[7:0]; + 5: st_dout <= sram_data[15:8]; + 6: st_dout <= 0; + 7: st_dout <= 0; + 8: st_dout <= ln_v[7:0]; + 9: st_dout <= vrender[7:0]; + default: st_dout <= 0; + endcase +end + +always @( posedge clk ) begin + if( rst ) begin + hblen <= 0; + hlim <= 0; + hcnt <= 0; + lhbl_l <= 0; + vsl <= 0; + end else if(pxl_cen) begin + lhbl_l <= lhbl; + vsl <= vs; + hcnt <= hcnt+1'd1; + if( ~lhbl & lhbl_l ) begin // enters blanking + hcnt <= 0; + hlim <= hcnt - hblen; // H limit below which we allow do_wr events + end + if( lhbl & ~lhbl_l ) begin // leaves blanking + hblen <= hcnt; + end + end +end + +wire skip_blank_lines = do_wr && fb_blank; + +always @( posedge clk ) begin + if( rst ) begin + sram_we <= 1; + sram_rd <= 0; + fb_addr <= 0; + fb_clr <= 0; + fb_done <= 0; + act_addr <= 0; + rd_addr <= 0; + line <= 0; + scr_we <= 0; + ln_done_l<= 0; + do_wr <= 0; + st <= IDLE; + end else begin + fb_done <= 0; + ln_done_l <= ln_done; + if (ln_done && !ln_done_l ) do_wr <= 1; + if( fb_clr ) begin + // the line is cleared outside the state machine so a + // read operation can happen independently + fb_addr <= fb_addr + 1'd1; + if( fb_over ) begin + fb_clr <= 0; + end + end + case( st ) + IDLE: begin + sram_we <= 1; + sram_rd <= 0; + scr_we <= 0; + if( lhbl_l & ~lhbl ) begin + act_addr <= { ~frame, vrender, {HW{1'd0}} }; + sram_rd <= 1; + rd_addr <= 0; + scr_we <= 1; + st <= READ; + end else if( skip_blank_lines ) begin + fb_done <= 1; + do_wr <= 0; + end else if( do_wr && !fb_clr && + hcnt. + + Author: Jose Tejada Gomez. Twitter: @topapate + Version: 1.0 + Date: 27-10-2017 */ + +module jtframe_linebuf #(parameter + DW=8, + AW=9 +)( + input clk, + input LHBL, // the line buffer is swapped when this signal goes low + // you can use ~HS instead of LHBL too + // New data writes + input [AW-1:0] wr_addr, + input [DW-1:0] wr_data, + input we, + // Old data reads + input [AW-1:0] rd_addr, + output [DW-1:0] rd_data, + output [DW-1:0] rd_gated +); + +reg line, last_LHBL; + +wire [DW-1:0] dump_data; + +`ifdef SIMULATION +initial begin + line = 0; +end +`endif + +always @(posedge clk) begin + last_LHBL <= LHBL; + if( !LHBL && last_LHBL ) + line <= ~line; +end + +assign rd_gated = LHBL ? rd_data : {DW{1'b0}}; + +jtframe_rpwp_ram #(.AW(AW+1),.DW(DW)) u_line( + .clk ( clk ), + + .din ( wr_data ), + .wr_addr( {line,wr_addr}), + .we ( we ), + + .rd_addr({~line,rd_addr}), + .dout ( rd_data ) +); + +endmodule \ No newline at end of file diff --git a/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/video/jtframe_linebuf_gate.v b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/video/jtframe_linebuf_gate.v new file mode 100644 index 0000000000000000000000000000000000000000..a1dddfb746da26fd2fb7af011a56c6d19a9bd7d4 --- /dev/null +++ b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/video/jtframe_linebuf_gate.v @@ -0,0 +1,104 @@ +/* This file is part of JTFRAME. + JTFRAME program is free software: you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation, either version 3 of the License, or + (at your option) any later version. + + JTFRAME program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with JTFRAME. If not, see . + + Author: Rafael Eduardo Paiva Feener. Copyright: Miki Saito + Version: 1.0 + Date: 07-08-2025 */ + +module jtframe_linebuf_gate #( + parameter HW = 9, + VW = 9, + PW = 8, + HS = 0, +parameter [HW-1:0] B_VIS = 9'd30, A_VIS=9'd37, VIS=9'd304, // number of counting points before, after and during visible section + RST_CT = 9'h058, // starting value for wr_addr + RD_DLY = 9'h00B, // number of times to delay hdump + WR_STRT = RST_CT + B_VIS, // wr_addr to start checking rom_ok & rom_cs + WR_END = WR_STRT+ VIS, // wr_addr where stops checking rom_ok & rom_cs + RD_END = WR_END + A_VIS, // + HTOT = 9'd384, // number of pxl_cen pulses in a line + HEND = RST_CT + HTOT, // value of wr_addr to stop cnt_cen + VB_END = 9'h10F // Must be same as in vtimer +) ( + input rst, + input clk, + input cen, + input pxl_cen, + input lvbl, + input hs, + input we, + + // screen + input [HW-1:0] hdump, + input [VW-1:0] vdump, + + // to graphics block + input [PW-1:0] pxl_data, + input rom_ok, // SDRAM output + input rom_cs, + output reg cnt_cen, + + output [PW-1:0] pxl_dump +); + +reg hs_cen, hs_l, done, fastwr; +wire pre_lvbl; +wire [HW-1:0] wr_addr, rd_addr; + +assign pre_lvbl = vdump==VB_END; + +always @(*) begin + done = wr_addr>=RD_END; + cnt_cen = 0; + hs_cen = 0; + fastwr = wr_addrWR_END && wr_addr. + + Author: Jose Tejada Gomez. Twitter: @topapate + Version: 1.0 + Date: 11-8-2022 */ + +module jtframe_logo #(parameter + COLORW = 4 +) ( + input rst, + input clk, + input pxl_cen, + + input [8:0] vdump, hdump, + + output reg [COLORW*3-1:0] rgb +); + +wire [10:1] tile_addr; +wire [ 8:0] vaddr; +wire [15:0] tile_data; +wire [ 7:0] tile_id; +wire [ 2:0] logopxl; + + +jtframe_prom #(.SYNHEX("logodata.hex"),.AW(10),.DW(16)) u_tiles( + .clk ( clk ), + .cen ( 1'b1 ), + .rd_addr( tile_addr ), + .data ( 16'd0 ), + .wr_addr( 10'd0 ), + .we ( 1'b0 ), + .q ( tile_data ) +); + +jtframe_prom #(.SYNHEX("logomap.hex"),.AW(9)) u_map( + .clk ( clk ), + .cen ( 1'b1 ), + .rd_addr( vaddr ), + .data ( 8'd0 ), + .wr_addr( 9'd0 ), + .we ( 1'b0 ), + .q ( tile_id ) +); + +always @* begin + case( logopxl[1:0] ) + 0: rgb = {3*COLORW{1'b0}}; // Black + 1: rgb = {3*COLORW{1'b1}}; // White + default: rgb = { {COLORW{1'b1}}, {2*COLORW{1'b0}} }; // Red + endcase +end + +jtframe_tilemap #( + .VA (9), + .CW (7), + .PW (3), + .BPP (2), + .MAP_HW(8), + .MAP_VW(7) +)u_tilemap( + .rst ( rst ), + .clk ( clk ), + .pxl_cen ( pxl_cen ), + + .vdump ( vdump[8:0]), + .hdump ( hdump[8:0]), + .blankn ( 1'b1 ), + .flip ( 1'b0 ), + + .vram_addr ( vaddr ), + + .code (tile_id[6:0]), + .pal (tile_id[7] ), + .hflip ( 1'b0 ), + .vflip ( 1'b0 ), + + .rom_addr ( tile_addr ), + .rom_data ( tile_data ), + .rom_cs ( ), + .rom_ok ( 1'b1 ), + + .pxl ( logopxl ) +); + +endmodule \ No newline at end of file diff --git a/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/video/jtframe_objdraw.v b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/video/jtframe_objdraw.v new file mode 100644 index 0000000000000000000000000000000000000000..ceca7b35729e658731f1e40a59af347cc4b1fb94 --- /dev/null +++ b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/video/jtframe_objdraw.v @@ -0,0 +1,120 @@ +/* This file is part of JTFRAME. + JTFRAME program is free software: you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation, either version 3 of the License, or + (at your option) any later version. + + JTFRAME program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with JTFRAME. If not, see . + + Author: Jose Tejada Gomez. Twitter: @topapate + Version: 1.0 + Date: 18-12-2022 */ + +// wrapper for jtframe_objdraw_gate that hides the +// buffer data ports (buf_pred and buf_din that let +// the core modify the data before storing it) +// object width is always 16 pixels + +module jtframe_objdraw #( parameter + AW = 9, + CW = 12, + PW = 8, + ZW = 6, + ZI = ZW-1, + ZENLARGE= 0, + SWAPH = 0, + HJUMP = 0, + HFIX = 1, + LATCH = 0, + FLIP_OFFSET=0, + KEEP_OLD = 0, + ALPHA = 0, + SHADOW = 0, + SHADOW_PEN = ALPHA, + SW = 1, + PACKED = 0 +)( + input rst, + input clk, + input pxl_cen, + input hs, + input flip, + input [AW-1:0] hdump, + + input draw, + output busy, + input [CW-1:0] code, + input [AW-1:0] xpos, + input [ 3:0] ysub, + // optional zoom, keep at zero for no zoom + input [ZW-1:0] hzoom, + input hz_keep, // set at 1 for the first tile + + input hflip, + input vflip, + input [PW-5:0] pal, + + output [CW+6:2] rom_addr, // {code,H,Y} + output rom_cs, + input rom_ok, + input [31:0] rom_data, + + output [PW-1:0] pxl +); + + wire [PW-1:0] buf_d; + + jtframe_objdraw_gate #( + .AW ( AW ), + .CW ( CW ), + .PW ( PW ), + .ZW ( ZW ), + .ZI ( ZI ), + .ZENLARGE ( ZENLARGE ), + .SWAPH ( SWAPH ), + .HJUMP ( HJUMP ), + .HFIX ( HFIX ), + .LATCH ( LATCH ), + .FLIP_OFFSET ( FLIP_OFFSET ), + .SHADOW ( SHADOW ), + .SW ( SW ), + .KEEP_OLD ( KEEP_OLD ), + .SHADOW_PEN ( SHADOW_PEN ), + .ALPHA ( ALPHA ), + .PACKED ( PACKED ) + )u_gate( + .rst ( rst ), + .clk ( clk ), + .pxl_cen ( pxl_cen ), + .hs ( hs ), + .flip ( flip ), + .hdump ( hdump ), + .draw ( draw ), + .busy ( busy ), + .code ( code ), + .xpos ( xpos ), + .ysub ( ysub ), + .trunc ( 2'd0 ), // always 16 pixels + .hzoom ( hzoom ), + .hz_keep ( hz_keep ), + .hflip ( hflip ), + .vflip ( vflip ), + .pal ( pal ), + .rom_addr ( rom_addr ), + .rom_cs ( rom_cs ), + .rom_ok ( rom_ok ), + .rom_data ( rom_data ), + + .buf_pred ( buf_d ), + .buf_din ( buf_d ), + + .pxl ( pxl ) + ); + +endmodule \ No newline at end of file diff --git a/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/video/jtframe_objdraw_gate.v b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/video/jtframe_objdraw_gate.v new file mode 100644 index 0000000000000000000000000000000000000000..ff47bbd312a93ce58bc89b8a9419d8537965d835 --- /dev/null +++ b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/video/jtframe_objdraw_gate.v @@ -0,0 +1,256 @@ +/* This file is part of JTFRAME. + JTFRAME program is free software: you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation, either version 3 of the License, or + (at your option) any later version. + + JTFRAME program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with JTFRAME. If not, see . + + Author: Jose Tejada Gomez. Twitter: @topapate + Version: 1.0 + Date: 18-12-2022 */ + +// Draws 16x16 sprites in a double-line buffer +// Assumes that the inputs are still during drawing, +// otherwise set LATCH=1 +// LATCH=1 will introduce an extra 1-clock per drawing +// operation, so use LATCH=0 when throughput is critical + +// Shadow operation follows TMNT style: an independent bit sets +// shadow for the pixel independently of the pixel color. The +// shadow bit is always written, even if the pixel is blank. +// The shadow bit must be the MSB + +module jtframe_objdraw_gate #( parameter + AW = 9, // Buffer with + CW = 12, // code width + PW = 8, // pixel width (lower four bits come from ROM) + ZW = 6, // zoom step width - see description in jtframe_draw + ZI = ZW-1, // integer part of the zoom width + ZENLARGE= 0, // enable zoom enlarging + SWAPH = 0, // swaps the two horizontal halves of the tile + HJUMP = 0, // set to 0 if hdump is a continuous count + // set to 1 if hdump jumps from FF to 180 (like KIWI) + // set to 2 if hdump jumps from 1FF to 80 (like JTTORA) + // See note below about hdump fix for HJUMP==0 + HFIX = 1, // Fixes some problems, but it may create others. Turn it off if objects are not rendered on part of the screen + LATCH = 0, // If set, latches code, xpos, ysub, hflip, vflip and pal when draw is set and busy is low + FLIP_OFFSET=0, // Added to ~hdump when flip==1 and HJUMP==0 + KEEP_OLD =0, // new writes do not overwrite old ones (reverse priority) + BUFDLY =0, // extra latency to add to buf_addr and buf_we, use if buf_din is not combinational + ALPHAW =4, + ALPHA =0, + SHADOW =0, // 1 for shadows + SW =1, // Shadow bits width (Use with SHADOW==1) + SHADOW_PEN = ALPHA, // Value used by only-shadow sprites. Use independently from SHADOW + // object line buffer + PACKED =0 // 0 if rom_data is { plane3, plane2, plane1, plane0 }, 8 bits each + // 1 if rom_data packs the 4 planes in nibbles +)( + input rst, + input clk, + input pxl_cen, + input hs, + input flip, + input [AW-1:0] hdump, + + input draw, + output busy, + input [CW-1:0] code, + input [AW-1:0] xpos, + input [ 3:0] ysub, + // Truncate to first 8 or 4 bits + input [ 1:0] trunc, // 00=no trunc, 10 = 8 pixels, 11 = 4 pixels + // optional zoom, keep at zero for no zoom + input [ZW-1:0] hzoom, + input hz_keep, // set at 1 for the first tile + + input hflip, + input vflip, + input [PW-5:0] pal, + + output [CW+6:2] rom_addr, // {code,H,Y} + output rom_cs, + input rom_ok, + input [31:0] rom_data, + + output [PW-1:0] buf_pred, // line buffer data to be altered and + input [PW-1:0] buf_din, // then fed back through these ports + + output [PW-1:0] pxl +); + +reg [AW-1:0] aeff, hdf, hdfix; +wire [AW-1:0] adly; + +reg [CW-1:0] dr_code; +reg [AW-1:0] dr_xpos; +reg [ 3:0] dr_ysub; +reg dr_hflip, dr_vflip, dr_draw; +reg [PW-5:0] dr_pal; + +reg [ZW-1:0] dr_hzoom; +reg dr_hz_keep; + +wire [AW-1:0] buf_addr; +wire buf_we, we_dly; +wire [31:0] rom_sorted; + +wire pre_bsy; + +assign rom_sorted = PACKED==0 ? rom_data : +{rom_data[31], rom_data[27], rom_data[23], rom_data[19], rom_data[15], rom_data[11], rom_data[7], rom_data[3], + rom_data[30], rom_data[26], rom_data[22], rom_data[18], rom_data[14], rom_data[10], rom_data[6], rom_data[2], + rom_data[29], rom_data[25], rom_data[21], rom_data[17], rom_data[13], rom_data[ 9], rom_data[5], rom_data[1], + rom_data[28], rom_data[24], rom_data[20], rom_data[16], rom_data[12], rom_data[ 8], rom_data[4], rom_data[0] }; + +generate + if( LATCH ) begin + always @(posedge clk) begin + dr_draw <= draw; + if( !pre_bsy ) begin + dr_code <= code; + dr_xpos <= xpos; + dr_ysub <= ysub; + dr_hflip <= hflip; + dr_vflip <= vflip; + dr_pal <= pal; + dr_hzoom <= hzoom; + dr_hz_keep <= hz_keep; + end + end + assign busy = pre_bsy | dr_draw; // busy is always assert 1 clock cycle after draw + end else begin + always @* begin + dr_draw = draw; + dr_code = code; + dr_xpos = xpos; + dr_ysub = ysub; + dr_hflip = hflip; + dr_vflip = vflip; + dr_pal = pal; + dr_hzoom = hzoom; + dr_hz_keep = hz_keep; + end + assign busy = pre_bsy; + end +endgenerate + +always @* begin + aeff = 0; + hdf = 0; + case( HJUMP ) //1 and 2 only work using 9 bits + 1: begin + aeff[8:0] = { buf_addr[8], buf_addr[8] ^ buf_addr[7], buf_addr[6:0] }; // 100~17F is translated to 180~1FF, and 180~1FF to 100~17F + hdf = hdump ^ { {AW-8{1'b0}}, flip&~hdump[8], {7{flip}} }; + end + 2: begin + aeff[8:0] = { buf_addr[8],~buf_addr[8] | buf_addr[7], buf_addr[6:0] }; // 00~ 7F is translated to 80~ FF + hdf = hdump ^ { {AW-8{1'b0}}, flip&hdump[8], {7{flip}} }; // untested line + end + default: begin + aeff = buf_addr; + hdf = flip ? ~hdfix+FLIP_OFFSET[8:0] : hdfix; + end + endcase +end + +generate + if(HJUMP==0 && HFIX==1) begin + // For HJUMP==0, it is common that the readout counter wraps around a bit before + // horizontal blank. That may read pixel data written to the start of the blank + // region instead of continuing the regular count. An example of this is + // scontra's final game boss. As it appears from the top (left unrotated) side + // of the screen, part of it is visible at the bottom (right). + // Instead of configuring this per game using macros, I have opted for detecting + // the situation generally and fixing it. The readout count will keep increasing + // until HS is hit. + always @(posedge clk, posedge rst) begin + if( rst ) begin + hdfix <= 0; + end else if(pxl_cen) begin + hdfix <= ( hdump > hdfix || hs ) ? hdump+9'd1 : hdfix+9'd1; + end + end + end else begin + always @* hdfix=hdump; + end +endgenerate + +generate + if(BUFDLY==0) begin + assign adly = aeff, + we_dly = buf_we; + end else begin + jtframe_sh #(.L(BUFDLY),.W(1+AW)) u_sh( + .clk ( clk ), + .clk_en ( 1'b1 ), + .din ( {aeff,buf_we} ), + .drop ( {adly,we_dly} ) + ); + end +endgenerate + +jtframe_draw #( + .AW ( AW ), + .CW ( CW ), + .PW ( PW ), + .ZW ( ZW ), + .ZI ( ZI ), + .ZENLARGE( ZENLARGE ), + .SWAPH ( SWAPH ), + .KEEP_OLD( KEEP_OLD ) +)u_draw( + .rst ( rst ), + .clk ( clk ), + .draw ( dr_draw ), + .busy ( pre_bsy ), + .code ( dr_code ), + .xpos ( dr_xpos ), + .ysub ( dr_ysub ), + .trunc ( trunc ), + .hz_keep ( dr_hz_keep), + .hzoom ( dr_hzoom ), + .hflip ( dr_hflip ), + .vflip ( dr_vflip ), + .pal ( dr_pal ), + .rom_addr ( rom_addr ), + .rom_cs ( rom_cs ), + .rom_ok ( rom_ok ), + .rom_data ( rom_sorted), + + .buf_addr ( buf_addr ), + .buf_we ( buf_we ), + .buf_din ( buf_pred ) +); + +jtframe_obj_buffer #( + .AW ( AW ), + .DW ( PW ), + .ALPHAW ( ALPHAW ), + .ALPHA ( ALPHA ), + .SW ( SW ), + .SHADOW ( SHADOW ), + .SHADOW_PEN ( SHADOW_PEN ), + .KEEP_OLD ( KEEP_OLD ) +) u_linebuf( + .clk ( clk ), + .flip ( 1'b0 ), // flip is solved before this instance + .LHBL ( ~hs ), + // New line writting + .we ( we_dly ), + .wr_data ( buf_din ), + .wr_addr ( adly ), + // Previous line reading + .rd ( pxl_cen ), + .rd_addr ( hdf ), + .rd_data ( pxl ) +); + +endmodule \ No newline at end of file diff --git a/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/video/jtframe_objdraw_trunc.v b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/video/jtframe_objdraw_trunc.v new file mode 100644 index 0000000000000000000000000000000000000000..9b516e67fed15826472e696c4007b6af76fe17e8 --- /dev/null +++ b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/video/jtframe_objdraw_trunc.v @@ -0,0 +1,113 @@ +/* This file is part of JTFRAME. + JTFRAME program is free software: you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation, either version 3 of the License, or + (at your option) any later version. + + JTFRAME program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with JTFRAME. If not, see . + + Author: Jose Tejada Gomez. Twitter: @topapate + Version: 1.0 + Date: 28-3-2024 */ + +// wrapper for jtframe_objdraw_gate that hides the +// buffer data ports (buf_pred and buf_din that let +// the core modify the data before storing it) +// object width is 16, 8 or 4 pixels + +module jtframe_objdraw_trunc #( parameter + CW = 12, + PW = 8, + ZW = 6, + ZI = ZW-1, + ZENLARGE= 0, + SWAPH = 0, + HJUMP = 0, + LATCH = 0, + FLIP_OFFSET=0, + KEEP_OLD = 0, + SHADOW = 0, + ALPHA = 0, + PACKED = 0 +)( + input rst, + input clk, + input pxl_cen, + input hs, + input flip, + input [ 8:0] hdump, + input [ 1:0] trunc, + + input draw, + output busy, + input [CW-1:0] code, + input [ 8:0] xpos, + input [ 3:0] ysub, + // optional zoom, keep at zero for no zoom + input [ZW-1:0] hzoom, + input hz_keep, // set at 1 for the first tile + + input hflip, + input vflip, + input [PW-5:0] pal, + + output [CW+6:2] rom_addr, // {code,H,Y} + output rom_cs, + input rom_ok, + input [31:0] rom_data, + + output [PW-1:0] pxl +); + + wire [PW-1:0] buf_d; + + jtframe_objdraw_gate #( + .CW ( CW ), + .PW ( PW ), + .ZW ( ZW ), + .ZI ( ZI ), + .ZENLARGE ( ZENLARGE ), + .SWAPH ( SWAPH ), + .HJUMP ( HJUMP ), + .LATCH ( LATCH ), + .FLIP_OFFSET ( FLIP_OFFSET ), + .SHADOW ( SHADOW ), + .KEEP_OLD ( KEEP_OLD ), + .ALPHA ( ALPHA ), + .PACKED ( PACKED ) + )u_gate( + .rst ( rst ), + .clk ( clk ), + .pxl_cen ( pxl_cen ), + .hs ( hs ), + .flip ( flip ), + .hdump ( hdump ), + .draw ( draw ), + .busy ( busy ), + .code ( code ), + .xpos ( xpos ), + .ysub ( ysub ), + .trunc ( trunc ), + .hzoom ( hzoom ), + .hz_keep ( hz_keep ), + .hflip ( hflip ), + .vflip ( vflip ), + .pal ( pal ), + .rom_addr ( rom_addr ), + .rom_cs ( rom_cs ), + .rom_ok ( rom_ok ), + .rom_data ( rom_data ), + + .buf_pred ( buf_d ), + .buf_din ( buf_d ), + + .pxl ( pxl ) + ); + +endmodule \ No newline at end of file diff --git a/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/video/jtframe_objscan.v b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/video/jtframe_objscan.v new file mode 100644 index 0000000000000000000000000000000000000000..1ab348001b6b9762dc44e231b67c9e51076b478d --- /dev/null +++ b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/video/jtframe_objscan.v @@ -0,0 +1,100 @@ +/* This file is part of JTCORES. + JTCORES program is free software: you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation, either version 3 of the License, or + (at your option) any later version. + + JTCORES program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with JTCORES. If not, see . + + Author: Jose Tejada Gomez. Twitter: @topapate + Version: 1.0 + Date: 2-1-2025 */ + +module jtframe_objscan #(parameter + OBJW=6, + STW=4, + HREPW=3, + HOLD_WHILE_DRBUSY=1, + // do not modify: + AW=OBJW+STW +)( + input clk, + input hs, + input blankn, + input [ 8:0] vrender, + output reg [ 8:0] vlatch, + output reg cen=0, + + input draw_step, + input skip, + input inzone, + + // support for multiple horizontal tiles + input [HREPW-1:0] hsize, // number of extra tiles to repeat (default zero) + output [HREPW-1:0] haddr, // tile code portion (goes to rom_addr) + output reg [HREPW-1:0] hsub=0, // H position delta + output [HREPW-1:0] hcnt_nx, + input hflip, + + input dr_busy, + output reg dr_draw = 0, + + output [AW-1:0] addr, + output reg[STW-1:0] step +); + +reg hs_l=0,done=0, hs_latched; +reg [OBJW-1:0] objcnt; +reg [HREPW-1:0] hcnt; // current tile repetition + +assign addr = {objcnt,step}; +assign haddr = hcnt^{HREPW{hflip}}; +assign hcnt_nx = hcnt+1'd1; + +always @(posedge clk) begin + cen <= ~cen; +end + +always @(posedge clk) if(cen) begin + hs_l <= hs; + dr_draw <= 0; + if( !done ) begin + if(!dr_busy && HOLD_WHILE_DRBUSY==1) step <= step + 1'd1; + if(step==0) begin + hcnt<=0; + end + if(skip) begin + step <= 0; + {done,objcnt} <= {1'd0,objcnt}+1'd1; + end + if(draw_step) begin + step <= step; + if( !dr_busy || !inzone ) begin + if(inzone) begin + dr_draw <= 1; + hsub <= hcnt; + end + if(hcnt!=hsize) begin + hcnt<=hcnt_nx; + end else begin + step <= 0; + {done,objcnt} <= {1'd0,objcnt}+1'd1; + end + end + end + end + if( hs && !hs_l && blankn ) begin + done <= 0; + objcnt <= 0; + step <= 0; + vlatch <= vrender; + end +end + +endmodule \ No newline at end of file diff --git a/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/video/jtframe_prom_colmix.v b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/video/jtframe_prom_colmix.v new file mode 100644 index 0000000000000000000000000000000000000000..cc46a14402df2e8a7c8152a5bec48fda186b9ab3 --- /dev/null +++ b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/video/jtframe_prom_colmix.v @@ -0,0 +1,107 @@ +/* This file is part of JTFRAME. + JTFRAME program is free software: you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation, either version 3 of the License, or + (at your option) any later version. + + JTFRAME program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with JTFRAME. If not, see . + + Author: Jose Tejada Gomez. Twitter: @topapate + Version: 1.0 + Date: 15-12-2022 */ + + +// Generic color mixer based on PROMs + +module jtframe_prom_colmix #( parameter + PROM_AW = 10, + SIMFILE0 = "", + SIMFILE1 = "", + CODING = "RGB", + COLORW = 4 +)( + input rst, + input clk, + input pxl_cen, + input LHBL, + input LVBL, + + input [PROM_AW-1:0] lyr0_addr, + input [PROM_AW-1:0] lyr1_addr, + input [PROM_AW-1:0] lyr2_addr, + input [PROM_AW-1:0] lyr3_addr, + input [1:0] lyr_sel, + + input [PROM_AW:0] prog_addr, + input [7:0] prog_data, + input prom_we, + + output reg [COLORW-1:0] red, + output reg [COLORW-1:0] green, + output reg [COLORW-1:0] blue + +); + +wire [PROM_AW-1:0] rd_addr; +wire prom_we0, prom_we1; +wire [7:0] prom0_dout, prom1_dout; +reg [PROM_AW-1:0] col_addr; +wire blank; + +assign prom_we0 = ~prog_addr[PROM_AW] & prom_we; +assign prom_we1 = prog_addr[PROM_AW] & prom_we; +assign blank = ~(LVBL&LHBL); + +always @(posedge clk) if(pxl_cen) begin + case( lyr_sel ) + 0: col_addr <= lyr0_addr; + 1: col_addr <= lyr1_addr; + 2: col_addr <= lyr2_addr; + 3: col_addr <= lyr3_addr; + endcase +end + +always @* begin + case( CODING ) + "RGB": {red,green,blue} = { prom1_dout[COLORW*3-9:0], prom0_dout }; + "BGR": {blue,green,red} = { prom1_dout[COLORW*3-9:0], prom0_dout }; + default: begin + {red,green,blue} = { prom1_dout[COLORW*3-9:0], prom0_dout }; +`ifdef SIMULATION + $display("ERROR: %m unsupported CODING"); + $finish; +`endif + end + endcase + if( blank ) {red,green,blue} = 0; +end + +jtframe_prom #(.AW(PROM_AW),.SIMFILE(SIMFILE0)) u_prom0( + .clk ( clk ), + .cen ( 1'b1 ), + .data ( prog_data ), + .rd_addr( col_addr ), + .wr_addr( prog_addr[PROM_AW-1:0] ), + .we ( prom_we0 ), + .q ( prom0_dout ) +); + +jtframe_prom #(.AW(PROM_AW),.SIMFILE(SIMFILE1)) u_prom1( + .clk ( clk ), + .cen ( 1'b1 ), + .data ( prog_data ), + .rd_addr( col_addr ), + .wr_addr( prog_addr[PROM_AW-1:0] ), + .we ( prom_we1 ), + .q ( prom1_dout ) +); + + + +endmodule \ No newline at end of file diff --git a/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/video/jtframe_pxl.v b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/video/jtframe_pxl.v new file mode 100644 index 0000000000000000000000000000000000000000..20c21c288b7cae5ed4c550e5b1c029fd80b83383 --- /dev/null +++ b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/video/jtframe_pxl.v @@ -0,0 +1,66 @@ +/* This file is part of JTFRAME. + JTFRAME program is free software: you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation, either version 3 of the License, or + (at your option) any later version. + + JTFRAME program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with JTFRAME. If not, see . + + Author: Jose Tejada Gomez. Twitter: @topapate + Version: 1.0 + Date: 3-IV-2019 */ + +module jtframe_pxl #(parameter wi=4, wo=6)( + input clk, + input cen, + input double, + input en_mix, + input [3*wi-1:0] rgb_in, + output [3*wo-1:0] rgb_out +); + +`ifdef SIMULATION +initial begin + if( wo. + + Author: Jose Tejada Gomez. Twitter: @topapate + Version: 1.0 + Date: 25-9-2019 */ + +module jtframe_resync( + input clk, + input pxl_cen, + input hs_in, + input vs_in, + input LVBL, + input LHBL, + input [3:0] hoffset, + input [3:0] voffset, + output reg hs_out, + output reg vs_out +); + +parameter CNTW = 10; // max 1024 pixels/lines + +reg [CNTW-1:0] hs_pos[0:1], vs_hpos[0:1], vs_vpos[0:1],// relative positions of the original sync pulses + hs_len[0:1], vs_len[0:1], // count the length of the original sync pulses + hs_cnt, vs_cnt, // count the position of the original sync pulses + hs_hold, vs_hold; +reg last_LHBL, last_LVBL, last_hsin, last_vsin; + +wire hb_edge, hs_edge, hs_n_edge, vb_edge, vs_edge, vs_n_edge; +reg field; + +wire [CNTW-1:0] hpos_off = { {CNTW-4{hoffset[3]}}, hoffset[3:0] }; +wire [CNTW-1:0] htrip = hs_pos[field] + hpos_off; +wire [CNTW-1:0] vs_htrip = vs_hpos[field] + hpos_off; +wire [CNTW-1:0] vs_vtrip = vs_vpos[field] + { {CNTW-4{voffset[3]}}, voffset[3:0] }; + +assign hb_edge = LHBL && !last_LHBL; +assign hs_edge = hs_in && !last_hsin; +assign hs_n_edge = !hs_in && last_hsin; +assign vb_edge = LVBL && !last_LVBL; +assign vs_edge = vs_in && !last_vsin; +assign vs_n_edge = !vs_in && last_vsin; + +always @(posedge clk) if(pxl_cen) begin + last_LHBL <= LHBL; + last_LVBL <= LVBL; + last_hsin <= hs_in; + last_vsin <= vs_in; + + hs_cnt <= hb_edge ? {CNTW{1'b0}} : hs_cnt+1'b1; + if( vb_edge ) begin + vs_cnt <= {CNTW{1'b0}}; + field <= ~field; + end else if(hb_edge) + vs_cnt <= vs_cnt+1'b1; + + // Horizontal + if( hs_edge ) hs_pos[field] <= hs_cnt; + if( hs_n_edge ) hs_len[field] <= hs_cnt - hs_pos[field]; + + if( hs_cnt == htrip ) begin + hs_out <= 1; + hs_hold <= hs_len[field] - 1'b1; + end else begin + if( |hs_hold ) hs_hold <= hs_hold - 1'b1; + if( hs_hold == 0 ) hs_out <= 0; + end + + // Vertical + if( vs_edge ) begin + vs_hpos[field] <= hs_cnt; + vs_vpos[field] <= vs_cnt; + end + if( vs_n_edge ) vs_len[field] <= vs_cnt - vs_vpos[field]; + + if( hs_cnt == vs_htrip ) begin + if( vs_cnt == vs_vtrip ) begin + vs_hold <= vs_len[field] - 1'b1; + vs_out <= 1; + end else begin + if( |vs_hold ) vs_hold <= vs_hold - 1'b1; + if( vs_hold == 0 ) vs_out <= 0; + end + end + +end + +`ifdef SIMULATION +initial begin + hs_cnt = {CNTW{1'b0}}; + vs_cnt = {CNTW{1'b0}}; + hs_out = 0; + vs_out = 0; +end +`endif + +endmodule diff --git a/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/video/jtframe_scan2x.v b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/video/jtframe_scan2x.v new file mode 100644 index 0000000000000000000000000000000000000000..8285426fd2005eca489dd79a2429bc3b5d42d873 --- /dev/null +++ b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/video/jtframe_scan2x.v @@ -0,0 +1,379 @@ +/* This file is part of JTFRAME. + JTFRAME program is free software: you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation, either version 3 of the License, or + (at your option) any later version. + + JTFRAME program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with JTFRAME. If not, see . + + Author: Jose Tejada Gomez. Twitter: @topapate + Version: 1.0 + Date: 25-9-2019 */ + +// Simple scan doubler +// CRT-like output: +// -simple blending of neighbouring pixels +// -50% scan lines + +// sl_mode for scan lines +// 0 = no scan lines +// 1 = dimmed +// 2 = more dimmed +// 3 = blank scan lines + +// hz_mode for horizontal pixel blending +// 0 = no blending +// 1 = linear interpolation +// 2 = blank (zero) + +module jtframe_scan2x #(parameter COLORW=4, HLEN=512)( + input rst, + input clk, + input pxl_cen, + input pxl2_cen, + + // configuration + input enb, // enable bar + input [1:0] sl_mode, // scanline modes + input blend_en, // horizontal blending modes + + // rotating + input [1:0] rotation, // 0 - no rotation, 1 - clockwise, 2 - anticlockwise + input hfilter, + input vfilter, + + input [COLORW*3-1:0] x1_pxl, + input x1_hs, + input x1_vs, + input x1_hb, + input x1_vb, + + output reg [COLORW*3-1:0] x2_pxl, + output reg x2_hs, + output reg x2_vs, + output x2_de, + output reg x2_HB, + output reg x2_VB, + + // SDRAM interface for rotation + input init, + inout [15:0] sd_data, + output [12:0] sd_addr, + output [1:0] sd_dqm, + output [1:0] sd_ba, + output sd_cs, + output sd_we, + output sd_ras, + output sd_cas, + output sd_cke +); + +localparam AW=HLEN<=512 ? 9:10; +localparam DW=COLORW*3; + +reg [DW-1:0] preout=0; +reg [AW-1:0] wraddr, rdaddr, hlen, hswidth, hb_rise, hb_fall, vb_rise, vb_fall, vs_rise, vs_fall; +reg scanline; +reg last_HS, last_VS, last_HB, last_VB; +reg vb_rising, vb_falling, vs_rising, vs_falling; +reg line=0; +reg vchng=0, vwait=0; +//reg x2_HB, x2_VB; + +wire HS_posedge = x1_hs && !last_HS; +wire HS_negedge = !x1_hs && last_HS; +wire [DW-1:0] next; +wire [DW-1:0] linebuf_q; +wire [DW-1:0] dim2, dim4; +reg [COLORW:0] ab; +wire [COLORW*3-1:0] gated_pxl; + +wire HB_posedge = x1_hb && !last_HB; +wire HB_negedge = !x1_hb && last_HB; +wire VB_posedge = x1_vb && !last_VB; +wire VB_negedge = !x1_vb && last_VB; +wire VS_posedge = x1_vs && !last_VS; +wire VS_negedge = !x1_vs && last_VS; + +function [COLORW-1:0] ave( + input [COLORW-1:0] a, + input [COLORW-1:0] b ); + begin + ab = {1'b0,a}+{1'b0,b}; + ave = ab[COLORW:1]; + end +endfunction + +function [DW-1:0] blend( + input [DW-1:0] a, + input [DW-1:0] b ); + blend = { + ave(a[COLORW*3-1:COLORW*2],b[COLORW*3-1:COLORW*2]), + ave(a[COLORW*2-1:COLORW],b[COLORW*2-1:COLORW]), + ave(a[COLORW-1:0],b[COLORW-1:0]) }; +endfunction + +// `ifdef JTFRAME_SDRAM96 +// localparam CLKSTEPS=8; +// localparam [CLKSTEPS-1:0] BLEND_ST = 8'b10; +// `else +localparam CLKSTEPS=4; +localparam [CLKSTEPS-1:0] BLEND_ST = 2; +// `endif + +localparam [CLKSTEPS-1:0] PURE_ST = 0; +reg alt_pxl=0; // this is needed in case pxl2_cen and pxl_cen are not aligned. +reg [CLKSTEPS-1:0] mixst; + +always@(posedge clk or posedge rst) begin + if( rst ) begin + preout <= {DW{1'b0}}; + end else begin + `ifndef JTFRAME_SCAN2X_NOBLEND + // mixing can only be done if clk is at least 4x pxl2_cen + mixst <= { mixst[0+:CLKSTEPS-1],pxl2_cen}; + if(mixst==BLEND_ST) begin + preout <= blend_en ? + blend( rdaddr=={AW{1'b0}} ? {DW{1'b0}} : preout, next) : + next; + end else if( mixst==PURE_ST ) + preout <= next; + `else + preout <= next; + `endif + end +end + +assign dim2 = blend( {DW{1'b0}}, preout); +assign dim4 = blend( {DW{1'b0}}, dim2 ); +assign gated_pxl = (x1_vb|x1_hb) ? {3*COLORW{1'b0}} : x1_pxl; + +// scan lines are black +always @(posedge clk) if(pxl2_cen) begin + if( scanline ) begin + case( sl_mode ) + 2'd0: x2_pxl <= preout; + 2'd1: x2_pxl <= dim2; + 2'd2: x2_pxl <= dim4; + 2'd3: x2_pxl <= {DW{1'b0}}; + endcase + end else x2_pxl <= preout; + if( enb ) x2_pxl <= x1_pxl; +end + +always @(posedge clk) if(pxl2_cen) begin + alt_pxl <= ~alt_pxl; + if( alt_pxl ) last_HS <= x1_hs; + if( alt_pxl & HS_posedge ) begin + wraddr <= {AW{1'b0}}; + rdaddr <= {AW{1'b0}}; + hlen <= wraddr; + line <= ~line; + scanline <= 0; + x2_hs <= 1; + end else begin + if(alt_pxl) wraddr <= wraddr + 1'd1; + if( rdaddr == hlen ) begin + rdaddr <= {AW{1'b0}}; + x2_hs <= 1; + scanline <= 1; + end else begin + rdaddr <= rdaddr+1'd1; + if( rdaddr == hswidth ) begin + x2_hs <= 0; + end + end + end + if( alt_pxl & HS_negedge ) begin + hswidth <= wraddr; + end + + last_HB <= x1_hb; + last_VB <= x1_vb; + last_VS <= x1_vs; + if (HB_posedge) begin + hb_rise <= wraddr; + if( vwait && vb_falling ) vchng <= 1; + if( vchng && vb_rising ) begin + {vwait, vchng} <= 2'b0; + vb_rise <= wraddr; + end + end + if (HB_negedge) begin + hb_fall <= wraddr; + if( vwait && vb_rising ) vchng <= 1; + if( vchng && vb_falling ) begin + {vwait, vchng} <= 2'b0; + vb_fall <= wraddr; + end + end + if (VB_posedge) begin + vwait <= 1; + // vb_rise <= wraddr; + vb_rising <= 1; + vb_falling <= 0; + end + if (VB_negedge) begin + vwait <= 1; + // vb_fall <= wraddr; + vb_falling <= 1; + vb_rising <= 0; + end + if (VS_posedge) begin + vs_rise <= wraddr; + vs_rising <= 1; + vs_falling <= 0; + end + if (VS_negedge) begin + vs_fall <= wraddr; + vs_falling <= 1; + vs_rising <= 0; + end + if (rdaddr == hb_rise) x2_HB <= 1; + if (rdaddr == hb_fall) x2_HB <= 0; + if (vb_rising && rdaddr == vb_rise) x2_VB <= 1; + if (vb_falling && rdaddr == vb_fall) x2_VB <= 0; + if (vs_rising && rdaddr == vs_rise) x2_vs <= 1; + if (vs_falling && rdaddr == vs_fall) x2_vs <= 0; + + if( enb ) {x2_hs,x2_HB,x2_vs,x2_VB} <= {x1_hs,x1_hb,x1_vs,x1_vb}; +end + +assign x2_de = ~(x2_VB | x2_HB); + +`ifdef JTFRAME_VERTICAL +`ifdef JTFRAME_SDRAM_ROTATION +`define JTFRAME_SCAN2X_ROTATE +`endif +`endif + +`ifdef JTFRAME_SCAN2X_ROTATE +wire [COLORW-1:0] rotate_r, rotate_g, rotate_b; +wire vidin_req; +wire [1:0] vidin_frame; +wire [10:0] vidin_row; +wire [10:0] vidin_col; +wire [15:0] vidin_d; +wire vidin_ack; + +wire vidout_req; +wire [1:0] vidout_frame; +wire [10:0] vidout_row; +wire [10:0] vidout_col; +wire [15:0] vidout_d; +wire vidout_ack; + +scandoubler_rotate #(.COLOR_DEPTH(COLORW), .OUT_COLOR_DEPTH(COLORW)) u_rotate( + .clk_sys ( clk ), + .rotation ( rotation ), + .rotateonly ( 1'b0 ), + .hfilter ( hfilter ), + .vfilter ( vfilter ), + .pe_in ( pxl_cen ), + .ppe_out ( pxl2_cen ), + .hb_in ( x1_hb ), + .vb_in ( x1_vb ), + .hs_in ( x1_hs ), + .vs_in ( x1_vs ), + .r_in ( x1_pxl[COLORW*3-1:COLORW*2] ), + .g_in ( x1_pxl[COLORW*2-1:COLORW] ), + .b_in ( x1_pxl[COLORW-1:0] ), + .hb_sd ( x2_HB ), + .vb_sd ( x2_VB ), + .vs_sd ( x2_vs ), + .r_out ( rotate_r ), + .g_out ( rotate_g ), + .b_out ( rotate_b ), + + // Memory interface + .vidin_req ( vidin_req ), + .vidin_frame( vidin_frame ), + .vidin_row ( vidin_row ), + .vidin_col ( vidin_col ), + .vidin_d ( vidin_d ), + .vidin_ack ( vidin_ack ), + + .vidout_req ( vidout_req ), + .vidout_frame ( vidout_frame ), + .vidout_row ( vidout_row ), + .vidout_col ( vidout_col ), + .vidout_d ( vidout_d ), + .vidout_ack ( vidout_ack ) +); + +scandoubler_sdram u_sdram ( + .init ( init ), + .clk ( clk ), + .ready ( ), + .sd_data ( sd_data ), + .sd_addr ( sd_addr ), + .sd_dqm ( sd_dqm ), + .sd_ba ( sd_ba ), + .sd_cs ( sd_cs ), + .sd_we ( sd_we ), + .sd_ras ( sd_ras ), + .sd_cas ( sd_cas ), + + .ram_din ( ), + .ram_dout ( ), + .ram_addr ( ), + .ram_ds ( ), + .ram_req ( ), + .ram_we ( ), + .ram_ack ( ), + + .rom_oe ( ), + .rom_addr ( ), + .rom_dout ( ), + + .vidin_req ( vidin_req ), + .vidin_frame ( vidin_frame ), + .vidin_row ( vidin_row ), + .vidin_col ( vidin_col ), + .vidin_d ( vidin_d ), + .vidin_ack ( vidin_ack ), + + .vidout_req ( vidout_req ), + .vidout_frame ( vidout_frame ), + .vidout_row ( vidout_row ), + .vidout_col ( vidout_col ), + .vidout_q ( vidout_d ), + .vidout_ack ( vidout_ack ) +); +assign sd_cke = 1; +assign next = |rotation ? {rotate_r, rotate_g, rotate_b} : linebuf_q; +`else +assign next = linebuf_q; +assign sd_data = 16'hZZZZ; +assign sd_addr = 0; +assign sd_dqm = 0; +assign sd_ba = 0; +assign sd_cs = 1; +assign sd_we = 1; +assign sd_ras = 1; +assign sd_cas = 1; +assign sd_cke = 0; +`endif + +jtframe_dual_ram #(.DW(DW),.AW(AW+1)) u_buffer( + .clk0 ( clk ), + .clk1 ( clk ), + // Port 0: read + .data0 ( {DW{1'b0}} ), + .addr0 ( {line, rdaddr} ), + .we0 ( 1'b0 ), + .q0 ( linebuf_q ), + // Port 1: write + .data1 ( gated_pxl ), + .addr1 ( {~line, wraddr}), + .we1 ( pxl_cen ), + .q1 ( ) +); + +endmodule // jtframe_scan2x diff --git a/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/video/jtframe_short_blank.v b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/video/jtframe_short_blank.v new file mode 100644 index 0000000000000000000000000000000000000000..caf57cef92030cbd5efcdbec7aacb3321ecc50bb --- /dev/null +++ b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/video/jtframe_short_blank.v @@ -0,0 +1,80 @@ +/* This file is part of JTFRAME. + JTFRAME program is free software: you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation, either version 3 of the License, or + (at your option) any later version. + + JTFRAME program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with JTFRAME. If not, see . + + Author: Rafael Eduardo Paiva Feener. Copyright: Miki Saito + Version: 1.0 + Date: 03-05-2024 */ + +// Makes blanking signals shorter +// This is used when the game software draws black frames around the +// image. Shortening the blanking signals will cause MiSTer/Pocket +// platforms to crop the black frames +// The core colmix should not produce color output during the extended +// blanking +module jtframe_short_blank #(parameter WIDTH=511, HEIGHT=264) ( + input clk, + input pxl_cen, + input LHBL, + input LVBL, + input HS, + + input h_en, // HB enlargement enable + input v_en, // VB enable + input wide, // 8 or 16 pixels (per side) + + output hb_out, // shortened outputs + output vb_out +); + +reg [5:0] clip; +reg [5:0] max_pxl_count; +reg [7:0] ln_count=0; +reg [8:0] ln_count2=0, max_ln_count2; +reg [8:0] max_pxl_count2; +reg [8:0] pxl_count=0; +reg lhbs, lvbs; +reg last_hb=0, last_vb=0, last_hs=0; + +assign hb_out = !h_en ? LHBL : lhbs; +assign vb_out = !v_en ? LVBL : lvbs; + +always @(*) begin + clip = wide ? 6'd16 : 6'd8; + max_pxl_count = clip-6'd2; + max_pxl_count2 = WIDTH[8:0] -{3'b0, clip}-9'd2; + max_ln_count2 = HEIGHT[8:0]-{3'b0, clip}-9'd2; +end + +always @(posedge clk) if(pxl_cen) begin + last_hb <= LHBL; + pxl_count <= pxl_count + 1'b1; + if( LHBL && !last_hb) pxl_count <= 0; + if(pxl_count ==max_pxl_count2) lhbs <= 0; + if(pxl_count[5:0]==max_pxl_count && LHBL) lhbs <= 1; +end + +always @(posedge clk) begin + last_hs <= HS; + if(HS) last_vb <= LVBL; + if(HS && !last_hs) begin + ln_count <= ln_count + 1'b1; + ln_count2 <= ln_count2 + 1'b1; + if( LVBL && !last_vb) ln_count <= 0; + if(!LVBL && last_vb) ln_count2 <= 0; + if(ln_count2==max_ln_count2) lvbs <= 0; + if(ln_count=={2'b0,max_pxl_count} && LVBL) lvbs <= 1; + end +end + +endmodule \ No newline at end of file diff --git a/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/video/jtframe_video_counter.v b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/video/jtframe_video_counter.v new file mode 100644 index 0000000000000000000000000000000000000000..f0ed332e12d1ddcbfced4d30b1f19faeaabb4f46 --- /dev/null +++ b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/video/jtframe_video_counter.v @@ -0,0 +1,59 @@ +/* This file is part of JTFRAME. + JTFRAME program is free software: you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation, either version 3 of the License, or + (at your option) any later version. + + JTFRAME program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with JTFRAME. If not, see . + + Author: Jose Tejada Gomez. Twitter: @topapate + Version: 1.0 + Date: 25-1-2025 */ + +// Provides H and V counters starting at zero while input +// LHBL and LVBL last +module jtframe_video_counter( + input rst, + input clk, + input pxl_cen, + + input lhbl, + input lvbl, + input flip, + + output [8:0] v, h +); + +reg [8:0] vcnt, hcnt; +reg lhbl_l; + +assign v = vcnt ^ { 1'b0, {8{flip}}}; +assign h = hcnt ^ { 1'b0, {8{flip}}}; + +always @(posedge clk) begin + if( rst ) begin + lhbl_l <= 0; + vcnt <= 0; + hcnt <= 0; + end else if(pxl_cen) begin + lhbl_l <= lhbl & lvbl; + if (!lvbl) begin + vcnt <= 0; + end else if( !lhbl && lhbl_l ) begin + vcnt <= vcnt + 9'd1; + end + if (!lhbl) begin + hcnt <= 0; + end else begin + hcnt <= hcnt + 9'd1; + end + end +end + +endmodule diff --git a/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/video/jtframe_vtimer.v b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/video/jtframe_vtimer.v new file mode 100644 index 0000000000000000000000000000000000000000..fd4df26e9d8cacfcddaee725ee1b5f9a436060b3 --- /dev/null +++ b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/video/jtframe_vtimer.v @@ -0,0 +1,204 @@ +/* This file is part of JTFRAME. + JTFRAME program is free software: you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation, either version 3 of the License, or + (at your option) any later version. + + JTFRAME program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with JTFRAME. If not, see . + + Author: Jose Tejada Gomez. Twitter: @topapate + Version: 1.0 + Date: 2-5-2020 */ + + +// Generic video timing generator +// By default vertical blanking and sync toggle with horizontal blanking and sync +// but some games make these signals toggle in the middle of the vertical ones +// See Side Arms for an example + +// By default, H/V counters end with the blanking signal, for some games it +// may be useful to define the end count differently +// Depending on how the graphic hardware is designed, H/V count start and end values +// can be important, as well as when signals toggle (like in a 8-multiple of H) +// but these limitations can be trade off for different ones if the design is changed + +// A default VS pulse of three lines and HS pulse of 4.5us will fit the TV standard +// but some games use different values +// See the parameter definition below to alter the needed parameters when +// instantiating the module + +`ifndef VERILATOR_KEEP_VTIMER +/* verilator tracing_off */ +`endif + +module jtframe_vtimer( + input clk, + input pxl_cen, + output reg [8:0] vdump, + output reg [8:0] vrender, // 1 line ahead of vdump + output reg [8:0] vrender1, // 2 lines ahead + output reg [8:0] H, + output reg Hinit, + output reg Vinit, + output reg LHBL, + output reg LVBL, + output reg HS, + output reg VS +); + +reg LVBL2, LVBL1; + +// Default values suit Contra arcade +parameter [8:0] V_START = 9'd0, + VB_START = 9'd239, + VB_END = 9'd255, + VS_START = 9'd244, + VS_END = (VS_START+9'd3), + VCNT_END = VB_END > VS_END ? VB_END : VS_END, + HB_END = 9'd395, + HB_START = HB_END-9'd116, + HS_START = 9'd330, + HS_END = HS_START+9'd27, // Default 4.5us for a 6MHz clock + H_VB = HB_START, + H_VS = HS_START, + H_VNEXT = HS_START, + HINIT = H_VNEXT, + HJUMP = 0, // set to 1 so the HCNT goes from 0 to FF and then from 180 to 1FF. + // HCNT_START and HCNT_END are ignored if HJUMP is set + HCNT_END = HB_END > HS_END ? HB_END : HS_END, + HCNT_START=9'd0; + +`ifdef SIMULATION +initial begin + // starts off at the beginning of the vertical blanking + // to match MAME timing + Hinit = 0; + Vinit = 0; + LVBL = 0; + LVBL1 = LVBL; + LVBL2 = LVBL; + HS = 0; + VS = 0; + LHBL = 1; + H = HB_START; + vdump = VB_START; + vrender = vdump+1'd1; + vrender1 = vrender+1'd1; + + // VS should be at least 3 line long + // In the case the count is expressed in a funny way + // with VS_END < VS_START, the check is not performed + /* verilator lint_off CMPCONST */ + if ( !(VS_END=3) ) begin + $display("%m assert failed "); + end + + // HS length check is not exact because the pixel clock + // is not known to the module + if ( !(HS_END=27) ) begin + $display("%m assert failed "); + end + /* verilator lint_on CMPCONST */ +end +`endif + +// H counter +always @(posedge clk) if(pxl_cen) begin + Hinit <= H == HINIT; + if( HJUMP[0] ) + H <= H==9'hFF ? 9'h180 : (H+9'd1); + else + H <= H == HCNT_END ? HCNT_START : (H+9'd1); +end + +always @(posedge clk) if(pxl_cen) begin + if( H == H_VNEXT ) begin + Vinit <= vdump==VB_END; + vrender1 <= vrender1==VCNT_END ? V_START : vrender1 + 9'd1; + vrender <= vrender1; + vdump <= vrender; + end + + if( H == HB_START ) begin + LHBL <= 0; + end else if( H == HB_END ) LHBL <= 1; + if( H == H_VB ) begin + { LVBL, LVBL1 } <= { LVBL1, LVBL2 }; + case( vrender1 ) + VB_START: LVBL2 <= 0; + VB_END: LVBL2 <= 1; + default:; + endcase // vdump + end + + if (H==HS_START) begin + HS <= 1; + end + + if (H==HS_END) begin + HS <= 0; + if (vdump==VS_START) VS <= 1; + if (vdump==VS_END ) VS <= 0; + end +end + +`ifdef SIMULATION_VTIMER +reg LVBL_Last, LHBL_last, VS_last, HS_last; + +wire new_line = LHBL_last && !LHBL; +wire new_frame = LVBL_Last && !LVBL; +wire new_HS = HS && !HS_last; +wire new_VS = VS && !VS_last; + +integer vbcnt=0, vcnt=0, hcnt=0, hbcnt=0, vs0, vs1, hs0, hs1; +integer framecnt=0; + +`ifdef SIMULATION_VTIMER_FCLK +real fclk = `SIMULATION_VTIMER_FCLK; +`else +real fclk = 6e6; +`endif + +initial begin + $display("Using %f clock for the results table",fclk); +end + +always @(posedge clk) if(pxl_cen) begin + LHBL_last <= LHBL; + HS_last <= HS; + VS_last <= VS; + if( new_HS ) hs1 <= hbcnt; + if( new_VS ) vs1 <= vbcnt; + if( new_line ) begin + LVBL_Last <= LVBL; + if( new_frame ) begin + if( framecnt>0 ) begin + $display("VB count = %3d (sync at %2d)", vbcnt, vs1 ); + $display("vdump total = %3d (%.2f Hz)", vcnt, fclk/(hcnt*vcnt) ); + $display("HB count = %3d (sync at %2d)", hbcnt, hs1 ); + $display("H total = %3d (%.2f Hz)", hcnt, fclk/hcnt ); + $display("-------------" ); + end + vbcnt <= 1; + vcnt <= 1; + framecnt <= framecnt+1; + end else begin + vcnt <= vcnt+1; + if( !LVBL ) vbcnt <= vbcnt+1; + end + hbcnt <= 1; + hcnt <= 1; + end else begin + hcnt <= hcnt+1; + if( !LHBL ) hbcnt <= hbcnt+1; + end +end +`endif + +endmodule diff --git a/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/video/jtframe_wirebw.v b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/video/jtframe_wirebw.v new file mode 100644 index 0000000000000000000000000000000000000000..0be6bb1abbf2eac00e7b98034647915280a0881b --- /dev/null +++ b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/video/jtframe_wirebw.v @@ -0,0 +1,152 @@ +/* This file is part of JTFRAME. + JTFRAME program is free software: you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation, either version 3 of the License, or + (at your option) any later version. + + JTFRAME program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with JTFRAME. If not, see . + + Author: Jose Tejada Gomez. Twitter: @topapate + Version: 1.0 + Date: 25-9-2019 */ + +// 1. Sets the video to zero during blanking +// 2. Adds a low bandwidth effect to the video signal when enabled + +module jtframe_wirebw #(parameter WIN=4, WOUT=5) ( + input clk, + input spl_in, // sample strobe + input [WIN-1:0] r_in, + input [WIN-1:0] g_in, + input [WIN-1:0] b_in, + input HS_in, + input VS_in, + input LHB_in, + input LVB_in, + input enable, + // filtered video + output reg HS_out, + output reg VS_out, + output reg LHB_out, + output reg LVB_out, + output reg [WOUT-1:0] r_out, + output reg [WOUT-1:0] g_out, + output reg [WOUT-1:0] b_out +); + +wire [ 3:0] dly; +wire [WOUT-1:0] pr, pg, pb; +wire bl_n; + +assign bl_n = enable ? &dly[1:0] : (LHB_in & LVB_in); + +jtframe_sh #(.W(4), .L(4)) u_sh( + .clk ( clk ), + .clk_en ( spl_in ), + .din ( {HS_in, VS_in, LHB_in, LVB_in } ), + .drop ( dly ) +); + +always @(posedge clk) begin + {HS_out, VS_out, LHB_out, LVB_out } <= + enable ? dly : {HS_in, VS_in, LHB_in, LVB_in }; + {r_out,g_out,b_out} <= bl_n ? {pr,pg,pb} : {3*WOUT{1'b0}}; +end + +jtframe_wirebw_unit #(.WIN(WIN),.WOUT(WOUT)) u_rfilter( + .clk ( clk ), + .spl_in ( spl_in ), + .enable ( enable ), + .din ( r_in ), + .dout ( pr ) +); + +jtframe_wirebw_unit #(.WIN(WIN),.WOUT(WOUT)) u_gfilter( + .clk ( clk ), + .spl_in ( spl_in ), + .enable ( enable ), + .din ( g_in ), + .dout ( pg ) +); + +jtframe_wirebw_unit #(.WIN(WIN),.WOUT(WOUT)) u_bfilter( + .clk ( clk ), + .spl_in ( spl_in ), + .enable ( enable ), + .din ( b_in ), + .dout ( pb ) +); + +endmodule + +module jtframe_wirebw_unit #( + parameter WIN = 4, // input data width + WOUT = 6, // output data width + WC = 5, // coefficient width + N = 5, // order, this is only meant to be used with N=3, 5, 7 atmost + AW=WIN+WC+3, // accumulator width + parameter [N*WC-1:0] COEFF = { 5'd0, 5'd7, 5'd20, 5'd7, 5'd0 } +) ( + input clk, // at least N clock pulses between spl_in strobes + input spl_in, // input sample strobe + input [WIN-1:0] din, + input enable, + output [WOUT-1:0] dout +); + +localparam MW=WIN*N; // memory width + +reg [ MW-1:0] mem; +reg [N*WC-1:0] coeff; +reg [ N:0] steps; +reg [ AW-1:0] acc, prod, result; +reg run; +reg [WOUT-1:0] pdout; + +wire [N*WC-1:0] coeff_rotate = { coeff[WC*(N-1)-1:0], coeff[N*WC-1:N*(WC-1)] }; +wire [ MW-1:0] mem_rotate = { mem[MW-WIN-1:0], mem[MW-1:MW-WIN] }; + +always @( coeff, mem ) begin + prod = coeff[WC-1:0] * mem[WIN-1:0]; +end + +always @(*) begin + result = acc >> (WC-(WOUT-WIN)); + if ( result > { {AW-WOUT{1'b0}}, {WOUT{1'b1}}} ) result = { {AW-WOUT{1'b0}}, {WOUT{1'b1}} } ; +end +/* verilator lint_off WIDTHEXPAND */ +function [WOUT-1:0] ext; // extends the input from WIN to WOUT + input [WIN-1:0] a; + ext = { a, {WOUT-WIN{1'b0}} } | (a>>(2*WIN-WOUT)) ; +endfunction +/* verilator lint_on WIDTHEXPAND */ + +// Mux it to avoid adding a clock cycle +assign dout = enable ? pdout : ext(din); + +always @( posedge clk ) begin + if( spl_in ) begin + mem <= { mem[MW-WIN-1:0], din }; + run <= enable; + acc <= {AW{1'd0}}; + steps <= {{N{1'd0}}, 1'd1}; + coeff <= COEFF; + pdout <= result[WOUT-1:0]; + end else if(!steps[N]) begin + steps <= steps<<1; + acc <= acc + prod; + if( run ) begin + coeff <= coeff_rotate; + mem <= mem_rotate; + end + if( steps[N-1] ) run <= 1'd0; + end +end + +endmodule \ No newline at end of file diff --git a/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/video/layouts/jtframe_8x8x4_packed_msb.v b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/video/layouts/jtframe_8x8x4_packed_msb.v new file mode 100644 index 0000000000000000000000000000000000000000..518010c7eb7ba7c04cdc8bc4876245b56104022b --- /dev/null +++ b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/video/layouts/jtframe_8x8x4_packed_msb.v @@ -0,0 +1,44 @@ +/* This file is part of JTFRAME. + JTFRAME program is free software: you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation, either version 3 of the License, or + (at your option) any later version. + + JTFRAME program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with JTFRAME. If not, see . + + Author: Jose Tejada Gomez. Twitter: @topapate + Version: 1.0 + Date: 1-1-2025 */ + +// converts pixel-packed data to plane-packed (MSB=left most pixel) +// packed gfxs; msb and lsb is start nibble of packed pixel byte +// const gfx_layout gfx_8x8x4_packed_msb = +// { +// 8,8, +// RGN_FRAC(1,1), +// 4, +// { STEP4(0,1) }, +// { STEP8(0,4) }, // x order : hi nibble first, low nibble second +// { STEP8(0,4*8) }, +// 8*8*4 +// }; + +module jtframe_8x8x4_packed_msb( + input [31:0] raw, + output [31:0] sorted +); + +assign sorted={ + raw[15], raw[11], raw[7], raw[3], raw[31], raw[27], raw[23], raw[19], + raw[14], raw[10], raw[6], raw[2], raw[30], raw[26], raw[22], raw[18], + raw[13], raw[ 9], raw[5], raw[1], raw[29], raw[25], raw[21], raw[17], + raw[12], raw[ 8], raw[4], raw[0], raw[28], raw[24], raw[20], raw[16] +}; + +endmodule \ No newline at end of file diff --git a/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/video/logodata.hex b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/video/logodata.hex new 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index 0000000000000000000000000000000000000000..bee448abdb58f0cc132e155533bfa5487572a3b8 --- /dev/null +++ b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/video/rotate/frac_interp.v @@ -0,0 +1,81 @@ +module frac_interp #(parameter bitwidth=10, parameter fracwidth=16, parameter centre=1) ( + input clk, + input reset_n, + input [bitwidth-1:0] num, // Larger value + input [bitwidth-1:0] den, // Smaller value + input [bitwidth-1:0] limit, // Blank after this value is reached. + input newfraction, + output reg ready, + input step_reset, + input step_in, + output reg step_out, + output [bitwidth-1:0] whole, + output reg [fracwidth-1:0] fraction, + output blank +); + +wire div_done; +wire [bitwidth+fracwidth-1:0] step; +wire [bitwidth+fracwidth-1:0] remain; /* not used */ + +unsigned_division #(.widthlog2(bitwidth+fracwidth)) div ( + .clk(clk), + .reset_n(reset_n), + .dividend({num,{fracwidth{1'b0}}}), + .divisor({{fracwidth{1'b0}},den}), + .quotient(step), + .remainder(remain), + .req(newfraction), + .ack(div_done) +); + +reg [bitwidth+fracwidth-1:0] spos; +wire [bitwidth-1:0] spos_whole = spos[bitwidth+fracwidth-1:fracwidth]; +wire [fracwidth-1:0] spos_frac = spos[fracwidth-1:0]; + +reg [bitwidth-1:0] dpos; + +reg [bitwidth-1:0] whole_i; +reg [bitwidth-1:0] offset; + +always @(posedge clk) begin + step_out<=1'b0; + if (step_in) begin + if(dpos>spos_whole) begin + spos<=spos+step; + fraction<=spos_frac; + step_out<=1'b1; + whole_i<=whole_i+1'd1; + end else + fraction<=0; + if(|offset) + offset<=offset-1'd1; + else + dpos<=dpos+1'b1; + end + if (newfraction || reset_n) + ready <= 1'b0; + + if (centre && whole_i>limit) // HACK: Extend the span by one pixel when processing rows. + offset<={bitwidth{1'b1}}; // Ensure the rest of the span is blanked + + if (!centre && whole_i==limit) + offset<={bitwidth{1'b1}}; // Ensure the rest of the span is blanked + + if (step_reset || newfraction || !reset_n) begin + spos<=0; + dpos<=0; + whole_i<=0; + offset<=(centre && den>num) ? (den-num) >> 1 : {bitwidth{1'b0}}; + end + + if(div_done) + ready<=1'b1; +end + +assign whole=whole_i; + +assign blank=|offset; + +endmodule + diff --git a/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/video/rotate/pixel_interp.v b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/video/rotate/pixel_interp.v new file mode 100644 index 0000000000000000000000000000000000000000..7cde23f1165a3a55fc707fb5b90fc8d3dff68aea --- /dev/null +++ b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/video/rotate/pixel_interp.v @@ -0,0 +1,32 @@ +module pixel_interp #(parameter signalwidth=8, parameter fracwidth = 8) +( + input clk, + input blank, + input [fracwidth-1:0] frac, + input [signalwidth-1:0] in, + input [signalwidth-1:0] in_prev, + output [signalwidth-1:0] out +); + +reg [fracwidth:0] invfrac; +reg [fracwidth:0] frac_d; + +reg [signalwidth+fracwidth:0] in_scaled; +reg [signalwidth+fracwidth:0] in_prev_scaled; + +reg [signalwidth+fracwidth:0] sum; + +always @(posedge clk) begin + invfrac <=1'b1 + {1'b0,~frac}; + frac_d <= {1'b0,frac}; + + in_scaled<=invfrac*in; + in_prev_scaled<=frac_d*in_prev; + + sum<=in_scaled+in_prev_scaled; +end + +assign out=blank ? {signalwidth{1'b0}} : sum[signalwidth+fracwidth-1:fracwidth]; + +endmodule + diff --git a/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/video/rotate/scandoubler_rgb_interp.v b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/video/rotate/scandoubler_rgb_interp.v new file mode 100644 index 0000000000000000000000000000000000000000..e59d3caf318dab28c80001f9dfcccd681bb168ff --- /dev/null +++ b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/video/rotate/scandoubler_rgb_interp.v @@ -0,0 +1,41 @@ +module scandoubler_rgb_interp ( + input clk_sys, + input blank, + input [7:0] fraction, + input [15:0] rgb_in, + input [15:0] rgb_in_prev, + output [15:0] rgb_out +); + +pixel_interp #(.signalwidth(5),.fracwidth(8)) interp_red +( + .clk(clk_sys), + .blank(blank), + .frac(fraction), + .in(rgb_in[15:11]), + .in_prev(rgb_in_prev[15:11]), + .out(rgb_out[15:11]) +); + +pixel_interp #(.signalwidth(6),.fracwidth(8)) interp_green +( + .clk(clk_sys), + .blank(blank), + .frac(fraction), + .in(rgb_in[10:5]), + .in_prev(rgb_in_prev[10:5]), + .out(rgb_out[10:5]) +); + +pixel_interp #(.signalwidth(5),.fracwidth(8)) interp_blue +( + .clk(clk_sys), + .blank(blank), + .frac(fraction), + .in(rgb_in[4:0]), + .in_prev(rgb_in_prev[4:0]), + .out(rgb_out[4:0]) +); + +endmodule + diff --git a/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/video/rotate/scandoubler_rotate.v b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/video/rotate/scandoubler_rotate.v new file mode 100644 index 0000000000000000000000000000000000000000..37baff6e785f71fbf1e5eb6f7eebe807b6a0dfcd --- /dev/null +++ b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/video/rotate/scandoubler_rotate.v @@ -0,0 +1,386 @@ +// +// scandoubler_rotate.v +// +// Copyright (c) 2024 Alastair M. Robinson +// +// This source file is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published +// by the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This source file is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . + +// Streams incoming video data to an SDRAM port, in 16-word bursts. +// Incoming data is scaled to RGB565 +// +// Streams data from SDRAM to output linebuffers in 8-word bursts +// Outgoing data is scaled to OUT_COLOR_DEPTH +// +// The SDRAM controller is responsible for the actual cornerturn. +// + +module scandoubler_rotate #(parameter + HCNT_WIDTH = 10, // Resolution of scandoubler buffer + COLOR_DEPTH = 6, // Bits per colour to be stored in the buffer + OUT_COLOR_DEPTH = 6, // Bits per color outputted + XPOS_MIN = 4'd10 // Filter out partial lines do to H/Vblank misalignments) +)( + // system interface + input clk_sys, + + input [1:0] rotation, // 0 - no rotation, 1 - clockwise, 2 - anticlockwise + input rotateonly, + input hfilter, + input vfilter, + + // Pixelclock + input pe_in, + input ppe_out, + + // incoming video interface + input hb_in, + input vb_in, + input hs_in, + input vs_in, + input [COLOR_DEPTH-1:0] r_in, + input [COLOR_DEPTH-1:0] g_in, + input [COLOR_DEPTH-1:0] b_in, + + // output interface + input hb_sd, + input vb_sd, + input vs_sd, + output [OUT_COLOR_DEPTH-1:0] r_out, + output [OUT_COLOR_DEPTH-1:0] g_out, + output [OUT_COLOR_DEPTH-1:0] b_out, + + // Memory interface - to RAM. Operates on 16-word bursts + output reg vidin_req, // High at start of row, remains high until burst of 16 pixels has been delivered + output wire [1:0] vidin_frame, // Odd or even frame for double-buffering + output reg [10:0] vidin_row, // X position of current row (after rotation). + output reg [10:0] vidin_col, // Y position of current burst (after rotation). + output reg [15:0] vidin_d, // Incoming video data + input wire vidin_ack, // Request next word from host + + // Memory interface - from RAM. Operates on 8-word bursts + output wire vidout_req, // High at start of row, remains high until entire row has been delivered + output wire [1:0] vidout_frame, // Odd or even frame for double-buffering + output wire [10:0] vidout_row, // Y position of current row. + output wire [10:0] vidout_col, // X position of current burst. + input wire [15:0] vidout_d, // Outgoing video data + input wire vidout_ack // Valid data available. +); + +// Scale incoming video signal to RGB565 +wire [15:0] vin_rgb565; + +scandoubler_scaledepth #(.IN_DEPTH(COLOR_DEPTH),.OUT_DEPTH(5)) scalein_r (.d(r_in),.q(vin_rgb565[15:11])); +scandoubler_scaledepth #(.IN_DEPTH(COLOR_DEPTH),.OUT_DEPTH(6)) scalein_g (.d(g_in),.q(vin_rgb565[10:5])); +scandoubler_scaledepth #(.IN_DEPTH(COLOR_DEPTH),.OUT_DEPTH(5)) scalein_b (.d(b_in),.q(vin_rgb565[4:0])); + + +// Stream incoming pixels to SDRAM, taking care of inverting either X or Y coordinates. +// The SDRAM controller does the actual cornerturn. + +// Framing +reg [HCNT_WIDTH-1:0] in_xpos; +reg [HCNT_WIDTH-1:0] in_ypos=239; +reg [HCNT_WIDTH-1:0] in_xpos_max = 320; +reg [HCNT_WIDTH-1:0] in_ypos_max = 238; +reg hb_in_d; + +// Toggle logical / physical frame every vblank +reg [1:0] logicalframe = 2'b00; +reg vb_d = 1'b1; + +always @(posedge clk_sys) if (pe_in) begin + vb_d<=vb_in; + if(!vb_d && vb_in) begin + logicalframe<=~logicalframe; + in_ypos_max<=in_ypos - (in_xpos <= XPOS_MIN); + end +end + +always @(posedge clk_sys) if (pe_in) begin + hb_in_d<=hb_in; + if(vb_in) + in_ypos<=0; + else if(!hb_in_d && hb_in && in_xpos > XPOS_MIN) begin // Increment row on hblank + in_ypos<=in_ypos+1'd1; + in_xpos_max <= in_xpos; + end +end + +reg [3:0] rowwptr; + +always @(posedge clk_sys) if (pe_in) begin + if((hb_in | vb_in) && rowwptr[3:0] == 0) + in_xpos<=0; + else if (!hb_in & !vb_in) + in_xpos<=in_xpos+1'd1; // Increment column on pixel enable +end + +// Buffer incoming video data and write to SDRAM. +// (16 word bursts, striped across two banks, SDRAM controller handles the actual cornerturn) + +reg [15:0] rowbuf[0:15] /* synthesis ramstyle="logic" */; +reg [3:0] rowrptr; +reg running=1'b0; + +wire [3:0] escape,start; + +always @(posedge clk_sys) begin + + // Reset on vblank + if(vb_in) begin + running<=1'b1; + rowwptr<=4'h0; + end + + // Don't update row during hblank (gives linebuffer time to empty) + if(!hb_in) begin + if(rotation[0]) + vidin_row<=in_ypos_max-in_ypos; + else + vidin_row<=in_ypos; + end + + // Write incoming pixels to a line buffer + if(running && pe_in && !vb_in && (!hb_in || rowwptr[3:0] != 0)) begin + rowbuf[rowwptr]<=vin_rgb565; + rowwptr<=rowwptr+1'b1; + if(rowwptr[2:0]==3'b111) begin + vidin_col<=in_xpos; + vidin_req<=1'b1; + rowrptr<={rowwptr[3],3'b000}; + end + end + + // Write pixels from linebuffer to SDRAM + vidin_d <= rowbuf[rowrptr]; + vidin_col[2:0] <= rowrptr[2:0]; + + // Terminate burst after 16 pixels + if(vidin_ack) begin + if(rowrptr[2:0]==3'b111) + vidin_req<=1'b0; + rowrptr<=rowrptr+1'b1; + end +end + +assign vidin_frame = logicalframe; + + +// Pixel read process - streams data from SDRAM to linebuffers. + +reg [15:0] linebuffer1 [0:2**HCNT_WIDTH-1]; +reg [15:0] linebuffer2 [0:2**HCNT_WIDTH-1]; + +reg fetch; + +reg [HCNT_WIDTH-1:0] fetch_xpos; +reg [HCNT_WIDTH-1:0] sd_ypos; + +reg hb_sd_d; +reg vs_sd_d; + +reg hb_sd_stb; +reg vs_sd_stb; + + +localparam vi_fracwidth=16; +localparam hi_fracwidth=16; + +wire [HCNT_WIDTH-1:0] vi_whole; // Row number +wire [hi_fracwidth-1:0] vi_fraction; // Blend factor +wire vi_step; // Move onto the next line +wire vi_ready; +wire vi_blank; + +frac_interp #(.bitwidth(HCNT_WIDTH),.fracwidth(vi_fracwidth),.centre(0)) interp_core_v ( + .clk(clk_sys), + .reset_n(1'b1), + //.num({in_ypos_max[HCNT_WIDTH-2:0],1'b0}), + .num(in_ypos_max[HCNT_WIDTH-1:0] << ~rotateonly), + .den(in_xpos_max), + .limit(in_xpos_max), + .newfraction(vs_sd_stb), + .ready(vi_ready), + .step_reset(vs_sd_stb), + .step_in(hb_sd_stb), + .step_out(vi_step), + .whole(vi_whole), + .fraction(vi_fraction), + .blank(vi_blank) +); + +reg fetchbuffer; +reg vs_sd_stb_d; + +always @(posedge clk_sys) begin + + hb_sd_d<=hb_sd; + vs_sd_d<=vs_sd; + + vs_sd_stb<=1'b0; + if(!vs_sd_d && vs_sd) + vs_sd_stb<=1'b1; + vs_sd_stb_d<=vs_sd_stb; + + sd_ypos <= rotation[0] ? vi_whole : in_xpos_max-vi_whole - 1'd1; + + hb_sd_stb<=1'b0; + if(!vb_sd && !hb_sd_d && hb_sd) + hb_sd_stb<=1'b1; + + if (vi_step) begin + fetch_xpos <= 0; + fetch<=1'b1; + fetchbuffer<=fetchbuffer ^ vfilter; + end + + if(vs_sd_stb_d) begin + fetch_xpos <= 0; // Pre-fetch the first row after the frac_interp has reset the row number + fetch<=1'b1; + fetchbuffer<=1'b0; + end + + if(fetch && fetch_xpos==in_ypos_max) + fetch<=1'b0; + + if(vidout_ack) begin + fetch_xpos<=fetch_xpos+1'd1; + if(fetchbuffer) + linebuffer1[fetch_xpos]<=vidout_d; + else + linebuffer2[fetch_xpos]<=vidout_d; + end + +end + +assign vidout_row = sd_ypos; +assign vidout_col = fetch_xpos; + +assign vidout_frame = ~logicalframe; +assign vidout_req = fetch; + + +// Basic horizontal interpolation + +wire [HCNT_WIDTH-1:0] hi_whole; // Index into pixel buffer +wire [hi_fracwidth-1:0] hi_fraction; // Blend factor +wire hi_step; // Move onto the next pixel +wire hi_ready; +wire hi_blank; + +frac_interp #(.bitwidth(HCNT_WIDTH),.fracwidth(hi_fracwidth),.centre(1)) interp_core_h ( + .clk(clk_sys), + .reset_n(1'b1), + //.num({in_ypos_max[HCNT_WIDTH-2:0],1'b0}), + .num(in_ypos_max), + .den(in_xpos_max), + .limit(in_ypos_max), + .newfraction(vs_sd_stb), + .ready(hi_ready), + .step_reset(hb_sd_stb), + .step_in(!hb_sd && ppe_out), + .step_out(hi_step), + .whole(hi_whole), + .fraction(hi_fraction), + .blank(hi_blank) +); + +// Interpolate pixels + +reg [15:0] row1_pix1; +reg [15:0] row2_pix1; +reg [15:0] row1_pix2; +reg [15:0] row2_pix2; +wire [15:0] col_pix1; +wire [15:0] col_pix2; +wire [15:0] final_rgb565; + +reg [2:0] hi_blank_d; + +always @(posedge clk_sys) begin + hi_blank_d<= {hi_blank_d[1:0],hi_blank}; + + if(fetchbuffer) begin + row1_pix1<=linebuffer1[hi_whole]; + row2_pix1<=linebuffer2[hi_whole]; + end else begin + row2_pix1<=linebuffer1[hi_whole]; + row1_pix1<=linebuffer2[hi_whole]; + end + + if(hi_step) begin + if(rotateonly) begin + if (fetchbuffer) begin + row1_pix2 <= row2_pix1; + row2_pix2 <= row2_pix1; + end + else + begin + row1_pix2 <= row1_pix1; + row2_pix2 <= row1_pix1; + end + end + else begin + row1_pix2<=row1_pix1; + row2_pix2<=row2_pix1; + end + end + + if(hi_whole > in_ypos_max) begin + {row1_pix1, row2_pix1} <= 0; + {row1_pix2, row2_pix2} <= 0; + end + +end + +wire [7:0] hfilter_fraction = hfilter ? hi_fraction[15:8] : 8'h00; +wire [7:0] vfilter_fraction = vfilter ? vi_fraction[15:8] : 8'h00; + +scandoubler_rgb_interp rgbinterp_h1 +( + .clk_sys(clk_sys), + .blank(hi_blank_d[2]), + .fraction(hfilter_fraction), + .rgb_in(row1_pix1), + .rgb_in_prev(row1_pix2), + .rgb_out(col_pix1) +); + +scandoubler_rgb_interp rgbinterp_h2 +( + .clk_sys(clk_sys), + .blank(hi_blank_d[2]), + .fraction(hfilter_fraction), + .rgb_in(row2_pix1), + .rgb_in_prev(row2_pix2), + .rgb_out(col_pix2) +); + +scandoubler_rgb_interp rgbinterp_v +( + .clk_sys(clk_sys), + .blank(vi_blank), + .fraction(vfilter_fraction), + .rgb_in(col_pix1), + .rgb_in_prev(col_pix2), + .rgb_out(final_rgb565) +); + +scandoubler_scaledepth #(.IN_DEPTH(5),.OUT_DEPTH(OUT_COLOR_DEPTH)) scaleout_r (.d(final_rgb565[15:11]),.q(r_out)); +scandoubler_scaledepth #(.IN_DEPTH(6),.OUT_DEPTH(OUT_COLOR_DEPTH)) scaleout_g (.d(final_rgb565[10: 5]),.q(g_out)); +scandoubler_scaledepth #(.IN_DEPTH(5),.OUT_DEPTH(OUT_COLOR_DEPTH)) scaleout_b (.d(final_rgb565[ 4: 0]),.q(b_out)); + +endmodule + + diff --git a/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/video/rotate/scandoubler_scaledepth.v b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/video/rotate/scandoubler_scaledepth.v new file mode 100644 index 0000000000000000000000000000000000000000..14964a7f676d1fd31a332d15cf6e02bb23c9a663 --- /dev/null +++ b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/video/rotate/scandoubler_scaledepth.v @@ -0,0 +1,36 @@ +// Utility module for scaling the bit depth of a signal +// Factored out of the scandoubler by AMR, and adjusted to cope with +// output bit depth being less than input depth + +module scandoubler_scaledepth #( +parameter IN_DEPTH = 6, + OUT_DEPTH = 6 +)( + input [IN_DEPTH-1:0] d, + output wire [OUT_DEPTH-1:0] q +); + +localparam m = OUT_DEPTH < IN_DEPTH ? 1 : OUT_DEPTH/IN_DEPTH; +localparam n = OUT_DEPTH < IN_DEPTH ? 0 : OUT_DEPTH%IN_DEPTH; +localparam o = OUT_DEPTH < IN_DEPTH ? OUT_DEPTH : IN_DEPTH; + +reg[OUT_DEPTH-1:0] scaled; + +always @(*) begin +/* Verilator lint_off SELRANGE */ +/* Verilator lint_off WIDTH */ + if (m>0) begin + if (n>0) begin + scaled = { {m{d[IN_DEPTH-1 -:o]}}, d[IN_DEPTH-1 -:n] }; + end else begin + scaled = { {m{d[IN_DEPTH-1 -:o]}} }; + end + end +/* Verilator lint_on SELRANGE */ +/* Verilator lint_on WIDTH */ +end + +assign q=scaled; + +endmodule + diff --git a/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/video/rotate/scandoubler_sdram.v b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/video/rotate/scandoubler_sdram.v new file mode 100644 index 0000000000000000000000000000000000000000..018e87a76cc0717219fd8c549ff638e0d7199445 --- /dev/null +++ b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/video/rotate/scandoubler_sdram.v @@ -0,0 +1,342 @@ +`timescale 1ns/10ps +// +// sdram.v +// +// sdram controller implementation for the MiST board +// https://github.com/mist-devel/mist-board +// +// Copyright (c) 2013 Till Harbaum +// +// This source file is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published +// by the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This source file is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +// + +module scandoubler_sdram ( + // interface to the MT48LC16M16 chip + inout wire [15:0] sd_data, // 16 bit bidirectional data bus + output reg [12:0] sd_addr, // 13 bit multiplexed address bus + output reg [1:0] sd_dqm, // two byte masks + output reg [1:0] sd_ba, // two banks + output wire sd_cs, // a single chip select + output wire sd_we, // write enable + output wire sd_ras, // row address select + output wire sd_cas, // columns address select + + // cpu/chipset interface + input wire init, // init signal after FPGA config to initialize RAM + input wire clk, + output wire ready, + + input wire [15:0] ram_din, // data input from chipset/cpu + output reg [15:0] ram_dout, + input wire [22:0] ram_addr, // 23 bit word address + input wire [1:0] ram_ds, // upper/lower data strobe + input wire ram_req, // cpu/chipset requests read/write + input wire ram_we, // cpu/chipset requests write + output reg ram_ack, + + input wire rom_oe, + input wire[22:0] rom_addr, + output reg [15:0] rom_dout, + + input wire vidin_req, // High at start of row, remains high until burst of 16 pixels has been delivered + input wire [1:0] vidin_frame, // Odd or even frame for double-buffering + input wire [10:0] vidin_row, // Y position of current row. + input wire [10:0] vidin_col, // X position of current burst. + input wire [15:0] vidin_d, // Incoming video data + output wire vidin_ack, // Request next word from host + + input wire vidout_req, // High at start of row, remains high until entire row has been delivered + input wire [1:0] vidout_frame, // Odd or even frame for double-buffering + input wire [10:0] vidout_row, // Y position of current row. (Controller maintains X counter) + input wire [10:0] vidout_col, // Y position of current row. (Controller maintains X counter) + output reg [15:0] vidout_q, // Outgoing video data + output reg vidout_ack // Valid data available. +); + +localparam RASCAS_DELAY = 3'd2; // tRCD=20ns -> 2 cycles@96MHz +localparam BURST_LENGTH = 3'b011; // 000=1, 001=2, 010=4, 011=8 +localparam ACCESS_TYPE = 1'b0; // 0=sequential, 1=interleaved +localparam CAS_LATENCY = 3'd2; // 2/3 allowed +localparam OP_MODE = 2'b00; // only 00 (standard operation) allowed +localparam NO_WRITE_BURST = 1'b1; // 0= write burst enabled, 1=only single access write + +localparam MODE = { 3'b000, NO_WRITE_BURST, OP_MODE, CAS_LATENCY, ACCESS_TYPE, BURST_LENGTH}; + + +// --------------------------------------------------------------------- +// ------------------------ cycle state machine ------------------------ +// --------------------------------------------------------------------- + +// The state machine runs at 96Mhz synchronous to the 8 Mhz chipset clock. +// It wraps from T15 to T0 on the rising edge of clk_8 + +localparam STATE_FIRST = 5'd0; // first state in cycle +localparam STATE_CMD_CONT = STATE_FIRST + {2'b00,RASCAS_DELAY}; // command can be continued +localparam STATE_READ = STATE_CMD_CONT + {2'b00,CAS_LATENCY} + 5'd2; +localparam STATE_END = 5'd7; // last state in cycle +localparam STATE_VIDREADEND = STATE_CMD_CONT+{2'b00,CAS_LATENCY}+5'd10; +localparam STATE_VIDWRITEEND = STATE_CMD_CONT+5'd11; + +reg [4:0] t = STATE_FIRST; + +// --------------------------------------------------------------------- +// --------------------------- startup/reset --------------------------- +// --------------------------------------------------------------------- + +// wait 1ms (32 8Mhz cycles) after FPGA config is done before going +// into normal operation. Initialize the ram in the last 16 reset cycles (cycles 15-0) +reg [4:0] reset = 5'h1f; +reg vidwrite = 0; +reg vidread = 0; +always @(posedge clk or posedge init) begin + if(init) begin + reset <= 5'h1f; + t <= STATE_FIRST; + end + else + begin + t<=t+1'd1; + + if (vidwrite & ~|reset) begin + if (t == STATE_VIDWRITEEND) + t <= STATE_FIRST; + end else if (vidread & ~|reset) begin + if (t == STATE_VIDREADEND) + t <= STATE_FIRST; + end else + if (t == STATE_END) + t <= STATE_FIRST; + + if((t == STATE_END) && (reset != 0)) + reset <= reset - 5'd1; + end +end + +// --------------------------------------------------------------------- +// ------------------ generate ram control signals --------------------- +// --------------------------------------------------------------------- + +// all possible commands +localparam CMD_INHIBIT = 4'b1111; +localparam CMD_NOP = 4'b0111; +localparam CMD_ACTIVE = 4'b0011; +localparam CMD_READ = 4'b0101; +localparam CMD_WRITE = 4'b0100; +localparam CMD_BURST_TERMINATE = 4'b0110; +localparam CMD_PRECHARGE = 4'b0010; +localparam CMD_AUTO_REFRESH = 4'b0001; +localparam CMD_LOAD_MODE = 4'b0000; + +reg [3:0] sd_cmd; // current command sent to sd ram +// drive control signals according to current command +assign sd_cs = sd_cmd[3]; +assign sd_ras = sd_cmd[2]; +assign sd_cas = sd_cmd[1]; +assign sd_we = sd_cmd[0]; + +reg [15:0] sd_din; + +// 4 byte read burst goes through four addresses +reg [15:0] sd_data_reg; +reg [15:0] data_latch; +reg [22:0] addr_latch; +reg [15:0] din_latch; +reg req_latch = 0; +reg rom_port; +reg we_latch; +reg drive_dq; + +reg vidwrite_next; + + +assign vidin_ack = vidwrite_next; + +assign sd_data=drive_dq ? sd_data_reg : 16'bZZZZZZZZZZZZZZZZ; + +assign ready = |reset ? 1'b0 : ~init; + +always @(posedge clk) begin + // permanently latch ram data to reduce delays + sd_din <= sd_data; + drive_dq<=1'b0; + sd_cmd <= CMD_NOP; // default: idle + sd_dqm <= 2'b11; + + if(reset != 0) begin + // initialization takes place at the end of the reset phase + sd_ba <= 0; + ram_ack <= ram_req; + if(t == STATE_FIRST) begin + if(reset == 13) begin + sd_cmd <= CMD_PRECHARGE; + sd_addr[10] <= 1'b1; // precharge all banks + end + + if(reset == 10 || reset == 8) begin + sd_cmd <= CMD_AUTO_REFRESH; + end + + if(reset == 2) begin + sd_cmd <= CMD_LOAD_MODE; + sd_addr <= MODE; + end + + end + end else begin + vidout_ack<=1'b0; + // normal operation + if(t == STATE_FIRST) begin + req_latch <=1'b0; + vidwrite<=1'b0; + vidread<=1'b0; + if (ram_req ^ ram_ack) begin + addr_latch <= ram_addr; + req_latch <= 1; + din_latch <= ram_din; + rom_port <= 0; + we_latch <= ram_we; + + // RAS phase + sd_cmd <= CMD_ACTIVE; + sd_addr <= ram_addr[21:9]; + sd_ba <= {1'b0,ram_addr[22]}; + + end else if (rom_oe && (addr_latch != rom_addr)) begin + addr_latch <= rom_addr; + req_latch <= 1; + rom_port <= 1; + we_latch <= 1'b0; + + // RAS phase + sd_cmd <= CMD_ACTIVE; + sd_addr <= rom_addr[21:9]; + sd_ba <= {1'b0,rom_addr[22]}; + end else if (vidin_req) begin + vidwrite<=1'b1; + sd_ba <= 2'b11; + sd_addr <= {vidin_frame,vidin_col[9:5],vidin_row[9:4]}; +// $display("vidwrite (%t) bank %d, row %h", $time, {1'b1,vidin_col[3]}, {2'b11,vidin_frame,vidin_col[9:4],~vidin_row[9:6]}); + sd_cmd <= CMD_ACTIVE; + end else if (vidout_req) begin + vidread<=1'b1; + // ba(0) <= x(3); // Stripe adjacent pixel blocks across banks + sd_ba <= 2'b11; + sd_addr <= {vidout_frame,vidout_row[9:5],vidout_col[9:4]}; + sd_cmd <= CMD_ACTIVE; +// $display("vidread (%t) read bank %d, row %h", $time, {1'b1,vidout_row[3]}, {2'b11,vidout_frame,vidout_row[9:4],~vidout_col[9:6]}); + + end else begin + req_latch <= 0; + sd_cmd <= CMD_AUTO_REFRESH; + end + end + + // Video write: + // Address mapping: + // col(3 downto 0) <= y(3 downto 0); // 4 bits, 16 words + // col(8 downto 4) <= x(4 downto 0); // 5 bits, 32 words + // col(9) <= y(10); // On 64 meg chips only + // row(5 downto 0) <= y(9 downto 4); // 6 bits + // row(10 downto 6) <= x(9 downto 5); // 5 bits + // row(12 downto 11) <= frame; + + vidwrite_next<=1'b0; + + if(vidwrite) begin + if(t>=(STATE_CMD_CONT-1) && t =STATE_CMD_CONT+1 && t<=STATE_CMD_CONT+8) begin + sd_dqm <= 2'b00; + sd_data_reg <= vidin_d; + drive_dq <= 1'b1; + + sd_addr[12:11] <= 2'b00; + sd_addr[10] <= 1'b0; + sd_ba <= 2'b11; + if(t==STATE_CMD_CONT+8) + sd_addr[10] <= 1'b1; // Auto precharge + sd_addr[9:0] <= {vidin_row[10],vidin_col[4:0],vidin_row[3:0]}; + sd_cmd<=CMD_WRITE; +// $display("vidwrite (%t) bank %d, col %h", $time, sd_ba, {1'b0,vidin_col[2:0],~vidin_row[5:0]}); + end + end + + // Video read: + // Address mapping: + // col(3 downto 0) <= x(3 downto 0); + // col(8 downto 4) <= y(4 downto 0); + // col(9) <= x(10; // on 64 meg chips only + // row(5 downto 0) <= x(9 downto 4); + // row(10 downto 6) <= y(9 downto 5); + // row(12 downto 11) <= frame; + + if(vidread) begin + if(t == STATE_CMD_CONT) begin + sd_addr[12:11] <= 2'b00; + sd_addr[10] <= 1'b1; // Auto precharge + sd_addr[9:0] <= {vidout_col[10],vidout_row[4:0],vidout_col[3],3'b0}; + sd_cmd <= CMD_READ; +// $display("vidread (%t) column %h", $time, {1'b0,vidout_row[2:0],vidout_col[5:0]}); + end + if(t>=STATE_CMD_CONT) sd_dqm <= 2'b00; + + if(t>=STATE_READ && t<(STATE_READ+8)) begin + vidout_q<=sd_din; + vidout_ack <= 1'b1; + end + end + + + // ------------------- cpu/chipset read/write ---------------------- + if(req_latch) begin + + // CAS phase + if(t == STATE_CMD_CONT) begin + sd_cmd <= we_latch?CMD_WRITE:CMD_READ; + if (we_latch) begin + sd_data_reg <= din_latch; + drive_dq<=1'b1; + ram_ack <= ram_req; + end + // always return both bytes in a read. The cpu may not + // need it, but the caches need to be able to store everything + sd_dqm <= we_latch ? ~ram_ds : 2'b00; + + sd_addr <= { we_latch ? 4'b0010 : 4'b0000, addr_latch[8:0] }; // auto precharge for writes only + end + + if(t == STATE_CMD_CONT+3) begin + if(!we_latch) begin + sd_cmd <= CMD_PRECHARGE; + sd_addr[10]<=1'b0; + end + end + + // read phase + if(!we_latch || rom_port) begin + if(t == STATE_READ) begin + if (rom_port) + rom_dout <= sd_din; + else begin + ram_dout <= sd_din; + ram_ack <= ram_req; + end + end + end + end + end +end + +endmodule diff --git a/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/video/rotate/unsigned_division.v b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/video/rotate/unsigned_division.v new file mode 100644 index 0000000000000000000000000000000000000000..079213200a9b73f69c5f45ace578de2cebaf27e7 --- /dev/null +++ b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/video/rotate/unsigned_division.v @@ -0,0 +1,78 @@ +module unsigned_division #( + parameter widthlog2 = 8 +) ( + input clk, + input reset_n, + input [widthlog2-1:0] dividend, + input [widthlog2-1:0] divisor, + output reg [widthlog2-1:0] quotient, + output reg [widthlog2-1:0] remainder, + input req, + output reg ack +); + +reg ack_int; +reg [widthlog2-1:0] bitcounter; +reg [widthlog2-1:0] quot; +reg [widthlog2-1:0] div; +reg [widthlog2-1:0] remain; + +localparam IDLE=0; +localparam RUN=1; +localparam FINALISE=2; + +reg [1:0] state=IDLE; + +always @(posedge clk) begin + ack <= 1'b0; + + if(!reset_n) begin + state <= IDLE; + end else begin + + case (state) + IDLE : begin + if(req) begin + remain=0; + quot<=dividend; + div<=divisor; + /* verilator lint_off WIDTH */ + bitcounter<=(widthlog2[widthlog2-1:0]-1'd1); + /* verilator lint_on WIDTH */ + state <= RUN; + end + end + + RUN : begin + if (remain[widthlog2-1]) + remain={remain[widthlog2-1-1:0],quot[widthlog2-1]} + div; + else + remain={remain[widthlog2-1-1:0],quot[widthlog2-1]} - div; + + quot[widthlog2-1:1]<=quot[widthlog2-1-1:0]; + quot[0]<=~remain[widthlog2-1]; + + if(|bitcounter) + bitcounter<=bitcounter-1'b1; + else + state <= FINALISE; + end + + FINALISE : begin + if (remain[widthlog2-1]) + remainder<=remain+div; + else + remainder<=remain; + + quotient<=quot; + ack<=1'b1; + state<=IDLE; + + end + + endcase + end +end + +endmodule + diff --git a/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/video/tilemap/jtframe_scroll.v b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/video/tilemap/jtframe_scroll.v new file mode 100644 index 0000000000000000000000000000000000000000..a3717723b74d8d37809ddbce42aeac3d213e6576 --- /dev/null +++ b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/video/tilemap/jtframe_scroll.v @@ -0,0 +1,141 @@ +/* This file is part of JTFRAME. + JTFRAME program is free software: you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation, either version 3 of the License, or + (at your option) any later version. + + JTFRAME program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with JTFRAME. If not, see . + + Author: Jose Tejada Gomez. Twitter: @topapate + Version: 1.0 + Date: 15-12-2022 */ + + +// Generic tile map generator with scroll +// The ROM data must be in these format +// code, H parts, V part +// pixel data is 4bpp, and arrives in four bytes. Each byte is for a plane + +module jtframe_scroll #( parameter + SIZE = 8, // 8x8, 16x16 or 32x32 + VA = 12, + CW = 12, + PW = 8, + MAP_HW = 9, // 2^MAP_HW = size of the map in pixels + MAP_VW = 9, + VR = SIZE==8 ? CW+3 : SIZE==16 ? CW+5 : CW+7, + // override VH and HW only for non rectangular tiles + VW = SIZE==8 ? 3 : SIZE==16 ? 4:5, + HW = VW, + ROM_HFLIP = 1, + XOR_HFLIP = 0, // set to 1 so hflip gets ^ with flip + XOR_VFLIP = 0, // set to 1 so vflip gets ^ with flip + HJUMP = 1, // set to 0 for linear hdump starting at zero after HB + HLOOP = 0, // see jtframe_scroll_offset + COL_SCROLL = 0 // set to 1 to enable 8-pixel column scroll +)( + input rst, + input clk, + input pxl_cen, + + input hs, + + input [8:0] vdump, + input [8:0] hdump, + input blankn, // if !blankn there are no ROM requests + input flip, // Screen flip + input [MAP_HW-1:0] scrx, + input [MAP_VW-1:0] scry, + + output [VA-1:0]vram_addr, + + input [CW-1:0]code, + input [PW-5:0]pal, + input hflip, + input vflip, + + output [VR-1:0]rom_addr, + input [31:0] rom_data, + output rom_cs, + input rom_ok, // ignored. It assumes that data is always right + + output [PW-1:0]pxl +); + +// hdump/vdump dimensions can be larger than the screen for the scroll use case +// but the MSBs will be fixed +localparam HDUMPW = MAP_HW, VDUMPW = MAP_VW; + +wire [VDUMPW-1:0] veff; +wire [HDUMPW-1:0] heff; + +jtframe_scroll_offset #( + .MAP_HW ( MAP_HW ), + .MAP_VW ( MAP_VW ), + .HDUMPW ( HDUMPW ), + .VDUMPW ( VDUMPW ), + .HLOOP ( HLOOP ), + .COL_SCROLL ( COL_SCROLL) +) u_offset( + .clk ( clk ), + .flip ( flip ), + .scrx ( scrx ), + .scry ( scry ), + .hs ( hs ), + .hdump ( hdump ), + .vdump ( vdump ), + .heff ( heff ), + .veff ( veff ) +); + +jtframe_tilemap #( + .SIZE ( SIZE ), + .VA ( VA ), + .CW ( CW ), + .PW ( PW ), + .MAP_HW ( MAP_HW ), + .MAP_VW ( MAP_VW ), + .HDUMPW ( HDUMPW ), + .VDUMPW ( VDUMPW ), + .FLIP_HDUMP ( 0 ), // hdump is already flipped, don't flip it again + .FLIP_VDUMP ( 0 ), // same for vdump + .FLIP_MSB ( 0 ), + .ROM_HFLIP ( ROM_HFLIP ), + .XOR_HFLIP ( XOR_HFLIP ), + .XOR_VFLIP ( XOR_VFLIP ), + .VW ( VW ), + .HW ( HW ), + .VR ( VR ), + .HJUMP ( HJUMP ) +)u_tilemap( + .rst ( rst ), + .clk ( clk ), + .pxl_cen ( pxl_cen ), + + .vdump ( veff ), + .hdump ( heff ), + .blankn ( blankn ), + .flip ( flip ), + + .vram_addr ( vram_addr ), + + .code ( code ), + .pal ( pal ), + .hflip ( hflip ), + .vflip ( vflip ), + + .rom_addr ( rom_addr ), + .rom_data ( rom_data ), + .rom_cs ( rom_cs ), + .rom_ok ( rom_ok ), + + .pxl ( pxl ) +); + +endmodule \ No newline at end of file diff --git a/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/video/tilemap/jtframe_scroll_offset.v b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/video/tilemap/jtframe_scroll_offset.v new file mode 100644 index 0000000000000000000000000000000000000000..1180fe896f81305fba180f3c2c7a21fc95d908a8 --- /dev/null +++ b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/video/tilemap/jtframe_scroll_offset.v @@ -0,0 +1,80 @@ +/* This file is part of JTFRAME. + JTFRAME program is free software: you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation, either version 3 of the License, or + (at your option) any later version. + + JTFRAME program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with JTFRAME. If not, see . + + Author: Jose Tejada Gomez. Twitter: @topapate + Version: 1.0 + Date: 7-2-2025 */ + +module jtframe_scroll_offset #(parameter + MAP_HW = 9, + MAP_VW = 9, + VDUMPW = 9, + HDUMPW = 9, + HLOOP = 0, // when !=0, it is the value of hdump at which + // hdump[8:7] are set to 1, and hdf uses &hdump[8:7] for MSBs + // this is useful to have heff correctly operate at the + // trasition from blanking to active + COL_SCROLL = 0 // set to 1 to enable 8-pixel column scroll +)( + input clk, + flip, hs, + input [8:0] hdump, vdump, + input [MAP_HW-1:0] scrx, + input [MAP_VW-1:0] scry, + + output reg [VDUMPW-1:0] veff, + output reg [HDUMPW-1:0] heff +); + +localparam VDW=9, HDW=10, + HEW = HDUMPW>HDW ? HDUMPW : HDW, + VEW = VDUMPW>VDW ? VDUMPW : VDW; + +reg [VDW-1:0] vdf; +reg [HDW-1:0] hdf; +reg [HEW-1:0] hfull; +reg [VEW-1:0] vfull; +wire h8,blank; +reg hsl, h8_l, + line_changed, tile_changed, update_veff; +wire [8:0] hdfix = HLOOP==0 ? hdump : + hdump>HLOOP ? {2'b11,hdump[6:0]} : hdump; + +assign h8 = heff[3]; +assign blank = HLOOP==0 ? hdump[8] : &hdfix[8:7]; + +always @* begin + // hdf should make a perfect subtraction during blanking + // HLOOP can be used to help achieve that + hdf = {blank,hdfix} ^ { 2'b0, {8{flip}} }; + hfull = hdf + {{HDW-MAP_HW{1'b0}},scrx}; + heff = hfull[HDUMPW-1:0]; + + vdf = vdump ^ { 1'b0, {8{flip}} }; + vfull = vdf + scry; +end + +always @* begin + line_changed = ~hs & hsl; + tile_changed = h8 != h8_l; + update_veff = COL_SCROLL==1 ? tile_changed : line_changed; +end + +always @(posedge clk) begin + hsl <= hs; + h8_l <= h8; + if( update_veff ) veff <= vfull[VDUMPW-1:0]; +end + +endmodule \ No newline at end of file diff --git a/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/video/tilemap/jtframe_tilebuf.v b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/video/tilemap/jtframe_tilebuf.v new file mode 100644 index 0000000000000000000000000000000000000000..6e3b241dc47aa22963ce6f93cd79c9dd9698f22e --- /dev/null +++ b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/video/tilemap/jtframe_tilebuf.v @@ -0,0 +1,90 @@ +/* This file is part of JTFRAME. + JTFRAME program is free software: you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation, either version 3 of the License, or + (at your option) any later version. + + JTFRAME program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with JTFRAME. If not, see . + + Author: Jose Tejada Gomez. Twitter: @topapate + Version: 1.0 + Date: 23-8-2020 */ + +module jtframe_tilebuf #( + parameter HW = 8, + VW = 8, + PALW = 4, + HOFFSET = 0, + PW = PALW+4, + parameter [HW-1:0] HOVER = {HW{1'd1}} // H count at which a new line starts +) ( + input rst, + input clk, + input pxl2_cen, + + // screen + input [HW-1:0] hdump, + input [VW-1:0] vdump, + + // to graphics block + output scan_cen, + output reg [HW-1:0] hscan, + output reg [VW-1:0] vscan, + input [PW-1:0] pxl_data, + input rom_ok, // SDRAM output + + output [PW-1:0] pxl_dump +); + +reg line, done; +wire [HW-1:0] hnext; +wire we; +wire [HW-1:0] hread = hdump + HOFFSET[HW-1:0]; + +assign hnext = hscan + 1'd1; +assign we = pxl2_cen & rom_ok & !done; +assign scan_cen = pxl2_cen & rom_ok; + +always @(posedge clk, posedge rst) begin + if( rst ) begin + hscan <= {HW{1'b0}}; + vscan <= {VW{1'b0}}; + line <= 0; + done <= 0; + end else begin + vscan <= vdump+1'd1; + + if( hdump==HOVER ) begin + if(done) line <= ~line; + hscan <= HOVER; + done <= 0; + end else + if( we ) begin + hscan <= hnext; + if( hnext == HOVER ) done <= 1; + end + end +end + +jtframe_dual_ram #(.AW(HW+1),.DW(PW)) u_line( + .clk0 ( clk ), + .clk1 ( clk ), + // Port 0 + .data0 ( pxl_data ), + .addr0 ( {line,hscan} ), + .we0 ( we ), + .q0 ( ), + // Port 1 + .data1 ( pxl_data ), + .addr1 ({~line,hread} ), + .we1 ( 1'b0 ), + .q1 ( pxl_dump ) +); + +endmodule diff --git a/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/video/tilemap/jtframe_tilemap.v b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/video/tilemap/jtframe_tilemap.v new file mode 100644 index 0000000000000000000000000000000000000000..7deeb8ba515ed3a742c87c3a58b2acf4a519996f --- /dev/null +++ b/snapshots/jotego_jtcores_pr1242/modules/jtframe/hdl/video/tilemap/jtframe_tilemap.v @@ -0,0 +1,171 @@ +/* This file is part of JTFRAME. + JTFRAME program is free software: you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation, either version 3 of the License, or + (at your option) any later version. + + JTFRAME program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with JTFRAME. If not, see . + + Author: Jose Tejada Gomez. Twitter: @topapate + Version: 1.0 + Date: 15-12-2022 */ + + +// Generic tile map generator with no scroll +// The ROM address must be in this format: {code, H parts, V part} +// pixel data has arbitrary bpp but it must arrive in groups of 8 pixels +// Each byte is for a plane + +module jtframe_tilemap #( parameter + SIZE = 8, // 8x8, 16x16 or 32x32 + VA = 10, // VRAM bit width + CW = 12, + PW = 8, // pixel width + BPP = 4, // bits per pixel. Palette width = PW-BPP + VR = SIZE==8 ? CW+3 : SIZE==16 ? CW+5 : CW+7, + MAP_HW = 8, // 2^MAP_HW = size of the map in pixels + MAP_VW = 8, + FLIP_MSB = 1, // set to 0 for scroll tile maps + FLIP_HDUMP = 1, + FLIP_VDUMP = 1, + ROM_HFLIP = 1, + XOR_HFLIP = 0, // set to 1 so hflip gets ^ with flip + XOR_VFLIP = 0, // set to 1 so vflip gets ^ with flip + HDUMP_OFFSET = 0, // adds an offset to hdump + HJUMP = 1, // see jtframe_scroll + // hdump/vdump dimensions can be larger than the screen for the scroll use case + // but the MSBs will be fixed + HDUMPW = 9, + VDUMPW = 9, + // override VH and HW only for non rectangular tiles + VW = SIZE==8 ? 3 : SIZE==16 ? 4:5, + HW = VW, + // localparam, do not modify + PALW = PW-BPP, + DW = 8*BPP +)( + input rst, + input clk, + input pxl_cen, + + input [VDUMPW-1:0] vdump, + input [HDUMPW-1:0] hdump, + input blankn, // if !blankn there are no ROM requests + input flip, // Screen flip + + output [VA-1:0] vram_addr, + + input [CW-1:0] code, + input [PALW-1:0] pal, + input hflip, + input vflip, + + output reg [VR-1:0]rom_addr, + input [DW-1:0]rom_data, // expects data packed as plane3,plane2,plane1,plane0, each of 8 bits + output reg rom_cs, + input rom_ok, // zeros used if rom_ok is not high in time + + output reg [PW-1:0]pxl +); + +reg [DW-1:0] pxl_data; +reg [PALW-1:0] cur_pal, nx_pal; +wire vflip_g, xhflip; +reg hflip_g, nx_hf; +reg [HDUMPW-1:0] heff, hoff; +wire [VDUMPW-1:0] veff; + +// not flipping the MSB is usually needed in scroll layers +assign veff = FLIP_VDUMP ? vdump ^ { FLIP_MSB[0]&flip, {VDUMPW-1{flip}}} : vdump; + +always @* begin + hoff = hdump - HDUMP_OFFSET[HDUMPW-1:0]; + heff = FLIP_HDUMP ? hoff ^ {HDUMPW{flip}} : hoff; +end + +initial begin + if( SIZE==32 ) begin + $display("WARNING %m: SIZE=32 has not been tested"); + end +end + +`ifdef SIMULATION +wire vram_len, vram_big; +assign vram_len = VA == (MAP_VW-VW + MAP_HW-HW); +assign vram_big = VA > (MAP_VW-VW + MAP_HW-HW); +initial begin + if( !vram_len ) begin + if( vram_big ) $display("WARNING %m: vram_addr has unassigned bits. Adjust parameters to avoid this"); + else $display("WARNING %m: vram_addr has bits assigned by two different sources. Adjust parameters to avoid this"); + $finish; + end +end +`endif + +assign xhflip = (flip & XOR_HFLIP[0])^hflip; +assign vflip_g = (flip & XOR_VFLIP[0])^vflip; + +// VRAM address width of H and V portions +localparam AHW=MAP_HW-HW, + AVW=MAP_VW-VW; + +assign vram_addr={ veff[MAP_VW-1:VW], heff[MAP_HW-1:HW] }; + +initial begin + if( AHW+AVW > VA ) begin + $display("vram address width is too narrow."); + $display("It should be at least %d",AHW+AVW); + $finish; + end +end + +integer i; +always @* begin + pxl[PW-1-:PALW] = cur_pal; + for(i=0;i>1) : (pxl_data<<1); + end + end +end + +endmodule \ No newline at end of file diff --git a/snapshots/muneeb-mbytes_pulpino__spi_master__subsystem_verification_pr28/.github/ISSUE_TEMPLATE/feature_request.md b/snapshots/muneeb-mbytes_pulpino__spi_master__subsystem_verification_pr28/.github/ISSUE_TEMPLATE/feature_request.md new file mode 100644 index 0000000000000000000000000000000000000000..c5e133dd1d1be776dc7dfaa41e651125574c9bb6 --- /dev/null +++ b/snapshots/muneeb-mbytes_pulpino__spi_master__subsystem_verification_pr28/.github/ISSUE_TEMPLATE/feature_request.md @@ -0,0 +1,29 @@ +--- +name: Feature request +about: Suggest an idea for this project +title: '' +labels: enhancement +assignees: '' + +--- + +**Is your feature request related to a problem? Please describe.** +A clear and concise description of what the problem is. Ex. I'm always frustrated when [...] + +**Describe the solution you'd like** +A clear and concise description of what you want to happen. + +**Describe alternatives you've considered** +A clear and concise description of any alternative solutions or features you've considered. + +**Additional context** +Add any other context or screenshots about the feature request here. + +**Additional lists of tasks to be accomplished** +- [ ] task 1 +- [ ] task 2 + +**Add the required following items to the issue** +1. Projects +2. Milestone +3. Assignee diff --git a/snapshots/muneeb-mbytes_pulpino__spi_master__subsystem_verification_pr28/.github/ISSUE_TEMPLATE/help_wanted_or_questions.md b/snapshots/muneeb-mbytes_pulpino__spi_master__subsystem_verification_pr28/.github/ISSUE_TEMPLATE/help_wanted_or_questions.md new file mode 100644 index 0000000000000000000000000000000000000000..06a160aa6116502cfeef5906a885d6ddcffbb874 --- /dev/null +++ b/snapshots/muneeb-mbytes_pulpino__spi_master__subsystem_verification_pr28/.github/ISSUE_TEMPLATE/help_wanted_or_questions.md @@ -0,0 +1,24 @@ +--- +name: 'Help wanted / Questions ' +about: 'Describe the assistance required ' +title: '' +labels: help wanted, question +assignees: muneebullashariff + +--- + +**Brief explanation of the question/help** +A clear and concise description of what the is required. + +**Describe the solution you'd like** +A clear and concise description of what you want to happen. + +**Describe alternatives you've considered** +A clear and concise description of any alternative solutions or features you've considered. + +**Additional context** +Add any other context or screenshots about the feature request here. + +**Add the required following items to the issue** +1. Projects +2. Milestone diff --git a/snapshots/muneeb-mbytes_pulpino__spi_master__subsystem_verification_pr28/.github/ISSUE_TEMPLATE/rtl_bug_report.md b/snapshots/muneeb-mbytes_pulpino__spi_master__subsystem_verification_pr28/.github/ISSUE_TEMPLATE/rtl_bug_report.md new file mode 100644 index 0000000000000000000000000000000000000000..e04c07450c5fa905ce387a119eee94b400b0f5ff --- /dev/null +++ b/snapshots/muneeb-mbytes_pulpino__spi_master__subsystem_verification_pr28/.github/ISSUE_TEMPLATE/rtl_bug_report.md @@ -0,0 +1,33 @@ +--- +name: RTL Bug Report +about: Create a report to help us improve +title: '' +labels: rtl bug +assignees: '' + +--- + +**Describe the bug** +A clear and concise description of what the bug is. + +**To Reproduce** +Steps to reproduce the behavior: +1. Go to '...' +2. Click on '....' +3. Branch name '...' +4. Scroll down to '....' +5. See error + +**Expected behavior** +A clear and concise description of what you expected to happen. + +**Screenshots** +If applicable, add screenshots to help explain your problem. + +**Additional context** +Add any other context about the problem here. + +**Add the required following items to the issue** +1. Projects +2. Milestone +3. Assignee diff --git a/snapshots/muneeb-mbytes_pulpino__spi_master__subsystem_verification_pr28/.github/ISSUE_TEMPLATE/verif_bug_report.md b/snapshots/muneeb-mbytes_pulpino__spi_master__subsystem_verification_pr28/.github/ISSUE_TEMPLATE/verif_bug_report.md new file mode 100644 index 0000000000000000000000000000000000000000..ee323e6024b72605471b6f2ef61aee8c339ee2db --- /dev/null +++ b/snapshots/muneeb-mbytes_pulpino__spi_master__subsystem_verification_pr28/.github/ISSUE_TEMPLATE/verif_bug_report.md @@ -0,0 +1,33 @@ +--- +name: Verif Bug Report +about: Create a report to help us improve +title: '' +labels: verif bug +assignees: '' + +--- + +**Describe the bug** +A clear and concise description of what the bug is. + +**To Reproduce** +Steps to reproduce the behavior: +1. Go to '...' +2. Click on '....' +3. Branch name '...' +4. Scroll down to '....' +5. See error + +**Expected behavior** +A clear and concise description of what you expected to happen. + +**Screenshots** +If applicable, add screenshots to help explain your problem. + +**Additional context** +Add any other context about the problem here. + +**Add the required following items to the issue** +1. Projects +2. Milestone +3. Assignee diff --git a/snapshots/muneeb-mbytes_pulpino__spi_master__subsystem_verification_pr28/.github/PULL_REQUEST_TEMPLATE/fix_request.md b/snapshots/muneeb-mbytes_pulpino__spi_master__subsystem_verification_pr28/.github/PULL_REQUEST_TEMPLATE/fix_request.md new file mode 100644 index 0000000000000000000000000000000000000000..468f460dcfcfca9161228dca9b67a7e5c1db1b6c --- /dev/null +++ b/snapshots/muneeb-mbytes_pulpino__spi_master__subsystem_verification_pr28/.github/PULL_REQUEST_TEMPLATE/fix_request.md @@ -0,0 +1,12 @@ +**Fixes #issue_number** (mention the issue using the pound symbol followed by the issue number) + + +**Changes proposed in this pull request** +- .... +- .... +- .... + +**Make sure you do the following:** +- [ ] Create the pull request to branch development_branch_v1 +- [ ] Use @mention to assign this pull request +- [ ] Select Reviewer diff --git a/snapshots/muneeb-mbytes_pulpino__spi_master__subsystem_verification_pr28/doc/Tb_architecture.md b/snapshots/muneeb-mbytes_pulpino__spi_master__subsystem_verification_pr28/doc/Tb_architecture.md new file mode 100644 index 0000000000000000000000000000000000000000..1cabbc50d7b77566d6502d6992301d7e350bd153 --- /dev/null +++ b/snapshots/muneeb-mbytes_pulpino__spi_master__subsystem_verification_pr28/doc/Tb_architecture.md @@ -0,0 +1 @@ +[Tb_architecture](https://drive.google.com/file/d/1EKrIioTSYH7G6aQRnAGOzXsLPKQrJoib/view?usp=sharing) diff --git a/snapshots/muneeb-mbytes_pulpino__spi_master__subsystem_verification_pr28/doc/coverage_plan.md b/snapshots/muneeb-mbytes_pulpino__spi_master__subsystem_verification_pr28/doc/coverage_plan.md new file mode 100644 index 0000000000000000000000000000000000000000..d578a58dd1cceff4f283a67629767b09319ef77f --- /dev/null +++ b/snapshots/muneeb-mbytes_pulpino__spi_master__subsystem_verification_pr28/doc/coverage_plan.md @@ -0,0 +1 @@ +[Coverage plan](https://docs.google.com/spreadsheets/d/1GucKY2iaH3BvcSWt0PU8ua03_pcyn5zPFGCS7HOfRQ8/edit#gid=0) diff --git a/snapshots/muneeb-mbytes_pulpino__spi_master__subsystem_verification_pr28/doc/pulpino_spi_master_assertion_plan.md b/snapshots/muneeb-mbytes_pulpino__spi_master__subsystem_verification_pr28/doc/pulpino_spi_master_assertion_plan.md new file mode 100644 index 0000000000000000000000000000000000000000..8b6b90cae88d562274cbc96c5e4517d02f9dc660 --- /dev/null +++ b/snapshots/muneeb-mbytes_pulpino__spi_master__subsystem_verification_pr28/doc/pulpino_spi_master_assertion_plan.md @@ -0,0 +1 @@ +[pulpino_spi_master_assertion_plan](https://docs.google.com/spreadsheets/d/e/2PACX-1vT7c946xAFlPVdf8Dsg3ompcWrFOtqFxcSzRtMQBYYU6qQh7JbYUeHgEh2cQ-_JhgVVLT8n7z4B6IrU/pubhtml) diff --git a/snapshots/muneeb-mbytes_pulpino__spi_master__subsystem_verification_pr28/doc/verification_plan.md b/snapshots/muneeb-mbytes_pulpino__spi_master__subsystem_verification_pr28/doc/verification_plan.md new file mode 100644 index 0000000000000000000000000000000000000000..f03ee633e84b9da8616ed4ca3fa8dde538b3fbb3 --- /dev/null +++ b/snapshots/muneeb-mbytes_pulpino__spi_master__subsystem_verification_pr28/doc/verification_plan.md @@ -0,0 +1 @@ +[verification_plan](https://docs.google.com/spreadsheets/d/e/2PACX-1vRKVBYfrdNXE6oRxeHd0wteiez_OUk924Q1kWwRIrV9504Eo09ba4qxGp6uUE_XwdVax8fwEk2QveiX/pubhtml) diff --git a/snapshots/muneeb-mbytes_pulpino__spi_master__subsystem_verification_pr28/sim/.git_ignore b/snapshots/muneeb-mbytes_pulpino__spi_master__subsystem_verification_pr28/sim/.git_ignore new file mode 100644 index 0000000000000000000000000000000000000000..91bca286b57d1f8481b92a1758b694d30aea9eef --- /dev/null +++ b/snapshots/muneeb-mbytes_pulpino__spi_master__subsystem_verification_pr28/sim/.git_ignore @@ -0,0 +1,11 @@ +*_test* +*.log* +*.do* +*work* +*cov* +*vish* +*vsim* +*transcript* +*.simvision/* +*INCA_libs/* +*.shm* diff --git a/snapshots/muneeb-mbytes_pulpino__spi_master__subsystem_verification_pr28/sim/questa_sim/basic_write_read_reg_test/basic_write_read_reg_test.log b/snapshots/muneeb-mbytes_pulpino__spi_master__subsystem_verification_pr28/sim/questa_sim/basic_write_read_reg_test/basic_write_read_reg_test.log new file mode 100644 index 0000000000000000000000000000000000000000..27b5948218f67dd9e682bf8fae7ffc9c89464946 --- /dev/null +++ b/snapshots/muneeb-mbytes_pulpino__spi_master__subsystem_verification_pr28/sim/questa_sim/basic_write_read_reg_test/basic_write_read_reg_test.log @@ -0,0 +1,4019 @@ +# vsim -vopt work.hvl_top work.hdl_top -voptargs="+acc=npr" -assertdebug "+UVM_TESTNAME=basic_write_read_reg_test" "+UVM_VERBOSITY=UVM_HIGH" "+define+pulpino_spi_master_subsystem_verification_base_test" -l basic_write_read_reg_test/basic_write_read_reg_test.log -sva -coverage -c -do "log -r /*; add wave -r /*; coverage save -onexit -assert -directive -cvg -codeAll basic_write_read_reg_test/basic_write_read_reg_test_coverage.ucdb; run -all; exit" -wlf basic_write_read_reg_test/waveform.wlf +# Start time: 12:57:39 on Mar 11,2022 +# ** Note: (vsim-3812) Design is being optimized... +# ** Note: (vopt-143) Recognized 1 FSM in module "spi_master_controller(fast)". +# ** Note: (vopt-143) Recognized 1 FSM in module "axi2apb32(fast)". +# ** Note: (vopt-143) Recognized 2 FSMs in module "apb_spi_master(fast)". +# ** Note: (vopt-143) Recognized 1 FSM in module "generic_fifo(fast)". +# ** Note: (vopt-143) Recognized 1 FSM in module "generic_fifo(fast__1)". +# ** Note: (vopt-143) Recognized 1 FSM in module "generic_fifo(fast__2)". +# ** Note: (vopt-143) Recognized 1 FSM in module "generic_fifo(fast__3)". +# ** Note: (vopt-143) Recognized 1 FSM in module "spi_master_rx(fast)". +# // Questa Sim +# // Version 10.6c linux Jul 25 2017 +# // +# // Copyright 1991-2017 Mentor Graphics Corporation +# // All Rights Reserved. +# // +# // QuestaSim and its associated documentation contain trade +# // secrets and commercial or financial information that are the property of +# // Mentor Graphics Corporation and are privileged, confidential, +# // and exempt from disclosure under the Freedom of Information Act, +# // 5 U.S.C. Section 552. Furthermore, this information +# // is prohibited from disclosure under the Trade Secrets Act, +# // 18 U.S.C. Section 1905. +# // +# Loading sv_std.std +# Loading mtiUvm.uvm_pkg +# Loading work.spi_master_uvm_pkg(fast) +# Loading work.spi_master_defines_pkg(fast) +# Loading work.axi4_master_driver_bfm(fast) +# Loading work.axi4_master_monitor_bfm(fast) +# Loading work.axi4_globals_pkg(fast) +# Loading work.axi4_master_pkg(fast) +# Loading work.spi_globals_pkg(fast) +# Loading work.axi4_reg_seq_pkg(fast) +# Loading work.spi_slave_driver_bfm(fast) +# Loading work.spi_slave_monitor_bfm(fast) +# Loading work.spi_slave_pkg(fast) +# Loading work.pulpino_spi_master_subsystem_global_pkg(fast) +# Loading work.pulpino_spi_master_subsystem_env_pkg(fast) +# Loading work.spi_slave_seq_pkg(fast) +# Loading work.axi4_master_seq_pkg(fast) +# Loading work.pulpino_spi_master_subsystem_virtual_seq_pkg(fast) +# Loading work.pulpino_spi_master_subsystem_test_pkg(fast) +# Loading work.hvl_top(fast) +# Loading work.hdl_top(fast) +# Loading work.axi4_if_sv_unit(fast) +# Loading work.axi4_if(fast) +# Loading work.axi4_master_agent_bfm(fast) +# Loading work.axi4_master_driver_bfm_sv_unit(fast) +# Loading work.axi4_master_driver_bfm(fast) +# Loading work.axi4_master_monitor_bfm_sv_unit(fast) +# Loading work.axi4_master_monitor_bfm(fast) +# Loading work.spi_if_sv_unit(fast) +# Loading work.spi_if(fast) +# Loading work.config_pkg(fast) +# Loading work.axi_bus_sv_unit(fast) +# Loading work.AXI_BUS(fast) +# Loading work.subsystem_top(fast) +# Loading work.apb_bus_sv_unit(fast) +# Loading work.APB_BUS(fast) +# Loading work.axi2apb_wrap(fast) +# Loading work.axi2apb32(fast) +# Loading work.axi_aw_buffer(fast) +# Loading work.generic_fifo(fast) +# Loading work.cluster_clock_gating(fast) +# Loading work.axi_ar_buffer(fast) +# Loading work.axi_w_buffer(fast) +# Loading work.generic_fifo(fast__1) +# Loading work.axi_r_buffer(fast) +# Loading work.generic_fifo(fast__2) +# Loading work.axi_b_buffer(fast) +# Loading work.generic_fifo(fast__3) +# Loading work.periph_bus_wrap(fast) +# Loading work.apb_node_wrap(fast) +# Loading work.apb_node(fast) +# Loading work.apb_spi_master(fast) +# Loading work.spi_master_apb_if(fast) +# Loading work.spi_master_fifo(fast) +# Loading work.spi_master_controller(fast) +# Loading work.spi_master_clkgen(fast) +# Loading work.spi_master_tx(fast) +# Loading work.spi_master_rx(fast) +# Loading work.spi_slave_agent_bfm(fast) +# Loading work.spi_slave_driver_bfm_sv_unit(fast) +# Loading work.spi_slave_driver_bfm(fast) +# Loading work.spi_slave_monitor_bfm_sv_unit(fast) +# Loading work.spi_slave_monitor_bfm(fast) +# Loading mtiUvm.questa_uvm_pkg(fast) +# Loading work.APB_BUS(fast__1) +# ** Warning: (vsim-3015) ../../src/dv/hdl_top/hdl_top.sv(152): [PCDPC] - Port size (2) does not match connection size (1) for port 'spi_master_csn0'. The port definition is at: ../../src/rtl/subsystem_top.sv(17). +# Time: 0 ns Iteration: 0 Instance: /hdl_top/DUT File: ../../src/rtl/subsystem_top.sv +# ** Warning: (vsim-3015) ../../src/rtl/axi2apb/axi2apb_wrap.sv(50): [PCDPC] - Port size (16) does not match connection size (4) for port 'AWID_i'. The port definition is at: ../../src/rtl/axi2apb/axi2apb32.sv(50). +# Time: 0 ns Iteration: 0 Instance: /hdl_top/DUT/AXI2APB_BRIDGE/genblk1/axi2apb_i File: ../../src/rtl/axi2apb/axi2apb32.sv +# ** Warning: (vsim-3015) ../../src/rtl/axi2apb/axi2apb_wrap.sv(50): [PCDPC] - Port size (1) does not match connection size (4) for port 'AWUSER_i'. The port definition is at: ../../src/rtl/axi2apb/axi2apb32.sv(59). +# Time: 0 ns Iteration: 0 Instance: /hdl_top/DUT/AXI2APB_BRIDGE/genblk1/axi2apb_i File: ../../src/rtl/axi2apb/axi2apb32.sv +# ** Warning: (vsim-3015) ../../src/rtl/axi2apb/axi2apb_wrap.sv(50): [PCDPC] - Port size (32) does not match connection size (64) for port 'WDATA_i'. The port definition is at: ../../src/rtl/axi2apb/axi2apb32.sv(66). +# Time: 0 ns Iteration: 0 Instance: /hdl_top/DUT/AXI2APB_BRIDGE/genblk1/axi2apb_i File: ../../src/rtl/axi2apb/axi2apb32.sv +# ** Warning: (vsim-3015) ../../src/rtl/axi2apb/axi2apb_wrap.sv(50): [PCDPC] - Port size (4) does not match connection size (8) for port 'WSTRB_i'. The port definition is at: ../../src/rtl/axi2apb/axi2apb32.sv(67). +# Time: 0 ns Iteration: 0 Instance: /hdl_top/DUT/AXI2APB_BRIDGE/genblk1/axi2apb_i File: ../../src/rtl/axi2apb/axi2apb32.sv +# ** Warning: (vsim-3015) ../../src/rtl/axi2apb/axi2apb_wrap.sv(50): [PCDPC] - Port size (1) does not match connection size (4) for port 'WUSER_i'. The port definition is at: ../../src/rtl/axi2apb/axi2apb32.sv(69). +# Time: 0 ns Iteration: 0 Instance: /hdl_top/DUT/AXI2APB_BRIDGE/genblk1/axi2apb_i File: ../../src/rtl/axi2apb/axi2apb32.sv +# ** Warning: (vsim-3015) ../../src/rtl/axi2apb/axi2apb_wrap.sv(50): [PCDPC] - Port size (16) does not match connection size (4) for port 'BID_o'. The port definition is at: ../../src/rtl/axi2apb/axi2apb32.sv(75). +# Time: 0 ns Iteration: 0 Instance: /hdl_top/DUT/AXI2APB_BRIDGE/genblk1/axi2apb_i File: ../../src/rtl/axi2apb/axi2apb32.sv +# ** Warning: (vsim-3015) ../../src/rtl/axi2apb/axi2apb_wrap.sv(50): [PCDPC] - Port size (1) does not match connection size (4) for port 'BUSER_o'. The port definition is at: ../../src/rtl/axi2apb/axi2apb32.sv(78). +# Time: 0 ns Iteration: 0 Instance: /hdl_top/DUT/AXI2APB_BRIDGE/genblk1/axi2apb_i File: ../../src/rtl/axi2apb/axi2apb32.sv +# ** Warning: (vsim-3015) ../../src/rtl/axi2apb/axi2apb_wrap.sv(50): [PCDPC] - Port size (16) does not match connection size (4) for port 'ARID_i'. The port definition is at: ../../src/rtl/axi2apb/axi2apb32.sv(83). +# Time: 0 ns Iteration: 0 Instance: /hdl_top/DUT/AXI2APB_BRIDGE/genblk1/axi2apb_i File: ../../src/rtl/axi2apb/axi2apb32.sv +# ** Warning: (vsim-3015) ../../src/rtl/axi2apb/axi2apb_wrap.sv(50): [PCDPC] - Port size (1) does not match connection size (4) for port 'ARUSER_i'. The port definition is at: ../../src/rtl/axi2apb/axi2apb32.sv(92). +# Time: 0 ns Iteration: 0 Instance: /hdl_top/DUT/AXI2APB_BRIDGE/genblk1/axi2apb_i File: ../../src/rtl/axi2apb/axi2apb32.sv +# ** Warning: (vsim-3015) ../../src/rtl/axi2apb/axi2apb_wrap.sv(50): [PCDPC] - Port size (16) does not match connection size (4) for port 'RID_o'. The port definition is at: ../../src/rtl/axi2apb/axi2apb32.sv(99). +# Time: 0 ns Iteration: 0 Instance: /hdl_top/DUT/AXI2APB_BRIDGE/genblk1/axi2apb_i File: ../../src/rtl/axi2apb/axi2apb32.sv +# ** Warning: (vsim-3015) ../../src/rtl/axi2apb/axi2apb_wrap.sv(50): [PCDPC] - Port size (32) does not match connection size (64) for port 'RDATA_o'. The port definition is at: ../../src/rtl/axi2apb/axi2apb32.sv(100). +# Time: 0 ns Iteration: 0 Instance: /hdl_top/DUT/AXI2APB_BRIDGE/genblk1/axi2apb_i File: ../../src/rtl/axi2apb/axi2apb32.sv +# ** Warning: (vsim-3015) ../../src/rtl/axi2apb/axi2apb_wrap.sv(50): [PCDPC] - Port size (1) does not match connection size (4) for port 'RUSER_o'. The port definition is at: ../../src/rtl/axi2apb/axi2apb32.sv(103). +# Time: 0 ns Iteration: 0 Instance: /hdl_top/DUT/AXI2APB_BRIDGE/genblk1/axi2apb_i File: ../../src/rtl/axi2apb/axi2apb32.sv +# ** Warning: (vsim-3015) ../../src/rtl/subsystem_top.sv(81): [PCDPC] - Port size (12) does not match connection size (32) for port 'PADDR'. The port definition is at: ../../src/rtl/peripherals/spi_master/apb_spi_master.sv(22). +# Time: 0 ns Iteration: 0 Instance: /hdl_top/DUT/DUT File: ../../src/rtl/peripherals/spi_master/apb_spi_master.sv +# ** Warning: (vsim-3015) ../../src/rtl/subsystem_top.sv(81): [PCDPC] - Port size (1) does not match connection size (2) for port 'spi_csn0'. The port definition is at: ../../src/rtl/peripherals/spi_master/apb_spi_master.sv(34). +# Time: 0 ns Iteration: 0 Instance: /hdl_top/DUT/DUT File: ../../src/rtl/peripherals/spi_master/apb_spi_master.sv +# Loading /tools/mentor/questasim_10.6c/questasim/uvm-1.1d/linux/uvm_dpi.so +# log -r /* +# add wave -r /* +# coverage save -onexit -assert -directive -cvg -codeAll basic_write_read_reg_test/basic_write_read_reg_test_coverage.ucdb +# run -all +# ---------------------------------------------------------------- +# UVM-1.1d +# (C) 2007-2013 Mentor Graphics Corporation +# (C) 2007-2013 Cadence Design Systems, Inc. +# (C) 2006-2013 Synopsys, Inc. +# (C) 2011-2013 Cypress Semiconductor Corp. +# ---------------------------------------------------------------- +# +# *********** IMPORTANT RELEASE NOTES ************ +# +# You are using a version of the UVM library that has been compiled +# with `UVM_NO_DEPRECATED undefined. +# See http://www.eda.org/svdb/view.php?id=3313 for more details. +# +# You are using a version of the UVM library that has been compiled +# with `UVM_OBJECT_MUST_HAVE_CONSTRUCTOR undefined. +# See http://www.eda.org/svdb/view.php?id=3770 for more details. +# +# (Specify +UVM_NO_RELNOTES to turn off this notice) +# +# UVM_INFO verilog_src/questa_uvm_pkg-1.2/src/questa_uvm_pkg.sv(215) @ 0: reporter [Questa UVM] QUESTA_UVM-1.2.3 +# UVM_INFO verilog_src/questa_uvm_pkg-1.2/src/questa_uvm_pkg.sv(217) @ 0: reporter [Questa UVM] questa_uvm::init(+struct) +# UVM_INFO @ 0: reporter [RNTST] Running test basic_write_read_reg_test... +# UVM_INFO ../../src/dv/hdl_top/hdl_top.sv(24) @ 0: reporter [UVM_INFO] hdl_top +# UVM_INFO ../../src/dv/hdl_top/axi4_master_agent_bfm/axi4_master_driver_bfm.sv(87) @ 0: reporter [AXI4_MASTER_DRIVER_BFM] AXI4_MASTER_DRIVER_BFM +# UVM_INFO ../../src/dv/hdl_top/axi4_master_agent_bfm/axi4_master_agent_bfm.sv(171) @ 0: reporter [axi4 master agent bfm] AXI4 MASTER AGENT BFM +# Slave Driver BFM +# Slave Monitor BFM +# spi_Slave Agent BFM +# UVM_INFO ../../src/dv/hvl_top/test//base_test.sv(71) @ 0: uvm_test_top [basic_write_read_reg_test] +# pulpino_spi_master_subsystem_ENV_CONFIG +# -------------------------------------------------------------------------------------------- +# Name Type Size Value +# -------------------------------------------------------------------------------------------- +# pulpino_spi_master_subsystem_env_cfg_h pulpino_spi_master_subsystem_env_config - @496 +# has_scoreboard integral 1 1 +# has_virtual_seqr integral 1 1 +# no_of_spi_slaves integral 32 'd1 +# -------------------------------------------------------------------------------------------- +# +# UVM_INFO ../../src/dv/hvl_top/test//base_test.sv(80) @ 0: uvm_test_top [basic_write_read_reg_test] +# axi4_master_agent_CONFIG +# ------------------------------------------------------------------------------ +# Name Type Size Value +# ------------------------------------------------------------------------------ +# axi4_master_agent_config axi4_master_agent_config - @497 +# is_active string 10 UVM_ACTIVE +# has_coverage integral 1 1 +# wait_count_write_address_channel integral 32 'd0 +# wait_count_write_data_channel integral 32 'd0 +# wait_count_read_address_channel integral 32 'd0 +# outstanding_write_tx integral 32 'd0 +# outstanding_read_tx integral 32 'd0 +# ------------------------------------------------------------------------------ +# +# UVM_INFO ../../src/dv/hvl_top/test//base_test.sv(145) @ 0: uvm_test_top [basic_write_read_reg_test] +# pulpino_spi_master_subsystem_SLAVE_CONFIG[0] +# ---------------------------------------------------------------- +# Name Type Size Value +# ---------------------------------------------------------------- +# slave_agent_config[0] spi_slave_agent_config - @502 +# is_active string 10 UVM_ACTIVE +# slave_id integral 2 'd0 +# spi_mode string 11 CPOL0_CPHA1 +# shift_dir string 9 MSB_FIRST +# has_coverage integral 1 1 +# spi_type string 10 SIMPLE_SPI +# ---------------------------------------------------------------- +# +# UVM_INFO @ 0: reporter [UVMTOP] UVM testbench topology: +# ------------------------------------------------------------------------------------------------------------- +# Name Type Size Value +# ------------------------------------------------------------------------------------------------------------- +# uvm_test_top basic_write_read_reg_test - @473 +# pulpino_spi_master_subsystem_env pulpino_spi_master_subsystem_env - @588 +# axi4_master_agent axi4_master_agent - @596 +# axi4_master_cov_h axi4_master_coverage - @1634 +# analysis_imp uvm_analysis_imp - @1641 +# axi4_master_drv_proxy_h axi4_master_driver_proxy - @1079 +# axi4_master_read_fifo_h uvm_tlm_analysis_fifo #(T) - @1181 +# analysis_export uvm_analysis_imp - @1220 +# get_ap uvm_analysis_port - @1212 +# get_peek_export uvm_get_peek_imp - @1196 +# put_ap uvm_analysis_port - @1204 +# put_export uvm_put_imp - @1188 +# axi4_master_write_fifo_h uvm_tlm_analysis_fifo #(T) - @1134 +# analysis_export uvm_analysis_imp - @1173 +# get_ap uvm_analysis_port - @1165 +# get_peek_export uvm_get_peek_imp - @1149 +# put_ap uvm_analysis_port - @1157 +# put_export uvm_put_imp - @1141 +# axi_read_rsp_port uvm_analysis_port - @1126 +# axi_read_seq_item_port uvm_seq_item_pull_port - @1110 +# axi_write_rsp_port uvm_analysis_port - @1118 +# axi_write_seq_item_port uvm_seq_item_pull_port - @1102 +# rsp_port uvm_analysis_port - @1094 +# seq_item_port uvm_seq_item_pull_port - @1086 +# axi4_master_mon_proxy_h axi4_master_monitor_proxy - @1446 +# axi4_master_read_address_analysis_port uvm_analysis_port - @1453 +# axi4_master_read_data_analysis_port uvm_analysis_port - @1461 +# axi4_master_read_fifo_h uvm_tlm_analysis_fifo #(T) - @1587 +# analysis_export uvm_analysis_imp - @1626 +# get_ap uvm_analysis_port - @1618 +# get_peek_export uvm_get_peek_imp - @1602 +# put_ap uvm_analysis_port - @1610 +# put_export uvm_put_imp - @1594 +# axi4_master_write_address_analysis_port uvm_analysis_port - @1469 +# axi4_master_write_address_fifo_h uvm_tlm_analysis_fifo #(T) - @1493 +# analysis_export uvm_analysis_imp - @1532 +# get_ap uvm_analysis_port - @1524 +# get_peek_export uvm_get_peek_imp - @1508 +# put_ap uvm_analysis_port - @1516 +# put_export uvm_put_imp - @1500 +# axi4_master_write_data_analysis_port uvm_analysis_port - @1477 +# axi4_master_write_data_fifo_h uvm_tlm_analysis_fifo #(T) - @1540 +# analysis_export uvm_analysis_imp - @1579 +# get_ap uvm_analysis_port - @1571 +# get_peek_export uvm_get_peek_imp - @1555 +# put_ap uvm_analysis_port - @1563 +# put_export uvm_put_imp - @1547 +# axi4_master_write_response_analysis_port uvm_analysis_port - @1485 +# axi4_master_read_seqr_h axi4_master_read_sequencer - @1337 +# rsp_export uvm_analysis_export - @1344 +# seq_item_export uvm_seq_item_pull_imp - @1438 +# arbitration_queue array 0 - +# lock_queue array 0 - +# num_last_reqs integral 32 'd1 +# num_last_rsps integral 32 'd1 +# axi4_master_write_seqr_h axi4_master_write_sequencer - @1228 +# rsp_export uvm_analysis_export - @1235 +# seq_item_export uvm_seq_item_pull_imp - @1329 +# arbitration_queue array 0 - +# lock_queue array 0 - +# num_last_reqs integral 32 'd1 +# num_last_rsps integral 32 'd1 +# axi4_master_coll_h axi4_master_collector - @1008 +# axi4_master_coll_analysis_port uvm_analysis_port - @1015 +# axi4_master_coll_imp_port uvm_analysis_imp - @1023 +# axi4_reg_predictor_h uvm_reg_predictor #(axi4_master_tx) - @1054 +# bus_in uvm_analysis_imp - @1061 +# reg_ap uvm_analysis_port - @1069 +# pulpino_spi_master_subsystem_scoreboard_h pulpino_spi_master_subsystem_scoreboard - @719 +# axi4_master_read_address_analysis_fifo uvm_tlm_analysis_fifo #(T) - @867 +# analysis_export uvm_analysis_imp - @906 +# get_ap uvm_analysis_port - @898 +# get_peek_export uvm_get_peek_imp - @882 +# put_ap uvm_analysis_port - @890 +# put_export uvm_put_imp - @874 +# axi4_master_read_data_analysis_fifo uvm_tlm_analysis_fifo #(T) - @914 +# analysis_export uvm_analysis_imp - @953 +# get_ap uvm_analysis_port - @945 +# get_peek_export uvm_get_peek_imp - @929 +# put_ap uvm_analysis_port - @937 +# put_export uvm_put_imp - @921 +# axi4_master_write_address_analysis_fifo uvm_tlm_analysis_fifo #(T) - @726 +# analysis_export uvm_analysis_imp - @765 +# get_ap uvm_analysis_port - @757 +# get_peek_export uvm_get_peek_imp - @741 +# put_ap uvm_analysis_port - @749 +# put_export uvm_put_imp - @733 +# axi4_master_write_data_analysis_fifo uvm_tlm_analysis_fifo #(T) - @773 +# analysis_export uvm_analysis_imp - @812 +# get_ap uvm_analysis_port - @804 +# get_peek_export uvm_get_peek_imp - @788 +# put_ap uvm_analysis_port - @796 +# put_export uvm_put_imp - @780 +# axi4_master_write_response_analysis_fifo uvm_tlm_analysis_fifo #(T) - @820 +# analysis_export uvm_analysis_imp - @859 +# get_ap uvm_analysis_port - @851 +# get_peek_export uvm_get_peek_imp - @835 +# put_ap uvm_analysis_port - @843 +# put_export uvm_put_imp - @827 +# spi_slave_analysis_fifo uvm_tlm_analysis_fifo #(T) - @961 +# analysis_export uvm_analysis_imp - @1000 +# get_ap uvm_analysis_port - @992 +# get_peek_export uvm_get_peek_imp - @976 +# put_ap uvm_analysis_port - @984 +# put_export uvm_put_imp - @968 +# pulpino_spi_master_subsystem_virtual_seqr_h pulpino_spi_master_subsystem_virtual_sequencer - @610 +# axi4_master_read_seqr_h axi4_master_read_sequencer - @1776 +# rsp_export uvm_analysis_export - @1783 +# seq_item_export uvm_seq_item_pull_imp - @1877 +# arbitration_queue array 0 - +# lock_queue array 0 - +# num_last_reqs integral 32 'd1 +# num_last_rsps integral 32 'd1 +# axi4_master_write_seqr_h axi4_master_write_sequencer - @1667 +# rsp_export uvm_analysis_export - @1674 +# seq_item_export uvm_seq_item_pull_imp - @1768 +# arbitration_queue array 0 - +# lock_queue array 0 - +# num_last_reqs integral 32 'd1 +# num_last_rsps integral 32 'd1 +# rsp_export uvm_analysis_export - @617 +# seq_item_export uvm_seq_item_pull_imp - @711 +# spi_slave_seqr_h spi_slave_sequencer - @1885 +# rsp_export uvm_analysis_export - @1892 +# seq_item_export uvm_seq_item_pull_imp - @1986 +# arbitration_queue array 0 - +# lock_queue array 0 - +# num_last_reqs integral 32 'd1 +# num_last_rsps integral 32 'd1 +# arbitration_queue array 0 - +# lock_queue array 0 - +# num_last_reqs integral 32 'd1 +# num_last_rsps integral 32 'd1 +# spi_slave_agent_h[0] spi_slave_agent - @603 +# spi_slave_cov_h spi_slave_coverage - @2158 +# analysis_imp uvm_analysis_imp - @2165 +# spi_slave_drv_proxy_h spi_slave_driver_proxy - @2011 +# rsp_port uvm_analysis_port - @2026 +# seq_item_port uvm_seq_item_pull_port - @2018 +# spi_slave_mon_proxy_h spi_slave_monitor_proxy - @2143 +# spi_slave_analysis_port uvm_analysis_port - @2150 +# spi_slave_seqr_h spi_slave_sequencer - @2034 +# rsp_export uvm_analysis_export - @2041 +# seq_item_export uvm_seq_item_pull_imp - @2135 +# arbitration_queue array 0 - +# lock_queue array 0 - +# num_last_reqs integral 32 'd1 +# num_last_rsps integral 32 'd1 +# spi_slave_coll_h spi_slave_collector - @1031 +# spi_slave_coll_analysis_port uvm_analysis_port - @1038 +# spi_slave_coll_imp_port uvm_analysis_imp - @1046 +# ------------------------------------------------------------------------------------------------------------- +# +# UVM_INFO verilog_src/questa_uvm_pkg-1.2/src/questa_uvm_pkg.sv(277) @ 0: reporter [Questa UVM] End Of Elaboration +# UVM_INFO ../../src/dv/hvl_top/test//basic_write_read_reg_test.sv(90) @ 0: uvm_test_top [basic_write_read_reg_test] basic_write_read_reg_test +# UVM_INFO ../../src/dv/hvl_top/spi_slave_agent//spi_slave_monitor_proxy.sv(222) @ 0: uvm_test_top.pulpino_spi_master_subsystem_env.spi_slave_agent_h[0].spi_slave_mon_proxy_h [spi_slave_monitor_proxy] Inside the spi_slave_monitor_proxy +# UVM_INFO ../../src/dv/hvl_top/test/virtual_sequences//virtual_basic_write_read_reg_seq.sv(57) @ 0: uvm_test_top.pulpino_spi_master_subsystem_env.pulpino_spi_master_subsystem_virtual_seqr_h@@virtual_basic_write_read_reg_seq_h [master_vseq] started master vseq +# UVM_INFO ../../src/dv/hvl_top/test/virtual_sequences//virtual_basic_write_read_reg_seq.sv(47) @ 0: uvm_test_top.pulpino_spi_master_subsystem_env.pulpino_spi_master_subsystem_virtual_seqr_h@@virtual_basic_write_read_reg_seq_h [slave_vseq] started slave vseq +# UVM_INFO ../../src/dv/hvl_top/test/sequences/master_sequences/reg_sequences//axi4_master_basic_write_read_reg_seq.sv(57) @ 0: uvm_test_top.pulpino_spi_master_subsystem_env.axi4_master_agent.axi4_master_write_seqr_h@@axi4_master_basic_write_read_reg_seq_h [CLOCK_DIV_REG_SEQ] WRITE:: REGISTER : spi_master_reg_block.CLKDIV, DATA = 32'h1 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_adapter.sv(53) @ 0: reporter [MSHA_DEBUG] +# rw.address = 1a102004 rw.data = 1 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_adapter.sv(73) @ 0: reporter [axi4_master_adapter] The converted reg2bus packet is ----------------------------------------------------------------------------------- +# Name Type Size Value +# ----------------------------------------------------------------------------------- +# axi4_master_tx axi4_master_tx - @2216 +# tx_type string 5 WRITE +# awid string 6 AWID_0 +# awaddr integral 32 'h1a102004 +# awlen integral 8 'd0 +# awsize string 13 WRITE_4_BYTES +# awburst string 10 WRITE_INCR +# awlock string 19 WRITE_NORMAL_ACCESS +# awcache string 16 WRITE_BUFFERABLE +# awprot string 24 WRITE_NORMAL_SECURE_DATA +# awqos integral 4 'h0 +# wait_count_write_address_channel integral 32 'h0 +# wdata[0] integral 64 'h1 +# wait_count_write_data_channel integral 32 'h0 +# bid string 5 BID_0 +# bresp string 10 WRITE_OKAY +# no_of_wait_states integral 32 'd0 +# wait_count_write_response_channel integral 32 'h0 +# transfer_type string 14 BLOCKING_WRITE +# ----------------------------------------------------------------------------------- +# +# +# UVM_INFO ../../src/dv/hdl_top/axi4_master_agent_bfm/axi4_master_driver_bfm.sv(96) @ 15: reporter [AXI4_MASTER_DRIVER_BFM] SYSTEM RESET DETECTED +# UVM_INFO ../../src/dv/hdl_top/axi4_master_agent_bfm/axi4_master_monitor_bfm.sv(87) @ 15: reporter [FROM MASTER MON BFM] SYSTEM RESET DETECTED +# UVM_INFO ../../src/dv/hdl_top/spi_slave_agent_bfm/spi_slave_driver_bfm.sv(48) @ 15: reporter [spi_slave_driver_bfm] System reset detected +# UVM_INFO ../../src/dv/hdl_top/spi_slave_agent_bfm/spi_slave_monitor_bfm.sv(44) @ 15: reporter [spi_slave_monitor_bfm] System reset detected +# UVM_INFO ../../src/dv/hdl_top/axi4_master_agent_bfm/axi4_master_driver_bfm.sv(103) @ 50: reporter [AXI4_MASTER_DRIVER_BFM] SYSTEM RESET DEACTIVATED +# UVM_INFO ../../src/dv/hdl_top/axi4_master_agent_bfm/axi4_master_monitor_bfm.sv(89) @ 50: reporter [FROM MASTER MON BFM] SYSTEM RESET DEACTIVATED +# UVM_INFO ../../src/dv/hdl_top/axi4_master_agent_bfm/axi4_master_monitor_bfm.sv(151) @ 50: reporter [FROM MASTER MON BFM] AFTER WHILE LOOP OF WRITE RESPONSE +# UVM_INFO ../../src/dv/hdl_top/spi_slave_agent_bfm/spi_slave_monitor_bfm.sv(46) @ 50: reporter [spi_slave_monitor_bfm] System reset deactivated +# UVM_INFO ../../src/dv/hdl_top/spi_slave_agent_bfm/spi_slave_driver_bfm.sv(50) @ 50: reporter [spi_slave_driver_bfm] System reset deactivated +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_driver_proxy.sv(167) @ 50: uvm_test_top.pulpino_spi_master_subsystem_env.axi4_master_agent.axi4_master_drv_proxy_h [axi4_master_driver_proxy] WRITE_TASK::Before Sending_req_write_packet = +# ----------------------------------------------------------------------------------- +# Name Type Size Value +# ----------------------------------------------------------------------------------- +# axi4_master_tx axi4_master_tx - @2216 +# tx_type string 5 WRITE +# awid string 6 AWID_0 +# awaddr integral 32 'h1a102004 +# awlen integral 8 'd0 +# awsize string 13 WRITE_4_BYTES +# awburst string 10 WRITE_INCR +# awlock string 19 WRITE_NORMAL_ACCESS +# awcache string 16 WRITE_BUFFERABLE +# awprot string 24 WRITE_NORMAL_SECURE_DATA +# awqos integral 4 'h0 +# wait_count_write_address_channel integral 32 'h0 +# wdata[0] integral 64 'h1 +# wait_count_write_data_channel integral 32 'h0 +# bid string 5 BID_0 +# bresp string 10 WRITE_OKAY +# no_of_wait_states integral 32 'd0 +# wait_count_write_response_channel integral 32 'h0 +# transfer_type string 14 BLOCKING_WRITE +# ----------------------------------------------------------------------------------- +# +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(47) @ 50: reporter [axi4_master_seq_item_conv_class] ---------------------------------------------------------------------- +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(49) @ 50: reporter [axi4_master_seq_item_conv_class] After converting awid = 0000 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(52) @ 50: reporter [axi4_master_seq_item_conv_class] After converting awlen = 00000000 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(55) @ 50: reporter [axi4_master_seq_item_conv_class] After randomizing awsize = 010 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(58) @ 50: reporter [axi4_master_seq_item_conv_class] After converting awburst = 01 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(61) @ 50: reporter [axi4_master_seq_item_conv_class] After converting awlock = 0 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(64) @ 50: reporter [axi4_master_seq_item_conv_class] After randomizing awcache = 0000 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(67) @ 50: reporter [axi4_master_seq_item_conv_class] After randomizing awprot = 000 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(70) @ 50: reporter [axi4_master_seq_item_conv_class] After converting bid = 0000 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(73) @ 50: reporter [axi4_master_seq_item_conv_class] After converting bresp = 00 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(76) @ 50: reporter [axi4_master_seq_item_conv_class] After converting buser = 0 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(81) @ 50: reporter [axi4_master_seq_item_conv_class] After converting awaddr = 1a102004 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(84) @ 50: reporter [axi4_master_seq_item_conv_class] After converting awqos = 0 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(89) @ 50: reporter [axi4_master_seq_item_conv_class] After converting wdata = 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(96) @ 50: reporter [axi4_master_seq_item_conv_class] After converting wstrb = 0 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(101) @ 50: reporter [axi4_master_seq_item_conv_class] After converting wlast = 0 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(104) @ 50: reporter [axi4_master_seq_item_conv_class] After converting wuser = 0 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(107) @ 50: reporter [axi4_master_seq_item_conv_class] After converting no_wait_states = 0 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_driver_proxy.sv(192) @ 50: uvm_test_top.pulpino_spi_master_subsystem_env.axi4_master_agent.axi4_master_drv_proxy_h [axi4_master_driver_proxy] WRITE_TASK::Checking transfer type = BLOCKING_WRITE +# UVM_INFO ../../src/dv/hdl_top/spi_slave_agent_bfm/spi_slave_driver_bfm.sv(64) @ 60: reporter [spi_slave_driver_bfm] IDLE condition has been detected +# UVM_INFO ../../src/dv/hdl_top/spi_slave_agent_bfm/spi_slave_monitor_bfm.sv(60) @ 60: reporter [spi_slave_monitor_bfm] IDLE condition has been detected +# UVM_INFO ../../src/dv/hdl_top/axi4_master_agent_bfm/axi4_master_driver_bfm.sv(117) @ 70: reporter [AXI4_MASTER_DRIVER_BFM] data_write_packet= +# '{awid:0, awaddr:437264388, awlen:0, awsize:2, awburst:1, awlock:0, awcache:0, awqos:0, awregion:0, awuser:0, awprot:0, awvalid:0, awready:0, wdata:'{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1}, wstrb:'{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, wuser:0, wlast:0, bid:0, bresp:0, buser:0, bvalid:0, tx_type:0, wait_count_write_address_channel:0, wait_count_write_data_channel:0, wait_count_write_response_channel:0, outstanding_write_tx:0, no_of_wait_states:0} +# UVM_INFO ../../src/dv/hdl_top/axi4_master_agent_bfm/axi4_master_driver_bfm.sv(118) @ 70: reporter [AXI4_MASTER_DRIVER_BFM] cfg_packet= +# '{min_address:0, max_address:0, wait_count_write_address_channel:0, wait_count_write_data_channel:0, wait_count_write_response_channel:0, wait_count_read_address_channel:0, wait_count_read_data_channel:0, outstanding_write_tx:0, outstanding_read_tx:0} +# UVM_INFO ../../src/dv/hdl_top/axi4_master_agent_bfm/axi4_master_driver_bfm.sv(119) @ 70: reporter [AXI4_MASTER_DRIVER_BFM] DRIVING_WRITE_ADDRESS_CHANNEL +# UVM_INFO ../../src/dv/hdl_top/axi4_master_agent_bfm/axi4_master_driver_bfm.sv(134) @ 70: reporter [AXI4_MASTER_DRIVER_BFM] detect_awready = 1 +# UVM_INFO ../../src/dv/hdl_top/axi4_master_agent_bfm/axi4_master_driver_bfm.sv(142) @ 90: reporter [AXI4_MASTER_DRIVER_BFM] After_loop_of_Detecting_awready = 1, awvalid = 1 +# UVM_INFO ../../src/dv/hdl_top/axi4_master_agent_bfm/axi4_master_driver_bfm.sv(153) @ 90: reporter [AXI4_MASTER_DRIVER_BFM] data_write_packet= +# '{awid:0, awaddr:437264388, awlen:0, awsize:2, awburst:1, awlock:0, awcache:0, awqos:0, awregion:0, awuser:0, awprot:0, awvalid:0, awready:0, wdata:'{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1}, wstrb:'{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, wuser:0, wlast:0, bid:0, bresp:0, buser:0, bvalid:0, tx_type:0, wait_count_write_address_channel:1, wait_count_write_data_channel:0, wait_count_write_response_channel:0, outstanding_write_tx:0, no_of_wait_states:0} +# UVM_INFO ../../src/dv/hdl_top/axi4_master_agent_bfm/axi4_master_driver_bfm.sv(154) @ 90: reporter [AXI4_MASTER_DRIVER_BFM] cfg_packet= +# '{min_address:0, max_address:0, wait_count_write_address_channel:0, wait_count_write_data_channel:0, wait_count_write_response_channel:0, wait_count_read_address_channel:0, wait_count_read_data_channel:0, outstanding_write_tx:0, outstanding_read_tx:0} +# UVM_INFO ../../src/dv/hdl_top/axi4_master_agent_bfm/axi4_master_driver_bfm.sv(155) @ 90: reporter [AXI4_MASTER_DRIVER_BFM] DRIVE TO WRITE DATA CHANNEL +# UVM_INFO ../../src/dv/hdl_top/axi4_master_agent_bfm/axi4_master_monitor_bfm.sv(102) @ 90: reporter [FROM MASTER MON BFM] after while loop ....... +# UVM_INFO ../../src/dv/hdl_top/axi4_master_agent_bfm/axi4_master_monitor_bfm.sv(112) @ 90: reporter [FROM MASTER MON BFM] datapacket ='{awid:0, awaddr:437264388, awlen:0, awsize:2, awburst:1, awlock:0, awcache:0, awqos:0, awregion:0, awuser:0, awprot:0, awvalid:0, awready:0, wdata:'{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, wstrb:'{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, wuser:0, wlast:0, bid:0, bresp:0, buser:0, bvalid:0, tx_type:0, wait_count_write_address_channel:0, wait_count_write_data_channel:0, wait_count_write_response_channel:0, outstanding_write_tx:0, no_of_wait_states:0} +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(198) @ 90: reporter [axi4_master_seq_item_conv_class] ---------------------------------------------------------------------- +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(204) @ 90: reporter [axi4_master_seq_item_conv_class] After converting awid = 0000000000000000 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(207) @ 90: reporter [axi4_master_seq_item_conv_class] After converting awlen = 00000000 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(210) @ 90: reporter [axi4_master_seq_item_conv_class] After randomizing awsize = 010 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(213) @ 90: reporter [axi4_master_seq_item_conv_class] After converting awburst = 01 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(216) @ 90: reporter [axi4_master_seq_item_conv_class] After converting awlock = 0 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(219) @ 90: reporter [axi4_master_seq_item_conv_class] After randomizing awcache = 0000 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(222) @ 90: reporter [axi4_master_seq_item_conv_class] After randomizing awprot = 000 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(225) @ 90: reporter [axi4_master_seq_item_conv_class] After converting awaddr = 1a102004 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(228) @ 90: reporter [axi4_master_seq_item_conv_class] After converting awqos = 0 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(231) @ 90: reporter [axi4_master_seq_item_conv_class] After converting wait_count_write_address_channel = 0 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(248) @ 90: reporter [axi4_master_seq_item_conv_class] After converting wlast = 0 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(251) @ 90: reporter [axi4_master_seq_item_conv_class] After converting wuser = 0 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(254) @ 90: reporter [axi4_master_seq_item_conv_class] After converting wait_count_write_data_channel = 0 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(257) @ 90: reporter [axi4_master_seq_item_conv_class] After converting bid = 0000000000000000 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(260) @ 90: reporter [axi4_master_seq_item_conv_class] After converting bresp = 00 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(263) @ 90: reporter [axi4_master_seq_item_conv_class] After converting wait_count_write_response_channel = 0 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_monitor_proxy.sv(159) @ 90: uvm_test_top.pulpino_spi_master_subsystem_env.axi4_master_agent.axi4_master_mon_proxy_h [axi4_master_monitor_proxy] Packet received from axi4_write_address clone packet is +# ----------------------------------------------------------------------------------- +# Name Type Size Value +# ----------------------------------------------------------------------------------- +# axi4_master_tx axi4_master_tx - @2392 +# tx_type string 5 WRITE +# awid string 6 AWID_0 +# awaddr integral 32 'h1a102004 +# awlen integral 8 'd0 +# awsize string 13 WRITE_4_BYTES +# awburst string 10 WRITE_INCR +# awlock string 19 WRITE_NORMAL_ACCESS +# awcache string 16 WRITE_BUFFERABLE +# awprot string 24 WRITE_NORMAL_SECURE_DATA +# awqos integral 4 'h0 +# wait_count_write_address_channel integral 32 'h0 +# wait_count_write_data_channel integral 32 'h0 +# bid string 5 BID_0 +# bresp string 10 WRITE_OKAY +# no_of_wait_states integral 32 'd0 +# wait_count_write_response_channel integral 32 'h0 +# transfer_type string 14 BLOCKING_WRITE +# ----------------------------------------------------------------------------------- +# +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_coverage.sv(223) @ 90: uvm_test_top.pulpino_spi_master_subsystem_env.axi4_master_agent.axi4_master_cov_h [axi4_master_coverage] Before calling SAMPLE METHOD +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_coverage.sv(227) @ 90: uvm_test_top.pulpino_spi_master_subsystem_env.axi4_master_agent.axi4_master_cov_h [axi4_master_coverage] After calling SAMPLE METHOD +# UVM_INFO ../../src/dv/hvl_top/env//axi4_master_collector.sv(60) @ 90: uvm_test_top.pulpino_spi_master_subsystem_env.axi4_master_coll_h [axi4_master_collector] Req print = ----------------------------------------------------------------------------------- +# Name Type Size Value +# ----------------------------------------------------------------------------------- +# axi4_master_tx axi4_master_tx - @2392 +# tx_type string 5 WRITE +# awid string 6 AWID_0 +# awaddr integral 32 'h1a102004 +# awlen integral 8 'd0 +# awsize string 13 WRITE_4_BYTES +# awburst string 10 WRITE_INCR +# awlock string 19 WRITE_NORMAL_ACCESS +# awcache string 16 WRITE_BUFFERABLE +# awprot string 24 WRITE_NORMAL_SECURE_DATA +# awqos integral 4 'h0 +# wait_count_write_address_channel integral 32 'h0 +# wait_count_write_data_channel integral 32 'h0 +# bid string 5 BID_0 +# bresp string 10 WRITE_OKAY +# no_of_wait_states integral 32 'd0 +# wait_count_write_response_channel integral 32 'h0 +# transfer_type string 14 BLOCKING_WRITE +# ----------------------------------------------------------------------------------- +# +# UVM_INFO ../../src/dv/hvl_top/env//axi4_master_collector.sv(64) @ 90: uvm_test_top.pulpino_spi_master_subsystem_env.axi4_master_coll_h [axi4_master_collector] rg_name = CLKDIV +# UVM_INFO ../../src/dv/hvl_top/env//axi4_master_collector.sv(65) @ 90: uvm_test_top.pulpino_spi_master_subsystem_env.axi4_master_coll_h [axi4_master_collector] rg_address = 1a102004 +# UVM_INFO ../../src/dv/hvl_top/env//axi4_master_collector.sv(66) @ 90: uvm_test_top.pulpino_spi_master_subsystem_env.axi4_master_coll_h [axi4_master_collector] rg_data = 1 +# UVM_INFO ../../src/dv/hvl_top/env//axi4_master_collector.sv(67) @ 90: uvm_test_top.pulpino_spi_master_subsystem_env.axi4_master_coll_h [axi4_master_collector] map_name = spi_master_reg_block.SPI_MASTER_MAP_ABP_IF +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_adapter.sv(118) @ 90: reporter [axi4_master_adapter] The converted bus2reg packet is ----------------------------------------------------------------------------------- +# Name Type Size Value +# ----------------------------------------------------------------------------------- +# axi4_master_tx axi4_master_tx - @2392 +# tx_type string 5 WRITE +# awid string 6 AWID_0 +# awaddr integral 32 'h1a102004 +# awlen integral 8 'd0 +# awsize string 13 WRITE_4_BYTES +# awburst string 10 WRITE_INCR +# awlock string 19 WRITE_NORMAL_ACCESS +# awcache string 16 WRITE_BUFFERABLE +# awprot string 24 WRITE_NORMAL_SECURE_DATA +# awqos integral 4 'h0 +# wait_count_write_address_channel integral 32 'h0 +# wait_count_write_data_channel integral 32 'h0 +# bid string 5 BID_0 +# bresp string 10 WRITE_OKAY +# no_of_wait_states integral 32 'd0 +# wait_count_write_response_channel integral 32 'h0 +# transfer_type string 14 BLOCKING_WRITE +# ----------------------------------------------------------------------------------- +# +# +# UVM_INFO verilog_src/uvm-1.1d/src/reg/uvm_reg_predictor.svh(221) @ 90: uvm_test_top.pulpino_spi_master_subsystem_env.axi4_reg_predictor_h [REG_PREDICT] Observed WRITE transaction to register spi_master_reg_block.CLKDIV: value='h0 : updated value = 'h0 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_adapter.sv(118) @ 90: reporter [axi4_master_adapter] The converted bus2reg packet is ----------------------------------------------------------------------------------- +# Name Type Size Value +# ----------------------------------------------------------------------------------- +# axi4_master_tx axi4_master_tx - @2392 +# tx_type string 5 WRITE +# awid string 6 AWID_0 +# awaddr integral 32 'h1a102004 +# awlen integral 8 'd0 +# awsize string 13 WRITE_4_BYTES +# awburst string 10 WRITE_INCR +# awlock string 19 WRITE_NORMAL_ACCESS +# awcache string 16 WRITE_BUFFERABLE +# awprot string 24 WRITE_NORMAL_SECURE_DATA +# awqos integral 4 'h0 +# wait_count_write_address_channel integral 32 'h0 +# wait_count_write_data_channel integral 32 'h0 +# bid string 5 BID_0 +# bresp string 10 WRITE_OKAY +# no_of_wait_states integral 32 'd0 +# wait_count_write_response_channel integral 32 'h0 +# transfer_type string 14 BLOCKING_WRITE +# ----------------------------------------------------------------------------------- +# +# +# UVM_INFO ../../src/dv/hvl_top/env//axi4_reg_predictor.sv(48) @ 90: uvm_test_top.pulpino_spi_master_subsystem_env.axi4_reg_predictor_h [axi4_reg_predictor] rg_data = {CLKDIV} 533 1 2400 @uvm_status_container@1 1 @spi_master_apb_if@1 null 32 8 { {@uvm_reg_map@1:1} } {@uvm_reg_field@10} 4 4 @semaphore@3 @18350080 {} 0 0 1 0 1 0 null @uvm_object_string_pool__3@2 32 1 @uvm_reg_field@9 @uvm_reg_field@10 {ref to covergroup #cg_vals#} {spi_master_apb_if__clkdiv} +# UVM_INFO ../../src/dv/hvl_top/env//axi4_reg_predictor.sv(49) @ 90: uvm_test_top.pulpino_spi_master_subsystem_env.axi4_reg_predictor_h [axi4_reg_predictor] rw_data = UVM_WRITE 437264388 0 0 0 UVM_IS_OK +# UVM_INFO ../../src/dv/hdl_top/axi4_master_agent_bfm/axi4_master_driver_bfm.sv(165) @ 110: reporter [AXI4_MASTER_DRIVER_BFM] DETECT_WRITE_DATA_WAIT_STATE +# UVM_INFO ../../src/dv/hdl_top/axi4_master_agent_bfm/axi4_master_driver_bfm.sv(176) @ 130: reporter [AXI4_MASTER_DRIVER_BFM] DEBUG_NA:WDATA[0]=1 +# UVM_INFO ../../src/dv/hdl_top/axi4_master_agent_bfm/axi4_master_driver_bfm.sv(181) @ 130: reporter [AXI4_MASTER_DRIVER_BFM] WRITE_DATA_COMP data_write_packet= +# '{awid:0, awaddr:437264388, awlen:0, awsize:2, awburst:1, awlock:0, awcache:0, awqos:0, awregion:0, awuser:0, awprot:0, awvalid:0, awready:0, wdata:'{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1}, wstrb:'{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, wuser:0, wlast:0, bid:0, bresp:0, buser:0, bvalid:0, tx_type:0, wait_count_write_address_channel:1, wait_count_write_data_channel:0, wait_count_write_response_channel:0, outstanding_write_tx:0, no_of_wait_states:0} +# UVM_INFO ../../src/dv/hdl_top/axi4_master_agent_bfm/axi4_master_driver_bfm.sv(190) @ 130: reporter [AXI4_MASTER_DRIVER_BFM] WRITE_RESP data_write_packet= +# '{awid:0, awaddr:437264388, awlen:0, awsize:2, awburst:1, awlock:0, awcache:0, awqos:0, awregion:0, awuser:0, awprot:0, awvalid:0, awready:0, wdata:'{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1}, wstrb:'{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, wuser:0, wlast:0, bid:0, bresp:0, buser:0, bvalid:0, tx_type:0, wait_count_write_address_channel:1, wait_count_write_data_channel:0, wait_count_write_response_channel:0, outstanding_write_tx:0, no_of_wait_states:0} +# UVM_INFO ../../src/dv/hdl_top/axi4_master_agent_bfm/axi4_master_driver_bfm.sv(191) @ 130: reporter [AXI4_MASTER_DRIVER_BFM] cfg_packet= +# '{min_address:0, max_address:0, wait_count_write_address_channel:0, wait_count_write_data_channel:0, wait_count_write_response_channel:0, wait_count_read_address_channel:0, wait_count_read_data_channel:0, outstanding_write_tx:0, outstanding_read_tx:0} +# UVM_INFO ../../src/dv/hdl_top/axi4_master_agent_bfm/axi4_master_driver_bfm.sv(192) @ 130: reporter [AXI4_MASTER_DRIVER_BFM] DRIVE TO WRITE RESPONSE CHANNEL +# UVM_INFO ../../src/dv/hdl_top/axi4_master_agent_bfm/axi4_master_monitor_bfm.sv(128) @ 130: reporter [FROM MASTER MON BFM] After while loop write data...... +# UVM_INFO ../../src/dv/hdl_top/axi4_master_agent_bfm/axi4_master_monitor_bfm.sv(135) @ 130: reporter [FROM MASTER MON BFM write data] write datapacket wdata[0] = 'h1 +# UVM_INFO ../../src/dv/hdl_top/axi4_master_agent_bfm/axi4_master_monitor_bfm.sv(136) @ 130: reporter [FROM MASTER MON BFM write data] write datapacket wstrb[0] = 'h0 +# UVM_INFO ../../src/dv/hdl_top/axi4_master_agent_bfm/axi4_master_monitor_bfm.sv(138) @ 130: reporter [FROM MASTER MON BFM write data] Inside wlast write datapacket ='{awid:0, awaddr:0, awlen:0, awsize:0, awburst:0, awlock:0, awcache:0, awqos:0, awregion:0, awuser:0, awprot:0, awvalid:0, awready:0, wdata:'{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1}, wstrb:'{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, wuser:0, wlast:1, bid:0, bresp:0, buser:0, bvalid:0, tx_type:0, wait_count_write_address_channel:0, wait_count_write_data_channel:0, wait_count_write_response_channel:0, outstanding_write_tx:0, no_of_wait_states:0} +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_monitor_proxy.sv(182) @ 130: uvm_test_top.pulpino_spi_master_subsystem_env.axi4_master_agent.axi4_master_mon_proxy_h [axi4_master_monitor_proxy] ADDR_Packet received from fifo is +# ----------------------------------------------------------------------------------- +# Name Type Size Value +# ----------------------------------------------------------------------------------- +# axi4_master_tx axi4_master_tx - @2388 +# tx_type string 5 WRITE +# awid string 6 AWID_0 +# awaddr integral 32 'h1a102004 +# awlen integral 8 'd0 +# awsize string 13 WRITE_4_BYTES +# awburst string 10 WRITE_INCR +# awlock string 19 WRITE_NORMAL_ACCESS +# awcache string 16 WRITE_BUFFERABLE +# awprot string 24 WRITE_NORMAL_SECURE_DATA +# awqos integral 4 'h0 +# wait_count_write_address_channel integral 32 'h0 +# wait_count_write_data_channel integral 32 'h0 +# bid string 5 BID_0 +# bresp string 10 WRITE_OKAY +# no_of_wait_states integral 32 'd0 +# wait_count_write_response_channel integral 32 'h0 +# transfer_type string 14 BLOCKING_WRITE +# ----------------------------------------------------------------------------------- +# +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(337) @ 130: reporter [axi4_master_seq_item_conv_class] ---------------------------------------------------------------------- +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(355) @ 130: reporter [axi4_master_seq_item_conv_class] After converting wdata[0] = 1 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(362) @ 130: reporter [axi4_master_seq_item_conv_class] After converting wstrb[0] = 0 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(370) @ 130: reporter [axi4_master_seq_item_conv_class] After converting = ----------------------------------------------------------------------------------- +# Name Type Size Value +# ----------------------------------------------------------------------------------- +# axi4_master_tx axi4_master_tx - @2400 +# tx_type string 5 WRITE +# awid string 6 AWID_0 +# awaddr integral 32 'h1a102004 +# awlen integral 8 'd0 +# awsize string 13 WRITE_4_BYTES +# awburst string 10 WRITE_INCR +# awlock string 19 WRITE_NORMAL_ACCESS +# awcache string 16 WRITE_BUFFERABLE +# awprot string 24 WRITE_NORMAL_SECURE_DATA +# awqos integral 4 'h0 +# wait_count_write_address_channel integral 32 'h0 +# wdata[0] integral 64 'h1 +# wstrb[0] integral 8 'h0 +# wait_count_write_data_channel integral 32 'h0 +# bid string 5 BID_0 +# bresp string 10 WRITE_OKAY +# no_of_wait_states integral 32 'd0 +# wait_count_write_response_channel integral 32 'h0 +# transfer_type string 14 BLOCKING_WRITE +# ----------------------------------------------------------------------------------- +# +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_monitor_proxy.sv(191) @ 130: uvm_test_top.pulpino_spi_master_subsystem_env.axi4_master_agent.axi4_master_mon_proxy_h [axi4_master_monitor_proxy] Packet received from axi4_write_data clone packet is +# ----------------------------------------------------------------------------------- +# Name Type Size Value +# ----------------------------------------------------------------------------------- +# axi4_master_tx axi4_master_tx - @2404 +# tx_type string 5 WRITE +# awid string 6 AWID_0 +# awaddr integral 32 'h1a102004 +# awlen integral 8 'd0 +# awsize string 13 WRITE_4_BYTES +# awburst string 10 WRITE_INCR +# awlock string 19 WRITE_NORMAL_ACCESS +# awcache string 16 WRITE_BUFFERABLE +# awprot string 24 WRITE_NORMAL_SECURE_DATA +# awqos integral 4 'h0 +# wait_count_write_address_channel integral 32 'h0 +# wdata[0] integral 64 'h1 +# wstrb[0] integral 8 'h0 +# wait_count_write_data_channel integral 32 'h0 +# bid string 5 BID_0 +# bresp string 10 WRITE_OKAY +# no_of_wait_states integral 32 'd0 +# wait_count_write_response_channel integral 32 'h0 +# transfer_type string 14 BLOCKING_WRITE +# ----------------------------------------------------------------------------------- +# +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_coverage.sv(223) @ 130: uvm_test_top.pulpino_spi_master_subsystem_env.axi4_master_agent.axi4_master_cov_h [axi4_master_coverage] Before calling SAMPLE METHOD +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_coverage.sv(227) @ 130: uvm_test_top.pulpino_spi_master_subsystem_env.axi4_master_agent.axi4_master_cov_h [axi4_master_coverage] After calling SAMPLE METHOD +# UVM_INFO ../../src/dv/hdl_top/axi4_master_agent_bfm/axi4_master_driver_bfm.sv(210) @ 190: reporter [AXI4_MASTER_DRIVER_BFM] CHECKING WRITE RESPONSE :: '{awid:0, awaddr:437264388, awlen:0, awsize:2, awburst:1, awlock:0, awcache:0, awqos:0, awregion:0, awuser:0, awprot:0, awvalid:0, awready:0, wdata:'{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1}, wstrb:'{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, wuser:0, wlast:0, bid:0, bresp:0, buser:0, bvalid:1, tx_type:0, wait_count_write_address_channel:1, wait_count_write_data_channel:0, wait_count_write_response_channel:0, outstanding_write_tx:0, no_of_wait_states:0} +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(198) @ 210: reporter [axi4_master_seq_item_conv_class] ---------------------------------------------------------------------- +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(204) @ 210: reporter [axi4_master_seq_item_conv_class] After converting awid = 0000000000000000 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(207) @ 210: reporter [axi4_master_seq_item_conv_class] After converting awlen = 00000000 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(210) @ 210: reporter [axi4_master_seq_item_conv_class] After randomizing awsize = 010 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(213) @ 210: reporter [axi4_master_seq_item_conv_class] After converting awburst = 01 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(216) @ 210: reporter [axi4_master_seq_item_conv_class] After converting awlock = 0 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(219) @ 210: reporter [axi4_master_seq_item_conv_class] After randomizing awcache = 0000 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(222) @ 210: reporter [axi4_master_seq_item_conv_class] After randomizing awprot = 000 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(225) @ 210: reporter [axi4_master_seq_item_conv_class] After converting awaddr = 1a102004 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(228) @ 210: reporter [axi4_master_seq_item_conv_class] After converting awqos = 0 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(231) @ 210: reporter [axi4_master_seq_item_conv_class] After converting wait_count_write_address_channel = 1 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(236) @ 210: reporter [axi4_master_seq_item_conv_class] After converting wdata[0] = 1 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(243) @ 210: reporter [axi4_master_seq_item_conv_class] After converting wstrb[0] = 0 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(248) @ 210: reporter [axi4_master_seq_item_conv_class] After converting wlast = 0 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(251) @ 210: reporter [axi4_master_seq_item_conv_class] After converting wuser = 0 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(254) @ 210: reporter [axi4_master_seq_item_conv_class] After converting wait_count_write_data_channel = 0 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(257) @ 210: reporter [axi4_master_seq_item_conv_class] After converting bid = 0000000000000000 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(260) @ 210: reporter [axi4_master_seq_item_conv_class] After converting bresp = 00 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(263) @ 210: reporter [axi4_master_seq_item_conv_class] After converting wait_count_write_response_channel = 0 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_driver_proxy.sv(202) @ 210: uvm_test_top.pulpino_spi_master_subsystem_env.axi4_master_agent.axi4_master_drv_proxy_h [axi4_master_driver_proxy] WRITE_TASK::Response Received_req_write_packet = +# ----------------------------------------------------------------------------------- +# Name Type Size Value +# ----------------------------------------------------------------------------------- +# axi4_master_tx axi4_master_tx - @2408 +# tx_type string 5 WRITE +# awid string 6 AWID_0 +# awaddr integral 32 'h1a102004 +# awlen integral 8 'd0 +# awsize string 13 WRITE_4_BYTES +# awburst string 10 WRITE_INCR +# awlock string 19 WRITE_NORMAL_ACCESS +# awcache string 16 WRITE_BUFFERABLE +# awprot string 24 WRITE_NORMAL_SECURE_DATA +# awqos integral 4 'h0 +# wait_count_write_address_channel integral 32 'h1 +# wdata[0] integral 64 'h1 +# wstrb[0] integral 8 'h0 +# wait_count_write_data_channel integral 32 'h0 +# bid string 5 BID_0 +# bresp string 10 WRITE_OKAY +# no_of_wait_states integral 32 'd0 +# wait_count_write_response_channel integral 32 'h0 +# transfer_type string 14 BLOCKING_WRITE +# ----------------------------------------------------------------------------------- +# +# UVM_INFO ../../src/dv/hdl_top/axi4_master_agent_bfm/axi4_master_monitor_bfm.sv(158) @ 210: reporter [FROM MASTER MON BFM::WRITE RESPONSE] WRITE RESPONSE PACKET: +# '{awid:0, awaddr:0, awlen:0, awsize:0, awburst:0, awlock:0, awcache:0, awqos:0, awregion:0, awuser:0, awprot:0, awvalid:0, awready:0, wdata:'{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, wstrb:'{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, wuser:0, wlast:0, bid:0, bresp:0, buser:0, bvalid:0, tx_type:0, wait_count_write_address_channel:0, wait_count_write_data_channel:0, wait_count_write_response_channel:0, outstanding_write_tx:0, no_of_wait_states:0} +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(198) @ 210: reporter [axi4_master_seq_item_conv_class] ---------------------------------------------------------------------- +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(204) @ 210: reporter [axi4_master_seq_item_conv_class] After converting awid = 0000000000000000 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(207) @ 210: reporter [axi4_master_seq_item_conv_class] After converting awlen = 00000000 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(210) @ 210: reporter [axi4_master_seq_item_conv_class] After randomizing awsize = 000 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(213) @ 210: reporter [axi4_master_seq_item_conv_class] After converting awburst = 00 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(216) @ 210: reporter [axi4_master_seq_item_conv_class] After converting awlock = 0 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(219) @ 210: reporter [axi4_master_seq_item_conv_class] After randomizing awcache = 0000 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(222) @ 210: reporter [axi4_master_seq_item_conv_class] After randomizing awprot = 000 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(225) @ 210: reporter [axi4_master_seq_item_conv_class] After converting awaddr = 0 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(228) @ 210: reporter [axi4_master_seq_item_conv_class] After converting awqos = 0 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(231) @ 210: reporter [axi4_master_seq_item_conv_class] After converting wait_count_write_address_channel = 0 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(248) @ 210: reporter [axi4_master_seq_item_conv_class] After converting wlast = 0 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(251) @ 210: reporter [axi4_master_seq_item_conv_class] After converting wuser = 0 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(254) @ 210: reporter [axi4_master_seq_item_conv_class] After converting wait_count_write_data_channel = 0 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(257) @ 210: reporter [axi4_master_seq_item_conv_class] After converting bid = 0000000000000000 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(260) @ 210: reporter [axi4_master_seq_item_conv_class] After converting bresp = 00 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(263) @ 210: reporter [axi4_master_seq_item_conv_class] After converting wait_count_write_response_channel = 0 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(384) @ 210: reporter [axi4_master_seq_item_conv_class] ---------------------------------------------------------------------- +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(402) @ 210: reporter [axi4_master_seq_item_conv_class] After converting wdata[0] = 1 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(409) @ 210: reporter [axi4_master_seq_item_conv_class] After converting wstrb[0] = 0 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(417) @ 210: reporter [axi4_master_seq_item_conv_class] After converting = ----------------------------------------------------------------------------------- +# Name Type Size Value +# ----------------------------------------------------------------------------------- +# axi4_master_tx axi4_master_tx - @2416 +# tx_type string 5 WRITE +# awid string 6 AWID_0 +# awaddr integral 32 'h1a102004 +# awlen integral 8 'd0 +# awsize string 13 WRITE_4_BYTES +# awburst string 10 WRITE_INCR +# awlock string 19 WRITE_NORMAL_ACCESS +# awcache string 16 WRITE_BUFFERABLE +# awprot string 24 WRITE_NORMAL_SECURE_DATA +# awqos integral 4 'h0 +# wait_count_write_address_channel integral 32 'h0 +# wdata[0] integral 64 'h1 +# wstrb[0] integral 8 'h0 +# wait_count_write_data_channel integral 32 'h0 +# bid string 5 BID_0 +# bresp string 10 WRITE_OKAY +# no_of_wait_states integral 32 'd0 +# wait_count_write_response_channel integral 32 'h0 +# transfer_type string 14 BLOCKING_WRITE +# ----------------------------------------------------------------------------------- +# +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_monitor_proxy.sv(220) @ 210: uvm_test_top.pulpino_spi_master_subsystem_env.axi4_master_agent.axi4_master_mon_proxy_h [axi4_master_monitor_proxy] Packet received from axi4_write_response clone packet is +# ----------------------------------------------------------------------------------- +# Name Type Size Value +# ----------------------------------------------------------------------------------- +# axi4_master_tx axi4_master_tx - @2420 +# tx_type string 5 WRITE +# awid string 6 AWID_0 +# awaddr integral 32 'h1a102004 +# awlen integral 8 'd0 +# awsize string 13 WRITE_4_BYTES +# awburst string 10 WRITE_INCR +# awlock string 19 WRITE_NORMAL_ACCESS +# awcache string 16 WRITE_BUFFERABLE +# awprot string 24 WRITE_NORMAL_SECURE_DATA +# awqos integral 4 'h0 +# wait_count_write_address_channel integral 32 'h0 +# wdata[0] integral 64 'h1 +# wstrb[0] integral 8 'h0 +# wait_count_write_data_channel integral 32 'h0 +# bid string 5 BID_0 +# bresp string 10 WRITE_OKAY +# no_of_wait_states integral 32 'd0 +# wait_count_write_response_channel integral 32 'h0 +# transfer_type string 14 BLOCKING_WRITE +# ----------------------------------------------------------------------------------- +# +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_coverage.sv(223) @ 210: uvm_test_top.pulpino_spi_master_subsystem_env.axi4_master_agent.axi4_master_cov_h [axi4_master_coverage] Before calling SAMPLE METHOD +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_coverage.sv(227) @ 210: uvm_test_top.pulpino_spi_master_subsystem_env.axi4_master_agent.axi4_master_cov_h [axi4_master_coverage] After calling SAMPLE METHOD +# UVM_INFO ../../src/dv/hdl_top/axi4_master_agent_bfm/axi4_master_monitor_bfm.sv(151) @ 210: reporter [FROM MASTER MON BFM] AFTER WHILE LOOP OF WRITE RESPONSE +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_adapter.sv(118) @ 210: reporter [axi4_master_adapter] The converted bus2reg packet is ----------------------------------------------------------------------------------- +# Name Type Size Value +# ----------------------------------------------------------------------------------- +# axi4_master_tx axi4_master_tx - @2216 +# tx_type string 5 WRITE +# awid string 6 AWID_0 +# awaddr integral 32 'h1a102004 +# awlen integral 8 'd0 +# awsize string 13 WRITE_4_BYTES +# awburst string 10 WRITE_INCR +# awlock string 19 WRITE_NORMAL_ACCESS +# awcache string 16 WRITE_BUFFERABLE +# awprot string 24 WRITE_NORMAL_SECURE_DATA +# awqos integral 4 'h0 +# wait_count_write_address_channel integral 32 'h0 +# wdata[0] integral 64 'h1 +# wait_count_write_data_channel integral 32 'h0 +# bid string 5 BID_0 +# bresp string 10 WRITE_OKAY +# no_of_wait_states integral 32 'd0 +# wait_count_write_response_channel integral 32 'h0 +# transfer_type string 14 BLOCKING_WRITE +# ----------------------------------------------------------------------------------- +# +# +# UVM_INFO @ 210: reporter [RegModel] Wrote register via map spi_master_reg_block.SPI_MASTER_MAP_ABP_IF: spi_master_reg_block.CLKDIV=0x1 +# UVM_INFO ../../src/dv/hvl_top/test/sequences/master_sequences/reg_sequences//axi4_master_basic_write_read_reg_seq.sv(91) @ 210: uvm_test_top.pulpino_spi_master_subsystem_env.axi4_master_agent.axi4_master_write_seqr_h@@axi4_master_basic_write_read_reg_seq_h [SPI_CMD_REG_SEQ] WRITE:: REGISTER : spi_master_reg_block.SPICMD, DATA = 32'hffffffff +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_adapter.sv(53) @ 210: reporter [MSHA_DEBUG] +# rw.address = 1a102008 rw.data = ffffffff +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_adapter.sv(73) @ 210: reporter [axi4_master_adapter] The converted reg2bus packet is ----------------------------------------------------------------------------------- +# Name Type Size Value +# ----------------------------------------------------------------------------------- +# axi4_master_tx axi4_master_tx - @2429 +# tx_type string 5 WRITE +# awid string 6 AWID_0 +# awaddr integral 32 'h1a102008 +# awlen integral 8 'd0 +# awsize string 13 WRITE_4_BYTES +# awburst string 10 WRITE_INCR +# awlock string 19 WRITE_NORMAL_ACCESS +# awcache string 16 WRITE_BUFFERABLE +# awprot string 24 WRITE_NORMAL_SECURE_DATA +# awqos integral 4 'h0 +# wait_count_write_address_channel integral 32 'h0 +# wdata[0] integral 64 'hffffffff +# wait_count_write_data_channel integral 32 'h0 +# bid string 5 BID_0 +# bresp string 10 WRITE_OKAY +# no_of_wait_states integral 32 'd0 +# wait_count_write_response_channel integral 32 'h0 +# transfer_type string 14 BLOCKING_WRITE +# ----------------------------------------------------------------------------------- +# +# +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_driver_proxy.sv(167) @ 210: uvm_test_top.pulpino_spi_master_subsystem_env.axi4_master_agent.axi4_master_drv_proxy_h [axi4_master_driver_proxy] WRITE_TASK::Before Sending_req_write_packet = +# ----------------------------------------------------------------------------------- +# Name Type Size Value +# ----------------------------------------------------------------------------------- +# axi4_master_tx axi4_master_tx - @2429 +# tx_type string 5 WRITE +# awid string 6 AWID_0 +# awaddr integral 32 'h1a102008 +# awlen integral 8 'd0 +# awsize string 13 WRITE_4_BYTES +# awburst string 10 WRITE_INCR +# awlock string 19 WRITE_NORMAL_ACCESS +# awcache string 16 WRITE_BUFFERABLE +# awprot string 24 WRITE_NORMAL_SECURE_DATA +# awqos integral 4 'h0 +# wait_count_write_address_channel integral 32 'h0 +# wdata[0] integral 64 'hffffffff +# wait_count_write_data_channel integral 32 'h0 +# bid string 5 BID_0 +# bresp string 10 WRITE_OKAY +# no_of_wait_states integral 32 'd0 +# wait_count_write_response_channel integral 32 'h0 +# transfer_type string 14 BLOCKING_WRITE +# ----------------------------------------------------------------------------------- +# +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(47) @ 210: reporter [axi4_master_seq_item_conv_class] ---------------------------------------------------------------------- +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(49) @ 210: reporter [axi4_master_seq_item_conv_class] After converting awid = 0000 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(52) @ 210: reporter [axi4_master_seq_item_conv_class] After converting awlen = 00000000 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(55) @ 210: reporter [axi4_master_seq_item_conv_class] After randomizing awsize = 010 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(58) @ 210: reporter [axi4_master_seq_item_conv_class] After converting awburst = 01 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(61) @ 210: reporter [axi4_master_seq_item_conv_class] After converting awlock = 0 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(64) @ 210: reporter [axi4_master_seq_item_conv_class] After randomizing awcache = 0000 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(67) @ 210: reporter [axi4_master_seq_item_conv_class] After randomizing awprot = 000 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(70) @ 210: reporter [axi4_master_seq_item_conv_class] After converting bid = 0000 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(73) @ 210: reporter [axi4_master_seq_item_conv_class] After converting bresp = 00 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(76) @ 210: reporter [axi4_master_seq_item_conv_class] After converting buser = 0 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(81) @ 210: reporter [axi4_master_seq_item_conv_class] After converting awaddr = 1a102008 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(84) @ 210: reporter [axi4_master_seq_item_conv_class] After converting awqos = 0 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(89) @ 210: reporter [axi4_master_seq_item_conv_class] After converting wdata = 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 4294967295 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(96) @ 210: reporter [axi4_master_seq_item_conv_class] After converting wstrb = 0 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(101) @ 210: reporter [axi4_master_seq_item_conv_class] After converting wlast = 0 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(104) @ 210: reporter [axi4_master_seq_item_conv_class] After converting wuser = 0 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(107) @ 210: reporter [axi4_master_seq_item_conv_class] After converting no_wait_states = 0 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_driver_proxy.sv(192) @ 210: uvm_test_top.pulpino_spi_master_subsystem_env.axi4_master_agent.axi4_master_drv_proxy_h [axi4_master_driver_proxy] WRITE_TASK::Checking transfer type = BLOCKING_WRITE +# UVM_INFO ../../src/dv/hdl_top/axi4_master_agent_bfm/axi4_master_driver_bfm.sv(117) @ 230: reporter [AXI4_MASTER_DRIVER_BFM] data_write_packet= +# '{awid:0, awaddr:437264392, awlen:0, awsize:2, awburst:1, awlock:0, awcache:0, awqos:0, awregion:0, awuser:0, awprot:0, awvalid:0, awready:0, wdata:'{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 4294967295}, wstrb:'{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, wuser:0, wlast:0, bid:0, bresp:0, buser:0, bvalid:0, tx_type:0, wait_count_write_address_channel:0, wait_count_write_data_channel:0, wait_count_write_response_channel:0, outstanding_write_tx:0, no_of_wait_states:0} +# UVM_INFO ../../src/dv/hdl_top/axi4_master_agent_bfm/axi4_master_driver_bfm.sv(118) @ 230: reporter [AXI4_MASTER_DRIVER_BFM] cfg_packet= +# '{min_address:0, max_address:0, wait_count_write_address_channel:0, wait_count_write_data_channel:0, wait_count_write_response_channel:0, wait_count_read_address_channel:0, wait_count_read_data_channel:0, outstanding_write_tx:0, outstanding_read_tx:0} +# UVM_INFO ../../src/dv/hdl_top/axi4_master_agent_bfm/axi4_master_driver_bfm.sv(119) @ 230: reporter [AXI4_MASTER_DRIVER_BFM] DRIVING_WRITE_ADDRESS_CHANNEL +# UVM_INFO ../../src/dv/hdl_top/axi4_master_agent_bfm/axi4_master_driver_bfm.sv(134) @ 230: reporter [AXI4_MASTER_DRIVER_BFM] detect_awready = 1 +# UVM_INFO ../../src/dv/hdl_top/axi4_master_agent_bfm/axi4_master_driver_bfm.sv(142) @ 250: reporter [AXI4_MASTER_DRIVER_BFM] After_loop_of_Detecting_awready = 1, awvalid = 1 +# UVM_INFO ../../src/dv/hdl_top/axi4_master_agent_bfm/axi4_master_driver_bfm.sv(153) @ 250: reporter [AXI4_MASTER_DRIVER_BFM] data_write_packet= +# '{awid:0, awaddr:437264392, awlen:0, awsize:2, awburst:1, awlock:0, awcache:0, awqos:0, awregion:0, awuser:0, awprot:0, awvalid:0, awready:0, wdata:'{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 4294967295}, wstrb:'{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, wuser:0, wlast:0, bid:0, bresp:0, buser:0, bvalid:0, tx_type:0, wait_count_write_address_channel:1, wait_count_write_data_channel:0, wait_count_write_response_channel:0, outstanding_write_tx:0, no_of_wait_states:0} +# UVM_INFO ../../src/dv/hdl_top/axi4_master_agent_bfm/axi4_master_driver_bfm.sv(154) @ 250: reporter [AXI4_MASTER_DRIVER_BFM] cfg_packet= +# '{min_address:0, max_address:0, wait_count_write_address_channel:0, wait_count_write_data_channel:0, wait_count_write_response_channel:0, wait_count_read_address_channel:0, wait_count_read_data_channel:0, outstanding_write_tx:0, outstanding_read_tx:0} +# UVM_INFO ../../src/dv/hdl_top/axi4_master_agent_bfm/axi4_master_driver_bfm.sv(155) @ 250: reporter [AXI4_MASTER_DRIVER_BFM] DRIVE TO WRITE DATA CHANNEL +# UVM_INFO ../../src/dv/hdl_top/axi4_master_agent_bfm/axi4_master_monitor_bfm.sv(102) @ 250: reporter [FROM MASTER MON BFM] after while loop ....... +# UVM_INFO ../../src/dv/hdl_top/axi4_master_agent_bfm/axi4_master_monitor_bfm.sv(112) @ 250: reporter [FROM MASTER MON BFM] datapacket ='{awid:0, awaddr:437264392, awlen:0, awsize:2, awburst:1, awlock:0, awcache:0, awqos:0, awregion:0, awuser:0, awprot:0, awvalid:0, awready:0, wdata:'{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, wstrb:'{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, wuser:0, wlast:0, bid:0, bresp:0, buser:0, bvalid:0, tx_type:0, wait_count_write_address_channel:0, wait_count_write_data_channel:0, wait_count_write_response_channel:0, outstanding_write_tx:0, no_of_wait_states:0} +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(198) @ 250: reporter [axi4_master_seq_item_conv_class] ---------------------------------------------------------------------- +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(204) @ 250: reporter [axi4_master_seq_item_conv_class] After converting awid = 0000000000000000 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(207) @ 250: reporter [axi4_master_seq_item_conv_class] After converting awlen = 00000000 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(210) @ 250: reporter [axi4_master_seq_item_conv_class] After randomizing awsize = 010 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(213) @ 250: reporter [axi4_master_seq_item_conv_class] After converting awburst = 01 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(216) @ 250: reporter [axi4_master_seq_item_conv_class] After converting awlock = 0 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(219) @ 250: reporter [axi4_master_seq_item_conv_class] After randomizing awcache = 0000 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(222) @ 250: reporter [axi4_master_seq_item_conv_class] After randomizing awprot = 000 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(225) @ 250: reporter [axi4_master_seq_item_conv_class] After converting awaddr = 1a102008 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(228) @ 250: reporter [axi4_master_seq_item_conv_class] After converting awqos = 0 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(231) @ 250: reporter [axi4_master_seq_item_conv_class] After converting wait_count_write_address_channel = 0 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(248) @ 250: reporter [axi4_master_seq_item_conv_class] After converting wlast = 0 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(251) @ 250: reporter [axi4_master_seq_item_conv_class] After converting wuser = 0 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(254) @ 250: reporter [axi4_master_seq_item_conv_class] After converting wait_count_write_data_channel = 0 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(257) @ 250: reporter [axi4_master_seq_item_conv_class] After converting bid = 0000000000000000 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(260) @ 250: reporter [axi4_master_seq_item_conv_class] After converting bresp = 00 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(263) @ 250: reporter [axi4_master_seq_item_conv_class] After converting wait_count_write_response_channel = 0 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_monitor_proxy.sv(159) @ 250: uvm_test_top.pulpino_spi_master_subsystem_env.axi4_master_agent.axi4_master_mon_proxy_h [axi4_master_monitor_proxy] Packet received from axi4_write_address clone packet is +# ----------------------------------------------------------------------------------- +# Name Type Size Value +# ----------------------------------------------------------------------------------- +# axi4_master_tx axi4_master_tx - @2437 +# tx_type string 5 WRITE +# awid string 6 AWID_0 +# awaddr integral 32 'h1a102008 +# awlen integral 8 'd0 +# awsize string 13 WRITE_4_BYTES +# awburst string 10 WRITE_INCR +# awlock string 19 WRITE_NORMAL_ACCESS +# awcache string 16 WRITE_BUFFERABLE +# awprot string 24 WRITE_NORMAL_SECURE_DATA +# awqos integral 4 'h0 +# wait_count_write_address_channel integral 32 'h0 +# wait_count_write_data_channel integral 32 'h0 +# bid string 5 BID_0 +# bresp string 10 WRITE_OKAY +# no_of_wait_states integral 32 'd0 +# wait_count_write_response_channel integral 32 'h0 +# transfer_type string 14 BLOCKING_WRITE +# ----------------------------------------------------------------------------------- +# +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_coverage.sv(223) @ 250: uvm_test_top.pulpino_spi_master_subsystem_env.axi4_master_agent.axi4_master_cov_h [axi4_master_coverage] Before calling SAMPLE METHOD +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_coverage.sv(227) @ 250: uvm_test_top.pulpino_spi_master_subsystem_env.axi4_master_agent.axi4_master_cov_h [axi4_master_coverage] After calling SAMPLE METHOD +# UVM_INFO ../../src/dv/hvl_top/env//axi4_master_collector.sv(60) @ 250: uvm_test_top.pulpino_spi_master_subsystem_env.axi4_master_coll_h [axi4_master_collector] Req print = ----------------------------------------------------------------------------------- +# Name Type Size Value +# ----------------------------------------------------------------------------------- +# axi4_master_tx axi4_master_tx - @2437 +# tx_type string 5 WRITE +# awid string 6 AWID_0 +# awaddr integral 32 'h1a102008 +# awlen integral 8 'd0 +# awsize string 13 WRITE_4_BYTES +# awburst string 10 WRITE_INCR +# awlock string 19 WRITE_NORMAL_ACCESS +# awcache string 16 WRITE_BUFFERABLE +# awprot string 24 WRITE_NORMAL_SECURE_DATA +# awqos integral 4 'h0 +# wait_count_write_address_channel integral 32 'h0 +# wait_count_write_data_channel integral 32 'h0 +# bid string 5 BID_0 +# bresp string 10 WRITE_OKAY +# no_of_wait_states integral 32 'd0 +# wait_count_write_response_channel integral 32 'h0 +# transfer_type string 14 BLOCKING_WRITE +# ----------------------------------------------------------------------------------- +# +# UVM_INFO ../../src/dv/hvl_top/env//axi4_master_collector.sv(64) @ 250: uvm_test_top.pulpino_spi_master_subsystem_env.axi4_master_coll_h [axi4_master_collector] rg_name = SPICMD +# UVM_INFO ../../src/dv/hvl_top/env//axi4_master_collector.sv(65) @ 250: uvm_test_top.pulpino_spi_master_subsystem_env.axi4_master_coll_h [axi4_master_collector] rg_address = 1a102008 +# UVM_INFO ../../src/dv/hvl_top/env//axi4_master_collector.sv(66) @ 250: uvm_test_top.pulpino_spi_master_subsystem_env.axi4_master_coll_h [axi4_master_collector] rg_data = ffffffff +# UVM_INFO ../../src/dv/hvl_top/env//axi4_master_collector.sv(67) @ 250: uvm_test_top.pulpino_spi_master_subsystem_env.axi4_master_coll_h [axi4_master_collector] map_name = spi_master_reg_block.SPI_MASTER_MAP_ABP_IF +# UVM_INFO ../../src/dv/hvl_top/env//axi4_master_collector.sv(82) @ 250: uvm_test_top.pulpino_spi_master_subsystem_env.axi4_master_coll_h [axi4_master_collector] cmd_local = ffffffff +# UVM_INFO ../../src/dv/hvl_top/env//axi4_master_collector.sv(83) @ 250: uvm_test_top.pulpino_spi_master_subsystem_env.axi4_master_coll_h [axi4_master_collector] spi_len[5:0] = 0 +# UVM_INFO ../../src/dv/hvl_top/env//axi4_master_collector.sv(95) @ 250: uvm_test_top.pulpino_spi_master_subsystem_env.axi4_master_coll_h [axi4_master_collector] Inside CMD-final_data=0 +# UVM_INFO ../../src/dv/hvl_top/env//axi4_master_collector.sv(97) @ 250: uvm_test_top.pulpino_spi_master_subsystem_env.axi4_master_coll_h [axi4_master_collector] cmd_data = 0 +# UVM_INFO ../../src/dv/hvl_top/env//axi4_master_collector.sv(98) @ 250: uvm_test_top.pulpino_spi_master_subsystem_env.axi4_master_coll_h [axi4_master_collector] Inside TX_FIFO -flag=1 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_adapter.sv(118) @ 250: reporter [axi4_master_adapter] The converted bus2reg packet is ----------------------------------------------------------------------------------- +# Name Type Size Value +# ----------------------------------------------------------------------------------- +# axi4_master_tx axi4_master_tx - @2437 +# tx_type string 5 WRITE +# awid string 6 AWID_0 +# awaddr integral 32 'h1a102008 +# awlen integral 8 'd0 +# awsize string 13 WRITE_4_BYTES +# awburst string 10 WRITE_INCR +# awlock string 19 WRITE_NORMAL_ACCESS +# awcache string 16 WRITE_BUFFERABLE +# awprot string 24 WRITE_NORMAL_SECURE_DATA +# awqos integral 4 'h0 +# wait_count_write_address_channel integral 32 'h0 +# wait_count_write_data_channel integral 32 'h0 +# bid string 5 BID_0 +# bresp string 10 WRITE_OKAY +# no_of_wait_states integral 32 'd0 +# wait_count_write_response_channel integral 32 'h0 +# transfer_type string 14 BLOCKING_WRITE +# ----------------------------------------------------------------------------------- +# +# +# UVM_INFO verilog_src/uvm-1.1d/src/reg/uvm_reg_predictor.svh(221) @ 250: uvm_test_top.pulpino_spi_master_subsystem_env.axi4_reg_predictor_h [REG_PREDICT] Observed WRITE transaction to register spi_master_reg_block.SPICMD: value='h0 : updated value = 'h0 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_adapter.sv(118) @ 250: reporter [axi4_master_adapter] The converted bus2reg packet is ----------------------------------------------------------------------------------- +# Name Type Size Value +# ----------------------------------------------------------------------------------- +# axi4_master_tx axi4_master_tx - @2437 +# tx_type string 5 WRITE +# awid string 6 AWID_0 +# awaddr integral 32 'h1a102008 +# awlen integral 8 'd0 +# awsize string 13 WRITE_4_BYTES +# awburst string 10 WRITE_INCR +# awlock string 19 WRITE_NORMAL_ACCESS +# awcache string 16 WRITE_BUFFERABLE +# awprot string 24 WRITE_NORMAL_SECURE_DATA +# awqos integral 4 'h0 +# wait_count_write_address_channel integral 32 'h0 +# wait_count_write_data_channel integral 32 'h0 +# bid string 5 BID_0 +# bresp string 10 WRITE_OKAY +# no_of_wait_states integral 32 'd0 +# wait_count_write_response_channel integral 32 'h0 +# transfer_type string 14 BLOCKING_WRITE +# ----------------------------------------------------------------------------------- +# +# +# UVM_INFO ../../src/dv/hvl_top/env//axi4_reg_predictor.sv(48) @ 250: uvm_test_top.pulpino_spi_master_subsystem_env.axi4_reg_predictor_h [axi4_reg_predictor] rg_data = {SPICMD} 539 1 2445 @uvm_status_container@1 1 @spi_master_apb_if@1 null 32 32 { {@uvm_reg_map@1:1} } {@uvm_reg_field@11} 4 4 @semaphore@4 @18350080 {} 0 0 1 0 1 0 null @uvm_object_string_pool__3@3 32 1 @uvm_reg_field@11 {ref to covergroup #cg_vals#} {spi_master_apb_if__spicmd} +# UVM_INFO ../../src/dv/hvl_top/env//axi4_reg_predictor.sv(49) @ 250: uvm_test_top.pulpino_spi_master_subsystem_env.axi4_reg_predictor_h [axi4_reg_predictor] rw_data = UVM_WRITE 437264392 0 0 0 UVM_IS_OK +# UVM_INFO ../../src/dv/hdl_top/axi4_master_agent_bfm/axi4_master_driver_bfm.sv(165) @ 270: reporter [AXI4_MASTER_DRIVER_BFM] DETECT_WRITE_DATA_WAIT_STATE +# UVM_INFO ../../src/dv/hdl_top/axi4_master_agent_bfm/axi4_master_driver_bfm.sv(176) @ 290: reporter [AXI4_MASTER_DRIVER_BFM] DEBUG_NA:WDATA[0]=ffffffff +# UVM_INFO ../../src/dv/hdl_top/axi4_master_agent_bfm/axi4_master_driver_bfm.sv(181) @ 290: reporter [AXI4_MASTER_DRIVER_BFM] WRITE_DATA_COMP data_write_packet= +# '{awid:0, awaddr:437264392, awlen:0, awsize:2, awburst:1, awlock:0, awcache:0, awqos:0, awregion:0, awuser:0, awprot:0, awvalid:0, awready:0, wdata:'{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 4294967295}, wstrb:'{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, wuser:0, wlast:0, bid:0, bresp:0, buser:0, bvalid:0, tx_type:0, wait_count_write_address_channel:1, wait_count_write_data_channel:0, wait_count_write_response_channel:0, outstanding_write_tx:0, no_of_wait_states:0} +# UVM_INFO ../../src/dv/hdl_top/axi4_master_agent_bfm/axi4_master_driver_bfm.sv(190) @ 290: reporter [AXI4_MASTER_DRIVER_BFM] WRITE_RESP data_write_packet= +# '{awid:0, awaddr:437264392, awlen:0, awsize:2, awburst:1, awlock:0, awcache:0, awqos:0, awregion:0, awuser:0, awprot:0, awvalid:0, awready:0, wdata:'{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 4294967295}, wstrb:'{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, wuser:0, wlast:0, bid:0, bresp:0, buser:0, bvalid:0, tx_type:0, wait_count_write_address_channel:1, wait_count_write_data_channel:0, wait_count_write_response_channel:0, outstanding_write_tx:0, no_of_wait_states:0} +# UVM_INFO ../../src/dv/hdl_top/axi4_master_agent_bfm/axi4_master_driver_bfm.sv(191) @ 290: reporter [AXI4_MASTER_DRIVER_BFM] cfg_packet= +# '{min_address:0, max_address:0, wait_count_write_address_channel:0, wait_count_write_data_channel:0, wait_count_write_response_channel:0, wait_count_read_address_channel:0, wait_count_read_data_channel:0, outstanding_write_tx:0, outstanding_read_tx:0} +# UVM_INFO ../../src/dv/hdl_top/axi4_master_agent_bfm/axi4_master_driver_bfm.sv(192) @ 290: reporter [AXI4_MASTER_DRIVER_BFM] DRIVE TO WRITE RESPONSE CHANNEL +# UVM_INFO ../../src/dv/hdl_top/axi4_master_agent_bfm/axi4_master_monitor_bfm.sv(128) @ 290: reporter [FROM MASTER MON BFM] After while loop write data...... +# UVM_INFO ../../src/dv/hdl_top/axi4_master_agent_bfm/axi4_master_monitor_bfm.sv(135) @ 290: reporter [FROM MASTER MON BFM write data] write datapacket wdata[0] = 'hffffffff +# UVM_INFO ../../src/dv/hdl_top/axi4_master_agent_bfm/axi4_master_monitor_bfm.sv(136) @ 290: reporter [FROM MASTER MON BFM write data] write datapacket wstrb[0] = 'h0 +# UVM_INFO ../../src/dv/hdl_top/axi4_master_agent_bfm/axi4_master_monitor_bfm.sv(138) @ 290: reporter [FROM MASTER MON BFM write data] Inside wlast write datapacket ='{awid:0, awaddr:0, awlen:0, awsize:0, awburst:0, awlock:0, awcache:0, awqos:0, awregion:0, awuser:0, awprot:0, awvalid:0, awready:0, wdata:'{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 4294967295}, wstrb:'{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, wuser:0, wlast:1, bid:0, bresp:0, buser:0, bvalid:0, tx_type:0, wait_count_write_address_channel:0, wait_count_write_data_channel:0, wait_count_write_response_channel:0, outstanding_write_tx:0, no_of_wait_states:0} +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_monitor_proxy.sv(182) @ 290: uvm_test_top.pulpino_spi_master_subsystem_env.axi4_master_agent.axi4_master_mon_proxy_h [axi4_master_monitor_proxy] ADDR_Packet received from fifo is +# ----------------------------------------------------------------------------------- +# Name Type Size Value +# ----------------------------------------------------------------------------------- +# axi4_master_tx axi4_master_tx - @2433 +# tx_type string 5 WRITE +# awid string 6 AWID_0 +# awaddr integral 32 'h1a102008 +# awlen integral 8 'd0 +# awsize string 13 WRITE_4_BYTES +# awburst string 10 WRITE_INCR +# awlock string 19 WRITE_NORMAL_ACCESS +# awcache string 16 WRITE_BUFFERABLE +# awprot string 24 WRITE_NORMAL_SECURE_DATA +# awqos integral 4 'h0 +# wait_count_write_address_channel integral 32 'h0 +# wait_count_write_data_channel integral 32 'h0 +# bid string 5 BID_0 +# bresp string 10 WRITE_OKAY +# no_of_wait_states integral 32 'd0 +# wait_count_write_response_channel integral 32 'h0 +# transfer_type string 14 BLOCKING_WRITE +# ----------------------------------------------------------------------------------- +# +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(337) @ 290: reporter [axi4_master_seq_item_conv_class] ---------------------------------------------------------------------- +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(355) @ 290: reporter [axi4_master_seq_item_conv_class] After converting wdata[0] = ffffffff +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(362) @ 290: reporter [axi4_master_seq_item_conv_class] After converting wstrb[0] = 0 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(370) @ 290: reporter [axi4_master_seq_item_conv_class] After converting = ----------------------------------------------------------------------------------- +# Name Type Size Value +# ----------------------------------------------------------------------------------- +# axi4_master_tx axi4_master_tx - @2445 +# tx_type string 5 WRITE +# awid string 6 AWID_0 +# awaddr integral 32 'h1a102008 +# awlen integral 8 'd0 +# awsize string 13 WRITE_4_BYTES +# awburst string 10 WRITE_INCR +# awlock string 19 WRITE_NORMAL_ACCESS +# awcache string 16 WRITE_BUFFERABLE +# awprot string 24 WRITE_NORMAL_SECURE_DATA +# awqos integral 4 'h0 +# wait_count_write_address_channel integral 32 'h0 +# wdata[0] integral 64 'hffffffff +# wstrb[0] integral 8 'h0 +# wait_count_write_data_channel integral 32 'h0 +# bid string 5 BID_0 +# bresp string 10 WRITE_OKAY +# no_of_wait_states integral 32 'd0 +# wait_count_write_response_channel integral 32 'h0 +# transfer_type string 14 BLOCKING_WRITE +# ----------------------------------------------------------------------------------- +# +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_monitor_proxy.sv(191) @ 290: uvm_test_top.pulpino_spi_master_subsystem_env.axi4_master_agent.axi4_master_mon_proxy_h [axi4_master_monitor_proxy] Packet received from axi4_write_data clone packet is +# ----------------------------------------------------------------------------------- +# Name Type Size Value +# ----------------------------------------------------------------------------------- +# axi4_master_tx axi4_master_tx - @2449 +# tx_type string 5 WRITE +# awid string 6 AWID_0 +# awaddr integral 32 'h1a102008 +# awlen integral 8 'd0 +# awsize string 13 WRITE_4_BYTES +# awburst string 10 WRITE_INCR +# awlock string 19 WRITE_NORMAL_ACCESS +# awcache string 16 WRITE_BUFFERABLE +# awprot string 24 WRITE_NORMAL_SECURE_DATA +# awqos integral 4 'h0 +# wait_count_write_address_channel integral 32 'h0 +# wdata[0] integral 64 'hffffffff +# wstrb[0] integral 8 'h0 +# wait_count_write_data_channel integral 32 'h0 +# bid string 5 BID_0 +# bresp string 10 WRITE_OKAY +# no_of_wait_states integral 32 'd0 +# wait_count_write_response_channel integral 32 'h0 +# transfer_type string 14 BLOCKING_WRITE +# ----------------------------------------------------------------------------------- +# +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_coverage.sv(223) @ 290: uvm_test_top.pulpino_spi_master_subsystem_env.axi4_master_agent.axi4_master_cov_h [axi4_master_coverage] Before calling SAMPLE METHOD +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_coverage.sv(227) @ 290: uvm_test_top.pulpino_spi_master_subsystem_env.axi4_master_agent.axi4_master_cov_h [axi4_master_coverage] After calling SAMPLE METHOD +# UVM_INFO ../../src/dv/hdl_top/axi4_master_agent_bfm/axi4_master_driver_bfm.sv(210) @ 350: reporter [AXI4_MASTER_DRIVER_BFM] CHECKING WRITE RESPONSE :: '{awid:0, awaddr:437264392, awlen:0, awsize:2, awburst:1, awlock:0, awcache:0, awqos:0, awregion:0, awuser:0, awprot:0, awvalid:0, awready:0, wdata:'{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 4294967295}, wstrb:'{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, wuser:0, wlast:0, bid:0, bresp:0, buser:0, bvalid:1, tx_type:0, wait_count_write_address_channel:1, wait_count_write_data_channel:0, wait_count_write_response_channel:0, outstanding_write_tx:0, no_of_wait_states:0} +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(198) @ 370: reporter [axi4_master_seq_item_conv_class] ---------------------------------------------------------------------- +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(204) @ 370: reporter [axi4_master_seq_item_conv_class] After converting awid = 0000000000000000 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(207) @ 370: reporter [axi4_master_seq_item_conv_class] After converting awlen = 00000000 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(210) @ 370: reporter [axi4_master_seq_item_conv_class] After randomizing awsize = 010 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(213) @ 370: reporter [axi4_master_seq_item_conv_class] After converting awburst = 01 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(216) @ 370: reporter [axi4_master_seq_item_conv_class] After converting awlock = 0 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(219) @ 370: reporter [axi4_master_seq_item_conv_class] After randomizing awcache = 0000 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(222) @ 370: reporter [axi4_master_seq_item_conv_class] After randomizing awprot = 000 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(225) @ 370: reporter [axi4_master_seq_item_conv_class] After converting awaddr = 1a102008 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(228) @ 370: reporter [axi4_master_seq_item_conv_class] After converting awqos = 0 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(231) @ 370: reporter [axi4_master_seq_item_conv_class] After converting wait_count_write_address_channel = 1 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(236) @ 370: reporter [axi4_master_seq_item_conv_class] After converting wdata[0] = ffffffff +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(243) @ 370: reporter [axi4_master_seq_item_conv_class] After converting wstrb[0] = 0 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(248) @ 370: reporter [axi4_master_seq_item_conv_class] After converting wlast = 0 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(251) @ 370: reporter [axi4_master_seq_item_conv_class] After converting wuser = 0 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(254) @ 370: reporter [axi4_master_seq_item_conv_class] After converting wait_count_write_data_channel = 0 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(257) @ 370: reporter [axi4_master_seq_item_conv_class] After converting bid = 0000000000000000 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(260) @ 370: reporter [axi4_master_seq_item_conv_class] After converting bresp = 00 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(263) @ 370: reporter [axi4_master_seq_item_conv_class] After converting wait_count_write_response_channel = 0 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_driver_proxy.sv(202) @ 370: uvm_test_top.pulpino_spi_master_subsystem_env.axi4_master_agent.axi4_master_drv_proxy_h [axi4_master_driver_proxy] WRITE_TASK::Response Received_req_write_packet = +# ----------------------------------------------------------------------------------- +# Name Type Size Value +# ----------------------------------------------------------------------------------- +# axi4_master_tx axi4_master_tx - @2453 +# tx_type string 5 WRITE +# awid string 6 AWID_0 +# awaddr integral 32 'h1a102008 +# awlen integral 8 'd0 +# awsize string 13 WRITE_4_BYTES +# awburst string 10 WRITE_INCR +# awlock string 19 WRITE_NORMAL_ACCESS +# awcache string 16 WRITE_BUFFERABLE +# awprot string 24 WRITE_NORMAL_SECURE_DATA +# awqos integral 4 'h0 +# wait_count_write_address_channel integral 32 'h1 +# wdata[0] integral 64 'hffffffff +# wstrb[0] integral 8 'h0 +# wait_count_write_data_channel integral 32 'h0 +# bid string 5 BID_0 +# bresp string 10 WRITE_OKAY +# no_of_wait_states integral 32 'd0 +# wait_count_write_response_channel integral 32 'h0 +# transfer_type string 14 BLOCKING_WRITE +# ----------------------------------------------------------------------------------- +# +# UVM_INFO ../../src/dv/hdl_top/axi4_master_agent_bfm/axi4_master_monitor_bfm.sv(158) @ 370: reporter [FROM MASTER MON BFM::WRITE RESPONSE] WRITE RESPONSE PACKET: +# '{awid:0, awaddr:0, awlen:0, awsize:0, awburst:0, awlock:0, awcache:0, awqos:0, awregion:0, awuser:0, awprot:0, awvalid:0, awready:0, wdata:'{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, wstrb:'{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, wuser:0, wlast:0, bid:0, bresp:0, buser:0, bvalid:0, tx_type:0, wait_count_write_address_channel:0, wait_count_write_data_channel:0, wait_count_write_response_channel:0, outstanding_write_tx:0, no_of_wait_states:0} +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(198) @ 370: reporter [axi4_master_seq_item_conv_class] ---------------------------------------------------------------------- +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(204) @ 370: reporter [axi4_master_seq_item_conv_class] After converting awid = 0000000000000000 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(207) @ 370: reporter [axi4_master_seq_item_conv_class] After converting awlen = 00000000 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(210) @ 370: reporter [axi4_master_seq_item_conv_class] After randomizing awsize = 000 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(213) @ 370: reporter [axi4_master_seq_item_conv_class] After converting awburst = 00 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(216) @ 370: reporter [axi4_master_seq_item_conv_class] After converting awlock = 0 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(219) @ 370: reporter [axi4_master_seq_item_conv_class] After randomizing awcache = 0000 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(222) @ 370: reporter [axi4_master_seq_item_conv_class] After randomizing awprot = 000 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(225) @ 370: reporter [axi4_master_seq_item_conv_class] After converting awaddr = 0 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(228) @ 370: reporter [axi4_master_seq_item_conv_class] After converting awqos = 0 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(231) @ 370: reporter [axi4_master_seq_item_conv_class] After converting wait_count_write_address_channel = 0 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(248) @ 370: reporter [axi4_master_seq_item_conv_class] After converting wlast = 0 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(251) @ 370: reporter [axi4_master_seq_item_conv_class] After converting wuser = 0 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(254) @ 370: reporter [axi4_master_seq_item_conv_class] After converting wait_count_write_data_channel = 0 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(257) @ 370: reporter [axi4_master_seq_item_conv_class] After converting bid = 0000000000000000 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(260) @ 370: reporter [axi4_master_seq_item_conv_class] After converting bresp = 00 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(263) @ 370: reporter [axi4_master_seq_item_conv_class] After converting wait_count_write_response_channel = 0 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(384) @ 370: reporter [axi4_master_seq_item_conv_class] ---------------------------------------------------------------------- +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(402) @ 370: reporter [axi4_master_seq_item_conv_class] After converting wdata[0] = ffffffff +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(409) @ 370: reporter [axi4_master_seq_item_conv_class] After converting wstrb[0] = 0 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(417) @ 370: reporter [axi4_master_seq_item_conv_class] After converting = ----------------------------------------------------------------------------------- +# Name Type Size Value +# ----------------------------------------------------------------------------------- +# axi4_master_tx axi4_master_tx - @2461 +# tx_type string 5 WRITE +# awid string 6 AWID_0 +# awaddr integral 32 'h1a102008 +# awlen integral 8 'd0 +# awsize string 13 WRITE_4_BYTES +# awburst string 10 WRITE_INCR +# awlock string 19 WRITE_NORMAL_ACCESS +# awcache string 16 WRITE_BUFFERABLE +# awprot string 24 WRITE_NORMAL_SECURE_DATA +# awqos integral 4 'h0 +# wait_count_write_address_channel integral 32 'h0 +# wdata[0] integral 64 'hffffffff +# wstrb[0] integral 8 'h0 +# wait_count_write_data_channel integral 32 'h0 +# bid string 5 BID_0 +# bresp string 10 WRITE_OKAY +# no_of_wait_states integral 32 'd0 +# wait_count_write_response_channel integral 32 'h0 +# transfer_type string 14 BLOCKING_WRITE +# ----------------------------------------------------------------------------------- +# +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_monitor_proxy.sv(220) @ 370: uvm_test_top.pulpino_spi_master_subsystem_env.axi4_master_agent.axi4_master_mon_proxy_h [axi4_master_monitor_proxy] Packet received from axi4_write_response clone packet is +# ----------------------------------------------------------------------------------- +# Name Type Size Value +# ----------------------------------------------------------------------------------- +# axi4_master_tx axi4_master_tx - @2465 +# tx_type string 5 WRITE +# awid string 6 AWID_0 +# awaddr integral 32 'h1a102008 +# awlen integral 8 'd0 +# awsize string 13 WRITE_4_BYTES +# awburst string 10 WRITE_INCR +# awlock string 19 WRITE_NORMAL_ACCESS +# awcache string 16 WRITE_BUFFERABLE +# awprot string 24 WRITE_NORMAL_SECURE_DATA +# awqos integral 4 'h0 +# wait_count_write_address_channel integral 32 'h0 +# wdata[0] integral 64 'hffffffff +# wstrb[0] integral 8 'h0 +# wait_count_write_data_channel integral 32 'h0 +# bid string 5 BID_0 +# bresp string 10 WRITE_OKAY +# no_of_wait_states integral 32 'd0 +# wait_count_write_response_channel integral 32 'h0 +# transfer_type string 14 BLOCKING_WRITE +# ----------------------------------------------------------------------------------- +# +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_coverage.sv(223) @ 370: uvm_test_top.pulpino_spi_master_subsystem_env.axi4_master_agent.axi4_master_cov_h [axi4_master_coverage] Before calling SAMPLE METHOD +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_coverage.sv(227) @ 370: uvm_test_top.pulpino_spi_master_subsystem_env.axi4_master_agent.axi4_master_cov_h [axi4_master_coverage] After calling SAMPLE METHOD +# UVM_INFO ../../src/dv/hdl_top/axi4_master_agent_bfm/axi4_master_monitor_bfm.sv(151) @ 370: reporter [FROM MASTER MON BFM] AFTER WHILE LOOP OF WRITE RESPONSE +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_adapter.sv(118) @ 370: reporter [axi4_master_adapter] The converted bus2reg packet is ----------------------------------------------------------------------------------- +# Name Type Size Value +# ----------------------------------------------------------------------------------- +# axi4_master_tx axi4_master_tx - @2429 +# tx_type string 5 WRITE +# awid string 6 AWID_0 +# awaddr integral 32 'h1a102008 +# awlen integral 8 'd0 +# awsize string 13 WRITE_4_BYTES +# awburst string 10 WRITE_INCR +# awlock string 19 WRITE_NORMAL_ACCESS +# awcache string 16 WRITE_BUFFERABLE +# awprot string 24 WRITE_NORMAL_SECURE_DATA +# awqos integral 4 'h0 +# wait_count_write_address_channel integral 32 'h0 +# wdata[0] integral 64 'hffffffff +# wait_count_write_data_channel integral 32 'h0 +# bid string 5 BID_0 +# bresp string 10 WRITE_OKAY +# no_of_wait_states integral 32 'd0 +# wait_count_write_response_channel integral 32 'h0 +# transfer_type string 14 BLOCKING_WRITE +# ----------------------------------------------------------------------------------- +# +# +# UVM_INFO @ 370: reporter [RegModel] Wrote register via map spi_master_reg_block.SPI_MASTER_MAP_ABP_IF: spi_master_reg_block.SPICMD=0xffffffff +# UVM_INFO ../../src/dv/hvl_top/test/sequences/master_sequences/reg_sequences//axi4_master_basic_write_read_reg_seq.sv(124) @ 370: uvm_test_top.pulpino_spi_master_subsystem_env.axi4_master_agent.axi4_master_write_seqr_h@@axi4_master_basic_write_read_reg_seq_h [SPI_ADDR_REG_SEQ] WRITE:: REGISTER : spi_master_reg_block.SPIADR, DATA = 32'hffffffff +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_adapter.sv(53) @ 370: reporter [MSHA_DEBUG] +# rw.address = 1a10200c rw.data = ffffffff +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_adapter.sv(73) @ 370: reporter [axi4_master_adapter] The converted reg2bus packet is ----------------------------------------------------------------------------------- +# Name Type Size Value +# ----------------------------------------------------------------------------------- +# axi4_master_tx axi4_master_tx - @2473 +# tx_type string 5 WRITE +# awid string 6 AWID_0 +# awaddr integral 32 'h1a10200c +# awlen integral 8 'd0 +# awsize string 13 WRITE_4_BYTES +# awburst string 10 WRITE_INCR +# awlock string 19 WRITE_NORMAL_ACCESS +# awcache string 16 WRITE_BUFFERABLE +# awprot string 24 WRITE_NORMAL_SECURE_DATA +# awqos integral 4 'h0 +# wait_count_write_address_channel integral 32 'h0 +# wdata[0] integral 64 'hffffffff +# wait_count_write_data_channel integral 32 'h0 +# bid string 5 BID_0 +# bresp string 10 WRITE_OKAY +# no_of_wait_states integral 32 'd0 +# wait_count_write_response_channel integral 32 'h0 +# transfer_type string 14 BLOCKING_WRITE +# ----------------------------------------------------------------------------------- +# +# +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_driver_proxy.sv(167) @ 370: uvm_test_top.pulpino_spi_master_subsystem_env.axi4_master_agent.axi4_master_drv_proxy_h [axi4_master_driver_proxy] WRITE_TASK::Before Sending_req_write_packet = +# ----------------------------------------------------------------------------------- +# Name Type Size Value +# ----------------------------------------------------------------------------------- +# axi4_master_tx axi4_master_tx - @2473 +# tx_type string 5 WRITE +# awid string 6 AWID_0 +# awaddr integral 32 'h1a10200c +# awlen integral 8 'd0 +# awsize string 13 WRITE_4_BYTES +# awburst string 10 WRITE_INCR +# awlock string 19 WRITE_NORMAL_ACCESS +# awcache string 16 WRITE_BUFFERABLE +# awprot string 24 WRITE_NORMAL_SECURE_DATA +# awqos integral 4 'h0 +# wait_count_write_address_channel integral 32 'h0 +# wdata[0] integral 64 'hffffffff +# wait_count_write_data_channel integral 32 'h0 +# bid string 5 BID_0 +# bresp string 10 WRITE_OKAY +# no_of_wait_states integral 32 'd0 +# wait_count_write_response_channel integral 32 'h0 +# transfer_type string 14 BLOCKING_WRITE +# ----------------------------------------------------------------------------------- +# +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(47) @ 370: reporter [axi4_master_seq_item_conv_class] ---------------------------------------------------------------------- +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(49) @ 370: reporter [axi4_master_seq_item_conv_class] After converting awid = 0000 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(52) @ 370: reporter [axi4_master_seq_item_conv_class] After converting awlen = 00000000 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(55) @ 370: reporter [axi4_master_seq_item_conv_class] After randomizing awsize = 010 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(58) @ 370: reporter [axi4_master_seq_item_conv_class] After converting awburst = 01 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(61) @ 370: reporter [axi4_master_seq_item_conv_class] After converting awlock = 0 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(64) @ 370: reporter [axi4_master_seq_item_conv_class] After randomizing awcache = 0000 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(67) @ 370: reporter [axi4_master_seq_item_conv_class] After randomizing awprot = 000 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(70) @ 370: reporter [axi4_master_seq_item_conv_class] After converting bid = 0000 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(73) @ 370: reporter [axi4_master_seq_item_conv_class] After converting bresp = 00 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(76) @ 370: reporter [axi4_master_seq_item_conv_class] After converting buser = 0 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(81) @ 370: reporter [axi4_master_seq_item_conv_class] After converting awaddr = 1a10200c +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(84) @ 370: reporter [axi4_master_seq_item_conv_class] After converting awqos = 0 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(89) @ 370: reporter [axi4_master_seq_item_conv_class] After converting wdata = 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 4294967295 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(96) @ 370: reporter [axi4_master_seq_item_conv_class] After converting wstrb = 0 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(101) @ 370: reporter [axi4_master_seq_item_conv_class] After converting wlast = 0 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(104) @ 370: reporter [axi4_master_seq_item_conv_class] After converting wuser = 0 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(107) @ 370: reporter [axi4_master_seq_item_conv_class] After converting no_wait_states = 0 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_driver_proxy.sv(192) @ 370: uvm_test_top.pulpino_spi_master_subsystem_env.axi4_master_agent.axi4_master_drv_proxy_h [axi4_master_driver_proxy] WRITE_TASK::Checking transfer type = BLOCKING_WRITE +# UVM_INFO ../../src/dv/hdl_top/axi4_master_agent_bfm/axi4_master_driver_bfm.sv(117) @ 390: reporter [AXI4_MASTER_DRIVER_BFM] data_write_packet= +# '{awid:0, awaddr:437264396, awlen:0, awsize:2, awburst:1, awlock:0, awcache:0, awqos:0, awregion:0, awuser:0, awprot:0, awvalid:0, awready:0, wdata:'{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 4294967295}, wstrb:'{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, wuser:0, wlast:0, bid:0, bresp:0, buser:0, bvalid:0, tx_type:0, wait_count_write_address_channel:0, wait_count_write_data_channel:0, wait_count_write_response_channel:0, outstanding_write_tx:0, no_of_wait_states:0} +# UVM_INFO ../../src/dv/hdl_top/axi4_master_agent_bfm/axi4_master_driver_bfm.sv(118) @ 390: reporter [AXI4_MASTER_DRIVER_BFM] cfg_packet= +# '{min_address:0, max_address:0, wait_count_write_address_channel:0, wait_count_write_data_channel:0, wait_count_write_response_channel:0, wait_count_read_address_channel:0, wait_count_read_data_channel:0, outstanding_write_tx:0, outstanding_read_tx:0} +# UVM_INFO ../../src/dv/hdl_top/axi4_master_agent_bfm/axi4_master_driver_bfm.sv(119) @ 390: reporter [AXI4_MASTER_DRIVER_BFM] DRIVING_WRITE_ADDRESS_CHANNEL +# UVM_INFO ../../src/dv/hdl_top/axi4_master_agent_bfm/axi4_master_driver_bfm.sv(134) @ 390: reporter [AXI4_MASTER_DRIVER_BFM] detect_awready = 1 +# UVM_INFO ../../src/dv/hdl_top/axi4_master_agent_bfm/axi4_master_driver_bfm.sv(142) @ 410: reporter [AXI4_MASTER_DRIVER_BFM] After_loop_of_Detecting_awready = 1, awvalid = 1 +# UVM_INFO ../../src/dv/hdl_top/axi4_master_agent_bfm/axi4_master_driver_bfm.sv(153) @ 410: reporter [AXI4_MASTER_DRIVER_BFM] data_write_packet= +# '{awid:0, awaddr:437264396, awlen:0, awsize:2, awburst:1, awlock:0, awcache:0, awqos:0, awregion:0, awuser:0, awprot:0, awvalid:0, awready:0, wdata:'{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 4294967295}, wstrb:'{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, wuser:0, wlast:0, bid:0, bresp:0, buser:0, bvalid:0, tx_type:0, wait_count_write_address_channel:1, wait_count_write_data_channel:0, wait_count_write_response_channel:0, outstanding_write_tx:0, no_of_wait_states:0} +# UVM_INFO ../../src/dv/hdl_top/axi4_master_agent_bfm/axi4_master_driver_bfm.sv(154) @ 410: reporter [AXI4_MASTER_DRIVER_BFM] cfg_packet= +# '{min_address:0, max_address:0, wait_count_write_address_channel:0, wait_count_write_data_channel:0, wait_count_write_response_channel:0, wait_count_read_address_channel:0, wait_count_read_data_channel:0, outstanding_write_tx:0, outstanding_read_tx:0} +# UVM_INFO ../../src/dv/hdl_top/axi4_master_agent_bfm/axi4_master_driver_bfm.sv(155) @ 410: reporter [AXI4_MASTER_DRIVER_BFM] DRIVE TO WRITE DATA CHANNEL +# UVM_INFO ../../src/dv/hdl_top/axi4_master_agent_bfm/axi4_master_monitor_bfm.sv(102) @ 410: reporter [FROM MASTER MON BFM] after while loop ....... +# UVM_INFO ../../src/dv/hdl_top/axi4_master_agent_bfm/axi4_master_monitor_bfm.sv(112) @ 410: reporter [FROM MASTER MON BFM] datapacket ='{awid:0, awaddr:437264396, awlen:0, awsize:2, awburst:1, awlock:0, awcache:0, awqos:0, awregion:0, awuser:0, awprot:0, awvalid:0, awready:0, wdata:'{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, wstrb:'{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, wuser:0, wlast:0, bid:0, bresp:0, buser:0, bvalid:0, tx_type:0, wait_count_write_address_channel:0, wait_count_write_data_channel:0, wait_count_write_response_channel:0, outstanding_write_tx:0, no_of_wait_states:0} +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(198) @ 410: reporter [axi4_master_seq_item_conv_class] ---------------------------------------------------------------------- +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(204) @ 410: reporter [axi4_master_seq_item_conv_class] After converting awid = 0000000000000000 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(207) @ 410: reporter [axi4_master_seq_item_conv_class] After converting awlen = 00000000 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(210) @ 410: reporter [axi4_master_seq_item_conv_class] After randomizing awsize = 010 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(213) @ 410: reporter [axi4_master_seq_item_conv_class] After converting awburst = 01 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(216) @ 410: reporter [axi4_master_seq_item_conv_class] After converting awlock = 0 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(219) @ 410: reporter [axi4_master_seq_item_conv_class] After randomizing awcache = 0000 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(222) @ 410: reporter [axi4_master_seq_item_conv_class] After randomizing awprot = 000 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(225) @ 410: reporter [axi4_master_seq_item_conv_class] After converting awaddr = 1a10200c +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(228) @ 410: reporter [axi4_master_seq_item_conv_class] After converting awqos = 0 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(231) @ 410: reporter [axi4_master_seq_item_conv_class] After converting wait_count_write_address_channel = 0 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(248) @ 410: reporter [axi4_master_seq_item_conv_class] After converting wlast = 0 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(251) @ 410: reporter [axi4_master_seq_item_conv_class] After converting wuser = 0 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(254) @ 410: reporter [axi4_master_seq_item_conv_class] After converting wait_count_write_data_channel = 0 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(257) @ 410: reporter [axi4_master_seq_item_conv_class] After converting bid = 0000000000000000 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(260) @ 410: reporter [axi4_master_seq_item_conv_class] After converting bresp = 00 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(263) @ 410: reporter [axi4_master_seq_item_conv_class] After converting wait_count_write_response_channel = 0 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_monitor_proxy.sv(159) @ 410: uvm_test_top.pulpino_spi_master_subsystem_env.axi4_master_agent.axi4_master_mon_proxy_h [axi4_master_monitor_proxy] Packet received from axi4_write_address clone packet is +# ----------------------------------------------------------------------------------- +# Name Type Size Value +# ----------------------------------------------------------------------------------- +# axi4_master_tx axi4_master_tx - @2481 +# tx_type string 5 WRITE +# awid string 6 AWID_0 +# awaddr integral 32 'h1a10200c +# awlen integral 8 'd0 +# awsize string 13 WRITE_4_BYTES +# awburst string 10 WRITE_INCR +# awlock string 19 WRITE_NORMAL_ACCESS +# awcache string 16 WRITE_BUFFERABLE +# awprot string 24 WRITE_NORMAL_SECURE_DATA +# awqos integral 4 'h0 +# wait_count_write_address_channel integral 32 'h0 +# wait_count_write_data_channel integral 32 'h0 +# bid string 5 BID_0 +# bresp string 10 WRITE_OKAY +# no_of_wait_states integral 32 'd0 +# wait_count_write_response_channel integral 32 'h0 +# transfer_type string 14 BLOCKING_WRITE +# ----------------------------------------------------------------------------------- +# +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_coverage.sv(223) @ 410: uvm_test_top.pulpino_spi_master_subsystem_env.axi4_master_agent.axi4_master_cov_h [axi4_master_coverage] Before calling SAMPLE METHOD +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_coverage.sv(227) @ 410: uvm_test_top.pulpino_spi_master_subsystem_env.axi4_master_agent.axi4_master_cov_h [axi4_master_coverage] After calling SAMPLE METHOD +# UVM_INFO ../../src/dv/hvl_top/env//axi4_master_collector.sv(60) @ 410: uvm_test_top.pulpino_spi_master_subsystem_env.axi4_master_coll_h [axi4_master_collector] Req print = ----------------------------------------------------------------------------------- +# Name Type Size Value +# ----------------------------------------------------------------------------------- +# axi4_master_tx axi4_master_tx - @2481 +# tx_type string 5 WRITE +# awid string 6 AWID_0 +# awaddr integral 32 'h1a10200c +# awlen integral 8 'd0 +# awsize string 13 WRITE_4_BYTES +# awburst string 10 WRITE_INCR +# awlock string 19 WRITE_NORMAL_ACCESS +# awcache string 16 WRITE_BUFFERABLE +# awprot string 24 WRITE_NORMAL_SECURE_DATA +# awqos integral 4 'h0 +# wait_count_write_address_channel integral 32 'h0 +# wait_count_write_data_channel integral 32 'h0 +# bid string 5 BID_0 +# bresp string 10 WRITE_OKAY +# no_of_wait_states integral 32 'd0 +# wait_count_write_response_channel integral 32 'h0 +# transfer_type string 14 BLOCKING_WRITE +# ----------------------------------------------------------------------------------- +# +# UVM_INFO ../../src/dv/hvl_top/env//axi4_master_collector.sv(64) @ 410: uvm_test_top.pulpino_spi_master_subsystem_env.axi4_master_coll_h [axi4_master_collector] rg_name = SPIADR +# UVM_INFO ../../src/dv/hvl_top/env//axi4_master_collector.sv(65) @ 410: uvm_test_top.pulpino_spi_master_subsystem_env.axi4_master_coll_h [axi4_master_collector] rg_address = 1a10200c +# UVM_INFO ../../src/dv/hvl_top/env//axi4_master_collector.sv(66) @ 410: uvm_test_top.pulpino_spi_master_subsystem_env.axi4_master_coll_h [axi4_master_collector] rg_data = ffffffff +# UVM_INFO ../../src/dv/hvl_top/env//axi4_master_collector.sv(67) @ 410: uvm_test_top.pulpino_spi_master_subsystem_env.axi4_master_coll_h [axi4_master_collector] map_name = spi_master_reg_block.SPI_MASTER_MAP_ABP_IF +# UVM_INFO ../../src/dv/hvl_top/env//axi4_master_collector.sv(106) @ 410: uvm_test_top.pulpino_spi_master_subsystem_env.axi4_master_coll_h [axi4_master_collector] addr_local = ffffffff +# UVM_INFO ../../src/dv/hvl_top/env//axi4_master_collector.sv(107) @ 410: uvm_test_top.pulpino_spi_master_subsystem_env.axi4_master_coll_h [axi4_master_collector] spi_len[13:8] = 0 +# UVM_INFO ../../src/dv/hvl_top/env//axi4_master_collector.sv(119) @ 410: uvm_test_top.pulpino_spi_master_subsystem_env.axi4_master_coll_h [axi4_master_collector] Inside ADR--final_data=0 +# UVM_INFO ../../src/dv/hvl_top/env//axi4_master_collector.sv(121) @ 410: uvm_test_top.pulpino_spi_master_subsystem_env.axi4_master_coll_h [axi4_master_collector] addr_data = 0 +# UVM_INFO ../../src/dv/hvl_top/env//axi4_master_collector.sv(122) @ 410: uvm_test_top.pulpino_spi_master_subsystem_env.axi4_master_coll_h [axi4_master_collector] Inside TX_FIFO -flag=2 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_adapter.sv(118) @ 410: reporter [axi4_master_adapter] The converted bus2reg packet is ----------------------------------------------------------------------------------- +# Name Type Size Value +# ----------------------------------------------------------------------------------- +# axi4_master_tx axi4_master_tx - @2481 +# tx_type string 5 WRITE +# awid string 6 AWID_0 +# awaddr integral 32 'h1a10200c +# awlen integral 8 'd0 +# awsize string 13 WRITE_4_BYTES +# awburst string 10 WRITE_INCR +# awlock string 19 WRITE_NORMAL_ACCESS +# awcache string 16 WRITE_BUFFERABLE +# awprot string 24 WRITE_NORMAL_SECURE_DATA +# awqos integral 4 'h0 +# wait_count_write_address_channel integral 32 'h0 +# wait_count_write_data_channel integral 32 'h0 +# bid string 5 BID_0 +# bresp string 10 WRITE_OKAY +# no_of_wait_states integral 32 'd0 +# wait_count_write_response_channel integral 32 'h0 +# transfer_type string 14 BLOCKING_WRITE +# ----------------------------------------------------------------------------------- +# +# +# UVM_INFO verilog_src/uvm-1.1d/src/reg/uvm_reg_predictor.svh(221) @ 410: uvm_test_top.pulpino_spi_master_subsystem_env.axi4_reg_predictor_h [REG_PREDICT] Observed WRITE transaction to register spi_master_reg_block.SPIADR: value='h0 : updated value = 'h0 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_adapter.sv(118) @ 410: reporter [axi4_master_adapter] The converted bus2reg packet is ----------------------------------------------------------------------------------- +# Name Type Size Value +# ----------------------------------------------------------------------------------- +# axi4_master_tx axi4_master_tx - @2481 +# tx_type string 5 WRITE +# awid string 6 AWID_0 +# awaddr integral 32 'h1a10200c +# awlen integral 8 'd0 +# awsize string 13 WRITE_4_BYTES +# awburst string 10 WRITE_INCR +# awlock string 19 WRITE_NORMAL_ACCESS +# awcache string 16 WRITE_BUFFERABLE +# awprot string 24 WRITE_NORMAL_SECURE_DATA +# awqos integral 4 'h0 +# wait_count_write_address_channel integral 32 'h0 +# wait_count_write_data_channel integral 32 'h0 +# bid string 5 BID_0 +# bresp string 10 WRITE_OKAY +# no_of_wait_states integral 32 'd0 +# wait_count_write_response_channel integral 32 'h0 +# transfer_type string 14 BLOCKING_WRITE +# ----------------------------------------------------------------------------------- +# +# +# UVM_INFO ../../src/dv/hvl_top/env//axi4_reg_predictor.sv(48) @ 410: uvm_test_top.pulpino_spi_master_subsystem_env.axi4_reg_predictor_h [axi4_reg_predictor] rg_data = {SPIADR} 544 1 2489 @uvm_status_container@1 1 @spi_master_apb_if@1 null 32 32 { {@uvm_reg_map@1:1} } {@uvm_reg_field@12} 4 4 @semaphore@5 @18350080 {} 0 0 1 0 1 0 null @uvm_object_string_pool__3@4 32 1 @uvm_reg_field@12 {ref to covergroup #cg_vals#} {spi_master_apb_if__spiadr} +# UVM_INFO ../../src/dv/hvl_top/env//axi4_reg_predictor.sv(49) @ 410: uvm_test_top.pulpino_spi_master_subsystem_env.axi4_reg_predictor_h [axi4_reg_predictor] rw_data = UVM_WRITE 437264396 0 0 0 UVM_IS_OK +# UVM_INFO ../../src/dv/hdl_top/axi4_master_agent_bfm/axi4_master_driver_bfm.sv(165) @ 430: reporter [AXI4_MASTER_DRIVER_BFM] DETECT_WRITE_DATA_WAIT_STATE +# UVM_INFO ../../src/dv/hdl_top/axi4_master_agent_bfm/axi4_master_driver_bfm.sv(176) @ 450: reporter [AXI4_MASTER_DRIVER_BFM] DEBUG_NA:WDATA[0]=ffffffff +# UVM_INFO ../../src/dv/hdl_top/axi4_master_agent_bfm/axi4_master_driver_bfm.sv(181) @ 450: reporter [AXI4_MASTER_DRIVER_BFM] WRITE_DATA_COMP data_write_packet= +# '{awid:0, awaddr:437264396, awlen:0, awsize:2, awburst:1, awlock:0, awcache:0, awqos:0, awregion:0, awuser:0, awprot:0, awvalid:0, awready:0, wdata:'{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 4294967295}, wstrb:'{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, wuser:0, wlast:0, bid:0, bresp:0, buser:0, bvalid:0, tx_type:0, wait_count_write_address_channel:1, wait_count_write_data_channel:0, wait_count_write_response_channel:0, outstanding_write_tx:0, no_of_wait_states:0} +# UVM_INFO ../../src/dv/hdl_top/axi4_master_agent_bfm/axi4_master_driver_bfm.sv(190) @ 450: reporter [AXI4_MASTER_DRIVER_BFM] WRITE_RESP data_write_packet= +# '{awid:0, awaddr:437264396, awlen:0, awsize:2, awburst:1, awlock:0, awcache:0, awqos:0, awregion:0, awuser:0, awprot:0, awvalid:0, awready:0, wdata:'{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 4294967295}, wstrb:'{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, wuser:0, wlast:0, bid:0, bresp:0, buser:0, bvalid:0, tx_type:0, wait_count_write_address_channel:1, wait_count_write_data_channel:0, wait_count_write_response_channel:0, outstanding_write_tx:0, no_of_wait_states:0} +# UVM_INFO ../../src/dv/hdl_top/axi4_master_agent_bfm/axi4_master_driver_bfm.sv(191) @ 450: reporter [AXI4_MASTER_DRIVER_BFM] cfg_packet= +# '{min_address:0, max_address:0, wait_count_write_address_channel:0, wait_count_write_data_channel:0, wait_count_write_response_channel:0, wait_count_read_address_channel:0, wait_count_read_data_channel:0, outstanding_write_tx:0, outstanding_read_tx:0} +# UVM_INFO ../../src/dv/hdl_top/axi4_master_agent_bfm/axi4_master_driver_bfm.sv(192) @ 450: reporter [AXI4_MASTER_DRIVER_BFM] DRIVE TO WRITE RESPONSE CHANNEL +# UVM_INFO ../../src/dv/hdl_top/axi4_master_agent_bfm/axi4_master_monitor_bfm.sv(128) @ 450: reporter [FROM MASTER MON BFM] After while loop write data...... +# UVM_INFO ../../src/dv/hdl_top/axi4_master_agent_bfm/axi4_master_monitor_bfm.sv(135) @ 450: reporter [FROM MASTER MON BFM write data] write datapacket wdata[0] = 'hffffffff +# UVM_INFO ../../src/dv/hdl_top/axi4_master_agent_bfm/axi4_master_monitor_bfm.sv(136) @ 450: reporter [FROM MASTER MON BFM write data] write datapacket wstrb[0] = 'h0 +# UVM_INFO ../../src/dv/hdl_top/axi4_master_agent_bfm/axi4_master_monitor_bfm.sv(138) @ 450: reporter [FROM MASTER MON BFM write data] Inside wlast write datapacket ='{awid:0, awaddr:0, awlen:0, awsize:0, awburst:0, awlock:0, awcache:0, awqos:0, awregion:0, awuser:0, awprot:0, awvalid:0, awready:0, wdata:'{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 4294967295}, wstrb:'{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, wuser:0, wlast:1, bid:0, bresp:0, buser:0, bvalid:0, tx_type:0, wait_count_write_address_channel:0, wait_count_write_data_channel:0, wait_count_write_response_channel:0, outstanding_write_tx:0, no_of_wait_states:0} +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_monitor_proxy.sv(182) @ 450: uvm_test_top.pulpino_spi_master_subsystem_env.axi4_master_agent.axi4_master_mon_proxy_h [axi4_master_monitor_proxy] ADDR_Packet received from fifo is +# ----------------------------------------------------------------------------------- +# Name Type Size Value +# ----------------------------------------------------------------------------------- +# axi4_master_tx axi4_master_tx - @2477 +# tx_type string 5 WRITE +# awid string 6 AWID_0 +# awaddr integral 32 'h1a10200c +# awlen integral 8 'd0 +# awsize string 13 WRITE_4_BYTES +# awburst string 10 WRITE_INCR +# awlock string 19 WRITE_NORMAL_ACCESS +# awcache string 16 WRITE_BUFFERABLE +# awprot string 24 WRITE_NORMAL_SECURE_DATA +# awqos integral 4 'h0 +# wait_count_write_address_channel integral 32 'h0 +# wait_count_write_data_channel integral 32 'h0 +# bid string 5 BID_0 +# bresp string 10 WRITE_OKAY +# no_of_wait_states integral 32 'd0 +# wait_count_write_response_channel integral 32 'h0 +# transfer_type string 14 BLOCKING_WRITE +# ----------------------------------------------------------------------------------- +# +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(337) @ 450: reporter [axi4_master_seq_item_conv_class] ---------------------------------------------------------------------- +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(355) @ 450: reporter [axi4_master_seq_item_conv_class] After converting wdata[0] = ffffffff +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(362) @ 450: reporter [axi4_master_seq_item_conv_class] After converting wstrb[0] = 0 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(370) @ 450: reporter [axi4_master_seq_item_conv_class] After converting = ----------------------------------------------------------------------------------- +# Name Type Size Value +# ----------------------------------------------------------------------------------- +# axi4_master_tx axi4_master_tx - @2489 +# tx_type string 5 WRITE +# awid string 6 AWID_0 +# awaddr integral 32 'h1a10200c +# awlen integral 8 'd0 +# awsize string 13 WRITE_4_BYTES +# awburst string 10 WRITE_INCR +# awlock string 19 WRITE_NORMAL_ACCESS +# awcache string 16 WRITE_BUFFERABLE +# awprot string 24 WRITE_NORMAL_SECURE_DATA +# awqos integral 4 'h0 +# wait_count_write_address_channel integral 32 'h0 +# wdata[0] integral 64 'hffffffff +# wstrb[0] integral 8 'h0 +# wait_count_write_data_channel integral 32 'h0 +# bid string 5 BID_0 +# bresp string 10 WRITE_OKAY +# no_of_wait_states integral 32 'd0 +# wait_count_write_response_channel integral 32 'h0 +# transfer_type string 14 BLOCKING_WRITE +# ----------------------------------------------------------------------------------- +# +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_monitor_proxy.sv(191) @ 450: uvm_test_top.pulpino_spi_master_subsystem_env.axi4_master_agent.axi4_master_mon_proxy_h [axi4_master_monitor_proxy] Packet received from axi4_write_data clone packet is +# ----------------------------------------------------------------------------------- +# Name Type Size Value +# ----------------------------------------------------------------------------------- +# axi4_master_tx axi4_master_tx - @2493 +# tx_type string 5 WRITE +# awid string 6 AWID_0 +# awaddr integral 32 'h1a10200c +# awlen integral 8 'd0 +# awsize string 13 WRITE_4_BYTES +# awburst string 10 WRITE_INCR +# awlock string 19 WRITE_NORMAL_ACCESS +# awcache string 16 WRITE_BUFFERABLE +# awprot string 24 WRITE_NORMAL_SECURE_DATA +# awqos integral 4 'h0 +# wait_count_write_address_channel integral 32 'h0 +# wdata[0] integral 64 'hffffffff +# wstrb[0] integral 8 'h0 +# wait_count_write_data_channel integral 32 'h0 +# bid string 5 BID_0 +# bresp string 10 WRITE_OKAY +# no_of_wait_states integral 32 'd0 +# wait_count_write_response_channel integral 32 'h0 +# transfer_type string 14 BLOCKING_WRITE +# ----------------------------------------------------------------------------------- +# +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_coverage.sv(223) @ 450: uvm_test_top.pulpino_spi_master_subsystem_env.axi4_master_agent.axi4_master_cov_h [axi4_master_coverage] Before calling SAMPLE METHOD +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_coverage.sv(227) @ 450: uvm_test_top.pulpino_spi_master_subsystem_env.axi4_master_agent.axi4_master_cov_h [axi4_master_coverage] After calling SAMPLE METHOD +# UVM_INFO ../../src/dv/hdl_top/axi4_master_agent_bfm/axi4_master_driver_bfm.sv(210) @ 510: reporter [AXI4_MASTER_DRIVER_BFM] CHECKING WRITE RESPONSE :: '{awid:0, awaddr:437264396, awlen:0, awsize:2, awburst:1, awlock:0, awcache:0, awqos:0, awregion:0, awuser:0, awprot:0, awvalid:0, awready:0, wdata:'{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 4294967295}, wstrb:'{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, wuser:0, wlast:0, bid:0, bresp:0, buser:0, bvalid:1, tx_type:0, wait_count_write_address_channel:1, wait_count_write_data_channel:0, wait_count_write_response_channel:0, outstanding_write_tx:0, no_of_wait_states:0} +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(198) @ 530: reporter [axi4_master_seq_item_conv_class] ---------------------------------------------------------------------- +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(204) @ 530: reporter [axi4_master_seq_item_conv_class] After converting awid = 0000000000000000 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(207) @ 530: reporter [axi4_master_seq_item_conv_class] After converting awlen = 00000000 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(210) @ 530: reporter [axi4_master_seq_item_conv_class] After randomizing awsize = 010 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(213) @ 530: reporter [axi4_master_seq_item_conv_class] After converting awburst = 01 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(216) @ 530: reporter [axi4_master_seq_item_conv_class] After converting awlock = 0 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(219) @ 530: reporter [axi4_master_seq_item_conv_class] After randomizing awcache = 0000 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(222) @ 530: reporter [axi4_master_seq_item_conv_class] After randomizing awprot = 000 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(225) @ 530: reporter [axi4_master_seq_item_conv_class] After converting awaddr = 1a10200c +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(228) @ 530: reporter [axi4_master_seq_item_conv_class] After converting awqos = 0 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(231) @ 530: reporter [axi4_master_seq_item_conv_class] After converting wait_count_write_address_channel = 1 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(236) @ 530: reporter [axi4_master_seq_item_conv_class] After converting wdata[0] = ffffffff +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(243) @ 530: reporter [axi4_master_seq_item_conv_class] After converting wstrb[0] = 0 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(248) @ 530: reporter [axi4_master_seq_item_conv_class] After converting wlast = 0 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(251) @ 530: reporter [axi4_master_seq_item_conv_class] After converting wuser = 0 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(254) @ 530: reporter [axi4_master_seq_item_conv_class] After converting wait_count_write_data_channel = 0 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(257) @ 530: reporter [axi4_master_seq_item_conv_class] After converting bid = 0000000000000000 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(260) @ 530: reporter [axi4_master_seq_item_conv_class] After converting bresp = 00 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(263) @ 530: reporter [axi4_master_seq_item_conv_class] After converting wait_count_write_response_channel = 0 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_driver_proxy.sv(202) @ 530: uvm_test_top.pulpino_spi_master_subsystem_env.axi4_master_agent.axi4_master_drv_proxy_h [axi4_master_driver_proxy] WRITE_TASK::Response Received_req_write_packet = +# ----------------------------------------------------------------------------------- +# Name Type Size Value +# ----------------------------------------------------------------------------------- +# axi4_master_tx axi4_master_tx - @2497 +# tx_type string 5 WRITE +# awid string 6 AWID_0 +# awaddr integral 32 'h1a10200c +# awlen integral 8 'd0 +# awsize string 13 WRITE_4_BYTES +# awburst string 10 WRITE_INCR +# awlock string 19 WRITE_NORMAL_ACCESS +# awcache string 16 WRITE_BUFFERABLE +# awprot string 24 WRITE_NORMAL_SECURE_DATA +# awqos integral 4 'h0 +# wait_count_write_address_channel integral 32 'h1 +# wdata[0] integral 64 'hffffffff +# wstrb[0] integral 8 'h0 +# wait_count_write_data_channel integral 32 'h0 +# bid string 5 BID_0 +# bresp string 10 WRITE_OKAY +# no_of_wait_states integral 32 'd0 +# wait_count_write_response_channel integral 32 'h0 +# transfer_type string 14 BLOCKING_WRITE +# ----------------------------------------------------------------------------------- +# +# UVM_INFO ../../src/dv/hdl_top/axi4_master_agent_bfm/axi4_master_monitor_bfm.sv(158) @ 530: reporter [FROM MASTER MON BFM::WRITE RESPONSE] WRITE RESPONSE PACKET: +# '{awid:0, awaddr:0, awlen:0, awsize:0, awburst:0, awlock:0, awcache:0, awqos:0, awregion:0, awuser:0, awprot:0, awvalid:0, awready:0, wdata:'{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, wstrb:'{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, wuser:0, wlast:0, bid:0, bresp:0, buser:0, bvalid:0, tx_type:0, wait_count_write_address_channel:0, wait_count_write_data_channel:0, wait_count_write_response_channel:0, outstanding_write_tx:0, no_of_wait_states:0} +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(198) @ 530: reporter [axi4_master_seq_item_conv_class] ---------------------------------------------------------------------- +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(204) @ 530: reporter [axi4_master_seq_item_conv_class] After converting awid = 0000000000000000 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(207) @ 530: reporter [axi4_master_seq_item_conv_class] After converting awlen = 00000000 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(210) @ 530: reporter [axi4_master_seq_item_conv_class] After randomizing awsize = 000 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(213) @ 530: reporter [axi4_master_seq_item_conv_class] After converting awburst = 00 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(216) @ 530: reporter [axi4_master_seq_item_conv_class] After converting awlock = 0 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(219) @ 530: reporter [axi4_master_seq_item_conv_class] After randomizing awcache = 0000 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(222) @ 530: reporter [axi4_master_seq_item_conv_class] After randomizing awprot = 000 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(225) @ 530: reporter [axi4_master_seq_item_conv_class] After converting awaddr = 0 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(228) @ 530: reporter [axi4_master_seq_item_conv_class] After converting awqos = 0 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(231) @ 530: reporter [axi4_master_seq_item_conv_class] After converting wait_count_write_address_channel = 0 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(248) @ 530: reporter [axi4_master_seq_item_conv_class] After converting wlast = 0 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(251) @ 530: reporter [axi4_master_seq_item_conv_class] After converting wuser = 0 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(254) @ 530: reporter [axi4_master_seq_item_conv_class] After converting wait_count_write_data_channel = 0 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(257) @ 530: reporter [axi4_master_seq_item_conv_class] After converting bid = 0000000000000000 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(260) @ 530: reporter [axi4_master_seq_item_conv_class] After converting bresp = 00 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(263) @ 530: reporter [axi4_master_seq_item_conv_class] After converting wait_count_write_response_channel = 0 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(384) @ 530: reporter [axi4_master_seq_item_conv_class] ---------------------------------------------------------------------- +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(402) @ 530: reporter [axi4_master_seq_item_conv_class] After converting wdata[0] = ffffffff +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(409) @ 530: reporter [axi4_master_seq_item_conv_class] After converting wstrb[0] = 0 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(417) @ 530: reporter [axi4_master_seq_item_conv_class] After converting = ----------------------------------------------------------------------------------- +# Name Type Size Value +# ----------------------------------------------------------------------------------- +# axi4_master_tx axi4_master_tx - @2505 +# tx_type string 5 WRITE +# awid string 6 AWID_0 +# awaddr integral 32 'h1a10200c +# awlen integral 8 'd0 +# awsize string 13 WRITE_4_BYTES +# awburst string 10 WRITE_INCR +# awlock string 19 WRITE_NORMAL_ACCESS +# awcache string 16 WRITE_BUFFERABLE +# awprot string 24 WRITE_NORMAL_SECURE_DATA +# awqos integral 4 'h0 +# wait_count_write_address_channel integral 32 'h0 +# wdata[0] integral 64 'hffffffff +# wstrb[0] integral 8 'h0 +# wait_count_write_data_channel integral 32 'h0 +# bid string 5 BID_0 +# bresp string 10 WRITE_OKAY +# no_of_wait_states integral 32 'd0 +# wait_count_write_response_channel integral 32 'h0 +# transfer_type string 14 BLOCKING_WRITE +# ----------------------------------------------------------------------------------- +# +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_monitor_proxy.sv(220) @ 530: uvm_test_top.pulpino_spi_master_subsystem_env.axi4_master_agent.axi4_master_mon_proxy_h [axi4_master_monitor_proxy] Packet received from axi4_write_response clone packet is +# ----------------------------------------------------------------------------------- +# Name Type Size Value +# ----------------------------------------------------------------------------------- +# axi4_master_tx axi4_master_tx - @2509 +# tx_type string 5 WRITE +# awid string 6 AWID_0 +# awaddr integral 32 'h1a10200c +# awlen integral 8 'd0 +# awsize string 13 WRITE_4_BYTES +# awburst string 10 WRITE_INCR +# awlock string 19 WRITE_NORMAL_ACCESS +# awcache string 16 WRITE_BUFFERABLE +# awprot string 24 WRITE_NORMAL_SECURE_DATA +# awqos integral 4 'h0 +# wait_count_write_address_channel integral 32 'h0 +# wdata[0] integral 64 'hffffffff +# wstrb[0] integral 8 'h0 +# wait_count_write_data_channel integral 32 'h0 +# bid string 5 BID_0 +# bresp string 10 WRITE_OKAY +# no_of_wait_states integral 32 'd0 +# wait_count_write_response_channel integral 32 'h0 +# transfer_type string 14 BLOCKING_WRITE +# ----------------------------------------------------------------------------------- +# +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_coverage.sv(223) @ 530: uvm_test_top.pulpino_spi_master_subsystem_env.axi4_master_agent.axi4_master_cov_h [axi4_master_coverage] Before calling SAMPLE METHOD +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_coverage.sv(227) @ 530: uvm_test_top.pulpino_spi_master_subsystem_env.axi4_master_agent.axi4_master_cov_h [axi4_master_coverage] After calling SAMPLE METHOD +# UVM_INFO ../../src/dv/hdl_top/axi4_master_agent_bfm/axi4_master_monitor_bfm.sv(151) @ 530: reporter [FROM MASTER MON BFM] AFTER WHILE LOOP OF WRITE RESPONSE +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_adapter.sv(118) @ 530: reporter [axi4_master_adapter] The converted bus2reg packet is ----------------------------------------------------------------------------------- +# Name Type Size Value +# ----------------------------------------------------------------------------------- +# axi4_master_tx axi4_master_tx - @2473 +# tx_type string 5 WRITE +# awid string 6 AWID_0 +# awaddr integral 32 'h1a10200c +# awlen integral 8 'd0 +# awsize string 13 WRITE_4_BYTES +# awburst string 10 WRITE_INCR +# awlock string 19 WRITE_NORMAL_ACCESS +# awcache string 16 WRITE_BUFFERABLE +# awprot string 24 WRITE_NORMAL_SECURE_DATA +# awqos integral 4 'h0 +# wait_count_write_address_channel integral 32 'h0 +# wdata[0] integral 64 'hffffffff +# wait_count_write_data_channel integral 32 'h0 +# bid string 5 BID_0 +# bresp string 10 WRITE_OKAY +# no_of_wait_states integral 32 'd0 +# wait_count_write_response_channel integral 32 'h0 +# transfer_type string 14 BLOCKING_WRITE +# ----------------------------------------------------------------------------------- +# +# +# UVM_INFO @ 530: reporter [RegModel] Wrote register via map spi_master_reg_block.SPI_MASTER_MAP_ABP_IF: spi_master_reg_block.SPIADR=0xffffffff +# UVM_INFO ../../src/dv/hvl_top/test/sequences/master_sequences/reg_sequences//axi4_master_basic_write_read_reg_seq.sv(160) @ 530: uvm_test_top.pulpino_spi_master_subsystem_env.axi4_master_agent.axi4_master_write_seqr_h@@axi4_master_basic_write_read_reg_seq_h [axi4_master_basic_write_read_reg_seq] Write :: Register cmd_length = 8 +# UVM_INFO ../../src/dv/hvl_top/test/sequences/master_sequences/reg_sequences//axi4_master_basic_write_read_reg_seq.sv(161) @ 530: uvm_test_top.pulpino_spi_master_subsystem_env.axi4_master_agent.axi4_master_write_seqr_h@@axi4_master_basic_write_read_reg_seq_h [axi4_master_basic_write_read_reg_seq] Write :: Register addr_length = 8 +# UVM_INFO ../../src/dv/hvl_top/test/sequences/master_sequences/reg_sequences//axi4_master_basic_write_read_reg_seq.sv(162) @ 530: uvm_test_top.pulpino_spi_master_subsystem_env.axi4_master_agent.axi4_master_write_seqr_h@@axi4_master_basic_write_read_reg_seq_h [axi4_master_basic_write_read_reg_seq] Write :: Register data_length = 20 +# UVM_INFO ../../src/dv/hvl_top/test/sequences/master_sequences/reg_sequences//axi4_master_basic_write_read_reg_seq.sv(176) @ 530: uvm_test_top.pulpino_spi_master_subsystem_env.axi4_master_agent.axi4_master_write_seqr_h@@axi4_master_basic_write_read_reg_seq_h [SPI_LEN_REG_SEQ] WRITE:: REGISTER : spi_master_reg_block.SPILEN, DATA = 32'h20c8c8 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_adapter.sv(53) @ 530: reporter [MSHA_DEBUG] +# rw.address = 1a102010 rw.data = 20c8c8 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_adapter.sv(73) @ 530: reporter [axi4_master_adapter] The converted reg2bus packet is ----------------------------------------------------------------------------------- +# Name Type Size Value +# ----------------------------------------------------------------------------------- +# axi4_master_tx axi4_master_tx - @2517 +# tx_type string 5 WRITE +# awid string 6 AWID_0 +# awaddr integral 32 'h1a102010 +# awlen integral 8 'd0 +# awsize string 13 WRITE_4_BYTES +# awburst string 10 WRITE_INCR +# awlock string 19 WRITE_NORMAL_ACCESS +# awcache string 16 WRITE_BUFFERABLE +# awprot string 24 WRITE_NORMAL_SECURE_DATA +# awqos integral 4 'h0 +# wait_count_write_address_channel integral 32 'h0 +# wdata[0] integral 64 'h20c8c8 +# wait_count_write_data_channel integral 32 'h0 +# bid string 5 BID_0 +# bresp string 10 WRITE_OKAY +# no_of_wait_states integral 32 'd0 +# wait_count_write_response_channel integral 32 'h0 +# transfer_type string 14 BLOCKING_WRITE +# ----------------------------------------------------------------------------------- +# +# +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_driver_proxy.sv(167) @ 530: uvm_test_top.pulpino_spi_master_subsystem_env.axi4_master_agent.axi4_master_drv_proxy_h [axi4_master_driver_proxy] WRITE_TASK::Before Sending_req_write_packet = +# ----------------------------------------------------------------------------------- +# Name Type Size Value +# ----------------------------------------------------------------------------------- +# axi4_master_tx axi4_master_tx - @2517 +# tx_type string 5 WRITE +# awid string 6 AWID_0 +# awaddr integral 32 'h1a102010 +# awlen integral 8 'd0 +# awsize string 13 WRITE_4_BYTES +# awburst string 10 WRITE_INCR +# awlock string 19 WRITE_NORMAL_ACCESS +# awcache string 16 WRITE_BUFFERABLE +# awprot string 24 WRITE_NORMAL_SECURE_DATA +# awqos integral 4 'h0 +# wait_count_write_address_channel integral 32 'h0 +# wdata[0] integral 64 'h20c8c8 +# wait_count_write_data_channel integral 32 'h0 +# bid string 5 BID_0 +# bresp string 10 WRITE_OKAY +# no_of_wait_states integral 32 'd0 +# wait_count_write_response_channel integral 32 'h0 +# transfer_type string 14 BLOCKING_WRITE +# ----------------------------------------------------------------------------------- +# +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(47) @ 530: reporter [axi4_master_seq_item_conv_class] ---------------------------------------------------------------------- +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(49) @ 530: reporter [axi4_master_seq_item_conv_class] After converting awid = 0000 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(52) @ 530: reporter [axi4_master_seq_item_conv_class] After converting awlen = 00000000 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(55) @ 530: reporter [axi4_master_seq_item_conv_class] After randomizing awsize = 010 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(58) @ 530: reporter [axi4_master_seq_item_conv_class] After converting awburst = 01 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(61) @ 530: reporter [axi4_master_seq_item_conv_class] After converting awlock = 0 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(64) @ 530: reporter [axi4_master_seq_item_conv_class] After randomizing awcache = 0000 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(67) @ 530: reporter [axi4_master_seq_item_conv_class] After randomizing awprot = 000 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(70) @ 530: reporter [axi4_master_seq_item_conv_class] After converting bid = 0000 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(73) @ 530: reporter [axi4_master_seq_item_conv_class] After converting bresp = 00 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(76) @ 530: reporter [axi4_master_seq_item_conv_class] After converting buser = 0 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(81) @ 530: reporter [axi4_master_seq_item_conv_class] After converting awaddr = 1a102010 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(84) @ 530: reporter [axi4_master_seq_item_conv_class] After converting awqos = 0 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(89) @ 530: reporter [axi4_master_seq_item_conv_class] After converting wdata = 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2148552 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(96) @ 530: reporter [axi4_master_seq_item_conv_class] After converting wstrb = 0 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(101) @ 530: reporter [axi4_master_seq_item_conv_class] After converting wlast = 0 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(104) @ 530: reporter [axi4_master_seq_item_conv_class] After converting wuser = 0 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(107) @ 530: reporter [axi4_master_seq_item_conv_class] After converting no_wait_states = 0 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_driver_proxy.sv(192) @ 530: uvm_test_top.pulpino_spi_master_subsystem_env.axi4_master_agent.axi4_master_drv_proxy_h [axi4_master_driver_proxy] WRITE_TASK::Checking transfer type = BLOCKING_WRITE +# UVM_INFO ../../src/dv/hdl_top/axi4_master_agent_bfm/axi4_master_driver_bfm.sv(117) @ 550: reporter [AXI4_MASTER_DRIVER_BFM] data_write_packet= +# '{awid:0, awaddr:437264400, awlen:0, awsize:2, awburst:1, awlock:0, awcache:0, awqos:0, awregion:0, awuser:0, awprot:0, awvalid:0, awready:0, wdata:'{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 2148552}, wstrb:'{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, wuser:0, wlast:0, bid:0, bresp:0, buser:0, bvalid:0, tx_type:0, wait_count_write_address_channel:0, wait_count_write_data_channel:0, wait_count_write_response_channel:0, outstanding_write_tx:0, no_of_wait_states:0} +# UVM_INFO ../../src/dv/hdl_top/axi4_master_agent_bfm/axi4_master_driver_bfm.sv(118) @ 550: reporter [AXI4_MASTER_DRIVER_BFM] cfg_packet= +# '{min_address:0, max_address:0, wait_count_write_address_channel:0, wait_count_write_data_channel:0, wait_count_write_response_channel:0, wait_count_read_address_channel:0, wait_count_read_data_channel:0, outstanding_write_tx:0, outstanding_read_tx:0} +# UVM_INFO ../../src/dv/hdl_top/axi4_master_agent_bfm/axi4_master_driver_bfm.sv(119) @ 550: reporter [AXI4_MASTER_DRIVER_BFM] DRIVING_WRITE_ADDRESS_CHANNEL +# UVM_INFO ../../src/dv/hdl_top/axi4_master_agent_bfm/axi4_master_driver_bfm.sv(134) @ 550: reporter [AXI4_MASTER_DRIVER_BFM] detect_awready = 1 +# UVM_INFO ../../src/dv/hdl_top/axi4_master_agent_bfm/axi4_master_driver_bfm.sv(142) @ 570: reporter [AXI4_MASTER_DRIVER_BFM] After_loop_of_Detecting_awready = 1, awvalid = 1 +# UVM_INFO ../../src/dv/hdl_top/axi4_master_agent_bfm/axi4_master_driver_bfm.sv(153) @ 570: reporter [AXI4_MASTER_DRIVER_BFM] data_write_packet= +# '{awid:0, awaddr:437264400, awlen:0, awsize:2, awburst:1, awlock:0, awcache:0, awqos:0, awregion:0, awuser:0, awprot:0, awvalid:0, awready:0, wdata:'{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 2148552}, wstrb:'{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, wuser:0, wlast:0, bid:0, bresp:0, buser:0, bvalid:0, tx_type:0, wait_count_write_address_channel:1, wait_count_write_data_channel:0, wait_count_write_response_channel:0, outstanding_write_tx:0, no_of_wait_states:0} +# UVM_INFO ../../src/dv/hdl_top/axi4_master_agent_bfm/axi4_master_driver_bfm.sv(154) @ 570: reporter [AXI4_MASTER_DRIVER_BFM] cfg_packet= +# '{min_address:0, max_address:0, wait_count_write_address_channel:0, wait_count_write_data_channel:0, wait_count_write_response_channel:0, wait_count_read_address_channel:0, wait_count_read_data_channel:0, outstanding_write_tx:0, outstanding_read_tx:0} +# UVM_INFO ../../src/dv/hdl_top/axi4_master_agent_bfm/axi4_master_driver_bfm.sv(155) @ 570: reporter [AXI4_MASTER_DRIVER_BFM] DRIVE TO WRITE DATA CHANNEL +# UVM_INFO ../../src/dv/hdl_top/axi4_master_agent_bfm/axi4_master_monitor_bfm.sv(102) @ 570: reporter [FROM MASTER MON BFM] after while loop ....... +# UVM_INFO ../../src/dv/hdl_top/axi4_master_agent_bfm/axi4_master_monitor_bfm.sv(112) @ 570: reporter [FROM MASTER MON BFM] datapacket ='{awid:0, awaddr:437264400, awlen:0, awsize:2, awburst:1, awlock:0, awcache:0, awqos:0, awregion:0, awuser:0, awprot:0, awvalid:0, awready:0, wdata:'{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, wstrb:'{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, wuser:0, wlast:0, bid:0, bresp:0, buser:0, bvalid:0, tx_type:0, wait_count_write_address_channel:0, wait_count_write_data_channel:0, wait_count_write_response_channel:0, outstanding_write_tx:0, no_of_wait_states:0} +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(198) @ 570: reporter [axi4_master_seq_item_conv_class] ---------------------------------------------------------------------- +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(204) @ 570: reporter [axi4_master_seq_item_conv_class] After converting awid = 0000000000000000 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(207) @ 570: reporter [axi4_master_seq_item_conv_class] After converting awlen = 00000000 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(210) @ 570: reporter [axi4_master_seq_item_conv_class] After randomizing awsize = 010 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(213) @ 570: reporter [axi4_master_seq_item_conv_class] After converting awburst = 01 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(216) @ 570: reporter [axi4_master_seq_item_conv_class] After converting awlock = 0 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(219) @ 570: reporter [axi4_master_seq_item_conv_class] After randomizing awcache = 0000 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(222) @ 570: reporter [axi4_master_seq_item_conv_class] After randomizing awprot = 000 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(225) @ 570: reporter [axi4_master_seq_item_conv_class] After converting awaddr = 1a102010 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(228) @ 570: reporter [axi4_master_seq_item_conv_class] After converting awqos = 0 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(231) @ 570: reporter [axi4_master_seq_item_conv_class] After converting wait_count_write_address_channel = 0 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(248) @ 570: reporter [axi4_master_seq_item_conv_class] After converting wlast = 0 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(251) @ 570: reporter [axi4_master_seq_item_conv_class] After converting wuser = 0 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(254) @ 570: reporter [axi4_master_seq_item_conv_class] After converting wait_count_write_data_channel = 0 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(257) @ 570: reporter [axi4_master_seq_item_conv_class] After converting bid = 0000000000000000 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(260) @ 570: reporter [axi4_master_seq_item_conv_class] After converting bresp = 00 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(263) @ 570: reporter [axi4_master_seq_item_conv_class] After converting wait_count_write_response_channel = 0 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_monitor_proxy.sv(159) @ 570: uvm_test_top.pulpino_spi_master_subsystem_env.axi4_master_agent.axi4_master_mon_proxy_h [axi4_master_monitor_proxy] Packet received from axi4_write_address clone packet is +# ----------------------------------------------------------------------------------- +# Name Type Size Value +# ----------------------------------------------------------------------------------- +# axi4_master_tx axi4_master_tx - @2525 +# tx_type string 5 WRITE +# awid string 6 AWID_0 +# awaddr integral 32 'h1a102010 +# awlen integral 8 'd0 +# awsize string 13 WRITE_4_BYTES +# awburst string 10 WRITE_INCR +# awlock string 19 WRITE_NORMAL_ACCESS +# awcache string 16 WRITE_BUFFERABLE +# awprot string 24 WRITE_NORMAL_SECURE_DATA +# awqos integral 4 'h0 +# wait_count_write_address_channel integral 32 'h0 +# wait_count_write_data_channel integral 32 'h0 +# bid string 5 BID_0 +# bresp string 10 WRITE_OKAY +# no_of_wait_states integral 32 'd0 +# wait_count_write_response_channel integral 32 'h0 +# transfer_type string 14 BLOCKING_WRITE +# ----------------------------------------------------------------------------------- +# +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_coverage.sv(223) @ 570: uvm_test_top.pulpino_spi_master_subsystem_env.axi4_master_agent.axi4_master_cov_h [axi4_master_coverage] Before calling SAMPLE METHOD +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_coverage.sv(227) @ 570: uvm_test_top.pulpino_spi_master_subsystem_env.axi4_master_agent.axi4_master_cov_h [axi4_master_coverage] After calling SAMPLE METHOD +# UVM_INFO ../../src/dv/hvl_top/env//axi4_master_collector.sv(60) @ 570: uvm_test_top.pulpino_spi_master_subsystem_env.axi4_master_coll_h [axi4_master_collector] Req print = ----------------------------------------------------------------------------------- +# Name Type Size Value +# ----------------------------------------------------------------------------------- +# axi4_master_tx axi4_master_tx - @2525 +# tx_type string 5 WRITE +# awid string 6 AWID_0 +# awaddr integral 32 'h1a102010 +# awlen integral 8 'd0 +# awsize string 13 WRITE_4_BYTES +# awburst string 10 WRITE_INCR +# awlock string 19 WRITE_NORMAL_ACCESS +# awcache string 16 WRITE_BUFFERABLE +# awprot string 24 WRITE_NORMAL_SECURE_DATA +# awqos integral 4 'h0 +# wait_count_write_address_channel integral 32 'h0 +# wait_count_write_data_channel integral 32 'h0 +# bid string 5 BID_0 +# bresp string 10 WRITE_OKAY +# no_of_wait_states integral 32 'd0 +# wait_count_write_response_channel integral 32 'h0 +# transfer_type string 14 BLOCKING_WRITE +# ----------------------------------------------------------------------------------- +# +# UVM_INFO ../../src/dv/hvl_top/env//axi4_master_collector.sv(64) @ 570: uvm_test_top.pulpino_spi_master_subsystem_env.axi4_master_coll_h [axi4_master_collector] rg_name = SPILEN +# UVM_INFO ../../src/dv/hvl_top/env//axi4_master_collector.sv(65) @ 570: uvm_test_top.pulpino_spi_master_subsystem_env.axi4_master_coll_h [axi4_master_collector] rg_address = 1a102010 +# UVM_INFO ../../src/dv/hvl_top/env//axi4_master_collector.sv(66) @ 570: uvm_test_top.pulpino_spi_master_subsystem_env.axi4_master_coll_h [axi4_master_collector] rg_data = 200808 +# UVM_INFO ../../src/dv/hvl_top/env//axi4_master_collector.sv(67) @ 570: uvm_test_top.pulpino_spi_master_subsystem_env.axi4_master_coll_h [axi4_master_collector] map_name = spi_master_reg_block.SPI_MASTER_MAP_ABP_IF +# UVM_INFO ../../src/dv/hvl_top/env//axi4_master_collector.sv(71) @ 570: uvm_test_top.pulpino_spi_master_subsystem_env.axi4_master_coll_h [axi4_master_collector] coll_pkt.spi_length = 200808 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_adapter.sv(118) @ 570: reporter [axi4_master_adapter] The converted bus2reg packet is ----------------------------------------------------------------------------------- +# Name Type Size Value +# ----------------------------------------------------------------------------------- +# axi4_master_tx axi4_master_tx - @2525 +# tx_type string 5 WRITE +# awid string 6 AWID_0 +# awaddr integral 32 'h1a102010 +# awlen integral 8 'd0 +# awsize string 13 WRITE_4_BYTES +# awburst string 10 WRITE_INCR +# awlock string 19 WRITE_NORMAL_ACCESS +# awcache string 16 WRITE_BUFFERABLE +# awprot string 24 WRITE_NORMAL_SECURE_DATA +# awqos integral 4 'h0 +# wait_count_write_address_channel integral 32 'h0 +# wait_count_write_data_channel integral 32 'h0 +# bid string 5 BID_0 +# bresp string 10 WRITE_OKAY +# no_of_wait_states integral 32 'd0 +# wait_count_write_response_channel integral 32 'h0 +# transfer_type string 14 BLOCKING_WRITE +# ----------------------------------------------------------------------------------- +# +# +# UVM_INFO verilog_src/uvm-1.1d/src/reg/uvm_reg_predictor.svh(221) @ 570: uvm_test_top.pulpino_spi_master_subsystem_env.axi4_reg_predictor_h [REG_PREDICT] Observed WRITE transaction to register spi_master_reg_block.SPILEN: value='h0 : updated value = 'h0 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_adapter.sv(118) @ 570: reporter [axi4_master_adapter] The converted bus2reg packet is ----------------------------------------------------------------------------------- +# Name Type Size Value +# ----------------------------------------------------------------------------------- +# axi4_master_tx axi4_master_tx - @2525 +# tx_type string 5 WRITE +# awid string 6 AWID_0 +# awaddr integral 32 'h1a102010 +# awlen integral 8 'd0 +# awsize string 13 WRITE_4_BYTES +# awburst string 10 WRITE_INCR +# awlock string 19 WRITE_NORMAL_ACCESS +# awcache string 16 WRITE_BUFFERABLE +# awprot string 24 WRITE_NORMAL_SECURE_DATA +# awqos integral 4 'h0 +# wait_count_write_address_channel integral 32 'h0 +# wait_count_write_data_channel integral 32 'h0 +# bid string 5 BID_0 +# bresp string 10 WRITE_OKAY +# no_of_wait_states integral 32 'd0 +# wait_count_write_response_channel integral 32 'h0 +# transfer_type string 14 BLOCKING_WRITE +# ----------------------------------------------------------------------------------- +# +# +# UVM_INFO ../../src/dv/hvl_top/env//axi4_reg_predictor.sv(48) @ 570: uvm_test_top.pulpino_spi_master_subsystem_env.axi4_reg_predictor_h [axi4_reg_predictor] rg_data = {SPILEN} 549 1 2533 @uvm_status_container@1 1 @spi_master_apb_if@1 null 32 28 { {@uvm_reg_map@1:1} } {@uvm_reg_field@17 @uvm_reg_field@15 @uvm_reg_field@13} 4 4 @semaphore@6 @18350080 {} 0 0 1 0 1 0 null @uvm_object_string_pool__3@5 32 1 @uvm_reg_field@13 @uvm_reg_field@14 @uvm_reg_field@15 @uvm_reg_field@16 @uvm_reg_field@17 {ref to covergroup #cg_vals#} {spi_master_apb_if__spilen} +# UVM_INFO ../../src/dv/hvl_top/env//axi4_reg_predictor.sv(49) @ 570: uvm_test_top.pulpino_spi_master_subsystem_env.axi4_reg_predictor_h [axi4_reg_predictor] rw_data = UVM_WRITE 437264400 0 0 0 UVM_IS_OK +# UVM_INFO ../../src/dv/hdl_top/axi4_master_agent_bfm/axi4_master_driver_bfm.sv(165) @ 590: reporter [AXI4_MASTER_DRIVER_BFM] DETECT_WRITE_DATA_WAIT_STATE +# UVM_INFO ../../src/dv/hdl_top/axi4_master_agent_bfm/axi4_master_driver_bfm.sv(176) @ 610: reporter [AXI4_MASTER_DRIVER_BFM] DEBUG_NA:WDATA[0]=20c8c8 +# UVM_INFO ../../src/dv/hdl_top/axi4_master_agent_bfm/axi4_master_driver_bfm.sv(181) @ 610: reporter [AXI4_MASTER_DRIVER_BFM] WRITE_DATA_COMP data_write_packet= +# '{awid:0, awaddr:437264400, awlen:0, awsize:2, awburst:1, awlock:0, awcache:0, awqos:0, awregion:0, awuser:0, awprot:0, awvalid:0, awready:0, wdata:'{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 2148552}, wstrb:'{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, wuser:0, wlast:0, bid:0, bresp:0, buser:0, bvalid:0, tx_type:0, wait_count_write_address_channel:1, wait_count_write_data_channel:0, wait_count_write_response_channel:0, outstanding_write_tx:0, no_of_wait_states:0} +# UVM_INFO ../../src/dv/hdl_top/axi4_master_agent_bfm/axi4_master_driver_bfm.sv(190) @ 610: reporter [AXI4_MASTER_DRIVER_BFM] WRITE_RESP data_write_packet= +# '{awid:0, awaddr:437264400, awlen:0, awsize:2, awburst:1, awlock:0, awcache:0, awqos:0, awregion:0, awuser:0, awprot:0, awvalid:0, awready:0, wdata:'{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 2148552}, wstrb:'{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, wuser:0, wlast:0, bid:0, bresp:0, buser:0, bvalid:0, tx_type:0, wait_count_write_address_channel:1, wait_count_write_data_channel:0, wait_count_write_response_channel:0, outstanding_write_tx:0, no_of_wait_states:0} +# UVM_INFO ../../src/dv/hdl_top/axi4_master_agent_bfm/axi4_master_driver_bfm.sv(191) @ 610: reporter [AXI4_MASTER_DRIVER_BFM] cfg_packet= +# '{min_address:0, max_address:0, wait_count_write_address_channel:0, wait_count_write_data_channel:0, wait_count_write_response_channel:0, wait_count_read_address_channel:0, wait_count_read_data_channel:0, outstanding_write_tx:0, outstanding_read_tx:0} +# UVM_INFO ../../src/dv/hdl_top/axi4_master_agent_bfm/axi4_master_driver_bfm.sv(192) @ 610: reporter [AXI4_MASTER_DRIVER_BFM] DRIVE TO WRITE RESPONSE CHANNEL +# UVM_INFO ../../src/dv/hdl_top/axi4_master_agent_bfm/axi4_master_monitor_bfm.sv(128) @ 610: reporter [FROM MASTER MON BFM] After while loop write data...... +# UVM_INFO ../../src/dv/hdl_top/axi4_master_agent_bfm/axi4_master_monitor_bfm.sv(135) @ 610: reporter [FROM MASTER MON BFM write data] write datapacket wdata[0] = 'h20c8c8 +# UVM_INFO ../../src/dv/hdl_top/axi4_master_agent_bfm/axi4_master_monitor_bfm.sv(136) @ 610: reporter [FROM MASTER MON BFM write data] write datapacket wstrb[0] = 'h0 +# UVM_INFO ../../src/dv/hdl_top/axi4_master_agent_bfm/axi4_master_monitor_bfm.sv(138) @ 610: reporter [FROM MASTER MON BFM write data] Inside wlast write datapacket ='{awid:0, awaddr:0, awlen:0, awsize:0, awburst:0, awlock:0, awcache:0, awqos:0, awregion:0, awuser:0, awprot:0, awvalid:0, awready:0, wdata:'{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 2148552}, wstrb:'{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, wuser:0, wlast:1, bid:0, bresp:0, buser:0, bvalid:0, tx_type:0, wait_count_write_address_channel:0, wait_count_write_data_channel:0, wait_count_write_response_channel:0, outstanding_write_tx:0, no_of_wait_states:0} +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_monitor_proxy.sv(182) @ 610: uvm_test_top.pulpino_spi_master_subsystem_env.axi4_master_agent.axi4_master_mon_proxy_h [axi4_master_monitor_proxy] ADDR_Packet received from fifo is +# ----------------------------------------------------------------------------------- +# Name Type Size Value +# ----------------------------------------------------------------------------------- +# axi4_master_tx axi4_master_tx - @2521 +# tx_type string 5 WRITE +# awid string 6 AWID_0 +# awaddr integral 32 'h1a102010 +# awlen integral 8 'd0 +# awsize string 13 WRITE_4_BYTES +# awburst string 10 WRITE_INCR +# awlock string 19 WRITE_NORMAL_ACCESS +# awcache string 16 WRITE_BUFFERABLE +# awprot string 24 WRITE_NORMAL_SECURE_DATA +# awqos integral 4 'h0 +# wait_count_write_address_channel integral 32 'h0 +# wait_count_write_data_channel integral 32 'h0 +# bid string 5 BID_0 +# bresp string 10 WRITE_OKAY +# no_of_wait_states integral 32 'd0 +# wait_count_write_response_channel integral 32 'h0 +# transfer_type string 14 BLOCKING_WRITE +# ----------------------------------------------------------------------------------- +# +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(337) @ 610: reporter [axi4_master_seq_item_conv_class] ---------------------------------------------------------------------- +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(355) @ 610: reporter [axi4_master_seq_item_conv_class] After converting wdata[0] = 20c8c8 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(362) @ 610: reporter [axi4_master_seq_item_conv_class] After converting wstrb[0] = 0 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(370) @ 610: reporter [axi4_master_seq_item_conv_class] After converting = ----------------------------------------------------------------------------------- +# Name Type Size Value +# ----------------------------------------------------------------------------------- +# axi4_master_tx axi4_master_tx - @2533 +# tx_type string 5 WRITE +# awid string 6 AWID_0 +# awaddr integral 32 'h1a102010 +# awlen integral 8 'd0 +# awsize string 13 WRITE_4_BYTES +# awburst string 10 WRITE_INCR +# awlock string 19 WRITE_NORMAL_ACCESS +# awcache string 16 WRITE_BUFFERABLE +# awprot string 24 WRITE_NORMAL_SECURE_DATA +# awqos integral 4 'h0 +# wait_count_write_address_channel integral 32 'h0 +# wdata[0] integral 64 'h20c8c8 +# wstrb[0] integral 8 'h0 +# wait_count_write_data_channel integral 32 'h0 +# bid string 5 BID_0 +# bresp string 10 WRITE_OKAY +# no_of_wait_states integral 32 'd0 +# wait_count_write_response_channel integral 32 'h0 +# transfer_type string 14 BLOCKING_WRITE +# ----------------------------------------------------------------------------------- +# +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_monitor_proxy.sv(191) @ 610: uvm_test_top.pulpino_spi_master_subsystem_env.axi4_master_agent.axi4_master_mon_proxy_h [axi4_master_monitor_proxy] Packet received from axi4_write_data clone packet is +# ----------------------------------------------------------------------------------- +# Name Type Size Value +# ----------------------------------------------------------------------------------- +# axi4_master_tx axi4_master_tx - @2537 +# tx_type string 5 WRITE +# awid string 6 AWID_0 +# awaddr integral 32 'h1a102010 +# awlen integral 8 'd0 +# awsize string 13 WRITE_4_BYTES +# awburst string 10 WRITE_INCR +# awlock string 19 WRITE_NORMAL_ACCESS +# awcache string 16 WRITE_BUFFERABLE +# awprot string 24 WRITE_NORMAL_SECURE_DATA +# awqos integral 4 'h0 +# wait_count_write_address_channel integral 32 'h0 +# wdata[0] integral 64 'h20c8c8 +# wstrb[0] integral 8 'h0 +# wait_count_write_data_channel integral 32 'h0 +# bid string 5 BID_0 +# bresp string 10 WRITE_OKAY +# no_of_wait_states integral 32 'd0 +# wait_count_write_response_channel integral 32 'h0 +# transfer_type string 14 BLOCKING_WRITE +# ----------------------------------------------------------------------------------- +# +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_coverage.sv(223) @ 610: uvm_test_top.pulpino_spi_master_subsystem_env.axi4_master_agent.axi4_master_cov_h [axi4_master_coverage] Before calling SAMPLE METHOD +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_coverage.sv(227) @ 610: uvm_test_top.pulpino_spi_master_subsystem_env.axi4_master_agent.axi4_master_cov_h [axi4_master_coverage] After calling SAMPLE METHOD +# UVM_INFO ../../src/dv/hdl_top/axi4_master_agent_bfm/axi4_master_driver_bfm.sv(210) @ 670: reporter [AXI4_MASTER_DRIVER_BFM] CHECKING WRITE RESPONSE :: '{awid:0, awaddr:437264400, awlen:0, awsize:2, awburst:1, awlock:0, awcache:0, awqos:0, awregion:0, awuser:0, awprot:0, awvalid:0, awready:0, wdata:'{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 2148552}, wstrb:'{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, wuser:0, wlast:0, bid:0, bresp:0, buser:0, bvalid:1, tx_type:0, wait_count_write_address_channel:1, wait_count_write_data_channel:0, wait_count_write_response_channel:0, outstanding_write_tx:0, no_of_wait_states:0} +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(198) @ 690: reporter [axi4_master_seq_item_conv_class] ---------------------------------------------------------------------- +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(204) @ 690: reporter [axi4_master_seq_item_conv_class] After converting awid = 0000000000000000 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(207) @ 690: reporter [axi4_master_seq_item_conv_class] After converting awlen = 00000000 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(210) @ 690: reporter [axi4_master_seq_item_conv_class] After randomizing awsize = 010 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(213) @ 690: reporter [axi4_master_seq_item_conv_class] After converting awburst = 01 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(216) @ 690: reporter [axi4_master_seq_item_conv_class] After converting awlock = 0 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(219) @ 690: reporter [axi4_master_seq_item_conv_class] After randomizing awcache = 0000 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(222) @ 690: reporter [axi4_master_seq_item_conv_class] After randomizing awprot = 000 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(225) @ 690: reporter [axi4_master_seq_item_conv_class] After converting awaddr = 1a102010 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(228) @ 690: reporter [axi4_master_seq_item_conv_class] After converting awqos = 0 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(231) @ 690: reporter [axi4_master_seq_item_conv_class] After converting wait_count_write_address_channel = 1 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(236) @ 690: reporter [axi4_master_seq_item_conv_class] After converting wdata[0] = 20c8c8 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(243) @ 690: reporter [axi4_master_seq_item_conv_class] After converting wstrb[0] = 0 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(248) @ 690: reporter [axi4_master_seq_item_conv_class] After converting wlast = 0 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(251) @ 690: reporter [axi4_master_seq_item_conv_class] After converting wuser = 0 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(254) @ 690: reporter [axi4_master_seq_item_conv_class] After converting wait_count_write_data_channel = 0 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(257) @ 690: reporter [axi4_master_seq_item_conv_class] After converting bid = 0000000000000000 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(260) @ 690: reporter [axi4_master_seq_item_conv_class] After converting bresp = 00 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(263) @ 690: reporter [axi4_master_seq_item_conv_class] After converting wait_count_write_response_channel = 0 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_driver_proxy.sv(202) @ 690: uvm_test_top.pulpino_spi_master_subsystem_env.axi4_master_agent.axi4_master_drv_proxy_h [axi4_master_driver_proxy] WRITE_TASK::Response Received_req_write_packet = +# ----------------------------------------------------------------------------------- +# Name Type Size Value +# ----------------------------------------------------------------------------------- +# axi4_master_tx axi4_master_tx - @2541 +# tx_type string 5 WRITE +# awid string 6 AWID_0 +# awaddr integral 32 'h1a102010 +# awlen integral 8 'd0 +# awsize string 13 WRITE_4_BYTES +# awburst string 10 WRITE_INCR +# awlock string 19 WRITE_NORMAL_ACCESS +# awcache string 16 WRITE_BUFFERABLE +# awprot string 24 WRITE_NORMAL_SECURE_DATA +# awqos integral 4 'h0 +# wait_count_write_address_channel integral 32 'h1 +# wdata[0] integral 64 'h20c8c8 +# wstrb[0] integral 8 'h0 +# wait_count_write_data_channel integral 32 'h0 +# bid string 5 BID_0 +# bresp string 10 WRITE_OKAY +# no_of_wait_states integral 32 'd0 +# wait_count_write_response_channel integral 32 'h0 +# transfer_type string 14 BLOCKING_WRITE +# ----------------------------------------------------------------------------------- +# +# UVM_INFO ../../src/dv/hdl_top/axi4_master_agent_bfm/axi4_master_monitor_bfm.sv(158) @ 690: reporter [FROM MASTER MON BFM::WRITE RESPONSE] WRITE RESPONSE PACKET: +# '{awid:0, awaddr:0, awlen:0, awsize:0, awburst:0, awlock:0, awcache:0, awqos:0, awregion:0, awuser:0, awprot:0, awvalid:0, awready:0, wdata:'{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, wstrb:'{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, wuser:0, wlast:0, bid:0, bresp:0, buser:0, bvalid:0, tx_type:0, wait_count_write_address_channel:0, wait_count_write_data_channel:0, wait_count_write_response_channel:0, outstanding_write_tx:0, no_of_wait_states:0} +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(198) @ 690: reporter [axi4_master_seq_item_conv_class] ---------------------------------------------------------------------- +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(204) @ 690: reporter [axi4_master_seq_item_conv_class] After converting awid = 0000000000000000 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(207) @ 690: reporter [axi4_master_seq_item_conv_class] After converting awlen = 00000000 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(210) @ 690: reporter [axi4_master_seq_item_conv_class] After randomizing awsize = 000 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(213) @ 690: reporter [axi4_master_seq_item_conv_class] After converting awburst = 00 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(216) @ 690: reporter [axi4_master_seq_item_conv_class] After converting awlock = 0 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(219) @ 690: reporter [axi4_master_seq_item_conv_class] After randomizing awcache = 0000 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(222) @ 690: reporter [axi4_master_seq_item_conv_class] After randomizing awprot = 000 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(225) @ 690: reporter [axi4_master_seq_item_conv_class] After converting awaddr = 0 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(228) @ 690: reporter [axi4_master_seq_item_conv_class] After converting awqos = 0 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(231) @ 690: reporter [axi4_master_seq_item_conv_class] After converting wait_count_write_address_channel = 0 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(248) @ 690: reporter [axi4_master_seq_item_conv_class] After converting wlast = 0 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(251) @ 690: reporter [axi4_master_seq_item_conv_class] After converting wuser = 0 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(254) @ 690: reporter [axi4_master_seq_item_conv_class] After converting wait_count_write_data_channel = 0 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(257) @ 690: reporter [axi4_master_seq_item_conv_class] After converting bid = 0000000000000000 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(260) @ 690: reporter [axi4_master_seq_item_conv_class] After converting bresp = 00 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(263) @ 690: reporter [axi4_master_seq_item_conv_class] After converting wait_count_write_response_channel = 0 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(384) @ 690: reporter [axi4_master_seq_item_conv_class] ---------------------------------------------------------------------- +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(402) @ 690: reporter [axi4_master_seq_item_conv_class] After converting wdata[0] = 20c8c8 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(409) @ 690: reporter [axi4_master_seq_item_conv_class] After converting wstrb[0] = 0 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(417) @ 690: reporter [axi4_master_seq_item_conv_class] After converting = ----------------------------------------------------------------------------------- +# Name Type Size Value +# ----------------------------------------------------------------------------------- +# axi4_master_tx axi4_master_tx - @2549 +# tx_type string 5 WRITE +# awid string 6 AWID_0 +# awaddr integral 32 'h1a102010 +# awlen integral 8 'd0 +# awsize string 13 WRITE_4_BYTES +# awburst string 10 WRITE_INCR +# awlock string 19 WRITE_NORMAL_ACCESS +# awcache string 16 WRITE_BUFFERABLE +# awprot string 24 WRITE_NORMAL_SECURE_DATA +# awqos integral 4 'h0 +# wait_count_write_address_channel integral 32 'h0 +# wdata[0] integral 64 'h20c8c8 +# wstrb[0] integral 8 'h0 +# wait_count_write_data_channel integral 32 'h0 +# bid string 5 BID_0 +# bresp string 10 WRITE_OKAY +# no_of_wait_states integral 32 'd0 +# wait_count_write_response_channel integral 32 'h0 +# transfer_type string 14 BLOCKING_WRITE +# ----------------------------------------------------------------------------------- +# +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_monitor_proxy.sv(220) @ 690: uvm_test_top.pulpino_spi_master_subsystem_env.axi4_master_agent.axi4_master_mon_proxy_h [axi4_master_monitor_proxy] Packet received from axi4_write_response clone packet is +# ----------------------------------------------------------------------------------- +# Name Type Size Value +# ----------------------------------------------------------------------------------- +# axi4_master_tx axi4_master_tx - @2553 +# tx_type string 5 WRITE +# awid string 6 AWID_0 +# awaddr integral 32 'h1a102010 +# awlen integral 8 'd0 +# awsize string 13 WRITE_4_BYTES +# awburst string 10 WRITE_INCR +# awlock string 19 WRITE_NORMAL_ACCESS +# awcache string 16 WRITE_BUFFERABLE +# awprot string 24 WRITE_NORMAL_SECURE_DATA +# awqos integral 4 'h0 +# wait_count_write_address_channel integral 32 'h0 +# wdata[0] integral 64 'h20c8c8 +# wstrb[0] integral 8 'h0 +# wait_count_write_data_channel integral 32 'h0 +# bid string 5 BID_0 +# bresp string 10 WRITE_OKAY +# no_of_wait_states integral 32 'd0 +# wait_count_write_response_channel integral 32 'h0 +# transfer_type string 14 BLOCKING_WRITE +# ----------------------------------------------------------------------------------- +# +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_coverage.sv(223) @ 690: uvm_test_top.pulpino_spi_master_subsystem_env.axi4_master_agent.axi4_master_cov_h [axi4_master_coverage] Before calling SAMPLE METHOD +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_coverage.sv(227) @ 690: uvm_test_top.pulpino_spi_master_subsystem_env.axi4_master_agent.axi4_master_cov_h [axi4_master_coverage] After calling SAMPLE METHOD +# UVM_INFO ../../src/dv/hdl_top/axi4_master_agent_bfm/axi4_master_monitor_bfm.sv(151) @ 690: reporter [FROM MASTER MON BFM] AFTER WHILE LOOP OF WRITE RESPONSE +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_adapter.sv(118) @ 690: reporter [axi4_master_adapter] The converted bus2reg packet is ----------------------------------------------------------------------------------- +# Name Type Size Value +# ----------------------------------------------------------------------------------- +# axi4_master_tx axi4_master_tx - @2517 +# tx_type string 5 WRITE +# awid string 6 AWID_0 +# awaddr integral 32 'h1a102010 +# awlen integral 8 'd0 +# awsize string 13 WRITE_4_BYTES +# awburst string 10 WRITE_INCR +# awlock string 19 WRITE_NORMAL_ACCESS +# awcache string 16 WRITE_BUFFERABLE +# awprot string 24 WRITE_NORMAL_SECURE_DATA +# awqos integral 4 'h0 +# wait_count_write_address_channel integral 32 'h0 +# wdata[0] integral 64 'h20c8c8 +# wait_count_write_data_channel integral 32 'h0 +# bid string 5 BID_0 +# bresp string 10 WRITE_OKAY +# no_of_wait_states integral 32 'd0 +# wait_count_write_response_channel integral 32 'h0 +# transfer_type string 14 BLOCKING_WRITE +# ----------------------------------------------------------------------------------- +# +# +# UVM_INFO @ 690: reporter [RegModel] Wrote register via map spi_master_reg_block.SPI_MASTER_MAP_ABP_IF: spi_master_reg_block.SPILEN=0x20c8c8 +# UVM_INFO ../../src/dv/hvl_top/test/sequences/master_sequences/reg_sequences//axi4_master_basic_write_read_reg_seq.sv(210) @ 690: uvm_test_top.pulpino_spi_master_subsystem_env.axi4_master_agent.axi4_master_write_seqr_h@@axi4_master_basic_write_read_reg_seq_h [axi4_master_basic_write_read_reg_seq] Write :: Register dummy_wr = ffff +# UVM_INFO ../../src/dv/hvl_top/test/sequences/master_sequences/reg_sequences//axi4_master_basic_write_read_reg_seq.sv(211) @ 690: uvm_test_top.pulpino_spi_master_subsystem_env.axi4_master_agent.axi4_master_write_seqr_h@@axi4_master_basic_write_read_reg_seq_h [axi4_master_basic_write_read_reg_seq] Write :: Register dummy_rd = ffff +# UVM_INFO ../../src/dv/hvl_top/test/sequences/master_sequences/reg_sequences//axi4_master_basic_write_read_reg_seq.sv(222) @ 690: uvm_test_top.pulpino_spi_master_subsystem_env.axi4_master_agent.axi4_master_write_seqr_h@@axi4_master_basic_write_read_reg_seq_h [DUMMY_REG_SEQ] WRITE:: REGISTER : spi_master_reg_block.SPIDUM, DATA = 32'h0 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_adapter.sv(53) @ 690: reporter [MSHA_DEBUG] +# rw.address = 1a102014 rw.data = 0 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_adapter.sv(73) @ 690: reporter [axi4_master_adapter] The converted reg2bus packet is ----------------------------------------------------------------------------------- +# Name Type Size Value +# ----------------------------------------------------------------------------------- +# axi4_master_tx axi4_master_tx - @2561 +# tx_type string 5 WRITE +# awid string 6 AWID_0 +# awaddr integral 32 'h1a102014 +# awlen integral 8 'd0 +# awsize string 13 WRITE_4_BYTES +# awburst string 10 WRITE_INCR +# awlock string 19 WRITE_NORMAL_ACCESS +# awcache string 16 WRITE_BUFFERABLE +# awprot string 24 WRITE_NORMAL_SECURE_DATA +# awqos integral 4 'h0 +# wait_count_write_address_channel integral 32 'h0 +# wdata[0] integral 64 'h0 +# wait_count_write_data_channel integral 32 'h0 +# bid string 5 BID_0 +# bresp string 10 WRITE_OKAY +# no_of_wait_states integral 32 'd0 +# wait_count_write_response_channel integral 32 'h0 +# transfer_type string 14 BLOCKING_WRITE +# ----------------------------------------------------------------------------------- +# +# +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_driver_proxy.sv(167) @ 690: uvm_test_top.pulpino_spi_master_subsystem_env.axi4_master_agent.axi4_master_drv_proxy_h [axi4_master_driver_proxy] WRITE_TASK::Before Sending_req_write_packet = +# ----------------------------------------------------------------------------------- +# Name Type Size Value +# ----------------------------------------------------------------------------------- +# axi4_master_tx axi4_master_tx - @2561 +# tx_type string 5 WRITE +# awid string 6 AWID_0 +# awaddr integral 32 'h1a102014 +# awlen integral 8 'd0 +# awsize string 13 WRITE_4_BYTES +# awburst string 10 WRITE_INCR +# awlock string 19 WRITE_NORMAL_ACCESS +# awcache string 16 WRITE_BUFFERABLE +# awprot string 24 WRITE_NORMAL_SECURE_DATA +# awqos integral 4 'h0 +# wait_count_write_address_channel integral 32 'h0 +# wdata[0] integral 64 'h0 +# wait_count_write_data_channel integral 32 'h0 +# bid string 5 BID_0 +# bresp string 10 WRITE_OKAY +# no_of_wait_states integral 32 'd0 +# wait_count_write_response_channel integral 32 'h0 +# transfer_type string 14 BLOCKING_WRITE +# ----------------------------------------------------------------------------------- +# +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(47) @ 690: reporter [axi4_master_seq_item_conv_class] ---------------------------------------------------------------------- +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(49) @ 690: reporter [axi4_master_seq_item_conv_class] After converting awid = 0000 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(52) @ 690: reporter [axi4_master_seq_item_conv_class] After converting awlen = 00000000 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(55) @ 690: reporter [axi4_master_seq_item_conv_class] After randomizing awsize = 010 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(58) @ 690: reporter [axi4_master_seq_item_conv_class] After converting awburst = 01 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(61) @ 690: reporter [axi4_master_seq_item_conv_class] After converting awlock = 0 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(64) @ 690: reporter [axi4_master_seq_item_conv_class] After randomizing awcache = 0000 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(67) @ 690: reporter [axi4_master_seq_item_conv_class] After randomizing awprot = 000 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(70) @ 690: reporter [axi4_master_seq_item_conv_class] After converting bid = 0000 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(73) @ 690: reporter [axi4_master_seq_item_conv_class] After converting bresp = 00 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(76) @ 690: reporter [axi4_master_seq_item_conv_class] After converting buser = 0 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(81) @ 690: reporter [axi4_master_seq_item_conv_class] After converting awaddr = 1a102014 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(84) @ 690: reporter [axi4_master_seq_item_conv_class] After converting awqos = 0 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(101) @ 690: reporter [axi4_master_seq_item_conv_class] After converting wlast = 0 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(104) @ 690: reporter [axi4_master_seq_item_conv_class] After converting wuser = 0 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(107) @ 690: reporter [axi4_master_seq_item_conv_class] After converting no_wait_states = 0 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_driver_proxy.sv(192) @ 690: uvm_test_top.pulpino_spi_master_subsystem_env.axi4_master_agent.axi4_master_drv_proxy_h [axi4_master_driver_proxy] WRITE_TASK::Checking transfer type = BLOCKING_WRITE +# UVM_INFO ../../src/dv/hdl_top/axi4_master_agent_bfm/axi4_master_driver_bfm.sv(117) @ 710: reporter [AXI4_MASTER_DRIVER_BFM] data_write_packet= +# '{awid:0, awaddr:437264404, awlen:0, awsize:2, awburst:1, awlock:0, awcache:0, awqos:0, awregion:0, awuser:0, awprot:0, awvalid:0, awready:0, wdata:'{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, wstrb:'{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, wuser:0, wlast:0, bid:0, bresp:0, buser:0, bvalid:0, tx_type:0, wait_count_write_address_channel:0, wait_count_write_data_channel:0, wait_count_write_response_channel:0, outstanding_write_tx:0, no_of_wait_states:0} +# UVM_INFO ../../src/dv/hdl_top/axi4_master_agent_bfm/axi4_master_driver_bfm.sv(118) @ 710: reporter [AXI4_MASTER_DRIVER_BFM] cfg_packet= +# '{min_address:0, max_address:0, wait_count_write_address_channel:0, wait_count_write_data_channel:0, wait_count_write_response_channel:0, wait_count_read_address_channel:0, wait_count_read_data_channel:0, outstanding_write_tx:0, outstanding_read_tx:0} +# UVM_INFO ../../src/dv/hdl_top/axi4_master_agent_bfm/axi4_master_driver_bfm.sv(119) @ 710: reporter [AXI4_MASTER_DRIVER_BFM] DRIVING_WRITE_ADDRESS_CHANNEL +# UVM_INFO ../../src/dv/hdl_top/axi4_master_agent_bfm/axi4_master_driver_bfm.sv(134) @ 710: reporter [AXI4_MASTER_DRIVER_BFM] detect_awready = 1 +# UVM_INFO ../../src/dv/hdl_top/axi4_master_agent_bfm/axi4_master_driver_bfm.sv(142) @ 730: reporter [AXI4_MASTER_DRIVER_BFM] After_loop_of_Detecting_awready = 1, awvalid = 1 +# UVM_INFO ../../src/dv/hdl_top/axi4_master_agent_bfm/axi4_master_driver_bfm.sv(153) @ 730: reporter [AXI4_MASTER_DRIVER_BFM] data_write_packet= +# '{awid:0, awaddr:437264404, awlen:0, awsize:2, awburst:1, awlock:0, awcache:0, awqos:0, awregion:0, awuser:0, awprot:0, awvalid:0, awready:0, wdata:'{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, wstrb:'{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, wuser:0, wlast:0, bid:0, bresp:0, buser:0, bvalid:0, tx_type:0, wait_count_write_address_channel:1, wait_count_write_data_channel:0, wait_count_write_response_channel:0, outstanding_write_tx:0, no_of_wait_states:0} +# UVM_INFO ../../src/dv/hdl_top/axi4_master_agent_bfm/axi4_master_driver_bfm.sv(154) @ 730: reporter [AXI4_MASTER_DRIVER_BFM] cfg_packet= +# '{min_address:0, max_address:0, wait_count_write_address_channel:0, wait_count_write_data_channel:0, wait_count_write_response_channel:0, wait_count_read_address_channel:0, wait_count_read_data_channel:0, outstanding_write_tx:0, outstanding_read_tx:0} +# UVM_INFO ../../src/dv/hdl_top/axi4_master_agent_bfm/axi4_master_driver_bfm.sv(155) @ 730: reporter [AXI4_MASTER_DRIVER_BFM] DRIVE TO WRITE DATA CHANNEL +# UVM_INFO ../../src/dv/hdl_top/axi4_master_agent_bfm/axi4_master_monitor_bfm.sv(102) @ 730: reporter [FROM MASTER MON BFM] after while loop ....... +# UVM_INFO ../../src/dv/hdl_top/axi4_master_agent_bfm/axi4_master_monitor_bfm.sv(112) @ 730: reporter [FROM MASTER MON BFM] datapacket ='{awid:0, awaddr:437264404, awlen:0, awsize:2, awburst:1, awlock:0, awcache:0, awqos:0, awregion:0, awuser:0, awprot:0, awvalid:0, awready:0, wdata:'{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, wstrb:'{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, wuser:0, wlast:0, bid:0, bresp:0, buser:0, bvalid:0, tx_type:0, wait_count_write_address_channel:0, wait_count_write_data_channel:0, wait_count_write_response_channel:0, outstanding_write_tx:0, no_of_wait_states:0} +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(198) @ 730: reporter [axi4_master_seq_item_conv_class] ---------------------------------------------------------------------- +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(204) @ 730: reporter [axi4_master_seq_item_conv_class] After converting awid = 0000000000000000 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(207) @ 730: reporter [axi4_master_seq_item_conv_class] After converting awlen = 00000000 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(210) @ 730: reporter [axi4_master_seq_item_conv_class] After randomizing awsize = 010 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(213) @ 730: reporter [axi4_master_seq_item_conv_class] After converting awburst = 01 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(216) @ 730: reporter [axi4_master_seq_item_conv_class] After converting awlock = 0 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(219) @ 730: reporter [axi4_master_seq_item_conv_class] After randomizing awcache = 0000 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(222) @ 730: reporter [axi4_master_seq_item_conv_class] After randomizing awprot = 000 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(225) @ 730: reporter [axi4_master_seq_item_conv_class] After converting awaddr = 1a102014 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(228) @ 730: reporter [axi4_master_seq_item_conv_class] After converting awqos = 0 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(231) @ 730: reporter [axi4_master_seq_item_conv_class] After converting wait_count_write_address_channel = 0 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(248) @ 730: reporter [axi4_master_seq_item_conv_class] After converting wlast = 0 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(251) @ 730: reporter [axi4_master_seq_item_conv_class] After converting wuser = 0 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(254) @ 730: reporter [axi4_master_seq_item_conv_class] After converting wait_count_write_data_channel = 0 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(257) @ 730: reporter [axi4_master_seq_item_conv_class] After converting bid = 0000000000000000 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(260) @ 730: reporter [axi4_master_seq_item_conv_class] After converting bresp = 00 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(263) @ 730: reporter [axi4_master_seq_item_conv_class] After converting wait_count_write_response_channel = 0 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_monitor_proxy.sv(159) @ 730: uvm_test_top.pulpino_spi_master_subsystem_env.axi4_master_agent.axi4_master_mon_proxy_h [axi4_master_monitor_proxy] Packet received from axi4_write_address clone packet is +# ----------------------------------------------------------------------------------- +# Name Type Size Value +# ----------------------------------------------------------------------------------- +# axi4_master_tx axi4_master_tx - @2569 +# tx_type string 5 WRITE +# awid string 6 AWID_0 +# awaddr integral 32 'h1a102014 +# awlen integral 8 'd0 +# awsize string 13 WRITE_4_BYTES +# awburst string 10 WRITE_INCR +# awlock string 19 WRITE_NORMAL_ACCESS +# awcache string 16 WRITE_BUFFERABLE +# awprot string 24 WRITE_NORMAL_SECURE_DATA +# awqos integral 4 'h0 +# wait_count_write_address_channel integral 32 'h0 +# wait_count_write_data_channel integral 32 'h0 +# bid string 5 BID_0 +# bresp string 10 WRITE_OKAY +# no_of_wait_states integral 32 'd0 +# wait_count_write_response_channel integral 32 'h0 +# transfer_type string 14 BLOCKING_WRITE +# ----------------------------------------------------------------------------------- +# +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_coverage.sv(223) @ 730: uvm_test_top.pulpino_spi_master_subsystem_env.axi4_master_agent.axi4_master_cov_h [axi4_master_coverage] Before calling SAMPLE METHOD +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_coverage.sv(227) @ 730: uvm_test_top.pulpino_spi_master_subsystem_env.axi4_master_agent.axi4_master_cov_h [axi4_master_coverage] After calling SAMPLE METHOD +# UVM_INFO ../../src/dv/hvl_top/env//axi4_master_collector.sv(60) @ 730: uvm_test_top.pulpino_spi_master_subsystem_env.axi4_master_coll_h [axi4_master_collector] Req print = ----------------------------------------------------------------------------------- +# Name Type Size Value +# ----------------------------------------------------------------------------------- +# axi4_master_tx axi4_master_tx - @2569 +# tx_type string 5 WRITE +# awid string 6 AWID_0 +# awaddr integral 32 'h1a102014 +# awlen integral 8 'd0 +# awsize string 13 WRITE_4_BYTES +# awburst string 10 WRITE_INCR +# awlock string 19 WRITE_NORMAL_ACCESS +# awcache string 16 WRITE_BUFFERABLE +# awprot string 24 WRITE_NORMAL_SECURE_DATA +# awqos integral 4 'h0 +# wait_count_write_address_channel integral 32 'h0 +# wait_count_write_data_channel integral 32 'h0 +# bid string 5 BID_0 +# bresp string 10 WRITE_OKAY +# no_of_wait_states integral 32 'd0 +# wait_count_write_response_channel integral 32 'h0 +# transfer_type string 14 BLOCKING_WRITE +# ----------------------------------------------------------------------------------- +# +# UVM_INFO ../../src/dv/hvl_top/env//axi4_master_collector.sv(64) @ 730: uvm_test_top.pulpino_spi_master_subsystem_env.axi4_master_coll_h [axi4_master_collector] rg_name = SPIDUM +# UVM_INFO ../../src/dv/hvl_top/env//axi4_master_collector.sv(65) @ 730: uvm_test_top.pulpino_spi_master_subsystem_env.axi4_master_coll_h [axi4_master_collector] rg_address = 1a102014 +# UVM_INFO ../../src/dv/hvl_top/env//axi4_master_collector.sv(66) @ 730: uvm_test_top.pulpino_spi_master_subsystem_env.axi4_master_coll_h [axi4_master_collector] rg_data = 0 +# UVM_INFO ../../src/dv/hvl_top/env//axi4_master_collector.sv(67) @ 730: uvm_test_top.pulpino_spi_master_subsystem_env.axi4_master_coll_h [axi4_master_collector] map_name = spi_master_reg_block.SPI_MASTER_MAP_ABP_IF +# UVM_INFO ../../src/dv/hvl_top/env//axi4_master_collector.sv(133) @ 730: uvm_test_top.pulpino_spi_master_subsystem_env.axi4_master_coll_h [axi4_master_collector] dummy_wr_local = 0 +# UVM_INFO ../../src/dv/hvl_top/env//axi4_master_collector.sv(143) @ 730: uvm_test_top.pulpino_spi_master_subsystem_env.axi4_master_coll_h [axi4_master_collector] Inside DUMMY_WR--final_data=0 +# UVM_INFO ../../src/dv/hvl_top/env//axi4_master_collector.sv(145) @ 730: uvm_test_top.pulpino_spi_master_subsystem_env.axi4_master_coll_h [axi4_master_collector] dummy_wr_data = 0 +# UVM_INFO ../../src/dv/hvl_top/env//axi4_master_collector.sv(146) @ 730: uvm_test_top.pulpino_spi_master_subsystem_env.axi4_master_coll_h [axi4_master_collector] Inside TX_FIFO -flag=3 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_adapter.sv(118) @ 730: reporter [axi4_master_adapter] The converted bus2reg packet is ----------------------------------------------------------------------------------- +# Name Type Size Value +# ----------------------------------------------------------------------------------- +# axi4_master_tx axi4_master_tx - @2569 +# tx_type string 5 WRITE +# awid string 6 AWID_0 +# awaddr integral 32 'h1a102014 +# awlen integral 8 'd0 +# awsize string 13 WRITE_4_BYTES +# awburst string 10 WRITE_INCR +# awlock string 19 WRITE_NORMAL_ACCESS +# awcache string 16 WRITE_BUFFERABLE +# awprot string 24 WRITE_NORMAL_SECURE_DATA +# awqos integral 4 'h0 +# wait_count_write_address_channel integral 32 'h0 +# wait_count_write_data_channel integral 32 'h0 +# bid string 5 BID_0 +# bresp string 10 WRITE_OKAY +# no_of_wait_states integral 32 'd0 +# wait_count_write_response_channel integral 32 'h0 +# transfer_type string 14 BLOCKING_WRITE +# ----------------------------------------------------------------------------------- +# +# +# UVM_INFO verilog_src/uvm-1.1d/src/reg/uvm_reg_predictor.svh(221) @ 730: uvm_test_top.pulpino_spi_master_subsystem_env.axi4_reg_predictor_h [REG_PREDICT] Observed WRITE transaction to register spi_master_reg_block.SPIDUM: value='h0 : updated value = 'h0 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_adapter.sv(118) @ 730: reporter [axi4_master_adapter] The converted bus2reg packet is ----------------------------------------------------------------------------------- +# Name Type Size Value +# ----------------------------------------------------------------------------------- +# axi4_master_tx axi4_master_tx - @2569 +# tx_type string 5 WRITE +# awid string 6 AWID_0 +# awaddr integral 32 'h1a102014 +# awlen integral 8 'd0 +# awsize string 13 WRITE_4_BYTES +# awburst string 10 WRITE_INCR +# awlock string 19 WRITE_NORMAL_ACCESS +# awcache string 16 WRITE_BUFFERABLE +# awprot string 24 WRITE_NORMAL_SECURE_DATA +# awqos integral 4 'h0 +# wait_count_write_address_channel integral 32 'h0 +# wait_count_write_data_channel integral 32 'h0 +# bid string 5 BID_0 +# bresp string 10 WRITE_OKAY +# no_of_wait_states integral 32 'd0 +# wait_count_write_response_channel integral 32 'h0 +# transfer_type string 14 BLOCKING_WRITE +# ----------------------------------------------------------------------------------- +# +# +# UVM_INFO ../../src/dv/hvl_top/env//axi4_reg_predictor.sv(48) @ 730: uvm_test_top.pulpino_spi_master_subsystem_env.axi4_reg_predictor_h [axi4_reg_predictor] rg_data = {SPIDUM} 558 1 2577 @uvm_status_container@1 1 @spi_master_apb_if@1 null 32 32 { {@uvm_reg_map@1:1} } {@uvm_reg_field@19 @uvm_reg_field@18} 4 4 @semaphore@7 @18350080 {} 0 0 1 0 1 0 null @uvm_object_string_pool__3@6 32 1 @uvm_reg_field@18 @uvm_reg_field@19 {ref to covergroup #cg_vals#} {spi_master_apb_if__spidum} +# UVM_INFO ../../src/dv/hvl_top/env//axi4_reg_predictor.sv(49) @ 730: uvm_test_top.pulpino_spi_master_subsystem_env.axi4_reg_predictor_h [axi4_reg_predictor] rw_data = UVM_WRITE 437264404 0 0 0 UVM_IS_OK +# UVM_INFO ../../src/dv/hdl_top/axi4_master_agent_bfm/axi4_master_driver_bfm.sv(165) @ 750: reporter [AXI4_MASTER_DRIVER_BFM] DETECT_WRITE_DATA_WAIT_STATE +# UVM_INFO ../../src/dv/hdl_top/axi4_master_agent_bfm/axi4_master_driver_bfm.sv(176) @ 770: reporter [AXI4_MASTER_DRIVER_BFM] DEBUG_NA:WDATA[0]=0 +# UVM_INFO ../../src/dv/hdl_top/axi4_master_agent_bfm/axi4_master_driver_bfm.sv(181) @ 770: reporter [AXI4_MASTER_DRIVER_BFM] WRITE_DATA_COMP data_write_packet= +# '{awid:0, awaddr:437264404, awlen:0, awsize:2, awburst:1, awlock:0, awcache:0, awqos:0, awregion:0, awuser:0, awprot:0, awvalid:0, awready:0, wdata:'{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, wstrb:'{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, wuser:0, wlast:0, bid:0, bresp:0, buser:0, bvalid:0, tx_type:0, wait_count_write_address_channel:1, wait_count_write_data_channel:0, wait_count_write_response_channel:0, outstanding_write_tx:0, no_of_wait_states:0} +# UVM_INFO ../../src/dv/hdl_top/axi4_master_agent_bfm/axi4_master_driver_bfm.sv(190) @ 770: reporter [AXI4_MASTER_DRIVER_BFM] WRITE_RESP data_write_packet= +# '{awid:0, awaddr:437264404, awlen:0, awsize:2, awburst:1, awlock:0, awcache:0, awqos:0, awregion:0, awuser:0, awprot:0, awvalid:0, awready:0, wdata:'{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, wstrb:'{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, wuser:0, wlast:0, bid:0, bresp:0, buser:0, bvalid:0, tx_type:0, wait_count_write_address_channel:1, wait_count_write_data_channel:0, wait_count_write_response_channel:0, outstanding_write_tx:0, no_of_wait_states:0} +# UVM_INFO ../../src/dv/hdl_top/axi4_master_agent_bfm/axi4_master_driver_bfm.sv(191) @ 770: reporter [AXI4_MASTER_DRIVER_BFM] cfg_packet= +# '{min_address:0, max_address:0, wait_count_write_address_channel:0, wait_count_write_data_channel:0, wait_count_write_response_channel:0, wait_count_read_address_channel:0, wait_count_read_data_channel:0, outstanding_write_tx:0, outstanding_read_tx:0} +# UVM_INFO ../../src/dv/hdl_top/axi4_master_agent_bfm/axi4_master_driver_bfm.sv(192) @ 770: reporter [AXI4_MASTER_DRIVER_BFM] DRIVE TO WRITE RESPONSE CHANNEL +# UVM_INFO ../../src/dv/hdl_top/axi4_master_agent_bfm/axi4_master_monitor_bfm.sv(128) @ 770: reporter [FROM MASTER MON BFM] After while loop write data...... +# UVM_INFO ../../src/dv/hdl_top/axi4_master_agent_bfm/axi4_master_monitor_bfm.sv(135) @ 770: reporter [FROM MASTER MON BFM write data] write datapacket wdata[0] = 'h0 +# UVM_INFO ../../src/dv/hdl_top/axi4_master_agent_bfm/axi4_master_monitor_bfm.sv(136) @ 770: reporter [FROM MASTER MON BFM write data] write datapacket wstrb[0] = 'h0 +# UVM_INFO ../../src/dv/hdl_top/axi4_master_agent_bfm/axi4_master_monitor_bfm.sv(138) @ 770: reporter [FROM MASTER MON BFM write data] Inside wlast write datapacket ='{awid:0, awaddr:0, awlen:0, awsize:0, awburst:0, awlock:0, awcache:0, awqos:0, awregion:0, awuser:0, awprot:0, awvalid:0, awready:0, wdata:'{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, wstrb:'{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, wuser:0, wlast:1, bid:0, bresp:0, buser:0, bvalid:0, tx_type:0, wait_count_write_address_channel:0, wait_count_write_data_channel:0, wait_count_write_response_channel:0, outstanding_write_tx:0, no_of_wait_states:0} +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_monitor_proxy.sv(182) @ 770: uvm_test_top.pulpino_spi_master_subsystem_env.axi4_master_agent.axi4_master_mon_proxy_h [axi4_master_monitor_proxy] ADDR_Packet received from fifo is +# ----------------------------------------------------------------------------------- +# Name Type Size Value +# ----------------------------------------------------------------------------------- +# axi4_master_tx axi4_master_tx - @2565 +# tx_type string 5 WRITE +# awid string 6 AWID_0 +# awaddr integral 32 'h1a102014 +# awlen integral 8 'd0 +# awsize string 13 WRITE_4_BYTES +# awburst string 10 WRITE_INCR +# awlock string 19 WRITE_NORMAL_ACCESS +# awcache string 16 WRITE_BUFFERABLE +# awprot string 24 WRITE_NORMAL_SECURE_DATA +# awqos integral 4 'h0 +# wait_count_write_address_channel integral 32 'h0 +# wait_count_write_data_channel integral 32 'h0 +# bid string 5 BID_0 +# bresp string 10 WRITE_OKAY +# no_of_wait_states integral 32 'd0 +# wait_count_write_response_channel integral 32 'h0 +# transfer_type string 14 BLOCKING_WRITE +# ----------------------------------------------------------------------------------- +# +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(337) @ 770: reporter [axi4_master_seq_item_conv_class] ---------------------------------------------------------------------- +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(370) @ 770: reporter [axi4_master_seq_item_conv_class] After converting = ----------------------------------------------------------------------------------- +# Name Type Size Value +# ----------------------------------------------------------------------------------- +# axi4_master_tx axi4_master_tx - @2577 +# tx_type string 5 WRITE +# awid string 6 AWID_0 +# awaddr integral 32 'h1a102014 +# awlen integral 8 'd0 +# awsize string 13 WRITE_4_BYTES +# awburst string 10 WRITE_INCR +# awlock string 19 WRITE_NORMAL_ACCESS +# awcache string 16 WRITE_BUFFERABLE +# awprot string 24 WRITE_NORMAL_SECURE_DATA +# awqos integral 4 'h0 +# wait_count_write_address_channel integral 32 'h0 +# wait_count_write_data_channel integral 32 'h0 +# bid string 5 BID_0 +# bresp string 10 WRITE_OKAY +# no_of_wait_states integral 32 'd0 +# wait_count_write_response_channel integral 32 'h0 +# transfer_type string 14 BLOCKING_WRITE +# ----------------------------------------------------------------------------------- +# +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_monitor_proxy.sv(191) @ 770: uvm_test_top.pulpino_spi_master_subsystem_env.axi4_master_agent.axi4_master_mon_proxy_h [axi4_master_monitor_proxy] Packet received from axi4_write_data clone packet is +# ----------------------------------------------------------------------------------- +# Name Type Size Value +# ----------------------------------------------------------------------------------- +# axi4_master_tx axi4_master_tx - @2581 +# tx_type string 5 WRITE +# awid string 6 AWID_0 +# awaddr integral 32 'h1a102014 +# awlen integral 8 'd0 +# awsize string 13 WRITE_4_BYTES +# awburst string 10 WRITE_INCR +# awlock string 19 WRITE_NORMAL_ACCESS +# awcache string 16 WRITE_BUFFERABLE +# awprot string 24 WRITE_NORMAL_SECURE_DATA +# awqos integral 4 'h0 +# wait_count_write_address_channel integral 32 'h0 +# wait_count_write_data_channel integral 32 'h0 +# bid string 5 BID_0 +# bresp string 10 WRITE_OKAY +# no_of_wait_states integral 32 'd0 +# wait_count_write_response_channel integral 32 'h0 +# transfer_type string 14 BLOCKING_WRITE +# ----------------------------------------------------------------------------------- +# +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_coverage.sv(223) @ 770: uvm_test_top.pulpino_spi_master_subsystem_env.axi4_master_agent.axi4_master_cov_h [axi4_master_coverage] Before calling SAMPLE METHOD +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_coverage.sv(227) @ 770: uvm_test_top.pulpino_spi_master_subsystem_env.axi4_master_agent.axi4_master_cov_h [axi4_master_coverage] After calling SAMPLE METHOD +# UVM_INFO ../../src/dv/hdl_top/axi4_master_agent_bfm/axi4_master_driver_bfm.sv(210) @ 830: reporter [AXI4_MASTER_DRIVER_BFM] CHECKING WRITE RESPONSE :: '{awid:0, awaddr:437264404, awlen:0, awsize:2, awburst:1, awlock:0, awcache:0, awqos:0, awregion:0, awuser:0, awprot:0, awvalid:0, awready:0, wdata:'{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, wstrb:'{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, wuser:0, wlast:0, bid:0, bresp:0, buser:0, bvalid:1, tx_type:0, wait_count_write_address_channel:1, wait_count_write_data_channel:0, wait_count_write_response_channel:0, outstanding_write_tx:0, no_of_wait_states:0} +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(198) @ 850: reporter [axi4_master_seq_item_conv_class] ---------------------------------------------------------------------- +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(204) @ 850: reporter [axi4_master_seq_item_conv_class] After converting awid = 0000000000000000 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(207) @ 850: reporter [axi4_master_seq_item_conv_class] After converting awlen = 00000000 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(210) @ 850: reporter [axi4_master_seq_item_conv_class] After randomizing awsize = 010 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(213) @ 850: reporter [axi4_master_seq_item_conv_class] After converting awburst = 01 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(216) @ 850: reporter [axi4_master_seq_item_conv_class] After converting awlock = 0 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(219) @ 850: reporter [axi4_master_seq_item_conv_class] After randomizing awcache = 0000 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(222) @ 850: reporter [axi4_master_seq_item_conv_class] After randomizing awprot = 000 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(225) @ 850: reporter [axi4_master_seq_item_conv_class] After converting awaddr = 1a102014 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(228) @ 850: reporter [axi4_master_seq_item_conv_class] After converting awqos = 0 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(231) @ 850: reporter [axi4_master_seq_item_conv_class] After converting wait_count_write_address_channel = 1 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(248) @ 850: reporter [axi4_master_seq_item_conv_class] After converting wlast = 0 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(251) @ 850: reporter [axi4_master_seq_item_conv_class] After converting wuser = 0 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(254) @ 850: reporter [axi4_master_seq_item_conv_class] After converting wait_count_write_data_channel = 0 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(257) @ 850: reporter [axi4_master_seq_item_conv_class] After converting bid = 0000000000000000 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(260) @ 850: reporter [axi4_master_seq_item_conv_class] After converting bresp = 00 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(263) @ 850: reporter [axi4_master_seq_item_conv_class] After converting wait_count_write_response_channel = 0 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_driver_proxy.sv(202) @ 850: uvm_test_top.pulpino_spi_master_subsystem_env.axi4_master_agent.axi4_master_drv_proxy_h [axi4_master_driver_proxy] WRITE_TASK::Response Received_req_write_packet = +# ----------------------------------------------------------------------------------- +# Name Type Size Value +# ----------------------------------------------------------------------------------- +# axi4_master_tx axi4_master_tx - @2585 +# tx_type string 5 WRITE +# awid string 6 AWID_0 +# awaddr integral 32 'h1a102014 +# awlen integral 8 'd0 +# awsize string 13 WRITE_4_BYTES +# awburst string 10 WRITE_INCR +# awlock string 19 WRITE_NORMAL_ACCESS +# awcache string 16 WRITE_BUFFERABLE +# awprot string 24 WRITE_NORMAL_SECURE_DATA +# awqos integral 4 'h0 +# wait_count_write_address_channel integral 32 'h1 +# wait_count_write_data_channel integral 32 'h0 +# bid string 5 BID_0 +# bresp string 10 WRITE_OKAY +# no_of_wait_states integral 32 'd0 +# wait_count_write_response_channel integral 32 'h0 +# transfer_type string 14 BLOCKING_WRITE +# ----------------------------------------------------------------------------------- +# +# UVM_INFO ../../src/dv/hdl_top/axi4_master_agent_bfm/axi4_master_monitor_bfm.sv(158) @ 850: reporter [FROM MASTER MON BFM::WRITE RESPONSE] WRITE RESPONSE PACKET: +# '{awid:0, awaddr:0, awlen:0, awsize:0, awburst:0, awlock:0, awcache:0, awqos:0, awregion:0, awuser:0, awprot:0, awvalid:0, awready:0, wdata:'{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, wstrb:'{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, wuser:0, wlast:0, bid:0, bresp:0, buser:0, bvalid:0, tx_type:0, wait_count_write_address_channel:0, wait_count_write_data_channel:0, wait_count_write_response_channel:0, outstanding_write_tx:0, no_of_wait_states:0} +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(198) @ 850: reporter [axi4_master_seq_item_conv_class] ---------------------------------------------------------------------- +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(204) @ 850: reporter [axi4_master_seq_item_conv_class] After converting awid = 0000000000000000 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(207) @ 850: reporter [axi4_master_seq_item_conv_class] After converting awlen = 00000000 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(210) @ 850: reporter [axi4_master_seq_item_conv_class] After randomizing awsize = 000 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(213) @ 850: reporter [axi4_master_seq_item_conv_class] After converting awburst = 00 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(216) @ 850: reporter [axi4_master_seq_item_conv_class] After converting awlock = 0 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(219) @ 850: reporter [axi4_master_seq_item_conv_class] After randomizing awcache = 0000 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(222) @ 850: reporter [axi4_master_seq_item_conv_class] After randomizing awprot = 000 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(225) @ 850: reporter [axi4_master_seq_item_conv_class] After converting awaddr = 0 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(228) @ 850: reporter [axi4_master_seq_item_conv_class] After converting awqos = 0 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(231) @ 850: reporter [axi4_master_seq_item_conv_class] After converting wait_count_write_address_channel = 0 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(248) @ 850: reporter [axi4_master_seq_item_conv_class] After converting wlast = 0 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(251) @ 850: reporter [axi4_master_seq_item_conv_class] After converting wuser = 0 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(254) @ 850: reporter [axi4_master_seq_item_conv_class] After converting wait_count_write_data_channel = 0 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(257) @ 850: reporter [axi4_master_seq_item_conv_class] After converting bid = 0000000000000000 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(260) @ 850: reporter [axi4_master_seq_item_conv_class] After converting bresp = 00 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(263) @ 850: reporter [axi4_master_seq_item_conv_class] After converting wait_count_write_response_channel = 0 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(384) @ 850: reporter [axi4_master_seq_item_conv_class] ---------------------------------------------------------------------- +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(417) @ 850: reporter [axi4_master_seq_item_conv_class] After converting = ----------------------------------------------------------------------------------- +# Name Type Size Value +# ----------------------------------------------------------------------------------- +# axi4_master_tx axi4_master_tx - @2593 +# tx_type string 5 WRITE +# awid string 6 AWID_0 +# awaddr integral 32 'h1a102014 +# awlen integral 8 'd0 +# awsize string 13 WRITE_4_BYTES +# awburst string 10 WRITE_INCR +# awlock string 19 WRITE_NORMAL_ACCESS +# awcache string 16 WRITE_BUFFERABLE +# awprot string 24 WRITE_NORMAL_SECURE_DATA +# awqos integral 4 'h0 +# wait_count_write_address_channel integral 32 'h0 +# wait_count_write_data_channel integral 32 'h0 +# bid string 5 BID_0 +# bresp string 10 WRITE_OKAY +# no_of_wait_states integral 32 'd0 +# wait_count_write_response_channel integral 32 'h0 +# transfer_type string 14 BLOCKING_WRITE +# ----------------------------------------------------------------------------------- +# +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_monitor_proxy.sv(220) @ 850: uvm_test_top.pulpino_spi_master_subsystem_env.axi4_master_agent.axi4_master_mon_proxy_h [axi4_master_monitor_proxy] Packet received from axi4_write_response clone packet is +# ----------------------------------------------------------------------------------- +# Name Type Size Value +# ----------------------------------------------------------------------------------- +# axi4_master_tx axi4_master_tx - @2597 +# tx_type string 5 WRITE +# awid string 6 AWID_0 +# awaddr integral 32 'h1a102014 +# awlen integral 8 'd0 +# awsize string 13 WRITE_4_BYTES +# awburst string 10 WRITE_INCR +# awlock string 19 WRITE_NORMAL_ACCESS +# awcache string 16 WRITE_BUFFERABLE +# awprot string 24 WRITE_NORMAL_SECURE_DATA +# awqos integral 4 'h0 +# wait_count_write_address_channel integral 32 'h0 +# wait_count_write_data_channel integral 32 'h0 +# bid string 5 BID_0 +# bresp string 10 WRITE_OKAY +# no_of_wait_states integral 32 'd0 +# wait_count_write_response_channel integral 32 'h0 +# transfer_type string 14 BLOCKING_WRITE +# ----------------------------------------------------------------------------------- +# +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_coverage.sv(223) @ 850: uvm_test_top.pulpino_spi_master_subsystem_env.axi4_master_agent.axi4_master_cov_h [axi4_master_coverage] Before calling SAMPLE METHOD +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_coverage.sv(227) @ 850: uvm_test_top.pulpino_spi_master_subsystem_env.axi4_master_agent.axi4_master_cov_h [axi4_master_coverage] After calling SAMPLE METHOD +# UVM_INFO ../../src/dv/hdl_top/axi4_master_agent_bfm/axi4_master_monitor_bfm.sv(151) @ 850: reporter [FROM MASTER MON BFM] AFTER WHILE LOOP OF WRITE RESPONSE +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_adapter.sv(118) @ 850: reporter [axi4_master_adapter] The converted bus2reg packet is ----------------------------------------------------------------------------------- +# Name Type Size Value +# ----------------------------------------------------------------------------------- +# axi4_master_tx axi4_master_tx - @2561 +# tx_type string 5 WRITE +# awid string 6 AWID_0 +# awaddr integral 32 'h1a102014 +# awlen integral 8 'd0 +# awsize string 13 WRITE_4_BYTES +# awburst string 10 WRITE_INCR +# awlock string 19 WRITE_NORMAL_ACCESS +# awcache string 16 WRITE_BUFFERABLE +# awprot string 24 WRITE_NORMAL_SECURE_DATA +# awqos integral 4 'h0 +# wait_count_write_address_channel integral 32 'h0 +# wdata[0] integral 64 'h0 +# wait_count_write_data_channel integral 32 'h0 +# bid string 5 BID_0 +# bresp string 10 WRITE_OKAY +# no_of_wait_states integral 32 'd0 +# wait_count_write_response_channel integral 32 'h0 +# transfer_type string 14 BLOCKING_WRITE +# ----------------------------------------------------------------------------------- +# +# +# UVM_INFO @ 850: reporter [RegModel] Wrote register via map spi_master_reg_block.SPI_MASTER_MAP_ABP_IF: spi_master_reg_block.SPIDUM=0x0 +# UVM_INFO ../../src/dv/hvl_top/test/sequences/master_sequences/reg_sequences//axi4_master_basic_write_read_reg_seq.sv(252) @ 850: uvm_test_top.pulpino_spi_master_subsystem_env.axi4_master_agent.axi4_master_write_seqr_h@@axi4_master_basic_write_read_reg_seq_h [axi4_master_basic_write_read_reg_seq] Write :: Register tx_fifo = fffff01a +# UVM_INFO ../../src/dv/hvl_top/test/sequences/master_sequences/reg_sequences//axi4_master_basic_write_read_reg_seq.sv(260) @ 850: uvm_test_top.pulpino_spi_master_subsystem_env.axi4_master_agent.axi4_master_write_seqr_h@@axi4_master_basic_write_read_reg_seq_h [TX_FIFO_SEQ] WRITE:: REGISTER : spi_master_reg_block.TXFIFO, DATA = 32'hfffff01a +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_adapter.sv(53) @ 850: reporter [MSHA_DEBUG] +# rw.address = 1a102018 rw.data = fffff01a +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_adapter.sv(73) @ 850: reporter [axi4_master_adapter] The converted reg2bus packet is ----------------------------------------------------------------------------------- +# Name Type Size Value +# ----------------------------------------------------------------------------------- +# axi4_master_tx axi4_master_tx - @2605 +# tx_type string 5 WRITE +# awid string 6 AWID_0 +# awaddr integral 32 'h1a102018 +# awlen integral 8 'd0 +# awsize string 13 WRITE_4_BYTES +# awburst string 10 WRITE_INCR +# awlock string 19 WRITE_NORMAL_ACCESS +# awcache string 16 WRITE_BUFFERABLE +# awprot string 24 WRITE_NORMAL_SECURE_DATA +# awqos integral 4 'h0 +# wait_count_write_address_channel integral 32 'h0 +# wdata[0] integral 64 'hfffff01a +# wait_count_write_data_channel integral 32 'h0 +# bid string 5 BID_0 +# bresp string 10 WRITE_OKAY +# no_of_wait_states integral 32 'd0 +# wait_count_write_response_channel integral 32 'h0 +# transfer_type string 14 BLOCKING_WRITE +# ----------------------------------------------------------------------------------- +# +# +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_driver_proxy.sv(167) @ 850: uvm_test_top.pulpino_spi_master_subsystem_env.axi4_master_agent.axi4_master_drv_proxy_h [axi4_master_driver_proxy] WRITE_TASK::Before Sending_req_write_packet = +# ----------------------------------------------------------------------------------- +# Name Type Size Value +# ----------------------------------------------------------------------------------- +# axi4_master_tx axi4_master_tx - @2605 +# tx_type string 5 WRITE +# awid string 6 AWID_0 +# awaddr integral 32 'h1a102018 +# awlen integral 8 'd0 +# awsize string 13 WRITE_4_BYTES +# awburst string 10 WRITE_INCR +# awlock string 19 WRITE_NORMAL_ACCESS +# awcache string 16 WRITE_BUFFERABLE +# awprot string 24 WRITE_NORMAL_SECURE_DATA +# awqos integral 4 'h0 +# wait_count_write_address_channel integral 32 'h0 +# wdata[0] integral 64 'hfffff01a +# wait_count_write_data_channel integral 32 'h0 +# bid string 5 BID_0 +# bresp string 10 WRITE_OKAY +# no_of_wait_states integral 32 'd0 +# wait_count_write_response_channel integral 32 'h0 +# transfer_type string 14 BLOCKING_WRITE +# ----------------------------------------------------------------------------------- +# +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(47) @ 850: reporter [axi4_master_seq_item_conv_class] ---------------------------------------------------------------------- +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(49) @ 850: reporter [axi4_master_seq_item_conv_class] After converting awid = 0000 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(52) @ 850: reporter [axi4_master_seq_item_conv_class] After converting awlen = 00000000 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(55) @ 850: reporter [axi4_master_seq_item_conv_class] After randomizing awsize = 010 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(58) @ 850: reporter [axi4_master_seq_item_conv_class] After converting awburst = 01 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(61) @ 850: reporter [axi4_master_seq_item_conv_class] After converting awlock = 0 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(64) @ 850: reporter [axi4_master_seq_item_conv_class] After randomizing awcache = 0000 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(67) @ 850: reporter [axi4_master_seq_item_conv_class] After randomizing awprot = 000 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(70) @ 850: reporter [axi4_master_seq_item_conv_class] After converting bid = 0000 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(73) @ 850: reporter [axi4_master_seq_item_conv_class] After converting bresp = 00 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(76) @ 850: reporter [axi4_master_seq_item_conv_class] After converting buser = 0 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(81) @ 850: reporter [axi4_master_seq_item_conv_class] After converting awaddr = 1a102018 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(84) @ 850: reporter [axi4_master_seq_item_conv_class] After converting awqos = 0 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(89) @ 850: reporter [axi4_master_seq_item_conv_class] After converting wdata = 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 4294963226 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(96) @ 850: reporter [axi4_master_seq_item_conv_class] After converting wstrb = 0 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(101) @ 850: reporter [axi4_master_seq_item_conv_class] After converting wlast = 0 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(104) @ 850: reporter [axi4_master_seq_item_conv_class] After converting wuser = 0 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(107) @ 850: reporter [axi4_master_seq_item_conv_class] After converting no_wait_states = 0 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_driver_proxy.sv(192) @ 850: uvm_test_top.pulpino_spi_master_subsystem_env.axi4_master_agent.axi4_master_drv_proxy_h [axi4_master_driver_proxy] WRITE_TASK::Checking transfer type = BLOCKING_WRITE +# UVM_INFO ../../src/dv/hdl_top/axi4_master_agent_bfm/axi4_master_driver_bfm.sv(117) @ 870: reporter [AXI4_MASTER_DRIVER_BFM] data_write_packet= +# '{awid:0, awaddr:437264408, awlen:0, awsize:2, awburst:1, awlock:0, awcache:0, awqos:0, awregion:0, awuser:0, awprot:0, awvalid:0, awready:0, wdata:'{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 4294963226}, wstrb:'{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, wuser:0, wlast:0, bid:0, bresp:0, buser:0, bvalid:0, tx_type:0, wait_count_write_address_channel:0, wait_count_write_data_channel:0, wait_count_write_response_channel:0, outstanding_write_tx:0, no_of_wait_states:0} +# UVM_INFO ../../src/dv/hdl_top/axi4_master_agent_bfm/axi4_master_driver_bfm.sv(118) @ 870: reporter [AXI4_MASTER_DRIVER_BFM] cfg_packet= +# '{min_address:0, max_address:0, wait_count_write_address_channel:0, wait_count_write_data_channel:0, wait_count_write_response_channel:0, wait_count_read_address_channel:0, wait_count_read_data_channel:0, outstanding_write_tx:0, outstanding_read_tx:0} +# UVM_INFO ../../src/dv/hdl_top/axi4_master_agent_bfm/axi4_master_driver_bfm.sv(119) @ 870: reporter [AXI4_MASTER_DRIVER_BFM] DRIVING_WRITE_ADDRESS_CHANNEL +# UVM_INFO ../../src/dv/hdl_top/axi4_master_agent_bfm/axi4_master_driver_bfm.sv(134) @ 870: reporter [AXI4_MASTER_DRIVER_BFM] detect_awready = 1 +# UVM_INFO ../../src/dv/hdl_top/axi4_master_agent_bfm/axi4_master_driver_bfm.sv(142) @ 890: reporter [AXI4_MASTER_DRIVER_BFM] After_loop_of_Detecting_awready = 1, awvalid = 1 +# UVM_INFO ../../src/dv/hdl_top/axi4_master_agent_bfm/axi4_master_driver_bfm.sv(153) @ 890: reporter [AXI4_MASTER_DRIVER_BFM] data_write_packet= +# '{awid:0, awaddr:437264408, awlen:0, awsize:2, awburst:1, awlock:0, awcache:0, awqos:0, awregion:0, awuser:0, awprot:0, awvalid:0, awready:0, wdata:'{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 4294963226}, wstrb:'{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, wuser:0, wlast:0, bid:0, bresp:0, buser:0, bvalid:0, tx_type:0, wait_count_write_address_channel:1, wait_count_write_data_channel:0, wait_count_write_response_channel:0, outstanding_write_tx:0, no_of_wait_states:0} +# UVM_INFO ../../src/dv/hdl_top/axi4_master_agent_bfm/axi4_master_driver_bfm.sv(154) @ 890: reporter [AXI4_MASTER_DRIVER_BFM] cfg_packet= +# '{min_address:0, max_address:0, wait_count_write_address_channel:0, wait_count_write_data_channel:0, wait_count_write_response_channel:0, wait_count_read_address_channel:0, wait_count_read_data_channel:0, outstanding_write_tx:0, outstanding_read_tx:0} +# UVM_INFO ../../src/dv/hdl_top/axi4_master_agent_bfm/axi4_master_driver_bfm.sv(155) @ 890: reporter [AXI4_MASTER_DRIVER_BFM] DRIVE TO WRITE DATA CHANNEL +# UVM_INFO ../../src/dv/hdl_top/axi4_master_agent_bfm/axi4_master_monitor_bfm.sv(102) @ 890: reporter [FROM MASTER MON BFM] after while loop ....... +# UVM_INFO ../../src/dv/hdl_top/axi4_master_agent_bfm/axi4_master_monitor_bfm.sv(112) @ 890: reporter [FROM MASTER MON BFM] datapacket ='{awid:0, awaddr:437264408, awlen:0, awsize:2, awburst:1, awlock:0, awcache:0, awqos:0, awregion:0, awuser:0, awprot:0, awvalid:0, awready:0, wdata:'{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, wstrb:'{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, wuser:0, wlast:0, bid:0, bresp:0, buser:0, bvalid:0, tx_type:0, wait_count_write_address_channel:0, wait_count_write_data_channel:0, wait_count_write_response_channel:0, outstanding_write_tx:0, no_of_wait_states:0} +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(198) @ 890: reporter [axi4_master_seq_item_conv_class] ---------------------------------------------------------------------- +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(204) @ 890: reporter [axi4_master_seq_item_conv_class] After converting awid = 0000000000000000 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(207) @ 890: reporter [axi4_master_seq_item_conv_class] After converting awlen = 00000000 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(210) @ 890: reporter [axi4_master_seq_item_conv_class] After randomizing awsize = 010 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(213) @ 890: reporter [axi4_master_seq_item_conv_class] After converting awburst = 01 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(216) @ 890: reporter [axi4_master_seq_item_conv_class] After converting awlock = 0 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(219) @ 890: reporter [axi4_master_seq_item_conv_class] After randomizing awcache = 0000 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(222) @ 890: reporter [axi4_master_seq_item_conv_class] After randomizing awprot = 000 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(225) @ 890: reporter [axi4_master_seq_item_conv_class] After converting awaddr = 1a102018 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(228) @ 890: reporter [axi4_master_seq_item_conv_class] After converting awqos = 0 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(231) @ 890: reporter [axi4_master_seq_item_conv_class] After converting wait_count_write_address_channel = 0 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(248) @ 890: reporter [axi4_master_seq_item_conv_class] After converting wlast = 0 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(251) @ 890: reporter [axi4_master_seq_item_conv_class] After converting wuser = 0 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(254) @ 890: reporter [axi4_master_seq_item_conv_class] After converting wait_count_write_data_channel = 0 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(257) @ 890: reporter [axi4_master_seq_item_conv_class] After converting bid = 0000000000000000 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(260) @ 890: reporter [axi4_master_seq_item_conv_class] After converting bresp = 00 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(263) @ 890: reporter [axi4_master_seq_item_conv_class] After converting wait_count_write_response_channel = 0 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_monitor_proxy.sv(159) @ 890: uvm_test_top.pulpino_spi_master_subsystem_env.axi4_master_agent.axi4_master_mon_proxy_h [axi4_master_monitor_proxy] Packet received from axi4_write_address clone packet is +# ----------------------------------------------------------------------------------- +# Name Type Size Value +# ----------------------------------------------------------------------------------- +# axi4_master_tx axi4_master_tx - @2613 +# tx_type string 5 WRITE +# awid string 6 AWID_0 +# awaddr integral 32 'h1a102018 +# awlen integral 8 'd0 +# awsize string 13 WRITE_4_BYTES +# awburst string 10 WRITE_INCR +# awlock string 19 WRITE_NORMAL_ACCESS +# awcache string 16 WRITE_BUFFERABLE +# awprot string 24 WRITE_NORMAL_SECURE_DATA +# awqos integral 4 'h0 +# wait_count_write_address_channel integral 32 'h0 +# wait_count_write_data_channel integral 32 'h0 +# bid string 5 BID_0 +# bresp string 10 WRITE_OKAY +# no_of_wait_states integral 32 'd0 +# wait_count_write_response_channel integral 32 'h0 +# transfer_type string 14 BLOCKING_WRITE +# ----------------------------------------------------------------------------------- +# +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_coverage.sv(223) @ 890: uvm_test_top.pulpino_spi_master_subsystem_env.axi4_master_agent.axi4_master_cov_h [axi4_master_coverage] Before calling SAMPLE METHOD +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_coverage.sv(227) @ 890: uvm_test_top.pulpino_spi_master_subsystem_env.axi4_master_agent.axi4_master_cov_h [axi4_master_coverage] After calling SAMPLE METHOD +# UVM_INFO ../../src/dv/hvl_top/env//axi4_master_collector.sv(60) @ 890: uvm_test_top.pulpino_spi_master_subsystem_env.axi4_master_coll_h [axi4_master_collector] Req print = ----------------------------------------------------------------------------------- +# Name Type Size Value +# ----------------------------------------------------------------------------------- +# axi4_master_tx axi4_master_tx - @2613 +# tx_type string 5 WRITE +# awid string 6 AWID_0 +# awaddr integral 32 'h1a102018 +# awlen integral 8 'd0 +# awsize string 13 WRITE_4_BYTES +# awburst string 10 WRITE_INCR +# awlock string 19 WRITE_NORMAL_ACCESS +# awcache string 16 WRITE_BUFFERABLE +# awprot string 24 WRITE_NORMAL_SECURE_DATA +# awqos integral 4 'h0 +# wait_count_write_address_channel integral 32 'h0 +# wait_count_write_data_channel integral 32 'h0 +# bid string 5 BID_0 +# bresp string 10 WRITE_OKAY +# no_of_wait_states integral 32 'd0 +# wait_count_write_response_channel integral 32 'h0 +# transfer_type string 14 BLOCKING_WRITE +# ----------------------------------------------------------------------------------- +# +# UVM_INFO ../../src/dv/hvl_top/env//axi4_master_collector.sv(64) @ 890: uvm_test_top.pulpino_spi_master_subsystem_env.axi4_master_coll_h [axi4_master_collector] rg_name = TXFIFO +# UVM_INFO ../../src/dv/hvl_top/env//axi4_master_collector.sv(65) @ 890: uvm_test_top.pulpino_spi_master_subsystem_env.axi4_master_coll_h [axi4_master_collector] rg_address = 1a102018 +# UVM_INFO ../../src/dv/hvl_top/env//axi4_master_collector.sv(66) @ 890: uvm_test_top.pulpino_spi_master_subsystem_env.axi4_master_coll_h [axi4_master_collector] rg_data = fffff01a +# UVM_INFO ../../src/dv/hvl_top/env//axi4_master_collector.sv(67) @ 890: uvm_test_top.pulpino_spi_master_subsystem_env.axi4_master_coll_h [axi4_master_collector] map_name = spi_master_reg_block.SPI_MASTER_MAP_ABP_IF +# UVM_INFO ../../src/dv/hvl_top/env//axi4_master_collector.sv(153) @ 890: uvm_test_top.pulpino_spi_master_subsystem_env.axi4_master_coll_h [axi4_master_collector] mosi_data_local = fffff01a +# UVM_INFO ../../src/dv/hvl_top/env//axi4_master_collector.sv(154) @ 890: uvm_test_top.pulpino_spi_master_subsystem_env.axi4_master_coll_h [axi4_master_collector] spi_len[16:31] = 20 +# UVM_INFO ../../src/dv/hvl_top/env//axi4_master_collector.sv(160) @ 890: uvm_test_top.pulpino_spi_master_subsystem_env.axi4_master_coll_h [axi4_master_collector] mosi_data = fffff01a +# UVM_INFO ../../src/dv/hvl_top/env//axi4_master_collector.sv(161) @ 890: uvm_test_top.pulpino_spi_master_subsystem_env.axi4_master_coll_h [axi4_master_collector] Inside TX_FIFO -final_data=fffff01a +# UVM_INFO ../../src/dv/hvl_top/env//axi4_master_collector.sv(162) @ 890: uvm_test_top.pulpino_spi_master_subsystem_env.axi4_master_coll_h [axi4_master_collector] Inside TX_FIFO -flag=4 +# UVM_INFO ../../src/dv/hvl_top/env//axi4_master_collector.sv(166) @ 890: uvm_test_top.pulpino_spi_master_subsystem_env.axi4_master_coll_h [axi4_master_collector] final_data=fffff01a +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_adapter.sv(118) @ 890: reporter [axi4_master_adapter] The converted bus2reg packet is ----------------------------------------------------------------------------------- +# Name Type Size Value +# ----------------------------------------------------------------------------------- +# axi4_master_tx axi4_master_tx - @2613 +# tx_type string 5 WRITE +# awid string 6 AWID_0 +# awaddr integral 32 'h1a102018 +# awlen integral 8 'd0 +# awsize string 13 WRITE_4_BYTES +# awburst string 10 WRITE_INCR +# awlock string 19 WRITE_NORMAL_ACCESS +# awcache string 16 WRITE_BUFFERABLE +# awprot string 24 WRITE_NORMAL_SECURE_DATA +# awqos integral 4 'h0 +# wait_count_write_address_channel integral 32 'h0 +# wait_count_write_data_channel integral 32 'h0 +# bid string 5 BID_0 +# bresp string 10 WRITE_OKAY +# no_of_wait_states integral 32 'd0 +# wait_count_write_response_channel integral 32 'h0 +# transfer_type string 14 BLOCKING_WRITE +# ----------------------------------------------------------------------------------- +# +# +# UVM_INFO verilog_src/uvm-1.1d/src/reg/uvm_reg_predictor.svh(221) @ 890: uvm_test_top.pulpino_spi_master_subsystem_env.axi4_reg_predictor_h [REG_PREDICT] Observed WRITE transaction to register spi_master_reg_block.TXFIFO: value='h0 : updated value = 'h0 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_adapter.sv(118) @ 890: reporter [axi4_master_adapter] The converted bus2reg packet is ----------------------------------------------------------------------------------- +# Name Type Size Value +# ----------------------------------------------------------------------------------- +# axi4_master_tx axi4_master_tx - @2613 +# tx_type string 5 WRITE +# awid string 6 AWID_0 +# awaddr integral 32 'h1a102018 +# awlen integral 8 'd0 +# awsize string 13 WRITE_4_BYTES +# awburst string 10 WRITE_INCR +# awlock string 19 WRITE_NORMAL_ACCESS +# awcache string 16 WRITE_BUFFERABLE +# awprot string 24 WRITE_NORMAL_SECURE_DATA +# awqos integral 4 'h0 +# wait_count_write_address_channel integral 32 'h0 +# wait_count_write_data_channel integral 32 'h0 +# bid string 5 BID_0 +# bresp string 10 WRITE_OKAY +# no_of_wait_states integral 32 'd0 +# wait_count_write_response_channel integral 32 'h0 +# transfer_type string 14 BLOCKING_WRITE +# ----------------------------------------------------------------------------------- +# +# +# UVM_INFO ../../src/dv/hvl_top/env//axi4_reg_predictor.sv(48) @ 890: uvm_test_top.pulpino_spi_master_subsystem_env.axi4_reg_predictor_h [axi4_reg_predictor] rg_data = {TXFIFO} 564 1 2621 @uvm_status_container@1 1 @spi_master_apb_if@1 null 32 32 { {@uvm_reg_map@1:1} } {@uvm_reg_field@20} 4 4 @semaphore@8 @18350080 {} 0 0 1 0 1 0 null @uvm_object_string_pool__3@7 32 1 @uvm_reg_field@20 {ref to covergroup #cg_vals#} {spi_master_apb_if__txfifo} +# UVM_INFO ../../src/dv/hvl_top/env//axi4_reg_predictor.sv(49) @ 890: uvm_test_top.pulpino_spi_master_subsystem_env.axi4_reg_predictor_h [axi4_reg_predictor] rw_data = UVM_WRITE 437264408 0 0 0 UVM_IS_OK +# UVM_INFO ../../src/dv/hdl_top/axi4_master_agent_bfm/axi4_master_driver_bfm.sv(165) @ 910: reporter [AXI4_MASTER_DRIVER_BFM] DETECT_WRITE_DATA_WAIT_STATE +# UVM_INFO ../../src/dv/hdl_top/axi4_master_agent_bfm/axi4_master_driver_bfm.sv(176) @ 930: reporter [AXI4_MASTER_DRIVER_BFM] DEBUG_NA:WDATA[0]=fffff01a +# UVM_INFO ../../src/dv/hdl_top/axi4_master_agent_bfm/axi4_master_driver_bfm.sv(181) @ 930: reporter [AXI4_MASTER_DRIVER_BFM] WRITE_DATA_COMP data_write_packet= +# '{awid:0, awaddr:437264408, awlen:0, awsize:2, awburst:1, awlock:0, awcache:0, awqos:0, awregion:0, awuser:0, awprot:0, awvalid:0, awready:0, wdata:'{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 4294963226}, wstrb:'{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, wuser:0, wlast:0, bid:0, bresp:0, buser:0, bvalid:0, tx_type:0, wait_count_write_address_channel:1, wait_count_write_data_channel:0, wait_count_write_response_channel:0, outstanding_write_tx:0, no_of_wait_states:0} +# UVM_INFO ../../src/dv/hdl_top/axi4_master_agent_bfm/axi4_master_driver_bfm.sv(190) @ 930: reporter [AXI4_MASTER_DRIVER_BFM] WRITE_RESP data_write_packet= +# '{awid:0, awaddr:437264408, awlen:0, awsize:2, awburst:1, awlock:0, awcache:0, awqos:0, awregion:0, awuser:0, awprot:0, awvalid:0, awready:0, wdata:'{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 4294963226}, wstrb:'{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, wuser:0, wlast:0, bid:0, bresp:0, buser:0, bvalid:0, tx_type:0, wait_count_write_address_channel:1, wait_count_write_data_channel:0, wait_count_write_response_channel:0, outstanding_write_tx:0, no_of_wait_states:0} +# UVM_INFO ../../src/dv/hdl_top/axi4_master_agent_bfm/axi4_master_driver_bfm.sv(191) @ 930: reporter [AXI4_MASTER_DRIVER_BFM] cfg_packet= +# '{min_address:0, max_address:0, wait_count_write_address_channel:0, wait_count_write_data_channel:0, wait_count_write_response_channel:0, wait_count_read_address_channel:0, wait_count_read_data_channel:0, outstanding_write_tx:0, outstanding_read_tx:0} +# UVM_INFO ../../src/dv/hdl_top/axi4_master_agent_bfm/axi4_master_driver_bfm.sv(192) @ 930: reporter [AXI4_MASTER_DRIVER_BFM] DRIVE TO WRITE RESPONSE CHANNEL +# UVM_INFO ../../src/dv/hdl_top/axi4_master_agent_bfm/axi4_master_monitor_bfm.sv(128) @ 930: reporter [FROM MASTER MON BFM] After while loop write data...... +# UVM_INFO ../../src/dv/hdl_top/axi4_master_agent_bfm/axi4_master_monitor_bfm.sv(135) @ 930: reporter [FROM MASTER MON BFM write data] write datapacket wdata[0] = 'hfffff01a +# UVM_INFO ../../src/dv/hdl_top/axi4_master_agent_bfm/axi4_master_monitor_bfm.sv(136) @ 930: reporter [FROM MASTER MON BFM write data] write datapacket wstrb[0] = 'h0 +# UVM_INFO ../../src/dv/hdl_top/axi4_master_agent_bfm/axi4_master_monitor_bfm.sv(138) @ 930: reporter [FROM MASTER MON BFM write data] Inside wlast write datapacket ='{awid:0, awaddr:0, awlen:0, awsize:0, awburst:0, awlock:0, awcache:0, awqos:0, awregion:0, awuser:0, awprot:0, awvalid:0, awready:0, wdata:'{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 4294963226}, wstrb:'{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, wuser:0, wlast:1, bid:0, bresp:0, buser:0, bvalid:0, tx_type:0, wait_count_write_address_channel:0, wait_count_write_data_channel:0, wait_count_write_response_channel:0, outstanding_write_tx:0, no_of_wait_states:0} +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_monitor_proxy.sv(182) @ 930: uvm_test_top.pulpino_spi_master_subsystem_env.axi4_master_agent.axi4_master_mon_proxy_h [axi4_master_monitor_proxy] ADDR_Packet received from fifo is +# ----------------------------------------------------------------------------------- +# Name Type Size Value +# ----------------------------------------------------------------------------------- +# axi4_master_tx axi4_master_tx - @2609 +# tx_type string 5 WRITE +# awid string 6 AWID_0 +# awaddr integral 32 'h1a102018 +# awlen integral 8 'd0 +# awsize string 13 WRITE_4_BYTES +# awburst string 10 WRITE_INCR +# awlock string 19 WRITE_NORMAL_ACCESS +# awcache string 16 WRITE_BUFFERABLE +# awprot string 24 WRITE_NORMAL_SECURE_DATA +# awqos integral 4 'h0 +# wait_count_write_address_channel integral 32 'h0 +# wait_count_write_data_channel integral 32 'h0 +# bid string 5 BID_0 +# bresp string 10 WRITE_OKAY +# no_of_wait_states integral 32 'd0 +# wait_count_write_response_channel integral 32 'h0 +# transfer_type string 14 BLOCKING_WRITE +# ----------------------------------------------------------------------------------- +# +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(337) @ 930: reporter [axi4_master_seq_item_conv_class] ---------------------------------------------------------------------- +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(355) @ 930: reporter [axi4_master_seq_item_conv_class] After converting wdata[0] = fffff01a +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(362) @ 930: reporter [axi4_master_seq_item_conv_class] After converting wstrb[0] = 0 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(370) @ 930: reporter [axi4_master_seq_item_conv_class] After converting = ----------------------------------------------------------------------------------- +# Name Type Size Value +# ----------------------------------------------------------------------------------- +# axi4_master_tx axi4_master_tx - @2621 +# tx_type string 5 WRITE +# awid string 6 AWID_0 +# awaddr integral 32 'h1a102018 +# awlen integral 8 'd0 +# awsize string 13 WRITE_4_BYTES +# awburst string 10 WRITE_INCR +# awlock string 19 WRITE_NORMAL_ACCESS +# awcache string 16 WRITE_BUFFERABLE +# awprot string 24 WRITE_NORMAL_SECURE_DATA +# awqos integral 4 'h0 +# wait_count_write_address_channel integral 32 'h0 +# wdata[0] integral 64 'hfffff01a +# wstrb[0] integral 8 'h0 +# wait_count_write_data_channel integral 32 'h0 +# bid string 5 BID_0 +# bresp string 10 WRITE_OKAY +# no_of_wait_states integral 32 'd0 +# wait_count_write_response_channel integral 32 'h0 +# transfer_type string 14 BLOCKING_WRITE +# ----------------------------------------------------------------------------------- +# +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_monitor_proxy.sv(191) @ 930: uvm_test_top.pulpino_spi_master_subsystem_env.axi4_master_agent.axi4_master_mon_proxy_h [axi4_master_monitor_proxy] Packet received from axi4_write_data clone packet is +# ----------------------------------------------------------------------------------- +# Name Type Size Value +# ----------------------------------------------------------------------------------- +# axi4_master_tx axi4_master_tx - @2625 +# tx_type string 5 WRITE +# awid string 6 AWID_0 +# awaddr integral 32 'h1a102018 +# awlen integral 8 'd0 +# awsize string 13 WRITE_4_BYTES +# awburst string 10 WRITE_INCR +# awlock string 19 WRITE_NORMAL_ACCESS +# awcache string 16 WRITE_BUFFERABLE +# awprot string 24 WRITE_NORMAL_SECURE_DATA +# awqos integral 4 'h0 +# wait_count_write_address_channel integral 32 'h0 +# wdata[0] integral 64 'hfffff01a +# wstrb[0] integral 8 'h0 +# wait_count_write_data_channel integral 32 'h0 +# bid string 5 BID_0 +# bresp string 10 WRITE_OKAY +# no_of_wait_states integral 32 'd0 +# wait_count_write_response_channel integral 32 'h0 +# transfer_type string 14 BLOCKING_WRITE +# ----------------------------------------------------------------------------------- +# +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_coverage.sv(223) @ 930: uvm_test_top.pulpino_spi_master_subsystem_env.axi4_master_agent.axi4_master_cov_h [axi4_master_coverage] Before calling SAMPLE METHOD +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_coverage.sv(227) @ 930: uvm_test_top.pulpino_spi_master_subsystem_env.axi4_master_agent.axi4_master_cov_h [axi4_master_coverage] After calling SAMPLE METHOD +# UVM_INFO ../../src/dv/hdl_top/axi4_master_agent_bfm/axi4_master_driver_bfm.sv(210) @ 990: reporter [AXI4_MASTER_DRIVER_BFM] CHECKING WRITE RESPONSE :: '{awid:0, awaddr:437264408, awlen:0, awsize:2, awburst:1, awlock:0, awcache:0, awqos:0, awregion:0, awuser:0, awprot:0, awvalid:0, awready:0, wdata:'{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 4294963226}, wstrb:'{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, wuser:0, wlast:0, bid:0, bresp:0, buser:0, bvalid:1, tx_type:0, wait_count_write_address_channel:1, wait_count_write_data_channel:0, wait_count_write_response_channel:0, outstanding_write_tx:0, no_of_wait_states:0} +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(198) @ 1010: reporter [axi4_master_seq_item_conv_class] ---------------------------------------------------------------------- +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(204) @ 1010: reporter [axi4_master_seq_item_conv_class] After converting awid = 0000000000000000 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(207) @ 1010: reporter [axi4_master_seq_item_conv_class] After converting awlen = 00000000 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(210) @ 1010: reporter [axi4_master_seq_item_conv_class] After randomizing awsize = 010 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(213) @ 1010: reporter [axi4_master_seq_item_conv_class] After converting awburst = 01 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(216) @ 1010: reporter [axi4_master_seq_item_conv_class] After converting awlock = 0 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(219) @ 1010: reporter [axi4_master_seq_item_conv_class] After randomizing awcache = 0000 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(222) @ 1010: reporter [axi4_master_seq_item_conv_class] After randomizing awprot = 000 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(225) @ 1010: reporter [axi4_master_seq_item_conv_class] After converting awaddr = 1a102018 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(228) @ 1010: reporter [axi4_master_seq_item_conv_class] After converting awqos = 0 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(231) @ 1010: reporter [axi4_master_seq_item_conv_class] After converting wait_count_write_address_channel = 1 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(236) @ 1010: reporter [axi4_master_seq_item_conv_class] After converting wdata[0] = fffff01a +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(243) @ 1010: reporter [axi4_master_seq_item_conv_class] After converting wstrb[0] = 0 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(248) @ 1010: reporter [axi4_master_seq_item_conv_class] After converting wlast = 0 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(251) @ 1010: reporter [axi4_master_seq_item_conv_class] After converting wuser = 0 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(254) @ 1010: reporter [axi4_master_seq_item_conv_class] After converting wait_count_write_data_channel = 0 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(257) @ 1010: reporter [axi4_master_seq_item_conv_class] After converting bid = 0000000000000000 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(260) @ 1010: reporter [axi4_master_seq_item_conv_class] After converting bresp = 00 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(263) @ 1010: reporter [axi4_master_seq_item_conv_class] After converting wait_count_write_response_channel = 0 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_driver_proxy.sv(202) @ 1010: uvm_test_top.pulpino_spi_master_subsystem_env.axi4_master_agent.axi4_master_drv_proxy_h [axi4_master_driver_proxy] WRITE_TASK::Response Received_req_write_packet = +# ----------------------------------------------------------------------------------- +# Name Type Size Value +# ----------------------------------------------------------------------------------- +# axi4_master_tx axi4_master_tx - @2629 +# tx_type string 5 WRITE +# awid string 6 AWID_0 +# awaddr integral 32 'h1a102018 +# awlen integral 8 'd0 +# awsize string 13 WRITE_4_BYTES +# awburst string 10 WRITE_INCR +# awlock string 19 WRITE_NORMAL_ACCESS +# awcache string 16 WRITE_BUFFERABLE +# awprot string 24 WRITE_NORMAL_SECURE_DATA +# awqos integral 4 'h0 +# wait_count_write_address_channel integral 32 'h1 +# wdata[0] integral 64 'hfffff01a +# wstrb[0] integral 8 'h0 +# wait_count_write_data_channel integral 32 'h0 +# bid string 5 BID_0 +# bresp string 10 WRITE_OKAY +# no_of_wait_states integral 32 'd0 +# wait_count_write_response_channel integral 32 'h0 +# transfer_type string 14 BLOCKING_WRITE +# ----------------------------------------------------------------------------------- +# +# UVM_INFO ../../src/dv/hdl_top/axi4_master_agent_bfm/axi4_master_monitor_bfm.sv(158) @ 1010: reporter [FROM MASTER MON BFM::WRITE RESPONSE] WRITE RESPONSE PACKET: +# '{awid:0, awaddr:0, awlen:0, awsize:0, awburst:0, awlock:0, awcache:0, awqos:0, awregion:0, awuser:0, awprot:0, awvalid:0, awready:0, wdata:'{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, wstrb:'{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, wuser:0, wlast:0, bid:0, bresp:0, buser:0, bvalid:0, tx_type:0, wait_count_write_address_channel:0, wait_count_write_data_channel:0, wait_count_write_response_channel:0, outstanding_write_tx:0, no_of_wait_states:0} +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(198) @ 1010: reporter [axi4_master_seq_item_conv_class] ---------------------------------------------------------------------- +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(204) @ 1010: reporter [axi4_master_seq_item_conv_class] After converting awid = 0000000000000000 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(207) @ 1010: reporter [axi4_master_seq_item_conv_class] After converting awlen = 00000000 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(210) @ 1010: reporter [axi4_master_seq_item_conv_class] After randomizing awsize = 000 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(213) @ 1010: reporter [axi4_master_seq_item_conv_class] After converting awburst = 00 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(216) @ 1010: reporter [axi4_master_seq_item_conv_class] After converting awlock = 0 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(219) @ 1010: reporter [axi4_master_seq_item_conv_class] After randomizing awcache = 0000 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(222) @ 1010: reporter [axi4_master_seq_item_conv_class] After randomizing awprot = 000 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(225) @ 1010: reporter [axi4_master_seq_item_conv_class] After converting awaddr = 0 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(228) @ 1010: reporter [axi4_master_seq_item_conv_class] After converting awqos = 0 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(231) @ 1010: reporter [axi4_master_seq_item_conv_class] After converting wait_count_write_address_channel = 0 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(248) @ 1010: reporter [axi4_master_seq_item_conv_class] After converting wlast = 0 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(251) @ 1010: reporter [axi4_master_seq_item_conv_class] After converting wuser = 0 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(254) @ 1010: reporter [axi4_master_seq_item_conv_class] After converting wait_count_write_data_channel = 0 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(257) @ 1010: reporter [axi4_master_seq_item_conv_class] After converting bid = 0000000000000000 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(260) @ 1010: reporter [axi4_master_seq_item_conv_class] After converting bresp = 00 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(263) @ 1010: reporter [axi4_master_seq_item_conv_class] After converting wait_count_write_response_channel = 0 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(384) @ 1010: reporter [axi4_master_seq_item_conv_class] ---------------------------------------------------------------------- +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(402) @ 1010: reporter [axi4_master_seq_item_conv_class] After converting wdata[0] = fffff01a +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(409) @ 1010: reporter [axi4_master_seq_item_conv_class] After converting wstrb[0] = 0 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(417) @ 1010: reporter [axi4_master_seq_item_conv_class] After converting = ----------------------------------------------------------------------------------- +# Name Type Size Value +# ----------------------------------------------------------------------------------- +# axi4_master_tx axi4_master_tx - @2637 +# tx_type string 5 WRITE +# awid string 6 AWID_0 +# awaddr integral 32 'h1a102018 +# awlen integral 8 'd0 +# awsize string 13 WRITE_4_BYTES +# awburst string 10 WRITE_INCR +# awlock string 19 WRITE_NORMAL_ACCESS +# awcache string 16 WRITE_BUFFERABLE +# awprot string 24 WRITE_NORMAL_SECURE_DATA +# awqos integral 4 'h0 +# wait_count_write_address_channel integral 32 'h0 +# wdata[0] integral 64 'hfffff01a +# wstrb[0] integral 8 'h0 +# wait_count_write_data_channel integral 32 'h0 +# bid string 5 BID_0 +# bresp string 10 WRITE_OKAY +# no_of_wait_states integral 32 'd0 +# wait_count_write_response_channel integral 32 'h0 +# transfer_type string 14 BLOCKING_WRITE +# ----------------------------------------------------------------------------------- +# +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_monitor_proxy.sv(220) @ 1010: uvm_test_top.pulpino_spi_master_subsystem_env.axi4_master_agent.axi4_master_mon_proxy_h [axi4_master_monitor_proxy] Packet received from axi4_write_response clone packet is +# ----------------------------------------------------------------------------------- +# Name Type Size Value +# ----------------------------------------------------------------------------------- +# axi4_master_tx axi4_master_tx - @2641 +# tx_type string 5 WRITE +# awid string 6 AWID_0 +# awaddr integral 32 'h1a102018 +# awlen integral 8 'd0 +# awsize string 13 WRITE_4_BYTES +# awburst string 10 WRITE_INCR +# awlock string 19 WRITE_NORMAL_ACCESS +# awcache string 16 WRITE_BUFFERABLE +# awprot string 24 WRITE_NORMAL_SECURE_DATA +# awqos integral 4 'h0 +# wait_count_write_address_channel integral 32 'h0 +# wdata[0] integral 64 'hfffff01a +# wstrb[0] integral 8 'h0 +# wait_count_write_data_channel integral 32 'h0 +# bid string 5 BID_0 +# bresp string 10 WRITE_OKAY +# no_of_wait_states integral 32 'd0 +# wait_count_write_response_channel integral 32 'h0 +# transfer_type string 14 BLOCKING_WRITE +# ----------------------------------------------------------------------------------- +# +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_coverage.sv(223) @ 1010: uvm_test_top.pulpino_spi_master_subsystem_env.axi4_master_agent.axi4_master_cov_h [axi4_master_coverage] Before calling SAMPLE METHOD +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_coverage.sv(227) @ 1010: uvm_test_top.pulpino_spi_master_subsystem_env.axi4_master_agent.axi4_master_cov_h [axi4_master_coverage] After calling SAMPLE METHOD +# UVM_INFO ../../src/dv/hdl_top/axi4_master_agent_bfm/axi4_master_monitor_bfm.sv(151) @ 1010: reporter [FROM MASTER MON BFM] AFTER WHILE LOOP OF WRITE RESPONSE +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_adapter.sv(118) @ 1010: reporter [axi4_master_adapter] The converted bus2reg packet is ----------------------------------------------------------------------------------- +# Name Type Size Value +# ----------------------------------------------------------------------------------- +# axi4_master_tx axi4_master_tx - @2605 +# tx_type string 5 WRITE +# awid string 6 AWID_0 +# awaddr integral 32 'h1a102018 +# awlen integral 8 'd0 +# awsize string 13 WRITE_4_BYTES +# awburst string 10 WRITE_INCR +# awlock string 19 WRITE_NORMAL_ACCESS +# awcache string 16 WRITE_BUFFERABLE +# awprot string 24 WRITE_NORMAL_SECURE_DATA +# awqos integral 4 'h0 +# wait_count_write_address_channel integral 32 'h0 +# wdata[0] integral 64 'hfffff01a +# wait_count_write_data_channel integral 32 'h0 +# bid string 5 BID_0 +# bresp string 10 WRITE_OKAY +# no_of_wait_states integral 32 'd0 +# wait_count_write_response_channel integral 32 'h0 +# transfer_type string 14 BLOCKING_WRITE +# ----------------------------------------------------------------------------------- +# +# +# UVM_INFO @ 1010: reporter [RegModel] Wrote register via map spi_master_reg_block.SPI_MASTER_MAP_ABP_IF: spi_master_reg_block.TXFIFO=0xfffff01a +# UVM_INFO ../../src/dv/hvl_top/test/sequences/master_sequences/reg_sequences//axi4_master_basic_write_read_reg_seq.sv(309) @ 1010: uvm_test_top.pulpino_spi_master_subsystem_env.axi4_master_agent.axi4_master_write_seqr_h@@axi4_master_basic_write_read_reg_seq_h [axi4_master_basic_write_read_reg_seq] Write :: Register thtx_value = 1f +# UVM_INFO ../../src/dv/hvl_top/test/sequences/master_sequences/reg_sequences//axi4_master_basic_write_read_reg_seq.sv(310) @ 1010: uvm_test_top.pulpino_spi_master_subsystem_env.axi4_master_agent.axi4_master_write_seqr_h@@axi4_master_basic_write_read_reg_seq_h [axi4_master_basic_write_read_reg_seq] Write :: Register rhtx_value = 1f +# UVM_INFO ../../src/dv/hvl_top/test/sequences/master_sequences/reg_sequences//axi4_master_basic_write_read_reg_seq.sv(311) @ 1010: uvm_test_top.pulpino_spi_master_subsystem_env.axi4_master_agent.axi4_master_write_seqr_h@@axi4_master_basic_write_read_reg_seq_h [axi4_master_basic_write_read_reg_seq] Write :: Register cnttx_value = 4 +# UVM_INFO ../../src/dv/hvl_top/test/sequences/master_sequences/reg_sequences//axi4_master_basic_write_read_reg_seq.sv(312) @ 1010: uvm_test_top.pulpino_spi_master_subsystem_env.axi4_master_agent.axi4_master_write_seqr_h@@axi4_master_basic_write_read_reg_seq_h [axi4_master_basic_write_read_reg_seq] Write :: Register cntrx_value = 4 +# UVM_INFO ../../src/dv/hvl_top/test/sequences/master_sequences/reg_sequences//axi4_master_basic_write_read_reg_seq.sv(327) @ 1010: uvm_test_top.pulpino_spi_master_subsystem_env.axi4_master_agent.axi4_master_write_seqr_h@@axi4_master_basic_write_read_reg_seq_h [INTERUPT_REG_SEQ] WRITE:: REGISTER : spi_master_reg_block.INTCFG DATA = 32'he4e4ff1f +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_adapter.sv(53) @ 1010: reporter [MSHA_DEBUG] +# rw.address = 1a102024 rw.data = e4e4ff1f +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_adapter.sv(73) @ 1010: reporter [axi4_master_adapter] The converted reg2bus packet is ----------------------------------------------------------------------------------- +# Name Type Size Value +# ----------------------------------------------------------------------------------- +# axi4_master_tx axi4_master_tx - @2649 +# tx_type string 5 WRITE +# awid string 6 AWID_0 +# awaddr integral 32 'h1a102024 +# awlen integral 8 'd0 +# awsize string 13 WRITE_4_BYTES +# awburst string 10 WRITE_INCR +# awlock string 19 WRITE_NORMAL_ACCESS +# awcache string 16 WRITE_BUFFERABLE +# awprot string 24 WRITE_NORMAL_SECURE_DATA +# awqos integral 4 'h0 +# wait_count_write_address_channel integral 32 'h0 +# wdata[0] integral 64 'he4e4ff1f +# wait_count_write_data_channel integral 32 'h0 +# bid string 5 BID_0 +# bresp string 10 WRITE_OKAY +# no_of_wait_states integral 32 'd0 +# wait_count_write_response_channel integral 32 'h0 +# transfer_type string 14 BLOCKING_WRITE +# ----------------------------------------------------------------------------------- +# +# +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_driver_proxy.sv(167) @ 1010: uvm_test_top.pulpino_spi_master_subsystem_env.axi4_master_agent.axi4_master_drv_proxy_h [axi4_master_driver_proxy] WRITE_TASK::Before Sending_req_write_packet = +# ----------------------------------------------------------------------------------- +# Name Type Size Value +# ----------------------------------------------------------------------------------- +# axi4_master_tx axi4_master_tx - @2649 +# tx_type string 5 WRITE +# awid string 6 AWID_0 +# awaddr integral 32 'h1a102024 +# awlen integral 8 'd0 +# awsize string 13 WRITE_4_BYTES +# awburst string 10 WRITE_INCR +# awlock string 19 WRITE_NORMAL_ACCESS +# awcache string 16 WRITE_BUFFERABLE +# awprot string 24 WRITE_NORMAL_SECURE_DATA +# awqos integral 4 'h0 +# wait_count_write_address_channel integral 32 'h0 +# wdata[0] integral 64 'he4e4ff1f +# wait_count_write_data_channel integral 32 'h0 +# bid string 5 BID_0 +# bresp string 10 WRITE_OKAY +# no_of_wait_states integral 32 'd0 +# wait_count_write_response_channel integral 32 'h0 +# transfer_type string 14 BLOCKING_WRITE +# ----------------------------------------------------------------------------------- +# +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(47) @ 1010: reporter [axi4_master_seq_item_conv_class] ---------------------------------------------------------------------- +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(49) @ 1010: reporter [axi4_master_seq_item_conv_class] After converting awid = 0000 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(52) @ 1010: reporter [axi4_master_seq_item_conv_class] After converting awlen = 00000000 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(55) @ 1010: reporter [axi4_master_seq_item_conv_class] After randomizing awsize = 010 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(58) @ 1010: reporter [axi4_master_seq_item_conv_class] After converting awburst = 01 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(61) @ 1010: reporter [axi4_master_seq_item_conv_class] After converting awlock = 0 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(64) @ 1010: reporter [axi4_master_seq_item_conv_class] After randomizing awcache = 0000 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(67) @ 1010: reporter [axi4_master_seq_item_conv_class] After randomizing awprot = 000 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(70) @ 1010: reporter [axi4_master_seq_item_conv_class] After converting bid = 0000 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(73) @ 1010: reporter [axi4_master_seq_item_conv_class] After converting bresp = 00 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(76) @ 1010: reporter [axi4_master_seq_item_conv_class] After converting buser = 0 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(81) @ 1010: reporter [axi4_master_seq_item_conv_class] After converting awaddr = 1a102024 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(84) @ 1010: reporter [axi4_master_seq_item_conv_class] After converting awqos = 0 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(89) @ 1010: reporter [axi4_master_seq_item_conv_class] After converting wdata = 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 3840212767 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(96) @ 1010: reporter [axi4_master_seq_item_conv_class] After converting wstrb = 0 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(101) @ 1010: reporter [axi4_master_seq_item_conv_class] After converting wlast = 0 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(104) @ 1010: reporter [axi4_master_seq_item_conv_class] After converting wuser = 0 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(107) @ 1010: reporter [axi4_master_seq_item_conv_class] After converting no_wait_states = 0 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_driver_proxy.sv(192) @ 1010: uvm_test_top.pulpino_spi_master_subsystem_env.axi4_master_agent.axi4_master_drv_proxy_h [axi4_master_driver_proxy] WRITE_TASK::Checking transfer type = BLOCKING_WRITE +# UVM_INFO ../../src/dv/hdl_top/axi4_master_agent_bfm/axi4_master_driver_bfm.sv(117) @ 1030: reporter [AXI4_MASTER_DRIVER_BFM] data_write_packet= +# '{awid:0, awaddr:437264420, awlen:0, awsize:2, awburst:1, awlock:0, awcache:0, awqos:0, awregion:0, awuser:0, awprot:0, awvalid:0, awready:0, wdata:'{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 3840212767}, wstrb:'{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, wuser:0, wlast:0, bid:0, bresp:0, buser:0, bvalid:0, tx_type:0, wait_count_write_address_channel:0, wait_count_write_data_channel:0, wait_count_write_response_channel:0, outstanding_write_tx:0, no_of_wait_states:0} +# UVM_INFO ../../src/dv/hdl_top/axi4_master_agent_bfm/axi4_master_driver_bfm.sv(118) @ 1030: reporter [AXI4_MASTER_DRIVER_BFM] cfg_packet= +# '{min_address:0, max_address:0, wait_count_write_address_channel:0, wait_count_write_data_channel:0, wait_count_write_response_channel:0, wait_count_read_address_channel:0, wait_count_read_data_channel:0, outstanding_write_tx:0, outstanding_read_tx:0} +# UVM_INFO ../../src/dv/hdl_top/axi4_master_agent_bfm/axi4_master_driver_bfm.sv(119) @ 1030: reporter [AXI4_MASTER_DRIVER_BFM] DRIVING_WRITE_ADDRESS_CHANNEL +# UVM_INFO ../../src/dv/hdl_top/axi4_master_agent_bfm/axi4_master_driver_bfm.sv(134) @ 1030: reporter [AXI4_MASTER_DRIVER_BFM] detect_awready = 1 +# UVM_INFO ../../src/dv/hdl_top/axi4_master_agent_bfm/axi4_master_driver_bfm.sv(142) @ 1050: reporter [AXI4_MASTER_DRIVER_BFM] After_loop_of_Detecting_awready = 1, awvalid = 1 +# UVM_INFO ../../src/dv/hdl_top/axi4_master_agent_bfm/axi4_master_driver_bfm.sv(153) @ 1050: reporter [AXI4_MASTER_DRIVER_BFM] data_write_packet= +# '{awid:0, awaddr:437264420, awlen:0, awsize:2, awburst:1, awlock:0, awcache:0, awqos:0, awregion:0, awuser:0, awprot:0, awvalid:0, awready:0, wdata:'{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 3840212767}, wstrb:'{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, wuser:0, wlast:0, bid:0, bresp:0, buser:0, bvalid:0, tx_type:0, wait_count_write_address_channel:1, wait_count_write_data_channel:0, wait_count_write_response_channel:0, outstanding_write_tx:0, no_of_wait_states:0} +# UVM_INFO ../../src/dv/hdl_top/axi4_master_agent_bfm/axi4_master_driver_bfm.sv(154) @ 1050: reporter [AXI4_MASTER_DRIVER_BFM] cfg_packet= +# '{min_address:0, max_address:0, wait_count_write_address_channel:0, wait_count_write_data_channel:0, wait_count_write_response_channel:0, wait_count_read_address_channel:0, wait_count_read_data_channel:0, outstanding_write_tx:0, outstanding_read_tx:0} +# UVM_INFO ../../src/dv/hdl_top/axi4_master_agent_bfm/axi4_master_driver_bfm.sv(155) @ 1050: reporter [AXI4_MASTER_DRIVER_BFM] DRIVE TO WRITE DATA CHANNEL +# UVM_INFO ../../src/dv/hdl_top/axi4_master_agent_bfm/axi4_master_monitor_bfm.sv(102) @ 1050: reporter [FROM MASTER MON BFM] after while loop ....... +# UVM_INFO ../../src/dv/hdl_top/axi4_master_agent_bfm/axi4_master_monitor_bfm.sv(112) @ 1050: reporter [FROM MASTER MON BFM] datapacket ='{awid:0, awaddr:437264420, awlen:0, awsize:2, awburst:1, awlock:0, awcache:0, awqos:0, awregion:0, awuser:0, awprot:0, awvalid:0, awready:0, wdata:'{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, wstrb:'{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, wuser:0, wlast:0, bid:0, bresp:0, buser:0, bvalid:0, tx_type:0, wait_count_write_address_channel:0, wait_count_write_data_channel:0, wait_count_write_response_channel:0, outstanding_write_tx:0, no_of_wait_states:0} +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(198) @ 1050: reporter [axi4_master_seq_item_conv_class] ---------------------------------------------------------------------- +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(204) @ 1050: reporter [axi4_master_seq_item_conv_class] After converting awid = 0000000000000000 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(207) @ 1050: reporter [axi4_master_seq_item_conv_class] After converting awlen = 00000000 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(210) @ 1050: reporter [axi4_master_seq_item_conv_class] After randomizing awsize = 010 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(213) @ 1050: reporter [axi4_master_seq_item_conv_class] After converting awburst = 01 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(216) @ 1050: reporter [axi4_master_seq_item_conv_class] After converting awlock = 0 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(219) @ 1050: reporter [axi4_master_seq_item_conv_class] After randomizing awcache = 0000 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(222) @ 1050: reporter [axi4_master_seq_item_conv_class] After randomizing awprot = 000 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(225) @ 1050: reporter [axi4_master_seq_item_conv_class] After converting awaddr = 1a102024 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(228) @ 1050: reporter [axi4_master_seq_item_conv_class] After converting awqos = 0 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(231) @ 1050: reporter [axi4_master_seq_item_conv_class] After converting wait_count_write_address_channel = 0 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(248) @ 1050: reporter [axi4_master_seq_item_conv_class] After converting wlast = 0 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(251) @ 1050: reporter [axi4_master_seq_item_conv_class] After converting wuser = 0 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(254) @ 1050: reporter [axi4_master_seq_item_conv_class] After converting wait_count_write_data_channel = 0 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(257) @ 1050: reporter [axi4_master_seq_item_conv_class] After converting bid = 0000000000000000 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(260) @ 1050: reporter [axi4_master_seq_item_conv_class] After converting bresp = 00 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(263) @ 1050: reporter [axi4_master_seq_item_conv_class] After converting wait_count_write_response_channel = 0 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_monitor_proxy.sv(159) @ 1050: uvm_test_top.pulpino_spi_master_subsystem_env.axi4_master_agent.axi4_master_mon_proxy_h [axi4_master_monitor_proxy] Packet received from axi4_write_address clone packet is +# ----------------------------------------------------------------------------------- +# Name Type Size Value +# ----------------------------------------------------------------------------------- +# axi4_master_tx axi4_master_tx - @2657 +# tx_type string 5 WRITE +# awid string 6 AWID_0 +# awaddr integral 32 'h1a102024 +# awlen integral 8 'd0 +# awsize string 13 WRITE_4_BYTES +# awburst string 10 WRITE_INCR +# awlock string 19 WRITE_NORMAL_ACCESS +# awcache string 16 WRITE_BUFFERABLE +# awprot string 24 WRITE_NORMAL_SECURE_DATA +# awqos integral 4 'h0 +# wait_count_write_address_channel integral 32 'h0 +# wait_count_write_data_channel integral 32 'h0 +# bid string 5 BID_0 +# bresp string 10 WRITE_OKAY +# no_of_wait_states integral 32 'd0 +# wait_count_write_response_channel integral 32 'h0 +# transfer_type string 14 BLOCKING_WRITE +# ----------------------------------------------------------------------------------- +# +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_coverage.sv(223) @ 1050: uvm_test_top.pulpino_spi_master_subsystem_env.axi4_master_agent.axi4_master_cov_h [axi4_master_coverage] Before calling SAMPLE METHOD +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_coverage.sv(227) @ 1050: uvm_test_top.pulpino_spi_master_subsystem_env.axi4_master_agent.axi4_master_cov_h [axi4_master_coverage] After calling SAMPLE METHOD +# UVM_INFO ../../src/dv/hvl_top/env//axi4_master_collector.sv(60) @ 1050: uvm_test_top.pulpino_spi_master_subsystem_env.axi4_master_coll_h [axi4_master_collector] Req print = ----------------------------------------------------------------------------------- +# Name Type Size Value +# ----------------------------------------------------------------------------------- +# axi4_master_tx axi4_master_tx - @2657 +# tx_type string 5 WRITE +# awid string 6 AWID_0 +# awaddr integral 32 'h1a102024 +# awlen integral 8 'd0 +# awsize string 13 WRITE_4_BYTES +# awburst string 10 WRITE_INCR +# awlock string 19 WRITE_NORMAL_ACCESS +# awcache string 16 WRITE_BUFFERABLE +# awprot string 24 WRITE_NORMAL_SECURE_DATA +# awqos integral 4 'h0 +# wait_count_write_address_channel integral 32 'h0 +# wait_count_write_data_channel integral 32 'h0 +# bid string 5 BID_0 +# bresp string 10 WRITE_OKAY +# no_of_wait_states integral 32 'd0 +# wait_count_write_response_channel integral 32 'h0 +# transfer_type string 14 BLOCKING_WRITE +# ----------------------------------------------------------------------------------- +# +# UVM_INFO ../../src/dv/hvl_top/env//axi4_master_collector.sv(64) @ 1050: uvm_test_top.pulpino_spi_master_subsystem_env.axi4_master_coll_h [axi4_master_collector] rg_name = INTCFG +# UVM_INFO ../../src/dv/hvl_top/env//axi4_master_collector.sv(65) @ 1050: uvm_test_top.pulpino_spi_master_subsystem_env.axi4_master_coll_h [axi4_master_collector] rg_address = 1a102024 +# UVM_INFO ../../src/dv/hvl_top/env//axi4_master_collector.sv(66) @ 1050: uvm_test_top.pulpino_spi_master_subsystem_env.axi4_master_coll_h [axi4_master_collector] rg_data = c4041f1f +# UVM_INFO ../../src/dv/hvl_top/env//axi4_master_collector.sv(67) @ 1050: uvm_test_top.pulpino_spi_master_subsystem_env.axi4_master_coll_h [axi4_master_collector] map_name = spi_master_reg_block.SPI_MASTER_MAP_ABP_IF +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_adapter.sv(118) @ 1050: reporter [axi4_master_adapter] The converted bus2reg packet is ----------------------------------------------------------------------------------- +# Name Type Size Value +# ----------------------------------------------------------------------------------- +# axi4_master_tx axi4_master_tx - @2657 +# tx_type string 5 WRITE +# awid string 6 AWID_0 +# awaddr integral 32 'h1a102024 +# awlen integral 8 'd0 +# awsize string 13 WRITE_4_BYTES +# awburst string 10 WRITE_INCR +# awlock string 19 WRITE_NORMAL_ACCESS +# awcache string 16 WRITE_BUFFERABLE +# awprot string 24 WRITE_NORMAL_SECURE_DATA +# awqos integral 4 'h0 +# wait_count_write_address_channel integral 32 'h0 +# wait_count_write_data_channel integral 32 'h0 +# bid string 5 BID_0 +# bresp string 10 WRITE_OKAY +# no_of_wait_states integral 32 'd0 +# wait_count_write_response_channel integral 32 'h0 +# transfer_type string 14 BLOCKING_WRITE +# ----------------------------------------------------------------------------------- +# +# +# UVM_INFO verilog_src/uvm-1.1d/src/reg/uvm_reg_predictor.svh(221) @ 1050: uvm_test_top.pulpino_spi_master_subsystem_env.axi4_reg_predictor_h [REG_PREDICT] Observed WRITE transaction to register spi_master_reg_block.INTCFG: value='h0 : updated value = 'h0 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_adapter.sv(118) @ 1050: reporter [axi4_master_adapter] The converted bus2reg packet is ----------------------------------------------------------------------------------- +# Name Type Size Value +# ----------------------------------------------------------------------------------- +# axi4_master_tx axi4_master_tx - @2657 +# tx_type string 5 WRITE +# awid string 6 AWID_0 +# awaddr integral 32 'h1a102024 +# awlen integral 8 'd0 +# awsize string 13 WRITE_4_BYTES +# awburst string 10 WRITE_INCR +# awlock string 19 WRITE_NORMAL_ACCESS +# awcache string 16 WRITE_BUFFERABLE +# awprot string 24 WRITE_NORMAL_SECURE_DATA +# awqos integral 4 'h0 +# wait_count_write_address_channel integral 32 'h0 +# wait_count_write_data_channel integral 32 'h0 +# bid string 5 BID_0 +# bresp string 10 WRITE_OKAY +# no_of_wait_states integral 32 'd0 +# wait_count_write_response_channel integral 32 'h0 +# transfer_type string 14 BLOCKING_WRITE +# ----------------------------------------------------------------------------------- +# +# +# UVM_INFO ../../src/dv/hvl_top/env//axi4_reg_predictor.sv(48) @ 1050: uvm_test_top.pulpino_spi_master_subsystem_env.axi4_reg_predictor_h [axi4_reg_predictor] rg_data = {INTCFG} 574 1 2665 @uvm_status_container@1 1 @spi_master_apb_if@1 null 32 22 { {@uvm_reg_map@1:1} } {@uvm_reg_field@31 @uvm_reg_field@29 @uvm_reg_field@27 @uvm_reg_field@25 @uvm_reg_field@23 @uvm_reg_field@22} 4 4 @semaphore@10 @18350080 {} 0 0 1 0 1 0 null @uvm_object_string_pool__3@9 32 1 @uvm_reg_field@22 @uvm_reg_field@23 @uvm_reg_field@24 @uvm_reg_field@25 @uvm_reg_field@26 @uvm_reg_field@27 @uvm_reg_field@28 @uvm_reg_field@29 @uvm_reg_field@30 @uvm_reg_field@31 {ref to covergroup #cg_vals#} {spi_master_apb_if__intcfg} +# UVM_INFO ../../src/dv/hvl_top/env//axi4_reg_predictor.sv(49) @ 1050: uvm_test_top.pulpino_spi_master_subsystem_env.axi4_reg_predictor_h [axi4_reg_predictor] rw_data = UVM_WRITE 437264420 0 0 0 UVM_IS_OK +# UVM_INFO ../../src/dv/hdl_top/axi4_master_agent_bfm/axi4_master_driver_bfm.sv(165) @ 1070: reporter [AXI4_MASTER_DRIVER_BFM] DETECT_WRITE_DATA_WAIT_STATE +# UVM_INFO ../../src/dv/hdl_top/axi4_master_agent_bfm/axi4_master_driver_bfm.sv(176) @ 1090: reporter [AXI4_MASTER_DRIVER_BFM] DEBUG_NA:WDATA[0]=e4e4ff1f +# UVM_INFO ../../src/dv/hdl_top/axi4_master_agent_bfm/axi4_master_driver_bfm.sv(181) @ 1090: reporter [AXI4_MASTER_DRIVER_BFM] WRITE_DATA_COMP data_write_packet= +# '{awid:0, awaddr:437264420, awlen:0, awsize:2, awburst:1, awlock:0, awcache:0, awqos:0, awregion:0, awuser:0, awprot:0, awvalid:0, awready:0, wdata:'{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 3840212767}, wstrb:'{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, wuser:0, wlast:0, bid:0, bresp:0, buser:0, bvalid:0, tx_type:0, wait_count_write_address_channel:1, wait_count_write_data_channel:0, wait_count_write_response_channel:0, outstanding_write_tx:0, no_of_wait_states:0} +# UVM_INFO ../../src/dv/hdl_top/axi4_master_agent_bfm/axi4_master_driver_bfm.sv(190) @ 1090: reporter [AXI4_MASTER_DRIVER_BFM] WRITE_RESP data_write_packet= +# '{awid:0, awaddr:437264420, awlen:0, awsize:2, awburst:1, awlock:0, awcache:0, awqos:0, awregion:0, awuser:0, awprot:0, awvalid:0, awready:0, wdata:'{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 3840212767}, wstrb:'{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, wuser:0, wlast:0, bid:0, bresp:0, buser:0, bvalid:0, tx_type:0, wait_count_write_address_channel:1, wait_count_write_data_channel:0, wait_count_write_response_channel:0, outstanding_write_tx:0, no_of_wait_states:0} +# UVM_INFO ../../src/dv/hdl_top/axi4_master_agent_bfm/axi4_master_driver_bfm.sv(191) @ 1090: reporter [AXI4_MASTER_DRIVER_BFM] cfg_packet= +# '{min_address:0, max_address:0, wait_count_write_address_channel:0, wait_count_write_data_channel:0, wait_count_write_response_channel:0, wait_count_read_address_channel:0, wait_count_read_data_channel:0, outstanding_write_tx:0, outstanding_read_tx:0} +# UVM_INFO ../../src/dv/hdl_top/axi4_master_agent_bfm/axi4_master_driver_bfm.sv(192) @ 1090: reporter [AXI4_MASTER_DRIVER_BFM] DRIVE TO WRITE RESPONSE CHANNEL +# UVM_INFO ../../src/dv/hdl_top/axi4_master_agent_bfm/axi4_master_monitor_bfm.sv(128) @ 1090: reporter [FROM MASTER MON BFM] After while loop write data...... +# UVM_INFO ../../src/dv/hdl_top/axi4_master_agent_bfm/axi4_master_monitor_bfm.sv(135) @ 1090: reporter [FROM MASTER MON BFM write data] write datapacket wdata[0] = 'he4e4ff1f +# UVM_INFO ../../src/dv/hdl_top/axi4_master_agent_bfm/axi4_master_monitor_bfm.sv(136) @ 1090: reporter [FROM MASTER MON BFM write data] write datapacket wstrb[0] = 'h0 +# UVM_INFO ../../src/dv/hdl_top/axi4_master_agent_bfm/axi4_master_monitor_bfm.sv(138) @ 1090: reporter [FROM MASTER MON BFM write data] Inside wlast write datapacket ='{awid:0, awaddr:0, awlen:0, awsize:0, awburst:0, awlock:0, awcache:0, awqos:0, awregion:0, awuser:0, awprot:0, awvalid:0, awready:0, wdata:'{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 3840212767}, wstrb:'{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, wuser:0, wlast:1, bid:0, bresp:0, buser:0, bvalid:0, tx_type:0, wait_count_write_address_channel:0, wait_count_write_data_channel:0, wait_count_write_response_channel:0, outstanding_write_tx:0, no_of_wait_states:0} +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_monitor_proxy.sv(182) @ 1090: uvm_test_top.pulpino_spi_master_subsystem_env.axi4_master_agent.axi4_master_mon_proxy_h [axi4_master_monitor_proxy] ADDR_Packet received from fifo is +# ----------------------------------------------------------------------------------- +# Name Type Size Value +# ----------------------------------------------------------------------------------- +# axi4_master_tx axi4_master_tx - @2653 +# tx_type string 5 WRITE +# awid string 6 AWID_0 +# awaddr integral 32 'h1a102024 +# awlen integral 8 'd0 +# awsize string 13 WRITE_4_BYTES +# awburst string 10 WRITE_INCR +# awlock string 19 WRITE_NORMAL_ACCESS +# awcache string 16 WRITE_BUFFERABLE +# awprot string 24 WRITE_NORMAL_SECURE_DATA +# awqos integral 4 'h0 +# wait_count_write_address_channel integral 32 'h0 +# wait_count_write_data_channel integral 32 'h0 +# bid string 5 BID_0 +# bresp string 10 WRITE_OKAY +# no_of_wait_states integral 32 'd0 +# wait_count_write_response_channel integral 32 'h0 +# transfer_type string 14 BLOCKING_WRITE +# ----------------------------------------------------------------------------------- +# +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(337) @ 1090: reporter [axi4_master_seq_item_conv_class] ---------------------------------------------------------------------- +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(355) @ 1090: reporter [axi4_master_seq_item_conv_class] After converting wdata[0] = e4e4ff1f +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(362) @ 1090: reporter [axi4_master_seq_item_conv_class] After converting wstrb[0] = 0 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(370) @ 1090: reporter [axi4_master_seq_item_conv_class] After converting = ----------------------------------------------------------------------------------- +# Name Type Size Value +# ----------------------------------------------------------------------------------- +# axi4_master_tx axi4_master_tx - @2665 +# tx_type string 5 WRITE +# awid string 6 AWID_0 +# awaddr integral 32 'h1a102024 +# awlen integral 8 'd0 +# awsize string 13 WRITE_4_BYTES +# awburst string 10 WRITE_INCR +# awlock string 19 WRITE_NORMAL_ACCESS +# awcache string 16 WRITE_BUFFERABLE +# awprot string 24 WRITE_NORMAL_SECURE_DATA +# awqos integral 4 'h0 +# wait_count_write_address_channel integral 32 'h0 +# wdata[0] integral 64 'he4e4ff1f +# wstrb[0] integral 8 'h0 +# wait_count_write_data_channel integral 32 'h0 +# bid string 5 BID_0 +# bresp string 10 WRITE_OKAY +# no_of_wait_states integral 32 'd0 +# wait_count_write_response_channel integral 32 'h0 +# transfer_type string 14 BLOCKING_WRITE +# ----------------------------------------------------------------------------------- +# +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_monitor_proxy.sv(191) @ 1090: uvm_test_top.pulpino_spi_master_subsystem_env.axi4_master_agent.axi4_master_mon_proxy_h [axi4_master_monitor_proxy] Packet received from axi4_write_data clone packet is +# ----------------------------------------------------------------------------------- +# Name Type Size Value +# ----------------------------------------------------------------------------------- +# axi4_master_tx axi4_master_tx - @2669 +# tx_type string 5 WRITE +# awid string 6 AWID_0 +# awaddr integral 32 'h1a102024 +# awlen integral 8 'd0 +# awsize string 13 WRITE_4_BYTES +# awburst string 10 WRITE_INCR +# awlock string 19 WRITE_NORMAL_ACCESS +# awcache string 16 WRITE_BUFFERABLE +# awprot string 24 WRITE_NORMAL_SECURE_DATA +# awqos integral 4 'h0 +# wait_count_write_address_channel integral 32 'h0 +# wdata[0] integral 64 'he4e4ff1f +# wstrb[0] integral 8 'h0 +# wait_count_write_data_channel integral 32 'h0 +# bid string 5 BID_0 +# bresp string 10 WRITE_OKAY +# no_of_wait_states integral 32 'd0 +# wait_count_write_response_channel integral 32 'h0 +# transfer_type string 14 BLOCKING_WRITE +# ----------------------------------------------------------------------------------- +# +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_coverage.sv(223) @ 1090: uvm_test_top.pulpino_spi_master_subsystem_env.axi4_master_agent.axi4_master_cov_h [axi4_master_coverage] Before calling SAMPLE METHOD +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_coverage.sv(227) @ 1090: uvm_test_top.pulpino_spi_master_subsystem_env.axi4_master_agent.axi4_master_cov_h [axi4_master_coverage] After calling SAMPLE METHOD +# UVM_INFO ../../src/dv/hdl_top/axi4_master_agent_bfm/axi4_master_driver_bfm.sv(210) @ 1150: reporter [AXI4_MASTER_DRIVER_BFM] CHECKING WRITE RESPONSE :: '{awid:0, awaddr:437264420, awlen:0, awsize:2, awburst:1, awlock:0, awcache:0, awqos:0, awregion:0, awuser:0, awprot:0, awvalid:0, awready:0, wdata:'{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 3840212767}, wstrb:'{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, wuser:0, wlast:0, bid:0, bresp:0, buser:0, bvalid:1, tx_type:0, wait_count_write_address_channel:1, wait_count_write_data_channel:0, wait_count_write_response_channel:0, outstanding_write_tx:0, no_of_wait_states:0} +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(198) @ 1170: reporter [axi4_master_seq_item_conv_class] ---------------------------------------------------------------------- +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(204) @ 1170: reporter [axi4_master_seq_item_conv_class] After converting awid = 0000000000000000 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(207) @ 1170: reporter [axi4_master_seq_item_conv_class] After converting awlen = 00000000 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(210) @ 1170: reporter [axi4_master_seq_item_conv_class] After randomizing awsize = 010 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(213) @ 1170: reporter [axi4_master_seq_item_conv_class] After converting awburst = 01 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(216) @ 1170: reporter [axi4_master_seq_item_conv_class] After converting awlock = 0 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(219) @ 1170: reporter [axi4_master_seq_item_conv_class] After randomizing awcache = 0000 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(222) @ 1170: reporter [axi4_master_seq_item_conv_class] After randomizing awprot = 000 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(225) @ 1170: reporter [axi4_master_seq_item_conv_class] After converting awaddr = 1a102024 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(228) @ 1170: reporter [axi4_master_seq_item_conv_class] After converting awqos = 0 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(231) @ 1170: reporter [axi4_master_seq_item_conv_class] After converting wait_count_write_address_channel = 1 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(236) @ 1170: reporter [axi4_master_seq_item_conv_class] After converting wdata[0] = e4e4ff1f +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(243) @ 1170: reporter [axi4_master_seq_item_conv_class] After converting wstrb[0] = 0 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(248) @ 1170: reporter [axi4_master_seq_item_conv_class] After converting wlast = 0 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(251) @ 1170: reporter [axi4_master_seq_item_conv_class] After converting wuser = 0 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(254) @ 1170: reporter [axi4_master_seq_item_conv_class] After converting wait_count_write_data_channel = 0 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(257) @ 1170: reporter [axi4_master_seq_item_conv_class] After converting bid = 0000000000000000 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(260) @ 1170: reporter [axi4_master_seq_item_conv_class] After converting bresp = 00 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(263) @ 1170: reporter [axi4_master_seq_item_conv_class] After converting wait_count_write_response_channel = 0 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_driver_proxy.sv(202) @ 1170: uvm_test_top.pulpino_spi_master_subsystem_env.axi4_master_agent.axi4_master_drv_proxy_h [axi4_master_driver_proxy] WRITE_TASK::Response Received_req_write_packet = +# ----------------------------------------------------------------------------------- +# Name Type Size Value +# ----------------------------------------------------------------------------------- +# axi4_master_tx axi4_master_tx - @2673 +# tx_type string 5 WRITE +# awid string 6 AWID_0 +# awaddr integral 32 'h1a102024 +# awlen integral 8 'd0 +# awsize string 13 WRITE_4_BYTES +# awburst string 10 WRITE_INCR +# awlock string 19 WRITE_NORMAL_ACCESS +# awcache string 16 WRITE_BUFFERABLE +# awprot string 24 WRITE_NORMAL_SECURE_DATA +# awqos integral 4 'h0 +# wait_count_write_address_channel integral 32 'h1 +# wdata[0] integral 64 'he4e4ff1f +# wstrb[0] integral 8 'h0 +# wait_count_write_data_channel integral 32 'h0 +# bid string 5 BID_0 +# bresp string 10 WRITE_OKAY +# no_of_wait_states integral 32 'd0 +# wait_count_write_response_channel integral 32 'h0 +# transfer_type string 14 BLOCKING_WRITE +# ----------------------------------------------------------------------------------- +# +# UVM_INFO ../../src/dv/hdl_top/axi4_master_agent_bfm/axi4_master_monitor_bfm.sv(158) @ 1170: reporter [FROM MASTER MON BFM::WRITE RESPONSE] WRITE RESPONSE PACKET: +# '{awid:0, awaddr:0, awlen:0, awsize:0, awburst:0, awlock:0, awcache:0, awqos:0, awregion:0, awuser:0, awprot:0, awvalid:0, awready:0, wdata:'{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, wstrb:'{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, wuser:0, wlast:0, bid:0, bresp:0, buser:0, bvalid:0, tx_type:0, wait_count_write_address_channel:0, wait_count_write_data_channel:0, wait_count_write_response_channel:0, outstanding_write_tx:0, no_of_wait_states:0} +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(198) @ 1170: reporter [axi4_master_seq_item_conv_class] ---------------------------------------------------------------------- +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(204) @ 1170: reporter [axi4_master_seq_item_conv_class] After converting awid = 0000000000000000 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(207) @ 1170: reporter [axi4_master_seq_item_conv_class] After converting awlen = 00000000 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(210) @ 1170: reporter [axi4_master_seq_item_conv_class] After randomizing awsize = 000 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(213) @ 1170: reporter [axi4_master_seq_item_conv_class] After converting awburst = 00 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(216) @ 1170: reporter [axi4_master_seq_item_conv_class] After converting awlock = 0 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(219) @ 1170: reporter [axi4_master_seq_item_conv_class] After randomizing awcache = 0000 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(222) @ 1170: reporter [axi4_master_seq_item_conv_class] After randomizing awprot = 000 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(225) @ 1170: reporter [axi4_master_seq_item_conv_class] After converting awaddr = 0 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(228) @ 1170: reporter [axi4_master_seq_item_conv_class] After converting awqos = 0 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(231) @ 1170: reporter [axi4_master_seq_item_conv_class] After converting wait_count_write_address_channel = 0 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(248) @ 1170: reporter [axi4_master_seq_item_conv_class] After converting wlast = 0 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(251) @ 1170: reporter [axi4_master_seq_item_conv_class] After converting wuser = 0 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(254) @ 1170: reporter [axi4_master_seq_item_conv_class] After converting wait_count_write_data_channel = 0 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(257) @ 1170: reporter [axi4_master_seq_item_conv_class] After converting bid = 0000000000000000 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(260) @ 1170: reporter [axi4_master_seq_item_conv_class] After converting bresp = 00 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(263) @ 1170: reporter [axi4_master_seq_item_conv_class] After converting wait_count_write_response_channel = 0 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(384) @ 1170: reporter [axi4_master_seq_item_conv_class] ---------------------------------------------------------------------- +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(402) @ 1170: reporter [axi4_master_seq_item_conv_class] After converting wdata[0] = e4e4ff1f +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(409) @ 1170: reporter [axi4_master_seq_item_conv_class] After converting wstrb[0] = 0 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(417) @ 1170: reporter [axi4_master_seq_item_conv_class] After converting = ----------------------------------------------------------------------------------- +# Name Type Size Value +# ----------------------------------------------------------------------------------- +# axi4_master_tx axi4_master_tx - @2681 +# tx_type string 5 WRITE +# awid string 6 AWID_0 +# awaddr integral 32 'h1a102024 +# awlen integral 8 'd0 +# awsize string 13 WRITE_4_BYTES +# awburst string 10 WRITE_INCR +# awlock string 19 WRITE_NORMAL_ACCESS +# awcache string 16 WRITE_BUFFERABLE +# awprot string 24 WRITE_NORMAL_SECURE_DATA +# awqos integral 4 'h0 +# wait_count_write_address_channel integral 32 'h0 +# wdata[0] integral 64 'he4e4ff1f +# wstrb[0] integral 8 'h0 +# wait_count_write_data_channel integral 32 'h0 +# bid string 5 BID_0 +# bresp string 10 WRITE_OKAY +# no_of_wait_states integral 32 'd0 +# wait_count_write_response_channel integral 32 'h0 +# transfer_type string 14 BLOCKING_WRITE +# ----------------------------------------------------------------------------------- +# +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_monitor_proxy.sv(220) @ 1170: uvm_test_top.pulpino_spi_master_subsystem_env.axi4_master_agent.axi4_master_mon_proxy_h [axi4_master_monitor_proxy] Packet received from axi4_write_response clone packet is +# ----------------------------------------------------------------------------------- +# Name Type Size Value +# ----------------------------------------------------------------------------------- +# axi4_master_tx axi4_master_tx - @2685 +# tx_type string 5 WRITE +# awid string 6 AWID_0 +# awaddr integral 32 'h1a102024 +# awlen integral 8 'd0 +# awsize string 13 WRITE_4_BYTES +# awburst string 10 WRITE_INCR +# awlock string 19 WRITE_NORMAL_ACCESS +# awcache string 16 WRITE_BUFFERABLE +# awprot string 24 WRITE_NORMAL_SECURE_DATA +# awqos integral 4 'h0 +# wait_count_write_address_channel integral 32 'h0 +# wdata[0] integral 64 'he4e4ff1f +# wstrb[0] integral 8 'h0 +# wait_count_write_data_channel integral 32 'h0 +# bid string 5 BID_0 +# bresp string 10 WRITE_OKAY +# no_of_wait_states integral 32 'd0 +# wait_count_write_response_channel integral 32 'h0 +# transfer_type string 14 BLOCKING_WRITE +# ----------------------------------------------------------------------------------- +# +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_coverage.sv(223) @ 1170: uvm_test_top.pulpino_spi_master_subsystem_env.axi4_master_agent.axi4_master_cov_h [axi4_master_coverage] Before calling SAMPLE METHOD +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_coverage.sv(227) @ 1170: uvm_test_top.pulpino_spi_master_subsystem_env.axi4_master_agent.axi4_master_cov_h [axi4_master_coverage] After calling SAMPLE METHOD +# UVM_INFO ../../src/dv/hdl_top/axi4_master_agent_bfm/axi4_master_monitor_bfm.sv(151) @ 1170: reporter [FROM MASTER MON BFM] AFTER WHILE LOOP OF WRITE RESPONSE +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_adapter.sv(118) @ 1170: reporter [axi4_master_adapter] The converted bus2reg packet is ----------------------------------------------------------------------------------- +# Name Type Size Value +# ----------------------------------------------------------------------------------- +# axi4_master_tx axi4_master_tx - @2649 +# tx_type string 5 WRITE +# awid string 6 AWID_0 +# awaddr integral 32 'h1a102024 +# awlen integral 8 'd0 +# awsize string 13 WRITE_4_BYTES +# awburst string 10 WRITE_INCR +# awlock string 19 WRITE_NORMAL_ACCESS +# awcache string 16 WRITE_BUFFERABLE +# awprot string 24 WRITE_NORMAL_SECURE_DATA +# awqos integral 4 'h0 +# wait_count_write_address_channel integral 32 'h0 +# wdata[0] integral 64 'he4e4ff1f +# wait_count_write_data_channel integral 32 'h0 +# bid string 5 BID_0 +# bresp string 10 WRITE_OKAY +# no_of_wait_states integral 32 'd0 +# wait_count_write_response_channel integral 32 'h0 +# transfer_type string 14 BLOCKING_WRITE +# ----------------------------------------------------------------------------------- +# +# +# UVM_INFO @ 1170: reporter [RegModel] Wrote register via map spi_master_reg_block.SPI_MASTER_MAP_ABP_IF: spi_master_reg_block.INTCFG=0xe4e4ff1f +# UVM_INFO ../../src/dv/hvl_top/test/sequences/master_sequences/reg_sequences//axi4_master_basic_write_read_reg_seq.sv(360) @ 1170: uvm_test_top.pulpino_spi_master_subsystem_env.axi4_master_agent.axi4_master_write_seqr_h@@axi4_master_basic_write_read_reg_seq_h [axi4_master_basic_write_read_reg_seq] Write :: Register cs_value = 1110 +# UVM_INFO ../../src/dv/hvl_top/test/sequences/master_sequences/reg_sequences//axi4_master_basic_write_read_reg_seq.sv(372) @ 1170: uvm_test_top.pulpino_spi_master_subsystem_env.axi4_master_agent.axi4_master_write_seqr_h@@axi4_master_basic_write_read_reg_seq_h [STATUS_REG_SEQ] WRITE:: REGISTER : spi_master_reg_block.STATUS, DATA = 32'h1 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_adapter.sv(53) @ 1170: reporter [MSHA_DEBUG] +# rw.address = 1a102000 rw.data = 1 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_adapter.sv(73) @ 1170: reporter [axi4_master_adapter] The converted reg2bus packet is ----------------------------------------------------------------------------------- +# Name Type Size Value +# ----------------------------------------------------------------------------------- +# axi4_master_tx axi4_master_tx - @2693 +# tx_type string 5 WRITE +# awid string 6 AWID_0 +# awaddr integral 32 'h1a102000 +# awlen integral 8 'd0 +# awsize string 13 WRITE_4_BYTES +# awburst string 10 WRITE_INCR +# awlock string 19 WRITE_NORMAL_ACCESS +# awcache string 16 WRITE_BUFFERABLE +# awprot string 24 WRITE_NORMAL_SECURE_DATA +# awqos integral 4 'h0 +# wait_count_write_address_channel integral 32 'h0 +# wdata[0] integral 64 'h1 +# wait_count_write_data_channel integral 32 'h0 +# bid string 5 BID_0 +# bresp string 10 WRITE_OKAY +# no_of_wait_states integral 32 'd0 +# wait_count_write_response_channel integral 32 'h0 +# transfer_type string 14 BLOCKING_WRITE +# ----------------------------------------------------------------------------------- +# +# +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_driver_proxy.sv(167) @ 1170: uvm_test_top.pulpino_spi_master_subsystem_env.axi4_master_agent.axi4_master_drv_proxy_h [axi4_master_driver_proxy] WRITE_TASK::Before Sending_req_write_packet = +# ----------------------------------------------------------------------------------- +# Name Type Size Value +# ----------------------------------------------------------------------------------- +# axi4_master_tx axi4_master_tx - @2693 +# tx_type string 5 WRITE +# awid string 6 AWID_0 +# awaddr integral 32 'h1a102000 +# awlen integral 8 'd0 +# awsize string 13 WRITE_4_BYTES +# awburst string 10 WRITE_INCR +# awlock string 19 WRITE_NORMAL_ACCESS +# awcache string 16 WRITE_BUFFERABLE +# awprot string 24 WRITE_NORMAL_SECURE_DATA +# awqos integral 4 'h0 +# wait_count_write_address_channel integral 32 'h0 +# wdata[0] integral 64 'h1 +# wait_count_write_data_channel integral 32 'h0 +# bid string 5 BID_0 +# bresp string 10 WRITE_OKAY +# no_of_wait_states integral 32 'd0 +# wait_count_write_response_channel integral 32 'h0 +# transfer_type string 14 BLOCKING_WRITE +# ----------------------------------------------------------------------------------- +# +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(47) @ 1170: reporter [axi4_master_seq_item_conv_class] ---------------------------------------------------------------------- +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(49) @ 1170: reporter [axi4_master_seq_item_conv_class] After converting awid = 0000 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(52) @ 1170: reporter [axi4_master_seq_item_conv_class] After converting awlen = 00000000 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(55) @ 1170: reporter [axi4_master_seq_item_conv_class] After randomizing awsize = 010 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(58) @ 1170: reporter [axi4_master_seq_item_conv_class] After converting awburst = 01 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(61) @ 1170: reporter [axi4_master_seq_item_conv_class] After converting awlock = 0 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(64) @ 1170: reporter [axi4_master_seq_item_conv_class] After randomizing awcache = 0000 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(67) @ 1170: reporter [axi4_master_seq_item_conv_class] After randomizing awprot = 000 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(70) @ 1170: reporter [axi4_master_seq_item_conv_class] After converting bid = 0000 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(73) @ 1170: reporter [axi4_master_seq_item_conv_class] After converting bresp = 00 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(76) @ 1170: reporter [axi4_master_seq_item_conv_class] After converting buser = 0 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(81) @ 1170: reporter [axi4_master_seq_item_conv_class] After converting awaddr = 1a102000 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(84) @ 1170: reporter [axi4_master_seq_item_conv_class] After converting awqos = 0 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(89) @ 1170: reporter [axi4_master_seq_item_conv_class] After converting wdata = 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(96) @ 1170: reporter [axi4_master_seq_item_conv_class] After converting wstrb = 0 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(101) @ 1170: reporter [axi4_master_seq_item_conv_class] After converting wlast = 0 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(104) @ 1170: reporter [axi4_master_seq_item_conv_class] After converting wuser = 0 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(107) @ 1170: reporter [axi4_master_seq_item_conv_class] After converting no_wait_states = 0 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_driver_proxy.sv(192) @ 1170: uvm_test_top.pulpino_spi_master_subsystem_env.axi4_master_agent.axi4_master_drv_proxy_h [axi4_master_driver_proxy] WRITE_TASK::Checking transfer type = BLOCKING_WRITE +# UVM_INFO ../../src/dv/hdl_top/axi4_master_agent_bfm/axi4_master_driver_bfm.sv(117) @ 1190: reporter [AXI4_MASTER_DRIVER_BFM] data_write_packet= +# '{awid:0, awaddr:437264384, awlen:0, awsize:2, awburst:1, awlock:0, awcache:0, awqos:0, awregion:0, awuser:0, awprot:0, awvalid:0, awready:0, wdata:'{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1}, wstrb:'{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, wuser:0, wlast:0, bid:0, bresp:0, buser:0, bvalid:0, tx_type:0, wait_count_write_address_channel:0, wait_count_write_data_channel:0, wait_count_write_response_channel:0, outstanding_write_tx:0, no_of_wait_states:0} +# UVM_INFO ../../src/dv/hdl_top/axi4_master_agent_bfm/axi4_master_driver_bfm.sv(118) @ 1190: reporter [AXI4_MASTER_DRIVER_BFM] cfg_packet= +# '{min_address:0, max_address:0, wait_count_write_address_channel:0, wait_count_write_data_channel:0, wait_count_write_response_channel:0, wait_count_read_address_channel:0, wait_count_read_data_channel:0, outstanding_write_tx:0, outstanding_read_tx:0} +# UVM_INFO ../../src/dv/hdl_top/axi4_master_agent_bfm/axi4_master_driver_bfm.sv(119) @ 1190: reporter [AXI4_MASTER_DRIVER_BFM] DRIVING_WRITE_ADDRESS_CHANNEL +# UVM_INFO ../../src/dv/hdl_top/axi4_master_agent_bfm/axi4_master_driver_bfm.sv(134) @ 1190: reporter [AXI4_MASTER_DRIVER_BFM] detect_awready = 1 +# UVM_INFO ../../src/dv/hdl_top/axi4_master_agent_bfm/axi4_master_driver_bfm.sv(142) @ 1210: reporter [AXI4_MASTER_DRIVER_BFM] After_loop_of_Detecting_awready = 1, awvalid = 1 +# UVM_INFO ../../src/dv/hdl_top/axi4_master_agent_bfm/axi4_master_driver_bfm.sv(153) @ 1210: reporter [AXI4_MASTER_DRIVER_BFM] data_write_packet= +# '{awid:0, awaddr:437264384, awlen:0, awsize:2, awburst:1, awlock:0, awcache:0, awqos:0, awregion:0, awuser:0, awprot:0, awvalid:0, awready:0, wdata:'{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1}, wstrb:'{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, wuser:0, wlast:0, bid:0, bresp:0, buser:0, bvalid:0, tx_type:0, wait_count_write_address_channel:1, wait_count_write_data_channel:0, wait_count_write_response_channel:0, outstanding_write_tx:0, no_of_wait_states:0} +# UVM_INFO ../../src/dv/hdl_top/axi4_master_agent_bfm/axi4_master_driver_bfm.sv(154) @ 1210: reporter [AXI4_MASTER_DRIVER_BFM] cfg_packet= +# '{min_address:0, max_address:0, wait_count_write_address_channel:0, wait_count_write_data_channel:0, wait_count_write_response_channel:0, wait_count_read_address_channel:0, wait_count_read_data_channel:0, outstanding_write_tx:0, outstanding_read_tx:0} +# UVM_INFO ../../src/dv/hdl_top/axi4_master_agent_bfm/axi4_master_driver_bfm.sv(155) @ 1210: reporter [AXI4_MASTER_DRIVER_BFM] DRIVE TO WRITE DATA CHANNEL +# UVM_INFO ../../src/dv/hdl_top/axi4_master_agent_bfm/axi4_master_monitor_bfm.sv(102) @ 1210: reporter [FROM MASTER MON BFM] after while loop ....... +# UVM_INFO ../../src/dv/hdl_top/axi4_master_agent_bfm/axi4_master_monitor_bfm.sv(112) @ 1210: reporter [FROM MASTER MON BFM] datapacket ='{awid:0, awaddr:437264384, awlen:0, awsize:2, awburst:1, awlock:0, awcache:0, awqos:0, awregion:0, awuser:0, awprot:0, awvalid:0, awready:0, wdata:'{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, wstrb:'{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, wuser:0, wlast:0, bid:0, bresp:0, buser:0, bvalid:0, tx_type:0, wait_count_write_address_channel:0, wait_count_write_data_channel:0, wait_count_write_response_channel:0, outstanding_write_tx:0, no_of_wait_states:0} +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(198) @ 1210: reporter [axi4_master_seq_item_conv_class] ---------------------------------------------------------------------- +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(204) @ 1210: reporter [axi4_master_seq_item_conv_class] After converting awid = 0000000000000000 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(207) @ 1210: reporter [axi4_master_seq_item_conv_class] After converting awlen = 00000000 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(210) @ 1210: reporter [axi4_master_seq_item_conv_class] After randomizing awsize = 010 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(213) @ 1210: reporter [axi4_master_seq_item_conv_class] After converting awburst = 01 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(216) @ 1210: reporter [axi4_master_seq_item_conv_class] After converting awlock = 0 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(219) @ 1210: reporter [axi4_master_seq_item_conv_class] After randomizing awcache = 0000 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(222) @ 1210: reporter [axi4_master_seq_item_conv_class] After randomizing awprot = 000 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(225) @ 1210: reporter [axi4_master_seq_item_conv_class] After converting awaddr = 1a102000 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(228) @ 1210: reporter [axi4_master_seq_item_conv_class] After converting awqos = 0 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(231) @ 1210: reporter [axi4_master_seq_item_conv_class] After converting wait_count_write_address_channel = 0 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(248) @ 1210: reporter [axi4_master_seq_item_conv_class] After converting wlast = 0 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(251) @ 1210: reporter [axi4_master_seq_item_conv_class] After converting wuser = 0 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(254) @ 1210: reporter [axi4_master_seq_item_conv_class] After converting wait_count_write_data_channel = 0 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(257) @ 1210: reporter [axi4_master_seq_item_conv_class] After converting bid = 0000000000000000 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(260) @ 1210: reporter [axi4_master_seq_item_conv_class] After converting bresp = 00 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(263) @ 1210: reporter [axi4_master_seq_item_conv_class] After converting wait_count_write_response_channel = 0 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_monitor_proxy.sv(159) @ 1210: uvm_test_top.pulpino_spi_master_subsystem_env.axi4_master_agent.axi4_master_mon_proxy_h [axi4_master_monitor_proxy] Packet received from axi4_write_address clone packet is +# ----------------------------------------------------------------------------------- +# Name Type Size Value +# ----------------------------------------------------------------------------------- +# axi4_master_tx axi4_master_tx - @2701 +# tx_type string 5 WRITE +# awid string 6 AWID_0 +# awaddr integral 32 'h1a102000 +# awlen integral 8 'd0 +# awsize string 13 WRITE_4_BYTES +# awburst string 10 WRITE_INCR +# awlock string 19 WRITE_NORMAL_ACCESS +# awcache string 16 WRITE_BUFFERABLE +# awprot string 24 WRITE_NORMAL_SECURE_DATA +# awqos integral 4 'h0 +# wait_count_write_address_channel integral 32 'h0 +# wait_count_write_data_channel integral 32 'h0 +# bid string 5 BID_0 +# bresp string 10 WRITE_OKAY +# no_of_wait_states integral 32 'd0 +# wait_count_write_response_channel integral 32 'h0 +# transfer_type string 14 BLOCKING_WRITE +# ----------------------------------------------------------------------------------- +# +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_coverage.sv(223) @ 1210: uvm_test_top.pulpino_spi_master_subsystem_env.axi4_master_agent.axi4_master_cov_h [axi4_master_coverage] Before calling SAMPLE METHOD +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_coverage.sv(227) @ 1210: uvm_test_top.pulpino_spi_master_subsystem_env.axi4_master_agent.axi4_master_cov_h [axi4_master_coverage] After calling SAMPLE METHOD +# UVM_INFO ../../src/dv/hvl_top/env//axi4_master_collector.sv(60) @ 1210: uvm_test_top.pulpino_spi_master_subsystem_env.axi4_master_coll_h [axi4_master_collector] Req print = ----------------------------------------------------------------------------------- +# Name Type Size Value +# ----------------------------------------------------------------------------------- +# axi4_master_tx axi4_master_tx - @2701 +# tx_type string 5 WRITE +# awid string 6 AWID_0 +# awaddr integral 32 'h1a102000 +# awlen integral 8 'd0 +# awsize string 13 WRITE_4_BYTES +# awburst string 10 WRITE_INCR +# awlock string 19 WRITE_NORMAL_ACCESS +# awcache string 16 WRITE_BUFFERABLE +# awprot string 24 WRITE_NORMAL_SECURE_DATA +# awqos integral 4 'h0 +# wait_count_write_address_channel integral 32 'h0 +# wait_count_write_data_channel integral 32 'h0 +# bid string 5 BID_0 +# bresp string 10 WRITE_OKAY +# no_of_wait_states integral 32 'd0 +# wait_count_write_response_channel integral 32 'h0 +# transfer_type string 14 BLOCKING_WRITE +# ----------------------------------------------------------------------------------- +# +# UVM_INFO ../../src/dv/hvl_top/env//axi4_master_collector.sv(64) @ 1210: uvm_test_top.pulpino_spi_master_subsystem_env.axi4_master_coll_h [axi4_master_collector] rg_name = STATUS +# UVM_INFO ../../src/dv/hvl_top/env//axi4_master_collector.sv(65) @ 1210: uvm_test_top.pulpino_spi_master_subsystem_env.axi4_master_coll_h [axi4_master_collector] rg_address = 1a102000 +# UVM_INFO ../../src/dv/hvl_top/env//axi4_master_collector.sv(66) @ 1210: uvm_test_top.pulpino_spi_master_subsystem_env.axi4_master_coll_h [axi4_master_collector] rg_data = 1 +# UVM_INFO ../../src/dv/hvl_top/env//axi4_master_collector.sv(67) @ 1210: uvm_test_top.pulpino_spi_master_subsystem_env.axi4_master_coll_h [axi4_master_collector] map_name = spi_master_reg_block.SPI_MASTER_MAP_ABP_IF +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_adapter.sv(118) @ 1210: reporter [axi4_master_adapter] The converted bus2reg packet is ----------------------------------------------------------------------------------- +# Name Type Size Value +# ----------------------------------------------------------------------------------- +# axi4_master_tx axi4_master_tx - @2701 +# tx_type string 5 WRITE +# awid string 6 AWID_0 +# awaddr integral 32 'h1a102000 +# awlen integral 8 'd0 +# awsize string 13 WRITE_4_BYTES +# awburst string 10 WRITE_INCR +# awlock string 19 WRITE_NORMAL_ACCESS +# awcache string 16 WRITE_BUFFERABLE +# awprot string 24 WRITE_NORMAL_SECURE_DATA +# awqos integral 4 'h0 +# wait_count_write_address_channel integral 32 'h0 +# wait_count_write_data_channel integral 32 'h0 +# bid string 5 BID_0 +# bresp string 10 WRITE_OKAY +# no_of_wait_states integral 32 'd0 +# wait_count_write_response_channel integral 32 'h0 +# transfer_type string 14 BLOCKING_WRITE +# ----------------------------------------------------------------------------------- +# +# +# UVM_INFO verilog_src/uvm-1.1d/src/reg/uvm_reg_predictor.svh(221) @ 1210: uvm_test_top.pulpino_spi_master_subsystem_env.axi4_reg_predictor_h [REG_PREDICT] Observed WRITE transaction to register spi_master_reg_block.STATUS: value='h0 : updated value = 'h0 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_adapter.sv(118) @ 1210: reporter [axi4_master_adapter] The converted bus2reg packet is ----------------------------------------------------------------------------------- +# Name Type Size Value +# ----------------------------------------------------------------------------------- +# axi4_master_tx axi4_master_tx - @2701 +# tx_type string 5 WRITE +# awid string 6 AWID_0 +# awaddr integral 32 'h1a102000 +# awlen integral 8 'd0 +# awsize string 13 WRITE_4_BYTES +# awburst string 10 WRITE_INCR +# awlock string 19 WRITE_NORMAL_ACCESS +# awcache string 16 WRITE_BUFFERABLE +# awprot string 24 WRITE_NORMAL_SECURE_DATA +# awqos integral 4 'h0 +# wait_count_write_address_channel integral 32 'h0 +# wait_count_write_data_channel integral 32 'h0 +# bid string 5 BID_0 +# bresp string 10 WRITE_OKAY +# no_of_wait_states integral 32 'd0 +# wait_count_write_response_channel integral 32 'h0 +# transfer_type string 14 BLOCKING_WRITE +# ----------------------------------------------------------------------------------- +# +# +# UVM_INFO ../../src/dv/hvl_top/env//axi4_reg_predictor.sv(48) @ 1210: uvm_test_top.pulpino_spi_master_subsystem_env.axi4_reg_predictor_h [axi4_reg_predictor] rg_data = {STATUS} 521 1 2709 @uvm_status_container@1 1 @spi_master_apb_if@1 null 32 9 { {@uvm_reg_map@1:1} } {@uvm_reg_field@8 @uvm_reg_field@7 @uvm_reg_field@6 @uvm_reg_field@5 @uvm_reg_field@4 @uvm_reg_field@2} 4 4 @semaphore@2 @18350080 {} 0 0 1 0 1 0 null @uvm_object_string_pool__3@1 32 1 @uvm_reg_field@1 @uvm_reg_field@2 @uvm_reg_field@3 @uvm_reg_field@4 @uvm_reg_field@5 @uvm_reg_field@6 @uvm_reg_field@7 @uvm_reg_field@8 {ref to covergroup #cg_vals#} {spi_master_apb_if__status} +# UVM_INFO ../../src/dv/hvl_top/env//axi4_reg_predictor.sv(49) @ 1210: uvm_test_top.pulpino_spi_master_subsystem_env.axi4_reg_predictor_h [axi4_reg_predictor] rw_data = UVM_WRITE 437264384 0 0 0 UVM_IS_OK +# UVM_INFO ../../src/dv/hdl_top/axi4_master_agent_bfm/axi4_master_driver_bfm.sv(165) @ 1230: reporter [AXI4_MASTER_DRIVER_BFM] DETECT_WRITE_DATA_WAIT_STATE +# UVM_INFO ../../src/dv/hdl_top/axi4_master_agent_bfm/axi4_master_driver_bfm.sv(176) @ 1250: reporter [AXI4_MASTER_DRIVER_BFM] DEBUG_NA:WDATA[0]=1 +# UVM_INFO ../../src/dv/hdl_top/axi4_master_agent_bfm/axi4_master_driver_bfm.sv(181) @ 1250: reporter [AXI4_MASTER_DRIVER_BFM] WRITE_DATA_COMP data_write_packet= +# '{awid:0, awaddr:437264384, awlen:0, awsize:2, awburst:1, awlock:0, awcache:0, awqos:0, awregion:0, awuser:0, awprot:0, awvalid:0, awready:0, wdata:'{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1}, wstrb:'{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, wuser:0, wlast:0, bid:0, bresp:0, buser:0, bvalid:0, tx_type:0, wait_count_write_address_channel:1, wait_count_write_data_channel:0, wait_count_write_response_channel:0, outstanding_write_tx:0, no_of_wait_states:0} +# UVM_INFO ../../src/dv/hdl_top/axi4_master_agent_bfm/axi4_master_driver_bfm.sv(190) @ 1250: reporter [AXI4_MASTER_DRIVER_BFM] WRITE_RESP data_write_packet= +# '{awid:0, awaddr:437264384, awlen:0, awsize:2, awburst:1, awlock:0, awcache:0, awqos:0, awregion:0, awuser:0, awprot:0, awvalid:0, awready:0, wdata:'{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1}, wstrb:'{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, wuser:0, wlast:0, bid:0, bresp:0, buser:0, bvalid:0, tx_type:0, wait_count_write_address_channel:1, wait_count_write_data_channel:0, wait_count_write_response_channel:0, outstanding_write_tx:0, no_of_wait_states:0} +# UVM_INFO ../../src/dv/hdl_top/axi4_master_agent_bfm/axi4_master_driver_bfm.sv(191) @ 1250: reporter [AXI4_MASTER_DRIVER_BFM] cfg_packet= +# '{min_address:0, max_address:0, wait_count_write_address_channel:0, wait_count_write_data_channel:0, wait_count_write_response_channel:0, wait_count_read_address_channel:0, wait_count_read_data_channel:0, outstanding_write_tx:0, outstanding_read_tx:0} +# UVM_INFO ../../src/dv/hdl_top/axi4_master_agent_bfm/axi4_master_driver_bfm.sv(192) @ 1250: reporter [AXI4_MASTER_DRIVER_BFM] DRIVE TO WRITE RESPONSE CHANNEL +# UVM_INFO ../../src/dv/hdl_top/axi4_master_agent_bfm/axi4_master_monitor_bfm.sv(128) @ 1250: reporter [FROM MASTER MON BFM] After while loop write data...... +# UVM_INFO ../../src/dv/hdl_top/axi4_master_agent_bfm/axi4_master_monitor_bfm.sv(135) @ 1250: reporter [FROM MASTER MON BFM write data] write datapacket wdata[0] = 'h1 +# UVM_INFO ../../src/dv/hdl_top/axi4_master_agent_bfm/axi4_master_monitor_bfm.sv(136) @ 1250: reporter [FROM MASTER MON BFM write data] write datapacket wstrb[0] = 'h0 +# UVM_INFO ../../src/dv/hdl_top/axi4_master_agent_bfm/axi4_master_monitor_bfm.sv(138) @ 1250: reporter [FROM MASTER MON BFM write data] Inside wlast write datapacket ='{awid:0, awaddr:0, awlen:0, awsize:0, awburst:0, awlock:0, awcache:0, awqos:0, awregion:0, awuser:0, awprot:0, awvalid:0, awready:0, wdata:'{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1}, wstrb:'{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, wuser:0, wlast:1, bid:0, bresp:0, buser:0, bvalid:0, tx_type:0, wait_count_write_address_channel:0, wait_count_write_data_channel:0, wait_count_write_response_channel:0, outstanding_write_tx:0, no_of_wait_states:0} +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_monitor_proxy.sv(182) @ 1250: uvm_test_top.pulpino_spi_master_subsystem_env.axi4_master_agent.axi4_master_mon_proxy_h [axi4_master_monitor_proxy] ADDR_Packet received from fifo is +# ----------------------------------------------------------------------------------- +# Name Type Size Value +# ----------------------------------------------------------------------------------- +# axi4_master_tx axi4_master_tx - @2697 +# tx_type string 5 WRITE +# awid string 6 AWID_0 +# awaddr integral 32 'h1a102000 +# awlen integral 8 'd0 +# awsize string 13 WRITE_4_BYTES +# awburst string 10 WRITE_INCR +# awlock string 19 WRITE_NORMAL_ACCESS +# awcache string 16 WRITE_BUFFERABLE +# awprot string 24 WRITE_NORMAL_SECURE_DATA +# awqos integral 4 'h0 +# wait_count_write_address_channel integral 32 'h0 +# wait_count_write_data_channel integral 32 'h0 +# bid string 5 BID_0 +# bresp string 10 WRITE_OKAY +# no_of_wait_states integral 32 'd0 +# wait_count_write_response_channel integral 32 'h0 +# transfer_type string 14 BLOCKING_WRITE +# ----------------------------------------------------------------------------------- +# +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(337) @ 1250: reporter [axi4_master_seq_item_conv_class] ---------------------------------------------------------------------- +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(355) @ 1250: reporter [axi4_master_seq_item_conv_class] After converting wdata[0] = 1 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(362) @ 1250: reporter [axi4_master_seq_item_conv_class] After converting wstrb[0] = 0 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(370) @ 1250: reporter [axi4_master_seq_item_conv_class] After converting = ----------------------------------------------------------------------------------- +# Name Type Size Value +# ----------------------------------------------------------------------------------- +# axi4_master_tx axi4_master_tx - @2709 +# tx_type string 5 WRITE +# awid string 6 AWID_0 +# awaddr integral 32 'h1a102000 +# awlen integral 8 'd0 +# awsize string 13 WRITE_4_BYTES +# awburst string 10 WRITE_INCR +# awlock string 19 WRITE_NORMAL_ACCESS +# awcache string 16 WRITE_BUFFERABLE +# awprot string 24 WRITE_NORMAL_SECURE_DATA +# awqos integral 4 'h0 +# wait_count_write_address_channel integral 32 'h0 +# wdata[0] integral 64 'h1 +# wstrb[0] integral 8 'h0 +# wait_count_write_data_channel integral 32 'h0 +# bid string 5 BID_0 +# bresp string 10 WRITE_OKAY +# no_of_wait_states integral 32 'd0 +# wait_count_write_response_channel integral 32 'h0 +# transfer_type string 14 BLOCKING_WRITE +# ----------------------------------------------------------------------------------- +# +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_monitor_proxy.sv(191) @ 1250: uvm_test_top.pulpino_spi_master_subsystem_env.axi4_master_agent.axi4_master_mon_proxy_h [axi4_master_monitor_proxy] Packet received from axi4_write_data clone packet is +# ----------------------------------------------------------------------------------- +# Name Type Size Value +# ----------------------------------------------------------------------------------- +# axi4_master_tx axi4_master_tx - @2713 +# tx_type string 5 WRITE +# awid string 6 AWID_0 +# awaddr integral 32 'h1a102000 +# awlen integral 8 'd0 +# awsize string 13 WRITE_4_BYTES +# awburst string 10 WRITE_INCR +# awlock string 19 WRITE_NORMAL_ACCESS +# awcache string 16 WRITE_BUFFERABLE +# awprot string 24 WRITE_NORMAL_SECURE_DATA +# awqos integral 4 'h0 +# wait_count_write_address_channel integral 32 'h0 +# wdata[0] integral 64 'h1 +# wstrb[0] integral 8 'h0 +# wait_count_write_data_channel integral 32 'h0 +# bid string 5 BID_0 +# bresp string 10 WRITE_OKAY +# no_of_wait_states integral 32 'd0 +# wait_count_write_response_channel integral 32 'h0 +# transfer_type string 14 BLOCKING_WRITE +# ----------------------------------------------------------------------------------- +# +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_coverage.sv(223) @ 1250: uvm_test_top.pulpino_spi_master_subsystem_env.axi4_master_agent.axi4_master_cov_h [axi4_master_coverage] Before calling SAMPLE METHOD +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_coverage.sv(227) @ 1250: uvm_test_top.pulpino_spi_master_subsystem_env.axi4_master_agent.axi4_master_cov_h [axi4_master_coverage] After calling SAMPLE METHOD +# UVM_INFO ../../src/dv/hdl_top/axi4_master_agent_bfm/axi4_master_driver_bfm.sv(210) @ 1310: reporter [AXI4_MASTER_DRIVER_BFM] CHECKING WRITE RESPONSE :: '{awid:0, awaddr:437264384, awlen:0, awsize:2, awburst:1, awlock:0, awcache:0, awqos:0, awregion:0, awuser:0, awprot:0, awvalid:0, awready:0, wdata:'{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1}, wstrb:'{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, wuser:0, wlast:0, bid:0, bresp:0, buser:0, bvalid:1, tx_type:0, wait_count_write_address_channel:1, wait_count_write_data_channel:0, wait_count_write_response_channel:0, outstanding_write_tx:0, no_of_wait_states:0} +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(198) @ 1330: reporter [axi4_master_seq_item_conv_class] ---------------------------------------------------------------------- +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(204) @ 1330: reporter [axi4_master_seq_item_conv_class] After converting awid = 0000000000000000 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(207) @ 1330: reporter [axi4_master_seq_item_conv_class] After converting awlen = 00000000 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(210) @ 1330: reporter [axi4_master_seq_item_conv_class] After randomizing awsize = 010 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(213) @ 1330: reporter [axi4_master_seq_item_conv_class] After converting awburst = 01 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(216) @ 1330: reporter [axi4_master_seq_item_conv_class] After converting awlock = 0 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(219) @ 1330: reporter [axi4_master_seq_item_conv_class] After randomizing awcache = 0000 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(222) @ 1330: reporter [axi4_master_seq_item_conv_class] After randomizing awprot = 000 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(225) @ 1330: reporter [axi4_master_seq_item_conv_class] After converting awaddr = 1a102000 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(228) @ 1330: reporter [axi4_master_seq_item_conv_class] After converting awqos = 0 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(231) @ 1330: reporter [axi4_master_seq_item_conv_class] After converting wait_count_write_address_channel = 1 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(236) @ 1330: reporter [axi4_master_seq_item_conv_class] After converting wdata[0] = 1 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(243) @ 1330: reporter [axi4_master_seq_item_conv_class] After converting wstrb[0] = 0 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(248) @ 1330: reporter [axi4_master_seq_item_conv_class] After converting wlast = 0 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(251) @ 1330: reporter [axi4_master_seq_item_conv_class] After converting wuser = 0 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(254) @ 1330: reporter [axi4_master_seq_item_conv_class] After converting wait_count_write_data_channel = 0 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(257) @ 1330: reporter [axi4_master_seq_item_conv_class] After converting bid = 0000000000000000 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(260) @ 1330: reporter [axi4_master_seq_item_conv_class] After converting bresp = 00 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(263) @ 1330: reporter [axi4_master_seq_item_conv_class] After converting wait_count_write_response_channel = 0 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_driver_proxy.sv(202) @ 1330: uvm_test_top.pulpino_spi_master_subsystem_env.axi4_master_agent.axi4_master_drv_proxy_h [axi4_master_driver_proxy] WRITE_TASK::Response Received_req_write_packet = +# ----------------------------------------------------------------------------------- +# Name Type Size Value +# ----------------------------------------------------------------------------------- +# axi4_master_tx axi4_master_tx - @2717 +# tx_type string 5 WRITE +# awid string 6 AWID_0 +# awaddr integral 32 'h1a102000 +# awlen integral 8 'd0 +# awsize string 13 WRITE_4_BYTES +# awburst string 10 WRITE_INCR +# awlock string 19 WRITE_NORMAL_ACCESS +# awcache string 16 WRITE_BUFFERABLE +# awprot string 24 WRITE_NORMAL_SECURE_DATA +# awqos integral 4 'h0 +# wait_count_write_address_channel integral 32 'h1 +# wdata[0] integral 64 'h1 +# wstrb[0] integral 8 'h0 +# wait_count_write_data_channel integral 32 'h0 +# bid string 5 BID_0 +# bresp string 10 WRITE_OKAY +# no_of_wait_states integral 32 'd0 +# wait_count_write_response_channel integral 32 'h0 +# transfer_type string 14 BLOCKING_WRITE +# ----------------------------------------------------------------------------------- +# +# UVM_INFO ../../src/dv/hdl_top/axi4_master_agent_bfm/axi4_master_monitor_bfm.sv(158) @ 1330: reporter [FROM MASTER MON BFM::WRITE RESPONSE] WRITE RESPONSE PACKET: +# '{awid:0, awaddr:0, awlen:0, awsize:0, awburst:0, awlock:0, awcache:0, awqos:0, awregion:0, awuser:0, awprot:0, awvalid:0, awready:0, wdata:'{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, wstrb:'{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, wuser:0, wlast:0, bid:0, bresp:0, buser:0, bvalid:0, tx_type:0, wait_count_write_address_channel:0, wait_count_write_data_channel:0, wait_count_write_response_channel:0, outstanding_write_tx:0, no_of_wait_states:0} +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(198) @ 1330: reporter [axi4_master_seq_item_conv_class] ---------------------------------------------------------------------- +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(204) @ 1330: reporter [axi4_master_seq_item_conv_class] After converting awid = 0000000000000000 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(207) @ 1330: reporter [axi4_master_seq_item_conv_class] After converting awlen = 00000000 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(210) @ 1330: reporter [axi4_master_seq_item_conv_class] After randomizing awsize = 000 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(213) @ 1330: reporter [axi4_master_seq_item_conv_class] After converting awburst = 00 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(216) @ 1330: reporter [axi4_master_seq_item_conv_class] After converting awlock = 0 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(219) @ 1330: reporter [axi4_master_seq_item_conv_class] After randomizing awcache = 0000 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(222) @ 1330: reporter [axi4_master_seq_item_conv_class] After randomizing awprot = 000 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(225) @ 1330: reporter [axi4_master_seq_item_conv_class] After converting awaddr = 0 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(228) @ 1330: reporter [axi4_master_seq_item_conv_class] After converting awqos = 0 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(231) @ 1330: reporter [axi4_master_seq_item_conv_class] After converting wait_count_write_address_channel = 0 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(248) @ 1330: reporter [axi4_master_seq_item_conv_class] After converting wlast = 0 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(251) @ 1330: reporter [axi4_master_seq_item_conv_class] After converting wuser = 0 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(254) @ 1330: reporter [axi4_master_seq_item_conv_class] After converting wait_count_write_data_channel = 0 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(257) @ 1330: reporter [axi4_master_seq_item_conv_class] After converting bid = 0000000000000000 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(260) @ 1330: reporter [axi4_master_seq_item_conv_class] After converting bresp = 00 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(263) @ 1330: reporter [axi4_master_seq_item_conv_class] After converting wait_count_write_response_channel = 0 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(384) @ 1330: reporter [axi4_master_seq_item_conv_class] ---------------------------------------------------------------------- +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(402) @ 1330: reporter [axi4_master_seq_item_conv_class] After converting wdata[0] = 1 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(409) @ 1330: reporter [axi4_master_seq_item_conv_class] After converting wstrb[0] = 0 +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_seq_item_converter.sv(417) @ 1330: reporter [axi4_master_seq_item_conv_class] After converting = ----------------------------------------------------------------------------------- +# Name Type Size Value +# ----------------------------------------------------------------------------------- +# axi4_master_tx axi4_master_tx - @2725 +# tx_type string 5 WRITE +# awid string 6 AWID_0 +# awaddr integral 32 'h1a102000 +# awlen integral 8 'd0 +# awsize string 13 WRITE_4_BYTES +# awburst string 10 WRITE_INCR +# awlock string 19 WRITE_NORMAL_ACCESS +# awcache string 16 WRITE_BUFFERABLE +# awprot string 24 WRITE_NORMAL_SECURE_DATA +# awqos integral 4 'h0 +# wait_count_write_address_channel integral 32 'h0 +# wdata[0] integral 64 'h1 +# wstrb[0] integral 8 'h0 +# wait_count_write_data_channel integral 32 'h0 +# bid string 5 BID_0 +# bresp string 10 WRITE_OKAY +# no_of_wait_states integral 32 'd0 +# wait_count_write_response_channel integral 32 'h0 +# transfer_type string 14 BLOCKING_WRITE +# ----------------------------------------------------------------------------------- +# +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_monitor_proxy.sv(220) @ 1330: uvm_test_top.pulpino_spi_master_subsystem_env.axi4_master_agent.axi4_master_mon_proxy_h [axi4_master_monitor_proxy] Packet received from axi4_write_response clone packet is +# ----------------------------------------------------------------------------------- +# Name Type Size Value +# ----------------------------------------------------------------------------------- +# axi4_master_tx axi4_master_tx - @2729 +# tx_type string 5 WRITE +# awid string 6 AWID_0 +# awaddr integral 32 'h1a102000 +# awlen integral 8 'd0 +# awsize string 13 WRITE_4_BYTES +# awburst string 10 WRITE_INCR +# awlock string 19 WRITE_NORMAL_ACCESS +# awcache string 16 WRITE_BUFFERABLE +# awprot string 24 WRITE_NORMAL_SECURE_DATA +# awqos integral 4 'h0 +# wait_count_write_address_channel integral 32 'h0 +# wdata[0] integral 64 'h1 +# wstrb[0] integral 8 'h0 +# wait_count_write_data_channel integral 32 'h0 +# bid string 5 BID_0 +# bresp string 10 WRITE_OKAY +# no_of_wait_states integral 32 'd0 +# wait_count_write_response_channel integral 32 'h0 +# transfer_type string 14 BLOCKING_WRITE +# ----------------------------------------------------------------------------------- +# +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_coverage.sv(223) @ 1330: uvm_test_top.pulpino_spi_master_subsystem_env.axi4_master_agent.axi4_master_cov_h [axi4_master_coverage] Before calling SAMPLE METHOD +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_coverage.sv(227) @ 1330: uvm_test_top.pulpino_spi_master_subsystem_env.axi4_master_agent.axi4_master_cov_h [axi4_master_coverage] After calling SAMPLE METHOD +# UVM_INFO ../../src/dv/hdl_top/axi4_master_agent_bfm/axi4_master_monitor_bfm.sv(151) @ 1330: reporter [FROM MASTER MON BFM] AFTER WHILE LOOP OF WRITE RESPONSE +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_adapter.sv(118) @ 1330: reporter [axi4_master_adapter] The converted bus2reg packet is ----------------------------------------------------------------------------------- +# Name Type Size Value +# ----------------------------------------------------------------------------------- +# axi4_master_tx axi4_master_tx - @2693 +# tx_type string 5 WRITE +# awid string 6 AWID_0 +# awaddr integral 32 'h1a102000 +# awlen integral 8 'd0 +# awsize string 13 WRITE_4_BYTES +# awburst string 10 WRITE_INCR +# awlock string 19 WRITE_NORMAL_ACCESS +# awcache string 16 WRITE_BUFFERABLE +# awprot string 24 WRITE_NORMAL_SECURE_DATA +# awqos integral 4 'h0 +# wait_count_write_address_channel integral 32 'h0 +# wdata[0] integral 64 'h1 +# wait_count_write_data_channel integral 32 'h0 +# bid string 5 BID_0 +# bresp string 10 WRITE_OKAY +# no_of_wait_states integral 32 'd0 +# wait_count_write_response_channel integral 32 'h0 +# transfer_type string 14 BLOCKING_WRITE +# ----------------------------------------------------------------------------------- +# +# +# UVM_INFO @ 1330: reporter [RegModel] Wrote register via map spi_master_reg_block.SPI_MASTER_MAP_ABP_IF: spi_master_reg_block.STATUS=0x1 +# UVM_INFO ../../src/dv/hvl_top/test/virtual_sequences//virtual_basic_write_read_reg_seq.sv(64) @ 1330: uvm_test_top.pulpino_spi_master_subsystem_env.pulpino_spi_master_subsystem_virtual_seqr_h@@virtual_basic_write_read_reg_seq_h [master_vseq] ended master vseq +# UVM_INFO verilog_src/uvm-1.1d/src/base/uvm_objection.svh(1268) @ 8330: reporter [TEST_DONE] 'run' phase is ready to proceed to the 'extract' phase +# UVM_INFO ../../src/dv/hvl_top/axi4_master_agent//axi4_master_coverage.sv(235) @ 8330: uvm_test_top.pulpino_spi_master_subsystem_env.axi4_master_agent.axi4_master_cov_h [axi4_master_coverage] AXI4 Master Agent Coverage = 15.75 % +# UVM_INFO ../../src/dv/hvl_top/spi_slave_agent//spi_slave_coverage.sv(242) @ 8330: uvm_test_top.pulpino_spi_master_subsystem_env.spi_slave_agent_h[0].spi_slave_cov_h [spi_slave_coverage] spi_slave Agent Coverage = 0.00 % +# +# --- UVM Report Summary --- +# +# ** Report counts by severity +# UVM_INFO : 1094 +# UVM_WARNING : 0 +# UVM_ERROR : 0 +# UVM_FATAL : 0 +# ** Report counts by id +# [AXI4_MASTER_DRIVER_BFM] 123 +# [CLOCK_DIV_REG_SEQ] 1 +# [DUMMY_REG_SEQ] 1 +# [FROM MASTER MON BFM] 35 +# [FROM MASTER MON BFM write data] 24 +# [FROM MASTER MON BFM::WRITE RESPONSE] 8 +# [INTERUPT_REG_SEQ] 1 +# [MSHA_DEBUG] 8 +# [Questa UVM] 3 +# [REG_PREDICT] 8 +# [RNTST] 1 +# [RegModel] 8 +# [SPI_ADDR_REG_SEQ] 1 +# [SPI_CMD_REG_SEQ] 1 +# [SPI_LEN_REG_SEQ] 1 +# [STATUS_REG_SEQ] 1 +# [TEST_DONE] 1 +# [TX_FIFO_SEQ] 1 +# [UVMTOP] 1 +# [UVM_INFO] 1 +# [axi4 master agent bfm] 1 +# [axi4_master_adapter] 32 +# [axi4_master_basic_write_read_reg_seq] 11 +# [axi4_master_collector] 61 +# [axi4_master_coverage] 49 +# [axi4_master_driver_proxy] 24 +# [axi4_master_monitor_proxy] 32 +# [axi4_master_seq_item_conv_class] 624 +# [axi4_reg_predictor] 16 +# [basic_write_read_reg_test] 4 +# [master_vseq] 2 +# [slave_vseq] 1 +# [spi_slave_coverage] 1 +# [spi_slave_driver_bfm] 3 +# [spi_slave_monitor_bfm] 3 +# [spi_slave_monitor_proxy] 1 +# ** Note: $finish : /tools/mentor/questasim_10.6c/questasim/linux/../verilog_src/uvm-1.1d/src/base/uvm_root.svh(430) +# Time: 8330 ns Iteration: 53 Instance: /hvl_top +# Saving coverage database on exit... +# End time: 12:57:47 on Mar 11,2022, Elapsed time: 0:00:08 +# Errors: 0, Warnings: 15 diff --git a/snapshots/muneeb-mbytes_pulpino__spi_master__subsystem_verification_pr28/sim/questa_sim/basic_write_read_reg_test/basic_write_read_reg_test_coverage.ucdb b/snapshots/muneeb-mbytes_pulpino__spi_master__subsystem_verification_pr28/sim/questa_sim/basic_write_read_reg_test/basic_write_read_reg_test_coverage.ucdb new file mode 100644 index 0000000000000000000000000000000000000000..416c754ecaf6e0cfc43b27c9d6fc655245b16e5d Binary files /dev/null and b/snapshots/muneeb-mbytes_pulpino__spi_master__subsystem_verification_pr28/sim/questa_sim/basic_write_read_reg_test/basic_write_read_reg_test_coverage.ucdb differ diff --git a/snapshots/muneeb-mbytes_pulpino__spi_master__subsystem_verification_pr28/sim/questa_sim/basic_write_read_reg_test/html_cov_report/args.list b/snapshots/muneeb-mbytes_pulpino__spi_master__subsystem_verification_pr28/sim/questa_sim/basic_write_read_reg_test/html_cov_report/args.list new file mode 100644 index 0000000000000000000000000000000000000000..69e5697bf733efc62f281fc91a9cfad47ca93960 --- /dev/null +++ b/snapshots/muneeb-mbytes_pulpino__spi_master__subsystem_verification_pr28/sim/questa_sim/basic_write_read_reg_test/html_cov_report/args.list @@ -0,0 +1,5 @@ +-html +basic_write_read_reg_test/basic_write_read_reg_test_coverage.ucdb +-htmldir +basic_write_read_reg_test/html_cov_report +-details diff --git a/snapshots/muneeb-mbytes_pulpino__spi_master__subsystem_verification_pr28/sim/questa_sim/basic_write_read_reg_test/html_cov_report/covsummary.html b/snapshots/muneeb-mbytes_pulpino__spi_master__subsystem_verification_pr28/sim/questa_sim/basic_write_read_reg_test/html_cov_report/covsummary.html new file mode 100644 index 0000000000000000000000000000000000000000..59d8bcba22cff3a4dc88578dc93317e3d6b51232 --- /dev/null +++ b/snapshots/muneeb-mbytes_pulpino__spi_master__subsystem_verification_pr28/sim/questa_sim/basic_write_read_reg_test/html_cov_report/covsummary.html @@ -0,0 +1,381 @@ + + + + + Questa Coverage Report + + + + + + + +

Questa Coverage Report

+
Number of tests run:1
Passed:1
Warning:0
Error:0
Fatal:0
+

List of tests included in report...

+

List of global attributes included in report...

+

List of Design Units included in report...

+

Coverage Summary by Structure:

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Design ScopeHits %Coverage %
hvl_top100.00%100.00%
hdl_top17.56%35.53%
axi_intf14.00%14.00%
axi4_master_agent_bfm_h21.08%36.79%
spi_intf41.66%41.66%
s_axi_bus13.22%13.22%
DUT17.28%37.27%
spi_agent_bfm_h18.22%14.37%
spi_master_uvm_pkg18.80%29.17%
spi_master_apb_if__status43.24%42.52%
spi_master_apb_if__clkdiv15.84%24.12%
spi_master_apb_if__spicmd15.00%23.46%
spi_master_apb_if__spiadr15.00%23.46%
spi_master_apb_if__spilen9.82%26.71%
spi_master_apb_if__spidum10.84%24.72%
spi_master_apb_if__txfifo15.00%23.46%
spi_master_apb_if__rxfifo7.00%11.47%
spi_master_apb_if__intcfg18.68%35.08%
spi_master_apb_if_coverage38.00%26.21%
spi_master_apb_if/new100.00%100.00%
spi_master_apb_if/get_type0.00%0.00%
spi_master_apb_if/get_object_type0.00%0.00%
spi_master_apb_if/create0.00%0.00%
spi_master_apb_if/get_type_name0.00%0.00%
spi_master_apb_if/__m_uvm_field_automation0.00%0.00%
spi_master_apb_if/build97.67%75.00%
spi_master_apb_if/sample60.00%75.00%
axi4_master_pkg21.77%31.59%
axi4_master_tx/new100.00%100.00%
axi4_master_tx/get_type0.00%0.00%
axi4_master_tx/get_object_type0.00%0.00%
axi4_master_tx/create80.00%75.00%
axi4_master_tx/get_type_name100.00%100.00%
axi4_master_tx/__m_uvm_field_automation41.66%37.50%
axi4_master_tx/do_copy89.47%61.02%
axi4_master_tx/do_compare0.00%0.00%
axi4_master_tx/do_print54.76%52.63%
axi4_master_agent_config/new100.00%100.00%
axi4_master_agent_config/get_type0.00%0.00%
axi4_master_agent_config/get_object_type0.00%0.00%
axi4_master_agent_config/create0.00%0.00%
axi4_master_agent_config/get_type_name100.00%100.00%
axi4_master_agent_config/__m_uvm_field_automation25.00%25.00%
axi4_master_agent_config/do_print81.81%81.81%
axi4_master_agent_config/master_min_addr_range0.00%0.00%
axi4_master_agent_config/master_max_addr_range0.00%0.00%
axi4_master_seq_item_converter/new0.00%0.00%
axi4_master_seq_item_converter/get_type0.00%0.00%
axi4_master_seq_item_converter/get_object_type0.00%0.00%
axi4_master_seq_item_converter/create0.00%0.00%
axi4_master_seq_item_converter/get_type_name0.00%0.00%
axi4_master_seq_item_converter/__m_uvm_field_automation0.00%0.00%
axi4_master_seq_item_converter/from_write_class77.50%77.50%
axi4_master_seq_item_converter/from_read_class0.00%0.00%
axi4_master_seq_item_converter/to_write_class77.10%77.38%
axi4_master_seq_item_converter/to_read_class0.00%0.00%
axi4_master_seq_item_converter/to_write_addr_data_class88.57%83.33%
axi4_master_seq_item_converter/to_write_addr_data_resp_class82.85%75.00%
axi4_master_seq_item_converter/to_read_addr_data_class0.00%0.00%
axi4_master_seq_item_converter/do_print0.00%0.00%
axi4_master_cfg_converter/new0.00%0.00%
axi4_master_cfg_converter/get_type0.00%0.00%
axi4_master_cfg_converter/get_object_type0.00%0.00%
axi4_master_cfg_converter/create0.00%0.00%
axi4_master_cfg_converter/get_type_name0.00%0.00%
axi4_master_cfg_converter/__m_uvm_field_automation0.00%0.00%
axi4_master_cfg_converter/from_class100.00%100.00%
axi4_master_cfg_converter/do_print0.00%0.00%
axi4_master_adapter/new100.00%100.00%
axi4_master_adapter/get_type0.00%0.00%
axi4_master_adapter/get_object_type0.00%0.00%
axi4_master_adapter/create0.00%0.00%
axi4_master_adapter/get_type_name100.00%100.00%
axi4_master_adapter/__m_uvm_field_automation0.00%0.00%
axi4_master_adapter/reg2bus60.00%57.35%
axi4_master_adapter/bus2reg40.90%40.83%
axi4_master_write_sequencer/new100.00%100.00%
axi4_master_write_sequencer/get_type0.00%0.00%
axi4_master_write_sequencer/get_object_type0.00%0.00%
axi4_master_write_sequencer/get_type_name100.00%100.00%
axi4_master_write_sequencer/build_phase100.00%100.00%
axi4_master_write_sequencer/connect_phase100.00%100.00%
axi4_master_write_sequencer/end_of_elaboration_phase100.00%100.00%
axi4_master_write_sequencer/start_of_simulation_phase100.00%100.00%
axi4_master_read_sequencer/new100.00%100.00%
axi4_master_read_sequencer/get_type0.00%0.00%
axi4_master_read_sequencer/get_object_type0.00%0.00%
axi4_master_read_sequencer/get_type_name100.00%100.00%
axi4_master_read_sequencer/build_phase100.00%100.00%
axi4_master_read_sequencer/connect_phase100.00%100.00%
axi4_master_read_sequencer/end_of_elaboration_phase100.00%100.00%
axi4_master_read_sequencer/start_of_simulation_phase100.00%100.00%
axi4_master_driver_proxy/new100.00%100.00%
axi4_master_driver_proxy/get_type0.00%0.00%
axi4_master_driver_proxy/get_object_type0.00%0.00%
axi4_master_driver_proxy/get_type_name100.00%100.00%
axi4_master_driver_proxy/build_phase33.33%37.50%
axi4_master_driver_proxy/end_of_elaboration_phase100.00%100.00%
axi4_master_driver_proxy/run_phase100.00%100.00%
axi4_master_driver_proxy/axi4_write_task17.75%17.95%
axi4_master_driver_proxy/axi4_read_task2.53%2.63%
axi4_master_monitor_proxy/new100.00%100.00%
axi4_master_monitor_proxy/get_type0.00%0.00%
axi4_master_monitor_proxy/get_object_type0.00%0.00%
axi4_master_monitor_proxy/get_type_name100.00%100.00%
axi4_master_monitor_proxy/build_phase33.33%37.50%
axi4_master_monitor_proxy/connect_phase100.00%100.00%
axi4_master_monitor_proxy/end_of_elaboration_phase100.00%100.00%
axi4_master_monitor_proxy/run_phase100.00%100.00%
axi4_master_monitor_proxy/axi4_write_address90.00%75.00%
axi4_master_monitor_proxy/axi4_write_data85.71%75.00%
axi4_master_monitor_proxy/axi4_write_response90.90%75.00%
axi4_master_monitor_proxy/axi4_read_address30.00%18.75%
axi4_master_monitor_proxy/axi4_read_data30.00%18.75%
axi4_master_coverage3.04%47.84%
axi4_master_agent/new100.00%100.00%
axi4_master_agent/get_type0.00%0.00%
axi4_master_agent/get_object_type0.00%0.00%
axi4_master_agent/get_type_name100.00%100.00%
axi4_master_agent/build_phase62.50%62.50%
axi4_master_agent/connect_phase88.88%75.00%
axi4_reg_seq_pkg59.15%55.06%
axi4_master_reg_base_seq/new100.00%100.00%
axi4_master_reg_base_seq/get_type0.00%0.00%
axi4_master_reg_base_seq/get_object_type0.00%0.00%
axi4_master_reg_base_seq/create0.00%0.00%
axi4_master_reg_base_seq/get_type_name0.00%0.00%
axi4_master_reg_base_seq/__m_uvm_field_automation0.00%0.00%
axi4_master_basic_write_read_reg_seq/new100.00%100.00%
axi4_master_basic_write_read_reg_seq/get_type0.00%0.00%
axi4_master_basic_write_read_reg_seq/get_object_type0.00%0.00%
axi4_master_basic_write_read_reg_seq/create0.00%0.00%
axi4_master_basic_write_read_reg_seq/get_type_name100.00%100.00%
axi4_master_basic_write_read_reg_seq/__m_uvm_field_automation0.00%0.00%
axi4_master_basic_write_read_reg_seq/body81.00%75.00%
spi_slave_pkg18.75%14.81%
spi_slave_tx/new100.00%100.00%
spi_slave_tx/get_type0.00%0.00%
spi_slave_tx/get_object_type0.00%0.00%
spi_slave_tx/create0.00%0.00%
spi_slave_tx/get_type_name100.00%100.00%
spi_slave_tx/__m_uvm_field_automation0.00%0.00%
spi_slave_tx/do_copy0.00%0.00%
spi_slave_tx/do_compare0.00%0.00%
spi_slave_tx/do_print0.00%0.00%
spi_slave_agent_config/new100.00%100.00%
spi_slave_agent_config/get_type0.00%0.00%
spi_slave_agent_config/get_object_type0.00%0.00%
spi_slave_agent_config/create0.00%0.00%
spi_slave_agent_config/get_type_name100.00%100.00%
spi_slave_agent_config/__m_uvm_field_automation25.00%25.00%
spi_slave_agent_config/do_print100.00%100.00%
spi_slave_seq_item_converter/new0.00%0.00%
spi_slave_seq_item_converter/from_class0.00%0.00%
spi_slave_seq_item_converter/to_class0.00%0.00%
spi_slave_seq_item_converter/from_class_msb_first0.00%0.00%
spi_slave_seq_item_converter/do_print0.00%0.00%
spi_slave_cfg_converter/new0.00%0.00%
spi_slave_cfg_converter/get_type0.00%0.00%
spi_slave_cfg_converter/get_object_type0.00%0.00%
spi_slave_cfg_converter/create0.00%0.00%
spi_slave_cfg_converter/get_type_name0.00%0.00%
spi_slave_cfg_converter/__m_uvm_field_automation0.00%0.00%
spi_slave_cfg_converter/from_class0.00%0.00%
spi_slave_cfg_converter/do_print0.00%0.00%
spi_slave_sequencer/new100.00%100.00%
spi_slave_sequencer/get_type0.00%0.00%
spi_slave_sequencer/get_object_type0.00%0.00%
spi_slave_sequencer/get_type_name100.00%100.00%
spi_slave_driver_proxy/new100.00%100.00%
spi_slave_driver_proxy/get_type0.00%0.00%
spi_slave_driver_proxy/get_object_type0.00%0.00%
spi_slave_driver_proxy/get_type_name100.00%100.00%
spi_slave_driver_proxy/build_phase33.33%37.50%
spi_slave_driver_proxy/connect_phase100.00%100.00%
spi_slave_driver_proxy/end_of_elaboration_phase100.00%100.00%
spi_slave_driver_proxy/run_phase21.73%16.66%
spi_slave_driver_proxy/drive_to_bfm0.00%0.00%
spi_slave_driver_proxy/reset_detected0.00%0.00%
spi_slave_monitor_proxy/new100.00%100.00%
spi_slave_monitor_proxy/get_type0.00%0.00%
spi_slave_monitor_proxy/get_object_type0.00%0.00%
spi_slave_monitor_proxy/get_type_name100.00%100.00%
spi_slave_monitor_proxy/build_phase33.33%37.50%
spi_slave_monitor_proxy/end_of_elaboration_phase100.00%100.00%
spi_slave_monitor_proxy/run_phase31.81%27.67%
spi_slave_monitor_proxy/reset_detected0.00%0.00%
spi_slave_coverage5.05%35.71%
spi_slave_agent/new100.00%100.00%
spi_slave_agent/get_type0.00%0.00%
spi_slave_agent/get_object_type0.00%0.00%
spi_slave_agent/get_type_name100.00%100.00%
spi_slave_agent/build_phase57.14%60.41%
spi_slave_agent/connect_phase81.81%75.00%
pulpino_spi_master_subsystem_env_pkg69.09%65.00%
pulpino_spi_master_subsystem_env_config/new100.00%100.00%
pulpino_spi_master_subsystem_env_config/get_type0.00%0.00%
pulpino_spi_master_subsystem_env_config/get_object_type0.00%0.00%
pulpino_spi_master_subsystem_env_config/create0.00%0.00%
pulpino_spi_master_subsystem_env_config/get_type_name100.00%100.00%
pulpino_spi_master_subsystem_env_config/__m_uvm_field_automation25.00%25.00%
pulpino_spi_master_subsystem_env_config/do_print100.00%100.00%
axi4_reg_predictor/axi4_reg_predictor__1/new100.00%100.00%
axi4_reg_predictor/axi4_reg_predictor__1/get_type0.00%0.00%
axi4_reg_predictor/axi4_reg_predictor__1/get_object_type0.00%0.00%
axi4_reg_predictor/axi4_reg_predictor__1/write80.00%75.00%
pulpino_spi_master_subsystem_virtual_sequencer/new100.00%100.00%
pulpino_spi_master_subsystem_virtual_sequencer/get_type0.00%0.00%
pulpino_spi_master_subsystem_virtual_sequencer/get_object_type0.00%0.00%
pulpino_spi_master_subsystem_virtual_sequencer/get_type_name100.00%100.00%
pulpino_spi_master_subsystem_virtual_sequencer/build_phase100.00%100.00%
pulpino_spi_master_subsystem_scoreboard/new100.00%100.00%
pulpino_spi_master_subsystem_scoreboard/get_type0.00%0.00%
pulpino_spi_master_subsystem_scoreboard/get_object_type0.00%0.00%
pulpino_spi_master_subsystem_scoreboard/get_type_name100.00%100.00%
pulpino_spi_master_subsystem_scoreboard/build_phase100.00%100.00%
pulpino_spi_master_subsystem_scoreboard/run_phase100.00%100.00%
pulpino_spi_master_subsystem_scoreboard/check_phase100.00%100.00%
pulpino_spi_master_subsystem_scoreboard/report_phase100.00%100.00%
axi4_master_collector/new100.00%100.00%
axi4_master_collector/get_type0.00%0.00%
axi4_master_collector/get_object_type0.00%0.00%
axi4_master_collector/get_type_name100.00%100.00%
axi4_master_collector/build_phase100.00%100.00%
axi4_master_collector/write70.74%70.47%
spi_slave_collector/new100.00%100.00%
spi_slave_collector/get_type0.00%0.00%
spi_slave_collector/get_object_type0.00%0.00%
spi_slave_collector/get_type_name100.00%100.00%
spi_slave_collector/build_phase100.00%100.00%
spi_slave_collector/write0.00%0.00%
pulpino_spi_master_subsystem_env/new100.00%100.00%
pulpino_spi_master_subsystem_env/get_type0.00%0.00%
pulpino_spi_master_subsystem_env/get_object_type0.00%0.00%
pulpino_spi_master_subsystem_env/get_type_name100.00%100.00%
pulpino_spi_master_subsystem_env/build_phase68.42%64.20%
pulpino_spi_master_subsystem_env/connect_phase90.47%75.00%
spi_slave_seq_pkg8.92%8.92%
spi_slave_base_seq/new100.00%100.00%
spi_slave_base_seq/get_type0.00%0.00%
spi_slave_base_seq/get_object_type0.00%0.00%
spi_slave_base_seq/create0.00%0.00%
spi_slave_base_seq/get_type_name0.00%0.00%
spi_slave_base_seq/__m_uvm_field_automation0.00%0.00%
spi_fd_basic_slave_seq/new100.00%100.00%
spi_fd_basic_slave_seq/get_type0.00%0.00%
spi_fd_basic_slave_seq/get_object_type0.00%0.00%
spi_fd_basic_slave_seq/create0.00%0.00%
spi_fd_basic_slave_seq/get_type_name100.00%100.00%
spi_fd_basic_slave_seq/__m_uvm_field_automation0.00%0.00%
spi_fd_basic_slave_seq/body14.28%16.66%
axi4_master_seq_pkg0.00%0.00%
axi4_master_base_seq/new0.00%0.00%
axi4_master_base_seq/get_type0.00%0.00%
axi4_master_base_seq/get_object_type0.00%0.00%
axi4_master_base_seq/create0.00%0.00%
axi4_master_base_seq/get_type_name0.00%0.00%
axi4_master_base_seq/__m_uvm_field_automation0.00%0.00%
axi4_master_base_seq/body0.00%0.00%
axi4_master_basic_write_seq/new0.00%0.00%
axi4_master_basic_write_seq/get_type0.00%0.00%
axi4_master_basic_write_seq/get_object_type0.00%0.00%
axi4_master_basic_write_seq/create0.00%0.00%
axi4_master_basic_write_seq/get_type_name0.00%0.00%
axi4_master_basic_write_seq/__m_uvm_field_automation0.00%0.00%
axi4_master_basic_write_seq/body0.00%0.00%
axi4_master_basic_read_seq/new0.00%0.00%
axi4_master_basic_read_seq/get_type0.00%0.00%
axi4_master_basic_read_seq/get_object_type0.00%0.00%
axi4_master_basic_read_seq/create0.00%0.00%
axi4_master_basic_read_seq/get_type_name0.00%0.00%
axi4_master_basic_read_seq/__m_uvm_field_automation0.00%0.00%
axi4_master_basic_read_seq/body0.00%0.00%
pulpino_spi_master_subsystem_virtual_seq_pkg12.01%11.25%
virtual_base_seq/new100.00%100.00%
virtual_base_seq/get_type0.00%0.00%
virtual_base_seq/get_object_type0.00%0.00%
virtual_base_seq/create0.00%0.00%
virtual_base_seq/get_type_name0.00%0.00%
virtual_base_seq/__m_uvm_field_automation0.00%0.00%
virtual_base_seq/m_set_p_sequencer33.33%37.50%
virtual_base_seq/body42.85%45.83%
virtual_basic_write_read_reg_seq/new100.00%100.00%
virtual_basic_write_read_reg_seq/get_type0.00%0.00%
virtual_basic_write_read_reg_seq/get_object_type0.00%0.00%
virtual_basic_write_read_reg_seq/create0.00%0.00%
virtual_basic_write_read_reg_seq/get_type_name100.00%100.00%
virtual_basic_write_read_reg_seq/__m_uvm_field_automation0.00%0.00%
virtual_basic_write_read_reg_seq/body69.56%62.08%
virtual_basic_write_seq/new0.00%0.00%
virtual_basic_write_seq/get_type0.00%0.00%
virtual_basic_write_seq/get_object_type0.00%0.00%
virtual_basic_write_seq/create0.00%0.00%
virtual_basic_write_seq/get_type_name0.00%0.00%
virtual_basic_write_seq/__m_uvm_field_automation0.00%0.00%
virtual_basic_write_seq/body0.00%0.00%
virtual_basic_read_seq/new0.00%0.00%
virtual_basic_read_seq/get_type0.00%0.00%
virtual_basic_read_seq/get_object_type0.00%0.00%
virtual_basic_read_seq/create0.00%0.00%
virtual_basic_read_seq/get_type_name0.00%0.00%
virtual_basic_read_seq/__m_uvm_field_automation0.00%0.00%
virtual_basic_read_seq/body0.00%0.00%
virtual_reg_seq/new0.00%0.00%
virtual_reg_seq/get_type0.00%0.00%
virtual_reg_seq/get_object_type0.00%0.00%
virtual_reg_seq/create0.00%0.00%
virtual_reg_seq/get_type_name0.00%0.00%
virtual_reg_seq/__m_uvm_field_automation0.00%0.00%
virtual_reg_seq/body0.00%0.00%
pulpino_spi_master_subsystem_test_pkg57.44%48.48%
base_test/new100.00%100.00%
base_test/get_type0.00%0.00%
base_test/get_object_type0.00%0.00%
base_test/get_type_name0.00%0.00%
base_test/build_phase100.00%100.00%
base_test/setup_pulpino_spi_master_subsystem_env_config86.36%75.00%
base_test/setup_axi4_master_agent_config100.00%100.00%
base_test/setup_spi_slave_agent_config92.30%75.00%
base_test/end_of_elaboration_phase100.00%100.00%
base_test/run_phase0.00%0.00%
basic_write_read_reg_test/new100.00%100.00%
basic_write_read_reg_test/get_type0.00%0.00%
basic_write_read_reg_test/get_object_type0.00%0.00%
basic_write_read_reg_test/get_type_name100.00%100.00%
basic_write_read_reg_test/build_phase100.00%100.00%
basic_write_read_reg_test/connect_phase100.00%100.00%
basic_write_read_reg_test/end_of_elaboration_phase100.00%100.00%
basic_write_read_reg_test/start_of_simulation_phase100.00%100.00%
basic_write_read_reg_test/run_phase85.71%75.00%
basic_write_test/new0.00%0.00%
basic_write_test/get_type0.00%0.00%
basic_write_test/get_object_type0.00%0.00%
basic_write_test/get_type_name0.00%0.00%
basic_write_test/run_phase0.00%0.00%
axi4_simple_reg_test/new0.00%0.00%
axi4_simple_reg_test/get_type0.00%0.00%
axi4_simple_reg_test/get_object_type0.00%0.00%
axi4_simple_reg_test/get_type_name0.00%0.00%
axi4_simple_reg_test/build_phase0.00%0.00%
axi4_simple_reg_test/connect_phase0.00%0.00%
axi4_simple_reg_test/end_of_elaboration_phase0.00%0.00%
axi4_simple_reg_test/start_of_simulation_phase0.00%0.00%
axi4_simple_reg_test/run_phase0.00%0.00%
+

Coverage Summary by Type:

+ + + + + + + + + + + +
Total Coverage:18.63%29.19%
Coverage TypeBinsHitsMissesWeight% HitCoverage
Covergroups205263198913.07%12.38%
Statements303417811253158.70%58.70%
Branches16445081136130.90%30.90%
FEC Expressions782355129.48%29.48%
FEC Conditions1212497119.83%19.83%
Toggles22587308519502113.65%13.65%
FSMs1103872134.54%39.43%
States382117155.26%55.26%
Transitions721755123.61%23.61%
+
Report generated by Questa (ver. 10.6c) on Friday 11 March 2022 12:57:48 PM IST with command line:
 vcover report -html basic_write_read_reg_test/basic_write_read_reg_test_coverage.ucdb -htmldir basic_write_read_reg_test/html_cov_report -details
+ + + diff --git a/snapshots/muneeb-mbytes_pulpino__spi_master__subsystem_verification_pr28/sim/questa_sim/basic_write_read_reg_test/html_cov_report/css/covsummary.css b/snapshots/muneeb-mbytes_pulpino__spi_master__subsystem_verification_pr28/sim/questa_sim/basic_write_read_reg_test/html_cov_report/css/covsummary.css new file mode 100644 index 0000000000000000000000000000000000000000..de19410f7f624a1af8b884471f2b17e1a83416eb --- /dev/null +++ b/snapshots/muneeb-mbytes_pulpino__spi_master__subsystem_verification_pr28/sim/questa_sim/basic_write_read_reg_test/html_cov_report/css/covsummary.css @@ -0,0 +1,45 @@ +table, th, td { + border-width: 1px; + border-style: solid; +} +th.odd { + color: black; + background-color: #80CCCC; + font-weight: bold; +} +th.even { + color: black; + background-color: #90CCCC; + font-weight: bold; +} +td.odd { + color: black; + background-color: #EEEEEE; +} +td.even { + color: black; + background-color: #FAFAFA; +} +td.red { + color: white; + background-color: red; + text-align: center; + font-weight: bold; +} +td.yellow { + color: black; + background-color: yellow; + text-align: center; + font-weight: bold; +} +td.green { + color: white; + background-color: green; + text-align: center; + font-weight: bold; +} +pre.indent { + position: relative; + left: 10px; + top: 0px; +} diff --git a/snapshots/muneeb-mbytes_pulpino__spi_master__subsystem_verification_pr28/sim/questa_sim/basic_write_read_reg_test/html_cov_report/css/hdl2html.css b/snapshots/muneeb-mbytes_pulpino__spi_master__subsystem_verification_pr28/sim/questa_sim/basic_write_read_reg_test/html_cov_report/css/hdl2html.css new file mode 100644 index 0000000000000000000000000000000000000000..0906d1e45223a1c893f64a3e253b80455e521089 --- /dev/null +++ b/snapshots/muneeb-mbytes_pulpino__spi_master__subsystem_verification_pr28/sim/questa_sim/basic_write_read_reg_test/html_cov_report/css/hdl2html.css @@ -0,0 +1,45 @@ +#hdl2html { + color:black; background:white; +} +q-m { /* comment */ + color:green; +} +q-l { /* literal */ + color:red; +} +q-c { /* compile directive */ + color:purple; +} +q-w { /* keyword */ + color:blue; +} +q-t { /* key type */ + color:maroon; +} +q-a { /* key attribute */ + color:red; +} +q-v { /* key value */ + color:teal; +} +q-i { /* a link (for "include" statement) */ + color:red; +} +q-n { /* number line */ + color:red; +} + +/*** this is the old ucdb2html stuff that should eventually be deleted */ + +BODY { /* main_body */ + background:#FFFFFF; + color:#000000; +} + +/* verilog/vhdl language elements */ +SPAN.C { color:#0000FF; } /* comment */ +SPAN.K { color:#CC3300; } /* keyword */ +SPAN.S { color:#009900; } /* string */ +SPAN.T { color:#660033; } /* type */ +SPAN.A { color:RED; } /* attribute */ +SPAN.D { color:#AA0026; font-weight:bold; } /* Compiler Directives */ diff --git a/snapshots/muneeb-mbytes_pulpino__spi_master__subsystem_verification_pr28/sim/questa_sim/basic_write_read_reg_test/html_cov_report/css/mtitree.css b/snapshots/muneeb-mbytes_pulpino__spi_master__subsystem_verification_pr28/sim/questa_sim/basic_write_read_reg_test/html_cov_report/css/mtitree.css new file mode 100644 index 0000000000000000000000000000000000000000..f29d793a79ab0011f63a2bfc9b3c7a7740e51aa4 --- /dev/null +++ b/snapshots/muneeb-mbytes_pulpino__spi_master__subsystem_verification_pr28/sim/questa_sim/basic_write_read_reg_test/html_cov_report/css/mtitree.css @@ -0,0 +1,65 @@ +.header { + margin: 0; + background-color: #cccccc; +} + +.mtitree { + white-space: nowrap; + font-family: sans-serif; +} + +.mtitree img { + border-width: 0; + vertical-align: middle; +} + +.mtitree a { + color: black; + background-color: white; + border-style: none; + text-decoration: none; +} + +.mtitree a.underlineNode:hover { + text-decoration: underline; +} + +.mtitree a.node, +.mtitree a.nodeGray, +.mtitree a.nodeExcluded, +.mtitree a.nodeGraySel, +.mtitree a.nodeSel { + white-space: nowrap; +} + +.mtitree a.nodeSel { + color: white; + background-color: blue; +} + +.mtitree a.nodeGraySel { + color: gray; + background-color: blue; +} + +.mtitree a.nodeGray { + color: gray; +} + +.mtitree a.nodeExcluded { + color: gray; +} + +.mtitree .darknode { + white-space: nowrap; + color: gray; +} + +.mtitree .clip { + overflow: hidden; +} + +/* new look */ +.header_new { + background-color: white; +} diff --git a/snapshots/muneeb-mbytes_pulpino__spi_master__subsystem_verification_pr28/sim/questa_sim/basic_write_read_reg_test/html_cov_report/css/rank2html.css b/snapshots/muneeb-mbytes_pulpino__spi_master__subsystem_verification_pr28/sim/questa_sim/basic_write_read_reg_test/html_cov_report/css/rank2html.css new file mode 100644 index 0000000000000000000000000000000000000000..72950f4bc460d2f41d8b30be676c0bba271b2b03 --- /dev/null +++ b/snapshots/muneeb-mbytes_pulpino__spi_master__subsystem_verification_pr28/sim/questa_sim/basic_write_read_reg_test/html_cov_report/css/rank2html.css @@ -0,0 +1,130 @@ +table.tableTheme { + border-spacing: 0; + border-collapse: collapse; + border-style: none; + box-shadow: 0 1px 2px #d1d1d1; + -webkit-box-shadow: 0 1px 2px #d1d1d1; + -moz-box-shadow: 0 1px 2px #d1d1d1; + font-family: Helvetica, Arial, sans-serif; + font-size: 13px; +} +table.tableTheme td { + border-style: none; + border-radius: 0; /* no rounded corners */ + -webkit-border-radius: 0; + -moz-border-radius: 0; + padding: 8px 18px; +} + +table.tableTheme th { + border-style: none; + border-radius: 0; /* no rounded corners */ + -webkit-border-radius: 0; + -moz-border-radius: 0; + padding: 8px 18px; + font-weight: bold; + background-color: #90CCCC; +} + +table.tableTheme tr:first-child th:last-child { + border-top-right-radius:3px; + -webkit-border-top-right-radius:3px; + -moz-border-top-right-radius:3px; +} +table.tableTheme tr:first-child th:first-child { + border-top-left-radius:3px; + -webkit-border-top-left-radius:3px; + -moz-border-top-left-radius:3px; +} + +td.sumTableTd { + vertical-align: top; +} + +td.sumChartTd { + padding-left: 50px; +} + +td.sumLegendTd { + vertical-align: bottom; +} + +span.legendSpan { + padding-left: 2em; +} + +div.sumTableDiv { + width: 300px; +} + +div.rankdiv { + width: 100%; +} + +div.rankTableDiv { + width: 100%; +} + +td.right { + text-align: right; + white-space: nowrap; +} + +td.left { + text-align: left; +} + +tr.comp { + background-color: SkyBlue !important; +} + +tr.compstr { + background-color: LightSkyBlue !important; +} + +tr.cont { + background-color: PaleTurquoise !important; +} + +tr.contstr { + background-color: LightCyan !important; +} + +tr.noncont { + background-color: Gainsboro !important; +} + +tr.noncontstr { + background-color: LightGray !important; +} + +h2.rankBlockHeader { + background: gray; +} + +td.comp { + background-color: SkyBlue; +} + +td.cont { + background-color: PaleTurquoise; +} + +td.noncont { + background-color: Gainsboro; +} + +td.verAxisTd { + transform: rotate(270deg); +} + +td.horAxisTd { + text-align: center; +} + +span.nowrap { + white-space: nowrap; +} +span.nested { + padding-left: 2em; +} diff --git a/snapshots/muneeb-mbytes_pulpino__spi_master__subsystem_verification_pr28/sim/questa_sim/basic_write_read_reg_test/html_cov_report/css/testplan.css b/snapshots/muneeb-mbytes_pulpino__spi_master__subsystem_verification_pr28/sim/questa_sim/basic_write_read_reg_test/html_cov_report/css/testplan.css new file mode 100644 index 0000000000000000000000000000000000000000..92bcbf51ea1dc74e4d5c59663ce897e39069f5c1 --- /dev/null +++ b/snapshots/muneeb-mbytes_pulpino__spi_master__subsystem_verification_pr28/sim/questa_sim/basic_write_read_reg_test/html_cov_report/css/testplan.css @@ -0,0 +1,423 @@ +table, th { + border-width: 1px; + border-style: solid; +} + +table td { + /* default td is invisible, so we should undo that for any other td class */ + width: 20px; + border-width: 0; + border-style: none; +} + +th { + font-weight: bold; + background-color: #90CCCC; +} + +td.OddTd { + width: auto; + border-width: 1px; + border-style: solid; + + background-color: #EEEEEE; +} + +td.ExclOddTd { + width: auto; + border-width: 1px; + border-style: solid; + + background-color: #EEEEEE; + color:gray; +} + +td.ExclCntrOddTd { + width: auto; + border-width: 1px; + border-style: solid; + + background-color: #EEEEEE; + text-align: center; + color:gray; +} + +td.GrayRightOddTd { + width: auto; + border-width: 1px; + border-style: solid; + + background-color: #EEEEEE; + text-align: right; + color:gray; +} + +td.GrayCntrOddTd { + width: auto; + border-width: 1px; + border-style: solid; + + background-color: #EEEEEE; + text-align: center; + color:gray; +} + +td.GrayOddTd { + width: auto; + border-width: 1px; + border-style: solid; + + background-color: #EEEEEE; + color:gray; +} + +td.GrayRightEvenTd { + width: auto; + border-width: 1px; + border-style: solid; + + background-color: #FAFAFA; + text-align: right; + color:gray; +} + +td.GrayCntrEvenTd { + width: auto; + border-width: 1px; + border-style: solid; + + background-color: #FAFAFA; + text-align: center; + color:gray; +} + +td.GrayEvenTd { + width: auto; + border-width: 1px; + border-style: solid; + + background-color: #FAFAFA; + color:gray; +} +td.GrayRightOddTgTd { + width: auto; + border: 2px solid #9ac1c9; + background: url(../images/linkbg_odd.gif); + + text-align: right; + color:gray; +} + +td.GrayCntrOddTgTd { + width: auto; + border: 2px solid #9ac1c9; + background: url(../images/linkbg_odd.gif); + text-align: center; + color:gray; +} + +td.GrayOddTgTd { + width: auto; + border: 2px solid #9ac1c9; + background: url(../images/linkbg_odd.gif); + color:gray; +} + +td.GrayRightEvenTgTd { + width: auto; + border: 2px solid #9ac1c9; + background: url(../images/linkbg_even.gif); + text-align: right; + color:gray; +} + +td.GrayCntrEvenTgTd { + width: auto; + border: 2px solid #9ac1c9; + background: url(../images/linkbg_even.gif); + text-align: center; + color:gray; +} + +td.GrayEvenTgTd { + width: auto; + border: 2px solid #9ac1c9; + background: url(../images/linkbg_even.gif); + color:gray; +} + +td.CntrOddTd { /* odd - center text alignment */ + width: auto; + border-width: 1px; + border-style: solid; + + background-color: #EEEEEE; + text-align: center; +} + + +td.RightOddTd { /* odd - right text alignment */ + width: auto; + border-width: 1px; + border-style: solid; + + background-color: #EEEEEE; + text-align: right; +} + + +td.ExclCntrOddTd { /* odd - center text alignment */ + width: auto; + border-width: 1px; + border-style: solid; + + background-color: #EEEEEE; + text-align: center; + color:gray; +} + +td.EvenTd { + width: auto; + border-width: 1px; + border-style: solid; + + background-color: #FAFAFA; +} + +td.ExclEvenTd { + width: auto; + border-width: 1px; + border-style: solid; + + background-color: #FAFAFA; + color: gray; +} + +td.ExclCntrEvenTd { + width: auto; + border-width: 1px; + border-style: solid; + + background-color: #FAFAFA; + text-align: center; + color: gray; +} + +td.CntrEvenTd { /* even - center text alignment */ + width: auto; + border-width: 1px; + border-style: solid; + + background-color: #FAFAFA; + text-align: center; +} + +td.RightEvenTd { /* even - right text alignment */ + width: auto; + border-width: 1px; + border-style: solid; + + background-color: #FAFAFA; + text-align: right; +} + +td.ExclCntrEven { /* even - center text alignment */ + width: auto; + border-width: 1px; + border-style: solid; + + background-color: #FAFAFA; + text-align: center; + color:gray; +} + +td.bgRed { + width: auto; + border-width: 1px; + border-style: solid; + + color: white; + background-color: red; + font-weight: bold; + text-align: center; +} + +td.bgYellow { + width: auto; + border-width: 1px; + border-style: solid; + + color: black; + background-color: yellow; + font-weight: bold; + text-align: center; +} + +td.bgGreen { + width: auto; + border-width: 1px; + border-style: solid; + + color: white; + background-color: green; + font-weight: bold; + text-align: center; +} + +table.noborder { + border-style: none; +} + +div.pageHeaderDiv { + position: fixed; + background-color: black; + width: 100%; + top: 0; + left: 0; +} + +td.OddTgTd { /* tagged item td odd */ + width: auto; + border: 2px solid #9ac1c9; + background: url(../images/linkbg_odd.gif); +} + +td.ExclOddTgTd { /* excluded tagged item td odd */ + width: auto; + border: 2px solid #9ac1c9; + background: url(../images/linkbg_odd.gif); + color: gray; +} + +td.MissingOddTgTd { /* missing tagged item td odd */ + width: auto; + border: 2px solid #9ac1c9; + background: url(../images/linkbg_odd.gif); + color: red; +} + +td.EvenTgTd { /* tagged item td even */ + width: auto; + border: 2px solid #9ac1c9; + background: url(../images/linkbg_even.gif); +} + +td.ExclEvenTgTd { /* excluded tagged item td even */ + width: auto; + border: 2px solid #9ac1c9; + background: url(../images/linkbg_even.gif); + color: gray; +} + +td.MissingEvenTgTd { /* missing tagged item td even */ + width: auto; + border: 2px solid #9ac1c9; + background: url(../images/linkbg_even.gif); + color: red; +} + +td.CntrOddTgTd { /* tagged item td odd - Center text alignment */ + width: auto; + border: 2px solid #9ac1c9; + background: url(../images/linkbg_odd.gif); + text-align: center; +} + +td.ExclCntrOddTgTd { /* excluded tagged item td odd - Center text alignment */ + width: auto; + border: 2px solid #9ac1c9; + background: url(../images/linkbg_odd.gif); + text-align: center; + color: gray; +} + +td.MissingCntrOddTgTd { /* missing tagged item td odd - Center text alignment */ + width: auto; + border: 2px solid #9ac1c9; + background: url(../images/linkbg_odd.gif); + text-align: center; + color: red; +} + +td.CntrEvenTgTd { /* tagged item td even - Center text alignment */ + width: auto; + border: 2px solid #9ac1c9; + background: url(../images/linkbg_even.gif); + text-align: center; +} + +td.ExclCntrEvenTgTd { /* excluded tagged item td even - Center text alignment */ + width: auto; + border: 2px solid #9ac1c9; + background: url(../images/linkbg_even.gif); + text-align: center; + color: gray; +} + +td.MissingCntrEvenTgTd { /* missing tagged item td even - Center text alignment */ + width: auto; + border: 2px solid #9ac1c9; + background: url(../images/linkbg_even.gif); + text-align: center; + color: red; +} + +div.tpD { /* tpItem Div */ + display:inline; +} + +div.btnD { /* button Div */ + cursor:pointer; + display:inline; + vertical-align:middle; +} + +div.dimBtnD { /* dimmed button Div */ + display:inline; + vertical-align:middle; +} + +textarea.EvenTxtBox { + border:0; + background-color:#FAFAFA; + font-family:Serif; +} + +textarea.ExclEvenTxtBox { + border:0; + background-color:#FAFAFA; + font-family:Serif; + color:gray; +} + +textarea.GrayEvenTxtBox { + border:0; + background-color:#FAFAFA; + font-family:Serif; + color:gray; +} + +textarea.OddTxtBox { + border:0; + background-color:#EEEEEE; + font-family:Serif; +} + + +textarea.ExclOddTxtBox { + border:0; + background-color:#EEEEEE; + font-family:Serif; + color:gray; +} + +textarea.GrayOddTxtBox { + border:0; + background-color:#EEEEEE; + font-family:Serif; + color:gray; +} + +tr.fpTr { /* full path tr */ + display:none; +} diff --git a/snapshots/muneeb-mbytes_pulpino__spi_master__subsystem_verification_pr28/sim/questa_sim/basic_write_read_reg_test/html_cov_report/css/ucdb2html.css b/snapshots/muneeb-mbytes_pulpino__spi_master__subsystem_verification_pr28/sim/questa_sim/basic_write_read_reg_test/html_cov_report/css/ucdb2html.css new file mode 100644 index 0000000000000000000000000000000000000000..293335f8559b8f409f63a7cf9d895f996b9131d2 --- /dev/null +++ b/snapshots/muneeb-mbytes_pulpino__spi_master__subsystem_verification_pr28/sim/questa_sim/basic_write_read_reg_test/html_cov_report/css/ucdb2html.css @@ -0,0 +1,623 @@ +/* + * Base colors (id's are assigned to 'body' tag) + */ + +#ucdb2html_index { + color: black; + background-color: white; +} + +#ucdb2html_summary { + color: black; + background-color: white; +} + +#ucdb2html_detail { + color: black; + background-color: white; +} + +#loc_rec_tables { + border-color: white; +} + +#loc_rec_tables td,th{ + border-color: white; +} + +/* + * Common styles (summary and detail pages) + * + * To override a style for just one of the page types: + * ucdb2html_index Top-level index and title pages + * ucdb2html_summary Scope/testplan summary pages + * ucdb2html_detail Coverage detail pages + * add the page id designator to the style statement. + * + * Example: + * + * To change the background of "yellow" coverage percent + * cells, add the following style to the stylesheet: + * + * #ucdb2html_detail td.bgYellow { + * color: white; + * background-color: silver; + * font-weight: bold; + * } + */ + +table.tableTheme { + border-spacing: 0; + border-collapse: collapse; + border-style: none; + box-shadow: 0 1px 2px #d1d1d1; + -webkit-box-shadow: 0 1px 2px #d1d1d1; + -moz-box-shadow: 0 1px 2px #d1d1d1; + font-family: Helvetica, Arial, sans-serif; + font-size: 13px; +} +table.tableTheme td, table.tableTheme th { + border-style: none; + border-radius: 0; /* no rounded corners */ + -webkit-border-radius: 0; + -moz-border-radius: 0; + padding: 8px 18px; +} +table.tableTheme tr:first-child th:last-child { + border-top-right-radius:3px; + -webkit-border-top-right-radius:3px; + -moz-border-top-right-radius:3px; +} +table.tableTheme tr:first-child th:first-child { + border-top-left-radius:3px; + -webkit-border-top-left-radius:3px; + -moz-border-top-left-radius:3px; +} + +a.stmt_testdata:link { /* the link for pertest.htm in stmt details page */ + color:#FFFFFF; +} +a.stmt_testdata:visited { /* the link for pertest.htm in stmt details page */ + color:#A0A0A0; +} + +td.cvg_details_l { /* covergroups details left column */ + padding-right:5px; + border-style:none; /* no borders */ +} + +td.cvg_details_r { /* covergroups details right column */ + padding-left:5px; + border-style:none; /* no borders */ + text-align:right; +} + +table.nude, td.nude { + padding: 0; + border-style: none; /* table with no borders */ + border-spacing: 0; + border-collapse: collapse; +} + +table, th, td { + border-width: 1px; + border-style: solid; +} + +th { + font-weight: bold; + background-color: #90CCCC; +} + +table, th, td { + -webkit-border-radius: .3em; + -moz-border-radius: .3em; + border-radius: .3em; +} + +table { + border-color: lightgrey; +} + +th, td { + border-color: darkGrey; +} + +td.sharpEdge { + -webkit-border-radius: 0; + -moz-border-radius: 0; + border-radius: 0; +} + +td.stmtNoCvgBlock { + font-weight:bold; + height: 4em; +} + +tr.lightBlue { + background-color: #D3D3F2; +} + +th.clickable { + cursor: pointer; +} + +td.invisible { + /* This invisible cell force the background to be white + we need to do this so that we keep these indentation + cells out of the row color. + + There is another class called invisible_nobg to make + indentation but following a same background of the row. + */ + width: 20px; + border-width: 0; + background-color: #FFFFFF; +} + +td.invisible_nobg { + width: 20px; + border-width: 0; +} + +td.odd, td.odd_r, td.odd_rGrey , td.odd_c { + background-color: #EEEEEE; +} + +td.even, td.even_r, td.even_rGrey. td.even_c { + background-color: #FAFAFA; +} + +td.odd, td.even , td.even_c, td.odd_c { + color: #000000; +} + +td.odd_r, td.even_r, td.odd_rGrey, td.even_rGrey { + color: #000000; +} + + +td.odd_r, td.even_r, td.odd_rGrey, td.even_rGrey { + text-align: right; +} + +td.even_rGrey, td.odd_rGrey { + color: dimGrey; +} + +td.even_c, td.odd_c { + text-align: center; +} + +td.evenGrey { + color: dimGrey; + background-color: #FAFAFA; +} + +td.evenRed { + color: red; + background-color: #FAFAFA; +} + +td.oddGrey { + color: dimGrey; + background-color: #EEEEEE; +} + +td.oddRed { + color: red; + background-color: #EEEEEE; +} + +td.red { + color: red; + text-align: center; + font-weight: bold; +} + +td.grey { + text-align: center; + font-weight: bold; + color: white; + background-color: dimGrey; +} + +td.green { + color: green; + text-align: center; + font-weight: bold; +} + +td.bgRed, td.bgRed_r { + color: red; + background-color: rgb(255,247,247); + font-weight: bold; +} + +td.bgYellow, td.bgYellow_r { + color: black; + background-color: rgb(253,255,231); + font-weight: bold; +} + +td.bgGreen, td.bgGreen_r { + color: black; + background-color: rgb(231,255,235); + font-weight: bold; +} + +td.bgRed, td.bgYellow, td.bgGreen { + text-align: center; +} + +td.bgRed_r, td.bgYellow_r, td.bgGreen_r { + text-align: right; +} + +/* + * Coverage detail source listings (based on hdl2html) + */ + +table.src { + table-layout: fixed; + border-width: 0; +} + +table.src pre { + display: inline; /* we need this to remove the blank space added above/under + * the pre element. This blank space is added by default + * because, by default the pre element has "display: block". + * Changing "block" to "inline" will fix the problem. + */ +} + +textarea.exclEvenTxtBox { + border:0; + background-color:#FAFAFA; + font-family:Serif; + color:gray; +} + +textarea.exclOddTxtBox { + border:0; + background-color:#EEEEEE; + font-family:Serif; + color:gray; +} + +textarea.oddTxtBox { + border:0; + background-color:#EEEEEE; + font-family:Serif; +} + +td.srcL { + border-width: 0; + width: 50px; + color: red; + text-align: right; + font-family: monospace; +} + +td.srcS { + border-width: 0; + width: 50px; + color: red; + text-align: left; + font-family: monospace; +} + +td.sN { + border-width: 0; + width: 50px; + padding-right: 10px; + text-align: right; + font-family: monospace; +} + +td.sY { + border-width: 0; + width: 50px; + padding-right: 10px; + text-align: right; + font-family: monospace; +} + +td.sR { + border-width: 0; + width: 50px; + padding-right: 10px; + color: white; + background-color: red; + text-align: right; + font-family: monospace; +} + +td.sG { + border-width: 0; + width: 50px; + padding-right: 10px; + color: white; + background-color: green; + text-align: right; + font-family: monospace; +} + +td.sE { + border-width: 0; + width: 50px; + padding-right: 10px; + color: white; + background-color: dimGrey; + text-align: right; + font-family: monospace; +} + +td.srcN { + white-space: pre; + border-width: 0; + font-family: monospace; +} + +td.srcR { + white-space: pre; + border-width: 0; + color: white; + background-color: red; + font-family: monospace; +} + +td.srcY { + white-space: pre; + border-width: 0; + background-color: yellow; + font-family: monospace; +} + +td.srcG { + white-space: pre; + border-width: 0; + color: white; + background-color: green; + font-family: monospace; +} + +td.srcE { + white-space: pre; + border-width: 0; + color: white; + background-color: dimGrey; + font-family: monospace; +} + +/* + * Keyword highlighting styles -- these are not currently + * used because they could clash with the coverage bgcolor + * styles -- we need to expand these to take into account + * the "parent" span. + +#ucdb2html_detail span.comment { + color: green; +} +#ucdb2html_detail span.literal { + color: red; +} +#ucdb2html_detail span.compile { + color: purple; +} +#ucdb2html_detail span.keyword { + color: blue; +} +#ucdb2html_detail span.keytype { + color: maroon; +} +#ucdb2html_detail span.keyattr { + color: red; +} +#ucdb2html_detail span.keyvalu { + color: orange; +} + * + */ + +/* + * Hovering tooltips (for toggle detail page) + */ + +a:hover { + position: relative; +} + +a span { + display: none; +} + +a:hover span { + display: block; + position: absolute; + top: 10px; + left: 0; + padding: 5px; + margin: 10px; + z-index: 100; + background: #f0f0f0; + border: 1px dotted #c0c0c0; + opacity: 0.9; +} + +/* + * Buttons to show/hide detailed coverage items + */ + +table.buttons { + border-style: none; + background-color: white; +} + +td.button_on, +td.button_off { + border-style: outset; + font-weight: bold; + text-align: center; +} + +td.button_on { + color: white; + background-color: blue; +} + +td.button_off { + color: #a9a9a9; + background-color: #696969; +} + +td.button_on1, +td.button_off1 { + border-style: outset; + font-weight: bold; + text-align: center; +} + +/* + * ModelSim/Questa logo styles (lower-left frame) + * + * Note: ModelSim logo is slightly less tall than Questa logo + * so the "padding" centers each in the allotted frame. + */ + +#ucdb2html_model_logo { + background-color: white; +} + +#ucdb2html_model_logo img { + border-style: none; + padding: 12px; +} + +#ucdb2html_questa_logo { + background-color: black; +} + +#ucdb2html_questa_logo img { + border-style: none; + padding: 5px; +} + +/* *** The following classes introduced after merging all coverage types in a single page *** */ +table.fpw { /* fill Page Width Table */ + width: 100%; /* needed to force the table to occupy all the page */ + background-color: #D0D0D0; + border-style: none; + -webkit-border-radius: 0; + -moz-border-radius: 0; + border-radius: 0; +} + +td.styleNone { + border-style: none; +} + +/* currently; the following classes are used in covergroup details page only */ +tr.e { /* excluded row */ + color: dimGrey; +} + +td.R { /* red cell */ + color: red; + background-color: rgb(255,247,247); + font-weight: bold; +} + +td.Y { /* Yello cell */ + color: black; + background-color: rgb(253,255,231); + font-weight: bold; +} + +td.G { /* green cell */ + color: black; + background-color: rgb(231,255,235); + font-weight: bold; +} + +td.x { /* excluded cell */ + text-align: center; + font-weight: bold; + color: white; + background-color: dimGrey; +} +tr.v { /* even row. used in pertest.htm */ + background-color: #EEEEEE; +} +/* ****************** + * The following are used in the new cvg page after it has been redesigned + */ +.nested { + padding-left: 2em; +} +.handMouse { + /* When mouse hovers over this item, it takes the hand shape (hyperlink) */ + + /* we need the following 2 values to handle different browsers */ + cursor:pointer; + cursor:hand; +} +.fontBold { + font-weight: bold; +} +.nowrap { + /* This one is used by the row in the cvg type/inst table, in the span @ the + * instance cell. + * Notice that the library "DataTables" has its own "nowrap" class. So, don't + * mix between both. + */ + white-space: nowrap; +} +.grayFont { + color: #AAAAAA; +} + +/* This class 'whiteGrayRows' is used to create an alternating row colors table (black & white) */ +table.whiteGrayRows tr:nth-child(even) { + background-color: #ffffff; +} +table.whiteGrayRows tr:nth-child(odd) { + background-color: #f9f9f9; +} + +/* This class 'cvpcrs' is for the table that holds cvp/crs comulative numbers */ +table.cvpcrs tr td:FIRST-CHILD, +table.cvpcrs tr th:FIRST-CHILD { + text-align: left; +} +table.cvpcrs tr th+th, +table.cvpcrs tr td+td { + /* starting from 2nd TD (column), all TDs will be right aligned */ + text-align: right; +} +table.cvpcrs tr+tr+tr { + /* starting from 3rd row, all TRs will be this color */ + background-color: #f9f9f9 +} + +ul.noList { + /* a list that ha no indentation and no bullets */ + list-style-type:none; + padding-left:0; +} + +.truncate { + border: 1px solid transparent; +} +.truncate:hover { + border-color: #BBBBBB; +} + +tr.cvggroup { /* green cell */ + background-color: #DDDDDD !important; + font-weight: bold; +} + +div.htmlFormatedCmnt { + border: 1px solid #BBBBBB; +} diff --git a/snapshots/muneeb-mbytes_pulpino__spi_master__subsystem_verification_pr28/sim/questa_sim/basic_write_read_reg_test/html_cov_report/css/ucdb2htmlP.css b/snapshots/muneeb-mbytes_pulpino__spi_master__subsystem_verification_pr28/sim/questa_sim/basic_write_read_reg_test/html_cov_report/css/ucdb2htmlP.css new file mode 100644 index 0000000000000000000000000000000000000000..ccc58f376cca98d46b53f4e1a874a03f0b41a8c1 --- /dev/null +++ b/snapshots/muneeb-mbytes_pulpino__spi_master__subsystem_verification_pr28/sim/questa_sim/basic_write_read_reg_test/html_cov_report/css/ucdb2htmlP.css @@ -0,0 +1,225 @@ +/* + * Base colors (id's are assigned to 'body' tag) + */ + +#ucdb2html_index { + color: black; + background-color: white; +} + +#ucdb2html_summary { + color: black; + background-color: white; +} + +#ucdb2html_detail { + color: black; + background-color: white; +} + +/* + * Common styles (summary and detail pages) + * + * To override a style for just one of the page types: + * ucdb2html_index Top-level index and title pages + * ucdb2html_summary Scope/testplan summary pages + * ucdb2html_detail Coverage detail pages + * add the page id designator to the style statement. + * + * Example: + * + * To change the background of "yellow" coverage percent + * cells, add the following style to the stylesheet: + * + * #ucdb2html_detail td.bgGreen { + * color: white; + * background-color: silver; + * font-weight: bold; + * } + */ + +table, th, td { + border-width: 1px; + border-style: solid; +} + +th { + font-weight: bold; +} + +td.invisible { + border-width: 0; +} + +td.odd_r, td.even_r { + text-align: right; +} + +td.red { + color: red; + text-align: center; + font-weight: bold; +} + +td.green { + color: green; + text-align: center; + font-weight: bold; +} + +td.bgRed, td.bgRed_r { + color: red; + font-weight: bold; +} + +td.bgYellow, td.bgYellow_r { + color: #FFA500; + font-weight: bold; +} + +td.bgGreen, td.bgGreen_r { + color: green; + font-weight: bold; +} + +td.bgRed, td.bgYellow, td.bgGreen { + text-align: center; +} + +td.bgRed_r, td.bgYellow_r, td.bgGreen_r { + text-align: right; +} + +/* + * Coverage detail source listings (based on hdl2html) + */ + +table.src { + table-layout: fixed; + border-width: 0; +} + +td.srcLine { + border-width: 0; + width: 50px; + color: red; + text-align: right; + font-family: monospace; +} + +td.srcStmt { + border-width: 0; + width: 50px; + color: red; + text-align: left; + font-family: monospace; +} + +td.covNorm { + border-width: 0; + width: 50px; + padding-right: 10px; + text-align: right; + font-family: monospace; +} + +td.covRed { + border-width: 0; + width: 50px; + padding-right: 10px; + color: red; + text-align: right; + font-family: monospace; +} + +td.covGreen { + border-width: 0; + width: 50px; + padding-right: 10px; + color: green; + text-align: right; + font-family: monospace; +} + +td.srcNorm { + border-width: 0; + font-family: monospace; +} + +td.srcRed { + border-width: 0; + color: red; + font-family: monospace; +} + +td.srcYellow { + border-width: 0; + color: #FFA500; + font-family: monospace; +} + +td.srcGreen { + border-width: 0; + color: green; + font-family: monospace; +} + +/* + * Keyword highlighting styles -- these are not currently + * used because they could clash with the coverage bgcolor + * styles -- we need to expand these to take into account + * the "parent" span. + +#ucdb2html_detail span.comment { + color: green; +} +#ucdb2html_detail span.literal { + color: red; +} +#ucdb2html_detail span.compile { + color: purple; +} +#ucdb2html_detail span.keyword { + color: blue; +} +#ucdb2html_detail span.keytype { + color: maroon; +} +#ucdb2html_detail span.keyattr { + color: red; +} +#ucdb2html_detail span.keyvalu { + color: orange; +} + * + */ + +/* + * Disable show/hide buttons on printed output + */ + +table.buttons { + display: none; +} + +/* + * ModelSim/Questa logo styles (lower-left frame) + */ + +#ucdb2html_model_logo { + background-color: white; +} + +#ucdb2html_model_logo img { + border-style: none; + padding: 12px; +} + +#ucdb2html_questa_logo { + background-color: black; +} + +#ucdb2html_questa_logo img { + border-style: none; + padding: 10px; +} diff --git a/snapshots/muneeb-mbytes_pulpino__spi_master__subsystem_verification_pr28/sim/questa_sim/basic_write_read_reg_test/html_cov_report/css/ucdb2html_newlook.css b/snapshots/muneeb-mbytes_pulpino__spi_master__subsystem_verification_pr28/sim/questa_sim/basic_write_read_reg_test/html_cov_report/css/ucdb2html_newlook.css new file mode 100644 index 0000000000000000000000000000000000000000..e3acc9f4596986d267fa918a6ea81f326672cdde --- /dev/null +++ b/snapshots/muneeb-mbytes_pulpino__spi_master__subsystem_verification_pr28/sim/questa_sim/basic_write_read_reg_test/html_cov_report/css/ucdb2html_newlook.css @@ -0,0 +1,39 @@ +/* Customize look */ +/*background color for odd cells*/ +td.odd, td.odd_r, td.odd_rGrey, td.oddGrey { + /*background-color: #A0CFEC;*/ +} + +/*background color for even cells*/ +td.even, td.even_r, td.even_rGrey, td.evenGrey { + /*background-color: #87AFC7;*/ +} + +/*text color for odd and even cells*/ +td.odd, td.even, td.odd_r, td.even_r, td.odd_rGrey, td.even_rGrey { + /*color: #000000;*/ +} +/**************************************************************************************/ +/*text color and background color for excluded cells*/ +td.grey { + /*color: white;*/ + /*background-color: dimGrey;*/ +} + +/*text color and background color for missed cells*/ +td.bgRed, td.bgRed_r { + /*color: red;*/ + /*background-color: rgb(255,247,247);*/ +} + +/*text color and background color for yellow cells*/ +td.bgYellow, td.bgYellow_r { + /*color: black;*/ + /*background-color: rgb(253,255,231);*/ +} + +/*text color and background color for covered cells*/ +td.bgGreen, td.bgGreen_r { + /*color: black;*/ + /*background-color: rgb(231,255,235);*/ +} diff --git a/snapshots/muneeb-mbytes_pulpino__spi_master__subsystem_verification_pr28/sim/questa_sim/basic_write_read_reg_test/html_cov_report/dulist.html b/snapshots/muneeb-mbytes_pulpino__spi_master__subsystem_verification_pr28/sim/questa_sim/basic_write_read_reg_test/html_cov_report/dulist.html new file mode 100644 index 0000000000000000000000000000000000000000..23ac0b33ce6cd6836f460bfb3374ccddd495ef2f --- /dev/null +++ b/snapshots/muneeb-mbytes_pulpino__spi_master__subsystem_verification_pr28/sim/questa_sim/basic_write_read_reg_test/html_cov_report/dulist.html @@ -0,0 +1,24 @@ + + + + + Questa Coverage Report + + + + + + + + + + + + + diff --git a/snapshots/muneeb-mbytes_pulpino__spi_master__subsystem_verification_pr28/sim/questa_sim/basic_write_read_reg_test/html_cov_report/global.json b/snapshots/muneeb-mbytes_pulpino__spi_master__subsystem_verification_pr28/sim/questa_sim/basic_write_read_reg_test/html_cov_report/global.json new file mode 100644 index 0000000000000000000000000000000000000000..d38d0f05ce8c62dfd120c2f9ec8a910ccaad5570 --- /dev/null +++ b/snapshots/muneeb-mbytes_pulpino__spi_master__subsystem_verification_pr28/sim/questa_sim/basic_write_read_reg_test/html_cov_report/global.json @@ -0,0 +1,8 @@ +var g_oCONST = {}; +g_oCONST['genDetailsCovergroup'] = 1; +g_assertDebug = 0; +g_oCONST['prod'] = 'Questa'; +g_oCONST['gBinObjIdx'] = {type:0,name:1,cvps:2,cmnt:3,parentId:4,parentType:5,parentFileNum:6,parentName:7,hdlHash:8,hdlPath:9,binArr:10,autoBinArr:11}; +g_oCONST['gBinArrIdx'] = {type:0,atLeast:1,h:2,isRed:3,name:4}; +g_assertViews = 0; +g_directViews = 0; diff --git a/snapshots/muneeb-mbytes_pulpino__spi_master__subsystem_verification_pr28/sim/questa_sim/basic_write_read_reg_test/html_cov_report/globattrlist.html b/snapshots/muneeb-mbytes_pulpino__spi_master__subsystem_verification_pr28/sim/questa_sim/basic_write_read_reg_test/html_cov_report/globattrlist.html new file mode 100644 index 0000000000000000000000000000000000000000..0dd15e5346e6770d560160517874c8e8576a9b09 --- /dev/null +++ b/snapshots/muneeb-mbytes_pulpino__spi_master__subsystem_verification_pr28/sim/questa_sim/basic_write_read_reg_test/html_cov_report/globattrlist.html @@ -0,0 +1,18 @@ + + + + + Questa Coverage Report + + + + + +

Questa Coverage Report

+

Global Attributes included in report:

+ + + +
Global Attributes
AttributeValue
UCDB_TOGGLE_REPORT_FORMAT1
+ + diff --git a/snapshots/muneeb-mbytes_pulpino__spi_master__subsystem_verification_pr28/sim/questa_sim/basic_write_read_reg_test/html_cov_report/index.html b/snapshots/muneeb-mbytes_pulpino__spi_master__subsystem_verification_pr28/sim/questa_sim/basic_write_read_reg_test/html_cov_report/index.html new file mode 100644 index 0000000000000000000000000000000000000000..533a816d55a8e1350d5f3e97293e91f88c8891a6 --- /dev/null +++ b/snapshots/muneeb-mbytes_pulpino__spi_master__subsystem_verification_pr28/sim/questa_sim/basic_write_read_reg_test/html_cov_report/index.html @@ -0,0 +1,23 @@ + + + + + Questa Coverage Report + + + + +

Your browser does not support JavaScript!

+

+ This report works best when viewed with a browser which supports JavaScript. + Either your browser does not support JavaScript or you may have disabled JavaScript + support. In about 5 seconds you should be re-directed to a version of this report + which does not use JavaScript (or frames). If you are not redirected, please + click here. If you have any questions, please contact + MTI Customer Support.

+ + diff --git a/snapshots/muneeb-mbytes_pulpino__spi_master__subsystem_verification_pr28/sim/questa_sim/basic_write_read_reg_test/html_cov_report/legacy.html b/snapshots/muneeb-mbytes_pulpino__spi_master__subsystem_verification_pr28/sim/questa_sim/basic_write_read_reg_test/html_cov_report/legacy.html new file mode 100644 index 0000000000000000000000000000000000000000..33df9136ec6767ca1e187b3d4b2fe4dcc42148b4 --- /dev/null +++ b/snapshots/muneeb-mbytes_pulpino__spi_master__subsystem_verification_pr28/sim/questa_sim/basic_write_read_reg_test/html_cov_report/legacy.html @@ -0,0 +1,1218 @@ + + + + + Questa Coverage Report + + +

Questa Coverage Report

+

Contents:

 + +

Testplan hierarchy:

+

Back to top...

+ +

Design hierarchy:

+

Back to top...

+ +

Design units:

+

Back to top...

+ + + diff --git a/snapshots/muneeb-mbytes_pulpino__spi_master__subsystem_verification_pr28/sim/questa_sim/basic_write_read_reg_test/html_cov_report/lib/Chart/Chart.js b/snapshots/muneeb-mbytes_pulpino__spi_master__subsystem_verification_pr28/sim/questa_sim/basic_write_read_reg_test/html_cov_report/lib/Chart/Chart.js new file mode 100644 index 0000000000000000000000000000000000000000..7aa61fec71c9d7dc7b33a77b2ca3471761c14236 --- /dev/null +++ b/snapshots/muneeb-mbytes_pulpino__spi_master__subsystem_verification_pr28/sim/questa_sim/basic_write_read_reg_test/html_cov_report/lib/Chart/Chart.js @@ -0,0 +1,3726 @@ +/*! + * Chart.js + * http://chartjs.org/ + * Version: 1.0.2 + * + * Copyright 2015 Nick Downie + * Released under the MIT license + * https://github.com/nnnick/Chart.js/blob/master/LICENSE.md + */ + + +(function(){ + + "use strict"; + + //Declare root variable - window in the browser, global on the server + var root = this, + previous = root.Chart; + + //Occupy the global variable of Chart, and create a simple base class + var Chart = function(context){ + var chart = this; + this.canvas = context.canvas; + + this.ctx = context; + + //Variables global to the chart + var computeDimension = function(element,dimension) + { + if (element['offset'+dimension]) + { + return element['offset'+dimension]; + } + else + { + return document.defaultView.getComputedStyle(element).getPropertyValue(dimension); + } + }; + + var width = this.width = computeDimension(context.canvas,'Width') || context.canvas.width; + var height = this.height = computeDimension(context.canvas,'Height') || context.canvas.height; + + width = this.width = context.canvas.width; + height = this.height = context.canvas.height; + this.aspectRatio = this.width / this.height; + //High pixel density displays - multiply the size of the canvas height/width by the device pixel ratio, then scale. + helpers.retinaScale(this); + + return this; + }; + //Globally expose the defaults to allow for user updating/changing + Chart.defaults = { + global: { + // Boolean - Whether to animate the chart + animation: true, + + // Number - Number of animation steps + animationSteps: 60, + + // String - Animation easing effect + animationEasing: "easeOutQuart", + + // Boolean - If we should show the scale at all + showScale: true, + + // Boolean - If we want to override with a hard coded scale + scaleOverride: false, + + // ** Required if scaleOverride is true ** + // Number - The number of steps in a hard coded scale + scaleSteps: null, + // Number - The value jump in the hard coded scale + scaleStepWidth: null, + // Number - The scale starting value + scaleStartValue: null, + + // String - Colour of the scale line + scaleLineColor: "rgba(0,0,0,.1)", + + // Number - Pixel width of the scale line + scaleLineWidth: 1, + + // Boolean - Whether to show labels on the scale + scaleShowLabels: true, + + // Interpolated JS string - can access value + scaleLabel: "<%=value%>", + + // Boolean - Whether the scale should stick to integers, and not show any floats even if drawing space is there + scaleIntegersOnly: true, + + // Boolean - Whether the scale should start at zero, or an order of magnitude down from the lowest value + scaleBeginAtZero: false, + + // String - Scale label font declaration for the scale label + scaleFontFamily: "'Helvetica Neue', 'Helvetica', 'Arial', sans-serif", + + // Number - Scale label font size in pixels + scaleFontSize: 12, + + // String - Scale label font weight style + scaleFontStyle: "normal", + + // String - Scale label font colour + scaleFontColor: "#666", + + // Boolean - whether or not the chart should be responsive and resize when the browser does. + responsive: false, + + // Boolean - whether to maintain the starting aspect ratio or not when responsive, if set to false, will take up entire container + maintainAspectRatio: true, + + // Boolean - Determines whether to draw tooltips on the canvas or not - attaches events to touchmove & mousemove + showTooltips: true, + + // Boolean - Determines whether to draw built-in tooltip or call custom tooltip function + customTooltips: false, + + // Array - Array of string names to attach tooltip events + tooltipEvents: ["mousemove", "touchstart", "touchmove", "mouseout"], + + // String - Tooltip background colour + tooltipFillColor: "rgba(0,0,0,0.8)", + + // String - Tooltip label font declaration for the scale label + tooltipFontFamily: "'Helvetica Neue', 'Helvetica', 'Arial', sans-serif", + + // Number - Tooltip label font size in pixels + tooltipFontSize: 14, + + // String - Tooltip font weight style + tooltipFontStyle: "normal", + + // String - Tooltip label font colour + tooltipFontColor: "#fff", + + // String - Tooltip title font declaration for the scale label + tooltipTitleFontFamily: "'Helvetica Neue', 'Helvetica', 'Arial', sans-serif", + + // Number - Tooltip title font size in pixels + tooltipTitleFontSize: 14, + + // String - Tooltip title font weight style + tooltipTitleFontStyle: "bold", + + // String - Tooltip title font colour + tooltipTitleFontColor: "#fff", + + // String - Tooltip title template + tooltipTitleTemplate: "<%= label%>", + + // Number - pixel width of padding around tooltip text + tooltipYPadding: 6, + + // Number - pixel width of padding around tooltip text + tooltipXPadding: 6, + + // Number - Size of the caret on the tooltip + tooltipCaretSize: 8, + + // Number - Pixel radius of the tooltip border + tooltipCornerRadius: 6, + + // Number - Pixel offset from point x to tooltip edge + tooltipXOffset: 10, + + // String - Template string for single tooltips + tooltipTemplate: "<%if (label){%><%=label%>: <%}%><%= value %>", + + // String - Template string for single tooltips + multiTooltipTemplate: "<%= value %>", + + // String - Colour behind the legend colour block + multiTooltipKeyBackground: '#fff', + + // Array - A list of colors to use as the defaults + segmentColorDefault: ["#A6CEE3", "#1F78B4", "#B2DF8A", "#33A02C", "#FB9A99", "#E31A1C", "#FDBF6F", "#FF7F00", "#CAB2D6", "#6A3D9A", "#B4B482", "#B15928" ], + + // Array - A list of highlight colors to use as the defaults + segmentHighlightColorDefaults: [ "#CEF6FF", "#47A0DC", "#DAFFB2", "#5BC854", "#FFC2C1", "#FF4244", "#FFE797", "#FFA728", "#F2DAFE", "#9265C2", "#DCDCAA", "#D98150" ], + + // Function - Will fire on animation progression. + onAnimationProgress: function(){}, + + // Function - Will fire on animation completion. + onAnimationComplete: function(){} + + } + }; + + //Create a dictionary of chart types, to allow for extension of existing types + Chart.types = {}; + + //Global Chart helpers object for utility methods and classes + var helpers = Chart.helpers = {}; + + //-- Basic js utility methods + var each = helpers.each = function(loopable,callback,self){ + var additionalArgs = Array.prototype.slice.call(arguments, 3); + // Check to see if null or undefined firstly. + if (loopable){ + if (loopable.length === +loopable.length){ + var i; + for (i=0; i= 0; i--) { + var currentItem = arrayToSearch[i]; + if (filterCallback(currentItem)){ + return currentItem; + } + } + }, + inherits = helpers.inherits = function(extensions){ + //Basic javascript inheritance based on the model created in Backbone.js + var parent = this; + var ChartElement = (extensions && extensions.hasOwnProperty("constructor")) ? extensions.constructor : function(){ return parent.apply(this, arguments); }; + + var Surrogate = function(){ this.constructor = ChartElement;}; + Surrogate.prototype = parent.prototype; + ChartElement.prototype = new Surrogate(); + + ChartElement.extend = inherits; + + if (extensions) extend(ChartElement.prototype, extensions); + + ChartElement.__super__ = parent.prototype; + + return ChartElement; + }, + noop = helpers.noop = function(){}, + uid = helpers.uid = (function(){ + var id=0; + return function(){ + return "chart-" + id++; + }; + })(), + warn = helpers.warn = function(str){ + //Method for warning of errors + if (window.console && typeof window.console.warn === "function") console.warn(str); + }, + amd = helpers.amd = (typeof define === 'function' && define.amd), + //-- Math methods + isNumber = helpers.isNumber = function(n){ + return !isNaN(parseFloat(n)) && isFinite(n); + }, + max = helpers.max = function(array){ + return Math.max.apply( Math, array ); + }, + min = helpers.min = function(array){ + return Math.min.apply( Math, array ); + }, + cap = helpers.cap = function(valueToCap,maxValue,minValue){ + if(isNumber(maxValue)) { + if( valueToCap > maxValue ) { + return maxValue; + } + } + else if(isNumber(minValue)){ + if ( valueToCap < minValue ){ + return minValue; + } + } + return valueToCap; + }, + getDecimalPlaces = helpers.getDecimalPlaces = function(num){ + if (num%1!==0 && isNumber(num)){ + var s = num.toString(); + if(s.indexOf("e-") < 0){ + // no exponent, e.g. 0.01 + return s.split(".")[1].length; + } + else if(s.indexOf(".") < 0) { + // no decimal point, e.g. 1e-9 + return parseInt(s.split("e-")[1]); + } + else { + // exponent and decimal point, e.g. 1.23e-9 + var parts = s.split(".")[1].split("e-"); + return parts[0].length + parseInt(parts[1]); + } + } + else { + return 0; + } + }, + toRadians = helpers.radians = function(degrees){ + return degrees * (Math.PI/180); + }, + // Gets the angle from vertical upright to the point about a centre. + getAngleFromPoint = helpers.getAngleFromPoint = function(centrePoint, anglePoint){ + var distanceFromXCenter = anglePoint.x - centrePoint.x, + distanceFromYCenter = anglePoint.y - centrePoint.y, + radialDistanceFromCenter = Math.sqrt( distanceFromXCenter * distanceFromXCenter + distanceFromYCenter * distanceFromYCenter); + + + var angle = Math.PI * 2 + Math.atan2(distanceFromYCenter, distanceFromXCenter); + + //If the segment is in the top left quadrant, we need to add another rotation to the angle + if (distanceFromXCenter < 0 && distanceFromYCenter < 0){ + angle += Math.PI*2; + } + + return { + angle: angle, + distance: radialDistanceFromCenter + }; + }, + aliasPixel = helpers.aliasPixel = function(pixelWidth){ + return (pixelWidth % 2 === 0) ? 0 : 0.5; + }, + splineCurve = helpers.splineCurve = function(FirstPoint,MiddlePoint,AfterPoint,t){ + //Props to Rob Spencer at scaled innovation for his post on splining between points + //http://scaledinnovation.com/analytics/splines/aboutSplines.html + var d01=Math.sqrt(Math.pow(MiddlePoint.x-FirstPoint.x,2)+Math.pow(MiddlePoint.y-FirstPoint.y,2)), + d12=Math.sqrt(Math.pow(AfterPoint.x-MiddlePoint.x,2)+Math.pow(AfterPoint.y-MiddlePoint.y,2)), + fa=t*d01/(d01+d12),// scaling factor for triangle Ta + fb=t*d12/(d01+d12); + return { + inner : { + x : MiddlePoint.x-fa*(AfterPoint.x-FirstPoint.x), + y : MiddlePoint.y-fa*(AfterPoint.y-FirstPoint.y) + }, + outer : { + x: MiddlePoint.x+fb*(AfterPoint.x-FirstPoint.x), + y : MiddlePoint.y+fb*(AfterPoint.y-FirstPoint.y) + } + }; + }, + calculateOrderOfMagnitude = helpers.calculateOrderOfMagnitude = function(val){ + return Math.floor(Math.log(val) / Math.LN10); + }, + calculateScaleRange = helpers.calculateScaleRange = function(valuesArray, drawingSize, textSize, startFromZero, integersOnly){ + + //Set a minimum step of two - a point at the top of the graph, and a point at the base + var minSteps = 2, + maxSteps = Math.floor(drawingSize/(textSize * 1.5)), + skipFitting = (minSteps >= maxSteps); + + var maxValue = max(valuesArray), + minValue = min(valuesArray); + + // We need some degree of separation here to calculate the scales if all the values are the same + // Adding/minusing 0.5 will give us a range of 1. + if (maxValue === minValue){ + maxValue += 0.5; + // So we don't end up with a graph with a negative start value if we've said always start from zero + if (minValue >= 0.5 && !startFromZero){ + minValue -= 0.5; + } + else{ + // Make up a whole number above the values + maxValue += 0.5; + } + } + + var valueRange = Math.abs(maxValue - minValue), + rangeOrderOfMagnitude = calculateOrderOfMagnitude(valueRange), + graphMax = Math.ceil(maxValue / (1 * Math.pow(10, rangeOrderOfMagnitude))) * Math.pow(10, rangeOrderOfMagnitude), + graphMin = (startFromZero) ? 0 : Math.floor(minValue / (1 * Math.pow(10, rangeOrderOfMagnitude))) * Math.pow(10, rangeOrderOfMagnitude), + graphRange = graphMax - graphMin, + stepValue = Math.pow(10, rangeOrderOfMagnitude), + numberOfSteps = Math.round(graphRange / stepValue); + + //If we have more space on the graph we'll use it to give more definition to the data + while((numberOfSteps > maxSteps || (numberOfSteps * 2) < maxSteps) && !skipFitting) { + if(numberOfSteps > maxSteps){ + stepValue *=2; + numberOfSteps = Math.round(graphRange/stepValue); + // Don't ever deal with a decimal number of steps - cancel fitting and just use the minimum number of steps. + if (numberOfSteps % 1 !== 0){ + skipFitting = true; + } + } + //We can fit in double the amount of scale points on the scale + else{ + //If user has declared ints only, and the step value isn't a decimal + if (integersOnly && rangeOrderOfMagnitude >= 0){ + //If the user has said integers only, we need to check that making the scale more granular wouldn't make it a float + if(stepValue/2 % 1 === 0){ + stepValue /=2; + numberOfSteps = Math.round(graphRange/stepValue); + } + //If it would make it a float break out of the loop + else{ + break; + } + } + //If the scale doesn't have to be an int, make the scale more granular anyway. + else{ + stepValue /=2; + numberOfSteps = Math.round(graphRange/stepValue); + } + + } + } + + if (skipFitting){ + numberOfSteps = minSteps; + stepValue = graphRange / numberOfSteps; + } + + return { + steps : numberOfSteps, + stepValue : stepValue, + min : graphMin, + max : graphMin + (numberOfSteps * stepValue) + }; + + }, + /* jshint ignore:start */ + // Blows up jshint errors based on the new Function constructor + //Templating methods + //Javascript micro templating by John Resig - source at http://ejohn.org/blog/javascript-micro-templating/ + template = helpers.template = function(templateString, valuesObject){ + + // If templateString is function rather than string-template - call the function for valuesObject + + if(templateString instanceof Function){ + return templateString(valuesObject); + } + + var cache = {}; + function tmpl(str, data){ + // Figure out if we're getting a template, or if we need to + // load the template - and be sure to cache the result. + var fn = !/\W/.test(str) ? + cache[str] = cache[str] : + + // Generate a reusable function that will serve as a template + // generator (and which will be cached). + new Function("obj", + "var p=[],print=function(){p.push.apply(p,arguments);};" + + + // Introduce the data as local variables using with(){} + "with(obj){p.push('" + + + // Convert the template into pure JavaScript + str + .replace(/[\r\t\n]/g, " ") + .split("<%").join("\t") + .replace(/((^|%>)[^\t]*)'/g, "$1\r") + .replace(/\t=(.*?)%>/g, "',$1,'") + .split("\t").join("');") + .split("%>").join("p.push('") + .split("\r").join("\\'") + + "');}return p.join('');" + ); + + // Provide some basic currying to the user + return data ? fn( data ) : fn; + } + return tmpl(templateString,valuesObject); + }, + /* jshint ignore:end */ + generateLabels = helpers.generateLabels = function(templateString,numberOfSteps,graphMin,stepValue){ + var labelsArray = new Array(numberOfSteps); + if (templateString){ + each(labelsArray,function(val,index){ + labelsArray[index] = template(templateString,{value: (graphMin + (stepValue*(index+1)))}); + }); + } + return labelsArray; + }, + //--Animation methods + //Easing functions adapted from Robert Penner's easing equations + //http://www.robertpenner.com/easing/ + easingEffects = helpers.easingEffects = { + linear: function (t) { + return t; + }, + easeInQuad: function (t) { + return t * t; + }, + easeOutQuad: function (t) { + return -1 * t * (t - 2); + }, + easeInOutQuad: function (t) { + if ((t /= 1 / 2) < 1){ + return 1 / 2 * t * t; + } + return -1 / 2 * ((--t) * (t - 2) - 1); + }, + easeInCubic: function (t) { + return t * t * t; + }, + easeOutCubic: function (t) { + return 1 * ((t = t / 1 - 1) * t * t + 1); + }, + easeInOutCubic: function (t) { + if ((t /= 1 / 2) < 1){ + return 1 / 2 * t * t * t; + } + return 1 / 2 * ((t -= 2) * t * t + 2); + }, + easeInQuart: function (t) { + return t * t * t * t; + }, + easeOutQuart: function (t) { + return -1 * ((t = t / 1 - 1) * t * t * t - 1); + }, + easeInOutQuart: function (t) { + if ((t /= 1 / 2) < 1){ + return 1 / 2 * t * t * t * t; + } + return -1 / 2 * ((t -= 2) * t * t * t - 2); + }, + easeInQuint: function (t) { + return 1 * (t /= 1) * t * t * t * t; + }, + easeOutQuint: function (t) { + return 1 * ((t = t / 1 - 1) * t * t * t * t + 1); + }, + easeInOutQuint: function (t) { + if ((t /= 1 / 2) < 1){ + return 1 / 2 * t * t * t * t * t; + } + return 1 / 2 * ((t -= 2) * t * t * t * t + 2); + }, + easeInSine: function (t) { + return -1 * Math.cos(t / 1 * (Math.PI / 2)) + 1; + }, + easeOutSine: function (t) { + return 1 * Math.sin(t / 1 * (Math.PI / 2)); + }, + easeInOutSine: function (t) { + return -1 / 2 * (Math.cos(Math.PI * t / 1) - 1); + }, + easeInExpo: function (t) { + return (t === 0) ? 1 : 1 * Math.pow(2, 10 * (t / 1 - 1)); + }, + easeOutExpo: function (t) { + return (t === 1) ? 1 : 1 * (-Math.pow(2, -10 * t / 1) + 1); + }, + easeInOutExpo: function (t) { + if (t === 0){ + return 0; + } + if (t === 1){ + return 1; + } + if ((t /= 1 / 2) < 1){ + return 1 / 2 * Math.pow(2, 10 * (t - 1)); + } + return 1 / 2 * (-Math.pow(2, -10 * --t) + 2); + }, + easeInCirc: function (t) { + if (t >= 1){ + return t; + } + return -1 * (Math.sqrt(1 - (t /= 1) * t) - 1); + }, + easeOutCirc: function (t) { + return 1 * Math.sqrt(1 - (t = t / 1 - 1) * t); + }, + easeInOutCirc: function (t) { + if ((t /= 1 / 2) < 1){ + return -1 / 2 * (Math.sqrt(1 - t * t) - 1); + } + return 1 / 2 * (Math.sqrt(1 - (t -= 2) * t) + 1); + }, + easeInElastic: function (t) { + var s = 1.70158; + var p = 0; + var a = 1; + if (t === 0){ + return 0; + } + if ((t /= 1) == 1){ + return 1; + } + if (!p){ + p = 1 * 0.3; + } + if (a < Math.abs(1)) { + a = 1; + s = p / 4; + } else{ + s = p / (2 * Math.PI) * Math.asin(1 / a); + } + return -(a * Math.pow(2, 10 * (t -= 1)) * Math.sin((t * 1 - s) * (2 * Math.PI) / p)); + }, + easeOutElastic: function (t) { + var s = 1.70158; + var p = 0; + var a = 1; + if (t === 0){ + return 0; + } + if ((t /= 1) == 1){ + return 1; + } + if (!p){ + p = 1 * 0.3; + } + if (a < Math.abs(1)) { + a = 1; + s = p / 4; + } else{ + s = p / (2 * Math.PI) * Math.asin(1 / a); + } + return a * Math.pow(2, -10 * t) * Math.sin((t * 1 - s) * (2 * Math.PI) / p) + 1; + }, + easeInOutElastic: function (t) { + var s = 1.70158; + var p = 0; + var a = 1; + if (t === 0){ + return 0; + } + if ((t /= 1 / 2) == 2){ + return 1; + } + if (!p){ + p = 1 * (0.3 * 1.5); + } + if (a < Math.abs(1)) { + a = 1; + s = p / 4; + } else { + s = p / (2 * Math.PI) * Math.asin(1 / a); + } + if (t < 1){ + return -0.5 * (a * Math.pow(2, 10 * (t -= 1)) * Math.sin((t * 1 - s) * (2 * Math.PI) / p));} + return a * Math.pow(2, -10 * (t -= 1)) * Math.sin((t * 1 - s) * (2 * Math.PI) / p) * 0.5 + 1; + }, + easeInBack: function (t) { + var s = 1.70158; + return 1 * (t /= 1) * t * ((s + 1) * t - s); + }, + easeOutBack: function (t) { + var s = 1.70158; + return 1 * ((t = t / 1 - 1) * t * ((s + 1) * t + s) + 1); + }, + easeInOutBack: function (t) { + var s = 1.70158; + if ((t /= 1 / 2) < 1){ + return 1 / 2 * (t * t * (((s *= (1.525)) + 1) * t - s)); + } + return 1 / 2 * ((t -= 2) * t * (((s *= (1.525)) + 1) * t + s) + 2); + }, + easeInBounce: function (t) { + return 1 - easingEffects.easeOutBounce(1 - t); + }, + easeOutBounce: function (t) { + if ((t /= 1) < (1 / 2.75)) { + return 1 * (7.5625 * t * t); + } else if (t < (2 / 2.75)) { + return 1 * (7.5625 * (t -= (1.5 / 2.75)) * t + 0.75); + } else if (t < (2.5 / 2.75)) { + return 1 * (7.5625 * (t -= (2.25 / 2.75)) * t + 0.9375); + } else { + return 1 * (7.5625 * (t -= (2.625 / 2.75)) * t + 0.984375); + } + }, + easeInOutBounce: function (t) { + if (t < 1 / 2){ + return easingEffects.easeInBounce(t * 2) * 0.5; + } + return easingEffects.easeOutBounce(t * 2 - 1) * 0.5 + 1 * 0.5; + } + }, + //Request animation polyfill - http://www.paulirish.com/2011/requestanimationframe-for-smart-animating/ + requestAnimFrame = helpers.requestAnimFrame = (function(){ + return window.requestAnimationFrame || + window.webkitRequestAnimationFrame || + window.mozRequestAnimationFrame || + window.oRequestAnimationFrame || + window.msRequestAnimationFrame || + function(callback) { + return window.setTimeout(callback, 1000 / 60); + }; + })(), + cancelAnimFrame = helpers.cancelAnimFrame = (function(){ + return window.cancelAnimationFrame || + window.webkitCancelAnimationFrame || + window.mozCancelAnimationFrame || + window.oCancelAnimationFrame || + window.msCancelAnimationFrame || + function(callback) { + return window.clearTimeout(callback, 1000 / 60); + }; + })(), + animationLoop = helpers.animationLoop = function(callback,totalSteps,easingString,onProgress,onComplete,chartInstance){ + + var currentStep = 0, + easingFunction = easingEffects[easingString] || easingEffects.linear; + + var animationFrame = function(){ + currentStep++; + var stepDecimal = currentStep/totalSteps; + var easeDecimal = easingFunction(stepDecimal); + + callback.call(chartInstance,easeDecimal,stepDecimal, currentStep); + onProgress.call(chartInstance,easeDecimal,stepDecimal); + if (currentStep < totalSteps){ + chartInstance.animationFrame = requestAnimFrame(animationFrame); + } else{ + onComplete.apply(chartInstance); + } + }; + requestAnimFrame(animationFrame); + }, + //-- DOM methods + getRelativePosition = helpers.getRelativePosition = function(evt){ + var mouseX, mouseY; + var e = evt.originalEvent || evt, + canvas = evt.currentTarget || evt.srcElement, + boundingRect = canvas.getBoundingClientRect(); + + if (e.touches){ + mouseX = e.touches[0].clientX - boundingRect.left; + mouseY = e.touches[0].clientY - boundingRect.top; + + } + else{ + mouseX = e.clientX - boundingRect.left; + mouseY = e.clientY - boundingRect.top; + } + + return { + x : mouseX, + y : mouseY + }; + + }, + addEvent = helpers.addEvent = function(node,eventType,method){ + if (node.addEventListener){ + node.addEventListener(eventType,method); + } else if (node.attachEvent){ + node.attachEvent("on"+eventType, method); + } else { + node["on"+eventType] = method; + } + }, + removeEvent = helpers.removeEvent = function(node, eventType, handler){ + if (node.removeEventListener){ + node.removeEventListener(eventType, handler, false); + } else if (node.detachEvent){ + node.detachEvent("on"+eventType,handler); + } else{ + node["on" + eventType] = noop; + } + }, + bindEvents = helpers.bindEvents = function(chartInstance, arrayOfEvents, handler){ + // Create the events object if it's not already present + if (!chartInstance.events) chartInstance.events = {}; + + each(arrayOfEvents,function(eventName){ + chartInstance.events[eventName] = function(){ + handler.apply(chartInstance, arguments); + }; + addEvent(chartInstance.chart.canvas,eventName,chartInstance.events[eventName]); + }); + }, + unbindEvents = helpers.unbindEvents = function (chartInstance, arrayOfEvents) { + each(arrayOfEvents, function(handler,eventName){ + removeEvent(chartInstance.chart.canvas, eventName, handler); + }); + }, + getMaximumWidth = helpers.getMaximumWidth = function(domNode){ + var container = domNode.parentNode, + padding = parseInt(getStyle(container, 'padding-left')) + parseInt(getStyle(container, 'padding-right')); + // TODO = check cross browser stuff with this. + return container.clientWidth - padding; + }, + getMaximumHeight = helpers.getMaximumHeight = function(domNode){ + var container = domNode.parentNode, + padding = parseInt(getStyle(container, 'padding-bottom')) + parseInt(getStyle(container, 'padding-top')); + // TODO = check cross browser stuff with this. + return container.clientHeight - padding; + }, + getStyle = helpers.getStyle = function (el, property) { + return el.currentStyle ? + el.currentStyle[property] : + document.defaultView.getComputedStyle(el, null).getPropertyValue(property); + }, + getMaximumSize = helpers.getMaximumSize = helpers.getMaximumWidth, // legacy support + retinaScale = helpers.retinaScale = function(chart){ + var ctx = chart.ctx, + width = chart.canvas.width, + height = chart.canvas.height; + + if (window.devicePixelRatio) { + ctx.canvas.style.width = width + "px"; + ctx.canvas.style.height = height + "px"; + ctx.canvas.height = height * window.devicePixelRatio; + ctx.canvas.width = width * window.devicePixelRatio; + ctx.scale(window.devicePixelRatio, window.devicePixelRatio); + } + }, + //-- Canvas methods + clear = helpers.clear = function(chart){ + chart.ctx.clearRect(0,0,chart.width,chart.height); + }, + fontString = helpers.fontString = function(pixelSize,fontStyle,fontFamily){ + return fontStyle + " " + pixelSize+"px " + fontFamily; + }, + longestText = helpers.longestText = function(ctx,font,arrayOfStrings){ + ctx.font = font; + var longest = 0; + each(arrayOfStrings,function(string){ + var textWidth = ctx.measureText(string).width; + longest = (textWidth > longest) ? textWidth : longest; + }); + return longest; + }, + drawRoundedRectangle = helpers.drawRoundedRectangle = function(ctx,x,y,width,height,radius){ + ctx.beginPath(); + ctx.moveTo(x + radius, y); + ctx.lineTo(x + width - radius, y); + ctx.quadraticCurveTo(x + width, y, x + width, y + radius); + ctx.lineTo(x + width, y + height - radius); + ctx.quadraticCurveTo(x + width, y + height, x + width - radius, y + height); + ctx.lineTo(x + radius, y + height); + ctx.quadraticCurveTo(x, y + height, x, y + height - radius); + ctx.lineTo(x, y + radius); + ctx.quadraticCurveTo(x, y, x + radius, y); + ctx.closePath(); + }; + + + //Store a reference to each instance - allowing us to globally resize chart instances on window resize. + //Destroy method on the chart will remove the instance of the chart from this reference. + Chart.instances = {}; + + Chart.Type = function(data,options,chart){ + this.options = options; + this.chart = chart; + this.id = uid(); + //Add the chart instance to the global namespace + Chart.instances[this.id] = this; + + // Initialize is always called when a chart type is created + // By default it is a no op, but it should be extended + if (options.responsive){ + this.resize(); + } + this.initialize.call(this,data); + }; + + //Core methods that'll be a part of every chart type + extend(Chart.Type.prototype,{ + initialize : function(){return this;}, + clear : function(){ + clear(this.chart); + return this; + }, + stop : function(){ + // Stops any current animation loop occuring + Chart.animationService.cancelAnimation(this); + return this; + }, + resize : function(callback){ + this.stop(); + var canvas = this.chart.canvas, + newWidth = getMaximumWidth(this.chart.canvas), + newHeight = this.options.maintainAspectRatio ? newWidth / this.chart.aspectRatio : getMaximumHeight(this.chart.canvas); + + canvas.width = this.chart.width = newWidth; + canvas.height = this.chart.height = newHeight; + + retinaScale(this.chart); + + if (typeof callback === "function"){ + callback.apply(this, Array.prototype.slice.call(arguments, 1)); + } + return this; + }, + reflow : noop, + render : function(reflow){ + if (reflow){ + this.reflow(); + } + + if (this.options.animation && !reflow){ + var animation = new Chart.Animation(); + animation.numSteps = this.options.animationSteps; + animation.easing = this.options.animationEasing; + + // render function + animation.render = function(chartInstance, animationObject) { + var easingFunction = helpers.easingEffects[animationObject.easing]; + var stepDecimal = animationObject.currentStep / animationObject.numSteps; + var easeDecimal = easingFunction(stepDecimal); + + chartInstance.draw(easeDecimal, stepDecimal, animationObject.currentStep); + }; + + // user events + animation.onAnimationProgress = this.options.onAnimationProgress; + animation.onAnimationComplete = this.options.onAnimationComplete; + + Chart.animationService.addAnimation(this, animation); + } + else{ + this.draw(); + this.options.onAnimationComplete.call(this); + } + return this; + }, + generateLegend : function(){ + return template(this.options.legendTemplate,this); + }, + destroy : function(){ + this.clear(); + unbindEvents(this, this.events); + var canvas = this.chart.canvas; + + // Reset canvas height/width attributes starts a fresh with the canvas context + canvas.width = this.chart.width; + canvas.height = this.chart.height; + + // < IE9 doesn't support removeProperty + if (canvas.style.removeProperty) { + canvas.style.removeProperty('width'); + canvas.style.removeProperty('height'); + } else { + canvas.style.removeAttribute('width'); + canvas.style.removeAttribute('height'); + } + + delete Chart.instances[this.id]; + }, + showTooltip : function(ChartElements, forceRedraw){ + // Only redraw the chart if we've actually changed what we're hovering on. + if (typeof this.activeElements === 'undefined') this.activeElements = []; + + var isChanged = (function(Elements){ + var changed = false; + + if (Elements.length !== this.activeElements.length){ + changed = true; + return changed; + } + + each(Elements, function(element, index){ + if (element !== this.activeElements[index]){ + changed = true; + } + }, this); + return changed; + }).call(this, ChartElements); + + if (!isChanged && !forceRedraw){ + return; + } + else{ + this.activeElements = ChartElements; + } + this.draw(); + if(this.options.customTooltips){ + this.options.customTooltips(false); + } + if (ChartElements.length > 0){ + // If we have multiple datasets, show a MultiTooltip for all of the data points at that index + if (this.datasets && this.datasets.length > 1) { + var dataArray, + dataIndex; + + for (var i = this.datasets.length - 1; i >= 0; i--) { + dataArray = this.datasets[i].points || this.datasets[i].bars || this.datasets[i].segments; + dataIndex = indexOf(dataArray, ChartElements[0]); + if (dataIndex !== -1){ + break; + } + } + var tooltipLabels = [], + tooltipColors = [], + medianPosition = (function(index) { + + // Get all the points at that particular index + var Elements = [], + dataCollection, + xPositions = [], + yPositions = [], + xMax, + yMax, + xMin, + yMin; + helpers.each(this.datasets, function(dataset){ + dataCollection = dataset.points || dataset.bars || dataset.segments; + if (dataCollection[dataIndex] && dataCollection[dataIndex].hasValue()){ + Elements.push(dataCollection[dataIndex]); + } + }); + + helpers.each(Elements, function(element) { + xPositions.push(element.x); + yPositions.push(element.y); + + + //Include any colour information about the element + tooltipLabels.push(helpers.template(this.options.multiTooltipTemplate, element)); + tooltipColors.push({ + fill: element._saved.fillColor || element.fillColor, + stroke: element._saved.strokeColor || element.strokeColor + }); + + }, this); + + yMin = min(yPositions); + yMax = max(yPositions); + + xMin = min(xPositions); + xMax = max(xPositions); + + return { + x: (xMin > this.chart.width/2) ? xMin : xMax, + y: (yMin + yMax)/2 + }; + }).call(this, dataIndex); + + new Chart.MultiTooltip({ + x: medianPosition.x, + y: medianPosition.y, + xPadding: this.options.tooltipXPadding, + yPadding: this.options.tooltipYPadding, + xOffset: this.options.tooltipXOffset, + fillColor: this.options.tooltipFillColor, + textColor: this.options.tooltipFontColor, + fontFamily: this.options.tooltipFontFamily, + fontStyle: this.options.tooltipFontStyle, + fontSize: this.options.tooltipFontSize, + titleTextColor: this.options.tooltipTitleFontColor, + titleFontFamily: this.options.tooltipTitleFontFamily, + titleFontStyle: this.options.tooltipTitleFontStyle, + titleFontSize: this.options.tooltipTitleFontSize, + cornerRadius: this.options.tooltipCornerRadius, + labels: tooltipLabels, + legendColors: tooltipColors, + legendColorBackground : this.options.multiTooltipKeyBackground, + title: template(this.options.tooltipTitleTemplate,ChartElements[0]), + chart: this.chart, + ctx: this.chart.ctx, + custom: this.options.customTooltips + }).draw(); + + } else { + each(ChartElements, function(Element) { + var tooltipPosition = Element.tooltipPosition(); + new Chart.Tooltip({ + x: Math.round(tooltipPosition.x), + y: Math.round(tooltipPosition.y), + xPadding: this.options.tooltipXPadding, + yPadding: this.options.tooltipYPadding, + fillColor: this.options.tooltipFillColor, + textColor: this.options.tooltipFontColor, + fontFamily: this.options.tooltipFontFamily, + fontStyle: this.options.tooltipFontStyle, + fontSize: this.options.tooltipFontSize, + caretHeight: this.options.tooltipCaretSize, + cornerRadius: this.options.tooltipCornerRadius, + text: template(this.options.tooltipTemplate, Element), + chart: this.chart, + custom: this.options.customTooltips + }).draw(); + }, this); + } + } + return this; + }, + toBase64Image : function(){ + return this.chart.canvas.toDataURL.apply(this.chart.canvas, arguments); + } + }); + + Chart.Type.extend = function(extensions){ + + var parent = this; + + var ChartType = function(){ + return parent.apply(this,arguments); + }; + + //Copy the prototype object of the this class + ChartType.prototype = clone(parent.prototype); + //Now overwrite some of the properties in the base class with the new extensions + extend(ChartType.prototype, extensions); + + ChartType.extend = Chart.Type.extend; + + if (extensions.name || parent.prototype.name){ + + var chartName = extensions.name || parent.prototype.name; + //Assign any potential default values of the new chart type + + //If none are defined, we'll use a clone of the chart type this is being extended from. + //I.e. if we extend a line chart, we'll use the defaults from the line chart if our new chart + //doesn't define some defaults of their own. + + var baseDefaults = (Chart.defaults[parent.prototype.name]) ? clone(Chart.defaults[parent.prototype.name]) : {}; + + Chart.defaults[chartName] = extend(baseDefaults,extensions.defaults); + + Chart.types[chartName] = ChartType; + + //Register this new chart type in the Chart prototype + Chart.prototype[chartName] = function(data,options){ + var config = merge(Chart.defaults.global, Chart.defaults[chartName], options || {}); + return new ChartType(data,config,this); + }; + } else{ + warn("Name not provided for this chart, so it hasn't been registered"); + } + return parent; + }; + + Chart.Element = function(configuration){ + extend(this,configuration); + this.initialize.apply(this,arguments); + this.save(); + }; + extend(Chart.Element.prototype,{ + initialize : function(){}, + restore : function(props){ + if (!props){ + extend(this,this._saved); + } else { + each(props,function(key){ + this[key] = this._saved[key]; + },this); + } + return this; + }, + save : function(){ + this._saved = clone(this); + delete this._saved._saved; + return this; + }, + update : function(newProps){ + each(newProps,function(value,key){ + this._saved[key] = this[key]; + this[key] = value; + },this); + return this; + }, + transition : function(props,ease){ + each(props,function(value,key){ + this[key] = ((value - this._saved[key]) * ease) + this._saved[key]; + },this); + return this; + }, + tooltipPosition : function(){ + return { + x : this.x, + y : this.y + }; + }, + hasValue: function(){ + return isNumber(this.value); + } + }); + + Chart.Element.extend = inherits; + + + Chart.Point = Chart.Element.extend({ + display: true, + inRange: function(chartX,chartY){ + var hitDetectionRange = this.hitDetectionRadius + this.radius; + return ((Math.pow(chartX-this.x, 2)+Math.pow(chartY-this.y, 2)) < Math.pow(hitDetectionRange,2)); + }, + draw : function(){ + if (this.display){ + var ctx = this.ctx; + ctx.beginPath(); + + ctx.arc(this.x, this.y, this.radius, 0, Math.PI*2); + ctx.closePath(); + + ctx.strokeStyle = this.strokeColor; + ctx.lineWidth = this.strokeWidth; + + ctx.fillStyle = this.fillColor; + + ctx.fill(); + ctx.stroke(); + } + + + //Quick debug for bezier curve splining + //Highlights control points and the line between them. + //Handy for dev - stripped in the min version. + + // ctx.save(); + // ctx.fillStyle = "black"; + // ctx.strokeStyle = "black" + // ctx.beginPath(); + // ctx.arc(this.controlPoints.inner.x,this.controlPoints.inner.y, 2, 0, Math.PI*2); + // ctx.fill(); + + // ctx.beginPath(); + // ctx.arc(this.controlPoints.outer.x,this.controlPoints.outer.y, 2, 0, Math.PI*2); + // ctx.fill(); + + // ctx.moveTo(this.controlPoints.inner.x,this.controlPoints.inner.y); + // ctx.lineTo(this.x, this.y); + // ctx.lineTo(this.controlPoints.outer.x,this.controlPoints.outer.y); + // ctx.stroke(); + + // ctx.restore(); + + + + } + }); + + Chart.Arc = Chart.Element.extend({ + inRange : function(chartX,chartY){ + + var pointRelativePosition = helpers.getAngleFromPoint(this, { + x: chartX, + y: chartY + }); + + // Normalize all angles to 0 - 2*PI (0 - 360°) + var pointRelativeAngle = pointRelativePosition.angle % (Math.PI * 2), + startAngle = (Math.PI * 2 + this.startAngle) % (Math.PI * 2), + endAngle = (Math.PI * 2 + this.endAngle) % (Math.PI * 2) || 360; + + // Calculate wether the pointRelativeAngle is between the start and the end angle + var betweenAngles = (endAngle < startAngle) ? + pointRelativeAngle <= endAngle || pointRelativeAngle >= startAngle: + pointRelativeAngle >= startAngle && pointRelativeAngle <= endAngle; + + //Check if within the range of the open/close angle + var withinRadius = (pointRelativePosition.distance >= this.innerRadius && pointRelativePosition.distance <= this.outerRadius); + + return (betweenAngles && withinRadius); + //Ensure within the outside of the arc centre, but inside arc outer + }, + tooltipPosition : function(){ + var centreAngle = this.startAngle + ((this.endAngle - this.startAngle) / 2), + rangeFromCentre = (this.outerRadius - this.innerRadius) / 2 + this.innerRadius; + return { + x : this.x + (Math.cos(centreAngle) * rangeFromCentre), + y : this.y + (Math.sin(centreAngle) * rangeFromCentre) + }; + }, + draw : function(animationPercent){ + + var easingDecimal = animationPercent || 1; + + var ctx = this.ctx; + + ctx.beginPath(); + + ctx.arc(this.x, this.y, this.outerRadius < 0 ? 0 : this.outerRadius, this.startAngle, this.endAngle); + + ctx.arc(this.x, this.y, this.innerRadius < 0 ? 0 : this.innerRadius, this.endAngle, this.startAngle, true); + + ctx.closePath(); + ctx.strokeStyle = this.strokeColor; + ctx.lineWidth = this.strokeWidth; + + ctx.fillStyle = this.fillColor; + + ctx.fill(); + ctx.lineJoin = 'bevel'; + + if (this.showStroke){ + ctx.stroke(); + } + } + }); + + Chart.Rectangle = Chart.Element.extend({ + draw : function(){ + var ctx = this.ctx, + halfWidth = this.width/2, + leftX = this.x - halfWidth, + rightX = this.x + halfWidth, + top = this.base - (this.base - this.y), + halfStroke = this.strokeWidth / 2; + + // Canvas doesn't allow us to stroke inside the width so we can + // adjust the sizes to fit if we're setting a stroke on the line + if (this.showStroke){ + leftX += halfStroke; + rightX -= halfStroke; + top += halfStroke; + } + + ctx.beginPath(); + + ctx.fillStyle = this.fillColor; + ctx.strokeStyle = this.strokeColor; + ctx.lineWidth = this.strokeWidth; + + // It'd be nice to keep this class totally generic to any rectangle + // and simply specify which border to miss out. + ctx.moveTo(leftX, this.base); + ctx.lineTo(leftX, top); + ctx.lineTo(rightX, top); + ctx.lineTo(rightX, this.base); + ctx.fill(); + if (this.showStroke){ + ctx.stroke(); + } + }, + height : function(){ + return this.base - this.y; + }, + inRange : function(chartX,chartY){ + return (chartX >= this.x - this.width/2 && chartX <= this.x + this.width/2) && (chartY >= this.y && chartY <= this.base); + } + }); + + Chart.Animation = Chart.Element.extend({ + currentStep: null, // the current animation step + numSteps: 60, // default number of steps + easing: "", // the easing to use for this animation + render: null, // render function used by the animation service + + onAnimationProgress: null, // user specified callback to fire on each step of the animation + onAnimationComplete: null, // user specified callback to fire when the animation finishes + }); + + Chart.Tooltip = Chart.Element.extend({ + draw : function(){ + + var ctx = this.chart.ctx; + + ctx.font = fontString(this.fontSize,this.fontStyle,this.fontFamily); + + this.xAlign = "center"; + this.yAlign = "above"; + + //Distance between the actual element.y position and the start of the tooltip caret + var caretPadding = this.caretPadding = 2; + + var tooltipWidth = ctx.measureText(this.text).width + 2*this.xPadding, + tooltipRectHeight = this.fontSize + 2*this.yPadding, + tooltipHeight = tooltipRectHeight + this.caretHeight + caretPadding; + + if (this.x + tooltipWidth/2 >this.chart.width){ + this.xAlign = "left"; + } else if (this.x - tooltipWidth/2 < 0){ + this.xAlign = "right"; + } + + if (this.y - tooltipHeight < 0){ + this.yAlign = "below"; + } + + + var tooltipX = this.x - tooltipWidth/2, + tooltipY = this.y - tooltipHeight; + + ctx.fillStyle = this.fillColor; + + // Custom Tooltips + if(this.custom){ + this.custom(this); + } + else{ + switch(this.yAlign) + { + case "above": + //Draw a caret above the x/y + ctx.beginPath(); + ctx.moveTo(this.x,this.y - caretPadding); + ctx.lineTo(this.x + this.caretHeight, this.y - (caretPadding + this.caretHeight)); + ctx.lineTo(this.x - this.caretHeight, this.y - (caretPadding + this.caretHeight)); + ctx.closePath(); + ctx.fill(); + break; + case "below": + tooltipY = this.y + caretPadding + this.caretHeight; + //Draw a caret below the x/y + ctx.beginPath(); + ctx.moveTo(this.x, this.y + caretPadding); + ctx.lineTo(this.x + this.caretHeight, this.y + caretPadding + this.caretHeight); + ctx.lineTo(this.x - this.caretHeight, this.y + caretPadding + this.caretHeight); + ctx.closePath(); + ctx.fill(); + break; + } + + switch(this.xAlign) + { + case "left": + tooltipX = this.x - tooltipWidth + (this.cornerRadius + this.caretHeight); + break; + case "right": + tooltipX = this.x - (this.cornerRadius + this.caretHeight); + break; + } + + drawRoundedRectangle(ctx,tooltipX,tooltipY,tooltipWidth,tooltipRectHeight,this.cornerRadius); + + ctx.fill(); + + ctx.fillStyle = this.textColor; + ctx.textAlign = "center"; + ctx.textBaseline = "middle"; + ctx.fillText(this.text, tooltipX + tooltipWidth/2, tooltipY + tooltipRectHeight/2); + } + } + }); + + Chart.MultiTooltip = Chart.Element.extend({ + initialize : function(){ + this.font = fontString(this.fontSize,this.fontStyle,this.fontFamily); + + this.titleFont = fontString(this.titleFontSize,this.titleFontStyle,this.titleFontFamily); + + this.titleHeight = this.title ? this.titleFontSize * 1.5 : 0; + this.height = (this.labels.length * this.fontSize) + ((this.labels.length-1) * (this.fontSize/2)) + (this.yPadding*2) + this.titleHeight; + + this.ctx.font = this.titleFont; + + var titleWidth = this.ctx.measureText(this.title).width, + //Label has a legend square as well so account for this. + labelWidth = longestText(this.ctx,this.font,this.labels) + this.fontSize + 3, + longestTextWidth = max([labelWidth,titleWidth]); + + this.width = longestTextWidth + (this.xPadding*2); + + + var halfHeight = this.height/2; + + //Check to ensure the height will fit on the canvas + if (this.y - halfHeight < 0 ){ + this.y = halfHeight; + } else if (this.y + halfHeight > this.chart.height){ + this.y = this.chart.height - halfHeight; + } + + //Decide whether to align left or right based on position on canvas + if (this.x > this.chart.width/2){ + this.x -= this.xOffset + this.width; + } else { + this.x += this.xOffset; + } + + + }, + getLineHeight : function(index){ + var baseLineHeight = this.y - (this.height/2) + this.yPadding, + afterTitleIndex = index-1; + + //If the index is zero, we're getting the title + if (index === 0){ + return baseLineHeight + this.titleHeight / 3; + } else{ + return baseLineHeight + ((this.fontSize * 1.5 * afterTitleIndex) + this.fontSize / 2) + this.titleHeight; + } + + }, + draw : function(){ + // Custom Tooltips + if(this.custom){ + this.custom(this); + } + else{ + drawRoundedRectangle(this.ctx,this.x,this.y - this.height/2,this.width,this.height,this.cornerRadius); + var ctx = this.ctx; + ctx.fillStyle = this.fillColor; + ctx.fill(); + ctx.closePath(); + + ctx.textAlign = "left"; + ctx.textBaseline = "middle"; + ctx.fillStyle = this.titleTextColor; + ctx.font = this.titleFont; + + ctx.fillText(this.title,this.x + this.xPadding, this.getLineHeight(0)); + + ctx.font = this.font; + helpers.each(this.labels,function(label,index){ + ctx.fillStyle = this.textColor; + ctx.fillText(label,this.x + this.xPadding + this.fontSize + 3, this.getLineHeight(index + 1)); + + //A bit gnarly, but clearing this rectangle breaks when using explorercanvas (clears whole canvas) + //ctx.clearRect(this.x + this.xPadding, this.getLineHeight(index + 1) - this.fontSize/2, this.fontSize, this.fontSize); + //Instead we'll make a white filled block to put the legendColour palette over. + + ctx.fillStyle = this.legendColorBackground; + ctx.fillRect(this.x + this.xPadding, this.getLineHeight(index + 1) - this.fontSize/2, this.fontSize, this.fontSize); + + ctx.fillStyle = this.legendColors[index].fill; + ctx.fillRect(this.x + this.xPadding, this.getLineHeight(index + 1) - this.fontSize/2, this.fontSize, this.fontSize); + + + },this); + } + } + }); + + Chart.Scale = Chart.Element.extend({ + initialize : function(){ + this.fit(); + }, + buildYLabels : function(){ + this.yLabels = []; + + var stepDecimalPlaces = getDecimalPlaces(this.stepValue); + + for (var i=0; i<=this.steps; i++){ + this.yLabels.push(template(this.templateString,{value:(this.min + (i * this.stepValue)).toFixed(stepDecimalPlaces)})); + } + this.yLabelWidth = (this.display && this.showLabels) ? longestText(this.ctx,this.font,this.yLabels) + 10 : 0; + }, + addXLabel : function(label){ + this.xLabels.push(label); + this.valuesCount++; + this.fit(); + }, + removeXLabel : function(){ + this.xLabels.shift(); + this.valuesCount--; + this.fit(); + }, + // Fitting loop to rotate x Labels and figure out what fits there, and also calculate how many Y steps to use + fit: function(){ + // First we need the width of the yLabels, assuming the xLabels aren't rotated + + // To do that we need the base line at the top and base of the chart, assuming there is no x label rotation + this.startPoint = (this.display) ? this.fontSize : 0; + this.endPoint = (this.display) ? this.height - (this.fontSize * 1.5) - 5 : this.height; // -5 to pad labels + + // Apply padding settings to the start and end point. + this.startPoint += this.padding; + this.endPoint -= this.padding; + + // Cache the starting endpoint, excluding the space for x labels + var cachedEndPoint = this.endPoint; + + // Cache the starting height, so can determine if we need to recalculate the scale yAxis + var cachedHeight = this.endPoint - this.startPoint, + cachedYLabelWidth; + + // Build the current yLabels so we have an idea of what size they'll be to start + /* + * This sets what is returned from calculateScaleRange as static properties of this class: + * + this.steps; + this.stepValue; + this.min; + this.max; + * + */ + this.calculateYRange(cachedHeight); + + // With these properties set we can now build the array of yLabels + // and also the width of the largest yLabel + this.buildYLabels(); + + this.calculateXLabelRotation(); + + while((cachedHeight > this.endPoint - this.startPoint)){ + cachedHeight = this.endPoint - this.startPoint; + cachedYLabelWidth = this.yLabelWidth; + + this.calculateYRange(cachedHeight); + this.buildYLabels(); + + // Only go through the xLabel loop again if the yLabel width has changed + if (cachedYLabelWidth < this.yLabelWidth){ + this.endPoint = cachedEndPoint; + this.calculateXLabelRotation(); + } + } + + }, + calculateXLabelRotation : function(){ + //Get the width of each grid by calculating the difference + //between x offsets between 0 and 1. + + this.ctx.font = this.font; + + var firstWidth = this.ctx.measureText(this.xLabels[0]).width, + lastWidth = this.ctx.measureText(this.xLabels[this.xLabels.length - 1]).width, + firstRotated, + lastRotated; + + + this.xScalePaddingRight = lastWidth/2 + 3; + this.xScalePaddingLeft = (firstWidth/2 > this.yLabelWidth) ? firstWidth/2 : this.yLabelWidth; + + this.xLabelRotation = 0; + if (this.display){ + var originalLabelWidth = longestText(this.ctx,this.font,this.xLabels), + cosRotation, + firstRotatedWidth; + this.xLabelWidth = originalLabelWidth; + //Allow 3 pixels x2 padding either side for label readability + var xGridWidth = Math.floor(this.calculateX(1) - this.calculateX(0)) - 6; + + //Max label rotate should be 90 - also act as a loop counter + while ((this.xLabelWidth > xGridWidth && this.xLabelRotation === 0) || (this.xLabelWidth > xGridWidth && this.xLabelRotation <= 90 && this.xLabelRotation > 0)){ + cosRotation = Math.cos(toRadians(this.xLabelRotation)); + + firstRotated = cosRotation * firstWidth; + lastRotated = cosRotation * lastWidth; + + // We're right aligning the text now. + if (firstRotated + this.fontSize / 2 > this.yLabelWidth){ + this.xScalePaddingLeft = firstRotated + this.fontSize / 2; + } + this.xScalePaddingRight = this.fontSize/2; + + + this.xLabelRotation++; + this.xLabelWidth = cosRotation * originalLabelWidth; + + } + if (this.xLabelRotation > 0){ + this.endPoint -= Math.sin(toRadians(this.xLabelRotation))*originalLabelWidth + 3; + } + } + else{ + this.xLabelWidth = 0; + this.xScalePaddingRight = this.padding; + this.xScalePaddingLeft = this.padding; + } + + }, + // Needs to be overidden in each Chart type + // Otherwise we need to pass all the data into the scale class + calculateYRange: noop, + drawingArea: function(){ + return this.startPoint - this.endPoint; + }, + calculateY : function(value){ + var scalingFactor = this.drawingArea() / (this.min - this.max); + return this.endPoint - (scalingFactor * (value - this.min)); + }, + calculateX : function(index){ + var isRotated = (this.xLabelRotation > 0), + // innerWidth = (this.offsetGridLines) ? this.width - offsetLeft - this.padding : this.width - (offsetLeft + halfLabelWidth * 2) - this.padding, + innerWidth = this.width - (this.xScalePaddingLeft + this.xScalePaddingRight), + valueWidth = innerWidth/Math.max((this.valuesCount - ((this.offsetGridLines) ? 0 : 1)), 1), + valueOffset = (valueWidth * index) + this.xScalePaddingLeft; + + if (this.offsetGridLines){ + valueOffset += (valueWidth/2); + } + + return Math.round(valueOffset); + }, + update : function(newProps){ + helpers.extend(this, newProps); + this.fit(); + }, + draw : function(){ + var ctx = this.ctx, + yLabelGap = (this.endPoint - this.startPoint) / this.steps, + xStart = Math.round(this.xScalePaddingLeft); + if (this.display){ + ctx.fillStyle = this.textColor; + ctx.font = this.font; + each(this.yLabels,function(labelString,index){ + var yLabelCenter = this.endPoint - (yLabelGap * index), + linePositionY = Math.round(yLabelCenter), + drawHorizontalLine = this.showHorizontalLines; + + ctx.textAlign = "right"; + ctx.textBaseline = "middle"; + if (this.showLabels){ + ctx.fillText(labelString,xStart - 10,yLabelCenter); + } + + // This is X axis, so draw it + if (index === 0 && !drawHorizontalLine){ + drawHorizontalLine = true; + } + + if (drawHorizontalLine){ + ctx.beginPath(); + } + + if (index > 0){ + // This is a grid line in the centre, so drop that + ctx.lineWidth = this.gridLineWidth; + ctx.strokeStyle = this.gridLineColor; + } else { + // This is the first line on the scale + ctx.lineWidth = this.lineWidth; + ctx.strokeStyle = this.lineColor; + } + + linePositionY += helpers.aliasPixel(ctx.lineWidth); + + if(drawHorizontalLine){ + ctx.moveTo(xStart, linePositionY); + ctx.lineTo(this.width, linePositionY); + ctx.stroke(); + ctx.closePath(); + } + + ctx.lineWidth = this.lineWidth; + ctx.strokeStyle = this.lineColor; + ctx.beginPath(); + ctx.moveTo(xStart - 5, linePositionY); + ctx.lineTo(xStart, linePositionY); + ctx.stroke(); + ctx.closePath(); + + },this); + + each(this.xLabels,function(label,index){ + var xPos = this.calculateX(index) + aliasPixel(this.lineWidth), + // Check to see if line/bar here and decide where to place the line + linePos = this.calculateX(index - (this.offsetGridLines ? 0.5 : 0)) + aliasPixel(this.lineWidth), + isRotated = (this.xLabelRotation > 0), + drawVerticalLine = this.showVerticalLines; + + // This is Y axis, so draw it + if (index === 0 && !drawVerticalLine){ + drawVerticalLine = true; + } + + if (drawVerticalLine){ + ctx.beginPath(); + } + + if (index > 0){ + // This is a grid line in the centre, so drop that + ctx.lineWidth = this.gridLineWidth; + ctx.strokeStyle = this.gridLineColor; + } else { + // This is the first line on the scale + ctx.lineWidth = this.lineWidth; + ctx.strokeStyle = this.lineColor; + } + + if (drawVerticalLine){ + ctx.moveTo(linePos,this.endPoint); + ctx.lineTo(linePos,this.startPoint - 3); + ctx.stroke(); + ctx.closePath(); + } + + + ctx.lineWidth = this.lineWidth; + ctx.strokeStyle = this.lineColor; + + + // Small lines at the bottom of the base grid line + ctx.beginPath(); + ctx.moveTo(linePos,this.endPoint); + ctx.lineTo(linePos,this.endPoint + 5); + ctx.stroke(); + ctx.closePath(); + + ctx.save(); + ctx.translate(xPos,(isRotated) ? this.endPoint + 12 : this.endPoint + 8); + ctx.rotate(toRadians(this.xLabelRotation)*-1); + ctx.font = this.font; + ctx.textAlign = (isRotated) ? "right" : "center"; + ctx.textBaseline = (isRotated) ? "middle" : "top"; + ctx.fillText(label, 0, 0); + ctx.restore(); + },this); + + } + } + + }); + + Chart.RadialScale = Chart.Element.extend({ + initialize: function(){ + this.size = min([this.height, this.width]); + this.drawingArea = (this.display) ? (this.size/2) - (this.fontSize/2 + this.backdropPaddingY) : (this.size/2); + }, + calculateCenterOffset: function(value){ + // Take into account half font size + the yPadding of the top value + var scalingFactor = this.drawingArea / (this.max - this.min); + + return (value - this.min) * scalingFactor; + }, + update : function(){ + if (!this.lineArc){ + this.setScaleSize(); + } else { + this.drawingArea = (this.display) ? (this.size/2) - (this.fontSize/2 + this.backdropPaddingY) : (this.size/2); + } + this.buildYLabels(); + }, + buildYLabels: function(){ + this.yLabels = []; + + var stepDecimalPlaces = getDecimalPlaces(this.stepValue); + + for (var i=0; i<=this.steps; i++){ + this.yLabels.push(template(this.templateString,{value:(this.min + (i * this.stepValue)).toFixed(stepDecimalPlaces)})); + } + }, + getCircumference : function(){ + return ((Math.PI*2) / this.valuesCount); + }, + setScaleSize: function(){ + /* + * Right, this is really confusing and there is a lot of maths going on here + * The gist of the problem is here: https://gist.github.com/nnnick/696cc9c55f4b0beb8fe9 + * + * Reaction: https://dl.dropboxusercontent.com/u/34601363/toomuchscience.gif + * + * Solution: + * + * We assume the radius of the polygon is half the size of the canvas at first + * at each index we check if the text overlaps. + * + * Where it does, we store that angle and that index. + * + * After finding the largest index and angle we calculate how much we need to remove + * from the shape radius to move the point inwards by that x. + * + * We average the left and right distances to get the maximum shape radius that can fit in the box + * along with labels. + * + * Once we have that, we can find the centre point for the chart, by taking the x text protrusion + * on each side, removing that from the size, halving it and adding the left x protrusion width. + * + * This will mean we have a shape fitted to the canvas, as large as it can be with the labels + * and position it in the most space efficient manner + * + * https://dl.dropboxusercontent.com/u/34601363/yeahscience.gif + */ + + + // Get maximum radius of the polygon. Either half the height (minus the text width) or half the width. + // Use this to calculate the offset + change. - Make sure L/R protrusion is at least 0 to stop issues with centre points + var largestPossibleRadius = min([(this.height/2 - this.pointLabelFontSize - 5), this.width/2]), + pointPosition, + i, + textWidth, + halfTextWidth, + furthestRight = this.width, + furthestRightIndex, + furthestRightAngle, + furthestLeft = 0, + furthestLeftIndex, + furthestLeftAngle, + xProtrusionLeft, + xProtrusionRight, + radiusReductionRight, + radiusReductionLeft, + maxWidthRadius; + this.ctx.font = fontString(this.pointLabelFontSize,this.pointLabelFontStyle,this.pointLabelFontFamily); + for (i=0;i furthestRight) { + furthestRight = pointPosition.x + halfTextWidth; + furthestRightIndex = i; + } + if (pointPosition.x - halfTextWidth < furthestLeft) { + furthestLeft = pointPosition.x - halfTextWidth; + furthestLeftIndex = i; + } + } + else if (i < this.valuesCount/2) { + // Less than half the values means we'll left align the text + if (pointPosition.x + textWidth > furthestRight) { + furthestRight = pointPosition.x + textWidth; + furthestRightIndex = i; + } + } + else if (i > this.valuesCount/2){ + // More than half the values means we'll right align the text + if (pointPosition.x - textWidth < furthestLeft) { + furthestLeft = pointPosition.x - textWidth; + furthestLeftIndex = i; + } + } + } + + xProtrusionLeft = furthestLeft; + + xProtrusionRight = Math.ceil(furthestRight - this.width); + + furthestRightAngle = this.getIndexAngle(furthestRightIndex); + + furthestLeftAngle = this.getIndexAngle(furthestLeftIndex); + + radiusReductionRight = xProtrusionRight / Math.sin(furthestRightAngle + Math.PI/2); + + radiusReductionLeft = xProtrusionLeft / Math.sin(furthestLeftAngle + Math.PI/2); + + // Ensure we actually need to reduce the size of the chart + radiusReductionRight = (isNumber(radiusReductionRight)) ? radiusReductionRight : 0; + radiusReductionLeft = (isNumber(radiusReductionLeft)) ? radiusReductionLeft : 0; + + this.drawingArea = largestPossibleRadius - (radiusReductionLeft + radiusReductionRight)/2; + + //this.drawingArea = min([maxWidthRadius, (this.height - (2 * (this.pointLabelFontSize + 5)))/2]) + this.setCenterPoint(radiusReductionLeft, radiusReductionRight); + + }, + setCenterPoint: function(leftMovement, rightMovement){ + + var maxRight = this.width - rightMovement - this.drawingArea, + maxLeft = leftMovement + this.drawingArea; + + this.xCenter = (maxLeft + maxRight)/2; + // Always vertically in the centre as the text height doesn't change + this.yCenter = (this.height/2); + }, + + getIndexAngle : function(index){ + var angleMultiplier = (Math.PI * 2) / this.valuesCount; + // Start from the top instead of right, so remove a quarter of the circle + + return index * angleMultiplier - (Math.PI/2); + }, + getPointPosition : function(index, distanceFromCenter){ + var thisAngle = this.getIndexAngle(index); + return { + x : (Math.cos(thisAngle) * distanceFromCenter) + this.xCenter, + y : (Math.sin(thisAngle) * distanceFromCenter) + this.yCenter + }; + }, + draw: function(){ + if (this.display){ + var ctx = this.ctx; + each(this.yLabels, function(label, index){ + // Don't draw a centre value + if (index > 0){ + var yCenterOffset = index * (this.drawingArea/this.steps), + yHeight = this.yCenter - yCenterOffset, + pointPosition; + + // Draw circular lines around the scale + if (this.lineWidth > 0){ + ctx.strokeStyle = this.lineColor; + ctx.lineWidth = this.lineWidth; + + if(this.lineArc){ + ctx.beginPath(); + ctx.arc(this.xCenter, this.yCenter, yCenterOffset, 0, Math.PI*2); + ctx.closePath(); + ctx.stroke(); + } else{ + ctx.beginPath(); + for (var i=0;i= 0; i--) { + var centerOffset = null, outerPosition = null; + + if (this.angleLineWidth > 0){ + centerOffset = this.calculateCenterOffset(this.max); + outerPosition = this.getPointPosition(i, centerOffset); + ctx.beginPath(); + ctx.moveTo(this.xCenter, this.yCenter); + ctx.lineTo(outerPosition.x, outerPosition.y); + ctx.stroke(); + ctx.closePath(); + } + + if (this.backgroundColors && this.backgroundColors.length == this.valuesCount) { + if (centerOffset == null) + centerOffset = this.calculateCenterOffset(this.max); + + if (outerPosition == null) + outerPosition = this.getPointPosition(i, centerOffset); + + var previousOuterPosition = this.getPointPosition(i === 0 ? this.valuesCount - 1 : i - 1, centerOffset); + var nextOuterPosition = this.getPointPosition(i === this.valuesCount - 1 ? 0 : i + 1, centerOffset); + + var previousOuterHalfway = { x: (previousOuterPosition.x + outerPosition.x) / 2, y: (previousOuterPosition.y + outerPosition.y) / 2 }; + var nextOuterHalfway = { x: (outerPosition.x + nextOuterPosition.x) / 2, y: (outerPosition.y + nextOuterPosition.y) / 2 }; + + ctx.beginPath(); + ctx.moveTo(this.xCenter, this.yCenter); + ctx.lineTo(previousOuterHalfway.x, previousOuterHalfway.y); + ctx.lineTo(outerPosition.x, outerPosition.y); + ctx.lineTo(nextOuterHalfway.x, nextOuterHalfway.y); + ctx.fillStyle = this.backgroundColors[i]; + ctx.fill(); + ctx.closePath(); + } + // Extra 3px out for some label spacing + var pointLabelPosition = this.getPointPosition(i, this.calculateCenterOffset(this.max) + 5); + ctx.font = fontString(this.pointLabelFontSize,this.pointLabelFontStyle,this.pointLabelFontFamily); + ctx.fillStyle = this.pointLabelFontColor; + + var labelsCount = this.labels.length, + halfLabelsCount = this.labels.length/2, + quarterLabelsCount = halfLabelsCount/2, + upperHalf = (i < quarterLabelsCount || i > labelsCount - quarterLabelsCount), + exactQuarter = (i === quarterLabelsCount || i === labelsCount - quarterLabelsCount); + if (i === 0){ + ctx.textAlign = 'center'; + } else if(i === halfLabelsCount){ + ctx.textAlign = 'center'; + } else if (i < halfLabelsCount){ + ctx.textAlign = 'left'; + } else { + ctx.textAlign = 'right'; + } + + // Set the correct text baseline based on outer positioning + if (exactQuarter){ + ctx.textBaseline = 'middle'; + } else if (upperHalf){ + ctx.textBaseline = 'bottom'; + } else { + ctx.textBaseline = 'top'; + } + + ctx.fillText(this.labels[i], pointLabelPosition.x, pointLabelPosition.y); + } + } + } + } + }); + + Chart.animationService = { + frameDuration: 17, + animations: [], + dropFrames: 0, + addAnimation: function(chartInstance, animationObject) { + for (var index = 0; index < this.animations.length; ++ index){ + if (this.animations[index].chartInstance === chartInstance){ + // replacing an in progress animation + this.animations[index].animationObject = animationObject; + return; + } + } + + this.animations.push({ + chartInstance: chartInstance, + animationObject: animationObject + }); + + // If there are no animations queued, manually kickstart a digest, for lack of a better word + if (this.animations.length == 1) { + helpers.requestAnimFrame.call(window, this.digestWrapper); + } + }, + // Cancel the animation for a given chart instance + cancelAnimation: function(chartInstance) { + var index = helpers.findNextWhere(this.animations, function(animationWrapper) { + return animationWrapper.chartInstance === chartInstance; + }); + + if (index) + { + this.animations.splice(index, 1); + } + }, + // calls startDigest with the proper context + digestWrapper: function() { + Chart.animationService.startDigest.call(Chart.animationService); + }, + startDigest: function() { + + var startTime = Date.now(); + var framesToDrop = 0; + + if(this.dropFrames > 1){ + framesToDrop = Math.floor(this.dropFrames); + this.dropFrames -= framesToDrop; + } + + for (var i = 0; i < this.animations.length; i++) { + + if (this.animations[i].animationObject.currentStep === null){ + this.animations[i].animationObject.currentStep = 0; + } + + this.animations[i].animationObject.currentStep += 1 + framesToDrop; + if(this.animations[i].animationObject.currentStep > this.animations[i].animationObject.numSteps){ + this.animations[i].animationObject.currentStep = this.animations[i].animationObject.numSteps; + } + + this.animations[i].animationObject.render(this.animations[i].chartInstance, this.animations[i].animationObject); + + // Check if executed the last frame. + if (this.animations[i].animationObject.currentStep == this.animations[i].animationObject.numSteps){ + // Call onAnimationComplete + this.animations[i].animationObject.onAnimationComplete.call(this.animations[i].chartInstance); + // Remove the animation. + this.animations.splice(i, 1); + // Keep the index in place to offset the splice + i--; + } + } + + var endTime = Date.now(); + var delay = endTime - startTime - this.frameDuration; + var frameDelay = delay / this.frameDuration; + + if(frameDelay > 1){ + this.dropFrames += frameDelay; + } + + // Do we have more stuff to animate? + if (this.animations.length > 0){ + helpers.requestAnimFrame.call(window, this.digestWrapper); + } + } + }; + + // Attach global event to resize each chart instance when the browser resizes + helpers.addEvent(window, "resize", (function(){ + // Basic debounce of resize function so it doesn't hurt performance when resizing browser. + var timeout; + return function(){ + clearTimeout(timeout); + timeout = setTimeout(function(){ + each(Chart.instances,function(instance){ + // If the responsive flag is set in the chart instance config + // Cascade the resize event down to the chart. + if (instance.options.responsive){ + instance.resize(instance.render, true); + } + }); + }, 50); + }; + })()); + + + if (amd) { + define(function(){ + return Chart; + }); + } else if (typeof module === 'object' && module.exports) { + module.exports = Chart; + } + + root.Chart = Chart; + + Chart.noConflict = function(){ + root.Chart = previous; + return Chart; + }; + +}).call(this); + +(function(){ + "use strict"; + + var root = this, + Chart = root.Chart, + helpers = Chart.helpers; + + + var defaultConfig = { + //Boolean - Whether the scale should start at zero, or an order of magnitude down from the lowest value + scaleBeginAtZero : true, + + //Boolean - Whether grid lines are shown across the chart + scaleShowGridLines : true, + + //String - Colour of the grid lines + scaleGridLineColor : "rgba(0,0,0,.05)", + + //Number - Width of the grid lines + scaleGridLineWidth : 1, + + //Boolean - Whether to show horizontal lines (except X axis) + scaleShowHorizontalLines: true, + + //Boolean - Whether to show vertical lines (except Y axis) + scaleShowVerticalLines: true, + + //Boolean - If there is a stroke on each bar + barShowStroke : true, + + //Number - Pixel width of the bar stroke + barStrokeWidth : 2, + + //Number - Spacing between each of the X value sets + barValueSpacing : 5, + + //Number - Spacing between data sets within X values + barDatasetSpacing : 1, + + //String - A legend template + legendTemplate : "
    -legend\"><% for (var i=0; i
  • \"><%if(datasets[i].label){%><%=datasets[i].label%><%}%>
    • <%}%>
" + + }; + + + Chart.Type.extend({ + name: "Bar", + defaults : defaultConfig, + initialize: function(data){ + + //Expose options as a scope variable here so we can access it in the ScaleClass + var options = this.options; + + this.ScaleClass = Chart.Scale.extend({ + offsetGridLines : true, + calculateBarX : function(datasetCount, datasetIndex, barIndex){ + //Reusable method for calculating the xPosition of a given bar based on datasetIndex & width of the bar + var xWidth = this.calculateBaseWidth(), + xAbsolute = this.calculateX(barIndex) - (xWidth/2), + barWidth = this.calculateBarWidth(datasetCount); + + return xAbsolute + (barWidth * datasetIndex) + (datasetIndex * options.barDatasetSpacing) + barWidth/2; + }, + calculateBaseWidth : function(){ + return (this.calculateX(1) - this.calculateX(0)) - (2*options.barValueSpacing); + }, + calculateBarWidth : function(datasetCount){ + //The padding between datasets is to the right of each bar, providing that there are more than 1 dataset + var baseWidth = this.calculateBaseWidth() - ((datasetCount - 1) * options.barDatasetSpacing); + + return (baseWidth / datasetCount); + } + }); + + this.datasets = []; + + //Set up tooltip events on the chart + if (this.options.showTooltips){ + helpers.bindEvents(this, this.options.tooltipEvents, function(evt){ + var activeBars = (evt.type !== 'mouseout') ? this.getBarsAtEvent(evt) : []; + + this.eachBars(function(bar){ + bar.restore(['fillColor', 'strokeColor']); + }); + helpers.each(activeBars, function(activeBar){ + activeBar.fillColor = activeBar.highlightFill; + activeBar.strokeColor = activeBar.highlightStroke; + }); + this.showTooltip(activeBars); + }); + } + + //Declare the extension of the default point, to cater for the options passed in to the constructor + this.BarClass = Chart.Rectangle.extend({ + strokeWidth : this.options.barStrokeWidth, + showStroke : this.options.barShowStroke, + ctx : this.chart.ctx + }); + + //Iterate through each of the datasets, and build this into a property of the chart + helpers.each(data.datasets,function(dataset,datasetIndex){ + + var datasetObject = { + label : dataset.label || null, + fillColor : dataset.fillColor, + strokeColor : dataset.strokeColor, + bars : [] + }; + + this.datasets.push(datasetObject); + + helpers.each(dataset.data,function(dataPoint,index){ + //Add a new point for each piece of data, passing any required data to draw. + datasetObject.bars.push(new this.BarClass({ + value : dataPoint, + label : data.labels[index], + datasetLabel: dataset.label, + strokeColor : dataset.strokeColor, + fillColor : dataset.fillColor, + highlightFill : dataset.highlightFill || dataset.fillColor, + highlightStroke : dataset.highlightStroke || dataset.strokeColor + })); + },this); + + },this); + + this.buildScale(data.labels); + + this.BarClass.prototype.base = this.scale.endPoint; + + this.eachBars(function(bar, index, datasetIndex){ + helpers.extend(bar, { + width : this.scale.calculateBarWidth(this.datasets.length), + x: this.scale.calculateBarX(this.datasets.length, datasetIndex, index), + y: this.scale.endPoint + }); + bar.save(); + }, this); + + this.render(); + }, + update : function(){ + this.scale.update(); + // Reset any highlight colours before updating. + helpers.each(this.activeElements, function(activeElement){ + activeElement.restore(['fillColor', 'strokeColor']); + }); + + this.eachBars(function(bar){ + bar.save(); + }); + this.render(); + }, + eachBars : function(callback){ + helpers.each(this.datasets,function(dataset, datasetIndex){ + helpers.each(dataset.bars, callback, this, datasetIndex); + },this); + }, + getBarsAtEvent : function(e){ + var barsArray = [], + eventPosition = helpers.getRelativePosition(e), + datasetIterator = function(dataset){ + barsArray.push(dataset.bars[barIndex]); + }, + barIndex; + + for (var datasetIndex = 0; datasetIndex < this.datasets.length; datasetIndex++) { + for (barIndex = 0; barIndex < this.datasets[datasetIndex].bars.length; barIndex++) { + if (this.datasets[datasetIndex].bars[barIndex].inRange(eventPosition.x,eventPosition.y)){ + helpers.each(this.datasets, datasetIterator); + return barsArray; + } + } + } + + return barsArray; + }, + buildScale : function(labels){ + var self = this; + + var dataTotal = function(){ + var values = []; + self.eachBars(function(bar){ + values.push(bar.value); + }); + return values; + }; + + var scaleOptions = { + templateString : this.options.scaleLabel, + height : this.chart.height, + width : this.chart.width, + ctx : this.chart.ctx, + textColor : this.options.scaleFontColor, + fontSize : this.options.scaleFontSize, + fontStyle : this.options.scaleFontStyle, + fontFamily : this.options.scaleFontFamily, + valuesCount : labels.length, + beginAtZero : this.options.scaleBeginAtZero, + integersOnly : this.options.scaleIntegersOnly, + calculateYRange: function(currentHeight){ + var updatedRanges = helpers.calculateScaleRange( + dataTotal(), + currentHeight, + this.fontSize, + this.beginAtZero, + this.integersOnly + ); + helpers.extend(this, updatedRanges); + }, + xLabels : labels, + font : helpers.fontString(this.options.scaleFontSize, this.options.scaleFontStyle, this.options.scaleFontFamily), + lineWidth : this.options.scaleLineWidth, + lineColor : this.options.scaleLineColor, + showHorizontalLines : this.options.scaleShowHorizontalLines, + showVerticalLines : this.options.scaleShowVerticalLines, + gridLineWidth : (this.options.scaleShowGridLines) ? this.options.scaleGridLineWidth : 0, + gridLineColor : (this.options.scaleShowGridLines) ? this.options.scaleGridLineColor : "rgba(0,0,0,0)", + padding : (this.options.showScale) ? 0 : (this.options.barShowStroke) ? this.options.barStrokeWidth : 0, + showLabels : this.options.scaleShowLabels, + display : this.options.showScale + }; + + if (this.options.scaleOverride){ + helpers.extend(scaleOptions, { + calculateYRange: helpers.noop, + steps: this.options.scaleSteps, + stepValue: this.options.scaleStepWidth, + min: this.options.scaleStartValue, + max: this.options.scaleStartValue + (this.options.scaleSteps * this.options.scaleStepWidth) + }); + } + + this.scale = new this.ScaleClass(scaleOptions); + }, + addData : function(valuesArray,label){ + //Map the values array for each of the datasets + helpers.each(valuesArray,function(value,datasetIndex){ + //Add a new point for each piece of data, passing any required data to draw. + this.datasets[datasetIndex].bars.push(new this.BarClass({ + value : value, + label : label, + datasetLabel: this.datasets[datasetIndex].label, + x: this.scale.calculateBarX(this.datasets.length, datasetIndex, this.scale.valuesCount+1), + y: this.scale.endPoint, + width : this.scale.calculateBarWidth(this.datasets.length), + base : this.scale.endPoint, + strokeColor : this.datasets[datasetIndex].strokeColor, + fillColor : this.datasets[datasetIndex].fillColor + })); + },this); + + this.scale.addXLabel(label); + //Then re-render the chart. + this.update(); + }, + removeData : function(){ + this.scale.removeXLabel(); + //Then re-render the chart. + helpers.each(this.datasets,function(dataset){ + dataset.bars.shift(); + },this); + this.update(); + }, + reflow : function(){ + helpers.extend(this.BarClass.prototype,{ + y: this.scale.endPoint, + base : this.scale.endPoint + }); + var newScaleProps = helpers.extend({ + height : this.chart.height, + width : this.chart.width + }); + this.scale.update(newScaleProps); + }, + draw : function(ease){ + var easingDecimal = ease || 1; + this.clear(); + + var ctx = this.chart.ctx; + + this.scale.draw(easingDecimal); + + //Draw all the bars for each dataset + helpers.each(this.datasets,function(dataset,datasetIndex){ + helpers.each(dataset.bars,function(bar,index){ + if (bar.hasValue()){ + bar.base = this.scale.endPoint; + //Transition then draw + bar.transition({ + x : this.scale.calculateBarX(this.datasets.length, datasetIndex, index), + y : this.scale.calculateY(bar.value), + width : this.scale.calculateBarWidth(this.datasets.length) + }, easingDecimal).draw(); + } + },this); + + },this); + } + }); + + +}).call(this); + +(function(){ + "use strict"; + + var root = this, + Chart = root.Chart, + //Cache a local reference to Chart.helpers + helpers = Chart.helpers; + + var defaultConfig = { + //Boolean - Whether we should show a stroke on each segment + segmentShowStroke : true, + + //String - The colour of each segment stroke + segmentStrokeColor : "#fff", + + //Number - The width of each segment stroke + segmentStrokeWidth : 2, + + //The percentage of the chart that we cut out of the middle. + percentageInnerCutout : 50, + + //Number - Amount of animation steps + animationSteps : 100, + + //String - Animation easing effect + animationEasing : "easeOutBounce", + + //Boolean - Whether we animate the rotation of the Doughnut + animateRotate : true, + + //Boolean - Whether we animate scaling the Doughnut from the centre + animateScale : false, + + //String - A legend template + legendTemplate : "
    -legend\"><% for (var i=0; i
  • \"><%if(segments[i].label){%><%=segments[i].label%><%}%>
    • <%}%>
" + + }; + + Chart.Type.extend({ + //Passing in a name registers this chart in the Chart namespace + name: "Doughnut", + //Providing a defaults will also register the deafults in the chart namespace + defaults : defaultConfig, + //Initialize is fired when the chart is initialized - Data is passed in as a parameter + //Config is automatically merged by the core of Chart.js, and is available at this.options + initialize: function(data){ + + //Declare segments as a static property to prevent inheriting across the Chart type prototype + this.segments = []; + this.outerRadius = (helpers.min([this.chart.width,this.chart.height]) - this.options.segmentStrokeWidth/2)/2; + + this.SegmentArc = Chart.Arc.extend({ + ctx : this.chart.ctx, + x : this.chart.width/2, + y : this.chart.height/2 + }); + + //Set up tooltip events on the chart + if (this.options.showTooltips){ + helpers.bindEvents(this, this.options.tooltipEvents, function(evt){ + var activeSegments = (evt.type !== 'mouseout') ? this.getSegmentsAtEvent(evt) : []; + + helpers.each(this.segments,function(segment){ + segment.restore(["fillColor"]); + }); + helpers.each(activeSegments,function(activeSegment){ + activeSegment.fillColor = activeSegment.highlightColor; + }); + this.showTooltip(activeSegments); + }); + } + this.calculateTotal(data); + + helpers.each(data,function(datapoint, index){ + if (!datapoint.color) { + datapoint.color = 'hsl(' + (360 * index / data.length) + ', 100%, 50%)'; + } + this.addData(datapoint, index, true); + },this); + + this.render(); + }, + getSegmentsAtEvent : function(e){ + var segmentsArray = []; + + var location = helpers.getRelativePosition(e); + + helpers.each(this.segments,function(segment){ + if (segment.inRange(location.x,location.y)) segmentsArray.push(segment); + },this); + return segmentsArray; + }, + addData : function(segment, atIndex, silent){ + var index = atIndex !== undefined ? atIndex : this.segments.length; + if ( typeof(segment.color) === "undefined" ) { + segment.color = Chart.defaults.global.segmentColorDefault[index % Chart.defaults.global.segmentColorDefault.length]; + segment.highlight = Chart.defaults.global.segmentHighlightColorDefaults[index % Chart.defaults.global.segmentHighlightColorDefaults.length]; + } + this.segments.splice(index, 0, new this.SegmentArc({ + value : segment.value, + outerRadius : (this.options.animateScale) ? 0 : this.outerRadius, + innerRadius : (this.options.animateScale) ? 0 : (this.outerRadius/100) * this.options.percentageInnerCutout, + fillColor : segment.color, + highlightColor : segment.highlight || segment.color, + showStroke : this.options.segmentShowStroke, + strokeWidth : this.options.segmentStrokeWidth, + strokeColor : this.options.segmentStrokeColor, + startAngle : Math.PI * 1.5, + circumference : (this.options.animateRotate) ? 0 : this.calculateCircumference(segment.value), + label : segment.label + })); + if (!silent){ + this.reflow(); + this.update(); + } + }, + calculateCircumference : function(value) { + if ( this.total > 0 ) { + return (Math.PI*2)*(value / this.total); + } else { + return 0; + } + }, + calculateTotal : function(data){ + this.total = 0; + helpers.each(data,function(segment){ + this.total += Math.abs(segment.value); + },this); + }, + update : function(){ + this.calculateTotal(this.segments); + + // Reset any highlight colours before updating. + helpers.each(this.activeElements, function(activeElement){ + activeElement.restore(['fillColor']); + }); + + helpers.each(this.segments,function(segment){ + segment.save(); + }); + this.render(); + }, + + removeData: function(atIndex){ + var indexToDelete = (helpers.isNumber(atIndex)) ? atIndex : this.segments.length-1; + this.segments.splice(indexToDelete, 1); + this.reflow(); + this.update(); + }, + + reflow : function(){ + helpers.extend(this.SegmentArc.prototype,{ + x : this.chart.width/2, + y : this.chart.height/2 + }); + this.outerRadius = (helpers.min([this.chart.width,this.chart.height]) - this.options.segmentStrokeWidth/2)/2; + helpers.each(this.segments, function(segment){ + segment.update({ + outerRadius : this.outerRadius, + innerRadius : (this.outerRadius/100) * this.options.percentageInnerCutout + }); + }, this); + }, + draw : function(easeDecimal){ + var animDecimal = (easeDecimal) ? easeDecimal : 1; + this.clear(); + helpers.each(this.segments,function(segment,index){ + segment.transition({ + circumference : this.calculateCircumference(segment.value), + outerRadius : this.outerRadius, + innerRadius : (this.outerRadius/100) * this.options.percentageInnerCutout + },animDecimal); + + segment.endAngle = segment.startAngle + segment.circumference; + + segment.draw(); + if (index === 0){ + segment.startAngle = Math.PI * 1.5; + } + //Check to see if it's the last segment, if not get the next and update the start angle + if (index < this.segments.length-1){ + this.segments[index+1].startAngle = segment.endAngle; + } + },this); + + } + }); + + Chart.types.Doughnut.extend({ + name : "Pie", + defaults : helpers.merge(defaultConfig,{percentageInnerCutout : 0}) + }); + +}).call(this); + +(function(){ + "use strict"; + + var root = this, + Chart = root.Chart, + helpers = Chart.helpers; + + var defaultConfig = { + + ///Boolean - Whether grid lines are shown across the chart + scaleShowGridLines : true, + + //String - Colour of the grid lines + scaleGridLineColor : "rgba(0,0,0,.05)", + + //Number - Width of the grid lines + scaleGridLineWidth : 1, + + //Boolean - Whether to show horizontal lines (except X axis) + scaleShowHorizontalLines: true, + + //Boolean - Whether to show vertical lines (except Y axis) + scaleShowVerticalLines: true, + + //Boolean - Whether the line is curved between points + bezierCurve : true, + + //Number - Tension of the bezier curve between points + bezierCurveTension : 0.4, + + //Boolean - Whether to show a dot for each point + pointDot : true, + + //Number - Radius of each point dot in pixels + pointDotRadius : 4, + + //Number - Pixel width of point dot stroke + pointDotStrokeWidth : 1, + + //Number - amount extra to add to the radius to cater for hit detection outside the drawn point + pointHitDetectionRadius : 20, + + //Boolean - Whether to show a stroke for datasets + datasetStroke : true, + + //Number - Pixel width of dataset stroke + datasetStrokeWidth : 2, + + //Boolean - Whether to fill the dataset with a colour + datasetFill : true, + + //String - A legend template + legendTemplate : "
    -legend\"><% for (var i=0; i
  • \"><%if(datasets[i].label){%><%=datasets[i].label%><%}%>
    • <%}%>
", + + //Boolean - Whether to horizontally center the label and point dot inside the grid + offsetGridLines : false + + }; + + + Chart.Type.extend({ + name: "Line", + defaults : defaultConfig, + initialize: function(data){ + //Declare the extension of the default point, to cater for the options passed in to the constructor + this.PointClass = Chart.Point.extend({ + offsetGridLines : this.options.offsetGridLines, + strokeWidth : this.options.pointDotStrokeWidth, + radius : this.options.pointDotRadius, + display: this.options.pointDot, + hitDetectionRadius : this.options.pointHitDetectionRadius, + ctx : this.chart.ctx, + inRange : function(mouseX){ + return (Math.pow(mouseX-this.x, 2) < Math.pow(this.radius + this.hitDetectionRadius,2)); + } + }); + + this.datasets = []; + + //Set up tooltip events on the chart + if (this.options.showTooltips){ + helpers.bindEvents(this, this.options.tooltipEvents, function(evt){ + var activePoints = (evt.type !== 'mouseout') ? this.getPointsAtEvent(evt) : []; + this.eachPoints(function(point){ + point.restore(['fillColor', 'strokeColor']); + }); + helpers.each(activePoints, function(activePoint){ + activePoint.fillColor = activePoint.highlightFill; + activePoint.strokeColor = activePoint.highlightStroke; + }); + this.showTooltip(activePoints); + }); + } + + //Iterate through each of the datasets, and build this into a property of the chart + helpers.each(data.datasets,function(dataset){ + + var datasetObject = { + label : dataset.label || null, + fillColor : dataset.fillColor, + strokeColor : dataset.strokeColor, + pointColor : dataset.pointColor, + pointStrokeColor : dataset.pointStrokeColor, + points : [] + }; + + this.datasets.push(datasetObject); + + + helpers.each(dataset.data,function(dataPoint,index){ + //Add a new point for each piece of data, passing any required data to draw. + datasetObject.points.push(new this.PointClass({ + value : dataPoint, + label : data.labels[index], + datasetLabel: dataset.label, + strokeColor : dataset.pointStrokeColor, + fillColor : dataset.pointColor, + highlightFill : dataset.pointHighlightFill || dataset.pointColor, + highlightStroke : dataset.pointHighlightStroke || dataset.pointStrokeColor + })); + },this); + + this.buildScale(data.labels); + + + this.eachPoints(function(point, index){ + helpers.extend(point, { + x: this.scale.calculateX(index), + y: this.scale.endPoint + }); + point.save(); + }, this); + + },this); + + + this.render(); + }, + update : function(){ + this.scale.update(); + // Reset any highlight colours before updating. + helpers.each(this.activeElements, function(activeElement){ + activeElement.restore(['fillColor', 'strokeColor']); + }); + this.eachPoints(function(point){ + point.save(); + }); + this.render(); + }, + eachPoints : function(callback){ + helpers.each(this.datasets,function(dataset){ + helpers.each(dataset.points,callback,this); + },this); + }, + getPointsAtEvent : function(e){ + var pointsArray = [], + eventPosition = helpers.getRelativePosition(e); + helpers.each(this.datasets,function(dataset){ + helpers.each(dataset.points,function(point){ + if (point.inRange(eventPosition.x,eventPosition.y)) pointsArray.push(point); + }); + },this); + return pointsArray; + }, + buildScale : function(labels){ + var self = this; + + var dataTotal = function(){ + var values = []; + self.eachPoints(function(point){ + values.push(point.value); + }); + + return values; + }; + + var scaleOptions = { + templateString : this.options.scaleLabel, + height : this.chart.height, + width : this.chart.width, + ctx : this.chart.ctx, + textColor : this.options.scaleFontColor, + offsetGridLines : this.options.offsetGridLines, + fontSize : this.options.scaleFontSize, + fontStyle : this.options.scaleFontStyle, + fontFamily : this.options.scaleFontFamily, + valuesCount : labels.length, + beginAtZero : this.options.scaleBeginAtZero, + integersOnly : this.options.scaleIntegersOnly, + calculateYRange : function(currentHeight){ + var updatedRanges = helpers.calculateScaleRange( + dataTotal(), + currentHeight, + this.fontSize, + this.beginAtZero, + this.integersOnly + ); + helpers.extend(this, updatedRanges); + }, + xLabels : labels, + font : helpers.fontString(this.options.scaleFontSize, this.options.scaleFontStyle, this.options.scaleFontFamily), + lineWidth : this.options.scaleLineWidth, + lineColor : this.options.scaleLineColor, + showHorizontalLines : this.options.scaleShowHorizontalLines, + showVerticalLines : this.options.scaleShowVerticalLines, + gridLineWidth : (this.options.scaleShowGridLines) ? this.options.scaleGridLineWidth : 0, + gridLineColor : (this.options.scaleShowGridLines) ? this.options.scaleGridLineColor : "rgba(0,0,0,0)", + padding: (this.options.showScale) ? 0 : this.options.pointDotRadius + this.options.pointDotStrokeWidth, + showLabels : this.options.scaleShowLabels, + display : this.options.showScale + }; + + if (this.options.scaleOverride){ + helpers.extend(scaleOptions, { + calculateYRange: helpers.noop, + steps: this.options.scaleSteps, + stepValue: this.options.scaleStepWidth, + min: this.options.scaleStartValue, + max: this.options.scaleStartValue + (this.options.scaleSteps * this.options.scaleStepWidth) + }); + } + + + this.scale = new Chart.Scale(scaleOptions); + }, + addData : function(valuesArray,label){ + //Map the values array for each of the datasets + + helpers.each(valuesArray,function(value,datasetIndex){ + //Add a new point for each piece of data, passing any required data to draw. + this.datasets[datasetIndex].points.push(new this.PointClass({ + value : value, + label : label, + datasetLabel: this.datasets[datasetIndex].label, + x: this.scale.calculateX(this.scale.valuesCount+1), + y: this.scale.endPoint, + strokeColor : this.datasets[datasetIndex].pointStrokeColor, + fillColor : this.datasets[datasetIndex].pointColor + })); + },this); + + this.scale.addXLabel(label); + //Then re-render the chart. + this.update(); + }, + removeData : function(){ + this.scale.removeXLabel(); + //Then re-render the chart. + helpers.each(this.datasets,function(dataset){ + dataset.points.shift(); + },this); + this.update(); + }, + reflow : function(){ + var newScaleProps = helpers.extend({ + height : this.chart.height, + width : this.chart.width + }); + this.scale.update(newScaleProps); + }, + draw : function(ease){ + var easingDecimal = ease || 1; + this.clear(); + + var ctx = this.chart.ctx; + + // Some helper methods for getting the next/prev points + var hasValue = function(item){ + return item.value !== null; + }, + nextPoint = function(point, collection, index){ + return helpers.findNextWhere(collection, hasValue, index) || point; + }, + previousPoint = function(point, collection, index){ + return helpers.findPreviousWhere(collection, hasValue, index) || point; + }; + + if (!this.scale) return; + this.scale.draw(easingDecimal); + + + helpers.each(this.datasets,function(dataset){ + var pointsWithValues = helpers.where(dataset.points, hasValue); + + //Transition each point first so that the line and point drawing isn't out of sync + //We can use this extra loop to calculate the control points of this dataset also in this loop + + helpers.each(dataset.points, function(point, index){ + if (point.hasValue()){ + point.transition({ + y : this.scale.calculateY(point.value), + x : this.scale.calculateX(index) + }, easingDecimal); + } + },this); + + + // Control points need to be calculated in a separate loop, because we need to know the current x/y of the point + // This would cause issues when there is no animation, because the y of the next point would be 0, so beziers would be skewed + if (this.options.bezierCurve){ + helpers.each(pointsWithValues, function(point, index){ + var tension = (index > 0 && index < pointsWithValues.length - 1) ? this.options.bezierCurveTension : 0; + point.controlPoints = helpers.splineCurve( + previousPoint(point, pointsWithValues, index), + point, + nextPoint(point, pointsWithValues, index), + tension + ); + + // Prevent the bezier going outside of the bounds of the graph + + // Cap puter bezier handles to the upper/lower scale bounds + if (point.controlPoints.outer.y > this.scale.endPoint){ + point.controlPoints.outer.y = this.scale.endPoint; + } + else if (point.controlPoints.outer.y < this.scale.startPoint){ + point.controlPoints.outer.y = this.scale.startPoint; + } + + // Cap inner bezier handles to the upper/lower scale bounds + if (point.controlPoints.inner.y > this.scale.endPoint){ + point.controlPoints.inner.y = this.scale.endPoint; + } + else if (point.controlPoints.inner.y < this.scale.startPoint){ + point.controlPoints.inner.y = this.scale.startPoint; + } + },this); + } + + + //Draw the line between all the points + ctx.lineWidth = this.options.datasetStrokeWidth; + ctx.strokeStyle = dataset.strokeColor; + ctx.beginPath(); + + helpers.each(pointsWithValues, function(point, index){ + if (index === 0){ + ctx.moveTo(point.x, point.y); + } + else{ + if(this.options.bezierCurve){ + var previous = previousPoint(point, pointsWithValues, index); + + ctx.bezierCurveTo( + previous.controlPoints.outer.x, + previous.controlPoints.outer.y, + point.controlPoints.inner.x, + point.controlPoints.inner.y, + point.x, + point.y + ); + } + else{ + ctx.lineTo(point.x,point.y); + } + } + }, this); + + if (this.options.datasetStroke) { + ctx.stroke(); + } + + if (this.options.datasetFill && pointsWithValues.length > 0){ + //Round off the line by going to the base of the chart, back to the start, then fill. + ctx.lineTo(pointsWithValues[pointsWithValues.length - 1].x, this.scale.endPoint); + ctx.lineTo(pointsWithValues[0].x, this.scale.endPoint); + ctx.fillStyle = dataset.fillColor; + ctx.closePath(); + ctx.fill(); + } + + //Now draw the points over the line + //A little inefficient double looping, but better than the line + //lagging behind the point positions + helpers.each(pointsWithValues,function(point){ + point.draw(); + }); + },this); + } + }); + + +}).call(this); + +(function(){ + "use strict"; + + var root = this, + Chart = root.Chart, + //Cache a local reference to Chart.helpers + helpers = Chart.helpers; + + var defaultConfig = { + //Boolean - Show a backdrop to the scale label + scaleShowLabelBackdrop : true, + + //String - The colour of the label backdrop + scaleBackdropColor : "rgba(255,255,255,0.75)", + + // Boolean - Whether the scale should begin at zero + scaleBeginAtZero : true, + + //Number - The backdrop padding above & below the label in pixels + scaleBackdropPaddingY : 2, + + //Number - The backdrop padding to the side of the label in pixels + scaleBackdropPaddingX : 2, + + //Boolean - Show line for each value in the scale + scaleShowLine : true, + + //Boolean - Stroke a line around each segment in the chart + segmentShowStroke : true, + + //String - The colour of the stroke on each segment. + segmentStrokeColor : "#fff", + + //Number - The width of the stroke value in pixels + segmentStrokeWidth : 2, + + //Number - Amount of animation steps + animationSteps : 100, + + //String - Animation easing effect. + animationEasing : "easeOutBounce", + + //Boolean - Whether to animate the rotation of the chart + animateRotate : true, + + //Boolean - Whether to animate scaling the chart from the centre + animateScale : false, + + //String - A legend template + legendTemplate : "
    -legend\"><% for (var i=0; i
  • \"><%if(segments[i].label){%><%=segments[i].label%><%}%>
    • <%}%>
" + }; + + + Chart.Type.extend({ + //Passing in a name registers this chart in the Chart namespace + name: "PolarArea", + //Providing a defaults will also register the deafults in the chart namespace + defaults : defaultConfig, + //Initialize is fired when the chart is initialized - Data is passed in as a parameter + //Config is automatically merged by the core of Chart.js, and is available at this.options + initialize: function(data){ + this.segments = []; + //Declare segment class as a chart instance specific class, so it can share props for this instance + this.SegmentArc = Chart.Arc.extend({ + showStroke : this.options.segmentShowStroke, + strokeWidth : this.options.segmentStrokeWidth, + strokeColor : this.options.segmentStrokeColor, + ctx : this.chart.ctx, + innerRadius : 0, + x : this.chart.width/2, + y : this.chart.height/2 + }); + this.scale = new Chart.RadialScale({ + display: this.options.showScale, + fontStyle: this.options.scaleFontStyle, + fontSize: this.options.scaleFontSize, + fontFamily: this.options.scaleFontFamily, + fontColor: this.options.scaleFontColor, + showLabels: this.options.scaleShowLabels, + showLabelBackdrop: this.options.scaleShowLabelBackdrop, + backdropColor: this.options.scaleBackdropColor, + backdropPaddingY : this.options.scaleBackdropPaddingY, + backdropPaddingX: this.options.scaleBackdropPaddingX, + lineWidth: (this.options.scaleShowLine) ? this.options.scaleLineWidth : 0, + lineColor: this.options.scaleLineColor, + lineArc: true, + width: this.chart.width, + height: this.chart.height, + xCenter: this.chart.width/2, + yCenter: this.chart.height/2, + ctx : this.chart.ctx, + templateString: this.options.scaleLabel, + valuesCount: data.length + }); + + this.updateScaleRange(data); + + this.scale.update(); + + helpers.each(data,function(segment,index){ + this.addData(segment,index,true); + },this); + + //Set up tooltip events on the chart + if (this.options.showTooltips){ + helpers.bindEvents(this, this.options.tooltipEvents, function(evt){ + var activeSegments = (evt.type !== 'mouseout') ? this.getSegmentsAtEvent(evt) : []; + helpers.each(this.segments,function(segment){ + segment.restore(["fillColor"]); + }); + helpers.each(activeSegments,function(activeSegment){ + activeSegment.fillColor = activeSegment.highlightColor; + }); + this.showTooltip(activeSegments); + }); + } + + this.render(); + }, + getSegmentsAtEvent : function(e){ + var segmentsArray = []; + + var location = helpers.getRelativePosition(e); + + helpers.each(this.segments,function(segment){ + if (segment.inRange(location.x,location.y)) segmentsArray.push(segment); + },this); + return segmentsArray; + }, + addData : function(segment, atIndex, silent){ + var index = atIndex || this.segments.length; + + this.segments.splice(index, 0, new this.SegmentArc({ + fillColor: segment.color, + highlightColor: segment.highlight || segment.color, + label: segment.label, + value: segment.value, + outerRadius: (this.options.animateScale) ? 0 : this.scale.calculateCenterOffset(segment.value), + circumference: (this.options.animateRotate) ? 0 : this.scale.getCircumference(), + startAngle: Math.PI * 1.5 + })); + if (!silent){ + this.reflow(); + this.update(); + } + }, + removeData: function(atIndex){ + var indexToDelete = (helpers.isNumber(atIndex)) ? atIndex : this.segments.length-1; + this.segments.splice(indexToDelete, 1); + this.reflow(); + this.update(); + }, + calculateTotal: function(data){ + this.total = 0; + helpers.each(data,function(segment){ + this.total += segment.value; + },this); + this.scale.valuesCount = this.segments.length; + }, + updateScaleRange: function(datapoints){ + var valuesArray = []; + helpers.each(datapoints,function(segment){ + valuesArray.push(segment.value); + }); + + var scaleSizes = (this.options.scaleOverride) ? + { + steps: this.options.scaleSteps, + stepValue: this.options.scaleStepWidth, + min: this.options.scaleStartValue, + max: this.options.scaleStartValue + (this.options.scaleSteps * this.options.scaleStepWidth) + } : + helpers.calculateScaleRange( + valuesArray, + helpers.min([this.chart.width, this.chart.height])/2, + this.options.scaleFontSize, + this.options.scaleBeginAtZero, + this.options.scaleIntegersOnly + ); + + helpers.extend( + this.scale, + scaleSizes, + { + size: helpers.min([this.chart.width, this.chart.height]), + xCenter: this.chart.width/2, + yCenter: this.chart.height/2 + } + ); + + }, + update : function(){ + this.calculateTotal(this.segments); + + helpers.each(this.segments,function(segment){ + segment.save(); + }); + + this.reflow(); + this.render(); + }, + reflow : function(){ + helpers.extend(this.SegmentArc.prototype,{ + x : this.chart.width/2, + y : this.chart.height/2 + }); + this.updateScaleRange(this.segments); + this.scale.update(); + + helpers.extend(this.scale,{ + xCenter: this.chart.width/2, + yCenter: this.chart.height/2 + }); + + helpers.each(this.segments, function(segment){ + segment.update({ + outerRadius : this.scale.calculateCenterOffset(segment.value) + }); + }, this); + + }, + draw : function(ease){ + var easingDecimal = ease || 1; + //Clear & draw the canvas + this.clear(); + helpers.each(this.segments,function(segment, index){ + segment.transition({ + circumference : this.scale.getCircumference(), + outerRadius : this.scale.calculateCenterOffset(segment.value) + },easingDecimal); + + segment.endAngle = segment.startAngle + segment.circumference; + + // If we've removed the first segment we need to set the first one to + // start at the top. + if (index === 0){ + segment.startAngle = Math.PI * 1.5; + } + + //Check to see if it's the last segment, if not get the next and update the start angle + if (index < this.segments.length - 1){ + this.segments[index+1].startAngle = segment.endAngle; + } + segment.draw(); + }, this); + this.scale.draw(); + } + }); + +}).call(this); + +(function(){ + "use strict"; + + var root = this, + Chart = root.Chart, + helpers = Chart.helpers; + + + + Chart.Type.extend({ + name: "Radar", + defaults:{ + //Boolean - Whether to show lines for each scale point + scaleShowLine : true, + + //Boolean - Whether we show the angle lines out of the radar + angleShowLineOut : true, + + //Boolean - Whether to show labels on the scale + scaleShowLabels : false, + + // Boolean - Whether the scale should begin at zero + scaleBeginAtZero : true, + + //String - Colour of the angle line + angleLineColor : "rgba(0,0,0,.1)", + + //Number - Pixel width of the angle line + angleLineWidth : 1, + + //String - Point label font declaration + pointLabelFontFamily : "'Arial'", + + //String - Point label font weight + pointLabelFontStyle : "normal", + + //Number - Point label font size in pixels + pointLabelFontSize : 10, + + //String - Point label font colour + pointLabelFontColor : "#666", + + //Boolean - Whether to show a dot for each point + pointDot : true, + + //Number - Radius of each point dot in pixels + pointDotRadius : 3, + + //Number - Pixel width of point dot stroke + pointDotStrokeWidth : 1, + + //Number - amount extra to add to the radius to cater for hit detection outside the drawn point + pointHitDetectionRadius : 20, + + //Boolean - Whether to show a stroke for datasets + datasetStroke : true, + + //Number - Pixel width of dataset stroke + datasetStrokeWidth : 2, + + //Boolean - Whether to fill the dataset with a colour + datasetFill : true, + + //String - A legend template + legendTemplate : "
    -legend\"><% for (var i=0; i
  • \"><%if(datasets[i].label){%><%=datasets[i].label%><%}%>
    • <%}%>
" + + }, + + initialize: function(data){ + this.PointClass = Chart.Point.extend({ + strokeWidth : this.options.pointDotStrokeWidth, + radius : this.options.pointDotRadius, + display: this.options.pointDot, + hitDetectionRadius : this.options.pointHitDetectionRadius, + ctx : this.chart.ctx + }); + + this.datasets = []; + + this.buildScale(data); + + //Set up tooltip events on the chart + if (this.options.showTooltips){ + helpers.bindEvents(this, this.options.tooltipEvents, function(evt){ + var activePointsCollection = (evt.type !== 'mouseout') ? this.getPointsAtEvent(evt) : []; + + this.eachPoints(function(point){ + point.restore(['fillColor', 'strokeColor']); + }); + helpers.each(activePointsCollection, function(activePoint){ + activePoint.fillColor = activePoint.highlightFill; + activePoint.strokeColor = activePoint.highlightStroke; + }); + + this.showTooltip(activePointsCollection); + }); + } + + //Iterate through each of the datasets, and build this into a property of the chart + helpers.each(data.datasets,function(dataset){ + + var datasetObject = { + label: dataset.label || null, + fillColor : dataset.fillColor, + strokeColor : dataset.strokeColor, + pointColor : dataset.pointColor, + pointStrokeColor : dataset.pointStrokeColor, + points : [] + }; + + this.datasets.push(datasetObject); + + helpers.each(dataset.data,function(dataPoint,index){ + //Add a new point for each piece of data, passing any required data to draw. + var pointPosition; + if (!this.scale.animation){ + pointPosition = this.scale.getPointPosition(index, this.scale.calculateCenterOffset(dataPoint)); + } + datasetObject.points.push(new this.PointClass({ + value : dataPoint, + label : data.labels[index], + datasetLabel: dataset.label, + x: (this.options.animation) ? this.scale.xCenter : pointPosition.x, + y: (this.options.animation) ? this.scale.yCenter : pointPosition.y, + strokeColor : dataset.pointStrokeColor, + fillColor : dataset.pointColor, + highlightFill : dataset.pointHighlightFill || dataset.pointColor, + highlightStroke : dataset.pointHighlightStroke || dataset.pointStrokeColor + })); + },this); + + },this); + + this.render(); + }, + eachPoints : function(callback){ + helpers.each(this.datasets,function(dataset){ + helpers.each(dataset.points,callback,this); + },this); + }, + + getPointsAtEvent : function(evt){ + var mousePosition = helpers.getRelativePosition(evt), + fromCenter = helpers.getAngleFromPoint({ + x: this.scale.xCenter, + y: this.scale.yCenter + }, mousePosition); + + var anglePerIndex = (Math.PI * 2) /this.scale.valuesCount, + pointIndex = Math.round((fromCenter.angle - Math.PI * 1.5) / anglePerIndex), + activePointsCollection = []; + + // If we're at the top, make the pointIndex 0 to get the first of the array. + if (pointIndex >= this.scale.valuesCount || pointIndex < 0){ + pointIndex = 0; + } + + if (fromCenter.distance <= this.scale.drawingArea){ + helpers.each(this.datasets, function(dataset){ + activePointsCollection.push(dataset.points[pointIndex]); + }); + } + + return activePointsCollection; + }, + + buildScale : function(data){ + this.scale = new Chart.RadialScale({ + display: this.options.showScale, + fontStyle: this.options.scaleFontStyle, + fontSize: this.options.scaleFontSize, + fontFamily: this.options.scaleFontFamily, + fontColor: this.options.scaleFontColor, + showLabels: this.options.scaleShowLabels, + showLabelBackdrop: this.options.scaleShowLabelBackdrop, + backdropColor: this.options.scaleBackdropColor, + backgroundColors: this.options.scaleBackgroundColors, + backdropPaddingY : this.options.scaleBackdropPaddingY, + backdropPaddingX: this.options.scaleBackdropPaddingX, + lineWidth: (this.options.scaleShowLine) ? this.options.scaleLineWidth : 0, + lineColor: this.options.scaleLineColor, + angleLineColor : this.options.angleLineColor, + angleLineWidth : (this.options.angleShowLineOut) ? this.options.angleLineWidth : 0, + // Point labels at the edge of each line + pointLabelFontColor : this.options.pointLabelFontColor, + pointLabelFontSize : this.options.pointLabelFontSize, + pointLabelFontFamily : this.options.pointLabelFontFamily, + pointLabelFontStyle : this.options.pointLabelFontStyle, + height : this.chart.height, + width: this.chart.width, + xCenter: this.chart.width/2, + yCenter: this.chart.height/2, + ctx : this.chart.ctx, + templateString: this.options.scaleLabel, + labels: data.labels, + valuesCount: data.datasets[0].data.length + }); + + this.scale.setScaleSize(); + this.updateScaleRange(data.datasets); + this.scale.buildYLabels(); + }, + updateScaleRange: function(datasets){ + var valuesArray = (function(){ + var totalDataArray = []; + helpers.each(datasets,function(dataset){ + if (dataset.data){ + totalDataArray = totalDataArray.concat(dataset.data); + } + else { + helpers.each(dataset.points, function(point){ + totalDataArray.push(point.value); + }); + } + }); + return totalDataArray; + })(); + + + var scaleSizes = (this.options.scaleOverride) ? + { + steps: this.options.scaleSteps, + stepValue: this.options.scaleStepWidth, + min: this.options.scaleStartValue, + max: this.options.scaleStartValue + (this.options.scaleSteps * this.options.scaleStepWidth) + } : + helpers.calculateScaleRange( + valuesArray, + helpers.min([this.chart.width, this.chart.height])/2, + this.options.scaleFontSize, + this.options.scaleBeginAtZero, + this.options.scaleIntegersOnly + ); + + helpers.extend( + this.scale, + scaleSizes + ); + + }, + addData : function(valuesArray,label){ + //Map the values array for each of the datasets + this.scale.valuesCount++; + helpers.each(valuesArray,function(value,datasetIndex){ + var pointPosition = this.scale.getPointPosition(this.scale.valuesCount, this.scale.calculateCenterOffset(value)); + this.datasets[datasetIndex].points.push(new this.PointClass({ + value : value, + label : label, + datasetLabel: this.datasets[datasetIndex].label, + x: pointPosition.x, + y: pointPosition.y, + strokeColor : this.datasets[datasetIndex].pointStrokeColor, + fillColor : this.datasets[datasetIndex].pointColor + })); + },this); + + this.scale.labels.push(label); + + this.reflow(); + + this.update(); + }, + removeData : function(){ + this.scale.valuesCount--; + this.scale.labels.shift(); + helpers.each(this.datasets,function(dataset){ + dataset.points.shift(); + },this); + this.reflow(); + this.update(); + }, + update : function(){ + this.eachPoints(function(point){ + point.save(); + }); + this.reflow(); + this.render(); + }, + reflow: function(){ + helpers.extend(this.scale, { + width : this.chart.width, + height: this.chart.height, + size : helpers.min([this.chart.width, this.chart.height]), + xCenter: this.chart.width/2, + yCenter: this.chart.height/2 + }); + this.updateScaleRange(this.datasets); + this.scale.setScaleSize(); + this.scale.buildYLabels(); + }, + draw : function(ease){ + var easeDecimal = ease || 1, + ctx = this.chart.ctx; + this.clear(); + this.scale.draw(); + + helpers.each(this.datasets,function(dataset){ + + //Transition each point first so that the line and point drawing isn't out of sync + helpers.each(dataset.points,function(point,index){ + if (point.hasValue()){ + point.transition(this.scale.getPointPosition(index, this.scale.calculateCenterOffset(point.value)), easeDecimal); + } + },this); + + + + //Draw the line between all the points + ctx.lineWidth = this.options.datasetStrokeWidth; + ctx.strokeStyle = dataset.strokeColor; + ctx.beginPath(); + helpers.each(dataset.points,function(point,index){ + if (index === 0){ + ctx.moveTo(point.x,point.y); + } + else{ + ctx.lineTo(point.x,point.y); + } + },this); + ctx.closePath(); + ctx.stroke(); + + ctx.fillStyle = dataset.fillColor; + if(this.options.datasetFill){ + ctx.fill(); + } + //Now draw the points over the line + //A little inefficient double looping, but better than the line + //lagging behind the point positions + helpers.each(dataset.points,function(point){ + if (point.hasValue()){ + point.draw(); + } + }); + + },this); + + } + + }); + + + + + +}).call(this); diff --git a/snapshots/muneeb-mbytes_pulpino__spi_master__subsystem_verification_pr28/sim/questa_sim/basic_write_read_reg_test/html_cov_report/lib/Chart/src/Chart.Bar.js b/snapshots/muneeb-mbytes_pulpino__spi_master__subsystem_verification_pr28/sim/questa_sim/basic_write_read_reg_test/html_cov_report/lib/Chart/src/Chart.Bar.js new file mode 100644 index 0000000000000000000000000000000000000000..81532b4fd261bcaf96f848f1977d98bf97dd311f --- /dev/null +++ b/snapshots/muneeb-mbytes_pulpino__spi_master__subsystem_verification_pr28/sim/questa_sim/basic_write_read_reg_test/html_cov_report/lib/Chart/src/Chart.Bar.js @@ -0,0 +1,303 @@ +(function(){ + "use strict"; + + var root = this, + Chart = root.Chart, + helpers = Chart.helpers; + + + var defaultConfig = { + //Boolean - Whether the scale should start at zero, or an order of magnitude down from the lowest value + scaleBeginAtZero : true, + + //Boolean - Whether grid lines are shown across the chart + scaleShowGridLines : true, + + //String - Colour of the grid lines + scaleGridLineColor : "rgba(0,0,0,.05)", + + //Number - Width of the grid lines + scaleGridLineWidth : 1, + + //Boolean - Whether to show horizontal lines (except X axis) + scaleShowHorizontalLines: true, + + //Boolean - Whether to show vertical lines (except Y axis) + scaleShowVerticalLines: true, + + //Boolean - If there is a stroke on each bar + barShowStroke : true, + + //Number - Pixel width of the bar stroke + barStrokeWidth : 2, + + //Number - Spacing between each of the X value sets + barValueSpacing : 5, + + //Number - Spacing between data sets within X values + barDatasetSpacing : 1, + + //String - A legend template + legendTemplate : "
    -legend\"><% for (var i=0; i
  • \"><%if(datasets[i].label){%><%=datasets[i].label%><%}%>
    • <%}%>
" + + }; + + + Chart.Type.extend({ + name: "Bar", + defaults : defaultConfig, + initialize: function(data){ + + //Expose options as a scope variable here so we can access it in the ScaleClass + var options = this.options; + + this.ScaleClass = Chart.Scale.extend({ + offsetGridLines : true, + calculateBarX : function(datasetCount, datasetIndex, barIndex){ + //Reusable method for calculating the xPosition of a given bar based on datasetIndex & width of the bar + var xWidth = this.calculateBaseWidth(), + xAbsolute = this.calculateX(barIndex) - (xWidth/2), + barWidth = this.calculateBarWidth(datasetCount); + + return xAbsolute + (barWidth * datasetIndex) + (datasetIndex * options.barDatasetSpacing) + barWidth/2; + }, + calculateBaseWidth : function(){ + return (this.calculateX(1) - this.calculateX(0)) - (2*options.barValueSpacing); + }, + calculateBarWidth : function(datasetCount){ + //The padding between datasets is to the right of each bar, providing that there are more than 1 dataset + var baseWidth = this.calculateBaseWidth() - ((datasetCount - 1) * options.barDatasetSpacing); + + return (baseWidth / datasetCount); + } + }); + + this.datasets = []; + + //Set up tooltip events on the chart + if (this.options.showTooltips){ + helpers.bindEvents(this, this.options.tooltipEvents, function(evt){ + var activeBars = (evt.type !== 'mouseout') ? this.getBarsAtEvent(evt) : []; + + this.eachBars(function(bar){ + bar.restore(['fillColor', 'strokeColor']); + }); + helpers.each(activeBars, function(activeBar){ + activeBar.fillColor = activeBar.highlightFill; + activeBar.strokeColor = activeBar.highlightStroke; + }); + this.showTooltip(activeBars); + }); + } + + //Declare the extension of the default point, to cater for the options passed in to the constructor + this.BarClass = Chart.Rectangle.extend({ + strokeWidth : this.options.barStrokeWidth, + showStroke : this.options.barShowStroke, + ctx : this.chart.ctx + }); + + //Iterate through each of the datasets, and build this into a property of the chart + helpers.each(data.datasets,function(dataset,datasetIndex){ + + var datasetObject = { + label : dataset.label || null, + fillColor : dataset.fillColor, + strokeColor : dataset.strokeColor, + bars : [] + }; + + this.datasets.push(datasetObject); + + helpers.each(dataset.data,function(dataPoint,index){ + //Add a new point for each piece of data, passing any required data to draw. + datasetObject.bars.push(new this.BarClass({ + value : dataPoint, + label : data.labels[index], + datasetLabel: dataset.label, + strokeColor : dataset.strokeColor, + fillColor : dataset.fillColor, + highlightFill : dataset.highlightFill || dataset.fillColor, + highlightStroke : dataset.highlightStroke || dataset.strokeColor + })); + },this); + + },this); + + this.buildScale(data.labels); + + this.BarClass.prototype.base = this.scale.endPoint; + + this.eachBars(function(bar, index, datasetIndex){ + helpers.extend(bar, { + width : this.scale.calculateBarWidth(this.datasets.length), + x: this.scale.calculateBarX(this.datasets.length, datasetIndex, index), + y: this.scale.endPoint + }); + bar.save(); + }, this); + + this.render(); + }, + update : function(){ + this.scale.update(); + // Reset any highlight colours before updating. + helpers.each(this.activeElements, function(activeElement){ + activeElement.restore(['fillColor', 'strokeColor']); + }); + + this.eachBars(function(bar){ + bar.save(); + }); + this.render(); + }, + eachBars : function(callback){ + helpers.each(this.datasets,function(dataset, datasetIndex){ + helpers.each(dataset.bars, callback, this, datasetIndex); + },this); + }, + getBarsAtEvent : function(e){ + var barsArray = [], + eventPosition = helpers.getRelativePosition(e), + datasetIterator = function(dataset){ + barsArray.push(dataset.bars[barIndex]); + }, + barIndex; + + for (var datasetIndex = 0; datasetIndex < this.datasets.length; datasetIndex++) { + for (barIndex = 0; barIndex < this.datasets[datasetIndex].bars.length; barIndex++) { + if (this.datasets[datasetIndex].bars[barIndex].inRange(eventPosition.x,eventPosition.y)){ + helpers.each(this.datasets, datasetIterator); + return barsArray; + } + } + } + + return barsArray; + }, + buildScale : function(labels){ + var self = this; + + var dataTotal = function(){ + var values = []; + self.eachBars(function(bar){ + values.push(bar.value); + }); + return values; + }; + + var scaleOptions = { + templateString : this.options.scaleLabel, + height : this.chart.height, + width : this.chart.width, + ctx : this.chart.ctx, + textColor : this.options.scaleFontColor, + fontSize : this.options.scaleFontSize, + fontStyle : this.options.scaleFontStyle, + fontFamily : this.options.scaleFontFamily, + valuesCount : labels.length, + beginAtZero : this.options.scaleBeginAtZero, + integersOnly : this.options.scaleIntegersOnly, + calculateYRange: function(currentHeight){ + var updatedRanges = helpers.calculateScaleRange( + dataTotal(), + currentHeight, + this.fontSize, + this.beginAtZero, + this.integersOnly + ); + helpers.extend(this, updatedRanges); + }, + xLabels : labels, + font : helpers.fontString(this.options.scaleFontSize, this.options.scaleFontStyle, this.options.scaleFontFamily), + lineWidth : this.options.scaleLineWidth, + lineColor : this.options.scaleLineColor, + showHorizontalLines : this.options.scaleShowHorizontalLines, + showVerticalLines : this.options.scaleShowVerticalLines, + gridLineWidth : (this.options.scaleShowGridLines) ? this.options.scaleGridLineWidth : 0, + gridLineColor : (this.options.scaleShowGridLines) ? this.options.scaleGridLineColor : "rgba(0,0,0,0)", + padding : (this.options.showScale) ? 0 : (this.options.barShowStroke) ? this.options.barStrokeWidth : 0, + showLabels : this.options.scaleShowLabels, + display : this.options.showScale + }; + + if (this.options.scaleOverride){ + helpers.extend(scaleOptions, { + calculateYRange: helpers.noop, + steps: this.options.scaleSteps, + stepValue: this.options.scaleStepWidth, + min: this.options.scaleStartValue, + max: this.options.scaleStartValue + (this.options.scaleSteps * this.options.scaleStepWidth) + }); + } + + this.scale = new this.ScaleClass(scaleOptions); + }, + addData : function(valuesArray,label){ + //Map the values array for each of the datasets + helpers.each(valuesArray,function(value,datasetIndex){ + //Add a new point for each piece of data, passing any required data to draw. + this.datasets[datasetIndex].bars.push(new this.BarClass({ + value : value, + label : label, + datasetLabel: this.datasets[datasetIndex].label, + x: this.scale.calculateBarX(this.datasets.length, datasetIndex, this.scale.valuesCount+1), + y: this.scale.endPoint, + width : this.scale.calculateBarWidth(this.datasets.length), + base : this.scale.endPoint, + strokeColor : this.datasets[datasetIndex].strokeColor, + fillColor : this.datasets[datasetIndex].fillColor + })); + },this); + + this.scale.addXLabel(label); + //Then re-render the chart. + this.update(); + }, + removeData : function(){ + this.scale.removeXLabel(); + //Then re-render the chart. + helpers.each(this.datasets,function(dataset){ + dataset.bars.shift(); + },this); + this.update(); + }, + reflow : function(){ + helpers.extend(this.BarClass.prototype,{ + y: this.scale.endPoint, + base : this.scale.endPoint + }); + var newScaleProps = helpers.extend({ + height : this.chart.height, + width : this.chart.width + }); + this.scale.update(newScaleProps); + }, + draw : function(ease){ + var easingDecimal = ease || 1; + this.clear(); + + var ctx = this.chart.ctx; + + this.scale.draw(easingDecimal); + + //Draw all the bars for each dataset + helpers.each(this.datasets,function(dataset,datasetIndex){ + helpers.each(dataset.bars,function(bar,index){ + if (bar.hasValue()){ + bar.base = this.scale.endPoint; + //Transition then draw + bar.transition({ + x : this.scale.calculateBarX(this.datasets.length, datasetIndex, index), + y : this.scale.calculateY(bar.value), + width : this.scale.calculateBarWidth(this.datasets.length) + }, easingDecimal).draw(); + } + },this); + + },this); + } + }); + + +}).call(this); diff --git a/snapshots/muneeb-mbytes_pulpino__spi_master__subsystem_verification_pr28/sim/questa_sim/basic_write_read_reg_test/html_cov_report/lib/Chart/src/Chart.Core.js b/snapshots/muneeb-mbytes_pulpino__spi_master__subsystem_verification_pr28/sim/questa_sim/basic_write_read_reg_test/html_cov_report/lib/Chart/src/Chart.Core.js new file mode 100644 index 0000000000000000000000000000000000000000..16f9d50d1cc16449e54d0bb81674846e38e0f7b2 --- /dev/null +++ b/snapshots/muneeb-mbytes_pulpino__spi_master__subsystem_verification_pr28/sim/questa_sim/basic_write_read_reg_test/html_cov_report/lib/Chart/src/Chart.Core.js @@ -0,0 +1,2245 @@ +/*! + * Chart.js + * http://chartjs.org/ + * Version: {{ version }} + * + * Copyright 2015 Nick Downie + * Released under the MIT license + * https://github.com/nnnick/Chart.js/blob/master/LICENSE.md + */ + + +(function(){ + + "use strict"; + + //Declare root variable - window in the browser, global on the server + var root = this, + previous = root.Chart; + + //Occupy the global variable of Chart, and create a simple base class + var Chart = function(context){ + var chart = this; + this.canvas = context.canvas; + + this.ctx = context; + + //Variables global to the chart + var computeDimension = function(element,dimension) + { + if (element['offset'+dimension]) + { + return element['offset'+dimension]; + } + else + { + return document.defaultView.getComputedStyle(element).getPropertyValue(dimension); + } + }; + + var width = this.width = computeDimension(context.canvas,'Width') || context.canvas.width; + var height = this.height = computeDimension(context.canvas,'Height') || context.canvas.height; + + width = this.width = context.canvas.width; + height = this.height = context.canvas.height; + this.aspectRatio = this.width / this.height; + //High pixel density displays - multiply the size of the canvas height/width by the device pixel ratio, then scale. + helpers.retinaScale(this); + + return this; + }; + //Globally expose the defaults to allow for user updating/changing + Chart.defaults = { + global: { + // Boolean - Whether to animate the chart + animation: true, + + // Number - Number of animation steps + animationSteps: 60, + + // String - Animation easing effect + animationEasing: "easeOutQuart", + + // Boolean - If we should show the scale at all + showScale: true, + + // Boolean - If we want to override with a hard coded scale + scaleOverride: false, + + // ** Required if scaleOverride is true ** + // Number - The number of steps in a hard coded scale + scaleSteps: null, + // Number - The value jump in the hard coded scale + scaleStepWidth: null, + // Number - The scale starting value + scaleStartValue: null, + + // String - Colour of the scale line + scaleLineColor: "rgba(0,0,0,.1)", + + // Number - Pixel width of the scale line + scaleLineWidth: 1, + + // Boolean - Whether to show labels on the scale + scaleShowLabels: true, + + // Interpolated JS string - can access value + scaleLabel: "<%=value%>", + + // Boolean - Whether the scale should stick to integers, and not show any floats even if drawing space is there + scaleIntegersOnly: true, + + // Boolean - Whether the scale should start at zero, or an order of magnitude down from the lowest value + scaleBeginAtZero: false, + + // String - Scale label font declaration for the scale label + scaleFontFamily: "'Helvetica Neue', 'Helvetica', 'Arial', sans-serif", + + // Number - Scale label font size in pixels + scaleFontSize: 12, + + // String - Scale label font weight style + scaleFontStyle: "normal", + + // String - Scale label font colour + scaleFontColor: "#666", + + // Boolean - whether or not the chart should be responsive and resize when the browser does. + responsive: false, + + // Boolean - whether to maintain the starting aspect ratio or not when responsive, if set to false, will take up entire container + maintainAspectRatio: true, + + // Boolean - Determines whether to draw tooltips on the canvas or not - attaches events to touchmove & mousemove + showTooltips: true, + + // Boolean - Determines whether to draw built-in tooltip or call custom tooltip function + customTooltips: false, + + // Array - Array of string names to attach tooltip events + tooltipEvents: ["mousemove", "touchstart", "touchmove", "mouseout"], + + // String - Tooltip background colour + tooltipFillColor: "rgba(0,0,0,0.8)", + + // String - Tooltip label font declaration for the scale label + tooltipFontFamily: "'Helvetica Neue', 'Helvetica', 'Arial', sans-serif", + + // Number - Tooltip label font size in pixels + tooltipFontSize: 14, + + // String - Tooltip font weight style + tooltipFontStyle: "normal", + + // String - Tooltip label font colour + tooltipFontColor: "#fff", + + // String - Tooltip title font declaration for the scale label + tooltipTitleFontFamily: "'Helvetica Neue', 'Helvetica', 'Arial', sans-serif", + + // Number - Tooltip title font size in pixels + tooltipTitleFontSize: 14, + + // String - Tooltip title font weight style + tooltipTitleFontStyle: "bold", + + // String - Tooltip title font colour + tooltipTitleFontColor: "#fff", + + // String - Tooltip title template + tooltipTitleTemplate: "<%= label%>", + + // Number - pixel width of padding around tooltip text + tooltipYPadding: 6, + + // Number - pixel width of padding around tooltip text + tooltipXPadding: 6, + + // Number - Size of the caret on the tooltip + tooltipCaretSize: 8, + + // Number - Pixel radius of the tooltip border + tooltipCornerRadius: 6, + + // Number - Pixel offset from point x to tooltip edge + tooltipXOffset: 10, + + // String - Template string for single tooltips + tooltipTemplate: "<%if (label){%><%=label%>: <%}%><%= value %>", + + // String - Template string for single tooltips + multiTooltipTemplate: "<%= value %>", + + // String - Colour behind the legend colour block + multiTooltipKeyBackground: '#fff', + + // Array - A list of colors to use as the defaults + segmentColorDefault: ["#A6CEE3", "#1F78B4", "#B2DF8A", "#33A02C", "#FB9A99", "#E31A1C", "#FDBF6F", "#FF7F00", "#CAB2D6", "#6A3D9A", "#B4B482", "#B15928" ], + + // Array - A list of highlight colors to use as the defaults + segmentHighlightColorDefaults: [ "#CEF6FF", "#47A0DC", "#DAFFB2", "#5BC854", "#FFC2C1", "#FF4244", "#FFE797", "#FFA728", "#F2DAFE", "#9265C2", "#DCDCAA", "#D98150" ], + + // Function - Will fire on animation progression. + onAnimationProgress: function(){}, + + // Function - Will fire on animation completion. + onAnimationComplete: function(){} + + } + }; + + //Create a dictionary of chart types, to allow for extension of existing types + Chart.types = {}; + + //Global Chart helpers object for utility methods and classes + var helpers = Chart.helpers = {}; + + //-- Basic js utility methods + var each = helpers.each = function(loopable,callback,self){ + var additionalArgs = Array.prototype.slice.call(arguments, 3); + // Check to see if null or undefined firstly. + if (loopable){ + if (loopable.length === +loopable.length){ + var i; + for (i=0; i= 0; i--) { + var currentItem = arrayToSearch[i]; + if (filterCallback(currentItem)){ + return currentItem; + } + } + }, + inherits = helpers.inherits = function(extensions){ + //Basic javascript inheritance based on the model created in Backbone.js + var parent = this; + var ChartElement = (extensions && extensions.hasOwnProperty("constructor")) ? extensions.constructor : function(){ return parent.apply(this, arguments); }; + + var Surrogate = function(){ this.constructor = ChartElement;}; + Surrogate.prototype = parent.prototype; + ChartElement.prototype = new Surrogate(); + + ChartElement.extend = inherits; + + if (extensions) extend(ChartElement.prototype, extensions); + + ChartElement.__super__ = parent.prototype; + + return ChartElement; + }, + noop = helpers.noop = function(){}, + uid = helpers.uid = (function(){ + var id=0; + return function(){ + return "chart-" + id++; + }; + })(), + warn = helpers.warn = function(str){ + //Method for warning of errors + if (window.console && typeof window.console.warn === "function") console.warn(str); + }, + amd = helpers.amd = (typeof define === 'function' && define.amd), + //-- Math methods + isNumber = helpers.isNumber = function(n){ + return !isNaN(parseFloat(n)) && isFinite(n); + }, + max = helpers.max = function(array){ + return Math.max.apply( Math, array ); + }, + min = helpers.min = function(array){ + return Math.min.apply( Math, array ); + }, + cap = helpers.cap = function(valueToCap,maxValue,minValue){ + if(isNumber(maxValue)) { + if( valueToCap > maxValue ) { + return maxValue; + } + } + else if(isNumber(minValue)){ + if ( valueToCap < minValue ){ + return minValue; + } + } + return valueToCap; + }, + getDecimalPlaces = helpers.getDecimalPlaces = function(num){ + if (num%1!==0 && isNumber(num)){ + var s = num.toString(); + if(s.indexOf("e-") < 0){ + // no exponent, e.g. 0.01 + return s.split(".")[1].length; + } + else if(s.indexOf(".") < 0) { + // no decimal point, e.g. 1e-9 + return parseInt(s.split("e-")[1]); + } + else { + // exponent and decimal point, e.g. 1.23e-9 + var parts = s.split(".")[1].split("e-"); + return parts[0].length + parseInt(parts[1]); + } + } + else { + return 0; + } + }, + toRadians = helpers.radians = function(degrees){ + return degrees * (Math.PI/180); + }, + // Gets the angle from vertical upright to the point about a centre. + getAngleFromPoint = helpers.getAngleFromPoint = function(centrePoint, anglePoint){ + var distanceFromXCenter = anglePoint.x - centrePoint.x, + distanceFromYCenter = anglePoint.y - centrePoint.y, + radialDistanceFromCenter = Math.sqrt( distanceFromXCenter * distanceFromXCenter + distanceFromYCenter * distanceFromYCenter); + + + var angle = Math.PI * 2 + Math.atan2(distanceFromYCenter, distanceFromXCenter); + + //If the segment is in the top left quadrant, we need to add another rotation to the angle + if (distanceFromXCenter < 0 && distanceFromYCenter < 0){ + angle += Math.PI*2; + } + + return { + angle: angle, + distance: radialDistanceFromCenter + }; + }, + aliasPixel = helpers.aliasPixel = function(pixelWidth){ + return (pixelWidth % 2 === 0) ? 0 : 0.5; + }, + splineCurve = helpers.splineCurve = function(FirstPoint,MiddlePoint,AfterPoint,t){ + //Props to Rob Spencer at scaled innovation for his post on splining between points + //http://scaledinnovation.com/analytics/splines/aboutSplines.html + var d01=Math.sqrt(Math.pow(MiddlePoint.x-FirstPoint.x,2)+Math.pow(MiddlePoint.y-FirstPoint.y,2)), + d12=Math.sqrt(Math.pow(AfterPoint.x-MiddlePoint.x,2)+Math.pow(AfterPoint.y-MiddlePoint.y,2)), + fa=t*d01/(d01+d12),// scaling factor for triangle Ta + fb=t*d12/(d01+d12); + return { + inner : { + x : MiddlePoint.x-fa*(AfterPoint.x-FirstPoint.x), + y : MiddlePoint.y-fa*(AfterPoint.y-FirstPoint.y) + }, + outer : { + x: MiddlePoint.x+fb*(AfterPoint.x-FirstPoint.x), + y : MiddlePoint.y+fb*(AfterPoint.y-FirstPoint.y) + } + }; + }, + calculateOrderOfMagnitude = helpers.calculateOrderOfMagnitude = function(val){ + return Math.floor(Math.log(val) / Math.LN10); + }, + calculateScaleRange = helpers.calculateScaleRange = function(valuesArray, drawingSize, textSize, startFromZero, integersOnly){ + + //Set a minimum step of two - a point at the top of the graph, and a point at the base + var minSteps = 2, + maxSteps = Math.floor(drawingSize/(textSize * 1.5)), + skipFitting = (minSteps >= maxSteps); + + var maxValue = max(valuesArray), + minValue = min(valuesArray); + + // We need some degree of separation here to calculate the scales if all the values are the same + // Adding/minusing 0.5 will give us a range of 1. + if (maxValue === minValue){ + maxValue += 0.5; + // So we don't end up with a graph with a negative start value if we've said always start from zero + if (minValue >= 0.5 && !startFromZero){ + minValue -= 0.5; + } + else{ + // Make up a whole number above the values + maxValue += 0.5; + } + } + + var valueRange = Math.abs(maxValue - minValue), + rangeOrderOfMagnitude = calculateOrderOfMagnitude(valueRange), + graphMax = Math.ceil(maxValue / (1 * Math.pow(10, rangeOrderOfMagnitude))) * Math.pow(10, rangeOrderOfMagnitude), + graphMin = (startFromZero) ? 0 : Math.floor(minValue / (1 * Math.pow(10, rangeOrderOfMagnitude))) * Math.pow(10, rangeOrderOfMagnitude), + graphRange = graphMax - graphMin, + stepValue = Math.pow(10, rangeOrderOfMagnitude), + numberOfSteps = Math.round(graphRange / stepValue); + + //If we have more space on the graph we'll use it to give more definition to the data + while((numberOfSteps > maxSteps || (numberOfSteps * 2) < maxSteps) && !skipFitting) { + if(numberOfSteps > maxSteps){ + stepValue *=2; + numberOfSteps = Math.round(graphRange/stepValue); + // Don't ever deal with a decimal number of steps - cancel fitting and just use the minimum number of steps. + if (numberOfSteps % 1 !== 0){ + skipFitting = true; + } + } + //We can fit in double the amount of scale points on the scale + else{ + //If user has declared ints only, and the step value isn't a decimal + if (integersOnly && rangeOrderOfMagnitude >= 0){ + //If the user has said integers only, we need to check that making the scale more granular wouldn't make it a float + if(stepValue/2 % 1 === 0){ + stepValue /=2; + numberOfSteps = Math.round(graphRange/stepValue); + } + //If it would make it a float break out of the loop + else{ + break; + } + } + //If the scale doesn't have to be an int, make the scale more granular anyway. + else{ + stepValue /=2; + numberOfSteps = Math.round(graphRange/stepValue); + } + + } + } + + if (skipFitting){ + numberOfSteps = minSteps; + stepValue = graphRange / numberOfSteps; + } + + return { + steps : numberOfSteps, + stepValue : stepValue, + min : graphMin, + max : graphMin + (numberOfSteps * stepValue) + }; + + }, + /* jshint ignore:start */ + // Blows up jshint errors based on the new Function constructor + //Templating methods + //Javascript micro templating by John Resig - source at http://ejohn.org/blog/javascript-micro-templating/ + template = helpers.template = function(templateString, valuesObject){ + + // If templateString is function rather than string-template - call the function for valuesObject + + if(templateString instanceof Function){ + return templateString(valuesObject); + } + + var cache = {}; + function tmpl(str, data){ + // Figure out if we're getting a template, or if we need to + // load the template - and be sure to cache the result. + var fn = !/\W/.test(str) ? + cache[str] = cache[str] : + + // Generate a reusable function that will serve as a template + // generator (and which will be cached). + new Function("obj", + "var p=[],print=function(){p.push.apply(p,arguments);};" + + + // Introduce the data as local variables using with(){} + "with(obj){p.push('" + + + // Convert the template into pure JavaScript + str + .replace(/[\r\t\n]/g, " ") + .split("<%").join("\t") + .replace(/((^|%>)[^\t]*)'/g, "$1\r") + .replace(/\t=(.*?)%>/g, "',$1,'") + .split("\t").join("');") + .split("%>").join("p.push('") + .split("\r").join("\\'") + + "');}return p.join('');" + ); + + // Provide some basic currying to the user + return data ? fn( data ) : fn; + } + return tmpl(templateString,valuesObject); + }, + /* jshint ignore:end */ + generateLabels = helpers.generateLabels = function(templateString,numberOfSteps,graphMin,stepValue){ + var labelsArray = new Array(numberOfSteps); + if (templateString){ + each(labelsArray,function(val,index){ + labelsArray[index] = template(templateString,{value: (graphMin + (stepValue*(index+1)))}); + }); + } + return labelsArray; + }, + //--Animation methods + //Easing functions adapted from Robert Penner's easing equations + //http://www.robertpenner.com/easing/ + easingEffects = helpers.easingEffects = { + linear: function (t) { + return t; + }, + easeInQuad: function (t) { + return t * t; + }, + easeOutQuad: function (t) { + return -1 * t * (t - 2); + }, + easeInOutQuad: function (t) { + if ((t /= 1 / 2) < 1){ + return 1 / 2 * t * t; + } + return -1 / 2 * ((--t) * (t - 2) - 1); + }, + easeInCubic: function (t) { + return t * t * t; + }, + easeOutCubic: function (t) { + return 1 * ((t = t / 1 - 1) * t * t + 1); + }, + easeInOutCubic: function (t) { + if ((t /= 1 / 2) < 1){ + return 1 / 2 * t * t * t; + } + return 1 / 2 * ((t -= 2) * t * t + 2); + }, + easeInQuart: function (t) { + return t * t * t * t; + }, + easeOutQuart: function (t) { + return -1 * ((t = t / 1 - 1) * t * t * t - 1); + }, + easeInOutQuart: function (t) { + if ((t /= 1 / 2) < 1){ + return 1 / 2 * t * t * t * t; + } + return -1 / 2 * ((t -= 2) * t * t * t - 2); + }, + easeInQuint: function (t) { + return 1 * (t /= 1) * t * t * t * t; + }, + easeOutQuint: function (t) { + return 1 * ((t = t / 1 - 1) * t * t * t * t + 1); + }, + easeInOutQuint: function (t) { + if ((t /= 1 / 2) < 1){ + return 1 / 2 * t * t * t * t * t; + } + return 1 / 2 * ((t -= 2) * t * t * t * t + 2); + }, + easeInSine: function (t) { + return -1 * Math.cos(t / 1 * (Math.PI / 2)) + 1; + }, + easeOutSine: function (t) { + return 1 * Math.sin(t / 1 * (Math.PI / 2)); + }, + easeInOutSine: function (t) { + return -1 / 2 * (Math.cos(Math.PI * t / 1) - 1); + }, + easeInExpo: function (t) { + return (t === 0) ? 1 : 1 * Math.pow(2, 10 * (t / 1 - 1)); + }, + easeOutExpo: function (t) { + return (t === 1) ? 1 : 1 * (-Math.pow(2, -10 * t / 1) + 1); + }, + easeInOutExpo: function (t) { + if (t === 0){ + return 0; + } + if (t === 1){ + return 1; + } + if ((t /= 1 / 2) < 1){ + return 1 / 2 * Math.pow(2, 10 * (t - 1)); + } + return 1 / 2 * (-Math.pow(2, -10 * --t) + 2); + }, + easeInCirc: function (t) { + if (t >= 1){ + return t; + } + return -1 * (Math.sqrt(1 - (t /= 1) * t) - 1); + }, + easeOutCirc: function (t) { + return 1 * Math.sqrt(1 - (t = t / 1 - 1) * t); + }, + easeInOutCirc: function (t) { + if ((t /= 1 / 2) < 1){ + return -1 / 2 * (Math.sqrt(1 - t * t) - 1); + } + return 1 / 2 * (Math.sqrt(1 - (t -= 2) * t) + 1); + }, + easeInElastic: function (t) { + var s = 1.70158; + var p = 0; + var a = 1; + if (t === 0){ + return 0; + } + if ((t /= 1) == 1){ + return 1; + } + if (!p){ + p = 1 * 0.3; + } + if (a < Math.abs(1)) { + a = 1; + s = p / 4; + } else{ + s = p / (2 * Math.PI) * Math.asin(1 / a); + } + return -(a * Math.pow(2, 10 * (t -= 1)) * Math.sin((t * 1 - s) * (2 * Math.PI) / p)); + }, + easeOutElastic: function (t) { + var s = 1.70158; + var p = 0; + var a = 1; + if (t === 0){ + return 0; + } + if ((t /= 1) == 1){ + return 1; + } + if (!p){ + p = 1 * 0.3; + } + if (a < Math.abs(1)) { + a = 1; + s = p / 4; + } else{ + s = p / (2 * Math.PI) * Math.asin(1 / a); + } + return a * Math.pow(2, -10 * t) * Math.sin((t * 1 - s) * (2 * Math.PI) / p) + 1; + }, + easeInOutElastic: function (t) { + var s = 1.70158; + var p = 0; + var a = 1; + if (t === 0){ + return 0; + } + if ((t /= 1 / 2) == 2){ + return 1; + } + if (!p){ + p = 1 * (0.3 * 1.5); + } + if (a < Math.abs(1)) { + a = 1; + s = p / 4; + } else { + s = p / (2 * Math.PI) * Math.asin(1 / a); + } + if (t < 1){ + return -0.5 * (a * Math.pow(2, 10 * (t -= 1)) * Math.sin((t * 1 - s) * (2 * Math.PI) / p));} + return a * Math.pow(2, -10 * (t -= 1)) * Math.sin((t * 1 - s) * (2 * Math.PI) / p) * 0.5 + 1; + }, + easeInBack: function (t) { + var s = 1.70158; + return 1 * (t /= 1) * t * ((s + 1) * t - s); + }, + easeOutBack: function (t) { + var s = 1.70158; + return 1 * ((t = t / 1 - 1) * t * ((s + 1) * t + s) + 1); + }, + easeInOutBack: function (t) { + var s = 1.70158; + if ((t /= 1 / 2) < 1){ + return 1 / 2 * (t * t * (((s *= (1.525)) + 1) * t - s)); + } + return 1 / 2 * ((t -= 2) * t * (((s *= (1.525)) + 1) * t + s) + 2); + }, + easeInBounce: function (t) { + return 1 - easingEffects.easeOutBounce(1 - t); + }, + easeOutBounce: function (t) { + if ((t /= 1) < (1 / 2.75)) { + return 1 * (7.5625 * t * t); + } else if (t < (2 / 2.75)) { + return 1 * (7.5625 * (t -= (1.5 / 2.75)) * t + 0.75); + } else if (t < (2.5 / 2.75)) { + return 1 * (7.5625 * (t -= (2.25 / 2.75)) * t + 0.9375); + } else { + return 1 * (7.5625 * (t -= (2.625 / 2.75)) * t + 0.984375); + } + }, + easeInOutBounce: function (t) { + if (t < 1 / 2){ + return easingEffects.easeInBounce(t * 2) * 0.5; + } + return easingEffects.easeOutBounce(t * 2 - 1) * 0.5 + 1 * 0.5; + } + }, + //Request animation polyfill - http://www.paulirish.com/2011/requestanimationframe-for-smart-animating/ + requestAnimFrame = helpers.requestAnimFrame = (function(){ + return window.requestAnimationFrame || + window.webkitRequestAnimationFrame || + window.mozRequestAnimationFrame || + window.oRequestAnimationFrame || + window.msRequestAnimationFrame || + function(callback) { + return window.setTimeout(callback, 1000 / 60); + }; + })(), + cancelAnimFrame = helpers.cancelAnimFrame = (function(){ + return window.cancelAnimationFrame || + window.webkitCancelAnimationFrame || + window.mozCancelAnimationFrame || + window.oCancelAnimationFrame || + window.msCancelAnimationFrame || + function(callback) { + return window.clearTimeout(callback, 1000 / 60); + }; + })(), + animationLoop = helpers.animationLoop = function(callback,totalSteps,easingString,onProgress,onComplete,chartInstance){ + + var currentStep = 0, + easingFunction = easingEffects[easingString] || easingEffects.linear; + + var animationFrame = function(){ + currentStep++; + var stepDecimal = currentStep/totalSteps; + var easeDecimal = easingFunction(stepDecimal); + + callback.call(chartInstance,easeDecimal,stepDecimal, currentStep); + onProgress.call(chartInstance,easeDecimal,stepDecimal); + if (currentStep < totalSteps){ + chartInstance.animationFrame = requestAnimFrame(animationFrame); + } else{ + onComplete.apply(chartInstance); + } + }; + requestAnimFrame(animationFrame); + }, + //-- DOM methods + getRelativePosition = helpers.getRelativePosition = function(evt){ + var mouseX, mouseY; + var e = evt.originalEvent || evt, + canvas = evt.currentTarget || evt.srcElement, + boundingRect = canvas.getBoundingClientRect(); + + if (e.touches){ + mouseX = e.touches[0].clientX - boundingRect.left; + mouseY = e.touches[0].clientY - boundingRect.top; + + } + else{ + mouseX = e.clientX - boundingRect.left; + mouseY = e.clientY - boundingRect.top; + } + + return { + x : mouseX, + y : mouseY + }; + + }, + addEvent = helpers.addEvent = function(node,eventType,method){ + if (node.addEventListener){ + node.addEventListener(eventType,method); + } else if (node.attachEvent){ + node.attachEvent("on"+eventType, method); + } else { + node["on"+eventType] = method; + } + }, + removeEvent = helpers.removeEvent = function(node, eventType, handler){ + if (node.removeEventListener){ + node.removeEventListener(eventType, handler, false); + } else if (node.detachEvent){ + node.detachEvent("on"+eventType,handler); + } else{ + node["on" + eventType] = noop; + } + }, + bindEvents = helpers.bindEvents = function(chartInstance, arrayOfEvents, handler){ + // Create the events object if it's not already present + if (!chartInstance.events) chartInstance.events = {}; + + each(arrayOfEvents,function(eventName){ + chartInstance.events[eventName] = function(){ + handler.apply(chartInstance, arguments); + }; + addEvent(chartInstance.chart.canvas,eventName,chartInstance.events[eventName]); + }); + }, + unbindEvents = helpers.unbindEvents = function (chartInstance, arrayOfEvents) { + each(arrayOfEvents, function(handler,eventName){ + removeEvent(chartInstance.chart.canvas, eventName, handler); + }); + }, + getMaximumWidth = helpers.getMaximumWidth = function(domNode){ + var container = domNode.parentNode, + padding = parseInt(getStyle(container, 'padding-left')) + parseInt(getStyle(container, 'padding-right')); + // TODO = check cross browser stuff with this. + return container.clientWidth - padding; + }, + getMaximumHeight = helpers.getMaximumHeight = function(domNode){ + var container = domNode.parentNode, + padding = parseInt(getStyle(container, 'padding-bottom')) + parseInt(getStyle(container, 'padding-top')); + // TODO = check cross browser stuff with this. + return container.clientHeight - padding; + }, + getStyle = helpers.getStyle = function (el, property) { + return el.currentStyle ? + el.currentStyle[property] : + document.defaultView.getComputedStyle(el, null).getPropertyValue(property); + }, + getMaximumSize = helpers.getMaximumSize = helpers.getMaximumWidth, // legacy support + retinaScale = helpers.retinaScale = function(chart){ + var ctx = chart.ctx, + width = chart.canvas.width, + height = chart.canvas.height; + + if (window.devicePixelRatio) { + ctx.canvas.style.width = width + "px"; + ctx.canvas.style.height = height + "px"; + ctx.canvas.height = height * window.devicePixelRatio; + ctx.canvas.width = width * window.devicePixelRatio; + ctx.scale(window.devicePixelRatio, window.devicePixelRatio); + } + }, + //-- Canvas methods + clear = helpers.clear = function(chart){ + chart.ctx.clearRect(0,0,chart.width,chart.height); + }, + fontString = helpers.fontString = function(pixelSize,fontStyle,fontFamily){ + return fontStyle + " " + pixelSize+"px " + fontFamily; + }, + longestText = helpers.longestText = function(ctx,font,arrayOfStrings){ + ctx.font = font; + var longest = 0; + each(arrayOfStrings,function(string){ + var textWidth = ctx.measureText(string).width; + longest = (textWidth > longest) ? textWidth : longest; + }); + return longest; + }, + drawRoundedRectangle = helpers.drawRoundedRectangle = function(ctx,x,y,width,height,radius){ + ctx.beginPath(); + ctx.moveTo(x + radius, y); + ctx.lineTo(x + width - radius, y); + ctx.quadraticCurveTo(x + width, y, x + width, y + radius); + ctx.lineTo(x + width, y + height - radius); + ctx.quadraticCurveTo(x + width, y + height, x + width - radius, y + height); + ctx.lineTo(x + radius, y + height); + ctx.quadraticCurveTo(x, y + height, x, y + height - radius); + ctx.lineTo(x, y + radius); + ctx.quadraticCurveTo(x, y, x + radius, y); + ctx.closePath(); + }; + + + //Store a reference to each instance - allowing us to globally resize chart instances on window resize. + //Destroy method on the chart will remove the instance of the chart from this reference. + Chart.instances = {}; + + Chart.Type = function(data,options,chart){ + this.options = options; + this.chart = chart; + this.id = uid(); + //Add the chart instance to the global namespace + Chart.instances[this.id] = this; + + // Initialize is always called when a chart type is created + // By default it is a no op, but it should be extended + if (options.responsive){ + this.resize(); + } + this.initialize.call(this,data); + }; + + //Core methods that'll be a part of every chart type + extend(Chart.Type.prototype,{ + initialize : function(){return this;}, + clear : function(){ + clear(this.chart); + return this; + }, + stop : function(){ + // Stops any current animation loop occuring + Chart.animationService.cancelAnimation(this); + return this; + }, + resize : function(callback){ + this.stop(); + var canvas = this.chart.canvas, + newWidth = getMaximumWidth(this.chart.canvas), + newHeight = this.options.maintainAspectRatio ? newWidth / this.chart.aspectRatio : getMaximumHeight(this.chart.canvas); + + canvas.width = this.chart.width = newWidth; + canvas.height = this.chart.height = newHeight; + + retinaScale(this.chart); + + if (typeof callback === "function"){ + callback.apply(this, Array.prototype.slice.call(arguments, 1)); + } + return this; + }, + reflow : noop, + render : function(reflow){ + if (reflow){ + this.reflow(); + } + + if (this.options.animation && !reflow){ + var animation = new Chart.Animation(); + animation.numSteps = this.options.animationSteps; + animation.easing = this.options.animationEasing; + + // render function + animation.render = function(chartInstance, animationObject) { + var easingFunction = helpers.easingEffects[animationObject.easing]; + var stepDecimal = animationObject.currentStep / animationObject.numSteps; + var easeDecimal = easingFunction(stepDecimal); + + chartInstance.draw(easeDecimal, stepDecimal, animationObject.currentStep); + }; + + // user events + animation.onAnimationProgress = this.options.onAnimationProgress; + animation.onAnimationComplete = this.options.onAnimationComplete; + + Chart.animationService.addAnimation(this, animation); + } + else{ + this.draw(); + this.options.onAnimationComplete.call(this); + } + return this; + }, + generateLegend : function(){ + return template(this.options.legendTemplate,this); + }, + destroy : function(){ + this.clear(); + unbindEvents(this, this.events); + var canvas = this.chart.canvas; + + // Reset canvas height/width attributes starts a fresh with the canvas context + canvas.width = this.chart.width; + canvas.height = this.chart.height; + + // < IE9 doesn't support removeProperty + if (canvas.style.removeProperty) { + canvas.style.removeProperty('width'); + canvas.style.removeProperty('height'); + } else { + canvas.style.removeAttribute('width'); + canvas.style.removeAttribute('height'); + } + + delete Chart.instances[this.id]; + }, + showTooltip : function(ChartElements, forceRedraw){ + // Only redraw the chart if we've actually changed what we're hovering on. + if (typeof this.activeElements === 'undefined') this.activeElements = []; + + var isChanged = (function(Elements){ + var changed = false; + + if (Elements.length !== this.activeElements.length){ + changed = true; + return changed; + } + + each(Elements, function(element, index){ + if (element !== this.activeElements[index]){ + changed = true; + } + }, this); + return changed; + }).call(this, ChartElements); + + if (!isChanged && !forceRedraw){ + return; + } + else{ + this.activeElements = ChartElements; + } + this.draw(); + if(this.options.customTooltips){ + this.options.customTooltips(false); + } + if (ChartElements.length > 0){ + // If we have multiple datasets, show a MultiTooltip for all of the data points at that index + if (this.datasets && this.datasets.length > 1) { + var dataArray, + dataIndex; + + for (var i = this.datasets.length - 1; i >= 0; i--) { + dataArray = this.datasets[i].points || this.datasets[i].bars || this.datasets[i].segments; + dataIndex = indexOf(dataArray, ChartElements[0]); + if (dataIndex !== -1){ + break; + } + } + var tooltipLabels = [], + tooltipColors = [], + medianPosition = (function(index) { + + // Get all the points at that particular index + var Elements = [], + dataCollection, + xPositions = [], + yPositions = [], + xMax, + yMax, + xMin, + yMin; + helpers.each(this.datasets, function(dataset){ + dataCollection = dataset.points || dataset.bars || dataset.segments; + if (dataCollection[dataIndex] && dataCollection[dataIndex].hasValue()){ + Elements.push(dataCollection[dataIndex]); + } + }); + + helpers.each(Elements, function(element) { + xPositions.push(element.x); + yPositions.push(element.y); + + + //Include any colour information about the element + tooltipLabels.push(helpers.template(this.options.multiTooltipTemplate, element)); + tooltipColors.push({ + fill: element._saved.fillColor || element.fillColor, + stroke: element._saved.strokeColor || element.strokeColor + }); + + }, this); + + yMin = min(yPositions); + yMax = max(yPositions); + + xMin = min(xPositions); + xMax = max(xPositions); + + return { + x: (xMin > this.chart.width/2) ? xMin : xMax, + y: (yMin + yMax)/2 + }; + }).call(this, dataIndex); + + new Chart.MultiTooltip({ + x: medianPosition.x, + y: medianPosition.y, + xPadding: this.options.tooltipXPadding, + yPadding: this.options.tooltipYPadding, + xOffset: this.options.tooltipXOffset, + fillColor: this.options.tooltipFillColor, + textColor: this.options.tooltipFontColor, + fontFamily: this.options.tooltipFontFamily, + fontStyle: this.options.tooltipFontStyle, + fontSize: this.options.tooltipFontSize, + titleTextColor: this.options.tooltipTitleFontColor, + titleFontFamily: this.options.tooltipTitleFontFamily, + titleFontStyle: this.options.tooltipTitleFontStyle, + titleFontSize: this.options.tooltipTitleFontSize, + cornerRadius: this.options.tooltipCornerRadius, + labels: tooltipLabels, + legendColors: tooltipColors, + legendColorBackground : this.options.multiTooltipKeyBackground, + title: template(this.options.tooltipTitleTemplate,ChartElements[0]), + chart: this.chart, + ctx: this.chart.ctx, + custom: this.options.customTooltips + }).draw(); + + } else { + each(ChartElements, function(Element) { + var tooltipPosition = Element.tooltipPosition(); + new Chart.Tooltip({ + x: Math.round(tooltipPosition.x), + y: Math.round(tooltipPosition.y), + xPadding: this.options.tooltipXPadding, + yPadding: this.options.tooltipYPadding, + fillColor: this.options.tooltipFillColor, + textColor: this.options.tooltipFontColor, + fontFamily: this.options.tooltipFontFamily, + fontStyle: this.options.tooltipFontStyle, + fontSize: this.options.tooltipFontSize, + caretHeight: this.options.tooltipCaretSize, + cornerRadius: this.options.tooltipCornerRadius, + text: template(this.options.tooltipTemplate, Element), + chart: this.chart, + custom: this.options.customTooltips + }).draw(); + }, this); + } + } + return this; + }, + toBase64Image : function(){ + return this.chart.canvas.toDataURL.apply(this.chart.canvas, arguments); + } + }); + + Chart.Type.extend = function(extensions){ + + var parent = this; + + var ChartType = function(){ + return parent.apply(this,arguments); + }; + + //Copy the prototype object of the this class + ChartType.prototype = clone(parent.prototype); + //Now overwrite some of the properties in the base class with the new extensions + extend(ChartType.prototype, extensions); + + ChartType.extend = Chart.Type.extend; + + if (extensions.name || parent.prototype.name){ + + var chartName = extensions.name || parent.prototype.name; + //Assign any potential default values of the new chart type + + //If none are defined, we'll use a clone of the chart type this is being extended from. + //I.e. if we extend a line chart, we'll use the defaults from the line chart if our new chart + //doesn't define some defaults of their own. + + var baseDefaults = (Chart.defaults[parent.prototype.name]) ? clone(Chart.defaults[parent.prototype.name]) : {}; + + Chart.defaults[chartName] = extend(baseDefaults,extensions.defaults); + + Chart.types[chartName] = ChartType; + + //Register this new chart type in the Chart prototype + Chart.prototype[chartName] = function(data,options){ + var config = merge(Chart.defaults.global, Chart.defaults[chartName], options || {}); + return new ChartType(data,config,this); + }; + } else{ + warn("Name not provided for this chart, so it hasn't been registered"); + } + return parent; + }; + + Chart.Element = function(configuration){ + extend(this,configuration); + this.initialize.apply(this,arguments); + this.save(); + }; + extend(Chart.Element.prototype,{ + initialize : function(){}, + restore : function(props){ + if (!props){ + extend(this,this._saved); + } else { + each(props,function(key){ + this[key] = this._saved[key]; + },this); + } + return this; + }, + save : function(){ + this._saved = clone(this); + delete this._saved._saved; + return this; + }, + update : function(newProps){ + each(newProps,function(value,key){ + this._saved[key] = this[key]; + this[key] = value; + },this); + return this; + }, + transition : function(props,ease){ + each(props,function(value,key){ + this[key] = ((value - this._saved[key]) * ease) + this._saved[key]; + },this); + return this; + }, + tooltipPosition : function(){ + return { + x : this.x, + y : this.y + }; + }, + hasValue: function(){ + return isNumber(this.value); + } + }); + + Chart.Element.extend = inherits; + + + Chart.Point = Chart.Element.extend({ + display: true, + inRange: function(chartX,chartY){ + var hitDetectionRange = this.hitDetectionRadius + this.radius; + return ((Math.pow(chartX-this.x, 2)+Math.pow(chartY-this.y, 2)) < Math.pow(hitDetectionRange,2)); + }, + draw : function(){ + if (this.display){ + var ctx = this.ctx; + ctx.beginPath(); + + ctx.arc(this.x, this.y, this.radius, 0, Math.PI*2); + ctx.closePath(); + + ctx.strokeStyle = this.strokeColor; + ctx.lineWidth = this.strokeWidth; + + ctx.fillStyle = this.fillColor; + + ctx.fill(); + ctx.stroke(); + } + + + //Quick debug for bezier curve splining + //Highlights control points and the line between them. + //Handy for dev - stripped in the min version. + + // ctx.save(); + // ctx.fillStyle = "black"; + // ctx.strokeStyle = "black" + // ctx.beginPath(); + // ctx.arc(this.controlPoints.inner.x,this.controlPoints.inner.y, 2, 0, Math.PI*2); + // ctx.fill(); + + // ctx.beginPath(); + // ctx.arc(this.controlPoints.outer.x,this.controlPoints.outer.y, 2, 0, Math.PI*2); + // ctx.fill(); + + // ctx.moveTo(this.controlPoints.inner.x,this.controlPoints.inner.y); + // ctx.lineTo(this.x, this.y); + // ctx.lineTo(this.controlPoints.outer.x,this.controlPoints.outer.y); + // ctx.stroke(); + + // ctx.restore(); + + + + } + }); + + Chart.Arc = Chart.Element.extend({ + inRange : function(chartX,chartY){ + + var pointRelativePosition = helpers.getAngleFromPoint(this, { + x: chartX, + y: chartY + }); + + // Normalize all angles to 0 - 2*PI (0 - 360°) + var pointRelativeAngle = pointRelativePosition.angle % (Math.PI * 2), + startAngle = (Math.PI * 2 + this.startAngle) % (Math.PI * 2), + endAngle = (Math.PI * 2 + this.endAngle) % (Math.PI * 2) || 360; + + // Calculate wether the pointRelativeAngle is between the start and the end angle + var betweenAngles = (endAngle < startAngle) ? + pointRelativeAngle <= endAngle || pointRelativeAngle >= startAngle: + pointRelativeAngle >= startAngle && pointRelativeAngle <= endAngle; + + //Check if within the range of the open/close angle + var withinRadius = (pointRelativePosition.distance >= this.innerRadius && pointRelativePosition.distance <= this.outerRadius); + + return (betweenAngles && withinRadius); + //Ensure within the outside of the arc centre, but inside arc outer + }, + tooltipPosition : function(){ + var centreAngle = this.startAngle + ((this.endAngle - this.startAngle) / 2), + rangeFromCentre = (this.outerRadius - this.innerRadius) / 2 + this.innerRadius; + return { + x : this.x + (Math.cos(centreAngle) * rangeFromCentre), + y : this.y + (Math.sin(centreAngle) * rangeFromCentre) + }; + }, + draw : function(animationPercent){ + + var easingDecimal = animationPercent || 1; + + var ctx = this.ctx; + + ctx.beginPath(); + + ctx.arc(this.x, this.y, this.outerRadius < 0 ? 0 : this.outerRadius, this.startAngle, this.endAngle); + + ctx.arc(this.x, this.y, this.innerRadius < 0 ? 0 : this.innerRadius, this.endAngle, this.startAngle, true); + + ctx.closePath(); + ctx.strokeStyle = this.strokeColor; + ctx.lineWidth = this.strokeWidth; + + ctx.fillStyle = this.fillColor; + + ctx.fill(); + ctx.lineJoin = 'bevel'; + + if (this.showStroke){ + ctx.stroke(); + } + } + }); + + Chart.Rectangle = Chart.Element.extend({ + draw : function(){ + var ctx = this.ctx, + halfWidth = this.width/2, + leftX = this.x - halfWidth, + rightX = this.x + halfWidth, + top = this.base - (this.base - this.y), + halfStroke = this.strokeWidth / 2; + + // Canvas doesn't allow us to stroke inside the width so we can + // adjust the sizes to fit if we're setting a stroke on the line + if (this.showStroke){ + leftX += halfStroke; + rightX -= halfStroke; + top += halfStroke; + } + + ctx.beginPath(); + + ctx.fillStyle = this.fillColor; + ctx.strokeStyle = this.strokeColor; + ctx.lineWidth = this.strokeWidth; + + // It'd be nice to keep this class totally generic to any rectangle + // and simply specify which border to miss out. + ctx.moveTo(leftX, this.base); + ctx.lineTo(leftX, top); + ctx.lineTo(rightX, top); + ctx.lineTo(rightX, this.base); + ctx.fill(); + if (this.showStroke){ + ctx.stroke(); + } + }, + height : function(){ + return this.base - this.y; + }, + inRange : function(chartX,chartY){ + return (chartX >= this.x - this.width/2 && chartX <= this.x + this.width/2) && (chartY >= this.y && chartY <= this.base); + } + }); + + Chart.Animation = Chart.Element.extend({ + currentStep: null, // the current animation step + numSteps: 60, // default number of steps + easing: "", // the easing to use for this animation + render: null, // render function used by the animation service + + onAnimationProgress: null, // user specified callback to fire on each step of the animation + onAnimationComplete: null, // user specified callback to fire when the animation finishes + }); + + Chart.Tooltip = Chart.Element.extend({ + draw : function(){ + + var ctx = this.chart.ctx; + + ctx.font = fontString(this.fontSize,this.fontStyle,this.fontFamily); + + this.xAlign = "center"; + this.yAlign = "above"; + + //Distance between the actual element.y position and the start of the tooltip caret + var caretPadding = this.caretPadding = 2; + + var tooltipWidth = ctx.measureText(this.text).width + 2*this.xPadding, + tooltipRectHeight = this.fontSize + 2*this.yPadding, + tooltipHeight = tooltipRectHeight + this.caretHeight + caretPadding; + + if (this.x + tooltipWidth/2 >this.chart.width){ + this.xAlign = "left"; + } else if (this.x - tooltipWidth/2 < 0){ + this.xAlign = "right"; + } + + if (this.y - tooltipHeight < 0){ + this.yAlign = "below"; + } + + + var tooltipX = this.x - tooltipWidth/2, + tooltipY = this.y - tooltipHeight; + + ctx.fillStyle = this.fillColor; + + // Custom Tooltips + if(this.custom){ + this.custom(this); + } + else{ + switch(this.yAlign) + { + case "above": + //Draw a caret above the x/y + ctx.beginPath(); + ctx.moveTo(this.x,this.y - caretPadding); + ctx.lineTo(this.x + this.caretHeight, this.y - (caretPadding + this.caretHeight)); + ctx.lineTo(this.x - this.caretHeight, this.y - (caretPadding + this.caretHeight)); + ctx.closePath(); + ctx.fill(); + break; + case "below": + tooltipY = this.y + caretPadding + this.caretHeight; + //Draw a caret below the x/y + ctx.beginPath(); + ctx.moveTo(this.x, this.y + caretPadding); + ctx.lineTo(this.x + this.caretHeight, this.y + caretPadding + this.caretHeight); + ctx.lineTo(this.x - this.caretHeight, this.y + caretPadding + this.caretHeight); + ctx.closePath(); + ctx.fill(); + break; + } + + switch(this.xAlign) + { + case "left": + tooltipX = this.x - tooltipWidth + (this.cornerRadius + this.caretHeight); + break; + case "right": + tooltipX = this.x - (this.cornerRadius + this.caretHeight); + break; + } + + drawRoundedRectangle(ctx,tooltipX,tooltipY,tooltipWidth,tooltipRectHeight,this.cornerRadius); + + ctx.fill(); + + ctx.fillStyle = this.textColor; + ctx.textAlign = "center"; + ctx.textBaseline = "middle"; + ctx.fillText(this.text, tooltipX + tooltipWidth/2, tooltipY + tooltipRectHeight/2); + } + } + }); + + Chart.MultiTooltip = Chart.Element.extend({ + initialize : function(){ + this.font = fontString(this.fontSize,this.fontStyle,this.fontFamily); + + this.titleFont = fontString(this.titleFontSize,this.titleFontStyle,this.titleFontFamily); + + this.titleHeight = this.title ? this.titleFontSize * 1.5 : 0; + this.height = (this.labels.length * this.fontSize) + ((this.labels.length-1) * (this.fontSize/2)) + (this.yPadding*2) + this.titleHeight; + + this.ctx.font = this.titleFont; + + var titleWidth = this.ctx.measureText(this.title).width, + //Label has a legend square as well so account for this. + labelWidth = longestText(this.ctx,this.font,this.labels) + this.fontSize + 3, + longestTextWidth = max([labelWidth,titleWidth]); + + this.width = longestTextWidth + (this.xPadding*2); + + + var halfHeight = this.height/2; + + //Check to ensure the height will fit on the canvas + if (this.y - halfHeight < 0 ){ + this.y = halfHeight; + } else if (this.y + halfHeight > this.chart.height){ + this.y = this.chart.height - halfHeight; + } + + //Decide whether to align left or right based on position on canvas + if (this.x > this.chart.width/2){ + this.x -= this.xOffset + this.width; + } else { + this.x += this.xOffset; + } + + + }, + getLineHeight : function(index){ + var baseLineHeight = this.y - (this.height/2) + this.yPadding, + afterTitleIndex = index-1; + + //If the index is zero, we're getting the title + if (index === 0){ + return baseLineHeight + this.titleHeight / 3; + } else{ + return baseLineHeight + ((this.fontSize * 1.5 * afterTitleIndex) + this.fontSize / 2) + this.titleHeight; + } + + }, + draw : function(){ + // Custom Tooltips + if(this.custom){ + this.custom(this); + } + else{ + drawRoundedRectangle(this.ctx,this.x,this.y - this.height/2,this.width,this.height,this.cornerRadius); + var ctx = this.ctx; + ctx.fillStyle = this.fillColor; + ctx.fill(); + ctx.closePath(); + + ctx.textAlign = "left"; + ctx.textBaseline = "middle"; + ctx.fillStyle = this.titleTextColor; + ctx.font = this.titleFont; + + ctx.fillText(this.title,this.x + this.xPadding, this.getLineHeight(0)); + + ctx.font = this.font; + helpers.each(this.labels,function(label,index){ + ctx.fillStyle = this.textColor; + ctx.fillText(label,this.x + this.xPadding + this.fontSize + 3, this.getLineHeight(index + 1)); + + //A bit gnarly, but clearing this rectangle breaks when using explorercanvas (clears whole canvas) + //ctx.clearRect(this.x + this.xPadding, this.getLineHeight(index + 1) - this.fontSize/2, this.fontSize, this.fontSize); + //Instead we'll make a white filled block to put the legendColour palette over. + + ctx.fillStyle = this.legendColorBackground; + ctx.fillRect(this.x + this.xPadding, this.getLineHeight(index + 1) - this.fontSize/2, this.fontSize, this.fontSize); + + ctx.fillStyle = this.legendColors[index].fill; + ctx.fillRect(this.x + this.xPadding, this.getLineHeight(index + 1) - this.fontSize/2, this.fontSize, this.fontSize); + + + },this); + } + } + }); + + Chart.Scale = Chart.Element.extend({ + initialize : function(){ + this.fit(); + }, + buildYLabels : function(){ + this.yLabels = []; + + var stepDecimalPlaces = getDecimalPlaces(this.stepValue); + + for (var i=0; i<=this.steps; i++){ + this.yLabels.push(template(this.templateString,{value:(this.min + (i * this.stepValue)).toFixed(stepDecimalPlaces)})); + } + this.yLabelWidth = (this.display && this.showLabels) ? longestText(this.ctx,this.font,this.yLabels) + 10 : 0; + }, + addXLabel : function(label){ + this.xLabels.push(label); + this.valuesCount++; + this.fit(); + }, + removeXLabel : function(){ + this.xLabels.shift(); + this.valuesCount--; + this.fit(); + }, + // Fitting loop to rotate x Labels and figure out what fits there, and also calculate how many Y steps to use + fit: function(){ + // First we need the width of the yLabels, assuming the xLabels aren't rotated + + // To do that we need the base line at the top and base of the chart, assuming there is no x label rotation + this.startPoint = (this.display) ? this.fontSize : 0; + this.endPoint = (this.display) ? this.height - (this.fontSize * 1.5) - 5 : this.height; // -5 to pad labels + + // Apply padding settings to the start and end point. + this.startPoint += this.padding; + this.endPoint -= this.padding; + + // Cache the starting endpoint, excluding the space for x labels + var cachedEndPoint = this.endPoint; + + // Cache the starting height, so can determine if we need to recalculate the scale yAxis + var cachedHeight = this.endPoint - this.startPoint, + cachedYLabelWidth; + + // Build the current yLabels so we have an idea of what size they'll be to start + /* + * This sets what is returned from calculateScaleRange as static properties of this class: + * + this.steps; + this.stepValue; + this.min; + this.max; + * + */ + this.calculateYRange(cachedHeight); + + // With these properties set we can now build the array of yLabels + // and also the width of the largest yLabel + this.buildYLabels(); + + this.calculateXLabelRotation(); + + while((cachedHeight > this.endPoint - this.startPoint)){ + cachedHeight = this.endPoint - this.startPoint; + cachedYLabelWidth = this.yLabelWidth; + + this.calculateYRange(cachedHeight); + this.buildYLabels(); + + // Only go through the xLabel loop again if the yLabel width has changed + if (cachedYLabelWidth < this.yLabelWidth){ + this.endPoint = cachedEndPoint; + this.calculateXLabelRotation(); + } + } + + }, + calculateXLabelRotation : function(){ + //Get the width of each grid by calculating the difference + //between x offsets between 0 and 1. + + this.ctx.font = this.font; + + var firstWidth = this.ctx.measureText(this.xLabels[0]).width, + lastWidth = this.ctx.measureText(this.xLabels[this.xLabels.length - 1]).width, + firstRotated, + lastRotated; + + + this.xScalePaddingRight = lastWidth/2 + 3; + this.xScalePaddingLeft = (firstWidth/2 > this.yLabelWidth) ? firstWidth/2 : this.yLabelWidth; + + this.xLabelRotation = 0; + if (this.display){ + var originalLabelWidth = longestText(this.ctx,this.font,this.xLabels), + cosRotation, + firstRotatedWidth; + this.xLabelWidth = originalLabelWidth; + //Allow 3 pixels x2 padding either side for label readability + var xGridWidth = Math.floor(this.calculateX(1) - this.calculateX(0)) - 6; + + //Max label rotate should be 90 - also act as a loop counter + while ((this.xLabelWidth > xGridWidth && this.xLabelRotation === 0) || (this.xLabelWidth > xGridWidth && this.xLabelRotation <= 90 && this.xLabelRotation > 0)){ + cosRotation = Math.cos(toRadians(this.xLabelRotation)); + + firstRotated = cosRotation * firstWidth; + lastRotated = cosRotation * lastWidth; + + // We're right aligning the text now. + if (firstRotated + this.fontSize / 2 > this.yLabelWidth){ + this.xScalePaddingLeft = firstRotated + this.fontSize / 2; + } + this.xScalePaddingRight = this.fontSize/2; + + + this.xLabelRotation++; + this.xLabelWidth = cosRotation * originalLabelWidth; + + } + if (this.xLabelRotation > 0){ + this.endPoint -= Math.sin(toRadians(this.xLabelRotation))*originalLabelWidth + 3; + } + } + else{ + this.xLabelWidth = 0; + this.xScalePaddingRight = this.padding; + this.xScalePaddingLeft = this.padding; + } + + }, + // Needs to be overidden in each Chart type + // Otherwise we need to pass all the data into the scale class + calculateYRange: noop, + drawingArea: function(){ + return this.startPoint - this.endPoint; + }, + calculateY : function(value){ + var scalingFactor = this.drawingArea() / (this.min - this.max); + return this.endPoint - (scalingFactor * (value - this.min)); + }, + calculateX : function(index){ + var isRotated = (this.xLabelRotation > 0), + // innerWidth = (this.offsetGridLines) ? this.width - offsetLeft - this.padding : this.width - (offsetLeft + halfLabelWidth * 2) - this.padding, + innerWidth = this.width - (this.xScalePaddingLeft + this.xScalePaddingRight), + valueWidth = innerWidth/Math.max((this.valuesCount - ((this.offsetGridLines) ? 0 : 1)), 1), + valueOffset = (valueWidth * index) + this.xScalePaddingLeft; + + if (this.offsetGridLines){ + valueOffset += (valueWidth/2); + } + + return Math.round(valueOffset); + }, + update : function(newProps){ + helpers.extend(this, newProps); + this.fit(); + }, + draw : function(){ + var ctx = this.ctx, + yLabelGap = (this.endPoint - this.startPoint) / this.steps, + xStart = Math.round(this.xScalePaddingLeft); + if (this.display){ + ctx.fillStyle = this.textColor; + ctx.font = this.font; + each(this.yLabels,function(labelString,index){ + var yLabelCenter = this.endPoint - (yLabelGap * index), + linePositionY = Math.round(yLabelCenter), + drawHorizontalLine = this.showHorizontalLines; + + ctx.textAlign = "right"; + ctx.textBaseline = "middle"; + if (this.showLabels){ + ctx.fillText(labelString,xStart - 10,yLabelCenter); + } + + // This is X axis, so draw it + if (index === 0 && !drawHorizontalLine){ + drawHorizontalLine = true; + } + + if (drawHorizontalLine){ + ctx.beginPath(); + } + + if (index > 0){ + // This is a grid line in the centre, so drop that + ctx.lineWidth = this.gridLineWidth; + ctx.strokeStyle = this.gridLineColor; + } else { + // This is the first line on the scale + ctx.lineWidth = this.lineWidth; + ctx.strokeStyle = this.lineColor; + } + + linePositionY += helpers.aliasPixel(ctx.lineWidth); + + if(drawHorizontalLine){ + ctx.moveTo(xStart, linePositionY); + ctx.lineTo(this.width, linePositionY); + ctx.stroke(); + ctx.closePath(); + } + + ctx.lineWidth = this.lineWidth; + ctx.strokeStyle = this.lineColor; + ctx.beginPath(); + ctx.moveTo(xStart - 5, linePositionY); + ctx.lineTo(xStart, linePositionY); + ctx.stroke(); + ctx.closePath(); + + },this); + + each(this.xLabels,function(label,index){ + var xPos = this.calculateX(index) + aliasPixel(this.lineWidth), + // Check to see if line/bar here and decide where to place the line + linePos = this.calculateX(index - (this.offsetGridLines ? 0.5 : 0)) + aliasPixel(this.lineWidth), + isRotated = (this.xLabelRotation > 0), + drawVerticalLine = this.showVerticalLines; + + // This is Y axis, so draw it + if (index === 0 && !drawVerticalLine){ + drawVerticalLine = true; + } + + if (drawVerticalLine){ + ctx.beginPath(); + } + + if (index > 0){ + // This is a grid line in the centre, so drop that + ctx.lineWidth = this.gridLineWidth; + ctx.strokeStyle = this.gridLineColor; + } else { + // This is the first line on the scale + ctx.lineWidth = this.lineWidth; + ctx.strokeStyle = this.lineColor; + } + + if (drawVerticalLine){ + ctx.moveTo(linePos,this.endPoint); + ctx.lineTo(linePos,this.startPoint - 3); + ctx.stroke(); + ctx.closePath(); + } + + + ctx.lineWidth = this.lineWidth; + ctx.strokeStyle = this.lineColor; + + + // Small lines at the bottom of the base grid line + ctx.beginPath(); + ctx.moveTo(linePos,this.endPoint); + ctx.lineTo(linePos,this.endPoint + 5); + ctx.stroke(); + ctx.closePath(); + + ctx.save(); + ctx.translate(xPos,(isRotated) ? this.endPoint + 12 : this.endPoint + 8); + ctx.rotate(toRadians(this.xLabelRotation)*-1); + ctx.font = this.font; + ctx.textAlign = (isRotated) ? "right" : "center"; + ctx.textBaseline = (isRotated) ? "middle" : "top"; + ctx.fillText(label, 0, 0); + ctx.restore(); + },this); + + } + } + + }); + + Chart.RadialScale = Chart.Element.extend({ + initialize: function(){ + this.size = min([this.height, this.width]); + this.drawingArea = (this.display) ? (this.size/2) - (this.fontSize/2 + this.backdropPaddingY) : (this.size/2); + }, + calculateCenterOffset: function(value){ + // Take into account half font size + the yPadding of the top value + var scalingFactor = this.drawingArea / (this.max - this.min); + + return (value - this.min) * scalingFactor; + }, + update : function(){ + if (!this.lineArc){ + this.setScaleSize(); + } else { + this.drawingArea = (this.display) ? (this.size/2) - (this.fontSize/2 + this.backdropPaddingY) : (this.size/2); + } + this.buildYLabels(); + }, + buildYLabels: function(){ + this.yLabels = []; + + var stepDecimalPlaces = getDecimalPlaces(this.stepValue); + + for (var i=0; i<=this.steps; i++){ + this.yLabels.push(template(this.templateString,{value:(this.min + (i * this.stepValue)).toFixed(stepDecimalPlaces)})); + } + }, + getCircumference : function(){ + return ((Math.PI*2) / this.valuesCount); + }, + setScaleSize: function(){ + /* + * Right, this is really confusing and there is a lot of maths going on here + * The gist of the problem is here: https://gist.github.com/nnnick/696cc9c55f4b0beb8fe9 + * + * Reaction: https://dl.dropboxusercontent.com/u/34601363/toomuchscience.gif + * + * Solution: + * + * We assume the radius of the polygon is half the size of the canvas at first + * at each index we check if the text overlaps. + * + * Where it does, we store that angle and that index. + * + * After finding the largest index and angle we calculate how much we need to remove + * from the shape radius to move the point inwards by that x. + * + * We average the left and right distances to get the maximum shape radius that can fit in the box + * along with labels. + * + * Once we have that, we can find the centre point for the chart, by taking the x text protrusion + * on each side, removing that from the size, halving it and adding the left x protrusion width. + * + * This will mean we have a shape fitted to the canvas, as large as it can be with the labels + * and position it in the most space efficient manner + * + * https://dl.dropboxusercontent.com/u/34601363/yeahscience.gif + */ + + + // Get maximum radius of the polygon. Either half the height (minus the text width) or half the width. + // Use this to calculate the offset + change. - Make sure L/R protrusion is at least 0 to stop issues with centre points + var largestPossibleRadius = min([(this.height/2 - this.pointLabelFontSize - 5), this.width/2]), + pointPosition, + i, + textWidth, + halfTextWidth, + furthestRight = this.width, + furthestRightIndex, + furthestRightAngle, + furthestLeft = 0, + furthestLeftIndex, + furthestLeftAngle, + xProtrusionLeft, + xProtrusionRight, + radiusReductionRight, + radiusReductionLeft, + maxWidthRadius; + this.ctx.font = fontString(this.pointLabelFontSize,this.pointLabelFontStyle,this.pointLabelFontFamily); + for (i=0;i furthestRight) { + furthestRight = pointPosition.x + halfTextWidth; + furthestRightIndex = i; + } + if (pointPosition.x - halfTextWidth < furthestLeft) { + furthestLeft = pointPosition.x - halfTextWidth; + furthestLeftIndex = i; + } + } + else if (i < this.valuesCount/2) { + // Less than half the values means we'll left align the text + if (pointPosition.x + textWidth > furthestRight) { + furthestRight = pointPosition.x + textWidth; + furthestRightIndex = i; + } + } + else if (i > this.valuesCount/2){ + // More than half the values means we'll right align the text + if (pointPosition.x - textWidth < furthestLeft) { + furthestLeft = pointPosition.x - textWidth; + furthestLeftIndex = i; + } + } + } + + xProtrusionLeft = furthestLeft; + + xProtrusionRight = Math.ceil(furthestRight - this.width); + + furthestRightAngle = this.getIndexAngle(furthestRightIndex); + + furthestLeftAngle = this.getIndexAngle(furthestLeftIndex); + + radiusReductionRight = xProtrusionRight / Math.sin(furthestRightAngle + Math.PI/2); + + radiusReductionLeft = xProtrusionLeft / Math.sin(furthestLeftAngle + Math.PI/2); + + // Ensure we actually need to reduce the size of the chart + radiusReductionRight = (isNumber(radiusReductionRight)) ? radiusReductionRight : 0; + radiusReductionLeft = (isNumber(radiusReductionLeft)) ? radiusReductionLeft : 0; + + this.drawingArea = largestPossibleRadius - (radiusReductionLeft + radiusReductionRight)/2; + + //this.drawingArea = min([maxWidthRadius, (this.height - (2 * (this.pointLabelFontSize + 5)))/2]) + this.setCenterPoint(radiusReductionLeft, radiusReductionRight); + + }, + setCenterPoint: function(leftMovement, rightMovement){ + + var maxRight = this.width - rightMovement - this.drawingArea, + maxLeft = leftMovement + this.drawingArea; + + this.xCenter = (maxLeft + maxRight)/2; + // Always vertically in the centre as the text height doesn't change + this.yCenter = (this.height/2); + }, + + getIndexAngle : function(index){ + var angleMultiplier = (Math.PI * 2) / this.valuesCount; + // Start from the top instead of right, so remove a quarter of the circle + + return index * angleMultiplier - (Math.PI/2); + }, + getPointPosition : function(index, distanceFromCenter){ + var thisAngle = this.getIndexAngle(index); + return { + x : (Math.cos(thisAngle) * distanceFromCenter) + this.xCenter, + y : (Math.sin(thisAngle) * distanceFromCenter) + this.yCenter + }; + }, + draw: function(){ + if (this.display){ + var ctx = this.ctx; + each(this.yLabels, function(label, index){ + // Don't draw a centre value + if (index > 0){ + var yCenterOffset = index * (this.drawingArea/this.steps), + yHeight = this.yCenter - yCenterOffset, + pointPosition; + + // Draw circular lines around the scale + if (this.lineWidth > 0){ + ctx.strokeStyle = this.lineColor; + ctx.lineWidth = this.lineWidth; + + if(this.lineArc){ + ctx.beginPath(); + ctx.arc(this.xCenter, this.yCenter, yCenterOffset, 0, Math.PI*2); + ctx.closePath(); + ctx.stroke(); + } else{ + ctx.beginPath(); + for (var i=0;i= 0; i--) { + var centerOffset = null, outerPosition = null; + + if (this.angleLineWidth > 0){ + centerOffset = this.calculateCenterOffset(this.max); + outerPosition = this.getPointPosition(i, centerOffset); + ctx.beginPath(); + ctx.moveTo(this.xCenter, this.yCenter); + ctx.lineTo(outerPosition.x, outerPosition.y); + ctx.stroke(); + ctx.closePath(); + } + + if (this.backgroundColors && this.backgroundColors.length == this.valuesCount) { + if (centerOffset == null) + centerOffset = this.calculateCenterOffset(this.max); + + if (outerPosition == null) + outerPosition = this.getPointPosition(i, centerOffset); + + var previousOuterPosition = this.getPointPosition(i === 0 ? this.valuesCount - 1 : i - 1, centerOffset); + var nextOuterPosition = this.getPointPosition(i === this.valuesCount - 1 ? 0 : i + 1, centerOffset); + + var previousOuterHalfway = { x: (previousOuterPosition.x + outerPosition.x) / 2, y: (previousOuterPosition.y + outerPosition.y) / 2 }; + var nextOuterHalfway = { x: (outerPosition.x + nextOuterPosition.x) / 2, y: (outerPosition.y + nextOuterPosition.y) / 2 }; + + ctx.beginPath(); + ctx.moveTo(this.xCenter, this.yCenter); + ctx.lineTo(previousOuterHalfway.x, previousOuterHalfway.y); + ctx.lineTo(outerPosition.x, outerPosition.y); + ctx.lineTo(nextOuterHalfway.x, nextOuterHalfway.y); + ctx.fillStyle = this.backgroundColors[i]; + ctx.fill(); + ctx.closePath(); + } + // Extra 3px out for some label spacing + var pointLabelPosition = this.getPointPosition(i, this.calculateCenterOffset(this.max) + 5); + ctx.font = fontString(this.pointLabelFontSize,this.pointLabelFontStyle,this.pointLabelFontFamily); + ctx.fillStyle = this.pointLabelFontColor; + + var labelsCount = this.labels.length, + halfLabelsCount = this.labels.length/2, + quarterLabelsCount = halfLabelsCount/2, + upperHalf = (i < quarterLabelsCount || i > labelsCount - quarterLabelsCount), + exactQuarter = (i === quarterLabelsCount || i === labelsCount - quarterLabelsCount); + if (i === 0){ + ctx.textAlign = 'center'; + } else if(i === halfLabelsCount){ + ctx.textAlign = 'center'; + } else if (i < halfLabelsCount){ + ctx.textAlign = 'left'; + } else { + ctx.textAlign = 'right'; + } + + // Set the correct text baseline based on outer positioning + if (exactQuarter){ + ctx.textBaseline = 'middle'; + } else if (upperHalf){ + ctx.textBaseline = 'bottom'; + } else { + ctx.textBaseline = 'top'; + } + + ctx.fillText(this.labels[i], pointLabelPosition.x, pointLabelPosition.y); + } + } + } + } + }); + + Chart.animationService = { + frameDuration: 17, + animations: [], + dropFrames: 0, + addAnimation: function(chartInstance, animationObject) { + for (var index = 0; index < this.animations.length; ++ index){ + if (this.animations[index].chartInstance === chartInstance){ + // replacing an in progress animation + this.animations[index].animationObject = animationObject; + return; + } + } + + this.animations.push({ + chartInstance: chartInstance, + animationObject: animationObject + }); + + // If there are no animations queued, manually kickstart a digest, for lack of a better word + if (this.animations.length == 1) { + helpers.requestAnimFrame.call(window, this.digestWrapper); + } + }, + // Cancel the animation for a given chart instance + cancelAnimation: function(chartInstance) { + var index = helpers.findNextWhere(this.animations, function(animationWrapper) { + return animationWrapper.chartInstance === chartInstance; + }); + + if (index) + { + this.animations.splice(index, 1); + } + }, + // calls startDigest with the proper context + digestWrapper: function() { + Chart.animationService.startDigest.call(Chart.animationService); + }, + startDigest: function() { + + var startTime = Date.now(); + var framesToDrop = 0; + + if(this.dropFrames > 1){ + framesToDrop = Math.floor(this.dropFrames); + this.dropFrames -= framesToDrop; + } + + for (var i = 0; i < this.animations.length; i++) { + + if (this.animations[i].animationObject.currentStep === null){ + this.animations[i].animationObject.currentStep = 0; + } + + this.animations[i].animationObject.currentStep += 1 + framesToDrop; + if(this.animations[i].animationObject.currentStep > this.animations[i].animationObject.numSteps){ + this.animations[i].animationObject.currentStep = this.animations[i].animationObject.numSteps; + } + + this.animations[i].animationObject.render(this.animations[i].chartInstance, this.animations[i].animationObject); + + // Check if executed the last frame. + if (this.animations[i].animationObject.currentStep == this.animations[i].animationObject.numSteps){ + // Call onAnimationComplete + this.animations[i].animationObject.onAnimationComplete.call(this.animations[i].chartInstance); + // Remove the animation. + this.animations.splice(i, 1); + // Keep the index in place to offset the splice + i--; + } + } + + var endTime = Date.now(); + var delay = endTime - startTime - this.frameDuration; + var frameDelay = delay / this.frameDuration; + + if(frameDelay > 1){ + this.dropFrames += frameDelay; + } + + // Do we have more stuff to animate? + if (this.animations.length > 0){ + helpers.requestAnimFrame.call(window, this.digestWrapper); + } + } + }; + + // Attach global event to resize each chart instance when the browser resizes + helpers.addEvent(window, "resize", (function(){ + // Basic debounce of resize function so it doesn't hurt performance when resizing browser. + var timeout; + return function(){ + clearTimeout(timeout); + timeout = setTimeout(function(){ + each(Chart.instances,function(instance){ + // If the responsive flag is set in the chart instance config + // Cascade the resize event down to the chart. + if (instance.options.responsive){ + instance.resize(instance.render, true); + } + }); + }, 50); + }; + })()); + + + if (amd) { + define(function(){ + return Chart; + }); + } else if (typeof module === 'object' && module.exports) { + module.exports = Chart; + } + + root.Chart = Chart; + + Chart.noConflict = function(){ + root.Chart = previous; + return Chart; + }; + +}).call(this); diff --git a/snapshots/muneeb-mbytes_pulpino__spi_master__subsystem_verification_pr28/sim/questa_sim/basic_write_read_reg_test/html_cov_report/lib/Chart/src/Chart.Doughnut.js b/snapshots/muneeb-mbytes_pulpino__spi_master__subsystem_verification_pr28/sim/questa_sim/basic_write_read_reg_test/html_cov_report/lib/Chart/src/Chart.Doughnut.js new file mode 100644 index 0000000000000000000000000000000000000000..90d886b79219ed1caa21221e0a07f341f75c7ff6 --- /dev/null +++ b/snapshots/muneeb-mbytes_pulpino__spi_master__subsystem_verification_pr28/sim/questa_sim/basic_write_read_reg_test/html_cov_report/lib/Chart/src/Chart.Doughnut.js @@ -0,0 +1,194 @@ +(function(){ + "use strict"; + + var root = this, + Chart = root.Chart, + //Cache a local reference to Chart.helpers + helpers = Chart.helpers; + + var defaultConfig = { + //Boolean - Whether we should show a stroke on each segment + segmentShowStroke : true, + + //String - The colour of each segment stroke + segmentStrokeColor : "#fff", + + //Number - The width of each segment stroke + segmentStrokeWidth : 2, + + //The percentage of the chart that we cut out of the middle. + percentageInnerCutout : 50, + + //Number - Amount of animation steps + animationSteps : 100, + + //String - Animation easing effect + animationEasing : "easeOutBounce", + + //Boolean - Whether we animate the rotation of the Doughnut + animateRotate : true, + + //Boolean - Whether we animate scaling the Doughnut from the centre + animateScale : false, + + //String - A legend template + legendTemplate : "
    -legend\"><% for (var i=0; i
  • \"><%if(segments[i].label){%><%=segments[i].label%><%}%>
    • <%}%>
" + + }; + + Chart.Type.extend({ + //Passing in a name registers this chart in the Chart namespace + name: "Doughnut", + //Providing a defaults will also register the deafults in the chart namespace + defaults : defaultConfig, + //Initialize is fired when the chart is initialized - Data is passed in as a parameter + //Config is automatically merged by the core of Chart.js, and is available at this.options + initialize: function(data){ + + //Declare segments as a static property to prevent inheriting across the Chart type prototype + this.segments = []; + this.outerRadius = (helpers.min([this.chart.width,this.chart.height]) - this.options.segmentStrokeWidth/2)/2; + + this.SegmentArc = Chart.Arc.extend({ + ctx : this.chart.ctx, + x : this.chart.width/2, + y : this.chart.height/2 + }); + + //Set up tooltip events on the chart + if (this.options.showTooltips){ + helpers.bindEvents(this, this.options.tooltipEvents, function(evt){ + var activeSegments = (evt.type !== 'mouseout') ? this.getSegmentsAtEvent(evt) : []; + + helpers.each(this.segments,function(segment){ + segment.restore(["fillColor"]); + }); + helpers.each(activeSegments,function(activeSegment){ + activeSegment.fillColor = activeSegment.highlightColor; + }); + this.showTooltip(activeSegments); + }); + } + this.calculateTotal(data); + + helpers.each(data,function(datapoint, index){ + if (!datapoint.color) { + datapoint.color = 'hsl(' + (360 * index / data.length) + ', 100%, 50%)'; + } + this.addData(datapoint, index, true); + },this); + + this.render(); + }, + getSegmentsAtEvent : function(e){ + var segmentsArray = []; + + var location = helpers.getRelativePosition(e); + + helpers.each(this.segments,function(segment){ + if (segment.inRange(location.x,location.y)) segmentsArray.push(segment); + },this); + return segmentsArray; + }, + addData : function(segment, atIndex, silent){ + var index = atIndex !== undefined ? atIndex : this.segments.length; + if ( typeof(segment.color) === "undefined" ) { + segment.color = Chart.defaults.global.segmentColorDefault[index % Chart.defaults.global.segmentColorDefault.length]; + segment.highlight = Chart.defaults.global.segmentHighlightColorDefaults[index % Chart.defaults.global.segmentHighlightColorDefaults.length]; + } + this.segments.splice(index, 0, new this.SegmentArc({ + value : segment.value, + outerRadius : (this.options.animateScale) ? 0 : this.outerRadius, + innerRadius : (this.options.animateScale) ? 0 : (this.outerRadius/100) * this.options.percentageInnerCutout, + fillColor : segment.color, + highlightColor : segment.highlight || segment.color, + showStroke : this.options.segmentShowStroke, + strokeWidth : this.options.segmentStrokeWidth, + strokeColor : this.options.segmentStrokeColor, + startAngle : Math.PI * 1.5, + circumference : (this.options.animateRotate) ? 0 : this.calculateCircumference(segment.value), + label : segment.label + })); + if (!silent){ + this.reflow(); + this.update(); + } + }, + calculateCircumference : function(value) { + if ( this.total > 0 ) { + return (Math.PI*2)*(value / this.total); + } else { + return 0; + } + }, + calculateTotal : function(data){ + this.total = 0; + helpers.each(data,function(segment){ + this.total += Math.abs(segment.value); + },this); + }, + update : function(){ + this.calculateTotal(this.segments); + + // Reset any highlight colours before updating. + helpers.each(this.activeElements, function(activeElement){ + activeElement.restore(['fillColor']); + }); + + helpers.each(this.segments,function(segment){ + segment.save(); + }); + this.render(); + }, + + removeData: function(atIndex){ + var indexToDelete = (helpers.isNumber(atIndex)) ? atIndex : this.segments.length-1; + this.segments.splice(indexToDelete, 1); + this.reflow(); + this.update(); + }, + + reflow : function(){ + helpers.extend(this.SegmentArc.prototype,{ + x : this.chart.width/2, + y : this.chart.height/2 + }); + this.outerRadius = (helpers.min([this.chart.width,this.chart.height]) - this.options.segmentStrokeWidth/2)/2; + helpers.each(this.segments, function(segment){ + segment.update({ + outerRadius : this.outerRadius, + innerRadius : (this.outerRadius/100) * this.options.percentageInnerCutout + }); + }, this); + }, + draw : function(easeDecimal){ + var animDecimal = (easeDecimal) ? easeDecimal : 1; + this.clear(); + helpers.each(this.segments,function(segment,index){ + segment.transition({ + circumference : this.calculateCircumference(segment.value), + outerRadius : this.outerRadius, + innerRadius : (this.outerRadius/100) * this.options.percentageInnerCutout + },animDecimal); + + segment.endAngle = segment.startAngle + segment.circumference; + + segment.draw(); + if (index === 0){ + segment.startAngle = Math.PI * 1.5; + } + //Check to see if it's the last segment, if not get the next and update the start angle + if (index < this.segments.length-1){ + this.segments[index+1].startAngle = segment.endAngle; + } + },this); + + } + }); + + Chart.types.Doughnut.extend({ + name : "Pie", + defaults : helpers.merge(defaultConfig,{percentageInnerCutout : 0}) + }); + +}).call(this); diff --git a/snapshots/muneeb-mbytes_pulpino__spi_master__subsystem_verification_pr28/sim/questa_sim/basic_write_read_reg_test/html_cov_report/lib/Chart/src/Chart.Line.js b/snapshots/muneeb-mbytes_pulpino__spi_master__subsystem_verification_pr28/sim/questa_sim/basic_write_read_reg_test/html_cov_report/lib/Chart/src/Chart.Line.js new file mode 100644 index 0000000000000000000000000000000000000000..fdf1b0169b7ea324d8ff9ac167e4c5e323b2fe2b --- /dev/null +++ b/snapshots/muneeb-mbytes_pulpino__spi_master__subsystem_verification_pr28/sim/questa_sim/basic_write_read_reg_test/html_cov_report/lib/Chart/src/Chart.Line.js @@ -0,0 +1,383 @@ +(function(){ + "use strict"; + + var root = this, + Chart = root.Chart, + helpers = Chart.helpers; + + var defaultConfig = { + + ///Boolean - Whether grid lines are shown across the chart + scaleShowGridLines : true, + + //String - Colour of the grid lines + scaleGridLineColor : "rgba(0,0,0,.05)", + + //Number - Width of the grid lines + scaleGridLineWidth : 1, + + //Boolean - Whether to show horizontal lines (except X axis) + scaleShowHorizontalLines: true, + + //Boolean - Whether to show vertical lines (except Y axis) + scaleShowVerticalLines: true, + + //Boolean - Whether the line is curved between points + bezierCurve : true, + + //Number - Tension of the bezier curve between points + bezierCurveTension : 0.4, + + //Boolean - Whether to show a dot for each point + pointDot : true, + + //Number - Radius of each point dot in pixels + pointDotRadius : 4, + + //Number - Pixel width of point dot stroke + pointDotStrokeWidth : 1, + + //Number - amount extra to add to the radius to cater for hit detection outside the drawn point + pointHitDetectionRadius : 20, + + //Boolean - Whether to show a stroke for datasets + datasetStroke : true, + + //Number - Pixel width of dataset stroke + datasetStrokeWidth : 2, + + //Boolean - Whether to fill the dataset with a colour + datasetFill : true, + + //String - A legend template + legendTemplate : "
    -legend\"><% for (var i=0; i
  • \"><%if(datasets[i].label){%><%=datasets[i].label%><%}%>
    • <%}%>
", + + //Boolean - Whether to horizontally center the label and point dot inside the grid + offsetGridLines : false + + }; + + + Chart.Type.extend({ + name: "Line", + defaults : defaultConfig, + initialize: function(data){ + //Declare the extension of the default point, to cater for the options passed in to the constructor + this.PointClass = Chart.Point.extend({ + offsetGridLines : this.options.offsetGridLines, + strokeWidth : this.options.pointDotStrokeWidth, + radius : this.options.pointDotRadius, + display: this.options.pointDot, + hitDetectionRadius : this.options.pointHitDetectionRadius, + ctx : this.chart.ctx, + inRange : function(mouseX){ + return (Math.pow(mouseX-this.x, 2) < Math.pow(this.radius + this.hitDetectionRadius,2)); + } + }); + + this.datasets = []; + + //Set up tooltip events on the chart + if (this.options.showTooltips){ + helpers.bindEvents(this, this.options.tooltipEvents, function(evt){ + var activePoints = (evt.type !== 'mouseout') ? this.getPointsAtEvent(evt) : []; + this.eachPoints(function(point){ + point.restore(['fillColor', 'strokeColor']); + }); + helpers.each(activePoints, function(activePoint){ + activePoint.fillColor = activePoint.highlightFill; + activePoint.strokeColor = activePoint.highlightStroke; + }); + this.showTooltip(activePoints); + }); + } + + //Iterate through each of the datasets, and build this into a property of the chart + helpers.each(data.datasets,function(dataset){ + + var datasetObject = { + label : dataset.label || null, + fillColor : dataset.fillColor, + strokeColor : dataset.strokeColor, + pointColor : dataset.pointColor, + pointStrokeColor : dataset.pointStrokeColor, + points : [] + }; + + this.datasets.push(datasetObject); + + + helpers.each(dataset.data,function(dataPoint,index){ + //Add a new point for each piece of data, passing any required data to draw. + datasetObject.points.push(new this.PointClass({ + value : dataPoint, + label : data.labels[index], + datasetLabel: dataset.label, + strokeColor : dataset.pointStrokeColor, + fillColor : dataset.pointColor, + highlightFill : dataset.pointHighlightFill || dataset.pointColor, + highlightStroke : dataset.pointHighlightStroke || dataset.pointStrokeColor + })); + },this); + + this.buildScale(data.labels); + + + this.eachPoints(function(point, index){ + helpers.extend(point, { + x: this.scale.calculateX(index), + y: this.scale.endPoint + }); + point.save(); + }, this); + + },this); + + + this.render(); + }, + update : function(){ + this.scale.update(); + // Reset any highlight colours before updating. + helpers.each(this.activeElements, function(activeElement){ + activeElement.restore(['fillColor', 'strokeColor']); + }); + this.eachPoints(function(point){ + point.save(); + }); + this.render(); + }, + eachPoints : function(callback){ + helpers.each(this.datasets,function(dataset){ + helpers.each(dataset.points,callback,this); + },this); + }, + getPointsAtEvent : function(e){ + var pointsArray = [], + eventPosition = helpers.getRelativePosition(e); + helpers.each(this.datasets,function(dataset){ + helpers.each(dataset.points,function(point){ + if (point.inRange(eventPosition.x,eventPosition.y)) pointsArray.push(point); + }); + },this); + return pointsArray; + }, + buildScale : function(labels){ + var self = this; + + var dataTotal = function(){ + var values = []; + self.eachPoints(function(point){ + values.push(point.value); + }); + + return values; + }; + + var scaleOptions = { + templateString : this.options.scaleLabel, + height : this.chart.height, + width : this.chart.width, + ctx : this.chart.ctx, + textColor : this.options.scaleFontColor, + offsetGridLines : this.options.offsetGridLines, + fontSize : this.options.scaleFontSize, + fontStyle : this.options.scaleFontStyle, + fontFamily : this.options.scaleFontFamily, + valuesCount : labels.length, + beginAtZero : this.options.scaleBeginAtZero, + integersOnly : this.options.scaleIntegersOnly, + calculateYRange : function(currentHeight){ + var updatedRanges = helpers.calculateScaleRange( + dataTotal(), + currentHeight, + this.fontSize, + this.beginAtZero, + this.integersOnly + ); + helpers.extend(this, updatedRanges); + }, + xLabels : labels, + font : helpers.fontString(this.options.scaleFontSize, this.options.scaleFontStyle, this.options.scaleFontFamily), + lineWidth : this.options.scaleLineWidth, + lineColor : this.options.scaleLineColor, + showHorizontalLines : this.options.scaleShowHorizontalLines, + showVerticalLines : this.options.scaleShowVerticalLines, + gridLineWidth : (this.options.scaleShowGridLines) ? this.options.scaleGridLineWidth : 0, + gridLineColor : (this.options.scaleShowGridLines) ? this.options.scaleGridLineColor : "rgba(0,0,0,0)", + padding: (this.options.showScale) ? 0 : this.options.pointDotRadius + this.options.pointDotStrokeWidth, + showLabels : this.options.scaleShowLabels, + display : this.options.showScale + }; + + if (this.options.scaleOverride){ + helpers.extend(scaleOptions, { + calculateYRange: helpers.noop, + steps: this.options.scaleSteps, + stepValue: this.options.scaleStepWidth, + min: this.options.scaleStartValue, + max: this.options.scaleStartValue + (this.options.scaleSteps * this.options.scaleStepWidth) + }); + } + + + this.scale = new Chart.Scale(scaleOptions); + }, + addData : function(valuesArray,label){ + //Map the values array for each of the datasets + + helpers.each(valuesArray,function(value,datasetIndex){ + //Add a new point for each piece of data, passing any required data to draw. + this.datasets[datasetIndex].points.push(new this.PointClass({ + value : value, + label : label, + datasetLabel: this.datasets[datasetIndex].label, + x: this.scale.calculateX(this.scale.valuesCount+1), + y: this.scale.endPoint, + strokeColor : this.datasets[datasetIndex].pointStrokeColor, + fillColor : this.datasets[datasetIndex].pointColor + })); + },this); + + this.scale.addXLabel(label); + //Then re-render the chart. + this.update(); + }, + removeData : function(){ + this.scale.removeXLabel(); + //Then re-render the chart. + helpers.each(this.datasets,function(dataset){ + dataset.points.shift(); + },this); + this.update(); + }, + reflow : function(){ + var newScaleProps = helpers.extend({ + height : this.chart.height, + width : this.chart.width + }); + this.scale.update(newScaleProps); + }, + draw : function(ease){ + var easingDecimal = ease || 1; + this.clear(); + + var ctx = this.chart.ctx; + + // Some helper methods for getting the next/prev points + var hasValue = function(item){ + return item.value !== null; + }, + nextPoint = function(point, collection, index){ + return helpers.findNextWhere(collection, hasValue, index) || point; + }, + previousPoint = function(point, collection, index){ + return helpers.findPreviousWhere(collection, hasValue, index) || point; + }; + + if (!this.scale) return; + this.scale.draw(easingDecimal); + + + helpers.each(this.datasets,function(dataset){ + var pointsWithValues = helpers.where(dataset.points, hasValue); + + //Transition each point first so that the line and point drawing isn't out of sync + //We can use this extra loop to calculate the control points of this dataset also in this loop + + helpers.each(dataset.points, function(point, index){ + if (point.hasValue()){ + point.transition({ + y : this.scale.calculateY(point.value), + x : this.scale.calculateX(index) + }, easingDecimal); + } + },this); + + + // Control points need to be calculated in a separate loop, because we need to know the current x/y of the point + // This would cause issues when there is no animation, because the y of the next point would be 0, so beziers would be skewed + if (this.options.bezierCurve){ + helpers.each(pointsWithValues, function(point, index){ + var tension = (index > 0 && index < pointsWithValues.length - 1) ? this.options.bezierCurveTension : 0; + point.controlPoints = helpers.splineCurve( + previousPoint(point, pointsWithValues, index), + point, + nextPoint(point, pointsWithValues, index), + tension + ); + + // Prevent the bezier going outside of the bounds of the graph + + // Cap puter bezier handles to the upper/lower scale bounds + if (point.controlPoints.outer.y > this.scale.endPoint){ + point.controlPoints.outer.y = this.scale.endPoint; + } + else if (point.controlPoints.outer.y < this.scale.startPoint){ + point.controlPoints.outer.y = this.scale.startPoint; + } + + // Cap inner bezier handles to the upper/lower scale bounds + if (point.controlPoints.inner.y > this.scale.endPoint){ + point.controlPoints.inner.y = this.scale.endPoint; + } + else if (point.controlPoints.inner.y < this.scale.startPoint){ + point.controlPoints.inner.y = this.scale.startPoint; + } + },this); + } + + + //Draw the line between all the points + ctx.lineWidth = this.options.datasetStrokeWidth; + ctx.strokeStyle = dataset.strokeColor; + ctx.beginPath(); + + helpers.each(pointsWithValues, function(point, index){ + if (index === 0){ + ctx.moveTo(point.x, point.y); + } + else{ + if(this.options.bezierCurve){ + var previous = previousPoint(point, pointsWithValues, index); + + ctx.bezierCurveTo( + previous.controlPoints.outer.x, + previous.controlPoints.outer.y, + point.controlPoints.inner.x, + point.controlPoints.inner.y, + point.x, + point.y + ); + } + else{ + ctx.lineTo(point.x,point.y); + } + } + }, this); + + if (this.options.datasetStroke) { + ctx.stroke(); + } + + if (this.options.datasetFill && pointsWithValues.length > 0){ + //Round off the line by going to the base of the chart, back to the start, then fill. + ctx.lineTo(pointsWithValues[pointsWithValues.length - 1].x, this.scale.endPoint); + ctx.lineTo(pointsWithValues[0].x, this.scale.endPoint); + ctx.fillStyle = dataset.fillColor; + ctx.closePath(); + ctx.fill(); + } + + //Now draw the points over the line + //A little inefficient double looping, but better than the line + //lagging behind the point positions + helpers.each(pointsWithValues,function(point){ + point.draw(); + }); + },this); + } + }); + + +}).call(this); diff --git a/snapshots/muneeb-mbytes_pulpino__spi_master__subsystem_verification_pr28/sim/questa_sim/basic_write_read_reg_test/html_cov_report/lib/Chart/src/Chart.PolarArea.js b/snapshots/muneeb-mbytes_pulpino__spi_master__subsystem_verification_pr28/sim/questa_sim/basic_write_read_reg_test/html_cov_report/lib/Chart/src/Chart.PolarArea.js new file mode 100644 index 0000000000000000000000000000000000000000..d1802f5d61754f3ead44d64ba8b053314cc39979 --- /dev/null +++ b/snapshots/muneeb-mbytes_pulpino__spi_master__subsystem_verification_pr28/sim/questa_sim/basic_write_read_reg_test/html_cov_report/lib/Chart/src/Chart.PolarArea.js @@ -0,0 +1,250 @@ +(function(){ + "use strict"; + + var root = this, + Chart = root.Chart, + //Cache a local reference to Chart.helpers + helpers = Chart.helpers; + + var defaultConfig = { + //Boolean - Show a backdrop to the scale label + scaleShowLabelBackdrop : true, + + //String - The colour of the label backdrop + scaleBackdropColor : "rgba(255,255,255,0.75)", + + // Boolean - Whether the scale should begin at zero + scaleBeginAtZero : true, + + //Number - The backdrop padding above & below the label in pixels + scaleBackdropPaddingY : 2, + + //Number - The backdrop padding to the side of the label in pixels + scaleBackdropPaddingX : 2, + + //Boolean - Show line for each value in the scale + scaleShowLine : true, + + //Boolean - Stroke a line around each segment in the chart + segmentShowStroke : true, + + //String - The colour of the stroke on each segment. + segmentStrokeColor : "#fff", + + //Number - The width of the stroke value in pixels + segmentStrokeWidth : 2, + + //Number - Amount of animation steps + animationSteps : 100, + + //String - Animation easing effect. + animationEasing : "easeOutBounce", + + //Boolean - Whether to animate the rotation of the chart + animateRotate : true, + + //Boolean - Whether to animate scaling the chart from the centre + animateScale : false, + + //String - A legend template + legendTemplate : "
    -legend\"><% for (var i=0; i
  • \"><%if(segments[i].label){%><%=segments[i].label%><%}%>
    • <%}%>
" + }; + + + Chart.Type.extend({ + //Passing in a name registers this chart in the Chart namespace + name: "PolarArea", + //Providing a defaults will also register the deafults in the chart namespace + defaults : defaultConfig, + //Initialize is fired when the chart is initialized - Data is passed in as a parameter + //Config is automatically merged by the core of Chart.js, and is available at this.options + initialize: function(data){ + this.segments = []; + //Declare segment class as a chart instance specific class, so it can share props for this instance + this.SegmentArc = Chart.Arc.extend({ + showStroke : this.options.segmentShowStroke, + strokeWidth : this.options.segmentStrokeWidth, + strokeColor : this.options.segmentStrokeColor, + ctx : this.chart.ctx, + innerRadius : 0, + x : this.chart.width/2, + y : this.chart.height/2 + }); + this.scale = new Chart.RadialScale({ + display: this.options.showScale, + fontStyle: this.options.scaleFontStyle, + fontSize: this.options.scaleFontSize, + fontFamily: this.options.scaleFontFamily, + fontColor: this.options.scaleFontColor, + showLabels: this.options.scaleShowLabels, + showLabelBackdrop: this.options.scaleShowLabelBackdrop, + backdropColor: this.options.scaleBackdropColor, + backdropPaddingY : this.options.scaleBackdropPaddingY, + backdropPaddingX: this.options.scaleBackdropPaddingX, + lineWidth: (this.options.scaleShowLine) ? this.options.scaleLineWidth : 0, + lineColor: this.options.scaleLineColor, + lineArc: true, + width: this.chart.width, + height: this.chart.height, + xCenter: this.chart.width/2, + yCenter: this.chart.height/2, + ctx : this.chart.ctx, + templateString: this.options.scaleLabel, + valuesCount: data.length + }); + + this.updateScaleRange(data); + + this.scale.update(); + + helpers.each(data,function(segment,index){ + this.addData(segment,index,true); + },this); + + //Set up tooltip events on the chart + if (this.options.showTooltips){ + helpers.bindEvents(this, this.options.tooltipEvents, function(evt){ + var activeSegments = (evt.type !== 'mouseout') ? this.getSegmentsAtEvent(evt) : []; + helpers.each(this.segments,function(segment){ + segment.restore(["fillColor"]); + }); + helpers.each(activeSegments,function(activeSegment){ + activeSegment.fillColor = activeSegment.highlightColor; + }); + this.showTooltip(activeSegments); + }); + } + + this.render(); + }, + getSegmentsAtEvent : function(e){ + var segmentsArray = []; + + var location = helpers.getRelativePosition(e); + + helpers.each(this.segments,function(segment){ + if (segment.inRange(location.x,location.y)) segmentsArray.push(segment); + },this); + return segmentsArray; + }, + addData : function(segment, atIndex, silent){ + var index = atIndex || this.segments.length; + + this.segments.splice(index, 0, new this.SegmentArc({ + fillColor: segment.color, + highlightColor: segment.highlight || segment.color, + label: segment.label, + value: segment.value, + outerRadius: (this.options.animateScale) ? 0 : this.scale.calculateCenterOffset(segment.value), + circumference: (this.options.animateRotate) ? 0 : this.scale.getCircumference(), + startAngle: Math.PI * 1.5 + })); + if (!silent){ + this.reflow(); + this.update(); + } + }, + removeData: function(atIndex){ + var indexToDelete = (helpers.isNumber(atIndex)) ? atIndex : this.segments.length-1; + this.segments.splice(indexToDelete, 1); + this.reflow(); + this.update(); + }, + calculateTotal: function(data){ + this.total = 0; + helpers.each(data,function(segment){ + this.total += segment.value; + },this); + this.scale.valuesCount = this.segments.length; + }, + updateScaleRange: function(datapoints){ + var valuesArray = []; + helpers.each(datapoints,function(segment){ + valuesArray.push(segment.value); + }); + + var scaleSizes = (this.options.scaleOverride) ? + { + steps: this.options.scaleSteps, + stepValue: this.options.scaleStepWidth, + min: this.options.scaleStartValue, + max: this.options.scaleStartValue + (this.options.scaleSteps * this.options.scaleStepWidth) + } : + helpers.calculateScaleRange( + valuesArray, + helpers.min([this.chart.width, this.chart.height])/2, + this.options.scaleFontSize, + this.options.scaleBeginAtZero, + this.options.scaleIntegersOnly + ); + + helpers.extend( + this.scale, + scaleSizes, + { + size: helpers.min([this.chart.width, this.chart.height]), + xCenter: this.chart.width/2, + yCenter: this.chart.height/2 + } + ); + + }, + update : function(){ + this.calculateTotal(this.segments); + + helpers.each(this.segments,function(segment){ + segment.save(); + }); + + this.reflow(); + this.render(); + }, + reflow : function(){ + helpers.extend(this.SegmentArc.prototype,{ + x : this.chart.width/2, + y : this.chart.height/2 + }); + this.updateScaleRange(this.segments); + this.scale.update(); + + helpers.extend(this.scale,{ + xCenter: this.chart.width/2, + yCenter: this.chart.height/2 + }); + + helpers.each(this.segments, function(segment){ + segment.update({ + outerRadius : this.scale.calculateCenterOffset(segment.value) + }); + }, this); + + }, + draw : function(ease){ + var easingDecimal = ease || 1; + //Clear & draw the canvas + this.clear(); + helpers.each(this.segments,function(segment, index){ + segment.transition({ + circumference : this.scale.getCircumference(), + outerRadius : this.scale.calculateCenterOffset(segment.value) + },easingDecimal); + + segment.endAngle = segment.startAngle + segment.circumference; + + // If we've removed the first segment we need to set the first one to + // start at the top. + if (index === 0){ + segment.startAngle = Math.PI * 1.5; + } + + //Check to see if it's the last segment, if not get the next and update the start angle + if (index < this.segments.length - 1){ + this.segments[index+1].startAngle = segment.endAngle; + } + segment.draw(); + }, this); + this.scale.draw(); + } + }); + +}).call(this); diff --git a/snapshots/muneeb-mbytes_pulpino__spi_master__subsystem_verification_pr28/sim/questa_sim/basic_write_read_reg_test/html_cov_report/lib/Chart/src/Chart.Radar.js b/snapshots/muneeb-mbytes_pulpino__spi_master__subsystem_verification_pr28/sim/questa_sim/basic_write_read_reg_test/html_cov_report/lib/Chart/src/Chart.Radar.js new file mode 100644 index 0000000000000000000000000000000000000000..93d7352fd9838f399ec725e979159649c6d30d10 --- /dev/null +++ b/snapshots/muneeb-mbytes_pulpino__spi_master__subsystem_verification_pr28/sim/questa_sim/basic_write_read_reg_test/html_cov_report/lib/Chart/src/Chart.Radar.js @@ -0,0 +1,346 @@ +(function(){ + "use strict"; + + var root = this, + Chart = root.Chart, + helpers = Chart.helpers; + + + + Chart.Type.extend({ + name: "Radar", + defaults:{ + //Boolean - Whether to show lines for each scale point + scaleShowLine : true, + + //Boolean - Whether we show the angle lines out of the radar + angleShowLineOut : true, + + //Boolean - Whether to show labels on the scale + scaleShowLabels : false, + + // Boolean - Whether the scale should begin at zero + scaleBeginAtZero : true, + + //String - Colour of the angle line + angleLineColor : "rgba(0,0,0,.1)", + + //Number - Pixel width of the angle line + angleLineWidth : 1, + + //String - Point label font declaration + pointLabelFontFamily : "'Arial'", + + //String - Point label font weight + pointLabelFontStyle : "normal", + + //Number - Point label font size in pixels + pointLabelFontSize : 10, + + //String - Point label font colour + pointLabelFontColor : "#666", + + //Boolean - Whether to show a dot for each point + pointDot : true, + + //Number - Radius of each point dot in pixels + pointDotRadius : 3, + + //Number - Pixel width of point dot stroke + pointDotStrokeWidth : 1, + + //Number - amount extra to add to the radius to cater for hit detection outside the drawn point + pointHitDetectionRadius : 20, + + //Boolean - Whether to show a stroke for datasets + datasetStroke : true, + + //Number - Pixel width of dataset stroke + datasetStrokeWidth : 2, + + //Boolean - Whether to fill the dataset with a colour + datasetFill : true, + + //String - A legend template + legendTemplate : "
    -legend\"><% for (var i=0; i
  • \"><%if(datasets[i].label){%><%=datasets[i].label%><%}%>
    • <%}%>
" + + }, + + initialize: function(data){ + this.PointClass = Chart.Point.extend({ + strokeWidth : this.options.pointDotStrokeWidth, + radius : this.options.pointDotRadius, + display: this.options.pointDot, + hitDetectionRadius : this.options.pointHitDetectionRadius, + ctx : this.chart.ctx + }); + + this.datasets = []; + + this.buildScale(data); + + //Set up tooltip events on the chart + if (this.options.showTooltips){ + helpers.bindEvents(this, this.options.tooltipEvents, function(evt){ + var activePointsCollection = (evt.type !== 'mouseout') ? this.getPointsAtEvent(evt) : []; + + this.eachPoints(function(point){ + point.restore(['fillColor', 'strokeColor']); + }); + helpers.each(activePointsCollection, function(activePoint){ + activePoint.fillColor = activePoint.highlightFill; + activePoint.strokeColor = activePoint.highlightStroke; + }); + + this.showTooltip(activePointsCollection); + }); + } + + //Iterate through each of the datasets, and build this into a property of the chart + helpers.each(data.datasets,function(dataset){ + + var datasetObject = { + label: dataset.label || null, + fillColor : dataset.fillColor, + strokeColor : dataset.strokeColor, + pointColor : dataset.pointColor, + pointStrokeColor : dataset.pointStrokeColor, + points : [] + }; + + this.datasets.push(datasetObject); + + helpers.each(dataset.data,function(dataPoint,index){ + //Add a new point for each piece of data, passing any required data to draw. + var pointPosition; + if (!this.scale.animation){ + pointPosition = this.scale.getPointPosition(index, this.scale.calculateCenterOffset(dataPoint)); + } + datasetObject.points.push(new this.PointClass({ + value : dataPoint, + label : data.labels[index], + datasetLabel: dataset.label, + x: (this.options.animation) ? this.scale.xCenter : pointPosition.x, + y: (this.options.animation) ? this.scale.yCenter : pointPosition.y, + strokeColor : dataset.pointStrokeColor, + fillColor : dataset.pointColor, + highlightFill : dataset.pointHighlightFill || dataset.pointColor, + highlightStroke : dataset.pointHighlightStroke || dataset.pointStrokeColor + })); + },this); + + },this); + + this.render(); + }, + eachPoints : function(callback){ + helpers.each(this.datasets,function(dataset){ + helpers.each(dataset.points,callback,this); + },this); + }, + + getPointsAtEvent : function(evt){ + var mousePosition = helpers.getRelativePosition(evt), + fromCenter = helpers.getAngleFromPoint({ + x: this.scale.xCenter, + y: this.scale.yCenter + }, mousePosition); + + var anglePerIndex = (Math.PI * 2) /this.scale.valuesCount, + pointIndex = Math.round((fromCenter.angle - Math.PI * 1.5) / anglePerIndex), + activePointsCollection = []; + + // If we're at the top, make the pointIndex 0 to get the first of the array. + if (pointIndex >= this.scale.valuesCount || pointIndex < 0){ + pointIndex = 0; + } + + if (fromCenter.distance <= this.scale.drawingArea){ + helpers.each(this.datasets, function(dataset){ + activePointsCollection.push(dataset.points[pointIndex]); + }); + } + + return activePointsCollection; + }, + + buildScale : function(data){ + this.scale = new Chart.RadialScale({ + display: this.options.showScale, + fontStyle: this.options.scaleFontStyle, + fontSize: this.options.scaleFontSize, + fontFamily: this.options.scaleFontFamily, + fontColor: this.options.scaleFontColor, + showLabels: this.options.scaleShowLabels, + showLabelBackdrop: this.options.scaleShowLabelBackdrop, + backdropColor: this.options.scaleBackdropColor, + backgroundColors: this.options.scaleBackgroundColors, + backdropPaddingY : this.options.scaleBackdropPaddingY, + backdropPaddingX: this.options.scaleBackdropPaddingX, + lineWidth: (this.options.scaleShowLine) ? this.options.scaleLineWidth : 0, + lineColor: this.options.scaleLineColor, + angleLineColor : this.options.angleLineColor, + angleLineWidth : (this.options.angleShowLineOut) ? this.options.angleLineWidth : 0, + // Point labels at the edge of each line + pointLabelFontColor : this.options.pointLabelFontColor, + pointLabelFontSize : this.options.pointLabelFontSize, + pointLabelFontFamily : this.options.pointLabelFontFamily, + pointLabelFontStyle : this.options.pointLabelFontStyle, + height : this.chart.height, + width: this.chart.width, + xCenter: this.chart.width/2, + yCenter: this.chart.height/2, + ctx : this.chart.ctx, + templateString: this.options.scaleLabel, + labels: data.labels, + valuesCount: data.datasets[0].data.length + }); + + this.scale.setScaleSize(); + this.updateScaleRange(data.datasets); + this.scale.buildYLabels(); + }, + updateScaleRange: function(datasets){ + var valuesArray = (function(){ + var totalDataArray = []; + helpers.each(datasets,function(dataset){ + if (dataset.data){ + totalDataArray = totalDataArray.concat(dataset.data); + } + else { + helpers.each(dataset.points, function(point){ + totalDataArray.push(point.value); + }); + } + }); + return totalDataArray; + })(); + + + var scaleSizes = (this.options.scaleOverride) ? + { + steps: this.options.scaleSteps, + stepValue: this.options.scaleStepWidth, + min: this.options.scaleStartValue, + max: this.options.scaleStartValue + (this.options.scaleSteps * this.options.scaleStepWidth) + } : + helpers.calculateScaleRange( + valuesArray, + helpers.min([this.chart.width, this.chart.height])/2, + this.options.scaleFontSize, + this.options.scaleBeginAtZero, + this.options.scaleIntegersOnly + ); + + helpers.extend( + this.scale, + scaleSizes + ); + + }, + addData : function(valuesArray,label){ + //Map the values array for each of the datasets + this.scale.valuesCount++; + helpers.each(valuesArray,function(value,datasetIndex){ + var pointPosition = this.scale.getPointPosition(this.scale.valuesCount, this.scale.calculateCenterOffset(value)); + this.datasets[datasetIndex].points.push(new this.PointClass({ + value : value, + label : label, + datasetLabel: this.datasets[datasetIndex].label, + x: pointPosition.x, + y: pointPosition.y, + strokeColor : this.datasets[datasetIndex].pointStrokeColor, + fillColor : this.datasets[datasetIndex].pointColor + })); + },this); + + this.scale.labels.push(label); + + this.reflow(); + + this.update(); + }, + removeData : function(){ + this.scale.valuesCount--; + this.scale.labels.shift(); + helpers.each(this.datasets,function(dataset){ + dataset.points.shift(); + },this); + this.reflow(); + this.update(); + }, + update : function(){ + this.eachPoints(function(point){ + point.save(); + }); + this.reflow(); + this.render(); + }, + reflow: function(){ + helpers.extend(this.scale, { + width : this.chart.width, + height: this.chart.height, + size : helpers.min([this.chart.width, this.chart.height]), + xCenter: this.chart.width/2, + yCenter: this.chart.height/2 + }); + this.updateScaleRange(this.datasets); + this.scale.setScaleSize(); + this.scale.buildYLabels(); + }, + draw : function(ease){ + var easeDecimal = ease || 1, + ctx = this.chart.ctx; + this.clear(); + this.scale.draw(); + + helpers.each(this.datasets,function(dataset){ + + //Transition each point first so that the line and point drawing isn't out of sync + helpers.each(dataset.points,function(point,index){ + if (point.hasValue()){ + point.transition(this.scale.getPointPosition(index, this.scale.calculateCenterOffset(point.value)), easeDecimal); + } + },this); + + + + //Draw the line between all the points + ctx.lineWidth = this.options.datasetStrokeWidth; + ctx.strokeStyle = dataset.strokeColor; + ctx.beginPath(); + helpers.each(dataset.points,function(point,index){ + if (index === 0){ + ctx.moveTo(point.x,point.y); + } + else{ + ctx.lineTo(point.x,point.y); + } + },this); + ctx.closePath(); + ctx.stroke(); + + ctx.fillStyle = dataset.fillColor; + if(this.options.datasetFill){ + ctx.fill(); + } + //Now draw the points over the line + //A little inefficient double looping, but better than the line + //lagging behind the point positions + helpers.each(dataset.points,function(point){ + if (point.hasValue()){ + point.draw(); + } + }); + + },this); + + } + + }); + + + + + +}).call(this); diff --git a/snapshots/muneeb-mbytes_pulpino__spi_master__subsystem_verification_pr28/sim/questa_sim/basic_write_read_reg_test/html_cov_report/lib/DataTables/css/jquery.dataTables.css b/snapshots/muneeb-mbytes_pulpino__spi_master__subsystem_verification_pr28/sim/questa_sim/basic_write_read_reg_test/html_cov_report/lib/DataTables/css/jquery.dataTables.css new file mode 100644 index 0000000000000000000000000000000000000000..e9f356e6002321045df55dfcdd2f2eb36d17a7e1 --- /dev/null +++ b/snapshots/muneeb-mbytes_pulpino__spi_master__subsystem_verification_pr28/sim/questa_sim/basic_write_read_reg_test/html_cov_report/lib/DataTables/css/jquery.dataTables.css @@ -0,0 +1,371 @@ +/* + * Table styles + */ +table.dataTable { + width: 100%; + margin: 0 auto; + clear: both; + border-collapse: separate; + border-spacing: 0; + /* + * Header and footer styles + */ + /* + * Body styles + */ } + table.dataTable thead th, + table.dataTable tfoot th { + font-weight: bold; } + table.dataTable thead th, + table.dataTable thead td { + padding: 10px 18px; + border-bottom: 0px none #111111; } + table.dataTable thead th:active, + table.dataTable thead td:active { + outline: none; } + table.dataTable tfoot th, + table.dataTable tfoot td { + padding: 10px 18px 6px 18px; + border-top: 0px none #111111; } + table.dataTable thead .sorting, + table.dataTable thead .sorting_asc, + table.dataTable thead .sorting_desc { + cursor: pointer; + *cursor: hand; } + table.dataTable thead .sorting, + table.dataTable thead .sorting_asc, + table.dataTable thead .sorting_desc, + table.dataTable thead .sorting_asc_disabled, + table.dataTable thead .sorting_desc_disabled { + background-repeat: no-repeat; + background-position: center right; } + table.dataTable thead .sorting { + background-image: url("../images/sort_both.png"); } + table.dataTable thead .sorting_asc { + background-image: url("../images/sort_asc.png"); } + table.dataTable thead .sorting_desc { + background-image: url("../images/sort_desc.png"); } + table.dataTable thead .sorting_asc_disabled { + background-image: url("../images/sort_asc_disabled.png"); } + table.dataTable thead .sorting_desc_disabled { + background-image: url("../images/sort_desc_disabled.png"); } + table.dataTable tbody tr { + background-color: white; } + table.dataTable tbody tr.selected { + background-color: #b0bed9; } + table.dataTable tbody th, + table.dataTable tbody td { + padding: 8px 10px; } + table.dataTable.row-border tbody th, table.dataTable.row-border tbody td, table.dataTable.display tbody th, table.dataTable.display tbody td { + border-top: 1px solid #dddddd; } + table.dataTable.row-border tbody tr:first-child th, + table.dataTable.row-border tbody tr:first-child td, table.dataTable.display tbody tr:first-child th, + table.dataTable.display tbody tr:first-child td { + border-top: none; } + table.dataTable.cell-border tbody th, table.dataTable.cell-border tbody td { + border-top: 1px solid #dddddd; + border-right: 1px solid #dddddd; } + table.dataTable.cell-border tbody tr th:first-child, + table.dataTable.cell-border tbody tr td:first-child { + border-left: 1px solid #dddddd; } + table.dataTable.cell-border tbody tr:first-child th, + table.dataTable.cell-border tbody tr:first-child td { + border-top: none; } + table.dataTable.stripe tbody tr.odd, table.dataTable.display tbody tr.odd { + background-color: #f9f9f9; } + table.dataTable.stripe tbody tr.odd.selected, table.dataTable.display tbody tr.odd.selected { + background-color: #abb9d3; } + table.dataTable.hover tbody tr:hover, table.dataTable.display tbody tr:hover { + background-color: whitesmoke; } + table.dataTable.hover tbody tr:hover.selected, table.dataTable.display tbody tr:hover.selected { + background-color: #a9b7d1; } + table.dataTable.order-column tbody tr > .sorting_1, + table.dataTable.order-column tbody tr > .sorting_2, + table.dataTable.order-column tbody tr > .sorting_3, table.dataTable.display tbody tr > .sorting_1, + table.dataTable.display tbody tr > .sorting_2, + table.dataTable.display tbody tr > .sorting_3 { + background-color: #f9f9f9; } + table.dataTable.order-column tbody tr.selected > .sorting_1, + table.dataTable.order-column tbody tr.selected > .sorting_2, + table.dataTable.order-column tbody tr.selected > .sorting_3, table.dataTable.display tbody tr.selected > .sorting_1, + table.dataTable.display tbody tr.selected > .sorting_2, + table.dataTable.display tbody tr.selected > .sorting_3 { + background-color: #acbad4; } + table.dataTable.display tbody tr.odd > .sorting_1, table.dataTable.order-column.stripe tbody tr.odd > .sorting_1 { + background-color: #f1f1f1; } + table.dataTable.display tbody tr.odd > .sorting_2, table.dataTable.order-column.stripe tbody tr.odd > .sorting_2 { + background-color: #f3f3f3; } + table.dataTable.display tbody tr.odd > .sorting_3, table.dataTable.order-column.stripe tbody tr.odd > .sorting_3 { + background-color: whitesmoke; } + table.dataTable.display tbody tr.odd.selected > .sorting_1, table.dataTable.order-column.stripe tbody tr.odd.selected > .sorting_1 { + background-color: #a6b3cd; } + table.dataTable.display tbody tr.odd.selected > .sorting_2, table.dataTable.order-column.stripe tbody tr.odd.selected > .sorting_2 { + background-color: #a7b5ce; } + table.dataTable.display tbody tr.odd.selected > .sorting_3, table.dataTable.order-column.stripe tbody tr.odd.selected > .sorting_3 { + background-color: #a9b6d0; } + table.dataTable.display tbody tr.even > .sorting_1, table.dataTable.order-column.stripe tbody tr.even > .sorting_1 { + background-color: #f9f9f9; } + table.dataTable.display tbody tr.even > .sorting_2, table.dataTable.order-column.stripe tbody tr.even > .sorting_2 { + background-color: #fbfbfb; } + table.dataTable.display tbody tr.even > .sorting_3, table.dataTable.order-column.stripe tbody tr.even > .sorting_3 { + background-color: #fdfdfd; } + table.dataTable.display tbody tr.even.selected > .sorting_1, table.dataTable.order-column.stripe tbody tr.even.selected > .sorting_1 { + background-color: #acbad4; } + table.dataTable.display tbody tr.even.selected > .sorting_2, table.dataTable.order-column.stripe tbody tr.even.selected > .sorting_2 { + background-color: #adbbd6; } + table.dataTable.display tbody tr.even.selected > .sorting_3, table.dataTable.order-column.stripe tbody tr.even.selected > .sorting_3 { + background-color: #afbdd8; } + table.dataTable.display tbody tr:hover > .sorting_1, table.dataTable.order-column.hover tbody tr:hover > .sorting_1 { + background-color: #eaeaea; } + table.dataTable.display tbody tr:hover > .sorting_2, table.dataTable.order-column.hover tbody tr:hover > .sorting_2 { + background-color: #ebebeb; } + table.dataTable.display tbody tr:hover > .sorting_3, table.dataTable.order-column.hover tbody tr:hover > .sorting_3 { + background-color: #eeeeee; } + table.dataTable.display tbody tr:hover.selected > .sorting_1, table.dataTable.order-column.hover tbody tr:hover.selected > .sorting_1 { + background-color: #a1aec7; } + table.dataTable.display tbody tr:hover.selected > .sorting_2, table.dataTable.order-column.hover tbody tr:hover.selected > .sorting_2 { + background-color: #a2afc8; } + table.dataTable.display tbody tr:hover.selected > .sorting_3, table.dataTable.order-column.hover tbody tr:hover.selected > .sorting_3 { + background-color: #a4b2cb; } + table.dataTable.no-footer { + border-bottom: 0px none #111111; } + table.dataTable.nowrap th, table.dataTable.nowrap td { + white-space: nowrap; } + table.dataTable.compact thead th, + table.dataTable.compact thead td { + padding: 4px 17px 4px 4px; } + table.dataTable.compact tfoot th, + table.dataTable.compact tfoot td { + padding: 4px; } + table.dataTable.compact tbody th, + table.dataTable.compact tbody td { + padding: 4px; } + table.dataTable th.dt-left, + table.dataTable td.dt-left { + text-align: left; } + table.dataTable th.dt-center, + table.dataTable td.dt-center, + table.dataTable td.dataTables_empty { + text-align: center; } + table.dataTable th.dt-right, + table.dataTable td.dt-right { + text-align: right; } + table.dataTable th.dt-justify, + table.dataTable td.dt-justify { + text-align: justify; } + table.dataTable th.dt-nowrap, + table.dataTable td.dt-nowrap { + white-space: nowrap; } + table.dataTable thead th.dt-head-left, + table.dataTable thead td.dt-head-left, + table.dataTable tfoot th.dt-head-left, + table.dataTable tfoot td.dt-head-left { + text-align: left; } + table.dataTable thead th.dt-head-center, + table.dataTable thead td.dt-head-center, + table.dataTable tfoot th.dt-head-center, + table.dataTable tfoot td.dt-head-center { + text-align: center; } + table.dataTable thead th.dt-head-right, + table.dataTable thead td.dt-head-right, + table.dataTable tfoot th.dt-head-right, + table.dataTable tfoot td.dt-head-right { + text-align: right; } + table.dataTable thead th.dt-head-justify, + table.dataTable thead td.dt-head-justify, + table.dataTable tfoot th.dt-head-justify, + table.dataTable tfoot td.dt-head-justify { + text-align: justify; } + table.dataTable thead th.dt-head-nowrap, + table.dataTable thead td.dt-head-nowrap, + table.dataTable tfoot th.dt-head-nowrap, + table.dataTable tfoot td.dt-head-nowrap { + white-space: nowrap; } + table.dataTable tbody th.dt-body-left, + table.dataTable tbody td.dt-body-left { + text-align: left; } + table.dataTable tbody th.dt-body-center, + table.dataTable tbody td.dt-body-center { + text-align: center; } + table.dataTable tbody th.dt-body-right, + table.dataTable tbody td.dt-body-right { + text-align: right; } + table.dataTable tbody th.dt-body-justify, + table.dataTable tbody td.dt-body-justify { + text-align: justify; } + table.dataTable tbody th.dt-body-nowrap, + table.dataTable tbody td.dt-body-nowrap { + white-space: nowrap; } + +table.dataTable, +table.dataTable th, +table.dataTable td { + -webkit-box-sizing: content-box; + -moz-box-sizing: content-box; + box-sizing: content-box; } + +/* + * Control feature layout + */ +.dataTables_wrapper { + position: relative; + clear: both; + *zoom: 1; + zoom: 1; } + .dataTables_wrapper .dataTables_length { + float: left; } + .dataTables_wrapper .dataTables_filter { + float: right; + text-align: right; } + .dataTables_wrapper .dataTables_filter input { + margin-left: 0.5em; } + .dataTables_wrapper .dataTables_info { + clear: both; + float: left; + padding-top: 0.755em; } + .dataTables_wrapper .dataTables_paginate { + float: right; + text-align: right; + padding-top: 0.25em; } + .dataTables_wrapper .dataTables_paginate .paginate_button { + box-sizing: border-box; + display: inline-block; + min-width: 1.5em; + padding: 0.5em 1em; + margin-left: 2px; + text-align: center; + text-decoration: none !important; + cursor: pointer; + *cursor: hand; + color: #333333 !important; + border: 1px solid transparent; } + .dataTables_wrapper .dataTables_paginate .paginate_button.current, .dataTables_wrapper .dataTables_paginate .paginate_button.current:hover { + color: #333333 !important; + border: 1px solid #cacaca; + background-color: white; + background: -webkit-gradient(linear, left top, left bottom, color-stop(0%, white), color-stop(100%, gainsboro)); + /* Chrome,Safari4+ */ + background: -webkit-linear-gradient(top, white 0%, gainsboro 100%); + /* Chrome10+,Safari5.1+ */ + background: -moz-linear-gradient(top, white 0%, gainsboro 100%); + /* FF3.6+ */ + background: -ms-linear-gradient(top, white 0%, gainsboro 100%); + /* IE10+ */ + background: -o-linear-gradient(top, white 0%, gainsboro 100%); + /* Opera 11.10+ */ + background: linear-gradient(to bottom, white 0%, gainsboro 100%); + /* W3C */ } + .dataTables_wrapper .dataTables_paginate .paginate_button.disabled, .dataTables_wrapper .dataTables_paginate .paginate_button.disabled:hover, .dataTables_wrapper .dataTables_paginate .paginate_button.disabled:active { + cursor: default; + color: #666 !important; + border: 1px solid transparent; + background: transparent; + box-shadow: none; } + .dataTables_wrapper .dataTables_paginate .paginate_button:hover { + color: white !important; + border: 1px solid #111111; + background-color: #585858; + background: -webkit-gradient(linear, left top, left bottom, color-stop(0%, #585858), color-stop(100%, #111111)); + /* Chrome,Safari4+ */ + background: -webkit-linear-gradient(top, #585858 0%, #111111 100%); + /* Chrome10+,Safari5.1+ */ + background: -moz-linear-gradient(top, #585858 0%, #111111 100%); + /* FF3.6+ */ + background: -ms-linear-gradient(top, #585858 0%, #111111 100%); + /* IE10+ */ + background: -o-linear-gradient(top, #585858 0%, #111111 100%); + /* Opera 11.10+ */ + background: linear-gradient(to bottom, #585858 0%, #111111 100%); + /* W3C */ } + .dataTables_wrapper .dataTables_paginate .paginate_button:active { + outline: none; + background-color: #2b2b2b; + background: -webkit-gradient(linear, left top, left bottom, color-stop(0%, #2b2b2b), color-stop(100%, #0c0c0c)); + /* Chrome,Safari4+ */ + background: -webkit-linear-gradient(top, #2b2b2b 0%, #0c0c0c 100%); + /* Chrome10+,Safari5.1+ */ + background: -moz-linear-gradient(top, #2b2b2b 0%, #0c0c0c 100%); + /* FF3.6+ */ + background: -ms-linear-gradient(top, #2b2b2b 0%, #0c0c0c 100%); + /* IE10+ */ + background: -o-linear-gradient(top, #2b2b2b 0%, #0c0c0c 100%); + /* Opera 11.10+ */ + background: linear-gradient(to bottom, #2b2b2b 0%, #0c0c0c 100%); + /* W3C */ + box-shadow: inset 0 0 3px #111; } + .dataTables_wrapper .dataTables_paginate .ellipsis { + padding: 0 1em; } + .dataTables_wrapper .dataTables_processing { + position: absolute; + top: 50%; + left: 50%; + width: 100%; + height: 40px; + margin-left: -50%; + margin-top: -25px; + padding-top: 20px; + text-align: center; + font-size: 1.2em; + background-color: white; + background: -webkit-gradient(linear, left top, right top, color-stop(0%, rgba(255, 255, 255, 0)), color-stop(25%, rgba(255, 255, 255, 0.9)), color-stop(75%, rgba(255, 255, 255, 0.9)), color-stop(100%, rgba(255, 255, 255, 0))); + /* Chrome,Safari4+ */ + background: -webkit-linear-gradient(left, rgba(255, 255, 255, 0) 0%, rgba(255, 255, 255, 0.9) 25%, rgba(255, 255, 255, 0.9) 75%, rgba(255, 255, 255, 0) 100%); + /* Chrome10+,Safari5.1+ */ + background: -moz-linear-gradient(left, rgba(255, 255, 255, 0) 0%, rgba(255, 255, 255, 0.9) 25%, rgba(255, 255, 255, 0.9) 75%, rgba(255, 255, 255, 0) 100%); + /* FF3.6+ */ + background: -ms-linear-gradient(left, rgba(255, 255, 255, 0) 0%, rgba(255, 255, 255, 0.9) 25%, rgba(255, 255, 255, 0.9) 75%, rgba(255, 255, 255, 0) 100%); + /* IE10+ */ + background: -o-linear-gradient(left, rgba(255, 255, 255, 0) 0%, rgba(255, 255, 255, 0.9) 25%, rgba(255, 255, 255, 0.9) 75%, rgba(255, 255, 255, 0) 100%); + /* Opera 11.10+ */ + background: linear-gradient(to right, rgba(255, 255, 255, 0) 0%, rgba(255, 255, 255, 0.9) 25%, rgba(255, 255, 255, 0.9) 75%, rgba(255, 255, 255, 0) 100%); + /* W3C */ } + .dataTables_wrapper .dataTables_length, + .dataTables_wrapper .dataTables_filter, + .dataTables_wrapper .dataTables_info, + .dataTables_wrapper .dataTables_processing, + .dataTables_wrapper .dataTables_paginate { + color: #333333; } + .dataTables_wrapper .dataTables_scroll { + clear: both; } + .dataTables_wrapper .dataTables_scroll div.dataTables_scrollBody { + *margin-top: -1px; + -webkit-overflow-scrolling: touch; } + .dataTables_wrapper .dataTables_scroll div.dataTables_scrollBody th > div.dataTables_sizing, + .dataTables_wrapper .dataTables_scroll div.dataTables_scrollBody td > div.dataTables_sizing { + height: 0; + overflow: hidden; + margin: 0 !important; + padding: 0 !important; } + .dataTables_wrapper.no-footer .dataTables_scrollBody { + border-bottom: 0px none #111111; } + .dataTables_wrapper.no-footer div.dataTables_scrollHead table, + .dataTables_wrapper.no-footer div.dataTables_scrollBody table { + border-bottom: none; } + .dataTables_wrapper:after { + visibility: hidden; + display: block; + content: ""; + clear: both; + height: 0; } + +@media screen and (max-width: 767px) { + .dataTables_wrapper .dataTables_info, + .dataTables_wrapper .dataTables_paginate { + float: none; + text-align: center; } + .dataTables_wrapper .dataTables_paginate { + margin-top: 0.5em; } } +@media screen and (max-width: 640px) { + .dataTables_wrapper .dataTables_length, + .dataTables_wrapper .dataTables_filter { + float: none; + text-align: center; } + .dataTables_wrapper .dataTables_filter { + margin-top: 0.5em; } } + +/* ********** mti customization ********** */ + +.dataTables_filter { + /* to make a margin between the filter text box and the table */ + margin-bottom: 3px; +} diff --git a/snapshots/muneeb-mbytes_pulpino__spi_master__subsystem_verification_pr28/sim/questa_sim/basic_write_read_reg_test/html_cov_report/lib/DataTables/js/jquery.dataTables.js b/snapshots/muneeb-mbytes_pulpino__spi_master__subsystem_verification_pr28/sim/questa_sim/basic_write_read_reg_test/html_cov_report/lib/DataTables/js/jquery.dataTables.js new file mode 100644 index 0000000000000000000000000000000000000000..2a9bdb36e7b872b0a4ae6e0d897ff96337fdd0c8 --- /dev/null +++ b/snapshots/muneeb-mbytes_pulpino__spi_master__subsystem_verification_pr28/sim/questa_sim/basic_write_read_reg_test/html_cov_report/lib/DataTables/js/jquery.dataTables.js @@ -0,0 +1,14951 @@ +/*! DataTables 1.10.7 + * ©2008-2014 SpryMedia Ltd - datatables.net/license + */ + +/** + * @summary DataTables + * @description Paginate, search and order HTML tables + * @version 1.10.7 + * @file jquery.dataTables.js + * @author SpryMedia Ltd (www.sprymedia.co.uk) + * @contact www.sprymedia.co.uk/contact + * @copyright Copyright 2008-2014 SpryMedia Ltd. + * + * This source file is free software, available under the following license: + * MIT license - http://datatables.net/license + * + * This source file is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + * or FITNESS FOR A PARTICULAR PURPOSE. See the license files for details. + * + * For details please refer to: http://www.datatables.net + */ + +/*jslint evil: true, undef: true, browser: true */ +/*globals $,require,jQuery,define,_selector_run,_selector_opts,_selector_first,_selector_row_indexes,_ext,_Api,_api_register,_api_registerPlural,_re_new_lines,_re_html,_re_formatted_numeric,_re_escape_regex,_empty,_intVal,_numToDecimal,_isNumber,_isHtml,_htmlNumeric,_pluck,_pluck_order,_range,_stripHtml,_unique,_fnBuildAjax,_fnAjaxUpdate,_fnAjaxParameters,_fnAjaxUpdateDraw,_fnAjaxDataSrc,_fnAddColumn,_fnColumnOptions,_fnAdjustColumnSizing,_fnVisibleToColumnIndex,_fnColumnIndexToVisible,_fnVisbleColumns,_fnGetColumns,_fnColumnTypes,_fnApplyColumnDefs,_fnHungarianMap,_fnCamelToHungarian,_fnLanguageCompat,_fnBrowserDetect,_fnAddData,_fnAddTr,_fnNodeToDataIndex,_fnNodeToColumnIndex,_fnGetCellData,_fnSetCellData,_fnSplitObjNotation,_fnGetObjectDataFn,_fnSetObjectDataFn,_fnGetDataMaster,_fnClearTable,_fnDeleteIndex,_fnInvalidate,_fnGetRowElements,_fnCreateTr,_fnBuildHead,_fnDrawHead,_fnDraw,_fnReDraw,_fnAddOptionsHtml,_fnDetectHeader,_fnGetUniqueThs,_fnFeatureHtmlFilter,_fnFilterComplete,_fnFilterCustom,_fnFilterColumn,_fnFilter,_fnFilterCreateSearch,_fnEscapeRegex,_fnFilterData,_fnFeatureHtmlInfo,_fnUpdateInfo,_fnInfoMacros,_fnInitialise,_fnInitComplete,_fnLengthChange,_fnFeatureHtmlLength,_fnFeatureHtmlPaginate,_fnPageChange,_fnFeatureHtmlProcessing,_fnProcessingDisplay,_fnFeatureHtmlTable,_fnScrollDraw,_fnApplyToChildren,_fnCalculateColumnWidths,_fnThrottle,_fnConvertToWidth,_fnScrollingWidthAdjust,_fnGetWidestNode,_fnGetMaxLenString,_fnStringToCss,_fnScrollBarWidth,_fnSortFlatten,_fnSort,_fnSortAria,_fnSortListener,_fnSortAttachListener,_fnSortingClasses,_fnSortData,_fnSaveState,_fnLoadState,_fnSettingsFromNode,_fnLog,_fnMap,_fnBindAction,_fnCallbackReg,_fnCallbackFire,_fnLengthOverflow,_fnRenderer,_fnDataSource,_fnRowAttributes*/ + +(/** @lends */function( window, document, undefined ) { + +(function( factory ) { + "use strict"; + + if ( typeof define === 'function' && define.amd ) { + // Define as an AMD module if possible + define( 'datatables', ['jquery'], factory ); + } + else if ( typeof exports === 'object' ) { + // Node/CommonJS + module.exports = factory( require( 'jquery' ) ); + } + else if ( jQuery && !jQuery.fn.dataTable ) { + // Define using browser globals otherwise + // Prevent multiple instantiations if the script is loaded twice + factory( jQuery ); + } +} +(/** @lends */function( $ ) { + "use strict"; + + /** + * DataTables is a plug-in for the jQuery Javascript library. It is a highly + * flexible tool, based upon the foundations of progressive enhancement, + * which will add advanced interaction controls to any HTML table. For a + * full list of features please refer to + * [DataTables.net](href="http://datatables.net). + * + * Note that the `DataTable` object is not a global variable but is aliased + * to `jQuery.fn.DataTable` and `jQuery.fn.dataTable` through which it may + * be accessed. + * + * @class + * @param {object} [init={}] Configuration object for DataTables. Options + * are defined by {@link DataTable.defaults} + * @requires jQuery 1.7+ + * + * @example + * // Basic initialisation + * $(document).ready( function { + * $('#example').dataTable(); + * } ); + * + * @example + * // Initialisation with configuration options - in this case, disable + * // pagination and sorting. + * $(document).ready( function { + * $('#example').dataTable( { + * "paginate": false, + * "sort": false + * } ); + * } ); + */ + var DataTable; + + + /* + * It is useful to have variables which are scoped locally so only the + * DataTables functions can access them and they don't leak into global space. + * At the same time these functions are often useful over multiple files in the + * core and API, so we list, or at least document, all variables which are used + * by DataTables as private variables here. This also ensures that there is no + * clashing of variable names and that they can easily referenced for reuse. + */ + + + // Defined else where + // _selector_run + // _selector_opts + // _selector_first + // _selector_row_indexes + + var _ext; // DataTable.ext + var _Api; // DataTable.Api + var _api_register; // DataTable.Api.register + var _api_registerPlural; // DataTable.Api.registerPlural + + var _re_dic = {}; + var _re_new_lines = /[\r\n]/g; + var _re_html = /<.*?>/g; + var _re_date_start = /^[\w\+\-]/; + var _re_date_end = /[\w\+\-]$/; + + // Escape regular expression special characters + var _re_escape_regex = new RegExp( '(\\' + [ '/', '.', '*', '+', '?', '|', '(', ')', '[', ']', '{', '}', '\\', '$', '^', '-' ].join('|\\') + ')', 'g' ); + + // http://en.wikipedia.org/wiki/Foreign_exchange_market + // - \u20BD - Russian ruble. + // - \u20a9 - South Korean Won + // - \u20BA - Turkish Lira + // - \u20B9 - Indian Rupee + // - R - Brazil (R$) and South Africa + // - fr - Swiss Franc + // - kr - Swedish krona, Norwegian krone and Danish krone + // - \u2009 is thin space and \u202F is narrow no-break space, both used in many + // standards as thousands separators. + var _re_formatted_numeric = /[',$£€¥%\u2009\u202F\u20BD\u20a9\u20BArfk]/gi; + + + var _empty = function ( d ) { + return !d || d === true || d === '-' ? true : false; + }; + + + var _intVal = function ( s ) { + var integer = parseInt( s, 10 ); + return !isNaN(integer) && isFinite(s) ? integer : null; + }; + + // Convert from a formatted number with characters other than `.` as the + // decimal place, to a Javascript number + var _numToDecimal = function ( num, decimalPoint ) { + // Cache created regular expressions for speed as this function is called often + if ( ! _re_dic[ decimalPoint ] ) { + _re_dic[ decimalPoint ] = new RegExp( _fnEscapeRegex( decimalPoint ), 'g' ); + } + return typeof num === 'string' && decimalPoint !== '.' ? + num.replace( /\./g, '' ).replace( _re_dic[ decimalPoint ], '.' ) : + num; + }; + + + var _isNumber = function ( d, decimalPoint, formatted ) { + var strType = typeof d === 'string'; + + // If empty return immediately so there must be a number if it is a + // formatted string (this stops the string "k", or "kr", etc being detected + // as a formatted number for currency + if ( _empty( d ) ) { + return true; + } + + if ( decimalPoint && strType ) { + d = _numToDecimal( d, decimalPoint ); + } + + if ( formatted && strType ) { + d = d.replace( _re_formatted_numeric, '' ); + } + + return !isNaN( parseFloat(d) ) && isFinite( d ); + }; + + + // A string without HTML in it can be considered to be HTML still + var _isHtml = function ( d ) { + return _empty( d ) || typeof d === 'string'; + }; + + + var _htmlNumeric = function ( d, decimalPoint, formatted ) { + if ( _empty( d ) ) { + return true; + } + + var html = _isHtml( d ); + return ! html ? + null : + _isNumber( _stripHtml( d ), decimalPoint, formatted ) ? + true : + null; + }; + + + var _pluck = function ( a, prop, prop2 ) { + var out = []; + var i=0, ien=a.length; + + // Could have the test in the loop for slightly smaller code, but speed + // is essential here + if ( prop2 !== undefined ) { + for ( ; i') + .css( { + position: 'absolute', + top: 0, + left: 0, + height: 1, + width: 1, + overflow: 'hidden' + } ) + .append( + $('
') + .css( { + position: 'absolute', + top: 1, + left: 1, + width: 100, + overflow: 'scroll' + } ) + .append( + $('
') + .css( { + width: '100%', + height: 10 + } ) + ) + ) + .appendTo( 'body' ); + + var test = n.find('.test'); + + // IE6/7 will oversize a width 100% element inside a scrolling element, to + // include the width of the scrollbar, while other browsers ensure the inner + // element is contained without forcing scrolling + browser.bScrollOversize = test[0].offsetWidth === 100; + + // In rtl text layout, some browsers (most, but not all) will place the + // scrollbar on the left, rather than the right. + browser.bScrollbarLeft = Math.round( test.offset().left ) !== 1; + + n.remove(); + } + + + /** + * Array.prototype reduce[Right] method, used for browsers which don't support + * JS 1.6. Done this way to reduce code size, since we iterate either way + * @param {object} settings dataTables settings object + * @memberof DataTable#oApi + */ + function _fnReduce ( that, fn, init, start, end, inc ) + { + var + i = start, + value, + isSet = false; + + if ( init !== undefined ) { + value = init; + isSet = true; + } + + while ( i !== end ) { + if ( ! that.hasOwnProperty(i) ) { + continue; + } + + value = isSet ? + fn( value, that[i], i, that ) : + that[i]; + + isSet = true; + i += inc; + } + + return value; + } + + /** + * Add a column to the list used for the table with default values + * @param {object} oSettings dataTables settings object + * @param {node} nTh The th element for this column + * @memberof DataTable#oApi + */ + function _fnAddColumn( oSettings, nTh ) + { + // Add column to aoColumns array + var oDefaults = DataTable.defaults.column; + var iCol = oSettings.aoColumns.length; + var oCol = $.extend( {}, DataTable.models.oColumn, oDefaults, { + "nTh": nTh ? nTh : document.createElement('th'), + "sTitle": oDefaults.sTitle ? oDefaults.sTitle : nTh ? nTh.innerHTML : '', + "aDataSort": oDefaults.aDataSort ? oDefaults.aDataSort : [iCol], + "mData": oDefaults.mData ? oDefaults.mData : iCol, + idx: iCol + } ); + oSettings.aoColumns.push( oCol ); + + // Add search object for column specific search. Note that the `searchCols[ iCol ]` + // passed into extend can be undefined. This allows the user to give a default + // with only some of the parameters defined, and also not give a default + var searchCols = oSettings.aoPreSearchCols; + searchCols[ iCol ] = $.extend( {}, DataTable.models.oSearch, searchCols[ iCol ] ); + + // Use the default column options function to initialise classes etc + _fnColumnOptions( oSettings, iCol, $(nTh).data() ); + } + + + /** + * Apply options for a column + * @param {object} oSettings dataTables settings object + * @param {int} iCol column index to consider + * @param {object} oOptions object with sType, bVisible and bSearchable etc + * @memberof DataTable#oApi + */ + function _fnColumnOptions( oSettings, iCol, oOptions ) + { + var oCol = oSettings.aoColumns[ iCol ]; + var oClasses = oSettings.oClasses; + var th = $(oCol.nTh); + + // Try to get width information from the DOM. We can't get it from CSS + // as we'd need to parse the CSS stylesheet. `width` option can override + if ( ! oCol.sWidthOrig ) { + // Width attribute + oCol.sWidthOrig = th.attr('width') || null; + + // Style attribute + var t = (th.attr('style') || '').match(/width:\s*(\d+[pxem%]+)/); + if ( t ) { + oCol.sWidthOrig = t[1]; + } + } + + /* User specified column options */ + if ( oOptions !== undefined && oOptions !== null ) + { + // Backwards compatibility + _fnCompatCols( oOptions ); + + // Map camel case parameters to their Hungarian counterparts + _fnCamelToHungarian( DataTable.defaults.column, oOptions ); + + /* Backwards compatibility for mDataProp */ + if ( oOptions.mDataProp !== undefined && !oOptions.mData ) + { + oOptions.mData = oOptions.mDataProp; + } + + if ( oOptions.sType ) + { + oCol._sManualType = oOptions.sType; + } + + // `class` is a reserved word in Javascript, so we need to provide + // the ability to use a valid name for the camel case input + if ( oOptions.className && ! oOptions.sClass ) + { + oOptions.sClass = oOptions.className; + } + + $.extend( oCol, oOptions ); + _fnMap( oCol, oOptions, "sWidth", "sWidthOrig" ); + + /* iDataSort to be applied (backwards compatibility), but aDataSort will take + * priority if defined + */ + if ( oOptions.iDataSort !== undefined ) + { + oCol.aDataSort = [ oOptions.iDataSort ]; + } + _fnMap( oCol, oOptions, "aDataSort" ); + } + + /* Cache the data get and set functions for speed */ + var mDataSrc = oCol.mData; + var mData = _fnGetObjectDataFn( mDataSrc ); + var mRender = oCol.mRender ? _fnGetObjectDataFn( oCol.mRender ) : null; + + var attrTest = function( src ) { + return typeof src === 'string' && src.indexOf('@') !== -1; + }; + oCol._bAttrSrc = $.isPlainObject( mDataSrc ) && ( + attrTest(mDataSrc.sort) || attrTest(mDataSrc.type) || attrTest(mDataSrc.filter) + ); + + oCol.fnGetData = function (rowData, type, meta) { + var innerData = mData( rowData, type, undefined, meta ); + + return mRender && type ? + mRender( innerData, type, rowData, meta ) : + innerData; + }; + oCol.fnSetData = function ( rowData, val, meta ) { + return _fnSetObjectDataFn( mDataSrc )( rowData, val, meta ); + }; + + // Indicate if DataTables should read DOM data as an object or array + // Used in _fnGetRowElements + if ( typeof mDataSrc !== 'number' ) { + oSettings._rowReadObject = true; + } + + /* Feature sorting overrides column specific when off */ + if ( !oSettings.oFeatures.bSort ) + { + oCol.bSortable = false; + th.addClass( oClasses.sSortableNone ); // Have to add class here as order event isn't called + } + + /* Check that the class assignment is correct for sorting */ + var bAsc = $.inArray('asc', oCol.asSorting) !== -1; + var bDesc = $.inArray('desc', oCol.asSorting) !== -1; + if ( !oCol.bSortable || (!bAsc && !bDesc) ) + { + oCol.sSortingClass = oClasses.sSortableNone; + oCol.sSortingClassJUI = ""; + } + else if ( bAsc && !bDesc ) + { + oCol.sSortingClass = oClasses.sSortableAsc; + oCol.sSortingClassJUI = oClasses.sSortJUIAscAllowed; + } + else if ( !bAsc && bDesc ) + { + oCol.sSortingClass = oClasses.sSortableDesc; + oCol.sSortingClassJUI = oClasses.sSortJUIDescAllowed; + } + else + { + oCol.sSortingClass = oClasses.sSortable; + oCol.sSortingClassJUI = oClasses.sSortJUI; + } + } + + + /** + * Adjust the table column widths for new data. Note: you would probably want to + * do a redraw after calling this function! + * @param {object} settings dataTables settings object + * @memberof DataTable#oApi + */ + function _fnAdjustColumnSizing ( settings ) + { + /* Not interested in doing column width calculation if auto-width is disabled */ + if ( settings.oFeatures.bAutoWidth !== false ) + { + var columns = settings.aoColumns; + + _fnCalculateColumnWidths( settings ); + for ( var i=0 , iLen=columns.length ; i