{"instance_id": "AUCOHL_Lighter_pr16", "issue_text": "Minimal fail-to-pass extraction for AUCOHL/Lighter PR 16, \"bug fix in FF\nMapping cells\".\n\nThe reduced snapshot models the sky130 `\\$dffe` mapping cell.  The buggy\nmapping feeds `EN` directly into the clock-gate cell and ignores\n`EN_POLARITY`, so an active-low enable does not capture data.  The patch adds\nthe polarity-adjusted gate enable used by the real PR.  The Verilator\ntestbench drives an active-low enable and checks capture/hold behavior.\n\n## PR Content from GitHub\n\n# Pull Request Summary\n\n**PR Title:** bug fix in FF Mapping cells\n\n**PR Number:** #16\n\n**Status:** Merged (Sep 28, 2023)\n\n---\n\n## PR Description\n\n**Signed by:** Youssef Kandil\n\n**Contributor:** @dineshannayya\n\n**Context:**\nThe clock gating functionality of $SDFFE cells was causing validation failures. The issue stemmed from forced positive signaling of clock and enable signals.\n\n**Changes:**\nThe fix implements polarity checking for both \"clock\" and \"enable\" signals, adjusting their signs accordingly. This resolves issue #2.\n\n**Mentions:** @dineshannayya, @shalan\n\n---\n\n## Linked Issue\n\n**Title:** SDFFE mapping crashes validation\n\nThis PR successfully merged after closing the referenced issue.\n\n---\n\n## Participants\n\n- @kanndil (merged the PR)\n- @dineshannayya (contributor)\n\nNo formal reviews were recorded, and no labels, assignees, or milestone were set for this pull request.\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/AUCOHL_Lighter_pr16", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/AUCOHL_Lighter_pr16.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/AUCOHL_Lighter_pr16", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/AUCOHL_Lighter_pr16"}
{"instance_id": "AsFigo_pyslint_pr138", "issue_text": "# SVA: expect construct usage - compatibility issue\n\n- Source URL: https://github.com/AsFigo/pyslint/issues/136\n\nhttps://verificationacademy.com/forums/systemverilog/expect-assertion#answer-117075\r\n\r\n```verilog\r\nmodule test;\r\n \r\n  bit req1,req2;\r\n  bit clk;\r\n \r\n  always #5 clk=~clk;\r\n \r\n \r\n  initial begin\r\n  #100;\r\n    expect(@(posedge clk) req1 ##2 req2) else $error (\"expect failure\");\r\n    $display(\"DONE\");\r\nend\r\n \r\n  initial\r\n    begin\r\n      repeat(10)\r\n        begin\r\n            req1=$urandom;\r\n            req2=$urandom;\r\n            #12;\r\n        end\r\n      $finish;\r\n    end\r\nendmodule\r\n```\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/AsFigo_pyslint_pr138", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/AsFigo_pyslint_pr138.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/AsFigo_pyslint_pr138", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/AsFigo_pyslint_pr138"}
{"instance_id": "AsFigo_pyslint_pr140", "issue_text": "# SV: post/pre randomize return value check - COMPAT issue\n\n- Source URL: https://github.com/AsFigo/pyslint/issues/139\n\n```verilog\nclass gen_c;\n  rand bit b;\n\n  function pre_randomize();\n  endfunction\n\n  function post_randomize();\n  endfunction\nendclass : gen_c\n```\n\nAbove code works fine in one but not in all others.\n\n## PR Content from GitHub\n\n# Pull Request #140 Summary\n\n**PR Title:** Added rule to address issue 139\n\n**PR Description Body:**\nThe page does not display a full description body beyond the title. The only substantive comment is: \"Fixes #139\"\n\n**PR Comments:**\n- **Author: svenka3** - \"Fixes #139\"\n\n**Linked Issue #139:**\n**Title:** \"SV: post/pre randomize return value check - COMPAT issue\"\n\n**Issue Body:**\nNot provided in the extracted content.\n\n**Status:** This PR was merged by svenka3 on November 29, 2023, into the main branch from the i139 branch.\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/AsFigo_pyslint_pr140", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/AsFigo_pyslint_pr140.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/AsFigo_pyslint_pr140", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/AsFigo_pyslint_pr140"}
{"instance_id": "AsFigo_pyslint_pr149", "issue_text": "# DPI - checks needed inside interface context\n\n- Source URL: https://github.com/AsFigo/pyslint/issues/147\n\nDPI checks to be added for interface context.\n\n```verilog\ninterface af_sv_if;\n  import \"DPI\" function int c_sum();\nendinterface : af_sv_if\n```\n\n## PR Content from GitHub\n\n# Pull Request Summary\n\n**PR Title:** DPI enhancements\n\n**PR Number:** #149\n\n**Status:** Merged\n\n**Author:** svenka3\n\n**Merge Date:** December 1, 2023\n\n---\n\n## PR Description\n\nThe pull request description is minimal. The author only states: \"Fixes #147 and #148\"\n\n---\n\n## Commits\n\nTwo commits were included:\n1. \"Fixes Issue #147\" (commit f340d60)\n2. \"Support for DPI inside PKG is added\" (commit e15120a)\n\n---\n\n## Comments\n\n**svenka3** commented on December 1, 2023:\n\"Fixes #147 and #148\"\n\n---\n\n## Linked Issues\n\nThis PR references two issues:\n- **Issue #147:** \"DPI - checks needed inside interface context\"\n- **Issue #148:** \"DPI - checks need to be performed for package scoped DPI methods\"\n\nThe pull request successfully closed Issue #147. Issue #148 was also referenced and addressed through the implementation of DPI (Direct Programming Interface) support within package scoping contexts.\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/AsFigo_pyslint_pr149", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/AsFigo_pyslint_pr149.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/AsFigo_pyslint_pr149", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/AsFigo_pyslint_pr149"}
{"instance_id": "AsFigo_pyslint_pr164", "issue_text": "# Avoid begin..end around timing control\n\n- Source URL: https://github.com/AsFigo/pyslint/issues/161\n\nhttps://verificationacademy.com/forums/systemverilog/memory-read-showing-xxx-values-apb-verification#reply-117165\r\n\r\n```verilog\r\ntask Write();\r\nbegin\r\n   @(negedge pclk) begin \r\n\t \tpsel = 1;\r\n       \tpenb = 0;\r\n     for (int i = 0; i < 64; i=i+1) begin\r\n    @(negedge pclk) begin \r\n        penb = 1 ;\r\n\t \tpwrite = 1;\r\n\t\tpaddr = i;\r\n\t\tpwdata = i;\r\n\t$display(\"PADDR %h, PWDATA %h  \",paddr,pwdata);\r\n\t end\r\nend\r\n   end\r\n end\r\nendtask\r\n \r\n```\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/AsFigo_pyslint_pr164", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/AsFigo_pyslint_pr164.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/AsFigo_pyslint_pr164", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/AsFigo_pyslint_pr164"}
{"instance_id": "AsFigo_pyslint_pr166", "issue_text": "# VLT: no clocking blocks in interface\n\n- Source URL: https://github.com/AsFigo/pyslint/issues/165\n\nVerilator does not support clocking block based driving (as of today). Add a rule to check.\n\n## PR Content from GitHub\n\n# PR Summary\n\n**PR Title:** Added rule for CB check for Verilator issue 165\n\n**PR Number:** #166\n\n**Status:** Merged\n\n**Author:** svenka3\n\n**Merge Date:** December 6, 2023\n\n---\n\n## PR Description Body\n\nThe PR description was not fully visible in the provided content. Only a reference appears:\n\n**Comment by svenka3:**\n\"Fixes #165\"\n\n---\n\n## Linked Issue\n\n**Issue #165 Title:** VLT: no clocking blocks in interface\n\nThe issue details were not included in the available content, but the PR was designed to address this specific Verilator-related constraint.\n\n---\n\n## Additional Context\n\nThe pull request contained 1 commit (ea905ff) that was merged into the main branch. The change implements a rule to check for clocking blocks within interfaces, addressing a Verilator linting requirement.\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/AsFigo_pyslint_pr166", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/AsFigo_pyslint_pr166.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/AsFigo_pyslint_pr166", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/AsFigo_pyslint_pr166"}
{"instance_id": "AsFigo_pyslint_pr167", "issue_text": "# Avoid begin..end around task/function\n\n- Source URL: https://github.com/AsFigo/pyslint/issues/160\n\n```verilog\n\ntask Write();\nbegin\n\n\t$display(\"PADDR %h, PWDATA %h  \",paddr,pwdata);\n\nend\n\nendtask\n```\n\n## PR Content from GitHub\n\n# GitHub Pull Request Summary\n\n**PR Title:** Support for issue 160 added\n\n**PR Number:** #167\n\n**Author:** svenka3\n\n**Status:** Merged (Dec 6, 2023)\n\n---\n\n## PR Description Body\n\nThe PR description body is not fully visible in the provided content. Only a comment referencing the issue is shown.\n\n---\n\n## PR Comments\n\n**@svenka3** (Dec 6, 2023):\n\"Fixes #160\"\n\n---\n\n## Linked Issue\n\n**Issue #160 Title:** \"Avoid begin..end around task/function\"\n\n**Issue Body:** Not provided in the source material.\n\n---\n\n## Additional Details\n\n- **Commits:** 1 commit (18608ad)\n- **Merged into:** main branch\n- **Source branch:** i160\n- **Reviews:** None\n- **Assignees:** None\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/AsFigo_pyslint_pr167", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/AsFigo_pyslint_pr167.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/AsFigo_pyslint_pr167", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/AsFigo_pyslint_pr167"}
{"instance_id": "AsFigo_pyslint_pr169", "issue_text": "# COMPAT rule - function with ref arg shall be automatic\n\n- Source URL: https://github.com/AsFigo/pyslint/issues/159\n\nAdd a new rule to check that functions with ref arguments are declared automatic.\r\n\r\n```verilog\r\nmodule x;\r\n  integer x1;\r\n  function  func (ref integer a[]);\r\n    $display (\"%p\", a);\r\n  endfunction\r\n \r\n  initial begin\r\n    integer a [];\r\n    a = {1,2,3,4,5};\r\n    x1=func(a);\r\n  end\r\nendmodule \r\n```\r\n\r\n```log\r\n reference argument is illegal inside static task-function declaration.\r\n```\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/AsFigo_pyslint_pr169", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/AsFigo_pyslint_pr169.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/AsFigo_pyslint_pr169", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/AsFigo_pyslint_pr169"}
{"instance_id": "AsFigo_pyslint_pr175", "issue_text": "# COMPAT SVA missing ;\n\n- Source URL: https://github.com/AsFigo/pyslint/issues/174\n\n```verilog\nmodule m;\n  bit clk, a, b;\n\n  property p_ex;\n    @(posedge clk) a |=> b\n  endproperty : p_ex\n\nendmodule : m\n```\n\n## PR Content from GitHub\n\n# GitHub Pull Request Summary\n\n**PR Title:** Added rule 174 - COMPAT\n\n**PR Number:** #175\n\n**Status:** Merged\n\n**Author:** svenka3\n\n**Merge Date:** December 8, 2023\n\n---\n\n## PR Description\nThe PR description body is not explicitly shown in the provided content beyond the title.\n\n## Comments\n\n**svenka3** commented:\n> \"Fixes #174\"\n\nThis brief comment references the linked issue.\n\n---\n\n## Linked Issue\n\n**Issue #174 Title:** \"COMPAT SVA missing ;\"\n\nThe issue title indicates this PR addresses a missing semicolon issue related to COMPAT SVA functionality.\n\n---\n\n## Additional Details\n\n- **Commits:** 1 commit merged (09108a8)\n- **Branch:** Merged from `i174` into `main`\n- **Reviewers:** None listed\n- **Assignees:** None listed\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/AsFigo_pyslint_pr175", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/AsFigo_pyslint_pr175.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/AsFigo_pyslint_pr175", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/AsFigo_pyslint_pr175"}
{"instance_id": "AsFigo_pyslint_pr180", "issue_text": "# COMPAT - class parameter default value missing check\n\n- Source URL: https://github.com/AsFigo/pyslint/issues/178\n\n```verilog\n\nclass abstract_ifc #(int cwidth=1, int awidth=2, int dwidth);\n\nendclass\n\n```\n\nLOG\n```log\nOmitting the assignment to constant_param_expression in a param_assignment in a parameter_port_list currently is not supported.\n```\n\n## PR Content from GitHub\n\n# GitHub Pull Request Summary\n\n**PR Title:** Added new rule for #178\n\n**PR Number:** #180\n\n**Status:** Merged\n\n**Author:** svenka3\n\n**Merge Date:** December 29, 2023\n\n---\n\n## PR Description\nThe pull request body is not fully visible in the provided content, but the commit message indicates: \"Added new rule for #178\"\n\n---\n\n## Comments\n\n**svenka3** (Dec 29, 2023):\n\"Fixes #178\"\n\n---\n\n## Linked Issue\n\n**Issue #178 Title:** COMPAT - class parameter default value missing check\n\n**Issue Description:** Not provided in the extracted content.\n\n---\n\n## Additional Context\n\n- **Commits:** 1 commit included\n- **Commit Hash:** ee7ed6e\n- **Branch:** Merged from `i178` into `main`\n- **Merge Commit:** c55f299\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/AsFigo_pyslint_pr180", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/AsFigo_pyslint_pr180.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/AsFigo_pyslint_pr180", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/AsFigo_pyslint_pr180"}
{"instance_id": "AsFigo_pyslint_pr185", "issue_text": "# CNST - add new rule\n\n- Source URL: https://github.com/AsFigo/pyslint/issues/184\n\n```verilog\r\nclass bli_c;\r\n  bit foo_sel;\r\n  \r\n  rand int foo;\r\n  \r\n  constraint cst_1 {\r\n    foo == (foo_sel) ? 5 :6;\r\n  }\r\n  \r\n  function void post_randomize();\r\n    $display (\"%p\", this);\r\n  endfunction\r\nendclass\r\n\r\nmodule m;\r\n  bli_c u_bli_c_0;\r\n  \r\n  initial begin\r\n    u_bli_c_0 = new();\r\n    repeat (5) u_bli_c_0.randomize(); \r\n    #10;\r\n    $finish (2);\r\n  end\r\nendmodule\r\n```\r\nhttps://www.linkedin.com/posts/avidan-efody_appleabrdv-servingthenextbug-systemverilog-activity-7152673318020562944-tI2M?utm_source=share&utm_medium=member_desktop\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/AsFigo_pyslint_pr185", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/AsFigo_pyslint_pr185.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/AsFigo_pyslint_pr185", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/AsFigo_pyslint_pr185"}
{"instance_id": "AsFigo_pyslint_pr56", "issue_text": "# REUSE_NO_TDEF_IN_MOD - check for typedef inside module\n\n- Source URL: https://github.com/AsFigo/pyslint/issues/55\n\n**Is your feature request related to a new rule? Please describe.**\nAny typedef inside module scope would lead to reuse issues. Example:\n\nhttps://www.linkedin.com/posts/petermonsson_verification-systemverilog-verilog-activity-7114149452868632576-EbPn\n\n**Describe the solution you'd like**\nAdd a check to detect such declarations and suggest using package instead.\n\n## PR Content from GitHub\n\n# Pull Request #56 Summary\n\n**PR Title:** \"Added new rule to address issue #55 and a test\"\n\n**PR Description Body:** Not provided in the page content.\n\n**PR Comments:**\n\n- **@svenka3** (Collaborator): \"Fixes #55\"\n\n**Linked Issue:**\n\n- **Issue #55 Title:** \"REUSE_NO_TDEF_IN_MOD - check for typedef inside module\"\n- **Issue #55 Body:** Not provided in the page content.\n\n**Additional Details:**\n- Status: Merged on October 1, 2023\n- Merged by: @svenka3\n- Source branch: rtl_tdep_oct1\n- Target branch: main\n- Commits: 1 commit (1c588dd)\n- The branch was deleted on December 2, 2023\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/AsFigo_pyslint_pr56", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/AsFigo_pyslint_pr56.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/AsFigo_pyslint_pr56", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/AsFigo_pyslint_pr56"}
{"instance_id": "FPGA-MAFIA_fpga_mafia_pr428", "issue_text": "# change csr names and design to fit the spec\n\n- Source URL: https://github.com/FPGA-MAFIA/fpga_mafia/issues/421\n\nmake changes both to core_rrv and rv32i_ref\n\nPR Title: add cycle and instret User mode csr's\nPR Number: #428\nStatus: Merged\nAuthor: roman012285\nMerge Details: Merged on January 14, 2024, from branch core_rrv into main\n\nDescription:\nNo description was provided by the contributor.\n\nComments:\nroman012285 (Collaborator) - January 14, 2024:\nNo substantive comment; the PR was opened without explanation.\n\nLinked Issue:\nIssue #421: \"change csr names and design to fit the spec\"\nThis pull request was flagged as potentially closing this issue.\n\nMetadata:\n- Commits: 2 commits\n- Milestone: MAFIA 0.1 (later modified to include MAFIA 1.0)\n- Participants: roman012285, amichai-bd\n- Reviews: None documented\n- Assignees: None\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/FPGA-MAFIA_fpga_mafia_pr428", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/FPGA-MAFIA_fpga_mafia_pr428.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/FPGA-MAFIA_fpga_mafia_pr428", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/FPGA-MAFIA_fpga_mafia_pr428"}
{"instance_id": "FPGA-MAFIA_fpga_mafia_pr429", "issue_text": "# sc_core - screen is broken, and there is no reference model in TB\n\n- Source URL: https://github.com/FPGA-MAFIA/fpga_mafia/issues/423\n\n2 things to fix:\n1) add a reference model and EOT check to make sure IP is running correctly\n2) Make sure the display works. (have a dedicated memory region for VGA space)\n\nPR Title: integrate ref model to sc_core_tb and regress level 0\nStatus: Merged on January 14, 2024\n\nDescription:\nRoman012285 implemented the following changes:\n1. Added a reference model to sc_core_tb\n2. Introduced test cases including bubblesort\n3. Integrated rv32i_level0 into sc_core (modifying the mafia_sanity SC_CORE configuration)\n4. Did not yet work on VGA functionality\n\nThe author noted that verification requires adding \"+4\" to an addition operation; \"+1\" causes timeouts.\n\nKey Discussion:\nRoman asked about releasing sc_core's data memory at line 124 in sc_core.tb.sv.\n\nAmichai-bd responded: \"The use of 'Force' is to force the priority to the assignment in the TB over the RTL... I think that in the case of the '$readmemh' its getting priority without the use of 'force'.\"\n\nHe explained that using \"$readmemh\" for both DMem and NextDMem ensures data memory initialization without explicit release statements.\n\nMetadata:\n- Author: roman012285\n- Reviewer/Approver: amichai-bd\n- Assignee: roman012285\n- Labels: RV32I_REF, SC_CORE\n- Milestone: MAFIA 0.1\n- Linked Issue: #423 (sc_core screen broken, no reference model in TB)\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/FPGA-MAFIA_fpga_mafia_pr429", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/FPGA-MAFIA_fpga_mafia_pr429.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/FPGA-MAFIA_fpga_mafia_pr429", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/FPGA-MAFIA_fpga_mafia_pr429"}
{"instance_id": "FPGA-MAFIA_fpga_mafia_pr449", "issue_text": "# Remove the Parameter override from the build.\n\n- Source URL: https://github.com/FPGA-MAFIA/fpga_mafia/issues/441\n\nhttps://github.com/FPGA-MAFIA/fpga_mafia/blob/931deaa13c92a1fe5d29dee95ba23c76531a68f2/build.py#L241C16-L241C16\r\n\r\nI think there is room for creating a script that can override the parameter value by name - both in source (AKA rtl) and in verif\r\n\r\nThe way it should work is as following:\r\nIn the cfg file add a field that is called \"parameter_override\"\r\n``` json\r\n{\r\n    \"I_MEM_OFFSET\": 0,\r\n    \"I_MEM_LENGTH\": 65536,\r\n    \"D_MEM_OFFSET\": 65536,\r\n    \"D_MEM_LENGTH\": 61440,\r\n    \"crt0_file\"   : \"crt0_mini_rv32e.S\",\r\n    \"rv32_gcc\"    : \"rv32e -mabi=ilp32e\",\r\n    \"name\"        : \"rv32e\",\r\n    \"rtl_parameter_override\"  : {\r\n        \"RF_NUM_MSB\"  : 31,\r\n        \"RF_NUM_LSB\"  : 0,\r\n        \"OTHER_EXAMPLE\" : 31\r\n    },\r\n    \"verif_pkg_parameter_override\"  : {\r\n        \"TIMEOUT\" : 1000000,\r\n        \"OTHER_EXAMPLE\" : 65403540\r\n    }\r\n}\r\n```\r\n\r\nThen in the \"build\" call a new script that you need to create that accepts the list of parameters you need to change.\r\nMake sure use correct regular expression so it overrides only the \"parameter <name> = value\" instances\r\n\r\nThe scipt will search, find and replace the values that are mentioned in the cfg json file.\r\nThe scipt will also log the info by printing to the screen what he found, where, and what he has changed.\r\n\r\nDuring the find replace - add a comment in the line of parameter\r\nExample:\r\n```systemverilog\r\nparameter EXAMPLE = 15; // Note: This line was inserted using parameter override script\r\n```\r\n\r\n*Note:*\r\nThis Parameter change will actually change the value of the RTL!! \r\nThis is fine - as long as we test correctly the different parameter variations in the workflow.\r\n\r\nThis is not the best solution because this may cause many redundant commit changes in the git. (the Change in Value is tracked in the git add/commit flow)\r\nBut i think for us - this is a good solution.\r\n(We are not really expected to manually change the RTL parameters very often. but we want to make sure they are correct)\r\n\r\n\r\nI will note that the alternative is override the parameter value in the command line (simular to what i just added) but i have some trouble with overriding specific values in the param_pkg.\r\nAnother good alternative is to pass the parameter in the instance of each module -> but this also can get annoying. \r\nI think will need to this to the most common parameter overrides so we can simply intergrade different version of the same module in the same system. (similar to what we did with the RF_NUM_MSB which is getting override in the module instance)\r\n\r\nI think you can do this fairly simple\r\nLet me know if you have any questions\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/FPGA-MAFIA_fpga_mafia_pr449", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/FPGA-MAFIA_fpga_mafia_pr449.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/FPGA-MAFIA_fpga_mafia_pr449", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/FPGA-MAFIA_fpga_mafia_pr449"}
{"instance_id": "FPGA-MAFIA_fpga_mafia_pr451", "issue_text": "# Remove the Parameter override from the build.\n\n- Source URL: https://github.com/FPGA-MAFIA/fpga_mafia/issues/441\n\nhttps://github.com/FPGA-MAFIA/fpga_mafia/blob/931deaa13c92a1fe5d29dee95ba23c76531a68f2/build.py#L241C16-L241C16\r\n\r\nI think there is room for creating a script that can override the parameter value by name - both in source (AKA rtl) and in verif\r\n\r\nThe way it should work is as following:\r\nIn the cfg file add a field that is called \"parameter_override\"\r\n``` json\r\n{\r\n    \"I_MEM_OFFSET\": 0,\r\n    \"I_MEM_LENGTH\": 65536,\r\n    \"D_MEM_OFFSET\": 65536,\r\n    \"D_MEM_LENGTH\": 61440,\r\n    \"crt0_file\"   : \"crt0_mini_rv32e.S\",\r\n    \"rv32_gcc\"    : \"rv32e -mabi=ilp32e\",\r\n    \"name\"        : \"rv32e\",\r\n    \"rtl_parameter_override\"  : {\r\n        \"RF_NUM_MSB\"  : 31,\r\n        \"RF_NUM_LSB\"  : 0,\r\n        \"OTHER_EXAMPLE\" : 31\r\n    },\r\n    \"verif_pkg_parameter_override\"  : {\r\n        \"TIMEOUT\" : 1000000,\r\n        \"OTHER_EXAMPLE\" : 65403540\r\n    }\r\n}\r\n```\r\n\r\nThen in the \"build\" call a new script that you need to create that accepts the list of parameters you need to change.\r\nMake sure use correct regular expression so it overrides only the \"parameter <name> = value\" instances\r\n\r\nThe scipt will search, find and replace the values that are mentioned in the cfg json file.\r\nThe scipt will also log the info by printing to the screen what he found, where, and what he has changed.\r\n\r\nDuring the find replace - add a comment in the line of parameter\r\nExample:\r\n```systemverilog\r\nparameter EXAMPLE = 15; // Note: This line was inserted using parameter override script\r\n```\r\n\r\n*Note:*\r\nThis Parameter change will actually change the value of the RTL!! \r\nThis is fine - as long as we test correctly the different parameter variations in the workflow.\r\n\r\nThis is not the best solution because this may cause many redundant commit changes in the git. (the Change in Value is tracked in the git add/commit flow)\r\nBut i think for us - this is a good solution.\r\n(We are not really expected to manually change the RTL parameters very often. but we want to make sure they are correct)\r\n\r\n\r\nI will note that the alternative is override the parameter value in the command line (simular to what i just added) but i have some trouble with overriding specific values in the param_pkg.\r\nAnother good alternative is to pass the parameter in the instance of each module -> but this also can get annoying. \r\nI think will need to this to the most common parameter overrides so we can simply intergrade different version of the same module in the same system. (similar to what we did with the RF_NUM_MSB which is getting override in the module instance)\r\n\r\nI think you can do this fairly simple\r\nLet me know if you have any questions\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/FPGA-MAFIA_fpga_mafia_pr451", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/FPGA-MAFIA_fpga_mafia_pr451.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/FPGA-MAFIA_fpga_mafia_pr451", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/FPGA-MAFIA_fpga_mafia_pr451"}
{"instance_id": "FPGA-MAFIA_fpga_mafia_pr452", "issue_text": "# change the directory structure in the verification\n\n- Source URL: https://github.com/FPGA-MAFIA/fpga_mafia/issues/442\n\nThe directory structure in the verification is a little strange and i think it can be improved.\n\nThe idea is that we will have the same main directory as the RTL.\nMeaning the content of the \"verif/cache\" should be moved into mem_ss\nand the content of \"verif/router\" should be moved into fabric.\n\nThen the list.f file should be merged into a single file - but keep many different \"_tb\" files that can be used using the \"-top\" option in the compilation command.\n\nThis change will need carful merging in the list.f files, in the include and functions, and the workflow sanity command ext\n\nPR Title: Move the verif files around to have less DUT and use the -top flag to…\nPR Number: #452\nStatus: Merged\nAuthor: amichai-bd\nReviewer/Merger: roman012285\nDate Merged: January 19, 2024\n\nDescription:\nThe PR reorganizes verification files to reduce Device Under Test (DUT) instances and implements the -top flag for proper subIP execution, addressing issue #442 regarding directory structure changes in verification.\n\nKey Comments:\namichai-bd (Jan 20-21): Explained that a pycache file was inadvertently committed during the reorganization. This Python-generated file was created when importing local scripts in mem_ss_pp.py. To prevent future generation, the contributor added sys.dont_write_bytecode = True before the import statement and subsequently suggested consolidating the separate ref_orderer.py file directly into the main script.\n\nroman012285: Acknowledged understanding the rationale behind the solution and noted some errors in gui_build.py that were outside the scope of immediate fixes.\n\nCommits:\nTwo commits were merged:\n1. Primary restructuring commit (b72c071)\n2. Flow name fix commit (d940f1e)\n\nThe branch was subsequently deleted on March 1, 2024.\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/FPGA-MAFIA_fpga_mafia_pr452", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/FPGA-MAFIA_fpga_mafia_pr452.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/FPGA-MAFIA_fpga_mafia_pr452", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/FPGA-MAFIA_fpga_mafia_pr452"}
{"instance_id": "FPGA-MAFIA_fpga_mafia_pr465", "issue_text": "# add HW interrupt support to core_rrv\n\n- Source URL: https://github.com/FPGA-MAFIA/fpga_mafia/issues/437\n\nThe interrupt will start when one of the counters will reach a predefined value.\n\nPR Title: fix issues we talked about csr\n\nDescription:\nThe contributor implemented an initial version that executes instructions once the timer interrupt is triggered. This approach ensures interrupts are processed when NOPs are absent, preventing loops. The implementation was tested with multiple timers using the comparison method for valid instructions. All relevant CSR updates are handled in the CSR module rather than software.\n\nCommits (4):\n1. Remove CSR check in ctrl and pass to CSR unit\n2. Merge branch 'main' into core_rrv\n3. Fix merge conflict issues\n4. Fix timer interrupt handler\n\nComments:\nroman012285 (Collaborator): \"I chose to implement our initial version and execute the instruction once the timer interrupt is triggered... All the updated of relevant csrs are handled in CSR module and not in the software.\"\n\namichai-bd (Reviewer/Merger): \"Great job!\"\n\nLinked Issue: #437 - \"add HW interrupt support to core_rrv\"\n\nStatus: Merged by amichai-bd on February 2, 2024\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/FPGA-MAFIA_fpga_mafia_pr465", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/FPGA-MAFIA_fpga_mafia_pr465.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/FPGA-MAFIA_fpga_mafia_pr465", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/FPGA-MAFIA_fpga_mafia_pr465"}
{"instance_id": "FPGA-MAFIA_fpga_mafia_pr473", "issue_text": "# Disable correctly the interrupts & restore correctly the enable bits\n\n- Source URL: https://github.com/FPGA-MAFIA/fpga_mafia/issues/471\n\n![image](https://github.com/FPGA-MAFIA/fpga_mafia/assets/81047407/f3c2ce04-1feb-4806-879b-0bba8f41c702)\r\nThis is wrong - after mret we dont need to enable the \"csr_mie\" this way..  we need to restore the mstatus correctly!\r\n\r\n![image](https://github.com/FPGA-MAFIA/fpga_mafia/assets/81047407/b85930f0-e91d-4926-afbb-58b464701042)\r\nThis is also wrong - don't need to change the csr_mie - only the disable the mstatus\r\n\r\nPlease read carefully again:\r\n## Timer Interrupt Handling\r\nWhen a timer interrupt is taken, you correctly set the mcause with the MSB set to '1' indicating an interrupt, and the cause code for a timer interrupt (0x7). \r\nHowever, your handling of mie (Machine Interrupt Enable) and mstatus might not accurately reflect the typical behavior expected upon an interrupt.\r\nDisabling interrupts by setting mie might not be necessary here; instead, interrupts are usually disabled by clearing the MIE bit in the mstatus register, not by directly manipulating mie.\r\nThe update to mstatus seems to intend to manipulate interrupt enable bits directly. Typically, upon taking an interrupt, the hardware would clear the MIE bit in mstatus, saving the previous state in MPIE, and update MPP if needed. Your comment regarding setting mstatus[7] equal to mstatus[3] seems to misunderstand the mstatus register's bit fields.\r\n## Return from Interrupt (MRET)\r\nUpon executing MRET, the typical behavior is to restore the previous interrupt enable state by copying MPIE to MIE in mstatus, not by directly setting mie. Your code seems to directly enable interrupts by setting mie and mstatus which might not correctly restore the previous state.\r\nThe mstatus update to 0x8 directly seems incorrect. The MRET instruction itself should handle the restoration of mstatus fields, specifically MIE and MPIE, based on their pre-interrupt values.\r\nClearing mip directly on MRET might not be necessary or correct, as mip reflects pending interrupts and is typically managed by acknowledging the interrupt source (like writing to a timer register to clear the timer interrupt).\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/FPGA-MAFIA_fpga_mafia_pr473", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/FPGA-MAFIA_fpga_mafia_pr473.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/FPGA-MAFIA_fpga_mafia_pr473", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/FPGA-MAFIA_fpga_mafia_pr473"}
{"instance_id": "FPGA-MAFIA_fpga_mafia_pr479", "issue_text": "# core_rrv - create a dedicated test for the timer interrupt during a illegal instruction trap\n\n- Source URL: https://github.com/FPGA-MAFIA/fpga_mafia/issues/477\n\nCreate a test that has both \"illegal instruction trap\" and \"timer interrupts\".\n\nI am hoping to see hit this case:\n\n- illegal instruction trap exception handler is in progress (MIE set to 0 by HW)\n- Timer interrupt time condition met -> but MIE is 0, so no exception is taken yet\n- illegal instruction handler return with MRET (MIE back to 1)\n- Timer interrupt condition is still set so the timer interrupt exception handler takes place\n- We return from the timer interrupts and continue execution\n\nPR Title: add test timer exception after illegal instruction trap + debug csr's\nStatus: Merged on Feb 14, 2024\n\nDescription: No description was provided in the pull request.\n\nCommits (7 total):\n1. \"add clear and set csr macros\"\n2. \"add debud csrs. dpc, dcsr, dscratch0, dscratch1\"\n3. \"add test for checking alive illegal before timer interrupt\"\n4. \"disable mie to avoid timer exception while printing. may cause misses\"\n5. \"Merge branch 'main' into core_rrv\"\n6. \"modify regrees file\"\n7. \"add debug csrs, custom_mtime, custom_mtimecmp and custom_lfsr\"\n\nReview Comments:\namichai-bd (reviewer/approver):\n- Regarding cycle/instret counter synchronization: \"The plan is to artificially match the ref model performance IPC with the DUT performance so the 2 tests can be compared correctly.\"\n- On LFSR updates: Expected hardware LFSR updates \"only when there is a read/write from the LFSR CSR\" by moving logic into read/write cases\n\nroman012285 (author) response to LFSR comment: Indicated the fix hadn't been implemented yet (\"עוד לא הגעתי לזה\")\n\nLinked Issue:\nIssue #477: \"create a dedicated test for the timer interrupt during a illegal instruction trap\"\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/FPGA-MAFIA_fpga_mafia_pr479", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/FPGA-MAFIA_fpga_mafia_pr479.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/FPGA-MAFIA_fpga_mafia_pr479", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/FPGA-MAFIA_fpga_mafia_pr479"}
{"instance_id": "FPGA-MAFIA_fpga_mafia_pr495", "issue_text": "# rvc_sample_csr - this is not a name we should use for the specific csr read of 0xb00 and 0xb02\n\n- Source URL: https://github.com/FPGA-MAFIA/fpga_mafia/issues/489\n\nAcording to the spec - done we have a \"correct\" name for the mcycle and instret?\nPlease revisit this and fix the name, the way we use it, where we use it, etc..\n![image](https://github.com/FPGA-MAFIA/fpga_mafia/assets/81047407/36f4c59b-f1e9-4a53-904f-caf5ba0009d5)\n\nPR Title: refactor lfsr read condition and address of time and instret csr's\n\nDescription: No description provided.\n\nCommits:\n1. \"refactor CSR address from machine to user mode\"\n2. \"refactor - lfsr read condition\"\n3. Merge branch 'main' into core_rrv\n\nLinked Issue: #489 - \"rvc_sample_csr - this is not a name we should use for the specific csr read of 0xb00 and 0xb02\"\n\nComments:\namichai-bd (Reviewer): \"Still this function name makes no sense to me.. 'rvc_sample_csr' -> what is this function actually do? I feel like I'm missing something here\"\n\nroman012285 (Author): \"we read the clycle and instret in alive_ipc test and calculates ipc\"\n\nStatus: Merged by roman012285 on Feb 20, 2024\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/FPGA-MAFIA_fpga_mafia_pr495", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/FPGA-MAFIA_fpga_mafia_pr495.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/FPGA-MAFIA_fpga_mafia_pr495", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/FPGA-MAFIA_fpga_mafia_pr495"}
{"instance_id": "FPGA-MAFIA_fpga_mafia_pr499", "issue_text": "# remove nop from mini_core rv32e/i configuration fails to pass sanity test\n\n- Source URL: https://github.com/FPGA-MAFIA/fpga_mafia/issues/497\n\n`python build.py -dut 'mini_core' -regress rv32i_level0 -app -hw -sim -keep_going`\n./build.py -cfg mini_rv32i -dut mini_core -test basic -app -hw -sim -clean\n\nwhen nothing written after `ebreak` it causes that fail\n\nPR Title: fix ref_model didnt stop after ebreak\nStatus: Merged\nAuthor: roman012285\nBranch: core_rrv → main (merged Feb 21, 2024)\n\nDescription:\nNo description was provided for this pull request.\n\nCommits:\n1. \"fix ref_model didnt stopped after ebreak\" (2abdd32)\n2. \"remove nop\" (8e0c07f)\n\nComments:\nroman012285 changed the PR title from \"dix ref_model didnt stop after ebreak\" to the corrected version.\n\nLinked Issue:\n#497: \"remove nop from mini_core rv32e/i configuration fails to pass sanity test\"\n\nThis PR appears to address a bug where a reference model wasn't properly terminating after an \"ebreak\" instruction, with changes involving the removal of a no-operation instruction from a RISC-V core configuration.\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/FPGA-MAFIA_fpga_mafia_pr499", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/FPGA-MAFIA_fpga_mafia_pr499.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/FPGA-MAFIA_fpga_mafia_pr499", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/FPGA-MAFIA_fpga_mafia_pr499"}
{"instance_id": "FPGA-MAFIA_fpga_mafia_pr548", "issue_text": "# Add a-j to print function in vga lib\n\n- Source URL: https://github.com/FPGA-MAFIA/fpga_mafia/issues/531\n\nPR Title: charcters a-k and more\nStatus: Merged\nAuthor: jacobavitan837\nMerge Details: Merged 2 commits from jacob_branch into main on March 11, 2024 by roman012285\n\nDescription:\nThe PR extends the graphic VGA library with additional character support (letters a through k and beyond).\n\nKey Comments:\njacobavitan837's Request: \"please review and approve\"\n\nNoamRahat's Review Feedback:\nSuggested adhering to standard coding conventions by writing preprocessor directives in uppercase, noting: \"I think it would be a good idea to stick to common convention...\"\n\nroman012285's Response:\nAgreed with the styling feedback, recommending consistency with existing patterns where \"every thing is written in big letters except the letter itself\" (e.g., A_TOP format).\n\nNoamRahat's Clarification:\nProposed examples like changing Slash_TOP to SLASH_TOP and a_TOP to SMALL_A_TOP for consistency.\n\nLinked Issues:\n- Issue #531: \"Add a-j to print function in vga lib\"\n- Issue #545: \"add the rest characters to print function in vga lib\"\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/FPGA-MAFIA_fpga_mafia_pr548", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/FPGA-MAFIA_fpga_mafia_pr548.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/FPGA-MAFIA_fpga_mafia_pr548", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/FPGA-MAFIA_fpga_mafia_pr548"}
{"instance_id": "FPGA-MAFIA_fpga_mafia_pr559", "issue_text": "# rrv_core - Add a assertion for illegal memory access region.\n\n- Source URL: https://github.com/FPGA-MAFIA/fpga_mafia/issues/498\n\nWe should add an assertion making sure that if we have a load/store its for a d_mem/cr/vga region..\n(this would ease debugging when the SW tries to access the wrong memory space completely.. )\n\nPR Title: add assertion when accessing address out of range\nPR Number: #559\nStatus: Merged\nAuthor: roman012285\nReviewer/Merger: amichai-bd\nMerge Date: March 13, 2024\n\nDescription:\nNo formal description was provided by the author.\n\nKey Comments:\namichai-bd's Initial Review Questions:\n- Questioned why a SIM_ONLY definition was commented out in the test file list\n- Noted that a preprocessor directive should use ifdef instead of ifndef for the memory access assertion section\n\nroman012285's Responses:\nThe author acknowledged making changes immediately after pushing and committed to fixing the preprocessor directive, stating: \"I changed it right after I made push, I will commit it when i will be near computer. I must change ifndef to ifdef also\"\n\nAfter implementing corrections, roman012285 requested: \"fixed - Please review the changes\"\n\nFinal Approval:\namichai-bd approved the revised implementation and merged the pull request.\n\nRelated Issue:\nThis PR links to and likely closes issue #498: \"rrv_core - Add a assertion for illegal memory access region\"\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/FPGA-MAFIA_fpga_mafia_pr559", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/FPGA-MAFIA_fpga_mafia_pr559.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/FPGA-MAFIA_fpga_mafia_pr559", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/FPGA-MAFIA_fpga_mafia_pr559"}
{"instance_id": "FPGA-MAFIA_fpga_mafia_pr638", "issue_text": "# writing MC (memory controller) for communication between host and SDRAM\n\n- Source URL: https://github.com/FPGA-MAFIA/fpga_mafia/issues/611\n\n** Goal\n- Create communication interface between host computer and SDRAM\n\n** requirements\n- The controller will receive 128bit data (cache line) and transfer it to SDRAM at 16bit granularity.\n- The communication is bi-directional\n- The unit will take care of forwarding in case of RAW (read after write) that causes data hazard\n- The protocol designed to work with DE10-lite SDRAM\n- Support bursts\n**Further specifications will be added in the future**\n\nPR Title: Sdram controler for read/write 8 length bursts\n\nDescription:\nThe contributor submitted an FPGA design for an SDRAM controller supporting burst operations. Key details include:\n- Controller Location: source/mem_ss/sdram_ctrl_bursts\n- FPGA Design Location: /FPGA/sdram_full\n\nThe author noted temporary additions would be removed once the complete memory subsystem is functional, including some FPGA folders and .vh files within source/mem_ss.\n\nDemonstration:\nThe PR included three test case examples showing write/read functionality:\n- Writing to random address 0x0018\n- Reading from that address\n- Screenshots displaying read/write data and address values during operation\n\nCommits:\nThe PR merged 11 commits (May 1-9, 2024), including:\n- Controller implementation for burst operations\n- FPGA test directory additions\n- FSM implementations for random burst testing across addresses/banks\n- Debugging fixes and refresh logic enhancements\n\nStatus: Merged on May 10, 2024 by roman012285\nAssigned to: amichai-bd\nRelated Issue: #611 - \"writing MC (memory controller) for communication between host and SDRAM\"\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/FPGA-MAFIA_fpga_mafia_pr638", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/FPGA-MAFIA_fpga_mafia_pr638.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/FPGA-MAFIA_fpga_mafia_pr638", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/FPGA-MAFIA_fpga_mafia_pr638"}
{"instance_id": "FPGA-MAFIA_fpga_mafia_pr646", "issue_text": "# add M extension to big_core\n\n- Source URL: https://github.com/FPGA-MAFIA/fpga_mafia/issues/648\n\n- implement multiplication in HW in straight forward manner.  We do that because FPGA has dedicated multipliers\n- implement division as exception trap\n\nPR Title: add m_extension support\nStatus: Merged\nMerged by: amichai-bd on May 21, 2024\nSource Branch: big_core_RV32IM → main\nCommits: 4\n\nDescription:\nThe contributor successfully implemented RISC-V M extension (multiplication/division) support for the big_core processor. The implementation uses trap-based division handling and includes custom CSR functionality for storing the stack pointer.\n\nTest Command:\n./build.py -dut big_core -test m_extension -app -cfg big_core_rv32im -hw -sim\n\nResults demonstrated: Division, unsigned division, remainder, and unsigned remainder operations with test case 34÷4, plus negative number handling and overflow/division-by-zero edge cases.\n\nKey Comments:\nroman012285 (Author):\n- \"it took allot of time to understand the pointers and debug every thing\"\n- Acknowledged performance concerns with naive division algorithm\n- Noted potential stability issues with large unsigned number division and memory safety during interrupt handling\n\namichai-bd (Reviewer):\n- Flagged inefficient division algorithms with comments: \"Wow - this is why it takes so long! please change to a better algorithm\"\n- Requested terminology clarification (pointer vs. address; register file pointer vs. address)\n- Confirmed test was included: \"BIG_CORE -cfg big_core_rv32im with reference model\"\n\nLinked Issue:\n#648: add M extension to big_core - marked for closure\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/FPGA-MAFIA_fpga_mafia_pr646", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/FPGA-MAFIA_fpga_mafia_pr646.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/FPGA-MAFIA_fpga_mafia_pr646", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/FPGA-MAFIA_fpga_mafia_pr646"}
{"instance_id": "FPGA-MAFIA_fpga_mafia_pr655", "issue_text": "# Cache - support partiol read/write (byte enable)\n\n- Source URL: https://github.com/FPGA-MAFIA/fpga_mafia/issues/583\n\nCache - support partial read/write (byte enable)\nLHU, LBU, LW,LH,LB SW,SH,SB\nAlso, support signed and unsigned extends for the memory load request.\n\nPR Title: modify chach_tasks.vh to support random partial reads and writes\nPR Number: #655\nStatus: Merged\nRepository: FPGA-MAFIA/fpga_mafia\n\nDescription:\nNo formal description was provided by the author.\n\nComments:\namichai-bd (May 28, 2024):\n\"Small refactor into a single 'Case'\"\nThe reviewer noted a code consolidation effort with an accompanying image reference.\n\namichai-bd (May 28, 2024):\n\"I will also note that the verification env for this Cache is not really good.. It takes a long time to build and simulate - i suspect its due to something wring we did here.. Also a lot of code is duplicated - we should be able to use parameters to have different flavors of similar tasks.\"\nThe reviewer raised concerns about verification environment performance and code duplication, suggesting future refactoring opportunities.\n\nLinked Issue:\n#583 - \"Cache - support partiol read/write (byte enable)\" (Closed by this PR)\n\nCommits Overview:\n13 commits were merged, including initial test additions, byte offset support for D_CACHE, partial read/write handling, and byte enable offset fixes across fill requests.\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/FPGA-MAFIA_fpga_mafia_pr655", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/FPGA-MAFIA_fpga_mafia_pr655.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/FPGA-MAFIA_fpga_mafia_pr655", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/FPGA-MAFIA_fpga_mafia_pr655"}
{"instance_id": "FPGA-MAFIA_fpga_mafia_pr680", "issue_text": "# Refactor the CR memory space\n\n- Source URL: https://github.com/FPGA-MAFIA/fpga_mafia/issues/679\n\n## Issue Title\nRefactor the CR memory space\n\n## Issue Description\nCreate a simple struct for the all CR! This shold solve the error in the readafter write issue we have.\n\n(The issue proposes organizing the Control Register (CR) memory space using a structured data type to address read-after-write synchronization problems in the FPGA-MAFIA project.)\n\n## Issue Comments\nNone.\n\n## Issue Metadata\n- Status: Closed (linked to PR #680)\n- Assignee: amichai-bd\n- Labels: RTL design, build & env\n- Created: June 16, 2024\n\n## Linked Issues / PRs\n- PR #680 — the resolution implementation\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/FPGA-MAFIA_fpga_mafia_pr680", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/FPGA-MAFIA_fpga_mafia_pr680.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/FPGA-MAFIA_fpga_mafia_pr680", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/FPGA-MAFIA_fpga_mafia_pr680"}
{"instance_id": "HiSA-Team_Simply-V_pr102", "issue_text": "# [bugfix/sync_pbus_interrupts] Add synchronizers for PBUS interrupts\n\n- Source URL: https://github.com/HiSA-Team/Simply-V/issues/101\n\n## Issue Title\n[bugfix/sync_pbus_interrupts] Add synchronizers for PBUS interrupts\n\n## Issue Description\nDuring CDC (#91) we forgot to re-synchronize PBUS outgoing interrupts to the MAIN_CLOCK_DOMAIN.\n\nThis could be fixed by adding a NUM_IRQ-wide xpm_cdc_async_rst in pbus between int_o and each peripheral interrupt, instead of just assigning them as in the prior implementation.\n\nAdditionally, here we could also fix unassigned int_o bits.\n\n## Issue Comments\nNone visible.\n\n## Issue Metadata\n- Status: Closed (via PR #102)\n- Assignee: DOTTORM5\n- Milestone: MCU release\n- Author: MaistoV\n- Date Opened: April 8, 2025\n\n## Linked Issues / PRs\n- PR #102 — fix\n- Refers back to #91 (prior CDC work)\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/HiSA-Team_Simply-V_pr102", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/HiSA-Team_Simply-V_pr102.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/HiSA-Team_Simply-V_pr102", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/HiSA-Team_Simply-V_pr102"}
{"instance_id": "HiSA-Team_Simply-V_pr108", "issue_text": "# [feature/rv64/rtl] RV64: RTL & IPs adjustments\n\n- Source URL: https://github.com/HiSA-Team/Simply-V/issues/86\n\n**UninaSoC RTL**\n\n- [x]  header files (`svh`) for protocols can work with adjusting the DATA_WIDTH, STRB and ID. To do so, let's remove parameters (as they are not used) and move to parametric macros and declarations (including ports)\n- [x] Update files in `rtl` to support new `svh` macros\n- [x] Update `.svinc` file generation\n- [x] uninasoc.sv should be independent from XLEN, however all hardcoded references to 32 bits must be removed (if any).\n- [x] Clock_converters and Dwidth_converters: DDR4\n- [x] Clock_converters and Dwidth_converters: PBUS\n- [x] Clock_converters and Dwidth_converters: Sys Master\n- [x] Clock_converters and Dwidth_converters: PLIC\n- [x] Regarding the socket, the idea is to assume a user will always use a 64-bits CPU if XLEN=64; therefore a simple assert will do the job, stopping the build if the core selector is incompatible with the XLEN. **Note** in #83 core and xlen compatibility will be checked as well\n\n**UninaSoC IPS**\n\n- [x] Update files in `rtl` to support new `svh` macros\n- [x] The IP config files should take into account the change of data width and address width. (e.g. block mem generator).\n- [x] Custom IPS will be independent from the config flow. For now, all peripherals on the pbus will be at 32, and only the PLIC might change between 32 and 64.\n- [x] Add PLIC new Target (for socket S-mode) -> Moved to #107\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/HiSA-Team_Simply-V_pr108", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/HiSA-Team_Simply-V_pr108.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/HiSA-Team_Simply-V_pr108", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/HiSA-Team_Simply-V_pr108"}
{"instance_id": "HiSA-Team_Simply-V_pr118", "issue_text": "# [Submission] <hidden> 2025\n\n- Source URL: https://github.com/HiSA-Team/Simply-V/issues/65\n\n## Issue Title\n[Submission] <hidden> 2025\n\n## Issue Description\nThis issue tracks all the technical tasks for the <hidden> submission.\n\nPaper evaluation tasks:\n- CPU Benchmark (tacle-bench)\n- HLS integration\n- HLS peripheral iterative fast-prototyping\n- HLS experiments embedded\n- HLS experiments HPC\n- HLS experiments on HBUS\n- RV64: CVA6 tacle-bench on BRAM (embedded)\n- RV64: CVA6 tacle-bench on BRAM (hpc)\n- RV64: CVA6 tacle-bench on DDR (hpc)\n- RVV (tracked in #119)\n- Veer Core (tracked in #67)\n\nThe checklist shows 7 of 7 items completed. Issue linked to pull request #118.\n\n## Issue Comments\nNone visible.\n\n## Issue Metadata\n- Status: Closed\n- Assignee: MaistoV\n\n## Linked Issues / PRs\n- PR #118 — submission tracker resolution\n- #119: feature request for PULP Ara RVV support\n- #67: feature request for VeerWolf core integration\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/HiSA-Team_Simply-V_pr118", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/HiSA-Team_Simply-V_pr118.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/HiSA-Team_Simply-V_pr118", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/HiSA-Team_Simply-V_pr118"}
{"instance_id": "HiSA-Team_Simply-V_pr129", "issue_text": "# [feature/rv64/cv64a6] RV64: Integrate CV64A6\n\n- Source URL: https://github.com/HiSA-Team/Simply-V/issues/82\n\nIntegrating CV64A6\n\n**Generic**\n- [x] Rebase on Main\n- [x] Restore HBUS behaviour and revert openocd\n\n**Hardware**\n- [x] Integrate CV64A6 in the socket\n- [x] Integrate JTAG2AXI DWIDTH converter\n- [x] Fix RTL: peripheral crossbar generation\n- [x] Fix linker script generation: stack alignment\n- [x] Add patching in OpenHW fetch sources script\n- [x] Stabilize 64-bits toolchain\n- [x] Integrate 64-bits debugging\n- [x] Add our configs into Assets with symbolic linking\n- [x] Connect Interrupts\n\n**Software**\n- [x] Update tinyIO to be compiled at 64 bits\n- [x] Test Software : Blinky\n- [x] Test Software : Echo\n- [x] Test Software: Hello World\n- [x] Test Software: Interrupts\n- [x] Prototype bootrom\n\n> BUG: OpenHW CVA6 v0.5.1 with C-ext enabled can't run code without C-ext\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/HiSA-Team_Simply-V_pr129", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/HiSA-Team_Simply-V_pr129.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/HiSA-Team_Simply-V_pr129", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/HiSA-Team_Simply-V_pr129"}
{"instance_id": "HiSA-Team_Simply-V_pr147", "issue_text": "# [feature/rv64/microblazev] Integrate RV64 version of Microblaze-V\n\n- Source URL: https://github.com/HiSA-Team/Simply-V/issues/114\n\n## Issue Title\n[feature/rv64/microblazev] Integrate RV64 version of Microblaze-V\n\n## Issue Description\nAssigned to Salvatore Santoro.\n\nAdd microblaze_riscv_rv64 Xilinx IP (UG1629).\n\nW.r.t. microblaze_riscv IP, the only parameters to change are:\n1. CONFIG.C_DATA_SIZE = 64\n2. CONFIG.C_ADDR_SIZE — supported values: 32, 36, 40, 44, 48, 52, 56, 64\n\nNote that when enabling RV64 (rather than RV32), all the interfaces remain 32-bits wide, therefore a couple of dwidth adapters should do the trick.\n\n## Issue Comments\nNone visible.\n\n## Issue Metadata\n- Status: Closed (linked to PR #147)\n- Assignee: MaistoV\n\n## Linked Issues / PRs\n- PR #147 — implements this feature\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/HiSA-Team_Simply-V_pr147", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/HiSA-Team_Simply-V_pr147.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/HiSA-Team_Simply-V_pr147", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/HiSA-Team_Simply-V_pr147"}
{"instance_id": "HiSA-Team_Simply-V_pr166", "issue_text": "# [feature/rvv/ara] Integrate PULP Ara for RVV support\n\n- Source URL: https://github.com/HiSA-Team/Simply-V/issues/119\n\n## Issue Title\n[feature/rvv/ara] Integrate PULP Ara for RVV support\n\n## Issue Description\n- Need finalized CVA6 support\n- Integrate CVA6 + Ara as a single custom IP (different than standalone cv64a6)\n- Use Ara 2-lanes, matching CVA6 data width, e.g. 64-bits\n\nTODO (move to another issue):\n- Ara 4- and 8-lanes: Attach Ara AXI master to HBUS\n\n## Issue Comments\nNone visible.\n\n## Issue Metadata\n- Status: Closed (with associated PR #166)\n- Assignee: MaistoV\n\n## Linked Issues / PRs\n- PR #166 — addresses this feature request\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/HiSA-Team_Simply-V_pr166", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/HiSA-Team_Simply-V_pr166.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/HiSA-Team_Simply-V_pr166", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/HiSA-Team_Simply-V_pr166"}
{"instance_id": "HiSA-Team_Simply-V_pr184", "issue_text": "# [feature/axi_cdma/basic][student] Basic AXI CDMA integration\n\n- Source URL: https://github.com/HiSA-Team/Simply-V/issues/162\n\n## Issue Title\n[feature/axi_cdma/basic][student] Basic AXI CDMA integration\n\n## Issue Description\nAssigned to Michele Giugliano.\n\nIntegration design diagram is attached. See parent issue #153 for further details.\n\nThe submission represents a student-led feature development task related to AXI CDMA (Advanced eXtensible Interface Central Direct Memory Access) integration. It indicates a hierarchical issue structure with parent issue #153 containing broader requirements.\n\n## Issue Comments\nNone visible.\n\n## Issue Metadata\n- Status: Closed (merged via PR #184)\n- Assignee: MaistoV\n- Labels: None\n- Type: None\n- Project / milestone: None\n\n## Linked Issues / PRs\n- PR #184 — implementation\n- Parent issue: #153\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/HiSA-Team_Simply-V_pr184", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/HiSA-Team_Simply-V_pr184.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/HiSA-Team_Simply-V_pr184", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/HiSA-Team_Simply-V_pr184"}
{"instance_id": "HiSA-Team_Simply-V_pr48", "issue_text": "# [feature/debug_module] Integrate RISC-V debug module\n\n- Source URL: https://github.com/HiSA-Team/Simply-V/issues/22\n\n## Issue Title\n[feature/debug_module] Integrate RISC-V debug module\n\n## Issue Description\nAdd RISC-V debug module (https://github.com/pulp-platform/riscv-dbg/tree/v0.8.1) and expose it on Xilinx scanchain to make it visible to hw_server.\n\nTentatively try to integrate it with jtag-ext-bscan.vhdl (https://github.com/eugene-tarassov/vivado-risc-v/blob/master/vhdl-wrapper/src/net/largest/riscv/vhdl/jtag-ext-bscan.vhdl).\n\nMost likely there are going to be compatibility issues with JTAG, BSCAN and hw_server.\n\nAlternatively, just fall-back to PULP BSCAN tap (https://github.com/pulp-platform/riscv-dbg/blob/master/src/dmi_bscane_tap.sv) and OpenOCD. In this case, the issue would be the OpenOCD config file for Nexys and Alveo.\n\n## Issue Comments\nNo comments are present on this issue.\n\n## Issue Metadata\n- Status: Closed\n- Assignee: MaistoV\n- Milestone: MCU release\n\n## Linked Issues / PRs\n- PR #48 — associated pull request (closed)\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/HiSA-Team_Simply-V_pr48", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/HiSA-Team_Simply-V_pr48.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/HiSA-Team_Simply-V_pr48", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/HiSA-Team_Simply-V_pr48"}
{"instance_id": "HiSA-Team_Simply-V_pr52", "issue_text": "# [feature/core_selection] Add core selection to Make flow\n\n- Source URL: https://github.com/HiSA-Team/Simply-V/issues/20\n\n## Issue Title\n[feature/core_selection] Add core selection to Make flow\n\n## Issue Description\nAdd core selection to Make flow for RVM socket CORE_SELECTION parameter.\n\n## Issue Comments\nNone visible.\n\n## Issue Metadata\n- Status: Closed\n- Assignee: MaistoV\n- Milestone: MCU release\n\n## Linked Issues / PRs\n- PR #52 — implementation (closed)\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/HiSA-Team_Simply-V_pr52", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/HiSA-Team_Simply-V_pr52.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/HiSA-Team_Simply-V_pr52", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/HiSA-Team_Simply-V_pr52"}
{"instance_id": "HiSA-Team_Simply-V_pr68", "issue_text": "# [debug/plic] Fix PLIC integration\n\n- Source URL: https://github.com/HiSA-Team/Simply-V/issues/50\n\n## Issue Title\n[debug/plic] Fix PLIC integration\n\n## Issue Description\nNo description provided.\n\n## Issue Comments\nNone visible.\n\n## Issue Metadata\n- Status: Closed\n- Assignee: Granp4sso\n- Milestone: MCU release\n\n## Linked Issues / PRs\n- PR #68 — closing PR\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/HiSA-Team_Simply-V_pr68", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/HiSA-Team_Simply-V_pr68.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/HiSA-Team_Simply-V_pr68", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/HiSA-Team_Simply-V_pr68"}
{"instance_id": "HiSA-Team_Simply-V_pr92", "issue_text": "# [feature/cores/ibex] Integrate Ibex core as custom IP\n\n- Source URL: https://github.com/HiSA-Team/Simply-V/issues/66\n\n## Issue Title\n[feature/cores/ibex] Integrate Ibex core as custom IP\n\n## Issue Description\nFrom https://github.com/lowRISC/ibex.\n\nIssues:\n- which release?\n- which DTM to use? from PULP or ibex-demo-system?\n\n## Issue Comments\nNone visible.\n\n## Issue Metadata\n- Status: Closed (via PR #92)\n- Opened by: MaistoV on March 11, 2025\n- Assignees: Granp4sso, MaistoV\n\n## Linked Issues / PRs\n- PR #92 — appears to be the resolution implementation\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/HiSA-Team_Simply-V_pr92", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/HiSA-Team_Simply-V_pr92.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/HiSA-Team_Simply-V_pr92", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/HiSA-Team_Simply-V_pr92"}
{"instance_id": "IEEE-UCF_Gaming-CPU-Project_pr42", "issue_text": "# Subsystem: Design RAM Handler\n\n- Source URL: https://github.com/IEEE-UCF/Gaming-CPU-Project/issues/27\n\n**Purpose:** Orchestrate Double Data Rate (DDR) interactions between RAM and CPU system, including booting from ROM and connecting to AXI \n\n**Main File(s)**\n\n- [SRAM Dualport](https://github.com/IEEE-UCF/Gaming-CPU-Project/blob/main/rtl/mem/sram_dualport.sv)\n- [Boot ROM](https://github.com/IEEE-UCF/Gaming-CPU-Project/blob/main/rtl/mem/bootrom.sv)\n- [DMA](https://github.com/IEEE-UCF/Gaming-CPU-Project/blob/main/rtl/subsys/dma_subsys.sv)\n\n**Sub-Files**\n- [MIG AXI Wrapper](https://github.com/IEEE-UCF/Gaming-CPU-Project/blob/main/rtl/mem/ddr/mig_axi_wrap.sv)\n- [MIG Calibration Status](https://github.com/IEEE-UCF/Gaming-CPU-Project/blob/main/rtl/mem/ddr/calib_status_sync.sv)\n\n**Related Sub-Issues (Dependencies)**\nBus: #6 \nInput-Output: #26\n\n**Co-Lead**\nEvan Eichholz\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/IEEE-UCF_Gaming-CPU-Project_pr42", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/IEEE-UCF_Gaming-CPU-Project_pr42.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/IEEE-UCF_Gaming-CPU-Project_pr42", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/IEEE-UCF_Gaming-CPU-Project_pr42"}
{"instance_id": "KestrelComputer_polaris_pr21", "issue_text": "Datasheet assumes the user knows how to instantiate the processor in Verilog. And they probably do. However, in the interests of professionalism, I'd like to see an example Verilog application of the processor included in the data sheet showing how it's typically used.\n\n\nSimple RAM memory; 4KB ought to be way more than enough for our needs (512 x 64b).\n\nSimple ROM memory; 4KB ought to be plenty (1024 x 32b)\n\nSimple console I/O port.\n\nCharacter output port (prints character to screen)\n\nBit that exits the simulation.\n\nCustom CSR registers to demo the C-port?\n\nSimple address decoder.\n\nA simple hello-world type application that prints to the screen and exits the simulation.\n\nMemory bus bridge\n\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/KestrelComputer_polaris_pr21", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/KestrelComputer_polaris_pr21.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/KestrelComputer_polaris_pr21", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/KestrelComputer_polaris_pr21"}
{"instance_id": "KestrelComputer_polaris_pr22", "issue_text": "# Support SLT/SLTU instructions\n\n- Source URL: https://github.com/KestrelComputer/polaris/pull/22\n\nThe SLT and SLTU instructions are decoded. However, the driver signals are never propagated to the ALU. Moreover, I don't think the ALU itself has SLT/SLTU functionality baked into it just yet.\n\nWrite bench tests to check for this condition.\n\nConfirm malignant behavior with bench tests.\n\nPropagate ltu_en from sequencer to ALU.\n\nPropagate lts_en from sequencer to ALU.\n\nImplement magnitude comparison logic in ALU. Probably borrow/re-use same logic as BLT and BLTU instructions.\n\n## Fetched Issue/PR Details\n\nTitle: Support SLT/SLTU instructions.\n\nDescription: The pull request restores previously missing SLT/SLTU instructions. According to the contributor: \"These instructions were previously missing. They're back!\"\n\nStatus: Merged\nAuthor: sam-falvo\nMerge Date: November 26, 2016\nRepository: KestrelComputer/polaris\nBranch: master\n\nComments:\n- sam-falvo (Nov 26, 2016): Indicated that this PR resolves issue #18 in the KestrelComputer/polaris repository.\n\nLinked Issues: Closes issue #18 (the original local description above appears to capture the body of that referenced issue: missing propagation of SLT/SLTU driver signals into the ALU and missing magnitude-comparison logic in the ALU).\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/KestrelComputer_polaris_pr22", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/KestrelComputer_polaris_pr22.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/KestrelComputer_polaris_pr22", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/KestrelComputer_polaris_pr22"}
{"instance_id": "Lampro-Mellon_LM-RISCV-DV_pr81", "issue_text": "# Enable Verilator in the RTL Simulation Flow for SweRV integration\n\n- Source URL: https://github.com/Lampro-Mellon/LM-RISCV-DV/issues/69\n\n\n## Fetched Issue/PR Details\n\nTitle: Enable Verilator in the RTL Simulation Flow for SweRV integration (#69)\n\nDescription: No description was provided in the original issue.\n\nStatus: Closed (resolved via PR #81)\nAssignee: amnafayyaz28\nLabel: enhancement\nReporter: haroon-shafique\nOpened: January 7, 2021\n\nComments: No comments, reactions, or additional context were visible on the page.\n\nLinked Issues: Resolving PR #81. The issue requests integration of Verilator (an open-source RTL simulator) into the RTL simulation workflow for SweRV core integration within the LM-RISCV-DV project.\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/Lampro-Mellon_LM-RISCV-DV_pr81", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/Lampro-Mellon_LM-RISCV-DV_pr81.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/Lampro-Mellon_LM-RISCV-DV_pr81", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/Lampro-Mellon_LM-RISCV-DV_pr81"}
{"instance_id": "MPSU_APS_pr98", "issue_text": "# 6 лабораторная\n\n- Source URL: https://github.com/MPSU/APS/issues/94\n\nНе указано, что для работы симуляции память должна называться \"ram\", иначе выдаст ошибку.\n\n---\n\n## Pull Request\n\n**PR Title:** WIP: APS cumulative update\n\n**PR Number:** #98\n\n**Status:** Merged on September 2, 2024\n\n**Author:** HepoH3\n\n### Description\n\nNo description provided by the author.\n\n### Commits (16 total)\n\nThe pull request contains 16 commits including:\n- Updates to FPGA documentation\n- Reorganization of sequential logic content into separate documentation\n- Image corrections and formatting fixes\n- Vivado Basics section refactoring\n- Project creation guide updates with images\n- Link corrections across multiple sections (RTL analysis, bug hunting)\n- FPGA firmware guide refactoring\n- Mass updates and figure restorations\n\n### Linked Issue\n\n**Issue #94:** \"6 лабораторная\" (6th Laboratory)\n\n### Activity\n\n- Initial commit: August 23, 2024\n- Marked ready for review: September 2, 2024\n- Merged: September 2, 2024\n- Branch deleted: September 2, 2024 (cumulative_update branch)\n\n### Additional Details\n\n- Reviewers: None recorded\n- Assignees: None\n- Labels: None\n- Milestone: None\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/MPSU_APS_pr98", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/MPSU_APS_pr98.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/MPSU_APS_pr98", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/MPSU_APS_pr98"}
{"instance_id": "MiSTer-devel_Arcade-Robotron_MiSTer_pr25", "issue_text": "# Core is outputting at 296 x 243...\n\n- Source URL: https://github.com/MiSTer-devel/Arcade-Robotron_MiSTer/issues/24\n\n...instead of 292 x 240 and as such doesn't seem to want to scale to 720p.\n\n## Fetched Issue/PR Details\n\nTitle: Core is outputting at 296 x 243... (#24)\n\nDescription: The core outputs a resolution of 296 x 243 pixels instead of the expected 292 x 240, which prevents proper scaling to 720p.\n\nRepository: MiSTer-devel/Arcade-Robotron_MiSTer\nAuthor: dazzer69\nOpened: September 27, 2021\nStatus: Closed (linked to PR #25)\n\nAdditional Details:\n- No assignees or labels\n- No open branches or pull requests associated\n\nComments: No comments visible.\n\nLinked Issues: Resolving PR #25.\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/MiSTer-devel_Arcade-Robotron_MiSTer_pr25", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/MiSTer-devel_Arcade-Robotron_MiSTer_pr25.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/MiSTer-devel_Arcade-Robotron_MiSTer_pr25", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/MiSTer-devel_Arcade-Robotron_MiSTer_pr25"}
{"instance_id": "MiSTer-devel_C64_MiSTer_pr142", "issue_text": "# Arctic Shipwreck crashes on start\n\n- Source URL: https://github.com/MiSTer-devel/C64_MiSTer/issues/107\n\nTOSEC — Commodore C64 - Games - [D64]: Arctic Shipwreck (1983)(Commodore).d64\ncrc=684e5568 md5=aa9d3ed98bf0fe0b459626a1ff02bad1 sha1=a2139a5df6d949a4c402b726bd9f8bf11007a222\n\nThis game crashes on start, attempting to render its 3D ice floe. It also fails to play the music melody on title screen. Core settings set to PAL machine with standard KERNAL.\n\nFor comparison, the same disk file works properly in VICE emulator.\n\n## Fetched Issue/PR Details\n\nTitle: Arctic Shipwreck crashes on start (#107)\n\nDescription: The user reports that the game Arctic Shipwreck (1983) for Commodore 64 crashes when attempting to render its 3D ice floe at startup. Additionally, the title screen music fails to play. The core is configured for PAL machine with standard KERNAL. The same disk file functions properly in VICE emulator, indicating an emulation-specific compatibility issue rather than a corrupted ROM.\n\nGame Details:\n- Source: TOSEC - Commodore C64 - Games - [D64]\n- File: Arctic Shipwreck (1983)(Commodore).d64\n- Checksums: CRC=684e5568, MD5=aa9d3ed98bf0fe0b459626a1ff02bad1, SHA1=a2139a5df6d949a4c402b726bd9f8bf11007a222\n\nStatus: Closed via pull request #142.\n\nComments: No comments were present on the page.\n\nLinked Issues: Resolving PR #142.\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/MiSTer-devel_C64_MiSTer_pr142", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/MiSTer-devel_C64_MiSTer_pr142.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/MiSTer-devel_C64_MiSTer_pr142", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/MiSTer-devel_C64_MiSTer_pr142"}
{"instance_id": "MiSTer-devel_Gameboy_MiSTer_pr216", "issue_text": "# Perfect Dark (GBC) - No PCM Sound\n\n- Source URL: https://github.com/MiSTer-devel/Gameboy_MiSTer/issues/87\n\nIn the GBC game Perfect Dark the PCM sound (which plays a relatively big part in this game) does not work.\n\nSteps to reproduce: press start a few times once the game boots in order to select a new game and have the game automatically create a name for your save file. After the name entry screen, an intro dialog screen will appear.  This dialog should be fully voiced via PCM samples, but instead there's silence. Same goes for all the gunshots, footsteps, and various grunts/yells the characters make throughout the game.\n\nExample video with the PCM samples in the intro playing correctly; relevant section starts at about 54sec: https://youtu.be/xeLNNsVPSCA?t=54\n\n## Fetched Issue/PR Details\n\nTitle: Perfect Dark (GBC) - No PCM Sound (#87)\n\nRepository: MiSTer-devel/Gameboy_MiSTer\n\nDescription: The reporter identified that PCM sound functionality is non-functional in the Game Boy Color version of Perfect Dark. They noted: \"the PCM sound (which plays a relatively big part in this game) does not work.\"\n\nSteps to Reproduce: Start the game, press start multiple times to initiate a new save file with auto-generated naming, then proceed through the name entry screen to reach an intro dialog sequence that should feature voice acting via PCM samples.\n\nAffected Audio Elements:\n- Intro dialog voice acting\n- Gunshot sound effects\n- Footstep sounds\n- Character vocalizations (grunts/yells)\n\nReference Material: A YouTube link demonstrates the PCM samples functioning correctly, with the relevant audio sequence beginning around the 54-second mark.\n\nStatus: Closed (resolved via PR #216)\nLabel: bug\nOpened: June 24, 2020\n\nLinked Issues: Resolving PR #216.\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/MiSTer-devel_Gameboy_MiSTer_pr216", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/MiSTer-devel_Gameboy_MiSTer_pr216.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/MiSTer-devel_Gameboy_MiSTer_pr216", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/MiSTer-devel_Gameboy_MiSTer_pr216"}
{"instance_id": "MiSTer-devel_Gameboy_MiSTer_pr24", "issue_text": "# SRAM management\n\n- Source URL: https://github.com/MiSTer-devel/Gameboy_MiSTer/issues/13\n\nIs it possible to import/export SRAM data?\n\n## Fetched Issue/PR Details\n\nTitle: SRAM management (#13)\n\nDescription: \"Is it possible to import/export SRAM data?\"\n\nAuthor: catskull\nDate Opened: December 1, 2018\nStatus: Closed\nRelated pull request: #24 (closed)\n\nComments: No comments visible on the page.\n\nLinked Issues: Resolving PR #24. The issue raises a question about whether the Gameboy_MiSTer project supports functionality for importing and exporting SRAM (Static RAM) data, which typically stores game save files.\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/MiSTer-devel_Gameboy_MiSTer_pr24", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/MiSTer-devel_Gameboy_MiSTer_pr24.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/MiSTer-devel_Gameboy_MiSTer_pr24", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/MiSTer-devel_Gameboy_MiSTer_pr24"}
{"instance_id": "MiSTer-devel_Gameboy_MiSTer_pr240", "issue_text": "# Save states save and load to the wrong save state slot\n\n- Source URL: https://github.com/MiSTer-devel/Gameboy_MiSTer/issues/174\n\n@RobertPeip,\n\nI have found an interesting menu issue that seems to affect all cores save states implemented in them.   To reproduce this issue choose a save state slot 2, 3, or 4 and save your settings on the second menu page.  Close the core or switch to a different core then come back to the core.  The save slot displayed will be what was saved previously.  If you choose save or load save state it use slot 1 regardless of what slot is displayed (2,3,4).\n\nI thought I was going crazy until I realized slot 1 was briefly coming up onscreen when trying to load a save state.\n\nI also discovered more strange save state behavior for the cores that use bootX.rom files to auto load an initial game.   For Gameboy it's boot2.rom and NES boo1.rom.  Save states seem to work until exiting the core then cease to exist upon returning.   My guess the core probably doesn't have valid filename to use to store the save state.\n\n## Fetched Issue/PR Details\n\nTitle: Save states save and load to the wrong save state slot (#174)\n\nDescription: The reporter describes a menu issue affecting save state functionality across multiple cores. When selecting save state slots 2, 3, or 4 and saving settings on the second menu page, the core displays the previously saved slot number upon reopening. However, attempting to save or load always uses slot 1 regardless of the displayed slot. The user observed slot 1 briefly appearing onscreen when loading save states.\n\nAdditionally, the reporter notes problematic behavior with cores using boot ROM files (like boot2.rom for Gameboy and boot1.rom for NES). Save states function initially but \"cease to exist upon returning\" after exiting the core, suggesting the core lacks a valid filename for storing the save state data.\n\nStatus: Closed (linked to PR #240)\nReporter: dot-bob\nOpened: August 8, 2021\n\nComments: No comments or additional discussion visible on the page.\n\nLinked Issues: Resolving PR #240.\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/MiSTer-devel_Gameboy_MiSTer_pr240", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/MiSTer-devel_Gameboy_MiSTer_pr240.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/MiSTer-devel_Gameboy_MiSTer_pr240", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/MiSTer-devel_Gameboy_MiSTer_pr240"}
{"instance_id": "MiSTer-devel_Gameboy_MiSTer_pr52", "issue_text": "# Loading B/W games with GBC hardware set results in severe gfx glitches\n\n- Source URL: https://github.com/MiSTer-devel/Gameboy_MiSTer/issues/45\n\nSo, when you load up a standard non-colour game in a real GBC, you get the standard boot intro and then the game loads with a predetermined palette if the game ID is found in the list in the bootstrap rom (https://tcrf.net/Notes:Game_Boy_Color_Bootstrap_ROM). Palettes can be set with a button press when the Game Boy logo loads. Benefit of using GB games on a GBC include that there's actually more colours in play - sprites have a separate colour.\r\n\r\nAnyway, it's pretty glitchy on the current core build. I've taken some comparison photos to explain. MiSTer screenshot first, real hardware second:\r\n\r\n![20190623_104859-Wario Land - Super Mario Land 3 (World)](https://user-images.githubusercontent.com/52125847/59974730-7e25e300-95a7-11e9-8ad8-79ecc801ee93.png)\r\n\r\n![IMG_20190623_105248](https://user-images.githubusercontent.com/52125847/59974732-82520080-95a7-11e9-9693-f160825257d5.jpg)\r\n\r\n![20190623_104918-Wario Land - Super Mario Land 3 (World)](https://user-images.githubusercontent.com/52125847/59974733-87af4b00-95a7-11e9-8678-71438ecbf859.png)\r\n\r\n![IMG_20190623_105303](https://user-images.githubusercontent.com/52125847/59974736-8b42d200-95a7-11e9-8b7e-81c22e759181.jpg)\r\n\r\n![20190623_105019-DONKEYKONG](https://user-images.githubusercontent.com/52125847/59974737-9269e000-95a7-11e9-806d-f74d5e32a20c.png)\r\n\r\n![IMG_20190623_105323](https://user-images.githubusercontent.com/52125847/59974738-94cc3a00-95a7-11e9-823f-9bebd26451ae.jpg)\r\n\r\n![20190623_105042-DONKEYKONG](https://user-images.githubusercontent.com/52125847/59974741-9bf34800-95a7-11e9-92d5-a84f818cfdce.png)\r\n\r\n![IMG_20190623_105358](https://user-images.githubusercontent.com/52125847/59974744-9e55a200-95a7-11e9-9b61-18726e94a60b.jpg)\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/MiSTer-devel_Gameboy_MiSTer_pr52", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/MiSTer-devel_Gameboy_MiSTer_pr52.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/MiSTer-devel_Gameboy_MiSTer_pr52", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/MiSTer-devel_Gameboy_MiSTer_pr52"}
{"instance_id": "MiSTer-devel_Gameboy_MiSTer_pr96", "issue_text": "# Spot: title music and sound effects aren’t right\n\n- Source URL: https://github.com/MiSTer-devel/Gameboy_MiSTer/issues/51\n\nBoth the title music and the gameplay sound effects contain high-pitched noises and distortion that are not correct.\n\n---\n\n## Pull Request\n\n**PR Title:** SOUND: multiple Wave channel fixes and GB/GBC behavior\n\n**PR Number:** #96\n\n**Status:** Merged by sorgelig on July 5, 2020\n\n**Author:** brNX\n\n### Description\n\nThe PR author (brNX) provided the following overview:\n\n- \"General gbc_snd.vhd cleanup\"\n- Sound register writes now handled correctly between GB/GBC consoles, passing Blargg's tests 08 and 11\n- \"Wave table reads correctly implemented, it depends on the current index while channel is playing\"\n- Wave access only available when recently accessed in GB mode, passing Blargg's test 09\n- Wave table initialization with known values, resolving issues in specific games\n- The author notes the APU passes most Blargg sound tests but suspects additional issues remain with sound channel behavior during playback\n\n### Commits (6 total)\n\n1. Wave channel 3 read dependent on current wave index\n2. Wave trigger timing extended for GBC compatibility; added is_gbc input\n3. Wave table access timewindow added for DMG mode (returns 0xFF outside window)\n4. Whitespace cleanup\n5. Write process refactored for reset and DMG-specific behavior; wave table initialized\n6. Sound processing refactored; duty cycle accessibility restricted in DMG mode\n\n### Linked Issue\n\n**#51 - \"Spot: title music and sound effects aren't right\"** — addressed by this PR's wave table initialization improvements.\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/MiSTer-devel_Gameboy_MiSTer_pr96", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/MiSTer-devel_Gameboy_MiSTer_pr96.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/MiSTer-devel_Gameboy_MiSTer_pr96", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/MiSTer-devel_Gameboy_MiSTer_pr96"}
{"instance_id": "MiSTer-devel_Genesis_MiSTer_pr144", "issue_text": "# [MISSING ISSUE] MiSTer-devel/Genesis_MiSTer#143\n\n- Source URL: https://github.com/MiSTer-devel/Genesis_MiSTer/issues/143\n- Note: Issue content not available via API (recorded in missing_issues.*)\n\nFailed to fetch issue content.\nReason: graphql_error\nDetails: {\"reason\": \"graphql_error\", \"errors\": [{\"type\": \"NOT_FOUND\", \"path\": [\"repository\", \"issue\"], \"locations\": [{\"line\": 6, \"column\": 5}], \"message\": \"Could not resolve to an Issue with the number of 143.\"}]}\n\n---\n\n## Pull Request\n\n**PR Title:** One method of simulating Z80 open bus\n\n**PR Number:** #144\n\n**Status:** Merged on July 20, 2020\n\n**Author:** steven-a-wilson\n\n### Description\n\nsteven-a-wilson's implementation addresses issue #143 by implementing open bus behavior for non-read Z80 bus cycles. The contributor notes uncertainty about safety and cleanliness of the approach, having only conducted light testing.\n\nKey Changes:\n- Modified T80s DI connection to default to Z80_ZBUS_D instead of Z80_MBUS_D\n- Set Z80_ZBUS_D to 8'hFF during ZBUS_IDLE state when Z80_RD_N is not asserted\n- Mostly indentation adjustments; critical addition is the \"if (Z80_RD_N)\" condition\n\n### Comments\n\n**jotego (July 20, 2020):** Asked whether this resolves the related issue.\n\n**steven-a-wilson (July 19, 2020):** Marked ready for review per sorgelig's suggestion on issue #143.\n\n**steven-a-wilson (July 19, 2020):** Initial submission noting this represents one possible approach among several alternatives.\n\n### Linked Issue\n\n**#143:** \"Sonic Delta 40Mb sound problem (Z80 interrupt mode 0)\"\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/MiSTer-devel_Genesis_MiSTer_pr144", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/MiSTer-devel_Genesis_MiSTer_pr144.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/MiSTer-devel_Genesis_MiSTer_pr144", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/MiSTer-devel_Genesis_MiSTer_pr144"}
{"instance_id": "MiSTer-devel_Genesis_MiSTer_pr160", "issue_text": "# [MISSING ISSUE] MiSTer-devel/Genesis_MiSTer#154\n\n- Source URL: https://github.com/MiSTer-devel/Genesis_MiSTer/issues/154\n- Note: Issue content not available via API (recorded in missing_issues.*)\n\nFailed to fetch issue content.\nReason: graphql_error\nDetails: {\"reason\": \"graphql_error\", \"errors\": [{\"type\": \"NOT_FOUND\", \"path\": [\"repository\", \"issue\"], \"locations\": [{\"line\": 6, \"column\": 5}], \"message\": \"Could not resolve to an Issue with the number of 154.\"}]}\n\n---\n\n## Pull Request\n\n**PR Title:** Fixing EXT port read logic\n\n**PR Number:** #160\n\n**Status:** Merged\n\n**Author:** iequalshane\n\n**Merged by:** sorgelig on January 1, 2021\n\n### Description\n\nThe pull request description states: \"Fixes #154 Hyokkori Hyoutanjima (J) bin/md doesn't respond\"\n\nThe commit message provides additional context: \"Fixing EXT port read logic, which caused 'Hyokkori Hyoutanjima: Daitouryou wo Mezase!' input to not work.\"\n\n### Comments\n\n**iequalshane** (Contributor) commented on January 1, 2021:\nThe author referenced issue #154, indicating this PR resolves a problem where a specific game cartridge was unresponsive.\n\n### Linked Issue\n\n**Issue #154:** \"Hyokkori Hyoutanjima (J) bin/md doesn't respond\"\n\nThis pull request was intended to close this issue by correcting the EXT port reading logic that prevented proper input handling for the referenced game.\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/MiSTer-devel_Genesis_MiSTer_pr160", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/MiSTer-devel_Genesis_MiSTer_pr160.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/MiSTer-devel_Genesis_MiSTer_pr160", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/MiSTer-devel_Genesis_MiSTer_pr160"}
{"instance_id": "MiSTer-devel_MegaDrive_MiSTer_pr58", "issue_text": "# Incorrect button mapping for Master System games\n\nUsing a Mega Drive controller to play Master System games on either Mega Drive or Master System hardware, the Master System buttons 1 and 2 map to Mega Drive B and C respectively.\nThis is also handled correctly by the core using controllers via SNAC.\n\nHowever, MiSTer mapped controllers configured for the Mega Drive core use A for 1, and B for 2, rather than B and C.\n\nThis can of course be worked around by remapping a Mega Drive style modern controller every time you go between Mega Drive and Master System games if the original inputs are sought, but corrected mapping would be convenient.\n\nMany thanks\n\n---\n\n## Pull Request\n\n**PR Title:** Fix SMS Megadrive pad mapping\n\n**PR Number:** #58\n\n**Status:** Merged\n\n**Author:** birdybro\n\n**Merged by:** sorgelig on Feb 10, 2025\n\n**Branch:** birdybro:sms_pad_io_fix → MiSTer-devel:main\n\n### Description\n\nThe pull request resolves issue #57 regarding incorrect button mapping for Master System games. The PR contained 1 commit (93a6c50) that addressed the SMS pad input/output configuration problem.\n\n### Linked Issue\n\n**Issue #57:** \"Incorrect button mapping for Master System games\"\n\n### Participants\n\n- birdybro (Author)\n- sorgelig (Reviewer/Merger)\n\n### Notes\n\nNo detailed description text, reviews, or additional comments beyond the issue reference were provided in the pull request thread. The fix was straightforward and successfully merged into the main branch without complications.\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/MiSTer-devel_MegaDrive_MiSTer_pr58", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/MiSTer-devel_MegaDrive_MiSTer_pr58.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/MiSTer-devel_MegaDrive_MiSTer_pr58", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/MiSTer-devel_MegaDrive_MiSTer_pr58"}
{"instance_id": "MiSTer-devel_NES_MiSTer_pr121", "issue_text": "# Digital Devil Monogatari Megami Tensei #76\n\n- Source URL: https://github.com/MiSTer-devel/NES_MiSTer/issues/120\n\nthe game is crashing after game intro\nMapper 76\nonly NES_20181207.rbf works good\n\n---\n\n## Pull Request\n\n**PR Title:** mapper 76 mirroring adjustment #121\n\n**PR Number:** #121\n\n**Status:** Merged\n\n**Author:** Kitrinx\n\n**Merged by:** sorgelig on July 18, 2019\n\n**Commit:** 060b494e61fe4afa492d5c79c8535bd1f73a9f1e\n\n### Description\n\nThe PR description consists solely of a reference to issue #120, stating: \"fixes #120\"\n\n### Comments\n\nKitrinx's comment simply states: \"fixes #120\"\n\n### Linked Issue\n\nThe PR references issue #120, titled \"Digital Devil Monogatari Megami Tensei #76\" (a game that uses mapper 76 cartridge hardware).\n\n### Participants\n\nKitrinx and sorgelig\n\n### Additional Details\n\n- No reviews were conducted\n- No assignees were designated\n- No labels were applied\n- No milestone was set\n\nThe pull request appears to be a focused technical fix addressing mirroring behavior for NES mapper 76 cartridges.\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/MiSTer-devel_NES_MiSTer_pr121", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/MiSTer-devel_NES_MiSTer_pr121.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/MiSTer-devel_NES_MiSTer_pr121", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/MiSTer-devel_NES_MiSTer_pr121"}
{"instance_id": "MiSTer-devel_NES_MiSTer_pr132", "issue_text": "# Maharaja (FC):  Visual Glitches on boot.\n\n- Source URL: https://github.com/MiSTer-devel/NES_MiSTer/issues/131\n\nGame has visual glitches on boot and when in game is mainly a black screen with some glitched sprites.\n\n---\n\n## Pull Request\n\n**PR Title:** Fix mapper 68 mirroring, add battery WRAM support\n\n**PR Number:** #132\n\n**Status:** Merged on Aug 22, 2019\n\n### Description\n\nThe PR addresses issue #131 regarding the Maharaja game experiencing \"visual glitches on boot.\" The contributor verified that saving functionality works properly and that data is correctly backed up to the SD card.\n\n### Key Comments\n\n**paulb-nl** provided technical clarification: The `prg_bus_write` function wasn't necessary since `prg_dout` is consistently FF and doesn't require bus output. Open bus behavior functions correctly—when RAM reads are disabled at $6000-$7FFF, `prg_allow` becomes false, returning open bus data.\n\n**MP2E** confirmed this was the final version after incorporating feedback, noting they added explanatory comments before merge approval.\n\n**sorgelig** (maintainer) asked whether the PR was finalized before merging the single commit.\n\n### Linked Issue\n\n**#131: Maharaja (FC): Visual Glitches on boot**\n\n### Participants\n\nMP2E (contributor), paulb-nl (reviewer), sorgelig (maintainer)\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/MiSTer-devel_NES_MiSTer_pr132", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/MiSTer-devel_NES_MiSTer_pr132.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/MiSTer-devel_NES_MiSTer_pr132", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/MiSTer-devel_NES_MiSTer_pr132"}
{"instance_id": "MiSTer-devel_NES_MiSTer_pr135", "issue_text": "# Indiana Jones 3 glitchy title screen\n\n- Source URL: https://github.com/MiSTer-devel/NES_MiSTer/issues/129\n\nIndiana Jones and The Last Crusade (Taito) shows some flickering lines that shouldn't be there in the title screen.\n\n---\n\n## Pull Request\n\n**PR Title:** Timing fixes\n\n**PR Number:** #135\n\n**Status:** Merged on Sep 15, 2019\n\n### Description\n\nKitrinx's initial comment detailed the changes:\n\n> \"Several timing related fixes. Passes 3 more tests. Resolves #129 (Indiana Jones) Resolves flickering line on Zelda 2 title screen Resolves colored line on Micro Machines title screen\"\n\nThe PR also addressed preliminary support for Mapper 4, submacker 3 (Acclaim's MMC3) for games including Mickey's Safari in Letterland and Incredible Crash Dummies. Additionally, it fixed SNAC controller swap issues and cleaned up compiler warnings.\n\n### Comments\n\n**MP2E** responded positively: \"Outstanding work\"\n\n**Kitrinx** added: The update also resolved SNAC controller swap issues and cleaned up several warnings.\n\n**yxkalle** expressed gratitude: \"Thank you very much\"\n\n### Linked Issues\n\nThe PR resolved **#129**: \"Indiana Jones 3 glitchy title screen\"\n\n### Participants\n\nKitrinx (author), sorgelig (merged), MP2E, yxkalle\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/MiSTer-devel_NES_MiSTer_pr135", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/MiSTer-devel_NES_MiSTer_pr135.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/MiSTer-devel_NES_MiSTer_pr135", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/MiSTer-devel_NES_MiSTer_pr135"}
{"instance_id": "MiSTer-devel_NES_MiSTer_pr147", "issue_text": "# Twin Dragons graphics corruption\n\n- Source URL: https://github.com/MiSTer-devel/NES_MiSTer/issues/146\n\nIn Twin Dragons ([https://www.brokestudio.fr/en/shop/twin-dragons-2/](url)) you encounter signs that activate a tutorial screen. Exiting out of one will result in a corrupted screen. Walking away and back restores the correct graphics.\n\n![IMG_4706](https://user-images.githubusercontent.com/22001441/68591018-10b01b80-0490-11ea-8d09-7b2770e6ad9b.jpg)\n![IMG_4707](https://user-images.githubusercontent.com/22001441/68591027-1443a280-0490-11ea-9556-6788ae429acb.jpg)\n![IMG_4708](https://user-images.githubusercontent.com/22001441/68591042-1c034700-0490-11ea-85a7-b08c61525241.jpg)\n![IMG_4709](https://user-images.githubusercontent.com/22001441/68591046-1e65a100-0490-11ea-9ccd-34042d80b0f5.jpg)\n\n---\n\n## Pull Request\n\n**PR Title:** mapper 30: fix Twin Dragons graphical corruption\n\n**PR Number:** #147\n\n**Status:** Merged on November 15, 2019\n\n**Author:** MP2E\n\n**Merge Commit:** a4b54f5\n\n### Description\n\nThe PR description states: \"fixes #146\"\n\nThe contributor tested the fix with several mapper 30 games including Battle Kid 2, Mystic Origins, and Trollburner Demo.\n\n### Comments\n\n**MP2E (Contributor)** - November 14, 2019:\n\"fixes #146\n\nTested with a few other mapper 30 games too, including Battle Kid 2, Mystic Origins, Trollburner Demo\"\n\n**sorgelig (Maintainer)** - November 15, 2019:\nMerged the pull request.\n\n**MP2E** - November 15, 2019:\nDeleted the mapper30fix branch following the merge.\n\n### Linked Issue\n\n**Issue #146:** \"Twin Dragons graphics corruption\"\n\nThis issue was successfully closed by the merged pull request.\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/MiSTer-devel_NES_MiSTer_pr147", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/MiSTer-devel_NES_MiSTer_pr147.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/MiSTer-devel_NES_MiSTer_pr147", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/MiSTer-devel_NES_MiSTer_pr147"}
{"instance_id": "MiSTer-devel_NES_MiSTer_pr187", "issue_text": "# Glitchy line in StarTropics\n\n- Source URL: https://github.com/MiSTer-devel/NES_MiSTer/issues/149\n\nCan be seen in dungeons in the HUD, here's a video, it's in the bottom right near the hearts:\nhttps://streamable.com/upnul\n\nVideo of console to compare:\nhttps://youtu.be/8b7x30_E0Ko?t=168\n\nI noticed in the footage of the console, when they transition between rooms the same glitchy line appears for a moment but goes away in the rooms themselves\n\n---\n\n## Pull Request\n\n**PR Title:** fix startropics line\n\n**PR Number:** #187\n\n**Status:** Merged on May 23, 2020\n\n### Description\n\nThe PR description states: \"Fix #149 and also glitchy line in Incredible crash dummies.\"\n\n### Comments\n\n**Kitrinx** (May 23, 2020):\nNoted the fix addresses issue #149 regarding a glitchy line in StarTropics, with an additional fix for a similar issue in Incredible Crash Dummies.\n\n**sorgelig** (May 23, 2020):\nMerged the commit (cf35775) into the master branch.\n\n**Kitrinx** (June 6, 2020):\nDeleted the startropics branch following the merge.\n\n### Linked Issue\n\n**Issue #149:** \"Glitchy line in StarTropics\" — This was successfully closed by merging this pull request.\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/MiSTer-devel_NES_MiSTer_pr187", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/MiSTer-devel_NES_MiSTer_pr187.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/MiSTer-devel_NES_MiSTer_pr187", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/MiSTer-devel_NES_MiSTer_pr187"}
{"instance_id": "MiSTer-devel_NES_MiSTer_pr436", "issue_text": "# More Glider (mapper 30) - continue feature not functioning\n\n- Source URL: https://github.com/MiSTer-devel/NES_MiSTer/issues/435\n\nMiSTer Main: 20250828\nNES core: 20251013\n\nMore Glider (USA) (Aftermarket) (Unl).nes\nCRC32: 4ED588CE\n\nMore Glider is an aftermarket NES game released by retroUSB, inspired by a classic shareware game Glider for Macintosh computers. More Glider itself is an updated release of an older aftermarket NES game, called simply Glider (incompatible with the MiSTer core since it uses mapper 29), featuring among other differences multiple new levels. The goal of the game is to navigate a paper airplane across multiple rooms in a house, avoiding other objects or falling to the ground.\n\nThe game features a continue feature. Upon running out of lives, player is moved to a simple room containing two chutes on the ceiling, marked as Continue and Reset. Entering the first chute returns player to the previous room in the game, while entering the second chute restarts the game from the first room.\n\n<img width=\"283\" height=\"242\" alt=\"Image\" src=\"https://github.com/user-attachments/assets/aa57ec9a-90a9-4098-a650-e2af5a43e993\" />\n\nOn the NES core this feature is broken. Entering the Continue chute just restarts this intermediate room, trapping player in a loop with an only exit being exiting through the Reset chute and restarting the game.\n\nThe game behaves correctly in Mesen emulator. The game features a battery save feature, remembering the latest room visited and loading it instead of the first room of a house after restarting console. I presume that this may be related to the issue, since the MiSTer core does not appear to save anything during gameplay. Maybe the game fails to write the room id in save memory, and then the continue screen tries to fetch a room to load afterwards from an invalid value?\n\nHeader information:\n<img width=\"480\" height=\"315\" alt=\"Image\" src=\"https://github.com/user-attachments/assets/c06764b5-e556-4031-9da6-957468192471\" />\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/MiSTer-devel_NES_MiSTer_pr436", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/MiSTer-devel_NES_MiSTer_pr436.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/MiSTer-devel_NES_MiSTer_pr436", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/MiSTer-devel_NES_MiSTer_pr436"}
{"instance_id": "MiSTer-devel_NES_MiSTer_pr438", "issue_text": "# Dungeons & DoomKnights (mapper #30) won't save\n\n- Source URL: https://github.com/MiSTer-devel/NES_MiSTer/issues/282\n\nThis game was made with NESMaker and it uses mapper 30 + some very obnoxious way of saving (\"self-flashing\"):\n\nhttps://github.com/SourMesen/Mesen/issues/753\n\nHaving at least save state enabled for Mapper 30 should be sufficient IMHO, as the way the game saves is really invasive and non-standard, so probably not worth supporting it through quirks.\n\n---\n\n## Pull Request\n\n**PR Title:** Persistent flash saving for mappers 30 and 111\n\n**PR Number:** #438\n\n**Status:** Merged\n\n**Author:** littlegamer87\n\n**Merged by:** sorgelig on November 9, 2025\n\n### Description\n\nThe contributor implemented flash save persistence by treating `prg_rom` as save memory for certain mappers. Key changes include:\n\n- Added a mapper flag `has_flashsaves` to enable flash save functionality\n- When activated, the core creates full dump save files without modifying the installed ROM\n- Expanded signal sizes to accommodate 512KB saves\n- Applied the feature to mappers 30 and 111\n- Flash saves open through the OSD interface like standard saves, though they require additional time due to file size\n\nThis resolves two reported issues where games using these mappers couldn't persist save data.\n\n### Linked Issues\n\n- **#282:** \"Dungeons & DoomKnights (mapper #30) won't save\"\n- **#284:** \"Anguna: Scourge of the Goblin King is not saving\"\n\n### Activity\n\n**Reactions:** 2 hooray emojis\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/MiSTer-devel_NES_MiSTer_pr438", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/MiSTer-devel_NES_MiSTer_pr438.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/MiSTer-devel_NES_MiSTer_pr438", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/MiSTer-devel_NES_MiSTer_pr438"}
{"instance_id": "MiSTer-devel_NES_MiSTer_pr441", "issue_text": "# Mapper 64 (RAMBO-1) Klax graphic glitches\n\n- Source URL: https://github.com/MiSTer-devel/NES_MiSTer/issues/439\n\nReported through Reddit: https://www.reddit.com/r/MiSTerFPGA/comments/1oguj3h/klax_usa_on_nes_core_graphics_issue/\n\nhttps://github.com/user-attachments/assets/7943bcf7-c733-480c-bffd-2271be30bc34\n\n---\n\n## Pull Request\n\n**PR Title:** Mapper 64 (Rambo1): Fix irq (Klax)\n\n**PR Number:** #441\n\n**Status:** Merged\n\n**Merged by:** sorgelig on November 11, 2025\n\n### Description\n\nThe contributor rewrote the interrupt handling according to NES documentation and emulator source code. The changes resolved graphical corruption issues in the game Klax while maintaining compatibility with two other affected titles (Hard Drivin and Skull & Crossbones).\n\n### Comments\n\n**littlegamer87** (November 10, 2025):\n\"Rewrote irq according to nesdev wiki and nintendulator source. The glitches in Klax are gone, the other 2 games impacted (Hard Drivin and Skull & Crossbones) run fine.\"\n\n### Linked Issue\n\n**Issue #439:** \"Mapper 64 (RAMBO-1) Klax graphic glitches\"\n\nThis pull request was intended to close that issue addressing display problems in the Klax game on the NES emulation layer.\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/MiSTer-devel_NES_MiSTer_pr441", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/MiSTer-devel_NES_MiSTer_pr441.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/MiSTer-devel_NES_MiSTer_pr441", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/MiSTer-devel_NES_MiSTer_pr441"}
{"instance_id": "MiSTer-devel_NES_MiSTer_pr448", "issue_text": "# Mapper 243 has corrupted graphics (Honey Peach)\n\n- Source URL: https://github.com/MiSTer-devel/NES_MiSTer/issues/446\n\nMapper 243 is listed as being both supported and with save states, but the only game that it supports, Honey Peach, has corrupted graphics.\n\n---\n\n## Pull Request\n\n**PR Title:** Mapper 141: Add 8KB unbanked CHR-RAM variant (Q boy), mapper 243: Fix CHR addressing (Honey Peach)\n\n**PR Number:** #448\n\n**Status:** Merged on Dec 19, 2025\n\n### Description\n\nThe contributor notes that the unlicensed Sachen game Q Boy uses \"a unique mapper\" recognized as mapper 141. The PR enables \"8KB unbanked CHR-RAM this game needs when CHR-RAM flags are set in the header.\" Headers in the no-intro set are reported as correctly configured.\n\nThe submission also includes a fix for mapper 243, which affects only one game.\n\n### Linked Issues\n\n1. **#447** — Mapper 141 has corrupted graphics (Q Boy)\n2. **#446** — Mapper 243 has corrupted graphics (Honey Peach)\n\n### Comments\n\nThe pull request received no written comments from reviewers. User @sorgelig merged the code, and @theypsilon pushed a related commit to the unstable nightlies branch on Dec 19, 2025.\n\n### Participants\n\nlittlegamer87, sorgelig\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/MiSTer-devel_NES_MiSTer_pr448", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/MiSTer-devel_NES_MiSTer_pr448.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/MiSTer-devel_NES_MiSTer_pr448", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/MiSTer-devel_NES_MiSTer_pr448"}
{"instance_id": "MiSTer-devel_S32X_MiSTer_pr42", "issue_text": "# Star Wars Arcade hangs in second level\n\n- Source URL: https://github.com/MiSTer-devel/S32X_MiSTer/issues/12\n\nGot up to the second level where you destroy TIE fighters with the Star Destroyers attacking you.\n\nIt froze after about thirty seconds of play with the music still going. After leaving it for about a few minutes, the music froze as well.\n\nUsing a Digital I/O board and a Dual SDRAM set up.\n\nEDIT: So switching the ROM Storage to SDRAM seems to have fixed the freezing for now. Been playing for ten minutes since then and no freeze. Playing this for now, one would have to switch ROM Storage to SDRAM\n\n---\n\n## Pull Request\n\n**PR Title:** SH: update to latest from https://github.com/srg320/SH\n\n**PR Number:** #42\n\n**Status:** Merged\n\n**Merged by:** sorgelig on October 1, 2022\n\n### Description\n\nThe pull request updates the SH component to the latest version, incorporating two commits from the upstream repository (srg320/SH):\n- Commit 79fbc3e\n- Commit 8189424\n\nA test build was provided as S32X.rbf.zip (https://github.com/MiSTer-devel/S32X_MiSTer/files/9690221/S32X.rbf.zip).\n\n### Linked Issues\n\nThis merge potentially resolves three issues:\n1. Issue #36: \"Star Wars Arcade - Randomly Crashes on Attract Mode, both JP and US versions\"\n2. Issue #12: \"Star Wars Arcade hangs in second level\"\n3. Issue #31: \"Star Wars Arcade\"\n\n### Participants\n\n- makigumo (contributor): Created the pull request\n- sorgelig: Merged the changes and approved them\n\nNo additional reviews or comments were documented in the conversation thread.\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/MiSTer-devel_S32X_MiSTer_pr42", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/MiSTer-devel_S32X_MiSTer_pr42.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/MiSTer-devel_S32X_MiSTer_pr42", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/MiSTer-devel_S32X_MiSTer_pr42"}
{"instance_id": "MiSTer-devel_S32X_MiSTer_pr44", "issue_text": "# Amazing Spider-Man, The - Web of Fire (USA) hang on first level\n\n- Source URL: https://github.com/MiSTer-devel/S32X_MiSTer/issues/9\n\nThe game hang on first level.\nAmazing Spider-Man, The - Web of Fire (USA)\nCRC: 29DCE257\n\n![IMG_20220421_111050](https://user-images.githubusercontent.com/52424890/164453950-d9b95872-d532-4b83-99f2-a7f4b4ea8a9e.jpg)\n)\n\n---\n\n## Pull Request\n\n**PR Title:** Latest cpu updates\n\n**PR Number:** #44\n\n**Status:** Merged on Nov 8, 2022\n\n### Description\n\nLatest CPU updates were sourced from an external repository. The contributor noted that testing indicated the changes resolved three reported issues: #9, #27, and #25. A test core file was provided for community testing.\n\n### Commits (4 total)\n\n1. Update files - fixes interrupts and FRT status flag clearing\n2. SH: fix DIVU busy\n3. Fix ADDV/SUBV opcodes\n4. Fix interrupt accepted timing\n\n### Linked Issues Resolved\n\n- \"Spider-Man Web of Fire\" - SH2 exception on first level (#27)\n- \"World Series Baseball starring Deion Sanders\" - SH2 engine error (#25)\n- \"Amazing Spider-Man, The - Web of Fire\" - hang on first level (#9)\n\n### Participants\n\nmakigumo (contributor), sorgelig (merger), srg320 (original author)\n\n### Key Details\n\nThe branch was deleted after successful merge. No formal reviews were recorded.\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/MiSTer-devel_S32X_MiSTer_pr44", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/MiSTer-devel_S32X_MiSTer_pr44.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/MiSTer-devel_S32X_MiSTer_pr44", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/MiSTer-devel_S32X_MiSTer_pr44"}
{"instance_id": "MiSTer-devel_Saturn_MiSTer_pr249", "issue_text": "# [FEATURE REQUEST] (Shuttle) Mouse support\n\n- Source URL: https://github.com/MiSTer-devel/Saturn_MiSTer/issues/146\n\nSome users have asked on the Discord if it would be possible to support the Shuttle mouse (or even just a more basic mouse) on the core in the future.\n\n---\n\n## Pull Request\n\n**PR Title:** Shuttle mouse support\n\n**PR Number:** #249\n\n**Status:** Merged\n\n**Merged by:** srg320 on Sep 18, 2024\n\n### Description\n\nThe pull request implements mouse support for Saturn games. Key features include:\n\n- Maps USB mice to player 1/player 2 Saturn Shuttle mouse functionality\n- Fixes joypad analog stick behavior when used as a mouse\n- Enables input merging between USB mouse and joypad, allowing seamless switching during gameplay\n- Maps left/middle/right USB mouse buttons to corresponding Shuttle Mouse buttons\n- Routes additional USB mouse buttons (side buttons, etc.) to function as the 4th button/Start\n- Scales joypad analog sensitivity to 37.5% to prevent oversensitivity\n\nThis addresses issue #146, a feature request for Shuttle Mouse support.\n\n### Comments\n\n**Zet-sensei** (Sep 17, 2024): Confirmed working functionality across multiple titles including Virtua Cop series, Tokimeki Memorial, Sakura Taisen series, Dokyuusei variants, and Policenauts.\n\n**rattboi** (Sep 18, 2024): Provided compiled RBF file link for easy access.\n\n### Linked Issue\n\n**#146:** \"[FEATURE REQUEST] (Shuttle) Mouse support\" — Successfully closed by this merge.\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/MiSTer-devel_Saturn_MiSTer_pr249", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/MiSTer-devel_Saturn_MiSTer_pr249.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/MiSTer-devel_Saturn_MiSTer_pr249", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/MiSTer-devel_Saturn_MiSTer_pr249"}
{"instance_id": "MiSTer-devel_ao486_MiSTer_pr118", "issue_text": "# King's Quest VII won't go to menu after core update\n\n- Source URL: https://github.com/MiSTer-devel/ao486_MiSTer/issues/117\n\nFull discussion here\nhttps://misterfpga.org/viewtopic.php?p=49685#p49685\n\nGame freeze befor geting to the menu. Logo works fine but after that there is a soft freeze.\n\nLast working core was from October 10 2021. All cores after that result in game freeze.\n\nSuspected reasons is this update, from February 11 2022:\n\nao486:\n- sound: Add busy wait to write port status on DSP (user7182).\n\nFound here\nhttps://misterfpga.org/viewtopic.php?p=43913#p43913\n\n## Fetched Issue/PR Details\n\nTitle: King's Quest VII won't go to menu after core update (#117)\n\nDescription: The user reports that King's Quest VII freezes before reaching the main menu in the ao486_MiSTer core. The game's logo displays correctly, then the system becomes unresponsive. The last functional core version was from October 10, 2021, with all subsequent versions causing the freeze. The user suspects an update from February 11, 2022, regarding sound: \"Add busy wait to write port status on DSP (user7182)\" as the likely culprit.\n\nAdditional Context:\n- Discussion link provided: https://misterfpga.org/viewtopic.php?p=49685#p49685\n- Suspect commit reference: https://misterfpga.org/viewtopic.php?p=43913#p43913\n- Issue opened: April 29, 2022\n- Status: Closed (with linked PR #118)\n\nComments: The page indicated this issue has been resolved through PR #118; specific comments and resolution details were not visible.\n\nLinked Issues: Resolving PR #118.\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/MiSTer-devel_ao486_MiSTer_pr118", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/MiSTer-devel_ao486_MiSTer_pr118.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/MiSTer-devel_ao486_MiSTer_pr118", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/MiSTer-devel_ao486_MiSTer_pr118"}
{"instance_id": "MiSTer-devel_ao486_MiSTer_pr172", "issue_text": "# BOOM and Allegro freeze\n\n- Source URL: https://github.com/MiSTer-devel/ao486_MiSTer/issues/128\n\nTested in working DOS 6.22 and FreeDOS environments. All versions of BOOM and Allegro (ASETUP, the setup EXE) freeze when I try to run them. It locks at a blinking cursor, I've waited for 10 minutes or so.\n\n(DOOM and DOOM2 all work in FreeDOS just fine.)\n\nThis is the version that comes packaged with other versions of FreeDOS, plus I have tried the classic version of BOOM available online.\n\n## Fetched Issue/PR Details\n\nTitle: BOOM and Allegro freeze (#128)\n\nDescription: The reporter tested BOOM and Allegro (including the ASETUP setup executable) in working DOS 6.22 and FreeDOS environments. When attempting to run these applications, they \"freeze when I try to run them. It locks at a blinking cursor, I've waited for 10 minutes or so.\" The user notes that DOOM and DOOM2 work fine in FreeDOS. They tested both the version packaged with FreeDOS and the classic BOOM version available online, with the same freezing behavior occurring.\n\nStatus: Closed (linked to PR #172)\n\nComments: None visible on the page.\n\nLinked Issues: Resolving PR #172.\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/MiSTer-devel_ao486_MiSTer_pr172", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/MiSTer-devel_ao486_MiSTer_pr172.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/MiSTer-devel_ao486_MiSTer_pr172", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/MiSTer-devel_ao486_MiSTer_pr172"}
{"instance_id": "MiSTer-devel_ao486_MiSTer_pr185", "issue_text": "# HIRAM issue with Release 20241227\n\n- Source URL: https://github.com/MiSTer-devel/ao486_MiSTer/issues/177\n\nHIRAM does not seem to work in the latest release (20241227).\n\nFor example, the top300 image with the previous core release in HIRAM mode had  627K of base memory:\n\nThe exact same image and settings with the latest core release results in only 529K, with nothing being loaded into upper mem:\n\nThis prevents many games to load. EMM386 and QEMM memory modes seem to work fine. Only HIRAM seems affected. At least two users have confirmed this issue with different DOS versions (6.2.2 and Win98 embedded DOS)\n\nCould this be related to the recent commit  #169 ?\n\n## Fetched Issue/PR Details\n\nTitle: HIRAM issue with Release 20241227 (#177)\n\nDescription: The reporter notes that HIRAM memory mode is not functioning properly in the latest core release. When running the top300 DOS image with HIRAM enabled, base memory decreased from 627K in the previous release to 529K in version 20241227, with nothing being loaded into upper memory. The issue affects game loading and has been confirmed by multiple users with different DOS versions (6.2.2 and Win98 embedded DOS). EMM386 and QEMM memory modes continue working normally. The reporter suspects this may be related to commit #169.\n\nStatus: Closed (with PR #185 linked as resolution)\nAuthor: ruenes1\nOpened: December 27, 2024\n\nComments: The issue body included comparative screenshots showing the memory difference between the two releases, but no comments or discussion text appeared on the page.\n\nLinked Issues: Resolving PR #185; suspected regression from #169.\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/MiSTer-devel_ao486_MiSTer_pr185", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/MiSTer-devel_ao486_MiSTer_pr185.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/MiSTer-devel_ao486_MiSTer_pr185", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/MiSTer-devel_ao486_MiSTer_pr185"}
{"instance_id": "MiSTer-devel_ao486_MiSTer_pr188", "issue_text": "# Last OPL music note keeps playing forever on core reboot\n\n- Source URL: https://github.com/MiSTer-devel/ao486_MiSTer/issues/174\n\nHello there,\n\nI noticed that, as the tittle says, if a program is playing an OPL music note an the core is reboot, that last note keeps sounding forever, until a new program resets the OPL.\n\n@humply Can you see this bug too?\n\n## Fetched Issue/PR Details\n\nTitle: OPL3: fix envelope RELEASE state on reset (PR #188)\n\nDescription: The pull request addresses a regression introduced in commit e881af1 where envelopes should transition to RELEASE state instead of remaining in SUSTAIN, causing notes to play indefinitely after reset. The fix involves resetting the key-on signal itself, as it is no longer edge-detected. Closes issue #174.\n\nStatus: Merged by sorgelig on Feb 24, 2025\n\nComments:\n- gtaylormb (Feb 23, 2025): Provided the original description with context about the regression and fix approach.\n- vanfanel (Feb 25, 2025): \"Sadly this doesn't fix #174 completely, a low-frequency tone keeps playing after resetting an OPL game.\" Reports that despite the merge, a residual tone persists after core reset via CTRL+ALT+SUP in games like Prince of Persia, though menu-based resets work correctly.\n\nLinked Issues: Closes #174 (\"Last OPL music note keeps playing forever on core reboot\").\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/MiSTer-devel_ao486_MiSTer_pr188", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/MiSTer-devel_ao486_MiSTer_pr188.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/MiSTer-devel_ao486_MiSTer_pr188", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/MiSTer-devel_ao486_MiSTer_pr188"}
{"instance_id": "MiSTer-devel_ao486_MiSTer_pr72", "issue_text": "# Tie Fighter CD Joystick buttons not responding\n\n- Source URL: https://github.com/MiSTer-devel/ao486_MiSTer/issues/30\n\nAfter the update from August 16th 2020 the Joystick is finally detected in Tie Fighter CD but it isn't responding to any button press. It works fine in X-Wing and Tie Figher.\n\n## Fetched Issue/PR Details\n\nTitle: Tie Fighter CD Joystick buttons not responding (#30)\n\nDescription: \"After the update from August 16th 2020 the Joystick is finally detected in Tie Fighter CD but it isn't responding to any button press. It works fine in X-Wing and Tie Figher.\"\n\nStatus: Closed (linked to PR #72)\nReporter: Chris5523\nOpened: August 16, 2020\n\nComments: No comments visible on the page.\n\nLinked Issues: Resolving PR #72. The joystick hardware was recognized after an update but failed to respond to input in this specific game variant, while functioning properly in related titles.\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/MiSTer-devel_ao486_MiSTer_pr72", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/MiSTer-devel_ao486_MiSTer_pr72.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/MiSTer-devel_ao486_MiSTer_pr72", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/MiSTer-devel_ao486_MiSTer_pr72"}
{"instance_id": "MiSTle-Dev_MiSTeryNano_pr99", "issue_text": "# Does second hid joystick work?\n\n- Source URL: https://github.com/MiSTle-Dev/MiSTeryNano/issues/97\n\nI've connected two USB gamepads via raspberry pico and I see in logs JOY0 and JOY1 that send command to FPGA, but when I wanted to test two joysticks in a game. Second one never works, so I tried to understand if second joystick port is supported on FPGA, so started reading Verilog (I'm beginner) and I found in misterynano.sv this:\n\n        .joystick0(hid_joy),\n        .joystick1()\n\nDoes it means that joystick1 (second joy) is not wired to hid data, which means second joy is not implemented?\n\nIf my analysis is correct, do you plan to implement second hid joy support?\n\n---\n\n## Pull Request\n\n**PR Title:** Add support for second usb joy and auto switch between joystick and mouse #99\n\n**PR Number:** #99\n\n**Status:** Merged\n\n### Description\n\nThe contributor's opening statement explains: \"Please find changes adding support for second HID joystick. I also added possibility in menu to switch between mapping HID joy to ports.\"\n\nThe implementation addresses several goals:\n\n1. **Dual joystick support** – Enables configuration where a DB9 joystick operates on port 2 while an HID joystick functions on port 1, allowing two-player gameplay.\n\n2. **Input switching mechanism** – Since joystick and mouse cannot operate simultaneously on port 1, the solution activates either device when its button is pressed, disabling the alternate input method.\n\n3. **Testing validation** – The author confirmed functionality \"works great and tested on Bubble bobble.\"\n\n### Comments\n\n**harbaum (Collaborator)** merged the PR and noted: \"Again, thanks a lot. And yes, switching between mouse and joystick via the buttons is how those auto-switchers back in the day also worked.\"\n\n**pawelka (Author)** responded: \"I haven't know that there where any auto switchers in a past, I switched manually in my Atari.\"\n\n**harbaum** later added: \"A fixed a small issue where the register with was 2 bit instead of 1.\"\n\n### Linked Issue\n\nThis PR closes **Issue #97:** \"Does second hid joystick work?\"\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/MiSTle-Dev_MiSTeryNano_pr99", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/MiSTle-Dev_MiSTeryNano_pr99.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/MiSTle-Dev_MiSTeryNano_pr99", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/MiSTle-Dev_MiSTeryNano_pr99"}
{"instance_id": "Multimedia-Processing_Digital-Logic-Design_pr46", "issue_text": "# 6-3 多工器與解多工器的實習\n\n- Source URL: https://github.com/Multimedia-Processing/Digital-Logic-Design/issues/44\n\n1. 明瞭多工器的原理與電路設計的方法\n2. 明瞭解多工器的原理與電路設計的方法\n3. 學習解多工器與解碼器的互用方式\n4. 學習直接套用制式IC完成所需\n\n---\n\n## Pull Request\n\n**PR Title:** 44 ch6 3 multiplexer and demultiplexer\n\n**PR Number:** #46\n\n**Status:** Merged on November 19, 2020\n\n**Author:** timmy61109\n\n### Description\n\nNo description provided in the pull request.\n\n### Commit Summary\n\nThe PR contains 20 commits addressing Chapter 6, Section 3 of a digital logic design project. Key commits include:\n\n- Implementation of 2-to-1 multiplexers and 4-to-2 multiplexers\n- Creation of a 4-to-1 multiplexer using three 2-to-1 multiplexers\n- Development of verification circuits for waveform testing\n- Implementation of 1-bit full adder (gate-level description)\n- Construction of 2-to-4 demultiplexer using IC 74139\n- Construction of 1-to-16 demultiplexer using IC 74139\n\n### Metadata\n\n- Labels: Documentation, Enhancement\n- Milestone: Chapter 6 (數位邏輯實習 FPGA篇)\n- Linked Issue: #44 \"6-3 多工器與解多工器的實習\" (Multiplexer and Demultiplexer Practice)\n- Assignee: timmy61109\n- Reviewers: None listed\n\n### Notes\n\nThe PR involved numerous file deletions and updates to the gitignore file for Vivado-generated directories. The branch \"44-CH6-3-multiplexer-and-demultiplexer\" was deleted after merging into master.\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/Multimedia-Processing_Digital-Logic-Design_pr46", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/Multimedia-Processing_Digital-Logic-Design_pr46.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/Multimedia-Processing_Digital-Logic-Design_pr46", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/Multimedia-Processing_Digital-Logic-Design_pr46"}
{"instance_id": "Multimedia-Processing_Digital-Logic-Design_pr48", "issue_text": "# 6-3 多工器與解多工器的實習\n\n- Source URL: https://github.com/Multimedia-Processing/Digital-Logic-Design/issues/44\n\n1. 明瞭多工器的原理與電路設計的方法\n2. 明瞭解多工器的原理與電路設計的方法\n3. 學習解多工器與解碼器的互用方式\n4. 學習直接套用制式IC完成所需\n\n---\n\n## Pull Request\n\n**PR Title:** 47 verilog hdl practice ch4\n\n**PR Number:** #48\n\n**Status:** Merged on November 19, 2020\n\n**Author:** timmy61109\n\n**Target:** master branch\n\n**Source Branch:** 47-VerilogHDL-Practice-CH4\n\n### Description\n\nNo description was provided by the author.\n\n### Commits (19 total)\n\nThe pull request contained 19 commits with messages in Traditional Chinese, including:\n\n- Updates to `.gitignore` for Vivado-generated directories\n- Implementation of 2-to-1 and 4-to-2 multiplexers\n- Completion of a 1-bit full adder with gate-level descriptions\n- Four work items related to Chapter 6, Section 3\n- 4-to-1 multiplexer implementation\n- Addition of execution scripts\n\n### Linked Issue\n\nThis PR closes issue #44: \"6-3 多工器與解多工器的實習\" (Chapter 6-3 Multiplexer and Demultiplexer Practice)\n\n### Metadata\n\n- Assigned to: JulianHsia, timmy61109, JulianXia-2020\n- Labels: documentation, enhancement\n- Milestone: Chapter 6\n- Participants: 3 users\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/Multimedia-Processing_Digital-Logic-Design_pr48", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/Multimedia-Processing_Digital-Logic-Design_pr48.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/Multimedia-Processing_Digital-Logic-Design_pr48", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/Multimedia-Processing_Digital-Logic-Design_pr48"}
{"instance_id": "Multimedia-Processing_Digital-Logic-Design_pr50", "issue_text": "# Verilog硬體描述語言實務 第二版 Chapter4\n\n- Source URL: https://github.com/Multimedia-Processing/Digital-Logic-Design/issues/47\n\n- 4-1 基本邏輯閘\n- 4-2 實例說明\n\n練習題\n\n- [x] 1\n- [x] 2\n\n---\n\n## Pull Request\n\n**PR Title:** 47 verilog hdl practice ch4\n\n**PR Number:** #50\n\n**Status:** Merged on November 27, 2020\n\n**Author:** timmy61109\n\n### Description\n\nNo description was provided for this pull request.\n\n### Commits\n\nThe PR contained three commits:\n1. \"如果採用，此提交將新增練習題第一題\" (adds practice problem 1)\n2. \"如果採用，此提交將完成第四章練習題第二題\" (completes Chapter 4 practice problem 2)\n3. \"如果採用，此提交將新增執行的腳本\" (adds execution scripts)\n\n### Labels\n\n- Documentation (improvements/additions to documentation)\n- Enhancement (new feature or request)\n\n### Assignees\n\n- JulianHsia\n- timmy61109\n- JulianXia-2020\n\n### Linked Issue\n\n\"Verilog硬體描述語言實務 第二版 Chapter4\" (#47)\n\n### Milestone\n\nVerilog硬體描述語言實務 第二版\n\n### Comments\n\nNo substantive comments were recorded in the conversation thread.\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/Multimedia-Processing_Digital-Logic-Design_pr50", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/Multimedia-Processing_Digital-Logic-Design_pr50.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/Multimedia-Processing_Digital-Logic-Design_pr50", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/Multimedia-Processing_Digital-Logic-Design_pr50"}
{"instance_id": "Multimedia-Processing_Digital-Logic-Design_pr60", "issue_text": "# Verilog硬體描述語言實務 第二版 Chapter5 資料留層次之敘述\n\n- Source URL: https://github.com/Multimedia-Processing/Digital-Logic-Design/issues/52\n\n- assign連續指定\n- 運算子\n- 綜合範例\n\n---\n\n## Pull Request\n\n**PR Title:** Verilog硬體描述語言實務 第二版 Chapter5 資料留層次之敘述 (#60)\n\n**PR Number:** #60\n\n**Status:** Merged on December 17, 2020\n\n### Description\n\nThe pull request introduces content for Chapter 5 of a Verilog hardware description language textbook (second edition), focusing on dataflow-level descriptions. The contributor listed three main topics:\n\n- assign連續指定 (continuous assignment)\n- 運算子 (operators)\n- 綜合範例 (synthesis examples)\n\n### Key Details\n\n**Author:** timmy61109\n\n**Commits:** 6 commits added between December 3-17, 2020\n\n**Linked Issue:** #52 - \"Verilog硬體描述語言實務 第二版 Chapter5 資料留層次之敘述\"\n\n**Labels:** documentation, enhancement\n\n**Milestone:** Verilog硬體描述語言實務 第二版\n\n### Notable Elements\n\nThe pull request included two example modules: \"vector\" (demonstrating vector access operations) and \"op\" (demonstrating operator calculations). Subsequent commits through 2022 expanded the content with arithmetic micro-operations, test files, presentations, and circuit diagrams.\n\n**Reviewers Requested:** JulianHsia, JulianXia-2020\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/Multimedia-Processing_Digital-Logic-Design_pr60", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/Multimedia-Processing_Digital-Logic-Design_pr60.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/Multimedia-Processing_Digital-Logic-Design_pr60", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/Multimedia-Processing_Digital-Logic-Design_pr60"}
{"instance_id": "Multimedia-Processing_Digital-Logic-Design_pr62", "issue_text": "# Verilog硬體描述語言實務 第二版 Chapter6 行為層次之敘述\n\n- Source URL: https://github.com/Multimedia-Processing/Digital-Logic-Design/issues/61\n\nTitle: Verilog硬體描述語言實務 第二版 Chapter6 行為層次之敘述 #61\n\nBody:\n- 6-1 always 程序結構區塊\n- 6-2 阻隔性與非阻隔性指定敘述\n- 6-3 if-else敘述\n- 6-4 case、casez與casex敘述\n- 6-5 迴圈敘述\n\nComments: None\n\nLinked PR: #62 (closed)\n\nMetadata:\n- Status: Closed\n- Milestone: Verilog硬體描述語言實務 第二版\n\nThis is a task tracking issue for documenting behavioral-level descriptions in a Verilog hardware description language textbook (second edition), specifically Chapter 6, covering procedural blocks, blocking/non-blocking assignments, conditional statements, case statements, and loop constructs.\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/Multimedia-Processing_Digital-Logic-Design_pr62", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/Multimedia-Processing_Digital-Logic-Design_pr62.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/Multimedia-Processing_Digital-Logic-Design_pr62", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/Multimedia-Processing_Digital-Logic-Design_pr62"}
{"instance_id": "Multimedia-Processing_Digital-Logic-Design_pr65", "issue_text": "# Chapter02 Verilog RTL 程式設計\n\n- Source URL: https://github.com/Multimedia-Processing/Digital-Logic-Design/issues/54\n\nTitle: Chapter02 Verilog RTL 程式設計 #54\n\nBody:\n- 2.1 Verilog語言與RTL描述\n- 2.2 Verilog描述敘述對應電路\n- 2.3 如何進行RTL設計\n- 2.4 RTL設計要點\n- 2.5 UART序列埠通訊設計實例\n\nComments: None\n\nMetadata:\n- Assignee: timmy61109\n- Labels: documentation, enhancement\n- Milestone: \"完成軟核心處理器設計 從ARM9到FPGA\" (Complete soft-core processor design from ARM9 to FPGA)\n- Status: Closed (with associated PR #65)\n\nThis issue outlines a documentation task covering Verilog RTL programming fundamentals, including language concepts, circuit mapping, design methodology, best practices, and a practical UART communications example.\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/Multimedia-Processing_Digital-Logic-Design_pr65", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/Multimedia-Processing_Digital-Logic-Design_pr65.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/Multimedia-Processing_Digital-Logic-Design_pr65", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/Multimedia-Processing_Digital-Logic-Design_pr65"}
{"instance_id": "Multimedia-Processing_Digital-Logic-Design_pr68", "issue_text": "# 第七章 組合邏輯電路設計\n\n- Source URL: https://github.com/Multimedia-Processing/Digital-Logic-Design/issues/67\n\nTitle: 第七章 組合邏輯電路設計 #67\n\nBody: 組合邏輯電路(Combinational Logic Circuit)\n\nComments: None\n\nLinked PR: #68 (closed)\n\nMetadata:\n- Assignee: timmy61109\n- Labels: documentation, enhancement\n- Milestone: Verilog硬體描述語言實務 第二版\n- Status: Closed\n\nThis is a documentation issue related to \"Chapter Seven: Combinational Logic Circuit Design\" for a digital logic design educational repository.\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/Multimedia-Processing_Digital-Logic-Design_pr68", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/Multimedia-Processing_Digital-Logic-Design_pr68.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/Multimedia-Processing_Digital-Logic-Design_pr68", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/Multimedia-Processing_Digital-Logic-Design_pr68"}
{"instance_id": "OpenPOWERFoundation_a2o_pr18", "issue_text": "# Fix uncompliant begin in generate blocks\n\nInstance: OpenPOWERFoundation_a2o_pr18\nSource: https://github.com/OpenPOWERFoundation/a2o/pull/18\nFetched: 2026-04-26\nRepository: OpenPOWERFoundation/a2o\nPull request: #18\nAuthor: flaviens\nState: closed\nBase branch: master\nHead branch: fix_begin_genvar\nCreated: 2022-10-26T08:57:01Z\nUpdated: 2022-11-30T00:04:25Z\nClosed: 2022-11-30T00:04:25Z\nMerged: 2022-11-30T00:04:25Z\n\nHi there!\r\n\r\nThis fixes [this Verilog uncompliance issue](https://github.com/pulp-platform/morty/issues/50).\r\n\r\nThanks!\r\nFlavien\n\n## Local Reproducer Notes\n\nOpenPOWERFoundation/a2o PR 18 reproducer.\n\nThe reduced module keeps the PR's generate-block compliance issue observable\nas a design output while also exercising normal sequential behavior.  The buggy\nsnapshot represents an unconditional `generate begin`; the patch changes it to\nthe compliant `generate if (1) begin` form and raises the compliance output.\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/OpenPOWERFoundation_a2o_pr18", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/OpenPOWERFoundation_a2o_pr18.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/OpenPOWERFoundation_a2o_pr18", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/OpenPOWERFoundation_a2o_pr18"}
{"instance_id": "Panda-Cores_PandaZero_pr14", "issue_text": "# C programs\n\nInstance: Panda-Cores_PandaZero_pr14\nSource: https://github.com/Panda-Cores/PandaZero/pull/14\nFetched: 2026-05-03\nRepository: Panda-Cores/PandaZero\nPull request: #14\nAuthor: GorgeousWalrus\nState: closed\nBase branch: master\nHead branch: c_programs\nCreated: 2020-08-05\nUpdated: 2020-08-05\nClosed: 2020-08-05\nMerged: 2020-08-05\n\n## PR Title\nC programs\n\n## PR Description\n(No PR body provided.)\n\n## PR Comments\n\n**GorgeousWalrus** (Aug 5, 2020):\n\"No description provided.\"\n\n## Linked Issues\n\n**Issue #13: AUIPC, JALR, JAL not correct**\nThe above instructions only trigger a jump to the respective address, but the flush happens immediately and thus it is no longer propagated to the other stages. As a result, the PC+4 is not stored and return is not possible.\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/Panda-Cores_PandaZero_pr14", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/Panda-Cores_PandaZero_pr14.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/Panda-Cores_PandaZero_pr14", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/Panda-Cores_PandaZero_pr14"}
{"instance_id": "Panda-Cores_PandaZero_pr3", "issue_text": "# Wishbone integration\n\nInstance: Panda-Cores_PandaZero_pr3\nSource: https://github.com/Panda-Cores/PandaZero/pull/3\nFetched: 2026-05-03\nRepository: Panda-Cores/PandaZero\nPull request: #3\nAuthor: GorgeousWalrus\nState: closed\nBase branch: master\nHead branch: wishbone_integration\nCreated: 2020-07-25\nUpdated: 2020-08-05\nClosed: 2020-07-25\nMerged: 2020-07-25\n\n## PR Title\nWishbone integration\n\n## PR Description\nAdded wishbone to mem & if stage, drastic performance drop when loads & stores are made. To be fixed (hopefully) with faster bus granting and/or caches.\n\n## PR Comments\n\n**GorgeousWalrus** (Jul 25, 2020):\n\"Added wishbone to mem&if stage, drastic performance drop when loads&stores are made. To be fixed (hopefully) with faster bus granting and/or caches\"\n\n## Linked Issues\n\n**Issue #1: Add wishbone to IF & MEM stages**\nMake the IF and MEM stages wishbone masters to enable usage of a wishbone interconnect, which in turn enables memory mapped peripherals.\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/Panda-Cores_PandaZero_pr3", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/Panda-Cores_PandaZero_pr3.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/Panda-Cores_PandaZero_pr3", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/Panda-Cores_PandaZero_pr3"}
{"instance_id": "Panda-Cores_PandaZero_pr4", "issue_text": "# Dbg module\n\nInstance: Panda-Cores_PandaZero_pr4\nSource: https://github.com/Panda-Cores/PandaZero/pull/4\nFetched: 2026-05-03\nRepository: Panda-Cores/PandaZero\nPull request: #4\nAuthor: GorgeousWalrus\nState: closed\nBase branch: master\nHead branch: dbg_module\nCreated: 2020-07-29\nUpdated: 2020-07-29\nClosed: 2020-07-29\nMerged: 2020-07-29\n\n## PR Title\nDbg module\n\n## PR Description\n(No PR body provided.)\n\n## PR Comments\n\n**GorgeousWalrus** (Jul 29, 2020):\n\"No description provided.\"\n\n## Linked Issues\n\n**Issue #2: Create debug module**\nWrite a debug module to enable easier testing than looking at the waveforms.\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/Panda-Cores_PandaZero_pr4", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/Panda-Cores_PandaZero_pr4.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/Panda-Cores_PandaZero_pr4", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/Panda-Cores_PandaZero_pr4"}
{"instance_id": "Panda-Cores_PandaZero_pr7", "issue_text": "# Dbg module\n\nInstance: Panda-Cores_PandaZero_pr7\nSource: https://github.com/Panda-Cores/PandaZero/pull/7\nFetched: 2026-05-03\nRepository: Panda-Cores/PandaZero\nPull request: #7\nAuthor: GorgeousWalrus\nState: closed\nBase branch: master\nHead branch: dbg_module\nCreated: 2020-08-02\nUpdated: 2020-08-02\nClosed: 2020-08-02\nMerged: 2020-08-02\n\n## PR Title\nDbg module\n\n## PR Description\nDebug module improved, wishbone on newest state.\n\n## PR Comments\n\n**GorgeousWalrus** (Aug 2, 2020):\n\"Debug module improved, wishbone on newest state\"\n\n## Linked Issues\n\n**Issue #5: Upgrade Wishbone**\ncommon repo has new wishbone interfaces, upgrade time!\n\n**Issue #6: upgrade debug module**\n(Closed by this PR; body not available.)\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/Panda-Cores_PandaZero_pr7", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/Panda-Cores_PandaZero_pr7.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/Panda-Cores_PandaZero_pr7", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/Panda-Cores_PandaZero_pr7"}
{"instance_id": "PeterMonsson_sv_waveterm_pr10", "issue_text": "# Clean up examples\n\nInstance: PeterMonsson_sv_waveterm_pr10\nSource: https://github.com/PeterMonsson/sv_waveterm/pull/10\nFetched: 2026-05-03\nRepository: PeterMonsson/sv_waveterm\nPull request: #10\nAuthor: PeterMonsson\nState: closed\nBase branch: main\nHead branch: clean-up-examples\nCreated: 2023-04-01\nUpdated: 2023-04-07\nClosed: 2023-04-01\nMerged: 2023-04-01\n\n## PR Title\nClean up examples\n\n## PR Description\n(No PR body provided beyond the title and the closing reference.)\n\n## PR Comments\n\n**PeterMonsson** (Apr 1, 2023):\n\"Closes #7\"\n\n## Linked Issues\n\n**Issue #7: Basic example: use $error instead of $display**\nRemoved when adding verilator support.\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/PeterMonsson_sv_waveterm_pr10", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/PeterMonsson_sv_waveterm_pr10.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/PeterMonsson_sv_waveterm_pr10", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/PeterMonsson_sv_waveterm_pr10"}
{"instance_id": "SpiNNakerManchester_spif_pr8", "issue_text": "# SpiNNaker peripheral output support\n\n- Source URL: https://github.com/SpiNNakerManchester/spif/issues/4\n\nspif does __not__ currently support SpiNNaker peripheral output.\r\n\r\nSome of the hardware is already in place:\r\n\r\n- The SpiNNaker FPGAs __do__ support peripheral output. The routing is done using peripheral routing key and mask registers.\r\n\r\n- spif demultiplexes SpiNNaker packets into _configuration_ and _peripheral_ streams. Configuration packets are handled by the spif register bank while peripheral packets are simply dumped.\r\n\r\n\r\n**Where should peripheral output be sent to?**\r\n\r\nThe best option seems to be to send them over Ethernet to a peripheral device at a specified IP address/UDP port. There should be registers to hold these values. These registers should be accessible from SpiNNaker and should also be accessible from the peripheral. SpiNNaker should use the existing spif configuration route. Peripheral devices should send a UDP frame to spif directed at a known UDP port and spif will write the sender IP address and UDP port into these registers.\r\n\r\n\r\n**When should peripheral output be sent?**\r\n\r\nA UDP frame sholud be triggered when one of two conditions arises:\r\n1. the memory buffer holding events fills above a high watermark,\r\n2. a periodic timer triggers. The timer period should be configurable through a spif register. A default of 2ms seems adequate.\r\n\r\n\r\n**SpiNNaker packet to peripheral event mapping**\r\n\r\nIt is not clear how spif should map SpiNNaker packet MC keys into peripheral events. Events may even need some form of data value that is carried as SpiNNaker packet payload. Simply reversing the input mapping does __not__ appear to be a good solution.\r\n\r\n\r\n**spif output pipeline microarchitecture**\r\n\r\n- spif HW should receive SpiNNaker packets, map them to peripheral events and store them in a memory buffer previously reserved for this purpose by the spif kernel module. The kernel module currently reserves memory for peripheral input only.\r\n\r\n- spif HW should interrupt spif SW when a UDP frame should be triggered, _i.e._, when one of the conditions listed above is met.\r\n\r\n- when interrupted, spif SW reads peripheral events from the memory buffer and sends them over Ethernet to the registered IP address and UDP port. It may need to send several UDP frames if the number of events exceeds the frame maximum size.\r\n\r\n- spif SW for peripheral output could be incorporated into spiffer as an additional thread.\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/SpiNNakerManchester_spif_pr8", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/SpiNNakerManchester_spif_pr8.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/SpiNNakerManchester_spif_pr8", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/SpiNNakerManchester_spif_pr8"}
{"instance_id": "SpiNNakerManchester_spio_pr40", "issue_text": "# packet store goes empty incorrectly\n\n- Source URL: https://github.com/SpiNNakerManchester/spio/issues/39\n\nThanks to Will Toms, University of Manchester, for spotting and diagnosing this bug.\n\nThe packet store read pointer **br** and the next packet sequence number **bpkt_seq** are **not** updated in the same clock cycle. Instead they are updated in consecutive ones. This opens a one clock cycle window in which the arrival of an **ack** for the very last  packet to be sent can update the ack pointer **ba** incorrectly. The incorrect update manifests only if **br** was updated exactly the cycle before the arrival of the **ack**.\n\nThe consequence is that the next 8 packets to enter the packet store will have already been identified incorrectly as ack'd and, thus, can be overwritten by new packets even before they are transmitted. The observable symptom is that up to 8 packets are \"thrown away\", *i. e.*, not transmitted.\n\nThere is no reason for this update misalignment. Therefore the simplest correct solution is to delay the **br** update one clock cycle so that it coincides with the **bpkt_seq** update.\n\n\n\n\nPR title: Fix packet store ba pointer bug\n\nSource: https://github.com/SpiNNakerManchester/spio/pull/40\n\nPR description:\n\"This pull request fixes the packet store bug documented in issue #39. The solution is the one outlined in the issue: br update is done one clock cycle later.\"\n\nThe library version number was incremented at the patch level due to this bug fix.\n\nCommit details:\n- Hash: cd0e0ff1c9cc064041b2de99cfa8a3c223e06676\n- Message: \"br and bpkt_seq are updated in the same clock cycle - version change for bug fix.\"\n\nLinked issue:\n- #39 \"packet store goes empty incorrectly\"\n\nComments:\nNo review comments are documented in the visible conversation thread. The PR was merged without recorded reviewer feedback, with only the author's initial description present.\n\nStatus: Merged December 6, 2020. Author: lplana.\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/SpiNNakerManchester_spio_pr40", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/SpiNNakerManchester_spio_pr40.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/SpiNNakerManchester_spio_pr40", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/SpiNNakerManchester_spio_pr40"}
{"instance_id": "StanfordVLSI_dragonphy2_pr122", "issue_text": "# Generate \"update\" signal for adc_unfolding directly, rather than through clock division circuitry\n\n- Source URL: https://github.com/StanfordVLSI/dragonphy2/issues/106\n\nAt the moment, we generate the ``update`` signal used in ``adc_unfolding`` by sampling ``clk_avg`` with ``clk_retimer`` and then generating a one-cycle pulse when ``clk_avg`` transitions from ``0`` to ``1``.  The issue is that ``clk_avg`` is generated with a ``freq_divider`` module that creates several generated clocks.  For FPGA synthesis, at least, this causes some timing issues.  By removing the ``freq_divider`` in ``digital_core`` and directly generating the ``update`` signal, we will get back to having only one clock signal in ``digital_core``, which is ``clk_adc``.  This will resolve the FPGA synthesis issue, while also simplifying ASIC synthesis.\n\n\n\n\n\n\n\n\n\n\n\nPR title: PFD offset calibration loop updates\n\nSource: https://github.com/StanfordVLSI/dragonphy2/pull/122\n\nPR description:\nThis PR updates the PFD offset calibration feature with new block- and system-level tests. The primary technical change replaces a generated clock signal with a clock enable signal for the `update` mechanism, streamlining both ASIC and FPGA synthesis workflows.\n\nKey changes:\n- System-level PFD offset calibration test via DC sweep.\n- Block-level tests for `adc_unfolding`, `avg_pulse`, `calib_hist`, `sample_avg` modules.\n- Bitwidth reviews addressing potential overflow risks.\n- JTAG register sampling now occurs at `update` cycle completion only.\n- New debugging/control JTAG registers: `pfd_cal_flip_feedback` (polarity inversion) and `en_pfd_cal_ext_ave` (averaging bypass).\n\nComments:\n- sjkim85 (Oct 6, 2020): \"All changes make sense. I like flipping polarity by a chicken bit and bypassing avg block for testing.\"\n\nLinked issue:\n- #106 \"Generate 'update' signal for adc_unfolding directly, rather than through clock division circuitry\"\n\nStatus: Merged Oct 6, 2020. 13 commits total across development and merge workflow.\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/StanfordVLSI_dragonphy2_pr122", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/StanfordVLSI_dragonphy2_pr122.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/StanfordVLSI_dragonphy2_pr122", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/StanfordVLSI_dragonphy2_pr122"}
{"instance_id": "StanfordVLSI_dragonphy2_pr126", "issue_text": "# Add method to trigger ADC dump without external pin\n\n- Source URL: https://github.com/StanfordVLSI/dragonphy2/issues/13\n\nAs I understand it, this would make lab testing easier\n\n\n\n\n\n\n\n\n\n\n\n\nPR title: Small fixes\n\nSource: https://github.com/StanfordVLSI/dragonphy2/pull/126\n\nPR description:\nThis PR addresses three open issues by implementing the following features:\n\n1. SRAM dump trigger via register - option to trigger SRAM dump without an external pin\n2. CDR update clamping - mode to limit Phase Interpolator (PI) code updates to +/-1\n3. PI local encoder fix - resolves X-optimism in the int_Qperi component\n\nImplementation details:\nThe contributor introduced a new 32-bit `misc_ctrl_bits` register to accommodate these features, with only 5 of 32 bits currently utilized. For SRAM dumping, setting bit [2] enables the feature while bit [3] toggles the internal dump_start signal. CDR clamping is enabled via bit [3], with adjustable clamp amounts through a `cdr_clamp_amt` register defaulting to +/-1.\n\nThe X-optimism fix was formally verified using JasperGold to ensure logical equivalence with the previous implementation. Additionally, a bug fix improved error reporting in make.py for JusTAG and genesis build failures.\n\nLinked issues:\n- #13 \"Add method to trigger ADC dump without external pin\"\n- #20 \"Investigate mode in CDR to limit updates in PI codes to +/-1\"\n- #63 \"Fix X-pessimism in int_Qperi in PI_local_encoder\"\n\nComments:\n- sgherbst (Oct 9): \"justag and genesis errors weren't previously raising exceptions in make.py\"\n- sjkim85 (Oct 13): Requested 30ps clock delay adjustment to \"loopback_sram_int\" test; confirmed no changes needed to \"mm_cdr_slew\" test after merge.\n- sgherbst (Oct 13): \"if `en_clamp` is `0` (which is the default), then the phase update is exactly the same as before\"\n\nStatus: Merged Oct 14, 2020.\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/StanfordVLSI_dragonphy2_pr126", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/StanfordVLSI_dragonphy2_pr126.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/StanfordVLSI_dragonphy2_pr126", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/StanfordVLSI_dragonphy2_pr126"}
{"instance_id": "StanfordVLSI_dragonphy2_pr141", "issue_text": "# Remove combo logic loop in qr_4t1_mux_top\n\n- Source URL: https://github.com/StanfordVLSI/dragonphy2/issues/140\n\nThere is currently a combo logic loop in ``qr_4t1_mux_top``, where ``data`` appears on both the ``RHS`` and ``LHS`` of an ``assign`` statement:\nhttps://github.com/StanfordVLSI/dragonphy2/blob/1f1c97ba5f52445fe06aa39ac60585e053916806/vlog/chip_src/tx_16t1/qr_4t1_mux_top.sv#L47\n\nI believe this was added to prevent glitches if clocks are non-overlapping, but there may be other ways to deal with this, for example given the 4-bit select signal ``{Q, I, QB, IB}``:\n* ``4'b1100`` or ``4'b0100``: choose ``D1MQ``\n* ``4'b0110`` or ``4'b0010``: choose ``D1MI``\n* ``4'b0011`` or ``4'b0001``: choose ``D2MQB``\n* ``4'b1001`` or ``4'b1000``: choose ``D2MIB``\n\nHowever, because this is such a critical block, it would be helpful to think about what the intended digital circuit is, so that we can make sure that is what will be produced by the Verilog.\n\nPR title: Combinational loop removed\n\nSource: https://github.com/StanfordVLSI/dragonphy2/pull/141\n\nPR description:\nNo description was provided by the pull request author.\n\nComments:\n- CansWang (October 27, 2020): No additional context provided beyond the PR title.\n- sgherbst (October 28, 2020): \"just noticed that the branch was out-of-date so I updated it. If the tests are still passing (will find out in ~1hr), then I'll merge the changes.\"\n- sgherbst (Approval, October 28, 2020): \"LGTM, thanks!\"\n\nLinked issue:\n- #140 \"Remove combo logic loop in qr_4t1_mux_top\"\n\nKey details:\n- Status: Merged\n- Merge date: October 28, 2020\n- Commits: 2 commits merged\n- Reviewers: sgherbst (approved)\n- Participants: CansWang, sgherbst\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/StanfordVLSI_dragonphy2_pr141", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/StanfordVLSI_dragonphy2_pr141.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/StanfordVLSI_dragonphy2_pr141", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/StanfordVLSI_dragonphy2_pr141"}
{"instance_id": "StanfordVLSI_dragonphy2_pr90", "issue_text": "# Update handling of Vcal net\n\n- Source URL: https://github.com/StanfordVLSI/dragonphy2/issues/32\n\nIn ButterPHY, we used a custom nettype for modeling the Vcal net, which can be driven externally or internally by a bias generator.  In DragonPHY, we're trying to support Xcelium and Vivado for most simulations, so this feature had to be temporarily removed (Vivado does not yet support a custom ``nettype``).  In most cases, this level of modeling detail is not needed, so it would be fine to have a \"simple modeling\" mode that supports Vivado and Xcelium, along with a \"detailed modeling mode\" that supports Xcelium only.  But we would need to do this in a way that doesn't require keeping two sets of code (since that's not maintainable).\n\n\n\n\n\n\n\n\n\n\n\nPR title: Update PRBS, Vcal, mflowgen, JTAG ID\n\nSource: https://github.com/StanfordVLSI/dragonphy2/pull/90\n\nPR description:\nThis pull request consolidated four distinct updates to the dragonphy2 project:\n\n1. mflowgen Integration: Incorporated recent updates from the mflowgen branch, including custom-geom, custom-init, and custom-power steps, utilizing default configurations for init and power steps pending further refinement by zamyers.\n2. Vcal Net Handling: Resolved the net type and direction issue by converting Vcal to an \"inout\" net as per design specifications, restoring an impedance-based driver model from ButterPHY.\n3. PRBS Checker Updates: Enhanced the PRBS checker implementation to be \"more robust and flexible,\" addressing feature requests for second-pass functionality.\n4. JTAG ID Implementation: Configured the JTAG ID to include the git commit hash along with a status bit indicating whether the repository is clean or contains modifications.\n\nComments:\n- zamyers: \"LGTM\" (Looks Good To Me)\n\nLinked issues resolved:\n- #58 \"Second-pass PRBS checker features\"\n- #32 \"Update handling of Vcal net\"\n\nStatus: Merged on May 14, 2020. Author: sgherbst. Reviewer: zamyers. The PR contained 23 commits and resulted in a slight decrease in code coverage while adding test coverage for new functionality.\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/StanfordVLSI_dragonphy2_pr90", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/StanfordVLSI_dragonphy2_pr90.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/StanfordVLSI_dragonphy2_pr90", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/StanfordVLSI_dragonphy2_pr90"}
{"instance_id": "StanfordVLSI_dragonphy2_pr94", "issue_text": "# Add integration test for MDLL\n\n- Source URL: https://github.com/StanfordVLSI/dragonphy2/issues/93\n\nIt does not appear that we have a test of the MDLL integration, since ``sel_clk_source`` defaults to ``0``, which selects ``in`` (``ext_clk``) rather than ``in_mdll``:\nhttps://github.com/StanfordVLSI/dragonphy2/blob/da6909bb8f7e136b11afc7fb2a11bfbd37764254/vlog/new_chip_src/analog_core/input_divider.sv#L19\n\n\n\n\n\n\n\n\n\n\nPR title: Add basic test for MDLL\n\nSource: https://github.com/StanfordVLSI/dragonphy2/pull/94\n\nPR description:\nThe PR resolves issue #93 by implementing a basic test for the MDLL (Multiplying Delay-Locked Loop). According to the author, an external clock is fed into the reference clock pins, and various signals are controlled to route the MDLL output clock through the analog and digital cores.\n\nThe submission includes \"a record of the steps that have to be taken to use the MDLL,\" which the author notes may be useful for laboratory testing. Key configuration steps documented include:\n\n- Enabling the reference clock buffer\n- Taking the MDLL out of reset and enabling the oscillator\n- Selecting the MDLL clock as the analog core source\n- Bypassing the initial divide-by-two stage\n\nComments:\n- zamyers: \"LGTM\" (Looks Good To Me)\n\nLinked issue:\n- #93 \"Add integration test for MDLL\"\n\nStatus: Merged. Author: sgherbst. Reviewer: zamyers (approved). The PR successfully merged 4 commits into the master branch on May 15, 2020.\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/StanfordVLSI_dragonphy2_pr94", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/StanfordVLSI_dragonphy2_pr94.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/StanfordVLSI_dragonphy2_pr94", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/StanfordVLSI_dragonphy2_pr94"}
{"instance_id": "UTOSS_risc-v_pr107", "issue_text": "# Set up basic execution environment for running on DE1-SoC\n\nInstance: UTOSS_risc-v_pr107\nSource: https://github.com/UTOSS/risc-v/pull/107\nFetched: 2026-05-03\nRepository: UTOSS/risc-v\nPull request: #107\nAuthor: TheDeepestSpace\nState: closed\nBase branch: main\nHead branch: boris/basic-execution-environment\nCreated: 2025-10-31\nUpdated: 2025-11-30\nClosed: 2025-11-30\nMerged: 2025-11-30\n\n## PR Title\nSet up basic execution environment for running on DE1-SoC\n\n## PR Description\nAddresses issues #103 and #104 by establishing two separate execution environments for the project: one for simulation (used by testbenches and RISCOF) and one for the DE1-SoC FPGA deployment target. The core architectural change is extracting the memory (MA) out of the processor core, treating it as a peripheral rather than an internal component. The PR also lays down a basic memory map for the DE1-SoC platform with LEDR MMIO, demonstrating buildable and loadable code as a proof-of-concept. Memory currently infers as general logic; future work targets on-chip SRAM. Pending follow-ups: documentation for building/running on DE1-SoC and overall README/repository organization.\n\n## PR Comments\n**TheDeepestSpace** (Oct 31, 2025): Initial submission with the description above. Multiple loading errors prevented some early comments from rendering when the page was fetched.\n\n**TheDeepestSpace** (Oct 31, 2025, code review): On the memory-map implementation - \"This line breaks the RAM inference when Quartus is synthesizing.\" Recommended a more advanced memory map with a separated canonical RAM module in a follow-up issue.\n\n**TheDeepestSpace** (Nov 25, 2025): \"note to self: need to figure out whats up with the ugly stack trace in the silently failing riscof task\"\n\nThe PR contains 32 commits and modifies multiple environment-configuration and source files.\n\n## Linked Issues\n- **Issue #103 - \"Set up Quartus project\"** (closed by this PR)\n  Body: \"Use Quartus ecosystem to set up a basic project that will compile top module for deployment onto DE1-SoC. Fix any issues stoping synthesis from succeeding.\"\n- **Issue #104 - \"Set up execution environment with basic peripheral\"** (also closed by this PR; body not fetched).\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/UTOSS_risc-v_pr107", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/UTOSS_risc-v_pr107.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/UTOSS_risc-v_pr107", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/UTOSS_risc-v_pr107"}
{"instance_id": "UTOSS_risc-v_pr114", "issue_text": "# Implement structured logging\n\n- Source URL: https://github.com/UTOSS/risc-v/issues/60\n\nAs the core gets bigger and more complicated, VCD diagrams will become harder to read especially at the top level. I think it would be good to have some sort of logging capability built into processor at least during development stages so that we can get diagnose issues more easily.\n\nExample of logging that I saw that our reference model for RISCOF has log callbacks set up here: https://github.com/riscv/sail-riscv/blob/cbddfcd979ba6ad4e2c5abbacb20636e3e1f4916/c_emulator/riscv_callbacks_log.cpp and the logs themselves look like something like\n```\n...\n[3] [M]: 0x0000100C (0x0182A283) lw t0, 0x18(t0)\nmem[R,0b0000000000000000000001000000011000] -> 0x80000000\nx5 <- 0x80000000\nmem[X,0b0000000000000000000001000000010000] -> 0x8067\nmem[X,0b0000000000000000000001000000010010] -> 0x0002\n[4] [M]: 0x00001010 (0x00028067) jalr zero, 0x0(t0)\nmem[X,0b0010000000000000000000000000000000] -> 0x0837\nmem[X,0b0010000000000000000000000000000010] -> 0x7D5C\n...\n```\n\nRISC-V also has a draft for a \"verification interface\" that defines similar attributes for traces (i.e. writing to mem/registers, current instruction, etc.): https://github.com/riscv-verification/RVVI\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/UTOSS_risc-v_pr114", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/UTOSS_risc-v_pr114.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/UTOSS_risc-v_pr114", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/UTOSS_risc-v_pr114"}
{"instance_id": "UTOSS_risc-v_pr115", "issue_text": "# some basic simplification for the decode module\n\nInstance: UTOSS_risc-v_pr115\nSource: https://github.com/UTOSS/risc-v/pull/115\nFetched: 2026-05-03\nRepository: UTOSS/risc-v\nPull request: #115\nAuthor: Invisipac\nState: closed\nBase branch: main\nHead branch: simplify-decode\nCreated: 2025-11-08\nUpdated: 2025-11-30\nClosed: 2025-11-30\nMerged: 2025-11-30\n\n## PR Title\nsome basic simplification for the decode module\n\n## PR Description\nThe PR description was not fully captured by the fetcher. Based on the commits and conversation, the changes:\n- Extract register values into named variables and combine related conditional statements\n- Convert several decode branches into case statements and remove conditionally-set zero values\n- Default registers to zero, eliminating prior default-value assignments\n- Remove unused register declarations\n\n## PR Comments\n**Invisipac** (Nov 9, 2025): \"I removed the default_rd, etc. values since I felt that there's no point doing that operation every cycle since sometimes they are not needed. Instead I just set all the addresses to 0 and change them if necessary.\"\n\n**TheDeepestSpace** (Nov 8, 2025): \"makes sense\"; suggested avoiding conditional zero assignment to reduce multiplexers; recommended converting to case statements for cleaner code organization; proposed making `opcode_t` an enumeration for improved type safety.\n\n**TheDeepestSpace** (Nov 25, 2025): Questioned whether certain register declarations were actually being used.\n\nParticipants: Invisipac (author), TheDeepestSpace (reviewer/merger).\n\n## Linked Issues\n**Issue #88 - \"Simplify decoding\"** (closed by this PR).\n\nIssue body (verbatim from the source URL):\n\"I noticed that rd/rs retrieval in the instruction docoder module is pretty repetitive, i.e.\nhttps://github.com/UTOSS/risc-v/blob/f31fc3790be901daedd1d2d306c9cf0e33647e37/src/Instruction_Decode/Instruction_Decode.v#L69-L119\n\nSimply this without breaking things.\"\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/UTOSS_risc-v_pr115", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/UTOSS_risc-v_pr115.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/UTOSS_risc-v_pr115", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/UTOSS_risc-v_pr115"}
{"instance_id": "UTOSS_risc-v_pr127", "issue_text": "# Fence added, and all riscof passed\n\nInstance: UTOSS_risc-v_pr127\nSource: https://github.com/UTOSS/risc-v/pull/127\nFetched: 2026-05-03\nRepository: UTOSS/risc-v\nPull request: #127\nAuthor: RunzeZhu28\nState: closed\nBase branch: main\nHead branch: tony-fence\nCreated: 2025-11-14\nUpdated: 2025-11-16\nClosed: 2025-11-16\nMerged: 2025-11-16\n\n## PR Title\nFence added, and all riscof passed\n\n## PR Description\nNo description provided by the author. The PR adds support for the RISC-V `fence` instruction so that the previously failing RISCOF tests for it now pass. The 5 commits are:\n1. \"Fence added, so all riscof passed\" (8878edb) - by zerotoasic et al.\n2. \"Update params.vh\" (37e869c) - RunzeZhu28\n3. \"Update Instruction_Decode.v\" (04d4c36) - RunzeZhu28\n4. \"Update ci.yaml\" (547dca4) - RunzeZhu28\n5. \"Update ci.yaml\" (11d1f06) - RunzeZhu28\n\n## PR Comments\n**RunzeZhu28** (Nov 14, 2025): \"No description provided.\" (No further conversation comments.)\n\nParticipants: RunzeZhu28 (author), TheDeepestSpace (merger).\n\n## Linked Issues\n**Issue #71 - \"Review RISCOF's `RV32I` failures\"** (referenced; this PR closes a portion of the task list).\n\nIssue body (verbatim from the source URL):\n\"Review latest RISCOF report (see artifacts of `main` branch's CI run) and fix issues individually as you find them.\"\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/UTOSS_risc-v_pr127", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/UTOSS_risc-v_pr127.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/UTOSS_risc-v_pr127", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/UTOSS_risc-v_pr127"}
{"instance_id": "UTOSS_risc-v_pr128", "issue_text": "# Cleanup memory instructions and swap assert_equals parameters\n\nInstance: UTOSS_risc-v_pr128\nSource: https://github.com/UTOSS/risc-v/pull/128\nFetched: 2026-05-03\nRepository: UTOSS/risc-v\nPull request: #128\nAuthor: thatlittlegit\nState: closed\nBase branch: main\nHead branch: duncanm/memory-insn-cleanup\nCreated: 2025-11-23\nUpdated: 2025-11-30\nClosed: 2025-11-30\nMerged: 2025-11-30\n\n## PR Title\nCleanup memory instructions and swap assert_equals parameters\n\n## PR Description\nThe contributor notes the scope may have grown beyond the original assignment but believes the changes are an improvement. Three main modifications:\n\n1. Reorders `assert_equals` parameters to match actual usage patterns observed in the codebase, keeping each assertion on a single line so error message line numbers remain accurate.\n2. Simplifies the MemoryLoad module by collapsing the separate code paths for signed and unsigned memory loads, potentially helping the compiler optimize better.\n3. Adds comprehensive test coverage for memory-load operations, addressing gaps in existing tests (including RISCOF) that had failed to catch issues such as \"16-to-32-bit sign extension using the wrong bits.\"\n\nThe contributor acknowledges the new tests are extensive and unpolished, and notes that store-operation testing would be a useful follow-up.\n\n## PR Comments\n**thatlittlegit** (Nov 23, 2025): Initial PR submission acknowledging the expanded scope.\n\n**TheDeepestSpace** (Nov 25, 2025): \"nice!\" on the single-line assertion approach. Also suggested exploring a `generate`-block rewrite for the case statement, while noting that may add complexity.\n\n**TheDeepestSpace** (Nov 25, 2025): Assigned the PR to thatlittlegit and subsequently merged at commit 118b417 with \"4 checks passed\".\n\n## Linked Issues\n**Issue #92 - \"Improve memory loader module\"** (closed by this PR).\n\nIssue body (verbatim from the source URL):\n\"* remove the unnecessary case clauses for half-word loading instructions\n* use a two-bit number for `byteindex` to save space\n* optionally make `funct3` into an enum (not a global one since `funct3` values are context-specific, but one for the load instructions in this module)\"\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/UTOSS_risc-v_pr128", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/UTOSS_risc-v_pr128.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/UTOSS_risc-v_pr128", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/UTOSS_risc-v_pr128"}
{"instance_id": "UTOSS_risc-v_pr132", "issue_text": "# Integrating Verilator into CI Setup\n\nInstance: UTOSS_risc-v_pr132\nSource: https://github.com/UTOSS/risc-v/pull/132\nFetched: 2026-05-03\nRepository: UTOSS/risc-v\nPull request: #132\nAuthor: marwannismail\nState: closed\nBase branch: main\nHead branch: mi_verilator_integration\nCreated: 2025-12-01\nUpdated: 2025-12-19\nClosed: 2025-12-19\nMerged: 2025-12-19\n\n## PR Title\nIntegrating Verilator into CI Setup\n\n## PR Description\nThe PR validates that Verilator is correctly integrated into the project's CI. The author fixed the test bench for the fetch module and modified the Makefile so Verilator runs inside the Docker CI environment. The PR contains 23 commits covering Verilator installation/dependency management, testbench fixes, TESTBENCH macro additions, directory restructuring, and CI configuration.\n\n## PR Comments\n**marwannismail** (Dec 1, 2025): \"This is a pull request meant to test whether the current implementation of the Verilator integration is working correctly.\"\n\n**marwannismail** (Dec 1, 2025): \"Fixed the test bench for the fetch module and now Verilator is integrated in the Docker CI, with the Makefile modified accordingly.\"\n\n**marwannismail** (Dec 19, 2025): \"Thanks @TheDeepestSpace for the bug fixes!\"\n\n**TheDeepestSpace** (Dec 19, 2025): \"No problem, great pr!\"\n\n## Linked Issues\n**Issue #40 - \"Review and consider integrating Verilator\"** (closed by this PR).\n\nIssue body (verbatim from the source URL):\n\"Seems like a cool tool that can help us write safer verilog. See https://www.veripool.org/verilator/\"\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/UTOSS_risc-v_pr132", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/UTOSS_risc-v_pr132.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/UTOSS_risc-v_pr132", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/UTOSS_risc-v_pr132"}
{"instance_id": "UTOSS_risc-v_pr134", "issue_text": "# Fix the reg reset issue to make all riscof test passing\n\nInstance: UTOSS_risc-v_pr134\nSource: https://github.com/UTOSS/risc-v/pull/134\nFetched: 2026-05-03\nRepository: UTOSS/risc-v\nPull request: #134\nAuthor: RunzeZhu28\nState: closed\nBase branch: main\nHead branch: risc-of-all-passed\nCreated: 2025-12-01\nUpdated: 2025-12-02\nClosed: 2025-12-02\nMerged: 2025-12-02\n\n## PR Title\nFix the reg reset issue to make all riscof test passing\n\n## PR Description\nNo description was provided by the contributor. The PR fixes a register-reset issue so that all RISCOF tests pass. 4 commits:\n1. Fix the reg reset issue to make all riscof test passing (04a5426)\n2. Add the macro of TESTBENCH (d17bdcc)\n3. Add the macro of TESTBENCH (6adc872)\n4. Add the macro of TESTBENCH (21784d6)\n\n## PR Comments\nThe PR shows minimal conversation activity. RunzeZhu28 submitted the pull request without additional commentary. TheDeepestSpace merged it on Dec 2, 2025; 5 checks passed.\n\nParticipants: RunzeZhu28 (contributor, assignee), TheDeepestSpace (reviewer/merger).\n\n## Linked Issues\n**Issue #71 - \"Review RISCOF's `RV32I` failures\"** (referenced; this PR contributes to closing it).\n\nIssue body (verbatim from the source URL):\n\"Review latest RISCOF report (see artifacts of `main` branch's CI run) and fix issues individually as you find them.\"\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/UTOSS_risc-v_pr134", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/UTOSS_risc-v_pr134.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/UTOSS_risc-v_pr134", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/UTOSS_risc-v_pr134"}
{"instance_id": "UTOSS_risc-v_pr138", "issue_text": "# Make some changes on FSM to ensure synchronous read and write for inferred RAM\n\nInstance: UTOSS_risc-v_pr138\nSource: https://github.com/UTOSS/risc-v/pull/138\nFetched: 2026-05-03\nRepository: UTOSS/risc-v\nPull request: #138\nAuthor: TheDeepestSpace\nState: closed\nBase branch: main\nHead branch: inferred-ram\nCreated: 2025-12-06\nUpdated: 2025-12-21\nClosed: 2025-12-21\nMerged: 2025-12-21\n\n## PR Title\nMake some changes on FSM to ensure synchronous read and write for inferred RAM\n\n## PR Description\nNo formal description was provided by the contributor. The PR adjusts the FSM to issue synchronous reads and writes so that the on-chip memory is correctly inferred as block RAM. 15 commits cover initial FSM synchronization changes, timing fixes that re-enable the loop PoC, VCD output corrections, testbench fixes, svlint compliance, memory-map cleanup, and support for clocked memory reads in simulation. The PR also splits memory into byte lanes to make byte-granularity writes synthesize cleanly.\n\n## PR Comments\n**TheDeepestSpace** (Dec 21, 2025): \"good call\"\n\n**TheDeepestSpace** (Dec 21, 2025): \"Just confirmed that it works on my board too! Cool trick with splitting the memory into byte lanes!\"\n\nParticipants: TheDeepestSpace (reviewer), RunzeZhu28 (assignee).\n\n## Linked Issues\n**Issue #135 - \"Research timing issues and set up a demo\"** (closed by this PR).\n\nIssue body (verbatim from the source URL):\n\"We have quite a bit of timing issues as part of synthesis. It seems like the branching instructions are not working well on the FPGA right now. Synthesis takes quite a long time\n\nAs part of the ticket:\n* attempt to fix the synthesis issues we are observing right now\n* attempt to infer memory as SRAM to speed up the feedback loop\n* attempt to implement a basic HEX/LEDR display demo that involves either something interactive, or just demo-able at the upcoming clubs fair.\"\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/UTOSS_risc-v_pr138", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/UTOSS_risc-v_pr138.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/UTOSS_risc-v_pr138", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/UTOSS_risc-v_pr138"}
{"instance_id": "UTOSS_risc-v_pr23", "issue_text": "# updating ALUdecoder testbench\n\nInstance: UTOSS_risc-v_pr23\nSource: https://github.com/UTOSS/risc-v/pull/23\nFetched: 2026-05-03\nRepository: UTOSS/risc-v\nPull request: #23\nAuthor: DanielTaoHuang123\nState: closed\nBase branch: main\nHead branch: main (DanielTaoHuang123/risc-v fork)\nCreated: 2025-03-30\nUpdated: 2025-03-30\nClosed: 2025-03-30\nMerged: 2025-03-30\n\n## PR Title\nupdating ALUdecoder testbench\n\n## PR Description\n\"add testbench for ALUdecoder and specifically for branchifeq fix minor mistakes in ALU.v and ALUdecoder.v\"\n\n## PR Comments\nNo conversation comments were posted on the PR; it was reviewed and merged by joon2022park on March 30, 2025. The branch contained 5 commits:\n1. f379a8d - \"a simple implementation of the ALU. implemented ADD, SUB, SLL, SLT, SLTU, XOR, XRL, SRA, OR, AND\"\n2. 200c1b5 - Merge branch 'UTOSS:main' into main\n3. 0c7eb38 - \"A simple implementation of the ALU. Implemented ADD, SUB, SLL, SLT, SLTU, XOR, XRL, SRA, OR, AND\"\n4. 2cc73ae - Delete ALU.v\n5. 063a7e4 - \"update the testbench for aludecoder and specifically for branchifeq; fix minor mistakes in ALU.v and ALUdecoder.v\"\n\nParticipants: DanielTaoHuang123 (author), joon2022park (reviewer/merger).\n\n## Linked Issues\n**Issue #13 - \"Add ALUOp to ALU Decoder\"** (closed by this PR). Issue body was empty.\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/UTOSS_risc-v_pr23", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/UTOSS_risc-v_pr23.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/UTOSS_risc-v_pr23", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/UTOSS_risc-v_pr23"}
{"instance_id": "UTOSS_risc-v_pr25", "issue_text": "# mihir_task 1 - instantiated instruction decoder in top.v\n\nInstance: UTOSS_risc-v_pr25\nSource: https://github.com/UTOSS/risc-v/pull/25\nFetched: 2026-05-03\nRepository: UTOSS/risc-v\nPull request: #25\nAuthor: MM871\nState: closed\nBase branch: main\nHead branch: 11-integrate-instruction-decode-with-memory-access\nCreated: 2025-03-30\nUpdated: 2025-07-21\nClosed: 2025-07-21\nMerged: 2025-07-21\n\n## PR Title\nmihir_task 1 - instantiated instruction decoder in top.v\n\n## PR Description\nNo description was provided in the original PR submission. Across the PR's life the work was: instantiate the Instruction Decode (ID) and Memory Access (MA) stages inside `top.v`, using Boris's `top.v` as a baseline reference, and bring all signals through correctly so the design compiles end-to-end.\n\n## PR Comments\n**MM871** (Mar 30, 2025): \"No description provided.\"\n\n**joon2022park** (Mar 30, 2025): \"Instantiate 3 modules (Use Boris's top.v as a baseline/reference) - ID stage (Instruction Decode) - MA stage (Memory access stage)\"\n\n**MM871** (Jun 9, 2025): \"commited new changed regarding instantiating the ID and MA\"\n\n**TheDeepestSpace** (Jul 18, 2025): \"Currently, it seems like we generally prefer `case` statements over dedicated modules for implementing muxes.\" Referenced a prior commit decision to remove a generic mux module.\n\n**TheDeepestSpace** (Jul 20, 2025): \"hey @MM871, I just merged master into you branch and resolved all conflicts; i think we are missing a couple of variables there...great job on using the case statements, you nailed it!\"\n\n**TheDeepestSpace** (Jul 21, 2025): \"I just threw in the missing registers and it all compiles now! Thanks @MM871, gonna merge this now\"\n\nParticipants: MM871, joon2022park, TheDeepestSpace.\n\n## Linked Issues\n**Issue #11 - \"Integrate Top Level Module\"** (closed by this PR). Issue body was empty.\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/UTOSS_risc-v_pr25", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/UTOSS_risc-v_pr25.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/UTOSS_risc-v_pr25", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/UTOSS_risc-v_pr25"}
{"instance_id": "UTOSS_risc-v_pr42", "issue_text": "# Implement `lw` instruction\n\nInstance: UTOSS_risc-v_pr42\nSource: https://github.com/UTOSS/risc-v/pull/42\nFetched: 2026-05-03\nRepository: UTOSS/risc-v\nPull request: #42\nAuthor: TheDeepestSpace\nState: closed\nBase branch: main\nHead branch: boris/lw\nCreated: 2025-07-21\nUpdated: 2025-07-27\nClosed: 2025-07-27\nMerged: 2025-07-27\n\n## PR Title\nImplement `lw` instruction\n\n## PR Description\nThe PR introduces architectural support for the load-word (`lw`) instruction:\n\n- Relocates the memory module from the `fetch` module up to the top-level module and adds an address selector\n- Adds a `pc_old` register inside the `fetch` module\n- Calibrates muxes and connects them to ALU inputs/outputs while separating the ALU output from the ALU result\n- Introduces enumerated types for various control signals\n\nThree test cases were validated: operations with no offset, with positive offset, and with negative offset.\n\n## PR Comments\n**TheDeepestSpace** (Jul 22, 2025): Posted the initial description detailing the major changes and test coverage.\n\n**Copilot AI** (Jul 22, 2025): Generated a code-review with suggestions about enum naming clarity.\n\n**joon2022park** (Jul 26, 2025): Left review comments on the types-definitions file.\n\n**TheDeepestSpace** (Jul 27, 2025): Added documentation strings for the new enums and merged. 30 commits in total covered file format conversion (.v -> .sv), enumeration introductions for ALU and address sources, memory architecture refactoring, and comprehensive testbench additions, plus refinements addressing spelling, duplicate wires, magic numbers and signal connections.\n\n## Linked Issues\n**Issue #36 - \"Implement `lw` instruction\"** (closed by this PR). Issue body was empty.\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/UTOSS_risc-v_pr42", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/UTOSS_risc-v_pr42.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/UTOSS_risc-v_pr42", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/UTOSS_risc-v_pr42"}
{"instance_id": "UTOSS_risc-v_pr48", "issue_text": "# Add testbench for `or` instruction\n\nInstance: UTOSS_risc-v_pr48\nSource: https://github.com/UTOSS/risc-v/pull/48\nFetched: 2026-05-03\nRepository: UTOSS/risc-v\nPull request: #48\nAuthor: TheDeepestSpace\nState: closed\nBase branch: main\nHead branch: boris/or\nCreated: 2025-07-29\nUpdated: 2025-08-10\nClosed: 2025-08-10\nMerged: 2025-08-10\n\n## PR Title\nAdd testbench for `or` instruction\n\n## PR Description\nAdds a SystemVerilog testbench for the `or` instruction as part of task #45. The testbench verifies correct execution of a bitwise OR operation through all processor pipeline stages, including instruction decoding, ALU operation, register-file updates, and verification of intermediate states and final results.\n\n## PR Comments\nNo human review comments were posted on the PR. Copilot AI was requested as a reviewer on July 29, 2025; the author self-assigned the same day. Merged on August 10, 2025.\n\nParticipants: TheDeepestSpace (author/merger), Copilot AI (automated reviewer).\n\n## Linked Issues\n**Issue #45 - \"Implement starter-pack instructions for RISCOF framework\"** (this PR contributes to the task list, the `or` task).\n\nIssue body (verbatim from the source URL):\n\"We need a couple of instructions before we can run the RISCOF arch-test quite, specifically:\n\n- [x] `addi` @DanielTaoHuang123 (#50)\n- [x] `auipc` @DanielTaoHuang123 / @houjingl (#59)\n- [x] `lui`  @houjingl / @TheDeepestSpace (#56, #59)\n- [x] `srli` @MM871 / @DanielTaoHuang123 (#54)\n- [x] `nop` @MM871 / @TheDeepestSpace / @joon2022park (#63)\n- [x] `or` @TheDeepestSpace  (#48)\"\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/UTOSS_risc-v_pr48", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/UTOSS_risc-v_pr48.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/UTOSS_risc-v_pr48", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/UTOSS_risc-v_pr48"}
{"instance_id": "UTOSS_risc-v_pr50", "issue_text": "# add sw_testbench\n\nInstance: UTOSS_risc-v_pr50\nSource: https://github.com/UTOSS/risc-v/pull/50\nFetched: 2026-05-03\nRepository: UTOSS/risc-v\nPull request: #50\nAuthor: DanielTaoHuang123\nState: closed\nBase branch: main\nHead branch: daniel\nCreated: 2025-08-03\nUpdated: 2025-08-10\nClosed: 2025-08-10\nMerged: 2025-08-10\n\n## PR Title\nadd sw_testbench\n\n## PR Description\n\"add sw testbench; add FF between RF and ALU\"\n\n## PR Comments\n**DanielTaoHuang123** (Aug 3, 2025): The contributor explained the changes: adding a software-store (`sw`) testbench, plus inserting a flip-flop between the Register File and the ALU.\n\n**TheDeepestSpace** (Aug 5, 2025): Provided technical clarification, noting \"the real problem was that the dataA and dataB registers here...were adding another clock cycle basically.\" The reviewer confirmed \"your implementation is probably more inline with how the diagram is layed out -- the sync register is outside of RF and the reads are combinational.\"\n\nThe PR contained 12 commits spanning multiple updates to top.v, RegisterFile.v, and addition of testbench files (addi_tb.sv, sw testbench).\n\n## Linked Issues\n- **Issue #37 - \"Implement `sw` instruction\"** (closed by this PR). Issue body was empty.\n- **Issue #45 - \"Implement starter-pack instructions for RISCOF framework\"** (referenced; this PR contributes to the `addi`/`sw` task list).\n\nIssue #45 body (verbatim):\n\"We need a couple of instructions before we can run the RISCOF arch-test quite, specifically:\n\n- [x] `addi` @DanielTaoHuang123 (#50)\n- [x] `auipc` @DanielTaoHuang123 / @houjingl (#59)\n- [x] `lui`  @houjingl / @TheDeepestSpace (#56, #59)\n- [x] `srli` @MM871 / @DanielTaoHuang123 (#54)\n- [x] `nop` @MM871 / @TheDeepestSpace / @joon2022park (#63)\n- [x] `or` @TheDeepestSpace  (#48)\"\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/UTOSS_risc-v_pr50", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/UTOSS_risc-v_pr50.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/UTOSS_risc-v_pr50", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/UTOSS_risc-v_pr50"}
{"instance_id": "UTOSS_risc-v_pr54", "issue_text": "# Add testbench for srli instruction\n\nInstance: UTOSS_risc-v_pr54\nSource: https://github.com/UTOSS/risc-v/pull/54\nFetched: 2026-05-03\nRepository: UTOSS/risc-v\nPull request: #54\nAuthor: DanielTaoHuang123\nState: closed\nBase branch: main\nHead branch: daniel\nCreated: 2025-08-22\nUpdated: 2025-09-06\nClosed: 2025-09-06\nMerged: 2025-09-06\n\n## PR Title\nAdd testbench for srli instruction\n\n## PR Description\nThe PR description consists of a single commit message - \"add srli_tb.sv\" - with the GitHub note: \"Sorry, something went wrong.\" (i.e., no body actually rendered).\n\n## PR Comments\nNo conversation comments were posted. Six commits by DanielTaoHuang123 iterated on the testbench:\n1. Create srli_tb.sv (f4469c4)\n2. Update srli_tb.sv (09ed557)\n3. Update srli_tb.sv (fdb309b)\n4. Update srli_tb.sv (adef2b2)\n5. Update srli_tb.sv (a135047)\n6. Update srli_tb.sv (4c82d1c)\n\nNo reviews were submitted before merging. Merged by TheDeepestSpace.\n\n## Linked Issues\n**Issue #45 - \"Implement starter-pack instructions for RISCOF framework\"** (this PR contributes the `srli` task).\n\nIssue body (verbatim from the source URL):\n\"We need a couple of instructions before we can run the RISCOF arch-test quite, specifically:\n\n- [x] `addi` @DanielTaoHuang123 (#50)\n- [x] `auipc` @DanielTaoHuang123 / @houjingl (#59)\n- [x] `lui`  @houjingl / @TheDeepestSpace (#56, #59)\n- [x] `srli` @MM871 / @DanielTaoHuang123 (#54)\n- [x] `nop` @MM871 / @TheDeepestSpace / @joon2022park (#63)\n- [x] `or` @TheDeepestSpace  (#48)\"\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/UTOSS_risc-v_pr54", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/UTOSS_risc-v_pr54.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/UTOSS_risc-v_pr54", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/UTOSS_risc-v_pr54"}
{"instance_id": "UTOSS_risc-v_pr59", "issue_text": "# lui tb and auipc tb and related FSM changes\n\nInstance: UTOSS_risc-v_pr59\nSource: https://github.com/UTOSS/risc-v/pull/59\nFetched: 2026-05-03\nRepository: UTOSS/risc-v\nPull request: #59\nAuthor: houjingl\nState: closed\nBase branch: main\nHead branch: JerryHou/lui\nCreated: 2025-09-06\nUpdated: 2025-09-07\nClosed: 2025-09-07\nMerged: 2025-09-07\n\n## PR Title\nlui tb and auipc tb and related FSM changes\n\n## PR Description\nThe PR introduces testbenches for the `lui` and `auipc` instructions, alongside modifications to the finite state machine, the instruction decoder, and the datapath needed to support these new instructions.\n\n## PR Comments\n**houjingl** (Sep 6, 2025): \"Added tb for lui and auipc instructions. Modified the FSM, instruction decoder and datapath to adapt new instructions\"\n\n**TheDeepestSpace** (Sep 6, 2025): Questioned whether the new instructions should route through the EXECUTEI state for potential pipelining benefits, noting an original similar approach was taken.\n\n16 commits in total covered testbench additions, FSM parameter updates, instruction-decoder modifications, and various bug fixes and naming corrections.\n\n## Linked Issues\n**Issue #45 - \"Implement starter-pack instructions for RISCOF framework\"** (this PR contributes `lui` and `auipc`).\n\nIssue body (verbatim from the source URL):\n\"We need a couple of instructions before we can run the RISCOF arch-test quite, specifically:\n\n- [x] `addi` @DanielTaoHuang123 (#50)\n- [x] `auipc` @DanielTaoHuang123 / @houjingl (#59)\n- [x] `lui`  @houjingl / @TheDeepestSpace (#56, #59)\n- [x] `srli` @MM871 / @DanielTaoHuang123 (#54)\n- [x] `nop` @MM871 / @TheDeepestSpace / @joon2022park (#63)\n- [x] `or` @TheDeepestSpace  (#48)\"\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/UTOSS_risc-v_pr59", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/UTOSS_risc-v_pr59.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/UTOSS_risc-v_pr59", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/UTOSS_risc-v_pr59"}
{"instance_id": "UTOSS_risc-v_pr63", "issue_text": "# Added testbench for NOP instruction\n\nInstance: UTOSS_risc-v_pr63\nSource: https://github.com/UTOSS/risc-v/pull/63\nFetched: 2026-05-03\nRepository: UTOSS/risc-v\nPull request: #63\nAuthor: joon2022park\nState: closed\nBase branch: main\nHead branch: joon-nop-riscof\nCreated: 2025-09-21\nUpdated: 2025-09-22\nClosed: 2025-09-22\nMerged: 2025-09-22\n\n## PR Title\nAdded testbench for NOP instruction\n\n## PR Description\nNotes that \"the NOP instruction (`addi x0, x0, 0`) does not seem to require architectural changes\" and mentions test-run results would be added to the branch.\n\n## PR Comments\n**TheDeepestSpace** (Sep 21, 2025): Tagged @joon2022park and posted the description above regarding NOP and architectural requirements.\n\nTwo commits:\n1. \"Added testbench for NOP instruction\" (ab977ce) - initial implementation\n2. \"fix nop tb\" (2804c8e) - correction to the testbench\n\nAssignees: TheDeepestSpace, joon2022park.\n\n## Linked Issues\n**Issue #45 - \"Implement starter-pack instructions for RISCOF framework\"** (this PR contributes the `nop` task).\n\nIssue body (verbatim from the source URL):\n\"We need a couple of instructions before we can run the RISCOF arch-test quite, specifically:\n\n- [x] `addi` @DanielTaoHuang123 (#50)\n- [x] `auipc` @DanielTaoHuang123 / @houjingl (#59)\n- [x] `lui`  @houjingl / @TheDeepestSpace (#56, #59)\n- [x] `srli` @MM871 / @DanielTaoHuang123 (#54)\n- [x] `nop` @MM871 / @TheDeepestSpace / @joon2022park (#63)\n- [x] `or` @TheDeepestSpace  (#48)\"\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/UTOSS_risc-v_pr63", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/UTOSS_risc-v_pr63.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/UTOSS_risc-v_pr63", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/UTOSS_risc-v_pr63"}
{"instance_id": "UTOSS_risc-v_pr70", "issue_text": "# Connect reset signal to fix issue of XXXXXXX in RISCOF\n\nInstance: UTOSS_risc-v_pr70\nSource: https://github.com/UTOSS/risc-v/pull/70\nFetched: 2026-05-03\nRepository: UTOSS/risc-v\nPull request: #70\nAuthor: RunzeZhu28\nState: closed\nBase branch: main\nHead branch: tony-riscof\nCreated: 2025-10-03\nUpdated: 2025-10-03\nClosed: 2025-10-03\nMerged: 2025-10-03\n\n## PR Title\nConnect reset signal to fix issue of XXXXXXX in RISCOF\n\n## PR Description\nConnects the previously unwired `reset` to the Register File so that x0 is initialised correctly, fixing an X-propagation problem observed in RISCOF runs. Per the conversation, the testbench was reworked so it doesn't try to write to x0 directly but instead asserts and the RegisterFile enforces x0=0.\n\n## PR Comments\n**TheDeepestSpace** (Oct 3, 2025): \"The `nop` testbench is failing because its using `x0` register which is supposed to always be zero. Since now the `reset` signal is passed to RF module properly, `x0` gets correctly initialized to zero and testbench overwrites the value, which we should not do.\"\n\n**RunzeZhu28** (Oct 3, 2025): \"I keep the tb to write to x0 but change the assert and modify the RegisterFile to ensure x0 is always 0. Now all passed\"\n\n5 commits, final commit f3b67d0; all 3 checks passed at merge.\n\n## Linked Issues\n**Issue #71 - \"Review RISCOF's `RV32I` failures\"** (this PR addresses one of the failures).\n\nIssue body (verbatim from the source URL):\n\"Review latest RISCOF report (see artifacts of `main` branch's CI run) and fix issues individually as you find them.\"\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/UTOSS_risc-v_pr70", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/UTOSS_risc-v_pr70.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/UTOSS_risc-v_pr70", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/UTOSS_risc-v_pr70"}
{"instance_id": "UTOSS_risc-v_pr77", "issue_text": "# Fixing RISCOF test cases add/sub/and/xor/or/slli/sll/sra/srl\n\nInstance: UTOSS_risc-v_pr77\nSource: https://github.com/UTOSS/risc-v/pull/77\nFetched: 2026-05-03\nRepository: UTOSS/risc-v\nPull request: #77\nAuthor: marwannismail\nState: closed\nBase branch: main\nHead branch: mi_riscof_debug\nCreated: 2025-10-12\nUpdated: 2025-10-13\nClosed: 2025-10-13\nMerged: 2025-10-13\n\n## PR Title\nFixing RISCOF test cases add/sub/and/xor/or/slli/sll/sra/srl\n\n## PR Description\nAdds `regWrite <= 1'b0` to ControlFSM.sv to set the register-file write enable low by default during the Fetch stage, preventing register overwrites and unblocking the listed RISCOF tests.\n\n## PR Comments\n**marwannismail** (Oct 13, 2025): \"Added regWrite <= 1'b0 to ControlFSM.sv to set it low by default to prevent overwriting of registers in the Fetch stage.\"\n\nTwo commits:\n1. \"Set regWrite = 0 in Fetch for CFSM\" (67291576...)\n2. \"Set regWrite = 0 by default for CFSM\" (290ab12b...)\n\nFour checks passed; reviewer requested was TheDeepestSpace; merged by marwannismail.\n\n## Linked Issues\n**Issue #71 - \"Review RISCOF's `RV32I` failures\"** (this PR closes a portion).\n\nIssue body (verbatim from the source URL):\n\"Review latest RISCOF report (see artifacts of `main` branch's CI run) and fix issues individually as you find them.\"\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/UTOSS_risc-v_pr77", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/UTOSS_risc-v_pr77.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/UTOSS_risc-v_pr77", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/UTOSS_risc-v_pr77"}
{"instance_id": "UTOSS_risc-v_pr79", "issue_text": "# SRAI Fix (New)\n\nInstance: UTOSS_risc-v_pr79\nSource: https://github.com/UTOSS/risc-v/pull/79\nFetched: 2026-05-03\nRepository: UTOSS/risc-v\nPull request: #79\nAuthor: marwannismail\nState: closed\nBase branch: main\nHead branch: mi_srai_fix\nCreated: 2025-10-13\nUpdated: 2025-10-26\nClosed: 2025-10-26\nMerged: 2025-10-26\n\n## PR Title\nSRAI Fix (New)\n\n## PR Description\nPasses `funct7 = instr[31:25]` for IType_logic instructions so the `SRAI` test passes in RISCOF. Replaces an earlier debug branch (PR #78), which is now obsolete.\n\n## PR Comments\n**marwannismail** (Oct 13, 2025): \"Passed funct7 = instr[31:25] for IType_logic instructions. SRAI test passes in RISCOF. Made a new PR because I made more changes to my other debug branch. I will close the other PR so please ignore #78\"\n\nReviewer requested: TheDeepestSpace (Oct 13, 2025). Author self-assigned (Oct 13, 2025).\n\nMerged by DanielTaoHuang123 at commit ac131e8 on Oct 26, 2025; 4 checks passed.\n\n## Linked Issues\n**Issue #71 - \"Review RISCOF's `RV32I` failures\"** (this PR contributes one of the fixes).\n\nIssue body (verbatim from the source URL):\n\"Review latest RISCOF report (see artifacts of `main` branch's CI run) and fix issues individually as you find them.\"\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/UTOSS_risc-v_pr79", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/UTOSS_risc-v_pr79.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/UTOSS_risc-v_pr79", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/UTOSS_risc-v_pr79"}
{"instance_id": "UTOSS_risc-v_pr80", "issue_text": "# Fix some test cases of lb, lbu, lh, lhu\n\nInstance: UTOSS_risc-v_pr80\nSource: https://github.com/UTOSS/risc-v/pull/80\nFetched: 2026-05-03\nRepository: UTOSS/risc-v\nPull request: #80\nAuthor: Invisipac\nState: closed\nBase branch: main\nHead branch: load-fixes\nCreated: 2025-10-19\nUpdated: 2025-10-26\nClosed: 2025-10-26\nMerged: 2025-10-26\n\n## PR Title\nFix some test cases of lb, lbu, lh, lhu\n\n## PR Description\nNo description provided. Across 5 commits this PR adds explicit `funct3` cases in `top` for the byte/half-word load instructions and corrects the data path so that `lb`, `lbu`, `lh`, and `lhu` produce the expected results.\n\n## PR Comments\nNo conversation comments were posted on the PR. Commits:\n1. \"fix a few of the test cases for the load instructions by adding cases for funct3 in top\" (6c33fa5)\n2. \"add some comments for funct3\" (816b7f7)\n3. \"made all load commands work\" (8b318ef)\n4. \"add some comments\" (3d01d6b)\n5. \"fixed small typo\" (7c697bf)\n\nParticipants: Invisipac (author), DanielTaoHuang123 (reviewer/merger).\n\n## Linked Issues\n**Issue #71 - \"Review RISCOF's `RV32I` failures\"** (this PR contributes load-instruction fixes).\n\nIssue body (verbatim from the source URL):\n\"Review latest RISCOF report (see artifacts of `main` branch's CI run) and fix issues individually as you find them.\"\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/UTOSS_risc-v_pr80", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/UTOSS_risc-v_pr80.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/UTOSS_risc-v_pr80", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/UTOSS_risc-v_pr80"}
{"instance_id": "UTOSS_risc-v_pr81", "issue_text": "# Fix testcases for sb, sh\n\nInstance: UTOSS_risc-v_pr81\nSource: https://github.com/UTOSS/risc-v/pull/81\nFetched: 2026-05-03\nRepository: UTOSS/risc-v\nPull request: #81\nAuthor: DanielTaoHuang123\nState: closed\nBase branch: main\nHead branch: daniel-sb-sh-fix\nCreated: 2025-10-26\nUpdated: 2025-11-03\nClosed: 2025-11-03\nMerged: 2025-11-03\n\n## PR Title\nFix testcases for sb, sh\n\n## PR Description\n\"change the WE in MA from 1 bit to 4 bits to support byte level write; change the WE of FSM accordingly; fix sb and sh (fix WD)\"\n\nThis is the follow-up to PR #80 (which fixed `lb`/`lh`/`lhu`). The Memory-Access Write Enable signal is widened from 1 bit to 4 bits to support byte-granularity writes; the FSM is updated accordingly; the `sb` and `sh` store instructions are corrected (including the write-data path). The MemoryLoader module is also enhanced to prepare data for storing into memory, where dataB is the raw word from the CPU and `__tmp_MemData` together with `MemWriteByteAddress` selects which byte to write.\n\n## PR Comments\n**TheDeepestSpace** (Nov 2, 2025): Clarified the architectural intent: \"MemoryLoader now also prepares the data for storing it into memory...dataB is essentially the raw word from the CPU to write to memory, and `__tmp_MemData` together with `MemWriteByteAddress` tell us exactly which byte to write.\"\n\n**DanielTaoHuang123** (Nov 9, 2025): \"yes\" (confirming the explanation).\n\nMerged by TheDeepestSpace on Nov 3, 2025.\n\n## Linked Issues\n**Issue #71 - \"Review RISCOF's `RV32I` failures\"** (this PR fixes the `sb`/`sh` failures).\n\nIssue body (verbatim from the source URL):\n\"Review latest RISCOF report (see artifacts of `main` branch's CI run) and fix issues individually as you find them.\"\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/UTOSS_risc-v_pr81", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/UTOSS_risc-v_pr81.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/UTOSS_risc-v_pr81", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/UTOSS_risc-v_pr81"}
{"instance_id": "UTOSS_risc-v_pr83", "issue_text": "# Extracted RF module and tested with RISCOF\n\nInstance: UTOSS_risc-v_pr83\nSource: https://github.com/UTOSS/risc-v/pull/83\nFetched: 2026-05-03\nRepository: UTOSS/risc-v\nPull request: #83\nAuthor: marwannismail\nState: closed\nBase branch: main\nHead branch: mi_rf_extraction\nCreated: 2025-10-26\nUpdated: 2025-10-28\nClosed: 2025-10-28\nMerged: 2025-10-28\n\n## PR Title\nExtracted RF module and tested with RISCOF\n\n## PR Description\nAddresses issue #58 by extracting the Register File (RF) module from the instruction decoder and relocating it to `top.v`. The change is validated through RISCOF testing - expected tests pass - and existing testbenches are modified to reflect the new signal locations.\n\n## PR Comments\n**marwannismail** (Oct 26, 2025): Noted that resolving the merge conflict required uncommenting the `funct3` declaration and accepting changes that removed `clk`, `reset`, `ResultsData`, `baseAddr`, and `writeData` as ports of the Instruction_Decode module.\n\n**marwannismail** (Oct 26, 2025): \"Merge conflict resolved manually once merged main into working branch and added tweaks.\"\n\n**TheDeepestSpace** (Oct 27, 2025): \"This looks great!\" Indicated willingness to merge pending feedback from another contributor.\n\n## Linked Issues\n**Issue #58 - \"Extract RF module from instruction decoder\"** (closed by this PR).\n\nIssue body (verbatim from the source URL):\n\"RF and instruction decoding seem to be quite different in their functionalities so it might make sense to stick RF right into `top` since its a pretty integral module.\"\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/UTOSS_risc-v_pr83", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/UTOSS_risc-v_pr83.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/UTOSS_risc-v_pr83", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/UTOSS_risc-v_pr83"}
{"instance_id": "UTOSS_risc-v_pr85", "issue_text": "# Add jalr feature, fix tb issues and add more tb for jal and jalr\n\nInstance: UTOSS_risc-v_pr85\nSource: https://github.com/UTOSS/risc-v/pull/85\nFetched: 2026-05-03\nRepository: UTOSS/risc-v\nPull request: #85\nAuthor: RunzeZhu28\nState: closed\nBase branch: main\nHead branch: tony_jalr\nCreated: 2025-10-27\nUpdated: 2025-10-28\nClosed: 2025-10-28\nMerged: 2025-10-28\n\n## PR Title\nAdd jalr feature, fix tb issues and add more tb for jal and jalr\n\n## PR Description\nNo description was provided. The PR adds support for `jalr`, fixes existing testbench issues, and expands tests for both `jal` and `jalr`. Two commits: 9828b2f and 5fef62b.\n\n## PR Comments\n**TheDeepestSpace** (Oct 28, 2025): Suggested minimising FSM states to reduce flip-flops. Noted that `JALR_CALC` duplicates `MEMADR` functionality and recommended renaming `JALR_STEP2` to `JALRWB` for consistency. Approved with \"Looks great, thanks Tony!\"\n\n## Linked Issues\n**Issue #71 - \"Review RISCOF's `RV32I` failures\"** (this PR contributes `jal`/`jalr` fixes).\n\nIssue body (verbatim from the source URL):\n\"Review latest RISCOF report (see artifacts of `main` branch's CI run) and fix issues individually as you find them.\"\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/UTOSS_risc-v_pr85", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/UTOSS_risc-v_pr85.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/UTOSS_risc-v_pr85", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/UTOSS_risc-v_pr85"}
{"instance_id": "UTOSS_risc-v_pr95", "issue_text": "# Update `iverilog` to latest snapshot\n\nInstance: UTOSS_risc-v_pr95\nSource: https://github.com/UTOSS/risc-v/pull/95\nFetched: 2026-05-03\nRepository: UTOSS/risc-v\nPull request: #95\nAuthor: TheDeepestSpace\nState: closed\nBase branch: main\nHead branch: boris/update-verilog\nCreated: 2025-10-28\nUpdated: 2025-10-28\nClosed: 2025-10-28\nMerged: 2025-10-28\n\n## PR Title\nUpdate `iverilog` to latest snapshot\n\n## PR Description\nNo description was provided. Single commit (9cdf413): \"update iverilog to latest snapshot.\"\n\n## PR Comments\nNo conversation comments. Activity: TheDeepestSpace self-assigned, linked issue #64, and merged at commit 0e5962b. 4 checks passed.\n\n## Linked Issues\n**Issue #64 - \"Update `iverilog`\"** (closed by this PR).\n\nIssue body (verbatim from the source URL):\n\"Move to a newer version of `iverilog`. We are at 12.0, which is the latest stable one but its over 2 years old, and we may be missing out on a log of bug fixes and new features. Let's bump up to latest master (see https://github.com/steveicarus/iverilog) and keep tabs on new releases.\"\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/UTOSS_risc-v_pr95", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/UTOSS_risc-v_pr95.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/UTOSS_risc-v_pr95", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/UTOSS_risc-v_pr95"}
{"instance_id": "UTOSS_risc-v_pr97", "issue_text": "# Fix more stylistic infractions\n\nInstance: UTOSS_risc-v_pr97\nSource: https://github.com/UTOSS/risc-v/pull/97\nFetched: 2026-05-03\nRepository: UTOSS/risc-v\nPull request: #97\nAuthor: TheDeepestSpace\nState: closed\nBase branch: main\nHead branch: boris/svlint-style-keyword\nCreated: 2025-10-28\nUpdated: 2025-10-28\nClosed: 2025-10-28\nMerged: 2025-10-28\n\n## PR Title\nFix more stylistic infractions\n\n## PR Description\nNo description was provided. Single commit \"fix more infractions\" (e745cd9). The PR addresses additional SVLint style-ruleset violations as part of the broader effort tracked in issue #91.\n\n## PR Comments\nNo conversation comments. TheDeepestSpace self-assigned, then merged commit 95d3d06 into main on Oct 28, 2025; 4 checks passed.\n\n## Linked Issues\n**Issue #91 - \"Integrate SVLint's style ruleset\"** (closed by this PR).\n\nIssue body (verbatim from the source URL):\n\"See https://github.com/dalance/svlint/blob/15d7ccba7de2ec55dffd4dbfbd174a700b912ff2/rulesets/style.toml\"\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/UTOSS_risc-v_pr97", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/UTOSS_risc-v_pr97.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/UTOSS_risc-v_pr97", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/UTOSS_risc-v_pr97"}
{"instance_id": "Wren6991_Hazard3_pr23", "issue_text": "# Fix abstract command using wrong register when initiated by abstractauto\n\nInstance: Wren6991_Hazard3_pr23\nSource: https://github.com/Wren6991/Hazard3/pull/23\nFetched: 2026-04-26\nRepository: Wren6991/Hazard3\nPull request: #23\nAuthor: Wren6991\nState: closed\nBase branch: stable\nHead branch: fix-dm-abstractauto-regno\nCreated: 2024-10-12T18:58:43Z\nUpdated: 2024-10-12T22:57:18Z\nClosed: 2024-10-12T19:03:45Z\nMerged: 2024-10-12T19:03:45Z\n\nThis affects memory downloads from the debugger when System Bus Access is not enabled or not configured.\r\n\r\nThis bug was introduced in https://github.com/Wren6991/Hazard3/commit/78a5cb98ea5d184c7b8bf31249ce8ac69e4abf68\r\n\r\nReleasing as a point fix due to severity and due to the fix being localised to the Debug Module.\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/Wren6991_Hazard3_pr23", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/Wren6991_Hazard3_pr23.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/Wren6991_Hazard3_pr23", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/Wren6991_Hazard3_pr23"}
{"instance_id": "Wren6991_Hazard3_pr28", "issue_text": "# Coding style change for Verilator compatibility (fixes #21)\n\nInstance: Wren6991_Hazard3_pr28\nSource: https://github.com/Wren6991/Hazard3/pull/28\nFetched: 2026-04-26\nRepository: Wren6991/Hazard3\nPull request: #28\nAuthor: Wren6991\nState: closed\nBase branch: stable\nHead branch: fix-21\nCreated: 2024-12-09T05:41:41Z\nUpdated: 2025-06-09T00:00:13Z\nClosed: 2024-12-09T05:55:00Z\nMerged: 2024-12-09T05:55:00Z\n\nThe boundary_conditions process in hazard3_frontend needs to be scheduled at least twice to resolve to the correct values. There are multiple possible interleavings, which should all result in the same result. However Verilator schedules the process only once.\r\n\r\nWork around this by moving the tie-off of the problematic variable into the synchronous update process.\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/Wren6991_Hazard3_pr28", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/Wren6991_Hazard3_pr28.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/Wren6991_Hazard3_pr28", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/Wren6991_Hazard3_pr28"}
{"instance_id": "Wren6991_Hazard3_pr41", "issue_text": "# Release v1.1.1 to stable\n\nInstance: Wren6991_Hazard3_pr41\nSource: https://github.com/Wren6991/Hazard3/pull/41\nFetched: 2026-04-26\nRepository: Wren6991/Hazard3\nPull request: #41\nAuthor: Wren6991\nState: closed\nBase branch: stable\nHead branch: develop\nCreated: 2026-03-12T18:19:01Z\nUpdated: 2026-03-12T18:28:21Z\nClosed: 2026-03-12T18:28:21Z\nMerged: 2026-03-12T18:28:21Z\n\n## PR Title\nRelease v1.1.1 to stable\n\n## PR Description\nNo description was provided for this pull request. The PR is a release-merge of `develop` into `stable` containing 8 commits that constitute Hazard3 v1.1.1:\n\n1. Update mimpid: 1.2 prerelease\n2. Fix repeated transfer on APB async bridge when instantiated separately to the JTAG-DTM\n3. Don't report failed exclusive writes as faults in `rvfi_bus_observer`; latch `rvfi_intr` signal; fix exclusives hookup in riscv-formal tb\n4. Fix uninitialised variable in `wfi_loop` tests\n5. Fix non-synthesisable statement in `hazard3_rvfi_monitor` when `HAZARD3_RVFI_STANDALONE` is defined\n6. Fix RVFI monitor reporting memory write for exclusive store that fails in data phase\n7. Fix: hardware breakpoint on CSR-writing instruction does not inhibit CSR write\n8. Set `mimpid` version to 1.1.1; update release notes in asciidoc\n\n## PR Comments\nNo conversation comments were posted on the PR. No assignees, labels, milestones, or external reviewers.\n\n## Linked Issues\nNo linked issues are referenced in this pull request.\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/Wren6991_Hazard3_pr41", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/Wren6991_Hazard3_pr41.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/Wren6991_Hazard3_pr41", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/Wren6991_Hazard3_pr41"}
{"instance_id": "YosysHQ_nerv_pr14", "issue_text": "# iverilog 13.0 errors\n\n- Source URL: https://github.com/YosysHQ/nerv/issues/13\n\nRunning `make` with the latest version of iverilog bundled with https://github.com/YosysHQ/oss-cad-suite-build/releases/tag/2025-02-20 gives the following error on Ubuntu 24.04.\n\n```\nriscv64-unknown-elf-gcc -march=rv32i_zicsr -mabi=ilp32 -Os -Wall -Wextra -Wl,-Bstatic,-T,sections.lds,--strip-debug -ffreestanding -nostdlib -o firmware.elf firmware.s vectors.s firmware.c\n/usr/lib/gcc/riscv64-unknown-elf/13.2.0/../../../riscv64-unknown-elf/bin/ld: warning: firmware.elf has a LOAD segment with RWX permissions\nriscv64-unknown-elf-objcopy -O verilog firmware.elf firmware.hex\n/home/philip/Downloads/oss-cad-suite-linux-x64-20250220/oss-cad-suite/bin/iverilog -g2012 -o testbench -D STALL -D NERV_DBGREGS testbench.sv nerv.sv\nnerv.sv:565: error: Unable to bind wire/reg/memory `irq_num' in `testbench.dut'\nnerv.sv:625:      : A symbol with that name was declared here. Check for declaration after use.\nnerv.sv:565: error: Unable to elaborate r-value: ((((running)&&(imem_valid))&&(!(irq_num)))&&((insn_opcode)==(OPCODE_SYSTEM)))?(insn_funct3['sd1:'sd0]):(2'd0)\nnerv.sv:612: error: Net csr_hpm_event_sel['sd2:'sd0] is not defined in this context.\nnerv.sv:1171:      : A symbol with that name was declared here. Check for declaration after use.\nnerv.sv:613: error: Net csr_hpm_counter_sel['sd1] is not defined in this context.\nnerv.sv:766:      : A symbol with that name was declared here. Check for declaration after use.\nnerv.sv:614: error: Net csr_hpm_counterh_sel['sd1] is not defined in this context.\nnerv.sv:967:      : A symbol with that name was declared here. Check for declaration after use.\nnerv.sv:1052: error: Unable to bind wire/reg/memory `mem_rdata' in `testbench.dut'\nnerv.sv:1087:      : A symbol with that name was declared here. Check for declaration after use.\n6 error(s) during elaboration.\nmake: *** [Makefile:32: testbench] Error 6\n```\n\n```\n/oss-cad-suite-linux-x64-20250220/oss-cad-suite/bin/iverilog -v\nIcarus Verilog version 13.0 (devel) (s20250103-25-g99580cd05)\n```\n\n\nReverting to iverilog 12.0 makes it work.\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/YosysHQ_nerv_pr14", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/YosysHQ_nerv_pr14.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/YosysHQ_nerv_pr14", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/YosysHQ_nerv_pr14"}
{"instance_id": "YosysHQ_picorv32_pr229", "issue_text": "# Bugfix: decode fence instruction\n\nInstance: YosysHQ_picorv32_pr229\nSource: https://github.com/YosysHQ/picorv32/pull/229\nFetched: 2026-05-03\nRepository: YosysHQ/picorv32\nPull request: #229\nAuthor: flaviens\nState: closed\nBase branch: master\nHead branch: fence\nCreated: 2023-02-20\nUpdated: 2023-11-16\nClosed: 2023-11-16\nMerged: 2023-11-16\n\n## PR Title\nBugfix: decode fence instruction\n\n## PR Description\nAddresses issue #228. Adds proper decoding for the base RV32I `fence` instruction so it no longer raises an instruction trap. The author invites style suggestions: \"Please feel free to improve the style.\"\n\n## PR Comments\n**flaviens** (Feb 20, 2023): \"Hi! This pull request fixes #228. Please feel free to improve the style. Thanks!\"\n\n**jix** (Feb 21, 2023, review): Noted that fence-instruction support was missing and identified an off-by-one error in the proposed decoding logic. Mentioned discussing the topic with @clairexen and referenced RISC-V specification requirements regarding future fence-extension forms with non-zero `rs1` and `rd` values. Stated intent to add fence support to riscv-formal before merging so the fix could be formally verified.\n\n**flaviens** (Feb 22, 2023): \"Hi @jix thank you for your quick review! That's absolutely right, I updated the PR.\"\n\n**clairexen** (Nov 16, 2023): Merged the PR into master at commit c0acaeb.\n\n## Linked Issues\n**Issue #228 - \"Bug report: fence instruction raises instruction trap\"** (closed by this PR).\n\nIssue body (verbatim from the source URL):\n\"Hi there!\n\nThe `fence` instruction is part of the base rv32i ISA and is incorrectly decoded in picorv32 since it systematically raises an instruction trap.\"\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/YosysHQ_picorv32_pr229", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/YosysHQ_picorv32_pr229.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/YosysHQ_picorv32_pr229", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/YosysHQ_picorv32_pr229"}
{"instance_id": "YosysHQ_picorv32_pr244", "issue_text": "# Fix RV32E shifts by immediates >= 0x10\n\nInstance: YosysHQ_picorv32_pr244\nSource: https://github.com/YosysHQ/picorv32/pull/244\nFetched: 2026-05-03\nRepository: YosysHQ/picorv32\nPull request: #244\nAuthor: MichaelBell\nState: closed\nBase branch: main\nHead branch: fix-rv32e\nCreated: 2023-08-20\nUpdated: 2024-03-26\nClosed: 2024-03-26\nMerged: 2024-03-26\n\n## PR Title\nFix RV32E shifts by immediates >= 0x10\n\n## PR Description\nResolves issue #211. Makes shift-by-immediate instructions on the RV32E configuration use the full 5-bit immediate field rather than truncating it to 4 bits, so e.g. `slli` works with shift amounts >= 0x10. The author notes they did not exhaustively test other RV32E instructions but did not find further breakage in cursory testing, and that the change appears not to break Q-register instructions on RV32I (untested).\n\n## PR Comments\n**MichaelBell** (Aug 20, 2023): \"This fixes #211. I haven't found any other broken instructions on RV32E, but I haven't done rigorous testing. A cursory check suggests this change doesn't break the Q register instructions in RV32I, but I haven't tested that at all.\"\n\n**KrystalDelusion** (Mar 26, 2024): Force-pushed and merged the PR at commit de92ce5.\n\n## Linked Issues\n**Issue #211 - \"Bug when using RV32E (ENABLE_REGS_16_31=0)\"** (closed by this PR).\n\nIssue body (verbatim from the source URL):\n\"Support for rv32e is buggy.  Setting ENABLE_REGS_16_31 = 0 leads to the following:\n\n- regindex_bits will be 4 (instead of 5)\n- decoded_rs2 will be 4 bits wide (instead of 5)\n- reg_sh will be set to the 4 least significant bits of the immediate field of the instruction, instead of the full 5 bits\n- shift immediate instructions will fail (e.g. slli)\n\nEasily fixed by setting decoded_rs2 (and possibly decoded_rs1 and decoded_rs) fixed 5 bits wide, instead of having it depend on the size of the register file.\"\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/YosysHQ_picorv32_pr244", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/YosysHQ_picorv32_pr244.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/YosysHQ_picorv32_pr244", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/YosysHQ_picorv32_pr244"}
{"instance_id": "YosysHQ_picorv32_pr9", "issue_text": "# Deassert pcpi_valid upon asserting sbreak IRQ\n\nInstance: YosysHQ_picorv32_pr9\nSource: https://github.com/YosysHQ/picorv32/pull/9\nFetched: 2026-05-03\nRepository: YosysHQ/picorv32\nPull request: #9\nAuthor: stevekerrison\nState: closed\nBase branch: master\nHead branch: master (stevekerrison/picorv32 fork)\nCreated: 2016-05-31\nUpdated: 2016-06-01\nClosed: 2016-06-01\nMerged: 2016-06-01\n\n## PR Title\nDeassert pcpi_valid upon asserting sbreak IRQ\n\n## PR Description\nAddresses issue #8 (incorrect handling of SBREAK / illegal instructions when PCPI is enabled): on `sbreak` / illegal instruction the core now deasserts `pcpi_valid` when raising the SBREAK IRQ, so the next valid PCPI instruction is not mis-flagged as another `sbreak`.\n\nThe author notes two remaining considerations:\n1. Instructions like `sbreak` take roughly 16 cycles to trigger an IRQ because of PCPI timeout delays; immediate IRQ triggering for these instructions could be useful, though external PCPI modules might handle it differently.\n2. The behaviour of `sbreak` or illegal instructions inside ISRs is not examined here, although trapping seems like the natural answer.\n\n## PR Comments\n**stevekerrison** (May 31, 2016): \"This fixes #8\" along with the two unresolved follow-up considerations described above.\n\nThe PR was merged on Jun 1, 2016.\n\n## Linked Issues\n**Issue #8 - \"Incorrect handling of SBREAK/ILLNSN with PCPI\"** (closed by this PR).\n\nIssue body (verbatim from the source URL):\n\"I'm trying to put a minimal example of this together (or a patch if I get there quicker), but won't get a chance until tomorrow. I leave this here for now as a test of my own sanity.\n\nIf PCPI is enabled and an illegal instruction or `sbreak` occur, upon `retirq`, the signal `pcpi_valid` remains asserted. The eventual effect of this is that when the next valid PCPI instruction comes along, it causes another `SBREAK` IRQ to occur, presumably because the PCPI timeout never got reset.\n\nI actually want to handle `ecall`, and I guess I could do it with another PCPI extension, but that seems like a less graceful solution.\"\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/YosysHQ_picorv32_pr9", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/YosysHQ_picorv32_pr9.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/YosysHQ_picorv32_pr9", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/YosysHQ_picorv32_pr9"}
{"instance_id": "ZipCPU_wb2axip_pr71", "issue_text": "# Fixed calculation of sufficiently_filled when the FIFO is full and aw_requests_remaining is less than a maximum burst\n\nInstance: ZipCPU_wb2axip_pr71\nSource: https://github.com/ZipCPU/wb2axip/pull/71\nFetched: 2026-05-03\nRepository: ZipCPU/wb2axip\nPull request: #71\nAuthor: mbiermann-mo-space\nState: closed\nBase branch: master\nHead branch: fix/axis2mm_sufficiently_filled\nCreated: 2025-01-16\nUpdated: 2025-02-05\nClosed: 2025-01-23\nMerged: 2025-01-23\n\n## PR Title\nFixed calculation of sufficiently_filled when the FIFO is full and aw_requests_remaining is less than a maximum burst\n\n## PR Description\nWhen `aw_requests_remaining` is less than `1 << LGMAXBURST`, the entire `data_available` value should be checked instead of just the lower `data_available[LGMAXBURST-1:0]` slice. In the contributor's case `data_available` was `0x200`, so the slice evaluated to 0 and the transfer never finished. Fixes issue #69.\n\n## PR Comments\n**mbiermann-mo-space** (Jan 16, 2025): Initial pull request submission with the problem description.\n\n**ZipCPU** (Jan 17, 2025): \"Pending further discussion and review.\"\n\n**ZipCPU** (Jan 23, 2025): \"Thank you. Dan\" - merged the PR.\n\n**mbiermann-mo-space** (Feb 5, 2025): Deleted the feature branch.\n\n## Linked Issues\n**Issue #69 - \"axis2mm hangs for small transaction sizes when the FIFO is full (i.e. when r_continuous is set to 1)\"** (closed by this PR).\n\nIssue body (verbatim from the source URL):\n\"Maybe I'm misinterpreting the correct usage of r_continuous.\nThe FIFO being reset means that some data is lost correct?\nI'd like to avoid that however this isn't critical for my application so for now a workaround is to just not use r_continuous.\n\nThe core reports it is busy however S_AXIS_TREADY stays at 0 and the transfer is never finished (even after several seconds r_busy stays 1 for small transfer sizes).\n\nFor me it happens when I:\n- direct the core to write 1MiB\n- don't start another transfer immediately after (no error bit is set though)\n- after a while start another transfer\n  - from a new address instead of the one where the core left off (the address is the same as for the first transfer)\n  - with a comparatively low length (16 bytes and 1024 bytes both don't work, 4096 bytes does)\"\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/ZipCPU_wb2axip_pr71", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/ZipCPU_wb2axip_pr71.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/ZipCPU_wb2axip_pr71", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/ZipCPU_wb2axip_pr71"}
{"instance_id": "alexforencich_verilog-pcie_pr19", "issue_text": "# Fix multi-driven net issue when S_RAM_SEL_WIDTH = 0\n\nInstance: alexforencich_verilog-pcie_pr19\nSource: https://github.com/alexforencich/verilog-pcie/pull/19\nFetched: 2026-04-26\nRepository: alexforencich/verilog-pcie\nPull request: #19\nAuthor: Basseuph\nState: closed\nBase branch: master\nHead branch: mle/fix_multi_net_driver\nCreated: 2021-12-10T16:52:24Z\nUpdated: 2021-12-10T20:56:16Z\nClosed: 2021-12-10T20:47:04Z\nMerged: 2021-12-10T20:47:04Z\n\n## PR Title\nFix multi-driven net issue when S_RAM_SEL_WIDTH = 0\n\n## PR Description\nAs per a discussion on slack we built a corundum design with a single interface and multiple ports and there were actually two issues. One was fixed already, see 3a124837115e51e2273ab7d1c61d80ee01f891c1 in verilog-pcie. A very similar one was still to be fixed and this PR now proposes the respective fix.\n\nThe PR adapts the same fix that was already applied to the `dma_ram_demux_rd.v` module to the `dma_ram_demux_wr.v` module.\n\n## PR Comments\n\n**Basseuph** (Dec 10, 2021):\nThe submitter's initial message explained the context and referenced a similar fix that had already been applied to the `dma_ram_demux_rd.v` module, noting this PR adapts that same solution to the `dma_ram_demux_wr.v` module.\n\n**alexforencich** (Dec 10, 2021):\n\"LGTM\" (looks good to me)\n\n**alexforencich** (Dec 10, 2021):\n\"dang it, I thought I selected the right option to avoid the merge commit. I guess I need to clean that up...\"\n\n**alexforencich** (Dec 10, 2021):\n\"I just pulled it directly from your branch; I'll get this merged into Corundum shortly. Also, I recommend adding your MLE email address to your github profile so your commits will link back to your github account.\"\n\n## Linked Issues\nNo linked issues are referenced in this pull request.\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/alexforencich_verilog-pcie_pr19", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/alexforencich_verilog-pcie_pr19.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/alexforencich_verilog-pcie_pr19", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/alexforencich_verilog-pcie_pr19"}
{"instance_id": "alexforencich_verilog-pcie_pr20", "issue_text": "# Fix reg to wire declaration\n\nInstance: alexforencich_verilog-pcie_pr20\nSource: https://github.com/alexforencich/verilog-pcie/pull/20\nFetched: 2026-04-26\nRepository: alexforencich/verilog-pcie\nPull request: #20\nAuthor: joft-mle\nState: closed\nBase branch: master\nHead branch: mle/fix-202112b\nCreated: 2021-12-15T18:14:34Z\nUpdated: 2021-12-17T08:39:51Z\nClosed: 2021-12-16T08:27:43Z\nMerged: 2021-12-16T08:27:43Z\n\n## PR Title\nFix reg to wire declaration\n\n## PR Description\nJust a small independent one-line issue spotted by @andreasbraun90 during the ongoing ZynqMP porting effort.\n\n## PR Comments\n\n**joft-mle** (Dec 15, 2021):\n\"Just a small independent one-line issue spotted by @andreasbraun90 during the ongoing ZynqMP porting effort.\"\n\n**alexforencich** (Dec 16, 2021):\n\"Nice, I will get this merged into Corundum shortly\"\n\n## PR Metadata\n- Status: Merged\n- Merged by: alexforencich\n- Merge date: Dec 16, 2021\n- Commit: be331e7\n- Author: Andreas Braun (missinglinkelectronics)\n- Participants: joft-mle, alexforencich, andreasbraun90\n\n## Linked Issues\nNo linked issues were referenced in this pull request.\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/alexforencich_verilog-pcie_pr20", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/alexforencich_verilog-pcie_pr20.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/alexforencich_verilog-pcie_pr20", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/alexforencich_verilog-pcie_pr20"}
{"instance_id": "aolofsson_oh_pr109", "issue_text": "# Fix width of padring 'dout' ports\n\nInstance: aolofsson_oh_pr109\nSource: https://github.com/aolofsson/oh/pull/109\nFetched: 2026-04-26\nRepository: aolofsson/oh\nPull request: #109\nAuthor: nmoroze\nState: closed\nBase branch: master\nHead branch: master\nCreated: 2021-07-06T21:52:56Z\nUpdated: 2021-07-25T02:11:39Z\nClosed: 2021-07-25T02:11:39Z\nMerged: 2021-07-25T02:11:39Z\n\n## PR Title\nFix width of padring 'dout' ports\n\n## PR Description\nNo description body was provided in this pull request.\n\n## PR Comments\n\n**nmoroze** (Jul 6, 2021):\n\"I believe the extra `-1`s are likely a typo!\"\n\n**aolofsson** (Jul 25, 2021):\n\"Thanks for the fix!\"\n\n## PR Metadata\n- Status: Merged\n- Merge Date: Jul 25, 2021\n- Commit Hash: b52c45d119d346094d92ae467abefcc073355eb9\n- Source Branch: nmoroze/oh:master\n- Target Branch: aolofsson/oh:master\n- Participants: nmoroze, aolofsson\n\n## Linked Issues\nNo linked issues were referenced in this pull request.\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/aolofsson_oh_pr109", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/aolofsson_oh_pr109.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/aolofsson_oh_pr109", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/aolofsson_oh_pr109"}
{"instance_id": "aolofsson_oh_pr110", "issue_text": "# Add \"tech config\" pass-through for technology-specific GPIO configuration\n\nInstance: aolofsson_oh_pr110\nSource: https://github.com/aolofsson/oh/pull/110\nFetched: 2026-04-26\nRepository: aolofsson/oh\nPull request: #110\nAuthor: nmoroze\nState: closed\nBase branch: master\nHead branch: master\nCreated: 2021-08-10T14:36:30Z\nUpdated: 2021-08-16T02:49:10Z\nClosed: 2021-08-16T02:49:10Z\nMerged: 2021-08-16T02:49:10Z\n\nSorry for the large diff, oh_padring.v had something going on with a mix of tabs and spaces that was screwing up my editor, so I fixed that up. \r\n\r\nAlso, I'm not 100% sold on the name tech_cfg, so happy to take suggestions there.\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/aolofsson_oh_pr110", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/aolofsson_oh_pr110.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/aolofsson_oh_pr110", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/aolofsson_oh_pr110"}
{"instance_id": "aolofsson_oh_pr111", "issue_text": "# Some tweaks to padring library\n\nInstance: aolofsson_oh_pr111\nSource: https://github.com/aolofsson/oh/pull/111\nFetched: 2026-04-26\nRepository: aolofsson/oh\nPull request: #111\nAuthor: nmoroze\nState: closed\nBase branch: master\nHead branch: master\nCreated: 2021-11-23T18:33:06Z\nUpdated: 2021-11-27T02:15:20Z\nClosed: 2021-11-27T02:15:20Z\nMerged: 2021-11-27T02:15:20Z\n\n## PR Title\nSome tweaks to padring library\n\n## PR Description\nNo description provided.\n\n## PR Comments\n\n**nmoroze** (Nov 23, 2021):\nNo comment text provided.\n\n**aolofsson** (Nov 27, 2021):\n\"Nice changes!\"\n\n## Commits Included\nThe PR contains 4 commits:\n1. Fix typo\n2. Add ring port for tech-specific power-ring signals\n3. Make tech_cfg an inout so it can expose tieoffs\n4. Pass through tech_cfg_width to iobuf\n\n## PR Status\nMerged on Nov 27, 2021 by aolofsson into the master branch.\n\n## Linked Issues\nNo linked issues are referenced in this pull request.\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/aolofsson_oh_pr111", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/aolofsson_oh_pr111.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/aolofsson_oh_pr111", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/aolofsson_oh_pr111"}
{"instance_id": "aolofsson_oh_pr114", "issue_text": "# Merging master into main\n\nInstance: aolofsson_oh_pr114\nSource: https://github.com/aolofsson/oh/pull/114\nFetched: 2026-04-26\nRepository: aolofsson/oh\nPull request: #114\nAuthor: aolofsson\nState: closed\nBase branch: main\nHead branch: master\nCreated: 2022-10-18T01:10:02Z\nUpdated: 2022-10-18T01:10:13Z\nClosed: 2022-10-18T01:10:13Z\nMerged: 2022-10-18T01:10:13Z\n\n## PR Title\nMerging master into main\n\n## PR Status\nMerged (October 18, 2022)\n\n## PR Description\nNo description provided.\n\n## Commits Included\nThe pull request contains 2 commits:\n1. \"Simplifying bin2gray converter\" (commit f21be19)\n2. \"Fixing random compile issue with -y include in surelog\" (commit b8a962e)\n\n## PR Comments\n**aolofsson** (Owner): No description provided.\n\n## Linked Issues\nNo linked issues are referenced in this pull request.\n\n## Additional Details\n- Author: aolofsson\n- Repository: aolofsson/oh\n- Merge Commit: c251f75\n- Reviewers: None\n- Assignees: None\n- Labels: None\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/aolofsson_oh_pr114", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/aolofsson_oh_pr114.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/aolofsson_oh_pr114", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/aolofsson_oh_pr114"}
{"instance_id": "aolofsson_oh_pr58", "issue_text": "# Initial Commit of 8b10b Encoder and Decoder\n\nInstance: aolofsson_oh_pr58\nSource: https://github.com/aolofsson/oh/pull/58\nFetched: 2026-04-26\nRepository: aolofsson/oh\nPull request: #58\nAuthor: prasadp4009\nState: closed\nBase branch: master\nHead branch: master\nCreated: 2016-03-25T23:08:19Z\nUpdated: 2016-03-25T23:19:44Z\nClosed: 2016-03-25T23:19:44Z\nMerged: 2016-03-25T23:19:44Z\n\n## PR Title\nInitial Commit of 8b10b Encoder and Decoder\n\n## PR Description\nSigned-off-by: Prasad Pandit <prasadp4009@gmail.com>\n\n## PR Comments\n\n**prasadp4009** (Mar 25, 2016):\n\"Both 8b10b Encoder and Decoder use K-map optimized logic. Further improvements are on way with pipeline to improve performance. Current synthesis report explains the both modules perform at 385MHz on Virtex II. Suggestions and improvements are welcome.\"\n\n**aolofsson** (Mar 25, 2016):\n\"Awesome!\"\n\n## Merge Information\n- Merged by: aolofsson\n- Merge commit: 0142315\n- Source branch: prasadp4009:master\n- Target branch: aolofsson:master\n\n## Linked Issues\nNone identified in the pull request content.\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/aolofsson_oh_pr58", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/aolofsson_oh_pr58.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/aolofsson_oh_pr58", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/aolofsson_oh_pr58"}
{"instance_id": "aolofsson_oh_pr73", "issue_text": "# GPIO: Fix hardcoded address width\n\nInstance: aolofsson_oh_pr73\nSource: https://github.com/aolofsson/oh/pull/73\nFetched: 2026-04-26\nRepository: aolofsson/oh\nPull request: #73\nAuthor: olajep\nState: closed\nBase branch: master\nHead branch: gpio-fix-hardcoded-width\nCreated: 2016-04-27T22:36:10Z\nUpdated: 2016-05-16T21:03:57Z\nClosed: 2016-04-29T16:42:06Z\nMerged: 2016-04-29T16:42:06Z\n\nUse parameter value (which can be smaller).\n\nSigned-off-by: Ola Jeppsson ola@adapteva.com\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/aolofsson_oh_pr73", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/aolofsson_oh_pr73.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/aolofsson_oh_pr73", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/aolofsson_oh_pr73"}
{"instance_id": "aolofsson_oh_pr74", "issue_text": "# Gpio fpga project\n\nInstance: aolofsson_oh_pr74\nSource: https://github.com/aolofsson/oh/pull/74\nFetched: 2026-04-26\nRepository: aolofsson/oh\nPull request: #74\nAuthor: olajep\nState: closed\nBase branch: master\nHead branch: gpio-fpga-project\nCreated: 2016-04-27T23:02:35Z\nUpdated: 2016-04-29T16:42:05Z\nClosed: 2016-04-29T16:42:05Z\nMerged: 2016-04-29T16:42:05Z\n\n@aolofsson \nShould probably not merge it yet but can you please have a peek at\naxi_gpio.v: does it look right?\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/aolofsson_oh_pr74", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/aolofsson_oh_pr74.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/aolofsson_oh_pr74", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/aolofsson_oh_pr74"}
{"instance_id": "aolofsson_oh_pr75", "issue_text": "# Gpio fpga project\n\nInstance: aolofsson_oh_pr75\nSource: https://github.com/aolofsson/oh/pull/75\nFetched: 2026-04-26\nRepository: aolofsson/oh\nPull request: #75\nAuthor: olajep\nState: closed\nBase branch: master\nHead branch: gpio-fpga-project\nCreated: 2016-05-03T15:49:33Z\nUpdated: 2016-05-03T17:35:54Z\nClosed: 2016-05-03T17:35:54Z\nMerged: 2016-05-03T17:35:54Z\n\nReading and writing from Porcupine pins now works.\n\nThere's something wrong with edge-triggered interrupts (what you can get via sysfs).\nLoks like clearing the interrupt (in the interrupt handler) will create a new edge and a new interrupt and ... spam the system with interrupts. Will look into that next.\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/aolofsson_oh_pr75", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/aolofsson_oh_pr75.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/aolofsson_oh_pr75", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/aolofsson_oh_pr75"}
{"instance_id": "aolofsson_oh_pr81", "issue_text": "# gpio: Fix issue with new emesh packet format\n\nInstance: aolofsson_oh_pr81\nSource: https://github.com/aolofsson/oh/pull/81\nFetched: 2026-04-26\nRepository: aolofsson/oh\nPull request: #81\nAuthor: olajep\nState: closed\nBase branch: master\nHead branch: gpio-fix\nCreated: 2016-05-19T12:06:57Z\nUpdated: 2016-05-19T14:19:35Z\nClosed: 2016-05-19T13:58:04Z\nMerged: 2016-05-19T13:58:04Z\n\nVivado complains since AW is 32 bits wide but emesh_readback.read_data\nis now 64 bits wide.\n\nSigned-off-by: Ola Jeppsson ola@adapteva.com\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/aolofsson_oh_pr81", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/aolofsson_oh_pr81.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/aolofsson_oh_pr81", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/aolofsson_oh_pr81"}
{"instance_id": "aolofsson_oh_pr82", "issue_text": "# Parallella oh gpio spi projects separate address space\n\nInstance: aolofsson_oh_pr82\nSource: https://github.com/aolofsson/oh/pull/82\nFetched: 2026-04-26\nRepository: aolofsson/oh\nPull request: #82\nAuthor: olajep\nState: closed\nBase branch: master\nHead branch: parallella-oh-gpio-spi-projects-separate-address-space\nCreated: 2016-05-19T12:13:56Z\nUpdated: 2016-05-19T14:19:47Z\nClosed: 2016-05-19T13:56:30Z\nMerged: 2016-05-19T13:56:30Z\n\n## PR Title\nParallella oh gpio spi projects separate address space\n\n## PR Description\nNo description provided.\n\n## PR Commits\nThe pull request contained 2 commits:\n\n1. \"gpio: Move out of the way of elink\" (Commit 8a6eb44)\n   - Signed-off-by: Ola Jeppsson <ola@adapteva.com>\n\n2. \"spi: Move out of the way of elink\" (Commit 15b2e9d)\n   - Signed-off-by: Ola Jeppsson <ola@adapteva.com>\n\n## PR Comments\n**@olajep** (May 19, 2016):\n\"No description provided.\"\n\n## Merge Information\n- Merged by: @aolofsson\n- Merge date: May 19, 2016\n- Merge commit: 434b8fd\n- Target branch: aolofsson:master\n- Source branch: olajep:parallella-oh-gpio-spi-projects-separate-address-space\n\n## Linked Issues\nNo linked issues were referenced in this pull request.\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/aolofsson_oh_pr82", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/aolofsson_oh_pr82.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/aolofsson_oh_pr82", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/aolofsson_oh_pr82"}
{"instance_id": "apfaudio_eurorack-pmod_pr36", "issue_text": "# VCO example seems broken after clocking rewrite\n\nAll the examples seem to work fine after switching to 48kHz all round and rewriting the clocking architecture -- except for the VCO example. It smells like a timing issue and this deserves investigation.\n\n- Actually this example still seems to work on the ECP5, it's only broken on ICE40\n\n## PR Content from GitHub\n\n# Pull Request #36: cores/vco - Fix and Modularize VCO Example\n\n## PR Title\n\"cores/vco: fix and modularize vco example\"\n\n## PR Description\nThe PR description is not fully visible in the provided content, but the PR appears to address issues with the VCO (Voltage Controlled Oscillator) example implementation.\n\n## Comments\n**vk2seb** (Sep 17, 2023):\n\"Seems to fix #35\"\n\n## Linked Issue\n**Issue #35 Title:** \"VCO example seems broken after clocking rewrite\"\n\n## Status\nThe pull request was merged on September 17, 2023. However, it was subsequently reverted on September 19, 2023 (commit 7a3af8c) due to place-and-route dependency issues on the icebreaker platform. The changes were later reapplied in October 2023 (commits 20a6b1e and d497970).\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/apfaudio_eurorack-pmod_pr36", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/apfaudio_eurorack-pmod_pr36.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/apfaudio_eurorack-pmod_pr36", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/apfaudio_eurorack-pmod_pr36"}
{"instance_id": "bensampson5_libsv_pr100", "issue_text": "# Combine encoders and decoders into coders\n\n- Source URL: https://github.com/bensampson5/libsv/issues/99\n\n\n## PR Content from GitHub\n\n# Pull Request Summary\n\n**PR Title:** Combine encoders and decoders into coders\n\n**PR Number:** #100\n\n**Status:** Merged\n\n**Repository:** bensampson5/libsv\n\n---\n\n## PR Description Body\n\nThe PR description is not fully visible in the provided content. However, the pull request references closing issue #99 with the same title.\n\n---\n\n## PR Comments\n\n**Author:** bensampson5\n**Comment:** \"Closes #99\"\n\n---\n\n## Linked Issue\n\n**Issue #99 Title:** Combine encoders and decoders into coders\n\n**Issue Body:** Not provided in the content above.\n\n---\n\n## Additional Details\n\n- **Merged by:** bensampson5\n- **Merge date:** November 24, 2021\n- **Commit:** \"Move encoders and decoders into coders\" (237e9b6)\n- **Label:** enhancement (New feature or request)\n- **Assignee:** bensampson5\n- **Branch deleted:** issue-99-Combine_encoders_and_decoders_into_coders\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/bensampson5_libsv_pr100", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/bensampson5_libsv_pr100.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/bensampson5_libsv_pr100", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/bensampson5_libsv_pr100"}
{"instance_id": "bensampson5_libsv_pr102", "issue_text": "# 8b/10b decoder\n\n- Source URL: https://github.com/bensampson5/libsv/issues/101\n\nhttps://en.wikipedia.org/wiki/8b/10b_encoding\n\n## PR Content from GitHub\n\n# GitHub PR #102 Summary\n\n**PR Title:** 8b/10b decoder\n\n**PR Description Body:**\nThe PR description states: \"Closes #101\" with a TODO list including:\n- Implement testbench\n- Implement module\n- Add documentation\n\n**PR Comments:**\nThe only substantive comment comes from @bensampson5 (the PR author), who notes: \"Closes #101\" and outlines the three remaining tasks needed for completion.\n\n**Linked Issue:**\nIssue #101 is titled \"8b/10b decoder\" (full body content not provided in the page).\n\n**PR Status:**\nThis pull request was merged on November 25, 2021, after progressing from draft status. It includes 5 commits covering testbench implementation, module implementation, and documentation additions. The branch `issue-101-8b/10b_decoder` was deleted following the merge.\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/bensampson5_libsv_pr102", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/bensampson5_libsv_pr102.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/bensampson5_libsv_pr102", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/bensampson5_libsv_pr102"}
{"instance_id": "bensampson5_libsv_pr106", "issue_text": "# 8b/10b encoder improvements\n\n- Source URL: https://github.com/bensampson5/libsv/issues/105\n\nFeature list\n- Change ``i_rd``/``o_rd`` to ``i_disp``/``o_disp``\n- Add output error signal for invalid control symbols\n- Add input clock, reset, and move running disparity to an internal calculation\n- Add enable input ``i_en``\n- Register 10b output\n\nAdditional TODO\n- Fix testbench\n- Update docs for 8b10b encoder\n\n## PR Content from GitHub\n\n# Pull Request #106: 8b10b Encoder Improvements\n\n**PR Title:** 8b10b encoder improvements\n\n**PR Description:**\nCloses #105\n\nFeature list\n- Change `i_rd`/`o_rd` to `i_disp`/`o_disp`\n- Add output error signal for invalid control symbols\n- Add input clock, reset, and move running disparity to an internal calculation\n- Add enable input `i_en`\n- Register 10b output\n\nAdditional TODO\n- Fix testbench\n- Update docs for 8b10b encoder\n\n**PR Status:** Merged on November 26, 2021\n\n**Author:** bensampson5\n\n**Commits:** 2 commits\n1. \"New 8b10b encoder features and testbench\" (fcea7ac)\n2. \"Add docs for updated 8b10b encoder\" (186bab7)\n\n**Linked Issue:** #105 - \"8b/10b encoder improvements\"\n\n**Note:** The page indicates there were loading errors when attempting to display the full conversation content and additional details, so the complete comment thread is not available from this source.\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/bensampson5_libsv_pr106", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/bensampson5_libsv_pr106.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/bensampson5_libsv_pr106", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/bensampson5_libsv_pr106"}
{"instance_id": "bensampson5_libsv_pr109", "issue_text": "# 8b/10b decoder improvements\n\n- Source URL: https://github.com/bensampson5/libsv/issues/107\n\nFeature list\n- Add input clock, reset, and move running disparity to an internal calculation\n- Add enable input ``i_en``\n- Register outputs\n\nAdditional TODO\n- Fix testbench\n- Update docs for 8b10b decoder (take a look at 8b10b encoder)\n\n## PR Content from GitHub\n\n# PR Summary: 8b/10b Decoder Improvements\n\n**PR Title:** 8b/10b decoder improvements #109\n\n**Status:** Merged (November 28, 2021)\n\n---\n\n## PR Description\n\nThis pull request addresses issue #107 and implements several enhancements to the 8b/10b decoder module:\n\n**Features Added:**\n- Input clock, reset signals, with running disparity moved to internal calculation\n- Enable input (`i_en`)\n- Registered outputs\n\n**Pending Tasks:**\n- Fix testbench\n- Update documentation (referencing the 8b10b encoder documentation as a model)\n\n---\n\n## PR Activity Timeline\n\n**Commits:** 4 commits were merged\n- Implementation of new 8b/10b decoder features\n- Format fixes\n- Linting corrections\n- Documentation updates\n\n**Labels:** enhancement (New feature or request)\n\n**Assignee:** bensampson5 (repository owner)\n\n**Linked Issue:** Successfully closes issue #107 regarding 8b/10b decoder improvements\n\n---\n\n## Discussion\n\nThe PR shows standard GitHub workflow activity with commit additions, label application, and self-assignment by the author. No reviewer comments or additional discussion beyond the initial feature list was documented.\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/bensampson5_libsv_pr109", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/bensampson5_libsv_pr109.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/bensampson5_libsv_pr109", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/bensampson5_libsv_pr109"}
{"instance_id": "bensampson5_libsv_pr119", "issue_text": "# Add include guards to all source files\n\n- Source URL: https://github.com/bensampson5/libsv/issues/117\n\n\n## PR Content from GitHub\n\n# GitHub Pull Request Summary\n\n**PR Title:** Issue 117 add include guards to all source files\n\n**PR Number:** #119\n\n**Status:** Merged\n\n**Repository:** bensampson5/libsv\n\n**Merge Date:** January 29, 2022\n\n**Author:** bensampson5\n\n---\n\n## PR Description\n\nThe pull request description area appears to have encountered loading errors on the page, preventing the full body text from being extracted. However, the PR references \"Closes #117,\" indicating it addresses a specific issue.\n\n---\n\n## Commits\n\n1. \"Add include guards to all files that don't have it\" (commit 6da745c)\n2. \"Fix format\" (commit b44a92d)\n\n---\n\n## Linked Issue\n\n**Issue #117:** \"Add include guards to all source files\"\n\nThe full issue body text could not be extracted due to page loading errors.\n\n---\n\n## Comments\n\nNo user comments were successfully loaded on the conversation thread due to technical issues with the page rendering.\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/bensampson5_libsv_pr119", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/bensampson5_libsv_pr119.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/bensampson5_libsv_pr119", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/bensampson5_libsv_pr119"}
{"instance_id": "bensampson5_libsv_pr132", "issue_text": "# Write documentation for priority encoder\n\n- Source URL: https://github.com/bensampson5/libsv/issues/113\n\n\n## PR Content from GitHub\n\n# Pull Request Summary\n\n**PR Title:** Add documentation for priority_encoder #132\n\n**PR Status:** Merged on January 30, 2022\n\n**PR Description Body:** Not explicitly provided in the page content.\n\n## PR Comments\n\n**Author: bensampson5** (Jan 30, 2022)\n\"Closes #113\"\n\n## Linked Issue\n\n**Issue Title:** Write documentation for priority encoder\n\n**Issue Number:** #113\n\n**Issue Description Body:** Not visible in the provided page content.\n\n## Additional Details\n\n- **Merged By:** bensampson5\n- **Commits:** 1 commit (8b7bf0f)\n- **Branch:** issue-113-Write_documentation_for_priority_encoder merged into main\n- **Assignee:** bensampson5\n- **Reviewers:** None\n- **Labels:** None\n- **Milestone:** None\n\nThe pull request successfully merged documentation additions for the priority_encoder component, directly addressing the requirements outlined in issue #113.\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/bensampson5_libsv_pr132", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/bensampson5_libsv_pr132.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/bensampson5_libsv_pr132", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/bensampson5_libsv_pr132"}
{"instance_id": "bensampson5_libsv_pr150", "issue_text": "# Fix reconvergence issue with synchronizer\n\n- Source URL: https://github.com/bensampson5/libsv/issues/149\n\nSynchronizer can't handle multibit data so update to be just a single bit synchronizer\n\n## PR Content from GitHub\n\n# Pull Request Summary\n\n**PR Title:** Fix reconvergence issue in synchronizer\n\n**PR Number:** #150\n\n**Repository:** bensampson5/libsv\n\n**Status:** Merged (February 7, 2022)\n\n---\n\n## PR Description\nThe PR description body was not fully visible in the provided content. The only explicit reference states: \"Closes #149\"\n\n---\n\n## Comments\n\n**Author:** bensampson5\n\nComment text: \"Closes #149\"\n\n---\n\n## Linked Issue\n\n**Issue #149 Title:** Fix reconvergence issue with synchronizer\n\n**Issue Description:** The full issue body was not included in the extracted content, though the PR references it as the issue being resolved.\n\n---\n\n## Merge Information\n\n- **Merged by:** bensampson5\n- **Merge commit:** 989a51a\n- **Source branch:** issue-149-Fix_reconvergence_issue_with_synchronizer\n- **Target branch:** main\n- **Commits included:** 1\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/bensampson5_libsv_pr150", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/bensampson5_libsv_pr150.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/bensampson5_libsv_pr150", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/bensampson5_libsv_pr150"}
{"instance_id": "bensampson5_libsv_pr153", "issue_text": "# Mistake in `libsv/libsv/coders/encoder_8b10b.sv`\n\n- Source URL: https://github.com/bensampson5/libsv/issues/151\n\nHello!\n\nI am working on implementing 8b/10b encoding in a different project, and I stumbled upon the lookup table for encoding in this project. After writing my tests, I think I have found a mistake in your code in [encoder_8b10b.sv](https://github.com/bensampson5/libsv/blob/main/libsv/coders/encoder_8b10b.sv): for all code groups D28.X, the last 6 bits are `001110` while they should actually be `011100` according to the table in IEEE 802.3. Could this be possible?\n\n## PR Content from GitHub\n\n# Pull Request Summary\n\n**PR Title:** fix 8b10b encoder issue\n\n**PR Number:** #153\n\n**Status:** Merged\n\n**Author:** bensampson5\n\n**Merge Date:** May 26, 2024\n\n---\n\n## PR Description\n\nThe PR description area contains an error message stating \"There was an error while loading. Please reload this page.\" The actual description content is not accessible in the provided content.\n\nHowever, the PR references and closes issue #151: \"Mistake in `libsv/libsv/coders/encoder_8b10b.sv`\"\n\n---\n\n## Activity Timeline\n\n- **Commit:** `beb1c29` with message \"fix encoder issue\"\n- **Label Added:** bug (Something isn't working)\n- **Assignee:** bensampson5 (self-assigned)\n- **Merge Commit:** `d3b4b3b` merged into main branch\n- **Branch Deleted:** issue-151-Mistake_in_libsv/libsv/coders/encoder_8b10b_sv\n\n---\n\n## Comments\n\nNo user comments are accessible due to loading errors displayed in the page content.\n\n---\n\n## Linked Issue\n\n**Issue #151:** \"Mistake in `libsv/libsv/coders/encoder_8b10b.sv`\" -- addressed by this PR.\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/bensampson5_libsv_pr153", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/bensampson5_libsv_pr153.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/bensampson5_libsv_pr153", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/bensampson5_libsv_pr153"}
{"instance_id": "bensampson5_libsv_pr19", "issue_text": "# Write Verilator testbench for counter\n\n- Source URL: https://github.com/bensampson5/libsv/issues/7\n\n\n## PR Content from GitHub\n\n# Pull Request Summary\n\n**PR Title:** Docker try catch2 #19\n\n**PR Status:** Merged (December 29, 2020)\n\n**PR Description Body:**\nThe description content failed to load properly in the provided page content, showing \"Uh oh! There was an error while loading. Please reload this page.\" However, the PR closing statement indicates: \"Closes #7\" and \"Closes #11\"\n\n**PR Comments:**\nNo readable comment content was successfully extracted from the conversation section due to loading errors displayed on the page.\n\n**Linked Issues:**\n1. **Issue #11:** \"See if catch2 can be leveraged for unit testing IP\"\n2. **Issue #7:** \"Write Verilator testbench for counter\"\n\n**Commits Included (6 total):**\n- Add catch2 install to Dockerfile\n- Integrate catch2\n- Write unit test for counter\n- Added SRC_DIR to CMake\n- Add ninja-build install to Dockerfile\n- Update readme and format counter.sv\n\n**Author:** bensampson5\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/bensampson5_libsv_pr19", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/bensampson5_libsv_pr19.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/bensampson5_libsv_pr19", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/bensampson5_libsv_pr19"}
{"instance_id": "bensampson5_libsv_pr2", "issue_text": "# Write some kind of IP\n\n- Source URL: https://github.com/bensampson5/libsv/issues/1\n\nThe catalog needs to be started with at least one kind of IP. Let's pick a parameterized counter that counts up.\n\nTasks:\n- [ ] Create a new Verilog file `counter.v`\n- [ ] Write a testbench for it\n- [ ] Simulate it to validate it's operation\n\n## PR Content from GitHub\n\n# GitHub Pull Request #2 Summary\n\n**PR Title:** \"1 write some kind of ip\"\n\n**PR Description Body:** \"Closes #1\"\n\n**Commits (6 total):**\n1. Implement counter.v\n2. Move counter.v into src/\n3. Add counter_tb.sv to tb/\n4. Create .gitignore and ignore .vcd files\n5. Add async active low reset to counter\n6. Add counter_tb\n\n**PR Comments:** None visible in the conversation section (loading error prevented full display)\n\n**Linked Issue #1 Title:** \"Write some kind of IP\"\n\n**Status:** Merged on December 23, 2020 by bensampson5\n\nThe pull request addressed a straightforward request to implement digital hardware IP (intellectual property), specifically a counter module written in SystemVerilog with accompanying testbench files.\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/bensampson5_libsv_pr2", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/bensampson5_libsv_pr2.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/bensampson5_libsv_pr2", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/bensampson5_libsv_pr2"}
{"instance_id": "bensampson5_libsv_pr59", "issue_text": "# Add mux ip block\n\n- Source URL: https://github.com/bensampson5/libsv/issues/33\n\n## Linked Issue Content from GitHub\n\n**Issue #33: Add mux ip block**\n\n- Issue Body: No description provided.\n- Comments: None.\n- Status: Closed (via PR #59)\n- Assignee: bensampson5\n- Label: enhancement\n- Opened: January 8, 2021\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/bensampson5_libsv_pr59", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/bensampson5_libsv_pr59.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/bensampson5_libsv_pr59", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/bensampson5_libsv_pr59"}
{"instance_id": "bensampson5_libsv_pr61", "issue_text": "# Add half adder IP\n\n- Source URL: https://github.com/bensampson5/libsv/issues/60\n\n## Linked Issue Content from GitHub\n\n**Issue #60: Add half adder IP**\n\n- Issue Body: No description provided.\n- Comments: None.\n- Status: Closed (resolved via PR #61)\n- Assignee: bensampson5\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/bensampson5_libsv_pr61", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/bensampson5_libsv_pr61.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/bensampson5_libsv_pr61", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/bensampson5_libsv_pr61"}
{"instance_id": "bensampson5_libsv_pr63", "issue_text": "# Add c++ linter\n\n- Source URL: https://github.com/bensampson5/libsv/issues/42\n\nclang-tidy?\n\n## Linked Issues from GitHub (PR #63 closes #42, #44, #45)\n\n**Issue #45: SystemVerilog/Verilog linter**\n- Body: \"Add a linter for SystemVerilog/Verilog. I think Verilator has one but Verible definitely has one. So compare and pick one\"\n- Comments: None.\n\n**Issue #44: iwyu for c++**\n- (Title only — likely \"include-what-you-use\" tool integration request)\n\n**Issue #42: Add c++ linter**\n- Body: \"clang-tidy?\"\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/bensampson5_libsv_pr63", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/bensampson5_libsv_pr63.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/bensampson5_libsv_pr63", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/bensampson5_libsv_pr63"}
{"instance_id": "bensampson5_libsv_pr73", "issue_text": "# BCD Decoder\n\n- Source URL: https://github.com/bensampson5/libsv/issues/72\n\nDevelop a purely combinatorial circuit for a BCD decoder (bcd -> bin)\n\n## Linked Issue Content from GitHub\n\n**Issue #72: BCD Decoder**\n\n- Body: \"Develop a purely combinatorial circuit for a BCD decoder (bcd -> bin)\"\n- Comments: None.\n- Status: Closed (with associated PR #73)\n- Author: bensampson5, Opened October 8, 2021, Assignee: bensampson5\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/bensampson5_libsv_pr73", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/bensampson5_libsv_pr73.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/bensampson5_libsv_pr73", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/bensampson5_libsv_pr73"}
{"instance_id": "bensampson5_libsv_pr98", "issue_text": "# 8b/10b encoder\n\n- Source URL: https://github.com/bensampson5/libsv/issues/97\n\nImplement 8b/10b encoder\n\nhttps://en.wikipedia.org/wiki/8b/10b_encoding\n\n## Linked Issue Content from GitHub\n\n**Issue #97: 8b/10b encoder**\n\n- Body: \"Implement 8b/10b encoder. https://en.wikipedia.org/wiki/8b/10b_encoding\"\n- Status: Closed (related PR #98)\n- Assignee: bensampson5, Label: enhancement, Created November 23, 2021\n- Comments: None.\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/bensampson5_libsv_pr98", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/bensampson5_libsv_pr98.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/bensampson5_libsv_pr98", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/bensampson5_libsv_pr98"}
{"instance_id": "bespoke-silicon-group_basejump_stl_pr371", "issue_text": "# macro defines in package\n\nhttps://github.com/bespoke-silicon-group/basejump_stl/blob/d4cd62042e6f83b953a6bad75c2257f10ce0c853/bsg_test/bsg_dramsim3_pkg.v#L86\n\nThis means that the correct operation of this module will depend on its include order on the VCS command line. We should factor out into a .vh file and include appropriately.\n\n## Linked Issue Content from GitHub\n\n**Issue #368: macro defines in package**\n\n- Body: bsg_test/bsg_dramsim3_pkg.v line 86 contains `\\`define dramsim3_ba_width(num_ba_mp) $clog2(num_ba_mp)`. Correct operation depends on include order on VCS command line. Suggested fix: factor out into a .vh file and include appropriately.\n- Status: Closed via PR #371.\n- Comments: None.\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/bespoke-silicon-group_basejump_stl_pr371", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/bespoke-silicon-group_basejump_stl_pr371.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/bespoke-silicon-group_basejump_stl_pr371", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/bespoke-silicon-group_basejump_stl_pr371"}
{"instance_id": "bespoke-silicon-group_basejump_stl_pr392", "issue_text": "# [bsg_tag_client] is widht_p=1 supported?\n\nhttps://github.com/bespoke-silicon-group/basejump_stl/blob/1862705e8bbb59c84dc9d942a8b1b31874f60406/bsg_tag/bsg_tag_client.v#L94\n\nwhen width_p=1,\n```\n\nError-[IRIPS] Illegal range in part select\n/mnt/users/workspace/homes/dcjung/bsg/basejump_stl/bsg_tag/bsg_tag_client.v, 94\n  The range of the part select is illegal:\n  tag_data_r[(width_p - 1):1]\n\n\nLint-[CAWM-L] Width mismatch\n/mnt/users/workspace/homes/dcjung/bsg/basejump_stl/bsg_tag/bsg_tag_client.v, 94\n  Continuous assignment width mismatch\n  1 bits (lhs) versus 3 bits (rhs).\n  Source info: assign tag_data_shift = {param_r, tag_data_r[(width_p - 1):1]};\n \n\n```\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/bespoke-silicon-group_basejump_stl_pr392", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/bespoke-silicon-group_basejump_stl_pr392.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/bespoke-silicon-group_basejump_stl_pr392", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/bespoke-silicon-group_basejump_stl_pr392"}
{"instance_id": "bespoke-silicon-group_basejump_stl_pr422", "issue_text": "basejump_stl/testing/bsg_test/bsg_nonsynth_dpi/top.v\n\nLine 22 in 61849cd\n\n (.o(ns_clk));\nThe current testbench attempts to do so, but actually multiply drives the ns_clk net. We're seeing potential issues with multiple clock gens in this BP issue: black-parrot/black-parrot#798\n\n## Linked Issue Content from GitHub\n\n**Issue #421: Test bsg_nonsynth_dpi_clock_gen with multiple clocks**\n\n- Body: The testbench at `basejump_stl/testing/bsg_test/bsg_nonsynth_dpi/top.v` line 22 contains `(.o(ns_clk));`. The testbench attempts to test multiple clock generators but actually multiply-drives the ns_clk net. References related Black Parrot issue #798.\n- Status: Closed (resolved by PR #422). Assigned: drichmond. Labels: bug.\n- Comments: None.\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/bespoke-silicon-group_basejump_stl_pr422", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/bespoke-silicon-group_basejump_stl_pr422.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/bespoke-silicon-group_basejump_stl_pr422", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/bespoke-silicon-group_basejump_stl_pr422"}
{"instance_id": "bespoke-silicon-group_basejump_stl_pr450", "issue_text": "# BSG_ABSTRACT does not work for verilator toplevel\n\nverilator --cc -pvalue+width_p=2 -pvalue+els_p=2 bsg_mux.v\n\n```\n%Warning-PINMISSING: bsg_mux.v:30: Cell has missing pin: data_i\n%Warning-PINMISSING: Use \"/* verilator lint_off PINMISSING */\" and lint_on around source to disable this message.\n%Warning-PINMISSING: bsg_mux.v:30: Cell has missing pin: sel_i\n%Warning-PINMISSING: bsg_mux.v:30: Cell has missing pin: data_o\n%Error: Specified --top-module 'bsg_mux' isn't at the top level, it's under another cell 'bsg_mux__abstract'\n%Error: Exiting due to 1 error(s), 3 warning(s)\n%Error: Command Failed /usr/bin/verilator_bin --cc -pvalue\\+width_p\\=2 -pvalue\\+els_p\\=2 --top-module bsg_mux bsg_mux.v\n```\n\nHaven't thought about this too hard. Seems like a Verilator issue, but could also be related to the spec. We could raise an issue there as well?\n\n## Linked Issue Content from GitHub\n\n**Issue #446: BSG_ABSTRACT does not work for verilator toplevel**\n\n- Body: User reports `verilator --cc -pvalue+width_p=2 -pvalue+els_p=2 bsg_mux.v` produces missing-pin warnings and a critical error: \"Specified --top-module 'bsg_mux' isn't at the top level, it's under another cell 'bsg_mux__abstract'\". Uncertain if Verilator bug or spec issue.\n- Status: Closed. Assignee: taylor-bsg. Labels: bug, question. Related PR: #450.\n- Comments: None.\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/bespoke-silicon-group_basejump_stl_pr450", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/bespoke-silicon-group_basejump_stl_pr450.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/bespoke-silicon-group_basejump_stl_pr450", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/bespoke-silicon-group_basejump_stl_pr450"}
{"instance_id": "bespoke-silicon-group_basejump_stl_pr472", "issue_text": "# Potential bug in hardened fifo module\n\nThe hardened fifo module contains a variable `read_write_same_addr_n`, which is currently assigned as `wptr_r == rptr_r`. The comment for this variable mentions that it should be 1 when the fifo is empty, but the condition is true for both empty and full fifo conditions. The line in question is given below:\n\nhttps://github.com/bespoke-silicon-group/basejump_stl/blob/4cfaeb454a7278f7d13eb766dad07ce34fefcdea/bsg_dataflow/bsg_fifo_1r1w_small_hardened.v#L118\n\nIf this variable is 1 when the fifo is full, it prevents the memory read as in https://github.com/bespoke-silicon-group/basejump_stl/blob/4cfaeb454a7278f7d13eb766dad07ce34fefcdea/bsg_dataflow/bsg_fifo_1r1w_small_hardened.v#L95\nThe assignment can instead be `assign read_write_same_addr_n = empty`.\n\n## Linked Issue Content from GitHub\n\n**Issue #465: Potential bug in hardened fifo module**\n\n- Body: `read_write_same_addr_n = wptr_r == rptr_r` is true for both empty AND full conditions, but the comment says it should be 1 only when empty. When fifo is full, this prevents memory read at line 95 (`r_v_i (~read_write_same_addr_n)`). Suggested fix: `assign read_write_same_addr_n = empty`.\n- Author: Shashank-Vijay, Opened July 19, 2021. Status: Closed (resolved via PR #472). Label: bug.\n- Comments: None.\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/bespoke-silicon-group_basejump_stl_pr472", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/bespoke-silicon-group_basejump_stl_pr472.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/bespoke-silicon-group_basejump_stl_pr472", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/bespoke-silicon-group_basejump_stl_pr472"}
{"instance_id": "bespoke-silicon-group_basejump_stl_pr668", "issue_text": "# Reusable module for IPOLY hashing logic\n\nInstance: bespoke-silicon-group_basejump_stl_pr668\nSource: https://github.com/bespoke-silicon-group/basejump_stl/pull/668\nFetched: 2026-04-26\nRepository: bespoke-silicon-group/basejump_stl\nPull request: #668\nAuthor: tommydcjung\nState: closed\nBase branch: master\nHead branch: ipoly_hashing_module\nCreated: 2023-12-06T00:58:23Z\nUpdated: 2023-12-09T17:55:30Z\nClosed: 2023-12-09T00:12:19Z\nMerged: 2023-12-09T00:12:19Z\n\n## PR Description\nNo description was provided by the contributor.\n\n## Comments and Discussion\n\ntommydcjung (Contributor) - December 6, 2023:\nInitial submission with no description provided.\n\ntommydcjung - December 6, 2023:\nCorrected the PR title from \"Reusuable\" to \"Reusable\".\n\ndpetrisko (Reviewer) - December 7, 2023:\nAsked whether supporting smaller bank configurations would be feasible, suggesting this feature \"might be worth it to support for tiny manycores / BP multicores\".\n\ntommydcjung - December 8, 2023:\nResponded by adding support for 4 and 8 banks in addition to the existing configuration.\n\ndpetrisko - December 9, 2023:\nApproved the changes and merged the pull request.\n\n## Additional Context\nThe PR branch `ipoly_hashing_module` was deleted after merging. The changes have been referenced in subsequent commits across multiple repositories.\n\nNo linked issues were referenced in this pull request.\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/bespoke-silicon-group_basejump_stl_pr668", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/bespoke-silicon-group_basejump_stl_pr668.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/bespoke-silicon-group_basejump_stl_pr668", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/bespoke-silicon-group_basejump_stl_pr668"}
{"instance_id": "bespoke-silicon-group_basejump_stl_pr673", "issue_text": "# bsg_dataflow/bsg_fifo_bypass.sv: Port/variable name mismatch\n\nIn bsg_dataflow/bsg_fifo_bypass.sv there is a variable `fifo_ready_param_i` that does not match up with any port name.\n\nhttps://github.com/bespoke-silicon-group/basejump_stl/blob/14f29e4d8a498ad62ec05fe232407f9d887e36a9/bsg_dataflow/bsg_fifo_bypass.sv#L4-L36\n\nBy comparison with the [testbench](https://github.com/bespoke-silicon-group/basejump_stl/blob/14f29e4d8a498ad62ec05fe232407f9d887e36a9/testing/bsg_dataflow/bsg_fifo_bypass/testbench.sv#L46), I assume this is supposed to be `fifo_ready_i`?\n\n## Linked Issue Content from GitHub\n\n**Issue #672: bsg_dataflow/bsg_fifo_bypass.sv: Port/variable name mismatch**\n\n- Body: Variable `fifo_ready_param_i` doesn't match any port name. Module ports declare `fifo_ready_i` but internal assignment uses `fifo_ready_param_i` (`assign ready_param_o = fifo_ready_param_i;`). Comparison with testbench suggests it should be `fifo_ready_i`.\n- Opened March 1, 2024. Linked PR: #673.\n- Comments: None.\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/bespoke-silicon-group_basejump_stl_pr673", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/bespoke-silicon-group_basejump_stl_pr673.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/bespoke-silicon-group_basejump_stl_pr673", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/bespoke-silicon-group_basejump_stl_pr673"}
{"instance_id": "bespoke-silicon-group_basejump_stl_pr675", "issue_text": "The variable addr_li is referenced before declaration in bsg_mem/bsg_mem_1rw_sync_mask_write_bit_from_1r1w.sv. While in principle an HDL shouldn't have any problem with this, some compilers don't like it very much. Causes compile errors in Questa/Modelsim and Synopsys DC (and possibly others as well).\n\nbasejump_stl/bsg_mem/bsg_mem_1rw_sync_mask_write_bit_from_1r1w.sv\n\nLines 65 to 69 in 2a73106\n\n   wire                      addr_match = w_addr_r == addr_li;\n   wire                      bypass_n = v_and_w_r & addr_match;\n   wire                      bypass_r;\n\n   wire [addr_width_lp-1:0]  addr_li = els_p > 1 ? addr_i : '0;\nThe easy solution is to move L69 up to before L65. This resolves errors in both tools.\n\n## Linked Issue Content from GitHub\n\n**Issue #674: bsg_mem/bsg_mem_1rw_sync_mask_write_bit_from_1r1w.sv: Variable used before declaration**\n\n- Body: `addr_li` referenced before declaration. Causes compile errors in Questa/Modelsim and Synopsys DC. Suggested fix: move line 69 (the `addr_li` declaration) up to before line 65.\n- Linked PR: #675.\n- Comments: None.\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/bespoke-silicon-group_basejump_stl_pr675", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/bespoke-silicon-group_basejump_stl_pr675.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/bespoke-silicon-group_basejump_stl_pr675", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/bespoke-silicon-group_basejump_stl_pr675"}
{"instance_id": "bespoke-silicon-group_basejump_stl_pr676", "issue_text": "# bsg_dmc/bsg_dmc_dly_line_v3.sv: Fix missing include\n\nInstance: bespoke-silicon-group_basejump_stl_pr676\nSource: https://github.com/bespoke-silicon-group/basejump_stl/pull/676\nFetched: 2026-04-26\nRepository: bespoke-silicon-group/basejump_stl\nPull request: #676\nAuthor: infinitymdm\nState: closed\nBase branch: master\nHead branch: fix_bsg_dmc_missing_include\nCreated: 2024-03-11T20:12:47Z\nUpdated: 2024-09-09T15:18:04Z\nClosed: 2024-03-11T21:39:37Z\nMerged: 2024-03-11T21:39:37Z\n\n## PR Description\n\ninfinitymdm reported that a necessary include statement was absent from the file `bsg_dmc/bsg_dmc_dly_line_v3.sv`. The contributor noted: \"Without this line we get errors when trying to run simulation since the file uses some of the macros defined in bsg_misc/bsg_defines.sv.\"\n\n## Comments\n\ndpetrisko (Reviewer/Approver):\n\"LGTM\" - indicating approval of the changes.\n\n## Additional Context\n\nMerged by dpetrisko on March 11, 2024. Branch deleted on September 9, 2024.\n\nNo linked issues were explicitly referenced in the pull request.\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/bespoke-silicon-group_basejump_stl_pr676", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/bespoke-silicon-group_basejump_stl_pr676.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/bespoke-silicon-group_basejump_stl_pr676", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/bespoke-silicon-group_basejump_stl_pr676"}
{"instance_id": "bespoke-silicon-group_basejump_stl_pr677", "issue_text": "# Update bsg_defines.sv for yosys\n\nInstance: bespoke-silicon-group_basejump_stl_pr677\nSource: https://github.com/bespoke-silicon-group/basejump_stl/pull/677\nFetched: 2026-04-26\nRepository: bespoke-silicon-group/basejump_stl\nPull request: #677\nAuthor: dpetrisko\nState: closed\nBase branch: master\nHead branch: dpetrisko-patch-24\nCreated: 2024-03-27T20:31:35Z\nUpdated: 2024-03-28T22:52:07Z\nClosed: 2024-03-28T22:52:06Z\nMerged: 2024-03-28T22:52:06Z\n\n## PR Description\nThe pull request lacks a detailed description body. The primary context comes from the comments.\n\n## Comments\n\ndpetrisko (Mar 27, 2024):\n\"YOSYS is not Vivado, so we should identify it as such\"\n\nstdavids (Mar 28, 2024):\nApproved the changes with a review of the modified files.\n\n## Additional Context\nLabels: bug. Commits: 1 (a47e1e1). The change updates `bsg_defines.sv` to properly distinguish between the YOSYS synthesis tool and Vivado, rather than treating them identically. The change was approved and incorporated into the master branch.\n\nNo linked issues were referenced in this pull request.\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/bespoke-silicon-group_basejump_stl_pr677", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/bespoke-silicon-group_basejump_stl_pr677.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/bespoke-silicon-group_basejump_stl_pr677", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/bespoke-silicon-group_basejump_stl_pr677"}
{"instance_id": "bespoke-silicon-group_basejump_stl_pr697", "issue_text": "# fix bsg_transpose_reduce\n\nInstance: bespoke-silicon-group_basejump_stl_pr697\nSource: https://github.com/bespoke-silicon-group/basejump_stl/pull/697\nFetched: 2026-04-26\nRepository: bespoke-silicon-group/basejump_stl\nPull request: #697\nAuthor: tommydcjung\nState: closed\nBase branch: master\nHead branch: bsg_transpose_reduce_fix\nCreated: 2024-10-04T20:39:37Z\nUpdated: 2024-10-06T17:35:28Z\nClosed: 2024-10-06T17:35:25Z\nMerged: 2024-10-06T17:35:25Z\n\n## PR Description\n\nNo description was provided for this pull request.\n\n## Comments\n\ndpetrisko (October 5, 2024):\n\"Looks good!\" - approval comment left during the review process.\n\n## Additional Context\n\nReviewers: dpetrisko approved the changes; taylor-bsg was requested for review. Commits: 1 commit (58dd32b). Merged by tommydcjung on October 6, 2024.\n\nNo linked issues were explicitly documented in the pull request.\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/bespoke-silicon-group_basejump_stl_pr697", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/bespoke-silicon-group_basejump_stl_pr697.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/bespoke-silicon-group_basejump_stl_pr697", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/bespoke-silicon-group_basejump_stl_pr697"}
{"instance_id": "bespoke-silicon-group_basejump_stl_pr699", "issue_text": "# SDR Token Clock Timing\n\nInstance: bespoke-silicon-group_basejump_stl_pr699\nSource: https://github.com/bespoke-silicon-group/basejump_stl/pull/699\nFetched: 2026-04-26\nRepository: bespoke-silicon-group/basejump_stl\nPull request: #699\nAuthor: gaozihou\nState: closed\nBase branch: master\nHead branch: sdr_token_clock_timing\nCreated: 2024-10-23T07:07:24Z\nUpdated: 2024-11-04T21:10:12Z\nClosed: 2024-11-04T21:10:12Z\nMerged: 2024-11-04T21:10:12Z\n\n## PR Description\n\nAdd token boundary cells to improve token clock driving strength. Update token clock timing constraints, add token clock driving cell.\n\n## Comments\n\ngaozihou (Contributor, Oct 23, 2024):\n\"Add token boundary cells to improve token clock driving strength. Update token clock timing constraints, add token clock driving cell\"\n\ndpetrisko (Approved, Nov 2, 2024):\n\"LGTM! These changes work in genus as well\"\n\n## Additional Context\n\nCommits: 4 total - \"Add sdr link token boundary cells to improve timing\", \"Update sdr link token timing constraints, add driving cells\", \"fix duplicated genblk error\", \"add explicit conditional generate constructs\". Reviewers: dpetrisko approved; taylor-bsg review pending at time of merge. Merged into master on November 4, 2024.\n\nNo linked issues were referenced in this pull request.\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/bespoke-silicon-group_basejump_stl_pr699", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/bespoke-silicon-group_basejump_stl_pr699.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/bespoke-silicon-group_basejump_stl_pr699", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/bespoke-silicon-group_basejump_stl_pr699"}
{"instance_id": "bespoke-silicon-group_basejump_stl_pr706", "issue_text": "# Update bsg_serial_in_parallel_out_full.sv\n\nInstance: bespoke-silicon-group_basejump_stl_pr706\nSource: https://github.com/bespoke-silicon-group/basejump_stl/pull/706\nFetched: 2026-04-26\nRepository: bespoke-silicon-group/basejump_stl\nPull request: #706\nAuthor: taylor-bsg\nState: closed\nBase branch: master\nHead branch: taylor-bsg-patch-3\nCreated: 2024-11-16T18:52:24Z\nUpdated: 2024-12-07T00:26:29Z\nClosed: 2024-12-07T00:26:29Z\nMerged: 2024-12-07T00:26:29Z\n\nPR Title: Update bsg_serial_in_parallel_out_full.sv\n\nPR Description:\nSupport more buffering inside SIPO\n\nPR Comments:\n(Comments could not be loaded from the page.)\n\nLinked Issues:\nThe page indicates \"Successfully merging this pull request may close these issues,\" but the specific issue numbers and details could not be loaded.\n\nStatus: Merged on December 7, 2024 by taylor-bsg.\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/bespoke-silicon-group_basejump_stl_pr706", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/bespoke-silicon-group_basejump_stl_pr706.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/bespoke-silicon-group_basejump_stl_pr706", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/bespoke-silicon-group_basejump_stl_pr706"}
{"instance_id": "bespoke-silicon-group_basejump_stl_pr710", "issue_text": "# Hotfix: verilog includes\n\nInstance: bespoke-silicon-group_basejump_stl_pr710\nSource: https://github.com/bespoke-silicon-group/basejump_stl/pull/710\nFetched: 2026-04-26\nRepository: bespoke-silicon-group/basejump_stl\nPull request: #710\nAuthor: dpetrisko\nState: closed\nBase branch: master\nHead branch: dpetrisko-patch-29\nCreated: 2024-11-25T00:47:01Z\nUpdated: 2024-11-25T01:17:56Z\nClosed: 2024-11-25T01:17:56Z\nMerged: 2024-11-25T01:17:56Z\n\nPR Title: Hotfix: verilog includes\n\nPR Description:\nThis PR fixes include paths unchanged from #666\n\nPR Comments:\n- dpetrisko (Nov 25, 2024): \"This PR fixes include paths unchanged from #666\"\n- gaozihou (Nov 25, 2024): \"LGTM!\"\n\nReviewers: gaozihou (approved)\nLabels: bug\nStatus: Merged by gaozihou on November 25, 2024\n\nLinked Issues: None explicitly referenced in the PR description (PR #666 is referenced).\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/bespoke-silicon-group_basejump_stl_pr710", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/bespoke-silicon-group_basejump_stl_pr710.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/bespoke-silicon-group_basejump_stl_pr710", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/bespoke-silicon-group_basejump_stl_pr710"}
{"instance_id": "bespoke-silicon-group_basejump_stl_pr715", "issue_text": "# Fix ipoly for bank 4 and 8\n\nInstance: bespoke-silicon-group_basejump_stl_pr715\nSource: https://github.com/bespoke-silicon-group/basejump_stl/pull/715\nFetched: 2026-04-26\nRepository: bespoke-silicon-group/basejump_stl\nPull request: #715\nAuthor: tommydcjung\nState: closed\nBase branch: master\nHead branch: hotfix_20250201\nCreated: 2025-02-01T13:23:29Z\nUpdated: 2025-02-02T00:00:51Z\nClosed: 2025-02-02T00:00:51Z\nMerged: 2025-02-02T00:00:51Z\n\nPR Title: Fix ipoly for bank 4 and 8\n\nPR Description:\n(No description provided.)\n\nPR Comments:\n- tommydcjung (Feb 1, 2025, 13:23): Requested review from gaozihou\n- gaozihou (Feb 1, 2025): \"LGTM, simple typo fix\" - Approved the changes\n\nStatus: Merged by gaozihou into master on Feb 2, 2025 (commit 5a8a602).\n\nLinked Issues: None explicitly mentioned.\n\nAdditional Context: The PR contains a single commit (a6c328e) with the message \"fix ipoly\" and was characterized as a straightforward typo correction.\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/bespoke-silicon-group_basejump_stl_pr715", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/bespoke-silicon-group_basejump_stl_pr715.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/bespoke-silicon-group_basejump_stl_pr715", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/bespoke-silicon-group_basejump_stl_pr715"}
{"instance_id": "bespoke-silicon-group_basejump_stl_pr735", "issue_text": "# Define BSG_HIDE_FROM_SYNTHESIS_EXPR macro\n\nInstance: bespoke-silicon-group_basejump_stl_pr735\nSource: https://github.com/bespoke-silicon-group/basejump_stl/pull/735\nFetched: 2026-04-26\nRepository: bespoke-silicon-group/basejump_stl\nPull request: #735\nAuthor: taylor-bsg\nState: closed\nBase branch: master\nHead branch: taylor-bsg-patch-4\nCreated: 2025-09-23T17:48:57Z\nUpdated: 2025-09-23T17:49:24Z\nClosed: 2025-09-23T17:49:24Z\nMerged: 2025-09-23T17:49:24Z\n\nPR Title: Define BSG_HIDE_FROM_SYNTHESIS_EXPR macro\n\nPR Description:\nAdd macro for conditional synthesis hiding expression\n\nPR Comments:\n(No additional discussion comments beyond the commit message.)\n\nLinked Issues:\nThe PR indicates \"Successfully merging this pull request may close these issues,\" but no specific issue titles or bodies are visible.\n\nStatus: Merged on Sep 23, 2025 by taylor-bsg.\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/bespoke-silicon-group_basejump_stl_pr735", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/bespoke-silicon-group_basejump_stl_pr735.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/bespoke-silicon-group_basejump_stl_pr735", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/bespoke-silicon-group_basejump_stl_pr735"}
{"instance_id": "bespoke-silicon-group_basejump_stl_pr737", "issue_text": "# Small fifo 1r1w hardened bug fix\n\nInstance: bespoke-silicon-group_basejump_stl_pr737\nSource: https://github.com/bespoke-silicon-group/basejump_stl/pull/737\nFetched: 2026-04-26\nRepository: bespoke-silicon-group/basejump_stl\nPull request: #737\nAuthor: gaozihou\nState: closed\nBase branch: master\nHead branch: small-fifo-hardened-bug-fix\nCreated: 2026-01-10T02:04:05Z\nUpdated: 2026-01-10T04:07:59Z\nClosed: 2026-01-10T04:07:59Z\nMerged: 2026-01-10T04:07:59Z\n\n- When read_write_same_addr happens, data will not be written into the hardened mem. Instead, always read from the bypass reg until deque.\r\n- Testbench coverages has been updated according to the RTL behavior changes\r\n- Achieves 100% coverage after 4500 iterations. Test is passing.\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/bespoke-silicon-group_basejump_stl_pr737", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/bespoke-silicon-group_basejump_stl_pr737.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/bespoke-silicon-group_basejump_stl_pr737", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/bespoke-silicon-group_basejump_stl_pr737"}
{"instance_id": "bespoke-silicon-group_basejump_stl_pr739", "issue_text": "# Update multi FIFO interface and tests\n\nInstance: bespoke-silicon-group_basejump_stl_pr739\nSource: https://github.com/bespoke-silicon-group/basejump_stl/pull/739\nFetched: 2026-04-26\nRepository: bespoke-silicon-group/basejump_stl\nPull request: #739\nAuthor: taylor-bsg\nState: closed\nBase branch: master\nHead branch: fifo-1r1w-small-hardened-multi\nCreated: 2026-01-13T06:33:37Z\nUpdated: 2026-01-13T06:34:56Z\nClosed: 2026-01-13T06:34:56Z\nMerged: 2026-01-13T06:34:56Z\n\nPR Title: Update multi FIFO interface and tests\n\nPR Description:\n(No description provided.)\n\nPR Comments:\n- taylor-bsg (Jan 13, 2026): No description provided.\n\nCommit Message: \"Update multi FIFO interface and tests\"\n\nLinked Issues: None identified.\n\nStatus: Merged into master on Jan 13, 2026 (commit 0fcf0fc). Branch: fifo-1r1w-small-hardened-multi to master.\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/bespoke-silicon-group_basejump_stl_pr739", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/bespoke-silicon-group_basejump_stl_pr739.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/bespoke-silicon-group_basejump_stl_pr739", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/bespoke-silicon-group_basejump_stl_pr739"}
{"instance_id": "bespoke-silicon-group_bsg_manycore_pr587", "issue_text": "# Tuning GCC libraries to bsg_vanilla_2020 causes RTL error\n\n- Source URL: https://github.com/bespoke-silicon-group/bsg_manycore/issues/586\n\nWhile searching for performance last week, I noticed that the GCC libraries for manycore are not tuned for the vanilla core pipeline. \r\n\r\nTo address this, I added `--with-tune=bsg_vanilla_2020` to software/riscv-tools/Makefile on line 139: \r\n```\r\n\t\t./configure --prefix=$(RISCV) --disable-linux --with-arch=$(TARGET_ARCH) --with-abi=$(TARGET_ABI) --disable-gdb --with-tune=bsg_vanilla_2020\r\n```\r\n\r\n(--with-tune is described here: [Link](https://gcc.gnu.org/install/configure.html))\r\n\r\nThe GCC toolchain seems to compile fine. It also seems to take the tuning flag correctly: \r\n```\r\nriscv-install/bin/riscv32-unknown-elf-dramfs-gcc -v\r\nUsing built-in specs.\r\nCOLLECT_GCC=riscv-install/bin/riscv32-unknown-elf-dramfs-gcc\r\nCOLLECT_LTO_WRAPPER=/mnt/users/spin0/no_backup/drichmond/Research/repositories/git/bsg_bladerunner.6/bsg_manycore/software/riscv-tools/riscv-install/libexec/gcc/riscv32-unknown-elf-dramfs/9.2.0/lto-wrapper\r\nTarget: riscv32-unknown-elf-dramfs\r\nConfigured with: /mnt/users/ssd2/homes/drichmond/Research/repositories/git/bsg_bladerunner.6/bsg_manycore/software/riscv-tools/riscv-gnu-toolchain/riscv-gcc/configure --target=riscv32-unknown-elf-dramfs --prefix=/mnt/users/spin0/no_backup/drichmond/Research/repositories/git/bsg_bladerunner.6/bsg_manycore/software/riscv-tools/riscv-install --disable-shared --disable-threads --enable-languages=c,c++ --with-system-zlib --enable-tls --with-newlib --with-sysroot=/mnt/users/spin0/no_backup/drichmond/Research/repositories/git/bsg_bladerunner.6/bsg_manycore/software/riscv-tools/riscv-install/riscv32-unknown-elf-dramfs --with-native-system-header-dir=/include --disable-libmudflap --disable-libssp --disable-libquadmath --disable-libgomp --disable-nls --disable-tm-clone-registry --src=.././riscv-gcc --enable-checking=yes --disable-multilib --with-abi=ilp32f --with-arch=rv32imaf --with-tune=bsg_vanilla_2020 'CFLAGS_FOR_TARGET=-Os -fno-common -mcmodel=medlow' 'CXXFLAGS_FOR_TARGET=-Os  -mcmodel=medlow'\r\nThread model: single\r\ngcc version 9.2.0 (GCC) \r\n```\r\n\r\nAnd it did make a small difference in performance. However, it causes an error to be printed from the RTL: \r\n\r\n```\r\n\"/mnt/users/spin0/no_backup/drichmond/Research/repositories/git/bsg_bladerunner.6/bsg_manycore/v/vanilla_bean/fcsr.v\", 187: spmd_testbench.tb.DUT.py[0].podrow.px[0].pod.mc_y[0].mc_x[0].mc.y[0].x[0].tile.proc.h.z.vcore.fcsr0.unnamed$$_3: s\r\ntarted at 1897000ps failed at 1897000ps\r\n        Offending '(~(|fflags_v_i))'\r\nError: \"/mnt/users/spin0/no_backup/drichmond/Research/repositories/git/bsg_bladerunner.6/bsg_manycore/v/vanilla_bean/fcsr.v\", 187: spmd_testbench.tb.DUT.py[0].podrow.px[0].pod.mc_y[0].mc_x[0].mc.y[0].x[0].tile.proc.h.z.vcore.fcsr0.unnamed\r\n$$_3: at time 1897000 ps\r\nException cannot be accrued while being written by fcsr op.\r\n```\r\n\r\nI've localized the issue to logf. \r\n\r\n\r\nTo reproduce this: \r\n\r\n1. Checkout the [logf_error](https://github.com/bespoke-silicon-group/bsg_manycore/tree/logf_error) branch.\r\n2. Build the toolchain from scratch (the branch includes the `--with-tune` flag above\r\n3. Run the SPMD test software/spmd/float_logf (~10 seconds)\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/bespoke-silicon-group_bsg_manycore_pr587", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/bespoke-silicon-group_bsg_manycore_pr587.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/bespoke-silicon-group_bsg_manycore_pr587", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/bespoke-silicon-group_bsg_manycore_pr587"}
{"instance_id": "bespoke-silicon-group_bsg_manycore_pr635", "issue_text": "# bsg_manycore_hetero_socket out of date\n\n- Source URL: https://github.com/bespoke-silicon-group/bsg_manycore/issues/612\n\n```\r\n%Error-PINNOTFOUND: /mnt/users/spin2/no_backup/buildbot/builddir/Le6_42-J/0/dpetrisko/bsg_manycore/bsg_manycore/v/bsg_manycore_hetero_socket.v:116:14: Pin not found: 'barrier_data_o'\r\n  116 |            ,.barrier_data_o                                                            \r\n      |              ^~~~~~~~~~~~~~\r\n%Error-PINNOTFOUND: /mnt/users/spin2/no_backup/buildbot/builddir/Le6_42-J/0/dpetrisko/bsg_manycore/bsg_manycore/v/bsg_manycore_hetero_socket.v:116:14: Pin not found: 'barrier_src_r_o'\r\n  116 |            ,.barrier_src_r_o                                                           \r\n      |              ^~~~~~~~~~~~~~~\r\n%Error-PINNOTFOUND: /mnt/users/spin2/no_backup/buildbot/builddir/Le6_42-J/0/dpetrisko/bsg_manycore/bsg_manycore/v/bsg_manycore_hetero_socket.v:116:14: Pin not found: 'barrier_dest_r_o'\r\n  116 |            ,.barrier_dest_r_o                                                          \r\n      |              ^~~~~~~~~~~~~~~~\r\n%Error-PINNOTFOUND: /mnt/users/spin2/no_backup/buildbot/builddir/Le6_42-J/0/dpetrisko/bsg_manycore/bsg_manycore/v/bsg_manycore_hetero_socket.v:116:29: Parameter pin not found: 'barrier_dirs_p'\r\n  116 |                           ,.barrier_dirs_p(barrier_dirs_p)  \r\n```\r\n\r\nFound in the verilator build: https://gitlab.com/dpetrisko/bsg_manycore/-/jobs/1860091449\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/bespoke-silicon-group_bsg_manycore_pr635", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/bespoke-silicon-group_bsg_manycore_pr635.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/bespoke-silicon-group_bsg_manycore_pr635", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/bespoke-silicon-group_bsg_manycore_pr635"}
{"instance_id": "black-parrot_black-parrot_pr1089", "issue_text": "PR Title: Fix nonsynth cache UC store hit bug\n\nPR Description:\nThe PR fixes issue #1086. According to the description: \"Root cause was implementation of the nonsynth cache used in the ME testbench. Uncached stores targeting valid cache blocks were not self-invalidating the block, causing the store to get lost if targeted by following cacheable load. Bug is only present in the ME testbench, not in a real BP system.\"\n\nPR Comments:\n- dpetrisko (May 4, 2022): \"Great find!\"\n\nLinked Issue #1086: Referenced as fixed by this PR (issue body not provided in the page content).\n\nMetadata:\n- Author: muwyse\n- Reviewer/Approver: dpetrisko\n- Labels: bug, testing\n- Merged: May 4, 2022\n\nOriginal local content (issue body context):\nArea\nme_regress testing, ucode\n\nCurrent behavior\nme_regress fails under current CI for:\nbp_cce.e_bp_test_multicore_half_cce_ucode_cfg.msi.set_test.mixed.sim.cce.none.err\nbp_cce.e_bp_test_multicore_half_cce_ucode_cfg.msi-nonspec.set_test.mixed.sim.cce.none.err\n\nI've tried to rewind SDK/ucode and RTL and no combination seems to pass within reasonable scope\n\nVerification\nme_regress passing\n\nAdditional Context\nhttps://gitlab.com/black-parrot/black-parrot/-/jobs/2343047561/artifacts/browse/bp_me/syn/reports/vcs/\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/black-parrot_black-parrot_pr1089", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/black-parrot_black-parrot_pr1089.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/black-parrot_black-parrot_pr1089", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/black-parrot_black-parrot_pr1089"}
{"instance_id": "black-parrot_black-parrot_pr1232", "issue_text": "# [bug] Case label selector mismatch\n\n- Source URL: https://github.com/black-parrot/black-parrot/issues/1230\n\nI'm doing some research related to static analysis of verilog and I found an interesting case that looks like a copy-paste bug.\n\n[Here](https://github.com/black-parrot/black-parrot/blob/08edfb479c7b5d55d665a63464785044c6b4cd35/bp_fe/src/v/bp_fe_icache.sv#L582) label with is equal to 4 bit which do not match with selector case (`opcode`) width which is 3.\n\nIs this done on purpose or is it a mistake or typo or copy-paste bug from [here](https://github.com/black-parrot/black-parrot/blob/08edfb479c7b5d55d665a63464785044c6b4cd35/bp_be/src/v/bp_be_dcache/bp_be_dcache.sv#L882)?\n\n---\n\nPR #1232: Fix case label mismatch\n\nPR Description:\nThe PR addresses issue #1230 (closes the issue).\n\nPR Comments:\n- likeamahoney (Nov 22, 2024): \"Closes #1230\"\n- dpetrisko (Jan 14, 2025): \"Thank you!\"\n\nLinked Issue #1230 - \"[bug] Case label selector mismatch\" (body shown above)\n\nStatus: Merged by dpetrisko on January 14, 2025.\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/black-parrot_black-parrot_pr1232", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/black-parrot_black-parrot_pr1232.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/black-parrot_black-parrot_pr1232", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/black-parrot_black-parrot_pr1232"}
{"instance_id": "black-parrot_black-parrot_pr947", "issue_text": "PR Title: fix LCE uncached store overflow - #945\n\nPR Description:\nSummary: This PR adjusts the cache request valid register in the LCE Request module and tweaks credit counting to prevent overwriting and dropping of uncached store requests.\n\nIssue Fixed: Fixes #945\n\nArea: LCE Request\n\nReasoning: Functional bug fix\n\nAdditional Changes Required: None\n\nVerification: A newly added `mc_uc_store` test in bp-tests exposes this bug. Testing revealed that \"~25% of stores were dropped in a sequence of 100 consecutive stores\" without the fix. With the fix applied, all stores are accounted for. A debug check was added to catch recurrence.\n\nPR Comments:\n- muwyse (Oct 13, 2021): \"Thanks for contributing to BlackParrot! Check out the CONTRIBUTING guide, if this is your first time.\"\n- dpetrisko (Oct 13, 2021): \"Thanks, great!\"\n\nLinked Issue #945: \"Potential uncached store drops in LCE\"\n\nOriginal local content (issue context):\nPotential uncached store drops in LCE #945\n\nblack-parrot/bp_me/src/v/lce/bp_lce_req.sv\n\nLine 223 in b095d30\n\n // TODO: This could drop uncached stores, if we accept but lce is not ready\nThis should be handled as in https://github.com/black-parrot/black-parrot/blob/master/bp_me/src/v/cce/bp_uce.sv#L599. where the request is not accepted if it cannot go on the network (or if there is no currently pending request)\n\nI thought the cache_req_yumi_o signal accounted for this:\n\nblack-parrot/bp_me/src/v/lce/bp_lce_req.sv\n\nLine 237 in b095d30\n\n cache_req_yumi_o = cache_req_v_i\nNamely, the first part of the && conditions is (~cache_req_v_r | lce_req_v_o), which will block a new request from being accepted from the cache if we already have a valid request and it is not sending this cycle.\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/black-parrot_black-parrot_pr947", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/black-parrot_black-parrot_pr947.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/black-parrot_black-parrot_pr947", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/black-parrot_black-parrot_pr947"}
{"instance_id": "black-parrot_black-parrot_pr974", "issue_text": "PR Title: Fix inferred latches\n\nPR Description:\nThe pull request removed inferred latches from `bp_me_axil_master` and `bp_me_axil_client` components. The issue was that `state_n` lacked a default value, causing it to become a latch unintentionally.\n\nArea Affected: AXI master and client subcomponents\n\nLinked Issue: Fixes #972\n\nPR Activity:\n- Self-assigned: dpetrisko (Dec 1, 2021)\n- Label added: bug\n- Merged commit: 7f9a1e2 (Dec 14, 2021)\n- Branch deleted: dev_fix_axilatch\n\nStatus: Merged on Dec 14, 2021 by dpetrisko.\n\nLinked Issue #972 body:\nI'm using:\nMaster branch / dd2d845\n\nArea\nThe 'state_n' variables in bp_me_axil_master and client will be inferred into latches due to incomplete cases.\n\nhttps://github.com/black-parrot/black-parrot/blob/master/bp_me/src/v/network/bp_me_axil_master.sv#L68\nhttps://github.com/black-parrot/black-parrot/blob/master/bp_me/src/v/network/bp_me_axil_client.sv#L73\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/black-parrot_black-parrot_pr974", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/black-parrot_black-parrot_pr974.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/black-parrot_black-parrot_pr974", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/black-parrot_black-parrot_pr974"}
{"instance_id": "budude2_openfpga-GBC_pr41", "issue_text": "PR Title: Fix audio channel mix-up\n\nPR Description:\nFixes #39.\n\nPR Comments:\n- hallmeier (Feb 25, 2024): \"Fixes #39. Sorry, something went wrong.\"\n- budude2 (Feb 26, 2024): Merged commit b57862f into the master branch.\n\nLinked Issue #39 Title: \"Stereo channels appear to be swapped in both the GB and GBC cores.\"\n\nLinked Issue #39 Body:\nI have created a Gameboy Test Cartridge for the Gameboy Color. While testing the ROM on all of the different Analogue Pocket cores, I discovered that these two cores play the opposite audio channels than what is expected.\n\nCore version used: v1.0.7\nCores affected: GB and GBC\n\nHere's my test ROM so you can experiment and see for yourself:\n[Stereo Tester.zip](https://github.com/budude2/openfgpa-GBC/files/14350415/Stereo.Tester.zip)\n\nStatus: Merged on Feb 26, 2024 by budude2 (commit 6fd8eb3).\n\nAuthor: hallmeier\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/budude2_openfpga-GBC_pr41", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/budude2_openfpga-GBC_pr41.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/budude2_openfpga-GBC_pr41", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/budude2_openfpga-GBC_pr41"}
{"instance_id": "buppu3_tnCart_pr17", "issue_text": "PR Title: fix leftover from CLK_14M cleanup\n\nPR Description:\nThe RTL hierarchy tab in GOWIN FPGA Designer displayed an error: \"ERROR EX3813 : 'CLK_14M' is not declared under prefix 'Primary'\" at rtl/src/peripheral/msx/bus.sv line 194.\n\nThe CLK_14M signal from the BUS_IF interface had been removed in a prior commit addressing issue #7 (\"Synchronize the operating clock with the bus clock\"). This PR removes the orphaned assignment that was still referencing the deleted signal.\n\nThe contributor noted uncertainty about why the assignment didn't trigger synthesis errors during bitstream compilation.\n\nPR Comments:\n- herraa1 (contributor, Sep 23, 2024): Provided the PR description detailing the error condition and rationale for the fix.\n- buppu3 (maintainer, Sep 24, 2024): \"This module was not being used anywhere so it was not showing as a fatal error.\"\n\nLinked Issue #7 Title: \"V9990 の DVI 出力がビデオキャプチャーできない\"\n\nLinked Issue #7 Body:\n- Source URL: https://github.com/buppu3/tnCart/issues/7\n\nGC533(HDMI ビデオキャプチャー)の最新ファームウェアでキャプチャができなくなった。\nV9990 エミュレーションのドットクロックタイミングは MSX バスクロックから生成しているが、MSX バスクロック (約3.58MHz) と DIV ドットクロック(27Mhz) の同期がとれず、VSYNC のタイミングがフレーム毎にブレてしまい信号が安定しない為。\n\nStatus: Merged.\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/buppu3_tnCart_pr17", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/buppu3_tnCart_pr17.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/buppu3_tnCart_pr17", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/buppu3_tnCart_pr17"}
{"instance_id": "chili-chips-ba_openeye-CamSI_pr13", "issue_text": "PR Title: Fixed I2C reset first issue\n\nPR Description:\n(No description provided.)\n\nPR Comments:\n- Juninho99 (Collaborator): No description provided.\n\nLinked Issue #12 (referenced as \"issue#1\" in the PR):\nThe PR indicates it may close issue #12.\n\nLinked Issue body (issue#1):\n# issue#1\n\n## Fix I2C reset issue\n\n### First Issue:\nThe `i2c_reset` signal, which is generated in the `top/u_clkrst_gen` module, is based on the `srst` signal from the `top/u_clkrst_gen/u_pll_top` module. Since the `srst` signal does not occur at the very beginning, the `i2c_reset` signal is also delayed, as shown in the attached image. The image illustrates that as a consequence, `i2c_sda` and `i2c_scl` start, but then halt due to the reset.\n\nThe solution would be to ensure that `i2c_reset` is initially set to 0 and remains 0 until the `rst_delay_cnt` counter reaches 4 (since the I2C is enabled only after 4 seconds from the system power-up).\n\n### Second Issue:\nWhen the `reset` signal in the `top/u_i2c` module goes to 0, data transmission on the I2C bus begins. However, at that moment, the value of the slave address, which is the first data transmitted via I2C, is set to an undefined value. Consequently, the setting of the `slave_address_plus_rw` (slave address plus read/write) signal is delayed by one data transmission cycle via I2C, which is not desirable. As a result, the first slave address written is 0.\n\nTo solve this second problem, the slave address should be set before the start of the I2C section. One approach is to introduce an additional input signal (which can be `cam_en`, as it occurs before the `i2c_reset`, as shown in the image).\n\n![image](https://github.com/chili-chips-ba/openeye-CamSI/assets/70281175/737a8a05-efec-4ea6-8eed-b327290e9d0c)\n\nPR Status: Merged on June 4, 2024.\nReviewers Requested: chili-chips-ba, IsamVrce, AnelXYZ\nAssignee: Juninho99\n\nCommits in PR:\n1. \"Fixed I2C reset first issue\" (df2200c)\n2. \"Minor clean up\" (c7dd6d0)\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/chili-chips-ba_openeye-CamSI_pr13", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/chili-chips-ba_openeye-CamSI_pr13.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/chili-chips-ba_openeye-CamSI_pr13", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/chili-chips-ba_openeye-CamSI_pr13"}
{"instance_id": "chili-chips-ba_openeye-CamSI_pr15", "issue_text": "# issue#2 - Testbench for I2C subsystem\n\n## Writing Testbench for I2C Part of Our Camera\r\n\r\nWe need to write a testbench for the I2C part of our camera. For this purpose, we have utilized the `cocotbext-i2c` library. Specifically, we used only the `I2CDevice.py` module from this library, which emulates the slave device. The master part, however, was implemented directly in RTL.\r\n\r\n### Challenges Encountered:\r\n1. **SDA/SCL Bidirectional Signals**:\r\n   - The primary challenge was handling the bidirectional (inout) nature of the SDA and SCL lines.\r\n   - To resolve this, we had to define these lines as follows in our RTL code:\r\n     ```verilog\r\n     inout tri1 i2c_sda,\r\n     inout tri1 i2c_scl,\r\n     ```\r\n   - This specific declaration was necessary for cocotb to properly drive these signals.\r\n\r\n2. **Simulator Selection**:\r\n   - Another significant issue was choosing the appropriate simulator.\r\n   - Verilator, which is commonly used, does not support 'Z (high impedance) and 'X (unknown) values, supporting only log0 and log1.\r\n   - This limitation made it unsuitable for our testbench, requiring us to explore alternative simulators that can handle these signal states.\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/chili-chips-ba_openeye-CamSI_pr15", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/chili-chips-ba_openeye-CamSI_pr15.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/chili-chips-ba_openeye-CamSI_pr15", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/chili-chips-ba_openeye-CamSI_pr15"}
{"instance_id": "chili-chips-ba_openeye-CamSI_pr26", "issue_text": "# issue#7 - Enable HiRez Sony camera\n\n# Add support for the 4-lane \"OneInch\" camera (Sony IMX283)\r\n## Description:\r\n\r\nThe next project milestone is to expand the existing 2-lane CSI to 4-lane, and establish video datapath for this particular high-end camera. This milestone encompasses the following tasks: \r\n\r\n### 1. Upgrade simulation environment to allow both 2 and 4-lane data paths, with 4 video formats: RAW8, RAW10, RAW12, RAW14\r\n- [x] CSI BFM \r\n- [x] Testbench and relevant sim scripts\r\n- [ ] Time permitting, also add 1-lane option \r\n\r\n### 2. Extend RTL from only RAW8 to also support RAW10, RAW12, and RAW14 image formats\r\n- [x] RAW2RGB block -- If it's too messy to support all 4 formats in one file, implement it in 4 separate files \r\n- [x] Integration\r\n\r\n### 3. End-to-end simulations\r\n- [x] Verify old and new data path options in functional simulation through the entirety of video processing chain \r\n\r\n### 4. Validate OneInch sensor and new data path on the real hardware\r\n- [x] Work out I2C configurations for the camera (as our sim setup does not cover that part)\r\n- [x] Check video pipeline stages from CSI all the way to HDMI. If needed, use Chipscope ILA for debug\r\n- [x] Crate a new demo, similar to the earlier for 2-lane RPi camera, but now with higher resolution Sony IMX294 camera\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/chili-chips-ba_openeye-CamSI_pr26", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/chili-chips-ba_openeye-CamSI_pr26.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/chili-chips-ba_openeye-CamSI_pr26", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/chili-chips-ba_openeye-CamSI_pr26"}
{"instance_id": "chili-chips-ba_openeye-CamSI_pr30", "issue_text": "PR Title: Updated i2c part according to issue#30\n\nPR Description:\n(No description was provided by the author.)\n\nPR Comments:\n- Juninho99 (Oct 29, 2024): No comment text provided.\n- Juninho99: Requested review from chili-chips-ba and self-assigned the PR.\n- chili-chips-ba (Nov 6, 2024): Merged the pull request into main.\n\nLinked Issue Title: \"Implementing Variable Pauses After I2C Register Writes in i2c_ctrl Module #29\"\nStatus: Closed (by this PR)\n\nLinked Issue body (issue#9):\n# issue#9 - Implementing Variable Pauses After I2C Register Writes in i2c_ctrl Module\n\n## Description:\nAccording to the camera's specification (**Sony IMX283**), after certain registers are written, there needs to be a pause of a few milliseconds before proceeding to the next set of registers.\n\n## Objective:\nModify the existing `i2c_ctrl` module and `i2c_top` module to implement variable pauses after specific I2C register writes, as specified by the camera's requirements.\n\n## Problem Statement:\nThe challenge is to introduce variable pauses after writing certain registers, as required by the camera's specification. These pauses are not periodic and occur only after specific registers. The pauses need to be controlled dynamically, allowing for different durations specified in milliseconds.\n\n## Proposed Solution:\n- Modify the `i2c_init.mem` file to include the pause duration for each register write.\n- Update the `i2c_data_init` array in the `i2c_top` module to read the pause durations along with register addresses and data.\n- Adjust the `i2c_ctrl` module to implement a **WAIT** state that counts the required pause duration using nested counters, avoiding resource-intensive multiplication.\n- Ensure that pauses are dynamically controlled based on the data read from i2c_init.mem.\n\nKey Details:\nThe PR contains 2 commits:\n1. \"Updated i2c part according to issue\" (d6b71f5)\n2. \"Changed names of .mem files\" (3c69f4b)\n\nThe changes were merged from the `issue#9` branch into `main` on November 6, 2024.\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/chili-chips-ba_openeye-CamSI_pr30", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/chili-chips-ba_openeye-CamSI_pr30.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/chili-chips-ba_openeye-CamSI_pr30", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/chili-chips-ba_openeye-CamSI_pr30"}
{"instance_id": "chipsalliance_Cores-VeeR-EL2_pr151", "issue_text": "# Export ECC violation signals to the top level as status outputs\n\n- Source URL: https://github.com/chipsalliance/Cores-VeeR-EL2/issues/147\n\nAs was done in the Caliptra VeeR core instance ([here](https://github.com/chipsalliance/caliptra-rtl/blob/main/src/riscv_core/veer_el2/rtl/el2_veer.sv#L380-L385)), it is useful to export SRAM ECC status signals so that integrators can make use of the status for RAS features. In some cases, ECC errors may occur that render the VeeR core unable to execute recovery code (such as code that reads internal mcause/mscause registers). Some ECC errors are not reported explicitly (such as an ICCM ECC error during an LSU read), so there is no way to diagnose corrupted bits as the root cause of the issue in lab debug.\n\n\n\n\n\n\n\n\n\n\n\n# GitHub Issue #147\n\n## Issue Title\nExport ECC violation signals to the top level as status outputs\n\n## Issue Description\nThe issue requests exporting SRAM ECC status signals to the top level, similar to what was implemented in the Caliptra VeeR core. The requester notes that \"ECC errors may occur that render the VeeR core unable to execute recovery code\" and that some ECC errors lack explicit reporting, making it difficult to diagnose corrupted bits during debugging.\n\n## Linked Pull Request\nPR #151 is associated with this issue (marked as closed).\n\n## Key Points\n- Purpose: Enable integrators to utilize ECC status signals for RAS (Reliability, Availability, and Serviceability) features\n- Problem: Certain ECC errors—such as ICCM ECC errors during LSU reads—are not explicitly reported, complicating root-cause analysis\n- Precedent: Similar implementation exists in Caliptra VeeR core repository\n\n## Metadata Status\n- No assignees listed\n- No labels or milestones assigned\n- Issue opened December 11, 2023\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/chipsalliance_Cores-VeeR-EL2_pr151", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/chipsalliance_Cores-VeeR-EL2_pr151.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/chipsalliance_Cores-VeeR-EL2_pr151", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/chipsalliance_Cores-VeeR-EL2_pr151"}
{"instance_id": "chipsalliance_Cores-VeeR-EL2_pr153", "issue_text": "# Synthesis issue due to perr_dat_ff signal\n\n- Source URL: https://github.com/chipsalliance/Cores-VeeR-EL2/issues/149\n\nThe issue is originally detailed in https://github.com/chipsalliance/caliptra-rtl/issues/317.\n\nWhen Icache is disabled in the VeeR core, this perr_dat_ff signal is unused but is not disabled in the RTL, which results in a no-driver synthesis warning.\n\n\n\n\n\n\n\n\n\n\n# GitHub Issue #149\n\n## Issue Title\nSynthesis issue due to perr_dat_ff signal\n\n## Issue Description\nWhen Icache is disabled in the VeeR core, this perr_dat_ff signal is unused but is not disabled in the RTL, which results in a no-driver synthesis warning.\n\nThe issue references a related problem documented in another repository's issue tracker (chipsalliance/caliptra-rtl#317).\n\n## Key Details\n- Status: Closed\n- Related PR: #153\n- Reporter: calebofearth\n- Opened: December 11, 2023\n- Comments/Responses: None visible\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/chipsalliance_Cores-VeeR-EL2_pr153", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/chipsalliance_Cores-VeeR-EL2_pr153.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/chipsalliance_Cores-VeeR-EL2_pr153", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/chipsalliance_Cores-VeeR-EL2_pr153"}
{"instance_id": "chipsalliance_Cores-VeeR-EL2_pr259", "issue_text": "# Export DMI enable/active signals for core TAP accesses\n\n- Source URL: https://github.com/chipsalliance/Cores-VeeR-EL2/issues/257\n\ndmi_mux.v has an uncore_enable signal that gates exported DMI accesses. We request a similar control signal be exported to gate internal core jtag accesses as well. We also request export of a \"dmi_active\" signal to indicate when the debug module is driving an access.\nThese reference commits show an implementation of both requests:\nhttps://github.com/chipsalliance/caliptra-rtl/commit/22c08e12334afa5a408393155ec97c5141f3d2a7\nhttps://github.com/chipsalliance/caliptra-rtl/commit/41173449344e8270515cde48aae5dc7a90f3ce10\n\n\n\n\n\n\n\n# Issue #257: Export DMI Enable/Active Signals for Core TAP Accesses\n\n## Issue Description\n\nAuthor: calebofearth (opened Nov 7, 2024)\n\nThe issue requests two enhancements to the VeeR-EL2 core's debug interface:\n\n1. Core JTAG Access Control: Export a control signal to gate internal core JTAG accesses, similar to the existing \"uncore_enable\" signal in dmi_mux.v that controls exported DMI accesses.\n\n2. DMI Activity Indicator: Export a \"dmi_active\" signal to indicate when the debug module is actively driving an access.\n\nReference Implementation: The requester provided two commits from the Caliptra RTL project demonstrating both features:\n- Commit 22c08e1\n- Commit 41173449\n\n## Status\n- State: Closed\n- Related PR: #259\n- Assignee: Unassigned\n- Labels: None\n\n## Comments\nNo comments were visible in the provided content.\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/chipsalliance_Cores-VeeR-EL2_pr259", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/chipsalliance_Cores-VeeR-EL2_pr259.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/chipsalliance_Cores-VeeR-EL2_pr259", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/chipsalliance_Cores-VeeR-EL2_pr259"}
{"instance_id": "chipsalliance_Cores-VeeR-EL2_pr265", "issue_text": "# Compile error - identifier undeclared\n\n- Source URL: https://github.com/chipsalliance/Cores-VeeR-EL2/issues/261\n\nI’m having a compile issue in [el2_dec_tlu_ctl.sv](https://github.com/chipsalliance/Cores-VeeR-EL2/blob/main/design/dec/el2_dec_tlu_ctl.sv) due to identifiers that are used before their declaration. One example:\n```\nError-[IND] Identifier not declared\ncaliptra-rtl/src/riscv_core/veer_el2/rtl/dec/el2_dec_tlu_ctl.sv, 998\n  Identifier 'CYCLEL' has not been declared yet. If this error is not\n  expected, please check if you have set `default_nettype to none.\n```\n\n\n\n\n\n# Issue #261: Compile Error - Identifier Undeclared\n\n## Issue Title\nCompile error - identifier undeclared\n\n## Author\ncalebofearth (opened Nov 7, 2024)\n\n## Issue Body\nThe user reported a compilation failure in `el2_dec_tlu_ctl.sv` where identifiers are referenced before being declared. The specific error message states:\n\n> \"Identifier 'CYCLEL' has not been declared yet. If this error is not expected, please check if you have set `default_nettype to none.\"\n\nThe error occurs at line 998 of the file located in the VeeR EL2 core's design/dec directory.\n\n## Related PR\nPR #265 is associated with this issue, indicating a fix was submitted to address the compilation problem.\n\n## Status\nThe issue is marked as Closed.\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/chipsalliance_Cores-VeeR-EL2_pr265", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/chipsalliance_Cores-VeeR-EL2_pr265.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/chipsalliance_Cores-VeeR-EL2_pr265", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/chipsalliance_Cores-VeeR-EL2_pr265"}
{"instance_id": "chipsalliance_Cores-VeeR-EL2_pr363", "issue_text": "# Request to review Lint Issues in Veer RTL\n\n- Source URL: https://github.com/chipsalliance/Cores-VeeR-EL2/issues/166\n\nHi, I am filling this issue to review couple of Lint issues inside Veer RTL.\r\n\r\n1. In **el2_veer.sv** file, below highlighted signals are read but never set.\r\n\r\n   assign ifu_axi_bready_int                  = pt.BUILD_AHB_LITE ? **ifu_axi_bready_ahb** : ifu_axi_bready;\r\n   assign lsu_axi_bready_int                  = pt.BUILD_AHB_LITE ? **lsu_axi_bready_ahb** : lsu_axi_bready;\r\n   assign sb_axi_bready_int                   = pt.BUILD_AHB_LITE ? **sb_axi_bready_ahb** : sb_axi_bready;\r\n\r\n\r\n2. Output signal highlighted below is never set.\r\n\r\nOutput '**ifu_bp_fa_index_f**' is never set. (veer_el2/rtl/ifu/el2_ifu_bp_ctl.sv)\r\nOutput '**exu_mp_pkt.br_start_error**' is never set. (veer_el2/rtl/exu/el2_exu.sv)\r\nOutput '**exu_mp_pkt.br_error**' is never set. (veer_el2/rtl/exu/el2_exu.sv)\r\nOutput '**exu_mp_pkt.prett[31:1]**' is never set. (veer_el2/rtl/exu/el2_exu.sv)\r\nOutput '**lsu_ld_data_r[31:0]**' is never set. (veer_el2/rtl/lsu/el2_lsu_dccm_ctl.sv)\r\nOutput '**dccm_rdata_lo_r[31:0]**' is never set. (veer_el2/rtl/lsu/el2_lsu_dccm_ctl.sv)\r\nOutput '**dccm_rdata_hi_r[31:0]**' is never set. (veer_el2/rtl/lsu/el2_lsu_dccm_ctl.sv)\r\nOutput '**dccm_data_ecc_lo_r[6:0]**' is never set. (veer_el2/rtl/lsu/el2_lsu_dccm_ctl.sv)\r\nOutput '**dccm_data_ecc_hi_r[6:0]**' is never set. (veer_el2/rtl/lsu/el2_lsu_dccm_ctl.sv)\r\nOutput '**ic_parerr[1:0]**' is never set. (veer_el2/rtl/el2_mem.sv)\r\n\r\nRequest to clean up the code to keep Lint happy.\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/chipsalliance_Cores-VeeR-EL2_pr363", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/chipsalliance_Cores-VeeR-EL2_pr363.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/chipsalliance_Cores-VeeR-EL2_pr363", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/chipsalliance_Cores-VeeR-EL2_pr363"}
{"instance_id": "chipsalliance_Cores-VeeR-EL2_pr423", "issue_text": "Changes in #285 cause the logic to fail when multiple LSU Read requests are issued. The symptom is observed when hready deasserts to stall the AHB request, in compliance with the AHB-lite specification.\n\nThis failing scenario may be reproduced in Calitpra by running the tmp_fpga_repro on this branch:\nhttps://github.com/chipsalliance/caliptra-rtl/tree/cwhitehead-msft-rv-b2b-access-dbg\n\nSpecifically, changes to the ahb_htrans signal in https://github.com/chipsalliance/Cores-VeeR-EL2/pull/285/files#diff-49cc6a6800643a1307ae082c5b50091ff340fbb656fa66e6e5abdd8999021448\ncause 2 problems:\n\nOn back-to-back reads, the htrans signal transitions from 2'b10 (NONSEQ request) to 2'11 (SEQ request) when the state machine enters the STREAM_RD state\nThis results in the lower 3-bits of buf_addr being masked incorrectly, which forces alignment on the ahb_haddr signal and overrides the buffered request address.\n\n\n\n# Pull Request Summary\n\nPR Title: 2.0 ahb fix\n\nPR Number: #423\n\nStatus: Merged (Oct 6, 2025)\n\nTarget Branch: 2.0-patches\n\nSource Branch: 2.0-ahb-fix\n\n## PR Description\nThe pull request addresses issue #418 and includes comprehensive fixes related to AHB protocol handling. The changes span multiple commits focused on improving the AXI to AHB translation functionality.\n\n## Key Comments\n- kgugala (Author): \"fixes #418\"\n- calebofearth (Reviewer): Initially requested adding the prefix_macros.sh script to the PR, then later approved the changes with a note: \"We will merge with lint test bypass - this is expected to be fixed in #424\"\n\n## Commits Included (6 total)\n1. CI infrastructure update - Updated test scripts for current testing infrastructure\n2. Revert commit - Reverted AXI4-to-AHB STREAM_RD state coverage addition\n3. ahb_lsu_dma_bridge behavior change - Modified to maintain AHB protocol throughout, eliminating unnecessary conversions and delays\n4. read_after_read test - Added new test case\n5. Prefix macro script - Script for adding custom prefixes to macros, parameter structures, and module names\n6. Design file name prefixing - Updated file naming when prefixing VeeR macros\n\n## Related Issues\nSuccessfully addresses: [BUG] AXI to AHB translator breaks with multiple back-to-back reads #418\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/chipsalliance_Cores-VeeR-EL2_pr423", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/chipsalliance_Cores-VeeR-EL2_pr423.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/chipsalliance_Cores-VeeR-EL2_pr423", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/chipsalliance_Cores-VeeR-EL2_pr423"}
{"instance_id": "chipsalliance_adams-bridge_pr175", "issue_text": "PR Title: [RTL] enabled external mu\n\nPR Description:\n(No description provided.)\n\nPR Comments:\n- mojtaba-bisheh (Collaborator): \"No description provided.\" (initial comment)\n- Nitsirks: Approved the changes on July 29, 2025\n\nLinked Issue Title: \"Enabing External_Mu mode\" (Issue #108)\n\nLinked Issue #108 body:\n# Enabing External_Mu mode\n\n- Source URL: https://github.com/chipsalliance/adams-bridge/issues/108\n\nWe hardcoded this mode internally to 0 until validation gets done. After that, this mode should be enabled.\n\nhttps://github.com/chipsalliance/adams-bridge/blob/ea5bba46ef92404a5e80c0913579b957a891f0f7/src/mldsa_top/rtl/mldsa_ctrl.sv#L389\n\nKey Details:\n- Status: Merged into main branch on July 29, 2025\n- Commits: 2 commits included\n- Reviewer approval: Nitsirks approved; upadhyayulakiran's review was pending\n- Branch deleted after merge: mojtaba_external_mu branch was deleted post-merge\n- All checks passed (5 checks)\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/chipsalliance_adams-bridge_pr175", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/chipsalliance_adams-bridge_pr175.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/chipsalliance_adams-bridge_pr175", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/chipsalliance_adams-bridge_pr175"}
{"instance_id": "chipsalliance_adams-bridge_pr176", "issue_text": "PR Title: [RTL][TB] Fix issues in compress, decompress, and input checks\n\nPR Description:\nThe PR addresses four GitHub issues (165, 167, 168, 169) by implementing several fixes:\n- Input validation for encapsulation keys (each coefficient must be < MLKEM Q)\n- Input validation for decapsulation keys (encapsulation portion and hash verification)\n- Reset of decompress write address after completion\n- Proper timing of done signal in compress operation after all pipeline stages empty\n- Random test cases for both input checks\n\nCommits (10 total):\nThe pull request includes commits addressing: decompress write address clearing, done signal timing, sequencer state renaming with ABR prefix, flop coding fixes, decompression logic corrections, error status implementation, test cases for encap/decap input errors, and error state persistence.\n\nAuthor: Nitsirks\nReviewer & Merger: mojtaba-bisheh (approved July 30, 2025)\n\nLinked Issues Closed:\n- #165: Compression block done signal assertion timing\n- #167: Second decompression raising done prematurely\n- #168: Decaps flow missing input check\n- #169: Encaps flow missing input check\n\nLinked Issue #165 body:\n# mlkem: compression block done signal asserts before tx end\n\n- Source URL: https://github.com/chipsalliance/adams-bridge/issues/165\n\nIn the compression when the last chunk of data being written to the memory the read done is asserted as the last rd is done but data arrives next cycle and buffer_valid_f to be set in next clock cycle. This would set the done and api write would happen in next clock cycle. But if the compress mode toggles in this cycle then the api wr isn't triggered and this causes the loss of data.\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/chipsalliance_adams-bridge_pr176", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/chipsalliance_adams-bridge_pr176.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/chipsalliance_adams-bridge_pr176", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/chipsalliance_adams-bridge_pr176"}
{"instance_id": "chipsalliance_adams-bridge_pr213", "issue_text": "# mlkem kv data present reset only dependent on mldsa_valid\n\n- Source URL: https://github.com/chipsalliance/adams-bridge/issues/215\n\nIn the abr_ctrl module \"kv_data_present_reset\" signal is used to reset mldsa seed, mlkem msg and seed. But the trigger for this signal is only dependent on the mldsa_valid_reg, instead it should be mldsa_valid_reg | mlkem_valid_reg.\n\nPR Title: added mlkem_valid to reset kv_data_present\nPR Number: #213\nStatus: Merged\nAuthor: mojtaba-bisheh\nMerge Date: September 15, 2025\n\nDescription:\nNo description was provided by the author.\n\nComments:\nmojtaba-bisheh (Collaborator) - September 15, 2025: \"_No description provided._\"\n\nLinked Issue:\nIssue #215: \"mlkem kv data present reset only dependent on mldsa_valid\"\nThis pull request may close the above issue.\n\nReview Status:\n- upadhyayulakiran: Approved\n- Nitsirks: Awaiting review\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/chipsalliance_adams-bridge_pr213", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/chipsalliance_adams-bridge_pr213.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/chipsalliance_adams-bridge_pr213", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/chipsalliance_adams-bridge_pr213"}
{"instance_id": "chipsalliance_adams-bridge_pr222", "issue_text": "# [RTL] Sequencer does not load entropy for MLKEM operation\n\n- Source URL: https://github.com/chipsalliance/adams-bridge/issues/223\n\nSequencer is missing steps in MLKEM operation to load entropy from API register to seed the LFSR for masking countermeasures.\n\nThis doesn't disable the countermeasures, randomness is still present but this strengthens them.\n\nPR Title: [RTL] MLKEM lfsr\nPR Number: #222\nStatus: Merged\nAuthor: mojtaba-bisheh\nMerge Date: September 30, 2025\n\nDescription:\nNo description was provided by the author.\n\nReview Activity:\n- Nitsirks approved the changes after the final commit\n- The review of earlier commits was dismissed due to subsequent updates\n\nLinked Issue:\nIssue #223: \"[RTL] Sequencer does not load entropy for MLKEM operation\" – appears to be resolved by this PR\n\nParticipants:\n- mojtaba-bisheh (author/merger)\n- Nitsirks (reviewer/approver)\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/chipsalliance_adams-bridge_pr222", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/chipsalliance_adams-bridge_pr222.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/chipsalliance_adams-bridge_pr222", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/chipsalliance_adams-bridge_pr222"}
{"instance_id": "chipsalliance_adams-bridge_pr228", "issue_text": "# [BUG] Shared key is exposed when msg or seed come from keyvault\n\n- Source URL: https://github.com/chipsalliance/adams-bridge/issues/227\n\nThe shared key can be read over the API if the msg or seed come from the keyvault, but the shared key was not programmed to write to the keyvault.\n\nThe data present bits are being reset as soon as the valids are asserted, which allows the shared key api to be read out.\n\nThe fix is to only reset the data present bits on the mandatory zeroize.\n\nPR Title: [RTL] Fix bug 227, only reset kv data present bits on mandatory zeroize\n\nDescription:\nThe pull request addresses a security vulnerability in Caliptra's instantiation of the adams-bridge component. The issue involved keyvault data present bits, which are designed to protect shared keys from being read when source data originates from the keyvault. Previously, these protection bits were being reset at the end of operations, potentially exposing the shared key through the read API if the destination wasn't set to the keyvault.\n\nThe fix ensures that \"data present bits will be reset when the mandatory zeroize is issued between operations.\"\n\nLinked Issue:\nIssue #227: \"[BUG] Shared key is exposed when msg or seed come from keyvault\"\n\nComments & Activity:\nNitsirks (Collaborator):\n- Initiated the PR, requesting review from mojtaba-bisheh\n- Changed the title from referencing \"bug 224\" to \"bug 227\"\n\nmojtaba-bisheh:\n- Approved the changes on October 3, 2025\n\nStatus:\n- Merged into main branch on October 3, 2025\n- 5 checks passed\n- 2 commits included\n- Branch subsequently deleted\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/chipsalliance_adams-bridge_pr228", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/chipsalliance_adams-bridge_pr228.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/chipsalliance_adams-bridge_pr228", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/chipsalliance_adams-bridge_pr228"}
{"instance_id": "chipsalliance_adams-bridge_pr245", "issue_text": "# MLDSA verif with msg stream operation is failing in second iteration\n\n- Source URL: https://github.com/chipsalliance/adams-bridge/issues/244\n\nThe verif operation o/p is not matching on second iteration. Looks like the first operation has some left over which is corrupting the second operation.\nThe test is vanilla https://github.com/chipsalliance/adams-bridge/blob/v1.0/src/mldsa_top/uvmf/uvmf_template_output/project_benches/mldsa/tb/sequences/src/ML_DSA_verif_KATs_stream_msg_sequence.svh\n\nThe commit I am at is : commit 774b4f1e140b04c2a4302c1d1909693c919bf3b9 (HEAD -> main, origin/main, origin/HEAD)\nAuthor: Michael Norris <108370498+Nitsirks@users.noreply.github.com>\nDate:   Thu Nov 13 06:59:57 2025 -0800\n\nPR Title: [VAL] fix for failing stream message KAT\nPR Number: #245\nStatus: Merged\nMerge Date: December 9, 2025\n\nDescription:\nThe pull request contains two key updates to the stream message KAT (Known Answer Test):\n1. Disable the scoreboard and rely on self-checking mechanisms\n2. Reset STROBE back to 0xF at the beginning of each KAT iteration\n\nComments:\nNitsirks (Collaborator) - December 9, 2025:\n\"update stream msg KAT to disable scoreboard and rely on self checking update stream msg KAT to set STROBE back to 0xF at the start of each KAT\"\n\nmojtaba-bisheh - December 9, 2025:\nApproved the changes after reviewing the modifications.\n\nLinked Issue:\nTitle: \"MLDSA verif with msg stream operation is failing in second iteration\"\nIssue Number: #244\nThis PR was intended to resolve the failing MLDSA verification issue occurring during the second iteration of message stream operations.\n\nParticipants:\n- Nitsirks (author)\n- mojtaba-bisheh (reviewer/merger)\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/chipsalliance_adams-bridge_pr245", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/chipsalliance_adams-bridge_pr245.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/chipsalliance_adams-bridge_pr245", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/chipsalliance_adams-bridge_pr245"}
{"instance_id": "chipsalliance_adams-bridge_pr66", "issue_text": "# [Security question] Extracting HW-bound keys of Caliptra\n\n- Source URL: https://github.com/chipsalliance/adams-bridge/issues/48\n\nReference commit: 46d8b6e9cfd0020d485012cf261a21278a5e8671\r\nRelated SV files: mldsa_ctrl.sv\r\n\r\n### High-level summary\r\n\r\nIf I understand correctly, when integrated into Caliptra, one of the security properties ABR wants to preserve is the secrecy of HW-bound keys (i.e. the seed originating from Key Vault IP) against Caliptra SW. In other words, ABR wants to make sure that no logical path is introduced to Caliptra with ABR that SW can exploit to extract HW-bound secrets. That should also include the intermediate secret values appearing in ML-DSA algorithms that give an attacker the signing capabilities. Such example values would be s_1, s_2 vectors, which are also part of the secret key.\r\n\r\nI reach to this security goal assumption from the fact that there is a dedicated Key Vault IP in Caliptra and that the ABR spec says \"If seed comes from key vault, this register will not contain the private key to avoid exposing secret assets to software.\" (Section 1.10).\r\n\r\nI am thinking about the following scenario, and my question is whether the HW-bound secret can be leaked. In particular, I am thinking about leaking s_1 and s_2 values through SW interactions (or simply the signing key as defined in ML-DSA).\r\n\r\nIf SW is compromised, I suspect it can do the following to extract the secret signing key (originating from Key Vault IP) from ABR:\r\n\r\n1. SW loads the seed value from Key Vault (by configuring `mldsa_kv_rd_seed_ctrl` register).\r\n2. SW starts the KeyGen operation and waits until the operation completes.\r\n3. In particular, SW does not run zeroize command.\r\n4. SW reads PRIVKEY_OUT register to extract HW-bound signing key.\r\n\r\n### Low-level details\r\n\r\nIn the following line:\r\n\r\nhttps://github.com/chipsalliance/adams-bridge/blob/46d8b6e9cfd0020d485012cf261a21278a5e8671/src/mldsa_top/rtl/mldsa_ctrl.sv#L585\r\n\r\nit seems to me that this line disables reading PRIVKEY_OUT register in two cases:\r\n\r\n* In the middle of the KeyGen operation (which is good),\r\n* when KeyGen is completed but the seed is coming from KeyVault. So I interpret this as an attempt to prevent SW from reading these values at the end of the KeyGen operation (`mldsa_privkey_lock` signal). This part does not seem right to me.\r\n\r\nMy understanding is that `mldsa_privkey_lock` goes down few clock cycles after KeyGen is completed. I trace this signal to `mldsa_valid_reg` in RTL eventually, if I am not mistaken. I think this signal goes down after few clock cycles KeyGen operation is completed:\r\nhttps://github.com/chipsalliance/adams-bridge/blob/46d8b6e9cfd0020d485012cf261a21278a5e8671/src/mldsa_top/rtl/mldsa_ctrl.sv#L187\r\n\r\n### Question\r\n\r\nI am wondering if SW can extract HW-bound ML-DSA signing key by simply running KeyGen and reading PRIVKEY_OUT register. \r\n\r\n@mojtaba-bisheh @ekarabu\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/chipsalliance_adams-bridge_pr66", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/chipsalliance_adams-bridge_pr66.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/chipsalliance_adams-bridge_pr66", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/chipsalliance_adams-bridge_pr66"}
{"instance_id": "chipsalliance_adams-bridge_pr68", "issue_text": "# lint waiver file doesn’t exist\n\n- Source URL: https://github.com/chipsalliance/adams-bridge/issues/67\n\nOne of the files provides pointers for lint waivers but the directories doesn’t exist in github\n\nhttps://github.com/chipsalliance/adams-bridge/blob/b4a3eec9a791a260a036f453f4e6ef3f596ea6c8/src/mldsa_top/config/compile.yml#L49\n\nPR Title: Update coverage file and updated max memory depth\nRepository: chipsalliance/adams-bridge\nStatus: Merged on January 16, 2025\n\nDescription:\nNo formal description was provided for this pull request.\n\nKey Commits (16 total):\nThe PR includes commits addressing:\n- Updated ABR coverage with PCR and error handling\n- Updated maximum memory depth parameter\n- Coverage expansion with failure cases\n- Fixed typos and MLDSA coverage port issues\n- Removed lint waiver file pointer reference\n- Renamed signal from reset_n to rst_b\n- Removed cptr_pwrgood element\n- Verification mode adjustments\n\nLinked Issue:\nThis PR may close issue #67: \"lint waiver file doesn't exist\"\n\nReviewers & Approvals:\n- upadhyayulakiran: Approved changes\n- Nitsirks: Left review comments, later approved\n\nTimeline:\n- Initial commits: January 8, 2025\n- Title changed and reviews requested: January 15, 2025\n- Merged: January 16, 2025\n- Branch deleted: February 14, 2025\n\nNote: The PR had stale reviews dismissed after additional commits, with final approval granted before merge.\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/chipsalliance_adams-bridge_pr68", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/chipsalliance_adams-bridge_pr68.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/chipsalliance_adams-bridge_pr68", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/chipsalliance_adams-bridge_pr68"}
{"instance_id": "chipsalliance_adams-bridge_pr77", "issue_text": "# keygen/signing/verifying_process signals need zeroize to be cleared\n\n- Source URL: https://github.com/chipsalliance/adams-bridge/issues/69\n\nwe need to clear them when the process is completed\nhttps://github.com/chipsalliance/adams-bridge/blob/b43c7bc0150e045a7bc2b86f5e5c2d9c36e22f6d/src/mldsa_top/rtl/mldsa_ctrl.sv#L1036C1-L1039C85\n\nPR Title: External_Mu enhancement\n\nDescription:\nThe PR description was not fully loaded in the content provided, but the initial comment indicates:\n- Fixed issue #69\n- Fixed issue #75\n\nLinked Issues:\nIssue #75: \"writing internal mu to hwif_in\"\nIssue #69: \"keygen/signing/verifying_process signals need zeroize to be cleared\"\n\nCommits (13 total):\nKey commits include:\n- Added ExternalMu support\n- Removed hardware write access to mu API\n- Moved external_mu register before memory API\n- Stored internal mu to hwif_in\n- Cleared keygen/signing/verify_process when process completes\n- Hard turned off ExternalMu until validation is ready\n- Multiple automated timestamp stamps and branch merges\n\nComments & Activity:\nmojtaba-bisheh (Jan 23, 2025): Opened PR and requested reviews from Nitsirks and upadhyayulakiran\nNitsirks (Jan 28, 2025): Approved changes and merged the PR\n\nStatus:\nMerged on January 28, 2025. The external_mu branch was subsequently deleted.\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/chipsalliance_adams-bridge_pr77", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/chipsalliance_adams-bridge_pr77.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/chipsalliance_adams-bridge_pr77", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/chipsalliance_adams-bridge_pr77"}
{"instance_id": "chipsalliance_adams-bridge_pr79", "issue_text": "# Main fsm in adamsbridge_ctrl module never checks if the last msg is sent or dropped in message interface.\n\n- Source URL: https://github.com/chipsalliance/adams-bridge/issues/78\n\nThe msg interface driven by the adamsbridge_ctrl has a valid(msg_valid_o) and ready(msg_rdy_i). The valid signal is asserted when the message is being loaded to the keccak buffer for the length defined by the sequencer. And this interface is flopped by a clk cycle. Now once the last msg which is set(msg_done and there is no hold) the fsm in the ctrl module makes a transition from  `MLDSA_CTRL_MSG_LOAD to   `MLDSA_CTRL_FUNC_START with  valid and valid data but if there is no ready signal incoming from the present clk cycle then the valid stays asserted till the ready is asserted. But the main fsm never checks if this last msg is ever sent to the keccak and advances in the transitions.\n\nPR Title: aligning msg fsm to msg interface better\nStatus: Merged (January 31, 2025)\nAuthor: Nitsirks\nBranch: user/dev/michnorris/msg_fsm_fix → main\n\nDescription:\nThe primary issue addressed: \"state won't transition to function start until the entire message has been sent\"\n\nCommits (5 total):\n1. Initial commit with FSM alignment improvements\n2. Fixed a typo in sample offset values for pk\n3. Merge of main branch\n4. Fixed privatekey read mechanism for keygen process unlock\n5. Automated pipeline timestamp/hash update\n\nReview Activity:\n- mojtaba-bisheh approved the changes (initially January 28, then again January 31 after additional commits)\n- upadhyayulakiran was requested for review but status remains pending\n\nLinked Issues:\nThis PR may close:\n- Issue #83: \"PRIVKEY_OUT read mechanism\"\n- Issue #78: \"Main fsm in adamsbridge_ctrl module never checks if the last msg is sent or dropped\"\n\nRepository: chipsalliance/adams-bridge\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/chipsalliance_adams-bridge_pr79", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/chipsalliance_adams-bridge_pr79.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/chipsalliance_adams-bridge_pr79", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/chipsalliance_adams-bridge_pr79"}
{"instance_id": "chipsalliance_adams-bridge_pr82", "issue_text": "# Update directed KATs with pure MLDSA\n\n- Source URL: https://github.com/chipsalliance/adams-bridge/issues/60\n\nPR Title: updated KATs\nStatus: Merged on January 30, 2025\n\nDescription:\nThe PR description provided only states: \"Updated KAT vectors\"\n\nCommits:\n1. 9c6c65b - \"updated KATs\"\n2. 1119aa7 - \"MICROSOFT AUTOMATED PIPELINE: Stamp 'user/dev/ekarabulut/KAT_uvm_update' with updated timestamp and hash after successful run\"\n\nComments:\nekarabu (Jan 29, 2025): \"Updated KAT vectors\"\nCopilot AI (Jan 30, 2025): Could not review the pull request. Five files with unsupported languages were present, including SystemVerilog sequence files and workflow metadata files.\nmojtaba-bisheh (Jan 30, 2025): Approved the changes\n\nLinked Issues:\n- #60 - \"Update directed KATs with pure MLDSA\" (closed by this PR)\n\nReviewers:\n- mojtaba-bisheh: Approved\n- Nitsirks: Awaiting review\n- upadhyayulakiran: Awaiting review\n- Copilot: Reviewed (unable to process files)\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/chipsalliance_adams-bridge_pr82", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/chipsalliance_adams-bridge_pr82.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/chipsalliance_adams-bridge_pr82", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/chipsalliance_adams-bridge_pr82"}
{"instance_id": "chipsalliance_caliptra-rtl_pr1132", "issue_text": "[2.0] Manu&Prod debug does not grant DMI register access #1129\n\nCaliptra DMI registers are not accessible in Manuf debug and Prod debug security states.\n\nNote: Credit to Nuvoton team for finding this\nThe Caliptra Core JTAG remains locked because the unlock_caliptra_security_state register stays asserted. This causes cptra_security_state_Latched_d.debug_locked and\ncptra_security_state_Latched_f.debug_locked to never reach the required state of both being 0. As a result, the Caliptra Core JTAG cannot be released.\n\nPR Title: [RTL] Fix for security state debug not unlocking after manuf/prod dbg unlock flow patch_v2.1\nPR Number: #1132\nStatus: Merged (November 22, 2025)\n\nDescription:\nThe pull request addresses a bug in the security state capturing logic. According to the author, the change \"removes the else condition from the second flop in the security state capturing logic.\" The static unlock signal was preventing the second register from receiving updated values after completing the debug unlock procedure.\n\nKey Changes:\nThe submission consisted of three commits:\n1. c724a52 - Removed the else term to allow the secondary flop to receive the updated value when manufacturing or production debug unlock is granted\n2. 9e92dc5 - Fixed security state capturing flops for lint by properly observing the reset term\n3. a7d582c - Automated pipeline timestamp and hash update following successful execution\n\nIssue Resolution:\nThis pull request addresses issue #1130, titled \"[2.1] Manu&Prod debug does not grant DMI register access\"\n\nReview & Approval:\n- calebofearth approved the changes on November 22, 2025\n- ekarabu approved the changes on November 22, 2025\n- calebofearth merged the pull request and deleted the feature branch\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/chipsalliance_caliptra-rtl_pr1132", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/chipsalliance_caliptra-rtl_pr1132.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/chipsalliance_caliptra-rtl_pr1132", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/chipsalliance_caliptra-rtl_pr1132"}
{"instance_id": "chipsalliance_caliptra-rtl_pr757", "issue_text": "# [RTL] AXI Sub Arb fix. Add recovery inf synchros. Export trace signals. Move SS dbg unlock reg to pwrgood.\n\nInstance: chipsalliance_caliptra-rtl_pr757\nSource: https://github.com/chipsalliance/caliptra-rtl/pull/757\nFetched: 2026-04-26\nRepository: chipsalliance/caliptra-rtl\nPull request: #757\nAuthor: calebofearth\nState: closed\nBase branch: msft-daily-20250226\nHead branch: cwhitehead-msft-axi-sub-fix\nCreated: 2025-02-26T06:10:12Z\nUpdated: 2025-02-27T07:10:02Z\nClosed: 2025-02-27T07:09:58Z\nMerged: 2025-02-27T07:09:58Z\n\nAXI Sub Arb fix. \r\n* Resolves #753 \r\n\r\nAdd synchronizers to input signals from subsystem recovery interface. \r\nExport RISC-V trace signals for debug.\r\nMove SS dbg unlock level reg to pwrgood so it's sticky and persists across warm resets without having to redo the debug unlock flow.\n\n## Local Reproducer Notes\n\n# chipsalliance_caliptra-rtl_pr757\n\nMinimal fail-to-pass Verilator case for the AXI subordinate arbiter priority fix.\n\nThe buggy arbiter does not keep write priority while a held final write beat is still in progress, allowing a later read to steal the component interface. The patch keeps priority for any in-progress transfer.\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/chipsalliance_caliptra-rtl_pr757", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/chipsalliance_caliptra-rtl_pr757.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/chipsalliance_caliptra-rtl_pr757", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/chipsalliance_caliptra-rtl_pr757"}
{"instance_id": "chipsalliance_caliptra-rtl_pr791", "issue_text": "# Port connection errors in aes_wrap.sv\n\n- Source URL: https://github.com/chipsalliance/caliptra-rtl/issues/766\n\nIn src/aes/rtl/aes_wrap.sv:\nh2d_intg.a_user.data_intg is driven both in line 69 (as part of a struct) and in line 75.\nunused_idle is 1 bit wide but the source, aes.idle_o (line 87), is of type mubi4_t which is 4 bit wide.\n\nPR Title: updating aes file lists to remove aes_wrap\n\nDescription:\nThe pull request removes aes_wrap from file lists because it is a testbench file rather than a production component. This change addresses issue #766, which documented port connection errors in the aes_wrap.sv file.\n\nAuthor: Nitsirks\nStatus: Merged on March 4, 2025\n\nKey Details:\n- Source Branch: user/dev/michnorris/aes_file_fix\n- Target Branch: msft-daily-20250303\n- Commits: 1 commit (86cfe52)\n- Reviewer Approval: Mojtaba Bisheh approved the changes\n\nRelated Issue:\nIssue #766 titled \"Port connection errors in aes_wrap.sv\" was addressed and closed by this pull request.\n\nComments:\nNitsirks provided a concise explanation: \"aes wrap is a tb file, removing from file lists fixes issue 766\"\n\nThe change was straightforward—removing a testbench file from production file lists to prevent configuration errors and streamline the build process.\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/chipsalliance_caliptra-rtl_pr791", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/chipsalliance_caliptra-rtl_pr791.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/chipsalliance_caliptra-rtl_pr791", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/chipsalliance_caliptra-rtl_pr791"}
{"instance_id": "chipsalliance_caliptra-rtl_pr883", "issue_text": "# caliptra_prim_macros.svh not found in caliptra_rtl directory\n\n- Source URL: https://github.com/chipsalliance/caliptra-rtl/issues/867\n\nHi Team,\n\nIn the RTL, there's an include for caliptra_prim_macros.svh,\nbut I wasn't able to find this file anywhere in the caliptra_rtl directory.\n\nCould you please let me know where this file is located or how I can obtain it?\n\n![Image](https://github.com/user-attachments/assets/556005c7-f51d-4f1b-961f-4e744c93f9b3)\n\nPR Title: [RTL] GitHub Issues fixes #883\nStatus: Merged on May 30, 2025\n\nDescription:\nThis PR addresses multiple GitHub issues by:\n- Changing INC_ASSERT to CALIPTRA_INC_ASSERT across RTL files\n- Adding ifndef SYNTHESIS guard in axi_if.sv to exclude simulation tasks from synthesis\n- Adding keyvault package dependencies to configuration files\n- Regenerating and updating file lists\n\nKey Changes:\nThe contributor updated assertion macros for consistency, modified compilation directives for tool-agnostic synthesis guards (initially XCELIUM-specific, later generalized to SYNTHESIS), and added missing macro definitions like CALIPTRA_WITHIN_MARGIN.\n\nReview Process:\nCopilot AI noted concerns about macro inconsistencies: \"The change in the assertion guard macro is inconsistent with other files that use CALIPTRA_INC_ASSERT\" and questioned whether SYNTHESIS was the correct condition for task compilation control.\n\nnileshbpat raised similar points about macro usage consistency.\n\nclayton8 approved after addressing concerns, confirming corrections to macro definitions and placements.\n\nupadhyayulakiran approved the final version.\n\nRelated Issues Closed:\n- Issue #811: Simulation tasks conflict with caliptra-ss RTL\n- Issue #867: Missing caliptra_prim_macros.svh file\n- Issue #888: Tasks incompatible with emulators\n\nParticipants: 6 contributors including anjpar (author), clayton8, upadhyayulakiran, nileshbpat, bharatpillilli (merger), and Copilot AI reviewer.\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/chipsalliance_caliptra-rtl_pr883", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/chipsalliance_caliptra-rtl_pr883.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/chipsalliance_caliptra-rtl_pr883", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/chipsalliance_caliptra-rtl_pr883"}
{"instance_id": "chipsalliance_caliptra-rtl_pr919", "issue_text": "# Simulation tasks in src/axi/rtl/axi_if.sv lines 167-399 conflict with caliptra-ss RTL in lc_ctrl.sv and otp_ctrl.sv\n\n- Source URL: https://github.com/chipsalliance/caliptra-rtl/issues/811\n\nWhen trying to compile caliptra-ss using Cadence Xcelium, there are conflicts between the axi_if simulation tasks (lines 167-399) and functional RTL.\n\nExample error (paths are relative to caliptra-ss top):\nxmelab: *E,ICDPAV (src/lc_ctrl/rtl/lc_ctrl.sv,201|28): Illegal combination of driver and procedural assignment to variable araddr detected (procedural assignment found in task/function rst_mgr at line 177 in file third_party/caliptra-rtl/src/axi/rtl/axi_if.sv).\n\nPR Title: [VAL] Add XCELIUM ifdef to resolve conflict of functional RTL and sim tasks\nPR Number: #919\nStatus: Merged\nAuthor: calebofearth\nMerge Date: July 11, 2025\n\nDescription:\nThis PR replaces #916 to allow running the full pipeline check and resolves issue #811. The change addresses a conflict between simulation tasks in the AXI interface and Caliptra-SS RTL modules.\n\nKey Details:\nRelated Issue: #811 - \"Simulation tasks in src/axi/rtl/axi_if.sv lines 167-399 conflict with caliptra-ss RTL\"\n\nCommits:\n1. Add define to resolve conflict of functional RTL and simulation tasks in Xcelium\n2. Microsoft automated pipeline timestamp and hash update\n\nReviewers & Approvals:\n- upadhyayulakiran (approved July 11)\n- nileshbpat (approved July 11)\n\nTest Status: 77 checks passed\n\nNotable Activity:\nThe PR underwent force-pushes and branch updates before final approval. Initial reviews from both approvers were dismissed on July 10, then re-requested July 11 after updates. The branch `assaf-nt-axi-if-tasks` was deleted following successful merge.\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/chipsalliance_caliptra-rtl_pr919", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/chipsalliance_caliptra-rtl_pr919.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/chipsalliance_caliptra-rtl_pr919", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/chipsalliance_caliptra-rtl_pr919"}
{"instance_id": "chipsalliance_caliptra-rtl_pr921", "issue_text": "# ECC pubkey check in ECDH\n\n- Source URL: https://github.com/chipsalliance/caliptra-rtl/issues/917\n\nIn the ECDH feature, ecc_dsa_ctrl we check if the input publickey is on the curve but the flag which is set when publickey is valid is not used for any external output indicating the publickey is valid or invalid. Ideally, I expect an error in this whereas the error_flag is not set in this case.\n\n[This line](https://github.com/chipsalliance/caliptra-rtl/blob/3964d76133a48befb0a192501e6f75b290e2d84e/src/ecc/rtl/ecc_dsa_ctrl.sv#L674) needs to be updated to validate pubkey in both verifying and ECDH flow.\n\nPR Title: [RTL/VAL] Fix ECDH pubkey check\nStatus: Merged on July 14, 2025\n\nDescription:\nThe PR addresses a bug in the ECDH feature where the ecc_dsa_ctrl block performs internal validation of input public keys to verify they lie on the curve. The update ensures that invalid public keys properly trigger error conditions rather than proceeding silently.\n\nRelated Issue: #917 - \"ECC pubkey check in ECDH\"\n\nKey Changes:\n- Fixed ECDH public key validation logic\n- Updated ECC test coverage\n- Includes automated pipeline stamps with updated timestamps\n\nReview & Approval:\nReviewers:\n- Nitsirks (approved)\n- calebofearth (approved and merged)\n\nParticipants: mojtaba-bisheh, calebofearth, Nitsirks\n\nCommits (6 total):\nNotable commits include:\n- \"fixed ECDH pbkey check\"\n- \"updated ecc coverage\"\n- Merge commits integrating main branch updates\n- Automated pipeline validation stamps\n\nThe pull request successfully passed 78 checks before merging.\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/chipsalliance_caliptra-rtl_pr921", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/chipsalliance_caliptra-rtl_pr921.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/chipsalliance_caliptra-rtl_pr921", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/chipsalliance_caliptra-rtl_pr921"}
{"instance_id": "chipsalliance_caliptra-rtl_pr963", "issue_text": "# Undefined macros in AES due to missing includes\n\n- Source URL: https://github.com/chipsalliance/caliptra-rtl/issues/977\n\nOn the 2.1 SS FPGA I hack aes_clp_wrapper.sv to include caliptra_reg_field_defines.svh and kv_macros.svh to avoid undefined macro errors. kv_macros.svh gets included from several of the crypto components like ecc, hmac, and sha512 but not for aes. caliptra_reg_field_defines.svh is included mostly from testbenches and soc_ifc.\nThe workaround for kv_macros.svh is also being used in the 2.0 FPGA.\nMy ask is that we consider if these includes should be added to AES.\n\nError requiring caliptra_reg_field_defines.svh:\n```\nERROR: [Synth 8-10157] use of undefined macro 'AES_REG_DATA_IN_0' [/fourtb/jlmahowa/caliptra-mcu-sw-lock/hw/fpga/caliptra_build/caliptra_fpga_project.gen/sources_1/bd/caliptra_fpga_project_bd/ipshared/25c5/src/aes_clp_wrapper.sv:190]\n```\nError requiring kv_macros.svh:\n```\nERROR: [Synth 8-10157] use of undefined macro 'CALIPTRA_KV_READ_CTRL_REG2STRUCT' [/fourtb/jlmahowa/caliptra-mcu-sw-lock/hw/fpga/caliptra_build/caliptra_fpga_project.gen/sources_1/bd/caliptra_fpga_project_bd/ipshared/978d/src/aes_clp_wrapper.sv:401]\n\nERROR: [Synth 8-10157] use of undefined macro 'CALIPTRA_KV_WRITE_CTRL_REG2STRUCT' [/fourtb/jlmahowa/caliptra-mcu-sw-lock/hw/fpga/caliptra_build/caliptra_fpga_project.gen/sources_1/bd/caliptra_fpga_project_bd/ipshared/978d/src/aes_clp_wrapper.sv:402]```\n\nPR Title: [RTL] Update KeyVault error flagging conditions and AES key manager reg stage\nPR Number: #963\nRepository: chipsalliance/caliptra-rtl\nStatus: Merged (Aug 27, 2025)\nBase Branch: msft-daily-20250827\n\nDescription:\nThe pull request addresses three main objectives:\n1. KeyVault Error Status Management: Modified KeyVault clients to \"latch and preserve error status on kv access instead of using the status from the final beat of the transfer\"\n2. AES Key Zeroization: Updated the AES Caliptra wrapper to \"clear (with zeroes) the intermediate key registering stage when reading a new key from keyvault\"\n3. Header File Inclusion: Added necessary header files to aes_clp_wrapper to resolve issue #977 regarding undefined macros\n\nVerification Approach:\nThe implementation includes:\n- Test cases validating KeyVault client reads with operation interrupts\n- Test assertions for AES zeroization of buffered key values\n- Directed tests for read error recovery scenarios\n\nContributors:\n- calebofearth (primary contributor)\n- Nitsirks (Michael Norris - co-author)\n- bharatpillilli (reviewer)\n\nReview Status:\nSuccessfully approved by both reviewers with 131 of 133 checks passing.\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/chipsalliance_caliptra-rtl_pr963", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/chipsalliance_caliptra-rtl_pr963.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/chipsalliance_caliptra-rtl_pr963", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/chipsalliance_caliptra-rtl_pr963"}
{"instance_id": "chipsalliance_caliptra-ss_pr550", "issue_text": "# MCU ROM\n\n- Source URL: https://github.com/chipsalliance/caliptra-ss/issues/533\n\nwhy does the MCU ROM has an AXI wr interface (rom is not wettable...)\n\nPR Title: [DOC][VAL] Disconnect MCU ROM wr path in TB; clarify MCU ROM if connection req and SRAM error handling sections\nPR Number: #550\nStatus: Merged\nMerge Date: June 26, 2025\nMerged By: calebofearth\nBranch: cwhitehead-msft-spec-upd-err-handle → main\n\nDescription:\nThe pull request addresses two related issues:\n- chipsalliance/Caliptra#320\n- caliptra-ss#533 (MCU ROM)\n\nThe changes involve documentation and validation updates focused on modifying MCU ROM write path connectivity in testbenches, clarifying MCU ROM connection requirements, and refining SRAM error handling documentation sections.\n\nKey Commits (15 total):\nNotable changes include:\n- Fixed typo in SS port naming\n- Updated memory export interface table and documentation\n- Added example register map pages link to README\n- Revised SRAM error/recovery flow section with clarifications\n- Updated ROM interface connectivity requirements with write path disabled\n- Disconnected write-path for MCU ROM\n- Renamed SRAM error handling section to emphasize example-only flow\n- Reduced unnecessary verbiage in error handling specifications\n- Regenerated table of contents\n\nReviews & Approvals:\n- bharatpillilli: Approved changes (with prior comment thread)\n- Nitsirks: Approved changes\n\nParticipants: 3 (calebofearth, bharatpillilli, Nitsirks)\n\nTechnical Details:\nAll 8 checks passed successfully before merge.\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/chipsalliance_caliptra-ss_pr550", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/chipsalliance_caliptra-ss_pr550.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/chipsalliance_caliptra-ss_pr550", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/chipsalliance_caliptra-ss_pr550"}
{"instance_id": "chipsalliance_caliptra-ss_pr565", "issue_text": "# VCS Error in testbench file fc_lcc_tb_services\n\n- Source URL: https://github.com/chipsalliance/caliptra-ss/issues/484\n\nIn the file caliptra_ss/src/integration/testbench/fc_lcc_tb_services.sv on line 34 is the statement\n\nlogic lcc_external_clk_req = 1'b0;\n\nThis signal is also used in an always block with non-blocking statements. It is also initialized there with the negedge of reset. For a least our version of VCS this is causing an error. To fix this require removing the initialization in the logic statement.\n\nlogic lcc_external_clk_req;\n\nPR Title: Coverage updates and fixed gh484\nStatus: Merged (July 3, 2025)\nAuthor: nileshbpat\nBranch: pateln_fix_gh484 → main\n\nDescription:\nThe PR addressed two main objectives:\n1. Updated coverage documentation - Refreshed links to coverage reports and added analysis notes from the latest coverage report findings.\n2. Fixed Issue #484 - Resolved a VCS error that was occurring in the testbench file fc_lcc_tb_services, specifically a \"multiple driver issue.\"\n\nCommits (4 total):\n- Resolved multiple driver issue\n- Updated Coverage links\n- Added Coverage Analysis notes and links from latest coverage reports\n- Microsoft automated pipeline timestamp/hash stamp\n\nReviews & Approvals:\nbharatpillilli approved the changes after reviewing the documentation updates.\ncalebofearth previously approved but the review was dismissed after subsequent commits.\n\nRelated Issue:\nThis PR successfully closes: \"VCS Error in testbench file fc_lcc_tb_services #484\"\n\nDownstream Impact:\nThis PR was later incorporated into larger feature merges, including PR #597 (\"MCI-LCC Updates with VolatileLock and Debug Connection\").\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/chipsalliance_caliptra-ss_pr565", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/chipsalliance_caliptra-ss_pr565.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/chipsalliance_caliptra-ss_pr565", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/chipsalliance_caliptra-ss_pr565"}
{"instance_id": "chipsalliance_caliptra-ss_pr590", "issue_text": "# Using axi wdata without wvalid qualification in TLUL\n\n- Source URL: https://github.com/chipsalliance/caliptra-ss/issues/535\n\nHi Caliptra team,\n        In Caliptra SS simulation, we encounter X value issue. By tracing the code, we found that there could be an issue  in the RTL code: caliptra-ss-main/src/tlul/rtl/tlul_cmd_ingt_chk.sv ( line 44 ).\n\n\n![Image](https://github.com/user-attachments/assets/c0ae44cc-8335-4501-8b44-e8aec0334985)\n\nThe issue is using \"data_err\" without checking qualification of AXI wvalid. \"tl_i.a_valid\" is from AXI awvalid or arvalid, but \"data_err\" is from AXI wdata, so there could be scenerio when AXI arvalid == 1, but wvalid == 0, wdata is unknown.\n\n\n        Could you help to check whether this is a real issue ?\n\n\nBest Regards\nDerek Wang\n\nPR Title: [BUG FIX] Drive a_data with zeroes for reads instead of wdata, which may be arbitrary\nPR Number: #590\nStatus: Merged\nMerged by: nileshbpat on July 23, 2025\n\nDescription:\nThe PR resolves issue #535 regarding improper handling of write data signals during read operations. The submitter notes this bug \"remain undetected so far as avery interconnect VIP drives zero instead of x for the undriven IOs.\"\n\nCommits (7 total):\n1. Drive 0 wdata for read commands\n2. Match the conditional assignment convention elsewhere in file\n3. Fix a force statement on sub2tlul wdata signal so it's not always driven\n4. Use more precise reg addr\n5. Actually fail the test when an error is observed\n6. Use a local a_data signal to allow TB to inject ECC errors at TL a_data\n7. MICROSOFT AUTOMATED PIPELINE: Stamp 'cwhitehead-msft-tlul-X-fix' with updated timestamp and hash after successful run\n\nReview & Approval:\nReviewer: upadhyayulakiran approved the changes on July 23, 2025\n\nLinked Issue:\nTitle: Using axi wdata without wvalid qualification in TLUL (Issue #535)\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/chipsalliance_caliptra-ss_pr590", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/chipsalliance_caliptra-ss_pr590.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/chipsalliance_caliptra-ss_pr590", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/chipsalliance_caliptra-ss_pr590"}
{"instance_id": "chipsalliance_caliptra-ss_pr750", "issue_text": "# [Val] FC Test uses local register definitions\n\n- Source URL: https://github.com/chipsalliance/caliptra-ss/issues/703\n\nUpdate this test such that each fuse map update does not break its structure.\n\nsrc/integration/test_suites/caliptra_ss_fuse_ctrl_read_lock/caliptra_ss_fuse_ctrl_read_lock.c\n\n\n<img width=\"712\" height=\"425\" alt=\"Image\" src=\"https://github.com/user-attachments/assets/2a3b720d-f6ab-4208-bb22-3628aac40b72\" />\n\n\nThere are similar issues in these tests too:\n\nsrc/integration/test_suites/caliptra_ss_fuse_ctrl_test_unlocked0_prov/caliptra_ss_fuse_ctrl_test_unlocked0_prov.c\nsrc/integration/test_suites/caliptra_ss_fuse_ctrl_manuf_prod_prov/caliptra_ss_fuse_ctrl_manuf_prod_prov.c\n\nThis test uses hard-coded fuse map address to separate UDS and FE from the other partitions. See the if condition with 0x40 and 0xD0\n\nPR Title: [fuse_ctrl,dv] Assorted cleanups to how FC tests look at magic registers\nPR Number: #750\nStatus: Merged\n\nDescription:\nThe author, rswarbrick, created this PR while tidying up related work in PR #727. The changes were deemed \"safe to apply separately\" despite uncertainty about the correctness of some modifications in the parent PR.\n\nCommits (5 total):\n1. Create fuse_ctrl_mmap.c - Prevents fuse_ctrl_mmap.h from defining instantiated objects that would cause linker failures when included in multiple compilation units.\n2. Add documentation for address range type - No functional changes; improves clarity of address range logic in the package.\n3. Tidy up tests for Caliptra secret addresses - Updates outdated values in caliptra_ss_fuse_ctrl_manuf_prod_prov from a prior change (275521b1) and applies consistent magic number sourcing to related tests.\n4. Avoid hard-coding read lock partitions - Removes hard-coded partition values by generating a template-based map that pulls actual addresses from soc_mmap.h at compile time.\n5. Automated pipeline stamp - Microsoft's automated pipeline updated timestamp and hash after successful test run.\n\nReview Activity:\nandreaskurth approved with comment: \"LGTM, thanks for fixing these tests\" (later re-approved after pipeline completion).\nekarabu merged the PR on September 30, 2025.\n\nLinked Issue:\nThis PR may close issue #703: \"[Val] FC Test uses local register definitions\"\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/chipsalliance_caliptra-ss_pr750", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/chipsalliance_caliptra-ss_pr750.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/chipsalliance_caliptra-ss_pr750", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/chipsalliance_caliptra-ss_pr750"}
{"instance_id": "chipsalliance_caliptra-ss_pr838", "issue_text": "# [Question] Regarding FcAxiFilterDaiAccessError_A assertion\n\n- Source URL: https://github.com/chipsalliance/caliptra-ss/issues/833\n\nHello calipra team,\n\nI have found FcAxiFilterDaiAccessError_A assertion error during caliptra_ss_fuse_ctrl_axi_id test when a valid write follows a discard write.\n\nhttps://github.com/chipsalliance/caliptra-ss/blob/28ef1cefb5bfcf22e258419cd5db8f836527042f/src/integration/asserts/caliptra_ss_top_sva.sv#L75-L78\n\nI think that discard_fuse_write signal remains asserted for two more cycles after otp_operation_done toggles, so the assertion impacts on the next valid write as well.\nTherefore, I’ve just tried it as below.\nI’d appreciate your feedback on these changes.\n\n  ```\n`CALIPTRA_ASSERT(FcAxiFilterDaiAccessError_A,\n                 dai_write_req ##1       // <=== add\n                 `FC_PATH.discard_fuse_write ##1\n                 `FC_PATH.otp_operation_done[->1] |=>\n                 `FC_PATH.u_otp_ctrl_dai.error_o == {AccessError})\n\n```\nRegards,\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/chipsalliance_caliptra-ss_pr838", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/chipsalliance_caliptra-ss_pr838.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/chipsalliance_caliptra-ss_pr838", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/chipsalliance_caliptra-ss_pr838"}
{"instance_id": "chipsalliance_i3c-core_pr35", "issue_text": "# Reading the TTI RX_DESC_QUEUE_PORT when there is no descriptor in the queue seems to crash\n\n- Source URL: https://github.com/chipsalliance/i3c-core/issues/32\n\nOn the FPGA, this will hard crash the host when trying to read that register if the interrupt has not been set.\n\n\n\n\n\n\n\n\n\n\n\n# GitHub Issue #32\n\n## Issue Title\nReading the TTI RX_DESC_QUEUE_PORT when there is no descriptor in the queue seems to crash\n\n## Issue Description\n\"On the FPGA, this will hard crash the host when trying to read that register if the interrupt has not been set.\"\n\n## Author\nswenson\n\n## Status\nClosed (linked to PR #35)\n\n## Additional Details\n- No assignees\n- No labels or type classification\n- Opened on April 2, 2025\n- No comments visible in the provided content\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/chipsalliance_i3c-core_pr35", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/chipsalliance_i3c-core_pr35.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/chipsalliance_i3c-core_pr35", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/chipsalliance_i3c-core_pr35"}
{"instance_id": "chipsalliance_sv-tests_pr7781", "issue_text": "# Foreach test is not synthesizable\n\n- Source URL: https://github.com/chipsalliance/sv-tests/issues/7780\n\nThe test case used for the `foreach` construct is non-synt.\n\nA new synthesizable testcase is needed to validate if the construct is correctly recognized in synth-only software\n\n/assign me\n\n\n\n\n\n\n\n# GitHub Issue #7780: Foreach test is not synthesizable\n\n## Author\n@matlupi (opened November 4, 2025)\n\n## Issue Description\n\"The test case used for the `foreach` construct is non-synt. A new synthesizable testcase is needed to validate if the construct is correctly recognized in synth-only software\"\n\nThe reporter assigned the issue to themselves.\n\n## Related PR\nPR #7781 was opened to address this issue.\n\n## Summary\nThis issue identifies that the existing `foreach` test in the sv-tests repository lacks synthesizability. The requester is seeking a replacement test case that can be properly validated by synthesis-focused tools and software.\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/chipsalliance_sv-tests_pr7781", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/chipsalliance_sv-tests_pr7781.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/chipsalliance_sv-tests_pr7781", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/chipsalliance_sv-tests_pr7781"}
{"instance_id": "darklife_darkriscv_pr95", "issue_text": "# Add cycle and instret counters (\"Zicntr\" extension)\n\n- Source URL: https://github.com/darklife/darkriscv/issues/94\n\nHello,\n\nThe ISA suggests it should be implemented, as it serves basic performance analysis. I need it too for Dhrystone benchmark.\nI can see that clocks and instructions are being counted with `__PERFMETER__` enabled. Why not make them accessible via CSRs?\n\n\n\n\n\n\n\n# GitHub Issue #94: Add cycle and instret counters (\"Zicntr\" extension)\n\n## Issue Body\nThe reporter notes that the RISC-V ISA suggests implementing cycle and instruction counters for basic performance analysis. They mention that clock and instruction counting already exist when `__PERFMETER__` is enabled, but these metrics should be made accessible through Control and Status Registers (CSRs). The requester needs this functionality for Dhrystone benchmark testing.\n\n## Status\nClosed (with associated PR #95)\n\n## Assignees\nsamsoniuk, MrJake222\n\n## Notes\nThe webpage content provided does not include visible comments from other users or additional linked issue details beyond the issue title and description shown.\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/darklife_darkriscv_pr95", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/darklife_darkriscv_pr95.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/darklife_darkriscv_pr95", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/darklife_darkriscv_pr95"}
{"instance_id": "dawsonjon_fpu_pr16", "issue_text": "# Fix sign bug\n\nInstance: dawsonjon_fpu_pr16\nSource: https://github.com/dawsonjon/fpu/pull/16\nFetched: 2026-04-26\nRepository: dawsonjon/fpu\nPull request: #16\nAuthor: andreast271\nState: closed\nBase branch: master\nHead branch: master\nCreated: 2019-01-21T16:34:51Z\nUpdated: 2019-01-21T18:26:12Z\nClosed: 2019-01-21T18:26:12Z\nMerged: 2019-01-21T18:26:12Z\n\nThe result of -a + a should be +0 (positive zero). Without this fix, the module returns -0 (negative zero).\n\n# PR #16: Fix sign bug\n\n## Title\nFix sign bug\n\n## Description\nThe result of -a + a should be +0 (positive zero). Without this fix, the module returns -0 (negative zero).\n\n## Comment by andreast271 (Jan 21, 2019)\n\"The result of -a + a should be +0 (positive zero). Without this fix, the module returns -0 (negative zero).\"\n\n## Merge Status\nMerged by dawsonjon on Jan 21, 2019\n\n## Commit\nc75ffcf92183c1777e84a87170e6759eaff70d17\n\nNo linked issues or additional comments were present in the pull request.\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/dawsonjon_fpu_pr16", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/dawsonjon_fpu_pr16.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/dawsonjon_fpu_pr16", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/dawsonjon_fpu_pr16"}
{"instance_id": "efabless_clear_pr20", "issue_text": "# Cocotb updates\n\nInstance: efabless_clear_pr20\nSource: https://github.com/efabless/clear/pull/20\nFetched: 2026-04-26\nRepository: efabless/clear\nPull request: #20\nAuthor: M0stafaRady\nState: closed\nBase branch: RTL-dev\nHead branch: cocotb-dev\nCreated: 2023-04-05T10:01:26Z\nUpdated: 2023-04-05T10:01:43Z\nClosed: 2023-04-05T10:01:43Z\nMerged: 2023-04-05T10:01:43Z\n\n- Develop script to get the hierarchy of the programming chain \r\n- Add test for counter\n\n## Local Reproducer Notes\n\nefabless/clear PR 20 reproducer.\n\nThe reduced RTL keeps the GPIO power-on macro touched by the PR and exposes\nthe decoded GPIO 3 pull configuration as signals.  The buggy snapshot powers\nGPIO 3 up with the management pulldown setting; the patch changes it to the\nmanagement pullup setting expected by the cocotb update.\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/efabless_clear_pr20", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/efabless_clear_pr20.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/efabless_clear_pr20", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/efabless_clear_pr20"}
{"instance_id": "esa-tu-darmstadt_tapasco_pr105", "issue_text": "Don't choke on patched Vivado versions #48\n\nCurrently, when using a patched Vivado version, Tapasco fails at least at two places:\n\nCould not find /scratch/mio/tapasco_f1/common/common_2018.2_AR71715.tcl, Vivado 2018.2_AR71715 is not supported yet!\n\nWhile this can easily be resolved by placing a symlink to the common_2018.2.tcl file, there is also a problem with the tapasco_status.json which causes Tapasco (or rather the JSON Parser) to throw an Exception and exit:\n\n   \"Versions\"              : [{\n        \"Software\" : \"Vivado\",\n        \"Year\"     : 2018_AR71715,\n        \"Release\"  : 2_AR71715\nResults in:\n\ncom.fasterxml.jackson.core.JsonParseException: Unexpected character ('_' (code 95))\n\n\n# Pull Request #105 Summary\n\n## PR Title\nReplace hard coded status core with dynamic version\n\n## PR Description\n- Replaces the custom, hard-coded status core format with a protobuf version\n- Enables easily adding information to the status core for use by runtime and driver\n- Adds necessary dependencies\n- Uses custom statically-linked rust executable to translate JSON from TaPaSCo flow to protobuf binary\n- Fixes all examples and tests them\n- Makes memory map from user space completely platform independent; driver translates virtual to device-specific addresses\n- Closes issue #48: \"Don't choke on patched Vivado versions\"\n- Closes issue #83: \"Replace custom status core format with something well known\"\n\n## Key Comments\n- cahz (approver): \"Tested with local memory, looks good to me.\"\n- m-ober (reviewer): Left review comments on file `runtime/kernel/dma/blue_dma.c`\n\n## Commits\n36 commits across the feature branch, including work on FlatBuffers conversion, protobuf implementation, driver modifications, and platform-independence improvements.\n\n## Status\nMerged on July 5, 2019\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/esa-tu-darmstadt_tapasco_pr105", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/esa-tu-darmstadt_tapasco_pr105.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/esa-tu-darmstadt_tapasco_pr105", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/esa-tu-darmstadt_tapasco_pr105"}
{"instance_id": "esa-tu-darmstadt_tapasco_pr186", "issue_text": "# HBM Adressing\n\n- Source URL: https://github.com/esa-tu-darmstadt/tapasco/issues/180\n\nWhen connecting multiple PEs to the HBM, only one can correctly access it's HBM memory block.\nThis is because the adresses of the HBM blocks do not all start at 0. Instead all HBM blocks together form a continous address space.\nTaPaSCo should automatically offset the addresses of each PE to the address range of the HBM block it is connected to. Then the address space the PEs \"see\" always starts at 0.\n\n\n\n\n\n\n\n\n\n\n# GitHub Issue #180: HBM Addressing\n\n## Issue Title\nHBM Adressing #180\n\n## Issue Status\nClosed (via PR #186)\n\n## Assigned to\nwirthjohannes\n\n## Labels\nbug\n\n## Milestone\n2020.4\n\n## Issue Description\nThe issue describes a problem with multiple Processing Elements (PEs) connected to HBM memory. When several PEs connect to the same HBM, only one PE can correctly access its memory block because:\n\n> \"the adresses of the HBM blocks do not all start at 0. Instead all HBM blocks together form a continous address space\"\n\nProposed Solution: TaPaSCo should automatically offset addresses for each PE to match the address range of its connected HBM block, ensuring each PE's address space starts at 0.\n\n## Key Details\n- Created: April 28, 2020\n- Repository: esa-tu-darmstadt/tapasco\n- Categorized as a bug (\"Something isn't working\")\n\nNote: No pull request description, comments, or additional linked issues were provided in the source content.\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/esa-tu-darmstadt_tapasco_pr186", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/esa-tu-darmstadt_tapasco_pr186.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/esa-tu-darmstadt_tapasco_pr186", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/esa-tu-darmstadt_tapasco_pr186"}
{"instance_id": "gtaylormb_opl3_fpga_pr51", "issue_text": "# Linting for boosting RTL quality and QA consistency\n\n- Source URL: https://github.com/gtaylormb/opl3_fpga/issues/48\n\n## Issue Title\nLinting for boosting RTL quality and QA consistency\n\n## Issue Description\nThe issue body referenced a related discussion from the openCologne project (https://github.com/chili-chips-ba/openCologne/issues/16). The issue is focused on implementing linting tools and processes to improve the quality and consistency of the RTL (Register Transfer Level) code within this FPGA design project.\n\n## Issue Comments\nNone visible.\n\n## Issue Metadata\n- Status: Closed (resolved via PR #51)\n- Author: chili-chips-ba\n- Created: June 12, 2024\n- Assignees: None\n- Labels: None\n- Milestone: None\n\n## Linked Issues / PRs\n- PR #51 — resolves this issue\n- Related discussion: openCologne #16\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/gtaylormb_opl3_fpga_pr51", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/gtaylormb_opl3_fpga_pr51.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/gtaylormb_opl3_fpga_pr51", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/gtaylormb_opl3_fpga_pr51"}
{"instance_id": "hdl-util_hdmi_pr12", "issue_text": "# Source tweaks for clean compilation on Verilator\n\nInstance: hdl-util_hdmi_pr12\nSource: https://github.com/hdl-util/hdmi/pull/12\nFetched: 2026-04-26\nRepository: hdl-util/hdmi\nPull request: #12\nAuthor: jamesbowman\nState: closed\nBase branch: master\nHead branch: master\nCreated: 2020-07-17T20:58:39Z\nUpdated: 2020-07-18T01:06:15Z\nClosed: 2020-07-18T01:06:15Z\nMerged: 2020-07-18T01:06:15Z\n\nHi Sameer, I'm working on a verification testbench for your HDMI code base.\r\nThis first commit makes some small syntax changes to get to clean build with Verilator and Icarus Verilog.\r\n\r\nThe next steps are:\r\n * a testbench that dumps the 3 x 10 bit TMDS values for N clocks\r\n * a stream analyzer that verifies HDMI against the spec and the settings\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/hdl-util_hdmi_pr12", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/hdl-util_hdmi_pr12.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/hdl-util_hdmi_pr12", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/hdl-util_hdmi_pr12"}
{"instance_id": "hdl-util_hdmi_pr15", "issue_text": "# add format 34 (1080p30)\n\nInstance: hdl-util_hdmi_pr15\nSource: https://github.com/hdl-util/hdmi/pull/15\nFetched: 2026-04-26\nRepository: hdl-util/hdmi\nPull request: #15\nAuthor: sameer\nState: closed\nBase branch: master\nHead branch: 1080p30\nCreated: 2021-02-06T23:53:38Z\nUpdated: 2021-02-06T23:57:06Z\nClosed: 2021-02-06T23:57:03Z\nMerged: 2021-02-06T23:57:03Z\n\n## PR Title\nadd format 34 (1080p30)\n\n## PR Description\nDerived from contributions by @nockieboy and BrianHG https://www.eevblog.com/forum/fpga/hdmi-dvi-encoder-with-audio-smart-quartus-pll-integration-in-systemverilog/\n\n## PR Comments\n\n**sameer** (Feb 6, 2021):\n\"Derived from contributions by @nockieboy and BrianHG https://www.eevblog.com/forum/fpga/hdmi-dvi-encoder-with-audio-smart-quartus-pll-integration-in-systemverilog/\"\n\n## PR Metadata\n- Status: Merged\n- Merge commit: 2a35976\n- Branch deleted after merge: 1080p30\n- Reviewers: None\n- Assignees: None\n- Labels: None\n\n## Linked Issues\nNo linked issues are referenced in this pull request.\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/hdl-util_hdmi_pr15", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/hdl-util_hdmi_pr15.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/hdl-util_hdmi_pr15", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/hdl-util_hdmi_pr15"}
{"instance_id": "hdl-util_hdmi_pr16", "issue_text": "# Switch to GH action\n\nInstance: hdl-util_hdmi_pr16\nSource: https://github.com/hdl-util/hdmi/pull/16\nFetched: 2026-04-26\nRepository: hdl-util/hdmi\nPull request: #16\nAuthor: sameer\nState: closed\nBase branch: master\nHead branch: github-action\nCreated: 2021-02-07T00:33:51Z\nUpdated: 2021-02-07T01:23:04Z\nClosed: 2021-02-07T01:23:01Z\nMerged: 2021-02-07T01:23:01Z\n\n## PR Title\nSwitch to GH action\n\n## PR Description\nNo description provided.\n\n## PR Comments\nNo substantive comments were recorded in the conversation thread beyond the automated merge notification.\n\n## PR Metadata\n- Status: Merged\n- Author force-pushed the github-action branch multiple times before merging\n- Purpose: transition the project's CI/CD infrastructure from Travis CI to GitHub Actions and update ModelSim dependencies\n- Branch deleted after merge: github-action\n\n## Linked Issues\nNo linked issues are referenced in this pull request.\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/hdl-util_hdmi_pr16", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/hdl-util_hdmi_pr16.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/hdl-util_hdmi_pr16", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/hdl-util_hdmi_pr16"}
{"instance_id": "hdl-util_hdmi_pr20", "issue_text": "# Xilinx support on master branch\n\nInstance: hdl-util_hdmi_pr20\nSource: https://github.com/hdl-util/hdmi/pull/20\nFetched: 2026-04-26\nRepository: hdl-util/hdmi\nPull request: #20\nAuthor: sameer\nState: closed\nBase branch: master\nHead branch: oserdes2\nCreated: 2021-02-28T04:03:44Z\nUpdated: 2021-02-28T04:04:23Z\nClosed: 2021-02-28T04:04:20Z\nMerged: 2021-02-28T04:04:20Z\n\nAdding support as tested with a series 7 fpga (SEA board)\r\n\r\nreorganizing the video formats and adding 4k30fps\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/hdl-util_hdmi_pr20", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/hdl-util_hdmi_pr20.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/hdl-util_hdmi_pr20", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/hdl-util_hdmi_pr20"}
{"instance_id": "hdl-util_hdmi_pr21", "issue_text": "# move screen to upper left corner in frame\n\nInstance: hdl-util_hdmi_pr21\nSource: https://github.com/hdl-util/hdmi/pull/21\nFetched: 2026-04-26\nRepository: hdl-util/hdmi\nPull request: #21\nAuthor: sameer\nState: closed\nBase branch: master\nHead branch: origin_is_screen_origin\nCreated: 2021-03-06T05:28:53Z\nUpdated: 2021-03-07T16:55:16Z\nClosed: 2021-03-07T16:55:13Z\nMerged: 2021-03-07T16:55:13Z\n\n## PR Title\nmove screen to upper left corner in frame\n\n## PR Description\nthis way, origin = screen origin\n\n## PR Comments\n\n**sameer** (Mar 6, 2021):\n\"this way, origin = screen origin\"\n\n## PR Metadata\n- Status: Merged\n- Commit: c003eba\n- Reviewers: None\n- Assignees: None\n- Labels: None\n- Branch deleted after merge: origin_is_screen_origin\n\n## Linked Issues\nNo linked issues are referenced in this pull request.\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/hdl-util_hdmi_pr21", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/hdl-util_hdmi_pr21.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/hdl-util_hdmi_pr21", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/hdl-util_hdmi_pr21"}
{"instance_id": "hdl-util_hdmi_pr22", "issue_text": "# support synchronous reset\n\nInstance: hdl-util_hdmi_pr22\nSource: https://github.com/hdl-util/hdmi/pull/22\nFetched: 2026-04-26\nRepository: hdl-util/hdmi\nPull request: #22\nAuthor: sameer\nState: closed\nBase branch: master\nHead branch: reset\nCreated: 2021-03-07T17:00:51Z\nUpdated: 2021-03-07T17:40:29Z\nClosed: 2021-03-07T17:40:26Z\nMerged: 2021-03-07T17:40:26Z\n\n## PR Title\nsupport synchronous reset\n\n## PR Description\nDidn't feel this was necessary at the time, but now I found a usecase with MIPI to help keep the fifo small.\n\n## PR Comments\n\n**sameer** (Mar 7, 2021):\n\"Didn't feel this was necessary at the time, but now I found a usecase with MIPI to help keep the fifo small.\"\n\n## PR Metadata\n- Status: Merged\n- Commit hash: e27e6ee\n- Merge commit: 33b8a60\n- Branch deleted after merge: reset\n\n## Linked Issues\nNo linked issues are referenced in this pull request.\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/hdl-util_hdmi_pr22", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/hdl-util_hdmi_pr22.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/hdl-util_hdmi_pr22", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/hdl-util_hdmi_pr22"}
{"instance_id": "hdl-util_hdmi_pr23", "issue_text": "# add ip-less option for non intel/xilinx\n\nInstance: hdl-util_hdmi_pr23\nSource: https://github.com/hdl-util/hdmi/pull/23\nFetched: 2026-04-26\nRepository: hdl-util/hdmi\nPull request: #23\nAuthor: sameer\nState: closed\nBase branch: master\nHead branch: no_ip\nCreated: 2021-03-07T17:43:44Z\nUpdated: 2021-03-07T18:05:15Z\nClosed: 2021-03-07T18:05:11Z\nMerged: 2021-03-07T18:05:11Z\n\nThis is the same implementation used in v1.1 but with added ip-less ddr io.\r\n\r\nHopefully it covers lattice and others but I don't know enough about those to confirm.\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/hdl-util_hdmi_pr23", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/hdl-util_hdmi_pr23.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/hdl-util_hdmi_pr23", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/hdl-util_hdmi_pr23"}
{"instance_id": "hdl-util_hdmi_pr28", "issue_text": "# Allow setting IT content flag, and make it default\n\nInstance: hdl-util_hdmi_pr28\nSource: https://github.com/hdl-util/hdmi/pull/28\nFetched: 2026-04-26\nRepository: hdl-util/hdmi\nPull request: #28\nAuthor: bkoropoff\nState: closed\nBase branch: master\nHead branch: it-content\nCreated: 2022-01-23T00:07:36Z\nUpdated: 2022-01-26T17:05:23Z\nClosed: 2022-01-26T17:05:23Z\nMerged: 2022-01-26T17:05:23Z\n\nThis is usually what you want for ad-hoc image generation.\r\nApplications that explicitly generate bandlimited signals\r\ncan turn it off.\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/hdl-util_hdmi_pr28", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/hdl-util_hdmi_pr28.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/hdl-util_hdmi_pr28", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/hdl-util_hdmi_pr28"}
{"instance_id": "hdl-util_hdmi_pr29", "issue_text": "# hdmi: allow setting start x/y with parameters\n\nInstance: hdl-util_hdmi_pr29\nSource: https://github.com/hdl-util/hdmi/pull/29\nFetched: 2026-04-26\nRepository: hdl-util/hdmi\nPull request: #29\nAuthor: bkoropoff\nState: closed\nBase branch: master\nHead branch: start-coord\nCreated: 2022-01-23T00:08:30Z\nUpdated: 2022-01-27T01:22:16Z\nClosed: 2022-01-27T01:22:16Z\nMerged: 2022-01-27T01:22:16Z\n\ngbaHD needs this synchronize the hdmi output with the start of a GBA\r\nframe, with the GBA image centered within the HDMI frame instead of\r\nstarting at 0,0.\r\n\r\nIt's easier and uses fewer FPGA resources to start the hdmi block in the\r\nmiddle of a frame than to count off the right number of cycles from GBA\r\nvsync to achieve the same phase relationship.  Receivers need to be able\r\nto synchronize from mid-stream anyway, so this doesn't cause any\r\nproblems.\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/hdl-util_hdmi_pr29", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/hdl-util_hdmi_pr29.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/hdl-util_hdmi_pr29", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/hdl-util_hdmi_pr29"}
{"instance_id": "hdl-util_hdmi_pr30", "issue_text": "# Change vsync timing to match CEA-861-D\n\nInstance: hdl-util_hdmi_pr30\nSource: https://github.com/hdl-util/hdmi/pull/30\nFetched: 2026-04-26\nRepository: hdl-util/hdmi\nPull request: #30\nAuthor: bkoropoff\nState: closed\nBase branch: master\nHead branch: vsync-timing\nCreated: 2022-02-05T07:00:01Z\nUpdated: 2022-02-06T01:02:31Z\nClosed: 2022-02-06T00:46:18Z\nMerged: 2022-02-06T00:46:18Z\n\nWhile looking for possible causes of reported display compatibility problems with gbaHD, I noticed that the CEA-861-D timing diagrams show that the edges of vsync should coincide with the leading edges of hsync.  The logic in the core only considers the current vertical position.  Since sync is only transmitted during control periods, the effect is that vsync starts earlier than the spec shows by the duration of the front porch (a handful of pixel clock cycles).  I don't know if this would really cause compatibility problems, but it seems like a theoretical deviation from the spec.\r\n\r\nI also changed some signal names to conform to standard nomenclature.  \"Porch\" refers to the regions during the blanking period before and after the sync pulses.\r\n\r\nEDIT: I have confirmation from at least one person that this change fixed compatibility with their finicky display/capture devices.\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/hdl-util_hdmi_pr30", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/hdl-util_hdmi_pr30.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/hdl-util_hdmi_pr30", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/hdl-util_hdmi_pr30"}
{"instance_id": "hdl-util_hdmi_pr34", "issue_text": "# Added Gowin serializer.\n\nInstance: hdl-util_hdmi_pr34\nSource: https://github.com/hdl-util/hdmi/pull/34\nFetched: 2026-04-26\nRepository: hdl-util/hdmi\nPull request: #34\nAuthor: zwenergy\nState: closed\nBase branch: master\nHead branch: master\nCreated: 2022-07-20T19:01:59Z\nUpdated: 2022-07-20T19:07:01Z\nClosed: 2022-07-20T19:07:00Z\nMerged: 2022-07-20T19:07:00Z\n\n## PR Title\nAdded Gowin serializer.\n\n## PR Description\nAdded serializer components for current Gowin FPGAs. As far as I can see, there is no variable set during synthesis using the Gowin synthesis tool, hence I added an \"arbitrary\" called \"GW_IDE\" which then has to be set prior in one of the source files.\n\n## PR Comments\n\n**zwenergy** (Jul 20, 2022):\n\"Added serializer components for current Gowin FPGAs. As far as I can see, there is no variable set during synthesis using the Gowin synthesis tool, hence I added an 'arbitrary' called 'GW_IDE' which then has to be set prior in one of the source files.\"\n\n**sameer** (Jul 20, 2022):\n\"Thanks for doing this! I'll update the README to indicate Gowin / Tang nano is now supported. If you have some time, would you mind adding a demo repo for your board in hdl-util/hdmi-demo?\"\n\n## PR Metadata\n- Status: Merged\n- Subsequently referenced in Issue #37 (\"IP-less serializer is not working\") on February 18, 2023\n\n## Linked Issues\nNo linked issues are referenced directly in this pull request, although it was later referenced from Issue #37.\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/hdl-util_hdmi_pr34", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/hdl-util_hdmi_pr34.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/hdl-util_hdmi_pr34", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/hdl-util_hdmi_pr34"}
{"instance_id": "hdl-util_hdmi_pr44", "issue_text": "# fixes #43: enforce hdmi 12px minimum control period during video and data-island preambles\n\nInstance: hdl-util_hdmi_pr44\nSource: https://github.com/hdl-util/hdmi/pull/44\nFetched: 2026-04-26\nRepository: hdl-util/hdmi\nPull request: #44\nAuthor: krisdover\nState: closed\nBase branch: master\nHead branch: bugfix-hmdi-12px-min-control-period\nCreated: 2023-08-20T02:45:45Z\nUpdated: 2023-08-20T16:58:39Z\nClosed: 2023-08-20T16:58:38Z\nMerged: 2023-08-20T16:58:38Z\n\n## PR Title\nfixes #43: enforce hdmi 12px minimum control period during video and data-island preambles\n\n## PR Description\nAlso fixes off-by-one errors on VG, VP, and VSync. I'm running some of this code on a Tang Nano 4K and after hooking it up to a logic analyzer and inspecting the pre-TMDS encoded signals, I noticed the VSync was delayed by an extra video line, and also VG and VP were being generated at the end of the last active video line.\n\n## PR Comments\n\n**sameer** (Aug 20, 2023):\n\"no VG at end of last line — good catch! This would end up being repeated, right?\"\n\n**krisdover** confirmed sameer's review with a thumbs-up reaction.\n\n## PR Metadata\n- Status: Merged\n- Has been referenced and ported to downstream projects, including commits to BrentRector's a2fpga_core repository acknowledging this PR's resolution of HDMI spec violations affecting sink compatibility.\n\n## Linked Issues\n**Issue #43**: The original bug report requesting enforcement of the HDMI 12px minimum control period specification during video and data-island preamble phases. (Body not retrieved verbatim.)\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/hdl-util_hdmi_pr44", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/hdl-util_hdmi_pr44.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/hdl-util_hdmi_pr44", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/hdl-util_hdmi_pr44"}
{"instance_id": "jotego_jt12_pr64", "issue_text": "# Genesis Regression: Bimini Run audio playing too fast\n\n- Source URL: https://github.com/jotego/jt12/issues/62\n\n## Issue Title\nGenesis Regression: Bimini Run audio playing too fast\n\n## Issue Description\nhttps://github.com/MiSTer-devel/Genesis_MiSTer/issues/26#issuecomment-1117934103 — as confirmed by gyurco, Bimini Run has a regression that points to this commit: https://github.com/jotego/jt12/commit/66eb9ee162e1b1cd3f31f7549af969c7bc191951\n\nThe issue reports a regression in the Bimini Run game where audio plays at an increased speed.\n\n## Issue Comments\nNone visible.\n\n## Issue Metadata\n- Status: Closed (resolved via PR #64)\n- Project: JTCores\n\n## Linked Issues / PRs\n- PR #64 — resolution\n- References Genesis_MiSTer #26\n- Points to commit 66eb9ee162e1b1cd3f31f7549af969c7bc191951\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/jotego_jt12_pr64", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/jotego_jt12_pr64.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/jotego_jt12_pr64", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/jotego_jt12_pr64"}
{"instance_id": "jotego_jtcores_pr1021", "issue_text": "# [JTALIENS] Misaligned sprites in the game \"Aliens\"\n\n- Source URL: https://github.com/jotego/jtcores/issues/1002\n\n## Issue Title\n[JTALIENS] Misaligned sprites in the game \"Aliens\"\n\n## Issue Description\nAfter destroying the head of the 1st boss the sprite is sometimes misaligned right down the middle. Had a hard time reproducing this again.\n\nAt the end of the truck driving stage the door where the little girl gets captured has misaligned sprites. Easily reproducible and seems to happen everytime.\n\nTested using rom sets \"Aliens (US)\" and \"Aliens (World Set 1)\".\n\n(An image was attached showing the sprite misalignment problem.)\n\n## Issue Comments\nNone visible.\n\n## Issue Metadata\n- Status: Closed (resolved via PR #1021)\n- Assignment: rp-jt\n- Label: core bug\n\n## Linked Issues / PRs\n- PR #1021 — resolution\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/jotego_jtcores_pr1021", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/jotego_jtcores_pr1021.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/jotego_jtcores_pr1021", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/jotego_jtcores_pr1021"}
{"instance_id": "jotego_jtcores_pr1069", "issue_text": "# ngp/ngpc: brown line appearing at the bottom of the screen\n\n- Source URL: https://github.com/jotego/jtcores/issues/994\n\n## Issue Title\nngp/ngpc: brown line appearing at the bottom of the screen\n\n## Issue Description\nTested for commit 31abc75893f2108052617b8c119cc2f7d7731b3f on Analogue Pocket.\n\n(Issue body details beyond the test commit reference were not fully captured.)\n\n## Issue Comments\nNone visible.\n\n## Issue Metadata\n- Status: Closed (marked Done in JTCores project)\n- Assignee: rp-jt\n\n## Linked Issues / PRs\n- PR #1111\n- PR #1069\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/jotego_jtcores_pr1069", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/jotego_jtcores_pr1069.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/jotego_jtcores_pr1069", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/jotego_jtcores_pr1069"}
{"instance_id": "jotego_jtcores_pr1077", "issue_text": "# [jtcircus] Jumping for a 4th time in a drum in 3rd stage doesn't show the clown trespassing the circus tent\n\n- Source URL: https://github.com/jotego/jtcores/issues/1053\n\nEnglish:\n\nOn the third stage ( and maybe other stages ), the clown is jumping from drum to drum to advance. If a jump on any given drum is repeated in the same drum, the clown gains momentum and jumps a bit higher each time. This is useful to catch the money bags that appear above the top of the elephant doors height. You jump three times over the same drum so you make the clown reach those money bags. However, if you jump for a fourth time, the jump is too high and the clown will trespass the circus tent at the top ( the yellow and blue one ) and a sprite representing the clown's face breaking the tent plastic will appear. This doesn't happen in the jtcircus core ( seen in Analogue Pocket ).\n\nhttps://youtu.be/Z2QPrSMYPx8\n\nPlease watch at 03:55, there's four jumps from that point:\n- the first one, arriving from the previous drum,\n- then a couple more jumps which make it jump higher but are still fine\n- and a fourth jump that makes it jump too far/high and the face trespassing the broken tent plastic sprite appears \n\n\nSpanish:\n\nEn el tercer nivel ( y quiza en otros niveles ), el payaso salta de tambor a tambor para avanzar. Si un salto en cualquier tambor se repite en ese mismo tambor, el payaso gana impulso y salta algo mas cada vez. Esto es util para alcanzar las bolsas de dinero que aparecen por encima de la altura de las puertas de los elephantes. Saltas tres veces encima del mismo tambor asi que haces que el payaso alcance esas bolsas de dinero. Sin embargo, si saltas una cuarta vez, el salto es demasiado alto y el payaso traspasa la tienda del circo que esta arriba del todo ( la de color amarillo y azul ) y aparecera el sprite que representa la cara del payaso rompiendo el plastico de la tienda. Esto no ocurre en el core jtcircus ( visto en la Analogue Pocket ).\n\nhttps://youtu.be/Z2QPrSMYPx8\n\nPor favor, vean en 03:55, hay cuatro saltos desde ese punto:\n- el primero, llegando desde el tambor anterior,\n- luego un par de saltos mas que lo hacen saltar mas alto pero todavia estan bien\n- y un cuarto salto que lo hace saltar demasiado lejos/alto y aparece el sprite de la cara traspasando el plastico roto de la tienda\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/jotego_jtcores_pr1077", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/jotego_jtcores_pr1077.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/jotego_jtcores_pr1077", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/jotego_jtcores_pr1077"}
{"instance_id": "jotego_jtcores_pr1087", "issue_text": "# riders: screen is offset by 1 pixel\n\n- Source URL: https://github.com/jotego/jtcores/issues/1080\n\n## Issue Title\nriders: screen is offset by 1 pixel\n\n## Issue Description\ncommit: 0d22db4\n\nVisible in service mode (screenshot attached).\n\nThe maintainer jotego opened this issue on June 13, 2025, referencing commit 0d22db4. The problem is described as visible in service mode, with an attached screenshot demonstrating the offset rendering.\n\n## Issue Comments\nNone visible.\n\n## Issue Metadata\n- Status: Closed (marked Done in JTCores project)\n- Assignment: rp-jt, jotego\n\n## Linked Issues / PRs\n- PR #1087 — closes this issue\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/jotego_jtcores_pr1087", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/jotego_jtcores_pr1087.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/jotego_jtcores_pr1087", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/jotego_jtcores_pr1087"}
{"instance_id": "jotego_jtcores_pr1089", "issue_text": "# s18: Sprites horizontally displaced\n\n- Source URL: https://github.com/jotego/jtcores/issues/1082\n\n## Issue Title\ns18: Sprites horizontally displaced\n\n## Issue Description\nI think the sprites are being drawn one or two pixels more to the right than where they should be.\n\nCan be seen in the space left at the left right of the life bar or the character picture in astorm or in the map from lghost (screenshots attached).\n\n## Issue Comments\nNone visible.\n\n## Issue Metadata\n- Status: Closed (via PR #1089)\n- Project: JTCores\n\n## Linked Issues / PRs\n- PR #1089 — resolution\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/jotego_jtcores_pr1089", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/jotego_jtcores_pr1089.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/jotego_jtcores_pr1089", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/jotego_jtcores_pr1089"}
{"instance_id": "jotego_jtcores_pr1097", "issue_text": "# riders -> lgtnfght: right half of boss disappears at high zoom values\n\n- Source URL: https://github.com/jotego/jtcores/issues/1083\n\n## Issue Title\nriders -> lgtnfght: right half of boss disappears at high zoom values\n\n## Issue Description\ncommit: 2aebeeec4\n\nWhen the boss appears on screen at a large zoom, the right half is not drawn (screenshot attached).\n\nAs the scale factor decreases, the whole ship is eventually visible.\n\n## Issue Comments\nNone visible.\n\n## Issue Metadata\n- Status: Closed via PR #1097\n- Assignment: rp-jt\n- Label: core bug\n- Project: JTCores (marked Done)\n- Opened: June 14, 2025\n\n## Linked Issues / PRs\n- PR #1097 — resolution\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/jotego_jtcores_pr1097", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/jotego_jtcores_pr1097.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/jotego_jtcores_pr1097", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/jotego_jtcores_pr1097"}
{"instance_id": "jotego_jtcores_pr1100", "issue_text": "# riders -> lgtnfght: correctly implement dimming\n\n- Source URL: https://github.com/jotego/jtcores/issues/1084\n\n## Issue Title\nriders -> lgtnfght: correctly implement dimming\n\n## Issue Description\nCurrently (5c567cc92) only the Sunset Riders implementation is in place. The task involves implementing dimming functionality for the lgtnfght (Light Fighting) game on the existing core.\n\n## Issue Comments\nNone visible.\n\n## Issue Metadata\n- Status: Closed (resolved via PR #1100)\n- Assignees: jotego, rp-jt\n- Labels: new game on existing core\n- Project: JTCores\n\n## Linked Issues / PRs\n- PR #1100 — resolution\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/jotego_jtcores_pr1100", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/jotego_jtcores_pr1100.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/jotego_jtcores_pr1100", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/jotego_jtcores_pr1100"}
{"instance_id": "jotego_jtcores_pr1101", "issue_text": "# riders/lgtnfght: Objects break when turning on Flip Switch\n\n- Source URL: https://github.com/jotego/jtcores/issues/1095\n\n## Issue Title\nriders/lgtnfght: Objects break when turning on Flip Switch\n\n## Issue Description\nWhen enabling DIP Switch \"flip\" in Lighting Fighters, scroll and fix layers work correctly but objects become broken and cannot be seen on screen or appear in the wrong position.\n\nThis could be related to it being a Vertical game.\n\nRiders use jt053244 which is very similar to jt05346, so check on adding changes in both modules, even though no vertical game uses jt053246 yet.\n\n## Issue Comments\nNone visible.\n\n## Issue Metadata\n- Status: Closed (resolved via PR #1101)\n- Assignee: rp-jt\n\n## Linked Issues / PRs\n- PR #1101 — resolution\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/jotego_jtcores_pr1101", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/jotego_jtcores_pr1101.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/jotego_jtcores_pr1101", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/jotego_jtcores_pr1101"}
{"instance_id": "jotego_jtcores_pr1108", "issue_text": "# NGP/NGPC: Buttons do not work properly and Pac Man does not start\n\n- Source URL: https://github.com/jotego/jtcores/issues/1037\n\n## Issue Title\nNGP/NGPC: Buttons do not work properly and Pac Man does not start\n\n## Issue Description\nButtons do not work properly in Metal Slug on NGP. It moves forward on its own, cannot retreat, and cannot jump.\n\nI have tried cores from the past and there may be a problem with cores from 30 August, Commit: 324e62c or earlier.\n\n## Issue Comments\nNone visible.\n\n## Issue Metadata\n- Status: Closed (resolved via PR #1108)\n- Assignee: rp-jt\n- Label: core bug\n- Milestone: ngp\n- Project: JTCores\n- Opened by: jtmiki on April 14, 2025\n\n## Linked Issues / PRs\n- PR #1108 — resolution\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/jotego_jtcores_pr1108", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/jotego_jtcores_pr1108.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/jotego_jtcores_pr1108", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/jotego_jtcores_pr1108"}
{"instance_id": "jotego_jtcores_pr1111", "issue_text": "# ngp/ngpc: brown line appearing at the bottom of the screen\n\n- Source URL: https://github.com/jotego/jtcores/issues/994\n\n## Issue Title\nngp/ngpc: brown line appearing at the bottom of the screen\n\n## Issue Description\nTested for commit 31abc75893f2108052617b8c119cc2f7d7731b3f on Analogue Pocket.\n\n(Issue body details beyond the test commit reference were not fully captured.)\n\n## Issue Comments\nNone visible.\n\n## Issue Metadata\n- Status: Closed (marked Done in JTCores project)\n- Assignee: rp-jt\n\n## Linked Issues / PRs\n- PR #1111\n- PR #1069\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/jotego_jtcores_pr1111", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/jotego_jtcores_pr1111.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/jotego_jtcores_pr1111", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/jotego_jtcores_pr1111"}
{"instance_id": "jotego_jtcores_pr1167", "issue_text": "# Vendetta: No character sprites\n\n- Source URL: https://github.com/jotego/jtcores/issues/1161\n\n## Issue Title\nVendetta: No character sprites\n\n## Issue Description\nBackground is fine, but no character or enemies display (they are there because you can hear game sounds).\n\nSprites will appear on continue screen, but will visually freeze in place if you continue (until the next continue screen.)\n\n(An image was attached.)\n\n## Issue Comments\nNone visible.\n\n## Issue Metadata\n- Status: Closed (linked to PR #1167)\n- Reporter: TheJesusFish (opened August 31, 2025)\n- Assignees: rp-jt\n- Project: JTCores\n\n## Linked Issues / PRs\n- PR #1167 — resolution\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/jotego_jtcores_pr1167", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/jotego_jtcores_pr1167.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/jotego_jtcores_pr1167", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/jotego_jtcores_pr1167"}
{"instance_id": "jotego_jtcores_pr1169", "issue_text": "# suratk: sprite on sprite shade\n\n- Source URL: https://github.com/jotego/jtcores/issues/1160\n\n## Issue Title\nsuratk: sprite on sprite shade\n\n## Issue Description\nSprites can currently cast a shadow on the background but not on other sprites. This feature is missing on master.\n\nIt works on the suratk-1160 branch but the change may be not be backwards compatible.\n\n(Two screenshot images were provided showing the visual difference between the current state and the desired implementation with sprite-on-sprite shadowing.)\n\n## Issue Comments\nNone visible.\n\n## Issue Metadata\n- Status: Closed (linked to PR #1169)\n- Assignee: rp-jt\n- Labels: core bug, new core\n- Project: JTCores (Status: Done)\n\n## Linked Issues / PRs\n- PR #1169 — resolution\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/jotego_jtcores_pr1169", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/jotego_jtcores_pr1169.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/jotego_jtcores_pr1169", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/jotego_jtcores_pr1169"}
{"instance_id": "jotego_jtcores_pr1177", "issue_text": "# support for SRAM memory on Analogue Pocket\n\n- Source URL: https://github.com/jotego/jtcores/issues/1147\n\n## Issue Title\nsupport for SRAM memory on Analogue Pocket\n\n## Issue Description\nAdd SRAM blocks to mem.yaml that can be enabled with macros.\n\n## Issue Comments\nNone visible.\n\n## Issue Metadata\n- Status: Closed (linked to PR #1177)\n- Assignee: jotego\n- Project: JTCores (Status: Done)\n\n## Linked Issues / PRs\n- PR #1177 — resolution\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/jotego_jtcores_pr1177", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/jotego_jtcores_pr1177.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/jotego_jtcores_pr1177", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/jotego_jtcores_pr1177"}
{"instance_id": "jotego_jtcores_pr1182", "issue_text": "# riders/glfgreat: Correct PSAC Alignment\n\n- Source URL: https://github.com/jotego/jtcores/issues/1181\n\n## Issue Title\nriders/glfgreat: Correct PSAC Alignment\n\n## Issue Description\nPSAC seems to be displaced in FPGA and long simulations.\n\nThis effect is not seen in scene simulation, where the tilemap memory is generated differently. Are the memory saved at game launch and the one generated for scene simulation different?\n\n(An image showing the visual discrepancy was attached to demonstrate the problem.)\n\n## Issue Comments\nNone visible.\n\n## Issue Metadata\n- Status: Closed (linked to PR #1182)\n- Assignee: rp-jt\n\n## Linked Issues / PRs\n- PR #1182 — correction to PSAC alignment\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/jotego_jtcores_pr1182", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/jotego_jtcores_pr1182.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/jotego_jtcores_pr1182", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/jotego_jtcores_pr1182"}
{"instance_id": "jotego_jtcores_pr1191", "issue_text": "# Rolling thunder title screen alignment\n\n- Source URL: https://github.com/jotego/jtcores/issues/1103\n\n## Issue Title\nRolling thunder title screen alignment\n\n## Issue Description\nNoticed the sprites go over the text by 1 pixel on the title screen compared to the PCB.\n\nPCB reference: https://youtu.be/23RK-z4V1jY?si=eq_2tYSYZ2Zn_vce\n\nMiSTer: in front of the T and S slightly (easier to see moving). (Screenshot attached.)\n\n## Issue Comments\nNone visible.\n\n## Issue Metadata\n- Status: Closed (via PR #1191)\n- Assignees: rp-jt, niknakniknak\n- Project: JTCores\n\n## Linked Issues / PRs\n- PR #1191 — resolution\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/jotego_jtcores_pr1191", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/jotego_jtcores_pr1191.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/jotego_jtcores_pr1191", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/jotego_jtcores_pr1191"}
{"instance_id": "jotego_jtcores_pr1193", "issue_text": "# karnov: Wonder Planet graphical issues if dip flip screen is set to ON\n\n- Source URL: https://github.com/jotego/jtcores/issues/1127\n\n## Issue Title\nkarnov: Wonder Planet graphical issues if dip flip screen is set to ON\n\n## Issue Description\nSee the screenshot!\n\n(A screenshot was attached showing graphical problems in the \"Wonder Planet\" game within the karnov core when the \"dip flip screen\" setting is enabled.)\n\nThanks.\n\n## Issue Comments\nNone visible.\n\n## Issue Metadata\n- Status: Closed (resolved via PR #1193)\n- Assignment: rp-jt\n- Label: core bug\n- Project: JTCores\n\n## Linked Issues / PRs\n- PR #1193 — resolution\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/jotego_jtcores_pr1193", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/jotego_jtcores_pr1193.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/jotego_jtcores_pr1193", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/jotego_jtcores_pr1193"}
{"instance_id": "jotego_jtcores_pr1202", "issue_text": "# karnov: objects not drawn at the end of the lines when flip=1\n\n- Source URL: https://github.com/jotego/jtcores/issues/1199\n\n## Issue Title\nkarnov: objects not drawn at the end of the lines when flip=1\n\n## Issue Description\nWhen dip flip is turned on for any game in the karnov core, objects cannot be drawn in the last 8-ish pixels of the line.\n\nIt is not a priority issue, since removing the other layers does not get you to see the full object.\n\n## Issue Comments\nNone visible.\n\n## Issue Metadata\n- Status: Closed (linked to PR #1202)\n- Assignee: rp-jt\n\n## Linked Issues / PRs\n- PR #1202 — resolution\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/jotego_jtcores_pr1202", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/jotego_jtcores_pr1202.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/jotego_jtcores_pr1202", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/jotego_jtcores_pr1202"}
{"instance_id": "jotego_jtcores_pr1205", "issue_text": "# Consider how to make analogizer part of Pocket target public\n\n- Source URL: https://github.com/jotego/jtcores/issues/1163\n\n## Issue Title\nConsider how to make analogizer part of Pocket target public\n\n## Issue Description\nTotalFury has been improving the analogizer and he would like to contribute his changes, but our files are part of the Pocket target, which is held private.\n\nConsider how to make the analogizer section of the Pocket target public so we can take PRs.\n\nThe core challenge involves balancing the private nature of the Pocket target repository while enabling public collaboration on the analogizer component specifically.\n\n## Issue Comments\nNone visible.\n\n## Issue Metadata\n- Status: Closed (marked Done in JTCores project)\n- Assignees: jotego, rp-jt\n\n## Linked Issues / PRs\n- PR #1205 — addresses this issue\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/jotego_jtcores_pr1205", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/jotego_jtcores_pr1205.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/jotego_jtcores_pr1205", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/jotego_jtcores_pr1205"}
{"instance_id": "jotego_jtcores_pr1228", "issue_text": "# tmnt2: graphic problem\n\n- Source URL: https://github.com/jotego/jtcores/issues/1220\n\n## Issue Title\ntmnt2: graphic problem\n\n## Issue Description\nThis screenshot is from a YouTube video. (Screenshot attached.)\n\nWhen playing this game on the MiSTer, at scene 4, if the protagonist or enemies move into the area where the spotlight is shining, they don't appear as shown in this image. Instead, they become completely invisible, as if hidden behind a wall.\n\nCommit: 701515f.\n\n## Issue Comments\nNone visible.\n\n## Issue Metadata\n- Status: Closed (resolved by PR #1228)\n- Assignee: rp-jt\n- Label: core bug\n- Project: JTCores (Status: Done)\n\n## Linked Issues / PRs\n- PR #1228 — resolution\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/jotego_jtcores_pr1228", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/jotego_jtcores_pr1228.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/jotego_jtcores_pr1228", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/jotego_jtcores_pr1228"}
{"instance_id": "jotego_jtcores_pr1229", "issue_text": "# s18: laser ghost controls on Analogue Pocket\n\n- Source URL: https://github.com/jotego/jtcores/issues/1096\n\n## Issue Title\ns18: laser ghost controls on Analogue Pocket\n\n## Issue Description\nIt is reported that it cannot be played on the D-PAD.\n\n## Issue Comments\nNone visible.\n\n## Issue Metadata\n- Status: Closed (linked to PR #1229)\n- Assignees: jotego, rp-jt\n\n## Linked Issues / PRs\n- PR #1229 — resolution\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/jotego_jtcores_pr1229", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/jotego_jtcores_pr1229.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/jotego_jtcores_pr1229", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/jotego_jtcores_pr1229"}
{"instance_id": "jotego_jtcores_pr1235", "issue_text": "# rungun: screen alignment\n\n- Source URL: https://github.com/jotego/jtcores/issues/1231\n\n## Issue Title\nrungun: screen alignment\n\n## Issue Description\nNo description provided.\n\n(The work appears to have been tracked through discussion or commits rather than detailed issue documentation.)\n\n## Issue Comments\nNone visible.\n\n## Issue Metadata\n- Status: Closed (resolved via PR #1235)\n- Assignee: rp-jt\n- Label: new core\n\n## Linked Issues / PRs\n- PR #1235 — resolution\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/jotego_jtcores_pr1235", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/jotego_jtcores_pr1235.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/jotego_jtcores_pr1235", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/jotego_jtcores_pr1235"}
{"instance_id": "jotego_jtcores_pr1242", "issue_text": "# s18/wwallyj: missing borders\n\n- Source URL: https://github.com/jotego/jtcores/issues/1061\n\n## Issue Title\ns18/wwallyj: missing borders\n\n## Issue Description\nBlack borders are missing for the sprites shown when explaining how to play the game (ball, button, table, hands).\n\nComparison screenshots were provided: the current core output versus the original arcade video, highlighting the visual discrepancy in border rendering.\n\nArcade reference video: https://www.youtube.com/watch?v=Kn0mct3ZUk4\n\n## Issue Comments\nNone visible.\n\n## Issue Metadata\n- Status: Closed (linked to PR #1242)\n- Assignee: rp-jt\n- Project: JTCores\n\n## Linked Issues / PRs\n- PR #1242 — resolution\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/jotego_jtcores_pr1242", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/jotego_jtcores_pr1242.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/jotego_jtcores_pr1242", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/jotego_jtcores_pr1242"}
{"instance_id": "jotego_jtcores_pr1248", "issue_text": "# ngp: prevent turning off by accident\n\n- Source URL: https://github.com/jotego/jtcores/issues/1232\n\n## Issue Title\nngp: prevent turning off by accident\n\n## Issue Description\nIn the ngp and ngpc cores, we can simulate turning off the console by pressing the coin button. This is necessary, for example, if you want to change the game you're playing without going through the console setup menu again.\n\nA user has requested a way to disable this button. Since it is of common use in other games, it is easy to click by accident, especially in Pocket handheld mode, making you lose progress midgame.\n\nPutting this button behind a menu option should not be the solution, since it is fundamental to the console's operation.\n\nAnother possibility is adding an option so that \"turning off\" becomes a button combination, instead of the coin button by itself.\n\n## Issue Comments\nNone visible.\n\n## Issue Metadata\n- Status: Closed (marked Done via PR #1248)\n- Assignee: rp-jt\n- Label: enhancement\n- Project: JTCores\n\n## Linked Issues / PRs\n- PR #1248 — resolution\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/jotego_jtcores_pr1248", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/jotego_jtcores_pr1248.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/jotego_jtcores_pr1248", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/jotego_jtcores_pr1248"}
{"instance_id": "jotego_jtcores_pr1252", "issue_text": "# suratk: move to paroda core and make public\n\n- Source URL: https://github.com/jotego/jtcores/issues/1246\n\n## Issue Title\nsuratk: move to paroda core and make public\n\n## Issue Description\nLet's make the binary public during November.\n\n(The issue requests moving the suratk component to the paroda core and making its binary publicly available during November 2025.)\n\n## Issue Comments\nNone visible.\n\n## Issue Metadata\n- Status: Closed (resolved via PR #1252)\n- Assignees: rp-jt, jotego\n- Project: JTCores\n- Opened: November 3, 2025 by jotego\n\n## Linked Issues / PRs\n- PR #1252 — resolution\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/jotego_jtcores_pr1252", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/jotego_jtcores_pr1252.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/jotego_jtcores_pr1252", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/jotego_jtcores_pr1252"}
{"instance_id": "jotego_jtcores_pr1260", "issue_text": "# rungun: Implement shadows\n\n- Source URL: https://github.com/jotego/jtcores/issues/1253\n\n## Issue Title\nrungun: Implement shadows\n\n## Issue Description\nNo description was provided for this issue.\n\n(This is a feature request for implementing shadow rendering functionality in the rungun arcade core within the JTCores project.)\n\n## Issue Comments\nNone visible.\n\n## Issue Metadata\n- Status: Closed (resolved via PR #1260)\n- Assignee: rp-jt\n- Project: JTCores\n- Opened: November 7, 2025\n\n## Linked Issues / PRs\n- PR #1260 — resolution\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/jotego_jtcores_pr1260", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/jotego_jtcores_pr1260.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/jotego_jtcores_pr1260", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/jotego_jtcores_pr1260"}
{"instance_id": "jotego_jtcores_pr1265", "issue_text": "# rungun: \"trash\" on the left side of the screen\n\n- Source URL: https://github.com/jotego/jtcores/issues/1264\n\n## Issue Title\nrungun: \"trash\" on the left side of the screen\n\n## Issue Description\nNo description provided.\n\n(The issue reports a visual glitch in the rungun arcade game emulation where unwanted graphical elements appear on the left portion of the display.)\n\n## Issue Comments\nNone visible.\n\n## Issue Metadata\n- Status: Closed (resolved via PR #1265)\n- Author: rp-jt (opened November 13, 2025)\n- Assignee: rp-jt\n- Project: JTCores\n\n## Linked Issues / PRs\n- PR #1265 — resolution\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/jotego_jtcores_pr1265", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/jotego_jtcores_pr1265.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/jotego_jtcores_pr1265", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/jotego_jtcores_pr1265"}
{"instance_id": "jotego_jtcores_pr1270", "issue_text": "# rungun: \"trash\" on top of the screen\n\n- Source URL: https://github.com/jotego/jtcores/issues/1269\n\n## Issue Title\nrungun: \"trash\" on top of the screen\n\n## Issue Description\nOn the second visible line of the screen, sometimes some weird graphics are drawn in the objects layer.\n\nThis effect is not seen in a short scene simulation.\n\nThrough a longer simulation, it is seen that this occurs when an object is at the bottom of the screen. The last line drawn for this object in jtframe_obj_buffer is not read, and therefore not deleted, until the top of the following frame is read, producing this effect.\n\n## Issue Comments\nNone visible.\n\n## Issue Metadata\n- Status: Closed (PR #1270)\n- Assignee: rp-jt\n- Project: JTCores\n\n## Linked Issues / PRs\n- PR #1270 — resolution\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/jotego_jtcores_pr1270", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/jotego_jtcores_pr1270.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/jotego_jtcores_pr1270", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/jotego_jtcores_pr1270"}
{"instance_id": "jotego_jtcores_pr1279", "issue_text": "# kiwi: Dr Toppel's Adventure Graphical Issue\n\n- Source URL: https://github.com/jotego/jtcores/issues/1276\n\nCopying from here: https://github.com/jotego/jtcores_mister/issues/13\n\n> https://youtu.be/UEeqoD7jRxc?t=56 timestamp - please notice the orange issues where background graphics are not drawing in properly - I am not sure when this started, I utilized update_all on 11/22/2025 prior to testing.\nNote - I tried all 3 MRAs and all have this issue (World, USA, and Japan).\nI also noticed sound seems a little off but I am not as well versed to know if this is inaccurate or an issue.\n\n## Fetched Issue/PR Details\n\nTitle: kiwi: Dr Toppel's Adventure Graphical Issue (#1276)\n\nDescription: The issue references a graphical problem in Dr. Toppel's Adventure where there are \"orange issues where background graphics are not drawing in properly.\" The reporter tested all three MRAs (World, USA, and Japan) and experienced the same graphical glitch after running an update on November 22, 2025. They also noted potential sound anomalies but were uncertain whether these represent actual bugs.\n\nStatus: Closed (linked to PR #1279)\nProject: JTCores\n\nComments: No comments were visible beyond the initial issue description.\n\nLinked Issues: References https://github.com/jotego/jtcores_mister/issues/13 (the original report copied into this issue).\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/jotego_jtcores_pr1279", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/jotego_jtcores_pr1279.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/jotego_jtcores_pr1279", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/jotego_jtcores_pr1279"}
{"instance_id": "jotego_jtcores_pr1290", "issue_text": "# rungun: set frame buffer CRAM clock to 48MHz\n\n- Source URL: https://github.com/jotego/jtcores/issues/1257\n\nCRAM access on Pocket has a ~3ns slack when operated at 96MHz. It is not necessary to operate it at full speed for the frame buffer operation. Modify the module so it can work with the core at 96MHz and the external CRAM at 48MHz.\n\n## Fetched Issue/PR Details\n\nTitle: rungun: set frame buffer CRAM clock to 48MHz (#1257)\n\nDescription: The issue describes a timing constraint problem with CRAM access on Pocket hardware. There is approximately 3 nanoseconds of slack when operating at 96MHz, creating a performance bottleneck. The proposed solution is to modify the module so the core can continue operating at 96MHz while reducing the external CRAM clock speed to 48MHz, eliminating the timing violation while maintaining adequate functionality for frame buffer operations.\n\nStatus: Closed (marked as Done)\nAssociated PR: #1290\nAssignees: rp-jt and jotego\nProject: JTCores\n\nComments: No comments were visible on the page.\n\nLinked Issues: None beyond the related PR #1290.\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/jotego_jtcores_pr1290", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/jotego_jtcores_pr1290.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/jotego_jtcores_pr1290", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/jotego_jtcores_pr1290"}
{"instance_id": "jotego_jtcores_pr1316", "issue_text": "# jttrack and jtroadf: input issue\n\n- Source URL: https://github.com/jotego/jtcores/issues/1302\n\nHi, i realized a strange issue within Track & Field and Hyper Sports in jttrack (v856edaf, Mister v250828).\n\nBoth games use the stick and buttons 1-3. When pushing the stick left/right too fast, button 2 is triggered.\n\nHow to reproduce: track&field long jump, Hyper Sports swimming: push stick left/right real fast and it will automatically trigger button 2. In long jump he will start jumping way to early, in swimming he will breath also too early. If you push left/right with medium speed everything runs fine.\n\nVerified on two independant Misters, one with usb joystick, one with jamma adapter. The issue exists for player 1 and 2.\nThe games did run fine some time ago (maybe 1-2 years ago).\n\nIf helpful I can try to add a video of the problem.\n\n## Fetched Issue/PR Details\n\nTitle: jttrack and jtroadf: input issue (#1302)\n\nDescription: The reporter identified a bug in Track & Field and Hyper Sports (jttrack core). When rapidly moving the joystick left/right, button 2 is unintentionally triggered, causing premature game actions (early jumps in long jump, premature breathing in swimming). The bug occurs with both USB joysticks and JAMMA adapters across multiple Mister systems and affects both player slots. The reporter notes the games functioned correctly approximately one to two years prior.\n\nStatus: Closed (resolved via PR #1316)\nAssigned to: rp-jt\nLabels: core bug\nProject: JTCores (status: Done)\n\nComments: No comments were visible on the page beyond the initial issue body.\n\nLinked Issues: None beyond the resolving PR #1316.\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/jotego_jtcores_pr1316", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/jotego_jtcores_pr1316.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/jotego_jtcores_pr1316", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/jotego_jtcores_pr1316"}
{"instance_id": "jotego_jtcores_pr623", "issue_text": "# shouse: support for dragon spirit\n\n- Source URL: https://github.com/jotego/jtcores/issues/616\n\n\n## Fetched Issue/PR Details\n\nTitle: shouse: support for dragon spirit (#616)\n\nDescription: No description provided in the issue body. The ticket requests support for the arcade game \"Dragon Spirit\" within the shouse core on the JTCores emulation project.\n\nStatus: Closed (resolved via PR #623)\nAssignee: gyurco\nLabels: enhancement, new game\nMilestone: Namco System 1\nProject: JTCores (status: Done)\nOpened: April 15, 2024\n\nComments: No comments were visible on the page.\n\nLinked Issues: None beyond the resolving PR #623.\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/jotego_jtcores_pr623", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/jotego_jtcores_pr623.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/jotego_jtcores_pr623", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/jotego_jtcores_pr623"}
{"instance_id": "jotego_jtcores_pr630", "issue_text": "# Name not displayed in high scores board\n\n- Source URL: https://github.com/vertrex/Arcade-JujuDensetsu_MiSTer/issues/4\n\nWhen game over, entered name is not displayed on the high scores board.\n\n## Fetched Issue/PR Details\n\nTitle: Name not displayed in high scores board (#4)\n\nDescription: \"When game over, entered name is not displayed on the high scores board.\"\n\nStatus: Closed (repository archived May 6, 2024)\nAuthor: onthewaveagain\nOpened: April 1, 2024\n\nAdditional Details:\n- No assignees\n- No labels\n- No linked pull requests or development branches in this repository\n- A related PR exists: jotego/jtcores#630\n\nComments: None visible in the provided content.\n\nLinked Issues: Related PR jotego/jtcores#630.\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/jotego_jtcores_pr630", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/jotego_jtcores_pr630.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/jotego_jtcores_pr630", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/jotego_jtcores_pr630"}
{"instance_id": "jotego_jtcores_pr634", "issue_text": "# toki: latches\n\n- Source URL: https://github.com/jotego/jtcores/issues/606\n\nHi @vertrex\n\nThere are some latches in the current design. You will get a latch warning when using `jtcore` to compile. Latches tend to cause obscure bugs so it is better to have a fully synchronous design without them.\n\nPlease try to remove them.\n\nThanks\n\n## Fetched Issue/PR Details\n\nTitle: toki: latches (#606)\n\nDescription: jotego opened the issue on April 8, 2024, asking vertrex to remove latches from the design. The message states: \"There are some latches in the current design. You will get a latch warning when using `jtcore` to compile. Latches tend to cause obscure bugs so it is better to have a fully synchronous design without them.\"\n\nStatus: Closed (resolved via PR #634)\nAssignees: vertrex, jotego\nProject: JTCores\n\nComments: No comments from other users were included in the page content.\n\nLinked Issues: None beyond the resolving PR #634.\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/jotego_jtcores_pr634", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/jotego_jtcores_pr634.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/jotego_jtcores_pr634", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/jotego_jtcores_pr634"}
{"instance_id": "jotego_jtcores_pr654", "issue_text": "# toki: PCM pitch wrong?\n\n- Source URL: https://github.com/jotego/jtcores/issues/650\n\nSeveral people have reported that PCM/FX pitch is wrong. I have tried listening to it but cannot really tell. Maybe it's worth having a look, @vertrex\n\n## Fetched Issue/PR Details\n\nTitle: toki: PCM pitch wrong? (#650)\n\nDescription: jotego reported that \"Several people have reported that PCM/FX pitch is wrong. I have tried listening to it but cannot really tell. Maybe it's worth having a look, @vertrex\".\n\nStatus: Closed (linked to PR #654)\nAssignee: vertrex\nLabel: question (Further information is requested)\n\nComments: None visible on the page.\n\nLinked Issues: None beyond the resolving PR #654.\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/jotego_jtcores_pr654", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/jotego_jtcores_pr654.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/jotego_jtcores_pr654", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/jotego_jtcores_pr654"}
{"instance_id": "jotego_jtcores_pr797", "issue_text": "# riders: xmen. plane duplicated and misplaced for very large shrink values\n\n- Source URL: https://github.com/jotego/jtcores/issues/762\n\nIn the intro sequence, the Blackbird (X-men's plane) should appear from the distance. The zoom does not work well as it displays it duplicated for large reduction and it seems to offset it to the left and up/down. Eventually one of the two copies disappears because it seems to fall outside the screen. When the zoom shrinkage is not that aggressive, the ship appears correctly.\n\ntwo planes\n![20240810_093652-screen](https://github.com/user-attachments/assets/dc65c5e1-d6e1-4e82-9ae5-558824bb03d8)\n\ntwo planes, bottom one visible\n\n## Fetched Issue/PR Details\n\nTitle: riders: xmen. plane duplicated and misplaced for very large shrink values (#762)\n\nDescription: The issue describes a graphical glitch in the X-Men game intro sequence. When the Blackbird (the team's aircraft) zooms in from a distance using aggressive shrink values, it displays duplicated. The artifact also appears offset to the upper-left, with one copy eventually disappearing off-screen. The reporter notes: \"The zoom does not work well as it displays it duplicated for large reduction and it seems to offset it to the left and up/down.\" When the zoom scaling is less extreme, the plane renders correctly as a single object.\n\nStatus: Closed (marked as Done in the JTCores project)\nAssigned to: rp-jt\nLabel: core bug\nRelated PR: #797\n\nComments: No visible comments from other users; only the initial issue report with attached screenshots demonstrating the duplication artifact at various zoom levels.\n\nLinked Issues: None beyond the resolving PR #797.\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/jotego_jtcores_pr797", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/jotego_jtcores_pr797.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/jotego_jtcores_pr797", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/jotego_jtcores_pr797"}
{"instance_id": "jotego_jtcores_pr852", "issue_text": "# riders: ssriders title logo not displayed correctly for large zoom values\n\n- Source URL: https://github.com/jotego/jtcores/issues/761\n\nThis part of the animation is not visible in the core (42941f5d):\n\n(images from mame)\n\nssriders use the same object chipset than Parodius, so this might be related to #724\n\n## Fetched Issue/PR Details\n\nTitle: riders: ssriders title logo not displayed correctly for large zoom values (#761)\n\nDescription: The reporter says \"This part of the animation is not visible in the core\" and includes three screenshot references comparing the display in the core versus MAME. The issue notes that ssriders shares the same object chipset as Parodius, potentially linking it to issue #724.\n\nStatus: Closed (resolved via PR #852)\nAssignee: rp-jt\nLabel: core bug\nProject: JTCores (Status: Done)\nOpened: August 10, 2024\n\nComments: No visible comments on the page.\n\nLinked Issues: References #724 (jtparoda Parodius graphical glitch when using blue bell explosion super power) and resolving PR #852.\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/jotego_jtcores_pr852", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/jotego_jtcores_pr852.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/jotego_jtcores_pr852", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/jotego_jtcores_pr852"}
{"instance_id": "jotego_jtcores_pr854", "issue_text": "# paroda: objects in wrong horizontal position\n\n- Source URL: https://github.com/jotego/jtcores/issues/851\n\nIn the second stage of Parodius, in the tunnel where the big walking woman appears, when she is walking back to the left, the \"hair\" sprites of her headdress exchange positions and stay at a distance.\nThis is until she starts walking to the right and they go back to normal.\n\n## Fetched Issue/PR Details\n\nTitle: paroda: objects in wrong horizontal position (#851)\n\nDescription: The issue describes a visual glitch in Parodius during the second stage. When a large walking woman character traverses a tunnel moving leftward, the \"hair\" sprites of her headdress switch positions and become separated. The sprites normalize once she changes direction and walks rightward. An image was provided showing the incorrect sprite positioning during the leftward movement sequence.\n\nStatus: Closed (via PR #854)\nAssigned to: rp-jt\nLabel: core bug\nProject: JTCores\n\nComments: No comments visible.\n\nLinked Issues: Resolving PR #854.\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/jotego_jtcores_pr854", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/jotego_jtcores_pr854.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/jotego_jtcores_pr854", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/jotego_jtcores_pr854"}
{"instance_id": "jotego_jtcores_pr855", "issue_text": "# jtparoda: Parodius graphical glitch when using blue bell explosion super power\n\n- Source URL: https://github.com/jotego/jtcores/issues/724\n\nIn the foreground the sprites of the explosion are correctly displayed while the scaling is taking place. But behind it appears the image of the explosion split into two halves horizontally and inverted vertically.\n\n## Fetched Issue/PR Details\n\nTitle: jtparoda: Parodius graphical glitch when using blue bell explosion super power (#724)\n\nDescription: The issue reports a graphical glitch in Parodius when the blue bell explosion super power is used. While the explosion sprites display correctly in the foreground during scaling, a corrupted version appears behind them: \"the image of the explosion split into two halves horizontally and inverted vertically.\"\n\nStatus: Open (marked as Done in project status)\nAssignee: rp-jt\nLabels: core bug\nReporter: RndMnkIII\nOpened: July 6, 2024\n\nComments: No comments visible on the page.\n\nLinked Issues: Resolving PR #855.\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/jotego_jtcores_pr855", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/jotego_jtcores_pr855.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/jotego_jtcores_pr855", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/jotego_jtcores_pr855"}
{"instance_id": "jotego_jtcores_pr863", "issue_text": "# jt1942 core display bug on CRT 15khz\n\n- Source URL: https://github.com/jotego/jtcores/issues/844\n\nJt1942 core has a graphical glitch when displayed on CRT. The last line at the bottom of the screen is missing and is displayed at the top instead (Tested on MiSTer and MiST).\n\n## Fetched Issue/PR Details\n\nTitle: jt1942 core display bug on CRT 15khz (#844)\n\nDescription: The jt1942 core exhibits a graphical glitch when displayed on CRT monitors. \"The last line at the bottom of the screen is missing and is displayed at the top instead.\" Tested on both MiSTer and MiST platforms.\n\nStatus: Closed (resolved via PR #863)\nAssignee: rp-jt\nLabels: core bug\nReporter: tdelage26\nOpened: October 13, 2024\nProject: JTCores (status: Done)\n\nComments: No additional comments were visible on the page.\n\nLinked Issues: Resolving PR #863.\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/jotego_jtcores_pr863", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/jotego_jtcores_pr863.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/jotego_jtcores_pr863", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/jotego_jtcores_pr863"}
{"instance_id": "jotego_jtcores_pr871", "issue_text": "# WWF Superstars - Analogue Pocket -- Right side of screen shows graphics\n\n- Source URL: https://github.com/jotego/jtcores/issues/866\n\nThe screen is not centered and the right column shows graphic assets. It does this for every Display Mode. Everything is otherwise playable. Cheers.\n\n## Fetched Issue/PR Details\n\nTitle: WWF Superstars - Analogue Pocket -- Right side of screen shows graphics (#866)\n\nDescription: \"The screen is not centered and the right column shows graphic assets. It does this for every Display Mode. Everything is otherwise playable.\"\n\nStatus: Closed (resolved via PR #871)\nAssignee: rp-jt\nLabel: core bug\n\nComments: The GitHub page indicated an error while loading, so additional comments and discussion details were not visible.\n\nLinked Issues: Resolving PR #871.\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/jotego_jtcores_pr871", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/jotego_jtcores_pr871.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/jotego_jtcores_pr871", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/jotego_jtcores_pr871"}
{"instance_id": "jotego_jtcores_pr875", "issue_text": "# jts18 Moonwalker: Player 3 isn't able to coin up properly or start\n\n- Source URL: https://github.com/jotego/jtcores/issues/872\n\nWhen playing Moonwalker the 3rd player is not able to coin up or join the the game (tested on Japan, World and US sets)\nThis is when the dip switches are set for 3 players and the coin chute is set to either common or individual.\nWhile on individual coin chute with 3 players, the coin button for player 1 inserts for player 3, still player 3 start button will not work\n\n\nAlso when the dips are set for 2 players and the coin chute is set individual, the coin buttons are reversed in game\nCoin 1 inserts for Player 2\nCoin 2 inserts for Player 1\n\n## Fetched Issue/PR Details\n\nTitle: jts18 Moonwalker: Player 3 isn't able to coin up properly or start (#872)\n\nDescription: The reported issues concern input handling in the Moonwalker arcade core:\n- 3-player mode: Player 3 cannot coin up or join games when the dipswitch is set for 3 players, regardless of coin chute configuration (common or individual).\n- Individual coin chute with 3 players: Player 1's coin button incorrectly inserts credits for Player 3, and Player 3's start button remains unresponsive.\n- 2-player mode with individual coins: The coin button inputs are reversed; Coin 1 inserts for Player 2 and Coin 2 inserts for Player 1.\n\nTested across Japan, World, and US ROM sets.\n\nStatus: Closed (Done)\nLinked PR: #875\n\nComments: No additional comments visible.\n\nLinked Issues: Resolving PR #875.\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/jotego_jtcores_pr875", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/jotego_jtcores_pr875.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/jotego_jtcores_pr875", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/jotego_jtcores_pr875"}
{"instance_id": "jotego_jtcores_pr893", "issue_text": "# JTWC Blocked movements\n\n- Source URL: https://github.com/jotego/jtcores/issues/887\n\nTehkan when moving left or right it stops moving up and down ... I have tried everything but it remains the same ... both USB pad and Sanwa arcade. (QMTECH fpga board) .. I have discovered that if I assign movement The movements work well with buttons and not a joystick. Greetings.\n\n## Fetched Issue/PR Details\n\nTitle: JTWC Blocked movements (#887)\n\nDescription: The reporter describes a control issue with the Tehkan game where \"when moving left or right it stops moving up and down.\" They tested with multiple input devices (USB pad and Sanwa arcade stick) on a QMTECH FPGA board. The reporter discovered the movements function properly when assigned to buttons rather than joystick input.\n\nStatus: Closed (linked to PR #893)\nAssignees: jtmiki, rp-jt\nLabel: core bug\n\nComments: No comments from other users visible. The issue describes input handling where simultaneous directional inputs are blocked during joystick operation but work correctly with button-based controls.\n\nLinked Issues: Resolving PR #893.\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/jotego_jtcores_pr893", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/jotego_jtcores_pr893.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/jotego_jtcores_pr893", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/jotego_jtcores_pr893"}
{"instance_id": "jotego_jtcores_pr951", "issue_text": "# Screen rotation on SiDi128 is broken since version 6d1d2ef of cores\n\n- Source URL: https://github.com/jotego/jtcores/issues/950\n\nCommit 8d403ed broke screen rotation on SiDi128. `bitcounter` is set to a wrong value.\n\nThis works better:\n\n```diff\n--- a/modules/jtframe/hdl/video/rotate/unsigned_division.v\n+++ b/modules/jtframe/hdl/video/rotate/unsigned_division.v\n@@ -37,7 +37,7 @@ always @(posedge clk) begin\n                                        quot<=dividend;\n                                        div<=divisor;\n                                        /* verilator lint_off WIDTH */\n-                                       bitcounter<={widthlog2{1'd1}};\n+                                       bitcounter<=(widthlog2[widthlog2-1:0]-1'd1);\n                                        /* verilator lint_on WIDTH */\n                                        state <= RUN;\n                                end                     \n```\n\nThanks!\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/jotego_jtcores_pr951", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/jotego_jtcores_pr951.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/jotego_jtcores_pr951", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/jotego_jtcores_pr951"}
{"instance_id": "jotego_jtcores_pr960", "issue_text": "# Adjusting Volume using keyboard does not work on pocket.\n\n- Source URL: https://github.com/jotego/jtcores/issues/935\n\nOn Mister it is possible to adjust the volume using F4 and F5 but this does not work on Analogue Pocket.\nSince it is not possible to adjust the volume on Analogue Pocket while in dock It would be useful if this was working.\n\n## Fetched Issue/PR Details\n\nTitle: Adjusting Volume using keyboard does not work on pocket. (#935)\n\nDescription: The reporter notes that on Mister, volume adjustment via F4 and F5 keyboard keys functions properly, but this capability is absent on Analogue Pocket. They request implementation of this feature, particularly since manual volume adjustment isn't possible while the Pocket is docked.\n\nStatus: Closed (resolved via PR #960)\nAssignee: rp-jt\nLabel: Enhancement\nProject: JTCores\nCreated: January 17, 2025\n\nComments: None visible on the page.\n\nLinked Issues: Resolving PR #960.\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/jotego_jtcores_pr960", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/jotego_jtcores_pr960.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/jotego_jtcores_pr960", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/jotego_jtcores_pr960"}
{"instance_id": "kumarrishav14_AMBA_APB_pr18", "issue_text": "# Add dut\n\n- Source URL: https://github.com/kumarrishav14/AMBA_APB/issues/15\n\nImplement a DUT which is a simple memory having **APB interface**\n\n## Fetched Issue/PR Details\n\nTitle: Add dut (#15)\n\nDescription: The issue requests implementation of a DUT (Device Under Test) component described as \"a simple memory having APB interface.\"\n\nRepository: kumarrishav14/AMBA_APB\nStatus: Closed (via PR #18)\nAssignee: kumarrishav14\nLabel: New Feature\nMilestone: version 1 release\nOpened: November 10, 2020\n\nComments: No comments visible.\n\nLinked Issues: Resolving PR #18.\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/kumarrishav14_AMBA_APB_pr18", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/kumarrishav14_AMBA_APB_pr18.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/kumarrishav14_AMBA_APB_pr18", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/kumarrishav14_AMBA_APB_pr18"}
{"instance_id": "lnis-uofu_OpenFPGA_pr2164", "issue_text": "# Support don't care bit 'x' in the mode bits definition of OpenFPGA Architecture Language\n\n- Source URL: https://github.com/lnis-uofu/OpenFPGA/issues/2161\n\n**Is your feature request related to a problem? Please describe.**\nWhen integrating custom blocks containing fracturable mode selection bits, it happens that a pb_type in a operating mode only requires to update partial mode-selection bits. \nFor example, a multiplier with the following fracturable operating modes:\n\n- Single 18x18 - Combinational\n- Single 18x18 with input registers\n- Dual 9x9 - Combinational\n- Dual 9x9 with input registers, each 9x9 can operate separately.\n\nIn the case, when users try to map two multiplier primitives\n\n- 9x9 combinational\n- 9x9 with input register\n\ninto a logic block (assume each logic block contains only 1 fracturable multiplier)\n\nWe want VPR to select the best location for each primitive in the logic block.\nTherefore, the mode selection bits for each primitive 9x9 with input register should require to update only part of the mode-selection bits of its physical pb_type.\n\n```\n<pb_type name=\"mult_16\" physical_mode_name=\"mult_16x16\"/>\n<!-- The first bit switches between 9x9 and 18x18 mode -->\n<!-- The second bit switches between enable/disable input register for the first 9x9 -->\n<!-- The third bit switches between enable/disable input register for the second 9x9 -->\n<pb_type name=\"mult_16[mult_16x16].mult_16x16_slice.mult_16x16\" circuit_model_name=\"frac_mult_16x16\" mode_bits=\"100\"/>\n<!-- The first 9x9 with register should only alter the second bit -->\n<pb_type name=\"mult_16[mult_8x8].mult_8x8_slice.mult_8x8_regin_0\" physical_pb_type_name=\"mult_16[mult_16x16].mult_16x16_slice.mult_16x16\" mode_bits=\"01x\"/>\n<!-- The first 9x9 with register should only alter the second bit -->\n<pb_type name=\"mult_16[mult_8x8].mult_8x8_slice.mult_8x8_comb_0\" physical_pb_type_name=\"mult_16[mult_16x16].mult_16x16_slice.mult_16x16\" mode_bits=\"00x\"/>\n<!-- The second 9x9 with register should only alter the third bit -->\n<pb_type name=\"mult_16[mult_8x8].mult_8x8_slice.mult_8x8_regin_1\" physical_pb_type_name=\"mult_16[mult_16x16].mult_16x16_slice.mult_16x16\" mode_bits=\"0x1\"/>\n<!-- The second 9x9 with register should only alter the third bit -->\n<pb_type name=\"mult_16[mult_8x8].mult_8x8_slice.mult_8x8_comb_1\" physical_pb_type_name=\"mult_16[mult_16x16].mult_16x16_slice.mult_16x16\" mode_bits=\"0x0\"/>\n```\n\n**Describe the solution you'd like**\n\n\nThe mode bits should support the don't care bit ``x``.\nWhen a bit is defined as 'x', the mode-selection bit of operating pb_type will not update the corresponding bit of its physical pb_type.\nAs such, partial mode bit mapping is achieved.\n**Only the operating modes allow don't care bits**\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/lnis-uofu_OpenFPGA_pr2164", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/lnis-uofu_OpenFPGA_pr2164.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/lnis-uofu_OpenFPGA_pr2164", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/lnis-uofu_OpenFPGA_pr2164"}
{"instance_id": "lowRISC_ibex_pr1821", "issue_text": "# [dv] Add MHPM Counter number param to SpikeCosim\n\nInstance: lowRISC_ibex_pr1821\nSource: https://github.com/lowRISC/ibex/pull/1821\nFetched: 2026-04-26\nRepository: lowRISC/ibex\nPull request: #1821\nAuthor: ctopal\nState: closed\nBase branch: master\nHead branch: mhpmcounter_spikecosim\nCreated: 2022-09-28T16:20:26Z\nUpdated: 2022-10-11T14:52:49Z\nClosed: 2022-10-11T14:52:42Z\nMerged: 2022-10-11T14:52:42Z\n\nThis commit adds another field in SpikeCosim class so that Spike can hardcode the correct event registers.\r\n\r\nSigned-off-by: Canberk Topal <ctopal@lowrisc.org>\r\n\r\nNeeds: https://github.com/lowRISC/riscv-isa-sim/pull/17\r\n\r\nResolves https://github.com/lowRISC/ibex/issues/1820\n\n## Local Reproducer Notes\n\n# lowRISC_ibex_pr1821\n\nMinimal fail-to-pass Verilator case for passing the MHPM counter count into the Spike cosim checker.\n\nThe buggy checker ignores the configured MHPM counter count. The patch forwards it to the observable cosim creation configuration.\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/lowRISC_ibex_pr1821", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/lowRISC_ibex_pr1821.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/lowRISC_ibex_pr1821", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/lowRISC_ibex_pr1821"}
{"instance_id": "lowRISC_ibex_pr1839", "issue_text": "# [pmp] Instruction straddling two TOR regions cosim mismatch\n\n- Source URL: https://github.com/lowRISC/ibex/pull/1839\n\nWhen running the following test:\n`make -j1 --keep-going IBEX_CONFIG=opentitan ITERATIONS=1 TEST=riscv_epmp_mml_test WAVES=0 COV=0 SEED=30325`\n\nIbex and Spike have different behavior. Spike throws an instruction access fault exception for the address `0x80005cc4`. The TOR region ends at `0x80005cc4`, which is the expected behavior.\n\nI think Ibex somehow does not perform the check for fetched instructions properly. In this test case there is a branch instruction that straddles two PMP entries, so Ibex must do two requests.\n\nIbex commit: 0e396d594435c0acca9df785ac40309c76576cc3\nSpike commit: 0dc2de5d76add7b218b31053792a676973034b9e\n\n> estimate 4\n\n## Fetched Issue/PR Details\n\nTitle: [if,pmp] Check second bit instead of third for instruction alignment (PR #1839)\n\nDescription: The PR addresses a bug where Ibex was checking the wrong bit when looking at PMP errors and when to count the error it received from instruction fetch +2. This PR closes issue #1837 (\"[pmp] Instruction straddling two TOR regions cosim mismatch\").\n\nStatus: Merged\nAuthor: marnovandermaas\nMerge Date: October 6, 2022\nReviewer: ctopal (approved)\nLabel: Type:Bug\n\nComments:\n- marnovandermaas (Oct 5, 2022): Provided the description above and noted this fixes a cosmetic simulation mismatch related to PMP instruction alignment checking.\n- ctopal (Oct 6, 2022): Approved the changes after reviewing file modifications.\n- GregAC (Oct 6, 2022): Added the \"Type:Bug\" label to categorize this as a bug fix.\n\nLinked Issues: Closes #1837 (the cosim mismatch reported above).\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/lowRISC_ibex_pr1839", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/lowRISC_ibex_pr1839.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/lowRISC_ibex_pr1839", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/lowRISC_ibex_pr1839"}
{"instance_id": "lowRISC_ibex_pr1865", "issue_text": "Observed Behavior\nThe core_busy_o output signal of the non-lockstep core is used to gate the core clock, which is used by the regular Ibex core and its lockstep counterpart.\n\nibex/rtl/ibex_top.sv\n\nLines 211 to 219 in 3943a4e\n\n assign clock_en     = core_busy_q | debug_req_i | irq_pending | irq_nm_i; \n assign core_sleep_o = ~clock_en; \n  \n prim_clock_gating core_clock_gate_i ( \n   .clk_i    (clk_i), \n   .en_i     (clock_en), \n   .test_en_i(test_en_i), \n   .clk_o    (clk) \n ); \n\nibex/rtl/ibex_top.sv\n\nLines 286 to 287 in 3943a4e\n\n ) u_ibex_core ( \n   .clk_i(clk), \n\nibex/rtl/ibex_top.sv\n\nLines 927 to 928 in 3943a4e\n\n ) u_ibex_lockstep ( \n   .clk_i                  (clk), \nThis means that the lockstep core gets gated in the same clock cycle as the regular core, even though the lockstep core is a few cycles delayed. A low-glitch in the core_busy_o output of the non-lockstep core thus does not lead to a comparison mismatch and a major alert because the lockstep core is already clock-gated when it would produce the value of core_busy_o that is used in the comparison.\n\nibex/rtl/ibex_lockstep.sv\n\nLines 453 to 454 in 3943a4e\n\n assign outputs_mismatch       = enable_cmp_q & (shadow_outputs_q != core_outputs_q[0]); \n assign alert_major_internal_o = outputs_mismatch | shadow_alert_major_internal; \nExpected Behavior\nA low-glitch/mismatch in the core_busy_o output signal of the non-lockstep core should lead to a major alert by the lockstep core.\n\nSteps to reproduce the issue\nRun the chip_sw_ibex_lockstep_glitch test in OpenTitan (currently in lowRISC/opentitan#15221) and override port_idx to the index of core_busy_o in output_ports.", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/lowRISC_ibex_pr1865", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/lowRISC_ibex_pr1865.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/lowRISC_ibex_pr1865", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/lowRISC_ibex_pr1865"}
{"instance_id": "lowRISC_ibex_pr1872", "issue_text": "# insn_trigger_exception coverpoint does not work\n\n- Source URL: https://github.com/lowRISC/ibex/pull/1872\n\nThe test riscv_debug_triggers_test added in #1801 generates stimulus to hit [this coverpoint](https://github.com/lowRISC/ibex/blob/ce536ae47677e952de02b7421e1b78efb5761ab2/dv/uvm/core_ibex/fcov/core_ibex_fcov_if.sv#L502), but it does not trigger.\n\nREPRO\n- Checkout https://github.com/lowRISC/ibex/pull/1801\n- Run: make TEST=riscv_debug_triggers_test ITERATIONS=1 SEED=14664 COV=1 -j12 -ik\n- The instruction/event that should trigger this coverpoint can be seen retiring at t = 1010124 ns\n\n## Fetched Issue/PR Details\n\nTitle: Misc fixes (PR #1872)\n\nDescription: PR contains three commits and fixes issue #1863:\n1. [rtl] Fix ebreak debug cause - \"We should only indicate an ebreak debug cause if an ebreak leads to a debug entry (otherwise when single stepping over an ebreak that traps to an exception we incorrectly enter debug mode with an ebreak cause).\"\n2. [dv] Remove cp_insn_trigger_exception coverpoint - \"This coverpoint does not make sense. The hardware breakpoint is triggered as the instruction moves into the ID/EX stage so it never has a chance to take an exception (it effectively never begins executing).\"\n3. [dv] Add single step over exception coverpoint.\n\nStatus: Merged (Oct 26, 2022)\nAuthor: GregAC\nBranch: GregAC:misc_fixes -> lowRISC:master\n\nReview Activity:\n- hcallahan-lowrisc approved the changes on Oct 26, 2022\n- ctopal was requested for review\n- PR merged by GregAC on Oct 26, 2022; branch deleted after merge\n\nLinked Issues: Closes issue #1863 (\"insn_trigger_exception coverpoint does not work\").\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/lowRISC_ibex_pr1872", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/lowRISC_ibex_pr1872.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/lowRISC_ibex_pr1872", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/lowRISC_ibex_pr1872"}
{"instance_id": "lowRISC_ibex_pr1917", "issue_text": "# [dv] Out of bounds access in dside access tracking logic\n\n- Source URL: https://github.com/lowRISC/ibex/pull/1917\n\nThis line: https://github.com/lowRISC/ibex/blob/056cb44ff75f797898709546ea1b0fd08d862e1a/rtl/ibex_top.sv#L1092\n\nUses `i - 1` and it's possible to evaluate this condition when `i == 0` giving an out of bounds access. This logic needs refactoring to more explicitly split out the `i == 0` case from the others to ensure this does not occur.\n\n> estimate 1\n\n## Fetched Issue/PR Details\n\nTitle: [fpv] Fix linting issues in oustanding access tracking logic (PR #1917)\n\nDescription: \"This refactors the code to avoid a -1 index access that caused no issues in functional verification but caused lint errors and is problematic for formal tools. Fixes #1799.\"\n\nAuthor: GregAC\nStatus: Merged (November 14, 2022)\nTarget: lowRISC/ibex master branch\nRelated Issue: #1799 (\"[dv] Out of bounds access in dside access tracking logic\")\n\nComments and Activity:\n- GitHub Actions Bot (November 9, 2022): Verible Verilog Lint flagged \"All generate block statements must have a label [Style: generate-statements]\".\n- GregAC force-pushed corrections on November 9 and November 12, 2022 to address linting feedback.\n- ctopal approved the changes on November 14, 2022.\n- GregAC merged the PR and deleted the tracking_logic_fix branch on November 14, 2022.\n\nLinked Issues: Closes #1799.\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/lowRISC_ibex_pr1917", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/lowRISC_ibex_pr1917.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/lowRISC_ibex_pr1917", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/lowRISC_ibex_pr1917"}
{"instance_id": "lowRISC_ibex_pr2166", "issue_text": "# Security vulnerability: Ibex leaks data when multiplication is aborted\n\n<!--\r\nThank you for your interest in Ibex. We are continuously improving Ibex, and your bug report will help us with that. To help us understand and reproduce your problem as quickly as possible we have prepared a little template below.\r\n\r\nNo text in blocks starting with < !-- will be shown in the final bug report.\r\n\r\nYou can also copy/paste images into the bug report, and you can attach files to it by simply dragging them into the issue window.\r\n-->\r\n\r\n## Observed Behavior\r\n<!--\r\nPlease describe the problem you saw. Include waveforms (in VCD or Verilator/GtkWave FST format only please) and log files if possible.\r\n-->\r\n\r\nA MULH instruction that is aborted by an unsolicited memory error response leaks information about its input values to a subsequent MUL instruction. The subsequent MUL instruction stores a value dependent on MULH's operands into its result register, thus produces a wrong result and leaking information.\r\n\r\nI believe that the reason is that the multiplication's module's internal state machine is not reset in case of an abort. \r\n\r\n## Expected Behavior\r\n<!-- Please describe the behavior you expected to see instead. -->\r\nIbex should not leak data in case of external interface errors.\r\n\r\n## Steps to reproduce the issue\r\n<!--\r\nPlease help us to reproduce the issue you're seeing by including a detailed description of what you did to get to the problem.\r\n\r\nFor example:\r\n* What command did you run? (Also include the output of the command.)\r\n* What parameters/defines did you set?\r\n* Did you make modifications to the source code?\r\n-->\r\nThe testbench in https://github.com/KatCe/ibex/tree/bug_mulh_reg_leakage/dv/bug_mulh_reg_leakage demonstrates the problem.\r\nThis testbench uses the default configuration. We have also observed the bug in secure configuration with the parameters commented in the testbench.\r\n\r\n## My Environment\r\n\r\n<!--\r\nLet us know how you're using Ibex. This helps us to better understand your problem and find a solution more quickly.\r\n-->\r\n\r\n**EDA tool and version:**\r\n<!--\r\nIf you are using an EDA tool to work with Ibex let us know which tool and which version you're using.\r\nFor example, \"Xilinx Vivado 2020.1\" or \"Synopsys VCS 2020.03-SP1\"\r\n-->\r\nQuesta Sim-64, Version 2022.3_1 linux_x86_64 Aug 12 2022\r\n\r\n**Operating system:**\r\n<!--\r\nPlease let us know the operating system/Linux distribution you're using.\r\nFor example \"Ubuntu Linux 18.04\" or \"CentOS 7.3\".\r\n-->\r\nUbuntu 20.04.6 LTS\r\n**Version of the Ibex source code:**\r\n<!--\r\nWhich version of the Ibex source code are you using?\r\nYou can call `git rev-parse HEAD` in your Ibex source directory to get this information.\r\nPlease also let us know if you have made changes to the code.\r\n-->\r\n5a8a1a99930afbb9efe107ff2c80d482239d7a5f\r\nThe exact list of files run by the test bench can be found in https://github.com/KatCe/ibex/blob/bug_mulh_reg_leakage/dv/bug_mulh_reg_leakage/flist.f\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/lowRISC_ibex_pr2166", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/lowRISC_ibex_pr2166.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/lowRISC_ibex_pr2166", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/lowRISC_ibex_pr2166"}
{"instance_id": "lowRISC_ibex_pr2214", "issue_text": "# Pipeline not being flushed on PMP register clears\n\n- Source URL: https://github.com/lowRISC/ibex/pull/2214\n\nIn [this commit](https://github.com/lowRISC/ibex/commit/46404cf86f60f72fb84a2bc693d2ab08011bdb37) the pipeline was made to flush on changes to PMP registers, changes made via `CSR_OP_CLEAR` however are missed.\n\nThis is likely because prior to this commit only mstatus and mie were listed, and clearing is safe for those.\n\nThis meant that instructions being fetched were passing PMP checks which they should not have been.\n\n## Fetched Issue/PR Details\n\nTitle: [rtl] Flush pipe on all CSR modifications (PR #2214)\n\nDescription: This fix addresses issue #2193, where bit clears in PMP-related CSRs weren't immediately applying to instructions already in the fetch stage due to missing pipeline flushes. The solution flushes the pipeline on all CSR modifications to make the system more resilient against similar oversights in the future.\n\nKey Changes:\n- CSR address reading optimization: Routes CSR addresses directly from the decoder to the ibex_cs_registers module rather than through operand muxes, improving timing.\n- Pipeline flush on CSR modifications: Implements a whitelist where most CSR writes trigger pipeline flushes, but specific CSRs (mscratch, mepc) are excluded since they don't affect instruction execution in the fetch stage.\n\nNotable Discussion:\n- Performance considerations: Reviewers raised concerns about CSR write frequency during exception handling. The author acknowledged that while some CSR operations (like csrrw for stack switching) are performance-sensitive, the actual performance impact is limited since Ibex has only a single fetch stage and CSR instructions typically aren't in tight loops.\n- Whitelist rationale: The team determined that mscratch and mepc don't require flushes - mscratch is purely a temporary storage location, and mepc is only read during exception returns, not during fetch-stage instruction execution.\n\nReview and Merge:\n- Approved by: vogelpi and marnovandermaas\n- Merged: February 17, 2025\n- Status: Merged into master\n\nThe PR underwent multiple iterations and force-pushes to address lint issues and incorporate feedback about the whitelist approach.\n\nLinked Issues: Fixes #2193.\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/lowRISC_ibex_pr2214", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/lowRISC_ibex_pr2214.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/lowRISC_ibex_pr2214", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/lowRISC_ibex_pr2214"}
{"instance_id": "lowRISC_ibex_pr2241", "issue_text": "# Undriven signal in ibex_register_file_fpga.sv\n\n## Observed Behavior\n<!--\nPlease describe the problem you saw. Include waveforms (in VCD or Verilator/GtkWave FST format only please) and log files if possible.\n-->\n\nOn the following line, `oh_raddr_a_err` is undriven if `RdataMuxCheck` is zero.\n\nhttps://github.com/lowRISC/ibex/blob/master/rtl/ibex_register_file_fpga.sv#L54\n\nThis was seen in Verilator linting when trying to integrate Ibex into my design.  I've searched the VLT files for any relevant waivers but can't see any relating to this level of hierarchy.\n\n```\nERROR: %Warning-UNDRIVEN: src/lowrisc_export_ibex_top_0/rtl/ibex_register_file_fpga.sv:54:9: Signal is not driven: 'oh_raddr_a_err'\n                                                                                    : ... note: In instance 'ibex_wb.u_top..gen_regfile_fpga.register_file_i'\n   54 |   logic oh_raddr_a_err, oh_raddr_b_err, oh_we_err;\n      |         ^~~~~~~~~~~~~~\n                   ... For warning description see https://verilator.org/warn/UNDRIVEN?v=5.024\n                   ... Use \"/* verilator lint_off UNDRIVEN */\" and lint_on around source to disable this message.\n%Warning-UNDRIVEN: src/lowrisc_export_ibex_top_0/rtl/ibex_register_file_fpga.sv:54:25: Signal is not driven: 'oh_raddr_b_err'\n                                                                                     : ... note: In instance 'ibex_wb.u_top..gen_regfile_fpga.register_file_i'\n   54 |   logic oh_raddr_a_err, oh_raddr_b_err, oh_we_err;\n      |                         ^~~~~~~~~~~~~~\n%Error: Exiting due to 2 warning(s)\nmake: *** [Makefile:23: lint-only] Error 1\n\nERROR: Failed to build nq:ip:ibex_wb:0 : '['make', 'lint-only']' exited with an error: 2\n```\n\n## Expected Behavior\n<!-- Please describe the behavior you expected to see instead. -->\nTis lint clean please.\n\n## Steps to reproduce the issue\n<!--\nPlease help us to reproduce the issue you're seeing by including a detailed description of what you did to get to the problem.\n\nFor example:\n* What command did you run? (Also include the output of the command.)\n* What parameters/defines did you set?\n* Did you make modifications to the source code?\n-->\n\nI'm trying to export the Ibex RTL source code to get around the fact that you are using a custom version of Fusesoc.  I'm instantiating Ibex with the following parameters:\n\n```\n  ibex_top #(\n      .RV32M  (ibex_pkg::RV32MSlow),\n      .RV32B  (ibex_pkg::RV32BNone),\n      .RegFile(ibex_pkg::RegFileFPGA)\n  ) u_top (\n<snip>\n```\n\nand then running a Verilator lint using the standard Fusesoc/Edalize flow.\n\n## My Environment\n\n<!--\nLet us know how you're using Ibex. This helps us to better understand your problem and find a solution more quickly.\n-->\n\n**EDA tool and version:**\nVerilator 5.024 2024-04-05 rev v5.024\n<!--\nIf you are using an EDA tool to work with Ibex let us know which tool and which version you're using.\nFor example, \"Xilinx Vivado 2020.1\" or \"Synopsys VCS 2020.03-SP1\"\n-->\n\n**Operating system:**\nRocky 9.4\n<!--\nPlease let us know the operating system/Linux distribution you're using.\nFor example \"Ubuntu Linux 18.04\" or \"CentOS 7.3\".\n-->\n\n**Version of the Ibex source code:**\n8f4c75c5e43e61b994248307c814e01860303056\n<!--\nWhich version of the Ibex source code are you using?\nYou can call `git rev-parse HEAD` in your Ibex source directory to get this information.\nPlease also let us know if you have made changes to the code.\n-->\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/lowRISC_ibex_pr2241", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/lowRISC_ibex_pr2241.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/lowRISC_ibex_pr2241", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/lowRISC_ibex_pr2241"}
{"instance_id": "lowRISC_ibex_pr2251", "issue_text": "# Ibex core assertion NoExecWhenFetchEnableNotOn not gated correctly.\n\n## Observed Behavior\nI'm seeing the NoExecWhenFetchEnableNotOn assertion fire inside of ibex_core.sv in a case where I'm not using the lockstep mode.  I have a single instance of Ibex with the default parameters including `parameter bit SecureIbex = 1'b0,`\n\nThe assertion in question is part of the following code block:\n\n```\n  // Keep track of the PC last seen in the ID stage when fetch is disabled\n  logic       [31:0] pc_at_fetch_disable;\n  ibex_mubi_t        last_fetch_enable;\n\n  always_ff @(posedge clk_i or negedge rst_ni) begin\n    if (!rst_ni) begin\n      pc_at_fetch_disable <= '0;\n      last_fetch_enable   <= '0;\n    end else begin\n      last_fetch_enable <= fetch_enable_i;\n\n      if ((fetch_enable_i != IbexMuBiOn) && (last_fetch_enable == IbexMuBiOn)) begin\n        pc_at_fetch_disable <= pc_id;\n      end\n    end\n  end\n\n  // When fetch is disabled no instructions should be executed. Once fetch is disabled either the\n  // ID/EX stage is not valid or the PC of the ID/EX stage must remain as it was at disable. The\n  // ID/EX valid should not ressert once it has been cleared.\n  `ASSERT(\n      NoExecWhenFetchEnableNotOn,\n      fetch_enable_i != IbexMuBiOn |=> (~instr_valid_id || (pc_id == pc_at_fetch_disable)) && ~$rose\n      (instr_valid_id))\n```\n\nMy understanding from reading the documentation about `fetch_enable_i` was that I just needed to tie the LSB to 1.  So I'm driving the input port to `4'b0001`.  If that is correct, then it looks like this assertion shouldn't be firing.  It should probably only be used when `SecureIbex == 1`?\n\nThe assertion fires for the first valid instruction fetched after reset.\n\n## Expected Behavior\nNo assertion should fire - unless I'm missing the fact that I'm doing something stupid.\n\n## Steps to reproduce the issue\nMy instantiation looks like:\n```\n  ibex_top #(\n      .RV32M  (ibex_pkg::RV32MSlow),\n      .RV32B  (ibex_pkg::RV32BNone),\n      .RegFile(ibex_pkg::RegFileFPGA)\n  ) u_top (\n      // Clock and reset\n      .clk_i      (clk),\n      .rst_ni     (!rst),\n      .test_en_i  ('0),\n      .scan_rst_ni('0),\n      .ram_cfg_i  ('0),\n\n      // Configuration\n      .hart_id_i  ('0),\n      .boot_addr_i('0),\n\n      // Instruction memory interface\n      .instr_req_o       (instr_req),\n      .instr_gnt_i       (instr_gnt),\n      .instr_rvalid_i    (instr_rvalid),\n      .instr_addr_o      (instr_addr),\n      .instr_rdata_i     (instr_rdata),\n      .instr_rdata_intg_i('0),\n      .instr_err_i       (instr_err),\n\n      // Data memory interface\n      .data_req_o       (data_req),\n      .data_gnt_i       (data_gnt),\n      .data_rvalid_i    (data_rvalid),\n      .data_we_o        (data_we),\n      .data_be_o        (data_be),\n      .data_addr_o      (data_addr),\n      .data_wdata_o     (data_wdata),\n      .data_wdata_intg_o(),\n      .data_rdata_i     (data_rdata),\n      .data_rdata_intg_i('0),\n      .data_err_i       (data_err),\n\n      // Interrupt inputs\n      .irq_software_i('0),\n      .irq_timer_i   (timer_irq),\n      .irq_external_i('0),\n      .irq_fast_i    ('0),\n      .irq_nm_i      ('0),\n\n      // Scrambling Interface\n      .scramble_key_valid_i('0),\n      .scramble_key_i      ('0),\n      .scramble_nonce_i    ('0),\n      .scramble_req_o      (),\n\n      // Debug interface\n      .debug_req_i        ('0),\n      .crash_dump_o       (),\n      .double_fault_seen_o(),\n\n      // Special control signals\n      .fetch_enable_i        (4'b0001),\n      .alert_minor_o         (),\n      .alert_major_internal_o(),\n      .alert_major_bus_o     (),\n      .core_sleep_o          ()\n  );\n```\n\n## My Environment\n\n**EDA tool and version:**\nCadence Xcelium 24.03\n\n**Operating system:**\nRHEL 9.5\n\n**Version of the Ibex source code:**\n8f4c75c5e43e61b994248307c814e01860303056\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/lowRISC_ibex_pr2251", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/lowRISC_ibex_pr2251.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/lowRISC_ibex_pr2251", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/lowRISC_ibex_pr2251"}
{"instance_id": "lowRISC_ibex_pr2261", "issue_text": "# simulator report error\n\n<!--\nThank you for your interest in Ibex. We are continuously improving Ibex, and your bug report will help us with that. To help us understand and reproduce your problem as quickly as possible we have prepared a little template below.\n\nNo text in blocks starting with < !-- will be shown in the final bug report.\n\nYou can also copy/paste images into the bug report, and you can attach files to it by simply dragging them into the issue window.\n-->\n\n## Observed Behavior\nTest ibex in verilator with cosim, simulator report error illegal instruction.\n```\n001003e8 <main>:\n  1003e8:\t1141                \taddi\tsp,sp,-16\n  1003ea:\tc606                \tsw\tra,12(sp)\n  1003ec:\t0000                \tunimp                # <---  This is the illegal instruction!\n  1003ee:\t0000                \tunimp\n  1003f0:\t37b9                \tjal\t10033e <func>\n  1003f2:\t00000517          \tauipc\ta0,0x0\n  1003f6:\t05650513          \taddi\ta0,a0,86 # 100448 <main+0x60>\n  1003fa:\t3959                \tjal\t100090 <puts>\n  1003fc:\t40b2                \tlw\tra,12(sp)\n  1003fe:\t4501                \tli\ta0,0\n  100400:\t0141                \taddi\tsp,sp,16\n  100402:\t8082                \tret\n```\n```\nDASM(0x00010413)\nmv      s0, sp\n```\n\n![Image](https://github.com/user-attachments/assets/321158de-0306-44b2-a11b-64c2fcfc4a7f)\n\nMTVAL in `ibex_simple_system.log` file is 0x00000000\n<!--\nPlease describe the problem you saw. Include waveforms (in VCD or Verilator/GtkWave FST format only please) and log files if possible.\n-->\n\n## Expected Behavior\nThe terminal should print right mtval value.\n<!-- Please describe the behavior you expected to see instead. -->\n\n## Steps to reproduce the issue\nRun `build/lowrisc_ibex_ibex_simple_system_cosim_0/sim-verilator/Vibex_simple_system --meminit=ram,ibex/examples/sw/simple_system/input/test.elf`\n```\n#include \"simple_system_common.h\"\nint main(void){\n    // puts(\"Starting test\");\n    __asm__ volatile(\".word 0x000000\");\n    puts(\"Test complete\");\n    return 0;\n}\n```\n<!--\nPlease help us to reproduce the issue you're seeing by including a detailed description of what you did to get to the problem.\n\nFor example:\n* What command did you run? (Also include the output of the command.)\n* What parameters/defines did you set?\n* Did you make modifications to the source code?\n-->\n\n## My Environment\nBuild verilator to run ibex by [co-sim](https://ibex-core.readthedocs.io/en/latest/03_reference/cosim.html#quick-build-and-run-instructions).\n<!--\nLet us know how you're using Ibex. This helps us to better understand your problem and find a solution more quickly.\n-->\n\n**EDA tool and version:**\nNone\n<!--\nIf you are using an EDA tool to work with Ibex let us know which tool and which version you're using.\nFor example, \"Xilinx Vivado 2020.1\" or \"Synopsys VCS 2020.03-SP1\"\n-->\n\n**Operating system:**\nUbuntu Linux 18.04\n<!--\nPlease let us know the operating system/Linux distribution you're using.\nFor example \"Ubuntu Linux 18.04\" or \"CentOS 7.3\".\n-->\n\n**Version of the Ibex source code:**\n8f4c75c5e43e61b994248307c814e01860303056\n<!--\nWhich version of the Ibex source code are you using?\nYou can call `git rev-parse HEAD` in your Ibex source directory to get this information.\nPlease also let us know if you have made changes to the code.\n-->\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/lowRISC_ibex_pr2261", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/lowRISC_ibex_pr2261.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/lowRISC_ibex_pr2261", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/lowRISC_ibex_pr2261"}
{"instance_id": "lowRISC_ibex_pr2269", "issue_text": "# [bug][ibex_decoder] Report a bug in Ibex\n\n- Source URL: https://github.com/lowRISC/ibex/pull/2269\n\nHi all!\n\nI am using a static analysis to found a various bugs in open source RTL designs.\n\nIt was founded that in `ibex_decoder.sv` RTL file dead code is exists [here](https://github.com/lowRISC/ibex/blob/master/rtl/ibex_decoder.sv#L439).\n\nThis assignment under `else` statement is never executed due to [this](https://github.com/lowRISC/ibex/blob/master/rtl/ibex_decoder.sv#L406) external `else` branch with `!instr[26]` condition.\n\n## Fetched Issue/PR Details\n\nTitle: [rtl] Minor tweak to decoder to avoid dead code (PR #2269)\n\nDescription: The PR addresses dead code in the instruction decoder. According to the submitter, an else branch was unreachable because the surrounding condition already established that instr[26] was zero, making a redundant check impossible to execute.\n\nStatus: Merged\nMerged by: andreaskurth\nMerge date: April 25, 2025\nReviewers: marnovandermaas, andreaskurth, vogelpi (awaiting)\nChecks passed: 11\n\nComments:\n- rswarbrick (Apr 23, 2025): \"The 'else' part of the if/else check here wasn't possible because the surrounding else branch...is already in the case where instr[26] is zero.\"\n- marnovandermaas (Apr 24, 2025): Suggested adding an assertion to clarify the constraint.\n- rswarbrick (response): Noted that the project lacks procedural assertions in RTL code and the constraint is syntactically visible.\n- andreaskurth (Apr 25, 2025): Approved with \"LGTM, thx @rswarbrick\".\n\nLinked Issues: Fixes issue #2268 (\"[bug][ibex_decoder] Report a bug in Ibex\").\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/lowRISC_ibex_pr2269", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/lowRISC_ibex_pr2269.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/lowRISC_ibex_pr2269", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/lowRISC_ibex_pr2269"}
{"instance_id": "lowRISC_opentitan_pr28469", "issue_text": "# [hw,pinmux,rtl] Remove sys reset when no strap sampling\n\nInstance: lowRISC_opentitan_pr28469\nSource: https://github.com/lowRISC/opentitan/pull/28469\nFetched: 2026-04-26\nRepository: lowRISC/opentitan\nPull request: #28469\nAuthor: Razer6\nState: closed\nBase branch: master\nHead branch: pinmux-sys-reset\nCreated: 2025-10-11T22:52:30Z\nUpdated: 2025-10-13T14:44:34Z\nClosed: 2025-10-13T14:44:33Z\nMerged: 2025-10-13T14:44:33Z\n\nThe sys reset in pinmux is only needed for the strap sampling logic. Since that feature is gated behind an ipgen parameter, also gate the reset with this flag and remove it for Darjeeling.\r\n\r\nCloses https://github.com/lowRISC/opentitan/issues/25410\n\n## Local Reproducer Notes\n\n# lowRISC_opentitan_pr28469\n\nMinimal fail-to-pass Verilator case for removing the sys reset dependency from pinmux strap sampling.\n\nThe buggy pinmux clears the sampled strap when `rst_sys_ni` is asserted low even though strap sampling should only depend on the primary reset. The patch ignores the sys reset for the sampled strap state.\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/lowRISC_opentitan_pr28469", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/lowRISC_opentitan_pr28469.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/lowRISC_opentitan_pr28469", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/lowRISC_opentitan_pr28469"}
{"instance_id": "lowRISC_opentitan_pr28698", "issue_text": "# [otbn,dv] Collecting coverage fails for various tests\n\n### Description\n\nThe current [OTBN Simulation Results page](https://nightly.reports.lowrisc.org/opentitan_weekly_earlgrey/2025_11_02/hw/ip/otbn/dv/uvm/report.html) reports many OTBN tests as failing for the master branch. For example the otbn_smoke or otbn_single test.\n\nWhen I run these tests locally with DV sim but without coverage reporting, they pass (I tested otbn_smoke, otbn_single and otbn_multi_err). I run the tests with:\n```\nutil/dvsim/dvsim.py hw/ip/otbn/dv/uvm/otbn_sim_cfg.hjson -i otbn_smoke\n```\n\nThese tests fail when coverage is enabled (with the `--cov` argument) because illegal values are sampled for the mnemonic coverpoints of the instruction covergroups. An example for such a coverpoint is:\n\nhttps://github.com/lowRISC/opentitan/blob/9baed2bba4eccd325684c27b74049391d865c76f/hw/ip/otbn/dv/uvm/env/otbn_env_cov.sv#L1185-L1200\n\nI pinpointed the error down to the commit e9986ef486. This commit changes the macro `DEF_MNEM_BIN` such that quotes are added around the mnemonic to satisfy Verissimo. As a consequence, the bin is looking for mnemonic values like `\"addi\"` (with the quotes). However, the sample function of the covergroup is always called with the mnemonic without quotes, e.g., the passed value is `addi` (without quotes). The passed value is then handled as an illegal value and thus an error is reported.\n\nWhen I revert the commit, the tests pass again. \n\n@rswarbrick Can you please explain to me why the quotes are required? And if they are, how the setup can be adapted such that mnemonics with quotes are passed/generated?\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/lowRISC_opentitan_pr28698", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/lowRISC_opentitan_pr28698.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/lowRISC_opentitan_pr28698", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/lowRISC_opentitan_pr28698"}
{"instance_id": "merledu_azadi-soc_pr10", "issue_text": "# SRAM(openram) support is required.\n\n- Source URL: https://github.com/merledu/azadi-soc/issues/9\n\nFor submitting design in Google MPW-3 shuttle we need to add sram(openram) support for having sufficient memory size, may be around 8kb for iccm and dccm.\n\n## Fetched Issue/PR Details\n\nTitle: SRAM(openram) support is required. (#9)\n\nDescription: \"For submitting design in Google MPW-3 shuttle we need to add sram(openram) support for having sufficient memory size, may be around 8kb for iccm and dccm.\"\n\nAuthor: sajjadahmed677\nOpened: September 27, 2021\nStatus: Closed\nRelated PR: #10 (closed)\n\nComments: No comments visible.\n\nLinked Issues: Resolving PR #10. The issue requests integration of OpenRAM-based SRAM modules to provide adequate memory capacity for ICCM and DCCM in the Azadi SoC design, specifically for submission to the Google MPW-3 shuttle program.\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/merledu_azadi-soc_pr10", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/merledu_azadi-soc_pr10.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/merledu_azadi-soc_pr10", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/merledu_azadi-soc_pr10"}
{"instance_id": "merledu_azadi-soc_pr14", "issue_text": "# Need a coverage plan for ibex core!\n\n- Source URL: https://github.com/merledu/azadi-soc/issues/13\n\n\n## Fetched Issue/PR Details\n\nTitle: Need a coverage plan for ibex core! (#13)\n\nDescription: No description provided in the original issue body. The issue appears to be a request for establishing test coverage documentation or strategy for the Ibex core component within the Azadi SoC project.\n\nRepository: merledu/azadi-soc\nStatus: Closed (linked to PR #14)\nAuthor: za1nrkhan\nCreated: November 19, 2021\n\nComments: None visible.\n\nLinked Issues: Resolving PR #14.\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/merledu_azadi-soc_pr14", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/merledu_azadi-soc_pr14.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/merledu_azadi-soc_pr14", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/merledu_azadi-soc_pr14"}
{"instance_id": "merledu_azadi-soc_pr2", "issue_text": "# Input signal declared as output\n\n- Source URL: https://github.com/merledu/azadi-soc/issues/1\n\nWhen simulating with Xcelium, these warnings appear:\r\n\r\n```\r\nxmelab: *W,DSEMEL: This SystemVerilog design will be simulated as per IEEE 1800-2009 SystemVerilog simulation semantics. Use -disable_sem2009 option for turning off SV 2009 simulation semantics.\r\n    .rd_data_o  (frm_q),\r\n                     |\r\nxmelab: *W,ENUMERR (/home/zrkhan/Desktop/uvm-runs/azadi-new/hw/vendor/lowrisc_ibex/rtl/ibex_cs_registers.sv,849|21): This assignment is a violation of SystemVerilog strong typing rules for enumeration datatypes.\r\n    .tag_i          ( 1                ),\r\n                      |\r\nxmelab: *W,CUVMPW (/home/zrkhan/Desktop/uvm-runs/azadi-new/hw/vendor/lowrisc_ibex/rtl/ibex_core.sv,1205|22): port sizes differ in port connection(32/1) for the instance(core_ibex_tb_top.dut.u_ibex_core) .\r\n      .fp_load_o                       ( fp_load               )\r\n               |\r\n```\r\nFollowed by this error message\r\n```\r\nxmelab: *E,MULDRN (/home/zrkhan/Desktop/uvm-runs/azadi-new/hw/vendor/lowrisc_ibex/rtl/ibex_core.sv,712|15): Variable 'core_ibex_tb_top.dut.u_ibex_core.fp_load' has multiple conflicting drivers and the indicated output port connection in scope 'core_ibex_tb_top.dut.u_ibex_core' is contributing to this conflict set.\r\n    .fp_load_i                      ( fp_load                      )\r\n             |\r\n```\r\n\r\nThe issue points out to the invalid port direction of `ibex_wb_write` module.\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/merledu_azadi-soc_pr2", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/merledu_azadi-soc_pr2.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/merledu_azadi-soc_pr2", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/merledu_azadi-soc_pr2"}
{"instance_id": "merledu_azadi-soc_pr5", "issue_text": "# Update RTL of devices\n\n- Source URL: https://github.com/merledu/azadi-soc/issues/4\n\n@sajjadahmed677 please update the RTL files of devices  at SoC level along with doc and dv folders, use RTL that is present in APR v0.10. Please make sure to use the tab of spaces and remove extra line if any.\n\n## Fetched Issue/PR Details\n\nTitle: Update RTL of devices (#4)\n\nDescription: The creator (@zeeshanrafique23) requested that @sajjadahmed677 update the RTL (Register Transfer Level) files for devices at the System-on-Chip level. The request includes updating documentation and design verification folders, utilizing RTL from APR version 0.10. The requester also emphasized: \"use the tab of spaces and remove extra line if any.\"\n\nStatus: Closed (with associated Pull Request #5)\nCreated: September 11, 2021\nAssignee: not listed in the issue metadata\n\nComments: No additional comments visible.\n\nLinked Issues: Resolving PR #5.\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/merledu_azadi-soc_pr5", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/merledu_azadi-soc_pr5.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/merledu_azadi-soc_pr5", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/merledu_azadi-soc_pr5"}
{"instance_id": "microsoft_cheriot-ibex_pr81", "issue_text": "# [bug, dbg] Don't cache instruction whilst in debug mode lowrisc/ibex#1472\n\n- Source URL: https://github.com/microsoft/cheriot-ibex/pull/81\n\nCHERIoT Ibex does not disable the instruction cache when in debug mode, leading to incorrect behaviour. This was previously discovered and fixed in upstream Ibex in 2021-2022.\n\nSee [lowRISC Ibex issue 1472](https://github.com/lowRISC/ibex/issues/1472) for details on the problem and [lowRISC Ibex commit 7b1be33](https://github.com/lowRISC/ibex/commit/7b1be3354d650bc5b23dff6f439459c353288e4f) for the fix implemented.\n\n## Fetched Issue/PR Details\n\nTitle: [rtl] Don't cache instructions in debug mode (PR #81)\n\nDescription: The PR addresses the need to disable instruction caching during debug mode. The submission states: \"RISC-V debug modules may utilise dynamically changing code. Don't cache any instructions in debug mode to correctly support this.\" This change resolves issue #79.\n\nStatus: Merged\nAuthor: marnovandermaas\nMerged by: kunyanliu (Mar 25, 2025)\n\nComments:\n- marnovandermaas (Mar 24, 2025): Explained that RISC-V debug modules can use code that changes at runtime, necessitating the removal of instruction caching during debug operations.\n- kunyanliu (Mar 25, 2025): Approved the changes and merged the pull request.\n\nLinked Issues:\n- microsoft/cheriot-ibex #79: \"[bug, dbg] Don't cache instruction whilst in debug mode\" (mirrors lowrisc/ibex#1472).\n\nParticipants: 3 (marnovandermaas, kunyanliu, GregAC).\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/microsoft_cheriot-ibex_pr81", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/microsoft_cheriot-ibex_pr81.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/microsoft_cheriot-ibex_pr81", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/microsoft_cheriot-ibex_pr81"}
{"instance_id": "mist-devel_nes_pr4", "issue_text": "# Turbo buttons\n\n- Source URL: https://github.com/mist-devel/nes/issues/3\n\nHi.\nIt's possible to bind X and Y keys as turbo (aka autofire) variants of A and B?\nAlmost 100% of Dendy consoles have turbo buttons and there is official gamepads for Famicom with turbo buttons (NES Max and BPS Max controllers).\nI'm ready to implement it my own and propose pull request.\n\n## Fetched Issue/PR Details\n\nTitle: Turbo buttons (#3)\n\nDescription: UzixLS requested the ability to bind X and Y keys as turbo (autofire) variants of A and B buttons. They noted that nearly all Dendy consoles include turbo buttons, and official Famicom gamepads like the NES Max and BPS Max controllers feature this functionality. The user indicated willingness to implement the feature and submit a pull request.\n\nStatus: Closed\nAuthor: UzixLS\nDate Opened: February 3, 2023\n\nComments: None visible on the page.\n\nLinked Issues: Resolving PR #4.\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/mist-devel_nes_pr4", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/mist-devel_nes_pr4.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/mist-devel_nes_pr4", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/mist-devel_nes_pr4"}
{"instance_id": "muneeb-mbytes_pulpino__spi_master__ip_verification_pr27", "issue_text": "# Get the required VIPs\n\n- Source URL: https://github.com/muneeb-mbytes/pulpino__spi_master__ip_verification/issues/7\n\nTitle: Get the required VIPs\n\nBody:\n- Get the SPI AVIP collateral into this repository\n- Get the APB AVIP collateral into this repository\n\nComments: None\n\nMetadata:\n- Status: Closed\n- Assignee: venkateshs-t\n- Milestone: 🛠 Setup\n\n---\n\n## Pull Request\n\n**PR Title:** Updated Dv folder with all required AVIP's\n\n**PR Number:** #27\n\n**Status:** Merged on Feb 9, 2022\n\n### Description\n\nThe contributor indicated this work \"Fixes Get the required VIPs #7\" and proposed \"Updated the dv folder with spi salve and apb master avip collaterals required for this project\"\n\n### Commits\n\nTwo commits were added with the message \"added apb master and spi slave collaterals\" (commit IDs: 9ccc1d1 and 0f735c1)\n\n### Linked Issue\n\n**Issue #7:** Get the required VIPs\n\n### Metadata\n\n- Author: venkateshs-t\n- Reviewer/Merger: muneebullashariff\n- Label: enhancement (New feature or request)\n- Milestone: 🛠 Setup\n- Branch merged to: development_branch_v1\n- Source branch: apb_spi_vip_branch (deleted Feb 11, 2022)\n\nNo additional comments from reviewers were documented in the conversation thread.\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/muneeb-mbytes_pulpino__spi_master__ip_verification_pr27", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/muneeb-mbytes_pulpino__spi_master__ip_verification_pr27.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/muneeb-mbytes_pulpino__spi_master__ip_verification_pr27", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/muneeb-mbytes_pulpino__spi_master__ip_verification_pr27"}
{"instance_id": "muneeb-mbytes_pulpino__spi_master__ip_verification_pr32", "issue_text": "# Get the simulation script\n\n- Source URL: https://github.com/muneeb-mbytes/pulpino__spi_master__ip_verification/issues/8\n\nTitle: Get the simulation script\n\nBody:\n- Get the script to simulate over Questa simulator\n- Develop the verif.f file and rtl.f files\n- Compile the design and TB components\n\nComments: None\n\nLinked PR: #32 (closed)\n\nMetadata:\n- Assignee: Nadeem-Ahmed-S\n- Milestone: 🛠 Setup\n\n---\n\n## Pull Request\n\n**PR Title:** [PR] :: Included the Simulation scripts needed\n\n**PR Number:** #32\n\n**Status:** Merged on Feb 10, 2022\n\n**Branches:** `simulation_script_branch` → `development_branch_v1`\n\n### Description\n\nThe contributor proposed these modifications:\n\n- Incorporated the sim folder containing questa_sim directory and compile.f file\n- Included all file paths specified in compile.f\n- Renamed HDL top modules from generic \"hdl_top\" to \"apb_master_hdl_top\" and \"spi_slave_hdl_top\"\n- Updated makefile simulate commands to reflect renamed modules\n- Verified compilation succeeded without errors\n\nLater updates divided .f files into \"rtl.f\" and \"verif.f\" containing paths for spi_master_rtl, apb_master_avip, and spi_slave_avip components.\n\n### Conversation Activity\n\n**Nadeem-Ahmed-S** (Author) posted the initial description and made 4 commits including makefile and compile.f additions, gitignore file creation, and monitor bind statement removal.\n\n**muneebullashariff** reviewed and approved the changes on Feb 10, 2022, then merged the pull request.\n\n### Linked Issue\n\n**Get the simulation script** (#8) - Successfully closed by this PR\n\n**Milestone:** 🛠 Setup\n**Label:** enhancement\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/muneeb-mbytes_pulpino__spi_master__ip_verification_pr32", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/muneeb-mbytes_pulpino__spi_master__ip_verification_pr32.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/muneeb-mbytes_pulpino__spi_master__ip_verification_pr32", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/muneeb-mbytes_pulpino__spi_master__ip_verification_pr32"}
{"instance_id": "muneeb-mbytes_pulpino__spi_master__ip_verification_pr36", "issue_text": "# Develop the RAL model\n\n- Source URL: https://github.com/muneeb-mbytes/pulpino__spi_master__ip_verification/issues/22\n\nTitle: Develop the RAL model #22\n\nBody:\n**Is your feature request related to a problem? Please describe.**\nDevelop the RAL model based on the SPI master registers information using systemRDL\n\n**Additional context**\nUse systemRDL language to describe the registers information\n\n**Additional lists of tasks to be accomplished**\n- Write the source systemRDL file\n- Get the required python script/projects to generate the collateral\n- Generate UVM and PDF doc collaterals\n\nComments: None\n\nLinked PR: #36 (closed)\n\nMetadata:\n- Status: Closed\n- Assignee: muneebullashariff\n- Label: enhancement\n- Milestone: Development\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/muneeb-mbytes_pulpino__spi_master__ip_verification_pr36", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/muneeb-mbytes_pulpino__spi_master__ip_verification_pr36.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/muneeb-mbytes_pulpino__spi_master__ip_verification_pr36", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/muneeb-mbytes_pulpino__spi_master__ip_verification_pr36"}
{"instance_id": "muneeb-mbytes_pulpino__spi_master__ip_verification_pr39", "issue_text": "# Integrate RTL and VIPs\n\n- Source URL: https://github.com/muneeb-mbytes/pulpino__spi_master__ip_verification/issues/9\n\nTitle: Integrate RTL and VIPs\n\nBody: Integrate the RTL design and VIPs by developing the top module\n\nComments: None\n\nLinked PR: #39 (closed)\n\nMetadata:\n- Assignee: Nadeem-Ahmed-S\n- Milestone: 💻 Development\n- Status: Closed\n- Created: February 5, 2022\n\n---\n\n## Pull Request\n\n**PR Title:** Integration of RTL and VIPs done as in TB Architecture\n\n**PR Number:** #39\n\n**Status:** Merged on February 18, 2022\n\n**Branch:** `rtl_vips_integration` → `development_branch_v1`\n\n### Description\n\nThe initial PR description outlined several key objectives:\n\n- \"Created two tops hvl_top and hdl_top inside dv folder\"\n- \"Added the bfm sides of both apb_master and spi_slave in hdl_top.sv file\"\n- \"Mapped the apb_master interface and spi_slave interface to rtl\"\n- \"Printing the topology as in the architecture diagram\"\n\nThe PR addressed issues #9 (Integrate RTL and VIPs) and #11 (Develop TB components).\n\n### Comments\n\n**Nadeem-Ahmed-S** (February 17, 2022) provided an update describing additional work:\n\nAdded comparisons for write data and MOSI data. Developed check and report phases within the scoreboard through separate commits addressing run_phase, check_phase, and report_phase implementations.\n\n### Review & Merge\n\n**muneebullashariff** approved the changes on February 18, 2022, with the comment: \"Merging the changes.\" The branch was subsequently deleted on March 1, 2022.\n\n**Participants:** 5 contributors including Nadeem-Ahmed-S, muneebullashariff, sahanapalesh, sivareddykostam, and Shwetapatil05.\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/muneeb-mbytes_pulpino__spi_master__ip_verification_pr39", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/muneeb-mbytes_pulpino__spi_master__ip_verification_pr39.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/muneeb-mbytes_pulpino__spi_master__ip_verification_pr39", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/muneeb-mbytes_pulpino__spi_master__ip_verification_pr39"}
{"instance_id": "muneeb-mbytes_pulpino__spi_master__ip_verification_pr42", "issue_text": "# Develop the first testcase\n\n- Source URL: https://github.com/muneeb-mbytes/pulpino__spi_master__ip_verification/issues/10\n\nTitle: Develop the first testcase #10\n\nBody: We need to develop a testcase and run to check the flow\n\nComments: None\n\nLinked PR: #42 (closed)\n\nMetadata:\n- Assignee: venkateshs-t\n- Milestone: 💻 Development\n- Status: Closed\n- Created: February 5, 2022\n- Author: muneebullashariff\n\n---\n\n## Pull Request\n\n**PR Title:** [PR] :: Added Directed testcases for each feature mention in the following issues\n\n**PR Number:** #42\n\n**Status:** Merged on Feb 18, 2022\n\n### Description\n\nThe contributor proposed synchronizing with the RTL VIPs integration branch and developing directed testcases aligned with feature requirements. Key accomplishments include:\n\n- Created initial testcase with required sequences and virtual sequences\n- Demonstrated data flow from APB master and SPI slave\n- Developed directed testcases for features outlined in issue #41\n\n**Testcases Added:**\nTwelve testcases covering basic read/write operations, standard mode configurations with varying command/address/data lengths, dummy cycle generation, clock division settings (even/odd), and timing parameter variations.\n\n### Comments\n\n**venkateshs-t** (Feb 17, 2022):\n\"Fixes #10 #14 #41\" - The contributor linked three related issues, indicating this work addresses multiple feature development and testing objectives.\n\n**muneebullashariff** (Feb 18, 2022):\nApproved changes with comment: \"Accepting the changes\"\n\n### Linked Issues Closed\n\n- Develop the first testcase (#10)\n- Develop more tests (#14)\n- Develop Directed Testcases (#41)\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/muneeb-mbytes_pulpino__spi_master__ip_verification_pr42", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/muneeb-mbytes_pulpino__spi_master__ip_verification_pr42.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/muneeb-mbytes_pulpino__spi_master__ip_verification_pr42", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/muneeb-mbytes_pulpino__spi_master__ip_verification_pr42"}
{"instance_id": "muneeb-mbytes_pulpino__spi_master__ip_verification_pr50", "issue_text": "# Instantiate RAL model\n\n- Source URL: https://github.com/muneeb-mbytes/pulpino__spi_master__ip_verification/issues/37\n\nTitle: Instantiate RAL model\n\nBody: No description provided.\n\nComments: None\n\nMetadata:\n- Issue #37 was opened on February 10, 2022 by muneebullashariff\n- The issue is related to the pulpino SPI master IP verification project\n- It was later closed via pull request #50\n- No assignees, labels, or additional metadata were specified\n\n---\n\n## Pull Request\n\n**PR Title:** Integrating RAL into the testbench\n\n**PR Number:** #50\n\n**Status:** Merged on February 21, 2022\n\n**Branches:** `integrate_ral` → `development_branch_v1`\n\n### Description\n\nThe contributor outlined these proposed modifications:\n\n- \"Created predictor component\"\n- \"Integration done at the environment\"\n- \"Wrote a register test to demonstrate the flow\"\n\nThis PR was designed to resolve issue #37: \"Instantiate RAL model\"\n\n### Comments\n\n**Author:** @muneebullashariff (February 21, 2022)\n\nThe sole comment referenced the linked issue using standard GitHub notation and listed the three changes noted above.\n\n### Metadata\n\n- Reviewers: None recorded\n- Assignees: None\n- Labels: None\n- Commits: 1 (commit hash: 44f3a36)\n- Merge Commit: 6b4c0b9\n\nThe `integrate_ral` branch was deleted following the merge.\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/muneeb-mbytes_pulpino__spi_master__ip_verification_pr50", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/muneeb-mbytes_pulpino__spi_master__ip_verification_pr50.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/muneeb-mbytes_pulpino__spi_master__ip_verification_pr50", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/muneeb-mbytes_pulpino__spi_master__ip_verification_pr50"}
{"instance_id": "muneeb-mbytes_pulpino__spi_master__ip_verification_pr53", "issue_text": "# Implement Collector Components\n\n- Source URL: https://github.com/muneeb-mbytes/pulpino__spi_master__ip_verification/issues/54\n\nTitle: Implement Collector Components #54\n\nBody:\n**The features it should support:**\n- The apb master collector should be able to access registers data.\n- Combine the data as cmd, addr and mosi_data from the respective registers.\n- Pass the resultant data from apb master collector to scoreboard.\n\nComments: None\n\nMetadata:\n- Assignee: Nadeem-Ahmed-S\n- Labels: enhancement\n- Milestone: 💻 Development\n- Status: Closed (linked to PR #53)\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/muneeb-mbytes_pulpino__spi_master__ip_verification_pr53", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/muneeb-mbytes_pulpino__spi_master__ip_verification_pr53.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/muneeb-mbytes_pulpino__spi_master__ip_verification_pr53", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/muneeb-mbytes_pulpino__spi_master__ip_verification_pr53"}
{"instance_id": "muneeb-mbytes_pulpino__spi_master__ip_verification_pr56", "issue_text": "# Incorrect Sampling of MOSI data\n\n- Source URL: https://github.com/muneeb-mbytes/pulpino__spi_master__ip_verification/issues/46\n\n**Brief explanation of the question/help**\r\n![image](https://user-images.githubusercontent.com/91044066/154654361-e0e54fd0-462f-4e01-b07e-760e85513ff5.png)\r\n![image](https://user-images.githubusercontent.com/91044066/154654513-40ef35ef-3cf2-40a0-8044-067d37249038.png)\r\n![image](https://user-images.githubusercontent.com/91044066/154654940-dcee028e-f69d-4d87-b7c3-2f15dd2d6be6.png)\r\n\r\nif you can see in fig(1) the first 2 locked cursors shows 8 bits of command data\r\nand 2nd block shows you the next 8 bits of address data\r\nand the last block shows you the 32 bits of actual MOSI data\r\n\r\nIn fig(2) shows you the both MOSI data that has been sampled and MISO data that was driven \r\nso if you observe MOSI data the MOSI[0] tells the first 8 bits of **CMD** data and MOSI[1] shows the next 8 bits of **ADDR** data and remaining four MOSI transfers shows the **actual data** \r\n\r\nIn fig(3) i have shown you the 8 bits of command data which is indicated by **SPICMD** label which is of **FF** but if you can observe the sampled command data in fig(2) it is **FE** there is 1 bit missing(last bit is supposed be 1 but it is sampling 0 this you can observe in fig(1))\r\n\r\nSimilarly for the address data bits and for the actual data bits there is miss match in data that has been send to the sampled data\r\n\r\n**Branch name:**  test_cases_branch\r\n**Test_name:**  apb_master_std_mode_write_8_cmd_8_addr_32_data_length_test.sv\r\n\r\n**Add the required following items to the issue**\r\n1.  Projects\r\n2.  Milestone\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/muneeb-mbytes_pulpino__spi_master__ip_verification_pr56", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/muneeb-mbytes_pulpino__spi_master__ip_verification_pr56.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/muneeb-mbytes_pulpino__spi_master__ip_verification_pr56", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/muneeb-mbytes_pulpino__spi_master__ip_verification_pr56"}
{"instance_id": "muneeb-mbytes_pulpino__spi_master__ip_verification_pr58", "issue_text": "# Develop randomized tests\n\n- Source URL: https://github.com/muneeb-mbytes/pulpino__spi_master__ip_verification/issues/15\n\nTitle: Develop randomized tests #15\n\nBody: No description provided.\n\nComments: None\n\nLinked Issues/PRs:\n- #68 (Pull Request)\n- #58 (Pull Request)\n\nMetadata:\n- Assignee: venkateshs-t\n- Milestone: 🔥 Regression Testing\n- Created: February 5, 2022\n- Status: Closed\n- Repository: muneeb-mbytes/pulpino__spi_master__ip_verification\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/muneeb-mbytes_pulpino__spi_master__ip_verification_pr58", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/muneeb-mbytes_pulpino__spi_master__ip_verification_pr58.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/muneeb-mbytes_pulpino__spi_master__ip_verification_pr58", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/muneeb-mbytes_pulpino__spi_master__ip_verification_pr58"}
{"instance_id": "muneeb-mbytes_pulpino__spi_master__ip_verification_pr61", "issue_text": "# Develop more test for covering the coverage holes\n\n- Source URL: https://github.com/muneeb-mbytes/pulpino__spi_master__ip_verification/issues/18\n\nTitle: Develop more test for covering the coverage holes\n\nBody: No description provided.\n\nComments: None\n\nLinked PR: #61 (Closed)\n\nMetadata:\n- Assignee: venkateshs-t\n- Milestone: 🥂 Coverage Closure\n\n## PR Title\n[PR] :: Testcases for Coverage closure\n\n## PR Description\nFixes #18\n\nChanges proposed in this pull request:\n- Added more tests cases to cover the coverage holes as suggested\n- added negative testcases for lsb shift\n- added tx fifo testcase to hit the max count of fifo\n- added the write test for 8 bit dummy cycles\n\nMake sure you do the following:\n- Create the pull request to branch development_branch_v1\n- Use @mention to assign this pull request\n- Select Reviewer\n\n## PR Comments\n\n**muneebullashariff** (March 14, 2022):\n\"Approved!\"\n\n## Linked Issue\n#18: Develop more test for covering the coverage holes\n\n## PR Metadata\n- Author: venkateshs-t\n- Reviewer/Merger: muneebullashariff\n- Status: Merged (March 14, 2022)\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/muneeb-mbytes_pulpino__spi_master__ip_verification_pr61", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/muneeb-mbytes_pulpino__spi_master__ip_verification_pr61.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/muneeb-mbytes_pulpino__spi_master__ip_verification_pr61", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/muneeb-mbytes_pulpino__spi_master__ip_verification_pr61"}
{"instance_id": "muneeb-mbytes_pulpino__spi_master__ip_verification_pr63", "issue_text": "# Issue with virtual sequences\n\n- Source URL: https://github.com/muneeb-mbytes/pulpino__spi_master__ip_verification/issues/62\n\nTitle: Issue with virtual sequences #62\n\nBody:\n**Is your feature request related to a problem? Please describe.**\nProvide some delay between the transfers so chip select can able to assert and slave can detect the other transfers\n\nComments: None\n\nLinked PR: #63 (closed)\n\nMetadata:\n- Assignee: venkateshs-t\n- Label: enhancement\n- Milestone: 🥂 Coverage Closure\n- Status: Closed\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/muneeb-mbytes_pulpino__spi_master__ip_verification_pr63", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/muneeb-mbytes_pulpino__spi_master__ip_verification_pr63.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/muneeb-mbytes_pulpino__spi_master__ip_verification_pr63", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/muneeb-mbytes_pulpino__spi_master__ip_verification_pr63"}
{"instance_id": "muneeb-mbytes_pulpino__spi_master__ip_verification_pr68", "issue_text": "# Develop randomized tests\n\n- Source URL: https://github.com/muneeb-mbytes/pulpino__spi_master__ip_verification/issues/15\n\nTitle: Develop randomized tests #15\n\nBody: No description provided.\n\nComments: None\n\nLinked Issues/PRs:\n- #68 (Pull Request)\n- #58 (Pull Request)\n\nMetadata:\n- Assignee: venkateshs-t\n- Milestone: 🔥 Regression Testing\n- Created: February 5, 2022\n- Status: Closed\n- Repository: muneeb-mbytes/pulpino__spi_master__ip_verification\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/muneeb-mbytes_pulpino__spi_master__ip_verification_pr68", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/muneeb-mbytes_pulpino__spi_master__ip_verification_pr68.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/muneeb-mbytes_pulpino__spi_master__ip_verification_pr68", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/muneeb-mbytes_pulpino__spi_master__ip_verification_pr68"}
{"instance_id": "muneeb-mbytes_pulpino__spi_master__subsystem_verification_pr18", "issue_text": "# Get the required VIPs\n\n- Source URL: https://github.com/muneeb-mbytes/pulpino__spi_master__subsystem_verification/issues/1\n\nTitle: Get the required VIPs #1\n\nBody: get VIPs of AXI and SPI\n\nComments: None\n\nLinked PR: #18\n\nMetadata:\n- Assignee: anithasamanthula\n- Milestone: 🛠 Setup\n- Status: Closed\n\n## PR Title\nAvi ps branch\n\n## PR Description\nFixes #1 (mention the issue using the pound symbol followed by the issue number)\n\nChanges proposed in this pull request:\n- added the AXI4 master components\n- added the SPI slave components\n- ....\n\nMake sure you do the following:\n- Create the pull request to branch development_branch_v1\n- Use @mention to assign this pull request\n- Select Reviewer\n\n## PR Comments\nNo substantive comments beyond the PR description template.\n\n## Linked Issue\n#1: Get the required VIPs\n\n## PR Metadata\n- Source Branch: AVIPs-branch\n- Target Branch: development_branch_v1\n- Assignees: anithasamanthula, sivareddykostam\n- Milestone: 🛠 Setup\n- Merged By: sivareddykostam\n- Status: Merged (March 3, 2022)\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/muneeb-mbytes_pulpino__spi_master__subsystem_verification_pr18", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/muneeb-mbytes_pulpino__spi_master__subsystem_verification_pr18.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/muneeb-mbytes_pulpino__spi_master__subsystem_verification_pr18", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/muneeb-mbytes_pulpino__spi_master__subsystem_verification_pr18"}
{"instance_id": "muneeb-mbytes_pulpino__spi_master__subsystem_verification_pr23", "issue_text": "# Develop TB components\n\n- Source URL: https://github.com/muneeb-mbytes/pulpino__spi_master__subsystem_verification/issues/5\n\nTitle: Develop TB components #5\n\nBody:\n- env\n- virtual sequencers\n- scoreboard\n\nComments: None\n\nLinked Issues/PRs: #23 (Pull Request - Closed)\n\nMetadata:\n- Assignees: sahanapalesh, sivareddykostam\n- Milestone: 💻 Development\n- Created: March 2, 2022\n\nSummary: This is a development task requesting the creation of three testbench (TB) components for the PULPino SPI master subsystem verification project: an environment setup, virtual sequencers, and a scoreboard - all essential elements in SystemVerilog/UVM-based hardware verification frameworks.\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/muneeb-mbytes_pulpino__spi_master__subsystem_verification_pr23", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/muneeb-mbytes_pulpino__spi_master__subsystem_verification_pr23.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/muneeb-mbytes_pulpino__spi_master__subsystem_verification_pr23", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/muneeb-mbytes_pulpino__spi_master__subsystem_verification_pr23"}
{"instance_id": "muneeb-mbytes_pulpino__spi_master__subsystem_verification_pr25", "issue_text": "# adapter_development\n\n- Source URL: https://github.com/muneeb-mbytes/pulpino__spi_master__subsystem_verification/issues/24\n\n**Is your feature request related to a problem? Please describe.**\r\nA clear and concise description of what the problem is. Ex. I'm always frustrated when [...]\r\n\r\n**Describe the solution you'd like**\r\nA clear and concise description of what you want to happen.\r\n\r\n**Describe alternatives you've considered**\r\nA clear and concise description of any alternative solutions or features you've considered.\r\n\r\n**Additional context**\r\nAdd any other context or screenshots about the feature request here.\r\n\r\n**Additional lists of tasks to be accomplished**\r\n- [ ] task 1\r\n- [ ] task 2\r\n\r\n**Add the required following items to the issue**\r\n1.  Projects\r\n2.  Milestone\r\n3.  Assignee\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/muneeb-mbytes_pulpino__spi_master__subsystem_verification_pr25", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/muneeb-mbytes_pulpino__spi_master__subsystem_verification_pr25.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/muneeb-mbytes_pulpino__spi_master__subsystem_verification_pr25", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/muneeb-mbytes_pulpino__spi_master__subsystem_verification_pr25"}
{"instance_id": "muneeb-mbytes_pulpino__spi_master__subsystem_verification_pr28", "issue_text": "# Integrate RTL and VIPs\n\n- Source URL: https://github.com/muneeb-mbytes/pulpino__spi_master__subsystem_verification/issues/4\n\nTitle: Integrate RTL and VIPs #4\n\nBody: Integrate the RTL design and VIPs by developing the top module\n\nComments: None\n\nLinked PR: #28 (Closed)\n\nMetadata:\n- Assignee: sivareddykostam\n- Milestone: 💻 Development\n- Status: Closed\n\n## PR Title\nAdded the final width for the axi data\n\n## PR Description\nFixes: #4 #2 #6\n\nChanges proposed in this pull request:\n- adding the .gitignore file\n- updated the collector\n\nRequirements checklist:\n- Create the pull request to branch development_branch_v1\n- Use @mention to assign this pull request\n- Select Reviewer\n\n## PR Comments\n\n**sivareddykostam** (Mar 14, 2022):\n\"added the .gitignore file to remove the unwanted files\"\n\n## Linked Issue\n#4: Integrate RTL and VIPs\n\n## PR Metadata\n- Author: sivareddykostam\n- Source Branch: collector_branch\n- Target Branch: development_branch_v1\n- Assignee: sivareddykostam\n- Milestone: 💻 Development\n- Status: Merged (Mar 14, 2022)\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/muneeb-mbytes_pulpino__spi_master__subsystem_verification_pr28", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/muneeb-mbytes_pulpino__spi_master__subsystem_verification_pr28.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/muneeb-mbytes_pulpino__spi_master__subsystem_verification_pr28", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/muneeb-mbytes_pulpino__spi_master__subsystem_verification_pr28"}
{"instance_id": "muneeb-mbytes_pulpino__spi_master__subsystem_verification_pr29", "issue_text": "# Implement Collector Components\n\n- Source URL: https://github.com/muneeb-mbytes/pulpino__spi_master__subsystem_verification/issues/6\n\nTitle: Implement Collector Components #6\n\nBody:\n**The features it should support:**\n- The axi4 master collector should be able to access registers data.\n- Pass the resultant data from axi4 master collector to scoreboard.\n\nComments: None\n\nLinked PR: #29 (Implement Collector Components)\n\n## PR Title\nupdating the collector\n\n## PR Description\nFixes #6\n\nChanges proposed in this pull request:\n- Adding the collector\n- ....\n\nMake sure you do the following:\n- Create the pull request to branch development_branch_v1\n- Use @mention to assign this pull request\n- Select Reviewer\n\n## PR Comments\nNo substantive comments beyond the PR description template. The contributor self-assigned the PR and added it to the Development milestone on March 14, 2022.\n\n## Linked Issue\n#6: Implement Collector Components\n\n## PR Metadata\n- Author: sivareddykostam\n- Source Branch: collector_branch\n- Target Branch: development_branch_v1\n- Assignee: sivareddykostam\n- Milestone: 💻 Development\n- Status: Merged (March 14, 2022)\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/muneeb-mbytes_pulpino__spi_master__subsystem_verification_pr29", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/muneeb-mbytes_pulpino__spi_master__subsystem_verification_pr29.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/muneeb-mbytes_pulpino__spi_master__subsystem_verification_pr29", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/muneeb-mbytes_pulpino__spi_master__subsystem_verification_pr29"}
{"instance_id": "muneeb-mbytes_pulpino__spi_master__subsystem_verification_pr31", "issue_text": "# Develop regression list\n\n- Source URL: https://github.com/muneeb-mbytes/pulpino__spi_master__subsystem_verification/issues/10\n\nTitle: Develop regression list\n\nBody: No description provided.\n\nComments: None\n\nLinked Issues/PRs: Pull Request #31 (closed)\n\nMetadata:\n- Assignee: anithasamanthula\n- Milestone: 🔥 Regression Testing\n- Created: March 3, 2022\n\n## PR Title\nadded regression list\n\n## PR Description\nFixes #10\n\nChanges proposed in this pull request:\n- added all the register testcases\n- and added the regression_handling.py\n- ....\n\nMake sure you do the following:\n- Create the pull request to branch development_branch_v1\n- Use @mention to assign this pull request\n- Select Reviewer\n\n## PR Comments\n\n**anithasamanthula** (Mar 14, 2022, edited):\nProvided the PR description details mentioned above.\n\n## Linked Issue\n#10: Develop regression list\n\n## PR Metadata\n- Author: anithasamanthula\n- Source Branch: regression_branch\n- Target Branch: development_branch_v1\n- Assignee: anithasamanthula\n- Milestone: 💻 Development\n- Status: Merged (Mar 14, 2022)\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/muneeb-mbytes_pulpino__spi_master__subsystem_verification_pr31", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/muneeb-mbytes_pulpino__spi_master__subsystem_verification_pr31.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/muneeb-mbytes_pulpino__spi_master__subsystem_verification_pr31", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/muneeb-mbytes_pulpino__spi_master__subsystem_verification_pr31"}
{"instance_id": "nand2mario_nestang_pr75", "issue_text": "# NES controller connection issue\n\n- Source URL: https://github.com/nand2mario/nestang/pull/75\n\nTitle: Fix NES controllers\n\nBody: Fixes #74\n\nComments:\n- nikitalita (May 23, 2024): \"Fixes #74\"\n- nand2mario (May 23, 2024): Merged commit 705d9c1 into master\n\nLinked Issue: NES controller connection issue (#74)\nLinked Issue Body: I see you recently added support for them; which pins do they connect to? I'm going to make my own connector with a breadboard and a voltage logic level converter.\n\nStatus: Merged on May 23, 2024\n\n## PR Title\nFix NES controllers\n\n## PR Description\nFixes #74\n\n## PR Comments\nNo substantive comments are documented in the conversation thread beyond the PR description referencing the issue.\n\n## Linked Issue\n#74: NES controller connection issue\nBody: I see you recently added support for them; which pins do they connect to? I'm going to make my own connector with a breadboard and a voltage logic level converter.\n\n## PR Metadata\n- Author: nikitalita\n- Repository: nand2mario/nestang\n- Merge commit: 705d9c14f0be84c54476b1f54e463fa971530bfb\n- Status: Merged on May 23, 2024 by nand2mario into master\n- Participants: nikitalita, nand2mario\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/nand2mario_nestang_pr75", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/nand2mario_nestang_pr75.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/nand2mario_nestang_pr75", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/nand2mario_nestang_pr75"}
{"instance_id": "olofk_serv_pr105", "issue_text": "# alu with support for W=4\n\nInstance: olofk_serv_pr105\nSource: https://github.com/olofk/serv/pull/105\nFetched: 2026-04-26\nRepository: olofk/serv\nPull request: #105\nAuthor: uhit332\nState: closed\nBase branch: main\nHead branch: incremental\nCreated: 2023-10-31T11:31:13Z\nUpdated: 2023-10-31T11:42:58Z\nClosed: 2023-10-31T11:42:52Z\nMerged: 2023-10-31T11:42:52Z\n\n## PR Title\nalu with support for W=4\n\n## PR Description\nNo description provided.\n\n## PR Comments\n\n**uhit332** (Contributor, Oct 31, 2023):\nNo description provided.\n\n**olofk** (Owner, Oct 31, 2023):\n\"Excellent! Approved\"\n\n## Linked Issues\nNo linked issues.\n\n## PR Metadata\n- Source branch: uhit332/serv:incremental\n- Target branch: olofk/serv:main\n- No reviews, assignees, labels, or milestone\n- Merged by olofk on Oct 31, 2023 (commit 2e23b53)\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/olofk_serv_pr105", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/olofk_serv_pr105.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/olofk_serv_pr105", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/olofk_serv_pr105"}
{"instance_id": "olofk_serv_pr107", "issue_text": "# support for W=4\n\nInstance: olofk_serv_pr107\nSource: https://github.com/olofk/serv/pull/107\nFetched: 2026-04-26\nRepository: olofk/serv\nPull request: #107\nAuthor: uhit332\nState: closed\nBase branch: main\nHead branch: incremental\nCreated: 2023-10-31T12:34:06Z\nUpdated: 2023-10-31T14:54:12Z\nClosed: 2023-10-31T14:53:37Z\nMerged: 2023-10-31T14:53:37Z\n\n## PR Title\nsupport for W=4\n\n## PR Description\nNo description provided.\n\n## PR Comments\n\n**olofk** (October 31, 2023):\n\"Perfect! Picked and pushed!\"\n\n## Linked Issues\nNo linked issues.\n\n## PR Metadata\n- Participants: uhit332 (contributor), olofk (owner)\n- Status: Merged into olofk:main on October 31, 2023\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/olofk_serv_pr107", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/olofk_serv_pr107.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/olofk_serv_pr107", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/olofk_serv_pr107"}
{"instance_id": "olofk_serv_pr109", "issue_text": "# Change timer wraparound behavior to be more useful\n\nInstance: olofk_serv_pr109\nSource: https://github.com/olofk/serv/pull/109\nFetched: 2026-04-26\nRepository: olofk/serv\nPull request: #109\nAuthor: alinja\nState: closed\nBase branch: main\nHead branch: timer_wraparound\nCreated: 2023-11-12T21:41:19Z\nUpdated: 2023-11-17T08:27:53Z\nClosed: 2023-11-17T08:27:53Z\nMerged: 2023-11-17T08:27:53Z\n\n## PR Title\nChange timer wraparound behavior to be more useful\n\n## PR Description\nRisc-v timer is specified to be 64 bits long, meaning wraparound times of hundreds or thousands of years, making wraparound practically a non-issue. Servant has 32-bit timer, and it is not useful then timer wraps around. To avoid actually using 64 bits, this makes the timer useful even when the timer wraps around.\n\n## PR Comments\n\n**alinja** (Nov 12, 2023):\nInitial submission explaining the wraparound problem with the 32-bit timer implementation.\n\n**olofk** (Nov 16, 2023):\n\"I trust that this is an improvement, but I'm terrible at Verilog math, so would you mind quickly explaining what the actual difference is?\"\n\n**alinja** (Nov 16, 2023):\nThe original unsigned comparison had about a 30-second wraparound period at 125MHz. When mtime neared its maximum, \"mtimecmp will wrap around and an interrupt is generated immediately.\" The signed comparison approach ensures interrupts trigger correctly across wraparound boundaries, though limiting advance scheduling to approximately 15 seconds.\n\n**olofk** (Nov 17, 2023):\n\"Aha! I think I understand. All good. Thanks for the explanation. Picked and pushed!\"\n\n## Linked Issues\nNo linked issues.\n\n## PR Metadata\n- Status: Merged on Nov 17, 2023\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/olofk_serv_pr109", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/olofk_serv_pr109.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/olofk_serv_pr109", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/olofk_serv_pr109"}
{"instance_id": "olofk_serv_pr114", "issue_text": "# add PolarFire Splash Kit support\n\nInstance: olofk_serv_pr114\nSource: https://github.com/olofk/serv/pull/114\nFetched: 2026-04-26\nRepository: olofk/serv\nPull request: #114\nAuthor: liambeguin\nState: closed\nBase branch: main\nHead branch: polarfire-splashkit\nCreated: 2023-12-29T21:07:30Z\nUpdated: 2023-12-29T22:53:32Z\nClosed: 2023-12-29T21:39:12Z\nMerged: 2023-12-29T21:39:12Z\n\n## PR Title\nadd PolarFire Splash Kit support\n\n## PR Description\nNo description provided.\n\n## PR Comments\n\n**olofk** (Dec 29, 2023):\n\"Excellent! I think this is actually the first Servant port to a MicroChip device. And the clock_gen changes makes sense too. It's more consistent this way. Thanks!\"\n\n**liambeguin** (Dec 29, 2023):\nMentioned attaching a resource report.\n\n## Linked Issues\nNo linked issues.\n\n## PR Metadata\n- Status: Merged on Dec 29, 2023 by olofk into main\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/olofk_serv_pr114", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/olofk_serv_pr114.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/olofk_serv_pr114", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/olofk_serv_pr114"}
{"instance_id": "olofk_serv_pr90", "issue_text": "# ice40_pll.v - Guarantee at least 2 cycles of o_rst after PLL locked.\n\nInstance: olofk_serv_pr90\nSource: https://github.com/olofk/serv/pull/90\nFetched: 2026-04-26\nRepository: olofk/serv\nPull request: #90\nAuthor: emeb\nState: closed\nBase branch: main\nHead branch: master\nCreated: 2022-08-08T23:30:57Z\nUpdated: 2022-08-10T09:02:55Z\nClosed: 2022-08-10T09:02:51Z\nMerged: 2022-08-10T09:02:51Z\n\nWhile helping gojimmypi to bring up FuseSOC Serv on a new ice40-based target we were having trouble with Serv not starting up after configuration. Digging into the clock and reset logic I discovered that the wb_rst signal generated in the ice40_pll.v module was not asserting during start up.\r\n\r\nThe existing circuit relies on the PLL lock signal to clear the reset after two clock cycles, but because the initial state of the two delay registers defaults to logic 0, the reset signal is not guaranteed to ever assert. By inverting the input and output of the 2-stage register pipeline we can ensure that at least two cycles of logic '1' are generated, thus providing a usable reset.\r\n\r\nThis change has been verified working on the icebreaker target and also on the new ice-v-wireless target that we're working on.\r\n\r\nNOTE - the verilator-based CI script that's part of the serv repo appears to be broken so that has been failing for me lately.\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/olofk_serv_pr90", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/olofk_serv_pr90.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/olofk_serv_pr90", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/olofk_serv_pr90"}
{"instance_id": "openhwgroup_core-v-verif_pr2585", "issue_text": "Minimal fail-to-pass extraction for openhwgroup/core-v-verif PR 2585, \"Restore\nVerilator compile/simulation\".\n\nThe reduced testbench wrapper models the real Verilator compile fix where the\nCV32E40P wrapper module was renamed to `cv32e40p_core_tb_wrapper` and the\nVerilator top instantiates the renamed wrapper.  The buggy snapshot has the\nrenamed file/top reference but the old module declaration, reproducing the\nmissing-module compile failure.  The patch renames the module so the Verilator\ntestbench can build and drive `fetch_enable_i`.\n\n## PR Title\nRestore Verilator compile/simulation\n\n## PR Description\nResolves #2584, and cleans up DSim compiles as well.\n\n## PR Comments\n\n**cairo-caplan** (Feb 11, 2025):\nSuggested that the \"-std=gnu++11\" compiler flag removal was necessary because recent Verilator versions no longer require it. They also recommended applying similar changes to cv32e40s and cv32e40x Makefiles and noted the filename should match the module name for consistency.\n\n**MikeOpenHWGroup** (Feb 11, 2025):\nReferenced Verilator Issue #4898, which recommends removing \"-std=c++11\". They acknowledged that cv32e40s and cv32e40x should receive similar updates on their respective development branches and confirmed they had updated the filename to match the renamed module.\n\n**cairo-caplan** (Feb 11, 2025):\nApproval. Confirmed testing on Verilator 5.033 and validated the changes resolved the original issue.\n\n## Linked Issue\n#2584: Followed the quick start for cv32e40p but got hit with 7 warnings (Status: Closed)\n\n## PR Metadata\n- Author: MikeOpenHWGroup\n- Target Branch: openhwgroup:cv32e40p/dev\n- Status: Merged (April 1, 2025)\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/openhwgroup_core-v-verif_pr2585", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/openhwgroup_core-v-verif_pr2585.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/openhwgroup_core-v-verif_pr2585", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/openhwgroup_core-v-verif_pr2585"}
{"instance_id": "openhwgroup_core-v-xif_pr139", "issue_text": "# CV-X-IF vs. CORE-V-XIF\n\nIn https://github.com/openhwgroup/core-v-xif/pull/124/commits/8d7a432ceaca51b62af772b449af29e26120ad02 the term `CORE-V-XIF` is replaced by `CV-X-IF` in `README.md` and `intro.rst` files.\n\nIs there any reason to keep `CORE-V-XIF` in `x_ext.rst` file? For the sake of consistency, it would be preferable to use only one acronym.\n\n## PR Title\nReplacing CORE-V-XIF with CV-X-IF\n\n## PR Description\nNo description provided.\n\n## PR Comments\nChristian Herber (contributor) requested a review from ASintzoff on February 6, 2024 at 08:37 AM.\n\n## Linked Issue\n#138: CV-X-IF vs. CORE-V-XIF\n\n## PR Metadata\n- Submitter: christian-herber-nxp\n- Reviewer/Merger: ASintzoff\n- Source Branch: 138-cv-x-if-vs-core-v-xif\n- Target Branch: main\n- Status: Merged (February 6, 2024)\n- Participants: christian-herber-nxp, ASintzoff\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/openhwgroup_core-v-xif_pr139", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/openhwgroup_core-v-xif_pr139.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/openhwgroup_core-v-xif_pr139", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/openhwgroup_core-v-xif_pr139"}
{"instance_id": "openhwgroup_core-v-xif_pr167", "issue_text": "# Some parameters need clarification\n\nIn particular, `X_MISA` and `X_ECS_XS` lack sufficient explanation to understand what they would be used for in a coprocessor. They also do not quite appear in the rest of the specification like other parameters.\n\n## PR Title\nImproving X_MISA parameter\n\n## PR Description\nThe pull request addressed two main objectives:\n\n1. Clarifying what a CPU is expected to do with this parameter\n2. Adjusting the parameter range:\n   - Previous range: 32:0\n   - Updated range: 25:0 (where the Extensions field is located)\n   - Rationale: Alignment with RISC-V specification (MXLEN-1:0)\n\n## PR Comments\n\n**jquevremont** (February 26, 2024):\nReviewed and left comments.\n\n**Silabs-ArjanB**:\nRequested review.\n\n## Linked Issue\n#69: Some parameters need clarification\n\n## PR Metadata\n- Author: christian-herber-nxp\n- Source Branch: 69-some-parameters-need-clarification\n- Target Branch: main\n- Status: Merged (February 27, 2024)\n- Participants: christian-herber-nxp, Silabs-ArjanB, jquevremont\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/openhwgroup_core-v-xif_pr167", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/openhwgroup_core-v-xif_pr167.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/openhwgroup_core-v-xif_pr167", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/openhwgroup_core-v-xif_pr167"}
{"instance_id": "openhwgroup_cv-hpdcache_pr119", "issue_text": "# Missing semicolon\n\nMissing semicolon in line 206 of `cva6_op_hpdcache_params_pkg.sv` that prevents compilation in Modelsim:\n\nhttps://github.com/openhwgroup/cv-hpdcache/blob/abd2ffe21fc42956703fafd626ce7fbac89934dd/rtl/src/target/cva6/cva6_op_hpdcache_params_pkg.sv#L206\n\n## PR Title\ncva6/openpiton: add missing semicolon (#81)\n\n## PR Description\nNo description provided.\n\n## PR Comments\n\n**cfuguet** (November 7, 2025):\nNo description provided.\n\n## Linked Issue\n#81: Missing semicolon\n\n## PR Metadata\n- Author: cfuguet\n- Self-assigned: cfuguet\n- Label: bug\n- Status: Merged (November 7, 2025) into master\n- Merge commit: c7417eb\n- Branch deleted: dev/fix_cva6_op\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/openhwgroup_cv-hpdcache_pr119", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/openhwgroup_cv-hpdcache_pr119.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/openhwgroup_cv-hpdcache_pr119", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/openhwgroup_cv-hpdcache_pr119"}
{"instance_id": "openhwgroup_cv-hpdcache_pr33", "issue_text": "# [PLRU Issue] In case of CMO_PREFETCH plru behaves differently in case if HIT or MISS\n\nHello,\n\nFollowing observation are made in the case of CMO_PREFETCH (prefetch_updt_plru == 1)\n\n1. in case of hit PLRU is not updated\n2. in case of miss PLRU is updated once the read memory response is received.\n\nThis seems inconsistant. Can you please take a look at it ?\n\nThanks and regards\nTanuj Khandelwal\n\n## PR Title\nfix: prefetch requests should update PLRU on cache hit\n\n## PR Description\nThis shall be the case when cfg_prefetch_updt_plru is set to 1\n\n## PR Comments\nNone from reviewers.\n\n## Linked Issue\n#18: [PLRU Issue] In case of CMO_PREFETCH plru behaves differently in case if HIT or MISS\n\n## PR Metadata\n- Author: cfuguet\n- Status: Merged (October 18, 2024)\n- Commit: 87837ee546d5b5d340e7c31f8007c397f8af2300\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/openhwgroup_cv-hpdcache_pr33", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/openhwgroup_cv-hpdcache_pr33.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/openhwgroup_cv-hpdcache_pr33", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/openhwgroup_cv-hpdcache_pr33"}
{"instance_id": "openhwgroup_cv-hpdcache_pr38", "issue_text": "# [Question] How are the error responses treated\n\nHello,\n\nI would like to understand, how error responses are treated. This is what I am observing.\n\n1. In the case where memory responds to a READ with an error, all the subsequent load which are hit at the same addresse have an error response.\n2. In the case where memory responds to a READ with an error, the store which follows at the same adresse has a response withtout and error.\n\nIs it correct ?\n\nThanks and Regards\nTanuj Khandelwal\n\n## PR Title\nfix: handling of errors for write miss requests\n\n## PR Description\nIn the RTAB, only tag a request as error if it is a write miss and its corresponding refill response is an error.\n\n- Add a new dependency bit in the RTAB to indicate the pending request is a write miss\n- Refactor the RTAB code to use a packed structure to represent the dependency bits\n\nCloses #31\n\n## PR Comments\nNo substantive comments in the conversation thread beyond the initial PR description.\n\n## Linked Issue\n#31: [Question] How are the error responses treated\n\n## PR Metadata\n- Author: cfuguet\n- Status: Merged (October 29, 2024) into master\n- Commit: 8c38d83\n- Self-assigned: cfuguet\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/openhwgroup_cv-hpdcache_pr38", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/openhwgroup_cv-hpdcache_pr38.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/openhwgroup_cv-hpdcache_pr38", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/openhwgroup_cv-hpdcache_pr38"}
{"instance_id": "openhwgroup_cv-hpdcache_pr48", "issue_text": "# Incorrect flagging of write request event\n\nHi, I have noticed that the write request event (`evt_write_req_o`) is not flagged when there is a write request with a write-back policy and the memory produces a response with the error bit set.\r\n\r\n## How to reproduce the issue\r\n\r\nUsing the verilator testbench, run the following command:\r\n\r\n```\r\nmake run SEQUENCE=random LOG_LEVEL=3 NTRANSACTIONS=69 SEED=42\r\n```\r\n\r\nThe faulting transaction will be the last one.\r\n\r\n## Issue description\r\n\r\nThe core makes a store request, using a write-back policy. This request causes a miss, causing the cache to issue a load request to memory due to the write-allocate policy. The write miss event (`evt_cache_write_miss_o`) is flagged, but the write request event (`evt_write_req_o`)  is not. The request is put in the RTAB while the cache waits for the memory response.\r\n\r\nOnce the response arrives, it has the error bit set. The original request is then replayed from the RTAB. Because it has been flagged with the error bit, it only sends a response to the core with this flag set. However, it does not flag any event and does not proceed any further. \r\n\r\nUnder normal circumstances, when the error bit is not set, the directory would be updated and the replayed request would hit the cache. It is under this logic when the write request event is flagged (see [hpdcache_ctrl_pe.sv:881](https://github.com/openhwgroup/cv-hpdcache/blob/master/rtl/src/hpdcache_ctrl_pe.sv#L881)).\r\n\r\n## Possible solutions\r\n\r\n- When replaying a request with the error bit set, check if it's a store with the write-back policy, and flag the event then (inside hpdcache_ctrl_pe.sv:404).\r\n- When there is a write-back store making a hit in the cache, check if it's a core request or a replay from the RTAB. Emit the write request event both when there is a miss and when the core (and not a replay due to a miss) makes a hit.\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/openhwgroup_cv-hpdcache_pr48", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/openhwgroup_cv-hpdcache_pr48.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/openhwgroup_cv-hpdcache_pr48", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/openhwgroup_cv-hpdcache_pr48"}
{"instance_id": "openhwgroup_cv32e40p_pr665", "issue_text": "# Add more checks for illegal conditions in the PULP decoder\n\nfollowing what the issue #650 and #629 report - this has to start after pull request #659 is merged\n\n## PR Title\nadding more checks for illegal conditions in pulp isa\n\n## PR Description\nThe pull request was initiated to address issues #663 and #629. The commit message: \"Signed-off-by: Schiavone Davide <davide@openhwgroup.org>\"\n\n## PR Comments\n\n**davideschiavone** (August 24, 2021):\nIndicated this submission \"should fix #663 and #629\"\n\n**pascalgouedo** (January 4, 2022):\nProvided multiple review suggestions recommending code clarity improvements. The reviewer suggested replacing comparisons like `!= '0` with explicit bit-width notation (e.g., `!= 5'b0`, `!= 12'b0`, `!= 4'b0`) across multiple conditional statements in the decoder file.\n\n**pascalgouedo** (January 5, 2022):\nApproved the changes after corrections were applied.\n\n## Linked Issues\n#663: Add more checks for illegal conditions in the PULP decoder\n#629: (related illegal condition issue)\n\n## PR Metadata\n- Author: davideschiavone\n- Status: Merged (January 5, 2022)\n- Labels: Component:RTL, PARAM:PULP_XPULP\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/openhwgroup_cv32e40p_pr665", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/openhwgroup_cv32e40p_pr665.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/openhwgroup_cv32e40p_pr665", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/openhwgroup_cv32e40p_pr665"}
{"instance_id": "openhwgroup_cv32e40s_pr254", "issue_text": "# RVFI \"pmpaddr\" wrong width\n\n**Component:RTL**: For issues in the RTL (e.g. for files in the rtl directory)\r\n**Component:Other**: For any other issues\r\n\r\n\r\n### Description\r\n\r\nWhen using PMP `G` different from 0.\r\nXcelium cannot compile.\r\n(G=3 in the example below.)\r\n```\r\nxmelab: *E,TYCMPAT (/work/ropeders/src/core-v-verif-pmp/core-v-cores/cv32e40s/bhv/cv32e40s_wrapper.sv,606|72):\r\nport or terminal connection type check failed on instance 'uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i'\r\n(expecting datatype compatible with 'unpacked array [0:63] of packed array [31:0] of logic'\r\nbut found 'unpacked array [0:63] of packed array [29:0] of logic' instead).\r\n```\r\n\r\nThe wrapper connects rvfi probing like `.csr_pmpaddr_q_i          ( core_i.cs_registers_i.pmp_addr_rdata`.\r\nBut RVFI expects 32 bits `input logic [31:0]                         csr_pmpaddr_q_i[PMP_MAX_REGIONS]`.\r\nWhile RTL saved a few bits `logic [PMP_ADDR_WIDTH-1:0]    pmp_addr_rdata[PMP_MAX_REGIONS];`.\r\n\r\n(This also causes CEXes in formal, because the rvfi pmpaddr csr values are wrong.)\r\n\r\n\r\n### Steps to Reproduce\r\n\r\n1. Use my fork and branch: https://github.com/silabs-robin/core-v-verif/tree/pmp_assert, hash `f7e1416c`.\r\n2. Go to `cv32e40s/sim/uvmt` and run `make comp CFG=pmp`.\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/openhwgroup_cv32e40s_pr254", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/openhwgroup_cv32e40s_pr254.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/openhwgroup_cv32e40s_pr254", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/openhwgroup_cv32e40s_pr254"}
{"instance_id": "openhwgroup_cv32e40s_pr259", "issue_text": "# Wrong execute permission with mseccfg.MML and no matching region\n\n### Component\n\n**Component:RTL**: For issues in the RTL (e.g. for files in the rtl directory)\n\n### Steps to Reproduce\nWhen the first instruction after reset sets mseccfg.MML, the fetch of the next instruction actually goes through. However, the Smepmp spec states that for MML set, \"Executing code from a region without a matching rule or with a matching S/U-mode-only rule is denied.\" With no PMPs set up, the whole memory should thus be denied execute access after setting MML. This is also nicely illustrated in the picture in section 2.2: setting MML is enough to deny execute rights to M mode without a matching region.\nThe issue was found with assertion RV_chk.ops.XCPT_IF_ID_a of the OneSpin Processor Verification App.\n\n## PR Title\nPMP fix (issue 249)\n\n## PR Description\nShould fix #249\n\nSigned-off-by: Arjan Bink <Arjan.Bink@silabs.com>\n\n## PR Comments\n\n**Silabs-ArjanB** (July 18, 2022):\n\"Should fix #249. Signed-off-by: Arjan Bink Arjan.Bink@silabs.com\"\n\n## Linked Issue\n#249: Wrong execute permission with mseccfg.MML and no matching region\n\n## PR Metadata\n- Author: Silabs-ArjanB\n- Reviewer: silabs-oivind (review requested)\n- Labels: Component:RTL\n- Status: Merged (July 18, 2022)\n- Commit hash: 38ed6a0\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/openhwgroup_cv32e40s_pr259", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/openhwgroup_cv32e40s_pr259.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/openhwgroup_cv32e40s_pr259", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/openhwgroup_cv32e40s_pr259"}
{"instance_id": "openhwgroup_cv32e40s_pr263", "issue_text": "# rvfi_mode lacks reset\n\n## rvfi_mode lacks reset\nrvfi_mode is only assigned on `wb_valid_adjusted && !is_dummy_instr_in_wb`, thus has undefined value out of reset\n\n### Steps to Reproduce\nGit hash:  70793cc8e187fcc2c49a752402af82efd1df958d\nbhv/cv32e40s_rvfi.sv, Line 1028, only assignment occurs here.\n\n## PR Title\nAdded reset value for rvfi_mode\n\n## PR Description\nSigned-off-by: Arjan Bink <Arjan.Bink@silabs.com>\n\n## PR Comments\nNo substantive comments.\n\n## Linked Issue\n#262: rvfi_mode lacks reset (Closed)\n\n## PR Metadata\n- Author: Silabs-ArjanB\n- Branch: ArjanB_mrv (deleted on merge)\n- Status: Merged into openhwgroup:master (July 18, 2022)\n- Commit: c3cb5b9\n- Participants: Silabs-ArjanB (author/merger), silabs-hfegran (linked the issue)\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/openhwgroup_cv32e40s_pr263", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/openhwgroup_cv32e40s_pr263.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/openhwgroup_cv32e40s_pr263", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/openhwgroup_cv32e40s_pr263"}
{"instance_id": "openhwgroup_cv32e40x_pr894", "issue_text": "# Zero PMA regions,attribution mismatch between cv32e40x_mpu_sva and cv32e40x_pma\n\n- Source URL: https://github.com/openhwgroup/cv32e40x/issues/893\n\n## Zero PMA regions,attribution mismatch between cv32e40x_mpu_sva and cv32e40x_pma\r\n\r\nGiven 0 PMA regions, PMA code still takes `trans_debug_region_i` into account, while mpu assertions do not. \r\nOccurred during simulation, and confirmed by code inspection - causes mismatches with atomic bit as that bit is enabled in the default configuration, and disallowed within the debug region:\r\n\r\n`cv32e40x_pma.sv`:\r\n```diff\r\n    if(PMA_NUM_REGIONS == 0) begin: no_pma\r\n\r\n      always_comb begin\r\n        // PMA is deconfigured, use NO_PMA_R_DEFAULT as default.\r\n        pma_cfg = NO_PMA_R_DEFAULT;\r\n\r\n        // Debug mode transactions within the Debug Module region use PMA_DBG as attributes for the DM range\r\n        if (trans_debug_region_i) begin\r\n          pma_cfg = PMA_DBG;\r\n        end\r\n      end\r\n\r\n    end\r\n```\r\n\r\n`cv32e40x_mpu_sva.sv`:\r\n```diff\r\n  always_comb begin\r\n    pma_expected_cfg = NO_PMA_R_DEFAULT;\r\n    if (PMA_NUM_REGIONS) begin\r\n      pma_expected_cfg = is_pma_dbg_matched ? '{main    : 1'b1, default : '0} :\r\n                         is_pma_matched     ? PMA_CFG[pma_lowest_match]       : PMA_R_DEFAULT;\r\n\r\n    end\r\n  end\r\n```\r\n\r\n### Steps to Reproduce\r\nPlease provide:\r\n1. core git hash: 8f4eb4cc65c6142cbb24a02cfba975f072ae6376\r\n2. Command line: \r\n`make comp_corev-dv gen_corev-dv test TEST=corev_rand_interrupt_debug CFG=clic_default USE_ISS=YES COV=YES RUN_INDEX=483 GEN_START_INDEX=483 RNDSEED=-585695672 WAVES=1`\r\nNote that the above state of core-v-verif is missing the appropriate debug region settings; the following two lines of code must be added inside the last else clause in the file after the line containing `const string pma_cfg_name = \"pma_noregion\"`:\r\n\r\n```\r\n   parameter logic [31:0] CORE_PARAM_DM_REGION_START = 32'h1A11_0000;\r\n   parameter logic [31:0] CORE_PARAM_DM_REGION_END   = 32'h1A11_1000;\r\n\r\n```\r\nThese will be added by an upcoming PR to core-v-verif\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/openhwgroup_cv32e40x_pr894", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/openhwgroup_cv32e40x_pr894.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/openhwgroup_cv32e40x_pr894", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/openhwgroup_cv32e40x_pr894"}
{"instance_id": "openhwgroup_cv32e41p_pr15", "issue_text": "# 40P conditional compilation flags in the 41P\n\n- Source URL: https://github.com/openhwgroup/cv32e41p/issues/10\n\nJust saw that there are 40P-related compilation flags in the 41P code.\nExample: https://github.com/openhwgroup/cv32e41p/blob/master/bhv/cv32e41p_wrapper.sv#L14\n\nIs there a specific reason for that?\n\n## PR Title\n1) Update the assertions and tracer ifdefs\n\n## PR Description\nNo detailed description was provided beyond the title. The PR notes \"Closes #10\".\n\n## PR Comments\n\n**abukharmeh** (Feb 7, 2022):\nOpened the PR, noting it \"Closes #10\".\n\n**MikeOpenHWGroup** (Feb 8, 2022):\nTitle updated; requested review from davideschiavone.\n\n**davideschiavone** (Feb 9, 2022):\nApproved changes and merged the PR.\n\n## Linked Issue\n#10: 40P conditional compilation flags in the 41P\n\n## PR Metadata\n- Author: abukharmeh\n- Reviewer/Merger: davideschiavone\n- Status: Merged (Feb 9, 2022) into master, commit 4b6befd\n- Note: Repository archived November 24, 2023 (read-only)\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/openhwgroup_cv32e41p_pr15", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/openhwgroup_cv32e41p_pr15.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/openhwgroup_cv32e41p_pr15", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/openhwgroup_cv32e41p_pr15"}
{"instance_id": "openhwgroup_cva5_pr29", "issue_text": "# Interrupts can lead to MEPC inconsistent with register state / actually retired operations or pointing to entirely illegal instructions\n\n- Source URL: https://github.com/openhwgroup/cva5/issues/19\n\nWhen an interrupt, such as a timer interrupt occurs, the captured MEPC does not always reflect the correct address where to continue execution after the interrupt finishes. This can randomly lead to significant corruption and crashes.\r\n\r\nI have observed the following 3 inconsistencies::\r\n * CSR modifications that were already started will always finish, yet MEPC can point to the CSR operation  (so as not-executed,to resume here after interrupt) \r\n * MEPC can sometimes capture a normal (register-write) instruction that still retires (when the retiring of said instruction falls into the same cycle as the capturing. Same as with CSR-modifications, if the respective operation uses the modified output as input (`addi a0, a0, 1`), erroneous re-execution leads to broken state / MEPC is inconsistent with the register state.\r\n *  addresses of prefetched instructions, yet not ever executed / possibly illegal instructions can be captured\r\n\r\nExample for the 3rd case:\r\n```\r\njr [label]\r\n[illegal instruction]\r\n``` \r\nThe illegal instruction will be fetched and maybe decoded prior to CVA5 executing the jump and flushing. Gc_unit does not prevent the address from being captured into MEPC when an interrupt hits at the right time.\r\n\r\nI have fixes for all 3 cases applied in my fork of CVA5, but my fork includes other changes, such as an FPU, reworked verilator implementation and for example modifying the timer interrupt input to match the RV-Privileged spec  (#20).\r\nI have also written a test program that recreates all 3 cases for my fork and specific CVA5 configuration, using a timer implemented according to the RV-Priviliged spec. The benchmark arms the timer and expects it to request an interrupt at a specific cycle (and therefor instruction in the benchmark) that is still influenced by the branch predicator (I am using my production CVA5 config to run it).\r\n\r\nI am also happy to share said benchmark and timer, but I have only tested them in my environment, which uses my own Picolibc build, runtime/board support library, CMake configuration, new binary input format and conversion tool for the verilator-simulator. So said test-code would probably need to be refactored into a test with specific, more consistent processor config and to only use the vanilla code base.\r\n\r\nTo outline the scope of fixes I have applied:\r\n * decouple MEPC capture from interrupt_taken signal\r\n *  delay MEPC capture depending on if a instruction is currently being retired, ongoing CSR modification\r\n *  changed oldest_pc from metadata_id block to next_retiring_insn_pc which applies branch_flush events and updates itself to not include illegal or unreachable addresses.\r\n\r\nThis was the simplest solution to fix the corruption and is probably not the most efficient solution to implementing interrupts. Looking at the timings it seems to be, every instruction that was already issued pre-interrupt could just retire normally instead of being rolled back (unlike when handling jumps/branches). Since we have to wait for all issued ops to retire anyways, it is wasteful to throw that state away (and can also take more cycles). Then some of my modifications would no longer be needed. But I found it too difficult to understand all the ways in which gc_unit needs to stay synchronized to other parts of the core to attempt that modification myself / expected this refactoring to be more work.\r\n\r\nI am afraid I do currently not have the time to rebase my changes and test them without my code base so that I could provide a simple, conflict-free and tested patch-set.\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/openhwgroup_cva5_pr29", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/openhwgroup_cva5_pr29.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/openhwgroup_cva5_pr29", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/openhwgroup_cva5_pr29"}
{"instance_id": "openhwgroup_cva5_pr7", "issue_text": "# Cached memory interface: AXI wstrb not stable if AW handshake completes first\n\n- Source URL: https://github.com/openhwgroup/cva5/issues/6\n\nCVA5's dcache memory interface (via l1_arbiter, l2_arbiter, axi_to_arb) starts each single beat AXI AW handshake simultaneously to the only W handshake. The byte enable value `be` (used for `wstrb`) is stored alongside the address in the `l2_request_t` structure, and the FIFO entry is popped as soon as the AW handshake is complete. However, `wstrb` is in the W handshake alongside `wdata`.\n\nScenario: Downstream bus component sets `wready` only after having accepted an AW handshake. CVA5 will pop from the request FIFO, and `wstrb` will change to whatever is in the next valid or invalid FIFO element, even though the W handshake is still active.\n\nEffect: Depends on the bus components. In our case (using only Xilinx IP downstream), the presence or absence of an AXI crossbar appears to determine whether `wstrb` is sampled in the first W handshake cycle, where the AW handshake is still valid and the fault would be hidden, or in a later cycle. In that case, bytes may unintenionally be masked on or off, so data in memory could become inconsistent.\n\n(Suggested) solution: Move `be`/`wstrb` to the same FIFO as the write data. I'm preparing a pull request but still doing some validation of the patches for upstream.\n\n## PR Title\nL2: Move be (i.e. wstrb for AXI) into the data FIFO (Fixes #6)\n\n## PR Description\nThe contributor moved the `be` signal to the same FIFO as write data and adapted the L2 interface accordingly. Testing included custom design simulation and taiga-project's compliance tests. The `litex/l1_to_wishbone.sv` example and AXI test bench remained untested due to unrelated compile errors.\n\n## PR Comments\n\n**e-matthews** (September 13, 2022):\n\"Thank you very much for both reporting and providing a fix for this issue. I've given a first look over the changes and they look good. I'll run some additional tests and we'll look at getting these changes in soon.\"\n\n**e-matthews** (April 17, 2023):\nApproved the changes.\n\n**MikeOpenHWGroup** (April 18, 2023):\n\"Merging based on @e-matthews approval.\"\n\n## Linked Issue\n#6: Cached memory interface: AXI wstrb not stable if AW handshake completes first\n\n## PR Metadata\n- Submitted by: flmeisel\n- Merged by: MikeOpenHWGroup\n- Status: Merged (April 18, 2023)\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/openhwgroup_cva5_pr7", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/openhwgroup_cva5_pr7.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/openhwgroup_cva5_pr7", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/openhwgroup_cva5_pr7"}
{"instance_id": "openhwgroup_cve2_pr118", "issue_text": "Minimal fail-to-pass extraction for openhwgroup/cve2 PR 118, \"add\nfetch_enable_i\".\n\nThe reduced controller models the RESET to BOOT_SET transition from the real\ndiff.  The buggy controller leaves RESET immediately after reset deassertion.\nThe patch gates that transition on `fetch_enable_i`, matching the PR.  The\nVerilator testbench holds `fetch_enable_i` low after reset, then asserts it and\nchecks that instruction fetch only starts after the enable is observed.\n\n## PR Title\nadd fetch_enable_i\n\n## PR Description\nAdding fetch_enable_i signal to prevent the core booting after reset\n\n## PR Comments\n\n**davideschiavone** (May 25, 2023):\nInitiated the pull request.\n\n**davideschiavone** (May 25, 2023):\nRequested review from szbieg.\n\n**davideschiavone** (May 31, 2023):\nAdded three additional commits: merged origin/main into add_fetch_enable, fixed missing signals, removed unused signals.\n\n**szbieg** (June 1, 2023):\n\"After adding this signal in TB with a fixed logic high, the rudimentary hello-world test runs OK\"\n\n**szbieg** (June 1, 2023):\nApproved with comment: \"Modified code passes hello-world testbench check\"\n\n## Linked Issue\n#117: add fetch_enable_i\n\n## PR Metadata\n- Author: davideschiavone\n- Reviewer: szbieg\n- Status: Merged (June 1, 2023) into main\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/openhwgroup_cve2_pr118", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/openhwgroup_cve2_pr118.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/openhwgroup_cve2_pr118", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/openhwgroup_cve2_pr118"}
{"instance_id": "openhwgroup_cve2_pr139", "issue_text": "Minimal fail-to-pass extraction for openhwgroup/cve2 PR 139, \"move nmi to irq\n32\".\n\nThe reduced IRQ cause/vector logic models the real diff: fast interrupts expand\nfrom 15 to 16 inputs, exception causes expand from 6 to 7 bits, fast IRQ15 uses\ncause 31, and NMI moves to cause 32.  The buggy snapshot still encodes NMI as\nthe old cause 31 and ignores fast IRQ15.  The Verilator testbench drives NMI\nand fast IRQ15 and checks both cause and vector address.\n\n## PR Title\nmove nmi to irq 32\n\n## PR Description\nNo description provided.\n\n## PR Comments\n\n**davideschiavone** (August 16, 2023):\nCreated the pull request with initial commit \"move nmi to irq 32\" and subsequently marked as draft.\n\n**davideschiavone** (August 16, 2023):\nAdded commit \"fix exc cause\" and marked the PR as ready for review.\n\n**christian-herber-nxp** (August 16, 2023):\nApproved the changes and requested that testing be conducted with specific parameters: \"nmi set to 0\" and \"irq_fast[15] set to 0.\"\n\n**LeeHoff** (August 16, 2023):\nAsked davideschiavone to update cve2_top_tracing.sv to match cve2_top since it's used in verification.\n\n**davideschiavone** (August 16, 2023):\nAdded commit \"update top tracing\" in response to LeeHoff's request.\n\n**davideschiavone** (August 21, 2023):\nAdded commit \"fix mcause read.\"\n\n**szbieg** (August 29, 2023):\nConfirmed functional equivalence after fixing external signals and internal write data bus parameters, noting \"equivalence is confirmed.\"\n\n**davideschiavone** (August 30, 2023):\nReported successful NMI testing, stating the core correctly jumps to ISR 32 with mcause register showing \"0x60\" and CSRR instruction reporting \"0x8000_0020.\"\n\n## Linked Issue\n#136: [TASK] Move NMI to interrupt ID 32 from 31\n\n## PR Metadata\n- Author: davideschiavone\n- Status: Merged (August 30, 2023)\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/openhwgroup_cve2_pr139", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/openhwgroup_cve2_pr139.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/openhwgroup_cve2_pr139", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/openhwgroup_cve2_pr139"}
{"instance_id": "openhwgroup_cve2_pr152", "issue_text": "# Values for MVENDORID, MARCHID and MIMPID\n\nThe values of  `MVENDORID`, `MARCHID` and `MIMPID` are currently as-cloned from IBEX.  The will need to be updated to match the CVE2 values.  A good example of these can be found in the CV32E40X User Manual ([link](https://docs.openhwgroup.org/projects/cv32e40x-user-manual/en/latest/control_status_registers.html#machine-vendor-id-mvendorid)).\n\n## PR Title\nfix vendorid and marchid\n\n## PR Description\nNo description provided.\n\n## PR Comments\n\n**davideschiavone** (September 20, 2023):\nRequested review from christian-herber-nxp.\n\n**christian-herber-nxp** (September 20, 2023):\nSuggested that the documentation should reference the `MARCHID` parameter from the package rather than a hardcoded value, noting: \"I guess this should now be the MARCHID parameter of the package\"\n\n**davideschiavone** (September 20, 2023):\nClarified that `MARCHID_VALUE` equals `MARCHID` in the codebase.\n\n**christian-herber-nxp** (September 21, 2023):\nQuestioned whether users should modify `MARCHID` directly, suggesting integrators would expect to change the parameter during module instantiation rather than within the package itself.\n\n**davideschiavone** (September 21, 2023):\nAcknowledged the point and offered to convert it to a `localparam` if preferred.\n\n**christian-herber-nxp** (September 21, 2023):\nConfirmed keeping it as a `parameter` was acceptable, allowing flexibility for core instantiation.\n\n**davideschiavone** (September 21, 2023):\nIndicated readiness to merge upon approval.\n\n**christian-herber-nxp** (September 26, 2023):\nApproved the changes and merged the pull request.\n\n## Linked Issues\n#58: JEDEC manufacturer ID for CV32E20\n#12: Values for MVENDORID, MARCHID and MIMPID\n\n## PR Metadata\n- Author: davideschiavone\n- Merged by: christian-herber-nxp\n- Status: Merged (September 26, 2023)\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/openhwgroup_cve2_pr152", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/openhwgroup_cve2_pr152.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/openhwgroup_cve2_pr152", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/openhwgroup_cve2_pr152"}
{"instance_id": "openhwgroup_cve2_pr180", "issue_text": "# [BUG] Incorrect instruction counting (MINSTRET) when executing a DRET in Machine mode.\n\n### Bug Description\n\nOn the execution of dret when in machine mode, the DUT is incrementing minstret.  As the dret causes an exception it is not retired and as such should not increment minstret.  Found during simulation of the debug_test with step-and-compare.\n\nPrivileged Specification, 3.1.10 Hardware Performance Monitor: The minstret CSR counts the number of instructions the hart has retired\n\n## PR Title\nDo not count dret instruction when not in debug mode - it won't retire\n\n## PR Description\nThe pull request references issue #164 and includes a signed commit by Szymon Bieganski (szymon.bieganski@oss.nxp.com).\n\nCommit Message: \"Do not count dret instruction when not in debug mode - it won't retire fixes #164\"\n\n## PR Comments\n\n**szbieg** (Dec 20, 2023):\n\"fixes #164\"\n\n**szbieg** (Dec 20, 2023):\nAdded the \"bug\" label and self-assigned the PR.\n\n**LeeHoff** (Dec 21, 2023):\nApproval. \"This looks right to me. I wasn't able to run against the reference model, but with ISS=NO, the simulation passes.\"\n\n## Linked Issue\n#164: [BUG] Incorrect instruction counting (MINSTRET) when executing a DRET in Machine mode.\n\n## PR Metadata\n- Author: szbieg\n- Reviewer: LeeHoff\n- Merged by: davideschiavone\n- Status: Merged (Feb 26, 2024) into main\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/openhwgroup_cve2_pr180", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/openhwgroup_cve2_pr180.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/openhwgroup_cve2_pr180", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/openhwgroup_cve2_pr180"}
{"instance_id": "openhwgroup_cvfpu_pr114", "issue_text": "# Proposal: allow the FMA addend to be in either `src_fmt_i` or `dst_fmt_i`\n\nCurrently, the addend operand of the FMA shares its FP format with the result:\r\n\r\nhttps://github.com/openhwgroup/cvfpu/blob/4aac6b3e87a30c8567dbe7401eba3274eea18afc/src/fpnew_fma_multi.sv#L37-L38\r\n\r\nThis makes sense when considering the various fused multiply-accumulate operations of the RISC-V spec, which add the product of two multiplicands given in one FP format to an accumulator in another FP format. However, the RISC-V vector spec defines [widening FP add and subtract operations](https://github.com/riscv/riscv-v-spec/blob/master/v-spec.adoc#133-vector-widening-floating-point-addsubtract-instructions) that come in two flavors:\r\n- one which sums two narrow operands and produces a wider result\r\n- one which sums one narrow and one wide operand to produce a wide result\r\n\r\nThe latter is directly supported by CVFPU but the former is not, as that would require the addend operand of the FMA to be in `src_fmt_i` as well.\r\n\r\nLooking at the source code of the FMA, nothing is fundamentally preventing the FMA addend to be in a different format than the result. It would suffice to change the following lines, which unpack the 3 operands, to use a different format for `operand_c` (and `info_c`):\r\n\r\nhttps://github.com/openhwgroup/cvfpu/blob/4aac6b3e87a30c8567dbe7401eba3274eea18afc/src/fpnew_fma_multi.sv#L234-L240\r\n\r\nHence, in order to improve support for these type of widening FP add/sub and potentially other operations and to generally increase the flexibility of CVFPU, **I propose to allow the FMA addend to be in either `src_fmt_i` or `dst_fmt_i` (at least for the add operation)**.\r\n\r\nThis change could be implemented, for instance, by:\r\n- Adding a new port `add_fmt_i` to the FMA, all opgroup modules and the `fpnew_top` module that specifies the format of the addend. This would be the most flexible option but changes the ports of the top module.\r\n- Adding a new operation `ADDW` to the `operation_e` enum, which behaves the same as the `ADD` operation except that `src_fmt_i` is used for the addend instead of `dst_fmt_i`. This would avoid changes of the top module.\r\n\r\n@davideschiavone @pascalgouedo @stmach @lucabertaccini Please let me know if you would support such a change and your preferred way of implementing it. If favorable, I would then prepare a PR.\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/openhwgroup_cvfpu_pr114", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/openhwgroup_cvfpu_pr114.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/openhwgroup_cvfpu_pr114", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/openhwgroup_cvfpu_pr114"}
{"instance_id": "openhwgroup_cvfpu_pr116", "issue_text": "# NONCOMP clears the result bit for signaling NaNs in \"not equal\" compare\n\nThe NONCOMP block sets the result bit when either operand of a \"not equal\" comparison is a NaN:\n\nhttps://github.com/openhwgroup/cvfpu/blob/4aac6b3e87a30c8567dbe7401eba3274eea18afc/src/fpnew_noncomp.sv#L276-L279\n\nHowever, it does so only for quiet NaNs, not for signaling NaNs.\n\nWhile the effect of the modifier bit on comparisons is not documented, a comment in the source code indicates that its effect should be to invert the boolean result of comparisons. If either operand is a NaN, the result bit is cleared, except for a \"not equal\" comparison, which sets the result bit when encountering a NaN. This is in line with the way NaN values are handled in compare instructions in the RISC-V spec.\n\nHence, in order to treat quiet and signaling NaNs consistently and to be in line with the RISC-V spec, I suggest to modify the NONCOMP compare logic to set the result bit when either of the operands of a \"not equal\" compare is a signaling NaN.\n\n## PR Title\nFix result of not equal compare w signaling NaNs\n\n## PR Description\nMichael Platzer explained that the NONCOMP block was inconsistently handling NaN comparisons. Specifically, it \"sets the result bit when either operand of a 'not equal' comparison is a quiet NaN but not for signaling NaNs.\" The PR modifies the logic to treat both types consistently and align with the RISC-V specification by setting the result bit when signaling NaNs are involved in \"not equal\" comparisons.\n\nThe change references and fixes issue #115.\n\n## PR Comments\n\n**michael-platzer** (May 8, 2024):\nRequested an initial review from lucabertaccini (code owner).\n\n**stmach** (collaborator, May 23, 2024):\nApproved the changes, noting \"LGTM\" and referencing a comment in issue #115.\n\n## Linked Issue\n#115: NONCOMP clears the result bit for signaling NaNs in \"not equal\" compare\n\n## PR Metadata\n- Repository: openhwgroup/cvfpu\n- Status: Merged by stmach (May 23, 2024)\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/openhwgroup_cvfpu_pr116", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/openhwgroup_cvfpu_pr116.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/openhwgroup_cvfpu_pr116", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/openhwgroup_cvfpu_pr116"}
{"instance_id": "openhwgroup_cvfpu_pr125", "issue_text": "# CVFPU incorrectly suppresses overflow flag on `I2F` conversions\n\nAccording to IEEE 754-2008, converting an integer to a floating-point value should trigger an overflow exception in case the rounded value exceeds the range of the floating-point type.\r\n\r\n![image](https://github.com/openhwgroup/cvfpu/assets/9446837/8b5c00bc-ca18-4ccf-aca6-e4e4efb63691)\r\n\r\nHowever, CVFPU suppresses the overflow flag when the source operand is an integer (i.e., on `I2F` conversions), and sets the invalid flag instead:\r\n\r\nhttps://github.com/openhwgroup/cvfpu/blob/81c53c5381f7438272c05025ee3265d752f96e02/src/fpnew_cast_multi.sv#L721-L727\r\n\r\nThe comment on line 721 is incorrect: an overflow should *not* trigger an invalid exception on `I2F` conversions.\r\n\r\nI believe this has been confused with the opposite case, converting a floating-point value to an integer, which indeed is not supposed to produce an overflow exception:\r\n\r\n![image](https://github.com/openhwgroup/cvfpu/assets/9446837/c43ce567-69f8-4b6c-94cd-fc6b83ac0776)\r\n\r\nFor single-precision and double-precision types an overflow cannot happen, because the exponent range is always large enough such that any 32-bit or 64-bit integer value does not exceed it. However, for half-precision values an overflow can occur on `I2F` conversions.\r\n\r\n@lucabertaccini @pascalgouedo @stmach Please let me know whether my assessment is correct. I will then move forward with a PR to fix the behavior.\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/openhwgroup_cvfpu_pr125", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/openhwgroup_cvfpu_pr125.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/openhwgroup_cvfpu_pr125", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/openhwgroup_cvfpu_pr125"}
{"instance_id": "openhwgroup_cvfpu_pr140", "issue_text": "# CVFPU incorrectly sets inexact flag on `F2F` conversions of infinity\n\nAccording to IEEE 754-2008, operations on infinite operands usually do not signal exceptions:\r\n\r\n![image](https://github.com/user-attachments/assets/f0985380-26c2-42b5-9641-4ac95065f1b9)\r\n\r\nHowever, CVFPU sets the `NX` flag on `F2F` conversions of infinite values.\r\n\r\nhttps://github.com/openhwgroup/cvfpu/blob/a6af691551ffbd76d5d9cf30774d3295a41615e4/src/fpnew_cast_multi.sv#L727-L728\r\n\r\nThe expression above suppresses the `NX` flag upon overflow if the operand is infinity, but not if any of the `fp_round_sticky_bits` are set. These sticky bits are extracted from the destination mantissa, which in turn is derived from `preshift_mant`:\r\n\r\nhttps://github.com/openhwgroup/cvfpu/blob/a6af691551ffbd76d5d9cf30774d3295a41615e4/src/fpnew_cast_multi.sv#L486-L494\r\n\r\nHowever, the bits of `preshift_mant` are all `'1` if the operand is infinity:\r\n\r\nhttps://github.com/openhwgroup/cvfpu/blob/a6af691551ffbd76d5d9cf30774d3295a41615e4/src/fpnew_cast_multi.sv#L462-L467\r\n\r\nAs a result, the bits in `fp_round_sticky_bits` are always set if the operand is infinity and consequently the `NX` flag is incorrectly set.\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/openhwgroup_cvfpu_pr140", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/openhwgroup_cvfpu_pr140.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/openhwgroup_cvfpu_pr140", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/openhwgroup_cvfpu_pr140"}
{"instance_id": "openhwgroup_cvfpu_pr147", "issue_text": "# Incorrect FCVT.W.D Signed Integer Conversion for Negative Double-Precision Input\n\n- **Operand**: 0xC1E0000000000000.\n- **Instruction**: fcvt.w.d\n- **rounded_abs**: 0xffffffff80000000 (correct signed integer result for the given input) (verified with Spike)\n- **rounded_int_res**: 0x0000000080000000\n- **rounded_sign**: 1 (straight from the input operand)\n\nWhat is the purpose of this statement? if this is inverting the obtained answer...\n`assign rounded_int_res = rounded_sign ? unsigned'(-rounded_abs) : rounded_abs;\n`\n\n## PR Title\nPerform sign extension after conversion and rounding\n\n## PR Description\nFixes #145. As discussed in the issue, the sign extension should be performed after the result has been brought to two's complement form and rounded.\n\n## PR Comments\n\n**emustafa96** (Feb 18, 2025):\nRequested review from lucabertaccini as code owner.\n\n**emustafa96** (Feb 18, 2025):\nChanged title from \"Fix sign extension after conversion and rounding\" to \"Perform sign extension after conversion and rounding\"\n\n**rgiunti** (Oct 20, 2025):\n\"I've just checked your PR using this UVM testbench... I replicated the same operation described in Issue #145 with your modifications and everything is fine. I also performed a regression test that involves random transactions with varying seeds and there are no problems in that case either. I think it can be merged.\"\n\n**MikeOpenHWGroup** (Oct 21, 2025):\nApproved the changes.\n\n**MikeOpenHWGroup** (Oct 21, 2025):\n\"Thanks @emustafa96 and @rgiunti. Much appreciated. Approving and merging.\"\n\n## Linked Issue\n#145: Incorrect FCVT.W.D Signed Integer Conversion for Negative Double-Precision Input\n\n## PR Metadata\n- Author: emustafa96\n- Status: Merged (Oct 21, 2025)\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/openhwgroup_cvfpu_pr147", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/openhwgroup_cvfpu_pr147.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/openhwgroup_cvfpu_pr147", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/openhwgroup_cvfpu_pr147"}
{"instance_id": "openhwgroup_cvfpu_pr87", "issue_text": "# Bug report: multifmt slice uses wrong FP width for third operand\n\nHi,\n\nthe `fpnew_opgroup_multifmt_slice` uses the wrong FP width for the third operand.\n\nAFAIK the third operand is only used by the `ADDMUL` opgroup, which expects that `operands_i[0]` and `operands_i[1]` have the FP format specified by `src_fmt_i`  and `operands_i[2]` and the result have the FP format `dst_fmt_i`:\n\nhttps://github.com/openhwgroup/cvfpu/blob/5da3b411f3309d41b39dbc68da7449456f6be444/src/fpnew_fma_multi.sv#L36-L37\n\nAccordingly, the `fpnew_opgroup_multifmt_slice` should use the width of FP format `dst_fmt_i` when assigning the individual elements of `operands_i[2]` to the lane instances. However, the width of `src_fmt_i` is used for all operands:\n\nhttps://github.com/openhwgroup/cvfpu/blob/5da3b411f3309d41b39dbc68da7449456f6be444/src/fpnew_opgroup_multifmt_slice.sv#L181-L183\n\nAs a result, the third operand is incorrect for all lanes (except for the first lane), as shown in the following waveform. The first group of signals shows the `src_fmt_i` (which is `FP16`) and `dst_fmt_i` (which is `FP32`), as well as `operands_i[0]` (for reference) and `operands_i[2]` of the `fpnew_opgroup_multifmt_slice`. The elements of `operands_i[0]` which are 16 bits wide are correctly assigned to the individual `fpnew_fma_multi` instances (as seen in the signal groups below, which show the input operands of the first three instances). However, the elements of `operands_i[2]` which are 32 bits wide are not correctly assigned. The individual elements of these operands are surrounded by rectangles of different colors.\n\n## PR Title\nFix width of third local operand of multifmt slice\n\n## PR Description\nMichael Platzer proposed a fix for issue #86 by adjusting how the third local operand is assigned in the `fpnew_opgroup_multifmt_slice`. The solution uses the width of the FP format `dst_fmt_i` for proper operand assignment. The submitter included a waveform diagram demonstrating that operands in individual `fpnew_fma_multi` instances are now assigned correctly.\n\n## PR Comments\n\n**stmach** (April 18, 2023):\nExpressed approval while suggesting an alternative approach: \"Good catch, see if my suggestion would also work for you\"\n\n**zarubaf** (April 19, 2023):\nAsked for clarification on merge authority: \"do you want to merge or should I? Not sure how it is handled here\"\n\n**lucabertaccini** (April 19, 2023):\nMerged the pull request.\n\n## Linked Issue\n#86: Bug report: multifmt slice uses wrong FP width for third operand\n\n## PR Metadata\n- Repository: openhwgroup/cvfpu\n- Status: Merged on April 19, 2023\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/openhwgroup_cvfpu_pr87", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/openhwgroup_cvfpu_pr87.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/openhwgroup_cvfpu_pr87", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/openhwgroup_cvfpu_pr87"}
{"instance_id": "openhwgroup_cvw_pr1554", "issue_text": "# Incorrect Exception Priority\n\nWorking on Ssstrict Csr test for supervisor mode and accidentally included the satp register. This caused a strange exception and led to a mismatch between IDV and Wally. According to the Priv spec exception code 4 should be returned when Zicclsm is not enabled.\n\nThis occurs when lh x5,0(x5) is executed at address 0x800001c4 in the included elf file. 0x5 contains value 0xffffffff since on instruction address 800054a4 the csr 0x2a test loaded -1 into a random register which happened to be x1 (ra). Then there was an instruction access faulty exception on instruction 0x80007a14 while testing csr 0x174. This IAF exception caused ra (holding all 1s) to replace the value in mepc. When instruction 0x800001c4 in the traphandler (lh x5,0(x5)) was executed, this misaligned and access fault address caused an exception. Wally classified this as a load access fault but IDV classified this as a load address misaligned.\n\nRunning the SsstrictCsrS.elf file should replicate this error. Make sure satp is not skipped in addins/cvw-arch-verif/bin/csrtest.py\n(line 207 of csrtest.py is `csrtests(pathname, sCsrSkip + uCsrSkip + [0x180] ) # 0x180 is the satp register`).\n\n![Image](https://github.com/user-attachments/assets/a34f6128-f42c-420a-9773-26b0c20bfb8d)\n\n[SsstrictCsrS.elf.gz](https://github.com/user-attachments/files/19660253/SsstrictCsrS.elf.gz)\n\n## PR Title\nWhen Zicclsm is unsupported, throw a misaligned exception even if the TLB misses\n\n## PR Description\nResolves #1350\n\n## PR Comments\nNo formal review comments were captured.\n\n## Linked Issue\n#1350: Incorrect Exception Priority\n\n## PR Metadata\n- Author: davidharrishmc\n- Merged by: jordancarlin\n- Status: Merged (November 10, 2025)\n- Participants: davidharrishmc (contributor), jordancarlin (reviewer/merger)\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/openhwgroup_cvw_pr1554", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/openhwgroup_cvw_pr1554.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/openhwgroup_cvw_pr1554", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/openhwgroup_cvw_pr1554"}
{"instance_id": "openhwgroup_cvw_pr1555", "issue_text": "# Possible tracer bugs\n\nI'm seeing two anomalies in the tracer while running a program with WFI and interrupts.\n\nSee chips ~harris/cvw/examples/exercises/8p9\nmake sim\n\nAfter Info 15, it prints attempt to read uninitialized RAM, even though it is reading from the GPIO_OUTPUT_VAL register, which has previously been written.\n\nThe mip.MTIP timer interrupt rises at Info 21 for no apparent reason.\n\nmip.MTIP falls at Info 27 after the WFI.  I would have expected the timer to go off during the WFI.\n\n\n\n```\n...\n# Info 15: 'refRoot/cpu', 0x0000000080000038(wait_loop+4): Machine 10500073 wfi\n# Info   MEMX 0x80000038 0x80000038 2 0073\n# Info   MEMX 0x8000003a 0x8000003a 2 1050\n# WARNING: Attempting to read from unitialized RAM.  Processor may go haywire if it uses x value. But this is normal in WALLY-mmu and ExceptionInstr tests.\n#   PCM = 80000040 InstrM = 00042283 (LW), IEUAdrM = 1006000c\n# WARNING: Attempting to read from unitialized RAM.  Processor may go haywire if it uses x value. But this is normal in WALLY-mmu and ExceptionInstr tests.\n#   PCM = 80000040 InstrM = 00042283 (LW), IEUAdrM = 1006000c\n# Info 16: 'refRoot/cpu', 0x000000008000003c(wait_loop+8): Machine c01022f3 csrrs   x5,time,x0\n# Info   MEMX 0x8000003c 0x8000003c 2 22f3\n# Info   MEMX 0x8000003e 0x8000003e 2 c010\n# Info   x5 0000002e -> 00000211\n# Info 17: 'refRoot/cpu', 0x0000000080000040(wait_loop+c): Machine 00042283 lw      x5,0(x8)\n# Info   MEMX 0x80000040 0x80000040 2 2283\n# Info   MEMX 0x80000042 0x80000042 2 0004\n# Info   MEMR 0x1006000c 0x1006000c 4 00000000\n# Info   x5 00000211 -> 00000000\n# Info 18: 'refRoot/cpu', 0x0000000080000044(wait_loop+10): Machine 0012c293 xori    x5,x5,1\n# Info   MEMX 0x80000044 0x80000044 2 c293\n# Info   MEMX 0x80000046 0x80000046 2 0012\n# Info   x5 00000000 -> 00000001\n# Info 19: 'refRoot/cpu', 0x0000000080000048(wait_loop+14): Machine 00542023 sw      x5,0(x8)\n# Info   MEMX 0x80000048 0x80000048 2 2023\n# Info   MEMX 0x8000004a 0x8000004a 2 0054\n# Info   MEMW 0x1006000c 0x1006000c 4 00000001\n# Info 20: 'refRoot/cpu', 0x000000008000004c(wait_loop+18): Machine 0004a283 lw      x5,0(x9)\n# Info   MEMX 0x8000004c 0x8000004c 2 a283\n# Info   MEMX 0x8000004e 0x8000004e 2 0004\n# Info   MEMR 0x2004000 0x2004000 4 00000210\n# Info   x5 00000001 -> 00000210\n# Info 21: 'refRoot/cpu', 0x0000000080000050(wait_loop+1c): Machine 012282b3 add     x5,x5,x18\n# Info   MEMX 0x80000050 0x80000050 2 82b3\n# Info   MEMX 0x80000052 0x80000052 2 0122\n# Info   x5 00000210 -> 00000404\n# Info (OP_NCH) GlobalTime:0.000000 LocalTime:0.000000 Net:refRoot/MTimerInterrupt 0 => 1\n# Info   mip 00000000 -> 00000080 [MEIP:0 SEIP:0 MTIP:0->1 STIP:0 MSIP:0 SSIP:0]\n# Info 22: 'refRoot/cpu', 0x0000000080000054(wait_loop+20): Machine 0054a023 sw      x5,0(x9)\n# Info   MEMX 0x80000054 0x80000054 2 a023\n# Info   MEMX 0x80000056 0x80000056 2 0054\n# Info   MEMW 0x2004000 0x2004000 4 00000404\n# Info 23: 'refRoot/cpu', 0x0000000080000058(wait_loop+24): Machine fff98993 addi    x19,x19,-1\n# Info   MEMX 0x80000058 0x80000058 2 8993\n# Info   MEMX 0x8000005a 0x8000005a 2 fff9\n# Info   x19 00000004 -> 00000003\n# Info 24: 'refRoot/cpu', 0x000000008000005c(wait_loop+28): Machine fc099ce3 bne     x19,x0,80000034\n# Info   MEMX 0x8000005c 0x8000005c 2 9ce3\n# Info   MEMX 0x8000005e 0x8000005e 2 fc09\n# Info 25: 'refRoot/cpu', 0x0000000080000034(wait_loop): Machine c01022f3 csrrs   x5,time,x0\n# Info   MEMX 0x80000034 0x80000034 2 22f3\n# Info   MEMX 0x80000036 0x80000036 2 c010\n# Info   x5 00000404 -> 0000022b\n# Info 26: 'refRoot/cpu', 0x0000000080000038(wait_loop+4): Machine 10500073 wfi\n# Info   MEMX 0x80000038 0x80000038 2 0073\n# Info   MEMX 0x8000003a 0x8000003a 2 1050\n# Info 27: 'refRoot/cpu', 0x000000008000003c(wait_loop+8): Machine c01022f3 csrrs   x5,time,x0\n# Info   MEMX 0x8000003c 0x8000003c 2 22f3\n# Info   MEMX 0x8000003e 0x8000003e 2 c010\n# Info   x5 0000022b -> 00000405\n# Info (OP_NCH) GlobalTime:0.000000 LocalTime:0.000000 Net:refRoot/MTimerInterrupt 1 => 0\n# Info   mip 00000080 -> 00000000 [MEIP:0 SEIP:0 MTIP:1->0 STIP:0 MSIP:0 SSIP:0]\n# Info 28: 'refRoot/cpu', 0x0000000080000040(wait_loop+c): Machine 00042283 lw      x5,0(x8)\n# Info   MEMX 0x80000040 0x80000040 2 2283\n# Info   MEMX 0x80000042 0x80000042 2 0004\n# Info   MEMR 0x1006000c 0x1006000c 4 00000001\n# Info   x5 00000405 -> 00000001\n```\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/openhwgroup_cvw_pr1555", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/openhwgroup_cvw_pr1555.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/openhwgroup_cvw_pr1555", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/openhwgroup_cvw_pr1555"}
{"instance_id": "openrisc_mor1kx_pr110", "issue_text": "# [Bug] l.fl1 instruction not decoded\n\n- Source URL: https://github.com/openrisc/mor1kx/issues/102\n\n@lifeasageek\n\nl.fl1 instruction is not decoded correctly.\nAny l.fl1 instruction can reproduce the error.\n\nWe can solve this with following change in mor1kx_decode.v\n\n```verilog\n  assign decode_op_ffl1_o = opc_insn == `OR1K_OPCODE_ALU &&\n                        (decode_insn_i[9:8] == 2'b00 || decode_insn_i[9:8] == 2'b01) &&\n                        opc_alu == `OR1K_ALU_OPC_FFL1;\n```\n\n## PR Title\nFix mor1kx_decode to accept valid l.fl1 (l.ff1) instructions\n\n## PR Description\nThe pull request addresses issue #102 regarding the l.fl1 instruction decoding problem. According to the commit messages: \"Both l.fl1 and l.ff1 have bit 9 set in the instruction as part of their op codes, mor1kx_decode does not currently properly check this.\"\n\n## PR Comments\n\n**JaewonHur** (December 19, 2019):\nOpened the PR referencing issue #102.\n\n**skristiansson** (December 19, 2019):\nRequested changes during review.\n\n**JaewonHur** (December 23, 2019):\nAdded 3 additional commits with refinements.\n\n**skristiansson** (December 22, 2019):\nApproved the changes and merged the PR.\n\n## Linked Issue\n#102: [Bug] l.fl1 instruction not decoded\n\n## PR Metadata\n- Author: JaewonHur\n- Reviewer/Merger: skristiansson\n- Status: Merged (December 22, 2019)\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/openrisc_mor1kx_pr110", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/openrisc_mor1kx_pr110.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/openrisc_mor1kx_pr110", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/openrisc_mor1kx_pr110"}
{"instance_id": "openrisc_mor1kx_pr54", "issue_text": "PCU: misses events #46\n\nThe PCU will at most increment the counters by one in a cycle. If there is more than one event enabled for a register, they are not counted. The workaround is to enable at most one event class per counter.\n\n## PR Title\nMake PCU work at all, and then make it work correctly\n\n## PR Description\nSee individual commits. Right now it's completely useless. Fixes #46.\n\n## PR Comments\n\n**wallento** (Oct 18, 2017):\n\"lgtm, ready to merge\"\n\n## Linked Issue\n#46: PCU: misses events\n\n## PR Metadata\n- Merged by: skristiansson (Oct 18, 2017)\n- Approved by: jordens, wallento\n- Total participants: 4\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/openrisc_mor1kx_pr54", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/openrisc_mor1kx_pr54.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/openrisc_mor1kx_pr54", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/openrisc_mor1kx_pr54"}
{"instance_id": "opensocdebug_osd-hw_pr50", "issue_text": "DEM UART: Add tests for irq functionality #49\n\nThe 16550 UART requires the irq signal to be used, however, this functionality is not tested in the cocotb-based tests (and it seems right now that there are some bugs in it). We need cocotb tests for this functionality.\n\n## PR Title\nUart fixes\n\n## PR Description\nFixes #49 and successfully shows Linux boot output (stdout) in simulation and synthesis up to userspace.\n\n## PR Comments\nNo substantive comments captured beyond commit summaries.\n\n## Linked Issue\n#49: DEM UART: Add tests for irq functionality\n\n## PR Metadata\n- Author: imphil\n- Branch: uart-fixes -> osd-next\n- Status: Merged (October 30, 2018)\n- Merge commit: 4c784b1\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/opensocdebug_osd-hw_pr50", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/opensocdebug_osd-hw_pr50.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/opensocdebug_osd-hw_pr50", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/opensocdebug_osd-hw_pr50"}
{"instance_id": "pezy-computing_pzbcm_pr2", "issue_text": "# introduce BROADCAST NON POSTED command\n\nInstance: pezy-computing_pzbcm_pr2\nSource: https://github.com/pezy-computing/pzbcm/pull/2\nFetched: 2026-05-03\nRepository: pezy-computing/pzbcm\nPull request: #2\nAuthor: taichi-ishitani\nState: closed\nBase branch: master\nHead branch: introduce_broadcat_nonposted_command\nCreated: 2023-03-29\nUpdated: 2024-04-04\nClosed: 2023-03-29\nMerged: 2023-03-29\n\n## PR Title\nintroduce BROADCAST NON POSTED command\n\n## PR Description\n(No PR body provided.)\n\n## PR Comments\n\n**taichi-ishitani** (Mar 29, 2023):\nReferenced issue \"#1\".\n\n## Linked Issues\n\n**Issue #1: [pzcorebus] broadcast non posted コマンドを追加する**\nBroadcast コマンドのレスポンスあり版である Broadcast non posted コマンドを追加する。\nエンコーディングは `0b11_01`。\n\n* pzcorebus_1_to_m_switch\n    * `MASTERS` 分の Broadcast non posted コマンドに対するレスポンスが返ってくるので、最後の 1 個のみを slave 側に流すようにする必要がある\n* pzcorebus_debug\n    * 対象コマンドを更新\n* pzcorebus_dummy_slave\n    * Broadcast non posted を受けた際は `serror` を 0 にして、レスポンスを返す\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/pezy-computing_pzbcm_pr2", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/pezy-computing_pzbcm_pr2.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/pezy-computing_pzbcm_pr2", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/pezy-computing_pzbcm_pr2"}
{"instance_id": "phanrahan_mantle_pr92", "issue_text": "# Enable eq operator\n\nInstance: phanrahan_mantle_pr92\nSource: https://github.com/phanrahan/mantle/pull/92\nFetched: 2026-05-03\nRepository: phanrahan/mantle\nPull request: #92\nAuthor: leonardt\nState: closed\nBase branch: master\nHead branch: enable-eq-operator\nCreated: 2018-07-23\nUpdated: 2018-07-23\nClosed: 2018-07-23\nMerged: 2018-07-23\n\n## PR Title\nEnable eq operator\n\n## PR Description\nResolves #51. Mantle, loam, and aetherling test suites pass on their master branches. Minor changes required to magma to switch `==` to `is` logic. (This one is a bit of a gotcha, basically we can't use `in` statements because those use `__eq__` rather than `is`.)\n\n## PR Comments\n\n**leonardt** (Jul 23, 2018):\n\"Resolves #51. Mantle, loam, and aetherling test suites pass on their master branches. Minor changes requires to magma to switch `==` to `is` logic.\" with note \"(This one is a bit of a gotcha, basically we can't use `in` statements because those use `__eq__` rather than `is`)\"\n\n## Linked Issues\n\n**Issue #51: Resolve == (eq) operator overloading**\n== is not implemented because it breaks stuff in the magma internals that use == to check for object equality. Offending code should be updated to use is instead so we can overload the == operator.\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/phanrahan_mantle_pr92", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/phanrahan_mantle_pr92.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/phanrahan_mantle_pr92", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/phanrahan_mantle_pr92"}
{"instance_id": "projf_projf-explore_pr173", "issue_text": "# Hitomezashi missing pixel fix\n\n- Source URL: https://github.com/projf/projf-explore/issues/172\n\nAt the price of one extra flipflop (**last_h_stitch0**) I extended h-line by one pixel.\r\nCode is in verilog due to the the fact that I use ISE with basys2 to play with VGA :)\r\n```\r\n\t//-------------------------------------------------------------\r\n\t// paint stitch pattern with 16x16 pixel grid\r\n\twire stitch;\r\n\twire v_line, v_on;\r\n\twire h_line, h_on;\r\n\treg last_h_stitch0;\r\n\t\r\n\tassign v_line = (sx[3:0] == 4'b0000);\r\n\tassign h_line = (sy[3:0] == 4'b0000);\r\n\tassign v_on = sy[4] ^ v_start[sx[9:4]];\r\n\tassign h_on = sx[4] ^ h_start[sy[8:4]];\r\n\tassign stitch = (v_line && v_on) || (h_line && h_on) || last_h_stitch0;\r\n\r\n        always @ ( posedge clk ) begin\r\n\t\tlast_h_stitch0 <= h_line && h_on;\r\n\tend\r\n\r\n```\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/projf_projf-explore_pr173", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/projf_projf-explore_pr173.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/projf_projf-explore_pr173", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/projf_projf-explore_pr173"}
{"instance_id": "projf_projf-explore_pr86", "issue_text": "# LFSR seed is now a signal.\n\nInstance: projf_projf-explore_pr86\nSource: https://github.com/projf/projf-explore/pull/86\nFetched: 2026-05-03\nRepository: projf/projf-explore\nPull request: #86\nAuthor: WillGreen\nState: closed\nBase branch: master\nHead branch: lfsr-seed-signal\nCreated: 2022-01-30\nUpdated: 2022-01-30\nClosed: 2022-01-30\nMerged: 2022-01-30\n\n## PR Title\nLFSR seed is now a signal.\n\n## PR Description\nThis PR fixes (closes) #83.\n\n## PR Comments\n\n**WillGreen** (Jan 30, 2022):\n\"This PR fixes closes #83.\"\n\n## Linked Issues\n\n**Issue #83: LFSR Seed Signal**\nThe LFSR module (`lib/maths/lfsr.sv`) takes the seed as a parameter, so it can't be changed at runtime.\n\nA fixed seed isn't ideal when used as a random number generator. Making the seed a signal is a simple change.\n\nOnce this change is made, we need to update _FPGA Graphics_ designs:\n* Starfield (Ad Astra)\n* David Fizzlefade (Framebuffers)\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/projf_projf-explore_pr86", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/projf_projf-explore_pr86.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/projf_projf-explore_pr86", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/projf_projf-explore_pr86"}
{"instance_id": "pulp-platform_apb_pr1", "issue_text": "# Release 0.2\n\nInstance: pulp-platform_apb_pr1\nSource: https://github.com/pulp-platform/apb/pull/1\nFetched: 2026-04-26\nRepository: pulp-platform/apb\nPull request: #1\nAuthor: andreaskurth\nState: closed\nBase branch: master\nHead branch: release-0.2\nCreated: 2019-06-03T16:25:24Z\nUpdated: 2026-02-14T23:10:31Z\nClosed: 2020-03-13T10:05:09Z\nMerged: 2020-03-13T10:05:09Z\n\n## PR Title\nRelease 0.2\n\n## PR Description\nIt's time to coordinate our scattered APB efforts and bring things together in this repository. This is the first steps, details are in the Changelog.\n\n## PR Comments\n\n**fabianschuiki** (Jun 5, 2019):\n\"This looks very good. Pretty nice to have a collection of APB IPs next to the AXI IPs.\"\n\n## Linked Issues\nNo linked issues are referenced in this pull request.\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/pulp-platform_apb_pr1", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/pulp-platform_apb_pr1.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/pulp-platform_apb_pr1", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/pulp-platform_apb_pr1"}
{"instance_id": "pulp-platform_apb_pr10", "issue_text": "# typedef: Add `APB_TYPEDEF_ALL` macro\n\nInstance: pulp-platform_apb_pr10\nSource: https://github.com/pulp-platform/apb/pull/10\nFetched: 2026-04-26\nRepository: pulp-platform/apb\nPull request: #10\nAuthor: niwis\nState: closed\nBase branch: master\nHead branch: typedef-all\nCreated: 2023-02-23T15:36:23Z\nUpdated: 2023-03-06T09:27:46Z\nClosed: 2023-03-04T17:08:21Z\nMerged: 2023-03-04T17:08:21Z\n\n## PR Title\ntypedef: Add `APB_TYPEDEF_ALL` macro\n\n## PR Description\nAdd a macro that defines both the request and response structs.\n\n## PR Comments\n\n**paulsc96** (Mar 4, 2023):\n\"👍. Do you need/want a release for that?\"\n\n**niwis** (Mar 6, 2023):\n\"Thanks! No need for a release from my side.\"\n\n## Linked Issues\nNo linked issues are referenced in this pull request.\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/pulp-platform_apb_pr10", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/pulp-platform_apb_pr10.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/pulp-platform_apb_pr10", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/pulp-platform_apb_pr10"}
{"instance_id": "pulp-platform_apb_pr2", "issue_text": "# APB4 structs\n\nInstance: pulp-platform_apb_pr2\nSource: https://github.com/pulp-platform/apb/pull/2\nFetched: 2026-04-26\nRepository: pulp-platform/apb\nPull request: #2\nAuthor: WRoenninger\nState: closed\nBase branch: master\nHead branch: apb-structs\nCreated: 2020-02-21T14:43:13Z\nUpdated: 2020-03-13T10:05:08Z\nClosed: 2020-03-13T10:05:07Z\nMerged: 2020-03-13T10:05:07Z\n\nThis PR  mainly has the same changes as [#1](https://github.com/pulp-platform/apb/pull/1).\r\nHowever this differs in the regard that the changes made here have the same structure as in the [AXI repository](https://github.com/pulp-platform/axi).\r\n* Added struct typedef macros.\r\n* Added struct assign macros.\r\n* Added APB4 read only / write only registers (+testbenches).\r\n* Added synthesis bench.\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/pulp-platform_apb_pr2", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/pulp-platform_apb_pr2.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/pulp-platform_apb_pr2", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/pulp-platform_apb_pr2"}
{"instance_id": "pulp-platform_apb_pr3", "issue_text": "# apb_regs: Tool compatibility improvements\n\nInstance: pulp-platform_apb_pr3\nSource: https://github.com/pulp-platform/apb/pull/3\nFetched: 2026-04-26\nRepository: pulp-platform/apb\nPull request: #3\nAuthor: zarubaf\nState: closed\nBase branch: master\nHead branch: tool-fixes\nCreated: 2020-04-23T07:10:42Z\nUpdated: 2026-02-14T23:10:27Z\nClosed: 2022-12-02T15:03:23Z\nMerged: 2022-12-02T15:03:23Z\n\n- Some tools require explicit hints on the type\r\n  for the structured assignment.\r\n- Reset values driven from signals are generally considered\r\n  unsafe. A tiny FSM initializes these values.\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/pulp-platform_apb_pr3", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/pulp-platform_apb_pr3.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/pulp-platform_apb_pr3", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/pulp-platform_apb_pr3"}
{"instance_id": "pulp-platform_apb_pr4", "issue_text": "# Bugfix in APB Assignment Macro\n\nInstance: pulp-platform_apb_pr4\nSource: https://github.com/pulp-platform/apb/pull/4\nFetched: 2026-04-26\nRepository: pulp-platform/apb\nPull request: #4\nAuthor: meggiman\nState: closed\nBase branch: master\nHead branch: bugfix_assign_macro\nCreated: 2021-06-02T08:12:35Z\nUpdated: 2026-02-14T23:10:26Z\nClosed: 2021-06-02T10:21:16Z\nMerged: 2021-06-02T10:21:16Z\n\n## PR Title\nBugfix in APB Assignment Macro\n\n## PR Description\nThis PR fixes a small typo in the APB_TO_RESP assignment macro.\n\n## PR Comments\n\n**meggiman** (Jun 2, 2021):\n\"This PR fixes a small typo in the APB_TO_RESP assignment macro.\"\n\n**andreaskurth** (Jun 2, 2021):\n\"Thanks for this fix, @meggiman!\"\n\n## Linked Issues\nNo linked issues are referenced in this pull request.\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/pulp-platform_apb_pr4", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/pulp-platform_apb_pr4.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/pulp-platform_apb_pr4", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/pulp-platform_apb_pr4"}
{"instance_id": "pulp-platform_apb_pr7", "issue_text": "# Apb demux\n\nInstance: pulp-platform_apb_pr7\nSource: https://github.com/pulp-platform/apb/pull/7\nFetched: 2026-04-26\nRepository: pulp-platform/apb\nPull request: #7\nAuthor: meggiman\nState: closed\nBase branch: master\nHead branch: apb_demux\nCreated: 2022-04-26T16:32:02Z\nUpdated: 2026-02-14T23:10:25Z\nClosed: 2022-12-20T12:03:27Z\nMerged: 2022-12-20T12:03:27Z\n\n## PR Title\nApb demux\n\n## PR Description\nThis commit adds an APB demultiplex module.\n\n## PR Comments\n\n**meggiman** (Apr 26, 2022):\n\"This commit adds an APB demultiplex module\"\n\n**meggiman** (Dec 5, 2022):\nMarked the pull request as ready for review and assigned it to paulsc96.\n\n**paulsc96** (Dec 20, 2022):\nApproved the changes after reviewing the files in commit ca1d84b.\n\n**paulsc96** (Dec 20, 2022):\nMerged commit 3b9e0e6 into master.\n\n## Linked Issues\nNo linked issues are referenced in this pull request.\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/pulp-platform_apb_pr7", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/pulp-platform_apb_pr7.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/pulp-platform_apb_pr7", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/pulp-platform_apb_pr7"}
{"instance_id": "pulp-platform_apb_pr8", "issue_text": "# Adds an APB Error Slave\n\nInstance: pulp-platform_apb_pr8\nSource: https://github.com/pulp-platform/apb/pull/8\nFetched: 2026-04-26\nRepository: pulp-platform/apb\nPull request: #8\nAuthor: meggiman\nState: closed\nBase branch: master\nHead branch: apb_err_slv\nCreated: 2022-12-05T20:41:29Z\nUpdated: 2026-02-14T23:10:24Z\nClosed: 2022-12-20T12:13:33Z\nMerged: 2022-12-20T12:13:33Z\n\n## PR Title\nAdds an APB Error Slave\n\n## PR Description\nDepends on #7\n\n## PR Comments\n\n**meggiman** (Dec 5, 2022):\n\"Depends on #7\"\n\n**meggiman** (Dec 20, 2022):\nMarked the pull request as ready for review.\n\n**paulsc96** (Dec 20, 2022):\nForce-pushed changes and merged commit c736c05 into master.\n\n## Linked Issues\nNo linked issues are referenced in this pull request.\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/pulp-platform_apb_pr8", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/pulp-platform_apb_pr8.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/pulp-platform_apb_pr8", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/pulp-platform_apb_pr8"}
{"instance_id": "pulp-platform_axi_pr138", "issue_text": "# axi_xbar: Improve compatibility with vsim 10.6c\n\nInstance: pulp-platform_axi_pr138\nSource: https://github.com/pulp-platform/axi/pull/138\nFetched: 2026-05-03\nRepository: pulp-platform/axi\nPull request: #138\nAuthor: andreaskurth\nState: closed\nBase branch: master\nHead branch: vsim-10.6c-improve-xbar-compatibility\nCreated: 2021-01-11\nUpdated: 2021-01-12\nClosed: 2021-01-12\nMerged: 2021-01-12\n\n## PR Title\naxi_xbar: Improve compatibility with vsim 10.6c\n\n## PR Description\nThis addresses a workaround for vsim 10.6c compatibility issues referenced in issue #133. The version reports an \"illegal output or inout port connection for port 'slv_resp_o'\" error (vsim-3053), which newer versions do not exhibit. The implementation preserves original functionality while resolving the simulator issue. Credit to jsailer for the implementation approach.\n\n## PR Comments\n\n**andreaskurth** (Jan 11, 2021):\nPosted the initial description noting the vsim 10.6c problem and crediting jsailer for the implementation approach.\n\n**andreaskurth** (Jan 11, 2021):\nSelf-assigned the PR.\n\n**andreaskurth** (Jan 12, 2021):\nMerged the PR into master.\n\n## Linked Issues\n\n**Issue #133: vsim 10.6c: axi_xbar: illegal port connection**\nThe error \"Illegal output or inout port connection for port 'slv_resp_o'\" (vsim-3053) appears at /ips/axi/axi/src/axi_xbar.sv(162) when running PULP-rt-example. The reporter encountered this when running PULP-rt-example with vsim 10.6c.\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/pulp-platform_axi_pr138", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/pulp-platform_axi_pr138.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/pulp-platform_axi_pr138", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/pulp-platform_axi_pr138"}
{"instance_id": "pulp-platform_axi_pr185", "issue_text": "# Fix latch inference on the data width converters with the Mentor Precision synthesis tool\n\nInstance: pulp-platform_axi_pr185\nSource: https://github.com/pulp-platform/axi/pull/185\nFetched: 2026-05-03\nRepository: pulp-platform/axi\nPull request: #185\nAuthor: suehtamacv\nState: closed\nBase branch: master\nHead branch: axi_dwc_fixes\nCreated: 2021-10-08\nUpdated: 2021-11-11\nClosed: 2021-11-11\nMerged: 2021-11-11\n\n## PR Title\nFix latch inference on the data width converters with the Mentor Precision synthesis tool\n\n## PR Description\nCloses #184. This PR reworks a construct that would cause latches to be inferred on both the `axi_dw_downsizer` and the `axi_dw_upsizer`, when synthesizing them with Mentor Precision.\n\n## PR Comments\n\n**suehtamacv** (Oct 8, 2021):\n\"Closes #184. This PR reworks a construct that would case latches to be infered on both the `axi_dw_downsizer` and the `axi_dw_upsizer`, when synthesizing them with the Mentor Precision.\"\n\n**andreaskurth** (Nov 11, 2021):\n\"LGTM, thanks!\"\n\n## Linked Issues\n\n**Issue #184: axi_dw_up/downsizer: Latch inference when synthesizing with Mentor Precision**\nWhen synthesizing with _Mentor Precision_, the tool infers latches in the `axi_dw_upsizer` and `axi_dw_downsizer`. The tool seems to have an issue with the automatic variable `r_data` and `w_data` in both modules. At least in `axi_dw_upsizer` the assignment of `r_data` should still be the default `'0`. So `r_data` is only saving the initialization value, which is then conditionally overwritten. Then however when synthesizing with SYNOPSYS the latches are not there. When adding an `else` statement to the `if` then the latch goes away at least in the first code snippet. So an idea for a fix is to add the `else` condition and remove the automatic variable.\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/pulp-platform_axi_pr185", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/pulp-platform_axi_pr185.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/pulp-platform_axi_pr185", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/pulp-platform_axi_pr185"}
{"instance_id": "pulp-platform_axi_pr224", "issue_text": "# Compilation error of axi_lite_mux_intf with XSim\n\nI get errors when trying to simulate the axi_lite_mux_intf module with XSim, these are some of them:\r\nERROR: [VRFC 10-2991] 'aw' is not declared under prefix 'slv_reqs_i' [axi_lite_mux.sv:129]\r\nERROR: [VRFC 10-2991] 'aw_valid' is not declared under prefix 'slv_reqs_i' [axi_lite_mux.sv:130]\r\nERROR: [VRFC 10-2991] 'aw_ready' is not declared under prefix 'slv_resps_o' [axi_lite_mux.sv:131]\r\nERROR: [VRFC 10-2991] 'w' is not declared under prefix 'slv_reqs_i' [axi_lite_mux.sv:222]\r\nERROR: [VRFC 10-2991] 'w_valid' is not declared under prefix 'slv_reqs_i' [axi_lite_mux.sv:223]\r\n\r\nI realized that the `axi_lite_mux` instantiation lacks the definition of the `axi_req_t` and `axi_resp_t` types, which are `logic` by default. I added these two lines and it works as expected:\r\n``` \r\naxi_lite_mux #(\r\n    .aw_chan_t     ( aw_chan_t     ), // AW Channel Type\r\n    .w_chan_t      (  w_chan_t     ), //  W Channel Type\r\n    .b_chan_t      (  b_chan_t     ), //  B Channel Type\r\n    .ar_chan_t     ( ar_chan_t     ), // AR Channel Type\r\n    .r_chan_t      (  r_chan_t     ), //  R Channel Type\r\n+   .axi_req_t     ( axi_req_t     ),\r\n+   .axi_resp_t    ( axi_resp_t    ),\r\n    .NoSlvPorts    ( NoSlvPorts    ), // Number of slave ports\r\n    .MaxTrans      ( MaxTrans      ),\r\n    .FallThrough   ( FallThrough   ),\r\n    .SpillAw       ( SpillAw       ),\r\n    .SpillW        ( SpillW        ),\r\n    .SpillB        ( SpillB        ),\r\n    .SpillAr       ( SpillAr       ),\r\n    .SpillR        ( SpillR        )\r\n) \r\n```\r\nSo probably this is just it, or am I doing something wrong?\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/pulp-platform_axi_pr224", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/pulp-platform_axi_pr224.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/pulp-platform_axi_pr224", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/pulp-platform_axi_pr224"}
{"instance_id": "pulp-platform_axi_pr228", "issue_text": "# AXI_BUS instead of AXI_LITE in axi_lite_mux_intf\n\nI am having issues elaborating `axi_lite_mux_intf` with Verilator. Basically it complains that it expects an `AXI_BUS` interface but it is getting an `AXI_LITE` one:\r\n\r\n```\r\n%Error: /path/Top_asic.sv:2000:6: Port 'mst' expects 'AXI_BUS' interface but pin connects 'AXI_LITE' interface\r\n: ... In instance chip_top.Top_asic_inst\r\n 2000 |     .mst      (axi_sauria)\r\n```\r\nThis is because in the module definition of `axi_lite_mux_intf` (in `axi_lite_mux.sv`) we have:\r\n\r\n```\r\n(\r\n  input  logic   clk_i,                // Clock\r\n  input  logic   rst_ni,               // Asynchronous reset active low\r\n  input  logic   test_i,               // Testmode enable\r\n  AXI_BUS.Slave  slv [NoSlvPorts-1:0], // slave ports\r\n  AXI_BUS.Master mst                   // master port\r\n);\r\n```\r\n\r\nWhere the ports `slv` and `mst` are incorrectly declared as `AXI_BUS`. Changing both to `AXI_LITE` seems to solve the problem for me.\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/pulp-platform_axi_pr228", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/pulp-platform_axi_pr228.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/pulp-platform_axi_pr228", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/pulp-platform_axi_pr228"}
{"instance_id": "pulp-platform_axi_pr245", "issue_text": "# axi_lite_mux: Reduce complexity of master port W channel\n\nInstance: pulp-platform_axi_pr245\nSource: https://github.com/pulp-platform/axi/pull/245\nFetched: 2026-05-03\nRepository: pulp-platform/axi\nPull request: #245\nAuthor: andreaskurth\nState: closed\nBase branch: master\nHead branch: axi_lite_mux-shorten-mst_w_chan\nCreated: 2022-08-06\nUpdated: 2022-08-06\nClosed: 2022-08-06\nMerged: 2022-08-06\n\n## PR Title\naxi_lite_mux: Reduce complexity of master port W channel\n\n## PR Description\nReduce complexity of W channel at master port by removing an unnecessary multiplexer. Resolves #243.\n\n## PR Comments\n\n**andreaskurth** (Aug 6, 2022):\nPosted the PR description above with reference to issue #243.\n\n## Linked Issues\n\n**Issue #243: Tie mst_w_chan to '0 when mst_w_valid!=0.**\nThe reporter referenced the assignment in `axi_lite_mux.sv`, observing that the muxes seem redundant and asking whether this is on purpose. If not, the muxes could be removed and replaced with `assign mst_w_chan = slv_reqs_i[w_select].w;`.\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/pulp-platform_axi_pr245", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/pulp-platform_axi_pr245.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/pulp-platform_axi_pr245", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/pulp-platform_axi_pr245"}
{"instance_id": "pulp-platform_axi_pr293", "issue_text": "# axi_pkg: keep hardcoded value in typedef for vivado ip packager\n\nInstance: pulp-platform_axi_pr293\nSource: https://github.com/pulp-platform/axi/pull/293\nFetched: 2026-05-03\nRepository: pulp-platform/axi\nPull request: #293\nAuthor: CyrilKoe\nState: closed\nBase branch: master\nHead branch: issue/axi_pkg_typedef\nCreated: 2023-03-29\nUpdated: 2023-05-08\nClosed: 2023-05-08\nMerged: 2023-05-08\n\n## PR Title\naxi_pkg: keep hardcoded value in typedef for vivado ip packager\n\n## PR Description\nSince commit fe4e020, the typedef `axi_pkg::burst_t` relied on a Verilog parameter `BurstWidth`. This caused compatibility issues when using these typedefs in custom Vivado IP ports, as \"the IP ports are contained within the port description of the HDL file.\" The proposed solution defines the typedef with a numerical value, then bases the parameter on the `$size` of this typedef.\n\n## PR Comments\n\n**CyrilKoe** (Mar 29, 2023):\nReferenced issue #292 and linked to commit d2f98d6 showing the proposition for the fix.\n\n**thommythomaso** (May 8, 2023):\nSelf-assigned the PR, force-pushed commits 4b20954 and 7b0db8e, then merged the PR into master. Deleted the branch afterward.\n\n## Linked Issues\n\n**Issue #292: axi_pkg::LenWidth not compatible with vivado IP packager**\nSince commit fe4e020 the typedef `axi_pkg::burst_t` now relies on a Verilog parameter `BurstWidth`. In Occamy emulation these typedefs are used at the ports of a custom packaged Vivado IP. But Vivado requires that \"the IP ports are contained within the port description of the HDL file\". So custom Vivado IPs can't use `axi_pkg::burst_t` at their top anymore. A possible fix is to define the typedef with a numerical value and then the parameter based on the `$size` of this typedef. See proposition in commit d2f98d6.\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/pulp-platform_axi_pr293", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/pulp-platform_axi_pr293.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/pulp-platform_axi_pr293", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/pulp-platform_axi_pr293"}
{"instance_id": "pulp-platform_axi_pr74", "issue_text": "# Verilator compile issues\n\nI am working on simulating the AXI4 code in Verilator and are running into a problem with the parameter types of the modules. The issue is the `parameter type resp_t = logic` definition in al modules. However renaming the definitions to `parameter type rsp_t = logic` seems to not trigger the issue. I think the issue could be that in `axi_pkg` the parameter `resp_t` is already defined and part of the response struct which is the parameter which has this problem. \r\nShould I do a fix for all modules, this will however break all other projects which are using the new AXI4 infrastructure currently. \r\n\r\nRelated to Verilator: In #43 there is in file `src/axi_dw_upsizer.sv` line 321 a struct definition for `r_req_d` and `r_req_q` inside a generate. Verilator complains about multiple type definitions.\r\nI was able to fix this by declaring a separate typedef outside the generate and defining the signals separate in the generate:\r\n\r\n```systemverilog\r\ntypedef struct packed {\r\n      ar_chan_t ar         ;\r\n      logic ar_valid       ;\r\n      logic ar_throw_error ;\r\n      slv_r_chan_t r       ;\r\n      logic r_valid        ;\r\n      burst_len_t burst_len;\r\n      size_t orig_ar_size  ;\r\n} r_req_t;\r\n\r\n// code\r\n\r\nfor (genvar ...\r\n  r_req_t r_req_d, r_req_q;\r\nend\r\n```\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/pulp-platform_axi_pr74", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/pulp-platform_axi_pr74.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/pulp-platform_axi_pr74", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/pulp-platform_axi_pr74"}
{"instance_id": "pulp-platform_axi_riscv_atomics_pr1", "issue_text": "# Release v0.1\n\nInstance: pulp-platform_axi_riscv_atomics_pr1\nSource: https://github.com/pulp-platform/axi_riscv_atomics/pull/1\nFetched: 2026-04-26\nRepository: pulp-platform/axi_riscv_atomics\nPull request: #1\nAuthor: andreaskurth\nState: closed\nBase branch: master\nHead branch: release-0.1\nCreated: 2019-02-19T12:27:07Z\nUpdated: 2019-02-20T15:45:08Z\nClosed: 2019-02-19T17:06:47Z\nMerged: 2019-02-19T17:06:47Z\n\n## PR Title\nRelease v0.1\n\n## PR Description\n(No PR body provided.)\n\n## PR Comments\nNo substantive comments were recorded in the conversation thread.\n\n## Linked Issues\nNo linked issues are referenced in this pull request.\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/pulp-platform_axi_riscv_atomics_pr1", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/pulp-platform_axi_riscv_atomics_pr1.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/pulp-platform_axi_riscv_atomics_pr1", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/pulp-platform_axi_riscv_atomics_pr1"}
{"instance_id": "pulp-platform_axi_riscv_atomics_pr12", "issue_text": "# axi_riscv_amos: Cleanup\n\nInstance: pulp-platform_axi_riscv_atomics_pr12\nSource: https://github.com/pulp-platform/axi_riscv_atomics/pull/12\nFetched: 2026-04-26\nRepository: pulp-platform/axi_riscv_atomics\nPull request: #12\nAuthor: SamuelRiedel\nState: closed\nBase branch: master\nHead branch: cleanup\nCreated: 2019-02-28T18:00:59Z\nUpdated: 2019-02-28T18:55:49Z\nClosed: 2019-02-28T18:34:12Z\nMerged: 2019-02-28T18:34:12Z\n\n## PR Title\naxi_riscv_amos: Cleanup\n\n## PR Description\nClean up the state machines to reduce duplicate code.\nMake the signal naming more consistent.\n\n## PR Comments\n\n**SamuelRiedel** (Feb 28, 2019):\n\"Clean up the state machines to reduce duplicate code. Make the signal naming more consistent.\"\n\n**andreaskurth** (Feb 28, 2019):\n\"👌 Perfect, thanks! I will sign and merge.\"\n\n## Linked Issues\nNo linked issues are referenced in this pull request.\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/pulp-platform_axi_riscv_atomics_pr12", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/pulp-platform_axi_riscv_atomics_pr12.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/pulp-platform_axi_riscv_atomics_pr12", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/pulp-platform_axi_riscv_atomics_pr12"}
{"instance_id": "pulp-platform_axi_riscv_atomics_pr13", "issue_text": "# amos: Change to incremental burst type\n\nInstance: pulp-platform_axi_riscv_atomics_pr13\nSource: https://github.com/pulp-platform/axi_riscv_atomics/pull/13\nFetched: 2026-04-26\nRepository: pulp-platform/axi_riscv_atomics\nPull request: #13\nAuthor: zarubaf\nState: closed\nBase branch: master\nHead branch: fix/incr-burst-type\nCreated: 2021-05-12T09:55:45Z\nUpdated: 2022-09-29T07:56:23Z\nClosed: 2021-05-12T16:02:07Z\nMerged: 2021-05-12T16:02:07Z\n\nIt seems that the most widely supported burst types are INCR and WRAP bursts, at least on\r\nthe Xilinx infrastructure. I am pretty confident that most of the infrastructure should have\r\nINCR bursts implemented since this is one of the main benefits of having an AXI-based\r\ninfrastructure.\r\n\r\nIn particular, this change fixes the burst type to incremental of the split RMW sequence, essentially\r\nmitigating an issue of the Xilinx SmartConnect blocks which do not support FIXED bursts.\r\n\r\nTwo notes:\r\n\r\n1. I realize this could also be implemented as a parameter. Given the above assumption I would still prefer to hard-code this in the module since this makes this module, IMHO, a little bit easier to use (no need to worry about).\r\n2. In case it is too controversial of a change, I can also live with a patch outside this repo.\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/pulp-platform_axi_riscv_atomics_pr13", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/pulp-platform_axi_riscv_atomics_pr13.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/pulp-platform_axi_riscv_atomics_pr13", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/pulp-platform_axi_riscv_atomics_pr13"}
{"instance_id": "pulp-platform_axi_riscv_atomics_pr15", "issue_text": "# Guarantee atomicity by tracking downstream transactions\n\nInstance: pulp-platform_axi_riscv_atomics_pr15\nSource: https://github.com/pulp-platform/axi_riscv_atomics/pull/15\nFetched: 2026-05-03\nRepository: pulp-platform/axi_riscv_atomics\nPull request: #15\nAuthor: SamuelRiedel\nState: closed\nBase branch: master\nHead branch: testbench\nCreated: 2022-02-23\nUpdated: 2022-03-11\nClosed: 2022-03-11\nMerged: 2022-03-11\n\n## PR Title\nGuarantee atomicity by tracking downstream transactions\n\n## PR Description\nThis PR adds several updates to the axi_riscv_atomics repository:\n\n- `axi_riscv_lrsc`: Tracks downstream writes to guarantee atomicity, addressing cases where reads can overtake writes in the downstream AXI bus, violating atomicity guarantees.\n- `axi_riscv_amos`: Uses the updated `axi_riscv_lrsc` module to guarantee atomicity of atomic memory operations without duplicating logic; translates AMOs into LR and SC operations.\n- `axi_riscv_atomics_tb`: Adds a testbench to verify both modules together.\n\nThe PR initially contained a bug identified in issue #16, which was subsequently fixed.\n\n## PR Comments\n\n**SamuelRiedel** (Feb 23, 2022):\nRequested review from andreaskurth, noting the PR contains WIP commits that looked good and offering to split into multiple PRs if preferred.\n\n**SamuelRiedel** (Mar 11, 2022):\nIndicated readiness pending AXI upstream changes and official release.\n\n**andreaskurth** (Mar 11, 2022):\nApproved changes; released axi v0.35.0.\n\n**SamuelRiedel** (Mar 11, 2022):\nConfirmed new AXI release works as expected; approved for merge.\n\n## Linked Issues\n\n**Issue #3: Add unit and top-level TBs to repo**\nRequires some common verification modules to be updated first.\n\n**Issue #4: Fix ordering guarantees for multiple outstanding and conflicting SWs/SCs/AMOs**\n(Closed by this PR; body not available.)\n\n**Issue #16: typedef typo in axi_riscv_lrsc.sv**\n(Closed by this PR; body not available.)\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/pulp-platform_axi_riscv_atomics_pr15", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/pulp-platform_axi_riscv_atomics_pr15.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/pulp-platform_axi_riscv_atomics_pr15", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/pulp-platform_axi_riscv_atomics_pr15"}
{"instance_id": "pulp-platform_axi_riscv_atomics_pr17", "issue_text": "# Make handling of illegal ATOPs conform with the axi repo\n\nInstance: pulp-platform_axi_riscv_atomics_pr17\nSource: https://github.com/pulp-platform/axi_riscv_atomics/pull/17\nFetched: 2026-04-26\nRepository: pulp-platform/axi_riscv_atomics\nPull request: #17\nAuthor: SamuelRiedel\nState: closed\nBase branch: master\nHead branch: axi-conformity\nCreated: 2022-03-16T21:31:14Z\nUpdated: 2022-09-29T07:56:18Z\nClosed: 2022-04-06T15:43:12Z\nMerged: 2022-04-06T15:43:12Z\n\nEnsure the way unspecified/illegal ATOP opcodes are treated is aligned with how the modules in the AXI repository do it.\r\n\r\n- Issue an R response to all ATOPs where the `axi_pkg::ATOP_R_RESP` bit is set.\r\n- Treat all opcodes with `slv_aw_atop_i[5:4] == axi_pkg::ATOP_NONE` as non-ATOPs and simply forward them instead of issuing an error response.\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/pulp-platform_axi_riscv_atomics_pr17", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/pulp-platform_axi_riscv_atomics_pr17.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/pulp-platform_axi_riscv_atomics_pr17", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/pulp-platform_axi_riscv_atomics_pr17"}
{"instance_id": "pulp-platform_axi_riscv_atomics_pr18", "issue_text": "# Allow using the `aw_user` signal as a reservation ID\n\nInstance: pulp-platform_axi_riscv_atomics_pr18\nSource: https://github.com/pulp-platform/axi_riscv_atomics/pull/18\nFetched: 2026-04-26\nRepository: pulp-platform/axi_riscv_atomics\nPull request: #18\nAuthor: SamuelRiedel\nState: closed\nBase branch: master\nHead branch: user-signal\nCreated: 2022-03-16T21:38:28Z\nUpdated: 2022-09-29T07:56:16Z\nClosed: 2022-04-13T08:44:38Z\nMerged: 2022-04-13T08:44:38Z\n\nTo decouple the size of the reservation table from the AXI ID width and eliminate the constraint of having a unique and consistent ID for each master, we add a parameter that uses the AXI user signal as the reservation ID instead of the AXI ID signal. This enables us to add ID width converters in front of the ATUN and that we do not have to allocate space in the reservation table for masters which do not issue atomics.\r\n\r\nTo enable this feature, set `AXI_USER_AS_ID` to one and specify which bits in the AW channel's user signal will be used for the reservation ID with: `reservation id = aw_user[AXI_USER_ID_MSB:AXI_USER_ID_LSB]`\r\n\r\n- [x] PR depends on #17 \r\n- [x] Update AXI with latest release\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/pulp-platform_axi_riscv_atomics_pr18", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/pulp-platform_axi_riscv_atomics_pr18.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/pulp-platform_axi_riscv_atomics_pr18", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/pulp-platform_axi_riscv_atomics_pr18"}
{"instance_id": "pulp-platform_axi_riscv_atomics_pr22", "issue_text": "# `axi_riscv_atomics`: Add new wrapper using structs\n\nInstance: pulp-platform_axi_riscv_atomics_pr22\nSource: https://github.com/pulp-platform/axi_riscv_atomics/pull/22\nFetched: 2026-04-26\nRepository: pulp-platform/axi_riscv_atomics\nPull request: #22\nAuthor: paulsc96\nState: closed\nBase branch: master\nHead branch: feature/structs\nCreated: 2023-03-09T18:33:10Z\nUpdated: 2023-07-03T15:07:11Z\nClosed: 2023-03-24T21:06:46Z\nMerged: 2023-03-24T21:06:46Z\n\nThis adds a wrapper for `axi_riscv_atomics` using AXI request and response structs for IO, simplifying its use in systems with struct-based interconnects.\r\n\r\nIf you choose to merge this, a new release would be appreciated.\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/pulp-platform_axi_riscv_atomics_pr22", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/pulp-platform_axi_riscv_atomics_pr22.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/pulp-platform_axi_riscv_atomics_pr22", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/pulp-platform_axi_riscv_atomics_pr22"}
{"instance_id": "pulp-platform_axi_riscv_atomics_pr23", "issue_text": "# axi_riscv_lrsc: Set reservation granularity to AXI DW\n\nInstance: pulp-platform_axi_riscv_atomics_pr23\nSource: https://github.com/pulp-platform/axi_riscv_atomics/pull/23\nFetched: 2026-04-26\nRepository: pulp-platform/axi_riscv_atomics\nPull request: #23\nAuthor: niwis\nState: closed\nBase branch: master\nHead branch: lrsc-granul\nCreated: 2023-06-27T16:35:14Z\nUpdated: 2023-07-03T12:14:35Z\nClosed: 2023-07-03T12:13:57Z\nMerged: 2023-07-03T12:13:57Z\n\n## PR Title\naxi_riscv_lrsc: Set reservation granularity to AXI DW\n\n## PR Description\n... and parametrise it. The reason is that an AXI beat can write up to `AXI_DATA_WIDTH` bits and should therefore clear any reservations in an `AXI_DATA_WIDTH` range. We could also set the default value for `AXI_ADDR_LSB` to `2` to keep this behaviorally equivalent.\n\n## PR Comments\n\n**niwis** (Jun 27, 2023):\nProvided the rationale for the changes, explaining that reservation clearing should align with AXI data width capabilities.\n\n**SamuelRiedel** (Jul 3, 2023):\n\"LGTM. Thanks 👍\"\n\n## Linked Issues\nNo linked issues are referenced in this pull request.\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/pulp-platform_axi_riscv_atomics_pr23", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/pulp-platform_axi_riscv_atomics_pr23.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/pulp-platform_axi_riscv_atomics_pr23", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/pulp-platform_axi_riscv_atomics_pr23"}
{"instance_id": "pulp-platform_axi_riscv_atomics_pr26", "issue_text": "# axi_riscv_lrsc: Support AXI write bursts\n\nInstance: pulp-platform_axi_riscv_atomics_pr26\nSource: https://github.com/pulp-platform/axi_riscv_atomics/pull/26\nFetched: 2026-04-26\nRepository: pulp-platform/axi_riscv_atomics\nPull request: #26\nAuthor: niwis\nState: closed\nBase branch: master\nHead branch: lrsc-burst\nCreated: 2023-07-03T12:30:50Z\nUpdated: 2023-07-03T14:13:32Z\nClosed: 2023-07-03T14:13:22Z\nMerged: 2023-07-03T14:13:21Z\n\nAdd support for AXI write bursts onto memory regions that may have reservations. In particular:\r\n- check and clear all reservations affected by an AXI write burst sequentially using an FSM in the AW handler,\r\n- stall `lr`s while there is a write in flight onto the same *page* (previously: *address*),\r\n- stall write burst AWs while there is an exclusive access in flight onto the same page.\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/pulp-platform_axi_riscv_atomics_pr26", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/pulp-platform_axi_riscv_atomics_pr26.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/pulp-platform_axi_riscv_atomics_pr26", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/pulp-platform_axi_riscv_atomics_pr26"}
{"instance_id": "pulp-platform_axi_riscv_atomics_pr27", "issue_text": "# [fix] lrsc: Add missing sequential logic for aw_wait reg\n\nInstance: pulp-platform_axi_riscv_atomics_pr27\nSource: https://github.com/pulp-platform/axi_riscv_atomics/pull/27\nFetched: 2026-04-26\nRepository: pulp-platform/axi_riscv_atomics\nPull request: #27\nAuthor: niwis\nState: closed\nBase branch: master\nHead branch: fix/aw_wait\nCreated: 2023-08-02T15:42:06Z\nUpdated: 2023-08-02T20:47:22Z\nClosed: 2023-08-02T16:42:57Z\nMerged: 2023-08-02T16:42:57Z\n\n## PR Title\n[fix] lrsc: Add missing sequential logic for aw_wait reg\n\n## PR Description\nNot sure how this was missed so far.\n\n## PR Comments\n\n**niwis** (Aug 2, 2023):\n\"Not sure how this was missed so far\"\n\n**SamuelRiedel** (Aug 2, 2023):\n\"Thanks! I also wonder how we could have missed this. But it indicates that the testbench never reaches the `AW_BURST` state. We have to double-check this.\"\n\n## Linked Issues\nNo linked issues are referenced in this pull request.\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/pulp-platform_axi_riscv_atomics_pr27", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/pulp-platform_axi_riscv_atomics_pr27.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/pulp-platform_axi_riscv_atomics_pr27", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/pulp-platform_axi_riscv_atomics_pr27"}
{"instance_id": "pulp-platform_axi_riscv_atomics_pr28", "issue_text": "# Enable full bandwidth on ID queues for performance\n\nInstance: pulp-platform_axi_riscv_atomics_pr28\nSource: https://github.com/pulp-platform/axi_riscv_atomics/pull/28\nFetched: 2026-04-26\nRepository: pulp-platform/axi_riscv_atomics\nPull request: #28\nAuthor: micprog\nState: closed\nBase branch: master\nHead branch: michaero/perf\nCreated: 2023-09-28T20:45:33Z\nUpdated: 2025-05-07T15:22:19Z\nClosed: 2023-10-04T15:26:12Z\nMerged: 2023-10-04T15:26:12Z\n\n## PR Title\nEnable full bandwidth on ID queues for performance\n\n## PR Description\n(No PR body provided.)\n\n## PR Comments\n\n**micprog** (Sep 28, 2023):\nRequested review from SamuelRiedel and thommythomaso.\n\n**SamuelRiedel** (Oct 4, 2023):\n\"Thanks, this looks good to me.\" (approved the changes)\n\n**SamuelRiedel** (Oct 4, 2023):\nMerged commit 9c6a0c8 into master.\n\n**micprog** (May 7, 2025):\nDeleted the michaero/perf branch.\n\n## Linked Issues\nNo linked issues are referenced in this pull request.\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/pulp-platform_axi_riscv_atomics_pr28", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/pulp-platform_axi_riscv_atomics_pr28.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/pulp-platform_axi_riscv_atomics_pr28", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/pulp-platform_axi_riscv_atomics_pr28"}
{"instance_id": "pulp-platform_axi_riscv_atomics_pr31", "issue_text": "# lrsc: Fix burst invalidation length\n\nInstance: pulp-platform_axi_riscv_atomics_pr31\nSource: https://github.com/pulp-platform/axi_riscv_atomics/pull/31\nFetched: 2026-05-03\nRepository: pulp-platform/axi_riscv_atomics\nPull request: #31\nAuthor: niwis\nState: closed\nBase branch: master\nHead branch: nwistoff/lrsc-burst-len\nCreated: 2023-10-02\nUpdated: 2023-10-05\nClosed: 2023-10-05\nMerged: 2023-10-05\n\n## PR Title\nlrsc: Fix burst invalidation length\n\n## PR Description\nTerminate invalidation after the last beat. Fixes #30.\n\n## PR Comments\n\n**niwis** (Oct 2, 2023):\nRequested review from SamuelRiedel.\n\n**SamuelRiedel** (Oct 5, 2023):\nForce-pushed the branch with commit 427f84d.\n\n**SamuelRiedel** (Oct 5, 2023):\nMerged commit 424697e into master and deleted the nwistoff/lrsc-burst-len branch.\n\n## Linked Issues\n\n**Issue #30: AW burst of length N clears N+1 addresses**\nWhen an AW burst of length N with start address A is sent to the axi_riscv_lrsc module, it submits a check+clear request for addresses [A, A+N], but the correct range would be [A, A+(N-1)]. Probably it would be sufficient to change line 761 from `clr_len_d = aw_res_len - 1;` to `clr_len_d = aw_res_len - 2;`.\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/pulp-platform_axi_riscv_atomics_pr31", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/pulp-platform_axi_riscv_atomics_pr31.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/pulp-platform_axi_riscv_atomics_pr31", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/pulp-platform_axi_riscv_atomics_pr31"}
{"instance_id": "pulp-platform_axi_riscv_atomics_pr33", "issue_text": "# Enable ID queues full bandwidth feature through parameter.\n\nInstance: pulp-platform_axi_riscv_atomics_pr33\nSource: https://github.com/pulp-platform/axi_riscv_atomics/pull/33\nFetched: 2026-04-26\nRepository: pulp-platform/axi_riscv_atomics\nPull request: #33\nAuthor: yvantor\nState: closed\nBase branch: master\nHead branch: astral\nCreated: 2024-04-17T05:47:45Z\nUpdated: 2024-05-08T10:12:37Z\nClosed: 2024-05-08T10:12:36Z\nMerged: 2024-05-08T10:12:36Z\n\n## PR Title\nEnable ID queues full bandwidth feature through parameter.\n\n## PR Description\n(No PR body provided.)\n\n## PR Comments\n\n**yvantor** (Apr 17, 2024):\nRequested review from SamuelRiedel.\n\n**SamuelRiedel** (Apr 30, 2024):\n\"Thanks. Generally, it looks good to me, but could you change the default to 1 to not change the default for other designs?\"\n\n**yvantor** (May 8, 2024):\n\"Should be done, thank you!\"\n\n**SamuelRiedel** (May 8, 2024):\nApproved the changes and merged the PR.\n\n## Linked Issues\nNo linked issues are referenced in this pull request.\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/pulp-platform_axi_riscv_atomics_pr33", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/pulp-platform_axi_riscv_atomics_pr33.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/pulp-platform_axi_riscv_atomics_pr33", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/pulp-platform_axi_riscv_atomics_pr33"}
{"instance_id": "pulp-platform_axi_riscv_atomics_pr35", "issue_text": "# Fix Non-Blocking Assignment in LRSC FF\n\nInstance: pulp-platform_axi_riscv_atomics_pr35\nSource: https://github.com/pulp-platform/axi_riscv_atomics/pull/35\nFetched: 2026-04-26\nRepository: pulp-platform/axi_riscv_atomics\nPull request: #35\nAuthor: domenicw\nState: closed\nBase branch: master\nHead branch: domenicw/fix/lrsc_ff_non_blocking\nCreated: 2024-04-29T07:18:39Z\nUpdated: 2024-04-29T15:43:08Z\nClosed: 2024-04-29T15:43:07Z\nMerged: 2024-04-29T15:43:07Z\n\n## PR Title\nFix Non-Blocking Assignment in LRSC FF\n\n## PR Description\nThe blocking assignment causes the `clr_len_q` to take an incorrect value during consecutive AXI bursts (value zero from the proceeding burst instead of the actual value). This leads to an underflow of the length value and the counter has to decrement until it reaches one and the `AW_BURST` state can finally be left. This issue was discovered under Verilator. The fix results in a 10x simulation speed improvement.\n\n## PR Comments\n\n**domenicw** (Apr 29, 2024):\nSubmitted the PR with the description above.\n\n**SamuelRiedel** (Apr 29, 2024):\n\"Good catch. Thanks a lot. The internal CI also passed, of course. :)\"\n\n## Linked Issues\nNo linked issues are referenced in this pull request.\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/pulp-platform_axi_riscv_atomics_pr35", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/pulp-platform_axi_riscv_atomics_pr35.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/pulp-platform_axi_riscv_atomics_pr35", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/pulp-platform_axi_riscv_atomics_pr35"}
{"instance_id": "pulp-platform_axi_riscv_atomics_pr37", "issue_text": "# Improve code style\n\nInstance: pulp-platform_axi_riscv_atomics_pr37\nSource: https://github.com/pulp-platform/axi_riscv_atomics/pull/37\nFetched: 2026-04-26\nRepository: pulp-platform/axi_riscv_atomics\nPull request: #37\nAuthor: niwis\nState: closed\nBase branch: master\nHead branch: nw/lrsc-seq-nonblock\nCreated: 2024-07-25T18:42:36Z\nUpdated: 2025-05-07T08:33:44Z\nClosed: 2025-05-07T08:33:42Z\nMerged: 2025-05-07T08:33:42Z\n\nThis aligns coding style and fixes Verilator warnings:\r\n- `axi_riscv_lrsc`: Use non-blocking assignments in sequential block.\r\n- `axi_res_tbl`: Declare the `match` signal outside the `always_comb` block.\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/pulp-platform_axi_riscv_atomics_pr37", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/pulp-platform_axi_riscv_atomics_pr37.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/pulp-platform_axi_riscv_atomics_pr37", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/pulp-platform_axi_riscv_atomics_pr37"}
{"instance_id": "pulp-platform_axi_riscv_atomics_pr38", "issue_text": "# Make the `CUT_OUP_POP_INP_GNT` ID queue parameter user visible and bump common cells\n\nInstance: pulp-platform_axi_riscv_atomics_pr38\nSource: https://github.com/pulp-platform/axi_riscv_atomics/pull/38\nFetched: 2026-04-26\nRepository: pulp-platform/axi_riscv_atomics\nPull request: #38\nAuthor: ricted98\nState: closed\nBase branch: master\nHead branch: rt/id-queue-cut-oup-pop-inp-gnt\nCreated: 2024-08-22T08:28:11Z\nUpdated: 2024-08-26T14:15:12Z\nClosed: 2024-08-26T14:15:09Z\nMerged: 2024-08-26T14:15:09Z\n\nThe use of `FULL_BANDWIDTH=1` ID queues paired with `CUT_OUP_POP_INP_GNT=0` (default value) might lead to combinational loops with downstream IPs. Cutting the combinational path between input and output solves the problem.\r\n\r\nThis PR extends https://github.com/pulp-platform/axi_riscv_atomics/pull/34 to make the `CUT_OUP_POP_INP_GNT` parameter user visible and bumps the `common_cells` dependency.\r\n\r\nWould it be better to allow more granularity, i.e. allowing for individual ID queues tuning?\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/pulp-platform_axi_riscv_atomics_pr38", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/pulp-platform_axi_riscv_atomics_pr38.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/pulp-platform_axi_riscv_atomics_pr38", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/pulp-platform_axi_riscv_atomics_pr38"}
{"instance_id": "pulp-platform_axi_riscv_atomics_pr39", "issue_text": "# Add support for limited number of reservations\n\nInstance: pulp-platform_axi_riscv_atomics_pr39\nSource: https://github.com/pulp-platform/axi_riscv_atomics/pull/39\nFetched: 2026-04-26\nRepository: pulp-platform/axi_riscv_atomics\nPull request: #39\nAuthor: micprog\nState: closed\nBase branch: master\nHead branch: num_reservations\nCreated: 2025-05-06T15:01:46Z\nUpdated: 2026-02-19T15:39:18Z\nClosed: 2026-02-19T15:39:16Z\nMerged: 2026-02-19T15:39:16Z\n\n## PR Title\nAdd support for limited number of reservations\n\n## PR Description\nIf limited LR/SC support is OK, NUM_RESERVATIONS can be set to reduce how many active atomics are supported, significantly improving PPA. This means that some reservations may be cleared without another actor accessing that address, as too many actors are reserving at the same time. If the parameter is not set, existing code will remain, so is backwards-compatible.\n\n## PR Comments\n\n**micprog** (May 6, 2025):\nProvided initial description explaining the feature's purpose and backward compatibility.\n\n**paulsc96** (May 7, 2025):\nApproved the changes after reviewing the pull request files.\n\n## Linked Issues\nNo linked issues are referenced in this pull request.\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/pulp-platform_axi_riscv_atomics_pr39", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/pulp-platform_axi_riscv_atomics_pr39.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/pulp-platform_axi_riscv_atomics_pr39", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/pulp-platform_axi_riscv_atomics_pr39"}
{"instance_id": "pulp-platform_carfield_pr27", "issue_text": "# hw: Bump security island\n\nInstance: pulp-platform_carfield_pr27\nSource: https://github.com/pulp-platform/carfield/pull/27\nFetched: 2026-05-03\nRepository: pulp-platform/carfield\nPull request: #27\nAuthor: alex96295\nState: closed\nBase branch: main\nHead branch: aottaviano/synth-fix\nCreated: 2023-05-09\nUpdated: 2023-07-21\nClosed: 2023-05-09\nMerged: 2023-05-09\n\n## PR Title\nhw: Bump security island\n\n## PR Description\nRemove behavioral string parameters: use combinational ROM and OTP. Fixes #26.\n\n## PR Comments\n\n**alex96295** (May 9, 2023):\n\"Remove behavioral string parameters: use combinational ROM and OTP\" / \"Fixes #26\"\n\n**alex96295** (May 9, 2023):\nAdded the bug label.\n\n**alex96295** (May 9, 2023):\nSelf-assigned the PR.\n\n**alex96295** (May 9, 2023):\nRequested review from luca-valente as code owner.\n\n**alex96295** (May 9, 2023):\nMerged commit 37d82b5 into main.\n\n**micprog** (Jul 21, 2023):\nDeleted the aottaviano/synth-fix branch.\n\n## Linked Issues\n\n**Issue #26: SYNTHESIS ERROR**\nLine 294 and 295 of carfield_pkg generate synthesis errors:\n\"Error: ...carfield_pkg.sv:294: The construct 'string' is not supported in synthesis.\"\n\"Error: ...carfield_pkg.sv:295: The construct 'string' is not supported in synthesis.\"\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/pulp-platform_carfield_pr27", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/pulp-platform_carfield_pr27.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/pulp-platform_carfield_pr27", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/pulp-platform_carfield_pr27"}
{"instance_id": "pulp-platform_carfield_pr41", "issue_text": "# Add atomics support to shared L2 memory\n\nInstance: pulp-platform_carfield_pr41\nSource: https://github.com/pulp-platform/carfield/pull/41\nFetched: 2026-05-03\nRepository: pulp-platform/carfield\nPull request: #41\nAuthor: alex96295\nState: closed\nBase branch: main\nHead branch: aottaviano/l2-atomics\nCreated: 2023-05-17\nUpdated: 2023-05-30\nClosed: 2023-05-30\nMerged: 2023-05-30\n\n## PR Title\nAdd atomics support to shared L2 memory\n\n## PR Description\nExpose extra parameters to config the `axi_riscv_atomics_structs`. They default to Cheshire, which is fine for now. Fixes #34.\n\n## PR Comments\n\n**alex96295** (May 17, 2023):\n\"Expose extra parameters to config the `axi_riscv_atomics_structs`. They default to Cheshire, which is fine for now.\"\n\n**husterZC** (May 17, 2023):\n\"Aha ;) , Thanks Ale!\"\n\n**husterZC** (May 17, 2023):\n\"Should we also change the `Bender.lock` there?\"\n\n**alex96295** (May 17, 2023):\n\"I upstreamed it\"\n\n**alex96295** (May 21, 2023):\n\"Rebased onto main\"\n\n**alex96295** (May 30, 2023):\n\"Rebased onto main\"\n\n**alex96295** (May 30, 2023):\n\"lgtm\"\n\n## Linked Issues\n\n**Issue #34: Check `atomics`: `axi_riscv_atomics_structs` before the L2 SPM**\nAtomics support is needed towards every memory inside `carfield`. `Cheshire` already instantiates `axi_riscv_atomics_structs` before the main memory, the debug module and the `idma` slave port. We need it before the `L2SPM`.\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/pulp-platform_carfield_pr41", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/pulp-platform_carfield_pr41.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/pulp-platform_carfield_pr41", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/pulp-platform_carfield_pr41"}
{"instance_id": "pulp-platform_cheshire_pr189", "issue_text": "# hw: Fix uncached SPM execute region\n\nInstance: pulp-platform_cheshire_pr189\nSource: https://github.com/pulp-platform/cheshire/pull/189\nFetched: 2026-04-26\nRepository: pulp-platform/cheshire\nPull request: #189\nAuthor: paulsc96\nState: closed\nBase branch: main\nHead branch: paulsc/spmu-ex\nCreated: 2025-03-28T11:57:58Z\nUpdated: 2025-04-13T18:42:51Z\nClosed: 2025-04-13T18:42:50Z\nMerged: 2025-04-13T18:42:50Z\n\nFixes #188.\r\n\r\nChanges:\r\n\r\n* Add uncached SPM as its own executable region (simplify parameterization a bit in the process)\r\n* Add a test `spm_uncached` executing from uncached SPM and verifying it is not cached\r\n\r\nAdditional changes:\r\n\r\n* Add argument to DMA calls to enable dynamic use of decoupling flags (this breaks DMA API compatibility)\r\n* Add `wfi` to default trap handler (this quiets core on exceptions, including on unhandled `ebreak`)\n\n## Local Reproducer Notes\n\n# pulp-platform_cheshire_pr189\n\nMinimal fail-to-pass Verilator case for the uncached SPM execute region fix.\n\nThe buggy configuration models cached and uncached SPM as one large executable region. The patch creates an explicit `AmSpmUnc` region and exposes cached and uncached SPM as separate execute rules.\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/pulp-platform_cheshire_pr189", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/pulp-platform_cheshire_pr189.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/pulp-platform_cheshire_pr189", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/pulp-platform_cheshire_pr189"}
{"instance_id": "pulp-platform_cheshire_pr203", "issue_text": "# treewide: Update iDMA and fix 1D transfers\n\nInstance: pulp-platform_cheshire_pr203\nSource: https://github.com/pulp-platform/cheshire/pull/203\nFetched: 2026-04-26\nRepository: pulp-platform/cheshire\nPull request: #203\nAuthor: alex96295\nState: closed\nBase branch: main\nHead branch: aottaviano/dma\nCreated: 2025-05-07T12:48:47Z\nUpdated: 2025-07-08T20:06:36Z\nClosed: 2025-07-08T20:06:35Z\nMerged: 2025-07-08T20:06:35Z\n\n* [x] Move DMA to Regbus, simplifying interconnect and fixing a known issue with accessing beyond 32-bit boundary\r\n* [x] Fix DMA HAL for 1D transfers (currently not working)\r\n* [x] Update iDMA\r\n* [x] Add new regression test for 1D transfers to CI (https://iis-git.ee.ethz.ch/pulp-restricted/cheshire-nonfree/-/merge_requests/22)\r\n* [x] Fix #208.\r\n* [x] Add new regression test for accesses beyond 32-bit boundary (access over serial link)\n\n## Local Reproducer Notes\n\npulp-platform/cheshire PR 203 reproducer.\n\nThe reduced RTL models the 1D DMA programming path through the AXI-to-register\nadapter.  The buggy snapshot instantiates the legacy adapter, which gates a\nvalid register write with test mode and drops the one-cycle start command.\nThe patch switches the wrapper to the v2 adapter interface used by the PR.\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/pulp-platform_cheshire_pr203", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/pulp-platform_cheshire_pr203.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/pulp-platform_cheshire_pr203", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/pulp-platform_cheshire_pr203"}
{"instance_id": "pulp-platform_clic_pr7", "issue_text": "# Memory Layout\n\n- Source URL: https://github.com/pulp-platform/clic/issues/6\n\nAccording to the RISC-V CLIC spec, the memory layout of the memory mapped registers should be as follows:\r\n```\r\n  0x1000+4*i 1B/input R or RW clicintip[i]\r\n  0x1001+4*i 1B/input RW clicintie[i]\r\n  0x1002+4*i 1B/input RW clicintattr[i]\r\n  0x1003+4*i 1B/input RW clicintctl[i]\r\n  ...\r\n  0x4FFC 1B/input R or RW clicintip[4095]\r\n  0x4FFD 1B/input RW clicintie[4095]\r\n  0x4FFE 1B/input RW clicintattr[4095]\r\n  0x4FFF 1B/input RW clicintctl[4095]\r\n```\r\nThe `clicint[ip/ie/attr/clt]` registers have a width of 1 byte. See https://github.com/riscv/riscv-fast-interrupt/blob/master/clic.adoc#clic-memory-map\r\n\r\nHowever, in the current implementation they are 4 bytes wide.\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/pulp-platform_clic_pr7", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/pulp-platform_clic_pr7.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/pulp-platform_clic_pr7", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/pulp-platform_clic_pr7"}
{"instance_id": "pulp-platform_common_cells_pr132", "issue_text": "# Configurable arbitrary integer clock divider\n\nInstance: pulp-platform_common_cells_pr132\nSource: https://github.com/pulp-platform/common_cells/pull/132\nFetched: 2026-04-26\nRepository: pulp-platform/common_cells\nPull request: #132\nAuthor: meggiman\nState: closed\nBase branch: master\nHead branch: clk_int_div\nCreated: 2022-03-21T00:00:00Z\nUpdated: 2022-03-30T00:00:00Z\nClosed: 2022-03-30T00:00:00Z\nMerged: 2022-03-30T00:00:00Z\n\n## PR Title\nConfigurable arbitrary integer clock divider\n\n## PR Description\nThe existing `clk_div` clock divider module had critical limitations: it was not runtime-configurable and produced extremely unbalanced duty cycles. This PR introduces `clk_int_div`, a new module that guarantees 50% duty cycle output regardless of division factor (supporting both even and odd divisions). The design uses toggle flip-flops with 90 degree phase shift for odd divisions and features a valid-ready handshaked configuration interface that gates the clock during changes to prevent glitching. All sequential logic uses only the input clock, with output consisting exclusively of sequential elements and dedicated clock gating cells. The module includes a dedicated testbench and deprecates the legacy `clk_div` with optional warning messages during elaboration.\n\n## PR Comments\n\n**meggiman** (Mar 21, 2022):\n\"This PR would replace PR #46 solving the mentioned issues with the previous implementation\"\n\n**niwis** (Mar 30, 2022):\n\"Great contribution, thank you a lot @meggiman!\"\n\n## Linked Issues\n\n**Issue #75: clk_div toggles clk output only once**\nThis issue was closed by the PR merge, addressing the fundamental problem with the deprecated clock divider module's output behavior.\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/pulp-platform_common_cells_pr132", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/pulp-platform_common_cells_pr132.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/pulp-platform_common_cells_pr132", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/pulp-platform_common_cells_pr132"}
{"instance_id": "pulp-platform_common_cells_pr151", "issue_text": "# Add stream_join_dynamic IP\n\nInstance: pulp-platform_common_cells_pr151\nSource: https://github.com/pulp-platform/common_cells/pull/151\nFetched: 2026-05-03\nRepository: pulp-platform/common_cells\nPull request: #151\nAuthor: colluca\nState: closed\nBase branch: master\nHead branch: new/stream-join-dynamic\nCreated: 2022-08-12\nUpdated: 2023-09-26\nClosed: 2023-09-26T06:53:00Z\nMerged: 2023-09-26T06:53:00Z\n\n## PR Title\nAdd stream_join_dynamic IP\n\n## PR Description\nThis PR addresses feature request (1) from issue #150.\n\n## PR Comments\n\n**colluca** (Aug 12, 2022):\n\"This PR addresses feature request (1) from issue #150.\"\n\n**niwis** (Aug 12, 2022):\nSuggested merging `stream_join` and `stream_join_dynamic` due to code similarity, proposing either wrapping `stream_join_dynamic` or instantiating `stream_join` with modified valid signal handling.\n\n**colluca** (Aug 12, 2022):\nAgreed with the first option, noting `stream_join_dynamic` is a superset of `stream_join` functionality and keeping `stream_join` only for reduced ports and backward compatibility.\n\n**niwis** (Aug 12, 2022):\nPreferred the second option structurally but agreed both approaches were acceptable without changing `stream_join` interface.\n\n**colluca** (Sep 6, 2022):\nIdentified corner case when mask disables all incoming streams; proposed basing `stream_join` on `stream_join_dynamic` instead for cleaner handling.\n\n**niwis** (Sep 19, 2023):\nRequested rebase onto master to re-run CI before merging.\n\n**niwis** (Sep 26, 2023):\nApproved with thanks.\n\n## Linked Issues\n\n**Issue #150: Stream join dynamic IP with independent input handshakes**\nThis is a feature request to extend the `stream_join` IP or provide the extended functionality in a separate IP. Currently, the `stream_join` IP enforces all of the streams to be joined together and all input handshakes to occur simultaneously, i.e. an input stream is granted ready only after all input streams are valid. Conversely, the request seeks to dynamically select a subset of streams to be joined and allow input streams to be granted independently of each other. Feature (1) is similar to the functionality `stream_fork_dynamic` provides over `stream_fork`. The `stream_fork` IP is \"specular\" in its functionality to `stream_join`.\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/pulp-platform_common_cells_pr151", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/pulp-platform_common_cells_pr151.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/pulp-platform_common_cells_pr151", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/pulp-platform_common_cells_pr151"}
{"instance_id": "pulp-platform_common_cells_pr155", "issue_text": "# Update `fall_through_register`'s fifo to `fifo_v3`\n\nInstance: pulp-platform_common_cells_pr155\nSource: https://github.com/pulp-platform/common_cells/pull/155\nFetched: 2026-05-03\nRepository: pulp-platform/common_cells\nPull request: #155\nAuthor: michael-platzer\nState: closed\nBase branch: master\nHead branch: fix_fall_through_fifo\nCreated: 2022-09-16\nUpdated: 2022-09-16\nClosed: 2022-09-16\nMerged: 2022-09-16\n\n## PR Title\nUpdate `fall_through_register`'s fifo to `fifo_v3`\n\n## PR Description\nThe `fall_through_register` still uses the deprecated `fifo_v2`. This PR updates it to `fifo_v3`. Fixes #84.\n\n## PR Comments\n\n**niwis** (Sep 16, 2022):\nRequested changes: \"Could you add the `usage_o` port of `fifo_v3` in this instantiation so that the port list is complete?\"\n\n**michael-platzer** (Sep 16, 2022):\n\"Sure, added it.\"\n\n**niwis** (Sep 16, 2022):\nApproved: \"Thanks! LGTM\"\n\n## Linked Issues\n\n**Issue #84: fall_through_register uses deprecated fifo_v2**\nShould probably be updated to `fifo_v3`.\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/pulp-platform_common_cells_pr155", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/pulp-platform_common_cells_pr155.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/pulp-platform_common_cells_pr155", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/pulp-platform_common_cells_pr155"}
{"instance_id": "pulp-platform_common_cells_pr170", "issue_text": "# Add shift_register_gated\n\nInstance: pulp-platform_common_cells_pr170\nSource: https://github.com/pulp-platform/common_cells/pull/170\nFetched: 2026-05-03\nRepository: pulp-platform/common_cells\nPull request: #170\nAuthor: qian-gu\nState: closed\nBase branch: master\nHead branch: master\nCreated: 2023-02-22\nUpdated: 2023-04-14\nClosed: 2023-04-14\nMerged: 2023-04-14\n\n## PR Title\nAdd shift_register_gated\n\n## PR Description\nA shift register with clock gating.\n\n## PR Comments\n\n**niwis** (Feb 23, 2023):\nRequested updates to avoid code fragmentation: adapt existing shift_reg module to instantiate the new module, tie valid_i to 1'b1, and update configuration files (Bender.yml, README.md, src_files.yml). Also requested rebase to master due to CI updates.\n\n**niwis** (Feb 23, 2023):\nFlagged unnecessary `default_nettype none` directive at module start; suggested removal for consistency.\n\n**niwis** (Feb 23, 2023):\nFlagged unnecessary `default_nettype wire` at module end.\n\n**niwis** (Feb 23, 2023):\nRequested coding convention alignment for variable declarations: consolidate related declarations.\n\n**qian-gu** (Feb 23, 2023):\nExplained the directive ensures explicit variable declarations; committed to removing it.\n\n**qian-gu** (Feb 27, 2023):\nReported CI authentication error attempting gitlab mirror push with HTTP credentials issue.\n\n**niwis** (Apr 14, 2023):\nApproved changes, acknowledged CI failures due to missing github secrets, noted working on solution.\n\n## Linked Issues\n\n**Issue #169: A gated shift register module**\nI have developed a new version of shift_reg which has a valid flag for data to enable DC insert ICG for the internal datapath, the new version shift_reg is backward compatible with the older one and has a better power comuption. Is it welcomed to add it to this library?\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/pulp-platform_common_cells_pr170", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/pulp-platform_common_cells_pr170.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/pulp-platform_common_cells_pr170", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/pulp-platform_common_cells_pr170"}
{"instance_id": "pulp-platform_common_cells_pr182", "issue_text": "# Clock divider configuration fails if divider value is 0\n\n@meggiman I ran into another issue with the clock divider.\n\nFollowing the description\n> // It is thus safe to statically tie the valid signal to logic high if\n> // we can guarantee, that the div_i value remains stable long enough (upper\n> // limit 2 output clock cycles).\n\nI tied `valid_i` to 1 and connected `div_i` to a register which has a reset value 0.\n\nThat's when I noticed that after `div_q = 0` is loaded, I'm not able to reconfigure the clock divider.\n\nAs far as I understood, it hangs in the `WAIT_END_PERIOD` state, because the following condition can never be satisfied.\nhttps://github.com/pulp-platform/common_cells/blob/f9528fa6e4d3080605c01074bdaf62dcb4aff7d2/src/clk_int_div.sv#L187\n\nPR Title: Fix deadlock on div_i == 0 and avoid hold issues on ungated_output_clock\n\nPR #182 (Merged May 11, 2023)\n\nDescription:\nThe PR addresses two issues in the clock divider component:\n\n1. Deadlock Prevention: Instead of directly storing div_i in the internal register div_q, the code now normalizes the value to be strictly greater than 0, preventing deadlock when preloading with zero.\n\n2. Hold Issues Resolution: The PR removes combinational checks on the ungated_output_clock phase to avoid synthesis hold violations. A dedicated flip-flop now tracks the output clock gate status instead of relying on combinational logic.\n\nThis change resolves GitHub issue #172.\n\nComments:\n\n@fimtrey (May 10, 2023):\n\"I tested in on a pynq-z2 FPGA and it works for my case and there're no hold issues anymore. Thank you @meggiman!\"\n\n@niwis (May 11, 2023):\nApproved with comment: \"Thanks! LGTM\"\n\nLinked Issue:\n#172: Clock divider configuration fails if divider value is 0\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/pulp-platform_common_cells_pr182", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/pulp-platform_common_cells_pr182.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/pulp-platform_common_cells_pr182", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/pulp-platform_common_cells_pr182"}
{"instance_id": "pulp-platform_common_cells_pr188", "issue_text": "# popcount for INPUT_WIDTH=1\n\n`popcount.sv` contradicts itself in the description and this commit https://github.com/pulp-platform/common_cells/commit/bf4db7cfa01030f36a59c1a4d21ee233f6aee01e whether the case `INPUT_WIDTH=1` is supported.\n\nFurthermore, it seems like the https://github.com/pulp-platform/common_cells/commit/bf4db7cfa01030f36a59c1a4d21ee233f6aee01e doesn't properly add full support for `INPUT_WIDTH=1` since\n\n```verilog\nlogic [PopcountWidth-2:0]         left_child_result, right_child_result;\n```\n\n(from here https://github.com/pulp-platform/common_cells/blob/master/src/popcount.sv#L30)\n\nbecomes negative causing at least VCS to crash. A simple hacky fix is to change the `-2`  to `-1` but I'm not sure if that works out well.\n\nMaybe @meggiman can you comment on this (since you seem to know the most being the designer of this module) ?\n\nPR Title: Simplify popcount and add proper support for all input widths\n\nPR #188 (Merged May 30, 2023)\n\nDescription:\nThe original popcount implementation relied on a recursive binary adder tree using nested modules. Testing with modern synthesis tools revealed that describing the popcount logic as a flat for loop achieved equal or superior results with faster compilation times. This refactor also resolves issue #187.\n\nComments:\n\n@meggiman (May 24, 2023):\n\"The popcount implementation so far used a recursive implementation using a binary adder tree. However, experiments using reasonably modern synthesis tools show that the logic optimization heuristics achieve the same or better results in less compilation time when the popcount logic is described in a flat for loop instead of nested modules.\"\n\n@bluewww (May 24, 2023):\n\"LGTM!\"\n\n@niwis (May 29, 2023):\n\"Thanks a lot! Just one typo from my side\" [Requested changes, later approved after corrections]\n\nLinked Issue:\n#187: popcount for INPUT_WIDTH=1\n\nParticipants:\n- @meggiman (author)\n- @niwis (reviewer/merger)\n- @bluewww (reviewer)\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/pulp-platform_common_cells_pr188", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/pulp-platform_common_cells_pr188.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/pulp-platform_common_cells_pr188", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/pulp-platform_common_cells_pr188"}
{"instance_id": "pulp-platform_common_cells_pr222", "issue_text": "# `stream_arbiter` with priority arbitration inherently violates assertion\n\nWhen configuring a `stream_arbiter` or `stream_arbiter_flushable` with `ARBITER = \"prio\"`, it instantiates an `rr_arb_tree` with both the `ExtPrio` and `LockIn` parameters set:\n\nhttps://github.com/pulp-platform/common_cells/blob/0d67563b6b592549542544f1abc0f43e5d4ee8b4/src/stream_arbiter_flushable.sv#L55-L61\n\nHowever, this directly violates an assertion in `rr_arb_tree`:\n\nhttps://github.com/pulp-platform/common_cells/blob/0d67563b6b592549542544f1abc0f43e5d4ee8b4/src/rr_arb_tree.sv#L319\n\nAs a result, any priority stream arbiters instantiated inherently cause a fatal assertion violation.\n\nPR Title: stream_arbiter_flushable: Do not lock prio arbiter\n\nPR #222 (Merged)\n\nDescription:\nThe PR addresses a technical issue with the priority arbiter implementation. According to the submitter, setting `LockIn` while `ExtPrio = 1'b1` violates the constraints of the `rr_arb_tree` and produces no effect. Additionally, locking a decision that may have lower priority contradicts the purpose of using a priority arbiter. The fix clears the `LockIn` parameter for the priority arbiter component.\n\nComments:\n\n@niwis (May 15, 2024):\n\"Setting `LockIn` while `ExtPrio = 1'b1` is disallowed by the `rr_arb_tree` and has no effect.\"\n\n@micprog (Jun 17, 2024):\n\"LGTM\"\n\nLinked Issue:\n#221: stream_arbiter with priority arbitration inherently violates assertion\n\nReviewers:\n- paulsc96 (approved May 15, 2024)\n- micprog (approved Jun 17, 2024)\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/pulp-platform_common_cells_pr222", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/pulp-platform_common_cells_pr222.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/pulp-platform_common_cells_pr222", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/pulp-platform_common_cells_pr222"}
{"instance_id": "pulp-platform_common_cells_pr224", "issue_text": "# `mem_to_banks_detailed`: Ensure no spurious response after full dead write\n\nInstance: pulp-platform_common_cells_pr224\nSource: https://github.com/pulp-platform/common_cells/pull/224\nFetched: 2026-04-26\nRepository: pulp-platform/common_cells\nPull request: #224\nAuthor: micprog\nState: closed\nBase branch: master\nHead branch: michaero/fix_memtobanks_deadwrite\nCreated: 2024-07-11T09:56:08Z\nUpdated: 2024-07-18T12:13:28Z\nClosed: 2024-07-18T12:13:26Z\nMerged: 2024-07-18T12:13:26Z\n\nPR Title: `mem_to_banks_detailed`: Ensure no spurious response after full dead write\n\nPR #224 (Merged)\n\nDescription:\nNo description was provided by the author.\n\nComments:\n\n@niwis (Collaborator) - July 18, 2024:\nReviewer raised three points: (1) Masking `dead_response` with `~dead_write_fifo_empty` makes sense; (2) questioned necessity of reduction changes at specific lines; (3) questioned why `dead_read_fifo` input changed from `bank_oup` to `bank_req`.\n\n@niwis (Collaborator) - July 18, 2024:\nClarified that the input data alignment change was necessary per in-person discussion, while the reductions could be removed.\n\nCommits (titles only):\n1. \"Ensure no spurious response after full dead write\"\n2. \"Fix HideStrb alignment\"\n3. \"Fix lint\"\n4. \"Remove unneeded strb reduction\"\n\nParticipants:\n- @micprog (author)\n- @niwis (reviewer/approver)\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/pulp-platform_common_cells_pr224", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/pulp-platform_common_cells_pr224.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/pulp-platform_common_cells_pr224", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/pulp-platform_common_cells_pr224"}
{"instance_id": "pulp-platform_common_cells_pr225", "issue_text": "# Add credit_counter\n\nInstance: pulp-platform_common_cells_pr225\nSource: https://github.com/pulp-platform/common_cells/pull/225\nFetched: 2026-04-26\nRepository: pulp-platform/common_cells\nPull request: #225\nAuthor: micprog\nState: closed\nBase branch: master\nHead branch: michaero/credit_counter\nCreated: 2024-07-17T15:32:28Z\nUpdated: 2024-07-18T12:03:48Z\nClosed: 2024-07-18T12:03:46Z\nMerged: 2024-07-18T12:03:46Z\n\nPR Title: Add credit_counter\n\nPR #225 (Merged Jul 18, 2024 by niwis into master branch)\n\nDescription:\nNo description was provided by the author.\n\nComments:\n\nmicprog (Jul 17, 2024) - posted no description.\n\nniwis (Jul 18, 2024):\n\"Can we use `FFARNC` instead of tying the load enable?\" — code review suggestion to replace `FFLARNC` with `FFARNC` to avoid manually tying the load enable signal.\n\nniwis (Jul 18, 2024):\nApproved changes after the suggestion was implemented.\n\npaulsc96 (Jul 17, 2024):\nApproved the initial submission.\n\nThe branch michaero/credit_counter was deleted after merge.\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/pulp-platform_common_cells_pr225", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/pulp-platform_common_cells_pr225.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/pulp-platform_common_cells_pr225", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/pulp-platform_common_cells_pr225"}
{"instance_id": "pulp-platform_common_cells_pr228", "issue_text": "# [delta_counter] Attach reset properly to overflow FF\n\nInstance: pulp-platform_common_cells_pr228\nSource: https://github.com/pulp-platform/common_cells/pull/228\nFetched: 2026-04-26\nRepository: pulp-platform/common_cells\nPull request: #228\nAuthor: FrancescoConti\nState: closed\nBase branch: master\nHead branch: master\nCreated: 2024-08-28T17:03:58Z\nUpdated: 2024-08-29T09:34:12Z\nClosed: 2024-08-29T09:34:12Z\nMerged: 2024-08-29T09:34:12Z\n\nPR Title: [delta_counter] Attach reset properly to overflow FF\n\nPR #228 (Merged August 29, 2024)\n\nDescription:\nFrancesco Conti explained that the previous implementation used a non-idiomatic approach with a ternary operator for the asynchronous reset. According to the PR author, \"some synthesis tools do not properly interpret this as a reset, resulting in gates being inserted on the reset network, which is undesirable.\"\n\nCommits (titles only):\n1. \"[delta_counter] Attach reset properly to overflow FF\" — addressed the synthesis tool interpretation issue with the reset mechanism.\n2. \"Update delta_counter.sv\" — adjustments to satisfy linting requirements.\n\nComments:\n\nniwis (reviewer/approver):\n\"Thanks a lot! LGTM\"\n\nParticipants:\n- Author: FrancescoConti\n- Reviewer/Merger: niwis\n\nNo linked issues were explicitly mentioned.\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/pulp-platform_common_cells_pr228", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/pulp-platform_common_cells_pr228.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/pulp-platform_common_cells_pr228", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/pulp-platform_common_cells_pr228"}
{"instance_id": "pulp-platform_common_cells_pr230", "issue_text": "# Make the number of compare ports in id_queue parametric\n\nInstance: pulp-platform_common_cells_pr230\nSource: https://github.com/pulp-platform/common_cells/pull/230\nFetched: 2026-04-26\nRepository: pulp-platform/common_cells\nPull request: #230\nAuthor: ricted98\nState: closed\nBase branch: master\nHead branch: rt/idqueue\nCreated: 2024-09-09T15:19:08Z\nUpdated: 2024-09-16T10:53:16Z\nClosed: 2024-09-16T10:53:15Z\nMerged: 2024-09-16T10:53:15Z\n\nPR Title: Make the number of compare ports in id_queue parametric\n\nPR #230 (Merged September 16, 2024)\n\nDescription:\n\"Add a parameter in ID QUEUE to generate multiple lookup ports.\"\n\nReview Activity:\n- niwis approved on September 9, 2024\n- paulsc96 approved on September 10, 2024\n\nMerge Details:\n- Merged by niwis on September 16, 2024\n- Branch deleted after merge (rt/idqueue)\n\nParticipants: ricted98 (author/assignee), niwis, paulsc96\n\nNotes:\nThe pull request introduces parametric control over the number of comparison ports in the ID queue module, enabling flexible port generation based on configuration requirements rather than fixed implementation.\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/pulp-platform_common_cells_pr230", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/pulp-platform_common_cells_pr230.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/pulp-platform_common_cells_pr230", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/pulp-platform_common_cells_pr230"}
{"instance_id": "pulp-platform_common_cells_pr236", "issue_text": "# stream_join_dynamic: Assert inp readies only for selected streams\n\nInstance: pulp-platform_common_cells_pr236\nSource: https://github.com/pulp-platform/common_cells/pull/236\nFetched: 2026-04-26\nRepository: pulp-platform/common_cells\nPull request: #236\nAuthor: ricted98\nState: closed\nBase branch: master\nHead branch: rt/stream-ips\nCreated: 2024-09-30T13:39:00Z\nUpdated: 2024-10-04T01:10:43Z\nClosed: 2024-10-04T01:10:41Z\nMerged: 2024-10-04T01:10:41Z\n\nPR Title: stream_join_dynamic: Assert inp readies only for selected streams\n\nPR #236 (Merged October 4, 2024)\n\nDescription:\nThe PR addresses a bug where successful handshakes on output ports would assert `ready=1` on all input ports regardless of the `sel_i` selection parameter. This caused unwanted handshakes on unselected input channels that had `valid=1`. The proposed fix ensures only selected input channels receive the ready signal.\n\nComments:\n\n@colluca (Approval, Sep 30, 2024):\n\"LGTM, thanks @ricted98 :)\"\n\n@niwis (Approval & Merge, Oct 4, 2024):\n\"Thanks @ricted98!\"\n\nParticipants:\n- @ricted98 (Author)\n- @niwis (Reviewer, Merged)\n- @colluca (Reviewer)\n\nRelated Issues:\nThe PR may close issue #213: \"'steam_join_dynamic' handshakes unselected streams\"\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/pulp-platform_common_cells_pr236", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/pulp-platform_common_cells_pr236.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/pulp-platform_common_cells_pr236", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/pulp-platform_common_cells_pr236"}
{"instance_id": "pulp-platform_common_cells_pr240", "issue_text": "# assertions: Keep helper macros defined\n\nInstance: pulp-platform_common_cells_pr240\nSource: https://github.com/pulp-platform/common_cells/pull/240\nFetched: 2026-04-26\nRepository: pulp-platform/common_cells\nPull request: #240\nAuthor: michael-platzer\nState: closed\nBase branch: master\nHead branch: michael-platzer/fix/inc-assert-undef\nCreated: 2024-10-08T12:10:56Z\nUpdated: 2024-10-09T01:36:57Z\nClosed: 2024-10-09T01:36:57Z\nMerged: 2024-10-09T01:36:57Z\n\nAnother day, another fix for PR #233. This time I realized that undefining a helper macro that is still needed later on is not a smart idea — turns out that due to this the assertion macros were not enabled so far.\r\n\r\nAlso, a comment in lowRISC's implementation made me realize that the helper macro can be useful outside of the header:\r\n\r\nhttps://github.com/lowRISC/opentitan/blob/28af81ab6e41d9ee6b270f28c7e62761d6c62c31/hw/ip/prim/rtl/prim_assert.sv#L59-L60\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/pulp-platform_common_cells_pr240", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/pulp-platform_common_cells_pr240.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/pulp-platform_common_cells_pr240", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/pulp-platform_common_cells_pr240"}
{"instance_id": "pulp-platform_common_cells_pr242", "issue_text": "# Fix inverted reset in delta_counter\n\nInstance: pulp-platform_common_cells_pr242\nSource: https://github.com/pulp-platform/common_cells/pull/242\nFetched: 2026-04-26\nRepository: pulp-platform/common_cells\nPull request: #242\nAuthor: olofk\nState: closed\nBase branch: master\nHead branch: delta_counter_reset\nCreated: 2024-10-09T08:21:14Z\nUpdated: 2024-10-09T10:15:54Z\nClosed: 2024-10-09T10:15:53Z\nMerged: 2024-10-09T10:15:53Z\n\nPR Title: Fix inverted reset in delta_counter\n\nPR #242 (Merged Oct 9, 2024 by niwis)\n\nDescription:\nThe PR addresses a bug in the delta_counter component. According to olofk's explanation: \"A recent fix to the reset logic in delta_counter [10dac0f] looks like it accidentally inverted the reset logic.\"\n\nComments:\n\nniwis (Collaborator):\nRequested the author use the logical negation operator instead (suggesting `!rst_ni` syntax).\n\nolofk (Author):\nResponded \"Better now?\" after implementing the requested change.\n\nFrancescoConti (Member):\nApproved with \"LGTM\".\n\nniwis (Collaborator):\nFinal approval stating \"Yep, thanks a lot!\" before merging.\n\nResolution:\nThe pull request was successfully merged with approvals from both FrancescoConti and niwis. The fix corrected the inverted reset logic using the logical negation operator as requested during review.\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/pulp-platform_common_cells_pr242", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/pulp-platform_common_cells_pr242.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/pulp-platform_common_cells_pr242", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/pulp-platform_common_cells_pr242"}
{"instance_id": "pulp-platform_common_cells_pr247", "issue_text": "# isochronous_spill_register: Replace non-resettable FF\n\nInstance: pulp-platform_common_cells_pr247\nSource: https://github.com/pulp-platform/common_cells/pull/247\nFetched: 2026-04-26\nRepository: pulp-platform/common_cells\nPull request: #247\nAuthor: colluca\nState: closed\nBase branch: master\nHead branch: remove-ffnr\nCreated: 2024-11-05T15:06:25Z\nUpdated: 2025-09-18T16:20:36Z\nClosed: 2025-09-18T16:20:35Z\nMerged: 2025-09-18T16:20:35Z\n\nFollowing https://github.com/pulp-platform/snitch_cluster/pull/154, there are still some non-resettable FFs in the Snitch cluster, that can be traced back to the `isochronous_spill_register` IP.\r\n\r\nThis PR is a placeholder for addressing this issue. The current solution has to be revised to ensure safety against metastability conditions.\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/pulp-platform_common_cells_pr247", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/pulp-platform_common_cells_pr247.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/pulp-platform_common_cells_pr247", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/pulp-platform_common_cells_pr247"}
{"instance_id": "pulp-platform_common_cells_pr257", "issue_text": "# Add mask, `ring_buffer` and `trip_counter` IPs\n\nInstance: pulp-platform_common_cells_pr257\nSource: https://github.com/pulp-platform/common_cells/pull/257\nFetched: 2026-04-26\nRepository: pulp-platform/common_cells\nPull request: #257\nAuthor: colluca\nState: closed\nBase branch: master\nHead branch: sequencer-ips\nCreated: 2025-06-04T16:36:11Z\nUpdated: 2025-09-17T13:11:12Z\nClosed: 2025-09-17T13:11:11Z\nMerged: 2025-09-17T13:11:10Z\n\nThis PR implements the following contributions:\r\n- Add an assertion to verify the stability of ready-valid interfaces.\r\n- Add a `ring_buffer` IP. Uses a sequential write interface and a random-access read interface. Other variants could be implemented as well.\r\n- Add a `trip_counter` IP. Resets automatically when it reaches a specified bound, useful e.g. for implementing hardware loop logic.\r\n- Correct a bug in the documentation of the `lzc` IP.\r\n- Add mask generation IPs (`heaviside` and `boxcar`), to encapsulate and abstract the bitwise expression logic to generate the masks. Also good for correctness and self-documentation.\r\n\r\nNote: this is currently based on https://github.com/pulp-platform/common_cells/pull/247.\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/pulp-platform_common_cells_pr257", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/pulp-platform_common_cells_pr257.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/pulp-platform_common_cells_pr257", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/pulp-platform_common_cells_pr257"}
{"instance_id": "pulp-platform_common_cells_pr262", "issue_text": "# Fix SpyGlass CDC Lint issues in CDC FIFOs\n\nInstance: pulp-platform_common_cells_pr262\nSource: https://github.com/pulp-platform/common_cells/pull/262\nFetched: 2026-04-26\nRepository: pulp-platform/common_cells\nPull request: #262\nAuthor: Scheremo\nState: closed\nBase branch: master\nHead branch: pr/cdclintfix\nCreated: 2025-07-18T09:10:45Z\nUpdated: 2025-08-18T11:01:38Z\nClosed: 2025-08-18T11:01:38Z\nMerged: 2025-08-18T11:01:38Z\n\nThis PR fixes CDC linting issues of type `Ac_cdc01` in the modules `cdc_fifo_gray` and `cdc_fifo_gray_clearable`.\r\nCurrently, the tool flags \"ClkCross Data Hold\" violations of some (but not all) paths originating from single bits of `wptr_q`.\r\n\r\nThe issue arise from the formulation of pushing new data to the FIFO. Currently, the FIFO push is enabled by the expression \r\n`src_valid_i & src_ready_o & (wptr_bin[LOG_DEPTH-1:0] == i)`, which in SpyGlass CDC is viewed as the qualifier of the crossing. Unfortunately this leads SpyGlass CDC to evaluate individual bits of `wptr_q` as being qualifiers for multiple clock domain crossings, which leads to the pointer not being properly recognized as a CDC FIFO write pointer. In turn, the tool will complain that (some) of those `wptr_q` bits violate fast-to-slow clock domain data hold checks, since they are allowed to change multiple times within a target domain clock cycle.\r\n\r\nReformulating (practically) the same functionality by removing `wptr` from the enable condition fixes this, enabling this code to pass strict_qual for SpyGlass CDC linting.\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/pulp-platform_common_cells_pr262", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/pulp-platform_common_cells_pr262.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/pulp-platform_common_cells_pr262", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/pulp-platform_common_cells_pr262"}
{"instance_id": "pulp-platform_common_cells_pr280", "issue_text": "# stream_mux: Fix select width when N_INP=1\n\nInstance: pulp-platform_common_cells_pr280\nSource: https://github.com/pulp-platform/common_cells/pull/280\nFetched: 2026-04-26\nRepository: pulp-platform/common_cells\nPull request: #280\nAuthor: colluca\nState: closed\nBase branch: master\nHead branch: fix-one-input-stream-mux\nCreated: 2026-03-10T19:34:30Z\nUpdated: 2026-03-23T13:47:14Z\nClosed: 2026-03-23T13:47:13Z\nMerged: 2026-03-23T13:47:12Z\n\nPR Title: stream_mux: Fix select width when N_INP=1\n\nPR #280 (Merged)\n\nDescription:\nThe pull request addresses a bug in the stream_mux component. When the parameter `N_INP` is set to 1, the calculation of `LOG_N_INP` results in zero, which causes a negative index to be applied to the `inp_sel_i` port. This fix resolves that indexing issue.\n\nAuthor: colluca\nReviewer/Merger: phsauter\n\nComments:\n\ncolluca:\n\"When `N_INP=1`, `LOG_N_INP` would be zero, resulting in a negative index in the `inp_sel_i` port.\"\n\nMerge Details:\nThe PR was merged into the master branch on March 23, 2026, via merge queue. All 5 checks passed.\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/pulp-platform_common_cells_pr280", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/pulp-platform_common_cells_pr280.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/pulp-platform_common_cells_pr280", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/pulp-platform_common_cells_pr280"}
{"instance_id": "pulp-platform_common_cells_pr93", "issue_text": "# stream_register: Error in Synopsys Synplify\n\nHi all,\r\n\r\nI'm facing a problem using the stream_register required for using Pulp AXI. This module is included in the axi_atop_filter. Unfortunately I get the following error message during compilation with Synopsys Synplify :\r\n\r\n**@E: CD671: /.../commom_cells/src/stream_register.sv: 36:31:36:31| Expecting array type.**\r\n\r\nIf I change the code from\r\n\r\n```\r\n    fifo_v2 #(\r\n        .FALL_THROUGH   (1'b0),\r\n        .DATA_WIDTH     ($size(T)),                     // <= change done here: $size() replaced with $bits()\r\n        .DEPTH          (1),\r\n        .dtype          (T)\r\n    ) i_fifo (\r\n        .clk_i          (clk_i),\r\n        .rst_ni         (rst_ni),\r\n        .flush_i        (clr_i),\r\n        .testmode_i     (testmode_i),\r\n        .full_o         (fifo_full),\r\n        .empty_o        (fifo_empty),\r\n        .alm_full_o     ( ),\r\n        .alm_empty_o    ( ),\r\n        .data_i         (data_i),\r\n        .push_i         (valid_i & ~fifo_full),\r\n        .data_o         (data_o),\r\n        .pop_i          (ready_i & ~fifo_empty)\r\n    );\r\n```\r\n\r\nto\r\n\r\n```\r\n    fifo_v2 #(\r\n        .FALL_THROUGH   (1'b0),\r\n        .DATA_WIDTH     ($bits(T)),                    // <= this is working\r\n        .DEPTH          (1),\r\n        .dtype          (T)\r\n    ) i_fifo (\r\n        .clk_i          (clk_i),\r\n        .rst_ni         (rst_ni),\r\n        .flush_i        (clr_i),\r\n        .testmode_i     (testmode_i),\r\n        .full_o         (fifo_full),\r\n        .empty_o        (fifo_empty),\r\n        .alm_full_o     ( ),\r\n        .alm_empty_o    ( ),\r\n        .data_i         (data_i),\r\n        .push_i         (valid_i & ~fifo_full),\r\n        .data_o         (data_o),\r\n        .pop_i          (ready_i & ~fifo_empty)\r\n    );\r\n```\r\n\r\nbut I think then the module does not have the intended behaviour any more. Does anybody know what the exact error is because I don't get the problem.\r\n\r\n**I simulate the whole design with MentorGraphics Questa and there it works without any problem. So it seems to be a problem with the Synthesis tool.**\r\n\r\nKind regards and thank you very much for helping!\r\nSebastian\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/pulp-platform_common_cells_pr93", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/pulp-platform_common_cells_pr93.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/pulp-platform_common_cells_pr93", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/pulp-platform_common_cells_pr93"}
{"instance_id": "pulp-platform_common_verification_pr10", "issue_text": "# $urandom_range() instead of std::randomize() with {} to simplify & make compatible with verilator\n\nInstance: pulp-platform_common_verification_pr10\nSource: https://github.com/pulp-platform/common_verification/pull/10\nFetched: 2026-04-26\nRepository: pulp-platform/common_verification\nPull request: #10\nAuthor: solomatnikov\nState: closed\nBase branch: master\nHead branch: simplify_n_verilator\nCreated: 2025-09-01T00:27:13Z\nUpdated: 2026-01-05T16:56:28Z\nClosed: 2026-01-05T16:56:27Z\nMerged: 2026-01-05T16:56:27Z\n\nSimplify by using `$urandom_range()` instead of `std::randomize() with {}`, which also makes it compilable with verilator.\r\n\r\nhttps://github.com/verilator/verilator/issues/4706\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/pulp-platform_common_verification_pr10", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/pulp-platform_common_verification_pr10.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/pulp-platform_common_verification_pr10", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/pulp-platform_common_verification_pr10"}
{"instance_id": "pulp-platform_common_verification_pr5", "issue_text": "# Add signal highlighter\n\nInstance: pulp-platform_common_verification_pr5\nSource: https://github.com/pulp-platform/common_verification/pull/5\nFetched: 2026-04-26\nRepository: pulp-platform/common_verification\nPull request: #5\nAuthor: micprog\nState: closed\nBase branch: master\nHead branch: highlighter\nCreated: 2022-08-03T14:52:52Z\nUpdated: 2022-08-29T17:38:50Z\nClosed: 2022-08-04T11:41:08Z\nMerged: 2022-08-04T11:41:08Z\n\nPR Title: Add signal highlighter\n\nPR #5 (Merged Aug 4, 2022)\n\nDescription:\nThe signal highlighter highlights a signal in the waveform for easier viewing.\n\nComments:\n\nmicprog (Aug 3, 2022):\n\"The signal highlighter highlights a signal in the waveform for easier viewing\"\n\nandreaskurth (Aug 4, 2022):\n\"LGTM, thanks!\"\n\nKey Details:\n- Author: micprog\n- Merged by: andreaskurth on Aug 4, 2022\n- Branch deleted: Aug 29, 2022 by thommythomaso\n- Reviewers: andreaskurth (approved), thommythomaso (awaiting review)\n\nNo linked issues were referenced.\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/pulp-platform_common_verification_pr5", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/pulp-platform_common_verification_pr5.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/pulp-platform_common_verification_pr5", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/pulp-platform_common_verification_pr5"}
{"instance_id": "pulp-platform_common_verification_pr6", "issue_text": "# Add stream_watchdog\n\nInstance: pulp-platform_common_verification_pr6\nSource: https://github.com/pulp-platform/common_verification/pull/6\nFetched: 2026-04-26\nRepository: pulp-platform/common_verification\nPull request: #6\nAuthor: micprog\nState: closed\nBase branch: master\nHead branch: watchdog\nCreated: 2022-08-03T14:53:37Z\nUpdated: 2022-08-29T17:53:35Z\nClosed: 2022-08-29T17:53:32Z\nMerged: 2022-08-29T17:53:32Z\n\nPR Title: Add stream_watchdog\n\nPR #6 (Merged August 29, 2022)\n\nDescription:\nThe stream_watchdog feature terminates a simulation when a ready-valid handshake becomes inactive or deadlocked for a specified number of cycles.\n\nParticipants:\n- micprog (author)\n- andreaskurth (reviewer)\n- thommythomaso (reviewer/merger)\n\nComments:\n\nthommythomaso:\nApproved with \"LGTM\"\n\nandreaskurth:\nProvided review feedback on `src/stream_watchdog.sv`, with comments marked as resolved.\n\nChanges Summary (commit titles only):\n- Initial commit adding stream_watchdog functionality\n- Style fixes and addition of `rst_ni` signal\n- Documentation updates to README and CHANGELOG\n\nNo linked issues were referenced.\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/pulp-platform_common_verification_pr6", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/pulp-platform_common_verification_pr6.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/pulp-platform_common_verification_pr6", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/pulp-platform_common_verification_pr6"}
{"instance_id": "pulp-platform_fpu_div_sqrt_mvp_pr16", "issue_text": "# Bug report: inexact flag not set in case of overflow or underflow.\n\n- Source URL: https://github.com/pulp-platform/fpu_div_sqrt_mvp/issues/15\n\nHello!\r\n\r\nFor some inputs, the underflow (UF) flag is set but not the inexact (NX) flag.\r\n\r\nHere is an example that triggers this bug:\r\n```\r\nRounding: RTZ\r\ninstr: fdiv.d f15, f10, f09\r\nOperand (f09): 0xc268a20e00000000 ('-8.46384e+11')\r\nOperand (f10): 0x000000000828d569 ('6.76345e-316')\r\nExpected (f15): 0x8000000000000000 ('-0')\r\nFloating ouptuts match.\r\nFflags:\r\n  Expected:    11 UF, NX\r\n  Received:    10 UF\r\n```\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/pulp-platform_fpu_div_sqrt_mvp_pr16", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/pulp-platform_fpu_div_sqrt_mvp_pr16.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/pulp-platform_fpu_div_sqrt_mvp_pr16", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/pulp-platform_fpu_div_sqrt_mvp_pr16"}
{"instance_id": "pulp-platform_fpu_div_sqrt_mvp_pr18", "issue_text": "# Bug report: division of zero by zero incorrectly sets the DZ flag\n\n- Source URL: https://github.com/pulp-platform/fpu_div_sqrt_mvp/issues/17\n\nHello!\n\nThe IEEE-754-2019 standard specifies that div(0,0) is an invalid instruction and therefore should not raise the divide by zero (DZ) flag.\n\nYou can test it for example with the pseude-assembly:\n```\nft0 = 0x0000000000000000\nft1 = 0x0000000000000000\nfdiv.d ft2, ft1, ft0\n```\n\nPR Title: Bugfix: unset DZ flag when dividing 0 by 0.\n\nPR #18 (Merged October 26, 2023)\n\nDescription:\nThe pull request addresses issue #17, which reported incorrect behavior when dividing zero by zero. The fix ensures the DZ (divide by zero) flag is properly unset in this edge case scenario.\n\nActivity:\nflaviens submitted the fix on February 16, 2023, noting: \"This fixes #17. I remain at your disposal.\"\n\nThe branch underwent two force pushes before being merged by lucabertaccini.\n\nLinked Issue:\n\"Bug report: division of zero by zero incorrectly sets the DZ flag\" (issue #17)\n\nThe implementation corrects floating-point division logic in this specialized FPU divide/square root module used in the PULP platform architecture.\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/pulp-platform_fpu_div_sqrt_mvp_pr18", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/pulp-platform_fpu_div_sqrt_mvp_pr18.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/pulp-platform_fpu_div_sqrt_mvp_pr18", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/pulp-platform_fpu_div_sqrt_mvp_pr18"}
{"instance_id": "pulp-platform_gpio_pr2", "issue_text": "# Comments mismatch with the website instructions and the GPIO_MODE regs might wrong\n\n- Source URL: https://github.com/pulp-platform/gpio/issues/1\n\n1)\r\nThe comments in the code mismatch with the description on the website\r\n```sv     \r\nalways_comb begin\r\n          `assert_condition(s_reg2hw.gpio_mode[gpio_idx], rst_ni);\r\n        case (s_reg2hw.gpio_mode[gpio_idx])\r\n          2'b00: begin //INPUT_ONLY\r\n            gpio_tx_en_o[gpio_idx] = 1'b0;\r\n          end\r\n          2'b01: begin //OUTPUT_ACTIVE\r\n            gpio_tx_en_o[gpio_idx] = 1'b1;\r\n          end\r\n          2'b10: begin // OPEN_DRAIN0 \r\n            gpio_tx_en_o[gpio_idx] = s_reg2hw.gpio_out[gpio_idx].q;\r\n          end\r\n          2'b11: begin // OPEN_DRAIN1\r\n            gpio_tx_en_o[gpio_idx] = s_reg2hw.gpio_out[gpio_idx].q;\r\n          end\r\n          default: begin\r\n            gpio_tx_en_o[gpio_idx] = 1'b0;\r\n          end\r\n        endcase\r\n      end\r\n```\r\n\r\nHere, on the website, 2'b10 points to OPEN_DRAIN1 and 2'b11 points to OPEN_DRAIN0.\r\n\r\n2)\r\nI think when the reg_mode is OPEN_DRIVEN0, the code should be\r\n```sv\r\n            gpio_tx_en_o[gpio_idx] = ~s_reg2hw.gpio_out[gpio_idx].q;\r\n```\r\notherwise, the s_reg2hw.gpio_out can not output 0.\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/pulp-platform_gpio_pr2", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/pulp-platform_gpio_pr2.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/pulp-platform_gpio_pr2", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/pulp-platform_gpio_pr2"}
{"instance_id": "pulp-platform_hci_pr27", "issue_text": "# Syntax error in `hci_helpers.svh` in Vivado\n\n- Source URL: https://github.com/pulp-platform/hci/issues/26\n\nThe helper macros in `hci_helpers.svh` https://github.com/pulp-platform/hci/blob/82dfd3ffe0c4d9ef77c9a6d4efbbb0411aa2662e/rtl/common/hci_helpers.svh#L19-L38 distinguish between synthesis and simulation tools with a `ifdef SYNTHESIS` due to different supported features of SystemVerilog. Apparently, Vivado likes the same syntax of simulation tools, which is not the one currently selected.\n\nPR Title: Manage the special case of FPGA targets in hci_helpers.svh\n\nPR #27 (Merged April 24, 2024)\n\nAuthor: FrancescoConti\n\nDescription:\nNo description was provided by the author.\n\nLinked Issue:\n- Title: \"Syntax error in `hci_helpers.svh` in Vivado\"\n- Issue #26\n\nKey Activity:\n- The branch \"26-syntax-error-in-hci_helperssvh-in-vivado\" was deleted after merging.\n- No reviews were recorded.\n- FrancescoConti self-assigned the PR.\n\nComments:\nThe sole comment from FrancescoConti states: \"No description provided.\"\n\nNotes:\nThis PR appears to address a syntax compatibility issue with Vivado (Xilinx's FPGA design tool) by handling FPGA targets as a special case within the SystemVerilog helper file.\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/pulp-platform_hci_pr27", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/pulp-platform_hci_pr27.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/pulp-platform_hci_pr27", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/pulp-platform_hci_pr27"}
{"instance_id": "pulp-platform_hci_pr37", "issue_text": "# RQ3-STABILITY violation in `hwpe_core_mux_ooo`: winner-takes-all ignores no-grant condition\n\n- Source URL: https://github.com/pulp-platform/hci/issues/34\n\n![image](https://github.com/pulp-platform/hci/assets/7882682/b2e9848c-ce99-46fb-8da0-1a36dc453642)\n\nIn some instances, when the `in_req` changes in absence of a `gnt` on the pop side, the MUX will switch priorities incorrectly.\n\nPR Title: Fix #34 by keeping winner_d stable in OOO Mux if there is an input request\n\nPR #37 (Merged May 23, 2024)\n\nAuthor: FrancescoConti\n\nDescription:\nThe pull request addresses a stability issue by preventing re-evaluation of the winner-takes-all output except under specific conditions. According to the author: \"Only re-evaluate WTA output after an output handshake or if any in_req was 0, otherwise a more recent in_req could overtake an older one causing a RQ3-STABILITY issue on the output side.\"\n\nThe author notes this represents a rebase of a previous attempt (PR #36) onto the current master branch.\n\nComments:\n\nFrancescoConti:\nCommented that the change prevents a scenario where newer input requests could improperly supersede older ones, which would violate stability requirements on the output side of the multiplexer.\n\nLinked Issue:\nIssue #34: \"RQ3-STABILITY violation in `hwpe_core_mux_ooo`: winner-takes-all ignores no-grant condition\"\n\nThe PR successfully merged one commit into the master branch.\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/pulp-platform_hci_pr37", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/pulp-platform_hci_pr37.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/pulp-platform_hci_pr37", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/pulp-platform_hci_pr37"}
{"instance_id": "pulp-platform_hci_pr67", "issue_text": "# erroneous r_id commit\n\n- Source URL: https://github.com/pulp-platform/hci/issues/66\n\nThis needs to be reverted: https://github.com/pulp-platform/hci/commit/5421524afca701e45a83d0f1ec47568c019e021a\n\nPR Title: Revert \"Fixed HCI Core Static MUX\"\n\nPR #67 (Merged December 1, 2025)\n\nAuthor: FrancescoConti\nTarget Branch: master\n\nDescription:\nThis pull request reverts commit 5421524 and addresses issue #66 regarding an erroneous commit related to the r_id field.\n\nComments:\n\narpansur (Dec 1, 2025):\n\"The static MUX has an assumption that the select line changes when all the outstanding transactions are complete...\" The commenter explained that the static MUX design assumes select line changes only after all transactions complete. They noted that requiring RID for r_valid would necessitate regressions to existing accelerators and is unnecessary given the MUX's design assumptions.\n\nFrancescoConti (Dec 1, 2025):\nRequested official approval from arpansur to proceed with the merge.\n\narpansur (Dec 1, 2025):\nApproved the changes with \"LGTM :)\"\n\nLinked Issue:\nIssue #66: \"erroneous r_id commit\"\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/pulp-platform_hci_pr67", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/pulp-platform_hci_pr67.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/pulp-platform_hci_pr67", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/pulp-platform_hci_pr67"}
{"instance_id": "pulp-platform_neureka_pr30", "issue_text": "# Depthwise mode is broken from 5a4d22f\n\n- Source URL: https://github.com/pulp-platform/neureka/issues/29\n\nDepthwise mode is broken from commit [5a4d22f](https://github.com/pulp-platform/neureka/commit/5a4d22fb7d1c7fde2d8638c5f64eabd24b7a17dc). The working depthwise version is [1ab44a9](https://github.com/pulp-platform/neureka/commit/1ab44a980e3340755798edd39409665e19c432fe)\n\nPR Title: Fix depthwise\n\nPR #30 (Merged March 26, 2025 by arpansur)\n\nDescription:\nThis PR addresses issue #29 (depthwise mode is broken). The changes include:\n- Fixes bugs from commits 5a4d22f and fcfd25d (the latter is temporarily reverted for later inspection)\n- Introduces depthwise tests in the CI\n\nCommits (titles only):\n1. \"Add DW tests to basic regression\"\n2. \"Fix depthwise issues in accumulator_normquant\"\n3. \"Revert 'Reactivate also binconv gating!' to fix depthwise execution\"\n\nComments:\n\nLuigiGhionda (Author, Mar 10):\nThis PR fixes issue #29 regarding broken depthwise mode functionality and adds CI tests.\n\narpansur (Collaborator, Review):\nSuggested \"adding partial utilised channels instead of only a factor of 32\" and \"tests stressing QW<8\" bitwidth variations.\n\narpansur (Response):\nRecommended expanding test coverage across dimensions like K_IN, K_OUT, H_IN, W_IN, and QW for partial tile utilization.\n\nFrancescoConti (Member, Review):\nApproved with comment \"LGTM except for an unexplained constant\" regarding the 32'h0F constant.\n\nFrancescoConti (Clarification):\nRecommended \"keeping this one dedicated to depthwise\" rather than adding broader test variations in the same PR.\n\nFrancescoConti (Final):\n\"OK, let's merge it then!\"\n\nLinked Issue:\nIssue #29: \"Depthwise mode is broken from 5a4d22f\"\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/pulp-platform_neureka_pr30", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/pulp-platform_neureka_pr30.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/pulp-platform_neureka_pr30", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/pulp-platform_neureka_pr30"}
{"instance_id": "pulp-platform_pulp_soc_pr23", "issue_text": "# AXI_ID_WIDTH wrong parameters\n\nSome fixes are needed for synthesis.\r\nThere are wrong parameters when instantiating AXI bus to communicate with the cluster.\r\n\r\nCurrent version:\r\n\r\nAXI_BUS_ASYNC #(\r\n        .AXI_ADDR_WIDTH ( AXI_ADDR_WIDTH     ),\r\n        .AXI_DATA_WIDTH ( AXI_DATA_OUT_WIDTH ),\r\n        **.AXI_ID_WIDTH   ( AXI_ID_OUT_WIDTH   ),**\r\n        .AXI_USER_WIDTH ( AXI_USER_WIDTH     ),\r\n        .BUFFER_WIDTH   ( BUFFER_WIDTH       )\r\n    ) s_data_master ();\r\n    AXI_BUS_ASYNC #(\r\n        .AXI_ADDR_WIDTH ( AXI_ADDR_WIDTH    ),\r\n        .AXI_DATA_WIDTH ( AXI_DATA_IN_WIDTH ),\r\n        **.AXI_ID_WIDTH   ( AXI_ID_OUT_WIDTH  ),**\r\n        .AXI_USER_WIDTH ( AXI_USER_WIDTH     ),\r\n        .BUFFER_WIDTH   ( BUFFER_WIDTH       )\r\n    ) s_data_slave ();\r\n\r\n    AXI_BUS #(\r\n        .AXI_ADDR_WIDTH ( AXI_ADDR_WIDTH    ),\r\n        .AXI_DATA_WIDTH ( AXI_DATA_IN_WIDTH ),\r\n        **.AXI_ID_WIDTH   ( AXI_ID_OUT_WIDTH  ),**\r\n        .AXI_USER_WIDTH ( AXI_USER_WIDTH    )\r\n    ) s_data_in_bus ();\r\n    AXI_BUS #(\r\n        .AXI_ADDR_WIDTH ( AXI_ADDR_WIDTH    ),\r\n        .AXI_DATA_WIDTH ( AXI_DATA_OUT_WIDTH),\r\n        **.AXI_ID_WIDTH   ( AXI_ID_OUT_WIDTH  ),**\r\n        .AXI_USER_WIDTH ( AXI_USER_WIDTH    )\r\n    ) s_data_out_bus (); \r\n\r\n\r\nHow it should be:\r\nAXI_BUS_ASYNC #(\r\n        .AXI_ADDR_WIDTH ( AXI_ADDR_WIDTH     ),\r\n        .AXI_DATA_WIDTH ( AXI_DATA_OUT_WIDTH ),\r\n        **.AXI_ID_WIDTH   ( AXI_ID_OUT_WIDTH   ),**\r\n        .AXI_USER_WIDTH ( AXI_USER_WIDTH     ),\r\n        .BUFFER_WIDTH   ( BUFFER_WIDTH       )\r\n    ) s_data_master ();\r\n\r\n    AXI_BUS_ASYNC #(\r\n        .AXI_ADDR_WIDTH ( AXI_ADDR_WIDTH    ),\r\n        .AXI_DATA_WIDTH ( AXI_DATA_IN_WIDTH ),\r\n        **.AXI_ID_WIDTH   ( AXI_ID_IN_WIDTH   ),**\r\n        .AXI_USER_WIDTH ( AXI_USER_WIDTH     ),\r\n        .BUFFER_WIDTH   ( BUFFER_WIDTH       )\r\n    ) s_data_slave ();\r\n\r\n    AXI_BUS #(\r\n        .AXI_ADDR_WIDTH ( AXI_ADDR_WIDTH    ),\r\n        .AXI_DATA_WIDTH ( AXI_DATA_IN_WIDTH ),\r\n        **.AXI_ID_WIDTH   ( AXI_ID_IN_WIDTH   ),**\r\n        .AXI_USER_WIDTH ( AXI_USER_WIDTH    )\r\n    ) s_data_in_bus ();\r\n\r\n\r\n    AXI_BUS #(\r\n        .AXI_ADDR_WIDTH ( AXI_ADDR_WIDTH    ),\r\n        .AXI_DATA_WIDTH ( AXI_DATA_OUT_WIDTH),\r\n        **.AXI_ID_WIDTH   ( AXI_ID_OUT_WIDTH  ),**\r\n        .AXI_USER_WIDTH ( AXI_USER_WIDTH    )\r\n    ) s_data_out_bus ();\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/pulp-platform_pulp_soc_pr23", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/pulp-platform_pulp_soc_pr23.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/pulp-platform_pulp_soc_pr23", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/pulp-platform_pulp_soc_pr23"}
{"instance_id": "pulp-platform_pulp_soc_pr41", "issue_text": "# Interleaved Memory space only partially accessible\n\nIn l2_ram_multibank.sv the wrong bits are selected for the interleaved memory banks. Currently, only the 2 LSBs are striped which converts from byte addressing to 32-bit word addressing. However, for the interleaved memory banks, we also have to remove $clog2(Nr_of_banks) bits that index the bank due to the interleaved address space mapping. The effect of not doing this is that we start to alias as soon as we try to write more than 128KB into L2 memory.\n\nPR Title: Fixes #40\n\nPR #41 (Merged Jan 7, 2021)\n\nDescription:\nThe PR addresses a bug in interleaved memory bank address extraction. The issue involved improper handling of address bits when accessing the 32-bit TCDM (Tightly Coupled Data Memory). According to the submitter, \"For the interleaved memory space, we have to remove the 2 LSBs since the SRAMs are 32-bit word aligned while TCDM uses byte addressing. However, in addition to that, we also have to remove $clog2(Nr_banks) additional LSBs since those bits are used to select the memory bank in interleaved addressing.\"\n\nComments:\n\nbluewww (Approver):\n\"Passes CI and fixes camera test regressions\"\n\nLinked Issue:\nIssue #40: \"Interleaved Memory space only partially accessible\"\n\nParticipants:\n- meggiman (Author)\n- bluewww (Reviewer/Merger)\n\nThe PR was successfully merged with one commit.\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/pulp-platform_pulp_soc_pr41", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/pulp-platform_pulp_soc_pr41.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/pulp-platform_pulp_soc_pr41", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/pulp-platform_pulp_soc_pr41"}
{"instance_id": "pulp-platform_pulp_soc_pr54", "issue_text": "# Unconnected input port `lint_r_aux_i` of `adbg_lintonly_top`\n\nIn `lint_jtag_wrap.sv` there's an unconnected input port [`lint_r_aux_i`](https://github.com/pulp-platform/pulp_soc/blob/master/rtl/pulp_soc/lint_jtag_wrap.sv#L63) of module `dbg_module_i`.\n\nPR Title: Add r_opc signal to tcdm_arbiter_2x1\n\nPR #54 (Merged on February 10, 2021)\n\nDescription:\nThe PR addressed missing signal connectivity and unconnected input ports in the TCDM arbiter component. It consisted of three commits:\n\n1. \"Add r_opc signal to tcdm_arbiter_2x1\" — Added the missing r_opc signal.\n2. \"Fix warning in Questasim\" — \"Due to the missing default statement, questasim issues a warning that no condition is true for the unique case statement\"\n3. \"Tie unused input port to 0\" — Connected an unused input port.\n\nRelated Issues:\n- Issue #51: \"Missing signal of tcdm bus in tcdm_arbiter_2x1.sv\"\n- Issue #50: \"Unconnected input port `lint_r_aux_i` of `adbg_lintonly_top`\"\n\nReview & Merge:\n- Author: meggiman (Contributor)\n- Reviewer: bluewww (Collaborator) — Approved with \"lgtm\" comment\n- Merged by: meggiman\n- 3 commits included in the merge\n\nThe pull request resolved both linked issues through hardware design fixes and simulation warning resolutions.\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/pulp-platform_pulp_soc_pr54", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/pulp-platform_pulp_soc_pr54.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/pulp-platform_pulp_soc_pr54", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/pulp-platform_pulp_soc_pr54"}
{"instance_id": "pulp-platform_pulp_soc_pr69", "issue_text": "# Replace generic srams with new tc_sram modules\n\nthis change would allows us to use xilinx parametrized macros for the FPGA port instead of separately synthesizing xilinx block memory IPs\n\nPR Title: Remove explicit fpga RAM instantiation\n\nPR #69 (Merged by bluewww on June 25, 2021)\n\nDescription:\nThe change eliminates the need for out-of-context synthesis of Xilinx SRAM IPs in FPGA ports. Instead, the `tech_cells_generic` `tc_sram` wrapper now handles Xilinx parametrized macro instantiation when bender/IPapprox targets are properly configured. This approach eliminates manual synchronization requirements between RTL and FPGA TCL scripts regarding SRAM memory sizes.\n\nParticipants & Activity:\n- Author: meggiman\n- Reviewer/Merger: bluewww (approved and merged the single commit)\n- Branch: fpga_ram_improvement -> master\n\nLinked Issue:\nIssue #55: \"Replace generic srams with new tc_sram modules\" (closed by this PR)\n\nThe PR contains one force-pushed commit and received approval before merging. The feature branch was deleted following the merge.\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/pulp-platform_pulp_soc_pr69", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/pulp-platform_pulp_soc_pr69.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/pulp-platform_pulp_soc_pr69", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/pulp-platform_pulp_soc_pr69"}
{"instance_id": "pulp-platform_pulp_soc_pr73", "issue_text": "# Remove apb_timer\n\nInstance: pulp-platform_pulp_soc_pr73\nSource: https://github.com/pulp-platform/pulp_soc/pull/73\nFetched: 2026-04-26\nRepository: pulp-platform/pulp_soc\nPull request: #73\nAuthor: bluewww\nState: closed\nBase branch: master\nHead branch: rm-timer\nCreated: 2022-02-21T08:58:36Z\nUpdated: 2022-02-21T11:46:27Z\nClosed: 2022-02-21T11:46:24Z\nMerged: 2022-02-21T11:46:24Z\n\nThis one is already present as IP in timer_unit\r\n\r\nFixes #73\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/pulp-platform_pulp_soc_pr73", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/pulp-platform_pulp_soc_pr73.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/pulp-platform_pulp_soc_pr73", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/pulp-platform_pulp_soc_pr73"}
{"instance_id": "pulp-platform_pulp_soc_pr95", "issue_text": "# Restricted/confidential code checked into repo\n\nHi there,\n\nhttps://github.com/pulp-platform/pulp_soc/blob/0573a85c8ec502ff5e3ef06946a75eaf567ce16a/rtl/components/tcdm_arbiter_2x1.sv#L5-L9\n\nI was doing a license audit and noticed that you have a file checked into your public repository that is expressly prohibited from distribution, which many users now have a copy of because it is automatically distributed when the repository is cloned.\n\nCan you please clarify the disposition of this file?\n\nPR Title: rtl: Fix wrong license header\n\nPR #95 (Merged on January 11, 2024)\n\nDescription:\nThe PR addresses a licensing oversight where the proper license header was not set for `tcdm_arbiter_2x1.sv`. The description states: \"We forgot to properly set the license header for `tcdm_arbiter_2x1.sv`. Fixes #94\"\n\nAuthor: bluewww\n\nComments:\nNo substantive discussion comments were present in the conversation thread.\n\nLinked Issue:\nIssue #94: \"Restricted/confidential code checked into repo\"\n\nKey Details:\n- Single commit merged\n- Branch deleted after merge\n- No reviews recorded\n- No assignees or labels applied\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/pulp-platform_pulp_soc_pr95", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/pulp-platform_pulp_soc_pr95.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/pulp-platform_pulp_soc_pr95", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/pulp-platform_pulp_soc_pr95"}
{"instance_id": "pulp-platform_pulpissimo_pr233", "issue_text": "# use of TCDM_ALIAS Address\n\n- Source URL: https://github.com/pulp-platform/pulpissimo/issues/228\n\nHi,\n    can someone explain the use of these two addresses in soc_mem_map.svh.\n\n`define SOC_MEM_MAP_TCDM_ALIAS_START_ADDR    32'h0000_0000\n`define SOC_MEM_MAP_TCDM_ALIAS_END_ADDR      32'h0010_0000\n\nI don't think they have been used in the code. Correct me if I am wrong\n\nPR Title: Remove unused TCDM alias region definitions\n\nPR #233 (Merged on March 18, 2021)\n\nAuthor: meggiman\nReviewer: bluewww\n\nDescription:\nThe PR references issue #228, titled \"use of TCDM_ALIAS Address,\" addressing the removal of unused alias region definitions from the codebase.\n\nComments:\n\nmeggiman (March 18, 2021):\n\"Fixes #228\"\n\nbluewww (March 18, 2021):\n\"lgtm\"\n\nBluewww subsequently approved the changes and meggiman merged the commit into the master branch.\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/pulp-platform_pulpissimo_pr233", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/pulp-platform_pulpissimo_pr233.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/pulp-platform_pulpissimo_pr233", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/pulp-platform_pulpissimo_pr233"}
{"instance_id": "pulp-platform_redundancy_cells_pr18", "issue_text": "# Dynamic arrays in synthesizable code\n\n- Source URL: https://github.com/pulp-platform/redundancy_cells/issues/17\n\n[Dynamic arrays](https://github.com/pulp-platform/redundancy_cells/blob/master/rtl/hsiao_ecc/hsiao_ecc_pkg.sv#L16) are probably not supported for RTL synthesis. [Synopsys DC](https://iis-git.ee.ethz.ch/github-mirror/carfield/-/jobs/997337#L429) and [Vivado](https://iis-git.ee.ethz.ch/github-mirror/carfield/-/jobs/997386#L4381) both complain.\n\nPR Title: Fix ECC synthesizability\n\nPR #18 (Merged February 19, 2024)\n\nAuthor: micprog\nReviewer: yvantor\n\nDescription:\nThe pull request description states: \"Fixes #17\"\n\nThis is a brief reference indicating the PR addresses issue #17 in the repository.\n\nCommits (titles only, 5 total):\n1. Fix testbench compilation\n2. Enforce fixed arrays for synthesizability\n3. Fix lint\n4. Fix data widths\n5. Add parameter explanations\n\nComments:\n\nyvantor (February 19, 2024):\n\"I left a few minor comments, apart from that it looks good!\"\n\nLinked Issue:\nIssue #17 Title: \"Dynamic arrays in synthesizable code\"\n\nThe PR addresses problems with using dynamic arrays in code meant for hardware synthesis.\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/pulp-platform_redundancy_cells_pr18", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/pulp-platform_redundancy_cells_pr18.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/pulp-platform_redundancy_cells_pr18", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/pulp-platform_redundancy_cells_pr18"}
{"instance_id": "pulp-platform_register_interface_pr17", "issue_text": "# src/reg_mux.sv: Delete duplicated assignment\n\nInstance: pulp-platform_register_interface_pr17\nSource: https://github.com/pulp-platform/register_interface/pull/17\nFetched: 2026-04-26\nRepository: pulp-platform/register_interface\nPull request: #17\nAuthor: Freakness109\nState: closed\nBase branch: master\nHead branch: master\nCreated: 2022-03-24T13:50:13Z\nUpdated: 2022-08-10T05:28:51Z\nClosed: 2022-08-10T05:28:51Z\nMerged: 2022-08-10T05:28:51Z\n\nPR Title: src/reg_mux.sv: Delete duplicated assignment\n\nPR #17 (Merged Aug 10, 2022)\n\nDescription:\nThe contributor identified a compilation error caused by the `valid` signal being assigned twice in the code (at lines 61 and 69). The fix prioritizes the assignment from the stream arbiter's valid port over the payload assignment.\n\nComments:\n\nFreakness109 (Original Author, Mar 24, 2022):\n\"The valid signal was being assigned to twice (Lines 61 and 69), which causes errors in compilation.\"\n\nbluewww (Aug 9, 2022):\n\"Looks like a real issue\"\n\nmeggiman (Approver, Aug 10, 2022):\n\"Sorry for the slow response and thanks a lot for contributing. This looks perfectly reasonable.\"\n\nMetadata:\n- Author: Freakness109\n- Merged by: meggiman\n- Label: bug\n- Participants: 3 (Freakness109, bluewww, meggiman)\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/pulp-platform_register_interface_pr17", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/pulp-platform_register_interface_pr17.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/pulp-platform_register_interface_pr17", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/pulp-platform_register_interface_pr17"}
{"instance_id": "pulp-platform_register_interface_pr21", "issue_text": "# add reg to tlul\n\nInstance: pulp-platform_register_interface_pr21\nSource: https://github.com/pulp-platform/register_interface/pull/21\nFetched: 2026-04-26\nRepository: pulp-platform/register_interface\nPull request: #21\nAuthor: davideschiavone\nState: closed\nBase branch: master\nHead branch: add_reg2tlul\nCreated: 2022-09-07T13:05:05Z\nUpdated: 2022-09-14T17:59:43Z\nClosed: 2022-09-14T17:59:43Z\nMerged: 2022-09-14T17:59:42Z\n\nPR Title: add reg to tlul\n\nPR #21 (Merged Sep 14, 2022)\n\nDescription:\nThe PR description was minimal. The author simply stated: \"As requested\"\n\nCommits (titles only):\n1. \"add reg to tlul\"\n2. \"Add reg2tlul parameters (#1) * add parameters to reg2tlul * add parameters\"\n\nComments:\n\ndavideschiavone (Sep 7, 2022):\n\"As requested\"\n\nmeggiman (Sep 14, 2022):\n\"Awesome! Thanks a lot for your contribution.\"\n\nMerge Information:\n- Merged by: meggiman\n- Merge date: Sep 14, 2022\n- Merged into: pulp-platform:master\n- Merged from: davideschiavone:add_reg2tlul\n\nParticipants:\n- davideschiavone (contributor)\n- meggiman (reviewer/merger)\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/pulp-platform_register_interface_pr21", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/pulp-platform_register_interface_pr21.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/pulp-platform_register_interface_pr21", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/pulp-platform_register_interface_pr21"}
{"instance_id": "pulp-platform_register_interface_pr23", "issue_text": "# Add simple error slave\n\nInstance: pulp-platform_register_interface_pr23\nSource: https://github.com/pulp-platform/register_interface/pull/23\nFetched: 2026-04-26\nRepository: pulp-platform/register_interface\nPull request: #23\nAuthor: Vyeow\nState: closed\nBase branch: master\nHead branch: feature/err_slv\nCreated: 2022-10-31T14:59:41Z\nUpdated: 2022-11-02T08:03:34Z\nClosed: 2022-11-02T08:03:26Z\nMerged: 2022-11-02T08:03:26Z\n\nPR Title: Add simple error slave\n\nPR #23 (Merged November 2, 2022)\n\nAuthor: Vyeow\nMerged by: meggiman\n\nDescription:\nThe PR description was minimal. Vyeow noted that \"req_i is not needed in the module, but thought it a good idea to keep it for cosmetic reasons.\"\n\nReview Comments:\n\nmeggiman's Initial Feedback (Nov 1, 2022):\n\n1. Metadata files: Contributor requested updates to Bender.yml and src_files.yml to register the error slave module.\n\n2. Type parameter suggestion: Proposed adding a `payload_t` type parameter defaulting to `logic[DW-1:0]` to support packed struct payloads, noting: \"the error slave cannot be used as is\" without this flexibility.\n\n3. Parameter defaults: Recommended using `-1` as the default for DW to discourage using modules \"without explicitly specifying the parameter values.\"\n\n4. Error value defaults: Suggested changing to `'0` as default, stating users should \"explicitly choose which error value they want to return.\"\n\nResolution:\nVyeow implemented the requested changes in a second commit. Meggiman approved with \"lgtm. Thanks a lot!\" and merged the PR on November 2, 2022, subsequently deleting the feature branch.\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/pulp-platform_register_interface_pr23", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/pulp-platform_register_interface_pr23.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/pulp-platform_register_interface_pr23", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/pulp-platform_register_interface_pr23"}
{"instance_id": "pulp-platform_register_interface_pr24", "issue_text": "# [feature] Add reg_to_apb adapter\n\nInstance: pulp-platform_register_interface_pr24\nSource: https://github.com/pulp-platform/register_interface/pull/24\nFetched: 2026-04-26\nRepository: pulp-platform/register_interface\nPull request: #24\nAuthor: creinwar\nState: closed\nBase branch: master\nHead branch: feature/reg_to_apb\nCreated: 2022-11-02T23:44:22Z\nUpdated: 2022-11-04T15:00:39Z\nClosed: 2022-11-04T15:00:35Z\nMerged: 2022-11-04T15:00:35Z\n\nPR Title: [feature] Add reg_to_apb adapter\n\nPR #24 (Merged November 4, 2022)\nBranch: feature/reg_to_apb -> master\n\nDescription:\nNo description was provided by the contributor.\n\nComments:\n\ncreinwar (Collaborator) - November 2, 2022, 23:44:\nRequested review from meggiman.\n\nmeggiman (Contributor) - November 4, 2022:\nLeft approval comment: \"lgtm. Thanks for the contribution!\" Merged into master and deleted the feature/reg_to_apb branch.\n\nParticipants:\n- creinwar (author)\n- meggiman (reviewer/approver)\n\nAdditional Details:\n- 1 commit included\n- No issues linked\n- No assignees\n- No labels\n- No milestone\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/pulp-platform_register_interface_pr24", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/pulp-platform_register_interface_pr24.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/pulp-platform_register_interface_pr24", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/pulp-platform_register_interface_pr24"}
{"instance_id": "pulp-platform_register_interface_pr26", "issue_text": "# Add interface variants to reggen\n\nInstance: pulp-platform_register_interface_pr26\nSource: https://github.com/pulp-platform/register_interface/pull/26\nFetched: 2026-04-26\nRepository: pulp-platform/register_interface\nPull request: #26\nAuthor: meggiman\nState: closed\nBase branch: master\nHead branch: add_interface_variant_to_reggen\nCreated: 2022-12-13T10:05:28Z\nUpdated: 2022-12-13T10:06:27Z\nClosed: 2022-12-13T10:06:22Z\nMerged: 2022-12-13T10:06:22Z\n\nPR Title: Add interface variants to reggen\n\nPR #26 (Merged on December 13, 2022)\n\nAuthor: meggiman\n\nDescription:\nNo description provided.\n\nCommits (titles only):\n1. \"Add interface variant of apb_to_reg converter\"\n2. \"Generate regfiles with interface variant and add missing signal type specifier for clock and reset\"\n\nComments:\nThe author posted only: \"No description provided.\"\n\nReviewers: None\nAssignees: None\nLabels: None\n\nLinked Issues: None explicitly linked.\n\nNotes:\nThis merged pull request introduced interface variants to the reggen component within the register_interface repository, specifically adding an interface variant of the apb_to_reg converter and updating register file generation with proper signal type specifications.\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/pulp-platform_register_interface_pr26", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/pulp-platform_register_interface_pr26.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/pulp-platform_register_interface_pr26", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/pulp-platform_register_interface_pr26"}
{"instance_id": "pulp-platform_register_interface_pr30", "issue_text": "# apb_to_reg: Add option to properly latch forward path\n\nInstance: pulp-platform_register_interface_pr30\nSource: https://github.com/pulp-platform/register_interface/pull/30\nFetched: 2026-04-26\nRepository: pulp-platform/register_interface\nPull request: #30\nAuthor: bluewww\nState: closed\nBase branch: master\nHead branch: apb-latch\nCreated: 2023-04-11T20:35:57Z\nUpdated: 2023-04-28T08:16:15Z\nClosed: 2023-04-28T08:00:44Z\nMerged: 2023-04-28T08:00:44Z\n\nAPB sel is meant to help you latch the addr, wdata and write. Feeding these signals through means basically repurposing apb to work like register interface.\r\n\r\nAdd option to allow you to do the request APB style with latching. Since there a bunch of quite broken APB masters out there which will break with this change we keep it in feedthrough mode by default.\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/pulp-platform_register_interface_pr30", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/pulp-platform_register_interface_pr30.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/pulp-platform_register_interface_pr30", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/pulp-platform_register_interface_pr30"}
{"instance_id": "pulp-platform_register_interface_pr31", "issue_text": "# Split `reg_cdc` into `reg_cdc_src` and `reg_cdc_dst`.\n\nInstance: pulp-platform_register_interface_pr31\nSource: https://github.com/pulp-platform/register_interface/pull/31\nFetched: 2026-04-26\nRepository: pulp-platform/register_interface\nPull request: #31\nAuthor: luca-valente\nState: closed\nBase branch: master\nHead branch: lv/split_cdc\nCreated: 2023-04-27T16:57:30Z\nUpdated: 2023-04-28T08:16:06Z\nClosed: 2023-04-28T08:04:10Z\nMerged: 2023-04-28T08:04:10Z\n\nPR Title: Split `reg_cdc` into `reg_cdc_src` and `reg_cdc_dst`\n\nPR #31 (Merged April 28, 2023)\n\nDescription:\nThe contributor provided no written description for this pull request.\n\nComments & Approvals:\n\nluca-valente (Contributor):\nInitiated the PR on April 27, 2023, requesting reviews from meggiman and micprog.\n\nmicprog (Member):\nApproved with comment: \"LGTM\"\n\nmeggiman (Contributor):\nApproved with comment: \"LGTM Thanks\" and subsequently merged the changes into the master branch.\n\nKey Details:\n- Commits: 1 commit\n- Merged by: meggiman on April 28, 2023\n- Branch deleted: lv/split_cdc was removed after merging\n\nNo linked issues or additional context were provided.\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/pulp-platform_register_interface_pr31", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/pulp-platform_register_interface_pr31.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/pulp-platform_register_interface_pr31", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/pulp-platform_register_interface_pr31"}
{"instance_id": "pulp-platform_register_interface_pr32", "issue_text": "# Add `reg_filter_empty_writes`\n\nInstance: pulp-platform_register_interface_pr32\nSource: https://github.com/pulp-platform/register_interface/pull/32\nFetched: 2026-04-26\nRepository: pulp-platform/register_interface\nPull request: #32\nAuthor: micprog\nState: closed\nBase branch: master\nHead branch: empty_write_filter\nCreated: 2023-04-27T18:04:37Z\nUpdated: 2023-04-28T08:15:54Z\nClosed: 2023-04-28T08:15:49Z\nMerged: 2023-04-28T08:15:49Z\n\nPR Title: Add `reg_filter_empty_writes`\n\nPR #32 (Merged Apr 28, 2023)\n\nDescription:\nThe PR adds a new module that \"Returns a ready without forwarding the valid for writes with strb='0.\"\n\nComments:\n\nmicprog (Author):\nExplained the use case: Data width downsizers like AXI may issue writes with empty strobes connected to proper writes. The regtool-generated register file doesn't handle this scenario well, prompting this addition.\n\nmeggiman (Reviewer):\nInitially questioned which IPs would issue empty write strobes, noting the addition doesn't affect other IPs. After receiving clarification about the AXI downsizer scenario, meggiman approved with: \"Fair enough. In that case, I have no objection.\"\n\nbluewww (Reviewer):\nApproved with a thumbs-up reaction, reportedly encountering this issue per micprog's comments.\n\nMetadata:\n- Repository: pulp-platform/register_interface\n- Branch: empty_write_filter -> master\n- Participants: micprog, meggiman, bluewww\n- Commits: 1\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/pulp-platform_register_interface_pr32", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/pulp-platform_register_interface_pr32.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/pulp-platform_register_interface_pr32", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/pulp-platform_register_interface_pr32"}
{"instance_id": "pulp-platform_register_interface_pr33", "issue_text": "# Fix typo in `reg_filter_empty_writes`\n\nInstance: pulp-platform_register_interface_pr33\nSource: https://github.com/pulp-platform/register_interface/pull/33\nFetched: 2026-04-26\nRepository: pulp-platform/register_interface\nPull request: #33\nAuthor: micprog\nState: closed\nBase branch: master\nHead branch: fix_empty_write\nCreated: 2023-04-28T15:33:07Z\nUpdated: 2023-04-28T15:34:43Z\nClosed: 2023-04-28T15:34:40Z\nMerged: 2023-04-28T15:34:40Z\n\nPR title: Fix typo in `reg_filter_empty_writes`\n\nPR description:\nNo description was provided by the pull request author.\n\nComments:\n- micprog (Apr 28, 2023): No substantive comment provided.\n- meggiman (Apr 28, 2023): Approved the changes and subsequently merged the pull request.\n\nLinked issues: None.\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/pulp-platform_register_interface_pr33", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/pulp-platform_register_interface_pr33.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/pulp-platform_register_interface_pr33", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/pulp-platform_register_interface_pr33"}
{"instance_id": "pulp-platform_register_interface_pr34", "issue_text": "# reg_filter_empty_write: Fix internal signal names\n\nInstance: pulp-platform_register_interface_pr34\nSource: https://github.com/pulp-platform/register_interface/pull/34\nFetched: 2026-04-26\nRepository: pulp-platform/register_interface\nPull request: #34\nAuthor: micprog\nState: closed\nBase branch: master\nHead branch: fix_empty_write\nCreated: 2023-05-02T08:14:05Z\nUpdated: 2023-05-05T13:05:40Z\nClosed: 2023-05-05T13:05:37Z\nMerged: 2023-05-05T13:05:36Z\n\nPR title: reg_filter_empty_write: Fix internal signal names\n\nPR description:\nNo explicit full description was provided. The PR body posted by the author at submission was:\n\"Now properly tested: https://github.com/pulp-platform/cheshire/tree/reg_filter\nSorry for the hasty, untested inclusion previously.\"\n\nComments:\n- micprog (May 2, 2023): \"Now properly tested: https://github.com/pulp-platform/cheshire/tree/reg_filter. Sorry for the hasty, untested inclusion previously.\"\n- meggiman (May 5, 2023): \"thanks for the fix\"\n\nReview and merge:\n- Reviewer: meggiman (approved May 5, 2023)\n- Merge commit: 47d2d83\n\nLinked issues: None.\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/pulp-platform_register_interface_pr34", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/pulp-platform_register_interface_pr34.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/pulp-platform_register_interface_pr34", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/pulp-platform_register_interface_pr34"}
{"instance_id": "pulp-platform_register_interface_pr35", "issue_text": "# Add minimal CI compiling files with internal tools\n\nInstance: pulp-platform_register_interface_pr35\nSource: https://github.com/pulp-platform/register_interface/pull/35\nFetched: 2026-04-26\nRepository: pulp-platform/register_interface\nPull request: #35\nAuthor: micprog\nState: closed\nBase branch: master\nHead branch: ci-tests\nCreated: 2023-05-03T09:58:50Z\nUpdated: 2026-02-14T23:13:34Z\nClosed: 2023-05-05T13:07:13Z\nMerged: 2023-05-05T13:07:13Z\n\nPR title: Add minimal CI compiling files with internal tools\n\nPR description:\nNo description provided.\n\nComments:\n- micprog (May 3, 2023): Opened the PR with no description.\n- meggiman (May 5, 2023): \"That's a very sensible addition. Thanks a lot!\"\n\nReview and merge:\n- Author: micprog\n- Reviewer/Merger: meggiman\n- Branch: ci-tests -> master\n\nLinked issues: None mentioned.\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/pulp-platform_register_interface_pr35", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/pulp-platform_register_interface_pr35.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/pulp-platform_register_interface_pr35", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/pulp-platform_register_interface_pr35"}
{"instance_id": "pulp-platform_register_interface_pr36", "issue_text": "# `reg_cdc`: option to choose `cdc_4phase` over `cdc_2phase`.\n\nInstance: pulp-platform_register_interface_pr36\nSource: https://github.com/pulp-platform/register_interface/pull/36\nFetched: 2026-04-26\nRepository: pulp-platform/register_interface\nPull request: #36\nAuthor: luca-valente\nState: closed\nBase branch: master\nHead branch: cdc_4phase\nCreated: 2023-05-05T13:02:51Z\nUpdated: 2023-05-24T19:34:24Z\nClosed: 2023-05-24T19:34:18Z\nMerged: 2023-05-24T19:34:18Z\n\nPR title: `reg_cdc`: option to choose `cdc_4phase` over `cdc_2phase`.\n\nPR description:\nNo formal description was provided by the author.\n\nComments:\n- luca-valente (Author, May 5): Acknowledged uncertainty about parameter handling, asking: \"We could use `localparam`, or use the default params or propagate them from the top level.\"\n- meggiman (Reviewer, May 17): Provided two specific suggestions:\n  1. \"Please stop using the `generate` keyword. It is not necessary anymore in SystemVerilog.\"\n  2. Recommended using a string parameter instead of a boolean flag for better design clarity.\n- meggiman (May 24, post-merge): \"I think now it looks fine. Thanks a lot for your contribution.\"\n\nParticipants:\n- luca-valente (contributor)\n- meggiman (maintainer/merger)\n- micprog (review requested but did not review)\n\nResolution:\nThe pull request was successfully merged after incorporating reviewer feedback, specifically replacing the boolean CDC parameter with a string parameter and removing deprecated `generate` statements.\n\nLinked issues: None.\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/pulp-platform_register_interface_pr36", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/pulp-platform_register_interface_pr36.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/pulp-platform_register_interface_pr36", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/pulp-platform_register_interface_pr36"}
{"instance_id": "pulp-platform_register_interface_pr38", "issue_text": "# Remov AND between input ready and valid to solve timing loops\n\nInstance: pulp-platform_register_interface_pr38\nSource: https://github.com/pulp-platform/register_interface/pull/38\nFetched: 2026-04-26\nRepository: pulp-platform/register_interface\nPull request: #38\nAuthor: yvantor\nState: closed\nBase branch: master\nHead branch: yt/timing-loop\nCreated: 2023-05-12T16:40:20Z\nUpdated: 2023-05-17T22:25:49Z\nClosed: 2023-05-17T22:25:43Z\nMerged: 2023-05-17T22:25:43Z\n\nPR title: Remov AND between input ready and valid to solve timing loops\n\nPR description:\n\"Fix protocol assign that might result in timing loops. The master and slave devices must take care of respecting the protocol, while the interface should only assign the various signals. See #37 .\"\n\nComments:\n- yvantor (May 12, 2023): Posted the initial PR description explaining the timing loop fix and linking to issue #37.\n- alex96295 (May 14, 2023): Modified the PR title slightly (corrected spelling from \"Removed\" to \"Remov\").\n- meggiman (May 17, 2023): Approved with the comment \"lgtm! Thanks for the PR\" and subsequently merged the changes.\n\nLinked issues:\n- #37 (referenced) regarding protocol violations.\n- Referenced in carfield PR #14 for RTL fixes against Spyglass and Synthesis.\n\nParticipants: yvantor (author), meggiman (reviewer/merger), alex96295 (contributor).\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/pulp-platform_register_interface_pr38", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/pulp-platform_register_interface_pr38.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/pulp-platform_register_interface_pr38", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/pulp-platform_register_interface_pr38"}
{"instance_id": "pulp-platform_register_interface_pr39", "issue_text": "# `reg_cut` to cut paths between regs interfaces.\n\nInstance: pulp-platform_register_interface_pr39\nSource: https://github.com/pulp-platform/register_interface/pull/39\nFetched: 2026-04-26\nRepository: pulp-platform/register_interface\nPull request: #39\nAuthor: luca-valente\nState: closed\nBase branch: master\nHead branch: lv/reg_cut\nCreated: 2023-05-24T14:16:40Z\nUpdated: 2023-06-12T20:16:13Z\nClosed: 2023-06-12T20:16:09Z\nMerged: 2023-06-12T20:16:09Z\n\nPR title: `reg_cut` to cut paths between regs interfaces.\n\nPR description:\nNo description was provided by the contributor. The accompanying commit message: \"`reg_cut` to cut combinatorial paths between regs interfaces.\" (commit hash 6f2b8bb3aa4cb6ac0cb373d205859f4fa7fd3d57).\n\nComments:\n- luca-valente (May 24, 2023): Requested review from meggiman and micprog.\n- meggiman (June 12, 2023): \"lgtm! Thanks for the contribution.\"\n\nMerge details:\n- Merged by: meggiman\n- Merge date: June 12, 2023\n- Branch deleted: lv/reg_cut\n\nParticipants: luca-valente (author), meggiman (reviewer/merger). micprog was requested for review but did not provide feedback.\n\nLinked issues: None.\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/pulp-platform_register_interface_pr39", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/pulp-platform_register_interface_pr39.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/pulp-platform_register_interface_pr39", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/pulp-platform_register_interface_pr39"}
{"instance_id": "pulp-platform_register_interface_pr40", "issue_text": "# axi_to_reg: Expose `axi_to_axi_lite` module's `FULL_BW` parameter\n\nInstance: pulp-platform_register_interface_pr40\nSource: https://github.com/pulp-platform/register_interface/pull/40\nFetched: 2026-04-26\nRepository: pulp-platform/register_interface\nPull request: #40\nAuthor: colluca\nState: closed\nBase branch: master\nHead branch: fix/full-bw\nCreated: 2023-06-12T07:35:22Z\nUpdated: 2023-09-12T09:06:30Z\nClosed: 2023-09-12T08:51:53Z\nMerged: 2023-09-12T08:51:53Z\n\nThis PR exposes the `FULL_BW` parameter of the `axi_to_axi_lite` module in the `axi_to_reg` IP. This enables AXI testbench memories built on `axi_to_reg` to have full bandwidth, i.e. respond with a maximum throughput of one R beat every cycle.\r\n\r\nDepends on [this PR](https://github.com/pulp-platform/axi/pull/307), so **wait for it to be merged first and update Bender dependency**.\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/pulp-platform_register_interface_pr40", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/pulp-platform_register_interface_pr40.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/pulp-platform_register_interface_pr40", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/pulp-platform_register_interface_pr40"}
{"instance_id": "pulp-platform_register_interface_pr46", "issue_text": "# axi_to_reg_v2: Add optional mem cuts\n\nInstance: pulp-platform_register_interface_pr46\nSource: https://github.com/pulp-platform/register_interface/pull/46\nFetched: 2026-04-26\nRepository: pulp-platform/register_interface\nPull request: #46\nAuthor: paulsc96\nState: closed\nBase branch: master\nHead branch: paulsc/cut-axi2reg\nCreated: 2024-02-23T17:19:21Z\nUpdated: 2024-03-01T14:06:58Z\nClosed: 2024-03-01T14:00:06Z\nMerged: 2024-03-01T14:00:06Z\n\nThe `axi_to_reg_v2` module, while greatly improving functionality, incurs rather long paths. \r\n\r\nFor example, even when inserting a retimed `axi_cut` right at its input, it still causes the longest (currently violating) path in Cheshire's FPGA implementation, with its `i_axi_to_detailed_mem` claiming more than half the path length alone.\r\n\r\nThis PR inserts optional (default disabled) mem request and response cuts right after `i_axi_to_detailed_mem`. While this may become quite expensive for large `AxiDataWidth/RegDataWidth`, it should efficiently mitigate timing issues, especially as register interfaces cannot be cut without bandwidth loss.\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/pulp-platform_register_interface_pr46", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/pulp-platform_register_interface_pr46.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/pulp-platform_register_interface_pr46", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/pulp-platform_register_interface_pr46"}
{"instance_id": "pulp-platform_register_interface_pr48", "issue_text": "# reg_to_axi: Add module\n\nInstance: pulp-platform_register_interface_pr48\nSource: https://github.com/pulp-platform/register_interface/pull/48\nFetched: 2026-04-26\nRepository: pulp-platform/register_interface\nPull request: #48\nAuthor: paulsc96\nState: closed\nBase branch: master\nHead branch: paulsc/reg_to_axi\nCreated: 2024-03-14T20:17:47Z\nUpdated: 2026-02-14T23:08:42Z\nClosed: 2024-03-14T22:06:52Z\nMerged: 2024-03-14T22:06:52Z\n\nPR title: reg_to_axi: Add module\n\nPR description:\n\"See pulp-platform/axi#335.\"\n\nActivity timeline:\n- March 14, 2024 20:22: Force-pushed branch with commit updates.\n- March 14, 2024 20:36: Marked PR as ready for review.\n- March 14, 2024 20:38: Additional force-push with refinements.\n- March 14, 2024 20:40: Final force-push before merge.\n- March 14, 2024: Merged into master branch via commit aa19b25.\n- February 14, 2026: Branch deleted post-merge.\n\nReviewers: None listed. Assignees: None. Labels: None.\n\nLinked references:\n- pulp-platform/axi#335 (external related pull request).\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/pulp-platform_register_interface_pr48", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/pulp-platform_register_interface_pr48.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/pulp-platform_register_interface_pr48", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/pulp-platform_register_interface_pr48"}
{"instance_id": "pulp-platform_register_interface_pr54", "issue_text": "# reg_to_axi: fix axi error detection\n\nInstance: pulp-platform_register_interface_pr54\nSource: https://github.com/pulp-platform/register_interface/pull/54\nFetched: 2026-04-26\nRepository: pulp-platform/register_interface\nPull request: #54\nAuthor: TheMightyDuckOfDoom\nState: closed\nBase branch: master\nHead branch: fix-reg2axi\nCreated: 2025-07-29T14:12:32Z\nUpdated: 2025-08-04T20:31:57Z\nClosed: 2025-08-04T20:31:57Z\nMerged: 2025-08-04T20:31:57Z\n\nCurrently, we raise the error bit if we get a \"RESP_OKAY\".\r\nI think we have an error if we get something else than \"RESP_OKAY\".\r\n\r\nThis commit fixes this problem.\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/pulp-platform_register_interface_pr54", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/pulp-platform_register_interface_pr54.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/pulp-platform_register_interface_pr54", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/pulp-platform_register_interface_pr54"}
{"instance_id": "pulp-platform_register_interface_pr55", "issue_text": "# apb_to_reg: Replace modport with struct in default converter\n\nInstance: pulp-platform_register_interface_pr55\nSource: https://github.com/pulp-platform/register_interface/pull/55\nFetched: 2026-04-26\nRepository: pulp-platform/register_interface\nPull request: #55\nAuthor: phsauter\nState: closed\nBase branch: master\nHead branch: phsauter/apb_to_reg_v2\nCreated: 2025-10-14T15:24:42Z\nUpdated: 2026-02-14T23:13:32Z\nClosed: 2025-11-20T17:25:40Z\nMerged: 2025-11-20T17:25:40Z\n\nIt is awkward to not have a converter without interfaces and leads to odd code choices elsewhere (eg https://github.com/pulp-platform/clic/blob/master/src/clic_apb.sv#L59).\r\n\r\nThis PR deprecated apb_to_reg and replaces it with apb_to_reg_v2. Note that the interface only version (apt_to_reg_intf) is not changed and moved to apv_to_reg_v2.sv since this one should not be deprecated.\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/pulp-platform_register_interface_pr55", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/pulp-platform_register_interface_pr55.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/pulp-platform_register_interface_pr55", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/pulp-platform_register_interface_pr55"}
{"instance_id": "pulp-platform_riscv-dbg_pr123", "issue_text": "Besides the additional Xilinx BSCANE2 related features, commit b5d1610 introduced some new logic to allow the dmi_jtag module to be reset with TMS cycling by entering the \"TestLogicReset\" state. However, the way this is implemented in dmi_jtag_tap.sv line 205 is extremely dangerous; the generated trst_no signal is prone to glitching and actually drives asynchronous resets within dmi_jtag.sv and dmi_cdc.sv\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\nPR title: Functional Resets and Async Reset Glitch Prevention\n\nSource: https://github.com/pulp-platform/riscv-dbg/pull/123\n\nPR description:\nThis PR addresses issue #120 and introduces support for `dtmcs.dmihardreset`. The key changes separate asynchronous JTAG reset (controlled by `jtag_trst` signal) from synchronous functional resets triggered by JTAG TestLogicReset state or DTM reset CSR. The implementation uses new clearable CDC modules that synchronize clear requests across clock domains.\n\nThe author modified the DMI testbench to issue random resets during transactions and fixed a JTAG verification IP bug where `ir_select` wasn't reset during master reset.\n\nComments:\n- meggiman (author): Explained that `dmi_rst_no` clears the DMI response FIFO within `dm_top`. To maintain backward compatibility while avoiding mixing functional and power-on-reset semantics, the signal was made glitch-free and derived from the synchronized clearable CDC output. Additional fixes addressed JTAG specification compliance regarding IR reset to IDCODE in TestLogicReset.\n- andreaskurth (reviewer): Approved with suggestions for changelog corrections and variable naming consistency (`core_dmi_rst_nq` to reflect active-low polarity).\n- bluewww (collaborator): Approved with comment \"lgtm\" and previously suggested adding synchronous clear functionality to `dm_top`.\n\nLinked issue:\n- #120 \"Fatal Glitching in Internal Asynchronous Reset Generation\"\n\nStatus: Merged by bluewww on April 4, 2022.\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/pulp-platform_riscv-dbg_pr123", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/pulp-platform_riscv-dbg_pr123.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/pulp-platform_riscv-dbg_pr123", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/pulp-platform_riscv-dbg_pr123"}
{"instance_id": "pulp-platform_riscv-dbg_pr145", "issue_text": "# [dm_mem] Addressing does not take strobes into account\n\nThe read/write logic in dm_mem.sv only looks at the request address and does not take the byte strobes into account which causes problems when trying to write the Halted, Going, Resuming and Exception locations from a bus that is larger than 32 bit as that would require misaligned requests.\n\nThis is patched in #145 by realigning the relevant addresses to 64 bits.\n\n\n\n\n\n\n\n\n\n\n\nPR title: [fix] Realign addresses to 64-bit\n\nSource: https://github.com/pulp-platform/riscv-dbg/pull/145\n\nPR description:\nThe PR addresses a critical issue where the read/write logic in `dm_mem.sv` only examines the request address without considering byte strobes. This limitation causes problems when writing to Halted, Going, Resuming, and Exception locations from buses larger than 32-bit, as such operations would require misaligned requests. The fix realigns these addresses to 64 bits, enabling the Debug Module to work properly with both 32-bit and 64-bit harts.\n\nComments:\n- creinwar (Nov 1, 2022): The contributor explained the root cause and solution, linking to issue #144.\n- bluewww (Nov 2, 2022): \"I'll double check otherwise looks good. Could you also please update the documentation?\"\n- bluewww (Nov 2, 2022): Approved with comment: \"lgtm\"\n\nLinked issue:\n- #144 \"[dm_mem] Addressing does not take strobes into account\"\n\nMerge info:\n- Merged by: bluewww\n- Commits: 2 total\n- Branch deleted after merge\n- Merged Nov 2, 2022.\n\nDownstream impact: This change affected address mappings in related projects. The Exception Address was changed from `0x808` to `0x810`, which required follow-up fixes in dependent systems like the Cheshire project.\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/pulp-platform_riscv-dbg_pr145", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/pulp-platform_riscv-dbg_pr145.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/pulp-platform_riscv-dbg_pr145", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/pulp-platform_riscv-dbg_pr145"}
{"instance_id": "pulp-platform_riscv-dbg_pr155", "issue_text": "# `sberror` not clearing properly causes OpenOCD interoperability issues\n\nThe OpenTitan project uses GDB/OpenOCD to develop top-level debug and manufacturing test cases. We have noticed some test failures when performing unaligned system bus accesses (see [here](https://github.com/lowRISC/opentitan/issues/17729#issuecomment-1488923308)).\n\nIn short, when an unaligned read operation is performed, `sberror` is set to 3 (which is correct according to the spec), but after, OpenOCD tries to clear the error with a W1C, by sending 0x7, however, the `sberror` field fails to clear. We believe there is an RTL bug described [here](https://github.com/lowRISC/opentitan/issues/17729#issuecomment-1489076212).\n\nCould someone confirm / fix?\n\n\n\n\n\n\n\n\n\nPR title: dm_csrs: Fix W1C behavior of `sberror`\n\nSource: https://github.com/pulp-platform/riscv-dbg/pull/155\n\nPR description:\n\"Prior to this PR, the W1C `sberror` field of the `sbcs` CSR only got cleared when `3b'001` was written to it. When other values, e.g., `3b111`, were written, the field did not get cleared. This is a mismatch to the RISC-V External Debug Support spec, which states 'Writing 1 to every bit clears the field'.\n\nThis PR fixes that mismatch in a backwards-compatible way, i.e., now any non-zero write to `sberror`, including `3'b001`, clears it. See issue #154 for further information and discussion.\n\nThis resolves #154.\n\nThis has been tested in OpenTitan with OpenOCD connected to this debug module instantiated on an FPGA to confirm that this solves the problem described in lowRISC/opentitan#17729.\"\n\nComments:\n- timothytrippel (Mar 31, 2023): \"Thanks @andreaskurth !\"\n- bluewww (Apr 5, 2023): \"I ran the tests locally everything seems to be in order. lgtm.\"\n\nLinked issue:\n- #154 \"`sberror` not clearing properly causes OpenOCD interoperability issues\"\n\nStatus: Merged on April 5, 2023 by bluewww.\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/pulp-platform_riscv-dbg_pr155", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/pulp-platform_riscv-dbg_pr155.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/pulp-platform_riscv-dbg_pr155", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/pulp-platform_riscv-dbg_pr155"}
{"instance_id": "pulp-platform_riscv-dbg_pr169", "issue_text": "# Reset state after trst_ni is wrong\n\nThis\n\nhttps://github.com/pulp-platform/riscv-dbg/blob/358f90110220adf7a083f8b65d157e836d706236/src/dmi_jtag_tap.sv#L306\n\nshould reset the TAP to the `Test-Logic-Reset` state.\n\nSee `4.6.1 Specifications` in `IEEE Standard for Test Access Port and Boundary-Scan Architecture 11491-2013`. @msfschaffner does that sound correct to you too?\n\n\n\n\n\n\n\nPR title: src: Fix wrong reset state for TAP after trst_ni\n\nSource: https://github.com/pulp-platform/riscv-dbg/pull/169\n\nPR description:\nThe PR addresses a bug where the TAP (Test Access Port) reset state was incorrect after `trst_ni` assertion. According to the author: \"This problem was didn't become visible as most/all drivers always run the software reset sequence as trst_ni is an optional signal.\"\n\nLinked issue:\n- #165 \"Reset state after trst_ni is wrong\"\n\nActivity:\nThe fix was subsequently applied upstream by Andreas Kurth in the OpenTitan project (July 15, 2024), which also reverted two related commits that had replicated the same problem in their DV (design verification) code.\n\nKey details:\n- Author: bluewww\n- Status: Merged\n- Merge date: July 8, 2024\n- Commits: 1 commit merged\n- Changes: Corrects the reset value of `tap_state_q`\n- Impact: Fixes edge cases where `trst_ni` is used without software reset sequences\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/pulp-platform_riscv-dbg_pr169", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/pulp-platform_riscv-dbg_pr169.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/pulp-platform_riscv-dbg_pr169", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/pulp-platform_riscv-dbg_pr169"}
{"instance_id": "pulp-platform_riscv-dbg_pr53", "issue_text": "# Add Continuous Integration\n\n* `riscv-tests/debug` + RI5CY testbench for gdb end to end testing\n* `openocd-compliance`\n\n\n\n\n\n\n\n\n\n\n\n\nPR title: Add tb running dm+ri5cy through OpenOCD compliance tests\n\nSource: https://github.com/pulp-platform/riscv-dbg/pull/53\n\nPR description:\nThe contributor implemented a testbench that runs the DM (Debug Module) alongside the RI5CY processor. A JTAG DPI bridge enables OpenOCD to interact with the simulation. The PR includes `ci/veri-run-openocd-compliance.sh`, a script that orchestrates the OpenOCD process with Verilator simulation and validates results by examining the OpenOCD log output. This work resolves issue #40 regarding continuous integration.\n\nCommits:\n1. Add tb running dm+ri5cy through OpenOCD compliance tests\n2. Update CHANGELOG.md\n3. Add CI badge to README.md\n4. Simplify cross compilation step\n\nKey details:\n- Author: bluewww\n- Status: Merged\n- Date: March 19, 2020\n- Branch: add-tb-and-ci -> master\n- 4 commits merged into master\n- The PR introduces testing infrastructure for compliance validation\n- No reviews were recorded; the author self-approved and merged\n- The branch was deleted post-merge\n- Related to PR #54 (\"Make second scratch register optional\")\n\nLinked issue:\n- #40 (resolved by this PR; \"Add Continuous Integration\")\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/pulp-platform_riscv-dbg_pr53", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/pulp-platform_riscv-dbg_pr53.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/pulp-platform_riscv-dbg_pr53", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/pulp-platform_riscv-dbg_pr53"}
{"instance_id": "pulp-platform_riscv-dbg_pr56", "issue_text": "# loop bounds incorrect in dm_csrc.sv (line 126)\n\nHi guys,\r\n\r\nthere seems to be a bug in dm_csrs.sv (master branch, https://github.com/pulp-platform/riscv-dbg/blob/master/src/dm_csrs.sv) line 126:\r\n\r\n```\r\nfor (int unsigned k = 0; k < NrHarts/2**5+1; k++) begin\r\n      halted_flat1[k] = |halted_reshaped0[k];\r\nend\r\n```\r\n\r\nThe array halted_reshaped0 is defined as:\r\n\r\n```\r\nlogic [(NrHarts-1)/2**5:0][31:0] halted_reshaped0;\r\n```\r\n\r\nTherefore, the loop above will access elements which are non-existing because the loop accesses elements above (NrHarts-1)/2**5+1.\r\n\r\nThe code should look imho as follows:\r\n\r\n```\r\nfor (int unsigned k = 0; k < (NrHarts-1)/2**5+1; k++) begin\r\n      halted_flat1[k] = |halted_reshaped0[k];\r\nend\r\n```\r\n\r\nBR, Dustin\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/pulp-platform_riscv-dbg_pr56", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/pulp-platform_riscv-dbg_pr56.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/pulp-platform_riscv-dbg_pr56", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/pulp-platform_riscv-dbg_pr56"}
{"instance_id": "pulp-platform_riscv-dbg_pr70", "issue_text": "# _be is stuck to 0 while reading\n\nShouldn't we have the same code as for the Write case regarding _be ?\n\n\n\n\n\n\n\n\n\n\n\n\n\nPR title: Fix for SBA 'be' when reading (fixes #22).\n\nSource: https://github.com/pulp-platform/riscv-dbg/pull/70\n\nPR description:\nThis pull request addresses issue #22, which concerns the SBA (System Bus Access) byte enable signal remaining stuck at 0 during read operations. The contributor notes that a previous branch had attempted to resolve this through logic duplication but was never merged.\n\nComments:\n- jm4rtin (July 1, 2020): \"Fixes #22...It looks like you have a branch that addressed this with a copy & paste of the combinatorial logic but it never got merged in.\"\n- bluewww (July 3, 2020): \"I want to make this a parameter, so that we stay compatible with the current way we do it.\"\n- jm4rtin (July 17, 2020): Asked about naming preferences for the parameter, proposing \"_ReadByteEnable=1_\" to default to new behavior.\n- bluewww (July 23, 2020): Requested a CHANGELOG.md entry before approval.\n- jm4rtin (July 23, 2020): Added the changelog entry; bluewww subsequently approved with \"lgtm.\"\n\nLinked issue:\n- #22 \"_be is stuck to 0 while reading\"\n\nStatus: Merged on July 23, 2020. The PR contained 4 commits introducing the `ReadByteEnable` parameter and correcting the `be_mask` signal logic.\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/pulp-platform_riscv-dbg_pr70", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/pulp-platform_riscv-dbg_pr70.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/pulp-platform_riscv-dbg_pr70", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/pulp-platform_riscv-dbg_pr70"}
{"instance_id": "pulp-platform_riscv-dbg_pr79", "issue_text": "# cmderr=0 when accessing data0 while busy\n\nHi,\n\nas you can see from the attached waveform\n![Screenshot from 2019-09-13 13-36-42](https://user-images.githubusercontent.com/25659164/66300764-2d3bbf80-e8f6-11e9-9490-5413a682afdf.png)\nthere is an attemped data write while the previous command (another data write) was still ongoing, and there is no cmderr flagging the conflict as per specs (paragraph 3.1211)\n`Accessing these registers while an abstract command is executing causes cmderr to be set to 1 (busy) if it is 0.`\n\n\n\n\n\n\n\n\nPR title: return CmdErrBusy if accessing data or progbuf while command was executing\n\nSource: https://github.com/pulp-platform/riscv-dbg/pull/79\n\nPR description:\nThis PR addresses a compliance issue with the RISC-V Debug Specification (section 3.12.6). The implementation was incomplete - it only blocked writes and autoexec operations during command execution but failed to set the error flag.\n\nComments:\n- noytzach (Author, Sep 10, 2020): According to the spec, \"an abstract command was executing while command, abstractcs, or abstractauto was written, or when one of the data or progbuf registers was read or written.\" The current code only prevented writes but didn't return the proper error code.\n- Silabs-ArjanB (Oct 15, 2020): Noted an additional specification requirement: \"This status is only written if cmderr contains 0.\" Suggested modifying the implementation to only set CmdErrBusy when no previous error exists, preventing error overwriting.\n- noytzach (Oct 27, 2020): Accepted the suggestion and implemented the correction in commit 0a54bd7.\n- bluewww (Nov 6, 2020): Approved the changes with \"lgtm, thanks for the patch\" and merged the PR.\n\nLinked issue:\n- Closes #37 \"cmderr=0 when accessing data0 while busy\"\n\nStatus: Merged on Nov 6, 2020.\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/pulp-platform_riscv-dbg_pr79", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/pulp-platform_riscv-dbg_pr79.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/pulp-platform_riscv-dbg_pr79", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/pulp-platform_riscv-dbg_pr79"}
{"instance_id": "pulp-platform_riscv-dbg_pr89", "issue_text": "# \"dmireset\" seems sticky and needs to be cleared afterwards\n\ndtmcs.dmireset is W1 in the spec.\n\nIn the design It seems that when it is set to 1, then it stays 1 until cleared by writing to dtmcs again. As per spec, dmireset should be a pulse that is used to clear the sticky error state.\n\n\n\n\n\n\n\n\n\n\n\nPR title: Fix for issue #77 and #88\n\nSource: https://github.com/pulp-platform/riscv-dbg/pull/89\n\nPR description:\nThe pull request addresses two related issues in the riscv-dbg repository. According to the commit message: \"Fix for issue #77 and #88\" with sign-off from Arjan Bink.\n\nComments:\n- Silabs-ArjanB (October 12, 2020): Opened the PR with the message \"Fix for #77 and #88\"\n- Silabs-ArjanB (October 13, 2020): Requested CI to be restarted, noting \"the failure is not due to the commit\"\n- bluewww (October 26, 2020): Approved with \"LGTM\" and subsequently merged the changes\n\nLinked issues:\n- #77 \"'dmireset' seems sticky and needs to be cleared afterwards\"\n- #88 \"dmireset can be accidentally triggered\"\n\nBoth issues were closed upon merging this PR.\n\nStatus: Merged October 26, 2020. Author: Silabs-ArjanB. Reviewer/Merger: bluewww.\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/pulp-platform_riscv-dbg_pr89", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/pulp-platform_riscv-dbg_pr89.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/pulp-platform_riscv-dbg_pr89", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/pulp-platform_riscv-dbg_pr89"}
{"instance_id": "pulp-platform_riscv-dbg_pr90", "issue_text": "# abstract cmd error? or a typo?  when two dscratch implemented\n\nHi sir, I find there may be wrong in the code below:\r\n1. the comment is  \"store a0 in dscratch1\" while used the \"dm::csrr\" which means that read a csr(dscratch1) and store it into a0.  so the code or comment maybe wrong here!\r\nhttps://github.com/pulp-platform/riscv-dbg/blob/3670267ab150f5a95e773bc18b1814e4031dc508/src/dm_mem.sv#L357\r\n2. the senario in which can execute a abstract cmd is executing this sequence : \"_entry\" , \"going\", \"whereto\" and going into abstract cmd.  codes can be expanded bellow (assume dscratch1 implemented ):\r\n\r\n_entry:\r\n....\r\ngoing:\r\n#ifdef SND_SCRATCH\r\n        sw zero, GOING(a0)          // When debug module sees this write, the GO flag is reset.\r\n        **csrr a0, CSR_DSCRATCH1      // Restore a0 here**  **_where CSR_DSCRATCH1 contains the original value of a0_**\r\n#else\r\n        sw zero, GOING(zero)          // When debug module sees this write, the GO flag is reset.\r\n#endif\r\n        csrr s0, CSR_DSCRATCH0      // Restore s0 here\r\n        jal zero, whereto\r\n\r\n// store a0 in dscratch1 \r\ndm::csrr(dm::CSR_DSCRATCH1, 5'd10)   **@AbstractCmdBaseAddr the first instruction**\r\nhere the values of CSR_DSCRATCH1 and a0 are the same (see the csrr a0, .. above)\r\nso why should we move data between CSR_DSCRATCH1 & a0 when thay already the same?\r\nso I think here no csr instruction is needed at all,   what do you think?\r\n......\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/pulp-platform_riscv-dbg_pr90", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/pulp-platform_riscv-dbg_pr90.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/pulp-platform_riscv-dbg_pr90", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/pulp-platform_riscv-dbg_pr90"}
{"instance_id": "pulp-platform_riscv-dbg_pr93", "issue_text": "# sba bursts in verilator simulation\n\nThis concerns commit f9cf9c4.  The attached screenshot, of a verilator simulation, shows a dmi request for an sba burst: the sbcs word, the address, and then the sequence of data words. Underneath is the debug module's master traffic.  Note that address 0xC0000004 gets the data which in the dmi request corresponds to 0xC0000018.  The intervening data items have been dropped.  (No doubt this problem would not occur with an FPGA emulation, where the dut would be running relatively much faster.)\n\nWould it be possible to defer asserting ```dmi_resp_valid_o``` until ```master_r_valid_i``` has been asserted?\n\n\n![Screenshot from 2020-09-30 17-42-53](https://user-images.githubusercontent.com/10117421/94743718-dec4d380-0345-11eb-932e-c14b8647a173.png)\n\n\n\n\n\n\n\n\nPR title: Fix for #81 and #91\n\nSource: https://github.com/pulp-platform/riscv-dbg/pull/93\n\nPR description:\nThis PR addresses two related system bus issues:\n- sba bursts in verilator simulation (#81)\n- Read of SBAddress0/1 can trigger SBBUSYERROR (#91)\n\nSigned-off-by: Arjan Bink <Arjan.Bink@silabs.com>\n\nComments:\n- Silabs-ArjanB (Contributor, Oct 19): Referenced the two issues being fixed, noting these address \"sbbusy related issues.\"\n- bluewww (Collaborator, Oct 19): Acknowledged receipt of bug fixes and indicated plans for manual review due to CI issues. Suggested that \"ideally we would also add simple testcases for each bug fix.\"\n- Silabs-ArjanB (Oct 19): Inquired about an alternative approach mentioned in PR #27 regarding tying datacount based on BusWidth configuration.\n- bluewww (Oct 26): Questioned the removal of `sbcs_d.sbbusyerror` setting during SBAddressX writes, citing RISC-V debug spec section 3.12.20 regarding required behavior when the system bus master is busy.\n- Silabs-ArjanB (Oct 26): Clarified that the change only affected reads, not writes, aligning with specification requirements.\n- bluewww (Approved Oct 26): Confirmed approval: \"Thanks you are right, I didn't look at the correct section. LGTM.\"\n\nLinked issues:\n- #81 \"sba bursts in verilator simulation\"\n- #91 \"Read of SBAddress0/1 can trigger SBBUSYERROR\"\n\nStatus: Merged Oct 26, 2020.\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/pulp-platform_riscv-dbg_pr93", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/pulp-platform_riscv-dbg_pr93.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/pulp-platform_riscv-dbg_pr93", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/pulp-platform_riscv-dbg_pr93"}
{"instance_id": "pulp-platform_snitch_pr259", "issue_text": "# AXI-Lite Master port for SBA\n\n\n\n\n\n\n\n\n\n\n\n\n\n\nPR title: occamy: Create AXI Lite to AXI connection\n\nSource: https://github.com/pulp-platform/snitch/pull/259\n\nPR description:\nThe PR references issue #257 without including additional descriptive text in the pull request body.\n\nComments:\n- niwis (Approved Sep 17, 2021): \"LGTM! Cool that SBAs work :-)\"\n- paulsc96 (Approved & Merged Sep 20, 2021): \"SBA works as advertised in simulation. good to go for me.\"\n\nLinked issue:\n- #257 \"AXI-Lite Master port for SBA\"\n\nThis pull request successfully closed issue #257 upon merging.\n\nStatus: Merged Sep 20, 2021. Author: zarubaf. Reviewers: niwis, paulsc96.\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/pulp-platform_snitch_pr259", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/pulp-platform_snitch_pr259.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/pulp-platform_snitch_pr259", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/pulp-platform_snitch_pr259"}
{"instance_id": "pulp-platform_snitch_pr388", "issue_text": "# SPI Host: FSM Bug CSAAT\n\nThe OpenTitan SPI host FSM contains a bug as it uses the `command_i.segment.csaat` signal instead of the latched `csaat_q` from the command that is currently being executed to decide how the chip select will be handled.\r\n\r\nSee [OpenTitans Fix](https://github.com/lowRISC/opentitan/commit/6c7ce7683b3a1ad82496db7cfd67f174164b6502)\r\n\r\nPatch to rectify the problem:\r\n```diff\r\ndiff --git a/hw/vendor/lowrisc_opentitan/spi_host/rtl/spi_host_fsm.sv b/hw/vendor/lowrisc_opentitan/spi_host/rtl/spi_host_fsm.sv\r\nindex 4fb1360d..e50d0e7e 100644\r\n--- a/hw/vendor/lowrisc_opentitan/spi_host/rtl/spi_host_fsm.sv\r\n+++ b/hw/vendor/lowrisc_opentitan/spi_host/rtl/spi_host_fsm.sv\r\n@@ -250,7 +250,7 @@ module spi_host_fsm\r\n           // and of CSAAT is asserted, the details of the subsequent command.\r\n           if (!last_bit || !last_byte) begin\r\n             prestall_st_d = InternalClkLow;\r\n-          end else if (!command_i.segment.csaat) begin\r\n+          end else if (!csaat_q) begin\r\n             prestall_st_d = WaitTrail;\r\n           end else if (!command_valid_i) begin\r\n             prestall_st_d = IdleCSBActive;\r\n```\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/pulp-platform_snitch_pr388", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/pulp-platform_snitch_pr388.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/pulp-platform_snitch_pr388", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/pulp-platform_snitch_pr388"}
{"instance_id": "pulp-platform_snitch_pr394", "issue_text": "# SPI Host: FSM Bug CSID Switch\n\nThe OpenTitan SPI host FSM contains a bug as it jumps to the WaitIdle state after receiving a command with a different CSID as the previous command. It therefore basically always skips the first command after a CSID change which this patch rectifies ([OpenTitan does it the same way](https://github.com/lowRISC/opentitan/blob/master/hw/ip/spi_host/rtl/spi_host_fsm.sv#L284)).\r\n\r\n```diff\r\ndiff --git a/hw/vendor/lowrisc_opentitan/spi_host/rtl/spi_host_fsm.sv b/hw/vendor/lowrisc_opentitan/spi_host/rtl/spi_host_fsm.sv\r\nindex 4fb1360d..babb6138 100644\r\n--- a/hw/vendor/lowrisc_opentitan/spi_host/rtl/spi_host_fsm.sv\r\n+++ b/hw/vendor/lowrisc_opentitan/spi_host/rtl/spi_host_fsm.sv\r\n@@ -290,7 +290,7 @@ module spi_host_fsm\r\n           if (idle_cntr_q == 4'h0) begin\r\n             prestall_st_d = WaitLead;\r\n           end else begin\r\n-            prestall_st_d = WaitIdle;\r\n+            prestall_st_d = CSBSwitch;\r\n           end\r\n         end\r\n         IdleCSBActive: begin\r\n```\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/pulp-platform_snitch_pr394", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/pulp-platform_snitch_pr394.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/pulp-platform_snitch_pr394", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/pulp-platform_snitch_pr394"}
{"instance_id": "pulp-platform_snitch_pr436", "issue_text": "# Occamy on FPGA - \"axi_flat.svh\" header file is missing on the repo\n\nThank you for your proving us Occamy source code.\r\nI tried to create Occamy FPGA code, based on your Occamy instruction on the repo. \r\n--> make occamy_vcu128\r\n\r\nThe following error message will be reported.\r\n\r\nERROR: [Synth 8-1766] cannot open include file axi_flat.svh [/home/nam/codeSim/project/snitch/hw/system/occamy/src/occamy_xilinx.sv:9]\r\nERROR: [Synth 8-2841] use of undefined macro AXI_FLATTEN_MASTER [/home/nam/codeSim/project/snitch/hw/system/occamy/src/occamy_xilinx.sv:525]\r\n\r\nI think \"occamy_xilinx.sv\" must include \"axi_flat.svh\" header file.\r\nBut, we can't find the header file on the Github repo. \r\nI think uploading of the header file was missed. \r\n\r\nIt would be very grateful to you if you upload \"axi_flat.svh\" header file on this repo.\r\nThank you.\r\n\r\nSeungseok\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/pulp-platform_snitch_pr436", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/pulp-platform_snitch_pr436.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/pulp-platform_snitch_pr436", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/pulp-platform_snitch_pr436"}
{"instance_id": "pulp-platform_tech_cells_generic_pr17", "issue_text": "# `tc_sram`: Add implementation key and IO\n\nInstance: pulp-platform_tech_cells_generic_pr17\nSource: https://github.com/pulp-platform/tech_cells_generic/pull/17\nFetched: 2026-04-26\nRepository: pulp-platform/tech_cells_generic\nPull request: #17\nAuthor: paulsc96\nState: closed\nBase branch: master\nHead branch: feature/tc_sram_impl\nCreated: 2021-10-08T14:56:31Z\nUpdated: 2022-10-25T16:30:43Z\nClosed: 2022-10-25T16:30:43Z\nMerged: 2022-10-25T16:30:43Z\n\nThis PR\r\n\r\n* Adds a metadata string parameter `ImplKey` to `tc_sram`, which serves as a key to identify a specific memory type. Together with an external description of the desired implementation for each key (e.g. macro type), this enables generating `tc_sram` implementation wrappers without having to identify memories by their parameters like width and depth.\r\n* Adds a wrapper `tc_sram_impl` around `tc_sram` with parametric implementation IO (`impl_i` and `impl_o`). This allows setting pseudo-static implementation-specific inputs (e.g. macro configuration) or reading implementation-specific outputs (e.g. physical sensor feedback, interrupts). Importantly, the behavioral model ignores `impl_i` and drives `impl_o` with a static, parameterizable value.\r\n\r\nThe addition of `ImplKey` is a first step towards addressing #14.\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/pulp-platform_tech_cells_generic_pr17", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/pulp-platform_tech_cells_generic_pr17.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/pulp-platform_tech_cells_generic_pr17", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/pulp-platform_tech_cells_generic_pr17"}
{"instance_id": "pulp-platform_tech_cells_generic_pr22", "issue_text": "# Add optional parameter to tc_clk_gating to flag functional gates\n\nInstance: pulp-platform_tech_cells_generic_pr22\nSource: https://github.com/pulp-platform/tech_cells_generic/pull/22\nFetched: 2026-04-26\nRepository: pulp-platform/tech_cells_generic\nPull request: #22\nAuthor: meggiman\nState: closed\nBase branch: master\nHead branch: functional_clk_gate_flagging\nCreated: 2022-03-17T13:15:38Z\nUpdated: 2022-03-17T13:51:27Z\nClosed: 2022-03-17T13:29:49Z\nMerged: 2022-03-17T13:29:49Z\n\nFor certain target platforms clock gating cells are not available or should be used very sparsingly (e.g. many FPGAs have very limited amounts of global clock buffer cells available for that purposes). For these cases it is important to distinguish between functional clock gates that are required for functional correctness of the design (e.g. in clock dividers or in peripherals) or if the clock gate is only used for hierarchical clock gating for power saving purposes. For clock gating resource limited targets, the later (non-functional clock gates) can be safely replaced with a simple feedthrough without affecting functionality. \r\n\r\nThis PR adds an optional parameter to the tc_clk_gating cell for designer to flag, wether a particular CG instance is functionally required or not. Target specific implementations of the generic tc_clk_gating module might then opt to use dedicated ICGs for functional clock gates while removing the not-strictly required ones.\r\n\r\nThe default value is 1'b1 which means the clock gate is functional. That way the change is backward compatible because by default we assume, that all tc_clk_gating instances in old designs are functionally required unless someone modifies the instantiations to mark them otherwise.\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/pulp-platform_tech_cells_generic_pr22", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/pulp-platform_tech_cells_generic_pr22.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/pulp-platform_tech_cells_generic_pr22", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/pulp-platform_tech_cells_generic_pr22"}
{"instance_id": "pulp-platform_tech_cells_generic_pr26", "issue_text": "# Add IS_FUNCTIONAL parameter to tc_clk_gating in tc_clk_xilinx.sv\n\nInstance: pulp-platform_tech_cells_generic_pr26\nSource: https://github.com/pulp-platform/tech_cells_generic/pull/26\nFetched: 2026-04-26\nRepository: pulp-platform/tech_cells_generic\nPull request: #26\nAuthor: creinwar\nState: closed\nBase branch: master\nHead branch: fix/tc_clk_xilinx_is_functional\nCreated: 2022-11-02T15:48:42Z\nUpdated: 2022-11-03T10:50:38Z\nClosed: 2022-11-02T20:12:37Z\nMerged: 2022-11-02T20:12:37Z\n\nPR title: Add IS_FUNCTIONAL parameter to tc_clk_gating in tc_clk_xilinx.sv\n\nPR description:\nNo description was provided with this pull request.\n\nComments:\n- niwis (Collaborator) - Approval comment: \"Thanks!\"\n\nKey details:\n- Commits: 1 commit (21abc77)\n- Requested reviewer: paulsc96 (awaiting review)\n- Branch: fix/tc_clk_xilinx_is_functional -> master\n- Merge commit: 325ece6\n\nThe pull request was successfully merged despite the requested reviewer not having provided feedback. The contributing branch was deleted after merging on November 3, 2022.\n\nLinked issues: None.\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/pulp-platform_tech_cells_generic_pr26", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/pulp-platform_tech_cells_generic_pr26.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/pulp-platform_tech_cells_generic_pr26", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/pulp-platform_tech_cells_generic_pr26"}
{"instance_id": "pulp-platform_tech_cells_generic_pr27", "issue_text": "# Add tc_clk_or2 And Add Warning About tc_clk_mux2 Usage\n\nInstance: pulp-platform_tech_cells_generic_pr27\nSource: https://github.com/pulp-platform/tech_cells_generic/pull/27\nFetched: 2026-04-26\nRepository: pulp-platform/tech_cells_generic\nPull request: #27\nAuthor: meggiman\nState: closed\nBase branch: master\nHead branch: add_clk_OR2\nCreated: 2022-12-11T11:31:43Z\nUpdated: 2022-12-12T10:26:20Z\nClosed: 2022-12-12T10:26:19Z\nMerged: 2022-12-12T10:26:19Z\n\nPR title: Add tc_clk_or2 And Add Warning About tc_clk_mux2 Usage\n\nPR description:\n\"This PR adds a new generic clock gate cell (OR-gate) to the `tc_clk.sv` cell family. Furthermore, I added a warning about the limitations of the `tc_clk_mux2` cell in common standard cell libraries. They are not glitch-free and must not be used for dynamic switching between two clocks without any additional precautionary steps.\"\n\nComments:\n- meggiman (Author, Dec 11, 2022): Explained that the PR adds a new generic clock gate cell and a cautionary warning about the `tc_clk_mux2` cell's limitations in standard cell libraries.\n- niwis (Reviewer/Maintainer, Dec 12, 2022): Approved with the comment \"Thanks a lot @meggiman, LGTM\" and merged the changes.\n\nCommits:\n- Add clk OR cell (b970419)\n- Add usage warning to clock mux cell (7a0f09d)\n- Update changelog (ef99266)\n\nLinked issues: None.\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/pulp-platform_tech_cells_generic_pr27", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/pulp-platform_tech_cells_generic_pr27.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/pulp-platform_tech_cells_generic_pr27", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/pulp-platform_tech_cells_generic_pr27"}
{"instance_id": "pulp-platform_tech_cells_generic_pr29", "issue_text": "# tc_sram_xilinx: Support ByteWidth != 8\n\nInstance: pulp-platform_tech_cells_generic_pr29\nSource: https://github.com/pulp-platform/tech_cells_generic/pull/29\nFetched: 2026-04-26\nRepository: pulp-platform/tech_cells_generic\nPull request: #29\nAuthor: niwis\nState: closed\nBase branch: master\nHead branch: xilinx-unpack\nCreated: 2023-08-11T20:00:55Z\nUpdated: 2023-08-11T22:06:28Z\nClosed: 2023-08-11T22:06:24Z\nMerged: 2023-08-11T22:06:24Z\n\nSupport ByteWidths != 8. To achieve this,\r\n- 8-bit-align the input bytes,\r\n- fan out be_i if ByteWidth > 8.\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/pulp-platform_tech_cells_generic_pr29", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/pulp-platform_tech_cells_generic_pr29.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/pulp-platform_tech_cells_generic_pr29", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/pulp-platform_tech_cells_generic_pr29"}
{"instance_id": "pulp-platform_tech_cells_generic_pr30", "issue_text": "# tc_sram_xilinx writes only the first byte\n\nThe signal `be_al` and `we_al` being only one bit wide only the first byte of a word is written on FPGA. See fix proposed in PR https://github.com/pulp-platform/tech_cells_generic/pull/30\n\n\n\n\n\n\n\n\n\n\n\n\n\n\nPR title: tc_sram_xilinx: Re-align be_al signal\n\nPR description:\n\"The be_al signal is only one bit wide which causes to write only the first byte of the dataword on the safety island on Carfield FPGA.\" The PR proposed a fix that was undergoing testing on the Carfield hardware platform.\n\nComments:\n- CyrilKoe (Sep 12, 2023): Opened the PR and requested review from niwis.\n- CyrilKoe (Sep 13, 2023): Reported successful testing results: \"Tested on Carfield safety-island, seems to work\"\n- niwis (Sep 14, 2023): Approved with the comment: \"Excellent, thanks a lot!\"\n- niwis (Sep 14, 2023): Merged the PR into the master branch.\n\nLinked issue:\n- Issue #31: \"tc_sram_xilinx writes only the first byte\" - successfully closed by this merge.\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/pulp-platform_tech_cells_generic_pr30", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/pulp-platform_tech_cells_generic_pr30.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/pulp-platform_tech_cells_generic_pr30", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/pulp-platform_tech_cells_generic_pr30"}
{"instance_id": "pulp-platform_udma_i2s_pr5", "issue_text": "# `comb_data` missing drivers\n\n- Source URL: https://github.com/pulp-platform/udma_i2s/issues/4\n\n```\r\nIn a recent tape-out we came across an issue that ended up manifesting itself under\r\n  soc_domain_i/\r\n    pulp_soc_i/\r\n      soc_peripherals_i/\r\n        i_udma/\r\n          i_i2s_udma/\r\n            i_i2s_txrx/\r\n              i_pdm/\r\n                i_varcic\r\n\r\nSpecifically the signal “comb_data” that connects a series of instances\r\n\r\n  cic_integrator_WIDTH51\r\n  cic_comb_WIDTH51\r\n\r\nends up without drivers.\r\n```\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/pulp-platform_udma_i2s_pr5", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/pulp-platform_udma_i2s_pr5.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/pulp-platform_udma_i2s_pr5", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/pulp-platform_udma_i2s_pr5"}
{"instance_id": "rggen_rggen-sv-rtl_pr10", "issue_text": "# Hierarchical lookup error on Xcelium simulator\n\n- Source URL: https://github.com/rggen/rggen-sv-rtl/issues/9\n\nXcelium cannot find the `'at_clock_edge` identifier. Need workaround.\n\n```\n    if (!backdoor_cb.at_clock_edge.triggered) begin\n                                           |\nxmelab: *E,CUVUNF (/home/kazt81/work/rggen-sample-testbench/rtl/rggen-sv-rtl/rggen_backdoor_if.sv,66|43): Hierarchical name component lookup failed for 'at_clock_edge' at 'top.u_block_0.g_register_9.g[0].u_register.u_register_common.u_backdoor.backdoor_if'.\n```\n\nrefs: https://github.com/taichi-ishitani/tvip-axi/pull/31#issuecomment-944423227\n\n\n\nPR title: add workaround for Xcelium simulator\n\nSource: https://github.com/rggen/rggen-sv-rtl/pull/10\n\nPR description:\nThe PR addresses issue #9 by implementing a workaround for the Xcelium simulator. The commit message indicates it resolves an \"unexpected hierarchical lookup error\" reported by the Xcelium simulator.\n\nComments:\n- taichi-ishitani: \"Add workaround for Xcelium simulator to fix #9\"\n\nThe pull request was successfully merged with one commit and had no reviews or assigned reviewers at the time of closure.\n\nLinked issue:\n- #9 \"Hierarchical lookup error on Xcelium simulator\"\n\nStatus: Merged October 25, 2021. Author: taichi-ishitani. Branch: fix_9 -> master. Commit: 985282031d9c86a17dd786deff439c2f76fb328b.\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/rggen_rggen-sv-rtl_pr10", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/rggen_rggen-sv-rtl_pr10.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/rggen_rggen-sv-rtl_pr10", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/rggen_rggen-sv-rtl_pr10"}
{"instance_id": "rggen_rggen-sv-rtl_pr4", "issue_text": "# Quartus support\n\n- Source URL: https://github.com/rggen/rggen-sv-rtl/issues/3\n\nInfo: *******************************************************************\r\nInfo: Running Quartus Prime Analysis & Elaboration\r\n\tInfo: Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition\r\n\tInfo: Processing started: Thu Feb  6 01:30:53 2020\r\nInfo: Command: quartus_map --read_settings_files=on --write_settings_files=off block_0 -c block_0 --analysis_and_elaboration\r\nWarning (18236): Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.\r\nInfo (20030): Parallel compilation is enabled and will use 2 of the 2 processors detected\r\nInfo (12021): Found 1 design units, including 0 entities, in source file /home/cra2ypierr0t/rggen-sv-rtl/rggen_rtl_pkg.sv\r\n\tInfo (12022): Found design unit 1: rggen_rtl_pkg (SystemVerilog)\r\nInfo (12021): Found 1 design units, including 1 entities, in source file /home/cra2ypierr0t/rggen-sv-rtl/rggen_register_if.sv\r\n\tInfo (12023): Found entity 1: rggen_register_if\r\nInfo (12021): Found 1 design units, including 1 entities, in source file /home/cra2ypierr0t/rggen-sv-rtl/rggen_register_common.sv\r\n\tInfo (12023): Found entity 1: rggen_register_common\r\nInfo (12021): Found 1 design units, including 1 entities, in source file /home/cra2ypierr0t/rggen-sv-rtl/rggen_mux.sv\r\n\tInfo (12023): Found entity 1: rggen_mux\r\nInfo (12021): Found 1 design units, including 1 entities, in source file /home/cra2ypierr0t/rggen-sv-rtl/rggen_indirect_register.sv\r\n\tInfo (12023): Found entity 1: rggen_indirect_register\r\nInfo (12021): Found 1 design units, including 1 entities, in source file /home/cra2ypierr0t/rggen-sv-rtl/rggen_external_register.sv\r\n\tInfo (12023): Found entity 1: rggen_external_register\r\nInfo (12021): Found 1 design units, including 1 entities, in source file /home/cra2ypierr0t/rggen-sv-rtl/rggen_default_register.sv\r\n\tInfo (12023): Found entity 1: rggen_default_register\r\nInfo (12021): Found 1 design units, including 1 entities, in source file /home/cra2ypierr0t/rggen-sv-rtl/rggen_bus_if.sv\r\n\tInfo (12023): Found entity 1: rggen_bus_if\r\nInfo (12021): Found 1 design units, including 1 entities, in source file /home/cra2ypierr0t/rggen-sv-rtl/rggen_bit_field_w01trg.sv\r\n\tInfo (12023): Found entity 1: rggen_bit_field_w01trg\r\nInfo (12021): Found 1 design units, including 1 entities, in source file /home/cra2ypierr0t/rggen-sv-rtl/rggen_bit_field_w01src.sv\r\n\tInfo (12023): Found entity 1: rggen_bit_field_w01src\r\nInfo (12021): Found 1 design units, including 1 entities, in source file /home/cra2ypierr0t/rggen-sv-rtl/rggen_bit_field_w01s.sv\r\n\tInfo (12023): Found entity 1: rggen_bit_field_w01s\r\nInfo (12021): Found 1 design units, including 1 entities, in source file /home/cra2ypierr0t/rggen-sv-rtl/rggen_bit_field_w01crs.sv\r\n\tInfo (12023): Found entity 1: rggen_bit_field_w01crs\r\nInfo (12021): Found 1 design units, including 1 entities, in source file /home/cra2ypierr0t/rggen-sv-rtl/rggen_bit_field_w01c.sv\r\n\tInfo (12023): Found entity 1: rggen_bit_field_w01c\r\nInfo (12021): Found 1 design units, including 1 entities, in source file /home/cra2ypierr0t/rggen-sv-rtl/rggen_bit_field_rws.sv\r\n\tInfo (12023): Found entity 1: rggen_bit_field_rws\r\nInfo (12021): Found 1 design units, including 1 entities, in source file /home/cra2ypierr0t/rggen-sv-rtl/rggen_bit_field_rwl.sv\r\n\tInfo (12023): Found entity 1: rggen_bit_field_rwl\r\nInfo (12021): Found 1 design units, including 1 entities, in source file /home/cra2ypierr0t/rggen-sv-rtl/rggen_bit_field_rwe.sv\r\n\tInfo (12023): Found entity 1: rggen_bit_field_rwe\r\nInfo (12021): Found 1 design units, including 1 entities, in source file /home/cra2ypierr0t/rggen-sv-rtl/rggen_bit_field_rwc.sv\r\n\tInfo (12023): Found entity 1: rggen_bit_field_rwc\r\nInfo (12021): Found 1 design units, including 1 entities, in source file /home/cra2ypierr0t/rggen-sv-rtl/rggen_bit_field_rw_wo.sv\r\n\tInfo (12023): Found entity 1: rggen_bit_field_rw_wo\r\nInfo (12021): Found 1 design units, including 1 entities, in source file /home/cra2ypierr0t/rggen-sv-rtl/rggen_bit_field_rs.sv\r\n\tInfo (12023): Found entity 1: rggen_bit_field_rs\r\nInfo (12021): Found 1 design units, including 1 entities, in source file /home/cra2ypierr0t/rggen-sv-rtl/rggen_bit_field_ro.sv\r\n\tInfo (12023): Found entity 1: rggen_bit_field_ro\r\nInfo (12021): Found 1 design units, including 1 entities, in source file /home/cra2ypierr0t/rggen-sv-rtl/rggen_bit_field_reserved.sv\r\n\tInfo (12023): Found entity 1: rggen_bit_field_reserved\r\nInfo (12021): Found 1 design units, including 1 entities, in source file /home/cra2ypierr0t/rggen-sv-rtl/rggen_bit_field_rc.sv\r\n\tInfo (12023): Found entity 1: rggen_bit_field_rc\r\nInfo (12021): Found 1 design units, including 1 entities, in source file /home/cra2ypierr0t/rggen-sv-rtl/rggen_bit_field_if.sv\r\n\tInfo (12023): Found entity 1: rggen_bit_field_if\r\nInfo (12021): Found 0 design units, including 0 entities, in source file /home/cra2ypierr0t/rggen-sv-rtl/rggen_backdoor_pkg.sv\r\nInfo (12021): Found 0 design units, including 0 entities, in source file /home/cra2ypierr0t/rggen-sv-rtl/rggen_backdoor_if.sv\r\nInfo (12021): Found 1 design units, including 1 entities, in source file /home/cra2ypierr0t/rggen-sv-rtl/rggen_axi4lite_if.sv\r\n\tInfo (12023): Found entity 1: rggen_axi4lite_if\r\nInfo (12021): Found 1 design units, including 1 entities, in source file /home/cra2ypierr0t/rggen-sv-rtl/rggen_axi4lite_bridge.sv\r\n\tInfo (12023): Found entity 1: rggen_axi4lite_bridge\r\nInfo (12021): Found 1 design units, including 1 entities, in source file /home/cra2ypierr0t/rggen-sv-rtl/rggen_axi4lite_adapter.sv\r\n\tInfo (12023): Found entity 1: rggen_axi4lite_adapter\r\nInfo (12021): Found 1 design units, including 1 entities, in source file /home/cra2ypierr0t/rggen-sv-rtl/rggen_apb_if.sv\r\n\tInfo (12023): Found entity 1: rggen_apb_if\r\nInfo (12021): Found 1 design units, including 1 entities, in source file /home/cra2ypierr0t/rggen-sv-rtl/rggen_apb_bridge.sv\r\n\tInfo (12023): Found entity 1: rggen_apb_bridge\r\nInfo (12021): Found 1 design units, including 1 entities, in source file /home/cra2ypierr0t/rggen-sv-rtl/rggen_apb_adapter.sv\r\n\tInfo (12023): Found entity 1: rggen_apb_adapter\r\nInfo (12021): Found 1 design units, including 1 entities, in source file /home/cra2ypierr0t/rggen-sv-rtl/rggen_address_decoder.sv\r\n\tInfo (12023): Found entity 1: rggen_address_decoder\r\nInfo (12021): Found 1 design units, including 1 entities, in source file /home/cra2ypierr0t/rggen-sv-rtl/rggen_adapter_common.sv\r\n\tInfo (12023): Found entity 1: rggen_adapter_common\r\nInfo (12021): Found 1 design units, including 1 entities, in source file out/block_0.sv\r\n\tInfo (12023): Found entity 1: block_0\r\nWarning (10037): Verilog HDL or VHDL warning at block_0.sv(111): conditional expression evaluates to a constant\r\nWarning (10037): Verilog HDL or VHDL warning at block_0.sv(127): conditional expression evaluates to a constant\r\nWarning (10037): Verilog HDL or VHDL warning at block_0.sv(143): conditional expression evaluates to a constant\r\nWarning (10037): Verilog HDL or VHDL warning at block_0.sv(159): conditional expression evaluates to a constant\r\nWarning (10037): Verilog HDL or VHDL warning at block_0.sv(94): conditional expression evaluates to a constant\r\nWarning (10037): Verilog HDL or VHDL warning at block_0.sv(193): conditional expression evaluates to a constant\r\nWarning (10037): Verilog HDL or VHDL warning at block_0.sv(176): conditional expression evaluates to a constant\r\nWarning (10037): Verilog HDL or VHDL warning at block_0.sv(227): conditional expression evaluates to a constant\r\nWarning (10037): Verilog HDL or VHDL warning at block_0.sv(237): conditional expression evaluates to a constant\r\nWarning (10037): Verilog HDL or VHDL warning at block_0.sv(247): conditional expression evaluates to a constant\r\nWarning (10037): Verilog HDL or VHDL warning at block_0.sv(258): conditional expression evaluates to a constant\r\nWarning (10037): Verilog HDL or VHDL warning at block_0.sv(210): conditional expression evaluates to a constant\r\nWarning (10037): Verilog HDL or VHDL warning at block_0.sv(283): conditional expression evaluates to a constant\r\nWarning (10037): Verilog HDL or VHDL warning at block_0.sv(299): conditional expression evaluates to a constant\r\nWarning (10037): Verilog HDL or VHDL warning at block_0.sv(315): conditional expression evaluates to a constant\r\nWarning (10037): Verilog HDL or VHDL warning at block_0.sv(328): conditional expression evaluates to a constant\r\nWarning (10037): Verilog HDL or VHDL warning at block_0.sv(266): conditional expression evaluates to a constant\r\nWarning (10037): Verilog HDL or VHDL warning at block_0.sv(359): conditional expression evaluates to a constant\r\nWarning (10037): Verilog HDL or VHDL warning at block_0.sv(376): conditional expression evaluates to a constant\r\nWarning (10037): Verilog HDL or VHDL warning at block_0.sv(393): conditional expression evaluates to a constant\r\nWarning (10037): Verilog HDL or VHDL warning at block_0.sv(403): conditional expression evaluates to a constant\r\nWarning (10037): Verilog HDL or VHDL warning at block_0.sv(342): conditional expression evaluates to a constant\r\nWarning (10037): Verilog HDL or VHDL warning at block_0.sv(436): conditional expression evaluates to a constant\r\nWarning (10037): Verilog HDL or VHDL warning at block_0.sv(451): conditional expression evaluates to a constant\r\nWarning (10037): Verilog HDL or VHDL warning at block_0.sv(466): conditional expression evaluates to a constant\r\nWarning (10037): Verilog HDL or VHDL warning at block_0.sv(482): conditional expression evaluates to a constant\r\nWarning (10037): Verilog HDL or VHDL warning at block_0.sv(498): conditional expression evaluates to a constant\r\nWarning (10037): Verilog HDL or VHDL warning at block_0.sv(513): conditional expression evaluates to a constant\r\nWarning (10037): Verilog HDL or VHDL warning at block_0.sv(528): conditional expression evaluates to a constant\r\nWarning (10037): Verilog HDL or VHDL warning at block_0.sv(543): conditional expression evaluates to a constant\r\nWarning (10037): Verilog HDL or VHDL warning at block_0.sv(558): conditional expression evaluates to a constant\r\nWarning (10037): Verilog HDL or VHDL warning at block_0.sv(573): conditional expression evaluates to a constant\r\nWarning (10037): Verilog HDL or VHDL warning at block_0.sv(419): conditional expression evaluates to a constant\r\nWarning (10037): Verilog HDL or VHDL warning at block_0.sv(606): conditional expression evaluates to a constant\r\nWarning (10037): Verilog HDL or VHDL warning at block_0.sv(624): conditional expression evaluates to a constant\r\nWarning (10037): Verilog HDL or VHDL warning at block_0.sv(642): conditional expression evaluates to a constant\r\nWarning (10037): Verilog HDL or VHDL warning at block_0.sv(652): conditional expression evaluates to a constant\r\nWarning (10037): Verilog HDL or VHDL warning at block_0.sv(670): conditional expression evaluates to a constant\r\nWarning (10037): Verilog HDL or VHDL warning at block_0.sv(688): conditional expression evaluates to a constant\r\nWarning (10037): Verilog HDL or VHDL warning at block_0.sv(698): conditional expression evaluates to a constant\r\nWarning (10037): Verilog HDL or VHDL warning at block_0.sv(714): conditional expression evaluates to a constant\r\nWarning (10037): Verilog HDL or VHDL warning at block_0.sv(589): conditional expression evaluates to a constant\r\nWarning (10037): Verilog HDL or VHDL warning at block_0.sv(748): conditional expression evaluates to a constant\r\nWarning (10037): Verilog HDL or VHDL warning at block_0.sv(763): conditional expression evaluates to a constant\r\nWarning (10037): Verilog HDL or VHDL warning at block_0.sv(778): conditional expression evaluates to a constant\r\nWarning (10037): Verilog HDL or VHDL warning at block_0.sv(793): conditional expression evaluates to a constant\r\nWarning (10037): Verilog HDL or VHDL warning at block_0.sv(731): conditional expression evaluates to a constant\r\nWarning (10037): Verilog HDL or VHDL warning at block_0.sv(828): conditional expression evaluates to a constant\r\nWarning (10037): Verilog HDL or VHDL warning at block_0.sv(847): conditional expression evaluates to a constant\r\nWarning (10037): Verilog HDL or VHDL warning at block_0.sv(865): conditional expression evaluates to a constant\r\nWarning (10037): Verilog HDL or VHDL warning at block_0.sv(809): conditional expression evaluates to a constant\r\nWarning (10037): Verilog HDL or VHDL warning at block_0.sv(911): conditional expression evaluates to a constant\r\nWarning (10037): Verilog HDL or VHDL warning at block_0.sv(930): conditional expression evaluates to a constant\r\nWarning (10037): Verilog HDL or VHDL warning at block_0.sv(886): conditional expression evaluates to a constant\r\nWarning (10037): Verilog HDL or VHDL warning at block_0.sv(973): conditional expression evaluates to a constant\r\nWarning (10037): Verilog HDL or VHDL warning at block_0.sv(952): conditional expression evaluates to a constant\r\nWarning (10037): Verilog HDL or VHDL warning at block_0.sv(1011): conditional expression evaluates to a constant\r\nWarning (10037): Verilog HDL or VHDL warning at block_0.sv(990): conditional expression evaluates to a constant\r\nWarning (10037): Verilog HDL or VHDL warning at block_0.sv(1028): conditional expression evaluates to a constant\r\nInfo (12127): Elaborating entity \"block_0\" for the top level hierarchy\r\nInfo (10008): Verilog HDL or VHDL information: EDA Netlist Writer cannot regroup multidimensional array \"o_register_8_bit_field_0\" into its bus\r\nInfo (10008): Verilog HDL or VHDL information: EDA Netlist Writer cannot regroup multidimensional array \"o_register_8_bit_field_1\" into its bus\r\nInfo (10008): Verilog HDL or VHDL information: EDA Netlist Writer cannot regroup multidimensional array \"o_register_8_bit_field_2\" into its bus\r\nInfo (10008): Verilog HDL or VHDL information: EDA Netlist Writer cannot regroup multidimensional array \"o_register_9_bit_field_0\" into its bus\r\nInfo (10008): Verilog HDL or VHDL information: EDA Netlist Writer cannot regroup multidimensional array \"o_register_9_bit_field_1\" into its bus\r\nInfo (10008): Verilog HDL or VHDL information: EDA Netlist Writer cannot regroup multidimensional array \"o_register_8_bit_field_0\" into its bus\r\nInfo (10008): Verilog HDL or VHDL information: EDA Netlist Writer cannot regroup multidimensional array \"o_register_8_bit_field_1\" into its bus\r\nInfo (10008): Verilog HDL or VHDL information: EDA Netlist Writer cannot regroup multidimensional array \"o_register_8_bit_field_2\" into its bus\r\nInfo (10008): Verilog HDL or VHDL information: EDA Netlist Writer cannot regroup multidimensional array \"o_register_9_bit_field_0\" into its bus\r\nInfo (10008): Verilog HDL or VHDL information: EDA Netlist Writer cannot regroup multidimensional array \"o_register_9_bit_field_1\" into its bus\r\nInfo (12128): Elaborating entity \"rggen_register_if\" for hierarchy \"rggen_register_if:register_if[22]\"\r\nInfo (12128): Elaborating entity \"rggen_apb_adapter\" for hierarchy \"rggen_apb_adapter:u_adapter\"\r\nWarning (10230): Verilog HDL assignment warning at rggen_apb_adapter.sv(19): truncated value with size 16 to match size of target (8)\r\nInfo (12128): Elaborating entity \"rggen_bus_if\" for hierarchy \"rggen_apb_adapter:u_adapter|rggen_bus_if:bus_if\"\r\nInfo (12128): Elaborating entity \"rggen_adapter_common\" for hierarchy \"rggen_apb_adapter:u_adapter|rggen_adapter_common:u_adapter_common\"\r\nWarning (10036): Verilog HDL or VHDL warning at rggen_adapter_common.sv(46): object \"status\" assigned a value but never read\r\nWarning (10036): Verilog HDL or VHDL warning at rggen_adapter_common.sv(47): object \"read_data\" assigned a value but never read\r\nWarning (10241): Verilog HDL Function Declaration warning at rggen_mux.sv(7): function \"mux\" may return a Don't Care value because its output register may not be assigned a value in every possible path through the function\r\nWarning (10030): Net \"u_status_mux.mux\" at rggen_mux.sv(7) has no driver or initial value, using a default initial value '0'\r\nWarning (10030): Net \"u_read_data_mux.mux\" at rggen_mux.sv(7) has no driver or initial value, using a default initial value '0'\r\nInfo (12128): Elaborating entity \"rggen_mux\" for hierarchy \"rggen_apb_adapter:u_adapter|rggen_adapter_common:u_adapter_common|rggen_mux:u_status_mux\"\r\nInfo (12128): Elaborating entity \"rggen_mux\" for hierarchy \"rggen_apb_adapter:u_adapter|rggen_adapter_common:u_adapter_common|rggen_mux:u_read_data_mux\"\r\nInfo (12128): Elaborating entity \"rggen_bit_field_if\" for hierarchy \"rggen_bit_field_if:g_register_0.bit_field_if\"\r\nInfo (12128): Elaborating entity \"rggen_default_register\" for hierarchy \"rggen_default_register:g_register_0.u_register\"\r\nInfo (12128): Elaborating entity \"rggen_register_common\" for hierarchy \"rggen_default_register:g_register_0.u_register|rggen_register_common:u_register_common\"\r\nWarning (10230): Verilog HDL assignment warning at rggen_register_common.sv(36): truncated value with size 32 to match size of target (8)\r\nWarning (10230): Verilog HDL assignment warning at rggen_register_common.sv(38): truncated value with size 32 to match size of target (8)\r\nError (10207): Verilog HDL error at rggen_register_common.sv(117): can't resolve reference to object \"mux\"\r\nError (10903): Verilog HDL error at rggen_register_common.sv(97): failed to elaborate task or function \"get_read_data\"\r\nError (12152): Can't elaborate user hierarchy \"rggen_default_register:g_register_0.u_register|rggen_register_common:u_register_common\"\r\nError: Quartus Prime Analysis & Elaboration was unsuccessful. 3 errors, 68 warnings\r\n\tError: Peak virtual memory: 1256 megabytes\r\n\tError: Processing ended: Thu Feb  6 01:31:04 2020\r\n\tError: Elapsed time: 00:00:11\r\n\tError: Total CPU time (on all processors): 00:00:27\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/rggen_rggen-sv-rtl_pr4", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/rggen_rggen-sv-rtl_pr4.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/rggen_rggen-sv-rtl_pr4", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/rggen_rggen-sv-rtl_pr4"}
{"instance_id": "secworks_aes_pr16", "issue_text": "# Bug Report: ready_reg in aes_key_mem.v reset value causes deadlock on initialization\n\n- Source URL: https://github.com/secworks/aes/issues/15\n\nThe `aes_key_mem.v` module incorrectly initializes `ready_reg` to `1'b0` during reset, causing a deadlock when controlling logic waits for the `ready` signal before initiating key expansion.\n\nAfter reset, the module enters the `CTRL_IDLE` state, indicating it should be available to accept new commands. However, `ready_reg = 1'b0` signals the module is busy, creating a contradiction between the FSM state and the ready flag.\n\n### Steps to Reproduce\n1. Instantiate `aes_key_mem` in a testbench\n2. Assert `reset_n` (active-low reset)\n3. Deassert `reset_n` and wait for `ready` signal\n4. **Result**: `ready` remains `0` indefinitely\n5. **Consequence**: Any master logic waiting on `ready` before asserting `init` will hang\n\n### Expected Behavior\nAfter reset, `aes_key_mem` should be idle and ready to accept a new key expansion operation. The `ready` signal should be `1'b1` to indicate the module is available for immediate use.\n\n\n- **Branch**: `master`\n- **File**: `src/rtl/aes_key_mem.v`\n- **Affected Line**: line 142\n\n`ready_reg <= 1'b0; ` **// Bug** \n`ready_reg <= 1'b1; ` **// Fix: Module is ready immediately after reset**\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/secworks_aes_pr16", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/secworks_aes_pr16.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/secworks_aes_pr16", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/secworks_aes_pr16"}
{"instance_id": "semify-eda_waveform-generator_pr13", "issue_text": "# Take a proper look at the wishbone interfaces\n\n- Source URL: https://github.com/semify-eda/waveform-generator/issues/9\n\nMaybe something doesn't work there\nWhy is the cycle signal used?\n\n\n\n\n\n\n\n\n\n\nPR title: Be a proper wishbone peripheral\n\nSource: https://github.com/semify-eda/waveform-generator/pull/13\n\nPR description:\nThe PR addresses issues with Wishbone peripheral implementation. The author notes that \"the `VexRiscv` core uses wishbone burst mode, despite being told not to\" and tested with `femtorv32_quark` instead.\n\nKey changes:\n- \"Interconnect now correctly transfers the data from the peripherals\"\n- \"Peripherals now only write their data when a read is in progress\"\n- \"`ack` is toggled immediately after being asserted\"\n\nCommits:\n1. Fix reading from registers\n2. Remove unnecessary bloat\n3. Fix reading registers for good (not evil)\n4. LiteX: Use class function for adding wfg\n\nComments and activity:\n- mole99 (author) created the PR on June 4, 2022 and made updates through June 6, 2022.\n- github-actions[bot] provided automated code review feedback regarding Verilog formatting suggestions via the verible-verilog-format tool.\n\nLinked issues closed:\n- Issue #12 \"Reading from peripheral doesn't set the whole output register\"\n- Issue #10 \"Try reading from wfg submodules\"\n- Issue #9 \"Take a proper look at the wishbone interfaces\"\n\nLabels: enhancement.\n\nStatus: Merged on June 8, 2022.\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/semify-eda_waveform-generator_pr13", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/semify-eda_waveform-generator_pr13.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/semify-eda_waveform-generator_pr13", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/semify-eda_waveform-generator_pr13"}
{"instance_id": "squared-studio_common_pr118", "issue_text": "# pll\n\n- Source URL: https://github.com/squared-studio/common/issues/111\n\n\n\n\n\n\n\n\n\n\n\n\n\nPR title: 111 pll\n\nSource: https://github.com/squared-studio/common/pull/118\n\nPR description:\nNo description provided.\n\nComments:\n- foez-ahmed (Contributor) - September 2, 2023: \"_No description provided._\"\n\nCommits (8 total):\nThe PR included 8 commits modifying PLL (Phase-Locked Loop) related files:\n- Modified rtl/model/pll.sv and rtl/pll.sv\n- Added testbench files (pll_tb.sv, wave.gtkw, configuration files)\n- Renamed rtl/model/pll.sv to rtl/pll.sv\n- Final merge commit into main branch\n\nLinked issue:\n- Issue #111 \"pll\" (closed by this PR).\n\nReviewers: None. Assignees: None. Labels: None. Milestone: None.\n\nStatus: Merged September 2, 2023. Author: foez-ahmed. Branch: 111-pll -> main.\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/squared-studio_common_pr118", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/squared-studio_common_pr118.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/squared-studio_common_pr118", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/squared-studio_common_pr118"}
{"instance_id": "svunit_svunit_pr110", "issue_text": "# Add JUnit XML\n\nInstance: svunit_svunit_pr110\nSource: https://github.com/svunit/svunit/pull/110\nFetched: 2026-05-03\nRepository: svunit/svunit\nPull request: #110\nAuthor: tudortimi\nState: closed\nBase branch: master\nHead branch: add-junit-xml\nCreated: 2021-03-14\nUpdated: 2021-03-14\nClosed: 2021-03-14\nMerged: 2021-03-14\n\n## PR Title\nAdd JUnit XML\n\n## PR Description\nNo description was provided for this pull request. The PR was authored by tudortimi and contained 24 commits implementing JUnit XML report export functionality for SVUnit. Work spanned creating tests that expect XML output, generating XML files after test runs, writing XML elements for testsuites, test suites and test cases, extracting an XmlElement class for element printing, adding failure-element handling, applying a Xcelium indentation workaround, updating documentation in the JUnit model classes, and updating the CHANGELOG.\n\n## PR Comments\nNo conversation comments were captured beyond the merge activity. The PR was merged on March 14, 2021 (merge commit 6266b81) and the add-junit-xml branch was deleted shortly afterwards on the same day.\n\n## Linked Issues\n**Issue #73 - \"Add export of JUnit XML report\"** (closed by this PR).\n\nIssue body (verbatim from the source URL):\n\"I remember that we had an issue for this, opened by someone else, but I can't find it.\n\nNow that I started using Jenkins more, I would like to have this as well.\"\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/svunit_svunit_pr110", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/svunit_svunit_pr110.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/svunit_svunit_pr110", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/svunit_svunit_pr110"}
{"instance_id": "svunit_svunit_pr113", "issue_text": "# Fix pytests utils\n\nInstance: svunit_svunit_pr113\nSource: https://github.com/svunit/svunit/pull/113\nFetched: 2026-05-03\nRepository: svunit/svunit\nPull request: #113\nAuthor: semihalf-bis-maciej (Maciej Bis)\nState: closed\nBase branch: master\nHead branch: fix-pytest\nCreated: 2021-07-09\nUpdated: 2021-08-16\nClosed: 2021-08-16\nMerged: 2021-08-16\n\n## PR Title\nFix pytests utils\n\n## PR Description\nThe PR addresses the `expect_*` methods in utils.py and how they are used in the test suite. The patch makes the tests raise exceptions on mismatches so that failures are actually caught by pytest. The author also notes that parentheses are special regex characters and need to be escaped in the patterns used by these helpers.\n\nThe PR is associated with issue #99 which observed that `expect_*` functions were merely returning True/False booleans without actually asserting any condition, so tests using them never failed.\n\n## PR Comments\n**semihalf-bis-maciej (Maciej Bis)** (Jul 9, 2021): Initial PR submission. Explains that `expect_*` helpers in utils.py never actually fail tests, and that this patch turns them into asserting helpers. Also notes the regex escaping fix for parentheses. Asks for review.\n\n**tudortimi** (Jul 2021): Identified the connection to issue #99 and requested some changes (e.g., asked the contributor to scope the fix more tightly and to clean up affected tests). Also raised the question of organization access permissions because maintainer edits to the contributor's branch were required.\n\n**semihalf-bis-maciej** (Jul-Aug 2021): Pushed follow-up commits addressing review feedback, disabling some `uvm_report_mock` tests that were broken under UVM 1.2 (out of scope for this PR), fixing the `sim_8` test, and removing an extraneous `.` from a file path used in `expect`.\n\n**tudortimi** (Aug 16, 2021): Approved and merged the PR after a final rebase onto master. 5 commits in total were included.\n\n## Linked Issues\n**Issue #99 - \"Tests that use `expect_*` don't check anything\"** (closed by this PR).\n\nIssue body (verbatim from the source URL):\n\"The `expect_*` functions just return `True` or `False`, but they don't check anything.\"\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/svunit_svunit_pr113", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/svunit_svunit_pr113.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/svunit_svunit_pr113", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/svunit_svunit_pr113"}
{"instance_id": "svunit_svunit_pr114", "issue_text": "# Evaluation of unknown values with FAIL_* macros\n\nInstance: svunit_svunit_pr114\nSource: https://github.com/svunit/svunit/pull/114\nFetched: 2026-05-03\nRepository: svunit/svunit\nPull request: #114\nAuthor: semihalf-bis-maciej (Maciej Bis)\nState: closed\nBase branch: master\nHead branch: fail-x\nCreated: 2021-07-09\nUpdated: 2021-07-21\nClosed: 2021-07-21\nMerged: 2021-07-21\n\n## PR Title\nEvaluation of unknown values with FAIL_* macros\n\n## PR Description\nThe PR implements proper handling of unknown ('x'/'z') values in the `FAIL_*` macro family so that comparisons follow SystemVerilog semantics. It addresses request #51 (\"Unexpected == evaluation of unknown values with svunit_testcase::fail()\"), where `==` against unknowns produced unexpected pass/fail outcomes.\n\n## PR Comments\n**semihalf-bis-maciej** (Jul 9, 2021): \"This is implementation of #51 request - evaluation of unknown values in `FAIL_*` macros. Please review.\"\n\n**tudortimi** (Jul 12, 2021): Asked for a CHANGELOG entry. Suggested the `FAIL_*` macros be restructured using `if`-statements for readability rather than the current expression form.\n\n**tudortimi** (Jul 12, 2021): Asked the contributor to rename test files/cases to something more descriptive so they would not collide with names used in other in-flight pull requests.\n\n**semihalf-bis-maciej** (Jul 13, 2021): Agreed to rename the new tests, pushed updated commits.\n\n**tudortimi** (Jul 19, 2021): Clarified the project's CHANGELOG policy - entries are only added for unreleased changes, and version strings get bumped at release time.\n\n**semihalf-bis-maciej** (Jul 20, 2021): Pushed CHANGELOG updates and noted some recent organizational changes around repository management.\n\n**tudortimi** (Jul 21, 2021): Approved and merged the PR, thanking the contributor.\n\n## Linked Issues\n**Issue #51 - \"Unexpected == evaluation of unknown values with svunit_testcase::fail()\"** (closed by this PR).\n\nIssue body (verbatim from the source URL):\n\"Since the fail() method takes a two-state argument of type bit for the expression argument, the evaluation for unknown values is inconsistent with pure SystemVerilog code due to the implicit type casting.\n\nThe expression 1'bx == 1'bx evaluates to X and branches to the else clause in the following code.\n\n    if(1'bx == 1'bx) $display(\\\"true\\\");\n    else    $display(\\\"false\\\");\n\nHowever, when the same expression is used in the `FAIL_UNLESS macro it will not generate an error.  A proposed fix is to change the b argument of the svunit_testcase::fail() function to a logic type and change the test operation from if(b) to if(b!==0).\"\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/svunit_svunit_pr114", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/svunit_svunit_pr114.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/svunit_svunit_pr114", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/svunit_svunit_pr114"}
{"instance_id": "svunit_svunit_pr197", "issue_text": "# Simple change to svunit_string_utils.svh to clean up VCS Warning-[IASC] Illegal argument in string comparison\n\n- Source URL: https://github.com/svunit/svunit/issues/193\n\nWhen using the latest SVUnit with VCS Version S-2021.09-SP2-4\r\nI get this warning which makes you do a double take each time you run tests:\r\n\r\nWarning-[IASC] Illegal argument in string comparison\r\n/proj/ccd_func_dev0/users/craftsmanship/repos/svunit/svunit_base/svunit_string_utils.svh, 17\r\nsvunit_pkg, \"s[i]\"\r\n  Either string or string literal is expected as first argument to the string \r\n  comparison operation.\r\n  Use the string cast operator to convert it to a string literal.\r\n\r\n\r\nThe fix is this:\r\niff --git a/svunit_base/svunit_string_utils.svh b/svunit_base/svunit_string_utils.svh\r\nindex 2b2e5b4..b1a437b 100644\r\n--- a/svunit_base/svunit_string_utils.svh\r\n+++ b/svunit_base/svunit_string_utils.svh\r\n@@ -13,7 +13,7 @@\r\n     for (int i = 0; i < s.len(); i++) begin\r\n       if (i == s.len()-1)\r\n         parts.push_back(s.substr(last_char_position+1, i));\r\n-      if (s[i] == char) begin\r\n+      if (string'(s[i]) == char) begin\r\n\r\n\r\nLet me know if I can be of more help.\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/svunit_svunit_pr197", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/svunit_svunit_pr197.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/svunit_svunit_pr197", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/svunit_svunit_pr197"}
{"instance_id": "taichi-ishitani_tvip-apb_pr5", "issue_text": "# Error when no wait states 3.1.1\n\n- Source URL: https://github.com/taichi-ishitani/tvip-apb/issues/3\n\nHi Taichi!  I find problem. When pready always == 1, then penable not assert,  and psel tick only 1 clk. \r\n\r\n![Screenshot from 2023-11-01 16-08-25](https://github.com/taichi-ishitani/tvip-apb/assets/35744340/2c2f8925-bde3-4887-8cbd-5db50d269c69)\r\n\r\n\r\nI think it's connected with  this part of code \r\nhttps://github.com/taichi-ishitani/tvip-apb/blob/master/src/tvip_apb_master_driver.svh#L91\r\n\r\n```\r\n  protected virtual task wait_for_done();\r\n    while (!vif.master_cb.pready) begin\r\n      @(vif.master_cb);\r\n    end\r\n```\r\n\r\ni think this must be \r\n```\r\n  protected virtual task wait_for_done();\r\n    do begin\r\n      @(vif.master_cb);\r\n    end while (!vif.master_cb.pready) ;\r\n```\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/taichi-ishitani_tvip-apb_pr5", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/taichi-ishitani_tvip-apb_pr5.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/taichi-ishitani_tvip-apb_pr5", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/taichi-ishitani_tvip-apb_pr5"}
{"instance_id": "taichi-ishitani_tvip-axi_pr20", "issue_text": "# Support wvalid preceding awvalid\n\nInstance: taichi-ishitani_tvip-axi_pr20\nSource: https://github.com/taichi-ishitani/tvip-axi/pull/20\nFetched: 2026-05-03\nRepository: taichi-ishitani/tvip-axi\nPull request: #20\nAuthor: taichi-ishitani\nState: closed\nBase branch: master\nHead branch: support_wvalid_preceding_awvalid\nCreated: 2020-09-02\nUpdated: 2020-09-02\nClosed: 2020-09-02\nMerged: 2020-09-02\n\n## PR Title\nSupport wvalid preceding awvalid\n\n## PR Description\nNo description was provided. The PR contains two commits:\n1. b3d67e1 - \"fix #19\" (the actual logic fix to allow wvalid to assert before awvalid in the slave driver/agent)\n2. a98680e - \"added a delay module to create the situation that wvalid precedes awvalid\" (testbench scaffolding to reproduce and exercise the corner case)\n\n## PR Comments\nNo conversation comments were posted. The PR was authored, reviewed and merged by taichi-ishitani (sole participant). The branch `support_wvalid_preceding_awvalid` was later deleted on Aug 1, 2022.\n\n## Linked Issues\n**Issue #19 - \"Slave driver data before address support\"** (closed by this PR).\n\nIssue body (verbatim from the source URL):\n\"In slave driver, if more than one wvalid is received before awvalid, only one bvalid is asserted, so the tests get stuck.\"\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/taichi-ishitani_tvip-axi_pr20", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/taichi-ishitani_tvip-axi_pr20.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/taichi-ishitani_tvip-axi_pr20", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/taichi-ishitani_tvip-axi_pr20"}
{"instance_id": "taichi-ishitani_tvip-axi_pr36", "issue_text": "# add null check to avoid null pointer exception\n\nInstance: taichi-ishitani_tvip-axi_pr36\nSource: https://github.com/taichi-ishitani/tvip-axi/pull/36\nFetched: 2026-05-03\nRepository: taichi-ishitani/tvip-axi\nPull request: #36\nAuthor: taichi-ishitani\nState: closed\nBase branch: master\nHead branch: fix_35\nCreated: 2022-05-19\nUpdated: 2022-05-19\nClosed: 2022-05-19\nMerged: 2022-05-19\n\n## PR Title\nadd null check to avoid null pointer exception\n\n## PR Description\n\"This PR is to fix #35.\"\n\nThe change adds a null-check guard so that the slave driver does not dereference a null sequence-item handle when it is reset partway through a transaction; the issue had been reported as a NULL pointer dereference in `uvm_transaction::get_event_pool` triggered by `tue_sequence_item_base::get_event` / `ended` being called from `tvip_axi_slave_driver`'s start-delay thread after a mid-transaction reset.\n\n## PR Comments\n**taichi-ishitani** (May 19, 2022): \"This PR is to fix #35.\" (Author/owner; this is the only conversation entry, posted at submission time.)\n\nNo code-review comments were posted; the PR was self-merged by taichi-ishitani at commit e2d29ef. The branch `fix_35` was deleted shortly after merge.\n\n## Linked Issues\n**Issue #35 - \"Another NULL pointer dereference after reset in the middle\"** (closed by this PR).\n\nIssue body (verbatim from the source URL):\n\"The latest version has another NULL pointer dereference as below:\n```\nxmsim: *E,TRNULLID: NULL pointer dereference.\n          File: /opt/eda/cadence/XCELIUM2103/tools/methodology/UVM/CDNS-1.2/sv/src/base/uvm_transaction.svh, line = 521, pos = 14\n         Scope: worklib.uvm_pkg::uvm_transaction::get_event_pool\n          Time: 7134 NS + 13\nVerilog Stack Trace:\n0: function worklib.uvm_pkg::uvm_transaction::get_event_pool at /opt/eda/cadence/XCELIUM2103/tools/methodology/UVM/CDNS-1.2/sv/src/base/uvm_transaction.svh:521\n1: function worklib.tue_pkg::tue_sequence_item_base#(uvm_pkg::uvm_sequence_item,tvip_axi_pkg::tvip_axi_configuration,tvip_axi_pkg::tvip_axi_status,tvip_axi_pkg::tvip_axi_configuration,tvip_axi_pkg::tvip_axi_status)::get_event at /path/to/tvip-axi/tue/src/seq/tue_sequence_item_base.svh:41\n2: function worklib.tue_pkg::tue_sequence_item_base#(uvm_pkg::uvm_sequence_item,tvip_axi_pkg::tvip_axi_configuration,tvip_axi_pkg::tvip_axi_status,tvip_axi_pkg::tvip_axi_configuration,tvip_axi_pkg::tvip_axi_status)::ended at /path/to/tvip-axi/tue/src/seq/tue_sequence_item_base.svh:51\n3: task worklib.tvip_axi_pkg::tvip_axi_slave_driver_start_delay_consumer@13753_2.delay_thread at /path/to/tvip-axi/src/tvip_axi_slave_driver.svh:66\n4: process in worklib.tvip_axi_pkg::tvip_axi_slave_driver_start_delay_consumer@13753_2.start_delay_thread.unmblk1 at /path/to/tvip-axi/src/tvip_axi_slave_driver.svh:48\n```\"\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/taichi-ishitani_tvip-axi_pr36", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/taichi-ishitani_tvip-axi_pr36.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/taichi-ishitani_tvip-axi_pr36", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/taichi-ishitani_tvip-axi_pr36"}
{"instance_id": "taichi-ishitani_tvip-axi_pr44", "issue_text": "# fix *E,EXPRPA error reported by Cadence Xcelium simulator\n\nInstance: taichi-ishitani_tvip-axi_pr44\nSource: https://github.com/taichi-ishitani/tvip-axi/pull/44\nFetched: 2026-05-03\nRepository: taichi-ishitani/tvip-axi\nPull request: #44\nAuthor: taichi-ishitani\nState: closed\nBase branch: master\nHead branch: fix_43\nCreated: 2022-07-25\nUpdated: 2022-07-25\nClosed: 2022-07-25\nMerged: 2022-07-25\n\n## PR Title\nfix *E,EXPRPA error reported by Cadence Xcelium simulator\n\n## PR Description\nThe PR rewrites the offending construct in `tvip_axi_slave_default_sequence.svh` so that the compile-time embedded assignment that Xcelium rejects (`if ((delay = get_address_ready_delay(item)) >= 0)`) is replaced by a separate variable assignment followed by a plain comparison, eliminating the `EXPRPA` parse error. References issue #43.\n\n## PR Comments\nThe conversation pane on this PR could not be fully rendered when fetched, but the only participant on record is the author taichi-ishitani. No code-review comments were posted before merge. The PR was self-merged at commit da6fdc8 / 93f9200 on July 25, 2022, and the `fix_43` branch was deleted on Aug 1, 2022.\n\n## Linked Issues\n**Issue #43 - \"Cadence Xcelium doesn't support variable substitution in if-condition\"** (closed by this PR).\n\nIssue body (verbatim from the source URL):\n\"Cadence Xcelium doesn't support variable substitution in if-condition as follows:\n```\n    if ((delay = get_address_ready_delay(item)) >= 0) begin\n               |\nxmvlog: *E,EXPRPA (/path/to/tvip-axi/src/tvip_axi_slave_default_sequence.svh,32|15): expecting a right parenthesis (')') [4.3][9.7(IEEE)].\n(`include file: /path/to/tvip-axi/src/tvip_axi_slave_default_sequence.svh line 32, file: /path/to/tvip-axi/src/tvip_axi_pkg.sv line 45)\n```\nThis issue can be reproduced by the command:\n```\ncd sample/work\nmake compile_xcelium\n```\nHere is the detailed log:\n[tvip-axi_a516ccd_sample_work_compile_xcelium.log](https://github.com/taichi-ishitani/tvip-axi/files/9177105/tvip-axi_a516ccd_sample_work_compile_xcelium.log)\"\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/taichi-ishitani_tvip-axi_pr44", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/taichi-ishitani_tvip-axi_pr44.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/taichi-ishitani_tvip-axi_pr44", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/taichi-ishitani_tvip-axi_pr44"}
{"instance_id": "taichi-ishitani_tvip-axi_pr47", "issue_text": "# Problem with On the Fly Reset  \n\n- Source URL: https://github.com/taichi-ishitani/tvip-axi/issues/46\n\nHi @taichi-ishitani ! I have a problem when i have reset on AXI.\r\nIn my test I have AXI4 slave and DUT.  \r\nWhen i asserted reset the BValid, Bid not reset to zero.  \r\nThe figure below \r\n![1_problem](https://user-images.githubusercontent.com/35744340/209571013-9d82fc3e-18c5-40e0-9aba-e40201c0ee53.jpg)\r\n\r\nSo i find the problem. I think it happened because of race conditions \r\nhttps://github.com/taichi-ishitani/tvip-axi/blob/master/src/tvip_axi_slave_driver.svh#L524\r\n\r\nthis happened after \r\n```\r\n  protected task drive_response(bit valid, tvip_axi_slave_driver_response_item item);\r\n    vif.slave_cb.bvalid <= valid;\r\n    if (valid) begin\r\n      vif.slave_cb.bid    <= item.get_id();\r\n      vif.slave_cb.bresp  <= item.get_response_status();\r\n    end\r\n  endtask\r\n```\r\nThis \r\n  ```\r\nprotected task reset_if();\r\n    vif.awready = configuration.default_awready;\r\n    vif.wready  = configuration.default_wready;\r\n    vif.bvalid  = '0;\r\n    vif.bid     = '0;\r\n    vif.bresp   = tvip_axi_response'(0);\r\n  endtask\r\n```\r\n\r\nSo my decision \r\n```\r\n  protected task drive_response(bit valid, tvip_axi_slave_driver_response_item item);\r\n    vif.bvalid <= valid;\r\n    if (valid) begin\r\n      vif.bid    <= item.get_id();\r\n      vif.bresp  <= item.get_response_status();\r\n    end\r\n  endtask\r\n```\r\nI'm not sure, that I understand your logic correctly, but in my case, it's work fine...\r\n\r\n![2_solve](https://user-images.githubusercontent.com/35744340/209571584-3d7cae05-5ffe-4947-88bb-d717157fa537.jpg)\r\n\r\n\r\nBest regards.\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/taichi-ishitani_tvip-axi_pr47", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/taichi-ishitani_tvip-axi_pr47.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/taichi-ishitani_tvip-axi_pr47", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/taichi-ishitani_tvip-axi_pr47"}
{"instance_id": "taichi-ishitani_tvip-axi_pr50", "issue_text": "# axi_slave_sub_driver don't reset response_queue\n\n- Source URL: https://github.com/taichi-ishitani/tvip-axi/issues/49\n\nHi Taichi! \r\nI have a problemlem connected with AXI Slave\r\n\r\n \r\n![Screenshot from 2023-04-11 11-27-07](https://user-images.githubusercontent.com/35744340/231102389-6b30e00d-b5be-4bf6-8aaa-79f85fd04db2.png)\r\n\r\nAfter reset i see response on R channel... \r\n\r\nI find a problem \r\nhttps://github.com/taichi-ishitani/tvip-axi/blob/master/src/tvip_axi_slave_driver.svh#L147\r\n\r\nmust delete in task \r\nhttps://github.com/taichi-ishitani/tvip-axi/blob/master/src/tvip_axi_slave_driver.svh#L196\r\n\r\n```\r\n\r\n    protected task do_reset();\r\n    start_delay_consumer.do_reset();\r\n\r\n    ...............................................\r\n\r\n    active_responses.delete();\r\n    active_ids.delete();\r\n    \r\n    response_queue.delete();    <-------- !\r\n\r\n\r\n    reset_if();\r\n    @(posedge vif.areset_n);\r\n  endtask\r\n\r\n```\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/taichi-ishitani_tvip-axi_pr50", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/taichi-ishitani_tvip-axi_pr50.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/taichi-ishitani_tvip-axi_pr50", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/taichi-ishitani_tvip-axi_pr50"}
{"instance_id": "taichi-ishitani_tvip-common_pr4", "issue_text": "# incorrect behavior when started  = 0\n\n- Source URL: https://github.com/taichi-ishitani/tvip-common/issues/3\n\nHi Taichi! I tried to create stop clk during simulation. \r\n\r\nI have this dependencies in interface\r\n```\r\n    tvip_clock_if gm_clk_if();\r\n    assign gm_clk_if.started = (clk_en == 1) ? 1 : 0 ;\r\n```\r\n\r\nSo, when clk_en = 0   ->   gm_clk_if.started = 0 \r\n\r\nI see figure below  \r\n![Screenshot_bad](https://user-images.githubusercontent.com/35744340/208059355-0a134b3e-4209-4e2c-b15e-6038418ad5f7.png)\r\n\r\nAs you can see, clk change value after clk_en = 0.\r\n\r\nI think it's not good behaviour. The main reason of it \r\n\r\nhttps://github.com/taichi-ishitani/tvip-common/blob/master/src/tvip_clock_if.sv#L36\r\n\r\n ```\r\n always @(posedge started) begin\r\n    while (started) begin\r\n      #(half_period);                                            <---\r\n      clk ^= 1;\r\n    end\r\n  end\r\n```\r\n\r\n\r\nthe delay should be after the after `clk ^= 1;`\r\n\r\n ```\r\n always @(posedge started) begin\r\n    while (started) begin\r\n      clk ^= 1;\r\n      #(half_period);\r\n    end\r\n  end\r\n```\r\n\r\nIn this case figure below \r\n![Screenshot_good](https://user-images.githubusercontent.com/35744340/208060094-0206d848-9865-42a2-8721-6644ef435d80.png)\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/taichi-ishitani_tvip-common_pr4", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/taichi-ishitani_tvip-common_pr4.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/taichi-ishitani_tvip-common_pr4", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/taichi-ishitani_tvip-common_pr4"}
{"instance_id": "va7deo_zerowing_pr17", "issue_text": "# Tile priority workaround for Truxton. Sprite position tweaks and fix. Keyboard handler.\n\nInstance: va7deo_zerowing_pr17\nSource: https://github.com/va7deo/zerowing/pull/17\nFetched: 2026-05-03\nRepository: va7deo/zerowing\nPull request: #17\nAuthor: blackwine\nState: closed\nBase branch: main\nHead branch: main (blackwine fork)\nCreated: 2022-02-05\nUpdated: 2022-02-05\nClosed: 2022-02-05\nMerged: 2022-02-05\n\n## PR Title\nTile priority workaround for Truxton. Sprite position tweaks and fix. Keyboard handler.\n\n## PR Description\nCloses issue #14. Includes 4 commits:\n1. \"Differentiate tile priority checks. Tweak sprite positions\" (76c900c)\n2. \"Add clock to chip select\" (8738db5)\n3. \"Add keyboard handler\" (7fca9f5)\n4. \"Fix regression with sprite pos. adjustments\" (481355f)\n\nTogether these add a Truxton-targeted tile-priority workaround, tweak/fix sprite positioning, and introduce a keyboard input handler so that JPAC-style controllers/MAME keyboards work out of the box.\n\n## PR Comments\n**blackwine** (Feb 5, 2022): \"Closes #14\"\n\n**va7deo** (Feb 5, 2022): Merged the pull request the same day.\n\n## Linked Issues\n**Issue #14 - \"Support for MAME keys\"** (closed by this PR).\n\nIssue body (verbatim from the source URL):\n\"Please add this, as it would make JPAC devices work out of the box.\"\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/va7deo_zerowing_pr17", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/va7deo_zerowing_pr17.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/va7deo_zerowing_pr17", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/va7deo_zerowing_pr17"}
{"instance_id": "verilator_verilator_pr6552", "issue_text": "# Support basic global constraints (#6551)\n\nInstance: verilator_verilator_pr6552\nSource: https://github.com/verilator/verilator/pull/6552\nFetched: 2026-05-03\nRepository: verilator/verilator\nPull request: #6552\nAuthor: YilouWang\nState: closed\nBase branch: master\nHead branch: new_branch_for_global_rand\nCreated: 2025-10-12\nUpdated: 2025-11-05\nClosed: 2025-11-05\nMerged: 2025-11-05\n\n## PR Title\nSupport basic global constraints (#6551)\n\n## PR Description\nImplements the global-constraints feature defined in IEEE 1800-2023 section 18.5.8, addressing issue #6551. The implementation has three main pieces:\n\n1. Global-constraint detection: an `isGlobalConstrained` flag is added to AstVar to identify variables participating in global constraints.\n2. Constraint hoisting: constraints from nested member classes are extracted and evaluated together at the top-level class so that cross-object constraint solving works.\n3. MemberSel handling: logic for nested member-access paths (e.g. `m1.inner.val`) is added so the SMT variable declaration is correct.\n\nThe author noted a memory leak issue early on which was addressed via subsequent refinements. The feature was developed across many commits between Sep 19 and Nov 5, 2025.\n\n## PR Comments\n**RRozak**: Pointed out that the implementation does not handle polymorphic-type scenarios where the declared class type differs from the actual runtime type. **YilouWang** agreed to handle this in a follow-up PR.\n\n**wsnyder**: Requested verification of `rand_mode` behaviour against the IEEE specification. Reviewed across multiple iterations and ultimately merged on Nov 5, 2025.\n\nOther participants: gezalore (review), udayaa-init (contributions/co-author).\n\n## Linked Issues\n**Issue #6551 - \"Support global constraints\"** (closed by this PR).\n\nIssue body (verbatim from the source URL):\n\"After [PR#5625](https://github.com/verilator/verilator/pull/5625), global constraints has been kept as an unsupported warning messages, which needs to be fixed.\"\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/verilator_verilator_pr6552", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/verilator_verilator_pr6552.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/verilator_verilator_pr6552", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/verilator_verilator_pr6552"}
{"instance_id": "verilator_verilator_pr6573", "issue_text": "# Support `std::randomize() with`\n\n- Source URL: https://github.com/verilator/verilator/issues/4706\n\nHi,\r\nI'm using some Pulp code which has the following construct in https://github.com/pulp-platform/riscv-dbg/blob/master/src/dmi_test.sv.\r\nWhen I run this test, I get \r\n%Error-UNSUPPORTED: dmi_test.sv:182:45: Unsupported: randomize() 'with' constraint\r\n  182 |       rand_success = std::randomize(cycles) with {\r\n      |                                             ^~~~\r\nIs there any ETA on adding this feature? Is this something which might come with UVM support?\r\n\r\nThanks\r\n\r\n    task automatic rand_wait(input int unsigned min, input int unsigned max);\r\n      int unsigned rand_success, cycles;\r\n      rand_success = std::randomize(cycles) with {\r\n        cycles >= min;\r\n        cycles <= max;\r\n        // Weigh the distribution so that the minimum cycle time is the common\r\n        // case.\r\n        cycles dist {min := 10, [min+1:max] := 1};\r\n      };\r\n      assert (rand_success) else $error(\"Failed to randomize wait cycles!\");\r\n      repeat (cycles) @(posedge this.drv.bus.clk_i);\r\n    endtask\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/verilator_verilator_pr6573", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/verilator_verilator_pr6573.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/verilator_verilator_pr6573", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/verilator_verilator_pr6573"}
{"instance_id": "verilator_verilator_pr6583", "issue_text": "# Trior/and wor/wand nettypes missing from FST trace module\n\n- Source URL: https://github.com/verilator/verilator/issues/6582\n\nThanks for the great software!\n\nIt appears maybe the relatively recently added support for `trior/and` and `wor/wand` net types was missing updates for FST dumping of the same?\n\n> Can you please attach an example that shows the issue or missing feature? \n\nUpdating `test_regress/t/t_trace_fst.v` with:\n\n```diff\ndiff --git a/test_regress/t/t_trace_fst.v b/test_regress/t/t_trace_fst.v\nindex 44ac7feac..4091d0e75 100644\n--- a/test_regress/t/t_trace_fst.v\n+++ b/test_regress/t/t_trace_fst.v\n@@ -38,7 +38,13 @@ module t (/*AUTOARG*/\n    tri0            fst_tri0;\n    tri1            fst_tri1;\n    tri             fst_tri;\n+   triand          fst_triand;\n+   trior           fst_trior;\n+   //trireg          fst_trireg; // Error-UNSUPPORTED\n+   wor             fst_wor;\n+   wand            fst_wand;\n    wire            fst_wire;\n+   uwire           fst_uwire;\n    inout           fst_inout;\n\n    Test test (/*AUTOINST*/\n```\n\n> What output from that test indicates it is wrong, and what is the correct or expected output?\n\nYields:\n\n```\n#vlt/t_trace_fst: %Error: Exec of make failed: Vt_trace_fst__Trace__0__Slow.cpp:41:102: error: ‘TRIAND’ is not a member of ‘VerilatedTraceSigKind’\n                make && test_regress/t/t_trace_fst.py  --vlt\n```\n\n> What 'verilator' command line do we use to run your example?\n\n`test_regress/t/t_trace_fst.py`\n\n> What 'verilator --version' are you using?  Did you try it with the git master version?  Did you try it with other simulators?\n\n[master@cc7723390](https://github.com/verilator/verilator/commit/cc77233902f40cf8b90fb267d00890f2a4e3755e)\n`Verilator 5.041 devel rev UNKNOWN.REV (mod)`\n\n> What OS and distribution are you using?\n\nUbuntu/WSL 2.0\n\n> May we assist you in trying to fix this in Verilator yourself?\n\nSure! New to contributing but happy to help if I can!\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/verilator_verilator_pr6583", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/verilator_verilator_pr6583.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/verilator_verilator_pr6583", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/verilator_verilator_pr6583"}
{"instance_id": "verilator_verilator_pr6596", "issue_text": "# repeat(@posedge) inside a task causes incorrect timing on second call\n\n- Source URL: https://github.com/verilator/verilator/issues/6593\n\nWhen using repeat(N) @(posedge CLK); inside a task, Verilator produces incorrect timing behavior only on the second call of the task.\n\n\nVerilator 5.041 devel rev v5.040-333-gd864057a6\n\n--------------------------------------------------------------------------------\n```\n`timescale 1ns/1ps\n`default_nettype none\n\nmodule tb();\n\n  // VCD or FST Dump\n  initial\n    if( $test$plusargs (\"WAVE\") ) begin\n      $dumpfile(\"wave_test1.dump\");\n      $dumpvars(0, tb);\n    end\n\n  parameter int PREOD = 100;          // 100ns(10MHz)\n\n  bit CLK;\n\n  localparam int H_PREOD = PREOD / 2;\n  always #H_PREOD\n    CLK = ~CLK;\n\n\n  task automatic next_bit();    // NG\n    repeat(4)\n      @(posedge CLK);\n  endtask\n\n/*\n  task automatic next_bit();    // OK\n    repeat(3)\n      @(posedge CLK);\n\n    @(posedge CLK);\n  endtask\n*/\n\n  bit [3:0] cnt = 0;\n\n  task test_txd();\n    cnt = 0;    \n    next_bit();\n    for(int i=0; i < 8; i++) begin\n      ++cnt;\n      next_bit();\n    end\n\n    ++cnt;\n    next_bit();\n  endtask\n\n\n  initial begin\n    test_txd();\n    test_txd();\n\n    repeat(10) @(posedge CLK);\n    $finish;    \n  end\n\nendmodule\n```\n--------------------------------------------------------------------------------\n\n<img width=\"1127\" height=\"612\" alt=\"Image\" src=\"https://github.com/user-attachments/assets/c6662bb8-ff29-4d32-8d0a-e3d327f7df42\" />\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/verilator_verilator_pr6596", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/verilator_verilator_pr6596.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/verilator_verilator_pr6596", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/verilator_verilator_pr6596"}
{"instance_id": "verilator_verilator_pr6630", "issue_text": "# `--coverage` triggers complaints for certain ternary assignments.\n\n- Source URL: https://github.com/verilator/verilator/issues/6629\n\nHi team at Verilator!\n\nIn version 5.042, we noticed multiple new warnings like the following:\n```\n%Warning-SIDEEFFECT: top.sv:36:67: Expression side effect may be mishandled\n                                 : ... Suggest use a temporary variable in place of this expression\n   36 | assign out_ipv4_header.header_chk_sum = csum == 16'hFFFF ? csum : ~csum;\n      |                                                                   ^\n                     ... For warning description see https://verilator.org/warn/SIDEEFFECT?v=5.042\n                     ... Use \"/* verilator lint_off SIDEEFFECT */\" and lint_on around source to disable this message.\n```\n\nTo reproduce the issue, please clone this repo.:\n[https://github.com/etep/verilator-5.042-possible-issue](https://github.com/etep/verilator-5.042-possible-issue)\n\nRun `make` or `make clean && make`.\n\nIf arg. `--coverage` is removed, the warnings are gone.\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/verilator_verilator_pr6630", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/verilator_verilator_pr6630.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/verilator_verilator_pr6630", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/verilator_verilator_pr6630"}
{"instance_id": "verilator_verilator_pr6631", "issue_text": "# \"Missed a time slot?\" simulation error when verilated with --timing and --x-initial-edge\n\n- Source URL: https://github.com/verilator/verilator/issues/6603\n\nThe following code causes simulation to abort when verilated with `--timing` and `--x-initial-edge`:\n```SystemVerilog\nmodule test; \ninitial begin \n    #10; \nend \nendmodule\n```\n\nThe error:\n```\n%Error: /usr/local/share/verilator/include/verilated_timing.cpp:83: %Error: Encountered process that should've been resumed at an earlier simulation time. Missed a time slot?\n```\nReproducing (`--binary` implies `--timing`):\n```\necho \"module test; initial begin #10; end endmodule\" > test.sv\nverilator --binary --x-initial-edge test.sv\n./obj_dir/Vtest\n```\nverilator --version:\n```\nVerilator 5.040 2025-08-30 rev v5.040 & Verilator 5.041 devel rev v5.040-358-gb65200923\n```\nOS: Ubuntu 24.04.2 LTS (and the one used in verilator docker container)\n\nSeems to be related to #5723, specifically this [comment](https://github.com/verilator/verilator/issues/5723#issuecomment-3407078256) there.\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/verilator_verilator_pr6631", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/verilator_verilator_pr6631.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/verilator_verilator_pr6631", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/verilator_verilator_pr6631"}
{"instance_id": "verilator_verilator_pr6668", "issue_text": "# Add --unroll-limit option (#6654)\n\nInstance: verilator_verilator_pr6668\nSource: https://github.com/verilator/verilator/pull/6668\nFetched: 2026-05-03\nRepository: verilator/verilator\nPull request: #6668\nAuthor: gezalore\nState: closed\nBase branch: master\nHead branch: unroll-error\nCreated: 2025-11-09\nUpdated: 2025-11-09\nClosed: 2025-11-09\nMerged: 2025-11-09\n\n## PR Title\nAdd --unroll-limit option (#6654)\n\n## PR Description\nSplits the dual-purpose `--unroll-count` knob requested in issue #6654 by introducing a new option that controls only the upper-bound used for infinite-loop detection in generate loops, V3Simulate and `unroll_full`, leaving `--unroll-count` to apply to procedural loops as before. The flag was originally proposed as `--unroll-error`; reviewer feedback led to renaming it to `--unroll-limit` to be consistent with `--converge-limit`.\n\n## PR Comments\n**gezalore** (Nov 9, 2025): \"Fixes #6654\"\n\n**wsnyder** (Nov 9, 2025, review): Suggested avoiding \"error\" in flag names; proposed `--unroll-limit` to match the naming pattern of existing options like `--converge-limit`, calling it \"better\" and a \"help understanding\".\n\n**gezalore** (Nov 9, 2025): \"Agreed that's better, renamed.\"\n\n**gezalore** (Nov 9, 2025): \"Please merge this if you are happy with it.\"\n\n**wsnyder** (Nov 9, 2025): Merged with 53 checks passing.\n\n## Linked Issues\n**Issue #6654 - \"Split --unroll-count option\"** (closed by this PR).\n\nIssue body (verbatim from the source URL):\n\"Currently `--unroll-count` applies both to procedural loop statements, and also to generate loops (with a fudge factor).\n\nIt is sometimes advantageous to reduce loop unrolling for procedural statement, but due to the same number being applied to generate loops, it cannot be set to an arbitrarily small number.\n\nThe only reason generate loops need a limit is to avoid infinite expansion when there is a user bug, e.g. a missing `++i` in the generate loop.\n\nI would like to propose to re-purpose `--unroll-count` to apply only to procedural loops, and add a new option (`--unroll-max` maybe?) with a very large default value (16K, which is the current default for generate+simulate usage?) that is only used for infinite loop detection (gen loops, V3Simulate, unroll_full pragma usage).\"\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/verilator_verilator_pr6668", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/verilator_verilator_pr6668.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/verilator_verilator_pr6668", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/verilator_verilator_pr6668"}
{"instance_id": "verilator_verilator_pr6697", "issue_text": "# Incorrect `streaming_concatenation`\n\n- Source URL: https://github.com/verilator/verilator/issues/6693\n\n> Thanks for taking the time to report this.\n> Can you please attach an example that shows the issue or missing feature?  (Must be openly licensed, completely self-contained so can directly run what you provide. Ideally use test_regress format, see https://veripool.org/guide/latest/contributing.html?highlight=test_regress#reporting-bugs)\n\nHere is code that reproduces the bug\n\n```sv\nmodule top;\n    logic [7:0] b = 8'hA5;\n    logic [31:0] y;\n    \n    // The problematic assignment\n    always_comb begin\n        y = {<<{b}};  // Should place result in MSBs, zeros in LSBs\n    end\n    \n    initial begin\n        #10; \n        \n        $display(\"Input b = %h (%b)\", b, b);\n        $display(\"Output y = %h (%b)\", y, y);\n        $display(\"\");\n        $display(\"According to IEEE 1800-2023:\");\n        $display(\"  Stream should be in MSBs: %h\", {b, 24'b0});\n        $display(\"  Zeros should be in LSBs\");\n        $display(\"\");\n        $display(\"Verilator result: %h\", y);\n        $display(\"Expected result:  %h\", {b, 24'b0});\n        $display(\"\");\n        \n        if (y == {b, 24'b0}) begin\n            $display(\"PASS: Verilator is correct\");\n        end else begin\n            $display(\"FAIL: Verilator bug - stream placed in LSBs instead of MSBs\");\n            $display(\"   Got: %h\", y);\n            $display(\"   Expected: %h\", {b, 24'b0});\n        end\n        \n        $finish;\n    end\nendmodule\n```\n\n> What output from that test indicates it is wrong, and what is the correct or expected output?  (Or, please make test self-checking if possible.)\n\nThe IEEE 1800-2023 in 11.4.14 specifies that \n>> If the target represents a fixed-size variable that is wider than the stream, the stream shall be widened to match it by filling with zero bits on the right.\n\n> What 'verilator' command line do we use to run your example?\n\n```sh\nverilator --binary --exe --build -Mdir obj_dir -sv --timing -Wno-WIDTHEXPAND top.sv && ./obj_dir/Vtop\n```\n\n> What 'verilator --version' are you using?  Did you try it with the git master version?  Did you try it with other simulators?\n\nI am using git upstream version `Verilator 5.043 devel rev v5.042-59-gf32095dd1`. All other simulators I tried it on succeeded.\n\n> What OS and distribution are you using?\n\nLinux arch\n\n> May we assist you in trying to fix this in Verilator yourself?\n\nI think this should not be too complicated to fix, so I wouldn't mind trying to fix it.\n\n> (Please avoid attaching screenshots that show text - you can convert images to text using e.g. https://ocr.space)\n\nWhen checking for open issues that contained the word `streaming` I did not have the impression that they explicitly mentionned that the result was incorrect compared to the IEEE. Sorry if this is a duplicate.\nThanks for the work on verilator !\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/verilator_verilator_pr6697", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/verilator_verilator_pr6697.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/verilator_verilator_pr6697", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/verilator_verilator_pr6697"}
{"instance_id": "verilator_verilator_pr6723", "issue_text": "# X input values are not handled correctly in UDPs\n\n- Source URL: https://github.com/verilator/verilator/issues/6722\n\nTo reproduce:\n\n```verilog\nmodule t ();\n\n   wire true;\n   not1 a(true, '0);\n\n   wire false;\n   not1 b(false, '1);\n\n   initial begin\n      if (true != '1) $stop;\n      if (false != '0) $stop;\n      $finish;\n   end\n\nendmodule // t\n\nprimitive not1 (q, d);\n   output q;\n   input  d;\n   table\n      0 : 1;\n      1 : 0;\n      x : x;\n   endtable\nendprimitive // not1\n```\n\nAnd the test driver code:\n\n```python3\nimport vltest_bootstrap\ntest.scenarios('vlt_all')\ntest.compile()\ntest.execute()\ntest.passes()\n```\n\nThe expected result is that the `true` and `false` wires will be 1 and 0, respectively. However, they are both set to X (depending on the value of the `--x-assign` command-line argument).\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/verilator_verilator_pr6723", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/verilator_verilator_pr6723.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/verilator_verilator_pr6723", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/verilator_verilator_pr6723"}
{"instance_id": "verilator_verilator_pr6737", "issue_text": "# Support complex std::randomize patterns using args replacement strategy (#6736)\n\nInstance: verilator_verilator_pr6737\nSource: https://github.com/verilator/verilator/pull/6737\nFetched: 2026-05-03\nRepository: verilator/verilator\nPull request: #6737\nAuthor: YilouWang\nState: closed\nBase branch: master\nHead branch: fix/std-randomize-foreach-arraysel\nCreated: 2025-11-26\nUpdated: 2025-12-01\nClosed: 2025-12-01\nMerged: 2025-12-01\n\n## PR Title\nSupport complex std::randomize patterns using args replacement strategy (#6736)\n\n## PR Description\nImplements an argument-replacement strategy for `std::randomize()` that supports:\n\n1. Array-element arguments (e.g. `std::randomize(arr[i])` inside `foreach` loops)\n2. Mixed argument types (`VarRef`, `MemberSel`, `ArraySel` in the same call)\n\nMechanically:\n- All arguments are replaced with `__Varg*` reference parameters\n- A `similarNode` matching predicate is added so semantic equality works across the three node types\n- `__Varg*` are excluded from being re-captured by `CaptureVisitor`\n- Null-pointer guards are added for robustness\n\nCloses issue #6736 (\"Support ArraySel in foreach case and Mixed arguments types case in std::randomize\"). 31 commits in total. Coverage at merge: 100% line, 75% branch.\n\n## PR Comments\nThe conversation contained iterative review feedback between YilouWang and the maintainers (wsnyder, udayaa-init) over the late-Nov / early-Dec window. The author addressed all review threads before wsnyder merged on Dec 1, 2025; 73 checks passed.\n\n## Linked Issues\n**Issue #6736 - \"Support 'ArraySel in foreach' case and 'Mixed arguments types' case in std::randomize\"** (closed by this PR).\n\nIssue body (verbatim from the source URL):\n\"Following PR #6719 , we found issues while testing other cases.\nCurrently, there are two cases that are problematic:\n\n1. ArraySel in foreach loop\n2. VarRef/MemberSel/ArraySel mixed case\n\nThe issues stem from how arguments are handled in std::randomize().\"\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/verilator_verilator_pr6737", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/verilator_verilator_pr6737.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/verilator_verilator_pr6737", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/verilator_verilator_pr6737"}
{"instance_id": "verilator_verilator_pr6815", "issue_text": "# Inline small CFuncs to reduce function call overhead\n\nInstance: verilator_verilator_pr6815\nSource: https://github.com/verilator/verilator/pull/6815\nFetched: 2026-05-03\nRepository: verilator/verilator\nPull request: #6815\nAuthor: 10U-Labs (contributor)\nState: closed\nBase branch: master\nHead branch: inline-cfuncs\nCreated: 2025-12-14\nUpdated: 2025-12-21\nClosed: 2025-12-21\nMerged: 2025-12-21\n\n## PR Title\nInline small CFuncs to reduce function call overhead\n\n## PR Description\nAdds two new command-line options - `--inline-cfuncs <n>` (default 20) and `--inline-cfuncs-product <n>` (default 200) - that let Verilator inline small CFunc calls directly into their callers, eliminating function-call overhead when `--output-split-cfuncs` puts callees in a separate translation unit that the C++ compiler cannot inline across.\n\nInlining criteria: function size <= n nodes (always inline), or size * call_count <= product threshold; the function must contain no `$c()` statements, return `void`, and be in the same scope as its callers. Local variables are cloned with unique names (`__Vinline_<func>_<var>`). The optimisation is automatically disabled by `--prof-cfuncs` or `--trace`.\n\nThis PR supersedes #6765, with the implementation moved out of `V3OrderCFuncEmitter` into a separate `V3InlineCFuncs` pass; `--inline-cfuncs` was changed from a boolean flag into a numeric threshold; variable merging was added; and `V3Stats` tracks \"Optimizations, Inlined CFuncs\". Coverage at merge: 100% line (80/80), 88.46% branches (46/52).\n\n## PR Comments\nThe maintainer requested allowing inlining of functions with local variables (rather than excluding them) and suggested using two tunable thresholds for flexibility - the author implemented both. Multiple test cases were added to cover enabled/disabled states and threshold behavior. Merged on Dec 21, 2025.\n\n## Linked Issues\n**Issue #2367 - \"Optimize short Active blocks inline into _eval\"** (closed by this PR).\n\nIssue body (verbatim from the source URL):\n\"EH1 has a lot of examples where a sequent CFunc contains only a handful ot statements (often 1 or 2) and is called only once. This causes a performance penalty when --output-split puts these in a different function than _eval and hence the compiler can't inline them, so we should inline these ourselve when it's obviously the right thing to do.\"\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/verilator_verilator_pr6815", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/verilator_verilator_pr6815.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/verilator_verilator_pr6815", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/verilator_verilator_pr6815"}
{"instance_id": "verilator_verilator_pr6822", "issue_text": "# Chisel 7.3.0 generated Mux1H simulates slower than Chisel 6\n\n- Source URL: https://github.com/verilator/verilator/issues/6760\n\nCan you please attach an example that shows the issue or missing feature?\n\nPlease see: https://github.com/cyyself/verilator-chisel7-regression\n\nWe discovered a significant performance regression in Verilator simulation when using Chisel 7 compared to Chisel 6 for designs that utilize `Mux1H` with a large number of inputs with LLVM-19.\n\n```scala\nclass Test extends RawModule {\n  val width = 7 // 2**7 = 128 entries\n  val io = IO(new Bundle {\n    val in = Input(Vec((1 << width), UInt(32.W)))\n    val sel = Input(UInt(width.W))\n    val out = Output(UInt(32.W))\n  })\n\n  val sel = UIntToOH(io.sel, 1 << width)\n  io.out := Mux1H(sel, io.in)\n}\n```\n\nIn Chisel 6.7.0, the Verilog will be like:\n\n```systemverilog\n  assign io_out =\n    (io_sel == 7'h0 ? io_in_0 : 32'h0) | (io_sel == 7'h1 ? io_in_1 : 32'h0)\n    | (io_sel == 7'h2 ? io_in_2 : 32'h0) | (io_sel == 7'h3 ? io_in_3 : 32'h0)\n    | (io_sel == 7'h4 ? io_in_4 : 32'h0) | (io_sel == 7'h5 ? io_in_5 : 32'h0)\n    | (io_sel == 7'h6 ? io_in_6 : 32'h0) | (io_sel == 7'h7 ? io_in_7 : 32'h0)\n    | (io_sel == 7'h8 ? io_in_8 : 32'h0) | (io_sel == 7'h9 ? io_in_9 : 32'h0)\n    // ... snip ...\n```\nIn Chisel 7.3.0, the Verilog will be like:\n\n```systemverilog\n  wire [127:0] sel = 128'h1 << io_sel;\t// src/main/scala/chisel3/util/OneHot.scala:65:12\n  assign io_out =\n    (sel[0] ? io_in_0 : 32'h0) | (sel[1] ? io_in_1 : 32'h0) | (sel[2] ? io_in_2 : 32'h0)\n    | (sel[3] ? io_in_3 : 32'h0) | (sel[4] ? io_in_4 : 32'h0) | (sel[5] ? io_in_5 : 32'h0)\n    | (sel[6] ? io_in_6 : 32'h0) | (sel[7] ? io_in_7 : 32'h0) | (sel[8] ? io_in_8 : 32'h0)\n    | (sel[9] ? io_in_9 : 32'h0) | (sel[10] ? io_in_10 : 32'h0)\n    // ... snip ...\n```\n\nIt has no difference in functionality, but let's look at the Verilator output for both versions.\n\nIn Chisel 6.7.0, Verilator generates the following code:\n\n```cpp\n    vlSelfRef.Test__DOT____VdfgBinToOneHot_Tab_h807d22cc_0_0[vlSelfRef.Test__DOT____VdfgBinToOneHot_Pre_h807d22cc_0_0] = 0U;\n    vlSelfRef.Test__DOT____VdfgBinToOneHot_Tab_h807d22cc_0_0[vlSelfRef.io_sel] = 1U;\n    vlSelfRef.Test__DOT____VdfgBinToOneHot_Pre_h807d22cc_0_0 \n        = vlSelfRef.io_sel;\n    __Vdeeptemp_h9151389e__0 = ((vlSelfRef.Test__DOT____VdfgBinToOneHot_Tab_h807d22cc_0_0\n                                 [9U] ? vlSelfRef.io_in_9\n                                  : 0U) | ((vlSelfRef.Test__DOT____VdfgBinToOneHot_Tab_h807d22cc_0_0\n                                            [0x0aU]\n                                             ? vlSelfRef.io_in_10\n                                             : 0U) \n                                           | ((vlSelfRef.Test__DOT____VdfgBinToOneHot_Tab_h807d22cc_0_0\n                                               [0x0bU]\n                                                ? vlSelfRef.io_in_11\n                                                : 0U) \n```\n\nIn Chisel 7.3.0, Verilator generates the following code:\n\n```cpp\n    __Vtemp_1[0U] = 1U;\n    __Vtemp_1[1U] = 0U;\n    __Vtemp_1[2U] = 0U;\n    __Vtemp_1[3U] = 0U;\n    VL_SHIFTL_WWI(128,128,7, __Vtemp_2, __Vtemp_1, (IData)(vlSelfRef.io_sel));\n    __Vtemp_3[0U] = 1U;\n    __Vtemp_3[1U] = 0U;\n    __Vtemp_3[2U] = 0U;\n    __Vtemp_3[3U] = 0U;\n    VL_SHIFTL_WWI(128,128,7, __Vtemp_4, __Vtemp_3, (IData)(vlSelfRef.io_sel));\n    __Vtemp_5[0U] = 1U;\n    __Vtemp_5[1U] = 0U;\n    __Vtemp_5[2U] = 0U;\n    __Vtemp_5[3U] = 0U;\n    VL_SHIFTL_WWI(128,128,7, __Vtemp_6, __Vtemp_5, (IData)(vlSelfRef.io_sel));\n    __Vtemp_7[0U] = 1U;\n    __Vtemp_7[1U] = 0U;\n    __Vtemp_7[2U] = 0U;\n    __Vtemp_7[3U] = 0U;\n    // ... snip ...\n```\n\nand Then:\n\n\n```cpp\n    __Vdeeptemp_h20de80fe__0 = (((0x00000400U & __Vtemp_20[0U])\n                                  ? vlSelfRef.io_in_10\n                                  : 0U) | (((0x00000800U \n                                             & __Vtemp_22[0U])\n                                             ? vlSelfRef.io_in_11\n                                             : 0U) \n                                           | (((0x00001000U \n                                                & __Vtemp_24[0U])\n                                                ? vlSelfRef.io_in_12\n                                                : 0U) \n    // ... snip ...\n```\n\nAs we can see, in Chisel 6.7.0, Verilator is able to optimize the Mux1H implementation into a simple array lookup, while in Chisel 7.3.0, Verilator generates a lot of shift operations and bitwise AND operations, which significantly increases the complexity of the generated code and leads to performance degradation during simulation.\n\nAs a result, let's look at the `analyze/chisel6.s` and `analyze/chisel7.s` files:\n\n```asm\nvoid VTest___024root___ico_sequent__TOP__0(VTest___024root* vlSelf) {\n     b40:\t55                   \tpush   %rbp\n# ... snip ...\n    285c:\te9 01 ee ff ff       \tjmp    1662 <_Z37VTest___024root___ico_sequent__TOP__0P15VTest___024root+0xb22>\n```\n\nThe code size is only `0x1d1c` bytes for Chisel 6.7.0, while for Chisel 7.3.0:\n\n```asm\nvoid VTest___024root___ico_sequent__TOP__0(VTest___024root* vlSelf) {\n     b10:\t55                   \tpush   %rbp\n    bbca:\teb b4                \tjmp    bb80 <_Z37VTest___024root___ico_sequent__TOP__0P15VTest___024root+0xb070>\n```\n\nThe code size is `0xb0ba` bytes for Chisel 7.3.0, which is more then **6x** larger than Chisel 6.7.0.\n\nWhat 'verilator' command line do we use to run your example?\n\n```bash\nverilator --build -O3 --cc rtl/chisel6/Test.sv --CFLAGS \"-O3 -g\"\nverilator --build -O3 --cc rtl/chisel7/Test.sv --CFLAGS \"-O3 -g\"\n```\n\nWhat 'verilator --version' are you using?  Did you try it with the git master version?  Did you try it with other simulators?\n\nSelf-compiled from the recent master branch 18dd44e97.\n\nWhat OS and distribution are you using?\n\nDebian sid.\n\nMay we assist you in trying to fix this in Verilator yourself?\n\nYes!\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/verilator_verilator_pr6822", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/verilator_verilator_pr6822.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/verilator_verilator_pr6822", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/verilator_verilator_pr6822"}
{"instance_id": "verilator_verilator_pr6823", "issue_text": "# Fix process reference giving no return statement error\n\n- Source URL: https://github.com/verilator/verilator/issues/6767\n\nThe below, rewritten from UVM tests/10resources/90Mantis/4666_no_process results in a compile-time error:\n\n```\nIn file included from Vt_0__ALL.cpp:4:\nVt_0___024root__0.cpp: In function â\\200\\230VlCoroutine Vt_0___024root___eval_initial__TOP__Vtiming__0(Vt_0___024root*, VlProcessRef)â\\200\\231:\nVt_0___024root__0.cpp:25:1: error: no return statement in function returning non-void [-Werror=return-type]\n```\n\n```\npackage uvm_pkg;\n  class uvm_object;\n  endclass\n\n  class uvm_config_db;\n    static uvm_object m_rsc[int];\n    static function void set(int cntxt);\n      if (!m_rsc.exists(cntxt)) begin\n        m_rsc[cntxt] = new;\n      end\n    endfunction\n  endclass\n\n  virtual class uvm_process_guard_base extends uvm_object;\n    protected process m_target_process;\n    function new(string name);\n      m_target_process = process::self();\n    endfunction\n  endclass\n\nendpackage\n\nmodule t;\n  import uvm_pkg::*;\n  int a;\n  assign a = something();\n  // verilator lint_off NORETURN\n  function int something();\n    uvm_config_db::set(1);\n    return 0;\n  endfunction\nendmodule\n```\n\nMight be related to #6106\n\n@RRozak et al, might you get a chance to look into this?  Thanks.\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/verilator_verilator_pr6823", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/verilator_verilator_pr6823.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/verilator_verilator_pr6823", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/verilator_verilator_pr6823"}
{"instance_id": "verilator_verilator_pr6833", "issue_text": "# Fix member-selected variable must have randmode\n\n- Source URL: https://github.com/verilator/verilator/issues/6800\n\n@YilouWang thanks for last fix, alas the same uvm-test tests/70regs/80examples/01model/30nofield got further but now resulted in a new error:\n\n```\n%Error: Internal Error: t/t_0.v:41:31: ../V3Randomize.cpp:901: Member-selected variable must have randmode in its class\n   41 |     constraint _dummy_is_reg {_dummy.value == value;}\n      |                               ^~~~~~\n```\n\nRewritten test:\n\n```\npackage uvm_pkg;\n  virtual class uvm_object;\n  endclass\n\n  class uvm_sequence_item;\n  endclass\n\n  virtual class uvm_sequencer_param_base;\n    function void send_request(uvm_sequence_item t);\n      uvm_sequence_item par;\n      if (0 == par.randomize()) begin\n      end\n    endfunction\n  endclass\n\n  class uvm_reg_item extends uvm_sequence_item;\n    rand uvm_object extension;\n  endclass\n\n  class uvm_reg_field extends uvm_object;\n    rand int value;\n    virtual function bit get_rand_mode();\n      return bit'(value.rand_mode());\n    endfunction\n  endclass\n\nendpackage\n\nprogram t;\n  import uvm_pkg::*;\n\n  class reg_r extends uvm_object;\n    rand int value;\n    local rand uvm_reg_field _dummy;\n    constraint _dummy_is_reg {_dummy.value == value;}\n  endclass\n\n  initial begin\n    reg_r r;\n    r = new;\n    $finish;\n  end\nendprogram\n```\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/verilator_verilator_pr6833", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/verilator_verilator_pr6833.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/verilator_verilator_pr6833", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/verilator_verilator_pr6833"}
{"instance_id": "verilator_verilator_pr6842", "issue_text": "# Control file lint_off  can be turned back on by source metacomment\n\n- Source URL: https://github.com/verilator/verilator/issues/6836\n\nGiven this `.vlt` file, one might expect there will be no FOO warnings from `file.sv` at all.\n\n```\n`verilator_config\nlint_off -rule FOO -file \"file.sv\"\n```\n\nHowever, if file.sv looks like this:\n\n```systemverilog\n   int a;\n   /* verilator lint_off FOO */\n   int b;\n   /* verilator lint_on FOO */\n   int c;\n```\n\nThe `lint_on` in the code turns the warning back on for the rest of the lines following it, effectively ignoring the directive from the control file.\n\nDon't think this is intentional. Can we make the effect of the control files sticky? I suspect that needs a second bitset in the message enable sets that are only affected by the control file directives, which should be ok.\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/verilator_verilator_pr6842", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/verilator_verilator_pr6842.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/verilator_verilator_pr6842", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/verilator_verilator_pr6842"}
{"instance_id": "verilator_verilator_pr6861", "issue_text": "# Support write to virtual interface in `if`\n\n- Source URL: https://github.com/verilator/verilator/issues/6558\n\nThe sv-tests easyUVM test is currently failing with this message:\n\n```\n%Error-UNSUPPORTED: sv-tests/third_party/tests/easyUVM/driver.sv:14:64: Unsupported: Write to virtual interface in if condition\n                                                                                             : ... note: In instance '$unit::driver'\n```\n\nThis can be recreated by running in a sv-test checkout:\n\n```\n$VERILATOR_ROOT/bin/verilator --binary -Wno-fatal third_party/tests/uvm/src/uvm_pkg.sv third_party/tests/easyUVM/top.sv -Ithird_party/tests/uvm/src -Ithird_party/tests/easyUVM\n```\n\nLooking at the code, if I simply comment out [the warning call in V3SchedVirtIface.cpp](https://github.com/verilator/verilator/blob/9dfc050fb508f350ebaa9db055ab7c33df73ec82/src/V3SchedVirtIface.cpp#L177) the test passes, but I don't know if the test is even testing the needed interface if.\n\n@kbieganski it looks like you gave a good amount of thought to the AstNodeIf visitor there, perhaps you could make a pull to support this?\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/verilator_verilator_pr6861", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/verilator_verilator_pr6861.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/verilator_verilator_pr6861", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/verilator_verilator_pr6861"}
{"instance_id": "verilator_verilator_pr6870", "issue_text": "# Support vpiSigned (#6868)\n\nInstance: verilator_verilator_pr6870\nSource: https://github.com/verilator/verilator/pull/6870\nFetched: 2026-05-03\nRepository: verilator/verilator\nPull request: #6870\nAuthor: ktbarrett\nState: closed\nBase branch: master\nHead branch: implement-vpiSigned\nCreated: 2025-12-29\nUpdated: 2025-12-30\nClosed: 2025-12-30\nMerged: 2025-12-30\n\n## PR Title\nSupport vpiSigned (#6868)\n\n## PR Description\nCloses issue #6868: implements the `vpiSigned` property on `vpiReg` and `vpiNet` objects so that callers can query whether a Verilog signal is signed via `vpi_get(vpiSigned, handle)`.\n\n## PR Comments\n**ktbarrett** (Dec 29, 2025): \"Closes #6868.\"\n\n**wsnyder** (Dec 29, 2025, title change): Renamed the PR title from \"Implement vpiSigned\" to \"Support vpiSigned (#6868)\".\n\n**wsnyder** (Dec 29, 2025, review): \"Great, exactly. Note there were CI test failures that need fixing (if you 'make format' and push they will be more obvious in the github web).\"\n\n**wsnyder** (Dec 29, 2025): \"BTW if you want this in the next release we'll need it by 12/30 (tomorrow).\"\n\n**ktbarrett** (Dec 29, 2025): \"Got a bit overzealous testing `vpi_get_str` which doesn't define a result on error.\"\n\nMerged on Dec 30, 2025 with 53 checks passed; included in Verilator 5.044 (released Jan 1, 2026).\n\n## Linked Issues\n**Issue #6868 - \"`vpiSigned` property not implemented\"** (closed by this PR).\n\nIssue body (verbatim from the source URL):\n\"The `vpiSigned` property available on `vpiReg` and `vpiNet` objects is not implemented.\n\n```\nauto handle = vpi_handle_by_name(\\\"top.signal\\\", nullptr);\nint signed = vpi_get(vpiSigned, handle);\n```\"\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/verilator_verilator_pr6870", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/verilator_verilator_pr6870.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/verilator_verilator_pr6870", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/verilator_verilator_pr6870"}
{"instance_id": "verilator_verilator_pr6876", "issue_text": "# Config file for lint_off/on - selecting rules\n\n- Source URL: https://github.com/verilator/verilator/issues/4185\n\nI am trying to use Verilator with a subset of lint rules. Say I want only WIDTHEXPAND to be flagged. I create a .vlt file as below:\r\n\r\n```config\r\n\r\n`verilator_config\r\nlint_off \r\nlint_on -rule WIDTHEXPAND \r\n```\r\nBut I don't get any warning on a code as below:\r\n```verilog\r\nmodule m;\r\n  wire [3:0] bits_4;\r\n  wire [7:0] bits_8;\r\n  assign bits_8 = bits_4;\r\nendmodule \r\n\r\n```\r\nIf I add a global lint_on as shown below, it works. \r\n```config\r\n\r\n`verilator_config\r\nlint_off \r\nlint_on -rule WIDTHEXPAND \r\nlint_on\r\n```\r\n\r\nLog:\r\n```log\r\n%Warning-WIDTHEXPAND: ../sv_tests/af_sv_mod.sv:6:17: Operator ASSIGNW expects 8 bits on the Assign RHS, but Assign RHS's VARREF 'bits_4' generates 4 bits.\r\n```\r\nSo my question is - how do I turn-off all rules and selectively enable a few?\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/verilator_verilator_pr6876", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/verilator_verilator_pr6876.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/verilator_verilator_pr6876", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/verilator_verilator_pr6876"}
{"instance_id": "verilator_verilator_pr6882", "issue_text": "# Internal Error: ../V3Scope.cpp:69: Can't locate package scope\n\n- Source URL: https://github.com/verilator/verilator/issues/6741\n\nThanks for taking the time to report this.\n\nCan you please attach an example that shows the issue or missing feature?  (Must be openly licensed, completely self-contained so can directly run what you provide. Ideally use test_regress format, see https://veripool.org/guide/latest/contributing.html?highlight=test_regress#reporting-bugs)\n\n```\nmodule tb_fifo_2in;\n  parameter int unsigned DEPTH = 8;\n  parameter int unsigned DATA_W = 32;\n  parameter int unsigned RUN_CYCLES = 50_000;\n  typedef logic [DATA_W-1:0] data_t;\n  logic clk;\n  logic full, not_full;\n  logic        enq0, enq1, deq;\n   data_t      enq0_data; \n  data_t golden_queue[$];\n  task automatic push(input data_t data, input string port);\n    golden_queue.push_back(data);\n  endtask\n  class Transaction;\n    rand bit        enq0;\n    rand bit        enq1;\n    rand bit        deq;\n    rand data_t     enq0_data;\n    constraint valid_enq {\n      if (golden_queue.size() >= DEPTH) {\n        enq0 == 0;\n        enq1 == 0;\n      } else if (golden_queue.size() == DEPTH-1) {\n\t(enq0 && enq1) == 0;\n      }\n      if (golden_queue.size() == 0) {\n        deq == 0;  \n      }\n    }\n  endclass\n  Transaction tr;\n  initial begin\n    tr = new();\n    repeat (RUN_CYCLES) begin\n      @(posedge clk);\n      if (tr.randomize() == 0) begin\n        $error(\"Randomization failed!\");\n        break;\n      end\n      enq0 <= tr.enq0;\n      deq  <= tr.deq;\n      enq0_data <= tr.enq0 ? tr.enq0_data : 'x;\n      if (tr.enq0 && not_full) begin\n        push(tr.enq0_data, \"P0\");\n      end\n    end\n    $finish; \n  end\n  property p_full_flag;\n    @(posedge clk)  \n    full == (golden_queue.size() == DEPTH);\n  endproperty\nendmodule\n```\n\nWhat output from that test indicates it is wrong, and what is the correct or expected output?  (Or, please make test self-checking if possible.)\n\n```\nverilator --binary test.sv\n%Error: Internal Error: test4.sv:20:11: ../V3Scope.cpp:69: Can't locate package scope\n                                      : ... note: In instance 'tb_fifo_2in.Transaction'\n   20 |       if (golden_queue.size() >= DEPTH) {\n      |           ^~~~~~~~~~~~\n                        ... See the manual at https://verilator.org/verilator_doc.html?v=5.043 for more assistance.\n```\n\nWhat 'verilator' command line do we use to run your example?\n\n```\nverilator --binary test.sv\n```\n\nWhat 'verilator --version' are you using?  Did you try it with the git master version?  Did you try it with other simulators?\n\n```\nVerilator 5.043 devel rev v5.042-110-gf2e05bc0b\n```\n\nWhat OS and distribution are you using?\n\n```\nLinux 5.14.0-570.37.1.el9_6.x86_64\n```\n\nMay we assist you in trying to fix this in Verilator yourself?\n\n(Please avoid attaching screenshots that show text - you can convert images to text using e.g. https://ocr.space)\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/verilator_verilator_pr6882", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/verilator_verilator_pr6882.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/verilator_verilator_pr6882", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/verilator_verilator_pr6882"}
{"instance_id": "wallento_wb2axi_pr4", "issue_text": "# Fix AxSIZE calculation\n\nInstance: wallento_wb2axi_pr4\nSource: https://github.com/wallento/wb2axi/pull/4\nFetched: 2026-05-03\nRepository: wallento/wb2axi\nPull request: #4\nAuthor: wallento\nState: closed\nBase branch: master\nHead branch: axsize\nCreated: 2019-05-24\nUpdated: 2019-05-25\nClosed: 2019-05-25\nMerged: 2019-05-25\n\n## PR Title\nFix AxSIZE calculation\n\n## PR Description\n\"Fixes #2\"\n\nThe change replaces the buggy `DATA_WIDTH >> 4` calculation for the AXI `AWSIZE`/`ARSIZE` registers with `$clog2(DATA_WIDTH)-3`, so the encoded transfer size is correct for data widths other than 32 bits.\n\n## PR Comments\n**wallento** (May 24, 2019): \"Fixes #2\"\n\nSingle commit (e44618a) with the same message. The branch `axsize` was deleted on May 25, 2019. No reviews, assignees, labels, or milestones.\n\n## Linked Issues\n**Issue #2 - \"Wrong AxSIZE\"** (closed by this PR).\n\nIssue body (verbatim from the source URL):\n\"The core defines the AXI AWSIZE and ARSIZE registers as the DATA_WIDTH >> 4.  For the given data width of 32 bits, this would be 2, the correct answer.  However, for a data width of 64, this would be 4--the wrong answer.  Similarly for a data width of 16 bits, the data width should be 1, not 0.\n\nThe correct AxSIZE value should be $clog2(DATA_WIDTH)-3.\"\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/wallento_wb2axi_pr4", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/wallento_wb2axi_pr4.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/wallento_wb2axi_pr4", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/wallento_wb2axi_pr4"}
{"instance_id": "xlsynth_bedrock-rtl_pr766", "issue_text": "# Allow credit counter to support >=32bit max values/changes.\n\nInstance: xlsynth_bedrock-rtl_pr766\nSource: https://github.com/xlsynth/bedrock-rtl/pull/766\nFetched: 2026-05-03\nRepository: xlsynth/bedrock-rtl\nPull request: #766\nAuthor: mattskl-openai\nState: closed\nBase branch: main\nHead branch: large_credits\nCreated: 2025-06-17\nUpdated: 2025-06-17\nClosed: 2025-06-17\nMerged: 2025-06-17\n\n## PR Title\nAllow credit counter to support >=32bit max values/changes.\n\n## PR Description\n\"fixes #751\" - the credit counter now supports MaxValue / MaxChange values that need more than 32 bits of width, instead of silently being capped by an `int` typed parameter. The PR also allows `bin2onehot` to be 1 and reverts the demux bin default to 2.\n\n## PR Comments\n**mattskl-openai** (Jun 17, 2025, 17:19): Pushed 2 commits with messages:\n- \"Also allow bin2onehot to be 1. Revert demux bin default to 2.\"\n- \"Allow credit counter to support >=32bit max values/changes.\"\n\n**mattskl-openai** (Jun 17, 2025, 17:31): Requested reviews from masai-openai and zhemao-openai.\n\n**zhemao-openai** (Jun 17, 2025): Approved.\n\n**masai-openai** (Jun 17, 2025): Approved.\n\n**mattskl-openai** (Jun 17, 2025, 18:05): Enabled auto-merge (squash); merged at commit 2697797.\n\n**mattskl-openai** (Jun 17, 2025, 18:06): Deleted the `large_credits` branch.\n\nThis PR was followed up by:\n- PR #767: Update FV env to allow MaxValWidth, MaxChangeWidth override\n- PR #768: Update FV `br_credit_counter` to allow MaxValWidth, MaxChangeWidth override\n\n## Linked Issues\n**Issue #751 - \"br_credit_counter needs to have width defined for MaxValue\"** (closed by this PR).\n\nIssue body (verbatim from the source URL):\n\"Currently defined as `int`, so it caps at 2^31-1\"\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/xlsynth_bedrock-rtl_pr766", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/xlsynth_bedrock-rtl_pr766.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/xlsynth_bedrock-rtl_pr766", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/xlsynth_bedrock-rtl_pr766"}
{"instance_id": "xlsynth_bedrock-rtl_pr785", "issue_text": "# Change br_flow_serializer's SerializeMostSignificantFirst param default to 0, matching deserializer default\n\nInstance: xlsynth_bedrock-rtl_pr785\nSource: https://github.com/xlsynth/bedrock-rtl/pull/785\nFetched: 2026-05-03\nRepository: xlsynth/bedrock-rtl\nPull request: #785\nAuthor: mgottscho\nState: closed\nBase branch: main\nHead branch: mgottscho/770\nCreated: 2025-07-22\nUpdated: 2025-07-22\nClosed: 2025-07-22\nMerged: 2025-07-22\n\n## PR Title\nChange br_flow_serializer's SerializeMostSignificantFirst param default to 0, matching deserializer default\n\n## PR Description\n\"Fixes #770\"\n\nThe PR changes the default value of `br_flow_serializer`'s `SerializeMostSignificantFirst` parameter from 1 to 0 so that it matches the default of `br_flow_deserializer`'s `DeserializeMostSignificantFirst`, restoring the property that the two blocks compose correctly with default parameters.\n\n## PR Comments\n**mgottscho** (Jul 22, 2025, 21:22): Requested review from obowen-openai; self-assigned the PR; added the \"bug\" label.\n\n**obowen-openai** (Jul 22, 2025): Approved the changes.\n\n**mgottscho** (Jul 22, 2025, 21:33): Merged at commit 8de00d5; deleted the `mgottscho/770` branch.\n\n17 checks passed.\n\n## Linked Issues\n**Issue #770 - \"Flow serializer and deserializer have opposite defaults for MostSignificantFirst\"** (closed by this PR).\n\nIssue body (verbatim from the source URL):\n\"br_flow_serializer has `DeserializeMostSignificantFirst = 0`,\nbr_flow_deserializer has `SerializeMostSignificantFirst = 1`\n\nThese two blocks should be compatible with one another by default.\"\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/xlsynth_bedrock-rtl_pr785", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/xlsynth_bedrock-rtl_pr785.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/xlsynth_bedrock-rtl_pr785", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/xlsynth_bedrock-rtl_pr785"}
{"instance_id": "xlsynth_bedrock-rtl_pr917", "issue_text": "# Allow br_arb_fixed to support a single requester\n\nInstance: xlsynth_bedrock-rtl_pr917\nSource: https://github.com/xlsynth/bedrock-rtl/pull/917\nFetched: 2026-05-03\nRepository: xlsynth/bedrock-rtl\nPull request: #917\nAuthor: mgottscho\nState: closed\nBase branch: main\nHead branch: mgottscho/codex/github-mention-br_arb_fixed-doesn-t-need-to-be-restricted-n\nCreated: 2025-11-05\nUpdated: 2025-11-10\nClosed: 2025-11-10\nMerged: 2025-11-10\n\n## PR Title\nAllow br_arb_fixed to support a single requester\n\n## PR Description\nRemoves the `NumRequesters >= 2` restriction so that `br_arb_fixed` and its internal implementation work correctly when `NumRequesters == 1`. Updates the fixed-priority FPV monitors to handle single-requester pass-through scenarios and generalises `arb_basic_fpv_monitor` so other downstream arbiters can re-use the same flexibility. Fixes issue #762.\n\n3 commits:\n1. Allow single requester br_arb_fixed (c1cd3b5)\n2. Manual fixes (d934dee)\n3. Fixes (29a6280)\n\n## PR Comments\n- **btowles-openai** (Nov 5, 2025): Approved.\n- **masai-openai** (Nov 6, 2025): Approved.\n- **zhemao-openai** (Nov 10, 2025): Approved.\n\nAssignee: mgottscho. Label: codex. Status at merge: 17 checks passed.\n\n## Linked Issues\n**Issue #762 - \"br_arb_fixed doesn't need to be restricted NumRequesters >= 2\"** (closed by this PR).\n\nIssue body (verbatim from the source URL):\n\"This may be true of some of the other arbiters, too. In general, it's nicer for if the arbiters work for a single input to avoid corner cases when incorporating them into other modules.\"\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/xlsynth_bedrock-rtl_pr917", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/xlsynth_bedrock-rtl_pr917.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/xlsynth_bedrock-rtl_pr917", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/xlsynth_bedrock-rtl_pr917"}
{"instance_id": "zephray_VerilogBoy_pr30", "issue_text": "# Super Mario Land hangs when entering bonus game\n\n- Source URL: https://github.com/zephray/VerilogBoy/issues/29\n\nAs you know, I use your VerilogBoy with real cartridges instead of ROM images and I ran into an issue with _Super Mario Land_ that I'm not sure where it's originating.\r\n\r\n**_Issue_**\r\n\r\nWhen _Super Mario Land_ is supposed to enter the bonus game (triggered by exiting through the upper door in level 1 and 2 or by finishing level 3), the execution of the game hangs.\r\n\r\nSo far I have determined that:\r\n\r\n- The execution is caught up in a loop between PC `0x97` and `0x9C` which is basically the following loop:\r\n\r\n```\r\nLDH A, [$FF41]\r\nADD $03\r\nJR NZ, $FA\r\n```\r\n\r\n- The loop waits for an HSYNC to occur that just won't happen.\r\n- The _stat register_ at `0xFF41` keeps a constant value of `0x41` and the PPU state stays on `s_IDLE` forever.\r\n\r\n**_Steps to reproduce_**\r\n\r\nExit level 1 or 2 through the upper door or finish level 3.\r\n\r\n**_Further considerations_**\r\n\r\nI'm not sure yet whether this is a general issue with VerilogBoy or whether this only arises when using real cartridges. It may be helpful to know if you can reproduce this behavior at all.\r\n\r\nI'll keep looking for the root cause but any suggestions on what might be the issue are very welcome 😊\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/zephray_VerilogBoy_pr30", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/zephray_VerilogBoy_pr30.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/zephray_VerilogBoy_pr30", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/zephray_VerilogBoy_pr30"}