diff --git "a/collect/lowRISC/lowRISC__ibex_s01_06_single_rtl_candidates.jsonl" "b/collect/lowRISC/lowRISC__ibex_s01_06_single_rtl_candidates.jsonl" new file mode 100644--- /dev/null +++ "b/collect/lowRISC/lowRISC__ibex_s01_06_single_rtl_candidates.jsonl" @@ -0,0 +1,89 @@ +{"repo": "lowRISC/ibex", "pr_id": 2449, "lang": "sv", "rtl_files": ["examples/simple_system/rtl/ibex_simple_system.sv"], "commit_id": "57d37bf9008640415532d23ad59018b795c642aa", "timestamp": "2026-06-09T14:34:00+00:00", "pr_title": "[simple_system] Fix initial assignment of `clk_sys`", "pr_body": "Remove the in-line initialization of the clock from the simple system, and handle the clock generation in a separate `initial` block instead.\r\n\r\nFixes https://github.com/lowRISC/ibex/issues/2447", "issue_title": "Fix ifdef VERILATOR breaking sv-tests ibex", "issue_body": "## Observed Behavior\n\nThe Ibex test that runs on Verilator as part of sv-tests at https://chipsalliance.github.io/sv-tests-results/?v=verilator+ibex+ibex\n\nfails with:\n\n```\n%Error-CONTASSINIT: build/lowrisc_ibex_ibex_simple_system_0/sim-verilator/../src/lowrisc_ibex_ibex_simple_system_core_0/rtl/ibex_simple_system.sv:68:19: Continuous assignment to variable with initial value: 'clk_sys'\n : ... note: In instance 'ibex_simple_system'\n : ... Location of variable initialization\n build/lowrisc_ibex_ibex_simple_system_0/sim-verilator/../src/lowrisc_ibex_ibex_simple_system_core_0/rtl/ibex_simple_system.sv:132:12: ... Location of continuous assignment\n ... For error description see https://verilator.org/warn/CONTASSINIT?v=5.049\n```\n\n## Expected Behavior\n\nDoes not fail.\n\n## Steps to reproduce the issue\n\nSee sv-tests for their command line.\n\n## Notes\n\nI believe this is because Verilator recently added/updated the continuous assignment error, previously this was (incorrectly) not an error. I believe that the error is correct, and is due to the `ifdef VERILATOR code around here:\n\nhttps://github.com/lowRISC/ibex/blob/2cf450db5133f6215c32d8463e65f8733e7323a3/examples/simple_system/rtl/ibex_simple_system.sv#L131\n\nit should be updated to be an always or otherwise not create IEEE-illegal code when VERILATOR is defined. Thanks.\n", "commit_message": "[simple_system] Fix initial assignment of `clk_sys`", "fix_patch": "diff --git a/examples/simple_system/rtl/ibex_simple_system.sv b/examples/simple_system/rtl/ibex_simple_system.sv\nindex 1f5e08602..fa2f6016f 100644\n--- a/examples/simple_system/rtl/ibex_simple_system.sv\n+++ b/examples/simple_system/rtl/ibex_simple_system.sv\n@@ -65,7 +65,7 @@ module ibex_simple_system (\n parameter bit BranchPredictor = 1'b0;\n parameter SRAMInitFile = \"\";\n \n- logic clk_sys = 1'b0, rst_sys_n;\n+ logic clk_sys, rst_sys_n;\n \n typedef enum logic {\n CoreD\n@@ -137,9 +137,12 @@ module ibex_simple_system (\n #8\n rst_sys_n = 1'b1;\n end\n- always begin\n- #1 clk_sys = 1'b0;\n- #1 clk_sys = 1'b1;\n+ initial begin\n+ clk_sys = 1'b0;\n+ forever begin\n+ #1 clk_sys = 1'b0;\n+ #1 clk_sys = 1'b1;\n+ end\n end\n `endif\n \n", "test_patch": "", "modified_files": ["examples/simple_system/rtl/ibex_simple_system.sv"], "lines_added": 7, "lines_removed": 4} +{"repo": "lowRISC/ibex", "pr_id": 2307, "lang": "sv", "rtl_files": ["dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_request_driver.sv"], "commit_id": "29f932486eb436d4b088c5c87794eaa057640e3f", "timestamp": "2025-08-17T19:50:55+00:00", "pr_title": "Fix #2302", "pr_body": "", "issue_title": "Verilator flags indentation warning that looks like a testbench bug", "issue_body": "I was trying to run Verilator lint on the full Ibex source code, including the testbench. I found that there was a lint warning about indentation. It actually looks like it's flagging a real bug:\n\n```\n%Warning-MISINDENT: ibex/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_request_driver.sv:87:17: Misleading indentation\n 87 | tr.intg = vif.request_driver_cb.rintg;\n | ^\n ibex/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_agent_pkg.sv:24:1: ... note: In file included from 'ibex_mem_intf_agent_pkg.sv'\n ibex/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_request_driver.sv:85:7: ... Expected indentation matching this earlier statement's line:\n 85 | if(tr.read_write == READ)\n | ^~\n ... For warning description see https://verilator.org/warn/MISINDENT?v=5.037\n ... Use \"/* verilator lint_off MISINDENT */\" and lint_on around source to disable this message.\n```\n\n## Observed Source Code Issue\n\nIn `ibex/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_request_driver.sv:87:17`:\n\n```\n if(tr.read_write == READ)\n tr.data = vif.request_driver_cb.rdata;\n tr.intg = vif.request_driver_cb.rintg;\n seq_item_port.put_response(tr);\n```\n\nThe two lines starting with `tr.` should probably both be under the if clause.\n\n## Expected Source Code\n\nThe driver should probably be fixed to have a `begin` and `end` to encapsulate these.\n\nIn `ibex/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_request_driver.sv:87:17`:\n\n```\n if(tr.read_write == READ) begin\n tr.data = vif.request_driver_cb.rdata;\n tr.intg = vif.request_driver_cb.rintg;\n end\n seq_item_port.put_response(tr);\n```\n\n## My Environment\n\n**EDA tool and version:** Verilator 5.037 devel\n\n**Operating system:** macOS 15.5 arm64\n\n**Version of the Ibex source code:** 479750353fdf2a74d507ec436028349ded1b951a\n", "commit_message": "Fix #2302", "fix_patch": "diff --git a/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_request_driver.sv b/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_request_driver.sv\nindex 6ad0a2679a..5bf7a290fe 100644\n--- a/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_request_driver.sv\n+++ b/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_request_driver.sv\n@@ -82,9 +82,10 @@ class ibex_mem_intf_request_driver extends uvm_driver #(ibex_mem_intf_seq_item);\n rdata_queue.get(tr);\n vif.wait_clks(1);\n while((vif.rvalid !== 1'b1 || vif.spurious_response === 1'b1)) vif.wait_clks(1);\n- if(tr.read_write == READ)\n+ if (tr.read_write == READ) begin\n tr.data = vif.request_driver_cb.rdata;\n tr.intg = vif.request_driver_cb.rintg;\n+ end\n seq_item_port.put_response(tr);\n end\n endtask : collect_response\n", "test_patch": "", "modified_files": ["dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_request_driver.sv"], "lines_added": 2, "lines_removed": 1} +{"repo": "lowRISC/ibex", "pr_id": 2269, "lang": "sv", "rtl_files": ["rtl/ibex_decoder.sv"], "commit_id": "594ea976c9dad793f87edf91ec1c4c1df447e6dc", "timestamp": "2025-04-25T12:57:41+00:00", "pr_title": "[rtl] Minor tweak to decoder to avoid dead code", "pr_body": "The \"else\" part of the if/else check here wasn't possible because the surrounding else branch (starting at line 406) is already in the case where instr[26] is zero.\r\n\r\nFixes #2268.", "issue_title": "[bug][ibex_decoder] Report a bug in Ibex", "issue_body": "Hi all!\n\nI am using a static analysis to found a various bugs in open source RTL designs.\n\nIt was founded that in `ibex_decoder.sv` RTL file dead code is exists [here](https://github.com/lowRISC/ibex/blob/master/rtl/ibex_decoder.sv#L439).\n\nThis assignment under `else` statement is never executed due to [this](https://github.com/lowRISC/ibex/blob/master/rtl/ibex_decoder.sv#L406) external `else` branch with `!instr[26]` condition.", "commit_message": "[rtl] Minor tweak to decoder to avoid dead code\n\nThe \"else\" part of the if/else check here wasn't possible because the\nsurrounding else branch (starting at line 406) is already in the case\nwhere instr[26] is zero.", "fix_patch": "diff --git a/rtl/ibex_decoder.sv b/rtl/ibex_decoder.sv\nindex 6e925f5651..880885575f 100644\n--- a/rtl/ibex_decoder.sv\n+++ b/rtl/ibex_decoder.sv\n@@ -433,11 +433,10 @@ module ibex_decoder #(\n end\n end\n 5'b0_0001: begin\n- if (instr[26] == 1'b0) begin // unshfl\n- illegal_insn = (RV32B == RV32BOTEarlGrey || RV32B == RV32BFull) ? 1'b0 : 1'b1;\n- end else begin\n- illegal_insn = 1'b1;\n- end\n+ // Since instr[26] is known to be 0, this must be the \"unshfl\" instruction, which\n+ // is part of the RISC-V bitmanip extension. This is supported for the\n+ // RV32BOTEarlGrey and RV32BFull bitmanip configurations.\n+ illegal_insn = (RV32B == RV32BOTEarlGrey || RV32B == RV32BFull) ? 1'b0 : 1'b1;\n end\n \n default: illegal_insn = 1'b1;\n", "test_patch": "", "modified_files": ["rtl/ibex_decoder.sv"], "lines_added": 4, "lines_removed": 5} +{"repo": "lowRISC/ibex", "pr_id": 2261, "lang": "sv", "rtl_files": ["rtl/ibex_controller.sv"], "commit_id": "6e466c1504b61333d1b2ba85c69bff94b65e9284", "timestamp": "2025-03-26T16:00:13+00:00", "pr_title": "fix: Illegal instruction display message", "pr_body": "Fix #2236 When encountering certain illegal compressed instructions, incorrect instruction information was displayed. Now, illegal instructions can be printed correctly.", "issue_title": "simulator report error", "issue_body": "\n\n## Observed Behavior\nTest ibex in verilator with cosim, simulator report error illegal instruction.\n```\n001003e8
:\n 1003e8:\t1141 \taddi\tsp,sp,-16\n 1003ea:\tc606 \tsw\tra,12(sp)\n 1003ec:\t0000 \tunimp # <--- This is the illegal instruction!\n 1003ee:\t0000 \tunimp\n 1003f0:\t37b9 \tjal\t10033e \n 1003f2:\t00000517 \tauipc\ta0,0x0\n 1003f6:\t05650513 \taddi\ta0,a0,86 # 100448 \n 1003fa:\t3959 \tjal\t100090 \n 1003fc:\t40b2 \tlw\tra,12(sp)\n 1003fe:\t4501 \tli\ta0,0\n 100400:\t0141 \taddi\tsp,sp,16\n 100402:\t8082 \tret\n```\n```\nDASM(0x00010413)\nmv s0, sp\n```\n\n![Image](https://github.com/user-attachments/assets/321158de-0306-44b2-a11b-64c2fcfc4a7f)\n\nMTVAL in `ibex_simple_system.log` file is 0x00000000\n\n\n## Expected Behavior\nThe terminal should print right mtval value.\n\n\n## Steps to reproduce the issue\nRun `build/lowrisc_ibex_ibex_simple_system_cosim_0/sim-verilator/Vibex_simple_system --meminit=ram,ibex/examples/sw/simple_system/input/test.elf`\n```\n#include \"simple_system_common.h\"\nint main(void){\n // puts(\"Starting test\");\n __asm__ volatile(\".word 0x000000\");\n puts(\"Test complete\");\n return 0;\n}\n```\n\n\n## My Environment\nBuild verilator to run ibex by [co-sim](https://ibex-core.readthedocs.io/en/latest/03_reference/cosim.html#quick-build-and-run-instructions).\n\n\n**EDA tool and version:**\nNone\n\n\n**Operating system:**\nUbuntu Linux 18.04\n\n\n**Version of the Ibex source code:**\n8f4c75c5e43e61b994248307c814e01860303056\n\n", "commit_message": "fix: Illegal instruction display message\n\nWhen encountering certain illegal compressed instructions, incorrect instruction information was displayed. Now, illegal instructions can be printed correctly.", "fix_patch": "diff --git a/rtl/ibex_controller.sv b/rtl/ibex_controller.sv\nindex 157d05a6e9..1b2666c0bc 100644\n--- a/rtl/ibex_controller.sv\n+++ b/rtl/ibex_controller.sv\n@@ -175,7 +175,7 @@ module ibex_controller #(\n // print warning in case of decoding errors\n if ((ctrl_fsm_cs == DECODE) && instr_valid_i && !instr_fetch_err_i && illegal_insn_d) begin\n $display(\"%t: Illegal instruction (hart %0x) at PC 0x%h: 0x%h\", $time, u_ibex_core.hart_id_i,\n- pc_id_i, id_stage_i.instr_rdata_i);\n+ pc_id_i, instr_is_compressed_i ? {16'b0, instr_compressed_i} : instr_i );\n end\n end\n // synopsys translate_on\n", "test_patch": "", "modified_files": ["rtl/ibex_controller.sv"], "lines_added": 1, "lines_removed": 1} +{"repo": "lowRISC/ibex", "pr_id": 2251, "lang": "sv", "rtl_files": ["rtl/ibex_core.sv"], "commit_id": "591c3812f951a4acc8014eb2d9d727936d11bf99", "timestamp": "2025-01-24T13:08:20+00:00", "pr_title": "[ibex_core] Fix assertion when SecureIbex is false", "pr_body": "This assertion wasn't quite correct if SecureIbex is false because it was checking for the magic IbexMuBiOn value instead of just looking at the bottom bit.\r\n\r\nFixes #2249.", "issue_title": "Ibex core assertion NoExecWhenFetchEnableNotOn not gated correctly.", "issue_body": "## Observed Behavior\nI'm seeing the NoExecWhenFetchEnableNotOn assertion fire inside of ibex_core.sv in a case where I'm not using the lockstep mode. I have a single instance of Ibex with the default parameters including `parameter bit SecureIbex = 1'b0,`\n\nThe assertion in question is part of the following code block:\n\n```\n // Keep track of the PC last seen in the ID stage when fetch is disabled\n logic [31:0] pc_at_fetch_disable;\n ibex_mubi_t last_fetch_enable;\n\n always_ff @(posedge clk_i or negedge rst_ni) begin\n if (!rst_ni) begin\n pc_at_fetch_disable <= '0;\n last_fetch_enable <= '0;\n end else begin\n last_fetch_enable <= fetch_enable_i;\n\n if ((fetch_enable_i != IbexMuBiOn) && (last_fetch_enable == IbexMuBiOn)) begin\n pc_at_fetch_disable <= pc_id;\n end\n end\n end\n\n // When fetch is disabled no instructions should be executed. Once fetch is disabled either the\n // ID/EX stage is not valid or the PC of the ID/EX stage must remain as it was at disable. The\n // ID/EX valid should not ressert once it has been cleared.\n `ASSERT(\n NoExecWhenFetchEnableNotOn,\n fetch_enable_i != IbexMuBiOn |=> (~instr_valid_id || (pc_id == pc_at_fetch_disable)) && ~$rose\n (instr_valid_id))\n```\n\nMy understanding from reading the documentation about `fetch_enable_i` was that I just needed to tie the LSB to 1. So I'm driving the input port to `4'b0001`. If that is correct, then it looks like this assertion shouldn't be firing. It should probably only be used when `SecureIbex == 1`?\n\nThe assertion fires for the first valid instruction fetched after reset.\n\n## Expected Behavior\nNo assertion should fire - unless I'm missing the fact that I'm doing something stupid.\n\n## Steps to reproduce the issue\nMy instantiation looks like:\n```\n ibex_top #(\n .RV32M (ibex_pkg::RV32MSlow),\n .RV32B (ibex_pkg::RV32BNone),\n .RegFile(ibex_pkg::RegFileFPGA)\n ) u_top (\n // Clock and reset\n .clk_i (clk),\n .rst_ni (!rst),\n .test_en_i ('0),\n .scan_rst_ni('0),\n .ram_cfg_i ('0),\n\n // Configuration\n .hart_id_i ('0),\n .boot_addr_i('0),\n\n // Instruction memory interface\n .instr_req_o (instr_req),\n .instr_gnt_i (instr_gnt),\n .instr_rvalid_i (instr_rvalid),\n .instr_addr_o (instr_addr),\n .instr_rdata_i (instr_rdata),\n .instr_rdata_intg_i('0),\n .instr_err_i (instr_err),\n\n // Data memory interface\n .data_req_o (data_req),\n .data_gnt_i (data_gnt),\n .data_rvalid_i (data_rvalid),\n .data_we_o (data_we),\n .data_be_o (data_be),\n .data_addr_o (data_addr),\n .data_wdata_o (data_wdata),\n .data_wdata_intg_o(),\n .data_rdata_i (data_rdata),\n .data_rdata_intg_i('0),\n .data_err_i (data_err),\n\n // Interrupt inputs\n .irq_software_i('0),\n .irq_timer_i (timer_irq),\n .irq_external_i('0),\n .irq_fast_i ('0),\n .irq_nm_i ('0),\n\n // Scrambling Interface\n .scramble_key_valid_i('0),\n .scramble_key_i ('0),\n .scramble_nonce_i ('0),\n .scramble_req_o (),\n\n // Debug interface\n .debug_req_i ('0),\n .crash_dump_o (),\n .double_fault_seen_o(),\n\n // Special control signals\n .fetch_enable_i (4'b0001),\n .alert_minor_o (),\n .alert_major_internal_o(),\n .alert_major_bus_o (),\n .core_sleep_o ()\n );\n```\n\n## My Environment\n\n**EDA tool and version:**\nCadence Xcelium 24.03\n\n**Operating system:**\nRHEL 9.5\n\n**Version of the Ibex source code:**\n8f4c75c5e43e61b994248307c814e01860303056\n", "commit_message": "[ibex_core] Fix assertion when SecureIbex is false\n\nThis assertion wasn't quite correct if SecureIbex is false because it\nwas checking for the magic IbexMuBiOn value instead of just looking at\nthe bottom bit.\n\nFixes #2249.", "fix_patch": "diff --git a/rtl/ibex_core.sv b/rtl/ibex_core.sv\nindex 67ab922466..3e19196284 100644\n--- a/rtl/ibex_core.sv\n+++ b/rtl/ibex_core.sv\n@@ -1020,13 +1020,19 @@ module ibex_core import ibex_pkg::*; #(\n end\n end\n \n- // When fetch is disabled no instructions should be executed. Once fetch is disabled either the\n+ // A 1-bit encoding of fetch_enable_i to avoid polluting the NoExecWhenFetchEnableNotOn assertion\n+ // with notes about SecureIbex and mubi values.\n+ logic fetch_enable_raw;\n+ assign fetch_enable_raw = SecureIbex ? (fetch_enable_i == IbexMuBiOn) : fetch_enable_i[0];\n+\n+ // When fetch is disabled, no instructions should be executed. Once fetch is disabled either the\n // ID/EX stage is not valid or the PC of the ID/EX stage must remain as it was at disable. The\n // ID/EX valid should not ressert once it has been cleared.\n- `ASSERT(NoExecWhenFetchEnableNotOn, fetch_enable_i != IbexMuBiOn |=>\n- (~instr_valid_id || (pc_id == pc_at_fetch_disable)) && ~$rose(instr_valid_id))\n+ `ASSERT(NoExecWhenFetchEnableNotOn,\n+ !fetch_enable_raw |=>\n+ (~instr_valid_id || (pc_id == pc_at_fetch_disable)) && ~$rose(instr_valid_id))\n \n- `endif\n+ `endif // INC_ASSERT\n \n ////////////////////////\n // RF (Register File) //\n", "test_patch": "", "modified_files": ["rtl/ibex_core.sv"], "lines_added": 10, "lines_removed": 4} +{"repo": "lowRISC/ibex", "pr_id": 2250, "lang": "sv", "rtl_files": ["rtl/ibex_register_file_fpga.sv"], "commit_id": "591c3812f951a4acc8014eb2d9d727936d11bf99", "timestamp": "2025-01-23T19:51:50+00:00", "pr_title": "[ibex_register_file_fpga] Drop two confusing comments", "pr_body": "These were noticed by someone responding to issue #2230. I think the author's original logic was to point out that there's a path from e.g. raddr_a_i to rdata_a_o which doesn't depend on any clock, so is \"asynchronous\".\r\n\r\nBut that's the same in the other modes and also for the other register file implementations, which don't have analogous comments.\r\n\r\nDrop these ones.", "issue_title": "[regfile_fpga] oh_raddr_*_err signals unassigned if RdataMuxCheck=0", "issue_body": "\n\n## Observed Behavior\nThe onehot-error signals in relation to the read addresses (`oh_raddr_a_err`, `oh_raddr_b_err`) in [rtl/ibex_register_file_fpga.sv](../blob/master/rtl/ibex_register_file_fpga.sv) are unassigned for non-secure Ibex configurations (which is for example used for opentitan FPGA top-levels IIRC):\nhttps://github.com/lowRISC/ibex/blob/667fd20d2ede51caececccbcbda3652074424ce2/rtl/ibex_register_file_fpga.sv#L152-L158\n\nThis leads to the regfile `err_o` signal becoming `x`\nhttps://github.com/lowRISC/ibex/blob/667fd20d2ede51caececccbcbda3652074424ce2/rtl/ibex_register_file_fpga.sv#L55\nwhich triggers assertions (at least for us) when simulating with the FPGA regfile. It however seems to not cause issues during synthesis, at least with Vivado.\n\nI am also unsure about the comments that refer to `rdata_*_o` as asynchronous:\nhttps://github.com/lowRISC/ibex/blob/667fd20d2ede51caececccbcbda3652074424ce2/rtl/ibex_register_file_fpga.sv#L153-L154\n\n## Expected Behavior\nSame as for the other regfile variants; signals in question being tied to `1'b0` for `RdataMuxCheck = 0`.\n\n", "commit_message": "[ibex_register_file_fpga] Drop two confusing comments\n\nThese were noticed by someone responding to issue #2230. I think the\nauthor's original logic was to point out that there's a path from e.g.\nraddr_a_i to rdata_a_o which doesn't depend on any clock, so is\n\"asynchronous\".\n\nBut that's the same in the other modes and also for the other register\nfile implementations, which don't have analogous comments.\n\nDrop these ones.", "fix_patch": "diff --git a/rtl/ibex_register_file_fpga.sv b/rtl/ibex_register_file_fpga.sv\nindex 2414d771d5..65698d1c51 100644\n--- a/rtl/ibex_register_file_fpga.sv\n+++ b/rtl/ibex_register_file_fpga.sv\n@@ -150,10 +150,7 @@ module ibex_register_file_fpga #(\n assign rdata_a_o = (raddr_a_i == '0) ? WordZeroVal : mem_o_a;\n assign rdata_b_o = (raddr_b_i == '0) ? WordZeroVal : mem_o_b;\n end else begin : gen_no_rdata_mux_check\n- // async_read a\n assign rdata_a_o = (raddr_a_i == '0) ? WordZeroVal : mem[raddr_a_i];\n-\n- // async_read b\n assign rdata_b_o = (raddr_b_i == '0) ? WordZeroVal : mem[raddr_b_i];\n \n assign oh_raddr_a_err = 1'b0;\n", "test_patch": "", "modified_files": ["rtl/ibex_register_file_fpga.sv"], "lines_added": 0, "lines_removed": 3} +{"repo": "lowRISC/ibex", "pr_id": 2241, "lang": "sv", "rtl_files": ["rtl/ibex_register_file_fpga.sv"], "commit_id": "8f4c75c5e43e61b994248307c814e01860303056", "timestamp": "2025-01-07T10:01:03+00:00", "pr_title": "[rtl] Drive oh_raddr_*_err if RdataMuxCheck=0", "pr_body": "These errors aren't detected or reported if the mux is disabled, but the RTL didn't actually drive them at all.\r\n\r\nFixes #2239.", "issue_title": "Undriven signal in ibex_register_file_fpga.sv", "issue_body": "## Observed Behavior\n\n\nOn the following line, `oh_raddr_a_err` is undriven if `RdataMuxCheck` is zero.\n\nhttps://github.com/lowRISC/ibex/blob/master/rtl/ibex_register_file_fpga.sv#L54\n\nThis was seen in Verilator linting when trying to integrate Ibex into my design. I've searched the VLT files for any relevant waivers but can't see any relating to this level of hierarchy.\n\n```\nERROR: %Warning-UNDRIVEN: src/lowrisc_export_ibex_top_0/rtl/ibex_register_file_fpga.sv:54:9: Signal is not driven: 'oh_raddr_a_err'\n : ... note: In instance 'ibex_wb.u_top..gen_regfile_fpga.register_file_i'\n 54 | logic oh_raddr_a_err, oh_raddr_b_err, oh_we_err;\n | ^~~~~~~~~~~~~~\n ... For warning description see https://verilator.org/warn/UNDRIVEN?v=5.024\n ... Use \"/* verilator lint_off UNDRIVEN */\" and lint_on around source to disable this message.\n%Warning-UNDRIVEN: src/lowrisc_export_ibex_top_0/rtl/ibex_register_file_fpga.sv:54:25: Signal is not driven: 'oh_raddr_b_err'\n : ... note: In instance 'ibex_wb.u_top..gen_regfile_fpga.register_file_i'\n 54 | logic oh_raddr_a_err, oh_raddr_b_err, oh_we_err;\n | ^~~~~~~~~~~~~~\n%Error: Exiting due to 2 warning(s)\nmake: *** [Makefile:23: lint-only] Error 1\n\nERROR: Failed to build nq:ip:ibex_wb:0 : '['make', 'lint-only']' exited with an error: 2\n```\n\n## Expected Behavior\n\nTis lint clean please.\n\n## Steps to reproduce the issue\n\n\nI'm trying to export the Ibex RTL source code to get around the fact that you are using a custom version of Fusesoc. I'm instantiating Ibex with the following parameters:\n\n```\n ibex_top #(\n .RV32M (ibex_pkg::RV32MSlow),\n .RV32B (ibex_pkg::RV32BNone),\n .RegFile(ibex_pkg::RegFileFPGA)\n ) u_top (\n\n```\n\nand then running a Verilator lint using the standard Fusesoc/Edalize flow.\n\n## My Environment\n\n\n\n**EDA tool and version:**\nVerilator 5.024 2024-04-05 rev v5.024\n\n\n**Operating system:**\nRocky 9.4\n\n\n**Version of the Ibex source code:**\n8f4c75c5e43e61b994248307c814e01860303056\n\n", "commit_message": "[rtl] Drive oh_raddr_*_err if RdataMuxCheck=0\n\nThese errors aren't detected or reported if the mux is disabled, but\nthe RTL didn't actually drive them at all.", "fix_patch": "diff --git a/rtl/ibex_register_file_fpga.sv b/rtl/ibex_register_file_fpga.sv\nindex 73e0afab2f..2414d771d5 100644\n--- a/rtl/ibex_register_file_fpga.sv\n+++ b/rtl/ibex_register_file_fpga.sv\n@@ -155,6 +155,9 @@ module ibex_register_file_fpga #(\n \n // async_read b\n assign rdata_b_o = (raddr_b_i == '0) ? WordZeroVal : mem[raddr_b_i];\n+\n+ assign oh_raddr_a_err = 1'b0;\n+ assign oh_raddr_b_err = 1'b0;\n end\n \n // we select\n", "test_patch": "", "modified_files": ["rtl/ibex_register_file_fpga.sv"], "lines_added": 3, "lines_removed": 0} +{"repo": "lowRISC/ibex", "pr_id": 2229, "lang": "sv", "rtl_files": ["rtl/ibex_counter.sv"], "commit_id": "54985d21b055967c39d0a77b45ae0d573b55b0f7", "timestamp": "2024-12-04T00:34:00+00:00", "pr_title": "Revert \"[rtl] Fix counter reset value on FPGA\"", "pr_body": "Reverts lowRISC/ibex#2226 because the scope for counter_q is incorrect resulting in synthesis failure for Xilinx targets.", "issue_title": "[rtl] Fix counter reset value on FPGA", "issue_body": "If the counter width is >= 49, we do not use a DSP on the FPGA. Then, we should use an asynchronous reset to initialize the counter.\r\n\r\nThis bug was detected when enabling the lockstep for the CW340. A lockstep mismatch happend as the mcycle counters of the main and shadow core did not match due to this bug.", "commit_message": "Revert \"[rtl] Fix counter reset value on FPGA\"\n\nThis reverts commit 54985d21b055967c39d0a77b45ae0d573b55b0f7.", "fix_patch": "diff --git a/rtl/ibex_counter.sv b/rtl/ibex_counter.sv\nindex d3ca14ca02..c78e510ee4 100644\n--- a/rtl/ibex_counter.sv\n+++ b/rtl/ibex_counter.sv\n@@ -51,17 +51,12 @@ module ibex_counter #(\n end\n \n `ifdef FPGA_XILINX\n- // On Xilinx FPGAs, 48-bit DSPs are available that can be used for the\n- // counter.\n- if (CounterWidth < 49) begin : g_dsp_counter\n- // Set DSP pragma for supported xilinx FPGAs\n- (* use_dsp = \"yes\" *) logic [CounterWidth-1:0] counter_q;\n- // DSP output register requires synchronous reset.\n- `define COUNTER_FLOP_RST posedge clk_i\n- end else begin : g_no_dsp_counter\n- (* use_dsp = \"no\" *) logic [CounterWidth-1:0] counter_q;\n- `define COUNTER_FLOP_RST posedge clk_i or negedge rst_ni\n- end\n+ // Set DSP pragma for supported xilinx FPGAs\n+ localparam int DspPragma = CounterWidth < 49 ? \"yes\" : \"no\";\n+ (* use_dsp = DspPragma *) logic [CounterWidth-1:0] counter_q;\n+\n+ // DSP output register requires synchronous reset.\n+ `define COUNTER_FLOP_RST posedge clk_i\n `else\n logic [CounterWidth-1:0] counter_q;\n \n@@ -70,7 +65,6 @@ module ibex_counter #(\n \n // Counter flop\n always_ff @(`COUNTER_FLOP_RST) begin\n- `undef COUNTER_FLOP_RST\n if (!rst_ni) begin\n counter_q <= '0;\n end else begin\n@@ -104,3 +98,6 @@ module ibex_counter #(\n assign counter_val_o = counter;\n \n endmodule\n+\n+// Keep helper defines file-local.\n+`undef COUNTER_FLOP_RST\n", "test_patch": "", "modified_files": ["rtl/ibex_counter.sv"], "lines_added": 9, "lines_removed": 12} +{"repo": "lowRISC/ibex", "pr_id": 2224, "lang": "sv", "rtl_files": ["rtl/ibex_register_file_fpga.sv"], "commit_id": "f0f6bfd79a18d676eb565b04b8235133f0f9eedf", "timestamp": "2024-11-18T14:12:06+00:00", "pr_title": "[rtl] Fix zero value in FPGA RF", "pr_body": "We should use `WordZeroVal` instead of `0` for reads from register `x0` in the FPGA register file.\r\n\r\nThis bug was discovered when enabling the `RegFileECC` parameter. When this is enabled, the core performs ECC checks, expecting that `WordZeroVal` is returned for `x0`. Else, we get a major alert.\r\n\r\nFixes lowRISC/opentitan#25146", "issue_title": "", "issue_body": "", "commit_message": "[rtl] Fix zero value in FPGA RF\n\nWe should use `WordZeroVal` instead of `0` for reads from register `x0` in the\nFPGA register file.\n\nThis bug was discovered when enabling the `RegFileECC` parameter. When this is\nenabled, the core performs ECC checks, expecting that `WordZeroVal` is returned\nfor `x0`. Else, we get a major alert.\n\nFixes lowRISC/opentitan#25146\n\nSigned-off-by: Pascal Nasahl ", "fix_patch": "diff --git a/rtl/ibex_register_file_fpga.sv b/rtl/ibex_register_file_fpga.sv\nindex 7a0ae34b15..73e0afab2f 100644\n--- a/rtl/ibex_register_file_fpga.sv\n+++ b/rtl/ibex_register_file_fpga.sv\n@@ -147,14 +147,14 @@ module ibex_register_file_fpga #(\n .out_o (mem_o_b)\n );\n \n- assign rdata_a_o = (raddr_a_i == '0) ? '0 : mem_o_a;\n- assign rdata_b_o = (raddr_b_i == '0) ? '0 : mem_o_b;\n+ assign rdata_a_o = (raddr_a_i == '0) ? WordZeroVal : mem_o_a;\n+ assign rdata_b_o = (raddr_b_i == '0) ? WordZeroVal : mem_o_b;\n end else begin : gen_no_rdata_mux_check\n // async_read a\n- assign rdata_a_o = (raddr_a_i == '0) ? '0 : mem[raddr_a_i];\n+ assign rdata_a_o = (raddr_a_i == '0) ? WordZeroVal : mem[raddr_a_i];\n \n // async_read b\n- assign rdata_b_o = (raddr_b_i == '0) ? '0 : mem[raddr_b_i];\n+ assign rdata_b_o = (raddr_b_i == '0) ? WordZeroVal : mem[raddr_b_i];\n end\n \n // we select\n", "test_patch": "", "modified_files": ["rtl/ibex_register_file_fpga.sv"], "lines_added": 4, "lines_removed": 4} +{"repo": "lowRISC/ibex", "pr_id": 1975, "lang": "sv", "rtl_files": ["rtl/ibex_top.sv"], "commit_id": "b1ac975c1ea3232c214e609fe0e1fce515e577e2", "timestamp": "2023-01-31T16:59:51+00:00", "pr_title": "[rtl/dv] Add assertions for icache scramble keys", "pr_body": "This commit adds two assertions in `ibex_top` to ensure that the scramble key is correctly applied to the icache scrambled memory primitives. Those assertions previously existed in the module that instantiated Ibex in OpenTitan, but the reference into the generate loops was problematic for some EDA tools; see lowRISC/opentitan#17155.", "issue_title": "", "issue_body": "", "commit_message": "[rtl/dv] Add assertions for icache scramble keys\n\nThis commit adds two assertions in `ibex_top` to ensure that the\nscramble key is correctly applied to the icache scrambled memory\nprimitives. Those assertions previously existed in the module that\ninstantiated Ibex in OpenTitan, but the reference into the generate\nloops was problematic for some EDA tools; see lowRISC/opentitan#17155.\n\nAdditionally, the assertions previously used the input scramble key\n(`scramble_key_i`) even though they tolerated a delay after which the\ninput scramble key was not necessarily valid anymore (i.e.,\n`scramble_key_valid_i` could go low and `scramble_key_i` could take any\nvalue). This mistake has been corrected by sampling the input scramble\nkey for the assertions when it is valid and using the sampled value in\nthe comparison of the assertions. This problem surfaced in the DV\nenvironment of Ibex (but not in OpenTitan), where multiple tests\n(including `riscv_rand_instr_test`, `riscv_mem_error_test`, and\n`riscv_multiple_interrupt_test`) failed; these tests now pass.\n\nSigned-off-by: Andreas Kurth ", "fix_patch": "diff --git a/rtl/ibex_top.sv b/rtl/ibex_top.sv\nindex 92d27cba9b..7621f21daf 100644\n--- a/rtl/ibex_top.sv\n+++ b/rtl/ibex_top.sv\n@@ -620,6 +620,36 @@ module ibex_top import ibex_pkg::*; #(\n .cfg_i (ram_cfg_i)\n );\n \n+ `ifdef INC_ASSERT\n+ // Sample scramble key whenever it is valid for use in the assertions below. This may be\n+ // redundant with the sampling performed in the actual design, but that is okay because\n+ // the assertions exist to check the correct functioning of the design.\n+ logic [SCRAMBLE_KEY_W-1:0] sampled_scramble_key;\n+ always_ff @(posedge clk_i, negedge rst_ni) begin\n+ if (!rst_ni) begin\n+ sampled_scramble_key <= 'x;\n+ end else if (scramble_key_valid_i) begin\n+ sampled_scramble_key <= scramble_key_i;\n+ end\n+ end\n+\n+ // Ensure that when a scramble key is received, it is correctly applied to the icache\n+ // scrambled memory primitives. The upper bound in the cycle ranges below is not exact,\n+ // but it should not take more than 10 cycles.\n+ `ASSERT(ScrambleKeyAppliedAtTagBank_A,\n+ scramble_key_valid_i\n+ |-> ##[0:10]\n+ tag_bank.key_valid_i && (tag_bank.key_i == sampled_scramble_key),\n+ clk_i, !rst_ni\n+ )\n+ `ASSERT(ScrambleKeyAppliedAtDataBank_A,\n+ scramble_key_valid_i\n+ |-> ##[0:10]\n+ data_bank.key_valid_i && (data_bank.key_i == sampled_scramble_key),\n+ clk_i, !rst_ni\n+ )\n+ `endif\n+\n end else begin : gen_noscramble_rams\n \n // Tag RAM instantiation\n", "test_patch": "", "modified_files": ["rtl/ibex_top.sv"], "lines_added": 30, "lines_removed": 0} +{"repo": "lowRISC/ibex", "pr_id": 1917, "lang": "sv", "rtl_files": ["rtl/ibex_top.sv"], "commit_id": "94f9517287f14c468d76296a719ee04c610ffbfd", "timestamp": "2022-11-14T11:07:50+00:00", "pr_title": "[fpv] Fix linting issues in oustanding access tracking logic", "pr_body": "This refactors the code to avoid a -1 index access that caused no issues in functional verification but caused lint errors and is problematic for formal tools.\r\n\r\nFixes #1799", "issue_title": "[dv] Out of bounds access in dside access tracking logic", "issue_body": "This line: https://github.com/lowRISC/ibex/blob/056cb44ff75f797898709546ea1b0fd08d862e1a/rtl/ibex_top.sv#L1092\r\n\r\nUses `i - 1` and it's possible to evaluate this condition when `i == 0` giving an out of bounds access. This logic needs refactoring to more explicitly split out the `i == 0` case from the others to ensure this does not occur.\r\n\r\n> estimate 1", "commit_message": "[fpv] Fix linting issues in oustanding access tracking logic\n\nThis refactors the code to avoid a -1 index access that caused no issues\nin functional verification but caused lint errors and is problematic for\nformal tools.\n\nFixes #1799", "fix_patch": "diff --git a/rtl/ibex_top.sv b/rtl/ibex_top.sv\nindex 84b0f9cd1f..d8a9f89162 100644\n--- a/rtl/ibex_top.sv\n+++ b/rtl/ibex_top.sv\n@@ -1117,15 +1117,21 @@ module ibex_top import ibex_pkg::*; #(\n end\n end\n \n- always_comb begin\n- pending_dside_accesses_d[i] = pending_dside_accesses_shifted[i];\n+ if (i == 0) begin : g_track_first_entry\n+ always_comb begin\n+ pending_dside_accesses_d[i] = pending_dside_accesses_shifted[i];\n \n- if (data_req_o && data_gnt_i) begin\n- if (i == 0 && !pending_dside_accesses_shifted[i].valid) begin\n+ if (data_req_o && data_gnt_i && !pending_dside_accesses_shifted[i].valid) begin\n pending_dside_accesses_d[i].valid = 1'b1;\n pending_dside_accesses_d[i].is_read = ~data_we_o;\n- end else if (pending_dside_accesses_shifted[i - 1].valid &\n- !pending_dside_accesses_shifted[i].valid) begin\n+ end\n+ end\n+ end else begin : g_track_other_entries\n+ always_comb begin\n+ pending_dside_accesses_d[i] = pending_dside_accesses_shifted[i];\n+\n+ if (data_req_o && data_gnt_i && pending_dside_accesses_shifted[i - 1].valid &&\n+ !pending_dside_accesses_shifted[i].valid) begin\n pending_dside_accesses_d[i].valid = 1'b1;\n pending_dside_accesses_d[i].is_read = ~data_we_o;\n end\n", "test_patch": "", "modified_files": ["rtl/ibex_top.sv"], "lines_added": 12, "lines_removed": 6} +{"repo": "lowRISC/ibex", "pr_id": 1881, "lang": "sv", "rtl_files": ["dv/uvm/core_ibex/env/core_ibex_dut_probe_if.sv"], "commit_id": "e9a866ef55997f05a62c4c3af9dd60586697e197", "timestamp": "2022-11-04T15:00:44+00:00", "pr_title": "[dv] Add test glitching register file read ports", "pr_body": "This PR addresses the integrity checking part of https://github.com/lowRISC/ibex/issues/1756 by verifying that a glitch on the data read from the register file raises a major alert by the core (if the data read from the register file is used by the core).\r\n\r\nThe **last** commit implements the actual test. The commits before that are prerequisites as follows:\r\n1. ~~duplicate from #1873, will be dropped once that PR is merged.~~\r\n2. ~~duplicate from #1879, will be dropped once that PR is merged.~~\r\n3. [dv] Add RF signals to `core_ibex_dut_probe_if` and\r\n4. [dv] Create signal probe functions in `core_ibex_dut_probe_if`: same approach as in #1879.\r\n\r\nPass rate is currently 100% (I tried 20 seeds) -- that is, alerts are produced and checked as expected ~~-- however the DV environment misinterprets passing tests as failures (probably due to the call to `dv_test_status_pkg::dv_test_status(1)` at the end of a successful test). Hints on how to fix this would be appreciated.~~", "issue_title": "[dv] Add test glitching PC of Ibex", "issue_body": "This PR addresses #1755 by verifying that a glitch on the PC of Ibex raises an internal major alert in the core.", "commit_message": "[dv] Add test glitching register file read data\n\nThis commit addresses the integrity checking part of #1756 by verifying\nthat a glitch on the data read from the register file raises a major\nalert by the core (if the data read from the register file is used by\nthe core).\n\nSigned-off-by: Andreas Kurth ", "fix_patch": "diff --git a/dv/uvm/core_ibex/env/core_ibex_dut_probe_if.sv b/dv/uvm/core_ibex/env/core_ibex_dut_probe_if.sv\nindex 06bb441112..7dec52c584 100644\n--- a/dv/uvm/core_ibex/env/core_ibex_dut_probe_if.sv\n+++ b/dv/uvm/core_ibex/env/core_ibex_dut_probe_if.sv\n@@ -4,6 +4,9 @@\n \n // Interface to probe DUT internal signal\n interface core_ibex_dut_probe_if(input logic clk);\n+\n+ import uvm_pkg::*;\n+\n logic reset;\n logic illegal_instr;\n logic ecall;\n@@ -21,6 +24,10 @@ interface core_ibex_dut_probe_if(input logic clk);\n ibex_pkg::ctrl_fsm_e ctrl_fsm_cs;\n logic debug_mode;\n logic double_fault_seen;\n+ logic rf_ren_a;\n+ logic rf_ren_b;\n+ logic rf_rd_a_wb_match;\n+ logic rf_rd_b_wb_match;\n \n clocking dut_cb @(posedge clk);\n output fetch_enable;\n@@ -40,10 +47,19 @@ interface core_ibex_dut_probe_if(input logic clk);\n input ctrl_fsm_cs;\n input debug_mode;\n input double_fault_seen;\n+ input rf_ren_a;\n+ input rf_ren_b;\n+ input rf_rd_a_wb_match;\n+ input rf_rd_b_wb_match;\n endclocking\n \n initial begin\n debug_req = 1'b0;\n end\n \n+ `DV_CREATE_SIGNAL_PROBE_FUNCTION(signal_probe_rf_ren_a, rf_ren_a)\n+ `DV_CREATE_SIGNAL_PROBE_FUNCTION(signal_probe_rf_ren_b, rf_ren_b)\n+ `DV_CREATE_SIGNAL_PROBE_FUNCTION(signal_probe_rf_rd_a_wb_match, rf_rd_a_wb_match)\n+ `DV_CREATE_SIGNAL_PROBE_FUNCTION(signal_probe_rf_rd_b_wb_match, rf_rd_b_wb_match)\n+\n endinterface\n", "test_patch": "diff --git a/dv/uvm/core_ibex/riscv_dv_extension/testlist.yaml b/dv/uvm/core_ibex/riscv_dv_extension/testlist.yaml\nindex 21099231d0..ed73334cd0 100644\n--- a/dv/uvm/core_ibex/riscv_dv_extension/testlist.yaml\n+++ b/dv/uvm/core_ibex/riscv_dv_extension/testlist.yaml\n@@ -646,6 +646,13 @@\n gen_test: riscv_rand_instr_test\n rtl_test: core_ibex_pc_intg_test\n \n+- test: riscv_rf_intg_test\n+ description: >\n+ Randomly corrupt the register file read port once in the middle of program execution\n+ iterations: 15\n+ gen_test: riscv_rand_instr_test\n+ rtl_test: core_ibex_rf_intg_test\n+\n - test: riscv_rv32im_instr_test\n description: >\n Random instruction test without compressed instructions\ndiff --git a/dv/uvm/core_ibex/tb/core_ibex_tb_top.sv b/dv/uvm/core_ibex/tb/core_ibex_tb_top.sv\nindex 91fd7216fe..c8256aa4fa 100644\n--- a/dv/uvm/core_ibex/tb/core_ibex_tb_top.sv\n+++ b/dv/uvm/core_ibex/tb/core_ibex_tb_top.sv\n@@ -200,16 +200,21 @@ module core_ibex_tb_top;\n // Irq interface connections\n assign irq_vif.reset = ~rst_n;\n // Dut_if interface connections\n- assign dut_if.ecall = dut.u_ibex_top.u_ibex_core.id_stage_i.controller_i.ecall_insn;\n- assign dut_if.wfi = dut.u_ibex_top.u_ibex_core.id_stage_i.controller_i.wfi_insn;\n- assign dut_if.ebreak = dut.u_ibex_top.u_ibex_core.id_stage_i.controller_i.ebrk_insn;\n- assign dut_if.illegal_instr = dut.u_ibex_top.u_ibex_core.id_stage_i.controller_i.illegal_insn_d;\n- assign dut_if.dret = dut.u_ibex_top.u_ibex_core.id_stage_i.controller_i.dret_insn;\n- assign dut_if.mret = dut.u_ibex_top.u_ibex_core.id_stage_i.controller_i.mret_insn;\n- assign dut_if.reset = ~rst_n;\n- assign dut_if.priv_mode = dut.u_ibex_top.u_ibex_core.priv_mode_id;\n- assign dut_if.ctrl_fsm_cs = dut.u_ibex_top.u_ibex_core.id_stage_i.controller_i.ctrl_fsm_cs;\n- assign dut_if.debug_mode = dut.u_ibex_top.u_ibex_core.id_stage_i.controller_i.debug_mode_q;\n+ assign dut_if.ecall = dut.u_ibex_top.u_ibex_core.id_stage_i.controller_i.ecall_insn;\n+ assign dut_if.wfi = dut.u_ibex_top.u_ibex_core.id_stage_i.controller_i.wfi_insn;\n+ assign dut_if.ebreak = dut.u_ibex_top.u_ibex_core.id_stage_i.controller_i.ebrk_insn;\n+ assign dut_if.illegal_instr\n+ = dut.u_ibex_top.u_ibex_core.id_stage_i.controller_i.illegal_insn_d;\n+ assign dut_if.dret = dut.u_ibex_top.u_ibex_core.id_stage_i.controller_i.dret_insn;\n+ assign dut_if.mret = dut.u_ibex_top.u_ibex_core.id_stage_i.controller_i.mret_insn;\n+ assign dut_if.reset = ~rst_n;\n+ assign dut_if.priv_mode = dut.u_ibex_top.u_ibex_core.priv_mode_id;\n+ assign dut_if.ctrl_fsm_cs = dut.u_ibex_top.u_ibex_core.id_stage_i.controller_i.ctrl_fsm_cs;\n+ assign dut_if.debug_mode = dut.u_ibex_top.u_ibex_core.id_stage_i.controller_i.debug_mode_q;\n+ assign dut_if.rf_ren_a = dut.u_ibex_top.u_ibex_core.rf_ren_a;\n+ assign dut_if.rf_ren_b = dut.u_ibex_top.u_ibex_core.rf_ren_b;\n+ assign dut_if.rf_rd_a_wb_match = dut.u_ibex_top.u_ibex_core.rf_rd_a_wb_match;\n+ assign dut_if.rf_rd_b_wb_match = dut.u_ibex_top.u_ibex_core.rf_rd_b_wb_match;\n // Instruction monitor connections\n assign instr_monitor_if.reset = ~rst_n;\n assign instr_monitor_if.valid_id = dut.u_ibex_top.u_ibex_core.id_stage_i.instr_valid_i;\ndiff --git a/dv/uvm/core_ibex/tests/core_ibex_test_lib.sv b/dv/uvm/core_ibex/tests/core_ibex_test_lib.sv\nindex 3b39a98c63..6ad5db284a 100644\n--- a/dv/uvm/core_ibex/tests/core_ibex_test_lib.sv\n+++ b/dv/uvm/core_ibex/tests/core_ibex_test_lib.sv\n@@ -88,6 +88,117 @@ class core_ibex_pc_intg_test extends core_ibex_base_test;\n \n endclass\n \n+// Test that corrupts data read from the register file and checks that an appropriate alert occurs.\n+class core_ibex_rf_intg_test extends core_ibex_base_test;\n+\n+ `uvm_component_utils(core_ibex_rf_intg_test)\n+ `uvm_component_new\n+\n+ uvm_report_server rs;\n+\n+ int unsigned reg_file_data_width;\n+\n+ string ibex_top_path = \"core_ibex_tb_top.dut.u_ibex_top\";\n+\n+ function automatic uvm_hdl_data_t read_data(string subpath);\n+ uvm_hdl_data_t result;\n+ string path = $sformatf(\"%s.%s\", ibex_top_path, subpath);\n+ `DV_CHECK_FATAL(uvm_hdl_read(path, result))\n+ return result;\n+ endfunction\n+\n+ function automatic int unsigned read_uint(string subpath);\n+ return read_data(subpath);\n+ endfunction\n+\n+ function automatic void force_data(string subpath, uvm_hdl_data_t value);\n+ string path = $sformatf(\"%s.%s\", ibex_top_path, subpath);\n+ `DV_CHECK_FATAL(uvm_hdl_force(path, value))\n+ endfunction\n+\n+ function automatic void release_force(string subpath);\n+ string path = $sformatf(\"%s.%s\", ibex_top_path, subpath);\n+ `DV_CHECK_FATAL(uvm_hdl_release(path))\n+ endfunction\n+\n+ virtual function void build_phase(uvm_phase phase);\n+ super.build_phase(phase);\n+\n+ // Obtain value of parameter defining data width of register file.\n+ reg_file_data_width = read_uint(\"RegFileDataWidth\");\n+ endfunction\n+\n+ virtual task send_stimulus();\n+ bit port_idx;\n+ string port_name;\n+\n+ vseq.start(env.vseqr);\n+\n+ // Pick port to corrupt.\n+ port_idx = $urandom_range(1);\n+ port_name = port_idx ? \"rf_rdata_b_ecc\" : \"rf_rdata_a_ecc\";\n+\n+ forever begin\n+ logic rf_ren, rf_rd_wb_match;\n+ int unsigned bit_idx;\n+ uvm_hdl_data_t data, mask;\n+ logic exp_alert, alert_major_internal;\n+\n+ clk_vif.wait_n_clks(1);\n+\n+ // Check if port is being read.\n+ if (port_idx) begin\n+ rf_ren = dut_vif.signal_probe_rf_ren_b(dv_utils_pkg::SignalProbeSample);\n+ rf_rd_wb_match = dut_vif.signal_probe_rf_rd_b_wb_match(dv_utils_pkg::SignalProbeSample);\n+ end else begin\n+ rf_ren = dut_vif.signal_probe_rf_ren_a(dv_utils_pkg::SignalProbeSample);\n+ rf_rd_wb_match = dut_vif.signal_probe_rf_rd_a_wb_match(dv_utils_pkg::SignalProbeSample);\n+ end\n+\n+ // Only corrupt port if it is read.\n+ if (!(rf_ren == 1'b1 && rf_rd_wb_match == 1'b0)) continue;\n+\n+ data = read_data(port_name);\n+ `uvm_info(`gfn, $sformatf(\"Corrupting %s; original value: 'h%0x\", port_name, data), UVM_LOW)\n+\n+ // Corrupt one bit of the data.\n+ bit_idx = $urandom_range(reg_file_data_width - 1);\n+ mask = 1 << bit_idx;\n+ data ^= mask;\n+\n+ // Disable TB assertion for alerts.\n+ `DV_ASSERT_CTRL_REQ(\"tb_no_alerts_triggered\", 1'b0)\n+\n+ // Force the corrupt value.\n+ `uvm_info(`gfn, $sformatf(\"Forcing corrupt value: 'h%0x\", data), UVM_LOW)\n+ force_data(port_name, data);\n+\n+ // Determine whether an alert is expected: if the instruction is valid.\n+ exp_alert = read_data(\"u_ibex_core.instr_valid_id\");\n+\n+ // Schedule a simulation step so the DUT can react.\n+ #1step;\n+\n+ // Check if the major alert matches our expectation.\n+ alert_major_internal = read_data(\"alert_major_internal_o\");\n+ `DV_CHECK_EQ_FATAL(alert_major_internal, exp_alert)\n+\n+ // Release force after one clock cycle.\n+ clk_vif.wait_n_clks(1);\n+ release_force(port_name);\n+\n+ // Complete test if alert has been correctly triggered.\n+ if (exp_alert) break;\n+ end\n+\n+ // Stop test at this point because cosim will mismatch.\n+ rs = uvm_report_server::get_server();\n+ rs.report_summarize();\n+ $finish();\n+ endtask\n+\n+endclass\n+\n // Reset test\n class core_ibex_reset_test extends core_ibex_base_test;\n \n", "modified_files": ["dv/uvm/core_ibex/env/core_ibex_dut_probe_if.sv", "dv/uvm/core_ibex/riscv_dv_extension/testlist.yaml", "dv/uvm/core_ibex/tb/core_ibex_tb_top.sv", "dv/uvm/core_ibex/tests/core_ibex_test_lib.sv"], "lines_added": 149, "lines_removed": 10} +{"repo": "lowRISC/ibex", "pr_id": 1879, "lang": "sv", "rtl_files": ["dv/uvm/core_ibex/env/core_ibex_dut_probe_if.sv"], "commit_id": "66b3ed1ac1df79cc6d285e586135fd1e68ab198f", "timestamp": "2022-11-04T15:28:09+00:00", "pr_title": "[dv] Add test glitching data/tag of icache", "pr_body": "This PR addresses the integrity part of https://github.com/lowRISC/ibex/issues/1759 by verifying that a glitch on the data or tag response from the instruction cache raises a minor alert by the core (if the data/tag returned from the cache is used by the core).\r\n\r\nThe **last** commit implements the actual test. The commits before that are prerequisites as follows:\r\n1. ~~[dv] Add assert control for `NoAlertsTriggered`: duplicate from #1873, will be dropped once that PR is merged.~~\r\n2. ~~[wip] Extend vendored-in `clk_rst_if`: adds two functions to that IF -- if we agree that this is appropriate and necessary, these functions should be upstreamed.~~\r\n3. ~~[wip] Locally import `DV_CREATE_SIGNAL_PROBE_FUNCTION`: adds a macro recently added in OpenTitan (I wanted to properly vendor it in, but the update failed). If we agree that this macro should be used here, we need to fix the vendor-update problems.~~\r\n4. [dv] Add icache signals to `core_ibex_dut_probe_if`: should be fairly uncontroversial.\r\n5. [dv] Create signal probe functions in `core_ibex_dut_probe_if`: these functions have benefits over `uvm_hdl_read()`; see the commit message.\r\n\r\nPass rate is currently 100% (I tried 20 seeds) -- that is, alerts are produced and checked as expected. Every test corrupts a used data/tag of the icache, but not in every test the data/tag is valid (even when not corrupted). The test takes this into account when checking for an alert.\r\n\r\n~~Note: This test currently only works correctly if waves are being logged. Otherwise, the simulator complains that it does not have access to the icache data/tag to glitch it.~~", "issue_title": "[dv] Add test glitching PC of Ibex", "issue_body": "This PR addresses #1755 by verifying that a glitch on the PC of Ibex raises an internal major alert in the core.", "commit_message": "[dv] Add test glitching icache data or tag\n\nThis commit addresses the integrity part of #1759 by verifying that a\nglitch on the data or tag response from the instruction cache raises a\nminor alert by the core (if the data/tag returned from the cache is used\nby the core).\n\nSigned-off-by: Andreas Kurth ", "fix_patch": "diff --git a/dv/uvm/core_ibex/env/core_ibex_dut_probe_if.sv b/dv/uvm/core_ibex/env/core_ibex_dut_probe_if.sv\nindex 7dec52c584..fdf40cce98 100644\n--- a/dv/uvm/core_ibex/env/core_ibex_dut_probe_if.sv\n+++ b/dv/uvm/core_ibex/env/core_ibex_dut_probe_if.sv\n@@ -7,27 +7,33 @@ interface core_ibex_dut_probe_if(input logic clk);\n \n import uvm_pkg::*;\n \n- logic reset;\n- logic illegal_instr;\n- logic ecall;\n- logic wfi;\n- logic ebreak;\n- logic dret;\n- logic mret;\n- ibex_pkg::ibex_mubi_t fetch_enable;\n- logic core_sleep;\n- logic alert_minor;\n- logic alert_major_internal;\n- logic alert_major_bus;\n- logic debug_req;\n- ibex_pkg::priv_lvl_e priv_mode;\n- ibex_pkg::ctrl_fsm_e ctrl_fsm_cs;\n- logic debug_mode;\n- logic double_fault_seen;\n- logic rf_ren_a;\n- logic rf_ren_b;\n- logic rf_rd_a_wb_match;\n- logic rf_rd_b_wb_match;\n+ logic reset;\n+ logic illegal_instr;\n+ logic ecall;\n+ logic wfi;\n+ logic ebreak;\n+ logic dret;\n+ logic mret;\n+ ibex_pkg::ibex_mubi_t fetch_enable;\n+ logic core_sleep;\n+ logic alert_minor;\n+ logic alert_major_internal;\n+ logic alert_major_bus;\n+ logic debug_req;\n+ logic [ibex_pkg::IC_NUM_WAYS-1:0] ic_tag_req;\n+ logic ic_tag_write;\n+ logic [ibex_pkg::IC_INDEX_W-1:0] ic_tag_addr;\n+ logic [ibex_pkg::IC_NUM_WAYS-1:0] ic_data_req;\n+ logic ic_data_write;\n+ logic [ibex_pkg::IC_INDEX_W-1:0] ic_data_addr;\n+ ibex_pkg::priv_lvl_e priv_mode;\n+ ibex_pkg::ctrl_fsm_e ctrl_fsm_cs;\n+ logic debug_mode;\n+ logic double_fault_seen;\n+ logic rf_ren_a;\n+ logic rf_ren_b;\n+ logic rf_rd_a_wb_match;\n+ logic rf_rd_b_wb_match;\n \n clocking dut_cb @(posedge clk);\n output fetch_enable;\n@@ -43,6 +49,12 @@ interface core_ibex_dut_probe_if(input logic clk);\n input alert_minor;\n input alert_major_internal;\n input alert_major_bus;\n+ input ic_tag_req;\n+ input ic_tag_write;\n+ input ic_tag_addr;\n+ input ic_data_req;\n+ input ic_data_write;\n+ input ic_data_addr;\n input priv_mode;\n input ctrl_fsm_cs;\n input debug_mode;\n@@ -61,5 +73,12 @@ interface core_ibex_dut_probe_if(input logic clk);\n `DV_CREATE_SIGNAL_PROBE_FUNCTION(signal_probe_rf_ren_b, rf_ren_b)\n `DV_CREATE_SIGNAL_PROBE_FUNCTION(signal_probe_rf_rd_a_wb_match, rf_rd_a_wb_match)\n `DV_CREATE_SIGNAL_PROBE_FUNCTION(signal_probe_rf_rd_b_wb_match, rf_rd_b_wb_match)\n+ `DV_CREATE_SIGNAL_PROBE_FUNCTION(signal_probe_alert_minor, alert_minor)\n+ `DV_CREATE_SIGNAL_PROBE_FUNCTION(signal_probe_ic_tag_req, ic_tag_req)\n+ `DV_CREATE_SIGNAL_PROBE_FUNCTION(signal_probe_ic_tag_write, ic_tag_write)\n+ `DV_CREATE_SIGNAL_PROBE_FUNCTION(signal_probe_ic_tag_addr, ic_tag_addr)\n+ `DV_CREATE_SIGNAL_PROBE_FUNCTION(signal_probe_ic_data_req, ic_data_req)\n+ `DV_CREATE_SIGNAL_PROBE_FUNCTION(signal_probe_ic_data_write, ic_data_write)\n+ `DV_CREATE_SIGNAL_PROBE_FUNCTION(signal_probe_ic_data_addr, ic_data_addr)\n \n endinterface\n", "test_patch": "diff --git a/dv/uvm/core_ibex/riscv_dv_extension/testlist.yaml b/dv/uvm/core_ibex/riscv_dv_extension/testlist.yaml\nindex ed73334cd0..0a6dba3069 100644\n--- a/dv/uvm/core_ibex/riscv_dv_extension/testlist.yaml\n+++ b/dv/uvm/core_ibex/riscv_dv_extension/testlist.yaml\n@@ -653,6 +653,13 @@\n gen_test: riscv_rand_instr_test\n rtl_test: core_ibex_rf_intg_test\n \n+- test: riscv_icache_intg_test\n+ description: >\n+ Randomly corrupt the instruction cache once in the middle of program execution\n+ iterations: 15\n+ gen_test: riscv_rand_instr_test\n+ rtl_test: core_ibex_icache_intg_test\n+\n - test: riscv_rv32im_instr_test\n description: >\n Random instruction test without compressed instructions\ndiff --git a/dv/uvm/core_ibex/tb/core_ibex_tb_top.sv b/dv/uvm/core_ibex/tb/core_ibex_tb_top.sv\nindex c8256aa4fa..bf9745bab2 100644\n--- a/dv/uvm/core_ibex/tb/core_ibex_tb_top.sv\n+++ b/dv/uvm/core_ibex/tb/core_ibex_tb_top.sv\n@@ -208,6 +208,12 @@ module core_ibex_tb_top;\n assign dut_if.dret = dut.u_ibex_top.u_ibex_core.id_stage_i.controller_i.dret_insn;\n assign dut_if.mret = dut.u_ibex_top.u_ibex_core.id_stage_i.controller_i.mret_insn;\n assign dut_if.reset = ~rst_n;\n+ assign dut_if.ic_tag_req = dut.u_ibex_top.ic_tag_req;\n+ assign dut_if.ic_tag_write = dut.u_ibex_top.ic_tag_write;\n+ assign dut_if.ic_tag_addr = dut.u_ibex_top.ic_tag_addr;\n+ assign dut_if.ic_data_req = dut.u_ibex_top.ic_data_req;\n+ assign dut_if.ic_data_write = dut.u_ibex_top.ic_data_write;\n+ assign dut_if.ic_data_addr = dut.u_ibex_top.ic_data_addr;\n assign dut_if.priv_mode = dut.u_ibex_top.u_ibex_core.priv_mode_id;\n assign dut_if.ctrl_fsm_cs = dut.u_ibex_top.u_ibex_core.id_stage_i.controller_i.ctrl_fsm_cs;\n assign dut_if.debug_mode = dut.u_ibex_top.u_ibex_core.id_stage_i.controller_i.debug_mode_q;\ndiff --git a/dv/uvm/core_ibex/tests/core_ibex_test_lib.sv b/dv/uvm/core_ibex/tests/core_ibex_test_lib.sv\nindex 6ad5db284a..ea67b099ae 100644\n--- a/dv/uvm/core_ibex/tests/core_ibex_test_lib.sv\n+++ b/dv/uvm/core_ibex/tests/core_ibex_test_lib.sv\n@@ -199,6 +199,275 @@ class core_ibex_rf_intg_test extends core_ibex_base_test;\n \n endclass\n \n+// Test that corrupts the instruction cache and checks that an appropriate alert occurs.\n+class core_ibex_icache_intg_test extends core_ibex_base_test;\n+\n+ `uvm_component_utils(core_ibex_icache_intg_test)\n+ `uvm_component_new\n+\n+ string ibex_top_path = \"core_ibex_tb_top.dut.u_ibex_top\";\n+\n+ int unsigned num_ways, num_entries, tag_size, line_size;\n+\n+ bit data_valid[][];\n+ bit tag_valid[][];\n+\n+ function automatic int unsigned read_uint(string subpath);\n+ int unsigned result;\n+ string path = $sformatf(\"%s.%s\", ibex_top_path, subpath);\n+ `DV_CHECK_FATAL(uvm_hdl_read(path, result))\n+ return result;\n+ endfunction\n+\n+ function automatic uvm_hdl_data_t read_data(string subpath);\n+ uvm_hdl_data_t result;\n+ string path = $sformatf(\"%s.%s\", ibex_top_path, subpath);\n+ `DV_CHECK_FATAL(uvm_hdl_read(path, result))\n+ return result;\n+ endfunction\n+\n+ function automatic void force_data(string subpath, uvm_hdl_data_t value);\n+ string path = $sformatf(\"%s.%s\", ibex_top_path, subpath);\n+ `DV_CHECK_FATAL(uvm_hdl_force(path, value))\n+ endfunction\n+\n+ function automatic void release_force(string subpath);\n+ string path = $sformatf(\"%s.%s\", ibex_top_path, subpath);\n+ `DV_CHECK_FATAL(uvm_hdl_release(path))\n+ endfunction\n+\n+ virtual function void build_phase(uvm_phase phase);\n+ super.build_phase(phase);\n+\n+ // Obtain value of parameters defining shape of cache.\n+ num_ways = ibex_pkg::IC_NUM_WAYS;\n+ num_entries = 1 << ibex_pkg::IC_INDEX_W;\n+ tag_size = read_uint(\"TagSizeECC\");\n+ line_size = read_uint(\"LineSizeECC\");\n+\n+ // Initialize memory entry status arrays.\n+ data_valid = new[num_ways];\n+ foreach (data_valid[i]) data_valid[i] = new[num_entries];\n+ tag_valid = new[num_ways];\n+ foreach (tag_valid[i]) tag_valid[i] = new[num_entries];\n+ endfunction\n+\n+ function automatic void reset_icache_status();\n+ foreach (data_valid[i]) begin\n+ foreach (data_valid[i][j]) data_valid[i][j] = 1'b0;\n+ end\n+ foreach (tag_valid[i]) begin\n+ foreach (tag_valid[i][j]) tag_valid[i][j] = 1'b0;\n+ end\n+ endfunction\n+\n+ // Track the status of the instruction cache (optimistically). Whenever a write to a data or tag\n+ // entry is observed on the icache ports, that data or tag is set to valid in the test. The test\n+ // then uses this information to corrupt only data or tags that are considered valid. The tracked\n+ // status is a necessary but not sufficient condition for the actual validity of a data or tag.\n+ task automatic track_icache_status();\n+ reset_icache_status();\n+ forever begin\n+ uvm_hdl_data_t data_req, data_write, data_addr, tag_req, tag_write, tag_addr;\n+ clk_vif.wait_clks(1);\n+ if (!clk_vif.rst_n) begin\n+ reset_icache_status();\n+ continue;\n+ end\n+ // Set data entries to valid based on data writes.\n+ data_req = dut_vif.signal_probe_ic_data_req(dv_utils_pkg::SignalProbeSample);\n+ data_write = dut_vif.signal_probe_ic_data_write(dv_utils_pkg::SignalProbeSample);\n+ if (data_req != '0 && data_write == 1'b1) begin\n+ data_addr = dut_vif.signal_probe_ic_data_addr(dv_utils_pkg::SignalProbeSample);\n+ for (int unsigned i = 0; i < num_ways; i++) begin\n+ if (data_req[i]) data_valid[i][data_addr] = 1'b1;\n+ end\n+ end\n+ // Set tag entries to valid based on tag writes.\n+ tag_req = dut_vif.signal_probe_ic_tag_req(dv_utils_pkg::SignalProbeSample);\n+ tag_write = dut_vif.signal_probe_ic_tag_write(dv_utils_pkg::SignalProbeSample);\n+ if (tag_req != '0 && tag_write == 1'b1) begin\n+ tag_addr = dut_vif.signal_probe_ic_tag_addr(dv_utils_pkg::SignalProbeSample);\n+ for (int unsigned i = 0; i < num_ways; i++) begin\n+ if (tag_req[i]) tag_valid[i][tag_addr] = 1'b1;\n+ end\n+ end\n+ end\n+ endtask\n+\n+ task automatic corrupt_used_icache_data();\n+ clk_vif.wait_n_clks(1);\n+ forever begin\n+ uvm_hdl_data_t data_req, data_write, data_addr;\n+ data_req = dut_vif.signal_probe_ic_data_req(dv_utils_pkg::SignalProbeSample);\n+ data_write = dut_vif.signal_probe_ic_data_write(dv_utils_pkg::SignalProbeSample);\n+\n+ // Check if at least one data way is being read.\n+ if (data_req != '0 && data_write == 1'b0) begin\n+ int unsigned valid_and_used_ways[$];\n+\n+ // Probe the data address.\n+ data_addr = dut_vif.signal_probe_ic_data_addr(dv_utils_pkg::SignalProbeSample);\n+\n+ // Find out which data ways are valid and used in this clock cycle.\n+ for (int unsigned i = 0; i < num_ways; i++) begin\n+ if (data_req[i] && data_valid[i][data_addr]) valid_and_used_ways.push_back(i);\n+ end\n+\n+ // The response comes in the next clock cycle, so wait one cycle.\n+ clk_vif.wait_n_clks(1);\n+\n+ // Check if at least one data way is valid and used.\n+ if (valid_and_used_ways.size() > 0) begin\n+ int unsigned way_idx, bit_idx;\n+ uvm_hdl_data_t data_rdata, mask, lookup_valid, tag_hit, alert_minor;\n+ logic exp_alert_minor;\n+\n+ `uvm_info(`gfn,\n+ $sformatf(\"The following I$ data ways are valid and used in this clock cycle: %p\",\n+ valid_and_used_ways), UVM_LOW)\n+\n+ // Pick a way to corrupt.\n+ way_idx = $urandom_range(valid_and_used_ways.size() - 1);\n+ `uvm_info(`gfn, $sformatf(\"Corrupting data way %0d\", way_idx), UVM_LOW)\n+\n+ // Probe response data.\n+ data_rdata = read_data($sformatf(\"ic_data_rdata[%0d]\", way_idx));\n+ `uvm_info(`gfn, $sformatf(\"Original data_rdata of way %0d: 'h%0x\", way_idx, data_rdata),\n+ UVM_LOW)\n+\n+ // Pick a bit to corrupt.\n+ bit_idx = $urandom_range(line_size - 1);\n+ mask = 1 << bit_idx;\n+ data_rdata ^= mask;\n+ `uvm_info(`gfn, $sformatf(\"Corrupting data_rdata: 'h%0x\", data_rdata), UVM_LOW)\n+\n+ // Disable TB assertion for alerts.\n+ `DV_ASSERT_CTRL_REQ(\"tb_no_alerts_triggered\", 1'b0)\n+\n+ // Force the corrupt value.\n+ force_data($sformatf(\"ic_data_rdata[%0d]\", way_idx), data_rdata);\n+\n+ // Give the DUT one clock cycle to react.\n+ clk_vif.wait_n_clks(1);\n+\n+ // Decide if an error is expected: if the lookup is valid and the tag hit.\n+ lookup_valid = read_data($sformatf(\n+ \"u_ibex_core.if_stage_i.gen_icache.icache_i.lookup_valid_ic1\"));\n+ tag_hit = read_data($sformatf(\n+ \"u_ibex_core.if_stage_i.gen_icache.icache_i.tag_hit_ic1\"));\n+ exp_alert_minor = lookup_valid & tag_hit;\n+ `DV_CHECK_FATAL(!$isunknown(exp_alert_minor))\n+\n+ // Check that the minor alert matches the expectation.\n+ alert_minor = dut_vif.signal_probe_alert_minor(dv_utils_pkg::SignalProbeSample);\n+ `DV_CHECK_EQ_FATAL(alert_minor, exp_alert_minor)\n+\n+ // Release force and complete task.\n+ release_force($sformatf(\"ic_data_rdata[%0d]\", way_idx));\n+ return;\n+ end\n+ end else begin\n+ clk_vif.wait_n_clks(1);\n+ end\n+ end\n+ endtask\n+\n+ task automatic corrupt_used_icache_tag();\n+ clk_vif.wait_n_clks(1);\n+ forever begin\n+ uvm_hdl_data_t tag_req, tag_write, tag_addr;\n+ tag_req = dut_vif.signal_probe_ic_tag_req(dv_utils_pkg::SignalProbeSample);\n+ tag_write = dut_vif.signal_probe_ic_tag_write(dv_utils_pkg::SignalProbeSample);\n+\n+ // Check if at least one tag way is being read.\n+ if (tag_req != '0 && tag_write == 1'b0) begin\n+ int unsigned valid_and_used_ways[$];\n+\n+ // Probe the tag address.\n+ tag_addr = dut_vif.signal_probe_ic_tag_addr(dv_utils_pkg::SignalProbeSample);\n+\n+ // Find out which tag ways are valid and used in this clock cycle.\n+ for (int unsigned i = 0; i < num_ways; i++) begin\n+ if (tag_req[i] && tag_valid[i][tag_addr]) valid_and_used_ways.push_back(i);\n+ end\n+\n+ // The response comes in the next clock cycle, so wait one cycle.\n+ clk_vif.wait_n_clks(1);\n+\n+ // Check if at least one tag way is valid and used.\n+ if (valid_and_used_ways.size() > 0) begin\n+ int unsigned way_idx, bit_idx;\n+ uvm_hdl_data_t tag_rdata, mask, alert_minor;\n+ logic lookup_valid;\n+\n+ `uvm_info(`gfn,\n+ $sformatf(\"The following I$ tag ways are valid and used in this clock cycle: %p\",\n+ valid_and_used_ways), UVM_LOW)\n+\n+ // Pick a way to corrupt.\n+ way_idx = $urandom_range(valid_and_used_ways.size() - 1);\n+ `uvm_info(`gfn, $sformatf(\"Corrupting tag way %0d\", way_idx), UVM_LOW)\n+\n+ // Probe response data.\n+ tag_rdata = read_data($sformatf(\"ic_tag_rdata[%0d]\", way_idx));\n+ `uvm_info(`gfn, $sformatf(\"Original tag_rdata of way %0d: 'h%0x\", way_idx, tag_rdata),\n+ UVM_LOW)\n+\n+ // Pick a bit to corrupt.\n+ bit_idx = $urandom_range(tag_size - 1);\n+ mask = 1 << bit_idx;\n+ tag_rdata ^= mask;\n+ `uvm_info(`gfn, $sformatf(\"Corrupting tag_rdata: 'h%0x\", tag_rdata), UVM_LOW)\n+\n+ // Disable TB assertion for alerts.\n+ `DV_ASSERT_CTRL_REQ(\"tb_no_alerts_triggered\", 1'b0)\n+\n+ // Force the corrupt value.\n+ force_data($sformatf(\"ic_tag_rdata[%0d]\", way_idx), tag_rdata);\n+\n+ // Give the DUT one clock cycle to react.\n+ clk_vif.wait_n_clks(1);\n+\n+ // Decide if an error is expected: if the lookup is valid.\n+ lookup_valid = read_data($sformatf(\n+ \"u_ibex_core.if_stage_i.gen_icache.icache_i.lookup_valid_ic1\"));\n+ `DV_CHECK_FATAL(!$isunknown(lookup_valid))\n+\n+ // Check that the minor alert matches the expectation.\n+ alert_minor = dut_vif.signal_probe_alert_minor(dv_utils_pkg::SignalProbeSample);\n+ `DV_CHECK_EQ_FATAL(alert_minor, lookup_valid)\n+\n+ // Release force and complete task.\n+ release_force($sformatf(\"ic_tag_rdata[%0d]\", way_idx));\n+ return;\n+ end\n+ end else begin\n+ clk_vif.wait_n_clks(1);\n+ end\n+ end\n+ endtask\n+\n+ task automatic corrupt_used_icache_entries();\n+ fork\n+ corrupt_used_icache_data();\n+ corrupt_used_icache_tag();\n+ join_any\n+\n+ // Re-enable TB assertion for alerts.\n+ `DV_ASSERT_CTRL_REQ(\"tb_no_alerts_triggered\", 1'b1)\n+ endtask\n+\n+ virtual task send_stimulus();\n+ vseq.start(env.vseqr);\n+ fork\n+ track_icache_status();\n+ corrupt_used_icache_entries();\n+ join_any\n+ endtask\n+\n+endclass\n+\n // Reset test\n class core_ibex_reset_test extends core_ibex_base_test;\n \n", "modified_files": ["dv/uvm/core_ibex/env/core_ibex_dut_probe_if.sv", "dv/uvm/core_ibex/riscv_dv_extension/testlist.yaml", "dv/uvm/core_ibex/tb/core_ibex_tb_top.sv", "dv/uvm/core_ibex/tests/core_ibex_test_lib.sv"], "lines_added": 322, "lines_removed": 21} +{"repo": "lowRISC/ibex", "pr_id": 1839, "lang": "sv", "rtl_files": ["rtl/ibex_if_stage.sv"], "commit_id": "0e396d594435c0acca9df785ac40309c76576cc3", "timestamp": "2022-10-06T09:23:01+00:00", "pr_title": "[if,pmp] Check second bit instead of third for instruction alignment", "pr_body": "Ibex was checking the wrong bit when looking at PMP errors and when to count the error it received from instruction fetch +2.\r\n\r\nCloses: https://github.com/lowRISC/ibex/issues/1837", "issue_title": "[pmp] Instruction straddling two TOR regions cosim mismatch", "issue_body": "When running the following test:\r\n`make -j1 --keep-going IBEX_CONFIG=opentitan ITERATIONS=1 TEST=riscv_epmp_mml_test WAVES=0 COV=0 SEED=30325`\r\n\r\nIbex and Spike have different behavior. Spike throws an instruction access fault exception for the address `0x80005cc4`. The TOR region ends at `0x80005cc4`, which is the expected behavior.\r\n\r\nI think Ibex somehow does not perform the check for fetched instructions properly. In this test case there is a branch instruction that straddles two PMP entries, so Ibex must do two requests.\r\n\r\nIbex commit: 0e396d594435c0acca9df785ac40309c76576cc3\r\nSpike commit: 0dc2de5d76add7b218b31053792a676973034b9e\r\n\r\n> estimate 4", "commit_message": "[if,pmp] Check second bit instead of third for instruction alignment\n\nSigned-off-by: Marno van der Maas ", "fix_patch": "diff --git a/rtl/ibex_if_stage.sv b/rtl/ibex_if_stage.sv\nindex 392980d8ad..1bf21ced1f 100644\n--- a/rtl/ibex_if_stage.sv\n+++ b/rtl/ibex_if_stage.sv\n@@ -386,13 +386,13 @@ module ibex_if_stage import ibex_pkg::*; #(\n // An error can come from the instruction address, or the next instruction address for unaligned,\n // uncompressed instructions.\n assign if_instr_pmp_err = pmp_err_if_i |\n- (if_instr_addr[2] & ~instr_is_compressed & pmp_err_if_plus2_i);\n+ (if_instr_addr[1] & ~instr_is_compressed & pmp_err_if_plus2_i);\n \n // Combine bus errors and pmp errors\n assign if_instr_err = if_instr_bus_err | if_instr_pmp_err;\n \n // Capture the second half of the address for errors on the second part of an instruction\n- assign if_instr_err_plus2 = ((if_instr_addr[2] & ~instr_is_compressed & pmp_err_if_plus2_i) |\n+ assign if_instr_err_plus2 = ((if_instr_addr[1] & ~instr_is_compressed & pmp_err_if_plus2_i) |\n fetch_err_plus2) & ~pmp_err_if_i;\n \n // compressed instruction decoding, or more precisely compressed instruction\n", "test_patch": "", "modified_files": ["rtl/ibex_if_stage.sv"], "lines_added": 2, "lines_removed": 2} +{"repo": "lowRISC/ibex", "pr_id": 1824, "lang": "sv", "rtl_files": ["rtl/ibex_controller.sv"], "commit_id": "3943a4eca3917d0a00406abb36f4951304c0b394", "timestamp": "2022-10-13T16:30:05+00:00", "pr_title": "Irq fixes", "pr_body": "I had a go at adding interrupts to the single step test. I ran into various failures but I suspect I'm chasing the same bugs as @ctopal and @hcallahan-lowrisc are in https://github.com/lowRISC/ibex/issues/1765 so I won't continue that work until #1765 is resolved.", "issue_title": "[dv] Investigate issues in mixed interrupts/traps/debug tests", "issue_body": "> estimate 16\r\n> remaining 2022-09-28 8", "commit_message": "[rtl] Ignore MIE bit in U mode", "fix_patch": "diff --git a/rtl/ibex_controller.sv b/rtl/ibex_controller.sv\nindex a14523a253..3dcdd1f77c 100644\n--- a/rtl/ibex_controller.sv\n+++ b/rtl/ibex_controller.sv\n@@ -143,6 +143,7 @@ module ibex_controller #(\n logic enter_debug_mode_prio_q;\n logic enter_debug_mode;\n logic ebreak_into_debug;\n+ logic irq_enabled;\n logic handle_irq;\n logic id_wb_pending;\n \n@@ -398,12 +399,16 @@ module ibex_controller #(\n // ibex_core) source. For internal sources the cause is specified via irq_nm_int_cause.\n assign irq_nm = irq_nm_ext_i | irq_nm_int;\n \n+ // MIE bit only applies when in M mode\n+ assign irq_enabled = csr_mstatus_mie_i | (priv_mode_i == PRIV_LVL_U);\n+\n // Interrupts including NMI are ignored,\n // - while in debug mode,\n // - while in NMI mode (nested NMIs are not supported, NMI has highest priority and\n- // cannot be interrupted by regular interrupts).\n- assign handle_irq = ~debug_mode_q & ~nmi_mode_q &\n- (irq_nm | (irq_pending_i & csr_mstatus_mie_i));\n+ // cannot be interrupted by regular interrupts),\n+ // - while single stepping.\n+ assign handle_irq = ~debug_mode_q & ~debug_single_step_i & ~nmi_mode_q &\n+ (irq_nm | (irq_pending_i & irq_enabled));\n \n // generate ID of fast interrupts, highest priority to lowest ID\n always_comb begin : gen_mfip_id\n", "test_patch": "", "modified_files": ["rtl/ibex_controller.sv"], "lines_added": 8, "lines_removed": 3} +{"repo": "lowRISC/ibex", "pr_id": 1816, "lang": "sv", "rtl_files": ["rtl/ibex_controller.sv"], "commit_id": "7b1be3354d650bc5b23dff6f439459c353288e4f", "timestamp": "2022-10-14T17:44:02+00:00", "pr_title": "[rtl] Change how we record debug causes", "pr_body": "This commit changes when we catch the debug causes. Since `debug_cause_o` only gets saved when `csr_save_cause_o` is high, it would work if we change the cause with a mux that is connected to the input signals.\r\n\r\nResolves #1772\r\n\r\nSigned-off-by: Canberk Topal ", "issue_title": "Cosim mismatch when reading DCSR.cause", "issue_body": "## Observed Behavior\r\nTest failures with the following error : \r\n```\r\nUVM_FATAL ibex_cosim_scoreboard.sv(138) @ 4049807: Cosim mismatch Register write data mismatch to x22 DUT: 40000100 expected: 400000c0\r\n```\r\n\r\nThis fails upon reading from `DCSR.cause`\r\nIn this case : \r\n\r\n![image](https://user-images.githubusercontent.com/102029880/184605611-4f106a6b-a987-4952-b636-760647e12afe.png)\r\n(IBEX)\r\n\r\n![image](https://user-images.githubusercontent.com/102029880/184605563-b1bd1eb8-b8c3-47c2-b263-3c84427153f3.png)\r\n(SPIKE)\r\n\r\nObserving the waveform below, we can see that `debug_req_i` is de-asserted shortly after `debug_mode_i` goes low due to leaving debug mode from a dret. We do re-enter debug mode, but the cause can be seen to be recorded as `DBG_CAUSE_STEP`. In spike, we read back `DBG_CAUSE_HALTREQ` at the same instruction, hence the mismatch.\r\n\r\n## Expected Behavior\r\n\r\nIbex should record `DCSR.cause` as DBG_CAUSE_HALTREQ.\r\n\r\nI think this might be due to the [ibex_controller.sv ](https://github.com/lowRISC/ibex/blob/2f8dfa9dfe2d938228118ed8ab6a543804d0c9ae/rtl/ibex_controller.sv#L662)state machine sampling the `debug_req_i` signal to determine the correct `cause` one cycle later than the decision to enter debug_mode.\r\n\r\n## Steps to reproduce the issue\r\n```\r\ncd dv/uvm/core_ibex/\r\nmake TEST=riscv_debug_basic_test ITERATIONS=1 WAVES=1 SEED=9892 -j12 -ik\r\n```\r\n![image](https://user-images.githubusercontent.com/102029880/184603232-ef1a9397-1cd2-4a0b-828b-1b2eb4e1745a.png)\r\n\r\n> estimate 8\r\n> remaining 2022-09-27 4\r\n> remaining 2022-10-12 1", "commit_message": "Fixup signal used when checking for ebreak cause", "fix_patch": "diff --git a/rtl/ibex_controller.sv b/rtl/ibex_controller.sv\nindex 3673967a00..ecaf64fb84 100644\n--- a/rtl/ibex_controller.sv\n+++ b/rtl/ibex_controller.sv\n@@ -114,6 +114,7 @@ module ibex_controller #(\n \n logic nmi_mode_q, nmi_mode_d;\n logic debug_mode_q, debug_mode_d;\n+ dbg_cause_e debug_cause_d, debug_cause_q;\n logic load_err_q, load_err_d;\n logic store_err_q, store_err_d;\n logic exc_req_q, exc_req_d;\n@@ -417,6 +418,26 @@ module ibex_controller #(\n \n assign unused_irq_timer = irqs_i.irq_timer;\n \n+ // Record the debug cause outside of the FSM\n+ // The decision to enter debug_mode and the write of the cause to DCSR happen\n+ // in seperate steps within the FSM. Hence, there are a small number of cycles\n+ // where a change in external stimulus can cause the cause to be recorded incorrectly.\n+ assign debug_cause_d = trigger_match_i ? DBG_CAUSE_TRIGGER :\n+ ebrk_insn_prio ? DBG_CAUSE_EBREAK :\n+ debug_req_i ? DBG_CAUSE_HALTREQ :\n+ do_single_step_d ? DBG_CAUSE_STEP :\n+ DBG_CAUSE_NONE ;\n+\n+ always_ff @(posedge clk_i or negedge rst_ni) begin\n+ if (!rst_ni) begin\n+ debug_cause_q <= DBG_CAUSE_NONE;\n+ end else begin\n+ debug_cause_q <= debug_cause_d;\n+ end\n+ end\n+\n+ assign debug_cause_o = debug_cause_q;\n+\n /////////////////////\n // Core controller //\n /////////////////////\n@@ -453,7 +474,6 @@ module ibex_controller #(\n flush_id = 1'b0;\n \n debug_csr_save_o = 1'b0;\n- debug_cause_o = DBG_CAUSE_EBREAK;\n debug_mode_d = debug_mode_q;\n nmi_mode_d = nmi_mode_q;\n \n@@ -657,13 +677,6 @@ module ibex_controller #(\n debug_csr_save_o = 1'b1;\n \n csr_save_cause_o = 1'b1;\n- if (trigger_match_i) begin\n- debug_cause_o = DBG_CAUSE_TRIGGER; // (priority 4)\n- end else if (debug_req_i) begin\n- debug_cause_o = DBG_CAUSE_HALTREQ; // (priority 1)\n- end else begin\n- debug_cause_o = DBG_CAUSE_STEP; // (priority 0, lowest)\n- end\n \n // enter debug mode\n debug_mode_d = 1'b1;\n@@ -693,7 +706,6 @@ module ibex_controller #(\n \n // dcsr\n debug_csr_save_o = 1'b1;\n- debug_cause_o = DBG_CAUSE_EBREAK;\n end\n \n // enter debug mode\n", "test_patch": "", "modified_files": ["rtl/ibex_controller.sv"], "lines_added": 21, "lines_removed": 9} +{"repo": "lowRISC/ibex", "pr_id": 1780, "lang": "sv", "rtl_files": ["rtl/ibex_cs_registers.sv"], "commit_id": "1affeff5278d5b2d84984cd3bf173f72d9f024da", "timestamp": "2022-08-18T14:45:28+00:00", "pr_title": "[rtl] Cannot add M mode executable PMP regions when MML = 1", "pr_body": "A rule that allows M mode execution (either M mode only or shared M/U\r\nmode) cannot be added when MML is set, unless RLB is also set.\r\n\r\nFixes #1740", "issue_title": "[rtl,epmp] Prevent addition of executable regions as required by the specification", "issue_body": "The Smepmp specification states:\r\n\r\n> Adding a rule with executable privileges that either is M-mode-only or a locked Shared-Region is not possible and such pmpcfg writes are ignored, leaving pmpcfg unchanged. This restriction can be temporarily lifted e.g. during the boot process, by setting mseccfg.RLB.****\r\n\r\nThis was overlooked during the original epmp implementation and must be added.\r\n\r\n> estimate 2\r\n> remaining 2022-18-08 1", "commit_message": "[rtl] Cannot add M mode executable PMP regions when MML = 1\n\nA rule that allows M mode execution (either M mode only or shared M/U\nmode) cannot be added when MML is set, unless RLB is also set.\n\nFixes #1740", "fix_patch": "diff --git a/rtl/ibex_cs_registers.sv b/rtl/ibex_cs_registers.sv\nindex d1d791ae69..5b2f6a28b6 100644\n--- a/rtl/ibex_cs_registers.sv\n+++ b/rtl/ibex_cs_registers.sv\n@@ -124,6 +124,22 @@ module ibex_cs_registers #(\n \n import ibex_pkg::*;\n \n+ // Is a PMP config a locked one that allows M-mode execution when MSECCFG.MML is set (either\n+ // M mode alone or shared M/U mode execution)?\n+ function automatic logic is_mml_m_exec_cfg(ibex_pkg::pmp_cfg_t pmp_cfg);\n+ logic unused_cfg;\n+ unused_cfg = ^{pmp_cfg.mode};\n+\n+ if (pmp_cfg.lock) begin\n+ case ({pmp_cfg.read, pmp_cfg.write, pmp_cfg.exec})\n+ 3'b001, 3'b010, 3'b011, 3'b101: return 1'b1;\n+ default: return 1'b0;\n+ endcase\n+ end\n+\n+ return 1'b0;\n+ endfunction\n+\n localparam int unsigned RV32BExtra = (RV32B == RV32BOTEarlGrey) || (RV32B == RV32BFull) ? 1 : 0;\n localparam int unsigned RV32MEnabled = (RV32M == RV32MNone) ? 0 : 1;\n localparam int unsigned PMPAddrWidth = (PMPGranularity > 0) ? 33 - PMPGranularity : 32;\n@@ -1045,6 +1061,7 @@ module ibex_cs_registers #(\n logic pmp_mseccfg_err;\n pmp_cfg_t pmp_cfg [PMPNumRegions];\n logic [PMPNumRegions-1:0] pmp_cfg_locked;\n+ logic [PMPNumRegions-1:0] pmp_cfg_wr_suppress;\n pmp_cfg_t pmp_cfg_wdata [PMPNumRegions];\n logic [PMPAddrWidth-1:0] pmp_addr [PMPNumRegions];\n logic [PMPNumRegions-1:0] pmp_cfg_we;\n@@ -1100,7 +1117,9 @@ module ibex_cs_registers #(\n // -------------------------\n // Instantiate cfg registers\n // -------------------------\n- assign pmp_cfg_we[i] = csr_we_int & ~pmp_cfg_locked[i] &\n+ assign pmp_cfg_we[i] = csr_we_int &\n+ ~pmp_cfg_locked[i] &\n+ ~pmp_cfg_wr_suppress[i] &\n (csr_addr == (CSR_OFF_PMP_CFG + (i[11:0] >> 2)));\n \n // Select the correct WDATA (each CSR contains 4 CFG fields, each with 2 RES bits)\n@@ -1140,6 +1159,12 @@ module ibex_cs_registers #(\n // set).\n assign pmp_cfg_locked[i] = pmp_cfg[i].lock & ~pmp_mseccfg_q.rlb;\n \n+ // When MSECCFG.MML is set cannot add new regions allowing M mode execution unless MSECCFG.RLB\n+ // is set\n+ assign pmp_cfg_wr_suppress[i] = pmp_mseccfg_q.mml &\n+ ~pmp_mseccfg.rlb &\n+ is_mml_m_exec_cfg(pmp_cfg_wdata[i]);\n+\n // --------------------------\n // Instantiate addr registers\n // --------------------------\n", "test_patch": "", "modified_files": ["rtl/ibex_cs_registers.sv"], "lines_added": 26, "lines_removed": 1} +{"repo": "lowRISC/ibex", "pr_id": 1744, "lang": "sv", "rtl_files": ["rtl/ibex_controller.sv"], "commit_id": "c4a97e05f5853b25e40fa1ea5b4edcfafba9a370", "timestamp": "2022-08-05T11:03:36+00:00", "pr_title": "Fix incorrect debug_cause priority against riscv-debug 1.0.0-STABLE", "pr_body": "The relevant page [Debug Spec v1.0.0-STABLE, p.53] gives the following\r\npriorities for resolving multiple concurrent reasons for entering debug mode....\r\n\r\n> DCSR.cause : Explains why Debug Mode was entered.\r\n> \r\n> When there are multiple reasons to enter Debug Mode in a single cycle,\r\n> hardware should set cause to the cause with the highest priority.\r\n> 1: An ebreak instruction was executed. (priority 3)\r\n> 2: A Trigger Module trigger fired with action=1. (priority 4)\r\n> 3: The debugger requested entry to Debug Mode using haltreq. (priority 1)\r\n> 4: The hart single stepped because step was set. (priority 0, lowest)\r\n> 5: The hart halted directly out of reset due to resethaltreq. (priority 2)\r\n> It is also acceptable to report 3 when this happens.\r\n> 6: The hart halted because it’s part of a halt group. (priority 5, highest)\r\n> Harts may report 3 for this cause instead.\r\n> \r\n> Other values are reserved for future use.\r\n\r\nFixes #1743 ", "issue_title": "Ibex DCSR.cause priority encoding does not match debug-spec 0.13.2 or 1.0.0-STABLE", "issue_body": "\r\n\r\n## Observed Behavior\r\n\r\nWhile testing single-step behaviour, a cosimulation-mismatch was encountered when reading DCSR.cause. It was tracked down to a simultaneous assertion of DCSR.step and debug_req_i when entering debug_mode, and I believe that the spike behaviour is correct in this case.\r\nAccording to both debug specifications [0.13.2](https://riscv.org/wp-content/uploads/2019/03/riscv-debug-release.pdf) and [1.0.0-STABLE](https://raw.githubusercontent.com/riscv/riscv-debug-spec/master/riscv-debug-stable.pdf), the priority among reporting DCSR.cause has **step** (0) as a lower priority than **haltreq** (1). Ibex [currently reports](https://ibex-core.readthedocs.io/en/latest/03_reference/debug.html#debug-support) debug support in compliance with the RISCV Debug Specification Version 0.13.\r\nCurrent ibex behaviour is a priority-encoder [which places **step** above **haltreq**](https://github.com/lowRISC/ibex/blob/c4a97e05f5853b25e40fa1ea5b4edcfafba9a370/rtl/ibex_controller.sv#L662).\r\n\r\n\r\n## Expected Behavior\r\n\r\nIbex should prioritize reporting DCSR.cause as **haltreq** above **step** when entering debug_mode with both stimulus present.\r\n", "commit_message": "Fix incorrect debug_cause priority against riscv-debug 1.0.0-STABLE\n\nThe relevant page [Debug Spec v1.0.0-STABLE, p.53] gives the following\npriorities for resolving multiple concurrent reasons for entering debug mode....\n\nDCSR.cause : Explains why Debug Mode was entered.\n\nWhen there are multiple reasons to enter Debug Mode in a single cycle,\nhardware should set cause to the cause with the highest priority.\n1: An ebreak instruction was executed. (priority 3)\n2: A Trigger Module trigger fired with action=1. (priority 4)\n3: The debugger requested entry to Debug Mode using haltreq. (priority 1)\n4: The hart single stepped because step was set. (priority 0, lowest)\n5: The hart halted directly out of reset due to resethaltreq. (priority 2)\n It is also acceptable to report 3 when this happens.\n6: The hart halted because it’s part of a halt group. (priority 5, highest)\n Harts may report 3 for this cause instead.\n\nOther values are reserved for future use.", "fix_patch": "diff --git a/rtl/ibex_controller.sv b/rtl/ibex_controller.sv\nindex f017b3a851..5ee3a6ed7c 100644\n--- a/rtl/ibex_controller.sv\n+++ b/rtl/ibex_controller.sv\n@@ -658,11 +658,11 @@ module ibex_controller #(\n \n csr_save_cause_o = 1'b1;\n if (trigger_match_i) begin\n- debug_cause_o = DBG_CAUSE_TRIGGER;\n- end else if (debug_single_step_i) begin\n- debug_cause_o = DBG_CAUSE_STEP;\n+ debug_cause_o = DBG_CAUSE_TRIGGER; // (priority 4)\n+ end else if (debug_req_i) begin\n+ debug_cause_o = DBG_CAUSE_HALTREQ; // (priority 1)\n end else begin\n- debug_cause_o = DBG_CAUSE_HALTREQ;\n+ debug_cause_o = DBG_CAUSE_STEP; // (priority 0, lowest)\n end\n \n // enter debug mode\n@@ -815,9 +815,14 @@ module ibex_controller #(\n // Leave all other signals as is to ensure CSRs and PC get set as if\n // core was entering exception handler, entry to debug mode will then\n // see the appropriate state and setup dpc correctly.\n+\n // If an EBREAK instruction is causing us to enter debug mode on the\n // same cycle as a debug_req or single step, honor the EBREAK and\n- // proceed to DBG_TAKEN_ID.\n+ // proceed to DBG_TAKEN_ID, as it has the highest priority.\n+ // [Debug Spec v1.0.0-STABLE, p.53]\n+ // cause==EBREAK -> prio 3 (highest)\n+ // cause==debug_req -> prio 2\n+ // cause==step -> prio 1 (lowest)\n if (enter_debug_mode_prio_q && !(ebrk_insn_prio && ebreak_into_debug)) begin\n ctrl_fsm_ns = DBG_TAKEN_IF;\n end\n", "test_patch": "", "modified_files": ["rtl/ibex_controller.sv"], "lines_added": 10, "lines_removed": 5} +{"repo": "lowRISC/ibex", "pr_id": 1735, "lang": "sv", "rtl_files": ["rtl/ibex_id_stage.sv"], "commit_id": "23806e2ad7d0d6fab429ae227d9a45cbd42f0fb3", "timestamp": "2022-08-05T12:50:42+00:00", "pr_title": "[rtl] Do not register instruction fetch errors", "pr_body": "Registering instruction fetch errors causes problem in the case of seeing\r\na PMP execution access block. ID/EX stage learns about\r\nthe instruction that it executed should be blocked a\r\ncycle late. This commit fixes that.\r\n\r\nFound this one while working on fixing https://github.com/lowRISC/ibex/issues/1720. However it does not fully solves the issue because we are still seeing some mismatches because of some self modifying code problems.\r\n\r\nSigned-off-by: Canberk Topal ", "issue_title": "[dv] Exception divergence using MML PMP mode", "issue_body": "\r\nI'm seeing a divergence between Spike and Ibex when in MML mode and setting region 0 to read only. Spike throws a trap and Ibex zeroes out a destination register. I'm not sure if this is an issue with Spike, Ibex or with the UVM comparison.\r\n\r\n## Observed Behavior\r\n\r\nCosimulation result:\r\n```\r\nname: riscv_epmp_mml_read_only_test\r\nseed: 14822\r\nbinary: out/run/riscv_epmp_mml_read_only_test.14822/test.o\r\nuvm_log: out/run/riscv_epmp_mml_read_only_test.14822/rtl.log\r\nrtl_trace: out/run/riscv_epmp_mml_read_only_test.14822/trace_core_00000000.log\r\nrtl_trace_csv: out/run/riscv_epmp_mml_read_only_test.14822/trace_core_00000000.log.csv\r\niss_trace: \r\niss_trace_csv: \r\nen_cosim: True\r\ncosim_trace: \r\ncosim_trace_csv: \r\ncomparison_log: \r\npassed: False\r\nfailure_message: |-\r\n UVM_FATAL /home/mvdmaas/ibex/dv/uvm/core_ibex/common/ibex_cosim_agent/ibex_cosim_scoreboard.sv(131) @ 7304: uvm_test_top.env.cosim_agent.scoreboard [ibex_cosim_agent_pkg::ibex_cosim_scoreboard.run_cosim_rvfi] Cosim mismatch Synchronous trap was expected at ISS PC: 80001900 but DUT didn't report one at PC 80000118\r\n [FAILED]: sim error seen\r\n```\r\n\r\nIbex RVFI trace:\r\n```\r\nTime\tCycle\tPC\tInsn\tDecoded instruction\tRegister and memory contents\r\n 2524\t 24\t80000080\t400015b7\tlui\tx11,0x40001\t x11=0x40001000\r\n 2864\t 41\t80000084\t10658593\taddi\tx11,x11,262\t x11:0x40001000 x11=0x40001106\r\n 3004\t 48\t80000088\t30159073\tcsrrw\tx0,misa,x11\t x11:0x40001106 x0=0x00000000\r\n 3024\t 49\t8000008c\t0002c397\tauipc\tx7,0x2c\t x7=0x8002c08c\r\n 3444\t 70\t80000090\tc5838393\taddi\tx7,x7,-936\t x7:0x8002c08c x7=0x8002bce4\r\n 3724\t 84\t80000094\t00002597\tauipc\tx11,0x2\t x11=0x80002094\r\n 3744\t 85\t80000098\t86c58593\taddi\tx11,x11,-1940\t x11:0x80002094 x11=0x80001900\r\n 3944\t 95\t8000009c\t0015e593\tori\tx11,x11,1\t x11:0x80001900 x11=0x80001901\r\n 4364\t 116\t800000a0\t30559073\tcsrrw\tx0,mtvec,x11\t x11:0x80001901 x0=0x00000000\r\n 4384\t 117\t800000a4\t00002b17\tauipc\tx22,0x2\t x22=0x800020a4\r\n 4404\t 118\t800000a8\t2f0b0b13\taddi\tx22,x22,752\t x22:0x800020a4 x22=0x80002394\r\n 4424\t 119\t800000ac\t002b5b13\tsrli\tx22,x22,0x2\t x22:0x80002394 x22=0x200008e5\r\n 4584\t 127\t800000b0\t3b0b1073\tcsrrw\tx0,pmpaddr0,x22\t x22:0x200008e5 x0=0x00000000\r\n 4604\t 128\t800000b4\t74725073\tcsrrwi\tx0,0x747,4\t x0=0x00000000\r\n 4924\t 144\t800000b8\t08c00b13\taddi\tx22,x0,140\t x0:0x00000000 x22=0x0000008c\r\n 4944\t 145\t800000bc\t3a0b1073\tcsrrw\tx0,pmpcfg0,x22\t x22:0x0000008c x0=0x00000000\r\n 4964\t 146\t800000c0\t7472d073\tcsrrwi\tx0,0x747,5\t x0=0x00000000\r\n 4984\t 147\t800000c4\t00002b17\tauipc\tx22,0x2\t x22=0x800020c4\r\n 5024\t 149\t800000c8\t2d0b0b13\taddi\tx22,x22,720\t x22:0x800020c4 x22=0x80002394\r\n 5124\t 154\t800000cc\t6589\tc.lui\tx11,0x2\t x11=0x00002000\r\n 5544\t 175\t800000ce\t66658593\taddi\tx11,x11,1638\t x11:0x00002000 x11=0x00002666\r\n 5564\t 176\t800000d2\t9b2e\tc.add\tx22,x11\t x22:0x80002394 x11:0x00002666 x22=0x800049fa\r\n 5584\t 177\t800000d4\t002b5b13\tsrli\tx22,x22,0x2\t x22:0x800049fa x22=0x2000127e\r\n 5604\t 178\t800000d8\t3b1b1073\tcsrrw\tx0,pmpaddr1,x22\t x22:0x2000127e x0=0x00000000\r\n 5664\t 181\t800000dc\t00002b17\tauipc\tx22,0x2\t x22=0x800020dc\r\n 5804\t 188\t800000e0\t2b8b0b13\taddi\tx22,x22,696\t x22:0x800020dc x22=0x80002394\r\n 5824\t 189\t800000e4\t6595\tc.lui\tx11,0x5\t x11=0x00005000\r\n 5944\t 195\t800000e6\tccc58593\taddi\tx11,x11,-820\t x11:0x00005000 x11=0x00004ccc\r\n 5964\t 196\t800000ea\t9b2e\tc.add\tx22,x11\t x22:0x80002394 x11:0x00004ccc x22=0x80007060\r\n 6364\t 216\t800000ec\t002b5b13\tsrli\tx22,x22,0x2\t x22:0x80007060 x22=0x20001c18\r\n 6384\t 217\t800000f0\t3b2b1073\tcsrrw\tx0,pmpaddr2,x22\t x22:0x20001c18 x0=0x00000000\r\n 6644\t 230\t800000f4\t00002b17\tauipc\tx22,0x2\t x22=0x800020f4\r\n 6704\t 233\t800000f8\t2a0b0b13\taddi\tx22,x22,672\t x22:0x800020f4 x22=0x80002394\r\n 6724\t 234\t800000fc\t659d\tc.lui\tx11,0x7\t x11=0x00007000\r\n 6744\t 235\t800000fe\t33258593\taddi\tx11,x11,818\t x11:0x00007000 x11=0x00007332\r\n 6764\t 236\t80000102\t9b2e\tc.add\tx22,x11\t x22:0x80002394 x11:0x00007332 x22=0x800096c6\r\n 6784\t 237\t80000104\t002b5b13\tsrli\tx22,x22,0x2\t x22:0x800096c6 x22=0x200025b1\r\n 6924\t 244\t80000108\t3b3b1073\tcsrrw\tx0,pmpaddr3,x22\t x22:0x200025b1 x0=0x00000000\r\n 7104\t 253\t8000010c\t8f8f9b37\tlui\tx22,0x8f8f9\t x22=0x8f8f9000\r\n 7124\t 254\t80000110\tf8fb0b13\taddi\tx22,x22,-113\t x22:0x8f8f9000 x22=0x8f8f8f8f\r\n 7264\t 261\t80000114\t3a0b1073\tcsrrw\tx0,pmpcfg0,x22\t x22:0x8f8f8f8f x0=0x00000000\r\n 7284\t 262\t80000118\t00002b17\tauipc\tx22,0x2\t x22=0x80002118\r\n 7304\t 263\t8000011c\t27cb0b13\taddi\tx0,x0,636\t x0:0x00000000 x0=0x00000000\r\n```\r\n\r\nSpike RVFI trace:\r\n```\r\ncore 0: 0x80000080 (0x400015b7) lui a1, 0x40001\r\ncore 0: 3 0x80000080 (0x400015b7) x11 0x40001000\r\ncore 0: 0x80000084 (0x10658593) addi a1, a1, 262\r\ncore 0: 3 0x80000084 (0x10658593) x11 0x40001106\r\ncore 0: 0x80000088 (0x30159073) csrw misa, a1\r\ncore 0: 3 0x80000088 (0x30159073) c769_misa 0x40901104\r\ncore 0: 0x8000008c (0x0002c397) auipc t2, 0x2c\r\ncore 0: 3 0x8000008c (0x0002c397) x7 0x8002c08c\r\ncore 0: 0x80000090 (0xc5838393) addi t2, t2, -936\r\ncore 0: 3 0x80000090 (0xc5838393) x7 0x8002bce4\r\ncore 0: 0x80000094 (0x00002597) auipc a1, 0x2\r\ncore 0: 3 0x80000094 (0x00002597) x11 0x80002094\r\ncore 0: 0x80000098 (0x86c58593) addi a1, a1, -1940\r\ncore 0: 3 0x80000098 (0x86c58593) x11 0x80001900\r\ncore 0: 0x8000009c (0x0015e593) ori a1, a1, 1\r\ncore 0: 3 0x8000009c (0x0015e593) x11 0x80001901\r\ncore 0: 0x800000a0 (0x30559073) csrw mtvec, a1\r\ncore 0: 3 0x800000a0 (0x30559073) c773_mtvec 0x80001901\r\ncore 0: 0x800000a4 (0x00002b17) auipc s6, 0x2\r\ncore 0: 3 0x800000a4 (0x00002b17) x22 0x800020a4\r\ncore 0: 0x800000a8 (0x2f0b0b13) addi s6, s6, 752\r\ncore 0: 3 0x800000a8 (0x2f0b0b13) x22 0x80002394\r\ncore 0: 0x800000ac (0x002b5b13) srli s6, s6, 2\r\ncore 0: 3 0x800000ac (0x002b5b13) x22 0x200008e5\r\ncore 0: 0x800000b0 (0x3b0b1073) csrw pmpaddr0, s6\r\ncore 0: 3 0x800000b0 (0x3b0b1073) c944_pmpaddr0 0x200008e5\r\ncore 0: 0x800000b4 (0x74725073) csrwi mseccfg, 4\r\ncore 0: 3 0x800000b4 (0x74725073) c1863_mseccfg 0x00000004\r\ncore 0: 0x800000b8 (0x08c00b13) li s6, 140\r\ncore 0: 3 0x800000b8 (0x08c00b13) x22 0x0000008c\r\ncore 0: 0x800000bc (0x3a0b1073) csrw pmpcfg0, s6\r\ncore 0: 3 0x800000bc (0x3a0b1073) c928_pmpcfg0 0x0000008c\r\ncore 0: 0x800000c0 (0x7472d073) csrwi mseccfg, 5\r\ncore 0: 3 0x800000c0 (0x7472d073) c1863_mseccfg 0x00000005\r\ncore 0: 0x800000c4 (0x00002b17) auipc s6, 0x2\r\ncore 0: 3 0x800000c4 (0x00002b17) x22 0x800020c4\r\ncore 0: 0x800000c8 (0x2d0b0b13) addi s6, s6, 720\r\ncore 0: 3 0x800000c8 (0x2d0b0b13) x22 0x80002394\r\ncore 0: 0x800000cc (0x00006589) c.lui a1, 0x2\r\ncore 0: 3 0x800000cc (0x6589) x11 0x00002000\r\ncore 0: 0x800000ce (0x66658593) addi a1, a1, 1638\r\ncore 0: 3 0x800000ce (0x66658593) x11 0x00002666\r\ncore 0: 0x800000d2 (0x00009b2e) c.add s6, a1\r\ncore 0: 3 0x800000d2 (0x9b2e) x22 0x800049fa\r\ncore 0: 0x800000d4 (0x002b5b13) srli s6, s6, 2\r\ncore 0: 3 0x800000d4 (0x002b5b13) x22 0x2000127e\r\ncore 0: 0x800000d8 (0x3b1b1073) csrw pmpaddr1, s6\r\ncore 0: 3 0x800000d8 (0x3b1b1073) c945_pmpaddr1 0x2000127e\r\ncore 0: 0x800000dc (0x00002b17) auipc s6, 0x2\r\ncore 0: 3 0x800000dc (0x00002b17) x22 0x800020dc\r\ncore 0: 0x800000e0 (0x2b8b0b13) addi s6, s6, 696\r\ncore 0: 3 0x800000e0 (0x2b8b0b13) x22 0x80002394\r\ncore 0: 0x800000e4 (0x00006595) c.lui a1, 0x5\r\ncore 0: 3 0x800000e4 (0x6595) x11 0x00005000\r\ncore 0: 0x800000e6 (0xccc58593) addi a1, a1, -820\r\ncore 0: 3 0x800000e6 (0xccc58593) x11 0x00004ccc\r\ncore 0: 0x800000ea (0x00009b2e) c.add s6, a1\r\ncore 0: 3 0x800000ea (0x9b2e) x22 0x80007060\r\ncore 0: 0x800000ec (0x002b5b13) srli s6, s6, 2\r\ncore 0: 3 0x800000ec (0x002b5b13) x22 0x20001c18\r\ncore 0: 0x800000f0 (0x3b2b1073) csrw pmpaddr2, s6\r\ncore 0: 3 0x800000f0 (0x3b2b1073) c946_pmpaddr2 0x20001c18\r\ncore 0: 0x800000f4 (0x00002b17) auipc s6, 0x2\r\ncore 0: 3 0x800000f4 (0x00002b17) x22 0x800020f4\r\ncore 0: 0x800000f8 (0x2a0b0b13) addi s6, s6, 672\r\ncore 0: 3 0x800000f8 (0x2a0b0b13) x22 0x80002394\r\ncore 0: 0x800000fc (0x0000659d) c.lui a1, 0x7\r\ncore 0: 3 0x800000fc (0x659d) x11 0x00007000\r\ncore 0: 0x800000fe (0x33258593) addi a1, a1, 818\r\ncore 0: 3 0x800000fe (0x33258593) x11 0x00007332\r\ncore 0: 0x80000102 (0x00009b2e) c.add s6, a1\r\ncore 0: 3 0x80000102 (0x9b2e) x22 0x800096c6\r\ncore 0: 0x80000104 (0x002b5b13) srli s6, s6, 2\r\ncore 0: 3 0x80000104 (0x002b5b13) x22 0x200025b1\r\ncore 0: 0x80000108 (0x3b3b1073) csrw pmpaddr3, s6\r\ncore 0: 3 0x80000108 (0x3b3b1073) c947_pmpaddr3 0x200025b1\r\ncore 0: 0x8000010c (0x8f8f9b37) lui s6, 0x8f8f9\r\ncore 0: 3 0x8000010c (0x8f8f9b37) x22 0x8f8f9000\r\ncore 0: 0x80000110 (0xf8fb0b13) addi s6, s6, -113\r\ncore 0: 3 0x80000110 (0xf8fb0b13) x22 0x8f8f8f8f\r\ncore 0: 0x80000114 (0x3a0b1073) csrw pmpcfg0, s6\r\ncore 0: 3 0x80000114 (0x3a0b1073) c928_pmpcfg0 0x8f8f8f8f\r\ncore 0: exception trap_instruction_access_fault, epc 0x80000118\r\ncore 0: tval 0x80000118\r\n```\r\n\r\n## Expected Behavior\r\n\r\nNot sure if it's a bug in Spike, Ibex or the cosimulation environment\r\n\r\n## Steps to reproduce the issue\r\n\r\nUsing the following commands from the root of the ibex repo:\r\n```console\r\ncd dv/uvm/core_ibex\r\nmake -j7 --keep-going IBEX_CONFIG=opentitan ITERATIONS=1 SEED=14822 TEST=riscv_epmp_mml_read_only_test WAVES=0 COV=0\r\n```\r\n\r\n## My Environment\r\n\r\n\r\n\r\n**EDA tool and version:**\r\n\r\nUsing Spike version ibex_cosim on commit: 9af9730baf7b956c3072c1b436d867aca5ef8f4c\r\n\r\n**Operating system:**\r\n\r\nUbuntu Linux 20.04\r\n\r\n**Version of the Ibex source code:**\r\n\r\nCurrently running inside this PR: https://github.com/lowRISC/ibex/pull/1695\r\n", "commit_message": "[rtl] Flush controller in PMP CSR write ops\n\nAs Greg pointed out:\n\nWhen we have an instruction in ID/EX that writes a PMP register that\nupdate gets written to the CSR the same cycle the next instruction\nmoves from IF to ID/EX with it's PMP check done with the old value.\n\nThe solution is to flush the pipeline when we get a PMP CSR write.\n\nSigned-off-by: Canberk Topal ", "fix_patch": "diff --git a/rtl/ibex_id_stage.sv b/rtl/ibex_id_stage.sv\nindex a1c9c0f82c..9cdc64d3f9 100644\n--- a/rtl/ibex_id_stage.sv\n+++ b/rtl/ibex_id_stage.sv\n@@ -502,7 +502,7 @@ module ibex_id_stage #(\n );\n \n /////////////////////////////////\n- // CSR-related pipline flushes //\n+ // CSR-related pipeline flushes //\n /////////////////////////////////\n always_comb begin : csr_pipeline_flushes\n csr_pipe_flush = 1'b0;\n@@ -511,10 +511,14 @@ module ibex_id_stage #(\n // - When enabling interrupts, pending IRQs become visible to the controller only during\n // the next cycle. If during that cycle the core disables interrupts again, it does not\n // see any pending IRQs and consequently does not start to handle interrupts.\n+ // - When modifying any PMP CSR, PMP check of the next instruction might get invalidated.\n+ // Hence, a pipeline flush is needed to instantiate another PMP check with the updated CSRs.\n // - When modifying debug CSRs - TODO: Check if this is really needed\n if (csr_op_en_o == 1'b1 && (csr_op_o == CSR_OP_WRITE || csr_op_o == CSR_OP_SET)) begin\n- if (csr_num_e'(instr_rdata_i[31:20]) == CSR_MSTATUS ||\n- csr_num_e'(instr_rdata_i[31:20]) == CSR_MIE) begin\n+ if (csr_num_e'(instr_rdata_i[31:20]) == CSR_MSTATUS ||\n+ csr_num_e'(instr_rdata_i[31:20]) == CSR_MIE ||\n+ // To catch all PMPCFG/PMPADDR registers, get the shared top most 7 bits.\n+ instr_rdata_i[31:25] == 7'h1D) begin\n csr_pipe_flush = 1'b1;\n end\n end else if (csr_op_en_o == 1'b1 && csr_op_o != CSR_OP_READ) begin\n", "test_patch": "", "modified_files": ["rtl/ibex_id_stage.sv"], "lines_added": 7, "lines_removed": 3} +{"repo": "lowRISC/ibex", "pr_id": 1725, "lang": "sv", "rtl_files": ["rtl/ibex_top.sv"], "commit_id": "7bae3b7ba34d9611bc263d84bd358ec5021f82d3", "timestamp": "2022-07-26T15:58:31+00:00", "pr_title": "[dv] Fix IbexDataRPayloadX assertion", "pr_body": "Some aspects of the memory response are only relevant to reads. This\r\nintroduces outstanding request tracking so we know which outstanding\r\nrequests are reads and applies X checks appropriately.\r\n\r\nFixes #1645", "issue_title": "Simple system VCS simulation fails with multiple errors", "issue_body": "\r\n\r\n\r\nI want to simulate the simple system example using VCS, the build passes without any issue, but when I run the simulation, I get multiple errors caused by failed assertion\r\n\r\n## My Environment\r\n\r\n\r\n\r\n**EDA tool and version:**\r\n\r\nVCS S-2021.09-SP1_Full64\r\n**Operating system:**\r\nRed Hat Enterprise Linux release 8.5 \r\n\r\n**Version of the Ibex source code:**\r\n master branch hash : 668856441a73ebd067c09fdd2432241a32b8f03d\r\n\r\n**first part of the long errors list**\r\n\r\nChronologic VCS simulator copyright 1991-2021\r\nContains Synopsys proprietary information.\r\nCompiler version S-2021.09-SP1_Full64; Runtime version S-2021.09-SP1_Full64; May 2 13:47 2022\r\nInitializing memory ibex_simple_system.u_ram.u_ram.gen_generic.u_impl_generic.unnamed$$_2.gen_meminit from file './examples/sw/simple_system/hello_test/hello_test.vmem'.\r\n\"../src/lowrisc_ibex_ibex_top_0.1/rtl/ibex_top.sv\", 982: ibex_simple_system.u_top.u_ibex_top.IbexInstrReqX: started at 18s failed at 18s\r\n\tOffending '(!$isunknown(instr_req_o))'\r\nError: \"../src/lowrisc_ibex_ibex_top_0.1/rtl/ibex_top.sv\", 982: ibex_simple_system.u_top.u_ibex_top.IbexInstrReqX: at time 18\r\n18: (../src/lowrisc_ibex_ibex_top_0.1/rtl/ibex_top.sv:982) [ibex_simple_system.u_top.u_ibex_top.IbexInstrReqX] [ASSERT FAILED] IbexInstrReqX\r\n\"../src/lowrisc_ibex_ibex_top_0.1/rtl/ibex_top.sv\", 983: ibex_simple_system.u_top.u_ibex_top.IbexInstrReqPayloadXKnownEnable: started at 18s failed at 18s\r\n\tOffending '(!$isunknown(instr_req_o))'\r\nError: \"../src/lowrisc_ibex_ibex_top_0.1/rtl/ibex_top.sv\", 983: ibex_simple_system.u_top.u_ibex_top.IbexInstrReqPayloadXKnownEnable: at time 18\r\n18: (../src/lowrisc_ibex_ibex_top_0.1/rtl/ibex_top.sv:983) [ibex_simple_system.u_top.u_ibex_top.IbexInstrReqPayloadXKnownEnable] [ASSERT FAILED] IbexInstrReqPayloadXKnownEnable\r\n\"../src/lowrisc_ibex_ibex_top_0.1/rtl/ibex_top.sv\", 1002: ibex_simple_system.u_top.u_ibex_top.IbexInstrGntX: started at 18s failed at 18s\r\n\tOffending '(!$isunknown(instr_gnt_i))'\r\nError: \"../src/lowrisc_ibex_ibex_top_0.1/rtl/ibex_top.sv\", 1002: ibex_simple_system.u_top.u_ibex_top.IbexInstrGntX: at time 18\r\n18: (../src/lowrisc_ibex_ibex_top_0.1/rtl/ibex_top.sv:1002) [ibex_simple_system.u_top.u_ibex_top.IbexInstrGntX] [ASSERT FAILED] IbexInstrGntX\r\n\"../src/lowrisc_ibex_ibex_top_0.1/rtl/ibex_top.sv\", 982: ibex_simple_system.u_top.u_ibex_top.IbexInstrReqX: started at 20s failed at 20s\r\n\tOffending '(!$isunknown(instr_req_o))'\r\nError: \"../src/lowrisc_ibex_ibex_top_0.1/rtl/ibex_top.sv\", 982: ibex_simple_system.u_top.u_ibex_top.IbexInstrReqX: at time 20\r\n20: (../src/lowrisc_ibex_ibex_top_0.1/rtl/ibex_top.sv:982) [ibex_simple_system.u_top.u_ibex_top.IbexInstrReqX] [ASSERT FAILED] IbexInstrReqX\r\n", "commit_message": "[dv] Fix IbexDataRPayloadX assertion\n\nSome aspects of the memory response are only relevant to reads. This\nintroduces outstanding request tracking so we know which outstanding\nrequests are reads and applies X checks appropriately.\n\nFixes #1645", "fix_patch": "diff --git a/rtl/ibex_top.sv b/rtl/ibex_top.sv\nindex e6056d1c58..01343f0a3b 100644\n--- a/rtl/ibex_top.sv\n+++ b/rtl/ibex_top.sv\n@@ -1045,7 +1045,78 @@ module ibex_top import ibex_pkg::*; #(\n \n `ASSERT_KNOWN(IbexDataGntX, data_gnt_i)\n `ASSERT_KNOWN(IbexDataRValidX, data_rvalid_i)\n- `ASSERT_KNOWN_IF(IbexDataRPayloadX, {data_rdata_i, data_rdata_intg_i, data_err_i}, data_rvalid_i)\n+ `ifdef INC_ASSERT\n+ // Ibex can have a maximum of 2 accesses outstanding on the DSide. This is because it does not\n+ // speculative data accesses so the only requests that can be in flight must relate to a single\n+ // ongoing load or store instruction. Due to unaligned access support a single load or store can\n+ // generate 2 accesses.\n+ localparam int unsigned MaxOutstandingDSideAccesses = 2;\n+\n+ typedef struct packed {\n+ logic valid;\n+ logic is_read;\n+ } pending_access_t;\n+\n+ pending_access_t pending_dside_accesses_q[MaxOutstandingDSideAccesses];\n+ pending_access_t pending_dside_accesses_d[MaxOutstandingDSideAccesses];\n+ pending_access_t pending_dside_accesses_shifted[MaxOutstandingDSideAccesses];\n+\n+ for (genvar i = 0; i < MaxOutstandingDSideAccesses; i++) begin : g_dside_tracker\n+ always_ff @(posedge clk or negedge rst_ni) begin\n+ if (!rst_ni) begin\n+ pending_dside_accesses_q[i] <= '0;\n+ end else begin\n+ pending_dside_accesses_q[i] <= pending_dside_accesses_d[i];\n+ end\n+ end\n+\n+ always_comb begin\n+ pending_dside_accesses_shifted[i] = pending_dside_accesses_q[i];\n+\n+ if (data_rvalid_i) begin\n+ if (i != MaxOutstandingDSideAccesses - 1) begin\n+ pending_dside_accesses_shifted[i] = pending_dside_accesses_q[i + 1];\n+ end else begin\n+ pending_dside_accesses_shifted[i] = '0;\n+ end\n+ end\n+ end\n+\n+ always_comb begin\n+ pending_dside_accesses_d[i] = pending_dside_accesses_shifted[i];\n+\n+ if (data_req_o && data_gnt_i) begin\n+ if (i == 0 && !pending_dside_accesses_shifted[i].valid) begin\n+ pending_dside_accesses_d[i].valid = 1'b1;\n+ pending_dside_accesses_d[i].is_read = ~data_we_o;\n+ end else if (pending_dside_accesses_shifted[i - 1].valid &\n+ !pending_dside_accesses_shifted[i].valid) begin\n+ pending_dside_accesses_d[i].valid = 1'b1;\n+ pending_dside_accesses_d[i].is_read = ~data_we_o;\n+ end\n+ end\n+ end\n+ end\n+\n+ // We should never start a new data request if we've already got the maximum outstanding. We can\n+ // start a new request in the same cycle an old one ends, in which case we'll see all pending\n+ // accesses valid but one will be ending this cycle so the empty slot can be immediately used by\n+ // the new request.\n+ `ASSERT(MaxOutstandingDSideAccessesCorrect,\n+ data_req_o |->\n+ ~pending_dside_accesses_d[MaxOutstandingDSideAccesses-1].valid | data_rvalid_i)\n+\n+ // Should only see a request response if we're expecting one\n+ `ASSERT(PendingAccessTrackingCorrect, data_rvalid_i |-> pending_dside_accesses_q[0])\n+\n+ // data_rdata_i and data_rdata_intg_i are only relevant to reads. Check neither are X on\n+ // a response to a read.\n+ `ASSERT_KNOWN_IF(IbexDataRPayloadX, {data_rdata_i, data_rdata_intg_i},\n+ data_rvalid_i & pending_dside_accesses_q[0].is_read)\n+\n+ // data_err_i relevant to both reads and writes. Check it isn't X on any response.\n+ `ASSERT_KNOWN_IF(IbexDataRErrPayloadX, data_err_i, data_rvalid_i)\n+ `endif\n \n `ASSERT_KNOWN(IbexIrqX, {irq_software_i, irq_timer_i, irq_external_i, irq_fast_i, irq_nm_i})\n \n", "test_patch": "", "modified_files": ["rtl/ibex_top.sv"], "lines_added": 72, "lines_removed": 1} +{"repo": "lowRISC/ibex", "pr_id": 1699, "lang": "sv", "rtl_files": ["dv/uvm/core_ibex/env/core_ibex_dut_probe_if.sv"], "commit_id": "ab510f8acf2804efbe0a8d4cf93452b02acc05fe", "timestamp": "2022-07-12T15:02:03+00:00", "pr_title": "[dv] Check privilege correctly after illegal insn", "pr_body": "Timing fix for dret_test and modelling controller behaviour for `FLUSH` transition.\r\n\r\nResolves #1691\r\n\r\nSigned-off-by: Canberk Topal ", "issue_title": "[dv] riscv_dret_test fails privilege mode check", "issue_body": "\r\n\r\n## Observed Behavior\r\n\r\nUVM fail with the error message below: \r\n\r\n`Check failed dut_vif.dut_cb.priv_mode == mode (0 [0x0] vs 3 [0x3]) Incorrect privilege mode`\r\n\r\n## Expected Behavior\r\n\r\nI think this happened because `dret` actually changes our privilege level and if our privilege level is `U` before entering debug, we'll set the privilege as so after receiving `dret`. So I believe the problem comes from us using `check_illegal_insn` task after we have a `dret`.\r\n## Steps to reproduce the issue\r\n\r\nRun this command while at the repository top.\r\n``` make -C dv/uvm/core_ibex TEST=riscv_dret_test ITERATIONS=1 SIMULATOR=xlm -j2 SEED=22633 ```\r\n", "commit_message": "[dv] Check privilege after DRET\n\nTiming fix for dret_test and modelling controller behaviour for FLUSH transition.\n\nSigned-off-by: Canberk Topal ", "fix_patch": "diff --git a/dv/uvm/core_ibex/env/core_ibex_dut_probe_if.sv b/dv/uvm/core_ibex/env/core_ibex_dut_probe_if.sv\nindex 43cab77fb9..24a35f93dc 100644\n--- a/dv/uvm/core_ibex/env/core_ibex_dut_probe_if.sv\n+++ b/dv/uvm/core_ibex/env/core_ibex_dut_probe_if.sv\n@@ -18,6 +18,7 @@ interface core_ibex_dut_probe_if(input logic clk);\n logic alert_major_bus;\n logic debug_req;\n ibex_pkg::priv_lvl_e priv_mode;\n+ ibex_pkg::ctrl_fsm_e ctrl_fsm_cs;\n \n clocking dut_cb @(posedge clk);\n output fetch_enable;\n@@ -34,6 +35,7 @@ interface core_ibex_dut_probe_if(input logic clk);\n input alert_major_internal;\n input alert_major_bus;\n input priv_mode;\n+ input ctrl_fsm_cs;\n endclocking\n \n initial begin\n", "test_patch": "diff --git a/dv/uvm/core_ibex/tb/core_ibex_tb_top.sv b/dv/uvm/core_ibex/tb/core_ibex_tb_top.sv\nindex 0efc4a5f9e..32a3215530 100644\n--- a/dv/uvm/core_ibex/tb/core_ibex_tb_top.sv\n+++ b/dv/uvm/core_ibex/tb/core_ibex_tb_top.sv\n@@ -191,6 +191,7 @@ module core_ibex_tb_top;\n assign dut_if.mret = dut.u_ibex_top.u_ibex_core.id_stage_i.controller_i.mret_insn;\n assign dut_if.reset = ~rst_n;\n assign dut_if.priv_mode = dut.u_ibex_top.u_ibex_core.priv_mode_id;\n+ assign dut_if.ctrl_fsm_cs = dut.u_ibex_top.u_ibex_core.id_stage_i.controller_i.ctrl_fsm_cs;\n // Instruction monitor connections\n assign instr_monitor_if.reset = ~rst_n;\n assign instr_monitor_if.valid_id = dut.u_ibex_top.u_ibex_core.id_stage_i.instr_valid_i;\ndiff --git a/dv/uvm/core_ibex/tests/core_ibex_test_lib.sv b/dv/uvm/core_ibex/tests/core_ibex_test_lib.sv\nindex 063ed0c2ff..7d1946f017 100644\n--- a/dv/uvm/core_ibex/tests/core_ibex_test_lib.sv\n+++ b/dv/uvm/core_ibex/tests/core_ibex_test_lib.sv\n@@ -491,9 +491,13 @@ class core_ibex_directed_test extends core_ibex_debug_intr_basic_test;\n // Illegal instruction checker\n virtual task check_illegal_insn(string exception_msg);\n check_next_core_status(HANDLING_EXCEPTION, \"Core did not jump to vectored exception handler\", 1000);\n- check_priv_mode(PRIV_LVL_M);\n check_next_core_status(ILLEGAL_INSTR_EXCEPTION, exception_msg, 1000);\n check_mcause(1'b0, ExcCauseIllegalInsn);\n+ // Ibex will wait to change the privilege mode until it is allowed to FLUSH. This happens because\n+ // we are blocking the current instruction until the instruction from WB stage is ready.\n+ wait (dut_vif.dut_cb.ctrl_fsm_cs == FLUSH);\n+ clk_vif.wait_clks(2);\n+ check_priv_mode(PRIV_LVL_M);\n wait_ret(\"mret\", 1500);\n endtask\n \n", "modified_files": ["dv/uvm/core_ibex/env/core_ibex_dut_probe_if.sv", "dv/uvm/core_ibex/tb/core_ibex_tb_top.sv", "dv/uvm/core_ibex/tests/core_ibex_test_lib.sv"], "lines_added": 8, "lines_removed": 1} +{"repo": "lowRISC/ibex", "pr_id": 1643, "lang": "sv", "rtl_files": ["rtl/ibex_top.sv"], "commit_id": "e34bb4d92f602ed1dde464da67818f99b5a1ed81", "timestamp": "2022-05-04T13:40:00+00:00", "pr_title": "Instantiate plain memory primitives for ICache when ICache scrambling is disabled", "pr_body": "Opening a PR to resolve issue #1514. Plain (ie. not scrambled) memory primitives are instantiated conditionally when parameter ICacheScramble=0. This change eliminates some unused logic when scrambling is disabled.\r\n\r\nI have successfully run riscv_machine_mode_rand_test with and without ICache enabled, as well as with and without ICache scrambling enabled. I have also run synthesis and see a minor reduction in cell area about 10-15% when ICache is enabled without scrambling, not including memory area itself.", "issue_title": "Use plain memory primitives when ICache scrambling is disabled", "issue_body": "The recent PR to add scrambling support to the ICache lacks an option to allow the use of non-scrambled RAMs. Scrambling is only of interest to applications requiring security hardening, other applications may simply want an ICache without scrambled memories.", "commit_message": "Update ibex_top.sv\n\nAdding conditional to instantiate non-scrambling instruction cache memories when ICacheScramble parameter is not set.", "fix_patch": "diff --git a/rtl/ibex_top.sv b/rtl/ibex_top.sv\nindex ab4934b095..5b5c691d53 100644\n--- a/rtl/ibex_top.sv\n+++ b/rtl/ibex_top.sv\n@@ -514,73 +514,117 @@ module ibex_top import ibex_pkg::*; #(\n \n for (genvar way = 0; way < IC_NUM_WAYS; way++) begin : gen_rams_inner\n \n- // SEC_CM: ICACHE.MEM.SCRAMBLE\n- // Tag RAM instantiation\n- prim_ram_1p_scr #(\n- .Width (TagSizeECC),\n- .Depth (IC_NUM_LINES),\n- .DataBitsPerMask (TagSizeECC),\n- .EnableParity (0),\n- .DiffWidth (TagSizeECC),\n- .NumAddrScrRounds (NumAddrScrRounds),\n- .NumDiffRounds (NumDiffRounds)\n- ) tag_bank (\n- .clk_i,\n- .rst_ni,\n-\n- .key_valid_i (scramble_key_valid_q),\n- .key_i (scramble_key_q),\n- .nonce_i (scramble_nonce_q),\n-\n- .req_i (ic_tag_req[way]),\n-\n- .gnt_o (),\n- .write_i (ic_tag_write),\n- .addr_i (ic_tag_addr),\n- .wdata_i (ic_tag_wdata),\n- .wmask_i ({TagSizeECC{1'b1}}),\n- .intg_error_i(1'b0),\n-\n- .rdata_o (ic_tag_rdata[way]),\n- .rvalid_o (),\n- .raddr_o (),\n- .rerror_o (),\n- .cfg_i (ram_cfg_i)\n- );\n+ if (ICacheScramble) begin : gen_scramble_rams\n+\n+ // SEC_CM: ICACHE.MEM.SCRAMBLE\n+ // Tag RAM instantiation\n+ prim_ram_1p_scr #(\n+ .Width (TagSizeECC),\n+ .Depth (IC_NUM_LINES),\n+ .DataBitsPerMask (TagSizeECC),\n+ .EnableParity (0),\n+ .DiffWidth (TagSizeECC),\n+ .NumAddrScrRounds (NumAddrScrRounds),\n+ .NumDiffRounds (NumDiffRounds)\n+ ) tag_bank (\n+ .clk_i,\n+ .rst_ni,\n+\n+ .key_valid_i (scramble_key_valid_q),\n+ .key_i (scramble_key_q),\n+ .nonce_i (scramble_nonce_q),\n+\n+ .req_i (ic_tag_req[way]),\n+\n+ .gnt_o (),\n+ .write_i (ic_tag_write),\n+ .addr_i (ic_tag_addr),\n+ .wdata_i (ic_tag_wdata),\n+ .wmask_i ({TagSizeECC{1'b1}}),\n+ .intg_error_i(1'b0),\n+\n+ .rdata_o (ic_tag_rdata[way]),\n+ .rvalid_o (),\n+ .raddr_o (),\n+ .rerror_o (),\n+ .cfg_i (ram_cfg_i)\n+ );\n+\n+ // Data RAM instantiation\n+ prim_ram_1p_scr #(\n+ .Width (LineSizeECC),\n+ .Depth (IC_NUM_LINES),\n+ .DataBitsPerMask (LineSizeECC),\n+ .ReplicateKeyStream (1),\n+ .EnableParity (0),\n+ .DiffWidth (LineSizeECC),\n+ .NumAddrScrRounds (NumAddrScrRounds),\n+ .NumDiffRounds (NumDiffRounds)\n+ ) data_bank (\n+ .clk_i,\n+ .rst_ni,\n+\n+ .key_valid_i (scramble_key_valid_q),\n+ .key_i (scramble_key_q),\n+ .nonce_i (scramble_nonce_q),\n+\n+ .req_i (ic_data_req[way]),\n+\n+ .gnt_o (),\n+ .write_i (ic_data_write),\n+ .addr_i (ic_data_addr),\n+ .wdata_i (ic_data_wdata),\n+ .wmask_i ({LineSizeECC{1'b1}}),\n+ .intg_error_i(1'b0),\n+\n+ .rdata_o (ic_data_rdata[way]),\n+ .rvalid_o (),\n+ .raddr_o (),\n+ .rerror_o (),\n+ .cfg_i (ram_cfg_i)\n+ );\n+\n+ end else begin : gen_noscramble_rams\n+\n+ // Tag RAM instantiation\n+ prim_ram_1p #(\n+ .Width (TagSizeECC),\n+ .Depth (IC_NUM_LINES),\n+ .DataBitsPerMask (TagSizeECC)\n+ ) tag_bank (\n+ .clk_i,\n+\n+ .req_i (ic_tag_req[way]),\n+\n+ .write_i (ic_tag_write),\n+ .addr_i (ic_tag_addr),\n+ .wdata_i (ic_tag_wdata),\n+ .wmask_i ({TagSizeECC{1'b1}}),\n+\n+ .rdata_o (ic_tag_rdata[way]),\n+ .cfg_i (ram_cfg_i)\n+ );\n+\n+ // Data RAM instantiation\n+ prim_ram_1p #(\n+ .Width (LineSizeECC),\n+ .Depth (IC_NUM_LINES),\n+ .DataBitsPerMask (LineSizeECC)\n+ ) data_bank (\n+ .clk_i,\n+\n+ .req_i (ic_data_req[way]),\n+\n+ .write_i (ic_data_write),\n+ .addr_i (ic_data_addr),\n+ .wdata_i (ic_data_wdata),\n+ .wmask_i ({LineSizeECC{1'b1}}),\n+\n+ .rdata_o (ic_data_rdata[way]),\n+ .cfg_i (ram_cfg_i)\n+ );\n \n- // Data RAM instantiation\n- prim_ram_1p_scr #(\n- .Width (LineSizeECC),\n- .Depth (IC_NUM_LINES),\n- .DataBitsPerMask (LineSizeECC),\n- .ReplicateKeyStream (1),\n- .EnableParity (0),\n- .DiffWidth (LineSizeECC),\n- .NumAddrScrRounds (NumAddrScrRounds),\n- .NumDiffRounds (NumDiffRounds)\n- ) data_bank (\n- .clk_i,\n- .rst_ni,\n-\n- .key_valid_i (scramble_key_valid_q),\n- .key_i (scramble_key_q),\n- .nonce_i (scramble_nonce_q),\n-\n- .req_i (ic_data_req[way]),\n-\n- .gnt_o (),\n- .write_i (ic_data_write),\n- .addr_i (ic_data_addr),\n- .wdata_i (ic_data_wdata),\n- .wmask_i ({LineSizeECC{1'b1}}),\n- .intg_error_i(1'b0),\n-\n- .rdata_o (ic_data_rdata[way]),\n- .rvalid_o (),\n- .raddr_o (),\n- .rerror_o (),\n- .cfg_i (ram_cfg_i)\n- );\n+ end\n end\n \n end else begin : gen_norams\n", "test_patch": "", "modified_files": ["rtl/ibex_top.sv"], "lines_added": 110, "lines_removed": 66} +{"repo": "lowRISC/ibex", "pr_id": 1620, "lang": "sv", "rtl_files": ["rtl/ibex_pkg.sv"], "commit_id": "8d044a3ddce53dba4652083b404a4821a7bc9be9", "timestamp": "2022-04-19T14:11:25+00:00", "pr_title": "Update fetch enable encoding", "pr_body": "This is done to match the encoding update done in the OpenTitan repo\r\nhere: [#12153](https://github.com/lowRISC/opentitan/pull/12153)\r\n\r\nSigned-off-by: Michael Schaffner ", "issue_title": "", "issue_body": "", "commit_message": "Update fetch enable encoding\n\nThis is done to match the encoding update done in the OpenTitan repo\nhere: https://github.com/lowRISC/opentitan/pull/12153\n\nSigned-off-by: Michael Schaffner ", "fix_patch": "diff --git a/rtl/ibex_pkg.sv b/rtl/ibex_pkg.sv\nindex 813f78ab4d..4dcae7b33b 100644\n--- a/rtl/ibex_pkg.sv\n+++ b/rtl/ibex_pkg.sv\n@@ -648,6 +648,6 @@ package ibex_pkg;\n // for Off. This allows the use of FetchEnableOn/FetchEnableOff to work for both secure and\n // non-secure Ibex. If this assumption is broken the RTL that uses the fetch_enable signal within\n // `ibex_core` may need adjusting.\n- parameter fetch_enable_t FetchEnableOn = 4'b1001;\n- parameter fetch_enable_t FetchEnableOff = 4'b0110;\n+ parameter fetch_enable_t FetchEnableOn = 4'b0101;\n+ parameter fetch_enable_t FetchEnableOff = 4'b1010;\n endpackage\n", "test_patch": "", "modified_files": ["rtl/ibex_pkg.sv"], "lines_added": 2, "lines_removed": 2} +{"repo": "lowRISC/ibex", "pr_id": 1595, "lang": "sv", "rtl_files": ["shared/rtl/ram_2p.sv"], "commit_id": "2fc4cde7d269e69c77f784468959779cef2f3a55", "timestamp": "2022-04-01T14:32:46+00:00", "pr_title": "[ram_2p] Set DataBitsPerMask parameter for prim_ram_2p", "pr_body": "It turned out that with the default value of 1, Vivado infers a separate 18 Kbit BRAM instance for each bit of the 32-bit word for the FPGA examples. This can be very wasteful in terms of resource utilization especially for smaller configurations.\r\n\r\nAs our examples don't use ECC or parity and mainly target simualation and FPGA, it's better to use a value of 8 for the DataBitsPerMask parameter. Vivado will then not distribute words across different BRAM instances which results in more efficient FPGA resource utilization.\r\n\r\nFor a detailed analysis and explanation, please refer to lowRISC/Ibex#1587.", "issue_title": "changing MEM_SIZE does not affect BRAM utilization ", "issue_body": "I wanted to check if 2 KB memory works with IBEX ARTY A7 example. The default is 64 KB with FPGAPowerAnalysis option set to '0' and 256 KB otherwise.\r\n\r\nI changed top_artya7.sv file such as:\r\n// parameter int MEM_SIZE = FPGAPowerAnalysis == 0 ? 64 * 1024 : 256 * 1024;\r\n parameter int MEM_SIZE = 2 * 1024; // use 2 KB RAM for instr & data\r\n\r\nI checked both synthesis results for 64 KB and 2 KB, somehow BRAM utilization numbers are the same: 16\r\n\r\nI checked synth reports (top_artya7.vds) and synth utilization reports (top_artya7_utilization_synth.rpt) and be sure that the parameters related to memory are really consistent according to my changes: \r\n\r\nThe log for 2 KB synth from top_artya7.vds\r\n\r\nINFO: [Synth 8-6157] synthesizing module 'top_artya7' [/home/mbaykenar/ibex_mba/ibex/build/lowrisc_ibex_top_artya7_0.1/src/lowrisc_ibex_top_artya7_0.1/rtl/top_artya7.sv:5]\r\n Parameter FPGAPowerAnalysis bound to: 32'sb00000000000000000000000000000000\r\n Parameter MEM_SIZE bound to: 32'sb00000000000000000000100000000000\r\n Parameter MEM_START bound to: 0 - type: integer\r\n Parameter MEM_MASK bound to: 32'b00000000000000000000011111111111\r\n Parameter SRAMInitFile bound to: ../../../../../examples/sw/led/led.vmem - type: string\r\n\r\nINFO: [Synth 8-6157] synthesizing module 'ram_2p' [/home/mbaykenar/ibex_mba/ibex/build/lowrisc_ibex_top_artya7_0.1/src/lowrisc_ibex_fpga_xilinx_shared_0/rtl/ram_2p.sv:11]\r\n Parameter Depth bound to: 32'sb00000000000000000000001000000000\r\n Parameter MemInitFile bound to: ../../../../../examples/sw/led/led.vmem - type: string\r\n Parameter Aw bound to: 32'sb00000000000000000000000000001001\r\nINFO: [Synth 8-6157] synthesizing module 'prim_ram_2p' [/home/mbaykenar/ibex_mba/ibex/build/lowrisc_ibex_top_artya7_0.1/src/lowrisc_prim_abstract_ram_2p_0/prim_ram_2p.sv:14]\r\n Parameter Width bound to: 32'sb00000000000000000000000000100000\r\n Parameter Depth bound to: 32'sb00000000000000000000001000000000\r\n Parameter DataBitsPerMask bound to: 32'sb00000000000000000000000000000001\r\n Parameter MemInitFile bound to: ../../../../../examples/sw/led/led.vmem - type: string\r\n Parameter Aw bound to: 32'sb00000000000000000000000000001001\r\nINFO: [Synth 8-6157] synthesizing module 'prim_generic_ram_2p' [/home/mbaykenar/ibex_mba/ibex/build/lowrisc_ibex_top_artya7_0.1/src/lowrisc_prim_generic_ram_2p_0/rtl/prim_generic_ram_2p.sv:9]\r\n Parameter Width bound to: 32'sb00000000000000000000000000100000\r\n Parameter Depth bound to: 32'sb00000000000000000000001000000000\r\n Parameter DataBitsPerMask bound to: 32'sb00000000000000000000000000000001\r\n Parameter MemInitFile bound to: ../../../../../examples/sw/led/led.vmem - type: string\r\n Parameter Aw bound to: 32'sb00000000000000000000000000001001\r\n Parameter MaskWidth bound to: 32'sb00000000000000000000000000100000\r\n\r\nThe log for 64 KB synth:\r\n\r\nINFO: [Synth 8-6157] synthesizing module 'top_artya7' [/home/mbaykenar/ibex_mba/ibex/build/lowrisc_ibex_top_artya7_0.1/src/lowrisc_ibex_top_artya7_0.1/rtl/top_artya7.sv:5]\r\n Parameter FPGAPowerAnalysis bound to: 32'sb00000000000000000000000000000000\r\n Parameter MEM_SIZE bound to: 32'sb00000000000000010000000000000000\r\n Parameter MEM_START bound to: 0 - type: integer\r\n Parameter MEM_MASK bound to: 32'b00000000000000001111111111111111\r\n Parameter SRAMInitFile bound to: ../../../../../examples/sw/led/led.vmem - type: string\r\n\r\nINFO: [Synth 8-6157] synthesizing module 'ram_2p' [/home/mbaykenar/ibex_mba/ibex/build/lowrisc_ibex_top_artya7_0.1/src/lowrisc_ibex_fpga_xilinx_shared_0/rtl/ram_2p.sv:11]\r\n Parameter Depth bound to: 32'sb00000000000000000100000000000000\r\n Parameter MemInitFile bound to: ../../../../../examples/sw/led/led.vmem - type: string\r\n Parameter Aw bound to: 32'sb00000000000000000000000000001110\r\nINFO: [Synth 8-6157] synthesizing module 'prim_ram_2p' [/home/mbaykenar/ibex_mba/ibex/build/lowrisc_ibex_top_artya7_0.1/src/lowrisc_prim_abstract_ram_2p_0/prim_ram_2p.sv:14]\r\n Parameter Width bound to: 32'sb00000000000000000000000000100000\r\n Parameter Depth bound to: 32'sb00000000000000000100000000000000\r\n Parameter DataBitsPerMask bound to: 32'sb00000000000000000000000000000001\r\n Parameter MemInitFile bound to: ../../../../../examples/sw/led/led.vmem - type: string\r\n Parameter Aw bound to: 32'sb00000000000000000000000000001110\r\nINFO: [Synth 8-6157] synthesizing module 'prim_generic_ram_2p' [/home/mbaykenar/ibex_mba/ibex/build/lowrisc_ibex_top_artya7_0.1/src/lowrisc_prim_generic_ram_2p_0/rtl/prim_generic_ram_2p.sv:9]\r\n Parameter Width bound to: 32'sb00000000000000000000000000100000\r\n Parameter Depth bound to: 32'sb00000000000000000100000000000000\r\n Parameter DataBitsPerMask bound to: 32'sb00000000000000000000000000000001\r\n Parameter MemInitFile bound to: ../../../../../examples/sw/led/led.vmem - type: string\r\n Parameter Aw bound to: 32'sb00000000000000000000000000001110\r\n Parameter MaskWidth bound to: 32'sb00000000000000000000000000100000\r\n\r\n\r\nI see that the parameters on prim_generic_ram_2p.sv are elaborated correctly:\r\n\r\n2 KB (32-bit * 512 = 2 KB)\r\n Parameter Width bound to: 32'sb00000000000000000000000000100000\r\n Parameter Depth bound to: 32'sb00000000000000000000001000000000\r\n64 KB (32-bit * 16384 = 64 KB)\r\n Parameter Width bound to: 32'sb00000000000000000000000000100000\r\n Parameter Depth bound to: 32'sb00000000000000000100000000000000\r\n\r\nI also checked detailed module level utilization and found out that all the BRAM instances are utilized for ram_2p. The register file utilizes LUT RAMs.\r\n\r\nDo I miss a detail on synthesizing for 2 KB RAM or what can cause inferring same amount of BRAM for 64 KB and 2 KB ?\r\n\r\nRegards,\r\n\r\n## My Environment\r\n\r\n**EDA tool and version:**\r\nVIVADO 2020.2\r\n\r\n**Operating system:**\r\nUBUNTU 20.04\r\n\r\n**Version of the Ibex source code:**\r\n6bb67e20f8a7c670e4baf5fe8f130a5ef360f411\r\n", "commit_message": "[ram_2p] Set DataBitsPerMask parameter for prim_ram_2p\n\nIt turned out that with the default value of 1, Vivado infers a separate\n18 Kbit BRAM instance for each bit of the 32-bit word for the FPGA\nexamples. This can be very wasteful in terms of resource utilization\nespecially for smaller configurations.\n\nAs our examples don't use ECC or parity and mainly target simualation\nand FPGA, it's better to use a value of 8 for the DataBitsPerMask\nparameter. Vivado will then not distribute words across different BRAM\ninstances which results in more efficient FPGA resource utilization.\n\nFor a detailed analysis and explanation, please refer to\nlowRISC/Ibex#1587.\n\nSigned-off-by: Pirmin Vogel ", "fix_patch": "diff --git a/shared/rtl/ram_2p.sv b/shared/rtl/ram_2p.sv\nindex e4cf238cad..52ff15598e 100644\n--- a/shared/rtl/ram_2p.sv\n+++ b/shared/rtl/ram_2p.sv\n@@ -68,6 +68,7 @@ module ram_2p #(\n prim_ram_2p #(\n .Width(32),\n .Depth(Depth),\n+ .DataBitsPerMask(8),\n .MemInitFile(MemInitFile)\n ) u_ram (\n .clk_a_i (clk_i),\n", "test_patch": "", "modified_files": ["shared/rtl/ram_2p.sv"], "lines_added": 1, "lines_removed": 0} +{"repo": "lowRISC/ibex", "pr_id": 1554, "lang": "sv", "rtl_files": ["examples/fpga/artya7/rtl/top_artya7.sv"], "commit_id": "e6eb4fb11d8e1626e01ca76052352696f476586e", "timestamp": "2022-03-15T15:37:03+00:00", "pr_title": "Fix port list in top_artya7 example", "pr_body": "The \"alert_major\" port was split into \"internal\" and \"bus\" parts back\r\nin commit 9943f9a. Update the example to match.\r\n\r\nFixes #1553.", "issue_title": "alert_major_o output port must be removed from ibex_top.sv module in top_artya7.sv ", "issue_body": "\r\n\r\n## Observed Behavior\r\n\r\n\r\n## Expected Behavior\r\n\r\n\r\n## Steps to reproduce the issue\r\n\r\n\r\n## My Environment\r\n\r\n\r\n\r\n**EDA tool and version:**\r\n\r\n\r\n**Operating system:**\r\n\r\n\r\n**Version of the Ibex source code:**\r\n\r\nalert_major_o output port of ibex_top.sv module has to be removed as Vivado throws error when synthesizing top_artya7.sv module. This port is not defined in ibex_top.sv module used in FPGA example", "commit_message": "Fix port list in top_artya7 example\n\nThe \"alert_major\" port was split into \"internal\" and \"bus\" parts back\nin commit 9943f9a. Update the example to match.", "fix_patch": "diff --git a/examples/fpga/artya7/rtl/top_artya7.sv b/examples/fpga/artya7/rtl/top_artya7.sv\nindex b15ee978d3..d6000a2067 100644\n--- a/examples/fpga/artya7/rtl/top_artya7.sv\n+++ b/examples/fpga/artya7/rtl/top_artya7.sv\n@@ -82,7 +82,8 @@ module top_artya7 (\n \n .fetch_enable_i ('b1),\n .alert_minor_o (),\n- .alert_major_o (),\n+ .alert_major_internal_o(),\n+ .alert_major_bus_o (),\n .core_sleep_o ()\n );\n \n", "test_patch": "", "modified_files": ["examples/fpga/artya7/rtl/top_artya7.sv"], "lines_added": 2, "lines_removed": 1} +{"repo": "lowRISC/ibex", "pr_id": 1547, "lang": "sv", "rtl_files": ["rtl/ibex_if_stage.sv"], "commit_id": "bdf2f2b44076c8e9a00fa6dcbee0a409026e5c3a", "timestamp": "2022-03-03T13:48:10+00:00", "pr_title": "[icache] Define some fake DPI functions to simplify linking", "pr_body": "This is triggered by the fact that if the `ICache` parameter is false\r\nthen we don't instantiate the `ibex_icache` module. For verilator\r\nsimulations, the module is then discarded entirely, which means that\r\nits two DPI functions are not defined. That's unfortunate because\r\nwe're also compiling the code in `scrambled_ecc32_mem_area.cc`, which\r\nexpects the functions to be defined.\r\n\r\nThe obvious solution (don't include `scrambled_ecc32_mem_area.cc` if you\r\ndon't have an icache) isn't easy to do, because FuseSoc doesn't\r\ncurrently allow us to use parameters to configure its dependency\r\ntree (see [fusesoc issue 438](https://github.com/olofk/fusesoc/issues/438) for a discussion).\r\n\r\nThe super-clever solution that I came up with before(!) was to declare\r\nthese symbols as weak in the C++ code. That way, we can do a runtime\r\ncheck to make sure that no-one is silly enough to call them without an\r\nicache, but everything will still build properly either way.\r\n\r\nUnfortunately, that doesn't work well with xcelium simulations.\r\nXcelium turns out to compile all the C++ code into one .so library and\r\ngenerate functions for exported DPI functions in another. These two\r\nsolibs then get loaded at runtime with `dlopen()`. But this doesn't work\r\nwith weak symbols: in fact, it seems you end up with the C++ version\r\nevery time. Boo!\r\n\r\nSo let's be stupider about it and define (bogus) versions of the DPI\r\nfunctions in this case. Fortunately, both of them are designed to\r\nreturn zero on failure so we can just return zero and needn't worry\r\ntoo much.\r\n\r\nThe idea is that when this lands, we can revert the [OpenTitan change](https://github.com/lowRISC/opentitan/pull/9304)\r\nthat switched the C++ code to using weak symbols and Xcelium\r\nsimulations will start working.", "issue_title": "Modify/Extend Simple System to be a more generic base ", "issue_body": "This PR https://github.com/lowRISC/ibex/pull/311 introduces Simple System. It allows you to build programs and easily run them on a basic Ibex system.\r\n\r\nIt shares many commonalities with the riscv-compliance system and the FPGA example. It should be possible to refactor these things so they are all working off the same base.\r\n\r\nIn addition it would be useful to add debugging support into Simple System to demonstrate how to setup a working debug environment. Though this may draw us away from it being a simple system so perhaps it would be a new example derived from Simple System.", "commit_message": "[icache] Define some fake DPI functions to simplify linking\n\nThis is triggered by the fact that if the ICache parameter is false\nthen we don't instantiate the ibex_icache module. For verilator\nsimulations, the module is then discarded entirely, which means that\nits two DPI functions are not defined. That's unfortunate because\nwe're also compiling the code in scrambled_ecc32_mem_area.cc, which\nexpects the functions to be defined.\n\nThe obvious solution (don't include scrambled_ecc32_mem_area.cc if you\ndon't have an icache) isn't easy to do, because FuseSoc doesn't\ncurrently allow us to use parameters to configure its dependency\ntree (see fusesoc issue 438 for a discussion).\n\nThe super-clever solution that I came up with before(!) was to declare\nthese symbols as weak in the C++ code. That way, we can do a runtime\ncheck to make sure that no-one is silly enough to call them without an\nicache, but everything will still build properly either way.\n\nUnfortunately, that doesn't work well with xcelium simulations.\nXcelium turns out to compile all the C++ code into one .so library and\ngenerate functions for exported DPI functions in another. These two\nsolibs then get loaded at runtime with dlopen(). But this doesn't work\nwith weak symbols: in fact, it seems you end up with the C++ version\nevery time. Boo!\n\nSo let's be stupider about it and define (bogus) versions of the DPI\nfunctions in this case. Fortunately, both of them are designed to\nreturn zero on failure so we can just return zero and needn't worry\ntoo much.\n\nThe idea is that when this lands, we can revert the OpenTitan change\nthat switched the C++ code to using weak symbols and Xcelium\nsimulations will start working.", "fix_patch": "diff --git a/rtl/ibex_if_stage.sv b/rtl/ibex_if_stage.sv\nindex aa63257872..2697833e41 100644\n--- a/rtl/ibex_if_stage.sv\n+++ b/rtl/ibex_if_stage.sv\n@@ -301,6 +301,23 @@ module ibex_if_stage import ibex_pkg::*; #(\n assign ic_data_write_o = 'b0;\n assign ic_data_addr_o = 'b0;\n assign ic_data_wdata_o = 'b0;\n+\n+`ifndef SYNTHESIS\n+ // If we don't instantiate an icache and this is a simulation then we have a problem because the\n+ // simulator might discard the icache module entirely, including some DPI exports that it\n+ // implies. This then causes problems for linking against C++ testbench code that expected them.\n+ // As a slightly ugly hack, let's define the DPI functions here (the real versions are defined\n+ // in prim_util_get_scramble_params.svh)\n+ export \"DPI-C\" function simutil_get_scramble_key;\n+ export \"DPI-C\" function simutil_get_scramble_nonce;\n+ function automatic int simutil_get_scramble_key(output bit [127:0] val);\n+ return 0;\n+ endfunction\n+ function automatic int simutil_get_scramble_nonce(output bit [319:0] nonce);\n+ return 0;\n+ endfunction\n+`endif\n+\n end\n \n assign unused_fetch_addr_n0 = fetch_addr_n[0];\n", "test_patch": "", "modified_files": ["rtl/ibex_if_stage.sv"], "lines_added": 17, "lines_removed": 0} +{"repo": "lowRISC/ibex", "pr_id": 1488, "lang": "sv", "rtl_files": ["rtl/ibex_register_file_fpga.sv"], "commit_id": "fa3df3b8ee1f6c7fc71f2d429f16b0015413f075", "timestamp": "2021-12-09T15:35:31+00:00", "pr_title": "[rtl] Replace always_ff with always @(posedge .. in FPGA regfile", "pr_body": "This resolves lowRISC/Ibex#1485.\r\n\r\nNote: I've tested that these changes don't impact the Vivado's capability to infer LUTRAM for the FPGA regfile.", "issue_title": "Wrong SV code - compilation error occurs", "issue_body": "\r\n\r\n## Observed Behavior\r\n\r\nAfter https://github.com/lowRISC/ibex/commit/169785d0711335c94561a93146e069766eec138c commit the \"ibex_simple_system\" and UVM tests cannot be compiled because of the error:\r\n\r\n`ALOG: Error: VCP2675 /ibex/build/lowrisc_ibex_ibex_simple_system_0/src/lowrisc_ibex_ibex_top_0.1/rtl/ibex_register_file_fpga.sv : (63, 1): Cannot write to a variable 'mem[k]' that is also driven by an always_comb/always_latch/always_ff procedural block. `\r\n\r\n\r\nThe problem is caused by wrong SV code:\r\nhttps://github.com/lowRISC/ibex/blob/c78acac8cc381293900f3648e365ddd136784789/rtl/ibex_register_file_fpga.sv#L54-L65\r\n\r\nIn this case the mem[] variable is written in always_ff and initial block what is prohibited by SV LRM:\r\n\r\n> \"The always_ff procedure imposes the restriction that it contains one and only one event control and no\r\n> blocking timing controls. Variables on the left-hand side of assignments within an always_ff procedure,\r\n> including variables from the contents of a called function, shall not be written to by any other process.\"\r\n\r\n## Expected Behavior\r\n\r\n\r\nThe code should compile without errors.\r\n\r\n## Steps to reproduce the issue\r\n\r\n\r\n## My Environment\r\n\r\n\r\n\r\n**EDA tool and version:**\r\n\r\nAldec Riviera-PRO\r\n\r\n**Operating system:**\r\n\r\nLinux, Ubuntu 20.04\r\n\r\n**Version of the Ibex source code:**\r\n\r\n", "commit_message": "[rtl] Replace always_ff with always @(posedge .. in FPGA regfile\n\nThis resolves lowRISC/Ibex#1485.\n\nSigned-off-by: Pirmin Vogel ", "fix_patch": "diff --git a/rtl/ibex_register_file_fpga.sv b/rtl/ibex_register_file_fpga.sv\nindex 3a5d425afe..678549aba6 100644\n--- a/rtl/ibex_register_file_fpga.sv\n+++ b/rtl/ibex_register_file_fpga.sv\n@@ -51,7 +51,12 @@ module ibex_register_file_fpga #(\n // we select\n assign we = (waddr_a_i == '0) ? 1'b0 : we_a_i;\n \n- always_ff @(posedge clk_i) begin : sync_write\n+ // Note that the SystemVerilog LRM requires variables on the LHS of assignments within\n+ // \"always_ff\" to not be written to by any other process. However, to enable the initialization\n+ // of the inferred RAM32M primitives with non-zero values, below \"initial\" procedure is needed.\n+ // Therefore, we use \"always\" instead of the generally preferred \"always_ff\" for the synchronous\n+ // write procedure.\n+ always @(posedge clk_i) begin : sync_write\n if (we == 1'b1) begin\n mem[waddr_a_i] <= wdata_a_i;\n end\n", "test_patch": "", "modified_files": ["rtl/ibex_register_file_fpga.sv"], "lines_added": 6, "lines_removed": 1} +{"repo": "lowRISC/ibex", "pr_id": 1446, "lang": "sv", "rtl_files": ["rtl/ibex_top_tracing.sv"], "commit_id": "45f727dfc6e59119347aca62e38e69175f680bf6", "timestamp": "2021-09-27T10:06:04+00:00", "pr_title": "Add missing parameters to ibex_top_tracing", "pr_body": "Fixes #1444", "issue_title": "Building dependency in Fusesoc step fails on Ubuntu 20.04", "issue_body": "\r\n\r\n\r\n\r\nHii, I am trying to run the ibex core on my Ubuntu 20.04 system as suggested in https://github.com/lowRISC/ibex/tree/master/examples/simple_system. \r\n\r\nThe dependencies are correctly installed, but the fusesoc building simulation step fails inspite of that:\r\nfusesoc --cores-root=. run --target=sim --setup --build lowrisc:ibex:ibex_simple_system --RV32E=0 --RV32M=ibex_pkg::RV32MFast\r\n\r\nThe error is as follows:\r\n\r\nINFO: Running pre_build script check_tool_requirements\r\nINFO: Tool verilator present: Sufficiently recent version (found 4.213; needed 4.028)\r\nINFO: Tool edalize present: Sufficiently recent version (found 0.2.2; needed 0.2.0)\r\nINFO: Building simulation model\r\nverilator -f lowrisc_ibex_ibex_simple_system_0.vc --trace --trace-fst --trace-structs --trace-params --trace-max-array 1024 -CFLAGS \"-std=c++11 -Wall -DVM_TRACE_FMT_FST -DTOPLEVEL_NAME=ibex_simple_system -g\" -LDFLAGS \"-pthread -lutil -lelf\" -Wall -Wwarn-IMPERFECTSCH --unroll-count 72\r\n%Warning-UNUSED: ../src/lowrisc_ibex_ibex_top_tracing_0.1/rtl/ibex_top_tracing.sv:27:26: Parameter is not used: 'RndCnstLfsrSeed'\r\n : ... In instance ibex_simple_system.u_top\r\n 27 | parameter lfsr_seed_t RndCnstLfsrSeed = RndCnstLfsrSeedDefault,\r\n | ^~~~~~~~~~~~~~~\r\n ... For warning description see https://verilator.org/warn/UNUSED?v=4.213\r\n ... Use \"/* verilator lint_off UNUSED */\" and lint_on around source to disable this message.\r\n%Warning-UNUSED: ../src/lowrisc_ibex_ibex_top_tracing_0.1/rtl/ibex_top_tracing.sv:28:26: Parameter is not used: 'RndCnstLfsrPerm'\r\n : ... In instance ibex_simple_system.u_top\r\n 28 | parameter lfsr_perm_t RndCnstLfsrPerm = RndCnstLfsrPermDefault,\r\n | ^~~~~~~~~~~~~~~\r\n%Error: Exiting due to 2 warning(s)\r\nMakefile:16: recipe for target 'Vibex_simple_system.mk' failed\r\nmake: *** [Vibex_simple_system.mk] Error 1\r\nERROR: Failed to build lowrisc:ibex:ibex_simple_system:0 : 'make' exited with an error code\r\n\r\n\r\nI am new to ibex, can anyone be kind to help me with the resolution of the error. \r\nThanks in advance.\r\n\r\n\r\n\r\n\r\n\r\n## My Environment\r\n\r\n\r\n\r\n**EDA tool and version:**\r\n\r\n\r\n**Operating system:**\r\n\r\n\r\n**Version of the Ibex source code:**\r\n\r\n", "commit_message": "Add missing parameters to ibex_top_tracing", "fix_patch": "diff --git a/rtl/ibex_top_tracing.sv b/rtl/ibex_top_tracing.sv\nindex 02aa9db15e..7bbc6fd722 100644\n--- a/rtl/ibex_top_tracing.sv\n+++ b/rtl/ibex_top_tracing.sv\n@@ -129,6 +129,8 @@ module ibex_top_tracing import ibex_pkg::*; #(\n .DbgHwBreakNum ( DbgHwBreakNum ),\n .WritebackStage ( WritebackStage ),\n .SecureIbex ( SecureIbex ),\n+ .RndCnstLfsrSeed ( RndCnstLfsrSeed ),\n+ .RndCnstLfsrPerm ( RndCnstLfsrPerm ),\n .DmHaltAddr ( DmHaltAddr ),\n .DmExceptionAddr ( DmExceptionAddr )\n ) u_ibex_top (\n", "test_patch": "", "modified_files": ["rtl/ibex_top_tracing.sv"], "lines_added": 2, "lines_removed": 0} +{"repo": "lowRISC/ibex", "pr_id": 1443, "lang": "sv", "rtl_files": ["rtl/ibex_tracer.sv"], "commit_id": "45f727dfc6e59119347aca62e38e69175f680bf6", "timestamp": "2021-10-01T16:51:18+00:00", "pr_title": "Remove unused RD in branch insn from tracer", "pr_body": "There is an unnecessary use of RD in branch instruction in `ibex_tracer.sv` which is removed. This PR resolves this issue #1441.\r\nhttps://github.com/lowRISC/ibex/blob/ac8934459b028220ce9fd20683bb018244b59756/rtl/ibex_tracer.sv#L493", "issue_title": "Use of RD in B type.", "issue_body": "https://github.com/lowRISC/ibex/blob/ac8934459b028220ce9fd20683bb018244b59756/rtl/ibex_tracer.sv#L493\r\n\r\nI am wondering why there is a use of RD in B-type instructions? Is this an issue or I am missing something.", "commit_message": "remove unused RD in branch insn from tracer", "fix_patch": "diff --git a/rtl/ibex_tracer.sv b/rtl/ibex_tracer.sv\nindex bbee71b662..be523686cb 100644\n--- a/rtl/ibex_tracer.sv\n+++ b/rtl/ibex_tracer.sv\n@@ -490,7 +490,7 @@ module ibex_tracer (\n rvfi_insn[30:25], rvfi_insn[11:8], 1'b0 });\n branch_target = rvfi_pc_rdata + imm;\n \n- data_accessed = RS1 | RS2 | RD;\n+ data_accessed = RS1 | RS2;\n decoded_str = $sformatf(\"%s\\tx%0d,x%0d,%0x\",\n mnemonic, rvfi_rs1_addr, rvfi_rs2_addr, branch_target);\n endfunction\n", "test_patch": "", "modified_files": ["rtl/ibex_tracer.sv"], "lines_added": 1, "lines_removed": 1} +{"repo": "lowRISC/ibex", "pr_id": 1380, "lang": "sv", "rtl_files": ["rtl/ibex_cs_registers.sv"], "commit_id": "7ceff60749bc5907bd720d554ce2fa6fe997d34d", "timestamp": "2021-06-09T13:59:33+00:00", "pr_title": "[rtl] Fix typo in MCOUNTEREN", "pr_body": "DbgTriggerEn has no impact on whether this is an illegal csr op.\r\n\r\nFixes #1379\r\n\r\nSigned-off-by: Tom Roberts ", "issue_title": "DbgTriggerEn impacts mcounteren", "issue_body": "Why does DbgTriggerEn impact mcounteren? That does not look correct to me.\r\n\r\n> // mcounteren: machine counter enable\r\n> CSR_MCOUNTEREN: begin\r\n> csr_rdata_int = '0;\r\n> illegal_csr = ~DbgTriggerEn;\r\n> end\r\n", "commit_message": "[rtl] Fix typo in MCOUNTEREN\n\nDbgTriggerEn has no impact on whether this is an illegal csr op.\n\nFixes #1379\n\nSigned-off-by: Tom Roberts ", "fix_patch": "diff --git a/rtl/ibex_cs_registers.sv b/rtl/ibex_cs_registers.sv\nindex 50a34a2176..75ef2e5de1 100644\n--- a/rtl/ibex_cs_registers.sv\n+++ b/rtl/ibex_cs_registers.sv\n@@ -322,7 +322,6 @@ module ibex_cs_registers #(\n // mcounteren: machine counter enable\n CSR_MCOUNTEREN: begin\n csr_rdata_int = '0;\n- illegal_csr = ~DbgTriggerEn;\n end\n \n CSR_MSCRATCH: csr_rdata_int = mscratch_q;\n", "test_patch": "", "modified_files": ["rtl/ibex_cs_registers.sv"], "lines_added": 0, "lines_removed": 1} +{"repo": "lowRISC/ibex", "pr_id": 1326, "lang": "sv", "rtl_files": ["rtl/ibex_compressed_decoder.sv"], "commit_id": "8d37af2751a25cffd50d09d91845cf2c111f39b3", "timestamp": "2021-04-06T16:22:56+00:00", "pr_title": "[rtl] Add SVA to ensure valid_i in compressed decoder is known", "pr_body": "This signal is used to gate several assertions related to unknown/invalid selector signals. We want to be sure to catch any X\r\nvalues entering the compressed decoder and ultimately ID.\r\n\r\nThis is related to lowRISC/Ibex#540.", "issue_title": "Check how X values end up in C decoder", "issue_body": "Currently, X values can end up in the C decoder when the IF stage does not have a valid instruction. This requires the assertions in the C decoder to be qualified with `instr_valid` (see #536).\r\n\r\nWe allow X values for uninitialized memories and the DV environment can drive them on the external bus. It seems that the X can come from both the uninitialized flops in the prefetch buffer (`ibex_fetch_fifo.sv`) or the bus signal directly, or a combination of the two (depending on the requested address, and FIFO fill status).\r\n\r\nWe need to understand where exactly these X come from in this particular case.\r\n\r\n", "commit_message": "[rtl] Add SVA to ensure valid_i in compressed decoder is known\n\nThis signal is used to gate several assertions related to\nunknown/invalid selector signals. We want to be sure to catch any X\nvalues entering the compressed decoder and ultimately ID.\n\nThis is related to lowRISC/Ibex#540.\n\nSigned-off-by: Pirmin Vogel ", "fix_patch": "diff --git a/rtl/ibex_compressed_decoder.sv b/rtl/ibex_compressed_decoder.sv\nindex 12a487fe1d..ec694f51cb 100644\n--- a/rtl/ibex_compressed_decoder.sv\n+++ b/rtl/ibex_compressed_decoder.sv\n@@ -282,6 +282,9 @@ module ibex_compressed_decoder (\n // Assertions //\n ////////////////\n \n+ // The valid_i signal used to gate below assertions must be known.\n+ `ASSERT_KNOWN(IbexInstrValidKnown, valid_i)\n+\n // Selectors must be known/valid.\n `ASSERT(IbexInstrLSBsKnown, valid_i |->\n !$isunknown(instr_i[1:0]))\n", "test_patch": "", "modified_files": ["rtl/ibex_compressed_decoder.sv"], "lines_added": 3, "lines_removed": 0} +{"repo": "lowRISC/ibex", "pr_id": 1300, "lang": "sv", "rtl_files": ["rtl/ibex_icache.sv"], "commit_id": "6d9e1aca8ad7cf09d4effcde97e471d6c213ead1", "timestamp": "2021-03-12T17:27:52+00:00", "pr_title": "[rtl/icache] Switch ECC granularity to 32bits", "pr_body": "Changes the ECC granularity in the data RAMs from 64bit to 32bit. This\r\nis to align with an upcoming change in bus ECC. Relates to\r\nlowRISC/opentitan#5450\r\n\r\nSigned-off-by: Tom Roberts ", "issue_title": "", "issue_body": "", "commit_message": "[rtl/icache] Switch ECC granularity to 32bits\n\nChanges the ECC granularity in the data RAMs from 64bit to 32bit. This\nis to align with an upcoming change in bus ECC. Relates to\nlowRISC/opentitan#5450\n\nSigned-off-by: Tom Roberts ", "fix_patch": "diff --git a/rtl/ibex_icache.sv b/rtl/ibex_icache.sv\nindex 346e6a28f4..504d005329 100644\n--- a/rtl/ibex_icache.sv\n+++ b/rtl/ibex_icache.sv\n@@ -64,14 +64,15 @@ module ibex_icache #(\n // Request throttling threshold\n localparam int unsigned FB_THRESHOLD = NUM_FB - 2;\n // Derived parameters\n- localparam int unsigned LINE_SIZE_ECC = ICacheECC ? (LineSize + 8) : LineSize;\n localparam int unsigned LINE_SIZE_BYTES = LineSize/8;\n localparam int unsigned LINE_W = $clog2(LINE_SIZE_BYTES);\n+ localparam int unsigned BUS_SIZE_ECC = ICacheECC ? (BusWidth + 7) : BusWidth;\n localparam int unsigned BUS_BYTES = BusWidth/8;\n localparam int unsigned BUS_W = $clog2(BUS_BYTES);\n localparam int unsigned LINE_BEATS = LINE_SIZE_BYTES / BUS_BYTES;\n localparam int unsigned LINE_BEATS_W = $clog2(LINE_BEATS);\n localparam int unsigned NUM_LINES = CacheSizeBytes / NumWays / LINE_SIZE_BYTES;\n+ localparam int unsigned LINE_SIZE_ECC = BUS_SIZE_ECC * LINE_BEATS;\n localparam int unsigned INDEX_W = $clog2(NUM_LINES);\n localparam int unsigned INDEX_HI = INDEX_W + LINE_W - 1;\n localparam int unsigned TAG_SIZE = ADDR_W - INDEX_W - LINE_W + 1; // 1 valid bit\n@@ -110,7 +111,8 @@ module ibex_icache #(\n // Cache pipelipe IC1 signals\n logic [TAG_SIZE_ECC-1:0] tag_rdata_ic1 [NumWays];\n logic [LINE_SIZE_ECC-1:0] data_rdata_ic1 [NumWays];\n- logic [LINE_SIZE_ECC-1:0] hit_data_ic1;\n+ logic [LINE_SIZE_ECC-1:0] hit_data_ecc_ic1;\n+ logic [LineSize-1:0] hit_data_ic1;\n logic lookup_valid_ic1;\n logic [ADDR_W-1:INDEX_HI+1] lookup_addr_ic1;\n logic [NumWays-1:0] tag_match_ic1;\n@@ -315,10 +317,12 @@ module ibex_icache #(\n assign tag_wdata_ic0 = {tag_ecc_output_padded[27:22],tag_ecc_output_padded[TAG_SIZE-1:0]};\n \n // Dataram ECC\n- prim_secded_72_64_enc data_ecc_enc (\n- .in (fill_wdata_ic0),\n- .out (data_wdata_ic0)\n- );\n+ for (genvar bank = 0; bank < LINE_BEATS; bank ++) begin : gen_ecc_banks\n+ prim_secded_39_32_enc data_ecc_enc (\n+ .in (fill_wdata_ic0[bank*BusWidth+:BusWidth]),\n+ .out (data_wdata_ic0[bank*BUS_SIZE_ECC+:BUS_SIZE_ECC])\n+ );\n+ end\n \n end else begin : gen_noecc_wdata\n assign tag_wdata_ic0 = fill_tag_ic0;\n@@ -390,10 +394,10 @@ module ibex_icache #(\n \n // Hit data mux\n always_comb begin\n- hit_data_ic1 = 'b0;\n+ hit_data_ecc_ic1 = 'b0;\n for (int way = 0; way < NumWays; way++) begin\n if (tag_match_ic1[way]) begin\n- hit_data_ic1 |= data_rdata_ic1[way];\n+ hit_data_ecc_ic1 |= data_rdata_ic1[way];\n end\n end\n end\n@@ -421,11 +425,11 @@ module ibex_icache #(\n \n // ECC checking logic\n if (ICacheECC) begin : gen_data_ecc_checking\n- logic [NumWays-1:0] tag_err_ic1;\n- logic [1:0] data_err_ic1;\n- logic ecc_correction_write_d, ecc_correction_write_q;\n- logic [NumWays-1:0] ecc_correction_ways_d, ecc_correction_ways_q;\n- logic [INDEX_W-1:0] lookup_index_ic1, ecc_correction_index_q;\n+ logic [NumWays-1:0] tag_err_ic1;\n+ logic [LINE_BEATS*2-1:0] data_err_ic1;\n+ logic ecc_correction_write_d, ecc_correction_write_q;\n+ logic [NumWays-1:0] ecc_correction_ways_d, ecc_correction_ways_q;\n+ logic [INDEX_W-1:0] lookup_index_ic1, ecc_correction_index_q;\n \n // Tag ECC checking\n for (genvar way = 0; way < NumWays; way++) begin : gen_tag_ecc\n@@ -448,12 +452,17 @@ module ibex_icache #(\n \n // Data ECC checking\n // Note - could generate for all ways and mux after\n- prim_secded_72_64_dec data_ecc_dec (\n- .in (hit_data_ic1),\n- .d_o (),\n- .syndrome_o (),\n- .err_o (data_err_ic1)\n- );\n+ for (genvar bank = 0; bank < LINE_BEATS; bank++) begin : gen_ecc_banks\n+ prim_secded_39_32_dec data_ecc_dec (\n+ .in (hit_data_ecc_ic1[bank*BUS_SIZE_ECC+:BUS_SIZE_ECC]),\n+ .d_o (),\n+ .syndrome_o (),\n+ .err_o (data_err_ic1[bank*2+:2])\n+ );\n+\n+ assign hit_data_ic1[bank*BusWidth+:BusWidth] = hit_data_ecc_ic1[bank*BUS_SIZE_ECC+:BusWidth];\n+\n+ end\n \n assign ecc_err_ic1 = lookup_valid_ic1 & ((|data_err_ic1) | (|tag_err_ic1));\n \n@@ -497,6 +506,7 @@ module ibex_icache #(\n assign ecc_write_req = 1'b0;\n assign ecc_write_ways = '0;\n assign ecc_write_index = '0;\n+ assign hit_data_ic1 = hit_data_ecc_ic1;\n end\n \n ///////////////////////////////\n@@ -782,7 +792,7 @@ module ibex_icache #(\n \n // Data either comes from the cache or the bus. If there was an ECC error, we must take\n // the incoming bus data since the cache hit data is corrupted.\n- assign fill_data_d[fb] = fill_hit_ic1[fb] ? hit_data_ic1[LineSize-1:0] :\n+ assign fill_data_d[fb] = fill_hit_ic1[fb] ? hit_data_ic1 :\n {LINE_BEATS{instr_rdata_i}};\n \n for (genvar b = 0; b < LINE_BEATS; b++) begin : gen_data_buf\n@@ -881,7 +891,7 @@ module ibex_icache #(\n ////////////////////////\n \n // Mux between line-width data sources\n- assign line_data = |fill_data_hit ? hit_data_ic1[LineSize-1:0] : fill_out_data;\n+ assign line_data = |fill_data_hit ? hit_data_ic1 : fill_out_data;\n assign line_err = |fill_data_hit ? {LINE_BEATS{1'b0}} : fill_out_err;\n \n // Mux the relevant beat of line data, based on the output address\n@@ -1059,7 +1069,7 @@ module ibex_icache #(\n \n // ECC primitives will need to be changed for different sizes\n `ASSERT_INIT(ecc_tag_param_legal, (TAG_SIZE <= 27))\n- `ASSERT_INIT(ecc_data_param_legal, (LineSize <= 121))\n+ `ASSERT_INIT(ecc_data_param_legal, !ICacheECC || (BusWidth == 32))\n \n // Lookups in the tag ram should always give a known result\n `ASSERT_KNOWN(TagHitKnown, lookup_valid_ic1 & tag_hit_ic1)\n", "test_patch": "", "modified_files": ["rtl/ibex_icache.sv"], "lines_added": 32, "lines_removed": 22} +{"repo": "lowRISC/ibex", "pr_id": 1216, "lang": "sv", "rtl_files": ["rtl/ibex_controller.sv"], "commit_id": "aa7582b8d420888541c2e8688447c17918a71aeb", "timestamp": "2020-12-17T11:25:04+00:00", "pr_title": "This is modification request for xcelium", "pr_body": "Assert not correctly understood by some versions of xcelium.\r\nA single character added line in rtl/ibex_controller.sv .", "issue_title": "'Assert' line 836 of file ibex_controller.sv not understood by some version of Xcelium", "issue_body": "Current code:\r\n`ASSERT(AlwaysInstrClearOnMispredict, nt_branch_mispredict_o -> instr_valid_clear_o)\r\n\r\nSuggested code (a 'pipe'='|' added):\r\n`ASSERT(AlwaysInstrClearOnMispredict, nt_branch_mispredict_o |-> instr_valid_clear_o)\r\n\r\nCurrent code fails with Xcellium 19.03-s001 for example. But works with a more recent version (20.10...)\r\n", "commit_message": "Use overlapping implications for Xcelium 19.03\n\nXcelium 19.03 doesn't support the `->` (binary logical) operator, but\nusing `|->` (overlapping implication) is equivalent here and supported;\nuse this operator instead.\n\nFixes #1213", "fix_patch": "diff --git a/rtl/ibex_controller.sv b/rtl/ibex_controller.sv\nindex b59833d5b6..db98a0ae48 100644\n--- a/rtl/ibex_controller.sv\n+++ b/rtl/ibex_controller.sv\n@@ -833,7 +833,7 @@ module ibex_controller #(\n // Assertions //\n ////////////////\n \n- `ASSERT(AlwaysInstrClearOnMispredict, nt_branch_mispredict_o -> instr_valid_clear_o)\n+ `ASSERT(AlwaysInstrClearOnMispredict, nt_branch_mispredict_o |-> instr_valid_clear_o)\n \n // Selectors must be known/valid.\n `ASSERT(IbexCtrlStateValid, ctrl_fsm_cs inside {\n", "test_patch": "", "modified_files": ["rtl/ibex_controller.sv"], "lines_added": 1, "lines_removed": 1} +{"repo": "lowRISC/ibex", "pr_id": 1182, "lang": "sv", "rtl_files": ["rtl/ibex_cs_registers.sv"], "commit_id": "9b0d78cf97fd4bd22db8b2479f30ed135f761a13", "timestamp": "2020-11-09T14:49:07+00:00", "pr_title": "[rtl] Reduce size of PMP addr CSRs to minimum", "pr_body": "- Reduce the size of the PMP address configuration registers to the permissible minimum depending on granularity.\r\n- Ensure consistency between PMP address CSR reads and the addresses forwarded to the PMP module.\r\n- Follow the specification more strictly, by returning bits pmpaddr[G-2:0] as all ones when pmpcfg.A[1] is set (i.e. mode is NAPOT or NA4, though the latter is invalid for G > 0) and bits pmpaddr[G-1:0] as all zeros when pmpcfg.A[0] is clear (i.e. mode is OFF or TOR).\r\n- Fixes #1181", "issue_title": "PMP CSR enhancement / bug", "issue_body": "Looking PMP granularity as part of #1178 I noticed we always keep the PMP address CSRs as 32bits despite the granularity. At best this is inefficient as we're missing out on area savings, at worst it's a bug since we use the raw address in the matching logic (which doesn't match the modified version the user sees on a CSR read).", "commit_message": "[rtl] Reduce size of PMP addr CSRs to minimum\n\n- Reduce the size of the PMP address configuration registers to the\n permissible minimum depending on granularity.\n- Ensure consistency between PMP address CSR reads and the addresses\n forwarded to the PMP module.\n- Follow the specification more strictly, by returning bits\n pmpaddr[G-2:0] as all ones when pmpcfg.A[1] is set (i.e. mode is\n NAPOT or NA4, though the latter is invalid for G > 0) and bits\n pmpaddr[G-1:0] as all zeros when pmpcfg.A[0] is clear (i.e. mode is\n OFF or TOR).\n- Fixes #1181", "fix_patch": "diff --git a/rtl/ibex_cs_registers.sv b/rtl/ibex_cs_registers.sv\nindex 36d1f793e1..16a8acd3fc 100644\n--- a/rtl/ibex_cs_registers.sv\n+++ b/rtl/ibex_cs_registers.sv\n@@ -120,6 +120,7 @@ module ibex_cs_registers #(\n import ibex_pkg::*;\n \n localparam int unsigned RV32MEnabled = (RV32M == RV32MNone) ? 0 : 1;\n+ localparam int unsigned PMPAddrWidth = (PMPGranularity > 0) ? 33 - PMPGranularity : 32;\n \n // misa\n localparam logic [31:0] MISA_VALUE =\n@@ -954,7 +955,7 @@ module ibex_cs_registers #(\n if (PMPEnable) begin : g_pmp_registers\n pmp_cfg_t pmp_cfg [PMPNumRegions];\n pmp_cfg_t pmp_cfg_wdata [PMPNumRegions];\n- logic [31:0] pmp_addr [PMPNumRegions];\n+ logic [PMPAddrWidth-1:0] pmp_addr [PMPNumRegions];\n logic [PMPNumRegions-1:0] pmp_cfg_we;\n logic [PMPNumRegions-1:0] pmp_cfg_err;\n logic [PMPNumRegions-1:0] pmp_addr_we;\n@@ -985,13 +986,12 @@ module ibex_cs_registers #(\n end else begin : g_pmp_g2\n // For G >= 2, bits are masked to one or zero depending on the mode\n always_comb begin\n- pmp_addr_rdata[i] = pmp_addr[i];\n+ // In NAPOT mode, bits [G-2:0] must read as one\n+ pmp_addr_rdata[i] = {pmp_addr[i], {PMPGranularity-1{1'b1}}};\n+\n if ((pmp_cfg[i].mode == PMP_MODE_OFF) || (pmp_cfg[i].mode == PMP_MODE_TOR)) begin\n // In TOR or OFF mode, bits [G-1:0] must read as zero\n pmp_addr_rdata[i][PMPGranularity-1:0] = '0;\n- end else if (pmp_cfg[i].mode == PMP_MODE_NAPOT) begin\n- // In NAPOT mode, bits [G-2:0] must read as one\n- pmp_addr_rdata[i][PMPGranularity-2:0] = '1;\n end\n end\n end\n@@ -1055,20 +1055,20 @@ module ibex_cs_registers #(\n end\n \n ibex_csr #(\n- .Width (32),\n+ .Width (PMPAddrWidth),\n .ShadowCopy (ShadowCSR),\n .ResetValue ('0)\n ) u_pmp_addr_csr (\n .clk_i (clk_i),\n .rst_ni (rst_ni),\n- .wr_data_i (csr_wdata_int),\n+ .wr_data_i (csr_wdata_int[31-:PMPAddrWidth]),\n .wr_en_i (pmp_addr_we[i]),\n .rd_data_o (pmp_addr[i]),\n .rd_error_o (pmp_addr_err[i])\n );\n \n assign csr_pmp_cfg_o[i] = pmp_cfg[i];\n- assign csr_pmp_addr_o[i] = {pmp_addr[i],2'b00};\n+ assign csr_pmp_addr_o[i] = {pmp_addr_rdata[i], 2'b00};\n end\n \n assign pmp_csr_err = (|pmp_cfg_err) | (|pmp_addr_err);\n", "test_patch": "", "modified_files": ["rtl/ibex_cs_registers.sv"], "lines_added": 8, "lines_removed": 8} +{"repo": "lowRISC/ibex", "pr_id": 1179, "lang": "sv", "rtl_files": ["rtl/ibex_pmp.sv"], "commit_id": "1f3b462b9477531a9bf8627a05f92cadfd3c54bb", "timestamp": "2020-11-06T17:47:27+00:00", "pr_title": "[rtl] Fix NAPOT address matching (#1178)", "pr_body": "Generate correct masks for NAPOT range addresses covering the entire granule. When PMPGranularity > 0, then a NAPOT range can span the whole granule, which requires the next-lowest bit (i.e. highest bit that is not part of the granule) to be 0. Fixes #1178 ", "issue_title": "PMP NAPOT masks are incorrect when the region address spans the entire granule", "issue_body": "The address masking logic in [`ibex_pmp.sv`](https://github.com/lowRISC/ibex/blob/master/rtl/ibex_pmp.sv) always considers the lowest bit of the granule of the PMP address configuration register (i.e. `csr_pmp_addr_i[r][PMPGranularity+2]`) not to be part of the range address in NAPOT mode. This is correct when `PMPGranularity == 0`, since then NA4 mode must be selected if the range address uses all bits, but it is incorrect when `PMPGranularity > 0`, since then it is legal in NAPOT mode to have a range address span the entire granule, with the next-lowest bit (i.e. `csr_pmp_addr_i[r][PMPGranularity+1]`) cleared to indicate that all higher bits are part of the range address.\r\n\r\nFor instance with `PMPGranularity == 28`, the granule covers bits `csr_pmp_addr_i[r][33:30]`, yet bit `csr_pmp_addr_i[r][29]` must also be considered to check whether a range address spans all 4 bits of the granule. A range address of `csr_pmp_addr_i[r] == 34'b00_0101_1111_1111_1111_1111_1111_1111_1111` could be used to specify a range from 1 GiB to 2 GiB for example and in that case the region address mask should be `region_addr_mask [r] == 4'b1111` (i.e. the entire granule). However, since only bits `csr_pmp_addr_i[r][33:30]` are currently considered when generating the mask, it is incorrectly set to `region_addr_mask [r] == 4'b1100`.\r\n\r\nThe specification states that bits `G-2:0` (i.e. bits `csr_pmp_addr_i[r][PMPGranularity:0]`) are implicitly set to all ones and hence do not need to be considered, but that implies that bit `G-1` (i.e. `csr_pmp_addr_i[r][PMPGranularity+1]`) is still used to specify the range:\r\n\r\n> When G≥1, the NA4 mode is not selectable. When G≥2 and pmpcfgi.A[1] is set, i.e. the mode is NAPOT, then bits pmpaddri[G-2:0] read as all ones.\r\n> -- [Volume II: RISC-V Privileged Architectures V20190608-Priv-MSU-Ratified, Sect. 3.6.1](https://github.com/riscv/riscv-isa-manual/releases/download/Ratified-IMFDQC-and-Priv-v1.11/riscv-privileged-20190608.pdf)", "commit_message": "[rtl] Fix NAPOT address matching\n\n- Generate correct masks for NAPOT range addresses covering the entire\n granule. When PMPGranularity > 0, then a NAPOT range can span the\n whole granule, which requires the next-lowest bit (i.e. highest bit\n that is not part of the granule) to be 0.\n- Fixes #1178", "fix_patch": "diff --git a/rtl/ibex_pmp.sv b/rtl/ibex_pmp.sv\nindex 1b48693a0a..cbe2193310 100644\n--- a/rtl/ibex_pmp.sv\n+++ b/rtl/ibex_pmp.sv\n@@ -55,8 +55,8 @@ module ibex_pmp #(\n end\n // Address mask for NA matching\n for (genvar b = PMPGranularity+2; b < 34; b++) begin : g_bitmask\n- if (b == PMPGranularity+2) begin : g_bit0\n- // Always mask bit (G+2) for NAPOT\n+ if (b == 2) begin : g_bit0\n+ // Always mask bit 2 for NAPOT\n assign region_addr_mask[r][b] = (csr_pmp_cfg_i[r].mode != PMP_MODE_NAPOT);\n end else begin : g_others\n // We will mask this bit if it is within the programmed granule\n@@ -65,7 +65,7 @@ module ibex_pmp #(\n // | This bit pos is the top of the mask, all lower bits set\n // thus mask = 1111 0000\n assign region_addr_mask[r][b] = (csr_pmp_cfg_i[r].mode != PMP_MODE_NAPOT) |\n- ~&csr_pmp_addr_i[r][b-1:PMPGranularity+2];\n+ ~&csr_pmp_addr_i[r][b-1:PMPGranularity+1];\n end\n end\n end\n", "test_patch": "", "modified_files": ["rtl/ibex_pmp.sv"], "lines_added": 3, "lines_removed": 3} +{"repo": "lowRISC/ibex", "pr_id": 1176, "lang": "sv", "rtl_files": ["dv/uvm/core_ibex/env/core_ibex_instr_monitor_if.sv"], "commit_id": "5826af8ad924eccdb51b8ea02dfd54a9d4719edf", "timestamp": "2020-11-06T09:25:41+00:00", "pr_title": "[dv] Fix riscv_debug_single_step_test", "pr_body": "Testbench computation of next PC when single stepping was broken. A\r\nbranch may stall before branch_set is asserted and this wasn't being\r\ntaken into account. Where the branch target ALU is present branch_set\r\ncan be set on the first cycle of the branch so this bug wasn't apparent.\r\nEven with the branch target ALU the branch may stall awaiting the result\r\nof a load when the writeback stage is present.\r\n\r\nTo make matters more complicated for a jump the PC being jumped to is\r\nonly available when jump_set is asserted which happens whilst the jump\r\ninstruction is stalling.\r\n\r\nThis alters the riscv_debug_single_step_test so when waiting for a\r\nsingle step it looks for either a branch_set or jump_set signal being\r\nasserted. Otherwise it waits until the instruction has unstalled. This\r\nshould give correct behaviour in all scenarios (potentially further\r\nthought required where exceptions and interrupts occur).\r\n\r\nFixes #1167\r\n\r\nSigned-off-by: Greg Chadwick ", "issue_title": "riscv_debug_single_step_test fail ", "issue_body": "Hi ,\r\nwhen SEED=27754, IBEX_CONFIG=small, ISS=ovpsim, riscv_debug_single_step_test fail because dpc record the branch target address when core executes a branch instruction, but the test bench think the dpc of the core should record the address of the branch instruction address +4, I think the RTL is right, please help double check it.\r\n\r\n\r\nThanks,\r\nLihua", "commit_message": "[dv] Fix riscv_debug_single_step_test\n\nTestbench computation of next PC when single stepping was broken. A\nbranch may stall before branch_set is asserted and this wasn't being\ntaken into account. Where the branch target ALU is present branch_set\ncan be set on the first cycle of the branch so this bug wasn't apparent.\nEven with the branch target ALU the branch may stall awaiting the result\nof a load when the writeback stage is present.\n\nTo make matters more complicated for a jump the PC being jumped to is\nonly available when jump_set is asserted which happens whilst the jump\ninstruction is stalling.\n\nThis alters the riscv_debug_single_step_test so when waiting for a\nsingle step it looks for either a branch_set or jump_set signal being\nasserted. Otherwise it waits until the instruction has unstalled. This\nshould give correct behaviour in all scenarios (potentially further\nthought required where exceptions and interrupts occur).\n\nFixes #1167\n\nSigned-off-by: Greg Chadwick ", "fix_patch": "diff --git a/dv/uvm/core_ibex/env/core_ibex_instr_monitor_if.sv b/dv/uvm/core_ibex/env/core_ibex_instr_monitor_if.sv\nindex 171d0f593e..9db8df37e2 100644\n--- a/dv/uvm/core_ibex/env/core_ibex_instr_monitor_if.sv\n+++ b/dv/uvm/core_ibex/env/core_ibex_instr_monitor_if.sv\n@@ -21,6 +21,8 @@ interface core_ibex_instr_monitor_if #(\n logic [DATA_WIDTH-1:0] pc_id;\n logic branch_taken_id;\n logic [DATA_WIDTH-1:0] branch_target_id;\n+ logic stall_id;\n+ logic jump_set_id;\n \n clocking instr_cb @(posedge clk);\n input valid_id;\n@@ -31,6 +33,8 @@ interface core_ibex_instr_monitor_if #(\n input pc_id;\n input branch_taken_id;\n input branch_target_id;\n+ input stall_id;\n+ input jump_set_id;\n endclocking\n \n endinterface\n", "test_patch": "diff --git a/dv/uvm/core_ibex/tb/core_ibex_tb_top.sv b/dv/uvm/core_ibex/tb/core_ibex_tb_top.sv\nindex 7ca8ac0ffe..ab572acfb1 100644\n--- a/dv/uvm/core_ibex/tb/core_ibex_tb_top.sv\n+++ b/dv/uvm/core_ibex/tb/core_ibex_tb_top.sv\n@@ -151,6 +151,8 @@ module core_ibex_tb_top;\n assign instr_monitor_if.pc_id = dut.u_ibex_core.pc_id;\n assign instr_monitor_if.branch_taken_id = dut.u_ibex_core.id_stage_i.controller_i.branch_set_i;\n assign instr_monitor_if.branch_target_id = dut.u_ibex_core.branch_target_ex;\n+ assign instr_monitor_if.stall_id = dut.u_ibex_core.id_stage_i.stall_id;\n+ assign instr_monitor_if.jump_set_id = dut.u_ibex_core.id_stage_i.jump_set;\n // CSR interface connections\n assign csr_if.csr_access = dut.u_ibex_core.csr_access;\n assign csr_if.csr_addr = dut.u_ibex_core.csr_addr;\ndiff --git a/dv/uvm/core_ibex/tests/core_ibex_test_lib.sv b/dv/uvm/core_ibex/tests/core_ibex_test_lib.sv\nindex 3a1f33f64b..3686c8e7f0 100644\n--- a/dv/uvm/core_ibex/tests/core_ibex_test_lib.sv\n+++ b/dv/uvm/core_ibex/tests/core_ibex_test_lib.sv\n@@ -985,6 +985,28 @@ class core_ibex_debug_single_step_test extends core_ibex_directed_test;\n `uvm_component_utils(core_ibex_debug_single_step_test)\n `uvm_component_new\n \n+ // Waits until PC has changed from `cur_pc` and continues waiting until PC two steps ahead from\n+ // `cur_pc` can be determined.\n+ //\n+ // cur_pc -> a_pc -> b_pc\n+ // ^\n+ // |\n+ //\n+ // This will wait until instruction execution is at `a_pc` and keep waiting until it is clear what\n+ // `b_pc` will be.\n+ virtual task wait_for_pc_change(bit [ibex_mem_intf_agent_pkg::DATA_WIDTH-1:0] cur_pc);\n+ // Wait for instruction PC to change then continuing waiting whilst it's stalled, immediately\n+ // stop waiting if a branch is taken or a jump is set (the PC following `cur_pc` will be\n+ // available the same cycle this happens). If `cur_pc` is a branch that isn't taken this will\n+ // be resolved when the branch is unstalled (i.e. `branch_taken_id` won't be set and the branch\n+ // definitely isn't taken).\n+ wait (instr_vif.instr_cb.pc_id != cur_pc &&\n+ instr_vif.instr_cb.valid_id &&\n+ (!instr_vif.instr_cb.stall_id ||\n+ instr_vif.instr_cb.branch_taken_id ||\n+ instr_vif.instr_cb.jump_set_id));\n+ endtask\n+\n virtual task check_stimulus();\n bit [ibex_mem_intf_agent_pkg::DATA_WIDTH-1:0] counter = 0;\n bit [ibex_mem_intf_agent_pkg::DATA_WIDTH-1:0] next_counter = 0;\n@@ -1015,9 +1037,8 @@ class core_ibex_debug_single_step_test extends core_ibex_directed_test;\n wait_ret(\"dret\", 5000);\n ret_pc = instr_vif.instr_cb.pc_id;\n // wait for the instruction after dret to log its PC and other information.\n- wait (instr_vif.instr_cb.pc_id != ret_pc &&\n- instr_vif.instr_cb.valid_id &&\n- !dut_vif.dut_cb.dret);\n+ wait(!dut_vif.dut_cb.dret);\n+ wait_for_pc_change(ret_pc);\n curr_pc = instr_vif.instr_cb.pc_id;\n step_instr = instr_vif.instr_cb.instr_id;\n is_compressed = instr_vif.instr_cb.is_compressed_id;\n@@ -1079,9 +1100,8 @@ class core_ibex_debug_single_step_test extends core_ibex_directed_test;\n ret_pc = instr_vif.instr_cb.pc_id;\n if (counter == 0) break;\n // wait until Ibex steps to the next instruction.\n- wait (instr_vif.instr_cb.pc_id != ret_pc &&\n- instr_vif.instr_cb.valid_id &&\n- !dut_vif.dut_cb.dret);\n+ wait(!dut_vif.dut_cb.dret);\n+ wait_for_pc_change(ret_pc);\n // log information about this instruction\n curr_pc = instr_vif.instr_cb.pc_id;\n step_instr = instr_vif.instr_cb.instr_id;\n", "modified_files": ["dv/uvm/core_ibex/env/core_ibex_instr_monitor_if.sv", "dv/uvm/core_ibex/tb/core_ibex_tb_top.sv", "dv/uvm/core_ibex/tests/core_ibex_test_lib.sv"], "lines_added": 32, "lines_removed": 6} +{"repo": "lowRISC/ibex", "pr_id": 1136, "lang": "sv", "rtl_files": ["rtl/ibex_cs_registers.sv"], "commit_id": "1a9545baaf973c361d4ee5ac7b715d5957a4ceef", "timestamp": "2020-10-14T16:35:01+00:00", "pr_title": "[rtl] Fix illegal write to DCSR cause field", "pr_body": "- This field is read-only to software, and so should retain its previous\r\n value on a write. This fixes #1134.\r\n\r\nSigned-off-by: Tom Roberts ", "issue_title": "Access rights - Illegal Write to Read Only Field - DCSR's cause", "issue_body": "#### RISC-V Specification\r\n\r\n> External Debug Support [4.8.1]\r\n\r\n#### Issue Description\r\n\r\nA read only field of `dcsr` is written. \r\n\r\n#### Steps to Reproduce\r\n\r\nAs shown below, while in debug mode, the instruction `csrrwi x17, dcsr, 0x4` updates the value of the `cause` field of `dcsr`, which has a read only access right.\r\n\r\n![dcsr_cause_write](https://user-images.githubusercontent.com/54367010/95985860-6ff77800-0e25-11eb-916e-ab3b01f116b6.PNG)\r\n\r\n---\r\nProduct: OneSpin 360 DV-Verify\r\nApp: Processor Verification App\r\nTool's version: 2020.2.0", "commit_message": "[rtl] Fix illegal write to DCSR cause field\n\n- This field is read-only to software, and so should retain its previous\n value on a write. This fixes #1134.\n\nSigned-off-by: Tom Roberts ", "fix_patch": "diff --git a/rtl/ibex_cs_registers.sv b/rtl/ibex_cs_registers.sv\nindex 9651e748fb..64fd64dc1b 100644\n--- a/rtl/ibex_cs_registers.sv\n+++ b/rtl/ibex_cs_registers.sv\n@@ -532,6 +532,9 @@ module ibex_cs_registers #(\n dcsr_d.prv = PRIV_LVL_M;\n end\n \n+ // Read-only for SW\n+ dcsr_d.cause = dcsr_q.cause;\n+\n // currently not supported:\n dcsr_d.nmip = 1'b0;\n dcsr_d.mprven = 1'b0;\n", "test_patch": "", "modified_files": ["rtl/ibex_cs_registers.sv"], "lines_added": 3, "lines_removed": 0} +{"repo": "lowRISC/ibex", "pr_id": 1130, "lang": "sv", "rtl_files": ["rtl/ibex_decoder.sv"], "commit_id": "bcbf1a7adf27c3bfc57205c684c2192c0d24fa3f", "timestamp": "2020-10-14T08:49:31+00:00", "pr_title": "[rtl] Fix missing else branch in decoder", "pr_body": "- Without the B extension, a gorci instruction should decode as an\r\n illegal instruction.\r\n- Relates to #1129\r\n\r\nSigned-off-by: Tom Roberts ", "issue_title": "Illegal Instruction Exception not Raised", "issue_body": "**RISC-V Specification:**\r\n\r\n> Unprivileged ISA\r\n\r\n**Issue Description:**\r\n\r\nAn illegal instruction updates the register file and the associated csrs and executes normally without raising an illegal instruction exception.\r\n\r\n**Example:**\r\n\r\nThe instruction 32'h2820d013 is decoded and executed with no illegal instruction exception being flagged, as machine csrs: mepc, mstatus and mcause aren't updated. \r\n\r\n![illegalInstr](https://user-images.githubusercontent.com/54367010/95882023-7cbe9200-0d79-11eb-97de-fd485e24e459.PNG)\r\n\r\n---\r\n\r\nProduct: OneSpin 360 DV-Verify\r\nApp: Processor Verification App\r\nTool's version: 2020.2.0", "commit_message": "[rtl] Fix missing else branch in decoder\n\n- Without the B extension, a gorci instruction should decode as an\n illegal instruction.\n- Relates to #1129\n\nSigned-off-by: Tom Roberts ", "fix_patch": "diff --git a/rtl/ibex_decoder.sv b/rtl/ibex_decoder.sv\nindex f55b719cec..c8d4141899 100644\n--- a/rtl/ibex_decoder.sv\n+++ b/rtl/ibex_decoder.sv\n@@ -408,6 +408,8 @@ module ibex_decoder #(\n illegal_insn = 1'b0; // gorci\n end else if (instr[24:20] == 5'b00111) begin\n illegal_insn = (RV32B == RV32BBalanced) ? 1'b0 : 1'b1; // orc.b\n+ end else begin\n+ illegal_insn = 1'b1;\n end\n end\n 5'b0_0001: begin\n", "test_patch": "", "modified_files": ["rtl/ibex_decoder.sv"], "lines_added": 2, "lines_removed": 0} +{"repo": "lowRISC/ibex", "pr_id": 1107, "lang": "sv", "rtl_files": ["rtl/ibex_controller.sv"], "commit_id": "c31d066130bdce11dfbacf7afab7641dbd9157f5", "timestamp": "2020-09-14T13:19:36+00:00", "pr_title": "[rtl] Fix debug step over EBREAK issue", "pr_body": "- If there is a request to enter debug mode (either due to a halt\r\n request or single stepping mode) on the same cycle as an EBREAK\r\n instruction, continue with the EBREAK and capture the ID PC rather\r\n than the IF PC.\r\n- relates to #1106\r\n\r\nSigned-off-by: Tom Roberts ", "issue_title": "The step operation is error when the SW bp is set in a J instruction.", "issue_body": "Hi Guys： \r\n I use the Ibex core running a simple test C code. \r\n I set a SW bp before a “jump” instruction, when the cpu fetched the SW bp instruction, the cpu is halted. \r\n But after that, i use the “step\" cmd in telnet, the PC in CPU is wrong, it's not the correct PC which the JUMP instruction expected , the dpc has been changed. \r\n When I use the HW bp， the dpc has‘t been changed.\r\n So, i think this is a bug\r\n please see the following figure.\r\n \r\n\r\n\r\n![image](https://user-images.githubusercontent.com/71075865/92725183-51254200-f39e-11ea-81fc-698ca50d9b6b.png)\r\n\r\n![image](https://user-images.githubusercontent.com/71075865/92725197-571b2300-f39e-11ea-8c1b-1e2a62d5aed7.png)\r\n\r\n![image](https://user-images.githubusercontent.com/71075865/92725252-70bc6a80-f39e-11ea-8581-3ed01bcebc3b.png)\r\n\r\n\r\n\r\n\r\n", "commit_message": "[rtl] Fix debug step over EBREAK issue\n\n- If there is a request to enter debug mode (either due to a halt\n request or single stepping mode) on the same cycle as an EBREAK\n instruction, continue with the EBREAK and capture the ID PC rather\n than the IF PC.\n- relates to #1106\n\nSigned-off-by: Tom Roberts ", "fix_patch": "diff --git a/rtl/ibex_controller.sv b/rtl/ibex_controller.sv\nindex afa7fff87b..f943b30d15 100644\n--- a/rtl/ibex_controller.sv\n+++ b/rtl/ibex_controller.sv\n@@ -766,7 +766,10 @@ module ibex_controller #(\n // Leave all other signals as is to ensure CSRs and PC get set as if\n // core was entering exception handler, entry to debug mode will then\n // see the appropriate state and setup dpc correctly.\n- if (enter_debug_mode) begin\n+ // If an EBREAK instruction is causing us to enter debug mode on the\n+ // same cycle as a debug_req or single step, honor the EBREAK and\n+ // proceed to DBG_TAKEN_ID.\n+ if (enter_debug_mode && !(ebrk_insn_prio && ebreak_into_debug)) begin\n ctrl_fsm_ns = DBG_TAKEN_IF;\n end\n end // FLUSH\n", "test_patch": "", "modified_files": ["rtl/ibex_controller.sv"], "lines_added": 4, "lines_removed": 1} +{"repo": "lowRISC/ibex", "pr_id": 1087, "lang": "sv", "rtl_files": ["rtl/ibex_decoder.sv"], "commit_id": "e145a49b321cbcf41d04b3fd7c29f40f521b6e52", "timestamp": "2020-08-21T10:09:13+00:00", "pr_title": "[rtl] Fix FENCE comment in decoder", "pr_body": "- Clarify FENCE treatment rationale\r\n- Update comment around ICache flushing\r\n- Fixes #1048\r\n\r\nSigned-off-by: Tom Roberts ", "issue_title": "Fix comment or code in decoder regarding FENCE behavior", "issue_body": "I just stumbled across this comment in the decoder:\r\n\r\nhttps://github.com/lowRISC/ibex/blob/94d505716870ddf240d0896021871176d6336579/rtl/ibex_decoder.sv#L538-L540\r\n\r\n@tomroberts-lowrisc Can you have a look at that behavior and (probably) update the comment to what we have today?", "commit_message": "[rtl] Fix FENCE comment in decoder\n\n- Clarify FENCE treatment rationale\n- Update comment around ICache flushing\n- Fixes #1048\n\nSigned-off-by: Tom Roberts ", "fix_patch": "diff --git a/rtl/ibex_decoder.sv b/rtl/ibex_decoder.sv\nindex 309ba04d11..f55b719cec 100644\n--- a/rtl/ibex_decoder.sv\n+++ b/rtl/ibex_decoder.sv\n@@ -535,11 +535,9 @@ module ibex_decoder #(\n /////////////\n \n OPCODE_MISC_MEM: begin\n- // For now, treat the FENCE (funct3 == 000) instruction as a NOP. This may not be correct\n- // in a system with caches and should be revisited.\n- // FENCE.I will flush the IF stage and prefetch buffer (or ICache) but nothing else.\n unique case (instr[14:12])\n 3'b000: begin\n+ // FENCE is treated as a NOP since all memory operations are already strictly ordered.\n rf_we = 1'b0;\n end\n 3'b001: begin\n@@ -1078,16 +1076,15 @@ module ibex_decoder #(\n /////////////\n \n OPCODE_MISC_MEM: begin\n- // For now, treat the FENCE (funct3 == 000) instruction as a NOP. This may not be correct\n- // in a system with caches and should be revisited.\n- // FENCE.I will flush the IF stage and prefetch buffer but nothing else.\n unique case (instr_alu[14:12])\n 3'b000: begin\n+ // FENCE is treated as a NOP since all memory operations are already strictly ordered.\n alu_operator_o = ALU_ADD; // nop\n alu_op_a_mux_sel_o = OP_A_REG_A;\n alu_op_b_mux_sel_o = OP_B_IMM;\n end\n 3'b001: begin\n+ // FENCE.I will flush the IF stage, prefetch buffer and ICache if present.\n if (BranchTargetALU) begin\n bt_a_mux_sel_o = OP_A_CURRPC;\n bt_b_mux_sel_o = IMM_B_INCR_PC;\n", "test_patch": "", "modified_files": ["rtl/ibex_decoder.sv"], "lines_added": 3, "lines_removed": 6} +{"repo": "lowRISC/ibex", "pr_id": 1054, "lang": "sv", "rtl_files": ["rtl/ibex_cs_registers.sv"], "commit_id": "ac51db259d7ba09616b47cb372e528d45358d6db", "timestamp": "2020-08-05T08:17:34+00:00", "pr_title": "[ibex/rtl] Fix pmpaddr write enable signal", "pr_body": "Updates the write enable for `pmpaddr[i]` CSRs to deny writes if\r\n`pmpcfg[i+1].lock == 1` and `pmpcfg[i+1].mode == TOR`, as per the\r\nspec.\r\nRelates to #1044.", "issue_title": "PMP TOR writes and behavior", "issue_body": "1. There appears to be a functional difference between [spike](https://github.com/riscv/riscv-isa-sim/blob/67b7edd0270d5d074136eb45474477d15aeee725/riscv/processor.cc#L809) and [ibex](https://github.com/lowRISC/ibex/blob/d7c13aa9045838e7b9751e87b6b4630e7893db39/rtl/ibex_cs_registers.sv#L828) in the interaction between L and A=TOR; riscv/riscv-isa-manual#545 endorsed the spike interpretation.\r\n\r\n2. Should https://github.com/lowRISC/ibex/blob/master/rtl/ibex_pmp.sv#L92-L93 be generating both ends of the TOR range from the same pmpaddr?", "commit_message": "[ibex/rtl] Fix pmpaddr write enable signal\n\nUpdates the write enable for `pmpaddr[i]` CSRs to deny writes if\n`pmpcfg[i+1].lock == 1` and `pmpcfg[i+1].mode == TOR`, as per the\nspec.", "fix_patch": "diff --git a/rtl/ibex_cs_registers.sv b/rtl/ibex_cs_registers.sv\nindex 6e5eaf4dc8..50d11073ac 100644\n--- a/rtl/ibex_cs_registers.sv\n+++ b/rtl/ibex_cs_registers.sv\n@@ -825,7 +825,7 @@ module ibex_cs_registers #(\n // --------------------------\n if (i < PMPNumRegions - 1) begin : g_lower\n assign pmp_addr_we[i] = csr_we_int & ~pmp_cfg[i].lock &\n- (pmp_cfg[i+1].mode != PMP_MODE_TOR) &\n+ (~pmp_cfg[i+1].lock | (pmp_cfg[i+1].mode != PMP_MODE_TOR)) &\n (csr_addr == (CSR_OFF_PMP_ADDR + i[11:0]));\n end else begin : g_upper\n assign pmp_addr_we[i] = csr_we_int & ~pmp_cfg[i].lock &\n", "test_patch": "", "modified_files": ["rtl/ibex_cs_registers.sv"], "lines_added": 1, "lines_removed": 1} +{"repo": "lowRISC/ibex", "pr_id": 1050, "lang": "sv", "rtl_files": ["dv/uvm/core_ibex/riscv_dv_extension/riscv_core_setting.sv"], "commit_id": "94d505716870ddf240d0896021871176d6336579", "timestamp": "2020-07-24T17:10:22+00:00", "pr_title": "[dv/ibex] Update CSR listings", "pr_body": "This PR updates the `implemented_csr` list in `riscv_core_setting.sv`\r\nand adds the two custom CSRs `cpuctrl` and `secureseed` to the\r\n`custom_csr` list. Both are for use by the riscv-dv generator.\r\n\r\nThis PR can only be merged after #1049 , which vendors in some updates to riscv-dv,\r\nincluding basic support for custom CSRs.\r\n\r\nSigned-off-by: Udi ", "issue_title": "Update google_riscv-dv to google/riscv-dv@3cf691d", "issue_body": "Update code from upstream repository https://github.com/google/riscv-\r\ndv to revision 3cf691dcb96f2cd72250690216b60f2b0c0ac804\r\n\r\n* remove hardcoded CSR names (Udi Jonnalagadda)\r\n* initial custom CSR support (Udi Jonnalagadda)\r\n* Add support for segmented load/store instructions (google/riscv-\r\n dv#656) (taoliug)\r\n* fix post_randomize issue (aneels3)\r\n* add MAX_LMUL to rv32i config (google/riscv-dv#649) (udinator)\r\n* Ignore log and asm file (aneels3)\r\n* Add Command Line Support (aneels3)\r\n* support for command-line arguments (pvipsyash)\r\n* Reorder import statements (aneels3)\r\n* Modified function randomize_gpr in instr_stream file\r\n (ShraddhaDevaiya)\r\n* Updated riscv_instr_sequence file and modified other python files to\r\n get main block in asm file. (ShraddhaDevaiya)\r\n* Modify get_rand_instr() (aneels3)\r\n* added uvm_glob_to_re in uvm_re_match (Dawid Zimonczyk)\r\n* Aldec Riviera-PRO compiler command line arguments modified.\r\n (google/riscv-dv#638) (Dariusz Stachańczyk)\r\n* allow coverage compilation to be run on LSF (google/riscv-dv#637)\r\n (udinator)\r\n* Add CHIPS Alliance work group information to the README\r\n (google/riscv-dv#633) (taoliug)\r\n* Add indexed/strided vector load/store instrution stream\r\n (google/riscv-dv#632) (taoliug)\r\n* Add constraint for mtvec alignment in vectored interrupt mode\r\n (google/riscv-dv#631) (taoliug)\r\n* Add bitstring requirement to pygen/experimental README\r\n (google/riscv-dv#630) (taoliug)\r\n* Add unsupported load/store instruction filtering (google/riscv-\r\n dv#629) (taoliug)\r\n* Add different methods to initialize the vregs (google/riscv-dv#627)\r\n (Josep Sans)\r\n* Support a vetor instruction only mode (google/riscv-dv#626)\r\n (taoliug)\r\n* Add riscv_instr_stream.py file (aneels3)\r\n* Importing PyVSC module (google/riscv-dv#625) (Hodjat Asghari\r\n Esfeden)\r\n* update pygen_src files (google/riscv-dv#612) (BharathNR1030)\r\n* Fix typo (google/riscv-dv#624) (taoliug)\r\n* Fix B-ext instruction generation issue (google/riscv-dv#620)\r\n (taoliug)\r\n\r\nMust be merged before #1050.\r\n\r\nSigned-off-by: Udi ", "commit_message": "[dv/ibex] Update CSR listings\n\nThis PR updates the `implemented_csrs` list in `riscv_core_setting.sv`\nand adds the two custom CSRs `cpuctrl` and `secureseed` to the\n`custom_csrs` list. Both are for use by the riscv-dv generator.\n\nSigned-off-by: Udi ", "fix_patch": "diff --git a/dv/uvm/core_ibex/riscv_dv_extension/riscv_core_setting.sv b/dv/uvm/core_ibex/riscv_dv_extension/riscv_core_setting.sv\nindex 937faf9288..5cba70cf2c 100644\n--- a/dv/uvm/core_ibex/riscv_dv_extension/riscv_core_setting.sv\n+++ b/dv/uvm/core_ibex/riscv_dv_extension/riscv_core_setting.sv\n@@ -159,7 +159,19 @@ const privileged_reg_t implemented_csr[] = {\n DCSR, // Debug control and status register\n DPC, // Debug PC\n DSCRATCH0, // Debug scratch register 0\n- DSCRATCH1 // Debug scratch register 1\n+ DSCRATCH1, // Debug scratch register 1\n+ TSELECT, // Trigger select register\n+ TDATA1, // Trigger data register 1\n+ TDATA2, // Trigger data register 2\n+ TDATA3, // Trigger data register 3\n+ MCONTEXT, // Machine context register\n+ SCONTEXT // Supervisor context register\n+};\n+\n+// Implementation-specific custom CSRs\n+const bit [11:0] custom_csr[] = {\n+ 12'h7C0, // cpuctrl - CPU control register\n+ 12'h7C1 // secureseed - Security feature random seed register\n };\n \n // --------------------------------------------------------------------------\n", "test_patch": "", "modified_files": ["dv/uvm/core_ibex/riscv_dv_extension/riscv_core_setting.sv"], "lines_added": 13, "lines_removed": 1} +{"repo": "lowRISC/ibex", "pr_id": 1037, "lang": "sv", "rtl_files": ["dv/uvm/core_ibex/env/core_ibex_instr_monitor_if.sv"], "commit_id": "7f9e704f362776ea544c318d82a33af5540c0145", "timestamp": "2020-07-17T18:15:14+00:00", "pr_title": "[dv/ibex] Enhance riscv_debug_single_step test", "pr_body": "As pointed out by @tomroberts-lowrisc in #983, the current\r\nimplementation of riscv_debug_single_step_test cannot handle\r\nsingle-stepping over instructions that change the PC.\r\nThis PR aims to introduce this functionality, utilizing the\r\nnew instr_monitor_if.\r\n\r\nNow, if the core single-steps onto a branch/jump instruction, the\r\ntestbench will log the new target PC and compare it against the actual\r\ntarget address stored in `dpc`.\r\n\"Normal\" instructions are checked as usual by incrementing the\r\ninstruction's PC by either 2 or 4 (depending whether it is compressed)\r\nand comparing that against `dpc`.\r\n\r\nThis test passes successfully when combined with the RTL patch in #1034.", "issue_title": "[rtl] remove lsu_req_in_id signal", "issue_body": "This signal aimed to ensure loads/stores completed succesfully when an\r\ninterrupt or debug request appeared at the same time they were being\r\nexecuted when the writeback stage is present. However other stall logic\r\nsuffices for this purpose (debug/interrupt will wait for instruction to\r\nunstall in ID/EX which only happens once request has been sent out, then\r\nfirst instruction of debug/interrupt handler will stall until load/store\r\nresponse has been seen based on the generic stall logic for lsu requests\r\nin the writeback stage).\r\n\r\nWith this signal in place debug single stepping was broken around loads\r\nand stores.\r\n\r\nFixes #1029\r\n\r\nThis half undoes the fix from this PR: https://github.com/lowRISC/ibex/pull/928 which was in response to this OT issue: https://github.com/lowRISC/opentitan/issues/2405\r\n\r\nI'm happy to accept this is not the correct fix but I did have a play with interrupts appearing the same cycle as a load in simple system with various delays on gnt/rvalid and it all seems to work fine. The DV interrupt tests all looked fine. The test in OT that found the original bug was broken on main yesterday (chip_uart_tx_rx) but looking at the latest nightly it seems to be fixed, so I'll have another play with that. Also realised there's some other timing scenarios I can check out with simple system.\r\n", "commit_message": "[dv/ibex] Enhance riscv_debug_single_step test\n\nAs pointed out by @tomroberts-lowrisc in #983, the current\nimplementation of riscv_debug_single_step_test cannot handle\nsingle-stepping over instructions that change the PC.\nThis PR aims to introduce this functionality, utilizing the\nnew instr_monitor_if.\n\nNow, if the core single-steps onto a branch/jump instruction, the\ntestbench will log the new target PC and compare it against the actual\ntarget address stored in `dpc`.\n\"Normal\" instructions are checked as usual by incrementing the\ninstruction's PC by either 2 or 4 (depending whether it is compressed)\nand comparing that against `dpc`.", "fix_patch": "diff --git a/dv/uvm/core_ibex/env/core_ibex_instr_monitor_if.sv b/dv/uvm/core_ibex/env/core_ibex_instr_monitor_if.sv\nindex 2ad60ef3a7..171d0f593e 100644\n--- a/dv/uvm/core_ibex/env/core_ibex_instr_monitor_if.sv\n+++ b/dv/uvm/core_ibex/env/core_ibex_instr_monitor_if.sv\n@@ -6,7 +6,11 @@\n //\n // TODO: does not support dummy instruction insertion right now,\n // might have to revisit and update.\n-interface core_ibex_instr_monitor_if #(parameter DATA_WIDTH = 32);\n+interface core_ibex_instr_monitor_if #(\n+ parameter DATA_WIDTH = 32\n+) (\n+ input clk\n+);\n \n // ID stage\n logic valid_id;\n@@ -14,5 +18,19 @@ interface core_ibex_instr_monitor_if #(parameter DATA_WIDTH = 32);\n logic is_compressed_id;\n logic [15:0] instr_compressed_id;\n logic [DATA_WIDTH-1:0] instr_id;\n+ logic [DATA_WIDTH-1:0] pc_id;\n+ logic branch_taken_id;\n+ logic [DATA_WIDTH-1:0] branch_target_id;\n+\n+ clocking instr_cb @(posedge clk);\n+ input valid_id;\n+ input err_id;\n+ input is_compressed_id;\n+ input instr_compressed_id;\n+ input instr_id;\n+ input pc_id;\n+ input branch_taken_id;\n+ input branch_target_id;\n+ endclocking\n \n endinterface\n", "test_patch": "diff --git a/dv/uvm/core_ibex/riscv_dv_extension/testlist.yaml b/dv/uvm/core_ibex/riscv_dv_extension/testlist.yaml\nindex 37d82b6c2e..d417b058ca 100644\n--- a/dv/uvm/core_ibex/riscv_dv_extension/testlist.yaml\n+++ b/dv/uvm/core_ibex/riscv_dv_extension/testlist.yaml\n@@ -535,11 +535,11 @@\n +require_signature_addr=1\n +gen_debug_section=1\n +no_ebreak=1\n- +no_branch_jump=1\n+ +no_branch_jump=0\n +instr_cnt=10000\n +no_csr_instr=1\n +no_fence=1\n- +num_of_sub_program=0\n+ +num_of_sub_program=2\n +randomize_csr=1\n +enable_debug_single_step=1\n rtl_test: core_ibex_debug_single_step_test\ndiff --git a/dv/uvm/core_ibex/tb/core_ibex_tb_top.sv b/dv/uvm/core_ibex/tb/core_ibex_tb_top.sv\nindex 9aa65affe3..c1dd52114a 100644\n--- a/dv/uvm/core_ibex/tb/core_ibex_tb_top.sv\n+++ b/dv/uvm/core_ibex/tb/core_ibex_tb_top.sv\n@@ -21,7 +21,7 @@ module core_ibex_tb_top;\n core_ibex_dut_probe_if dut_if(.clk(clk));\n \n // Instruction monitor interface\n- core_ibex_instr_monitor_if instr_monitor_if();\n+ core_ibex_instr_monitor_if instr_monitor_if(.clk(clk));\n \n // RVFI interface\n core_ibex_rvfi_if rvfi_if(.clk(clk));\n@@ -139,6 +139,9 @@ module core_ibex_tb_top;\n assign instr_monitor_if.is_compressed_id = dut.u_ibex_core.id_stage_i.instr_is_compressed_i;\n assign instr_monitor_if.instr_compressed_id = dut.u_ibex_core.id_stage_i.instr_rdata_c_i;\n assign instr_monitor_if.instr_id = dut.u_ibex_core.id_stage_i.instr_rdata_i;\n+ assign instr_monitor_if.pc_id = dut.u_ibex_core.pc_id;\n+ assign instr_monitor_if.branch_taken_id = dut.u_ibex_core.id_stage_i.controller_i.branch_set_i;\n+ assign instr_monitor_if.branch_target_id = dut.u_ibex_core.branch_target_ex;\n // CSR interface connections\n assign csr_if.csr_access = dut.u_ibex_core.csr_access;\n assign csr_if.csr_addr = dut.u_ibex_core.csr_addr;\ndiff --git a/dv/uvm/core_ibex/tests/core_ibex_test_lib.sv b/dv/uvm/core_ibex/tests/core_ibex_test_lib.sv\nindex 14426c5980..9ad59cd613 100644\n--- a/dv/uvm/core_ibex/tests/core_ibex_test_lib.sv\n+++ b/dv/uvm/core_ibex/tests/core_ibex_test_lib.sv\n@@ -483,7 +483,7 @@ class core_ibex_directed_test extends core_ibex_debug_intr_basic_test;\n bit [12:0] system_imm;\n instr_t instr_fields;\n \n- opcode = ibex_pkg::opcode_e'(instr[6:0]);\n+ opcode = ibex_pkg::opcode_e`(instr[6:0]);\n funct3 = instr[14:12];\n funct7 = instr[31:25];\n system_imm = instr[31:20];\n@@ -658,16 +658,16 @@ class core_ibex_interrupt_instr_test extends core_ibex_directed_test;\n vseq.irq_raise_single_seq_h.max_interval = 0;\n forever begin\n // hold until we see a valid instruction in the ID stage of the pipeline.\n- wait (instr_vif.valid_id && !(instr_vif.err_id || dut_vif.illegal_instr));\n+ wait (instr_vif.instr_cb.valid_id && !(instr_vif.instr_cb.err_id || dut_vif.illegal_instr));\n \n // We don't want to send fast interrupts, as due to the random setup of MIE,\n // there's no guarantee that the interrupt will actually be taken.\n- if (instr_vif.is_compressed_id) begin\n- if (decode_compressed_instr(instr_vif.instr_compressed_id)) begin\n+ if (instr_vif.instr_cb.is_compressed_id) begin\n+ if (decode_compressed_instr(instr_vif.instr_cb.instr_compressed_id)) begin\n send_irq_stimulus(.no_fast(1'b1));\n end\n end else begin\n- if (decode_instr(instr_vif.instr_id)) begin\n+ if (decode_instr(instr_vif.instr_cb.instr_id)) begin\n send_irq_stimulus(.no_fast(1'b1));\n end\n end\n@@ -829,21 +829,21 @@ class core_ibex_debug_instr_test extends core_ibex_directed_test;\n vseq.debug_seq_single_h.max_interval = 0;\n forever begin\n // hold until we see a valid instruction in the ID stage of the pipeline.\n- wait (instr_vif.valid_id && !(instr_vif.err_id || dut_vif.illegal_instr));\n+ wait (instr_vif.instr_cb.valid_id && !(instr_vif.instr_cb.err_id || dut_vif.illegal_instr));\n \n // We don't want to send fast interrupts, as due to the random setup of MIE,\n // there's no guarantee that the interrupt will actually be taken.\n- if (instr_vif.is_compressed_id) begin\n- if (decode_compressed_instr(instr_vif.instr_compressed_id)) begin\n+ if (instr_vif.instr_cb.is_compressed_id) begin\n+ if (decode_compressed_instr(instr_vif.instr_cb.instr_compressed_id)) begin\n send_debug_stimulus(init_operating_mode,\n $sformatf(\"Did not jump into debug mode after instruction[0x%0x]\",\n- instr_vif.instr_compressed_id));\n+ instr_vif.instr_cb.instr_compressed_id));\n end\n end else begin\n- if (decode_instr(instr_vif.instr_id)) begin\n+ if (decode_instr(instr_vif.instr_cb.instr_id)) begin\n send_debug_stimulus(init_operating_mode,\n $sformatf(\"Did not jump into debug mode after instruction[0x%0x]\",\n- instr_vif.instr_id));\n+ instr_vif.instr_cb.instr_id));\n end\n end\n clk_vif.wait_clks(1);\n@@ -986,38 +986,85 @@ class core_ibex_debug_single_step_test extends core_ibex_directed_test;\n `uvm_component_new\n \n virtual task check_stimulus();\n- bit[ibex_mem_intf_agent_pkg::DATA_WIDTH-1:0] ret_pc;\n bit [ibex_mem_intf_agent_pkg::DATA_WIDTH-1:0] counter = 0;\n bit [ibex_mem_intf_agent_pkg::DATA_WIDTH-1:0] next_counter = 0;\n+ bit [ibex_mem_intf_agent_pkg::DATA_WIDTH-1:0] ret_pc;\n+ bit [ibex_mem_intf_agent_pkg::DATA_WIDTH-1:0] curr_pc;\n+ bit [ibex_mem_intf_agent_pkg::DATA_WIDTH-1:0] next_pc;\n+ bit [ibex_mem_intf_agent_pkg::DATA_WIDTH-1:0] step_instr;\n+ bit [ibex_mem_intf_agent_pkg::DATA_WIDTH-1:0] branch_target;\n+ bit branch_taken;\n+ bit is_compressed;\n+\n forever begin\n clk_vif.wait_clks(2000);\n vseq.start_debug_single_seq();\n+ // perform the standard set of debug mode checks\n check_next_core_status(IN_DEBUG_MODE,\n \"Core did not enter debug mode after debug stimulus\", 1000);\n check_priv_mode(PRIV_LVL_M);\n wait_for_csr_write(CSR_DPC, 500);\n ret_pc = signature_data;\n wait_for_csr_write(CSR_DSCRATCH0, 500);\n- next_counter = signature_data;\n+ counter = signature_data;\n wait_for_csr_write(CSR_DCSR, 1000);\n check_dcsr_prv(init_operating_mode);\n check_dcsr_cause(DBG_CAUSE_HALTREQ);\n `DV_CHECK_EQ_FATAL(signature_data[2], 1'b1, \"dcsr.step is not set\")\n+ // wait for the DRET instruction indicating return out of debug mode.\n wait_ret(\"dret\", 5000);\n- // now we loop on the counter until we are done single stepping\n+ ret_pc = instr_vif.instr_cb.pc_id;\n+ // wait for the instruction after dret to log its PC and other information.\n+ wait (instr_vif.instr_cb.pc_id != ret_pc &&\n+ instr_vif.instr_cb.valid_id &&\n+ !dut_vif.dut_cb.dret);\n+ curr_pc = instr_vif.instr_cb.pc_id;\n+ step_instr = instr_vif.instr_cb.instr_id;\n+ is_compressed = instr_vif.instr_cb.is_compressed_id;\n+ branch_taken = instr_vif.instr_cb.branch_taken_id;\n+ // need to zero the bottom bit of branch_target to prevent unaligned addresses.\n+ branch_target = instr_vif.instr_cb.branch_target_id;\n+ branch_target[0] = 1'b0;\n+ // After the first DRET, the next instructions will cause a transition\n+ // into debug mode, as the core will single-step over all of them.\n+ //\n+ // Now we loop on the counter until we are done single stepping\n while (counter >= 0) begin\n- counter = next_counter;\n check_next_core_status(IN_DEBUG_MODE,\n \"Core did not enter debug mode after debug stimulus\", 1000);\n check_priv_mode(PRIV_LVL_M);\n wait_for_csr_write(CSR_DPC, 500);\n- if (signature_data - ret_pc !== 'h2 &&\n- signature_data - ret_pc !== 'h4) begin\n- `uvm_fatal(`gfn,\n- $sformatf(\"DPC value [0x%0x] is not the next instruction after ret_pc [0x%0x]\",\n- signature_data, ret_pc))\n- end\n ret_pc = signature_data;\n+ // checks depend whether the interrupt instruction is a branch/jump.\n+ // we can also assume the instruction is valid as this test disables illegal instructions.\n+ case (ibex_pkg::opcode_e`(step_instr[6:0]))\n+ OPCODE_JAL, OPCODE_JALR: begin\n+ `DV_CHECK_EQ_FATAL(branch_target, ret_pc,\n+ $sformatf(\"DPC value[0x%0x] does not match jump target[0x%0x] at PC[0x%0x]\",\n+ ret_pc, branch_target, curr_pc))\n+ end\n+ OPCODE_BRANCH: begin\n+ // first check whether branch is actually taken\n+ if (branch_taken) begin\n+ `DV_CHECK_EQ_FATAL(branch_target, ret_pc,\n+ $sformatf(\"DPC value[0x%0x] does not match branch target[0x%0x] at PC[0x%0x]\",\n+ ret_pc, branch_target, curr_pc))\n+ end else begin\n+ // branch is not taken\n+ next_pc = (is_compressed) ? curr_pc + 2 : curr_pc + 4;\n+ `DV_CHECK_EQ_FATAL(next_pc, ret_pc,\n+ $sformatf(\"DPC value[0x%0x] does not match expected next PC[0x%0x] at PC[0x%0x]\",\n+ ret_pc, next_pc, curr_pc))\n+ end\n+ end\n+ // all other instructions\n+ default: begin\n+ next_pc = (is_compressed) ? curr_pc + 2 : curr_pc + 4;\n+ `DV_CHECK_EQ_FATAL(next_pc, ret_pc,\n+ $sformatf(\"DPC value[0x%0x] does not match expected next PC[0x%0x] at PC[0x%0x]\",\n+ ret_pc, next_pc, curr_pc))\n+ end\n+ endcase\n wait_for_csr_write(CSR_DSCRATCH0, 500);\n next_counter = signature_data;\n wait_for_csr_write(CSR_DCSR, 500);\n@@ -1029,7 +1076,21 @@ class core_ibex_debug_single_step_test extends core_ibex_directed_test;\n `DV_CHECK_EQ_FATAL(signature_data[2], 1'b1, \"dcsr.step is not set\")\n end\n wait_ret(\"dret\", 5000);\n- if (counter === 0) break;\n+ ret_pc = instr_vif.instr_cb.pc_id;\n+ if (counter == 0) break;\n+ // wait until Ibex steps to the next instruction.\n+ wait (instr_vif.instr_cb.pc_id != ret_pc &&\n+ instr_vif.instr_cb.valid_id &&\n+ !dut_vif.dut_cb.dret);\n+ // log information about this instruction\n+ curr_pc = instr_vif.instr_cb.pc_id;\n+ step_instr = instr_vif.instr_cb.instr_id;\n+ is_compressed = instr_vif.instr_cb.is_compressed_id;\n+ branch_taken = instr_vif.instr_cb.branch_taken_id;\n+ // need to zero the bottom bit of branch_target to prevent unaligned addresses.\n+ branch_target = instr_vif.instr_cb.branch_target_id;\n+ branch_target[0] = 1'b0;\n+ counter = next_counter;\n end\n end\n endtask\n", "modified_files": ["dv/uvm/core_ibex/env/core_ibex_instr_monitor_if.sv", "dv/uvm/core_ibex/riscv_dv_extension/testlist.yaml", "dv/uvm/core_ibex/tb/core_ibex_tb_top.sv", "dv/uvm/core_ibex/tests/core_ibex_test_lib.sv"], "lines_added": 108, "lines_removed": 26} +{"repo": "lowRISC/ibex", "pr_id": 1036, "lang": "sv", "rtl_files": ["rtl/ibex_decoder.sv"], "commit_id": "03a8ae70d68159d2b4a1c53d1d896a5751625a89", "timestamp": "2020-07-17T15:05:37+00:00", "pr_title": "[rtl] Make sure decoder also checks bits 26 and 25 for slli, srli, srai", "pr_body": "Previously, these bits were not checked when decoding `slli`, `srli` and `srai`, causing some illegal instruction encodings not to trigger an illegal instructions exception.\r\n\r\nThis resolves lowRISC/Ibex#1018.", "issue_title": "Illegal Instruction Exception not Raised - Shift Instructions", "issue_body": "**RISC-V Specification:**\r\n\r\n- _\"Chapter 2.4 of Unprivileged ISA\"_\r\n\r\n**Issue Description:**\r\n\r\nAn illegal instruction updates the register file and the associated csrs and executes normally without raising an illegal instruction exception.\r\n\r\n**Example:**\r\n\r\nThe instruction 32'h02005913 is decoded at time point t##0 with no illegal instruction being flagged, as illegal_insn_did is de-asserted.\r\n\r\n![Issue_0](https://user-images.githubusercontent.com/54367010/86763358-913b1200-c047-11ea-9bfd-afd69a9bbd53.PNG)\r\n\r\n---\r\n\r\nProduct: OneSpin 360 DV-Verify\r\nApp: RVV\r\nTool's version: 2020.1.3", "commit_message": "[rtl] Make sure decoder also checks bits 26 and 25 for slli, srli, srai\n\nPreviously, these bits were not checked when decoding slli, srli and\nsrai, causing some illegal instruction encodings not to trigger an\nillegal instructions exception.\n\nThis resolves lowRISC/Ibex#1018.\n\nSigned-off-by: Pirmin Vogel ", "fix_patch": "diff --git a/rtl/ibex_decoder.sv b/rtl/ibex_decoder.sv\nindex 3b2807eb8f..5788f8d59e 100644\n--- a/rtl/ibex_decoder.sv\n+++ b/rtl/ibex_decoder.sv\n@@ -348,7 +348,7 @@ module ibex_decoder #(\n \n 3'b001: begin\n unique case (instr[31:27])\n- 5'b0_0000: illegal_insn = 1'b0; // slli\n+ 5'b0_0000: illegal_insn = (instr[26:25] == 2'b00) ? 1'b0 : 1'b1; // slli\n 5'b0_0100, // sloi\n 5'b0_1001, // sbclri\n 5'b0_0101, // sbseti\n@@ -385,7 +385,7 @@ module ibex_decoder #(\n end else begin\n unique case (instr[31:27])\n 5'b0_0000, // srli\n- 5'b0_1000: illegal_insn = 1'b0; // srai\n+ 5'b0_1000: illegal_insn = (instr[26:25] == 2'b00) ? 1'b0 : 1'b1; // srai\n \n 5'b0_0100, // sroi\n 5'b0_1100, // rori\n", "test_patch": "", "modified_files": ["rtl/ibex_decoder.sv"], "lines_added": 2, "lines_removed": 2} +{"repo": "lowRISC/ibex", "pr_id": 1002, "lang": "sv", "rtl_files": ["rtl/gift_pkg.sv"], "commit_id": "7eedd7f4a14824897c727b5768ff4623ae58ce52", "timestamp": "2020-07-03T13:15:05+00:00", "pr_title": "Unpack and reduce Gift package arrays", "pr_body": "As requested in #993 .\r\n\r\nUnpacked arrays have been reversed to keep the same order.", "issue_title": "Hook up real Gift cipher core", "issue_body": "I hook up real gift cipher core. Currently there are some line errors in the gift module, but I will fix it in another PR.", "commit_message": "Improved Gift package", "fix_patch": "diff --git a/rtl/gift_pkg.sv b/rtl/gift_pkg.sv\nindex 4ee76d17f3..3becc1bae9 100644\n--- a/rtl/gift_pkg.sv\n+++ b/rtl/gift_pkg.sv\n@@ -4,26 +4,24 @@\n \n package gift_pkg;\n \n- localparam logic [15:0][3:0] GSBOX = {\n- 4'hE, 4'h8, 4'h0, 4'h5, 4'h7, 4'hB, 4'hD, 4'h2, 4'h9, 4'h3, 4'hF, 4'h6, 4'hC, 4'h4, 4'hA,\n- 4'h1};\n-\n- localparam logic [63:0][5:0] P_PERMUT = {\n- 6'd15, 6'd62, 6'd45, 6'd28, 6'd31, 6'd14, 6'd61, 6'd44, 6'd47, 6'd30, 6'd13, 6'd60, 6'd63,\n- 6'd46, 6'd29, 6'd12, 6'd11, 6'd58, 6'd41, 6'd24, 6'd27, 6'd10, 6'd57, 6'd40, 6'd43, 6'd26,\n- 6'd9 , 6'd56, 6'd59, 6'd42, 6'd25, 6'd8 , 6'd7 , 6'd54, 6'd37, 6'd20, 6'd23, 6'd6 , 6'd53,\n- 6'd36, 6'd39, 6'd22, 6'd5 , 6'd52, 6'd55, 6'd38, 6'd21, 6'd4 , 6'd3 , 6'd50, 6'd33, 6'd16,\n- 6'd19, 6'd2 , 6'd49, 6'd32, 6'd35, 6'd18, 6'd1 , 6'd48, 6'd51, 6'd34, 6'd17, 6'd0\n+ localparam logic [3:0] GSBOX[16] = '{\n+ 4'h1, 4'hA, 4'h4, 4'hC, 4'h6, 4'hF, 4'h3, 4'h9, 4'h2, 4'hD, 4'hB, 4'h7, 4'h5, 4'h0, 4'h8, 4'hE\n };\n \n- localparam logic [31:0][5:0] RC = {\n- 6'h20, 6'h10, 6'h28, 6'h14, 6'h2a, 6'h15, 6'h0a, 6'h25, 6'h32, 6'h19, 6'h0c, 6'h26, 6'h13,\n- 6'h09, 6'h04, 6'h22, 6'h11, 6'h08, 6'h24, 6'h12, 6'h29, 6'h34, 6'h1A, 6'h2D, 6'h36, 6'h1B,\n- 6'h0D, 6'h06, 6'h23, 6'h31, 6'h38, 6'h1C, 6'h2E, 6'h17, 6'h0B, 6'h05, 6'h02, 6'h21, 6'h30,\n- 6'h18, 6'h2C, 6'h16, 6'h2B, 6'h35, 6'h3A, 6'h1D, 6'h0E, 6'h27, 6'h33, 6'h39, 6'h3C, 6'h1E,\n- 6'h2F, 6'h37, 6'h3B, 6'h3D, 6'h3E, 6'h1F, 6'h0F, 6'h07, 6'h03, 6'h01\n+ localparam logic [5:0] P_PERMUT[64] = '{\n+ 6'd0, 6'd17, 6'd34, 6'd51, 6'd48, 6'd1, 6'd18, 6'd35, 6'd32, 6'd49, 6'd2, 6'd19, 6'd16, 6'd33,\n+ 6'd50, 6'd3, 6'd4, 6'd21, 6'd38, 6'd55, 6'd52, 6'd5, 6'd22, 6'd39, 6'd36, 6'd53, 6'd6, 6'd23,\n+ 6'd20, 6'd37, 6'd54, 6'd7, 6'd8, 6'd25, 6'd42, 6'd59, 6'd56, 6'd9, 6'd26, 6'd43, 6'd40, 6'd57,\n+ 6'd10, 6'd27, 6'd24, 6'd41, 6'd58, 6'd11, 6'd12, 6'd29, 6'd46, 6'd63, 6'd60, 6'd13, 6'd30,\n+ 6'd47, 6'd44, 6'd61, 6'd14, 6'd31, 6'd28, 6'd45, 6'd62, 6'd15\n };\n \n+ localparam logic [5:0] RC[28] = '{\n+ 6'h01, 6'h03, 6'h07, 6'h0F, 6'h1F, 6'h3E, 6'h3D, 6'h3B, 6'h37, 6'h2F, 6'h1E, 6'h3C, 6'h39,\n+ 6'h33, 6'h27, 6'h0E, 6'h1D, 6'h3A, 6'h35, 6'h2B, 6'h16, 6'h2C, 6'h18, 6'h30, 6'h21, 6'h02,\n+ 6'h05, 6'h0B\n+ };\n+ \n typedef enum logic [1:0] {\n BASE_INPUT,\n BASE_1,\n", "test_patch": "", "modified_files": ["rtl/gift_pkg.sv"], "lines_added": 14, "lines_removed": 16} +{"repo": "lowRISC/ibex", "pr_id": 969, "lang": "sv", "rtl_files": ["rtl/ibex_decoder.sv"], "commit_id": "356fb55f7eac9be9ce39e06ebc1f81eee35d13db", "timestamp": "2020-06-18T14:38:06+00:00", "pr_title": "fix for #30", "pr_body": "Signed-off-by: Bert Pieters \r\n\r\nfor fox issue https://github.com/lowRISC/ibex/issues/30", "issue_title": "Cleanup: Remove REG_* defines from ibex_id_stage", "issue_body": "Can we get rid of those defines and replace them by parameters or structs?", "commit_message": "[rtl] Remove use of `define in decoder\n\nFixes #30\n\nSigned-off-by: Bert Pieters ", "fix_patch": "diff --git a/rtl/ibex_decoder.sv b/rtl/ibex_decoder.sv\nindex 96acd3d368..b8952754ba 100644\n--- a/rtl/ibex_decoder.sv\n+++ b/rtl/ibex_decoder.sv\n@@ -3,11 +3,6 @@\n // Licensed under the Apache License, Version 2.0, see LICENSE for details.\n // SPDX-License-Identifier: Apache-2.0\n \n-// Source/Destination register instruction index\n-`define REG_S1 19:15\n-`define REG_S2 24:20\n-`define REG_S3 31:27\n-`define REG_D 11:07\n \n /**\n * Instruction decoder\n@@ -111,6 +106,11 @@ module ibex_decoder #(\n \n logic [31:0] instr;\n logic [31:0] instr_alu;\n+ // Source/Destination register instruction index\n+ logic [4:0] instr_rs1;\n+ logic [4:0] instr_rs2;\n+ logic [4:0] instr_rs3;\n+ logic [4:0] instr_rd;\n \n logic use_rs3;\n \n@@ -137,14 +137,18 @@ module ibex_decoder #(\n assign imm_j_type_o = { {12{instr[31]}}, instr[19:12], instr[20], instr[30:21], 1'b0 };\n \n // immediate for CSR manipulation (zero extended)\n- assign zimm_rs1_type_o = { 27'b0, instr[`REG_S1] }; // rs1\n+ assign zimm_rs1_type_o = { 27'b0, instr_rs1 }; // rs1\n \n // source registers\n- assign rf_raddr_a_o = use_rs3 ? instr[`REG_S3] : instr[`REG_S1]; // rs3 / rs1\n- assign rf_raddr_b_o = instr[`REG_S2]; // rs2\n+ assign instr_rs1 = instr[19:15];\n+ assign instr_rs2 = instr[24:20];\n+ assign instr_rs3 = instr[31:27];\n+ assign rf_raddr_a_o = use_rs3 ? instr_rs3 : instr_rs1; // rs3 / rs1\n+ assign rf_raddr_b_o = instr_rs2; // rs2\n \n // destination register\n- assign rf_waddr_o = instr[`REG_D]; // rd\n+ assign instr_rd = instr[11:7];\n+ assign rf_waddr_o = instr_rd; // rd\n \n ////////////////////\n // Register check //\n@@ -166,7 +170,7 @@ module ibex_decoder #(\n // CSRRSI/CSRRCI must not write 0 to CSRs (uimm[4:0]=='0)\n // CSRRS/CSRRC must not write from x0 to CSRs (rs1=='0)\n if ((csr_op == CSR_OP_SET || csr_op == CSR_OP_CLEAR) &&\n- instr[`REG_S1] == '0) begin\n+ instr_rs1 == '0) begin\n csr_op_o = CSR_OP_READ;\n end\n end\n@@ -555,7 +559,7 @@ module ibex_decoder #(\n endcase\n \n // rs1 and rd must be 0\n- if (instr[`REG_S1] != 5'b0 || instr[`REG_D] != 5'b0) begin\n+ if (instr_rs1 != 5'b0 || instr_rd != 5'b0) begin\n illegal_insn = 1'b1;\n end\n end else begin\n", "test_patch": "", "modified_files": ["rtl/ibex_decoder.sv"], "lines_added": 15, "lines_removed": 11} +{"repo": "lowRISC/ibex", "pr_id": 905, "lang": "sv", "rtl_files": ["rtl/ibex_icache.sv"], "commit_id": "8b42024cd5ce5f76a0589a6143917d19fe9dd3d2", "timestamp": "2020-05-27T10:38:34+00:00", "pr_title": "Optimize use of RAM primitive in icache", "pr_body": "The RAM primitive provides a way to specify the granularity of the write\nmask (wmask) signal, which can be used to select an appropriate\nimplementation (e.g. a SRAM with only byte selects, or no subselects at\nall).\n\n---\nEven though this change should be safe, I've seen X asserts fire on this one previously in icache UVM DV. I cannot test right now until #904 is fixed.", "issue_title": "Failing UVM sanity with commit \"[rtl] Add speculative branch signal\"", "issue_body": "Commit 12b39476c0c6bb16dc0d43057730f263836dac95 (`[rtl] Add speculative branch signal`) broke the UVM sanity tests.\r\n\r\nRunning `./vendor/lowrisc_ip/dvsim/dvsim.py dv/uvm/icache/dv/ibex_icache_sim_cfg.hjson -t vcs --waves` I get:\r\n\r\n## List of Failures\r\n\r\n**TEST:** ibex_icache_sanity, **SEED:** 3278749286
\r\n**LOG:** $scratch_path/0.ibex_icache_sanity/out/run.log
\r\n```\r\nUVM_FATAL @ 189350 ps: (ibex_icache_mem_resp_seq.sv:113) uvm_test_top.env.mem_agent.sequencer [uvm_test_top.env.virtual_sequencer.ibex_icache_sanity_vseq.mem_seq] Check failed (i < N) No pending grant for address 0xxxxxxxxX (1 items in queue). \r\nUVM_INFO @ 189350 ps: (uvm_report_server.svh:894) [UVM/REPORT/SERVER] \r\n--- UVM Report Summary ---\r\n\r\nQuit count : 0 of 1\r\n```\r\n\r\n**TEST:** ibex_icache_passthru, **SEED:** 1046335328
\r\n**LOG:** $scratch_path/0.ibex_icache_passthru/out/run.log
\r\n```\r\nUVM_FATAL @ 688601 ps: (ibex_icache_mem_resp_seq.sv:113) uvm_test_top.env.mem_agent.sequencer [uvm_test_top.env.virtual_sequencer.ibex_icache_passthru_vseq.mem_seq] Check failed (i < N) No pending grant for address 0xxxxxxxxX (1 items in queue). \r\nUVM_INFO @ 688601 ps: (uvm_report_server.svh:894) [UVM/REPORT/SERVER] \r\n--- UVM Report Summary ---\r\n\r\nQuit count : 0 of 1\r\n```\r\n\r\n@tomroberts-lowrisc @rswarbrick ", "commit_message": "Optimize use of RAM primitive in icache\n\nThe RAM primitive provides a way to specify the granularity of the write\nmask (wmask) signal, which can be used to select an appropriate\nimplementation (e.g. a SRAM with only byte selects, or no subselects at\nall).", "fix_patch": "diff --git a/rtl/ibex_icache.sv b/rtl/ibex_icache.sv\nindex 086b27ddaf..f65725becb 100644\n--- a/rtl/ibex_icache.sv\n+++ b/rtl/ibex_icache.sv\n@@ -301,8 +301,9 @@ module ibex_icache #(\n for (genvar way = 0; way < NumWays; way++) begin : gen_rams\n // Tag RAM instantiation\n prim_ram_1p #(\n- .Width (TAG_SIZE_ECC),\n- .Depth (NUM_LINES)\n+ .Width (TAG_SIZE_ECC),\n+ .Depth (NUM_LINES),\n+ .DataBitsPerMask (TAG_SIZE_ECC)\n ) tag_bank (\n .clk_i (clk_i),\n .req_i (tag_req_ic0 & tag_banks_ic0[way]),\n@@ -314,8 +315,9 @@ module ibex_icache #(\n );\n // Data RAM instantiation\n prim_ram_1p #(\n- .Width (LINE_SIZE_ECC),\n- .Depth (NUM_LINES)\n+ .Width (LINE_SIZE_ECC),\n+ .Depth (NUM_LINES),\n+ .DataBitsPerMask (LINE_SIZE_ECC)\n ) data_bank (\n .clk_i (clk_i),\n .req_i (data_req_ic0 & data_banks_ic0[way]),\n", "test_patch": "", "modified_files": ["rtl/ibex_icache.sv"], "lines_added": 6, "lines_removed": 4} +{"repo": "lowRISC/ibex", "pr_id": 903, "lang": "sv", "rtl_files": ["rtl/ibex_pmp.sv"], "commit_id": "4b01580a7bd88d5293aba786bce1724536a823fa", "timestamp": "2020-06-02T12:41:04+00:00", "pr_title": "[rtl] Fix PMP NA4 address matching", "pr_body": "- Apply address masking to the bottom address bit for NA4 as well as\r\n NAPOT\r\n- Relates to #902\r\n\r\nSigned-off-by: Tom Roberts ", "issue_title": "Incorrect pmp NA4/NAPOT address matching", "issue_body": "#875 seems to have introduced an issue with `NA4/NAPOT` address matching modes - the scenario is as follows.\r\n\r\nIn my test, `csr_pmp_addr[3]` is `0x8000_3f54` with its corresponding configuration bits `csr_pmp_cfg[3]` set to `{0, PMP_MODE_NA4, 0, 1, 1}`, and the core requests an instruction fetch from `pmp_req_addr_i[0] = 0x8000_3f54`. Note that since we are using NA4 mode, `region_start_addr[3] = 0x8000_3f54` and `region_addr_mask[3] = 0xffff_ffff`. We are also using a granularity of 0.\r\n\r\nWith this setup, we should expect that the requested instruction fetch should match `pmpaddr3` but then then fail due to a fetch error since the corresponding access bit is disabled.\r\n\r\nHowever, `region_match_low[0][3]` goes high as expected since\r\n`pmp_req_addr_i[0][33:2] >= region_start_addr[3][33:2]`,\r\nbut `region_match_high[0][3]` stays low since the check\r\n`pmp_req_addr_i[0][33:2] < csr_pmp_addr[3][33:2]` will fail due to lack of equality checking - this causes an altogether mismatch with this PMP region.\r\n\r\nI think we still need to include equality checking to cover NA4 and NAPOT matching (as the error I describe above can also easily occur in NAPOT mode with any granularity), but these equality checks should only be enabled when we are in one of those two modes.", "commit_message": "[rtl] Fix PMP NA4 address matching\n\n- Split out address matching into less than, greater than and equals to\n correctly match NAPOT, NA4 and TOR modes.\n- Relates to #902\n\nSigned-off-by: Tom Roberts ", "fix_patch": "diff --git a/rtl/ibex_pmp.sv b/rtl/ibex_pmp.sv\nindex 63f84c13ad..1b48693a0a 100644\n--- a/rtl/ibex_pmp.sv\n+++ b/rtl/ibex_pmp.sv\n@@ -32,9 +32,10 @@ module ibex_pmp #(\n // Access Checking Signals\n logic [33:0] region_start_addr [PMPNumRegions];\n logic [33:PMPGranularity+2] region_addr_mask [PMPNumRegions];\n- logic [PMPNumChan-1:0][PMPNumRegions-1:0] region_match_high;\n- logic [PMPNumChan-1:0][PMPNumRegions-1:0] region_match_low;\n- logic [PMPNumChan-1:0][PMPNumRegions-1:0] region_match_both;\n+ logic [PMPNumChan-1:0][PMPNumRegions-1:0] region_match_gt;\n+ logic [PMPNumChan-1:0][PMPNumRegions-1:0] region_match_lt;\n+ logic [PMPNumChan-1:0][PMPNumRegions-1:0] region_match_eq;\n+ logic [PMPNumChan-1:0][PMPNumRegions-1:0] region_match_all;\n logic [PMPNumChan-1:0][PMPNumRegions-1:0] region_perm_check;\n logic [PMPNumChan-1:0] access_fault;\n \n@@ -71,16 +72,30 @@ module ibex_pmp #(\n \n for (genvar c = 0; c < PMPNumChan; c++) begin : g_access_check\n for (genvar r = 0; r < PMPNumRegions; r++) begin : g_regions\n- // TOR Region high/low matching is reused for all match types\n // Comparators are sized according to granularity\n- assign region_match_low[c][r] = pmp_req_addr_i[c][33:PMPGranularity+2] >=\n- (region_start_addr[r][33:PMPGranularity+2] &\n- region_addr_mask[r]);\n- assign region_match_high[c][r] = (pmp_req_addr_i[c][33:PMPGranularity+2] &\n- region_addr_mask[r]) <\n- csr_pmp_addr_i[r][33:PMPGranularity+2];\n- assign region_match_both[c][r] = region_match_low[c][r] & region_match_high[c][r] &\n- (csr_pmp_cfg_i[r].mode != PMP_MODE_OFF);\n+ assign region_match_eq[c][r] = (pmp_req_addr_i[c][33:PMPGranularity+2] &\n+ region_addr_mask[r]) ==\n+ (region_start_addr[r][33:PMPGranularity+2] &\n+ region_addr_mask[r]);\n+ assign region_match_gt[c][r] = pmp_req_addr_i[c][33:PMPGranularity+2] >\n+ region_start_addr[r][33:PMPGranularity+2];\n+ assign region_match_lt[c][r] = pmp_req_addr_i[c][33:PMPGranularity+2] <\n+ csr_pmp_addr_i[r][33:PMPGranularity+2];\n+\n+ always_comb begin\n+ region_match_all[c][r] = 1'b0;\n+ unique case (csr_pmp_cfg_i[r].mode)\n+ PMP_MODE_OFF : region_match_all[c][r] = 1'b0;\n+ PMP_MODE_NA4 : region_match_all[c][r] = region_match_eq[c][r];\n+ PMP_MODE_NAPOT : region_match_all[c][r] = region_match_eq[c][r];\n+ PMP_MODE_TOR : begin\n+ region_match_all[c][r] = (region_match_eq[c][r] | region_match_gt[c][r]) &\n+ region_match_lt[c][r];\n+ end\n+ default : region_match_all[c][r] = 1'b0;\n+ endcase\n+ end\n+\n // Check specific required permissions\n assign region_perm_check[c][r] =\n ((pmp_req_type_i[c] == PMP_ACC_EXEC) & csr_pmp_cfg_i[r].exec) |\n@@ -96,7 +111,7 @@ module ibex_pmp #(\n // PMP entries are statically prioritized, from 0 to N-1\n // The lowest-numbered PMP entry which matches an address determines accessability\n for (int r = PMPNumRegions-1; r >= 0; r--) begin\n- if (region_match_both[c][r]) begin\n+ if (region_match_all[c][r]) begin\n access_fault[c] = (priv_mode_i[c] == PRIV_LVL_M) ?\n // For M-mode, any region which matches with the L-bit clear, or with sufficient\n // access permissions will be allowed\n", "test_patch": "", "modified_files": ["rtl/ibex_pmp.sv"], "lines_added": 28, "lines_removed": 13} +{"repo": "lowRISC/ibex", "pr_id": 855, "lang": "sv", "rtl_files": ["dv/uvm/icache/dv/ibex_icache_core_agent/ibex_icache_core_driver.sv"], "commit_id": "863fb56eb166dc8d6e25f4e98b7319f0c7088564", "timestamp": "2020-05-11T15:28:49+00:00", "pr_title": "Always assert ready in core driver for ICache UVM testbench", "pr_body": "This works around a bug tracked in issue #850.", "issue_title": "ICache <-> core valid signal depends on ready", "issue_body": "As it currently stands, the documentation (that I wrote) suggests this shouldn't be the case. We either need to fix the documentation or change the code.", "commit_message": "Always assert ready in core driver for ICache UVM testbench\n\nThis works around a bug tracked in issue #850.", "fix_patch": "diff --git a/dv/uvm/icache/dv/ibex_icache_core_agent/ibex_icache_core_driver.sv b/dv/uvm/icache/dv/ibex_icache_core_agent/ibex_icache_core_driver.sv\nindex 87474e2488..d6e0d8ea19 100644\n--- a/dv/uvm/icache/dv/ibex_icache_core_agent/ibex_icache_core_driver.sv\n+++ b/dv/uvm/icache/dv/ibex_icache_core_agent/ibex_icache_core_driver.sv\n@@ -112,9 +112,15 @@ class ibex_icache_core_driver\n virtual task automatic read_insn();\n int unsigned delay;\n \n- // Maybe (1 time in 10) wait for a valid signal before even considering asserting ready.\n- if ($urandom_range(9) == 0)\n- wait (cfg.vif.driver_cb.valid);\n+ // TODO: The icache sometimes currently requires the ready signal before it asserts valid. This\n+ // is tracked by issue #850.\n+ if (0) begin\n+\n+ // Maybe (1 time in 10) wait for a valid signal before even considering asserting ready.\n+ if ($urandom_range(9) == 0)\n+ wait (cfg.vif.driver_cb.valid);\n+\n+ end\n \n // Then pick how long we wait before asserting that we are ready.\n //\n", "test_patch": "", "modified_files": ["dv/uvm/icache/dv/ibex_icache_core_agent/ibex_icache_core_driver.sv"], "lines_added": 9, "lines_removed": 3} +{"repo": "lowRISC/ibex", "pr_id": 854, "lang": "sv", "rtl_files": ["rtl/ibex_controller.sv"], "commit_id": "863fb56eb166dc8d6e25f4e98b7319f0c7088564", "timestamp": "2020-05-15T10:13:21+00:00", "pr_title": "[rtl] Fix instr_valid_i exception issue", "pr_body": "- The controller state machine could only progress to FLUSH to handle an\r\n exception if instr_valid_i was set\r\n- When the exception comes from a load/store in the Writeback stage, and\r\n no new instruction has been driven into the ID stage, this could cause\r\n exception to be missed\r\n- The instr_valid_i qualification is therefore removed from the state\r\n machine as all relevant signals inside that if block are already\r\n qualified by instr_valid_i anyway\r\n- Fixes #849\r\n\r\nSigned-off-by: Tom Roberts ", "issue_title": "PMP store fault does not jump to exception handler", "issue_body": "Hi Tom,\r\nI ran into this situation when debugging a PMP test (with icache disabled):\r\n![Screenshot from 2020-05-07 15-46-15](https://user-images.githubusercontent.com/16736281/81351754-e4a9d780-9079-11ea-87de-f571cd0a8829.png)\r\nThe instruction at `PC=0x8001fb0a` (under the cursor) is a store instruction to address `0x80031034`, which the PMP detection logic correctly flags as an error for not matching any pmp_cfg CSR in user-mode and prevents a request from being sent to the memory.\r\nDuring this, the controller is in the `DECODE` state, but it does not actually detect `special_req_all` going high because `instr_valid_i` has already gone low by the time it reflects the rising `exc_req_lsu` wire - as a result the core pretends everything is okay and goes on to execute the instruction at the next PC.\r\nI suspect this has to do with how `instr_valid_id_d/q` are set in the IF stage, as they appear to be dropping one cycle too early - additionally, when I enabled the icache and reran this test, this issue did not appear, e.g. `instr_valid_i` in the controller went high at the same time as `special_req_all` to qualify it due to `instr_valid_id_d/q` staying high for an additional cycle:\r\n![Screenshot from 2020-05-07 16-10-02](https://user-images.githubusercontent.com/16736281/81353183-428bee80-907d-11ea-8a52-a78fe0a96360.png)\r\nWe can see that with the icache, `instr_valid_id_d/q` stay high for extra cycles, allowing the controller to correctly qualify the PMP exception and then start fetching the address of the exception handler (`0x80001400`).", "commit_message": "[rtl] Fix instr_valid_i exception issue\n\n- The controller state machine could only progress to FLUSH to handle an\n exception if instr_valid_i was set\n- When the exception comes from a load/store in the Writeback stage, and\n no new instruction has been driven into the ID stage, this could cause\n exception to be missed\n- The instr_valid_i qualification is therefore removed from the state\n machine as all relevant signals inside that if block are already\n qualified by instr_valid_i anyway\n- Fixes #849\n\nSigned-off-by: Tom Roberts ", "fix_patch": "diff --git a/rtl/ibex_controller.sv b/rtl/ibex_controller.sv\nindex a256a33a34..f73dc2004b 100644\n--- a/rtl/ibex_controller.sv\n+++ b/rtl/ibex_controller.sv\n@@ -182,12 +182,14 @@ module ibex_controller #(\n // it is needed to break the path from ibex_cs_registers/illegal_csr_insn_o\n // to pc_set_o. Clear when controller is in FLUSH so it won't remain set\n // once illegal instruction is handled.\n+ // All terms in this expression are qualified by instr_valid_i\n assign illegal_insn_d = (illegal_insn_i | illegal_dret | illegal_umode) & (ctrl_fsm_cs != FLUSH);\n \n // exception requests\n // requests are flopped in exc_req_q. This is cleared when controller is in\n // the FLUSH state so the cycle following exc_req_q won't remain set for an\n // exception request that has just been handled.\n+ // All terms in this expression are qualified by instr_valid_i\n assign exc_req_d = (ecall_insn | ebrk_insn | illegal_insn_d | instr_fetch_err) &\n (ctrl_fsm_cs != FLUSH);\n \n@@ -205,10 +207,13 @@ module ibex_controller #(\n // request reasons that are relevant to a branch.\n \n // generic special request signal, applies to all instructions\n+ // All terms in this expression are qualified by instr_valid_i except exc_req_lsu which can come\n+ // from the Writeback stage with no instr_valid_i from the ID stage\n assign special_req_all = mret_insn | dret_insn | wfi_insn | csr_pipe_flush |\n exc_req_d | exc_req_lsu;\n \n // special request that can specifically occur during branch instructions\n+ // All terms in this expression are qualified by instr_valid_i\n assign special_req_branch = instr_fetch_err & (ctrl_fsm_cs != FLUSH);\n \n `ASSERT(SpecialReqBranchGivesSpecialReqAll,\n@@ -399,31 +404,29 @@ module ibex_controller #(\n // which helps timing.\n pc_mux_o = PC_JUMP;\n \n- if (instr_valid_i) begin\n \n- // get ready for special instructions, exceptions, pipeline flushes\n- if (special_req_all) begin\n- // Halt IF but don't flush ID. This leaves a valid instruction in\n- // ID so controller can determine appropriate action in the\n- // FLUSH state.\n- ctrl_fsm_ns = FLUSH;\n- halt_if = 1'b1;\n- end\n+ // Get ready for special instructions, exceptions, pipeline flushes\n+ if (special_req_all) begin\n+ // Halt IF but don't flush ID. This leaves a valid instruction in\n+ // ID so controller can determine appropriate action in the\n+ // FLUSH state.\n+ ctrl_fsm_ns = FLUSH;\n+ halt_if = 1'b1;\n+ end\n \n- if ((branch_set_i || jump_set_i) && ~special_req_branch) begin\n- pc_set_o = 1'b1;\n+ if ((branch_set_i || jump_set_i) && ~special_req_branch) begin\n+ pc_set_o = 1'b1;\n \n- perf_tbranch_o = branch_set_i;\n- perf_jump_o = jump_set_i;\n- end\n+ perf_tbranch_o = branch_set_i;\n+ perf_jump_o = jump_set_i;\n+ end\n \n- // If entering debug mode or handling an IRQ the core needs to wait\n- // until the current instruction has finished executing. Stall IF\n- // during that time.\n- if ((enter_debug_mode || handle_irq) && stall) begin\n- halt_if = 1'b1;\n- end\n- end // instr_valid_i\n+ // If entering debug mode or handling an IRQ the core needs to wait\n+ // until the current instruction has finished executing. Stall IF\n+ // during that time.\n+ if ((enter_debug_mode || handle_irq) && stall) begin\n+ halt_if = 1'b1;\n+ end\n \n if (!stall && !special_req_all) begin\n if (enter_debug_mode) begin\n", "test_patch": "", "modified_files": ["rtl/ibex_controller.sv"], "lines_added": 24, "lines_removed": 21} +{"repo": "lowRISC/ibex", "pr_id": 836, "lang": "sv", "rtl_files": ["rtl/ibex_id_stage.sv"], "commit_id": "439513ba68b57ace4e08365da7297caa215e9cf5", "timestamp": "2020-05-04T07:29:00+00:00", "pr_title": "[rtl] Fix jump signal stuck high during stall", "pr_body": "- Stalls due to preceding memory accesses in the WB stage shouldn't\r\n cause the jump signal to remain high.\r\n- The jump signal being stuck high causes repeated memory accesses to\r\n the same address, and unnecessary stalling.\r\n- Fixes lowRISC/opentitan#2099\r\n\r\nSigned-off-by: Tom Roberts ", "issue_title": "[dv] Improve instruction trace around faulting instructions", "issue_body": "When an executed instruction generates a fault we suppress its destination register write. On the RVFI interface this mean setting the write register index to 0. On the instruction trace this results in seeing `x0` as the destination register, rather than the actual destination register. This can be confusing. We should improve our trace output to include the actual destination register in the printed instruction along with a note the write is suppressed due to a trap.\r\n\r\nSee https://github.com/lowRISC/opentitan/issues/13134 for an example of this issue.", "commit_message": "[rtl] Fix jump signal stuck high during stall\n\n- Stalls due to preceding memory accesses in the WB stage shouldn't\n cause the jump signal to remain high.\n- The jump signal being stuck high causes repeated memory accesses to\n the same address, and unnecessary stalling.\n- Fixes lowRISC/opentitan#2099\n\nSigned-off-by: Tom Roberts ", "fix_patch": "diff --git a/rtl/ibex_id_stage.sv b/rtl/ibex_id_stage.sv\nindex 57ba30678e..5055859dc3 100644\n--- a/rtl/ibex_id_stage.sv\n+++ b/rtl/ibex_id_stage.sv\n@@ -192,6 +192,7 @@ module ibex_id_stage #(\n logic branch_set, branch_set_d;\n logic branch_taken;\n logic jump_in_dec;\n+ logic jump_set_dec;\n logic jump_set;\n \n logic instr_first_cycle;\n@@ -400,7 +401,7 @@ module ibex_id_stage #(\n .dret_insn_o ( dret_insn_dec ),\n .ecall_insn_o ( ecall_insn_dec ),\n .wfi_insn_o ( wfi_insn_dec ),\n- .jump_set_o ( jump_set ),\n+ .jump_set_o ( jump_set_dec ),\n .branch_taken_i ( branch_taken ),\n .icache_inval_o ( icache_inval_o ),\n \n@@ -663,6 +664,7 @@ module ibex_id_stage #(\n // could generate needless prefetch buffer flushes and instruction fetches. ID/EX is designed such\n // that this shouldn't ever happen.\n `ASSERT(NeverDoubleBranch, branch_set |=> ~branch_set)\n+ `ASSERT(NeverDoubleJump, jump_set |=> ~jump_set)\n \n ///////////////\n // ID-EX FSM //\n@@ -692,6 +694,7 @@ module ibex_id_stage #(\n stall_branch = 1'b0;\n stall_alu = 1'b0;\n branch_set_d = 1'b0;\n+ jump_set = 1'b0;\n perf_branch_o = 1'b0;\n \n if (instr_executing) begin\n@@ -733,6 +736,7 @@ module ibex_id_stage #(\n // BTALU means jumps only need one cycle\n id_fsm_d = BranchTargetALU ? FIRST_CYCLE : MULTI_CYCLE;\n stall_jump = ~BranchTargetALU;\n+ jump_set = jump_set_dec;\n end\n alu_multicycle_dec: begin\n stall_alu = 1'b1;\n", "test_patch": "", "modified_files": ["rtl/ibex_id_stage.sv"], "lines_added": 5, "lines_removed": 1} +{"repo": "lowRISC/ibex", "pr_id": 835, "lang": "sv", "rtl_files": ["rtl/ibex_load_store_unit.sv"], "commit_id": "5bcacb876d19c47e1b1461c6fd5b7d568485636b", "timestamp": "2020-05-05T08:26:57+00:00", "pr_title": "[rtl] Stop regfile writeback for load errors", "pr_body": "- A data or PMP error should stop the register file from being updated\r\n- Fixes #832\r\n\r\nSigned-off-by: Tom Roberts ", "issue_title": "PMP load error qualifies register writeback", "issue_body": "Hi,\r\nI encountered this situation when running some pmp tests on Ibex:\r\n![Screenshot from 2020-04-30 16-52-47](https://user-images.githubusercontent.com/16736281/80769870-68584700-8b03-11ea-8f60-089f23606a27.png)\r\nThe instruction at `PC=0x80002250` is an `lb` instruction that tries to access the address `0x800148e4`. One cycle after this instruction reaches the decode stage, it causes a PMP fault and `pmp_err_q` goes high for two cycles, but `lsu_rdata_valid_o` still goes high to `1'b1` even though the DMEM interface has not sent out a request at all, triggering an incorrect register writeback of of `XXXX_XXXX`.", "commit_message": "[rtl] Stop regfile writeback for load errors\n\n- A data or PMP error should stop the register file from being updated\n- Fixes #832\n\nSigned-off-by: Tom Roberts ", "fix_patch": "diff --git a/rtl/ibex_load_store_unit.sv b/rtl/ibex_load_store_unit.sv\nindex ec69a3a033..219dba5b7c 100644\n--- a/rtl/ibex_load_store_unit.sv\n+++ b/rtl/ibex_load_store_unit.sv\n@@ -476,7 +476,7 @@ module ibex_load_store_unit\n \n assign data_or_pmp_err = lsu_err_q | data_err_i | pmp_err_q;\n assign lsu_resp_valid_o = (data_rvalid_i | pmp_err_q) & (ls_fsm_cs == IDLE);\n- assign lsu_rdata_valid_o = lsu_resp_valid_o & ~data_we_q;\n+ assign lsu_rdata_valid_o = (ls_fsm_cs == IDLE) & data_rvalid_i & ~data_or_pmp_err & ~data_we_q;\n \n // output to register file\n assign lsu_rdata_o = data_rdata_ext;\n", "test_patch": "", "modified_files": ["rtl/ibex_load_store_unit.sv"], "lines_added": 1, "lines_removed": 1} +{"repo": "lowRISC/ibex", "pr_id": 813, "lang": "sv", "rtl_files": ["rtl/ibex_load_store_unit.sv"], "commit_id": "dcf18d86c3db4b7a3a5bb1f670ad74400dc77042", "timestamp": "2020-04-24T08:06:06+00:00", "pr_title": "[rtl/lsu] Fix bug in pmp error clearing", "pr_body": "- pmp_err_q needs to clear once the LSU state machine returns to idle,\r\n otherwise it will remain set indefinely.\r\n- Relates to #808\r\n\r\nSigned-off-by: Tom Roberts ", "issue_title": "SpecialReqAllGivesSpecialReqBranchIfBranchInst assertion failure", "issue_body": "Hi all,\r\nWhen running the `riscv_mmu_stress_test` with PMP regions enabled, I noticed that the `SpecialReqAllGivesSpecialReqBranchIfBranchInst` assertion was failing, shown below:\r\n![Screenshot from 2020-04-22 17-58-58](https://user-images.githubusercontent.com/16736281/80048119-20627000-84c4-11ea-8781-ff35e9498e63.png)\r\nA snippet of the OVPsim log of the relevant instruction execution is shown below:\r\n![Screenshot from 2020-04-22 17-58-47](https://user-images.githubusercontent.com/16736281/80048168-3d973e80-84c4-11ea-8d90-7ed850287d89.png)\r\nA waveform snippet of when the assertion fails is below, the failure occurs one cycle after the yellow marker, where the small red arrow is located:\r\n![Screenshot from 2020-04-22 17-59-14](https://user-images.githubusercontent.com/16736281/80048242-76371800-84c4-11ea-89f7-915839915d95.png)\r\nThe situation is as follows: the `sb` instruction at `PC=0x80005496` (at the green `M1` marker accesses memory at `0xffa839bc` from User-mode and this access correctly causes a PMP store address exception (all 16 regions are enabled and set to `TOR` mode, the address being accessed here is not contained within any of the enabled regions). The core then jumps to the PC stored in `mtvec`, which is a jump instruction at `PC=0x80001400`.\r\nHowever, one cycle after starting to execute this jump, the previously mentioned assertion fails, as even though `special_req_all` and `jump_set_i` are both high due to the PMP store exception and the resultant branch, the `special_req_branch` signal does not go high at all.", "commit_message": "[rtl/lsu] Fix bug in pmp error clearing\n\n- pmp_err_q needs to clear once the LSU state machine returns to idle,\n otherwise it will remain set indefinely.\n- Relates to #808\n\nSigned-off-by: Tom Roberts ", "fix_patch": "diff --git a/rtl/ibex_load_store_unit.sv b/rtl/ibex_load_store_unit.sv\nindex 689297b8f0..ec69a3a033 100644\n--- a/rtl/ibex_load_store_unit.sv\n+++ b/rtl/ibex_load_store_unit.sv\n@@ -352,6 +352,7 @@ module ibex_load_store_unit\n unique case (ls_fsm_cs)\n \n IDLE: begin\n+ pmp_err_d = 1'b0;\n if (lsu_req_i) begin\n data_req_o = 1'b1;\n pmp_err_d = data_pmp_err_i;\n", "test_patch": "", "modified_files": ["rtl/ibex_load_store_unit.sv"], "lines_added": 1, "lines_removed": 0} +{"repo": "lowRISC/ibex", "pr_id": 699, "lang": "sv", "rtl_files": ["shared/rtl/prim_assert.sv"], "commit_id": "39ce39e33241833b4e5212e8e65f4ee99d48a49e", "timestamp": "2020-03-13T10:47:42+00:00", "pr_title": "Remove property from assert message", "pr_body": "Assert macros in prim_assert.sv report the asserted property as part of\nthe error message if the assertion fails. Doing that requires us to\nstringify the property. If the property is multi-line in the source\ncode, this produces a multi-line string. According to the\nSystemVerilog standard, a multi-line string requires a backslash (`\\`)\nat the end of a line. Adding this backslash through a macro is not\npossible (at least to my knowledge), giving us no way to produce a\nstandards-compliant implementation of the `ASSERT` macros that report\nthe property as string.\n\nThis commit therefore removes the property from the error message if an\nassertion fails. It makes these messages less useful, but the\ninformation can still be recovered in a less convenient way through the\nname of the assertion, and the file and line numbers.\n\nFixes #669", "issue_title": "Questa complains about newlines in ASSERT macros", "issue_body": "(Spin-off from #622 by @danghai)\r\n\r\nCompiling Ibex with Questa gives the following warning:\r\n\r\n```\r\n** Warning: ** while parsing macro expansion: 'ASSERT' starting at /home/danghai/hhoangda/ibex/rtl/ibex_compressed_decoder.sv(286)\r\n** at /home/danghai/hhoangda/ibex/rtl/ibex_compressed_decoder.sv(286): (vlog-2643) Unterminated string literal continues onto next line.\r\n```\r\n\r\nThe code in question is\r\n\r\n```verilog\r\n// in ibex_compressed_decoder.sv\r\n `ASSERT(IbexInstrLSBsKnown, valid_i |->\r\n !$isunknown(instr_i[1:0]))\r\n\r\n// in prim_assert.sv\r\n`define ASSERT(__name, __prop, __clk = `ASSERT_DEFAULT_CLK, __rst = `ASSERT_DEFAULT_RST) \\\r\n`ifdef INC_ASSERT \\\r\n __name: assert property (@(posedge __clk) disable iff (__rst !== '0) (__prop)) \\\r\n else `ASSERT_RPT(`PRIM_STRINGIFY(__name), `PRIM_STRINGIFY(__prop)) \\\r\n`endif\r\n\r\n// Converts an arbitrary block of code into a Verilog string\r\n`define PRIM_STRINGIFY(__x) `\"__x`\"\r\n\r\n`define ASSERT_RPT(__name, __msg) \\\r\n`ifdef UVM \\\r\n assert_rpt_pkg::assert_rpt($sformatf(\"[%m] %s: %s (%s:%0d)\", \\\r\n __name, __msg, `__FILE__, `__LINE__)); \\\r\n`else \\\r\n $error(\"[ASSERT FAILED] [%m] %s: %s\", __name, __msg); \\\r\n`endif\r\n\r\n```\r\n\r\nGiven this code, I'm assuming the error message actually comes from the fact that `prop` (the second argument to `ASSERT`) is converted to a string before being used in `ASSERT_RPT`, and this use of `prop` with newlines isn't liked by Questa.\r\n\r\nAccording to SV2017, the definition of a string literal is \r\n\r\n![image](https://user-images.githubusercontent.com/1467123/76232809-2a375900-621f-11ea-9b3e-19b839f6469f.png)\r\n\r\nWhich indicates our code is actually wrong. I see a couple of options:\r\n- Remove the reporting of the property in `ASSERT_RPT`, and only report the message.\r\n- Add backslashes to the end-of-line of each multi-line property. I'm not sure if that's actually valid for the non-string case?\r\n- Avoid newlines in properties when writing `ASSERT` macros.\r\n\r\n\r\n@danghai:\r\n- First, let's check if the hypothesis holds: Does the warning go away if you remove the `ASSERT_RPT()` call from the definition of the `ASSERT` macro?\r\n- Can you try to add a backslash at the end of the property in `ibex_compressed_decoder.sv`, e.g. \r\n\r\n ```systemverilog\r\n `ASSERT(IbexInstrLSBsKnown, valid_i |-> \\\r\n !$isunknown(instr_i[1:0]))\r\n ```\r\n\r\n\r\nQuesta version info: QuestaSim-64 qrun 2019.4 Utility 2019.10 Oct 15 2019\r\n\r\n\r\nCC @msfschaffner @sriyerg ", "commit_message": "Remove property from assert message\n\nAssert macros in prim_assert.sv report the asserted property as part of\nthe error message if the assertion fails. Doing that requires us to\nstringify the property. If the property is multi-line in the source\ncode, this produces a multi-line string. According to the\nSystemVerilog standard, a multi-line string requires a backslash (`\\`)\nat the end of a line. Adding this backslash through a macro is not\npossible (at least to my knowledge), giving us no way to produce a\nstandards-compliant implementation of the `ASSERT` macros that report\nthe property as string.\n\nThis commit therefore removes the property from the error message if an\nassertion fails. It makes these messages less useful, but the\ninformation can still be recovered in a less convenient way through the\nname of the assertion, and the file and line numbers. File and line\nnumber were missing from the non-UVM code path before, this commit adds\nthem there as well.\n\nFixes #669", "fix_patch": "diff --git a/shared/rtl/prim_assert.sv b/shared/rtl/prim_assert.sv\nindex f569292c09..1e536bf84e 100644\n--- a/shared/rtl/prim_assert.sv\n+++ b/shared/rtl/prim_assert.sv\n@@ -34,13 +34,13 @@\n // Converts an arbitrary block of code into a Verilog string\n `define PRIM_STRINGIFY(__x) `\"__x`\"\n \n- // ASSERT_RPT is available to change the reporting mechanism when an assert fails\n-`define ASSERT_RPT(__name, __msg) \\\n-`ifdef UVM \\\n- assert_rpt_pkg::assert_rpt($sformatf(\"[%m] %s: %s (%s:%0d)\", \\\n- __name, __msg, `__FILE__, `__LINE__)); \\\n-`else \\\n- $error(\"[ASSERT FAILED] [%m] %s: %s\", __name, __msg); \\\n+// ASSERT_RPT is available to change the reporting mechanism when an assert fails\n+`define ASSERT_RPT(__name) \\\n+`ifdef UVM \\\n+ assert_rpt_pkg::assert_rpt($sformatf(\"[%m] %s (%s:%0d)\", \\\n+ __name, `__FILE__, `__LINE__)); \\\n+`else \\\n+ $error(\"[ASSERT FAILED] [%m] %s (%s:%0d)\", __name, `__FILE__, `__LINE__); \\\n `endif\n \n ///////////////////////////////////////\n@@ -53,18 +53,18 @@\n \n // Immediate assertion\n // Note that immediate assertions are sensitive to simulation glitches.\n-`define ASSERT_I(__name, __prop) \\\n-`ifdef INC_ASSERT \\\n- __name: assert (__prop) \\\n- else `ASSERT_RPT(`PRIM_STRINGIFY(__name), `PRIM_STRINGIFY(__prop)) \\\n+`define ASSERT_I(__name, __prop) \\\n+`ifdef INC_ASSERT \\\n+ __name: assert (__prop) \\\n+ else `ASSERT_RPT(`PRIM_STRINGIFY(__name)) \\\n `endif\n \n // Assertion in initial block. Can be used for things like parameter checking.\n-`define ASSERT_INIT(__name, __prop) \\\n-`ifdef INC_ASSERT \\\n- initial \\\n- __name: assert (__prop) \\\n- else `ASSERT_RPT(`PRIM_STRINGIFY(__name), `PRIM_STRINGIFY(__prop)) \\\n+`define ASSERT_INIT(__name, __prop) \\\n+`ifdef INC_ASSERT \\\n+ initial \\\n+ __name: assert (__prop) \\\n+ else `ASSERT_RPT(`PRIM_STRINGIFY(__name)) \\\n `endif\n \n // Assertion in final block. Can be used for things like queues being empty\n@@ -74,15 +74,15 @@\n `ifdef INC_ASSERT \\\n final \\\n __name: assert (__prop || $test$plusargs(\"disable_assert_final_checks\")) \\\n- else `ASSERT_RPT(`PRIM_STRINGIFY(__name), `PRIM_STRINGIFY(__prop)) \\\n+ else `ASSERT_RPT(`PRIM_STRINGIFY(__name)) \\\n `endif\n \n // Assert a concurrent property directly.\n // It can be called as a module (or interface) body item.\n `define ASSERT(__name, __prop, __clk = `ASSERT_DEFAULT_CLK, __rst = `ASSERT_DEFAULT_RST) \\\n `ifdef INC_ASSERT \\\n- __name: assert property (@(posedge __clk) disable iff (__rst !== '0) (__prop)) \\\n- else `ASSERT_RPT(`PRIM_STRINGIFY(__name), `PRIM_STRINGIFY(__prop)) \\\n+ __name: assert property (@(posedge __clk) disable iff ((__rst) !== '0) (__prop)) \\\n+ else `ASSERT_RPT(`PRIM_STRINGIFY(__name)) \\\n `endif\n // Note: Above we use (__rst !== '0) in the disable iff statements instead of\n // (__rst == '1). This properly disables the assertion in cases when reset is X at\n@@ -92,8 +92,8 @@\n // Assert a concurrent property NEVER happens\n `define ASSERT_NEVER(__name, __prop, __clk = `ASSERT_DEFAULT_CLK, __rst = `ASSERT_DEFAULT_RST) \\\n `ifdef INC_ASSERT \\\n- __name: assert property (@(posedge __clk) disable iff (__rst !== '0) not (__prop)) \\\n- else `ASSERT_RPT(`PRIM_STRINGIFY(__name), `PRIM_STRINGIFY(__prop)) \\\n+ __name: assert property (@(posedge __clk) disable iff ((__rst) !== '0) not (__prop)) \\\n+ else `ASSERT_RPT(`PRIM_STRINGIFY(__name)) \\\n `endif\n \n // Assert that signal has a known value (each bit is either '0' or '1') after reset.\n@@ -106,7 +106,7 @@\n // Cover a concurrent property\n `define COVER(__name, __prop, __clk = `ASSERT_DEFAULT_CLK, __rst = `ASSERT_DEFAULT_RST) \\\n `ifdef INC_ASSERT \\\n- __name: cover property (@(posedge __clk) disable iff (__rst !== '0) (__prop)); \\\n+ __name: cover property (@(posedge __clk) disable iff ((__rst) !== '0) (__prop)); \\\n `endif\n \n //////////////////////////////\n@@ -141,15 +141,15 @@\n // Assume a concurrent property\n `define ASSUME(__name, __prop, __clk = `ASSERT_DEFAULT_CLK, __rst = `ASSERT_DEFAULT_RST) \\\n `ifdef INC_ASSERT \\\n- __name: assume property (@(posedge __clk) disable iff (__rst !== '0) (__prop)) \\\n- else begin `ASSERT_RPT(`PRIM_STRINGIFY(__name), `PRIM_STRINGIFY(__prop)) end \\\n+ __name: assume property (@(posedge __clk) disable iff ((__rst) !== '0) (__prop)) \\\n+ else `ASSERT_RPT(`PRIM_STRINGIFY(__name)) \\\n `endif\n \n // Assume an immediate property\n-`define ASSUME_I(__name, __prop) \\\n-`ifdef INC_ASSERT \\\n- __name: assume (__prop) \\\n- else `ASSERT_RPT(`PRIM_STRINGIFY(__name), `PRIM_STRINGIFY(__prop)) \\\n+`define ASSUME_I(__name, __prop) \\\n+`ifdef INC_ASSERT \\\n+ __name: assume (__prop) \\\n+ else `ASSERT_RPT(`PRIM_STRINGIFY(__name)) \\\n `endif\n \n //////////////////////////////////\n", "test_patch": "", "modified_files": ["shared/rtl/prim_assert.sv"], "lines_added": 28, "lines_removed": 28} +{"repo": "lowRISC/ibex", "pr_id": 693, "lang": "sv", "rtl_files": ["rtl/ibex_counters.sv"], "commit_id": "b6dfb7192718462388232f3714abcf8944e72241", "timestamp": "2020-03-13T10:34:14+00:00", "pr_title": "Use a syntax compatible with Verible", "pr_body": "Verible doesn't do real pre-processing currently, and fails to parse\ncode if define sections span across headers of blocks, as we did.\n\nUse another syntax instead for the one case where we did that to work\naround this limitation. The code isn't less readable as result, making\nthis an acceptable trade-off.\n\nWorks around https://github.com/google/verible/issues/228", "issue_title": "DV: Test writable mtvec", "issue_body": "With #118 landed mtvec is now writable. We need DV to test this, and to ensure that the documented constraints (256B-aligned, only vectorized) are obeyed when reading the value back.", "commit_message": "Use a syntax compatible with Verible\n\nVerible doesn't do real pre-processing currently, and fails to parse\ncode if define sections span across headers of blocks, as we did.\n\nUse another syntax instead for the one case where we did that to work\naround this limitation. The code isn't less readable as result, making\nthis an acceptable trade-off.\n\nWorks around https://github.com/google/verible/issues/228", "fix_patch": "diff --git a/rtl/ibex_counters.sv b/rtl/ibex_counters.sv\nindex 9a28b9a98a..2d9a4ef43d 100644\n--- a/rtl/ibex_counters.sv\n+++ b/rtl/ibex_counters.sv\n@@ -54,17 +54,17 @@ module ibex_counters #(\n // Set DSP pragma for supported xilinx FPGAs\n localparam dsp_pragma = CounterWidth < 49 ? \"yes\" : \"no\";\n (* use_dsp = dsp_pragma *) logic [CounterWidth-1:0] counter_q;\n+\n+ // DSP output register requires synchronous reset.\n+ `define COUNTER_FLOP_RST posedge clk_i\n `else\n logic [CounterWidth-1:0] counter_q;\n+\n+ `define COUNTER_FLOP_RST posedge clk_i or negedge rst_ni\n `endif\n \n // Counter flop\n-`ifdef FPGA_XILINX\n- // DSP output register requires synchronous reset.\n- always @(posedge clk_i) begin\n-`else\n- always @(posedge clk_i or negedge rst_ni) begin\n-`endif\n+ always @(`COUNTER_FLOP_RST) begin\n if (!rst_ni) begin\n counter_q <= '0;\n end else begin\n@@ -84,3 +84,6 @@ module ibex_counters #(\n end\n \n endmodule\n+\n+// Keep helper defines file-local.\n+`undef COUNTER_FLOP_RST\n", "test_patch": "", "modified_files": ["rtl/ibex_counters.sv"], "lines_added": 9, "lines_removed": 6} +{"repo": "lowRISC/ibex", "pr_id": 658, "lang": "sv", "rtl_files": ["rtl/ibex_id_stage.sv"], "commit_id": "88f1a7e38f03bd044453356a84ef803fb06541bf", "timestamp": "2020-03-05T16:09:18+00:00", "pr_title": "Remove stray semicolon", "pr_body": "This seems to cause lint errors with ncsim (see bug #650).", "issue_title": "unexpected semicolon in ibex_id_stage.sv", "issue_body": "Looks, like there is small typo [here](https://github.com/lowRISC/ibex/blob/cb9413e38bc43117a0a5dfd7221bbf8155815478/rtl/ibex_id_stage.sv#L687). \r\nWarning message:\r\n ncvlog: *W,UEXPSC (ibex/rtl/ibex_id_stage.sv,687|89): Ignored unexpected semicolon following SystemVerilog description keyword (endif).", "commit_message": "Remove stray semicolon\n\nThis seems to cause lint errors with ncsim (see bug #650).", "fix_patch": "diff --git a/rtl/ibex_id_stage.sv b/rtl/ibex_id_stage.sv\nindex c95f19d6f2..572ecaaaf0 100644\n--- a/rtl/ibex_id_stage.sv\n+++ b/rtl/ibex_id_stage.sv\n@@ -684,7 +684,7 @@ module ibex_id_stage #(\n // Duplicated instruction flops must match\n // === as DV environment can produce instructions with Xs in, so must use precise match that\n // includes Xs\n- `ASSERT(IbexDuplicateInstrMatch, instr_valid_i |-> instr_rdata_i === instr_rdata_alu_i);\n+ `ASSERT(IbexDuplicateInstrMatch, instr_valid_i |-> instr_rdata_i === instr_rdata_alu_i)\n \n `ifdef CHECK_MISALIGNED\n `ASSERT(IbexMisalignedMemoryAccess, !lsu_addr_incr_req_i)\n", "test_patch": "", "modified_files": ["rtl/ibex_id_stage.sv"], "lines_added": 1, "lines_removed": 1} +{"repo": "lowRISC/ibex", "pr_id": 640, "lang": "sv", "rtl_files": ["dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_slave_seq_lib.sv"], "commit_id": "cb9413e38bc43117a0a5dfd7221bbf8155815478", "timestamp": "2020-03-05T14:59:27+00:00", "pr_title": "Fix qrun compile warning", "pr_body": "Relate to #622 ", "issue_title": "Add support for Qrun Questa", "issue_body": "Hi, I make PR to support for qrun simulator. I try to run; however, I got a lot of warning for compilation, and optimization. I attach the output file. Could you help me take the look? I hope qrun can support for running `ibex`. Thank you\r\n[qrun_compile_optimize.log](https://github.com/lowRISC/ibex/files/4238391/qrun_compile_optimize.log)\r\n", "commit_message": "Fix qrun compile warning", "fix_patch": "diff --git a/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_slave_seq_lib.sv b/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_slave_seq_lib.sv\nindex 681332bfc7..7da6780a8f 100644\n--- a/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_slave_seq_lib.sv\n+++ b/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_slave_seq_lib.sv\n@@ -84,7 +84,7 @@ class ibex_mem_intf_slave_seq extends uvm_sequence #(ibex_mem_intf_seq_item);\n end\n endtask : body\n \n- virtual function inject_error();\n+ virtual function void inject_error();\n this.enable_error = 1'b1;\n endfunction\n \n", "test_patch": "", "modified_files": ["dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_slave_seq_lib.sv"], "lines_added": 1, "lines_removed": 1} +{"repo": "lowRISC/ibex", "pr_id": 613, "lang": "sv", "rtl_files": ["rtl/ibex_cs_registers.sv"], "commit_id": "f90faa6ca365e02047d456ac3ad084ecc457ada0", "timestamp": "2020-02-20T14:29:33+00:00", "pr_title": "[rtl] Change misa for RV32E", "pr_body": "Following RISC-V privileged architecture version 1.11,\r\nthe \"E\" bit of misa should return the complement of the \"I\" bit.\r\n\r\nSet the \"I\" bit only if RV32E is not used.\r\n\r\nCloses lowRISC/ibex#612.", "issue_title": "CSR misa \"I\" bit value for \"E\" extension", "issue_body": "The \"I\" bit of the CSR misa is always set:\r\nhttps://github.com/lowRISC/ibex/blob/f90faa6ca365e02047d456ac3ad084ecc457ada0/rtl/ibex_cs_registers.sv#L113\r\n\r\nBut I think it should no be set if RV32E is used.\r\nThe priv spec says it 3.1.1 p. 16\r\n\r\n> The “I” bit will be set for RV32I, RV64I, RV128I base ISAs, and the “E” bit will be set for RV32E.\r\n\r\nand\r\n\r\n>The “E” bit is read-only.\r\n>Unless misa is hardwired to zero, the “E” bit always reads as the\r\n>complement of the “I” bit. An implementation that supports both RV32E and RV32I can select\r\n>RV32E by clearing the “I” bit.\r\n\r\nAny objections to the following change?\r\n```verilog\r\n| 32'(!RV32E) << 8)\r\n```", "commit_message": "[rtl] Change misa for RV32E\n\nFollowing RISC-V privileged architecture version 1.11,\nthe \"E\" bit of misa should return the complement of the \"I\" bit.\n\nSet the \"I\" bit only if RV32E is not used.\n\nCloses lowRISC/ibex#612.", "fix_patch": "diff --git a/rtl/ibex_cs_registers.sv b/rtl/ibex_cs_registers.sv\nindex 8ce5e6640a..3e8f13a72f 100644\n--- a/rtl/ibex_cs_registers.sv\n+++ b/rtl/ibex_cs_registers.sv\n@@ -105,18 +105,18 @@ module ibex_cs_registers #(\n // misa\n localparam logic [1:0] MXL = 2'd1; // M-XLEN: XLEN in M-Mode for RV32\n localparam logic [31:0] MISA_VALUE =\n- (0 << 0) // A - Atomic Instructions extension\n- | (1 << 2) // C - Compressed extension\n- | (0 << 3) // D - Double precision floating-point extension\n- | (32'(RV32E) << 4) // E - RV32E base ISA\n- | (0 << 5) // F - Single precision floating-point extension\n- | (1 << 8) // I - RV32I/64I/128I base ISA\n- | (32'(RV32M) << 12) // M - Integer Multiply/Divide extension\n- | (0 << 13) // N - User level interrupts supported\n- | (0 << 18) // S - Supervisor mode implemented\n- | (1 << 20) // U - User mode implemented\n- | (0 << 23) // X - Non-standard extensions present\n- | (32'(MXL) << 30); // M-XLEN\n+ (0 << 0) // A - Atomic Instructions extension\n+ | (1 << 2) // C - Compressed extension\n+ | (0 << 3) // D - Double precision floating-point extension\n+ | (32'(RV32E) << 4) // E - RV32E base ISA\n+ | (0 << 5) // F - Single precision floating-point extension\n+ | (32'(!RV32E) << 8) // I - RV32I/64I/128I base ISA\n+ | (32'(RV32M) << 12) // M - Integer Multiply/Divide extension\n+ | (0 << 13) // N - User level interrupts supported\n+ | (0 << 18) // S - Supervisor mode implemented\n+ | (1 << 20) // U - User mode implemented\n+ | (0 << 23) // X - Non-standard extensions present\n+ | (32'(MXL) << 30); // M-XLEN\n \n typedef struct packed {\n logic mie;\n", "test_patch": "", "modified_files": ["rtl/ibex_cs_registers.sv"], "lines_added": 12, "lines_removed": 12} +{"repo": "lowRISC/ibex", "pr_id": 560, "lang": "sv", "rtl_files": ["dv/uvm/env/core_ibex_env_cfg.sv"], "commit_id": "9d7b07f0f7682c2d6eea82824f8b92c11ffc77b0", "timestamp": "2020-01-23T23:11:55+00:00", "pr_title": "[DV] Test nested interrupts", "pr_body": "Tests scenarios where Ibex is executing an interrupt handler and receives a second set of interrupts in the middle of the first handler.\r\nAs per the discussion in #557, I have eliminated nested NMI interrupt test scenarios from this testcase.\r\nThis PR relies on https://github.com/google/riscv-dv/pull/444 to be functionally correct, so will only merge this PR after vendoring the latest riscv-dv copy.\r\n\r\nSigned-off-by: Udi ", "issue_title": "Nested NMI interrupts", "issue_body": "Hi,\r\nWhen debugging a test case in which I asserted two nested NMI interrupts to force the core to respond to the second NMI interrupt while executing the handler for the first NMI, resulting in this waveform:\r\n![Screenshot from 2020-01-16 13-01-12](https://user-images.githubusercontent.com/16736281/72562455-560e1200-3860-11ea-82bc-b7b538baff8d.png)\r\nAt the location of the cursor, Ibex is in the middle of executing the NMI interrupt handler and sees the input interrupt lines being changed to another set of incoming interrupts; these new interrupts are processed when `csr_save_cause_i` goes high at `3,843,000ns`. Note that `nmi_mode_q` in the controller is high before the second set of interrupts due to the NMI detection.\r\nHowever, this second set of interrupts also includes a NMI, but Ibex sets `mcause` to `0b11_1110 = 0x3e` indicating a fast interrupt, causing a testbench failure since we should expect `mcause` to be `0b11_1111 = 0x3f` for the NMI. This mismatch is due to the `IRQ_TAKEN` state in the controller, specifically this section:\r\n![Screenshot from 2020-01-16 13-21-00](https://user-images.githubusercontent.com/16736281/72563686-0d0b8d00-3863-11ea-8229-7ef814b02245.png).\r\nSince `nmi_mode_q` is already high from the first NMI that Ibex was initially handling, the core does not recognize the NMI asserted inside of the interrupt handler, and as such delegates it to be a fast interrupt, causing a mismatch in `mcause`.\r\n\r\nAnother potential issue that could arise is from this section in the CSR register file:\r\n![Screenshot from 2020-01-16 13-25-38](https://user-images.githubusercontent.com/16736281/72564000-b2befc00-3863-11ea-87e4-a4b7110aded3.png)\r\nSince Ibex restores CSR state from the `mstack` CSRs only in the case of NMI interrupts, I don't think the core would be able to correctly return from a series of nested NMIs, as the saved state from the first NMI in the `mstack` CSRs would be overwritten by the state of the second NMI.\r\n\r\nGiven these potential issues, my question is if this situation of nested NMI interrupts is something that Ibex can handle at all?", "commit_message": "[DV] Test nested interrupts\n\nSigned-off-by: Udi ", "fix_patch": "diff --git a/dv/uvm/env/core_ibex_env_cfg.sv b/dv/uvm/env/core_ibex_env_cfg.sv\nindex 06f99852cd..4152230ddd 100644\n--- a/dv/uvm/env/core_ibex_env_cfg.sv\n+++ b/dv/uvm/env/core_ibex_env_cfg.sv\n@@ -6,6 +6,7 @@ class core_ibex_env_cfg extends uvm_object;\n \n bit enable_irq_single_seq;\n bit enable_irq_multiple_seq;\n+ bit enable_nested_irq;\n bit enable_debug_seq;\n bit[31:0] max_interval;\n bit require_signature_addr;\n@@ -15,6 +16,7 @@ class core_ibex_env_cfg extends uvm_object;\n `uvm_object_utils_begin(core_ibex_env_cfg)\n `uvm_field_int(enable_irq_single_seq, UVM_DEFAULT)\n `uvm_field_int(enable_irq_multiple_seq, UVM_DEFAULT)\n+ `uvm_field_int(enable_nested_irq, UVM_DEFAULT)\n `uvm_field_int(enable_debug_seq, UVM_DEFAULT)\n `uvm_field_int(max_interval, UVM_DEFAULT)\n `uvm_field_int(require_signature_addr, UVM_DEFAULT)\n@@ -25,6 +27,7 @@ class core_ibex_env_cfg extends uvm_object;\n super.new(name);\n void'($value$plusargs(\"enable_irq_single_seq=%0d\", enable_irq_single_seq));\n void'($value$plusargs(\"enable_irq_multiple_seq=%0d\", enable_irq_multiple_seq));\n+ void'($value$plusargs(\"enable_nested_irq=%0d\", enable_nested_irq));\n void'($value$plusargs(\"enable_debug_seq=%0d\", enable_debug_seq));\n void'($value$plusargs(\"max_interval=%0d\", max_interval));\n void'($value$plusargs(\"require_signature_addr=%0d\", require_signature_addr));\n", "test_patch": "diff --git a/dv/uvm/riscv_dv_extension/testlist.yaml b/dv/uvm/riscv_dv_extension/testlist.yaml\nindex 351062a100..ac6104d4b4 100644\n--- a/dv/uvm/riscv_dv_extension/testlist.yaml\n+++ b/dv/uvm/riscv_dv_extension/testlist.yaml\n@@ -343,6 +343,26 @@\n compare_opts:\n compare_final_value_only: 1\n \n+- test: riscv_nested_interrupt_test\n+ description: >\n+ Assert interrupt, and then assert another interrupt during the first irq_handler routine\n+ iterations: 10\n+ gen_test: riscv_rand_instr_test\n+ gen_opts: >\n+ +instr_cnt=10000\n+ +require_signature_addr=1\n+ +enable_interrupt=1\n+ +enable_nested_interrupt=1\n+ +randomize_csr=1\n+ +no_csr_instr=1\n+ rtl_test: core_ibex_nested_irq_test\n+ sim_opts: >\n+ +require_signature_addr=1\n+ +enable_irq_multiple_seq=1\n+ +enable_nested_irq=1\n+ compare_opts:\n+ compare_final_value_only: 1\n+\n - test: riscv_interrupt_wfi_test\n description: >\n Inject interrupts after a encountering wfi instructions.\ndiff --git a/dv/uvm/tests/core_ibex_seq_lib.sv b/dv/uvm/tests/core_ibex_seq_lib.sv\nindex 165d158143..a90b645209 100644\n--- a/dv/uvm/tests/core_ibex_seq_lib.sv\n+++ b/dv/uvm/tests/core_ibex_seq_lib.sv\n@@ -70,12 +70,13 @@ class irq_raise_seq extends core_base_seq#(irq_seq_item);\n \n `uvm_object_utils(irq_raise_seq)\n `uvm_object_new\n+ bit no_nmi;\n \n virtual task send_req();\n irq_seq_item irq;\n irq = irq_seq_item::type_id::create($sformatf(\"irq_raise_single[%0d]\", iteration_cnt));\n start_item(irq);\n- `DV_CHECK_RANDOMIZE_WITH_FATAL(irq, num_of_interrupt > 1;)\n+ `DV_CHECK_RANDOMIZE_WITH_FATAL(irq, num_of_interrupt > 1; irq_nm == ~no_nmi;)\n finish_item(irq);\n get_response(irq);\n endtask\n@@ -86,12 +87,13 @@ class irq_raise_single_seq extends core_base_seq#(irq_seq_item);\n \n `uvm_object_utils(irq_raise_single_seq)\n `uvm_object_new\n+ bit no_nmi;\n \n virtual task send_req();\n irq_seq_item irq;\n irq = irq_seq_item::type_id::create($sformatf(\"irq_raise_single[%0d]\", iteration_cnt));\n start_item(irq);\n- `DV_CHECK_RANDOMIZE_WITH_FATAL(irq, num_of_interrupt == 1;)\n+ `DV_CHECK_RANDOMIZE_WITH_FATAL(irq, num_of_interrupt == 1; irq_nm == ~no_nmi;)\n finish_item(irq);\n get_response(irq);\n endtask\ndiff --git a/dv/uvm/tests/core_ibex_test_lib.sv b/dv/uvm/tests/core_ibex_test_lib.sv\nindex efc594fe00..daf26f3193 100644\n--- a/dv/uvm/tests/core_ibex_test_lib.sv\n+++ b/dv/uvm/tests/core_ibex_test_lib.sv\n@@ -154,6 +154,7 @@ class core_ibex_debug_intr_basic_test extends core_ibex_base_test;\n \n bit [ibex_mem_intf_agent_pkg::DATA_WIDTH-1:0] core_init_mstatus;\n bit [ibex_mem_intf_agent_pkg::DATA_WIDTH-1:0] core_init_mie;\n+ priv_lvl_e init_operating_mode;\n priv_lvl_e operating_mode;\n bit [$clog2(irq_agent_pkg::DATA_WIDTH)-1:0] irq_id;\n irq_seq_item irq_txn;\n@@ -162,6 +163,7 @@ class core_ibex_debug_intr_basic_test extends core_ibex_base_test;\n bit [ibex_mem_intf_agent_pkg::DATA_WIDTH-1:0] mcause;\n bit [ibex_mem_intf_agent_pkg::DATA_WIDTH-1:0] mip;\n bit [ibex_mem_intf_agent_pkg::DATA_WIDTH-1:0] mie;\n+ bit in_nested_trap;\n \n virtual task send_stimulus();\n fork\n@@ -194,27 +196,35 @@ class core_ibex_debug_intr_basic_test extends core_ibex_base_test;\n join_none\n endtask\n \n+ function priv_lvl_e select_mode();\n+ if (in_nested_trap) return operating_mode;\n+ else return init_operating_mode;\n+ endfunction\n+\n virtual task wait_for_core_setup();\n wait_for_csr_write(CSR_MSTATUS, 1000);\n core_init_mstatus = signature_data;\n // capture the initial privilege mode ibex will boot into\n- operating_mode = core_init_mstatus[12:11];\n+ init_operating_mode = core_init_mstatus[12:11];\n wait_for_csr_write(CSR_MIE, 500);\n core_init_mie = signature_data;\n check_next_core_status(INITIALIZED, \"Core initialization handshake failure\", 500);\n endtask\n \n- virtual task send_irq_stimulus();\n+ virtual task send_irq_stimulus_start(input bit no_nmi,\n+ output bit ret_val);\n bit irq_valid;\n // send the interrupt\n- if (cfg.enable_irq_single_seq) vseq.start_irq_raise_single_seq();\n- else if (cfg.enable_irq_multiple_seq) vseq.start_irq_raise_seq();\n+ if (cfg.enable_irq_single_seq) vseq.start_irq_raise_single_seq(no_nmi);\n+ else if (cfg.enable_irq_multiple_seq) vseq.start_irq_raise_seq(no_nmi);\n irq_collected_port.get(irq_txn);\n irq = {irq_txn.irq_nm, irq_txn.irq_fast, 4'b0, irq_txn.irq_external, 3'b0,\n irq_txn.irq_timer, 3'b0, irq_txn.irq_software, 3'b0};\n+ `uvm_info(`gfn, $sformatf(\"irq: 0x%0x\", irq), UVM_LOW)\n // Get the bit position of the highest priority interrupt - ibex will only handle this one if\n // there are multiple irqs asserted at once.\n irq_valid = get_max_valid_irq_id(irq);\n+ `uvm_info(`gfn, $sformatf(\"irq_id: 0x%0x\", irq_id), UVM_LOW)\n // If the interrupt is maskable, and the corresponding bit in MIE is not set, skip the next\n // checks, as it means the interrupt in question is not enabled by Ibex, and drop the interrupt\n // lines to avoid locking up the simulation.\n@@ -224,15 +234,16 @@ class core_ibex_debug_intr_basic_test extends core_ibex_base_test;\n irq = {irq_txn.irq_nm, irq_txn.irq_fast, 4'b0, irq_txn.irq_external, 3'b0,\n irq_txn.irq_timer, 3'b0, irq_txn.irq_software, 3'b0};\n `DV_CHECK_EQ_FATAL(irq, 0, \"Interrupt lines have not been dropped\")\n+ ret_val = irq_valid;\n return;\n end\n- `uvm_info(`gfn, $sformatf(\"irq: 0b%0b\", irq), UVM_LOW)\n check_next_core_status(HANDLING_IRQ, \"Core did not jump to vectored interrupt handler\", 750);\n check_priv_mode(PRIV_LVL_M);\n+ operating_mode = dut_vif.priv_mode;\n // check mstatus\n wait_for_csr_write(CSR_MSTATUS, 500);\n mstatus = signature_data;\n- `DV_CHECK_EQ_FATAL(mstatus[12:11], operating_mode, \"Incorrect privilege mode\")\n+ `DV_CHECK_EQ_FATAL(mstatus[12:11], select_mode(), \"Incorrect mstatus.mpp\")\n `DV_CHECK_EQ_FATAL(mstatus[7], 1'b1, \"mstatus.mpie was not set to 1'b1 after entering handler\")\n `DV_CHECK_EQ_FATAL(mstatus[3], 1'b0, \"mstatus.mie was not set to 1'b0 after entering handler\")\n // check mcause against the interrupt id\n@@ -254,18 +265,32 @@ class core_ibex_debug_intr_basic_test extends core_ibex_base_test;\n `DV_CHECK_EQ_FATAL(mip[irq_id], 1'b1,\n $sformatf(\"mip[%0d] is not set, but core responded to corresponding interrupt\", irq_id))\n end\n+ ret_val = irq_valid;\n+ return;\n+ endtask\n+\n+ virtual task send_irq_stimulus_end();\n // As Ibex interrupts are level sensitive, core must write to memory mapped address to\n // indicate that irq stimulus be dropped\n check_next_core_status(FINISHED_IRQ, \"Core did not signal end of interrupt properly\", 300);\n // Will receive irq_seq_item indicating that lines have been dropped\n vseq.start_irq_drop_seq();\n- irq_collected_port.get(irq_txn);\n- irq = {irq_txn.irq_nm, irq_txn.irq_fast, 4'b0, irq_txn.irq_external, 3'b0,\n- irq_txn.irq_timer, 3'b0, irq_txn.irq_software, 3'b0};\n- `DV_CHECK_EQ_FATAL(irq, 0, \"Interrupt lines have not been dropped\")\n+ // Want to skip this .get() call on the second MRET of nested interrupt scenarios\n+ if (!(cfg.enable_nested_irq && !in_nested_trap)) begin\n+ irq_collected_port.get(irq_txn);\n+ irq = {irq_txn.irq_nm, irq_txn.irq_fast, 4'b0, irq_txn.irq_external, 3'b0,\n+ irq_txn.irq_timer, 3'b0, irq_txn.irq_software, 3'b0};\n+ `DV_CHECK_EQ_FATAL(irq, 0, \"Interrupt lines have not been dropped\")\n+ end\n wait_ret(\"mret\", 1000);\n endtask\n \n+ virtual task send_irq_stimulus(bit no_nmi = 1'b0);\n+ bit ret_val;\n+ send_irq_stimulus_start(no_nmi, ret_val);\n+ if (ret_val) send_irq_stimulus_end();\n+ endtask\n+\n function int get_max_valid_irq_id(bit [irq_agent_pkg::DATA_WIDTH-1:0] irq);\n int i;\n // Ibex implementation of MIE does not mask NM interrupts, so need to check this separately\n@@ -288,6 +313,7 @@ class core_ibex_debug_intr_basic_test extends core_ibex_base_test;\n bit[ibex_mem_intf_agent_pkg::DATA_WIDTH-1:0] mcause;\n wait_for_csr_write(CSR_MCAUSE, 1000);\n mcause = signature_data;\n+ `uvm_info(`gfn, $sformatf(\"mcause: 0x%0x\", mcause), UVM_LOW)\n `DV_CHECK_EQ_FATAL(mcause[ibex_mem_intf_agent_pkg::DATA_WIDTH-1], irq_or_exc,\n $sformatf(\"mcause.interrupt is not set to 0x%0x\", irq_or_exc))\n `DV_CHECK_EQ_FATAL(mcause[ibex_mem_intf_agent_pkg::DATA_WIDTH-2:0], cause,\n@@ -328,7 +354,7 @@ class core_ibex_debug_intr_basic_test extends core_ibex_base_test;\n `uvm_fatal(`gfn, $sformatf(\"Invalid xRET instruction %0s\", ret))\n end\n endcase\n- wait (dut_vif.priv_mode === operating_mode);\n+ wait (dut_vif.priv_mode === select_mode());\n end\n begin : ret_timeout\n clk_vif.wait_clks(timeout);\n@@ -521,6 +547,36 @@ class core_ibex_debug_irq_test extends core_ibex_directed_test;\n \n endclass\n \n+// Nested interrupt test class (with multiple interrupts)\n+class core_ibex_nested_irq_test extends core_ibex_directed_test;\n+\n+ `uvm_component_utils(core_ibex_nested_irq_test)\n+ `uvm_component_new\n+\n+ virtual task check_stimulus();\n+ bit valid_irq;\n+ bit valid_nested_irq;\n+ int unsigned initial_irq_delay;\n+ forever begin\n+ send_irq_stimulus_start(1'b1, valid_irq);\n+ if (valid_irq) begin\n+ initial_irq_delay = vseq.irq_raise_seq_h.max_delay;\n+ vseq.irq_raise_seq_h.max_delay = 0;\n+ // Send nested interrupt after the checks of the first interrupt have finished\n+ in_nested_trap = 1'b1;\n+ // wait until we are setting mstatus.mie to 1'b1 to send the next set of interrupts\n+ wait(csr_vif.csr_access === 1'b1 && csr_vif.csr_addr === CSR_MSTATUS &&\n+ csr_vif.csr_op != CSR_OP_READ);\n+ send_irq_stimulus(1'b0);\n+ vseq.irq_raise_seq_h.max_delay = initial_irq_delay;\n+ in_nested_trap = 1'b0;\n+ send_irq_stimulus_end();\n+ end\n+ end\n+ endtask\n+\n+endclass\n+\n // Debug WFI test class\n class core_ibex_debug_wfi_test extends core_ibex_directed_test;\n \n@@ -543,7 +599,7 @@ class core_ibex_debug_wfi_test extends core_ibex_directed_test;\n // debug rom.\n // We also want to check that dcsr.cause has been set correctly\n wait_for_csr_write(CSR_DCSR, 500);\n- check_dcsr_prv(operating_mode);\n+ check_dcsr_prv(init_operating_mode);\n check_dcsr_cause(DBG_CAUSE_HALTREQ);\n wait_ret(\"dret\", 5000);\n end\n@@ -567,7 +623,7 @@ class core_ibex_debug_csr_test extends core_ibex_directed_test;\n 1000);\n check_priv_mode(PRIV_LVL_M);\n wait_for_csr_write(CSR_DCSR, 500);\n- check_dcsr_prv(operating_mode);\n+ check_dcsr_prv(init_operating_mode);\n check_dcsr_cause(DBG_CAUSE_HALTREQ);\n wait_ret(\"dret\", 5000);\n // wait for a dummy write to mie in the init code\n@@ -578,7 +634,7 @@ class core_ibex_debug_csr_test extends core_ibex_directed_test;\n 1000);\n check_priv_mode(PRIV_LVL_M);\n wait_for_csr_write(CSR_DCSR, 500);\n- check_dcsr_prv(operating_mode);\n+ check_dcsr_prv(init_operating_mode);\n check_dcsr_cause(DBG_CAUSE_HALTREQ);\n wait_ret(\"dret\", 5000);\n endtask\n@@ -616,7 +672,7 @@ class core_ibex_debug_ebreak_test extends core_ibex_directed_test;\n // capture the first write of dcsr\n check_priv_mode(PRIV_LVL_M);\n wait_for_csr_write(CSR_DCSR, 500);\n- check_dcsr_prv(operating_mode);\n+ check_dcsr_prv(init_operating_mode);\n dcsr = signature_data;\n // We also want to check that dcsr.cause has been set correctly\n check_dcsr_cause(DBG_CAUSE_HALTREQ);\n@@ -653,7 +709,7 @@ class core_ibex_debug_ebreakmu_test extends core_ibex_directed_test;\n // Read dcsr and verify the appropriate ebreak(m/s/u) bit has been set based on the prv field,\n // as well as the cause field\n wait_for_csr_write(CSR_DCSR, 500);\n- check_dcsr_prv(operating_mode);\n+ check_dcsr_prv(init_operating_mode);\n check_dcsr_ebreak();\n check_dcsr_cause(DBG_CAUSE_HALTREQ);\n wait_ret(\"dret\", 5000);\n@@ -664,7 +720,7 @@ class core_ibex_debug_ebreakmu_test extends core_ibex_directed_test;\n check_priv_mode(PRIV_LVL_M);\n // Read dcsr and verify the appropriate ebreak(m/s/u) bit has been set based on the prv field\n wait_for_csr_write(CSR_DCSR, 500);\n- check_dcsr_prv(operating_mode);\n+ check_dcsr_prv(init_operating_mode);\n check_dcsr_ebreak();\n check_dcsr_cause(DBG_CAUSE_EBREAK);\n wait_ret(\"dret\", 5000);\n@@ -693,7 +749,7 @@ class core_ibex_debug_single_step_test extends core_ibex_directed_test;\n wait_for_csr_write(CSR_DSCRATCH0, 500);\n next_counter = signature_data;\n wait_for_csr_write(CSR_DCSR, 1000);\n- check_dcsr_prv(operating_mode);\n+ check_dcsr_prv(init_operating_mode);\n check_dcsr_cause(DBG_CAUSE_HALTREQ);\n `DV_CHECK_EQ_FATAL(signature_data[2], 1'b1, \"dcsr.step is not set\")\n wait_ret(\"dret\", 5000);\n@@ -714,7 +770,7 @@ class core_ibex_debug_single_step_test extends core_ibex_directed_test;\n wait_for_csr_write(CSR_DSCRATCH0, 500);\n next_counter = signature_data;\n wait_for_csr_write(CSR_DCSR, 500);\n- check_dcsr_prv(operating_mode);\n+ check_dcsr_prv(init_operating_mode);\n check_dcsr_cause(DBG_CAUSE_STEP);\n if (counter === 0) begin\n `DV_CHECK_EQ_FATAL(signature_data[2], 1'b0, \"dcsr.step is set\")\n@@ -854,7 +910,7 @@ class core_ibex_invalid_csr_test extends core_ibex_directed_test;\n // Wait for a CSR access\n wait (csr_vif.csr_access == 1'b1);\n check_illegal_insn($sformatf(\"Core did not treat access to CSR 0x%0x from %0s as illegal\",\n- csr_vif.csr_addr, operating_mode));\n+ csr_vif.csr_addr, init_operating_mode));\n end\n endtask\n \ndiff --git a/dv/uvm/tests/core_ibex_vseq.sv b/dv/uvm/tests/core_ibex_vseq.sv\nindex d8d913437f..951bf3d8f8 100644\n--- a/dv/uvm/tests/core_ibex_vseq.sv\n+++ b/dv/uvm/tests/core_ibex_vseq.sv\n@@ -45,7 +45,7 @@ class core_ibex_vseq extends uvm_sequence;\n irq_drop_seq_h = irq_drop_seq::type_id::create(\"irq_drop_seq_h\");\n irq_drop_seq_h.num_of_iterations = 1;\n irq_drop_seq_h.max_interval = 1;\n- irq_drop_seq_h.max_delay = 1;\n+ irq_drop_seq_h.max_delay = 0;\n irq_drop_seq_h.interval = 0;\n end\n if (cfg.enable_debug_seq) begin\n@@ -93,11 +93,13 @@ class core_ibex_vseq extends uvm_sequence;\n debug_seq_single_h.start(null);\n endtask\n \n- virtual task start_irq_raise_single_seq();\n+ virtual task start_irq_raise_single_seq(bit no_nmi = 1'b0);\n+ irq_raise_single_seq_h.no_nmi = no_nmi;\n irq_raise_single_seq_h.start(p_sequencer.irq_seqr);\n endtask\n \n- virtual task start_irq_raise_seq();\n+ virtual task start_irq_raise_seq(bit no_nmi = 1'b0);\n+ irq_raise_seq_h.no_nmi = no_nmi;\n irq_raise_seq_h.start(p_sequencer.irq_seqr);\n endtask\n \n", "modified_files": ["dv/uvm/env/core_ibex_env_cfg.sv", "dv/uvm/riscv_dv_extension/testlist.yaml", "dv/uvm/tests/core_ibex_seq_lib.sv", "dv/uvm/tests/core_ibex_test_lib.sv", "dv/uvm/tests/core_ibex_vseq.sv"], "lines_added": 108, "lines_removed": 25} +{"repo": "lowRISC/ibex", "pr_id": 507, "lang": "sv", "rtl_files": ["dv/uvm/env/core_ibex_env_cfg.sv"], "commit_id": "43268b7604f40d4865a899988638d8c1b8e36dcb", "timestamp": "2019-12-03T16:23:51+00:00", "pr_title": "Pluseargs parsing fix", "pr_body": "This commit fixes $value$plusargs sytem function error described in #497.", "issue_title": "Cadence simulator plusargs command line argument parsing error", "issue_body": "Verification environment uses SystemVerilog line argument for getting signature address [(core_ibex_env_cfg.sv)](https://github.com/lowRISC/ibex/blob/ce7e38351e28bf54cbc7c2856ce6b65b9d2a3fbb/dv/uvm/env/core_ibex_env_cfg.sv#L30). Value is passed to environment at [(makefile)](https://github.com/lowRISC/ibex/blob/ce7e38351e28bf54cbc7c2856ce6b65b9d2a3fbb/dv/uvm/Makefile#L132) at run_sim step. The problem is Cadence simulator cannot recognize this argument as hexadecimal number:\r\n```\r\nvoid'($value$plusargs(\"signature_addr=%0h\", signature_addr));\r\n |\r\nncsim: *E,SYSFMT (ibex/dv/uvm/env/core_ibex_env_cfg.sv,30|24): $value$plusargs -- value found '0x8ffffffc' for plusarg 'signature_addr=' does not match specified format.\r\n```\r\nThis issue can be fixed with something like atohex() SystemVerilog function (this function should be supported by all simulators).", "commit_message": "Pluseargs parsing was corrected", "fix_patch": "diff --git a/dv/uvm/env/core_ibex_env_cfg.sv b/dv/uvm/env/core_ibex_env_cfg.sv\nindex 988de600ac..dd0e4e9612 100644\n--- a/dv/uvm/env/core_ibex_env_cfg.sv\n+++ b/dv/uvm/env/core_ibex_env_cfg.sv\n@@ -9,6 +9,7 @@ class core_ibex_env_cfg extends uvm_object;\n bit enable_debug_single_seq;\n bit[31:0] max_interval;\n bit require_signature_addr;\n+ string signature_addr_str;\n bit[31:0] signature_addr;\n \n `uvm_object_utils_begin(core_ibex_env_cfg)\n@@ -27,7 +28,8 @@ class core_ibex_env_cfg extends uvm_object;\n void'($value$plusargs(\"enable_debug_single_seq=%0d\", enable_debug_single_seq));\n void'($value$plusargs(\"max_interval=%0d\", max_interval));\n void'($value$plusargs(\"require_signature_addr=%0d\", require_signature_addr));\n- void'($value$plusargs(\"signature_addr=%0h\", signature_addr));\n+ void'($value$plusargs(\"signature_addr=%s\", signature_addr_str));\n+ signature_addr = signature_addr_str.atohex();\n endfunction\n \n endclass\n", "test_patch": "", "modified_files": ["dv/uvm/env/core_ibex_env_cfg.sv"], "lines_added": 3, "lines_removed": 1} +{"repo": "lowRISC/ibex", "pr_id": 470, "lang": "sv", "rtl_files": ["shared/rtl/sim/simulator_ctrl.sv"], "commit_id": "0927f085ee11f5bcb6a446ebc038e01126123c45", "timestamp": "2019-11-14T11:57:13+00:00", "pr_title": "Delay simulator finish", "pr_body": "The tracer needs time to log the final instruction.\r\nIntroduce a counter to delay calling the simulation finish.\r\n\r\n@imphil is that what you had in mind?", "issue_title": "Trace simulator control", "issue_body": "Using the simple system example:\r\n```\r\n$ fusesoc --cores-root=. run --target=sim --setup --build lowrisc:ibex:ibex_simple_system\r\n$ build/lowrisc_ibex_ibex_simple_system_0/sim-verilator/Vibex_simple_system --raminit=examples/sw/simple_system/hello_test/hello_test.vmem\r\n```\r\nproduces the following trace\r\n```\r\n% tail -n 4 trace_core_00000000.log \r\n 1260 626 00100308 8082 c.jr x1 x1:0x001002b8\r\n 1262 627 001002b8 000202b7 lui x5,0x20 x5=0x00020000\r\n 1264 628 001002bc 00428293 addi x5,x5,4 x5:0x00020000 x5=0x00020004\r\n 1266 629 001002c0 4305 c.li x6,1 x6=0x00000001\r\n```\r\n\r\nFrom `crt0.S`\r\n```\r\n /* Halt simulation */ \r\n li x5, SIM_CTRL_BASE + SIM_CTRL_CTRL \r\n li x6, 1 \r\n sw x6, 0(x5)\r\n```\r\nwe see the last store instruction (which terminates the simulation via `simulator_ctrl.sv +73`) is not part of the trace.\r\nProbably not the highest priority to fix, but wanted to document what I saw.", "commit_message": "Delay simulator finish\n\nThe tracer needs time to log the final instruction.\nIntroduce a counter to delay calling the simulation finish.\n\nFixes lowrisc/ibex#468", "fix_patch": "diff --git a/shared/rtl/sim/simulator_ctrl.sv b/shared/rtl/sim/simulator_ctrl.sv\nindex 9fa8de6615..002845a439 100644\n--- a/shared/rtl/sim/simulator_ctrl.sv\n+++ b/shared/rtl/sim/simulator_ctrl.sv\n@@ -36,6 +36,7 @@ module simulator_ctrl #(\n localparam SIM_CTRL_ADDR = 1;\n \n logic [7:0] ctrl_addr;\n+ logic [2:0] sim_finish;\n \n integer log_fd;\n \n@@ -52,6 +53,7 @@ module simulator_ctrl #(\n always_ff @(posedge clk_i or negedge rst_ni) begin\n if (~rst_ni) begin\n rvalid_o <= 0;\n+ sim_finish <= 'b0;\n end else begin\n // Immeditely respond to any request\n rvalid_o <= req_i;\n@@ -68,9 +70,9 @@ module simulator_ctrl #(\n end\n end\n SIM_CTRL_ADDR: begin\n- if (be_i[0] & wdata_i[0]) begin\n+ if ((be_i[0] & wdata_i[0]) && (sim_finish == 'b0)) begin\n $display(\"Terminating simulation by software request.\");\n- $finish;\n+ sim_finish <= 3'b001;\n end\n end\n endcase\n@@ -78,6 +80,14 @@ module simulator_ctrl #(\n end\n end\n \n+ always_ff @(posedge clk_i or negedge rst_ni) begin\n+ if (sim_finish != 'b0) begin\n+ sim_finish <= sim_finish + 1;\n+ end\n+ if (sim_finish >= 3'b010) begin\n+ $finish;\n+ end\n+ end\n assign rdata_o = '0;\n endmodule\n \n", "test_patch": "", "modified_files": ["shared/rtl/sim/simulator_ctrl.sv"], "lines_added": 12, "lines_removed": 2} +{"repo": "lowRISC/ibex", "pr_id": 461, "lang": "sv", "rtl_files": ["rtl/ibex_cs_registers.sv"], "commit_id": "9b390c5d4ed83bb426d8a3f047d9998572309fab", "timestamp": "2019-11-13T12:11:23+00:00", "pr_title": "[rtl] Ignore LSB only for writes to `dpc`", "pr_body": "Without this PR, writes to `dpc` with the LSB set are completely ignored. This PR changes the implementation to ignore the LSB only. This is the same behavior as seen required for `mepc`. This resolves lowRISC/ibex#444.", "issue_title": "Writing unaligned addresses to `dpc` CSR", "issue_body": "Currently, writes to the `dpc` CSR are simply ignored if the address is unaligned. The debug spec does not specify what should happen if an unaligned address is written to `dpc`. In contrast, the privileged spec says that `xepc` can only hold aligned addresses.\r\n\r\nI suggest to align the behavior of these two registers, i.e., to make the LSB of `dpc` to be always 0 instead of ignoring writes with non-zero LSB completely.", "commit_message": "[rtl] Ignore LSB only for writes to `dpc`\n\nWithout this commit, writes to `dpc` with the LSB set are completely\nignored. This commit changes the implementation to ignore the LSB only.\nThis is the same behavior as seen required for `mepc`. This resolves\nlowRISC/ibex#444.\n\nSigned-off-by: Pirmin Vogel ", "fix_patch": "diff --git a/rtl/ibex_cs_registers.sv b/rtl/ibex_cs_registers.sv\nindex caecdc756f..16b5f8b986 100644\n--- a/rtl/ibex_cs_registers.sv\n+++ b/rtl/ibex_cs_registers.sv\n@@ -459,12 +459,8 @@ module ibex_cs_registers #(\n dcsr_d.zero2 = 12'h0;\n end\n \n- CSR_DPC: begin\n- // Only valid PC addresses are allowed (half-word aligned with C ext.)\n- if (csr_wdata_int[0] == 1'b0) begin\n- depc_d = csr_wdata_int;\n- end\n- end\n+ // dpc: debug program counter\n+ CSR_DPC: depc_d = {csr_wdata_int[31:1], 1'b0};\n \n CSR_DSCRATCH0: dscratch0_d = csr_wdata_int;\n CSR_DSCRATCH1: dscratch1_d = csr_wdata_int;\n", "test_patch": "", "modified_files": ["rtl/ibex_cs_registers.sv"], "lines_added": 2, "lines_removed": 6} +{"repo": "lowRISC/ibex", "pr_id": 425, "lang": "sv", "rtl_files": ["rtl/ibex_load_store_unit.sv"], "commit_id": "294849bb18e27c0487b7317f53ca878217712ffd", "timestamp": "2019-10-26T13:51:20+00:00", "pr_title": "[rtl/lsu] Rework assertion checking response valid", "pr_body": "This commit replaces an obsolete assertion with one checking that response valid is received only if the LSU is ready to handle it.\r\n\r\nThis resolves lowRISC/ibex#421 reported by @udinator.", "issue_title": "LSU: Remove/correct obsolete assertion", "issue_body": "Inside `ibex_load_store_unit.sv`, we have an assertion checking that in the RVALID state, a grant can only be received while also getting the rvalid. This assertion has become obsolete in the process of adding PMP support. Currently, the RVALID state is only entered when a grant is no longer expected.\r\n\r\nThis assertion should be removed or corrected. ", "commit_message": "[rtl/lsu] Rework assertion checking response valid\n\nThis commit replaces an obsolete assertion with one checking that\nresponse valid is received only if the LSU is ready to handle it.\n\nThis resolves lowRISC/ibex#421 reported by @udinator.", "fix_patch": "diff --git a/rtl/ibex_load_store_unit.sv b/rtl/ibex_load_store_unit.sv\nindex 2c08892e0e..d823938ead 100644\n--- a/rtl/ibex_load_store_unit.sv\n+++ b/rtl/ibex_load_store_unit.sv\n@@ -483,18 +483,11 @@ module ibex_load_store_unit (\n ////////////////\n \n `ifndef VERILATOR\n- // make sure there is no new request when the old one is not yet completely done\n- // i.e. it should not be possible to get a grant without an rvalid for the\n- // last request\n+ // there should not be an rvalid unless the FSM is handlling it\n assert property (\n- @(posedge clk_i)\n- ((ls_fsm_cs == WAIT_RVALID) && (data_gnt_i == 1'b1)) |-> (data_rvalid_i == 1'b1) ) else\n- $display(\"Data grant set while LSU keeps waiting for rvalid\");\n-\n- // there should be no rvalid when we are in IDLE\n- assert property (\n- @(posedge clk_i) (ls_fsm_cs == IDLE) |-> (data_rvalid_i == 1'b0) ) else\n- $display(\"Data rvalid set while LSU idle\");\n+ @(posedge clk_i) (data_rvalid_i) |-> ((ls_fsm_cs == WAIT_RVALID) ||\n+ (ls_fsm_cs == WAIT_RVALID_MIS) || (ls_fsm_cs == WAIT_RVALID_DONE)) ) else\n+ $display(\"Data response valid received without expecting it\");\n \n // assert that errors are only sent at the same time as rvalid\n assert property (\n", "test_patch": "", "modified_files": ["rtl/ibex_load_store_unit.sv"], "lines_added": 4, "lines_removed": 11} +{"repo": "lowRISC/ibex", "pr_id": 416, "lang": "sv", "rtl_files": ["rtl/ibex_tracer.sv"], "commit_id": "8e40f65582e7925d2cd50021256005391ad07460", "timestamp": "2019-10-23T17:30:12+00:00", "pr_title": "[RTL/Tracer] Fix compressed jump RD write", "pr_body": "Fixes #414.", "issue_title": "[tracer] C.JALR does not display write to x1", "issue_body": "Hi all,\r\n![Screenshot from 2019-10-21 11-27-57](https://user-images.githubusercontent.com/16736281/67232342-056c5180-f3f6-11e9-8789-9d6f85472320.png)\r\nAs shown from this trace, even though `c.jalr` instruction will write `PC+2` to `x1`, this write is not reflected in the tracer log.\r\nBest,\r\nUdi", "commit_message": "[RTL/Tracer] Fix compressed jump RD write", "fix_patch": "diff --git a/rtl/ibex_tracer.sv b/rtl/ibex_tracer.sv\nindex deba8e549f..40eaa1e037 100644\n--- a/rtl/ibex_tracer.sv\n+++ b/rtl/ibex_tracer.sv\n@@ -463,7 +463,13 @@ module ibex_tracer (\n \n function void decode_cr_insn(input string mnemonic);\n if (rvfi_rs2_addr == 5'b0) begin\n- data_accessed = RS1;\n+ if (rvfi_insn[12] == 1'b1) begin\n+ // C.JALR\n+ data_accessed = RS1 | RD;\n+ end else begin\n+ // C.JR\n+ data_accessed = RS1;\n+ end\n decoded_str = $sformatf(\"%s\\tx%0d\", mnemonic, rvfi_rs1_addr);\n end else begin\n data_accessed = RS1 | RS2 | RD; // RS1 == RD\n@@ -549,6 +555,10 @@ module ibex_tracer (\n endfunction\n \n function void decode_cj_insn(input string mnemonic);\n+ if (rvfi_insn[15:13] == 3'b001) begin\n+ // C.JAL\n+ data_accessed = RD;\n+ end\n decoded_str = $sformatf(\"%s\\t%0x\", mnemonic, rvfi_pc_wdata);\n endfunction\n \n", "test_patch": "", "modified_files": ["rtl/ibex_tracer.sv"], "lines_added": 11, "lines_removed": 1} +{"repo": "lowRISC/ibex", "pr_id": 408, "lang": "sv", "rtl_files": ["rtl/ibex_tracer.sv"], "commit_id": "edb33cca5679415d8fb838b7697c6d7f48c373cd", "timestamp": "2019-10-17T12:48:31+00:00", "pr_title": "Tracer: Decode an all-zero instruction as INVALID", "pr_body": "Fixes #396", "issue_title": "[ibex_tracer] Ibex tracer improvements", "issue_body": "This is an issue to collect points that could be improved or \"beautified\" in the instruction tracer. Please feel free to modify/add to this list.\r\n\r\n1) Improve printout alignment of the trace (see example below).\r\n2) Correctly handle invalid instructions (see example below).\r\n3) Add more information about exceptions.\r\n\r\nExample snippet where an all-zero instruction is interpreted as `c.addi4spn` instead of marking it as INVALID:\r\n```\r\n23688 11839 1a110354 00000013 addi x0,x0,0 x0:0x00000000 x0=0x00000000\r\n23696 11843 1a110358 7b302573 csrrs x10,0x7b3,x0 x0:0x00000000 x10=0x00000032\r\n23700 11845 1a11035c 00100073 ebreak \r\n23708 11849 1a110360 0000 c.addi4spn x0,x2,0 x0=0x00000000\r\n23726 11858 1a110808 04c0006f jal x0,1a110854 x0=0x00000000\r\n23736 11863 1a110854 7b351073 csrrw x0,0x7b3,x10 x10:0x00000032 x0=0x00000000\r\n23744 11867 1a110858 00000517 auipc x10,0x0 x10=0x1a110858\r\n23748 11869 1a11085c 00c55513 srli x10,x10,0xc x10:0x1a110858 x10=0x0001a110\r\n``` \r\n\r\nNote: there exist other opensource RISC-V cores that have a tracer (such as [Ariane](https://github.com/pulp-platform/ariane/blob/master/src/util/)). Maybe some synergy could be leveraged here and/or the format could be aligned...\r\n\r\n\r\n\r\n", "commit_message": "Tracer: Decode an all-zero instruction as c.unimp\n\nFixes #396", "fix_patch": "diff --git a/rtl/ibex_tracer.sv b/rtl/ibex_tracer.sv\nindex 423b76d6bf..deba8e549f 100644\n--- a/rtl/ibex_tracer.sv\n+++ b/rtl/ibex_tracer.sv\n@@ -721,7 +721,14 @@ module ibex_tracer (\n end else begin\n unique casez (rvfi_insn[15:0])\n // C0 Opcodes\n- INSN_CADDI4SPN: decode_ciw_insn(\"c.addi4spn\");\n+ INSN_CADDI4SPN: begin\n+ if (rvfi_insn[12:2] == 11'h0) begin\n+ // Align with pseudo-mnemonic used by GNU binutils and LLVM's MC layer\n+ decode_mnemonic(\"c.unimp\");\n+ end else begin\n+ decode_ciw_insn(\"c.addi4spn\");\n+ end\n+ end\n INSN_CLW: decode_compressed_load_insn(\"c.lw\");\n INSN_CSW: decode_compressed_store_insn(\"c.sw\");\n // C1 Opcodes\n", "test_patch": "", "modified_files": ["rtl/ibex_tracer.sv"], "lines_added": 8, "lines_removed": 1} +{"repo": "lowRISC/ibex", "pr_id": 401, "lang": "sv", "rtl_files": ["rtl/ibex_controller.sv"], "commit_id": "b94961402cab9729cac4b0692a0710a840b108f0", "timestamp": "2019-10-16T09:23:06+00:00", "pr_title": "[RTL] Fix single stepping on exceptions", "pr_body": "When we single step over an instruction that causes an exception DPC\r\nshould be set to point to the exception handler (where we would have\r\ngone were we not single stepping).\r\n\r\nAs discussed on Zulip this looks to be the correct behaviour, see response to issue on riscv-debug-spec here https://github.com/riscv/riscv-debug-spec/issues/497", "issue_title": "Cadence simulator plusargs command line argument parsing error", "issue_body": "Verification environment uses SystemVerilog line argument for getting signature address [(core_ibex_env_cfg.sv)](https://github.com/lowRISC/ibex/blob/ce7e38351e28bf54cbc7c2856ce6b65b9d2a3fbb/dv/uvm/env/core_ibex_env_cfg.sv#L30). Value is passed to environment at [(makefile)](https://github.com/lowRISC/ibex/blob/ce7e38351e28bf54cbc7c2856ce6b65b9d2a3fbb/dv/uvm/Makefile#L132) at run_sim step. The problem is Cadence simulator cannot recognize this argument as hexadecimal number:\r\n```\r\nvoid'($value$plusargs(\"signature_addr=%0h\", signature_addr));\r\n |\r\nncsim: *E,SYSFMT (ibex/dv/uvm/env/core_ibex_env_cfg.sv,30|24): $value$plusargs -- value found '0x8ffffffc' for plusarg 'signature_addr=' does not match specified format.\r\n```\r\nThis issue can be fixed with something like atohex() SystemVerilog function (this function should be supported by all simulators).", "commit_message": "[RTL] Fix single stepping on exceptions\n\nWhen we single step over an instruction that causes an exception DPC\nshould be set to point to the exception handler (where we would have\ngone were we not single stepping).", "fix_patch": "diff --git a/rtl/ibex_controller.sv b/rtl/ibex_controller.sv\nindex 08530b1b63..07b64e35ef 100644\n--- a/rtl/ibex_controller.sv\n+++ b/rtl/ibex_controller.sv\n@@ -566,10 +566,13 @@ module ibex_controller (\n end\n end // exc_req_q\n \n- // single stepping\n- // set exception registers, but do not jump into handler [Debug Spec v0.13.2, p.44]\n+ // Entering debug mode due to either single step or debug_req. Ensure\n+ // registers are set for exception but then enter debug handler rather\n+ // than exception handler [Debug Spec v0.13.2, p.44]\n+ // Leave all other signals as is to ensure CSRs and PC get set as if\n+ // core was entering exception handler, entry to debug mode will then\n+ // see the appropriate state and setup dpc correctly.\n if (enter_debug_mode) begin\n- pc_set_o = 1'b0;\n ctrl_fsm_ns = DBG_TAKEN_IF;\n end\n end // FLUSH\n", "test_patch": "", "modified_files": ["rtl/ibex_controller.sv"], "lines_added": 6, "lines_removed": 3} +{"repo": "lowRISC/ibex", "pr_id": 377, "lang": "sv", "rtl_files": ["rtl/ibex_load_store_unit.sv"], "commit_id": "4a1806f16ffd87bded3201bc923da5317aec8210", "timestamp": "2019-10-09T09:07:08+00:00", "pr_title": "[RTL LSU] Change unaligned error behaviour", "pr_body": "- If an error is signalled in the first part of an unaligned\r\n transaction, the second part is issued anyway (to avoid a\r\n timing loop from data_err_i -> data_req_o)\r\n- Previously, the error was signalled and an exception was taken\r\n as soon as the first transaction completed. This commits makes\r\n the core wait until both transactions have completed.\r\n- This prevents strange behaviour caused by the lsu and controller\r\n being out of sync (fixes #374).", "issue_title": "DMEM fault during misaligned memory access", "issue_body": "Hi all,\r\nWhen running this set of instructions:\r\n![Screenshot from 2019-10-04 16-43-38](https://user-images.githubusercontent.com/16736281/66245995-26c70100-e6c6-11e9-8347-b284c658e62c.png)\r\nThe following waves were generated:\r\n![Screenshot from 2019-10-04 16-47-11](https://user-images.githubusercontent.com/16736281/66246078-a1901c00-e6c6-11e9-839a-a188fce292f5.png)\r\nThe `sw` instructions at `PC=0x800058d0` has a misaligned memory address, and is thus split into two internal memory transactions. In the waves, around 395,800,000ps corresponds to the memory response to the first of these two transactions, which is when the testbench randomly asserts a memory fault here. According to Ibex documentation for this situation, the second memory transaction should continue as normal, ignoring the response data, and then the core needs to also jump to the corresponding fault handler (located at `PC=0x80014000` in our case). The LSU's FSM transitions to it's error handling states from the misaligned transaction states, and the core jumps to `0x80014000` (which encodes the instruction `j 80014080`) directly after `0x800058d0`, but while executing this jump instruction, the core jumps to `0x8001e112` instead, throwing an illegal instruction exception, and then proceeds to wait for the `rvalid` corresponding to the second part of the original misaligned transaction. This occurs around 395,835,000ps, and after this, the core jumps back to the fault handler, and fully executes it. This intermediate PC of `0x8001e112` is calculated as the incorrect jump address from load address data that's already in the execution pipeline, and is muxed through due to `lsu_addr_incr_req_i` going high while waiting for the second half of the misaligned memory transaction to complete. Maybe a potential solution for this would be to only jump to the fault handler after the second part of the misaligned transactions has completed?\r\nBest,\r\nUdi", "commit_message": "[RTL LSU] Change unaligned error behaviour\n\n- If an error is signalled in the first part of an unaligned\n transaction, the second part is issued anyway (to avoid a\n timing loop from data_err_i -> data_req_o)\n- Previously, the error was signalled and an exception was taken\n as soon as the first transaction completed. This commits makes\n the core wait until both transactions have completed.\n- This prevents strange behaviour caused by the lsu and controller\n being out of sync (fixes #374).", "fix_patch": "diff --git a/rtl/ibex_load_store_unit.sv b/rtl/ibex_load_store_unit.sv\nindex c959ce2ddb..2c08892e0e 100644\n--- a/rtl/ibex_load_store_unit.sv\n+++ b/rtl/ibex_load_store_unit.sv\n@@ -42,7 +42,7 @@ module ibex_load_store_unit (\n output logic [31:0] addr_last_o, // address of last transaction -> to controller\n // -> mtval\n // -> AGU for misaligned accesses\n- output logic data_valid_o, // LSU has completed transaction -> to\n+ output logic data_valid_o, // LSU has completed transaction -> to ID/EX\n \n // exception signals\n output logic load_err_o,\n@@ -53,14 +53,16 @@ module ibex_load_store_unit (\n \n logic [31:0] data_addr;\n logic [31:0] data_addr_w_aligned;\n- logic [31:0] addr_last_q, addr_last_d;\n+ logic [31:0] addr_last_q;\n \n- logic data_update;\n- logic [31:0] rdata_q, rdata_d;\n- logic [1:0] rdata_offset_q, rdata_offset_d;\n- logic [1:0] data_type_q, data_type_d;\n- logic data_sign_ext_q, data_sign_ext_d;\n- logic data_we_q, data_we_d;\n+ logic addr_update;\n+ logic ctrl_update;\n+ logic rdata_update;\n+ logic [31:8] rdata_q;\n+ logic [1:0] rdata_offset_q;\n+ logic [1:0] data_type_q;\n+ logic data_sign_ext_q;\n+ logic data_we_q;\n \n logic [1:0] wdata_offset; // mux control for data to be written to memory\n \n@@ -76,13 +78,13 @@ module ibex_load_store_unit (\n logic split_misaligned_access;\n logic handle_misaligned_q, handle_misaligned_d; // high after receiving grant for first\n // part of a misaligned access\n- logic pmp_err_d;\n- logic pmp_err_q;\n+ logic pmp_err_q, pmp_err_d;\n+ logic lsu_err_q, lsu_err_d;\n logic data_or_pmp_err;\n \n typedef enum logic [2:0] {\n IDLE, WAIT_GNT_MIS, WAIT_RVALID_MIS, WAIT_GNT, WAIT_RVALID,\n- WAIT_GNT_ERR, WAIT_RVALID_ERR, WAIT_RVALID_DONE\n+ WAIT_RVALID_DONE\n } ls_fsm_e;\n \n ls_fsm_e ls_fsm_cs, ls_fsm_ns;\n@@ -165,40 +167,37 @@ module ibex_load_store_unit (\n // RData alignment //\n /////////////////////\n \n- // rdata_q holds data returned from memory for first part of misaligned loads\n- always_comb begin\n- rdata_d = rdata_q;\n- if (data_rvalid_i & ~data_we_q & handle_misaligned_q) begin\n- rdata_d = data_rdata_i;\n+ // register for unaligned rdata\n+ always_ff @(posedge clk_i or negedge rst_ni) begin\n+ if (!rst_ni) begin\n+ rdata_q <= '0;\n+ end else if (rdata_update) begin\n+ rdata_q <= data_rdata_i[31:8];\n end\n end\n \n- // update control signals for next read data upon receiving grant\n- // This must also be set for a pmp error (which might not actually be granted) to force\n- // data_we_q to update in order to signal the correct exception type (load or store)\n- // Note that we can use the registered pmp_err_q here since we will always take an\n- // extra cycle to progress to the RVALID state\n- assign data_update = data_gnt_i | pmp_err_q;\n-\n- assign rdata_offset_d = data_update ? data_addr[1:0] : rdata_offset_q;\n- assign data_type_d = data_update ? data_type_ex_i : data_type_q;\n- assign data_sign_ext_d = data_update ? data_sign_ext_ex_i : data_sign_ext_q;\n- assign data_we_d = data_update ? data_we_ex_i : data_we_q;\n-\n- // registers for rdata alignment and sign-extension\n+ // registers for transaction control\n always_ff @(posedge clk_i or negedge rst_ni) begin\n if (!rst_ni) begin\n- rdata_q <= '0;\n rdata_offset_q <= 2'h0;\n data_type_q <= 2'h0;\n data_sign_ext_q <= 1'b0;\n data_we_q <= 1'b0;\n- end else begin\n- rdata_q <= rdata_d;\n- rdata_offset_q <= rdata_offset_d;\n- data_type_q <= data_type_d;\n- data_sign_ext_q <= data_sign_ext_d;\n- data_we_q <= data_we_d;\n+ end else if (ctrl_update) begin\n+ rdata_offset_q <= data_addr[1:0];\n+ data_type_q <= data_type_ex_i;\n+ data_sign_ext_q <= data_sign_ext_ex_i;\n+ data_we_q <= data_we_ex_i;\n+ end\n+ end\n+\n+ // Store last address for mtval + AGU for misaligned transactions.\n+ // Do not update in case of errors, mtval needs the (first) failing address\n+ always_ff @(posedge clk_i or negedge rst_ni) begin\n+ if (!rst_ni) begin\n+ addr_last_q <= '0;\n+ end else if (addr_update) begin\n+ addr_last_q <= data_addr;\n end\n end\n \n@@ -324,6 +323,11 @@ module ibex_load_store_unit (\n handle_misaligned_d = handle_misaligned_q;\n data_or_pmp_err = 1'b0;\n pmp_err_d = pmp_err_q;\n+ lsu_err_d = lsu_err_q;\n+\n+ addr_update = 1'b0;\n+ ctrl_update = 1'b0;\n+ rdata_update = 1'b0;\n \n unique case (ls_fsm_cs)\n \n@@ -331,7 +335,10 @@ module ibex_load_store_unit (\n if (data_req_ex_i) begin\n data_req_o = 1'b1;\n pmp_err_d = data_pmp_err_i;\n+ lsu_err_d = 1'b0;\n if (data_gnt_i) begin\n+ ctrl_update = 1'b1;\n+ addr_update = 1'b1;\n handle_misaligned_d = split_misaligned_access;\n ls_fsm_ns = split_misaligned_access ? WAIT_RVALID_MIS : WAIT_RVALID;\n end else begin\n@@ -347,6 +354,8 @@ module ibex_load_store_unit (\n // pmp_err_q is only updated for new address phases and so can be used in WAIT_GNT* and\n // WAIT_RVALID* states\n if (data_gnt_i || pmp_err_q) begin\n+ addr_update = 1'b1;\n+ ctrl_update = 1'b1;\n handle_misaligned_d = 1'b1;\n ls_fsm_ns = WAIT_RVALID_MIS;\n end\n@@ -362,18 +371,14 @@ module ibex_load_store_unit (\n if (data_rvalid_i || pmp_err_q) begin\n // Update the PMP error for the second part\n pmp_err_d = data_pmp_err_i;\n- if (pmp_err_q || data_err_i) begin\n- // first part created an error, abort transaction\n- data_valid_o = 1'b1;\n- data_or_pmp_err = 1'b1;\n- handle_misaligned_d = 1'b0;\n- // If already granted, wait for second rvalid\n- ls_fsm_ns = data_gnt_i ? WAIT_RVALID_ERR : WAIT_GNT_ERR;\n-\n- end else begin\n- // No error in first part, proceed with second part\n- ls_fsm_ns = data_gnt_i ? WAIT_RVALID : WAIT_GNT;\n- end\n+ // Record the error status of the first part\n+ lsu_err_d = data_err_i | pmp_err_q;\n+ // Capture the first rdata for loads\n+ rdata_update = ~data_we_q;\n+ // If already granted, wait for second rvalid\n+ ls_fsm_ns = data_gnt_i ? WAIT_RVALID : WAIT_GNT;\n+ // Update the address for the second part, if no error\n+ addr_update = data_gnt_i & ~(data_err_i | pmp_err_q);\n \n end else begin\n // first part rvalid is NOT received\n@@ -389,15 +394,18 @@ module ibex_load_store_unit (\n addr_incr_req_o = handle_misaligned_q;\n data_req_o = 1'b1;\n if (data_gnt_i || pmp_err_q) begin\n- ls_fsm_ns = WAIT_RVALID;\n+ ctrl_update = 1'b1;\n+ // Update the address, unless there was an error\n+ addr_update = ~lsu_err_q;\n+ ls_fsm_ns = WAIT_RVALID;\n end\n end\n \n WAIT_RVALID: begin\n- data_req_o = 1'b0;\n if (data_rvalid_i || pmp_err_q) begin\n data_valid_o = 1'b1;\n- data_or_pmp_err = data_err_i | pmp_err_q;\n+ // Data error from either part\n+ data_or_pmp_err = lsu_err_q | data_err_i | pmp_err_q;\n handle_misaligned_d = 1'b0;\n ls_fsm_ns = IDLE;\n end else begin\n@@ -405,41 +413,22 @@ module ibex_load_store_unit (\n end\n end\n \n- WAIT_GNT_ERR: begin\n- // Wait for the grant of the abandoned second access\n- data_req_o = 1'b1;\n- // tell ID/EX stage to update the address\n- addr_incr_req_o = 1'b1;\n- if (pmp_err_q) begin\n- // The second part was suppressed by a PMP error\n- ls_fsm_ns = IDLE;\n- end else if (data_gnt_i) begin\n- ls_fsm_ns = WAIT_RVALID_ERR;\n- end\n- end\n-\n- WAIT_RVALID_ERR: begin\n- // Wait for the rvalid, but do nothing with it\n- if (data_rvalid_i || pmp_err_q) begin\n- ls_fsm_ns = IDLE;\n- end\n- end\n-\n WAIT_RVALID_DONE: begin\n+ // tell ID/EX stage to update the address (to make sure the\n+ // second address can be captured correctly for mtval and PMP checking)\n+ addr_incr_req_o = 1'b1;\n // Wait for the first rvalid, second request is already granted\n if (data_rvalid_i) begin\n // Update the pmp error for the second part\n pmp_err_d = data_pmp_err_i;\n // The first part cannot see a PMP error in this state\n- if (data_err_i) begin\n- // first part created an error, abort transaction and wait for second rvalid\n- data_valid_o = 1'b1;\n- data_or_pmp_err = 1'b1;\n- handle_misaligned_d = 1'b0;\n- ls_fsm_ns = WAIT_RVALID_ERR;\n- end else begin\n- ls_fsm_ns = WAIT_RVALID;\n- end\n+ lsu_err_d = data_err_i;\n+ // Now we can update the address for the second part if no error\n+ addr_update = ~data_err_i;\n+ // Capture the first rdata for loads\n+ rdata_update = ~data_we_q;\n+ // Wait for second rvalid\n+ ls_fsm_ns = WAIT_RVALID;\n end\n end\n \n@@ -449,28 +438,18 @@ module ibex_load_store_unit (\n endcase\n end\n \n- // store last address for mtval + AGU for misaligned transactions:\n- // - misaligned address needed for correct generation of data_be and data_rdata_ext\n- // - do not update in case of errors, mtval needs the failing address\n- always_comb begin\n- addr_last_d = addr_last_q;\n- if (data_req_o & data_gnt_i & ~(load_err_o | store_err_o)) begin\n- addr_last_d = data_addr;\n- end\n- end\n-\n // registers for FSM\n always_ff @(posedge clk_i or negedge rst_ni) begin\n if (!rst_ni) begin\n ls_fsm_cs <= IDLE;\n- addr_last_q <= '0;\n handle_misaligned_q <= '0;\n pmp_err_q <= '0;\n+ lsu_err_q <= '0;\n end else begin\n ls_fsm_cs <= ls_fsm_ns;\n- addr_last_q <= addr_last_d;\n handle_misaligned_q <= handle_misaligned_d;\n pmp_err_q <= pmp_err_d;\n+ lsu_err_q <= lsu_err_d;\n end\n end\n \n", "test_patch": "", "modified_files": ["rtl/ibex_load_store_unit.sv"], "lines_added": 71, "lines_removed": 92} +{"repo": "lowRISC/ibex", "pr_id": 375, "lang": "sv", "rtl_files": ["rtl/ibex_tracer.sv"], "commit_id": "d8e4852f769c197330199a7356694baaef1b1a82", "timestamp": "2019-10-06T11:56:00+00:00", "pr_title": "Tracer: Reference Verilator bug for miscompilation", "pr_body": "This miscompilation is now reported and fixed, mention it in the code to\nrefer back to it when we can revert back to the old code (which will\ntake a couple months until we can require a newer Verilator version).\n\nFixes #372", "issue_title": "Tracer: Debug miscompilation in decode_load_insn()", "issue_body": "In https://github.com/lowRISC/ibex/blob/2acb497d22a5da877a9c4350ef5693d0c767cc61/rtl/ibex_tracer.sv#L584-L613 we switched from case to if statements to get around potentially wrong behavior in Verilator. Note that the `return` in the default statement hides that the default statement is always taken; the output without the return looks even more confusing.\r\n\r\nUpstream bug report at https://www.veripool.org/issues/1536-Verilator-Misoptimization-in-if-and-case-with-default-statement-inside-a-function", "commit_message": "Tracer: Reference Verilator bug for miscompilation\n\nThis miscompilation is now reported and fixed, mention it in the code to\nrefer back to it when we can revert back to the old code (which will\ntake a couple months until we can require a newer Verilator version).\n\nFixes #372", "fix_patch": "diff --git a/rtl/ibex_tracer.sv b/rtl/ibex_tracer.sv\nindex 5d42905607..423b76d6bf 100644\n--- a/rtl/ibex_tracer.sv\n+++ b/rtl/ibex_tracer.sv\n@@ -583,7 +583,10 @@ module ibex_tracer (\n string mnemonic;\n \n /*\n- TODO: Gives wrong results in Verilator for unknown reasons. Debug what's going on.\n+ Gives wrong results in Verilator < 4.020.\n+ See https://github.com/lowRISC/ibex/issues/372 and\n+ https://www.veripool.org/issues/1536-Verilator-Misoptimization-in-if-and-case-with-default-statement-inside-a-function\n+\n unique case (rvfi_insn[14:12])\n 3'b000: mnemonic = \"lb\";\n 3'b001: mnemonic = \"lh\";\n", "test_patch": "", "modified_files": ["rtl/ibex_tracer.sv"], "lines_added": 4, "lines_removed": 1} +{"repo": "lowRISC/ibex", "pr_id": 373, "lang": "sv", "rtl_files": ["rtl/ibex_tracer.sv"], "commit_id": "2acb497d22a5da877a9c4350ef5693d0c767cc61", "timestamp": "2019-10-05T17:22:15+00:00", "pr_title": "Include rs1 and rd in trace of c.addi16sp", "pr_body": "New output looks like this:\n\n118 55 00000154 6121 c.addi16sp x2,64 x2:0x00000030 x2=0x00000070\n\nFixes #322", "issue_title": "Compressed tracer load/store issue", "issue_body": "Hi @raulbehl,\r\nI'm seeing some weird behavior with the tracer (from #262) involving long runs of compressed `lw` or `sw` instructions, below is the disassembled instruction sequence that is getting executed:\r\n![Screenshot from 2019-09-16 13-19-46](https://user-images.githubusercontent.com/16736281/64990442-afe7d680-d884-11e9-96a3-1c03d15861ca.png)\r\nAnd, below is what Ibex tracer is printing out for the exact same sequence:\r\n![Screenshot from 2019-09-16 13-20-56](https://user-images.githubusercontent.com/16736281/64990526-d3128600-d884-11e9-985a-0fb5a02ec7be.png)\r\n", "commit_message": "Include rs1 and rd in trace of c.addi16sp\n\nNew output looks like this:\n\n118 55 00000154 6121 c.addi16sp x2,64 x2:0x00000030 x2=0x00000070\n\nFixes #322", "fix_patch": "diff --git a/rtl/ibex_tracer.sv b/rtl/ibex_tracer.sv\nindex 370c66dee2..5d42905607 100644\n--- a/rtl/ibex_tracer.sv\n+++ b/rtl/ibex_tracer.sv\n@@ -488,6 +488,7 @@ module ibex_tracer (\n function void decode_ci_caddi16sp_insn(input string mnemonic);\n logic [9:0] nzimm;\n nzimm = {rvfi_insn[12], rvfi_insn[4:3], rvfi_insn[5], rvfi_insn[2], rvfi_insn[6], 4'b0};\n+ data_accessed = RS1 | RD;\n decoded_str = $sformatf(\"%s\\tx%0d,%0d\", mnemonic, rvfi_rd_addr, $signed(nzimm));\n endfunction\n \n", "test_patch": "", "modified_files": ["rtl/ibex_tracer.sv"], "lines_added": 1, "lines_removed": 0} +{"repo": "lowRISC/ibex", "pr_id": 316, "lang": "sv", "rtl_files": ["dv/riscv_compliance/rtl/bus.sv"], "commit_id": "0667c14f15612dd7c4b19aa808aef7acf59a0b21", "timestamp": "2019-09-16T12:36:24+00:00", "pr_title": "[DV] Fix latch in simple bus", "pr_body": "", "issue_title": "riscv-compliance test system: Fix arbitration error in bus", "issue_body": "@GregAC mentioned that this code\r\n\r\nhttps://github.com/lowRISC/ibex/blob/ac22439374a0bafd6fc2f9d38aefc02e44fa2abb/dv/riscv_compliance/rtl/bus.sv#L57-L64\r\n\r\ndoesn't work as expected in Verilator and gives out grants to two hosts at the same time. \r\n\r\n@GregAC can you\r\n- Double-check what the standard and other tools say should be the right behavior?\r\n- If this happens to be a bug in Verilator, file a bug report.\r\n- And possibly try to find a workaround?", "commit_message": "[DV] Fix latch in simple bus\n\nFixes #297", "fix_patch": "diff --git a/dv/riscv_compliance/rtl/bus.sv b/dv/riscv_compliance/rtl/bus.sv\nindex 4491e9e1e7..188a2b8312 100644\n--- a/dv/riscv_compliance/rtl/bus.sv\n+++ b/dv/riscv_compliance/rtl/bus.sv\n@@ -104,12 +104,13 @@ module bus #(\n \n always_comb begin\n for (integer host = 0; host < NrHosts; host = host + 1) begin\n+ host_gnt_o[host] = 1'b0;\n+\n if ($clog2(NrHosts)'(host) == host_sel_resp) begin\n host_rvalid_o[host] = device_rvalid_i[device_sel_resp];\n host_err_o[host] = device_err_i[device_sel_resp];\n host_rdata_o[host] = device_rdata_i[device_sel_resp];\n end else begin\n- host_gnt_o[host] = 1'b0;\n host_rvalid_o[host] = 1'b0;\n host_err_o[host] = 1'b0;\n host_rdata_o[host] = 'b0;\n", "test_patch": "", "modified_files": ["dv/riscv_compliance/rtl/bus.sv"], "lines_added": 2, "lines_removed": 1} +{"repo": "lowRISC/ibex", "pr_id": 302, "lang": "sv", "rtl_files": ["rtl/ibex_controller.sv"], "commit_id": "ac22439374a0bafd6fc2f9d38aefc02e44fa2abb", "timestamp": "2019-09-11T09:45:27+00:00", "pr_title": "Controller: fix `nmi_mode` default assignment", "pr_body": "Without this commit, the `nmi_mode` register is continuously cleared and set again, and the core can never handle the NMI.\r\n\r\nThis resolves lowRISC/ibex#300 reported by @udinator.", "issue_title": "Non-maskable interrupt handling", "issue_body": "Hi all,\r\nIn testing Ibex's interrupt interface, I ran into the following situation:\r\n![Screenshot from 2019-09-10 14-39-58](https://user-images.githubusercontent.com/16736281/64652505-e3d08100-d3d8-11e9-8886-8a355f31a7f7.png)\r\nI drive `irq_nm_i`, signaling a non-maskable interrupt to Ibex. Since Ibex treats interrupts as level sensitive, and relies on handler routines to deassert the interrupt lines, I treat non-maskable interrupts the same way, and leave it driven to `1'b1` until the handler code is completed. However, Ibex, after jumping into the `DECODE` state from `IRQ_TAKEN` upon detection of the `irq_nm`, seems to keep detecting that `irq_nm` is high, and then infinitely loops between the `DECODE` and `IRQ_TAKEN` states, causing the simulation to time out. Since according to #199 as well as the docs this seems to be incorrect behavior for `irq_nm`, would it be possible to clarify what expected behavior for non-maskable interrupt should be? ", "commit_message": "Controller: fix `nmi_mode` default assignment\n\nWithout this commit, the `nmi_mode` register is continuously cleared and\nset again, and the core can never handle the NMI.\n\nThis resolves lowRISC/ibex#300 reported by @udinator.", "fix_patch": "diff --git a/rtl/ibex_controller.sv b/rtl/ibex_controller.sv\nindex 1ef0fac7f6..5a8fc54a8e 100644\n--- a/rtl/ibex_controller.sv\n+++ b/rtl/ibex_controller.sv\n@@ -215,7 +215,7 @@ module ibex_controller (\n debug_csr_save_o = 1'b0;\n debug_cause_o = DBG_CAUSE_EBREAK;\n debug_mode_d = debug_mode_q;\n- nmi_mode_d = 1'b0;\n+ nmi_mode_d = nmi_mode_q;\n \n perf_tbranch_o = 1'b0;\n perf_jump_o = 1'b0;\n", "test_patch": "", "modified_files": ["rtl/ibex_controller.sv"], "lines_added": 1, "lines_removed": 1} +{"repo": "lowRISC/ibex", "pr_id": 295, "lang": "sv", "rtl_files": ["dv/uvm/common/ibex_mem_intf_agent/ibex_mem_intf_slave_driver.sv"], "commit_id": "8d3d87ae53254f7716852e944caffa788b473253", "timestamp": "2019-09-09T21:31:30+00:00", "pr_title": "Update slave_driver grant timing to pass Ibex assertion checks", "pr_body": "Update the timing of when the testbench sends grants to Ibex, partially addresses the assertion failures mentioned in #293.", "issue_title": "[I-side] - Fix issues found in tracing example", "issue_body": "- Fixes #288\r\n- Add missing grant qualification to stop spurious address updates\r\n- Make RTL robust to spurious rvalid signalling", "commit_message": "Update slave_driver grant timing to pass Ibex assertion checks", "fix_patch": "diff --git a/dv/uvm/common/ibex_mem_intf_agent/ibex_mem_intf_slave_driver.sv b/dv/uvm/common/ibex_mem_intf_agent/ibex_mem_intf_slave_driver.sv\nindex e57803ddab..2a48b9d8be 100644\n--- a/dv/uvm/common/ibex_mem_intf_agent/ibex_mem_intf_slave_driver.sv\n+++ b/dv/uvm/common/ibex_mem_intf_agent/ibex_mem_intf_slave_driver.sv\n@@ -10,9 +10,6 @@ class ibex_mem_intf_slave_driver extends uvm_driver #(ibex_mem_intf_seq_item);\n \n protected virtual ibex_mem_intf vif;\n \n- int unsigned min_grant_delay = 0;\n- int unsigned max_grant_delay = 10;\n-\n `uvm_component_utils(ibex_mem_intf_slave_driver)\n `uvm_component_new\n \n@@ -58,20 +55,15 @@ class ibex_mem_intf_slave_driver extends uvm_driver #(ibex_mem_intf_seq_item);\n join_none\n endtask : get_and_drive\n \n+ // TODO(udinator) - this direct send_grant logic is temporary until instruction fetch protocol\n+ // issue is clarified (https://github.com/lowRISC/ibex/pull/293). After resolution, will re-add\n+ // random delays insertion before driving grant to the ibex core.\n virtual protected task send_grant();\n int gnt_delay;\n forever begin\n while(vif.request !== 1'b1) begin\n @(negedge vif.clock);\n end\n- std::randomize(gnt_delay) with {\n- gnt_delay dist {\n- min_grant_delay :/ 1,\n- [min_grant_delay+1 : max_grant_delay-1] :/ 1,\n- max_grant_delay :/ 1\n- };\n- };\n- repeat(gnt_delay) @(negedge vif.clock);\n if(~vif.reset) begin\n vif.grant = 1'b1;\n @(negedge vif.clock);\n", "test_patch": "", "modified_files": ["dv/uvm/common/ibex_mem_intf_agent/ibex_mem_intf_slave_driver.sv"], "lines_added": 3, "lines_removed": 11} +{"repo": "lowRISC/ibex", "pr_id": 294, "lang": "sv", "rtl_files": ["rtl/ibex_controller.sv"], "commit_id": "b87ed7c82e0d4875ecc8bade1330a88e67f48090", "timestamp": "2019-09-09T12:05:49+00:00", "pr_title": "Controller: Fix exception cause ID of fast interrupts", "pr_body": "This commit fixes the generation of the exception cause ID of fast interrupt. Without this commit, the core tries to handle fast interrupts using the handlers of other interrupts like external, software, and timer interrupts.\r\n\r\nThis commit resolves lowRISC/ibex#290 reported by @udinator.", "issue_title": "Incorrect irq_fast ID assignment", "issue_body": "According to the documentation, Ibex should assign all of the fast interrupts `irq_fast_i[14:0]` an ID from 16 to 30, so that `irq_fast_i[0]` has an ID of 16, `irq_fast_i[1]` has an ID of 17, and so on. In the [Ibex CSR register file](https://github.com/lowRISC/ibex/blob/master/rtl/ibex_cs_registers.sv#L572), the entire 15 bit array is output to the [Ibex controller module](https://github.com/lowRISC/ibex/blob/master/rtl/ibex_controller.sv#L165), where `mfip_id` is assigned based on on the value of `irq_fast_i[14:0]`. However these assigned IDs are between 0 and 14. Later on in the controller, `exc_cause_o` is [assigned](https://github.com/lowRISC/ibex/blob/master/rtl/ibex_controller.sv#L363) by appending 1'b1 to `mfip_id`. This is sent to the [Ibex IF stage](https://github.com/lowRISC/ibex/blob/master/rtl/ibex_if_stage.sv#L109), where the 5 bit `irq_id`, which in this case is the ID assigned earlier in the controller, is multiplied by `0x4` and added to the address held in `mtvec` to get the trap address. However, the ID's of all fast interrupts are still from 0 to 14, which seems incorrect according to the RISC-V Privileged Spec Ch. 3.1.16. This means that there are now conflicts with all other interrupts that have ID's between 0 and 14, so Ibex will now jump to the wrong vectored address for all fast interrupts that are sent to the core. I think the `irq_fast` ID assignments in the CSR file should be from between 16 to 30 to fix this issue and comply with the spec.", "commit_message": "Controller: Fix exception cause ID of fast interrupts\n\nThis commit fixes the generation of the exception cause ID for fast\ninterrupts. Without this commit, the core tries to handle fast\ninterrupts using the handlers of other interrupts like external,\nsoftware, and timer interrupts.\n\nThis commit resolves lowRISC/ibex#290 reported by @udinator.", "fix_patch": "diff --git a/rtl/ibex_controller.sv b/rtl/ibex_controller.sv\nindex d61c3fddab..1ef0fac7f6 100644\n--- a/rtl/ibex_controller.sv\n+++ b/rtl/ibex_controller.sv\n@@ -113,7 +113,7 @@ module ibex_controller (\n logic enter_debug_mode;\n logic handle_irq;\n \n- logic [4:0] mfip_id;\n+ logic [3:0] mfip_id;\n logic unused_csr_mtip;\n \n `ifndef SYNTHESIS\n@@ -164,22 +164,22 @@ module ibex_controller (\n \n // generate ID of fast interrupts, highest priority to highest ID\n always_comb begin : gen_mfip_id\n- if (csr_mfip_i[14]) mfip_id = 5'd14;\n- else if (csr_mfip_i[13]) mfip_id = 5'd13;\n- else if (csr_mfip_i[12]) mfip_id = 5'd12;\n- else if (csr_mfip_i[11]) mfip_id = 5'd11;\n- else if (csr_mfip_i[10]) mfip_id = 5'd10;\n- else if (csr_mfip_i[ 9]) mfip_id = 5'd9;\n- else if (csr_mfip_i[ 8]) mfip_id = 5'd8;\n- else if (csr_mfip_i[ 7]) mfip_id = 5'd7;\n- else if (csr_mfip_i[ 6]) mfip_id = 5'd6;\n- else if (csr_mfip_i[ 5]) mfip_id = 5'd5;\n- else if (csr_mfip_i[ 5]) mfip_id = 5'd5;\n- else if (csr_mfip_i[ 4]) mfip_id = 5'd4;\n- else if (csr_mfip_i[ 3]) mfip_id = 5'd3;\n- else if (csr_mfip_i[ 2]) mfip_id = 5'd2;\n- else if (csr_mfip_i[ 1]) mfip_id = 5'd1;\n- else mfip_id = 5'd0;\n+ if (csr_mfip_i[14]) mfip_id = 4'd14;\n+ else if (csr_mfip_i[13]) mfip_id = 4'd13;\n+ else if (csr_mfip_i[12]) mfip_id = 4'd12;\n+ else if (csr_mfip_i[11]) mfip_id = 4'd11;\n+ else if (csr_mfip_i[10]) mfip_id = 4'd10;\n+ else if (csr_mfip_i[ 9]) mfip_id = 4'd9;\n+ else if (csr_mfip_i[ 8]) mfip_id = 4'd8;\n+ else if (csr_mfip_i[ 7]) mfip_id = 4'd7;\n+ else if (csr_mfip_i[ 6]) mfip_id = 4'd6;\n+ else if (csr_mfip_i[ 5]) mfip_id = 4'd5;\n+ else if (csr_mfip_i[ 5]) mfip_id = 4'd5;\n+ else if (csr_mfip_i[ 4]) mfip_id = 4'd4;\n+ else if (csr_mfip_i[ 3]) mfip_id = 4'd3;\n+ else if (csr_mfip_i[ 2]) mfip_id = 4'd2;\n+ else if (csr_mfip_i[ 1]) mfip_id = 4'd1;\n+ else mfip_id = 4'd0;\n end\n \n assign unused_csr_mtip = csr_mtip_i;\n@@ -360,7 +360,11 @@ module ibex_controller (\n exc_cause_o = EXC_CAUSE_IRQ_NM;\n nmi_mode_d = 1'b1; // enter NMI mode\n end else if (csr_mfip_i != 15'b0) begin\n- exc_cause_o = exc_cause_e'({1'b1, mfip_id});\n+ // generate exception cause ID from fast interrupt ID:\n+ // - first bit distinguishes interrupts from exceptions,\n+ // - second bit adds 16 to fast interrupt ID\n+ // for example EXC_CAUSE_IRQ_FAST_0 = {1'b1, 5'd16}\n+ exc_cause_o = exc_cause_e'({2'b11, mfip_id});\n end else if (csr_meip_i) begin\n exc_cause_o = EXC_CAUSE_IRQ_EXTERNAL_M;\n end else if (csr_msip_i) begin\n", "test_patch": "", "modified_files": ["rtl/ibex_controller.sv"], "lines_added": 22, "lines_removed": 18} +{"repo": "lowRISC/ibex", "pr_id": 289, "lang": "sv", "rtl_files": ["rtl/ibex_core_tracing.sv"], "commit_id": "60de915d6b85b61a4981263c7a7fa8fa922d3f4d", "timestamp": "2019-09-07T09:24:28+00:00", "pr_title": "Fix syntax error", "pr_body": "Fix a syntax error introduced by #284, addresses the first part of #287 ", "issue_title": "Add core_sleep_o to ibex interface (fixes #258)", "issue_body": "Signals the core is totally idle (WFI with no outstanding memory\r\ntransactions).", "commit_message": "Fix syntax error", "fix_patch": "diff --git a/rtl/ibex_core_tracing.sv b/rtl/ibex_core_tracing.sv\nindex b3cb53ca6d..7331923346 100644\n--- a/rtl/ibex_core_tracing.sv\n+++ b/rtl/ibex_core_tracing.sv\n@@ -148,7 +148,7 @@ module ibex_core_tracing #(\n .rvfi_mem_rdata,\n .rvfi_mem_wdata,\n \n- .fetch_enable_i\n+ .fetch_enable_i,\n .core_sleep_o\n );\n \n", "test_patch": "", "modified_files": ["rtl/ibex_core_tracing.sv"], "lines_added": 1, "lines_removed": 1} +{"repo": "lowRISC/ibex", "pr_id": 286, "lang": "sv", "rtl_files": ["rtl/ibex_cs_registers.sv"], "commit_id": "16177fe8db9012197c150d7487428437e020eaa6", "timestamp": "2019-09-06T14:32:16+00:00", "pr_title": "CSRs: reset `dcsr.XDEBUGVER` to `XDEBUGVER_STD` instead of 0", "pr_body": "This field is read only and should be set to the right value straight away.\r\n\r\nThis fixes lowRISC/ibex#285.", "issue_title": "Dcsr.xdebugver reset value", "issue_body": "Hi all,\r\nI noticed that in the CSR register module, `dcsr.xdebugver` is set to `XDEBUGVER_NO` upon reset, but after reset is over and an explicit write to `dcsr` occurs, the `xdebugver` field will then be permanently set to the value of `XDEBUGVER_STD` for the duration of the simulation. This seems to contradict with the behavior of the `dcsr.prv` field, which is set to `PRV_LVL_M` at reset, as well as whenever a write occurs outside of reset. Why does this separate reset behavior for `xdebugver` occur, instead of setting it to `XDEBUGVER_STD` from reset onwards especially since this field is read-only and stays as a constant?\r\nThank you!\r\nUdi", "commit_message": "CSRs: reset `dcsr.XDEBUGVER` to `XDEBUGVER_STD` instead of 0\n\nThis field is read only and should be set to the right value straight\naway.\n\nThis fixes lowRISC/ibex#285.", "fix_patch": "diff --git a/rtl/ibex_cs_registers.sv b/rtl/ibex_cs_registers.sv\nindex f65ab51c9a..d7763df226 100644\n--- a/rtl/ibex_cs_registers.sv\n+++ b/rtl/ibex_cs_registers.sv\n@@ -596,7 +596,7 @@ module ibex_cs_registers #(\n mtval_q <= '0;\n mtvec_q <= 32'b01;\n dcsr_q <= '{\n- xdebugver: XDEBUGVER_NO, // 4'h0\n+ xdebugver: XDEBUGVER_STD,\n cause: DBG_CAUSE_NONE, // 3'h0\n prv: PRIV_LVL_M,\n default: '0\n", "test_patch": "", "modified_files": ["rtl/ibex_cs_registers.sv"], "lines_added": 1, "lines_removed": 1} +{"repo": "lowRISC/ibex", "pr_id": 272, "lang": "sv", "rtl_files": ["rtl/ibex_controller.sv"], "commit_id": "68b170638ab4771623e5897d5cc44dd6f11a0872", "timestamp": "2019-08-29T10:59:05+00:00", "pr_title": "Fix behavior of DRET executed outside debug mode", "pr_body": "Executing a DRET instruction outside of debug mode now causes an illegal instruction exception as mandated by the Debug Spec v0.13.2 p.41.\r\n\r\nThis resolves lowRISC/ibex#270.", "issue_title": "DRET treated as normal instruction in M-mode", "issue_body": "![Screenshot from 2019-08-28 16-50-42](https://user-images.githubusercontent.com/16736281/63900092-46c32080-c9b4-11e9-8d3a-15851f1eefc7.png)\r\nWhile executing this code in M-mode and with no external debug/irq stimulus applied, the log shows ibex executing a dret and then jumping to `PC=0x00000000`, and the instruction at this address raises an illegal instruction exception, causing a jump to our vectored trap handler at `0x8001c000`.\r\n![Screenshot from 2019-08-28 16-51-38](https://user-images.githubusercontent.com/16736281/63900184-9a356e80-c9b4-11e9-93f6-f0410a35a79c.png)\r\nIn the waveform, we see that ibex recognizes the `dret` instruction, raising `dret_insn_dec`, but then when the core jumps to `FLUSH` state it executes the instruction as normal, and sets the next pc to `PC_DRET`, the value stored in the `dpc` CSR, or `0x00000000`. However according to the debug spec, executing `dret` while not in Debug Mode should cause an illegal instruction exception (Debug Spec, chapter 4.6), which does not seem to be the case in this situation.", "commit_message": "Controller: change behavior of DRET instruction\n\nExecuting a DRET instruction outside of debug mode now causes an\nillegal instruction exception as mandated by the Debug Spec v0.13.2\np.41.\n\nThis resolves lowRISC/ibex#270.", "fix_patch": "diff --git a/rtl/ibex_controller.sv b/rtl/ibex_controller.sv\nindex a59633c771..c7ef3e0b9c 100644\n--- a/rtl/ibex_controller.sv\n+++ b/rtl/ibex_controller.sv\n@@ -104,6 +104,8 @@ module ibex_controller (\n logic stall;\n logic halt_if;\n logic halt_id;\n+ logic illegal_dret;\n+ logic illegal_insn;\n logic exc_req;\n logic exc_req_lsu;\n logic special_req;\n@@ -119,7 +121,7 @@ module ibex_controller (\n // glitches\n always_ff @(negedge clk_i) begin\n // print warning in case of decoding errors\n- if ((ctrl_fsm_cs == DECODE) && instr_valid_i && illegal_insn_i) begin\n+ if ((ctrl_fsm_cs == DECODE) && instr_valid_i && illegal_insn) begin\n $display(\"%t: Illegal instruction (core %0d) at PC 0x%h: 0x%h\", $time, ibex_core.core_id_i,\n ibex_id_stage.pc_id_i, ibex_id_stage.instr_rdata_i);\n end\n@@ -134,8 +136,13 @@ module ibex_controller (\n assign load_err_d = load_err_i;\n assign store_err_d = store_err_i;\n \n+ // \"Executing DRET outside of Debug Mode causes an illegal instruction exception.\"\n+ // [Debug Spec v0.13.2, p.41]\n+ assign illegal_dret = dret_insn_i & ~debug_mode_q;\n+ assign illegal_insn = illegal_insn_i | illegal_dret;\n+\n // exception requests\n- assign exc_req = ecall_insn_i | ebrk_insn_i | illegal_insn_i | instr_fetch_err_i;\n+ assign exc_req = ecall_insn_i | ebrk_insn_i | illegal_insn | instr_fetch_err_i;\n \n // LSU exception requests\n assign exc_req_lsu = store_err_i | load_err_i;\n@@ -442,7 +449,7 @@ module ibex_controller (\n exc_cause_o = EXC_CAUSE_INSTR_ACCESS_FAULT;\n csr_mtval_o = pc_id_i;\n \n- end else if (illegal_insn_i) begin\n+ end else if (illegal_insn) begin\n exc_cause_o = EXC_CAUSE_ILLEGAL_INSN;\n csr_mtval_o = instr_is_compressed_i ? {16'b0, instr_compressed_i} : instr_i;\n \n", "test_patch": "", "modified_files": ["rtl/ibex_controller.sv"], "lines_added": 10, "lines_removed": 3} +{"repo": "lowRISC/ibex", "pr_id": 222, "lang": "sv", "rtl_files": ["rtl/ibex_id_stage.sv"], "commit_id": "e5bdf1ea9fd522bb345db6f7310b2c0f9253c706", "timestamp": "2019-08-06T16:04:58+00:00", "pr_title": "Fix IF stalls preventing deassertion of regfile write enable", "pr_body": "This PR makes sure the signal `instr_multicycle_done_q` is only evaluated when the decoder currently has a multicycle instruction (load/store, mult/div, branch, jump). If this signal is evaluated\r\nfor single-cycle instructions, it can prevent the reg file write enable from being de-asserted in the case of stalls due to the IF stage.\r\n\r\n@udinator: Could you please verify that this actually fixes the bug you reported in #216 before we merge it?", "issue_title": "instr_multicycle_done is not asserted, continuous register writes", "issue_body": "While executing the code shown below:\r\n![Screenshot from 2019-08-05 18-14-11](https://user-images.githubusercontent.com/16736281/62504340-e2de7b00-b7ac-11e9-8b26-0cc4090ccec3.png)\r\nWe see this incorrect behavior in the core:\r\n![Screenshot from 2019-08-05 18-13-52](https://user-images.githubusercontent.com/16736281/62504356-ee31a680-b7ac-11e9-8d28-748683269f7e.png)\r\n\r\nAs shown, the `addi` instruction at PC `0x80000088` appears to correctly load register `x13` with the value `0xa5a5a5a5`, but at the very next instruction (PC: `0x8000008c`), we can see from the trace log that `x13` now has the value `0xa5a5de17`. \r\n![Screenshot from 2019-08-05 18-12-33](https://user-images.githubusercontent.com/16736281/62504456-76b04700-b7ad-11e9-94ab-524900644a48.png)\r\n\r\nFrom the waveform, `rf_reg[13]` is written correctly by the `addi` after adding the immediate value `0x5a5` (`alu_operand_b_i`), and becomes `0xa5a5a5a5`. After this, the testbench does not assert the `instr_gnt_i` for a number of cycles, leading the core to stay in the DECODE phase while waiting for the next instruction fetch. However, we see that `rf_reg[13]` keeps getting written with the incremented values of `alu_result` in every consecutive cycle that the core waits, as `instr_multicycle_done_q` in the ID stage does not go high after the `addi` finishes. This keeps `regfile_we` at 1, causing the continuous writes.", "commit_message": "ID stage: only eval `instr_multicycle_done_q` for multi-cycle instr\n\nThis signal should only be evaluated if the ID/EX stage currently\nexecutes a multi-cycle instruction. Without this commit, the signal\nis also evaluated for single-cycle instructions and can for example\ncause the register file write enable to not be de-asserted in case of\nstalls in the IF stage.\n\nThis bug was repored by @udinator. This resolves lowrisc/ibex#216.", "fix_patch": "diff --git a/rtl/ibex_id_stage.sv b/rtl/ibex_id_stage.sv\nindex 1f8a35bb09..e6e36c487c 100644\n--- a/rtl/ibex_id_stage.sv\n+++ b/rtl/ibex_id_stage.sv\n@@ -163,6 +163,7 @@ module ibex_id_stage #(\n logic jump_set;\n \n logic instr_executing;\n+ logic instr_multicycle;\n logic instr_multicycle_done_n, instr_multicycle_done_q;\n logic stall_lsu;\n logic stall_multdiv;\n@@ -477,11 +478,14 @@ module ibex_id_stage #(\n // ID-EX/WB //\n //////////////\n \n+ assign multdiv_en_dec = mult_en_dec | div_en_dec;\n+ assign instr_multicycle = data_req_dec | multdiv_en_dec | branch_in_dec | jump_in_dec;\n+\n // Forward decoder output to EX, WB and controller only if current instr is still\n // being executed. This is the case if the current instr is either:\n // - a new instr (not yet done)\n // - a multicycle instr that is not yet done\n- assign instr_executing = (instr_new_i | ~instr_multicycle_done_q);\n+ assign instr_executing = instr_new_i | (instr_multicycle & ~instr_multicycle_done_q);\n assign data_req_id = instr_executing ? data_req_dec : 1'b0;\n assign mult_en_id = instr_executing ? mult_en_dec : 1'b0;\n assign div_en_id = instr_executing ? div_en_dec : 1'b0;\n@@ -489,6 +493,7 @@ module ibex_id_stage #(\n ///////////\n // ID-EX //\n ///////////\n+\n assign data_req_ex_o = data_req_id;\n assign data_we_ex_o = data_we_id;\n assign data_type_ex_o = data_type_id;\n@@ -531,8 +536,6 @@ module ibex_id_stage #(\n // ID-EX/WB FSM //\n //////////////////\n \n- assign multdiv_en_dec = mult_en_dec | div_en_dec;\n-\n always_comb begin : id_wb_fsm\n id_wb_fsm_ns = id_wb_fsm_cs;\n instr_multicycle_done_n = instr_multicycle_done_q;\n@@ -580,6 +583,7 @@ module ibex_id_stage #(\n instr_multicycle_done_n = 1'b0;\n end\n default: begin\n+ instr_multicycle_done_n = 1'b0;\n instr_ret_o = 1'b1;\n end\n endcase\n", "test_patch": "", "modified_files": ["rtl/ibex_id_stage.sv"], "lines_added": 7, "lines_removed": 3} +{"repo": "lowRISC/ibex", "pr_id": 196, "lang": "sv", "rtl_files": ["rtl/ibex_pkg.sv"], "commit_id": "1aa276dbc07edd925d265c9ae9c823d3833a37c1", "timestamp": "2019-07-26T10:38:10+00:00", "pr_title": "Correct cause number for illegal instruction exception", "pr_body": "This bug has beed reported by @taoliug. This resolves #195.", "issue_title": "Wrong encoding of EXC_CAUSE_ILLEGAL_INSN", "issue_body": "This issue seems to be introduced in this commit\r\nhttps://github.com/lowRISC/ibex/commit/c2fffe04406287bc7e1be3962999f0f6b44ebe87#diff-ef03dc5b772f9745e0a161472ea79c60R190\r\n\r\nEXC_CAUSE_ILLEGAL_INSN should be 2 according to RISC-V privileged mode spec", "commit_message": "Correct cause number for illegal instruction exception\n\nThis bug has beed reported by @taoliug. This resolves #195.", "fix_patch": "diff --git a/rtl/ibex_pkg.sv b/rtl/ibex_pkg.sv\nindex 819ab200b8..d65b9bedbc 100644\n--- a/rtl/ibex_pkg.sv\n+++ b/rtl/ibex_pkg.sv\n@@ -190,7 +190,7 @@ typedef enum logic [5:0] {\n // EXC_CAUSE_IRQ_FAST_14 = {1'b1, 5'd30},\n EXC_CAUSE_IRQ_NM = {1'b1, 5'd31}, // == EXC_CAUSE_IRQ_FAST_15\n EXC_CAUSE_INSN_ADDR_MISA = {1'b0, 5'd00},\n- EXC_CAUSE_ILLEGAL_INSN = {1'b0, 5'd01},\n+ EXC_CAUSE_ILLEGAL_INSN = {1'b0, 5'd02},\n EXC_CAUSE_BREAKPOINT = {1'b0, 5'd03},\n EXC_CAUSE_LOAD_ACCESS_FAULT = {1'b0, 5'd05},\n EXC_CAUSE_STORE_ACCESS_FAULT = {1'b0, 5'd07},\n", "test_patch": "", "modified_files": ["rtl/ibex_pkg.sv"], "lines_added": 1, "lines_removed": 1} +{"repo": "lowRISC/ibex", "pr_id": 176, "lang": "sv", "rtl_files": ["rtl/ibex_decoder.sv"], "commit_id": "04f4cd44f6b62a48af65f11143278be00d54132b", "timestamp": "2019-07-19T10:29:34+00:00", "pr_title": "Decoder: remove reg-reg load, make LWU illegal", "pr_body": "The custom reg-reg instruction was added in the original design but is\r\nno longer needed. This commit removes it. Also, load instructions with\r\n`instr[14:12] == 3'b110` are now decoded as illegal.\r\n\r\nThis resolves #25.", "issue_title": "Remove reg-reg loads", "issue_body": "reg-reg load (i.e., offset taken from a register and not from an immediate) should not be part of the Ibex ISA.\r\n\r\nThe code at line 261 here:\r\nhttps://github.com/lowRISC/ibex/blob/master/rtl/ibex_decoder.sv\r\n\r\nis a piece of code coming from RISCY and it should be removed.", "commit_message": "Decoder: remove reg-reg load, make LWU illegal\n\nThe custom reg-reg load instruction was added in the original design but\nis no longer needed. This commit removes it. Also, load instructions\nwith `instr[14:12] == 3'b110` are now decoded as illegal.\n\nThis resolves #25.", "fix_patch": "diff --git a/rtl/ibex_decoder.sv b/rtl/ibex_decoder.sv\nindex 7326bf0fec..7088d94eab 100644\n--- a/rtl/ibex_decoder.sv\n+++ b/rtl/ibex_decoder.sv\n@@ -299,12 +299,10 @@ module ibex_decoder #(\n \n // store size\n unique case (instr[13:12])\n- 2'b00: data_type_o = 2'b10; // SB\n- 2'b01: data_type_o = 2'b01; // SH\n- 2'b10: data_type_o = 2'b00; // SW\n- default: begin\n- illegal_insn = 1'b1;\n- end\n+ 2'b00: data_type_o = 2'b10; // SB\n+ 2'b01: data_type_o = 2'b01; // SH\n+ 2'b10: data_type_o = 2'b00; // SW\n+ default: illegal_insn = 1'b1;\n endcase\n end\n \n@@ -325,37 +323,18 @@ module ibex_decoder #(\n \n // load size\n unique case (instr[13:12])\n- 2'b00: data_type_o = 2'b10; // LB\n- 2'b01: data_type_o = 2'b01; // LH\n- 2'b10: data_type_o = 2'b00; // LW\n- default: data_type_o = 2'b00; // illegal or reg-reg\n- endcase\n-\n- // reg-reg load (different encoding)\n- if (instr[14:12] == 3'b111) begin\n- // offset from RS2\n- alu_op_b_mux_sel_o = OP_B_REG_B;\n-\n- // sign/zero extension\n- data_sign_extension_o = ~instr[30];\n-\n- // load size\n- unique case (instr[31:25])\n- 7'b0000_000,\n- 7'b0100_000: data_type_o = 2'b10; // LB, LBU\n- 7'b0001_000,\n- 7'b0101_000: data_type_o = 2'b01; // LH, LHU\n- 7'b0010_000: data_type_o = 2'b00; // LW\n- default: begin\n- illegal_insn = 1'b1;\n+ 2'b00: data_type_o = 2'b10; // LB(U)\n+ 2'b01: data_type_o = 2'b01; // LH(U)\n+ 2'b10: begin\n+ data_type_o = 2'b00; // LW\n+ if (instr[14]) begin\n+ illegal_insn = 1'b1; // LWU does not exist\n end\n- endcase\n- end\n-\n- if (instr[14:12] == 3'b011) begin\n- // LD -> RV64 only\n- illegal_insn = 1'b1;\n- end\n+ end\n+ default: begin\n+ illegal_insn = 1'b1;\n+ end\n+ endcase\n end\n \n /////////\n", "test_patch": "", "modified_files": ["rtl/ibex_decoder.sv"], "lines_added": 15, "lines_removed": 36} +{"repo": "lowRISC/ibex", "pr_id": 172, "lang": "sv", "rtl_files": ["rtl/ibex_decoder.sv"], "commit_id": "f12b94c2a21dfb4779be5c4b9c460eb3f3c48323", "timestamp": "2019-07-18T14:52:27+00:00", "pr_title": "Decoder: avoid setting PC upon illegal JALR instructions", "pr_body": "Without this commit, the PC is still set to a possible wrong jump target on illegal JALR instructions ultimately causing the wrong PC being saved to `mepc` during the illegal instruction exception.\r\n\r\nThis bug has been reported by @taoliug. This commit resolves #170.", "issue_title": "MEPC is not updated with correct value for illegal JALR instruction", "issue_body": "spike log\r\n\r\n```\r\ncore 0: 0xffffffff8000f720 (0x65d42c67) unknown\r\ncore 0: exception trap_illegal_instruction, epc 0xffffffff8000f720\r\ncore 0: tval 0x0000000000000000\r\ncore 0: 0x000000008001d000 (0x00007119) addi sp, sp, -128\r\n\r\n```\r\n0x65d42c67 is detected as illegal instruction by ibex correctly. However, seems like the core still executed the JALR instruction which causes the PC changed to some unexpected value(0x65a) and get saved to MEPC eventually.\r\n\r\nibex log:\r\n```\r\n 34443000 17123 8000f720 65d42c67 INVALID \r\n 34465000 17134 0000065a xxxxxxxx lui xx, 0xxxxxx000 \r\n```\r\n![screencapture-remotedesktop-corp-google-access-session-6fd70a76-592d-4962-9324-fb0b435c9f3d-2019-07-17-21_31_58](https://user-images.githubusercontent.com/34581368/61429489-5d695880-a8db-11e9-8493-ca7f5e4068aa.png)\r\n\r\n\r\n\r\n", "commit_message": "Decoder: avoid setting PC upon illegal JALR instructions\n\nWithout this commit, the PC is still set to a possible wrong jump\ntarget on illegal JALR instructions ultimately causing the wrong PC\nbeing saved to `mepc` during the illegal instruction exception.\n\nThis bug has been reported by @taoliug. This commit resolves #170.", "fix_patch": "diff --git a/rtl/ibex_decoder.sv b/rtl/ibex_decoder.sv\nindex 03910af64c..7326bf0fec 100644\n--- a/rtl/ibex_decoder.sv\n+++ b/rtl/ibex_decoder.sv\n@@ -602,9 +602,9 @@ module ibex_decoder #(\n end\n \n // make sure illegal instructions detected in the decoder do not propagate from decoder\n- // into register file, LSU, EX, WB, CSRs\n+ // into register file, LSU, EX, WB, CSRs, PC\n // NOTE: instructions can also be detected to be illegal inside the CSRs (upon accesses with\n- // insufficient privileges), in ID stage (when accessing Reg 16 or higher in RV32E config),\n+ // insufficient privileges), or when accessing non-available registers in RV32E,\n // these cases are not handled here\n if (illegal_insn) begin\n regfile_we = 1'b0;\n@@ -613,6 +613,7 @@ module ibex_decoder #(\n mult_en_o = 1'b0;\n div_en_o = 1'b0;\n jump_in_dec_o = 1'b0;\n+ jump_set_o = 1'b0;\n branch_in_dec_o = 1'b0;\n csr_access_o = 1'b0;\n end\n", "test_patch": "", "modified_files": ["rtl/ibex_decoder.sv"], "lines_added": 3, "lines_removed": 2} +{"repo": "lowRISC/ibex", "pr_id": 169, "lang": "sv", "rtl_files": ["rtl/ibex_id_stage.sv"], "commit_id": "f12b94c2a21dfb4779be5c4b9c460eb3f3c48323", "timestamp": "2019-07-18T10:28:14+00:00", "pr_title": "ID/EX stage: do not write to register file upon load errors", "pr_body": "This commit fixes the write back FSM to not store values returned from\r\nmemory to the register file when the LSU is reporting a load error.\r\n\r\nThis bug was reported by @ivanmgribeiro. This commit resolves #162.", "issue_title": "Load instructions that cause an error still write to registers", "issue_body": "Hi,\r\nThere seems to be a bug in Ibex when performing a read from memory which returns an error.\r\n\r\nI would expect that when the memory slave sets data_err high, the core would not write the data that was read in into a register, but it appears to still be written to the register regardless.\r\n\r\nWhat i observe is that the data is still written into the register.\r\n\r\nI'm using the following instructions:\r\n```\r\naddi r2, r0, 1\r\nlw r2, r2[2]\r\naddi r3, r2, 1\r\n```\r\nWhen using the load word instruction, the register is overwritten with 0x0, but when using load halfword or load byte, it seems to actually read what is returned by memory and store it in the register.\r\n\r\nMy memory slave is configured such that accesses outside of the range 0x80000000 - 0x80007fff will set data_err high.\r\n\r\nI've performed a fix that seemed to work locally by changing the line\r\nhttps://github.com/lowRISC/ibex/blob/b7ef64b62da74afe52bb40165e17a7e87539d47a/rtl/ibex_id_stage.sv#L283\r\nto\r\n```\r\nassign regfile_we = (illegal_csr_insn_i || !instr_executing || lsu_load_err_i) ? 1'b0 :\r\n```\r\n\r\nThis fix seems to work with other failing loads as well, but I'm not sure that it conforms to your style guide or whether it should be done here or at some other point in the code.", "commit_message": "ID/EX stage: do not write to register file upon load errors\n\nThis commit fixes the write back FSM to not store values returned from\nmemory to the register file when the LSU is reporting a load error.\n\nThis bug was reported by @ivanmgribeiro. This commit resolves #162.", "fix_patch": "diff --git a/rtl/ibex_id_stage.sv b/rtl/ibex_id_stage.sv\nindex 668a56a4d6..812282e42e 100644\n--- a/rtl/ibex_id_stage.sv\n+++ b/rtl/ibex_id_stage.sv\n@@ -622,7 +622,7 @@ module ibex_id_stage #(\n if ((data_req_dec & lsu_valid_i) | (~data_req_dec & ex_valid_i)) begin\n id_wb_fsm_ns = IDLE;\n instr_multicycle_done_n = 1'b1;\n- regfile_we_wb = regfile_we_dec;\n+ regfile_we_wb = regfile_we_dec & ~lsu_load_err_i;\n instr_ret_o = 1'b1;\n end else begin\n stall_lsu = data_req_dec;\n", "test_patch": "", "modified_files": ["rtl/ibex_id_stage.sv"], "lines_added": 1, "lines_removed": 1} +{"repo": "lowRISC/ibex", "pr_id": 167, "lang": "sv", "rtl_files": ["rtl/ibex_controller.sv"], "commit_id": "59254498489d441f64c24e6b344fce73d0d8bbce", "timestamp": "2019-07-17T10:17:38+00:00", "pr_title": "Controller: save next PC to dpc CSR upon a halt request", "pr_body": "This commit changes the controller to save the PC of the next\r\ninstruction to the dpc CSR when entering debug mode upon a halt\r\nrequest instead of the PC of the current instruction (only valid\r\nfor EBREAK instructions).\r\n\r\nThis bug was reported by @taoliug. This resolves #164.", "issue_title": "Debug request causes the same instruction to be executed twice", "issue_body": "In this test, debug_req is asserted while the core is executing instruction at PC 0x8000056a. dpc is saved to the current PC value rather than the next instruction. As a result, the instruction at 0x8000056a is executed again after exiting from debug mode(dret). \r\n\r\nibex log\r\n```\r\n 8487000 4145 8000056a 00cf9f93 slli x31, x31, 0xc x31=0x55508000 x31:0x9d655508\r\n 8595000 4199 80000040 3780e06f jal x0, 58232 \r\n 8639000 4221 8000e3b8 7b200073 dret \r\n 8683000 4243 8000056a 00cf9f93 slli x31, x31, 0xc x31=0x08000000 x31:0x55508000\r\n```\r\n![ebreak_issue](https://user-images.githubusercontent.com/34581368/61328147-46d5db00-a7cf-11e9-936b-24b943170987.png)\r\n", "commit_message": "Controller: save next PC to dpc CSR upon a halt request\n\nThis commit changes the controller to save the PC of the next\ninstruction to the dpc CSR when entering debug mode upon a halt\nrequest instead of the PC of the current instruction (only valid\nfor EBREAK instructions).\n\nThis bug was reported by @taoliug. This resolves #164.", "fix_patch": "diff --git a/rtl/ibex_controller.sv b/rtl/ibex_controller.sv\nindex d182155e2e..091a7f3c5e 100644\n--- a/rtl/ibex_controller.sv\n+++ b/rtl/ibex_controller.sv\n@@ -323,7 +323,7 @@ module ibex_controller (\n if (!stall && !special_req) begin\n if (enter_debug_mode) begin\n // enter debug mode\n- ctrl_fsm_ns = DBG_TAKEN_ID;\n+ ctrl_fsm_ns = DBG_TAKEN_IF;\n halt_if = 1'b1;\n halt_id = 1'b1;\n \n@@ -382,19 +382,17 @@ module ibex_controller (\n // enter debug mode and save PC in ID to dpc, used when encountering\n // 1. EBREAK during debug mode\n // 2. EBREAK with forced entry into debug mode (ebreakm or ebreaku set).\n- // 3. halt request during decode\n // regular ebreak's go through FLUSH.\n //\n- // for 1. do not update dcsr and dpc, for 2. and 3. do so [Debug Spec v0.13.2, p.39]\n+ // for 1. do not update dcsr and dpc, for 2. do so [Debug Spec v0.13.2, p.39]\n // jump to debug exception handler in debug memory\n- if (ebrk_insn_i || debug_req_i) begin\n+ if (ebrk_insn_i) begin\n pc_mux_o = PC_EXC;\n pc_set_o = 1'b1;\n exc_pc_mux_o = EXC_PC_DBD;\n \n // update dcsr and dpc\n- if ((ebrk_insn_i && debug_ebreakm_i && !debug_mode_q) || // ebreak with forced entry\n- (enter_debug_mode)) begin // halt request\n+ if (debug_ebreakm_i && !debug_mode_q) begin // ebreak with forced entry\n \n // dpc (set to the address of the EBREAK, i.e. set to PC in ID stage)\n csr_save_cause_o = 1'b1;\n@@ -402,11 +400,7 @@ module ibex_controller (\n \n // dcsr\n debug_csr_save_o = 1'b1;\n- if (debug_req_i) begin\n- debug_cause_o = DBG_CAUSE_HALTREQ;\n- end else begin\n- debug_cause_o = DBG_CAUSE_EBREAK;\n- end\n+ debug_cause_o = DBG_CAUSE_EBREAK;\n end\n \n // enter debug mode\n", "test_patch": "", "modified_files": ["rtl/ibex_controller.sv"], "lines_added": 5, "lines_removed": 11} +{"repo": "lowRISC/ibex", "pr_id": 166, "lang": "sv", "rtl_files": ["rtl/ibex_decoder.sv"], "commit_id": "c96ece04296c3c69df578d760aa8a66f9b886fef", "timestamp": "2019-07-17T10:04:16+00:00", "pr_title": "Decoder: fix signaling and detection of illegal instructions", "pr_body": "This commit fixes two bugs in the decoder:\r\n\r\n1. For illegal branch condition selections, the illegal instruction\r\ncondition must be signaled as long as the instruction is being executed\r\nand not just during the first cycle, as the controller cannot interrupt\r\nmulticycle instructions.\r\n\r\n2. Illegal instructions should also be signaled when `instr[28]` is set\r\nfor register-register ALU operations. Previously, these were not\r\nsignaled as the original design used `instr[28]` to encode custom bit-\r\nmanipulation instructions.\r\n\r\nThese bugs were discovered by @taoliug. This resolves issue #163.", "issue_title": "7d10b363 is not decoded as illegal instruction", "issue_body": "Based on the RISC-V instruction encoding, 7d10b363 doesn't map to any legal instruction. The trace log shows the instruction as INVALID. However, the id_stage doesn't assert the illegal_insn signal, and the core continues executing the instructions without jump to exception handling routine. Looks like the core can only detect illegal compressed instructions and illegal CSR instructions.\r\n\r\nSpike log\r\n\r\n```\r\ncore 0: 0xffffffff8000faaa (0x7d10b363) unknown\r\ncore 0: exception trap_illegal_instruction, epc 0xffffffff8000faaa\r\ncore 0: tval 0x0000000000000000\r\ncore 0: 0x000000008001d000 (0x00007119) addi sp, sp, -128\r\n```\r\n\r\nibex log\r\n```\r\n 22039000 10921 8000faa8 40b6d693 srai x13, x13, 0x40b x13=0x00000000 x13:0x00000000\r\n 22041000 10922 8000faaa 7d10b363 INVALID \r\n 22047000 10925 8000faae 001d0d13 addi x26, x26, 1 x26=0x5fab433a x26:0x5fab4339\r\n\r\n```", "commit_message": "Decoder: fix signaling and detection of illegal instructions\n\nThis commit fixes two bugs in the decoder:\n\n1. For illegal branch condition selections, the illegal instruction\ncondition must be signaled as long as the instruction is being executed\nand not just during the first cycle, as the controller cannot interrupt\nmulticycle instructions.\n\n2. Illegal instructions should also be signaled when `instr[28]` is set\nfor register-register ALU operations. Previously, these were not\nsignaled as the original design used `instr[28]` to encode custom bit-\nmanipulation instructions.\n\nThese bugs were discovered by @taoliug. This resolves issue #163.", "fix_patch": "diff --git a/rtl/ibex_decoder.sv b/rtl/ibex_decoder.sv\nindex 468f9ffba3..03910af64c 100644\n--- a/rtl/ibex_decoder.sv\n+++ b/rtl/ibex_decoder.sv\n@@ -253,19 +253,20 @@ module ibex_decoder #(\n \n OPCODE_BRANCH: begin // Branch\n branch_in_dec_o = 1'b1;\n+ // Check branch condition selection\n+ unique case (instr[14:12])\n+ 3'b000: alu_operator_o = ALU_EQ;\n+ 3'b001: alu_operator_o = ALU_NE;\n+ 3'b100: alu_operator_o = ALU_LT;\n+ 3'b101: alu_operator_o = ALU_GE;\n+ 3'b110: alu_operator_o = ALU_LTU;\n+ 3'b111: alu_operator_o = ALU_GEU;\n+ default: illegal_insn = 1'b1;\n+ endcase\n if (instr_new_i) begin\n // Evaluate branch condition\n alu_op_a_mux_sel_o = OP_A_REG_A;\n alu_op_b_mux_sel_o = OP_B_REG_B;\n- unique case (instr[14:12])\n- 3'b000: alu_operator_o = ALU_EQ;\n- 3'b001: alu_operator_o = ALU_NE;\n- 3'b100: alu_operator_o = ALU_LT;\n- 3'b101: alu_operator_o = ALU_GE;\n- 3'b110: alu_operator_o = ALU_LTU;\n- 3'b111: alu_operator_o = ALU_GEU;\n- default: illegal_insn = 1'b1;\n- endcase\n end else begin\n // Calculate jump target in EX\n alu_op_a_mux_sel_o = OP_A_CURRPC;\n@@ -422,7 +423,7 @@ module ibex_decoder #(\n \n if (instr[31]) begin\n illegal_insn = 1'b1;\n- end else if (!instr[28]) begin // non bit-manipulation instructions\n+ end else begin\n unique case ({instr[30:25], instr[14:12]})\n // RV32I ALU operations\n {6'b00_0000, 3'b000}: alu_operator_o = ALU_ADD; // Add\n", "test_patch": "", "modified_files": ["rtl/ibex_decoder.sv"], "lines_added": 11, "lines_removed": 10} +{"repo": "lowRISC/ibex", "pr_id": 157, "lang": "sv", "rtl_files": ["rtl/ibex_controller.sv"], "commit_id": "c4370083106042cc0398de615e69d661032c04ba", "timestamp": "2019-07-15T17:37:34+00:00", "pr_title": "Fix dpc CSR not updated", "pr_body": "This PR lets the core also check `debug_req_i` and `debug_single_step_i` while entering debug mode to avoid entering debug mode without setting up the debug CSRs properly (which anyway depend on these signals), if these signals go low during the procedure.\r\n\r\nThis resolves #153 .", "issue_title": "dpc is not updated properly if debug_req_i is a one cycle pulse", "issue_body": "As you can see from below waveform, debug_req_i is modeled as a pulse interrupt which is only asserted for one cycle. ibex can enter debug mode and start fetching instructions from DmHaltAddr. However, dpc is not updated properly (keep at default value 0). I cannot find in the RISC-V debug spec that whether the halt request should be a level or pulse signal, can you help to clarify? \r\n\r\n![screencapture-remotedesktop-corp-google-access-session-6fd70a76-592d-4962-9324-fb0b435c9f3d-2019-07-14-16_45_08](https://user-images.githubusercontent.com/34581368/61190801-d86e0d00-a656-11e9-98e2-4a928cc92108.png)\r\n", "commit_message": "Update ibex_controller.sv", "fix_patch": "diff --git a/rtl/ibex_controller.sv b/rtl/ibex_controller.sv\nindex 573189c2b0..a0c6c49600 100644\n--- a/rtl/ibex_controller.sv\n+++ b/rtl/ibex_controller.sv\n@@ -358,24 +358,24 @@ module ibex_controller (\n DBG_TAKEN_IF: begin\n // enter debug mode and save PC in IF to dpc\n // jump to debug exception handler in debug memory\n- pc_mux_o = PC_EXC;\n- pc_set_o = 1'b1;\n- exc_pc_mux_o = EXC_PC_DBD;\n+ if (debug_single_step_i || debug_req_i) begin\n+ pc_mux_o = PC_EXC;\n+ pc_set_o = 1'b1;\n+ exc_pc_mux_o = EXC_PC_DBD;\n \n- csr_save_if_o = 1'b1;\n- debug_csr_save_o = 1'b1;\n+ csr_save_if_o = 1'b1;\n+ debug_csr_save_o = 1'b1;\n \n- csr_save_cause_o = 1'b1;\n- if (debug_single_step_i) begin\n- debug_cause_o = DBG_CAUSE_STEP;\n- end else if (debug_req_i) begin\n- debug_cause_o = DBG_CAUSE_HALTREQ;\n- end else if (ebrk_insn_i) begin\n- debug_cause_o = DBG_CAUSE_EBREAK;\n- end\n+ csr_save_cause_o = 1'b1;\n+ if (debug_single_step_i) begin\n+ debug_cause_o = DBG_CAUSE_STEP;\n+ end else begin\n+ debug_cause_o = DBG_CAUSE_HALTREQ;\n+ end\n \n- // enter debug mode\n- debug_mode_d = 1'b1;\n+ // enter debug mode\n+ debug_mode_d = 1'b1;\n+ end\n \n ctrl_fsm_ns = DECODE;\n end\n@@ -389,29 +389,31 @@ module ibex_controller (\n //\n // for 1. do not update dcsr and dpc, for 2. and 3. do so [Debug Spec v0.13.2, p.39]\n // jump to debug exception handler in debug memory\n- pc_mux_o = PC_EXC;\n- pc_set_o = 1'b1;\n- exc_pc_mux_o = EXC_PC_DBD;\n-\n- // update dcsr and dpc\n- if ((ebrk_insn_i && debug_ebreakm_i && !debug_mode_q) || // ebreak with forced entry\n- (enter_debug_mode)) begin // halt request\n-\n- // dpc (set to the address of the EBREAK, i.e. set to PC in ID stage)\n- csr_save_cause_o = 1'b1;\n- csr_save_id_o = 1'b1;\n-\n- // dcsr\n- debug_csr_save_o = 1'b1;\n- if (debug_req_i) begin\n- debug_cause_o = DBG_CAUSE_HALTREQ;\n- end else if (ebrk_insn_i) begin\n- debug_cause_o = DBG_CAUSE_EBREAK;\n+ if (ebrk_insn_i || debug_req_i) begin\n+ pc_mux_o = PC_EXC;\n+ pc_set_o = 1'b1;\n+ exc_pc_mux_o = EXC_PC_DBD;\n+\n+ // update dcsr and dpc\n+ if ((ebrk_insn_i && debug_ebreakm_i && !debug_mode_q) || // ebreak with forced entry\n+ (enter_debug_mode)) begin // halt request\n+\n+ // dpc (set to the address of the EBREAK, i.e. set to PC in ID stage)\n+ csr_save_cause_o = 1'b1;\n+ csr_save_id_o = 1'b1;\n+\n+ // dcsr\n+ debug_csr_save_o = 1'b1;\n+ if (debug_req_i) begin\n+ debug_cause_o = DBG_CAUSE_HALTREQ;\n+ end else begin\n+ debug_cause_o = DBG_CAUSE_EBREAK;\n+ end\n end\n- end\n \n- // enter debug mode\n- debug_mode_d = 1'b1;\n+ // enter debug mode\n+ debug_mode_d = 1'b1;\n+ end\n \n ctrl_fsm_ns = DECODE;\n end\n", "test_patch": "", "modified_files": ["rtl/ibex_controller.sv"], "lines_added": 38, "lines_removed": 36} +{"repo": "lowRISC/ibex", "pr_id": 131, "lang": "sv", "rtl_files": ["rtl/ibex_decoder.sv"], "commit_id": "33b7904a124b39e78481eb3176c062e182bce5de", "timestamp": "2019-07-10T14:24:22+00:00", "pr_title": "Decoder: fix drive conflict, set `jump_set_o` for JALR", "pr_body": "This PR solves problems reported by @jeanlouismaquet in #130.", "issue_title": "Problem when the value of opcode FSM is OPCODE_JALR", "issue_body": "Hello,\r\n\r\nWith the new file ibex_decoder.sv (5093e0a), when the opcode FSM = OPCODE_JALR, the pc_mux_o FSM stays at PC_BOOT value. Normally, the pc_mux_o FSM must toogle to PC_JUMP value.\r\nI created a zip file containing:\r\n ibex_28may19.log : result from the ibex_tracer module. No problem \r\n ibex_last_version.log : result from the ibex_tracer module : problem line 43 (jalr)\r\n waves_AES_CBC_old.wlf : waveform (modelsim) : pc_mux_o signal : PC_JUMP -> PC_BOOT -> PC_JUMP -> PC_BOOT \r\n waves_AES_CBC_new.wlf : waveform (modelsim) : problem (pc_mux_o : PCPC_JUMP -> PC_BOOT) \r\n ibex_new_jalr.png printscreen of waveform (version with _**problem)**_\r\n ibex_old_jalr.png printscreen of waveform (correct version)\r\n\r\nSolution : In ibex_decoder.sv, after the line 239, add the following line:\r\n **_jump_set_o = 1'b1;_**\r\n\r\nRemark: During compilation of ibex_decoder.sv file with modelsim, I obtain the following error:\r\n **_Error (suppressible): (vlog-12003) /cad/projects/eSecure/jlm4/design/digital/modules/esecure_cpu/macro/IP_ibex/sources/hdl/ibex_decoder.sv(623): Variable 'illegal_insn_o' written by continuous and procedural assignments. See /cad/projects/eSecure/jlm4/design/digital/modules/esecure_cpu/macro/IP_ibex/sources/hdl/ibex_decoder.sv(554)._** \r\n\r\nSolution : At line 553 : change the **_illegal_insn_o_** signal by **_illegal_insn_**.\r\n\r\nDespite the addition of the line **_jump_set_o = 1'b1;_** , my simulation still has errors.\r\nI'm debugging this new problem.\r\n\r\nBest regards,\r\n\r\nJean-Louis\r\n[problem_ibex_jalr.zip](https://github.com/lowRISC/ibex/files/3377638/problem_ibex_jalr.zip)\r\n\r\n", "commit_message": "Decoder: fix drive conflict, set `jump_set_o` for JALR\n\nThis commit solves problems reported by @jeanlouismaquet in #130.", "fix_patch": "diff --git a/rtl/ibex_decoder.sv b/rtl/ibex_decoder.sv\nindex 6eee408791..30df485f99 100644\n--- a/rtl/ibex_decoder.sv\n+++ b/rtl/ibex_decoder.sv\n@@ -237,6 +237,7 @@ module ibex_decoder #(\n imm_b_mux_sel_o = IMM_B_I;\n alu_operator_o = ALU_ADD;\n regfile_we = 1'b0;\n+ jump_set_o = 1'b1;\n end else begin\n // Calculate and store PC+4\n alu_op_a_mux_sel_o = OP_A_CURRPC;\n@@ -550,7 +551,7 @@ module ibex_decoder #(\n \n // rs1 and rd must be 0\n if (instr[`REG_S1] || instr[`REG_D]) begin\n- illegal_insn_o = 1'b1;\n+ illegal_insn = 1'b1;\n end\n end else begin\n // instruction to read/modify CSR\n", "test_patch": "", "modified_files": ["rtl/ibex_decoder.sv"], "lines_added": 2, "lines_removed": 1} +{"repo": "lowRISC/ibex", "pr_id": 113, "lang": "sv", "rtl_files": ["rtl/ibex_core.sv"], "commit_id": "2d66834f14647e5d6fa753fbe0710f3014c3811a", "timestamp": "2019-07-01T16:57:00+00:00", "pr_title": "Switch to new signal name in tracer instantiation", "pr_body": "This got forgotten when renaming the signal inside ID stage in\r\ncommit b22a6a10defc7bad31dda7d8a33c7145d1a79a3b.\r\n\r\nThis fixes #112 .", "issue_title": "ibex compilation issue: is_compressed_i ", "issue_body": "I am getting this error while compiling ibex with VCS, PTAL. Looks like the port is renamed.\r\n\r\nError-[XMRE] Cross-module reference resolution error\r\n/usr/local/google/home/taliu/ibex/ibex/rtl/ibex_core.sv, 766\r\n Error found while trying to resolve cross-module reference.\r\n token 'is_compressed_i'. Originating module 'ibex_core'.\r\n Source info: .compressed_i (id_stage_i.is_compressed_i)\r\n", "commit_message": "Switch to new signal name in tracer instantiation\n\nThis got forgotten when renaming the signal inside ID stage in\ncommit b22a6a10defc7bad31dda7d8a33c7145d1a79a3b.", "fix_patch": "diff --git a/rtl/ibex_core.sv b/rtl/ibex_core.sv\nindex c4a5acb925..450b5c8859 100644\n--- a/rtl/ibex_core.sv\n+++ b/rtl/ibex_core.sv\n@@ -763,7 +763,7 @@ module ibex_core #(\n \n .pc_i ( id_stage_i.pc_id_i ),\n .instr_i ( id_stage_i.instr ),\n- .compressed_i ( id_stage_i.is_compressed_i ),\n+ .compressed_i ( id_stage_i.instr_is_compressed_i ),\n .id_valid_i ( id_stage_i.id_valid_o ),\n .is_decoding_i ( id_stage_i.is_decoding_o ),\n .is_branch_i ( id_stage_i.branch_in_id ),\n", "test_patch": "", "modified_files": ["rtl/ibex_core.sv"], "lines_added": 1, "lines_removed": 1} +{"repo": "lowRISC/ibex", "pr_id": 54, "lang": "sv", "rtl_files": ["rtl/ibex_compressed_decoder.sv"], "commit_id": "cd15ce88beba8ed8496f414af361f664764f47e2", "timestamp": "2019-05-31T16:26:20+00:00", "pr_title": "Fix decoding of C.LI, C.LUI, C.SRLI, C.SRAI, C.SSLI", "pr_body": "Hints encoded in these compressed instructions must decode into hints\r\nin the corresponding base instructions. This resolves #51.", "issue_title": "HINT instruction decoding issue - 0x7065", "issue_body": "Based on the spec, it should be decoded as HINT instruction (C.LUI, rd == 0), but it's decoded as illegal instruction by design incorrectly.\r\nhttps://github.com/lowRISC/ibex/blob/master/rtl/ibex_compressed_decoder.sv#L105\r\n\r\n```\r\n 3'b011: begin\r\n // c.lui -> lui rd, imm\r\n instr_o = {{15 {instr_i[12]}}, instr_i[6:2], instr_i[11:7], {OPCODE_LUI}};\r\n\r\n if (instr_i[11:7] == 5'h02) begin\r\n // c.addi16sp -> addi x2, x2, nzimm\r\n instr_o = {{3 {instr_i[12]}}, instr_i[4:3], instr_i[5], instr_i[2],\r\n instr_i[6], 4'b0, 5'h02, 3'b000, 5'h02, {OPCODE_OPIMM}};\r\n end else if (instr_i[11:7] == 5'b0) begin // this is INCORRECT\r\n illegal_instr_o = 1'b1;\r\n end\r\n\r\n if ({instr_i[12], instr_i[6:2]} == 6'b0) illegal_instr_o = 1'b1;\r\n end\r\n```\r\n", "commit_message": "Fix decoding of C.LI, C.LUI, C.SRLI, C.SRAI, C.SSLI\n\nHints encoded in these compressed instructions must decode into hints\nin the corresponding base instructions. This resolves #51.", "fix_patch": "diff --git a/rtl/ibex_compressed_decoder.sv b/rtl/ibex_compressed_decoder.sv\nindex d0b31dd7a0..536d384398 100644\n--- a/rtl/ibex_compressed_decoder.sv\n+++ b/rtl/ibex_compressed_decoder.sv\n@@ -88,21 +88,20 @@ module ibex_compressed_decoder (\n \n 3'b010: begin\n // c.li -> addi rd, x0, nzimm\n+ // (c.li hints are translated into an addi hint)\n instr_o = {{6 {instr_i[12]}}, instr_i[12], instr_i[6:2], 5'b0,\n 3'b0, instr_i[11:7], {OPCODE_OPIMM}};\n- if (instr_i[11:7] == 5'b0) illegal_instr_o = 1'b1;\n end\n \n 3'b011: begin\n // c.lui -> lui rd, imm\n+ // (c.lui hints are translated into a lui hint)\n instr_o = {{15 {instr_i[12]}}, instr_i[6:2], instr_i[11:7], {OPCODE_LUI}};\n \n if (instr_i[11:7] == 5'h02) begin\n // c.addi16sp -> addi x2, x2, nzimm\n instr_o = {{3 {instr_i[12]}}, instr_i[4:3], instr_i[5], instr_i[2],\n instr_i[6], 4'b0, 5'h02, 3'b000, 5'h02, {OPCODE_OPIMM}};\n- end else if (instr_i[11:7] == 5'b0) begin\n- illegal_instr_o = 1'b1;\n end\n \n if ({instr_i[12], instr_i[6:2]} == 6'b0) illegal_instr_o = 1'b1;\n@@ -114,10 +113,10 @@ module ibex_compressed_decoder (\n 2'b01: begin\n // 00: c.srli -> srli rd, rd, shamt\n // 01: c.srai -> srai rd, rd, shamt\n+ // (c.srli/c.srai hints are translated into a srli/srai hint)\n instr_o = {1'b0, instr_i[10], 5'b0, instr_i[6:2], 2'b01, instr_i[9:7],\n 3'b101, 2'b01, instr_i[9:7], {OPCODE_OPIMM}};\n if (instr_i[12] == 1'b1) illegal_instr_o = 1'b1;\n- if (instr_i[6:2] == 5'b0) illegal_instr_o = 1'b1;\n end\n \n 2'b10: begin\n@@ -192,9 +191,9 @@ module ibex_compressed_decoder (\n unique case (instr_i[15:13])\n 3'b000: begin\n // c.slli -> slli rd, rd, shamt\n+ // (c.ssli hints are translated into a slli hint)\n instr_o = {7'b0, instr_i[6:2], instr_i[11:7], 3'b001, instr_i[11:7], {OPCODE_OPIMM}};\n- if (instr_i[11:7] == 5'b0) illegal_instr_o = 1'b1;\n- if (instr_i[12] == 1'b1 || instr_i[6:2] == 5'b0) illegal_instr_o = 1'b1;\n+ if (instr_i[12] == 1'b1) illegal_instr_o = 1'b1; // reserved for custom extensions\n end\n \n 3'b010: begin\n", "test_patch": "", "modified_files": ["rtl/ibex_compressed_decoder.sv"], "lines_added": 5, "lines_removed": 6} +{"repo": "lowRISC/ibex", "pr_id": 48, "lang": "sv", "rtl_files": ["rtl/ibex_compressed_decoder.sv"], "commit_id": "145269fdc88e1d545fca692fd3e3a43c99e1ac12", "timestamp": "2019-05-23T09:05:04+00:00", "pr_title": "Compressed hints", "pr_body": "Fix handling of HINTs in compressed instructions. \r\n\r\nFixes #46 (and a bit more)\r\n\r\n\r\n@taoliug can you re-test with these modifications?\r\n@asb does my reading of the spec sound about right?", "issue_title": "Evaluate the feasibility of parameterising ibex by XLEN", "issue_body": "It could be interesting to support RV64I as well as RV32I (imagine small helper cores, with access to the same address space as a larger 64-bit application cores). Before leaping into doing this, someone needs to do the ground work to see how disruptive it might be, so we can evaluate the potential maintenance / readability costs vs the benefits of supporting an RV64I configuration.", "commit_message": "Fix handling of C.MV and C.JR\n\n- Decoding must give precedence to rs2 (i.e. instr_i[6:2]) to\n switch between C.MV and C.JR.\n \"C.MV is only valid when rs2̸=x0; the code points with rs2=x0\n correspond to the C.JR instruction. The code points with rs2̸=x0\n and rd=x0 are HINTs.\"\n\n- C.JR is only valid with rs1==x0. Throw an illegal instruction\n exception if that's not the case.\n \"C.JR is only valid when rs1̸=x0; the code point with rs1=x0\n is reserved.\" RV32 Spec, p103\n\nAll spec references based on RISC-V Unprivileged ISA\nV20190305-Base-Ratification", "fix_patch": "diff --git a/rtl/ibex_compressed_decoder.sv b/rtl/ibex_compressed_decoder.sv\nindex 1fac9d559f..d0b31dd7a0 100644\n--- a/rtl/ibex_compressed_decoder.sv\n+++ b/rtl/ibex_compressed_decoder.sv\n@@ -206,24 +206,28 @@ module ibex_compressed_decoder (\n \n 3'b100: begin\n if (instr_i[12] == 1'b0) begin\n- // c.mv -> add rd/rs1, x0, rs2\n- instr_o = {7'b0, instr_i[6:2], 5'b0, 3'b0, instr_i[11:7], {OPCODE_OP}};\n-\n- if (instr_i[6:2] == 5'b0) begin\n+ if (instr_i[6:2] != 5'b0) begin\n+ // c.mv -> add rd/rs1, x0, rs2\n+ // (c.mv hints are translated into an add hint)\n+ instr_o = {7'b0, instr_i[6:2], 5'b0, 3'b0, instr_i[11:7], {OPCODE_OP}};\n+ end else begin\n // c.jr -> jalr x0, rd/rs1, 0\n instr_o = {12'b0, instr_i[11:7], 3'b0, 5'b0, {OPCODE_JALR}};\n+ if (instr_i[11:7] == 5'b0) illegal_instr_o = 1'b1;\n end\n end else begin\n- // c.add -> add rd, rd, rs2\n- instr_o = {7'b0, instr_i[6:2], instr_i[11:7], 3'b0, instr_i[11:7], {OPCODE_OP}};\n-\n- if (instr_i[11:7] == 5'b0) begin\n- // c.ebreak -> ebreak\n- instr_o = {32'h00_10_00_73};\n- if (instr_i[6:2] != 5'b0) illegal_instr_o = 1'b1;\n- end else if (instr_i[6:2] == 5'b0) begin\n- // c.jalr -> jalr x1, rs1, 0\n- instr_o = {12'b0, instr_i[11:7], 3'b000, 5'b00001, {OPCODE_JALR}};\n+ if (instr_i[6:2] != 5'b0) begin\n+ // c.add -> add rd, rd, rs2\n+ // (c.add hints are translated into an add hint)\n+ instr_o = {7'b0, instr_i[6:2], instr_i[11:7], 3'b0, instr_i[11:7], {OPCODE_OP}};\n+ end else begin\n+ if (instr_i[11:7] == 5'b0) begin\n+ // c.ebreak -> ebreak\n+ instr_o = {32'h00_10_00_73};\n+ end else begin\n+ // c.jalr -> jalr x1, rs1, 0\n+ instr_o = {12'b0, instr_i[11:7], 3'b000, 5'b00001, {OPCODE_JALR}};\n+ end\n end\n end\n end\n", "test_patch": "", "modified_files": ["rtl/ibex_compressed_decoder.sv"], "lines_added": 18, "lines_removed": 14} +{"repo": "lowRISC/ibex", "pr_id": 40, "lang": "sv", "rtl_files": ["rtl/ibex_id_stage.sv"], "commit_id": "e87d0cc3e9225ed29cb6a89ccace2a5fe284a677", "timestamp": "2019-05-15T16:55:20+00:00", "pr_title": "Fix synthesis ikarageo", "pr_body": "Replaces #38 as the other one seemed to be messed up by GitHub", "issue_title": "Fix unsynthesizable construct and missing signal for tracer", "issue_body": "- Synthesis tools throw warnings with system task $stop. \r\n- Functionality of tracer broke after commit 53f2fb935030eee131e4d927f6890295f86344ac", "commit_message": "Restore functionality of tracer\n\nTracer functionality is broken after transition to ibex. \"operand_b_fw_id\" is missing from instruction decoder.", "fix_patch": "diff --git a/rtl/ibex_id_stage.sv b/rtl/ibex_id_stage.sv\nindex 93c16c4054..4ba1f90e99 100644\n--- a/rtl/ibex_id_stage.sv\n+++ b/rtl/ibex_id_stage.sv\n@@ -227,6 +227,7 @@ module ibex_id_stage #(\n op_fw_sel_e operand_a_fw_mux_sel;\n \n logic [31:0] operand_a_fw_id;\n+ logic [31:0] operand_b_fw_id;\n \n logic [31:0] alu_operand_a;\n logic [31:0] alu_operand_b;\n@@ -304,6 +305,7 @@ module ibex_id_stage #(\n \n // ALU_Op_b Mux\n assign alu_operand_b = (alu_op_b_mux_sel == OP_B_IMM) ? imm_b : regfile_data_rb_id;\n+ assign operand_b_fw_id = regfile_data_rb_id;\n \n ///////////////\n // Registers //\n@@ -645,7 +647,7 @@ module ibex_id_stage #(\n // make sure that branch decision is valid when jumping\n assert property (\n @(posedge clk_i) (branch_decision_i !== 1'bx || branch_in_id == 1'b0) ) else begin\n- $display(\"Branch decision is X\"); $stop; end\n+ $display(\"Branch decision is X\"); end\n \n `ifdef CHECK_MISALIGNED\n assert property (\n", "test_patch": "", "modified_files": ["rtl/ibex_id_stage.sv"], "lines_added": 3, "lines_removed": 1}