family_id stringlengths 9 26 | category stringclasses 12
values | description stringlengths 45 312 | rtl_variant stringclasses 8
values | rtl stringlengths 485 3.54k | spec_json stringlengths 3.12k 7.04k | properties_sva stringlengths 830 2.79k | properties_json stringlengths 1.19k 3.69k | mutants_json stringlengths 1.57k 8.14k |
|---|---|---|---|---|---|---|---|---|
arbiter_0001 | arbiter | A two-request fixed-priority arbiter. Request 0 has priority over request 1 when both are asserted. Grants are mutually exclusive and last for one cycle. | canonical_case.sv | module arbiter_0001_canonical_case (
input wire clk,
input wire rst,
input wire req0,
input wire req1,
output reg grant0,
output reg grant1
);
localparam [1:0] IDLE = 2'd0;
localparam [1:0] GRANT0 = 2'd1;
localparam [1:0] GRANT1 = 2'd2;
reg [1:0] state, next_state;
a... | {
"design_id": "arbiter_0001",
"category": "arbiter",
"template": "two_request_fixed_priority",
"description": "A two-request fixed-priority arbiter. Request 0 has priority over request 1 when both are asserted. Grants are mutually exclusive and last for one cycle.",
"clock": {
"name": "clk",
"edge": ... | // Generated from spec.json.
// Design: arbiter_0001
// P1_MUTUAL_EXCLUSION: the arbiter never grants both requesters at the same time.
p_mutual_exclusion: assert property (@(posedge clk) disable iff (rst)
!(grant0 && grant1));
// P2_RESET_NO_GRANT: reset clears both grants.
p_reset_no_grant: assert property (@(p... | [
{
"id": "P1_MUTUAL_EXCLUSION",
"type": "invariant",
"natural_language": "the arbiter never grants both requesters at the same time",
"disable": "rst",
"expression": "!(grant0 && grant1)"
},
{
"id": "P2_RESET_NO_GRANT",
"type": "next_cycle_implication",
"natural_language": "reset ... | {"grant0_stuck.sv": "module arbiter_0001_mutant_grant0_stuck (\n input wire clk,\n input wire rst,\n input wire req0,\n input wire req1,\n output reg grant0,\n output reg grant1\n);\n localparam [1:0] IDLE = 2'd0;\n localparam [1:0] GRANT0 = 2'd1;\n localparam [1:0] GRANT1 = 2'd2;\n\n ... |
arbiter_0001 | arbiter | A two-request fixed-priority arbiter. Request 0 has priority over request 1 when both are asserted. Grants are mutually exclusive and last for one cycle. | onehot_case.sv | module arbiter_0001_onehot_case (
input wire clk,
input wire rst,
input wire req0,
input wire req1,
output reg grant0,
output reg grant1
);
localparam [2:0] IDLE = 3'b001;
localparam [2:0] GRANT0 = 3'b010;
localparam [2:0] GRANT1 = 3'b100;
reg [2:0] state, next_state;
... | {
"design_id": "arbiter_0001",
"category": "arbiter",
"template": "two_request_fixed_priority",
"description": "A two-request fixed-priority arbiter. Request 0 has priority over request 1 when both are asserted. Grants are mutually exclusive and last for one cycle.",
"clock": {
"name": "clk",
"edge": ... | // Generated from spec.json.
// Design: arbiter_0001
// P1_MUTUAL_EXCLUSION: the arbiter never grants both requesters at the same time.
p_mutual_exclusion: assert property (@(posedge clk) disable iff (rst)
!(grant0 && grant1));
// P2_RESET_NO_GRANT: reset clears both grants.
p_reset_no_grant: assert property (@(p... | [
{
"id": "P1_MUTUAL_EXCLUSION",
"type": "invariant",
"natural_language": "the arbiter never grants both requesters at the same time",
"disable": "rst",
"expression": "!(grant0 && grant1)"
},
{
"id": "P2_RESET_NO_GRANT",
"type": "next_cycle_implication",
"natural_language": "reset ... | {"grant0_stuck.sv": "module arbiter_0001_mutant_grant0_stuck (\n input wire clk,\n input wire rst,\n input wire req0,\n input wire req1,\n output reg grant0,\n output reg grant1\n);\n localparam [1:0] IDLE = 2'd0;\n localparam [1:0] GRANT0 = 2'd1;\n localparam [1:0] GRANT1 = 2'd2;\n\n ... |
arbiter_0001 | arbiter | A two-request fixed-priority arbiter. Request 0 has priority over request 1 when both are asserted. Grants are mutually exclusive and last for one cycle. | nested_if.sv | module arbiter_0001_nested_if (
input wire clk,
input wire rst,
input wire req0,
input wire req1,
output wire grant0,
output wire grant1
);
localparam [1:0] S_IDLE = 2'd0;
localparam [1:0] S_GRANT0 = 2'd1;
localparam [1:0] S_GRANT1 = 2'd2;
reg [1:0] state;
always @(po... | {
"design_id": "arbiter_0001",
"category": "arbiter",
"template": "two_request_fixed_priority",
"description": "A two-request fixed-priority arbiter. Request 0 has priority over request 1 when both are asserted. Grants are mutually exclusive and last for one cycle.",
"clock": {
"name": "clk",
"edge": ... | // Generated from spec.json.
// Design: arbiter_0001
// P1_MUTUAL_EXCLUSION: the arbiter never grants both requesters at the same time.
p_mutual_exclusion: assert property (@(posedge clk) disable iff (rst)
!(grant0 && grant1));
// P2_RESET_NO_GRANT: reset clears both grants.
p_reset_no_grant: assert property (@(p... | [
{
"id": "P1_MUTUAL_EXCLUSION",
"type": "invariant",
"natural_language": "the arbiter never grants both requesters at the same time",
"disable": "rst",
"expression": "!(grant0 && grant1)"
},
{
"id": "P2_RESET_NO_GRANT",
"type": "next_cycle_implication",
"natural_language": "reset ... | {"grant0_stuck.sv": "module arbiter_0001_mutant_grant0_stuck (\n input wire clk,\n input wire rst,\n input wire req0,\n input wire req1,\n output reg grant0,\n output reg grant1\n);\n localparam [1:0] IDLE = 2'd0;\n localparam [1:0] GRANT0 = 2'd1;\n localparam [1:0] GRANT1 = 2'd2;\n\n ... |
arbiter_0001 | arbiter | A two-request fixed-priority arbiter. Request 0 has priority over request 1 when both are asserted. Grants are mutually exclusive and last for one cycle. | factored_flags.sv | module arbiter_0001_factored_flags (
input wire clk,
input wire rst,
input wire req0,
input wire req1,
output reg grant0,
output reg grant1
);
localparam [1:0] F_IDLE = 2'd0;
localparam [1:0] F_GRANT0 = 2'd1;
localparam [1:0] F_GRANT1 = 2'd2;
reg [1:0] ... | {
"design_id": "arbiter_0001",
"category": "arbiter",
"template": "two_request_fixed_priority",
"description": "A two-request fixed-priority arbiter. Request 0 has priority over request 1 when both are asserted. Grants are mutually exclusive and last for one cycle.",
"clock": {
"name": "clk",
"edge": ... | // Generated from spec.json.
// Design: arbiter_0001
// P1_MUTUAL_EXCLUSION: the arbiter never grants both requesters at the same time.
p_mutual_exclusion: assert property (@(posedge clk) disable iff (rst)
!(grant0 && grant1));
// P2_RESET_NO_GRANT: reset clears both grants.
p_reset_no_grant: assert property (@(p... | [
{
"id": "P1_MUTUAL_EXCLUSION",
"type": "invariant",
"natural_language": "the arbiter never grants both requesters at the same time",
"disable": "rst",
"expression": "!(grant0 && grant1)"
},
{
"id": "P2_RESET_NO_GRANT",
"type": "next_cycle_implication",
"natural_language": "reset ... | {"grant0_stuck.sv": "module arbiter_0001_mutant_grant0_stuck (\n input wire clk,\n input wire rst,\n input wire req0,\n input wire req1,\n output reg grant0,\n output reg grant1\n);\n localparam [1:0] IDLE = 2'd0;\n localparam [1:0] GRANT0 = 2'd1;\n localparam [1:0] GRANT1 = 2'd2;\n\n ... |
arbiter_0002 | arbiter | A two-request fixed-priority arbiter with held grants. Request 0 has priority when both requests arrive while idle. Once granted, ownership is retained until the winning requester deasserts its request. | canonical_case.sv | module arbiter_0002_canonical_case (
input wire clk,
input wire rst,
input wire req0,
input wire req1,
output reg grant0,
output reg grant1
);
localparam [1:0] IDLE = 2'd0;
localparam [1:0] GRANT0 = 2'd1;
localparam [1:0] GRANT1 = 2'd2;
reg [1:0] state, next_state;
a... | {
"design_id": "arbiter_0002",
"category": "arbiter",
"template": "held_grant_fixed_priority",
"description": "A two-request fixed-priority arbiter with held grants. Request 0 has priority when both requests arrive while idle. Once granted, ownership is retained until the winning requester deasserts its request... | // Generated from spec.json.
// Design: arbiter_0002
// P1_MUTUAL_EXCLUSION: the arbiter never grants both requesters simultaneously.
p_mutual_exclusion: assert property (@(posedge clk) disable iff (rst)
!(grant0 && grant1));
// P2_RESET_NO_GRANT: reset clears both grants.
p_reset_no_grant: assert property (@(pos... | [
{
"id": "P1_MUTUAL_EXCLUSION",
"type": "invariant",
"natural_language": "the arbiter never grants both requesters simultaneously",
"disable": "rst",
"expression": "!(grant0 && grant1)"
},
{
"id": "P2_RESET_NO_GRANT",
"type": "next_cycle_implication",
"natural_language": "reset cl... | {"drop_grant0.sv": "module arbiter_0002_mutant_drop_grant0 (\n input wire clk,\n input wire rst,\n input wire req0,\n input wire req1,\n output reg grant0,\n output reg grant1\n);\n localparam [1:0] IDLE = 2'd0;\n localparam [1:0] GRANT0 = 2'd1;\n localparam [1:0] GRANT1 = 2'd2;\n\n ... |
arbiter_0002 | arbiter | A two-request fixed-priority arbiter with held grants. Request 0 has priority when both requests arrive while idle. Once granted, ownership is retained until the winning requester deasserts its request. | onehot_case.sv | module arbiter_0002_onehot_case (
input wire clk,
input wire rst,
input wire req0,
input wire req1,
output reg grant0,
output reg grant1
);
localparam [2:0] IDLE = 3'b001;
localparam [2:0] GRANT0 = 3'b010;
localparam [2:0] GRANT1 = 3'b100;
reg [2:0] state, next_state;
... | {
"design_id": "arbiter_0002",
"category": "arbiter",
"template": "held_grant_fixed_priority",
"description": "A two-request fixed-priority arbiter with held grants. Request 0 has priority when both requests arrive while idle. Once granted, ownership is retained until the winning requester deasserts its request... | // Generated from spec.json.
// Design: arbiter_0002
// P1_MUTUAL_EXCLUSION: the arbiter never grants both requesters simultaneously.
p_mutual_exclusion: assert property (@(posedge clk) disable iff (rst)
!(grant0 && grant1));
// P2_RESET_NO_GRANT: reset clears both grants.
p_reset_no_grant: assert property (@(pos... | [
{
"id": "P1_MUTUAL_EXCLUSION",
"type": "invariant",
"natural_language": "the arbiter never grants both requesters simultaneously",
"disable": "rst",
"expression": "!(grant0 && grant1)"
},
{
"id": "P2_RESET_NO_GRANT",
"type": "next_cycle_implication",
"natural_language": "reset cl... | {"drop_grant0.sv": "module arbiter_0002_mutant_drop_grant0 (\n input wire clk,\n input wire rst,\n input wire req0,\n input wire req1,\n output reg grant0,\n output reg grant1\n);\n localparam [1:0] IDLE = 2'd0;\n localparam [1:0] GRANT0 = 2'd1;\n localparam [1:0] GRANT1 = 2'd2;\n\n ... |
arbiter_0002 | arbiter | A two-request fixed-priority arbiter with held grants. Request 0 has priority when both requests arrive while idle. Once granted, ownership is retained until the winning requester deasserts its request. | nested_if.sv | module arbiter_0002_nested_if (
input wire clk,
input wire rst,
input wire req0,
input wire req1,
output wire grant0,
output wire grant1
);
localparam [1:0] S_IDLE = 2'd0;
localparam [1:0] S_GRANT0 = 2'd1;
localparam [1:0] S_GRANT1 = 2'd2;
reg [1:0] state;
always @(po... | {
"design_id": "arbiter_0002",
"category": "arbiter",
"template": "held_grant_fixed_priority",
"description": "A two-request fixed-priority arbiter with held grants. Request 0 has priority when both requests arrive while idle. Once granted, ownership is retained until the winning requester deasserts its request... | // Generated from spec.json.
// Design: arbiter_0002
// P1_MUTUAL_EXCLUSION: the arbiter never grants both requesters simultaneously.
p_mutual_exclusion: assert property (@(posedge clk) disable iff (rst)
!(grant0 && grant1));
// P2_RESET_NO_GRANT: reset clears both grants.
p_reset_no_grant: assert property (@(pos... | [
{
"id": "P1_MUTUAL_EXCLUSION",
"type": "invariant",
"natural_language": "the arbiter never grants both requesters simultaneously",
"disable": "rst",
"expression": "!(grant0 && grant1)"
},
{
"id": "P2_RESET_NO_GRANT",
"type": "next_cycle_implication",
"natural_language": "reset cl... | {"drop_grant0.sv": "module arbiter_0002_mutant_drop_grant0 (\n input wire clk,\n input wire rst,\n input wire req0,\n input wire req1,\n output reg grant0,\n output reg grant1\n);\n localparam [1:0] IDLE = 2'd0;\n localparam [1:0] GRANT0 = 2'd1;\n localparam [1:0] GRANT1 = 2'd2;\n\n ... |
arbiter_0002 | arbiter | A two-request fixed-priority arbiter with held grants. Request 0 has priority when both requests arrive while idle. Once granted, ownership is retained until the winning requester deasserts its request. | factored_flags.sv | module arbiter_0002_factored_flags (
input wire clk,
input wire rst,
input wire req0,
input wire req1,
output reg grant0,
output reg grant1
);
localparam [1:0] F_IDLE = 2'd0;
localparam [1:0] F_GRANT0 = 2'd1;
localparam [1:0] F_GRANT1 = 2'd2;
reg [1:0] ... | {
"design_id": "arbiter_0002",
"category": "arbiter",
"template": "held_grant_fixed_priority",
"description": "A two-request fixed-priority arbiter with held grants. Request 0 has priority when both requests arrive while idle. Once granted, ownership is retained until the winning requester deasserts its request... | // Generated from spec.json.
// Design: arbiter_0002
// P1_MUTUAL_EXCLUSION: the arbiter never grants both requesters simultaneously.
p_mutual_exclusion: assert property (@(posedge clk) disable iff (rst)
!(grant0 && grant1));
// P2_RESET_NO_GRANT: reset clears both grants.
p_reset_no_grant: assert property (@(pos... | [
{
"id": "P1_MUTUAL_EXCLUSION",
"type": "invariant",
"natural_language": "the arbiter never grants both requesters simultaneously",
"disable": "rst",
"expression": "!(grant0 && grant1)"
},
{
"id": "P2_RESET_NO_GRANT",
"type": "next_cycle_implication",
"natural_language": "reset cl... | {"drop_grant0.sv": "module arbiter_0002_mutant_drop_grant0 (\n input wire clk,\n input wire rst,\n input wire req0,\n input wire req1,\n output reg grant0,\n output reg grant1\n);\n localparam [1:0] IDLE = 2'd0;\n localparam [1:0] GRANT0 = 2'd1;\n localparam [1:0] GRANT1 = 2'd2;\n\n ... |
arbiter_0003 | arbiter | A two-request fixed-priority arbiter with held ownership and direct handoff. Request 0 has priority while idle. A grant remains asserted while its requester remains active. When the current requester releases, ownership transfers directly to a waiting competing requester without an idle cycle. | canonical_case.sv | module arbiter_0003_canonical_case (
input wire clk,
input wire rst,
input wire req0,
input wire req1,
output reg grant0,
output reg grant1
);
localparam [1:0] IDLE = 2'd0;
localparam [1:0] GRANT0 = 2'd1;
localparam [1:0] GRANT1 = 2'd2;
reg [1:0] state, next_state;
a... | {
"design_id": "arbiter_0003",
"category": "arbiter",
"template": "held_grant_direct_handoff",
"description": "A two-request fixed-priority arbiter with held ownership and direct handoff. Request 0 has priority while idle. A grant remains asserted while its requester remains active. When the current requester r... | // Generated from spec.json.
// Design: arbiter_0003
// P1_MUTUAL_EXCLUSION: the arbiter never grants both requesters simultaneously.
p_mutual_exclusion: assert property (@(posedge clk) disable iff (rst)
!(grant0 && grant1));
// P2_RESET_NO_GRANT: reset clears both grants.
p_reset_no_grant: assert property (@(pos... | [
{
"id": "P1_MUTUAL_EXCLUSION",
"type": "invariant",
"natural_language": "the arbiter never grants both requesters simultaneously",
"disable": "rst",
"expression": "!(grant0 && grant1)"
},
{
"id": "P2_RESET_NO_GRANT",
"type": "next_cycle_implication",
"natural_language": "reset cl... | {"bubble_after_grant0.sv": "module arbiter_0003_mutant_bubble_after_grant0 (\n input wire clk,\n input wire rst,\n input wire req0,\n input wire req1,\n output reg grant0,\n output reg grant1\n);\n localparam [1:0] IDLE = 2'd0;\n localparam [1:0] GRANT0 = 2'd1;\n localparam [1:0] GRANT... |
arbiter_0003 | arbiter | A two-request fixed-priority arbiter with held ownership and direct handoff. Request 0 has priority while idle. A grant remains asserted while its requester remains active. When the current requester releases, ownership transfers directly to a waiting competing requester without an idle cycle. | onehot_case.sv | module arbiter_0003_onehot_case (
input wire clk,
input wire rst,
input wire req0,
input wire req1,
output reg grant0,
output reg grant1
);
localparam [2:0] IDLE = 3'b001;
localparam [2:0] GRANT0 = 3'b010;
localparam [2:0] GRANT1 = 3'b100;
reg [2:0] state, next_state;
... | {
"design_id": "arbiter_0003",
"category": "arbiter",
"template": "held_grant_direct_handoff",
"description": "A two-request fixed-priority arbiter with held ownership and direct handoff. Request 0 has priority while idle. A grant remains asserted while its requester remains active. When the current requester r... | // Generated from spec.json.
// Design: arbiter_0003
// P1_MUTUAL_EXCLUSION: the arbiter never grants both requesters simultaneously.
p_mutual_exclusion: assert property (@(posedge clk) disable iff (rst)
!(grant0 && grant1));
// P2_RESET_NO_GRANT: reset clears both grants.
p_reset_no_grant: assert property (@(pos... | [
{
"id": "P1_MUTUAL_EXCLUSION",
"type": "invariant",
"natural_language": "the arbiter never grants both requesters simultaneously",
"disable": "rst",
"expression": "!(grant0 && grant1)"
},
{
"id": "P2_RESET_NO_GRANT",
"type": "next_cycle_implication",
"natural_language": "reset cl... | {"bubble_after_grant0.sv": "module arbiter_0003_mutant_bubble_after_grant0 (\n input wire clk,\n input wire rst,\n input wire req0,\n input wire req1,\n output reg grant0,\n output reg grant1\n);\n localparam [1:0] IDLE = 2'd0;\n localparam [1:0] GRANT0 = 2'd1;\n localparam [1:0] GRANT... |
arbiter_0003 | arbiter | A two-request fixed-priority arbiter with held ownership and direct handoff. Request 0 has priority while idle. A grant remains asserted while its requester remains active. When the current requester releases, ownership transfers directly to a waiting competing requester without an idle cycle. | nested_if.sv | module arbiter_0003_nested_if (
input wire clk,
input wire rst,
input wire req0,
input wire req1,
output wire grant0,
output wire grant1
);
localparam [1:0] S_IDLE = 2'd0;
localparam [1:0] S_GRANT0 = 2'd1;
localparam [1:0] S_GRANT1 = 2'd2;
reg [1:0] state;
always @(po... | {
"design_id": "arbiter_0003",
"category": "arbiter",
"template": "held_grant_direct_handoff",
"description": "A two-request fixed-priority arbiter with held ownership and direct handoff. Request 0 has priority while idle. A grant remains asserted while its requester remains active. When the current requester r... | // Generated from spec.json.
// Design: arbiter_0003
// P1_MUTUAL_EXCLUSION: the arbiter never grants both requesters simultaneously.
p_mutual_exclusion: assert property (@(posedge clk) disable iff (rst)
!(grant0 && grant1));
// P2_RESET_NO_GRANT: reset clears both grants.
p_reset_no_grant: assert property (@(pos... | [
{
"id": "P1_MUTUAL_EXCLUSION",
"type": "invariant",
"natural_language": "the arbiter never grants both requesters simultaneously",
"disable": "rst",
"expression": "!(grant0 && grant1)"
},
{
"id": "P2_RESET_NO_GRANT",
"type": "next_cycle_implication",
"natural_language": "reset cl... | {"bubble_after_grant0.sv": "module arbiter_0003_mutant_bubble_after_grant0 (\n input wire clk,\n input wire rst,\n input wire req0,\n input wire req1,\n output reg grant0,\n output reg grant1\n);\n localparam [1:0] IDLE = 2'd0;\n localparam [1:0] GRANT0 = 2'd1;\n localparam [1:0] GRANT... |
arbiter_0003 | arbiter | A two-request fixed-priority arbiter with held ownership and direct handoff. Request 0 has priority while idle. A grant remains asserted while its requester remains active. When the current requester releases, ownership transfers directly to a waiting competing requester without an idle cycle. | factored_flags.sv | module arbiter_0003_factored_flags (
input wire clk,
input wire rst,
input wire req0,
input wire req1,
output reg grant0,
output reg grant1
);
localparam [1:0] F_IDLE = 2'd0;
localparam [1:0] F_GRANT0 = 2'd1;
localparam [1:0] F_GRANT1 = 2'd2;
reg [1:0] ... | {
"design_id": "arbiter_0003",
"category": "arbiter",
"template": "held_grant_direct_handoff",
"description": "A two-request fixed-priority arbiter with held ownership and direct handoff. Request 0 has priority while idle. A grant remains asserted while its requester remains active. When the current requester r... | // Generated from spec.json.
// Design: arbiter_0003
// P1_MUTUAL_EXCLUSION: the arbiter never grants both requesters simultaneously.
p_mutual_exclusion: assert property (@(posedge clk) disable iff (rst)
!(grant0 && grant1));
// P2_RESET_NO_GRANT: reset clears both grants.
p_reset_no_grant: assert property (@(pos... | [
{
"id": "P1_MUTUAL_EXCLUSION",
"type": "invariant",
"natural_language": "the arbiter never grants both requesters simultaneously",
"disable": "rst",
"expression": "!(grant0 && grant1)"
},
{
"id": "P2_RESET_NO_GRANT",
"type": "next_cycle_implication",
"natural_language": "reset cl... | {"bubble_after_grant0.sv": "module arbiter_0003_mutant_bubble_after_grant0 (\n input wire clk,\n input wire rst,\n input wire req0,\n input wire req1,\n output reg grant0,\n output reg grant1\n);\n localparam [1:0] IDLE = 2'd0;\n localparam [1:0] GRANT0 = 2'd1;\n localparam [1:0] GRANT... |
arbiter_0004 | arbiter | A two-request arbiter that alternates priority under sustained contention. Request 0 has initial priority from idle. After granting one requester, the other requester receives priority on the next arbitration cycle. If all requests disappear, the arbiter returns to idle and initial priority resets to request 0. | canonical_case.sv | module arbiter_0004_canonical_case (
input wire clk,
input wire rst,
input wire req0,
input wire req1,
output reg grant0,
output reg grant1
);
localparam [1:0] IDLE = 2'd0;
localparam [1:0] GRANT0 = 2'd1;
localparam [1:0] GRANT1 = 2'd2;
reg [1:0] state, next_state;
a... | {
"design_id": "arbiter_0004",
"category": "arbiter",
"template": "alternating_round_robin",
"description": "A two-request arbiter that alternates priority under sustained contention. Request 0 has initial priority from idle. After granting one requester, the other requester receives priority on the next arbitr... | // Generated from spec.json.
// Design: arbiter_0004
// P1_MUTUAL_EXCLUSION: the arbiter never grants both requesters simultaneously.
p_mutual_exclusion: assert property (@(posedge clk) disable iff (rst)
!(grant0 && grant1));
// P2_RESET_NO_GRANT: reset clears both grants.
p_reset_no_grant: assert property (@(pos... | [
{
"id": "P1_MUTUAL_EXCLUSION",
"type": "invariant",
"natural_language": "the arbiter never grants both requesters simultaneously",
"disable": "rst",
"expression": "!(grant0 && grant1)"
},
{
"id": "P2_RESET_NO_GRANT",
"type": "next_cycle_implication",
"natural_language": "reset cl... | {"grant0_stuck.sv": "module arbiter_0004_mutant_grant0_stuck (\n input wire clk,\n input wire rst,\n input wire req0,\n input wire req1,\n output reg grant0,\n output reg grant1\n);\n localparam [1:0] IDLE = 2'd0;\n localparam [1:0] GRANT0 = 2'd1;\n localparam [1:0] GRANT1 = 2'd2;\n\n ... |
arbiter_0004 | arbiter | A two-request arbiter that alternates priority under sustained contention. Request 0 has initial priority from idle. After granting one requester, the other requester receives priority on the next arbitration cycle. If all requests disappear, the arbiter returns to idle and initial priority resets to request 0. | onehot_case.sv | module arbiter_0004_onehot_case (
input wire clk,
input wire rst,
input wire req0,
input wire req1,
output reg grant0,
output reg grant1
);
localparam [2:0] IDLE = 3'b001;
localparam [2:0] GRANT0 = 3'b010;
localparam [2:0] GRANT1 = 3'b100;
reg [2:0] state, next_state;
... | {
"design_id": "arbiter_0004",
"category": "arbiter",
"template": "alternating_round_robin",
"description": "A two-request arbiter that alternates priority under sustained contention. Request 0 has initial priority from idle. After granting one requester, the other requester receives priority on the next arbitr... | // Generated from spec.json.
// Design: arbiter_0004
// P1_MUTUAL_EXCLUSION: the arbiter never grants both requesters simultaneously.
p_mutual_exclusion: assert property (@(posedge clk) disable iff (rst)
!(grant0 && grant1));
// P2_RESET_NO_GRANT: reset clears both grants.
p_reset_no_grant: assert property (@(pos... | [
{
"id": "P1_MUTUAL_EXCLUSION",
"type": "invariant",
"natural_language": "the arbiter never grants both requesters simultaneously",
"disable": "rst",
"expression": "!(grant0 && grant1)"
},
{
"id": "P2_RESET_NO_GRANT",
"type": "next_cycle_implication",
"natural_language": "reset cl... | {"grant0_stuck.sv": "module arbiter_0004_mutant_grant0_stuck (\n input wire clk,\n input wire rst,\n input wire req0,\n input wire req1,\n output reg grant0,\n output reg grant1\n);\n localparam [1:0] IDLE = 2'd0;\n localparam [1:0] GRANT0 = 2'd1;\n localparam [1:0] GRANT1 = 2'd2;\n\n ... |
arbiter_0004 | arbiter | A two-request arbiter that alternates priority under sustained contention. Request 0 has initial priority from idle. After granting one requester, the other requester receives priority on the next arbitration cycle. If all requests disappear, the arbiter returns to idle and initial priority resets to request 0. | nested_if.sv | module arbiter_0004_nested_if (
input wire clk,
input wire rst,
input wire req0,
input wire req1,
output wire grant0,
output wire grant1
);
localparam [1:0] S_IDLE = 2'd0;
localparam [1:0] S_GRANT0 = 2'd1;
localparam [1:0] S_GRANT1 = 2'd2;
reg [1:0] state;
always @(po... | {
"design_id": "arbiter_0004",
"category": "arbiter",
"template": "alternating_round_robin",
"description": "A two-request arbiter that alternates priority under sustained contention. Request 0 has initial priority from idle. After granting one requester, the other requester receives priority on the next arbitr... | // Generated from spec.json.
// Design: arbiter_0004
// P1_MUTUAL_EXCLUSION: the arbiter never grants both requesters simultaneously.
p_mutual_exclusion: assert property (@(posedge clk) disable iff (rst)
!(grant0 && grant1));
// P2_RESET_NO_GRANT: reset clears both grants.
p_reset_no_grant: assert property (@(pos... | [
{
"id": "P1_MUTUAL_EXCLUSION",
"type": "invariant",
"natural_language": "the arbiter never grants both requesters simultaneously",
"disable": "rst",
"expression": "!(grant0 && grant1)"
},
{
"id": "P2_RESET_NO_GRANT",
"type": "next_cycle_implication",
"natural_language": "reset cl... | {"grant0_stuck.sv": "module arbiter_0004_mutant_grant0_stuck (\n input wire clk,\n input wire rst,\n input wire req0,\n input wire req1,\n output reg grant0,\n output reg grant1\n);\n localparam [1:0] IDLE = 2'd0;\n localparam [1:0] GRANT0 = 2'd1;\n localparam [1:0] GRANT1 = 2'd2;\n\n ... |
arbiter_0004 | arbiter | A two-request arbiter that alternates priority under sustained contention. Request 0 has initial priority from idle. After granting one requester, the other requester receives priority on the next arbitration cycle. If all requests disappear, the arbiter returns to idle and initial priority resets to request 0. | factored_flags.sv | module arbiter_0004_factored_flags (
input wire clk,
input wire rst,
input wire req0,
input wire req1,
output reg grant0,
output reg grant1
);
localparam [1:0] F_IDLE = 2'd0;
localparam [1:0] F_GRANT0 = 2'd1;
localparam [1:0] F_GRANT1 = 2'd2;
reg [1:0] ... | {
"design_id": "arbiter_0004",
"category": "arbiter",
"template": "alternating_round_robin",
"description": "A two-request arbiter that alternates priority under sustained contention. Request 0 has initial priority from idle. After granting one requester, the other requester receives priority on the next arbitr... | // Generated from spec.json.
// Design: arbiter_0004
// P1_MUTUAL_EXCLUSION: the arbiter never grants both requesters simultaneously.
p_mutual_exclusion: assert property (@(posedge clk) disable iff (rst)
!(grant0 && grant1));
// P2_RESET_NO_GRANT: reset clears both grants.
p_reset_no_grant: assert property (@(pos... | [
{
"id": "P1_MUTUAL_EXCLUSION",
"type": "invariant",
"natural_language": "the arbiter never grants both requesters simultaneously",
"disable": "rst",
"expression": "!(grant0 && grant1)"
},
{
"id": "P2_RESET_NO_GRANT",
"type": "next_cycle_implication",
"natural_language": "reset cl... | {"grant0_stuck.sv": "module arbiter_0004_mutant_grant0_stuck (\n input wire clk,\n input wire rst,\n input wire req0,\n input wire req1,\n output reg grant0,\n output reg grant1\n);\n localparam [1:0] IDLE = 2'd0;\n localparam [1:0] GRANT0 = 2'd1;\n localparam [1:0] GRANT1 = 2'd2;\n\n ... |
arbiter_0005 | arbiter | A three-request fixed-priority arbiter. Request 0 has highest priority, followed by request 1 and then request 2. Grants are mutually exclusive and last for one cycle. | canonical_case.sv | module arbiter_0005_canonical_case (
input wire clk,
input wire rst,
input wire req0,
input wire req1,
input wire req2,
output reg grant0,
output reg grant1,
output reg grant2
);
localparam [1:0] IDLE = 2'd0;
localparam [1:0] GRANT0 = 2'd1;
localparam [1:0] GRANT1 = ... | {
"design_id": "arbiter_0005",
"category": "arbiter",
"template": "three_request_fixed_priority",
"description": "A three-request fixed-priority arbiter. Request 0 has highest priority, followed by request 1 and then request 2. Grants are mutually exclusive and last for one cycle.",
"clock": {
"name": "cl... | // Generated from spec.json.
// Design: arbiter_0005
// P1_MUTUAL_EXCLUSION: at most one requester is granted at a time.
p_mutual_exclusion: assert property (@(posedge clk) disable iff (rst)
!((grant0 && grant1) || (grant0 && grant2) || (grant1 && grant2)));
// P2_RESET_NO_GRANT: reset clears every grant.
p_reset... | [
{
"id": "P1_MUTUAL_EXCLUSION",
"type": "invariant",
"natural_language": "at most one requester is granted at a time",
"disable": "rst",
"expression": "!((grant0 && grant1) || (grant0 && grant2) || (grant1 && grant2))"
},
{
"id": "P2_RESET_NO_GRANT",
"type": "next_cycle_implication",
... | {"grant2_stuck.sv": "module arbiter_0005_mutant_grant2_stuck (\n input wire clk,\n input wire rst,\n input wire req0,\n input wire req1,\n input wire req2,\n output reg grant0,\n output reg grant1,\n output reg grant2\n);\n localparam [1:0] IDLE = 2'd0;\n localparam [1:0] GRANT0 =... |
arbiter_0005 | arbiter | A three-request fixed-priority arbiter. Request 0 has highest priority, followed by request 1 and then request 2. Grants are mutually exclusive and last for one cycle. | onehot_case.sv | module arbiter_0005_onehot_case (
input wire clk,
input wire rst,
input wire req0,
input wire req1,
input wire req2,
output reg grant0,
output reg grant1,
output reg grant2
);
localparam [3:0] IDLE = 4'b0001;
localparam [3:0] GRANT0 = 4'b0010;
localparam [3:0] GRANT1... | {
"design_id": "arbiter_0005",
"category": "arbiter",
"template": "three_request_fixed_priority",
"description": "A three-request fixed-priority arbiter. Request 0 has highest priority, followed by request 1 and then request 2. Grants are mutually exclusive and last for one cycle.",
"clock": {
"name": "cl... | // Generated from spec.json.
// Design: arbiter_0005
// P1_MUTUAL_EXCLUSION: at most one requester is granted at a time.
p_mutual_exclusion: assert property (@(posedge clk) disable iff (rst)
!((grant0 && grant1) || (grant0 && grant2) || (grant1 && grant2)));
// P2_RESET_NO_GRANT: reset clears every grant.
p_reset... | [
{
"id": "P1_MUTUAL_EXCLUSION",
"type": "invariant",
"natural_language": "at most one requester is granted at a time",
"disable": "rst",
"expression": "!((grant0 && grant1) || (grant0 && grant2) || (grant1 && grant2))"
},
{
"id": "P2_RESET_NO_GRANT",
"type": "next_cycle_implication",
... | {"grant2_stuck.sv": "module arbiter_0005_mutant_grant2_stuck (\n input wire clk,\n input wire rst,\n input wire req0,\n input wire req1,\n input wire req2,\n output reg grant0,\n output reg grant1,\n output reg grant2\n);\n localparam [1:0] IDLE = 2'd0;\n localparam [1:0] GRANT0 =... |
arbiter_0005 | arbiter | A three-request fixed-priority arbiter. Request 0 has highest priority, followed by request 1 and then request 2. Grants are mutually exclusive and last for one cycle. | nested_if.sv | module arbiter_0005_nested_if (
input wire clk,
input wire rst,
input wire req0,
input wire req1,
input wire req2,
output wire grant0,
output wire grant1,
output wire grant2
);
localparam [1:0] S_IDLE = 2'd0;
localparam [1:0] S_GRANT0 = 2'd1;
localparam [1:0] S_GRANT1 ... | {
"design_id": "arbiter_0005",
"category": "arbiter",
"template": "three_request_fixed_priority",
"description": "A three-request fixed-priority arbiter. Request 0 has highest priority, followed by request 1 and then request 2. Grants are mutually exclusive and last for one cycle.",
"clock": {
"name": "cl... | // Generated from spec.json.
// Design: arbiter_0005
// P1_MUTUAL_EXCLUSION: at most one requester is granted at a time.
p_mutual_exclusion: assert property (@(posedge clk) disable iff (rst)
!((grant0 && grant1) || (grant0 && grant2) || (grant1 && grant2)));
// P2_RESET_NO_GRANT: reset clears every grant.
p_reset... | [
{
"id": "P1_MUTUAL_EXCLUSION",
"type": "invariant",
"natural_language": "at most one requester is granted at a time",
"disable": "rst",
"expression": "!((grant0 && grant1) || (grant0 && grant2) || (grant1 && grant2))"
},
{
"id": "P2_RESET_NO_GRANT",
"type": "next_cycle_implication",
... | {"grant2_stuck.sv": "module arbiter_0005_mutant_grant2_stuck (\n input wire clk,\n input wire rst,\n input wire req0,\n input wire req1,\n input wire req2,\n output reg grant0,\n output reg grant1,\n output reg grant2\n);\n localparam [1:0] IDLE = 2'd0;\n localparam [1:0] GRANT0 =... |
arbiter_0005 | arbiter | A three-request fixed-priority arbiter. Request 0 has highest priority, followed by request 1 and then request 2. Grants are mutually exclusive and last for one cycle. | factored_flags.sv | module arbiter_0005_factored_flags (
input wire clk,
input wire rst,
input wire req0,
input wire req1,
input wire req2,
output reg grant0,
output reg grant1,
output reg grant2
);
localparam [1:0] F_IDLE = 2'd0;
localparam [1:0] F_GRANT0 = 2'd1;
localpara... | {
"design_id": "arbiter_0005",
"category": "arbiter",
"template": "three_request_fixed_priority",
"description": "A three-request fixed-priority arbiter. Request 0 has highest priority, followed by request 1 and then request 2. Grants are mutually exclusive and last for one cycle.",
"clock": {
"name": "cl... | // Generated from spec.json.
// Design: arbiter_0005
// P1_MUTUAL_EXCLUSION: at most one requester is granted at a time.
p_mutual_exclusion: assert property (@(posedge clk) disable iff (rst)
!((grant0 && grant1) || (grant0 && grant2) || (grant1 && grant2)));
// P2_RESET_NO_GRANT: reset clears every grant.
p_reset... | [
{
"id": "P1_MUTUAL_EXCLUSION",
"type": "invariant",
"natural_language": "at most one requester is granted at a time",
"disable": "rst",
"expression": "!((grant0 && grant1) || (grant0 && grant2) || (grant1 && grant2))"
},
{
"id": "P2_RESET_NO_GRANT",
"type": "next_cycle_implication",
... | {"grant2_stuck.sv": "module arbiter_0005_mutant_grant2_stuck (\n input wire clk,\n input wire rst,\n input wire req0,\n input wire req1,\n input wire req2,\n output reg grant0,\n output reg grant1,\n output reg grant2\n);\n localparam [1:0] IDLE = 2'd0;\n localparam [1:0] GRANT0 =... |
arbiter_0009 | arbiter | Two-client arbiter whose active grant can be locked. | canonical_case.sv | module arbiter_0009_canonical_case (
input wire clk,
input wire rst,
input wire req0,
input wire req1,
input wire lock,
output reg grant0,
output reg grant1
);
localparam [1:0] IDLE = 2'd0;
localparam [1:0] G0 = 2'd1;
localparam [1:0] G1 = 2'd2;
reg [1:0] state... | {
"design_id": "arbiter_0009",
"category": "arbiter",
"template": "lockable_two_client",
"description": "Two-client arbiter whose active grant can be locked.",
"clock": {
"name": "clk",
"edge": "posedge"
},
"reset": {
"name": "rst",
"active": "high",
"synchronous": true,
"state": "... | // Generated from spec.json.
// Design: arbiter_0009
// P1_STATE_ENCODING: observable state outputs always encode at most one active mode.
p_state_encoding: assert property (@(posedge clk) disable iff (rst)
$onehot0({grant0, grant1}));
// P2_RESET: reset returns the controller to its reset behavior.
p_reset_state... | [
{
"id": "P1_STATE_ENCODING",
"type": "invariant",
"natural_language": "observable state outputs always encode at most one active mode",
"expression": "$onehot0({grant0, grant1})",
"disable": "rst"
},
{
"id": "P2_RESET",
"type": "next_cycle_implication",
"natural_language": "reset... | {"drop_t1.sv": "module arbiter_0009_mutant_drop_t1 (\n input wire clk,\n input wire rst,\n input wire req0,\n input wire req1,\n input wire lock,\n output reg grant0,\n output reg grant1\n);\n localparam [1:0] IDLE = 2'd0;\n localparam [1:0] G0 = 2'd1;\n localparam [1:0] G1 =... |
arbiter_0009 | arbiter | Two-client arbiter whose active grant can be locked. | onehot_case.sv | module arbiter_0009_onehot_case (
input wire clk,
input wire rst,
input wire req0,
input wire req1,
input wire lock,
output reg grant0,
output reg grant1
);
localparam [2:0] IDLE = 3'b001;
localparam [2:0] G0 = 3'b010;
localparam [2:0] G1 = 3'b100;
reg [2:0] st... | {
"design_id": "arbiter_0009",
"category": "arbiter",
"template": "lockable_two_client",
"description": "Two-client arbiter whose active grant can be locked.",
"clock": {
"name": "clk",
"edge": "posedge"
},
"reset": {
"name": "rst",
"active": "high",
"synchronous": true,
"state": "... | // Generated from spec.json.
// Design: arbiter_0009
// P1_STATE_ENCODING: observable state outputs always encode at most one active mode.
p_state_encoding: assert property (@(posedge clk) disable iff (rst)
$onehot0({grant0, grant1}));
// P2_RESET: reset returns the controller to its reset behavior.
p_reset_state... | [
{
"id": "P1_STATE_ENCODING",
"type": "invariant",
"natural_language": "observable state outputs always encode at most one active mode",
"expression": "$onehot0({grant0, grant1})",
"disable": "rst"
},
{
"id": "P2_RESET",
"type": "next_cycle_implication",
"natural_language": "reset... | {"drop_t1.sv": "module arbiter_0009_mutant_drop_t1 (\n input wire clk,\n input wire rst,\n input wire req0,\n input wire req1,\n input wire lock,\n output reg grant0,\n output reg grant1\n);\n localparam [1:0] IDLE = 2'd0;\n localparam [1:0] G0 = 2'd1;\n localparam [1:0] G1 =... |
arbiter_0009 | arbiter | Two-client arbiter whose active grant can be locked. | nested_if.sv | module arbiter_0009_nested_if (
input wire clk,
input wire rst,
input wire req0,
input wire req1,
input wire lock,
output wire grant0,
output wire grant1
);
localparam [1:0] S_IDLE = 2'd0;
localparam [1:0] S_G0 = 2'd1;
localparam [1:0] S_G1 = 2'd2;
reg [1:0] s... | {
"design_id": "arbiter_0009",
"category": "arbiter",
"template": "lockable_two_client",
"description": "Two-client arbiter whose active grant can be locked.",
"clock": {
"name": "clk",
"edge": "posedge"
},
"reset": {
"name": "rst",
"active": "high",
"synchronous": true,
"state": "... | // Generated from spec.json.
// Design: arbiter_0009
// P1_STATE_ENCODING: observable state outputs always encode at most one active mode.
p_state_encoding: assert property (@(posedge clk) disable iff (rst)
$onehot0({grant0, grant1}));
// P2_RESET: reset returns the controller to its reset behavior.
p_reset_state... | [
{
"id": "P1_STATE_ENCODING",
"type": "invariant",
"natural_language": "observable state outputs always encode at most one active mode",
"expression": "$onehot0({grant0, grant1})",
"disable": "rst"
},
{
"id": "P2_RESET",
"type": "next_cycle_implication",
"natural_language": "reset... | {"drop_t1.sv": "module arbiter_0009_mutant_drop_t1 (\n input wire clk,\n input wire rst,\n input wire req0,\n input wire req1,\n input wire lock,\n output reg grant0,\n output reg grant1\n);\n localparam [1:0] IDLE = 2'd0;\n localparam [1:0] G0 = 2'd1;\n localparam [1:0] G1 =... |
arbiter_0009 | arbiter | Two-client arbiter whose active grant can be locked. | factored_flags.sv | module arbiter_0009_factored_flags (
input wire clk,
input wire rst,
input wire req0,
input wire req1,
input wire lock,
output reg grant0,
output reg grant1
);
localparam [1:0] F_IDLE = 2'd0;
localparam [1:0] F_G0 = 2'd1;
localparam [1:0] F_G1 =... | {
"design_id": "arbiter_0009",
"category": "arbiter",
"template": "lockable_two_client",
"description": "Two-client arbiter whose active grant can be locked.",
"clock": {
"name": "clk",
"edge": "posedge"
},
"reset": {
"name": "rst",
"active": "high",
"synchronous": true,
"state": "... | // Generated from spec.json.
// Design: arbiter_0009
// P1_STATE_ENCODING: observable state outputs always encode at most one active mode.
p_state_encoding: assert property (@(posedge clk) disable iff (rst)
$onehot0({grant0, grant1}));
// P2_RESET: reset returns the controller to its reset behavior.
p_reset_state... | [
{
"id": "P1_STATE_ENCODING",
"type": "invariant",
"natural_language": "observable state outputs always encode at most one active mode",
"expression": "$onehot0({grant0, grant1})",
"disable": "rst"
},
{
"id": "P2_RESET",
"type": "next_cycle_implication",
"natural_language": "reset... | {"drop_t1.sv": "module arbiter_0009_mutant_drop_t1 (\n input wire clk,\n input wire rst,\n input wire req0,\n input wire req1,\n input wire lock,\n output reg grant0,\n output reg grant1\n);\n localparam [1:0] IDLE = 2'd0;\n localparam [1:0] G0 = 2'd1;\n localparam [1:0] G1 =... |
counter_0001 | counter | Two-bit saturating up-counter with synchronous clear and enable. | canonical_next.sv | module counter_0001_canonical_next (
input wire clk,
input wire rst,
input wire clear,
input wire enable,
output reg [1:0] count,
output wire at_max
);
reg [1:0] next_count;
always @* begin
if (clear) next_count = 2'd0;
else if (enable && (count < 2'd3)) next_count... | {
"design_id": "counter_0001",
"category": "counter",
"model_type": "register_rules",
"template": "saturating_up_counter",
"description": "Two-bit saturating up-counter with synchronous clear and enable.",
"clock": {
"name": "clk",
"edge": "posedge"
},
"reset": {
"name": "rst",
"active":... | // Gold interface properties for counter_0001
// P1_AT_MAX_CONSISTENT: at_max is asserted exactly when count equals three
property p_at_max_consistent;
@(posedge clk) disable iff (rst) (at_max == (count == 2'd3));
endproperty
assert property (p_at_max_consistent);
// P2_RESET_ZERO: a reset cycle leaves the counte... | [
{
"id": "P1_AT_MAX_CONSISTENT",
"sva_name": "p_at_max_consistent",
"type": "invariant",
"natural_language": "at_max is asserted exactly when count equals three",
"disable": "rst",
"expression": "at_max == (count == 2'd3)"
},
{
"id": "P2_RESET_ZERO",
"sva_name": "p_reset_zero",
... | {"ignore_clear.sv": "module counter_0001_mutant_ignore_clear (\n input wire clk,\n input wire rst,\n input wire clear,\n input wire enable,\n output reg [1:0] count,\n output wire at_max\n);\n\n always @(posedge clk) begin\n if (rst) begin\n count <= 2'd0;\n end\n ... |
counter_0001 | counter | Two-bit saturating up-counter with synchronous clear and enable. | sequential_priority.sv | module counter_0001_sequential_priority (
input wire clk,
input wire rst,
input wire clear,
input wire enable,
output reg [1:0] count,
output wire at_max
);
always @(posedge clk) begin
if (rst) begin
count <= 2'd0;
end
else begin
if (clea... | {
"design_id": "counter_0001",
"category": "counter",
"model_type": "register_rules",
"template": "saturating_up_counter",
"description": "Two-bit saturating up-counter with synchronous clear and enable.",
"clock": {
"name": "clk",
"edge": "posedge"
},
"reset": {
"name": "rst",
"active":... | // Gold interface properties for counter_0001
// P1_AT_MAX_CONSISTENT: at_max is asserted exactly when count equals three
property p_at_max_consistent;
@(posedge clk) disable iff (rst) (at_max == (count == 2'd3));
endproperty
assert property (p_at_max_consistent);
// P2_RESET_ZERO: a reset cycle leaves the counte... | [
{
"id": "P1_AT_MAX_CONSISTENT",
"sva_name": "p_at_max_consistent",
"type": "invariant",
"natural_language": "at_max is asserted exactly when count equals three",
"disable": "rst",
"expression": "at_max == (count == 2'd3)"
},
{
"id": "P2_RESET_ZERO",
"sva_name": "p_reset_zero",
... | {"ignore_clear.sv": "module counter_0001_mutant_ignore_clear (\n input wire clk,\n input wire rst,\n input wire clear,\n input wire enable,\n output reg [1:0] count,\n output wire at_max\n);\n\n always @(posedge clk) begin\n if (rst) begin\n count <= 2'd0;\n end\n ... |
counter_0001 | counter | Two-bit saturating up-counter with synchronous clear and enable. | ternary_next.sv | module counter_0001_ternary_next (
input wire clk,
input wire rst,
input wire clear,
input wire enable,
output reg [1:0] count,
output wire at_max
);
wire [1:0] next_count;
assign next_count = (clear) ? (2'd0) : ((enable && (count < 2'd3)) ? (count + 2'd1) : (count));
always ... | {
"design_id": "counter_0001",
"category": "counter",
"model_type": "register_rules",
"template": "saturating_up_counter",
"description": "Two-bit saturating up-counter with synchronous clear and enable.",
"clock": {
"name": "clk",
"edge": "posedge"
},
"reset": {
"name": "rst",
"active":... | // Gold interface properties for counter_0001
// P1_AT_MAX_CONSISTENT: at_max is asserted exactly when count equals three
property p_at_max_consistent;
@(posedge clk) disable iff (rst) (at_max == (count == 2'd3));
endproperty
assert property (p_at_max_consistent);
// P2_RESET_ZERO: a reset cycle leaves the counte... | [
{
"id": "P1_AT_MAX_CONSISTENT",
"sva_name": "p_at_max_consistent",
"type": "invariant",
"natural_language": "at_max is asserted exactly when count equals three",
"disable": "rst",
"expression": "at_max == (count == 2'd3)"
},
{
"id": "P2_RESET_ZERO",
"sva_name": "p_reset_zero",
... | {"ignore_clear.sv": "module counter_0001_mutant_ignore_clear (\n input wire clk,\n input wire rst,\n input wire clear,\n input wire enable,\n output reg [1:0] count,\n output wire at_max\n);\n\n always @(posedge clk) begin\n if (rst) begin\n count <= 2'd0;\n end\n ... |
counter_0001 | counter | Two-bit saturating up-counter with synchronous clear and enable. | function_update.sv | module counter_0001_function_update (
input wire clk,
input wire rst,
input wire clear,
input wire enable,
output reg [1:0] count,
output wire at_max
);
function automatic [1:0] compute_next_count;
input [1:0] current;
input clear;
input enable;
begin
... | {
"design_id": "counter_0001",
"category": "counter",
"model_type": "register_rules",
"template": "saturating_up_counter",
"description": "Two-bit saturating up-counter with synchronous clear and enable.",
"clock": {
"name": "clk",
"edge": "posedge"
},
"reset": {
"name": "rst",
"active":... | // Gold interface properties for counter_0001
// P1_AT_MAX_CONSISTENT: at_max is asserted exactly when count equals three
property p_at_max_consistent;
@(posedge clk) disable iff (rst) (at_max == (count == 2'd3));
endproperty
assert property (p_at_max_consistent);
// P2_RESET_ZERO: a reset cycle leaves the counte... | [
{
"id": "P1_AT_MAX_CONSISTENT",
"sva_name": "p_at_max_consistent",
"type": "invariant",
"natural_language": "at_max is asserted exactly when count equals three",
"disable": "rst",
"expression": "at_max == (count == 2'd3)"
},
{
"id": "P2_RESET_ZERO",
"sva_name": "p_reset_zero",
... | {"ignore_clear.sv": "module counter_0001_mutant_ignore_clear (\n input wire clk,\n input wire rst,\n input wire clear,\n input wire enable,\n output reg [1:0] count,\n output wire at_max\n);\n\n always @(posedge clk) begin\n if (rst) begin\n count <= 2'd0;\n end\n ... |
counter_0002 | counter | Two-bit modulo up-counter that wraps from three to zero. | canonical_next.sv | module counter_0002_canonical_next (
input wire clk,
input wire rst,
input wire clear,
input wire enable,
output reg [1:0] count,
output wire is_zero
);
reg [1:0] next_count;
always @* begin
if (clear) next_count = 2'd0;
else if (enable && (count == 2'd3)) next_cou... | {
"design_id": "counter_0002",
"category": "counter",
"model_type": "register_rules",
"template": "modulo_up_counter",
"description": "Two-bit modulo up-counter that wraps from three to zero.",
"clock": {
"name": "clk",
"edge": "posedge"
},
"reset": {
"name": "rst",
"active": "high",
... | // Gold interface properties for counter_0002
// P1_ZERO_FLAG: is_zero is asserted exactly when count is zero
property p_zero_flag;
@(posedge clk) disable iff (rst) (is_zero == (count == 2'd0));
endproperty
assert property (p_zero_flag);
// P2_RESET_ZERO: reset leaves the counter at zero
property p_reset_zero;
... | [
{
"id": "P1_ZERO_FLAG",
"sva_name": "p_zero_flag",
"type": "invariant",
"natural_language": "is_zero is asserted exactly when count is zero",
"disable": "rst",
"expression": "is_zero == (count == 2'd0)"
},
{
"id": "P2_RESET_ZERO",
"sva_name": "p_reset_zero",
"type": "next_cyc... | {"ignore_clear.sv": "module counter_0002_mutant_ignore_clear (\n input wire clk,\n input wire rst,\n input wire clear,\n input wire enable,\n output reg [1:0] count,\n output wire is_zero\n);\n\n always @(posedge clk) begin\n if (rst) begin\n count <= 2'd0;\n end\n ... |
counter_0002 | counter | Two-bit modulo up-counter that wraps from three to zero. | sequential_priority.sv | module counter_0002_sequential_priority (
input wire clk,
input wire rst,
input wire clear,
input wire enable,
output reg [1:0] count,
output wire is_zero
);
always @(posedge clk) begin
if (rst) begin
count <= 2'd0;
end
else begin
if (cle... | {
"design_id": "counter_0002",
"category": "counter",
"model_type": "register_rules",
"template": "modulo_up_counter",
"description": "Two-bit modulo up-counter that wraps from three to zero.",
"clock": {
"name": "clk",
"edge": "posedge"
},
"reset": {
"name": "rst",
"active": "high",
... | // Gold interface properties for counter_0002
// P1_ZERO_FLAG: is_zero is asserted exactly when count is zero
property p_zero_flag;
@(posedge clk) disable iff (rst) (is_zero == (count == 2'd0));
endproperty
assert property (p_zero_flag);
// P2_RESET_ZERO: reset leaves the counter at zero
property p_reset_zero;
... | [
{
"id": "P1_ZERO_FLAG",
"sva_name": "p_zero_flag",
"type": "invariant",
"natural_language": "is_zero is asserted exactly when count is zero",
"disable": "rst",
"expression": "is_zero == (count == 2'd0)"
},
{
"id": "P2_RESET_ZERO",
"sva_name": "p_reset_zero",
"type": "next_cyc... | {"ignore_clear.sv": "module counter_0002_mutant_ignore_clear (\n input wire clk,\n input wire rst,\n input wire clear,\n input wire enable,\n output reg [1:0] count,\n output wire is_zero\n);\n\n always @(posedge clk) begin\n if (rst) begin\n count <= 2'd0;\n end\n ... |
counter_0002 | counter | Two-bit modulo up-counter that wraps from three to zero. | ternary_next.sv | module counter_0002_ternary_next (
input wire clk,
input wire rst,
input wire clear,
input wire enable,
output reg [1:0] count,
output wire is_zero
);
wire [1:0] next_count;
assign next_count = (clear) ? (2'd0) : ((enable && (count == 2'd3)) ? (2'd0) : ((enable && (count < 2'd3)) ... | {
"design_id": "counter_0002",
"category": "counter",
"model_type": "register_rules",
"template": "modulo_up_counter",
"description": "Two-bit modulo up-counter that wraps from three to zero.",
"clock": {
"name": "clk",
"edge": "posedge"
},
"reset": {
"name": "rst",
"active": "high",
... | // Gold interface properties for counter_0002
// P1_ZERO_FLAG: is_zero is asserted exactly when count is zero
property p_zero_flag;
@(posedge clk) disable iff (rst) (is_zero == (count == 2'd0));
endproperty
assert property (p_zero_flag);
// P2_RESET_ZERO: reset leaves the counter at zero
property p_reset_zero;
... | [
{
"id": "P1_ZERO_FLAG",
"sva_name": "p_zero_flag",
"type": "invariant",
"natural_language": "is_zero is asserted exactly when count is zero",
"disable": "rst",
"expression": "is_zero == (count == 2'd0)"
},
{
"id": "P2_RESET_ZERO",
"sva_name": "p_reset_zero",
"type": "next_cyc... | {"ignore_clear.sv": "module counter_0002_mutant_ignore_clear (\n input wire clk,\n input wire rst,\n input wire clear,\n input wire enable,\n output reg [1:0] count,\n output wire is_zero\n);\n\n always @(posedge clk) begin\n if (rst) begin\n count <= 2'd0;\n end\n ... |
counter_0002 | counter | Two-bit modulo up-counter that wraps from three to zero. | function_update.sv | module counter_0002_function_update (
input wire clk,
input wire rst,
input wire clear,
input wire enable,
output reg [1:0] count,
output wire is_zero
);
function automatic [1:0] compute_next_count;
input [1:0] current;
input clear;
input enable;
begin
... | {
"design_id": "counter_0002",
"category": "counter",
"model_type": "register_rules",
"template": "modulo_up_counter",
"description": "Two-bit modulo up-counter that wraps from three to zero.",
"clock": {
"name": "clk",
"edge": "posedge"
},
"reset": {
"name": "rst",
"active": "high",
... | // Gold interface properties for counter_0002
// P1_ZERO_FLAG: is_zero is asserted exactly when count is zero
property p_zero_flag;
@(posedge clk) disable iff (rst) (is_zero == (count == 2'd0));
endproperty
assert property (p_zero_flag);
// P2_RESET_ZERO: reset leaves the counter at zero
property p_reset_zero;
... | [
{
"id": "P1_ZERO_FLAG",
"sva_name": "p_zero_flag",
"type": "invariant",
"natural_language": "is_zero is asserted exactly when count is zero",
"disable": "rst",
"expression": "is_zero == (count == 2'd0)"
},
{
"id": "P2_RESET_ZERO",
"sva_name": "p_reset_zero",
"type": "next_cyc... | {"ignore_clear.sv": "module counter_0002_mutant_ignore_clear (\n input wire clk,\n input wire rst,\n input wire clear,\n input wire enable,\n output reg [1:0] count,\n output wire is_zero\n);\n\n always @(posedge clk) begin\n if (rst) begin\n count <= 2'd0;\n end\n ... |
counter_0003 | counter | Two-bit saturating counter that increments or decrements under direction control. | canonical_next.sv | module counter_0003_canonical_next (
input wire clk,
input wire rst,
input wire clear,
input wire enable,
input wire down,
output reg [1:0] count,
output wire at_min,
output wire at_max
);
reg [1:0] next_count;
always @* begin
if (clear) next_count = 2'd0;
... | {
"design_id": "counter_0003",
"category": "counter",
"model_type": "register_rules",
"template": "bidirectional_saturating_counter",
"description": "Two-bit saturating counter that increments or decrements under direction control.",
"clock": {
"name": "clk",
"edge": "posedge"
},
"reset": {
... | // Gold interface properties for counter_0003
// P1_MIN_FLAG: at_min matches count equal to zero
property p_min_flag;
@(posedge clk) disable iff (rst) (at_min == (count == 2'd0));
endproperty
assert property (p_min_flag);
// P2_MAX_FLAG: at_max matches count equal to three
property p_max_flag;
@(posedge clk) ... | [
{
"id": "P1_MIN_FLAG",
"sva_name": "p_min_flag",
"type": "invariant",
"natural_language": "at_min matches count equal to zero",
"disable": "rst",
"expression": "at_min == (count == 2'd0)"
},
{
"id": "P2_MAX_FLAG",
"sva_name": "p_max_flag",
"type": "invariant",
"natural_la... | {"ignore_direction.sv": "module counter_0003_mutant_ignore_direction (\n input wire clk,\n input wire rst,\n input wire clear,\n input wire enable,\n input wire down,\n output reg [1:0] count,\n output wire at_min,\n output wire at_max\n);\n\n always @(posedge clk) begin\n if (rs... |
counter_0003 | counter | Two-bit saturating counter that increments or decrements under direction control. | sequential_priority.sv | module counter_0003_sequential_priority (
input wire clk,
input wire rst,
input wire clear,
input wire enable,
input wire down,
output reg [1:0] count,
output wire at_min,
output wire at_max
);
always @(posedge clk) begin
if (rst) begin
count <= 2'd0;
... | {
"design_id": "counter_0003",
"category": "counter",
"model_type": "register_rules",
"template": "bidirectional_saturating_counter",
"description": "Two-bit saturating counter that increments or decrements under direction control.",
"clock": {
"name": "clk",
"edge": "posedge"
},
"reset": {
... | // Gold interface properties for counter_0003
// P1_MIN_FLAG: at_min matches count equal to zero
property p_min_flag;
@(posedge clk) disable iff (rst) (at_min == (count == 2'd0));
endproperty
assert property (p_min_flag);
// P2_MAX_FLAG: at_max matches count equal to three
property p_max_flag;
@(posedge clk) ... | [
{
"id": "P1_MIN_FLAG",
"sva_name": "p_min_flag",
"type": "invariant",
"natural_language": "at_min matches count equal to zero",
"disable": "rst",
"expression": "at_min == (count == 2'd0)"
},
{
"id": "P2_MAX_FLAG",
"sva_name": "p_max_flag",
"type": "invariant",
"natural_la... | {"ignore_direction.sv": "module counter_0003_mutant_ignore_direction (\n input wire clk,\n input wire rst,\n input wire clear,\n input wire enable,\n input wire down,\n output reg [1:0] count,\n output wire at_min,\n output wire at_max\n);\n\n always @(posedge clk) begin\n if (rs... |
counter_0003 | counter | Two-bit saturating counter that increments or decrements under direction control. | ternary_next.sv | module counter_0003_ternary_next (
input wire clk,
input wire rst,
input wire clear,
input wire enable,
input wire down,
output reg [1:0] count,
output wire at_min,
output wire at_max
);
wire [1:0] next_count;
assign next_count = (clear) ? (2'd0) : ((enable && down && (co... | {
"design_id": "counter_0003",
"category": "counter",
"model_type": "register_rules",
"template": "bidirectional_saturating_counter",
"description": "Two-bit saturating counter that increments or decrements under direction control.",
"clock": {
"name": "clk",
"edge": "posedge"
},
"reset": {
... | // Gold interface properties for counter_0003
// P1_MIN_FLAG: at_min matches count equal to zero
property p_min_flag;
@(posedge clk) disable iff (rst) (at_min == (count == 2'd0));
endproperty
assert property (p_min_flag);
// P2_MAX_FLAG: at_max matches count equal to three
property p_max_flag;
@(posedge clk) ... | [
{
"id": "P1_MIN_FLAG",
"sva_name": "p_min_flag",
"type": "invariant",
"natural_language": "at_min matches count equal to zero",
"disable": "rst",
"expression": "at_min == (count == 2'd0)"
},
{
"id": "P2_MAX_FLAG",
"sva_name": "p_max_flag",
"type": "invariant",
"natural_la... | {"ignore_direction.sv": "module counter_0003_mutant_ignore_direction (\n input wire clk,\n input wire rst,\n input wire clear,\n input wire enable,\n input wire down,\n output reg [1:0] count,\n output wire at_min,\n output wire at_max\n);\n\n always @(posedge clk) begin\n if (rs... |
counter_0003 | counter | Two-bit saturating counter that increments or decrements under direction control. | function_update.sv | module counter_0003_function_update (
input wire clk,
input wire rst,
input wire clear,
input wire enable,
input wire down,
output reg [1:0] count,
output wire at_min,
output wire at_max
);
function automatic [1:0] compute_next_count;
input [1:0] current;
input... | {
"design_id": "counter_0003",
"category": "counter",
"model_type": "register_rules",
"template": "bidirectional_saturating_counter",
"description": "Two-bit saturating counter that increments or decrements under direction control.",
"clock": {
"name": "clk",
"edge": "posedge"
},
"reset": {
... | // Gold interface properties for counter_0003
// P1_MIN_FLAG: at_min matches count equal to zero
property p_min_flag;
@(posedge clk) disable iff (rst) (at_min == (count == 2'd0));
endproperty
assert property (p_min_flag);
// P2_MAX_FLAG: at_max matches count equal to three
property p_max_flag;
@(posedge clk) ... | [
{
"id": "P1_MIN_FLAG",
"sva_name": "p_min_flag",
"type": "invariant",
"natural_language": "at_min matches count equal to zero",
"disable": "rst",
"expression": "at_min == (count == 2'd0)"
},
{
"id": "P2_MAX_FLAG",
"sva_name": "p_max_flag",
"type": "invariant",
"natural_la... | {"ignore_direction.sv": "module counter_0003_mutant_ignore_direction (\n input wire clk,\n input wire rst,\n input wire clear,\n input wire enable,\n input wire down,\n output reg [1:0] count,\n output wire at_min,\n output wire at_max\n);\n\n always @(posedge clk) begin\n if (rs... |
counter_0004 | counter | Two-bit saturating up-counter with a programmable synchronous load value. | canonical_next.sv | module counter_0004_canonical_next (
input wire clk,
input wire rst,
input wire clear,
input wire load,
input wire enable,
input wire [1:0] load_value,
output reg [1:0] count,
output wire at_max
);
reg [1:0] next_count;
always @* begin
if (clear) next_count = 2'd... | {
"design_id": "counter_0004",
"category": "counter",
"model_type": "register_rules",
"template": "programmable_load_up_counter",
"description": "Two-bit saturating up-counter with a programmable synchronous load value.",
"clock": {
"name": "clk",
"edge": "posedge"
},
"reset": {
"name": "rst... | // Gold interface properties for counter_0004
// P1_MAX_FLAG: at_max matches count equal to three
property p_max_flag;
@(posedge clk) disable iff (rst) (at_max == (count == 2'd3));
endproperty
assert property (p_max_flag);
// P2_CLEAR_PRIORITY: clear has priority over load and enable
property p_clear_priority;
... | [
{
"id": "P1_MAX_FLAG",
"sva_name": "p_max_flag",
"type": "invariant",
"natural_language": "at_max matches count equal to three",
"disable": "rst",
"expression": "at_max == (count == 2'd3)"
},
{
"id": "P2_CLEAR_PRIORITY",
"sva_name": "p_clear_priority",
"type": "next_cycle_imp... | {"ignore_load.sv": "module counter_0004_mutant_ignore_load (\n input wire clk,\n input wire rst,\n input wire clear,\n input wire load,\n input wire enable,\n input wire [1:0] load_value,\n output reg [1:0] count,\n output wire at_max\n);\n\n always @(posedge clk) begin\n if (rs... |
counter_0004 | counter | Two-bit saturating up-counter with a programmable synchronous load value. | sequential_priority.sv | module counter_0004_sequential_priority (
input wire clk,
input wire rst,
input wire clear,
input wire load,
input wire enable,
input wire [1:0] load_value,
output reg [1:0] count,
output wire at_max
);
always @(posedge clk) begin
if (rst) begin
count <= 2... | {
"design_id": "counter_0004",
"category": "counter",
"model_type": "register_rules",
"template": "programmable_load_up_counter",
"description": "Two-bit saturating up-counter with a programmable synchronous load value.",
"clock": {
"name": "clk",
"edge": "posedge"
},
"reset": {
"name": "rst... | // Gold interface properties for counter_0004
// P1_MAX_FLAG: at_max matches count equal to three
property p_max_flag;
@(posedge clk) disable iff (rst) (at_max == (count == 2'd3));
endproperty
assert property (p_max_flag);
// P2_CLEAR_PRIORITY: clear has priority over load and enable
property p_clear_priority;
... | [
{
"id": "P1_MAX_FLAG",
"sva_name": "p_max_flag",
"type": "invariant",
"natural_language": "at_max matches count equal to three",
"disable": "rst",
"expression": "at_max == (count == 2'd3)"
},
{
"id": "P2_CLEAR_PRIORITY",
"sva_name": "p_clear_priority",
"type": "next_cycle_imp... | {"ignore_load.sv": "module counter_0004_mutant_ignore_load (\n input wire clk,\n input wire rst,\n input wire clear,\n input wire load,\n input wire enable,\n input wire [1:0] load_value,\n output reg [1:0] count,\n output wire at_max\n);\n\n always @(posedge clk) begin\n if (rs... |
counter_0004 | counter | Two-bit saturating up-counter with a programmable synchronous load value. | ternary_next.sv | module counter_0004_ternary_next (
input wire clk,
input wire rst,
input wire clear,
input wire load,
input wire enable,
input wire [1:0] load_value,
output reg [1:0] count,
output wire at_max
);
wire [1:0] next_count;
assign next_count = (clear) ? (2'd0) : ((load) ? (lo... | {
"design_id": "counter_0004",
"category": "counter",
"model_type": "register_rules",
"template": "programmable_load_up_counter",
"description": "Two-bit saturating up-counter with a programmable synchronous load value.",
"clock": {
"name": "clk",
"edge": "posedge"
},
"reset": {
"name": "rst... | // Gold interface properties for counter_0004
// P1_MAX_FLAG: at_max matches count equal to three
property p_max_flag;
@(posedge clk) disable iff (rst) (at_max == (count == 2'd3));
endproperty
assert property (p_max_flag);
// P2_CLEAR_PRIORITY: clear has priority over load and enable
property p_clear_priority;
... | [
{
"id": "P1_MAX_FLAG",
"sva_name": "p_max_flag",
"type": "invariant",
"natural_language": "at_max matches count equal to three",
"disable": "rst",
"expression": "at_max == (count == 2'd3)"
},
{
"id": "P2_CLEAR_PRIORITY",
"sva_name": "p_clear_priority",
"type": "next_cycle_imp... | {"ignore_load.sv": "module counter_0004_mutant_ignore_load (\n input wire clk,\n input wire rst,\n input wire clear,\n input wire load,\n input wire enable,\n input wire [1:0] load_value,\n output reg [1:0] count,\n output wire at_max\n);\n\n always @(posedge clk) begin\n if (rs... |
counter_0004 | counter | Two-bit saturating up-counter with a programmable synchronous load value. | function_update.sv | module counter_0004_function_update (
input wire clk,
input wire rst,
input wire clear,
input wire load,
input wire enable,
input wire [1:0] load_value,
output reg [1:0] count,
output wire at_max
);
function automatic [1:0] compute_next_count;
input [1:0] current;
... | {
"design_id": "counter_0004",
"category": "counter",
"model_type": "register_rules",
"template": "programmable_load_up_counter",
"description": "Two-bit saturating up-counter with a programmable synchronous load value.",
"clock": {
"name": "clk",
"edge": "posedge"
},
"reset": {
"name": "rst... | // Gold interface properties for counter_0004
// P1_MAX_FLAG: at_max matches count equal to three
property p_max_flag;
@(posedge clk) disable iff (rst) (at_max == (count == 2'd3));
endproperty
assert property (p_max_flag);
// P2_CLEAR_PRIORITY: clear has priority over load and enable
property p_clear_priority;
... | [
{
"id": "P1_MAX_FLAG",
"sva_name": "p_max_flag",
"type": "invariant",
"natural_language": "at_max matches count equal to three",
"disable": "rst",
"expression": "at_max == (count == 2'd3)"
},
{
"id": "P2_CLEAR_PRIORITY",
"sva_name": "p_clear_priority",
"type": "next_cycle_imp... | {"ignore_load.sv": "module counter_0004_mutant_ignore_load (\n input wire clk,\n input wire rst,\n input wire clear,\n input wire load,\n input wire enable,\n input wire [1:0] load_value,\n output reg [1:0] count,\n output wire at_max\n);\n\n always @(posedge clk) begin\n if (rs... |
counter_0005 | counter | Two-bit programmable down-counter that decrements on tick and stops at zero. | canonical_next.sv | module counter_0005_canonical_next (
input wire clk,
input wire rst,
input wire clear,
input wire load,
input wire tick,
input wire [1:0] load_value,
output reg [1:0] count,
output wire expired
);
reg [1:0] next_count;
always @* begin
if (clear) next_count = 2'd0... | {
"design_id": "counter_0005",
"category": "counter",
"model_type": "register_rules",
"template": "programmable_down_counter",
"description": "Two-bit programmable down-counter that decrements on tick and stops at zero.",
"clock": {
"name": "clk",
"edge": "posedge"
},
"reset": {
"name": "rst... | // Gold interface properties for counter_0005
// P1_EXPIRED_FLAG: expired is asserted exactly when the count is zero
property p_expired_flag;
@(posedge clk) disable iff (rst) (expired == (count == 2'd0));
endproperty
assert property (p_expired_flag);
// P2_CLEAR: clear resets the counter and marks it expired
prop... | [
{
"id": "P1_EXPIRED_FLAG",
"sva_name": "p_expired_flag",
"type": "invariant",
"natural_language": "expired is asserted exactly when the count is zero",
"disable": "rst",
"expression": "expired == (count == 2'd0)"
},
{
"id": "P2_CLEAR",
"sva_name": "p_clear",
"type": "next_cyc... | {"decrement_without_tick.sv": "module counter_0005_mutant_decrement_without_tick (\n input wire clk,\n input wire rst,\n input wire clear,\n input wire load,\n input wire tick,\n input wire [1:0] load_value,\n output reg [1:0] count,\n output wire expired\n);\n\n always @(posedge clk) ... |
counter_0005 | counter | Two-bit programmable down-counter that decrements on tick and stops at zero. | sequential_priority.sv | module counter_0005_sequential_priority (
input wire clk,
input wire rst,
input wire clear,
input wire load,
input wire tick,
input wire [1:0] load_value,
output reg [1:0] count,
output wire expired
);
always @(posedge clk) begin
if (rst) begin
count <= 2'... | {
"design_id": "counter_0005",
"category": "counter",
"model_type": "register_rules",
"template": "programmable_down_counter",
"description": "Two-bit programmable down-counter that decrements on tick and stops at zero.",
"clock": {
"name": "clk",
"edge": "posedge"
},
"reset": {
"name": "rst... | // Gold interface properties for counter_0005
// P1_EXPIRED_FLAG: expired is asserted exactly when the count is zero
property p_expired_flag;
@(posedge clk) disable iff (rst) (expired == (count == 2'd0));
endproperty
assert property (p_expired_flag);
// P2_CLEAR: clear resets the counter and marks it expired
prop... | [
{
"id": "P1_EXPIRED_FLAG",
"sva_name": "p_expired_flag",
"type": "invariant",
"natural_language": "expired is asserted exactly when the count is zero",
"disable": "rst",
"expression": "expired == (count == 2'd0)"
},
{
"id": "P2_CLEAR",
"sva_name": "p_clear",
"type": "next_cyc... | {"decrement_without_tick.sv": "module counter_0005_mutant_decrement_without_tick (\n input wire clk,\n input wire rst,\n input wire clear,\n input wire load,\n input wire tick,\n input wire [1:0] load_value,\n output reg [1:0] count,\n output wire expired\n);\n\n always @(posedge clk) ... |
counter_0005 | counter | Two-bit programmable down-counter that decrements on tick and stops at zero. | ternary_next.sv | module counter_0005_ternary_next (
input wire clk,
input wire rst,
input wire clear,
input wire load,
input wire tick,
input wire [1:0] load_value,
output reg [1:0] count,
output wire expired
);
wire [1:0] next_count;
assign next_count = (clear) ? (2'd0) : ((load) ? (loa... | {
"design_id": "counter_0005",
"category": "counter",
"model_type": "register_rules",
"template": "programmable_down_counter",
"description": "Two-bit programmable down-counter that decrements on tick and stops at zero.",
"clock": {
"name": "clk",
"edge": "posedge"
},
"reset": {
"name": "rst... | // Gold interface properties for counter_0005
// P1_EXPIRED_FLAG: expired is asserted exactly when the count is zero
property p_expired_flag;
@(posedge clk) disable iff (rst) (expired == (count == 2'd0));
endproperty
assert property (p_expired_flag);
// P2_CLEAR: clear resets the counter and marks it expired
prop... | [
{
"id": "P1_EXPIRED_FLAG",
"sva_name": "p_expired_flag",
"type": "invariant",
"natural_language": "expired is asserted exactly when the count is zero",
"disable": "rst",
"expression": "expired == (count == 2'd0)"
},
{
"id": "P2_CLEAR",
"sva_name": "p_clear",
"type": "next_cyc... | {"decrement_without_tick.sv": "module counter_0005_mutant_decrement_without_tick (\n input wire clk,\n input wire rst,\n input wire clear,\n input wire load,\n input wire tick,\n input wire [1:0] load_value,\n output reg [1:0] count,\n output wire expired\n);\n\n always @(posedge clk) ... |
counter_0005 | counter | Two-bit programmable down-counter that decrements on tick and stops at zero. | function_update.sv | module counter_0005_function_update (
input wire clk,
input wire rst,
input wire clear,
input wire load,
input wire tick,
input wire [1:0] load_value,
output reg [1:0] count,
output wire expired
);
function automatic [1:0] compute_next_count;
input [1:0] current;
... | {
"design_id": "counter_0005",
"category": "counter",
"model_type": "register_rules",
"template": "programmable_down_counter",
"description": "Two-bit programmable down-counter that decrements on tick and stops at zero.",
"clock": {
"name": "clk",
"edge": "posedge"
},
"reset": {
"name": "rst... | // Gold interface properties for counter_0005
// P1_EXPIRED_FLAG: expired is asserted exactly when the count is zero
property p_expired_flag;
@(posedge clk) disable iff (rst) (expired == (count == 2'd0));
endproperty
assert property (p_expired_flag);
// P2_CLEAR: clear resets the counter and marks it expired
prop... | [
{
"id": "P1_EXPIRED_FLAG",
"sva_name": "p_expired_flag",
"type": "invariant",
"natural_language": "expired is asserted exactly when the count is zero",
"disable": "rst",
"expression": "expired == (count == 2'd0)"
},
{
"id": "P2_CLEAR",
"sva_name": "p_clear",
"type": "next_cyc... | {"decrement_without_tick.sv": "module counter_0005_mutant_decrement_without_tick (\n input wire clk,\n input wire rst,\n input wire clear,\n input wire load,\n input wire tick,\n input wire [1:0] load_value,\n output reg [1:0] count,\n output wire expired\n);\n\n always @(posedge clk) ... |
counter_0010 | counter | Loadable counter where load has priority over increment. | canonical_next.sv | module counter_0010_canonical_next (
input wire clk,
input wire rst,
input wire load,
input wire increment,
output reg [2:0] count,
output wire nonzero
);
reg [2:0] next_count;
always @* begin
if (load) next_count = 3'd4;
else if (!load && increment && (count < 3'd... | {
"design_id": "counter_0010",
"category": "counter",
"model_type": "register_rules",
"template": "priority_load_counter",
"description": "Loadable counter where load has priority over increment.",
"clock": {
"name": "clk",
"edge": "posedge"
},
"reset": {
"name": "rst",
"active": "high",... | // Gold interface properties for counter_0010
// P1_RESET: reset restores the register to its reset value
property p_reset_value;
@(posedge clk) (rst) |=> (count == 3'd0);
endproperty
assert property (p_reset_value);
// P2_NONZERO: nonzero is consistent with the observable register value
property p_nonzero;
@... | [
{
"id": "P1_RESET",
"sva_name": "p_reset_value",
"type": "next_cycle_implication",
"natural_language": "reset restores the register to its reset value",
"antecedent": "rst",
"consequent": "count == 3'd0",
"delay": 1
},
{
"id": "P2_NONZERO",
"sva_name": "p_nonzero",
"type"... | {"ignore_increment.sv": "module counter_0010_mutant_ignore_increment (\n input wire clk,\n input wire rst,\n input wire load,\n input wire increment,\n output reg [2:0] count,\n output wire nonzero\n);\n\n always @(posedge clk) begin\n if (rst) begin\n count <= 3'd0;\n ... |
counter_0010 | counter | Loadable counter where load has priority over increment. | sequential_priority.sv | module counter_0010_sequential_priority (
input wire clk,
input wire rst,
input wire load,
input wire increment,
output reg [2:0] count,
output wire nonzero
);
always @(posedge clk) begin
if (rst) begin
count <= 3'd0;
end
else begin
if (l... | {
"design_id": "counter_0010",
"category": "counter",
"model_type": "register_rules",
"template": "priority_load_counter",
"description": "Loadable counter where load has priority over increment.",
"clock": {
"name": "clk",
"edge": "posedge"
},
"reset": {
"name": "rst",
"active": "high",... | // Gold interface properties for counter_0010
// P1_RESET: reset restores the register to its reset value
property p_reset_value;
@(posedge clk) (rst) |=> (count == 3'd0);
endproperty
assert property (p_reset_value);
// P2_NONZERO: nonzero is consistent with the observable register value
property p_nonzero;
@... | [
{
"id": "P1_RESET",
"sva_name": "p_reset_value",
"type": "next_cycle_implication",
"natural_language": "reset restores the register to its reset value",
"antecedent": "rst",
"consequent": "count == 3'd0",
"delay": 1
},
{
"id": "P2_NONZERO",
"sva_name": "p_nonzero",
"type"... | {"ignore_increment.sv": "module counter_0010_mutant_ignore_increment (\n input wire clk,\n input wire rst,\n input wire load,\n input wire increment,\n output reg [2:0] count,\n output wire nonzero\n);\n\n always @(posedge clk) begin\n if (rst) begin\n count <= 3'd0;\n ... |
counter_0010 | counter | Loadable counter where load has priority over increment. | ternary_next.sv | module counter_0010_ternary_next (
input wire clk,
input wire rst,
input wire load,
input wire increment,
output reg [2:0] count,
output wire nonzero
);
wire [2:0] next_count;
assign next_count = (load) ? (3'd4) : ((!load && increment && (count < 3'd7)) ? (count + 3'd1) : (count))... | {
"design_id": "counter_0010",
"category": "counter",
"model_type": "register_rules",
"template": "priority_load_counter",
"description": "Loadable counter where load has priority over increment.",
"clock": {
"name": "clk",
"edge": "posedge"
},
"reset": {
"name": "rst",
"active": "high",... | // Gold interface properties for counter_0010
// P1_RESET: reset restores the register to its reset value
property p_reset_value;
@(posedge clk) (rst) |=> (count == 3'd0);
endproperty
assert property (p_reset_value);
// P2_NONZERO: nonzero is consistent with the observable register value
property p_nonzero;
@... | [
{
"id": "P1_RESET",
"sva_name": "p_reset_value",
"type": "next_cycle_implication",
"natural_language": "reset restores the register to its reset value",
"antecedent": "rst",
"consequent": "count == 3'd0",
"delay": 1
},
{
"id": "P2_NONZERO",
"sva_name": "p_nonzero",
"type"... | {"ignore_increment.sv": "module counter_0010_mutant_ignore_increment (\n input wire clk,\n input wire rst,\n input wire load,\n input wire increment,\n output reg [2:0] count,\n output wire nonzero\n);\n\n always @(posedge clk) begin\n if (rst) begin\n count <= 3'd0;\n ... |
counter_0010 | counter | Loadable counter where load has priority over increment. | function_update.sv | module counter_0010_function_update (
input wire clk,
input wire rst,
input wire load,
input wire increment,
output reg [2:0] count,
output wire nonzero
);
function automatic [2:0] compute_next_count;
input [2:0] current;
input load;
input increment;
beg... | {
"design_id": "counter_0010",
"category": "counter",
"model_type": "register_rules",
"template": "priority_load_counter",
"description": "Loadable counter where load has priority over increment.",
"clock": {
"name": "clk",
"edge": "posedge"
},
"reset": {
"name": "rst",
"active": "high",... | // Gold interface properties for counter_0010
// P1_RESET: reset restores the register to its reset value
property p_reset_value;
@(posedge clk) (rst) |=> (count == 3'd0);
endproperty
assert property (p_reset_value);
// P2_NONZERO: nonzero is consistent with the observable register value
property p_nonzero;
@... | [
{
"id": "P1_RESET",
"sva_name": "p_reset_value",
"type": "next_cycle_implication",
"natural_language": "reset restores the register to its reset value",
"antecedent": "rst",
"consequent": "count == 3'd0",
"delay": 1
},
{
"id": "P2_NONZERO",
"sva_name": "p_nonzero",
"type"... | {"ignore_increment.sv": "module counter_0010_mutant_ignore_increment (\n input wire clk,\n input wire rst,\n input wire load,\n input wire increment,\n output reg [2:0] count,\n output wire nonzero\n);\n\n always @(posedge clk) begin\n if (rst) begin\n count <= 3'd0;\n ... |
fifo_0001 | fifo_control | One-entry elastic FIFO allowing simultaneous pop and replacement push. | canonical_next.sv | module fifo_0001_canonical_next (
input wire clk,
input wire rst,
input wire push,
input wire pop,
input wire [1:0] din,
output wire [1:0] dout,
output wire valid,
output wire ready
);
reg [1:0] data_reg;
reg valid_reg;
reg [1:0] next_data_reg;
reg next_valid_reg;
... | {
"design_id": "fifo_0001",
"category": "fifo_control",
"model_type": "multi_register_rules",
"template": "elastic_single_entry_fifo",
"description": "One-entry elastic FIFO allowing simultaneous pop and replacement push.",
"clock": {
"name": "clk",
"edge": "posedge"
},
"reset": {
"name": "r... | // P1_READY: ready reflects whether a push can be accepted
property p_ready;
@(posedge clk) disable iff (rst) (ready == (!valid || pop));
endproperty
assert property (p_ready);
// P2_RESET_EMPTY: reset leaves the buffer empty
property p_reset_empty;
@(posedge clk) (rst) |=> (!valid);
endproperty
assert propert... | [
{
"id": "P1_READY",
"sva_name": "p_ready",
"type": "invariant",
"natural_language": "ready reflects whether a push can be accepted",
"disable": "rst",
"expression": "ready == (!valid || pop)"
},
{
"id": "P2_RESET_EMPTY",
"sva_name": "p_reset_empty",
"type": "next_cycle_implic... | {"drop_replacement.sv": "module fifo_0001_mutant_drop_replacement (\n input wire clk,\n input wire rst,\n input wire push,\n input wire pop,\n input wire [1:0] din,\n output wire [1:0] dout,\n output wire valid,\n output wire ready\n);\n\n reg [1:0] data_reg;\n reg valid_reg;\n\n a... |
fifo_0001 | fifo_control | One-entry elastic FIFO allowing simultaneous pop and replacement push. | sequential_priority.sv | module fifo_0001_sequential_priority (
input wire clk,
input wire rst,
input wire push,
input wire pop,
input wire [1:0] din,
output wire [1:0] dout,
output wire valid,
output wire ready
);
reg [1:0] data_reg;
reg valid_reg;
always @(posedge clk) begin
if (rst)... | {
"design_id": "fifo_0001",
"category": "fifo_control",
"model_type": "multi_register_rules",
"template": "elastic_single_entry_fifo",
"description": "One-entry elastic FIFO allowing simultaneous pop and replacement push.",
"clock": {
"name": "clk",
"edge": "posedge"
},
"reset": {
"name": "r... | // P1_READY: ready reflects whether a push can be accepted
property p_ready;
@(posedge clk) disable iff (rst) (ready == (!valid || pop));
endproperty
assert property (p_ready);
// P2_RESET_EMPTY: reset leaves the buffer empty
property p_reset_empty;
@(posedge clk) (rst) |=> (!valid);
endproperty
assert propert... | [
{
"id": "P1_READY",
"sva_name": "p_ready",
"type": "invariant",
"natural_language": "ready reflects whether a push can be accepted",
"disable": "rst",
"expression": "ready == (!valid || pop)"
},
{
"id": "P2_RESET_EMPTY",
"sva_name": "p_reset_empty",
"type": "next_cycle_implic... | {"drop_replacement.sv": "module fifo_0001_mutant_drop_replacement (\n input wire clk,\n input wire rst,\n input wire push,\n input wire pop,\n input wire [1:0] din,\n output wire [1:0] dout,\n output wire valid,\n output wire ready\n);\n\n reg [1:0] data_reg;\n reg valid_reg;\n\n a... |
fifo_0001 | fifo_control | One-entry elastic FIFO allowing simultaneous pop and replacement push. | ternary_next.sv | module fifo_0001_ternary_next (
input wire clk,
input wire rst,
input wire push,
input wire pop,
input wire [1:0] din,
output wire [1:0] dout,
output wire valid,
output wire ready
);
reg [1:0] data_reg;
reg valid_reg;
wire [1:0] next_data_reg;
wire next_valid_reg;
... | {
"design_id": "fifo_0001",
"category": "fifo_control",
"model_type": "multi_register_rules",
"template": "elastic_single_entry_fifo",
"description": "One-entry elastic FIFO allowing simultaneous pop and replacement push.",
"clock": {
"name": "clk",
"edge": "posedge"
},
"reset": {
"name": "r... | // P1_READY: ready reflects whether a push can be accepted
property p_ready;
@(posedge clk) disable iff (rst) (ready == (!valid || pop));
endproperty
assert property (p_ready);
// P2_RESET_EMPTY: reset leaves the buffer empty
property p_reset_empty;
@(posedge clk) (rst) |=> (!valid);
endproperty
assert propert... | [
{
"id": "P1_READY",
"sva_name": "p_ready",
"type": "invariant",
"natural_language": "ready reflects whether a push can be accepted",
"disable": "rst",
"expression": "ready == (!valid || pop)"
},
{
"id": "P2_RESET_EMPTY",
"sva_name": "p_reset_empty",
"type": "next_cycle_implic... | {"drop_replacement.sv": "module fifo_0001_mutant_drop_replacement (\n input wire clk,\n input wire rst,\n input wire push,\n input wire pop,\n input wire [1:0] din,\n output wire [1:0] dout,\n output wire valid,\n output wire ready\n);\n\n reg [1:0] data_reg;\n reg valid_reg;\n\n a... |
fifo_0001 | fifo_control | One-entry elastic FIFO allowing simultaneous pop and replacement push. | function_update.sv | module fifo_0001_function_update (
input wire clk,
input wire rst,
input wire push,
input wire pop,
input wire [1:0] din,
output wire [1:0] dout,
output wire valid,
output wire ready
);
reg [1:0] data_reg;
reg valid_reg;
function automatic [1:0] compute_next_data_reg;
... | {
"design_id": "fifo_0001",
"category": "fifo_control",
"model_type": "multi_register_rules",
"template": "elastic_single_entry_fifo",
"description": "One-entry elastic FIFO allowing simultaneous pop and replacement push.",
"clock": {
"name": "clk",
"edge": "posedge"
},
"reset": {
"name": "r... | // P1_READY: ready reflects whether a push can be accepted
property p_ready;
@(posedge clk) disable iff (rst) (ready == (!valid || pop));
endproperty
assert property (p_ready);
// P2_RESET_EMPTY: reset leaves the buffer empty
property p_reset_empty;
@(posedge clk) (rst) |=> (!valid);
endproperty
assert propert... | [
{
"id": "P1_READY",
"sva_name": "p_ready",
"type": "invariant",
"natural_language": "ready reflects whether a push can be accepted",
"disable": "rst",
"expression": "ready == (!valid || pop)"
},
{
"id": "P2_RESET_EMPTY",
"sva_name": "p_reset_empty",
"type": "next_cycle_implic... | {"drop_replacement.sv": "module fifo_0001_mutant_drop_replacement (\n input wire clk,\n input wire rst,\n input wire push,\n input wire pop,\n input wire [1:0] din,\n output wire [1:0] dout,\n output wire valid,\n output wire ready\n);\n\n reg [1:0] data_reg;\n reg valid_reg;\n\n a... |
fifo_0002 | fifo_control | One-entry FIFO that only accepts pushes while empty. | canonical_next.sv | module fifo_0002_canonical_next (
input wire clk,
input wire rst,
input wire push,
input wire pop,
input wire [1:0] din,
output wire [1:0] dout,
output wire valid,
output wire ready
);
reg [1:0] data_reg;
reg valid_reg;
reg [1:0] next_data_reg;
reg next_valid_reg;
... | {
"design_id": "fifo_0002",
"category": "fifo_control",
"model_type": "multi_register_rules",
"template": "strict_single_entry_fifo",
"description": "One-entry FIFO that only accepts pushes while empty.",
"clock": {
"name": "clk",
"edge": "posedge"
},
"reset": {
"name": "rst",
"active": ... | // P1_READY: ready is asserted exactly when the buffer is empty
property p_ready;
@(posedge clk) disable iff (rst) (ready == !valid);
endproperty
assert property (p_ready);
// P2_RESET: reset empties the buffer
property p_reset;
@(posedge clk) (rst) |=> (!valid);
endproperty
assert property (p_reset);
// P3_P... | [
{
"id": "P1_READY",
"sva_name": "p_ready",
"type": "invariant",
"natural_language": "ready is asserted exactly when the buffer is empty",
"disable": "rst",
"expression": "ready == !valid"
},
{
"id": "P2_RESET",
"sva_name": "p_reset",
"type": "next_cycle_implication",
"nat... | {"ignore_pop.sv": "module fifo_0002_mutant_ignore_pop (\n input wire clk,\n input wire rst,\n input wire push,\n input wire pop,\n input wire [1:0] din,\n output wire [1:0] dout,\n output wire valid,\n output wire ready\n);\n\n reg [1:0] data_reg;\n reg valid_reg;\n\n always @(pose... |
fifo_0002 | fifo_control | One-entry FIFO that only accepts pushes while empty. | sequential_priority.sv | module fifo_0002_sequential_priority (
input wire clk,
input wire rst,
input wire push,
input wire pop,
input wire [1:0] din,
output wire [1:0] dout,
output wire valid,
output wire ready
);
reg [1:0] data_reg;
reg valid_reg;
always @(posedge clk) begin
if (rst)... | {
"design_id": "fifo_0002",
"category": "fifo_control",
"model_type": "multi_register_rules",
"template": "strict_single_entry_fifo",
"description": "One-entry FIFO that only accepts pushes while empty.",
"clock": {
"name": "clk",
"edge": "posedge"
},
"reset": {
"name": "rst",
"active": ... | // P1_READY: ready is asserted exactly when the buffer is empty
property p_ready;
@(posedge clk) disable iff (rst) (ready == !valid);
endproperty
assert property (p_ready);
// P2_RESET: reset empties the buffer
property p_reset;
@(posedge clk) (rst) |=> (!valid);
endproperty
assert property (p_reset);
// P3_P... | [
{
"id": "P1_READY",
"sva_name": "p_ready",
"type": "invariant",
"natural_language": "ready is asserted exactly when the buffer is empty",
"disable": "rst",
"expression": "ready == !valid"
},
{
"id": "P2_RESET",
"sva_name": "p_reset",
"type": "next_cycle_implication",
"nat... | {"ignore_pop.sv": "module fifo_0002_mutant_ignore_pop (\n input wire clk,\n input wire rst,\n input wire push,\n input wire pop,\n input wire [1:0] din,\n output wire [1:0] dout,\n output wire valid,\n output wire ready\n);\n\n reg [1:0] data_reg;\n reg valid_reg;\n\n always @(pose... |
fifo_0002 | fifo_control | One-entry FIFO that only accepts pushes while empty. | ternary_next.sv | module fifo_0002_ternary_next (
input wire clk,
input wire rst,
input wire push,
input wire pop,
input wire [1:0] din,
output wire [1:0] dout,
output wire valid,
output wire ready
);
reg [1:0] data_reg;
reg valid_reg;
wire [1:0] next_data_reg;
wire next_valid_reg;
... | {
"design_id": "fifo_0002",
"category": "fifo_control",
"model_type": "multi_register_rules",
"template": "strict_single_entry_fifo",
"description": "One-entry FIFO that only accepts pushes while empty.",
"clock": {
"name": "clk",
"edge": "posedge"
},
"reset": {
"name": "rst",
"active": ... | // P1_READY: ready is asserted exactly when the buffer is empty
property p_ready;
@(posedge clk) disable iff (rst) (ready == !valid);
endproperty
assert property (p_ready);
// P2_RESET: reset empties the buffer
property p_reset;
@(posedge clk) (rst) |=> (!valid);
endproperty
assert property (p_reset);
// P3_P... | [
{
"id": "P1_READY",
"sva_name": "p_ready",
"type": "invariant",
"natural_language": "ready is asserted exactly when the buffer is empty",
"disable": "rst",
"expression": "ready == !valid"
},
{
"id": "P2_RESET",
"sva_name": "p_reset",
"type": "next_cycle_implication",
"nat... | {"ignore_pop.sv": "module fifo_0002_mutant_ignore_pop (\n input wire clk,\n input wire rst,\n input wire push,\n input wire pop,\n input wire [1:0] din,\n output wire [1:0] dout,\n output wire valid,\n output wire ready\n);\n\n reg [1:0] data_reg;\n reg valid_reg;\n\n always @(pose... |
fifo_0002 | fifo_control | One-entry FIFO that only accepts pushes while empty. | function_update.sv | module fifo_0002_function_update (
input wire clk,
input wire rst,
input wire push,
input wire pop,
input wire [1:0] din,
output wire [1:0] dout,
output wire valid,
output wire ready
);
reg [1:0] data_reg;
reg valid_reg;
function automatic [1:0] compute_next_data_reg;
... | {
"design_id": "fifo_0002",
"category": "fifo_control",
"model_type": "multi_register_rules",
"template": "strict_single_entry_fifo",
"description": "One-entry FIFO that only accepts pushes while empty.",
"clock": {
"name": "clk",
"edge": "posedge"
},
"reset": {
"name": "rst",
"active": ... | // P1_READY: ready is asserted exactly when the buffer is empty
property p_ready;
@(posedge clk) disable iff (rst) (ready == !valid);
endproperty
assert property (p_ready);
// P2_RESET: reset empties the buffer
property p_reset;
@(posedge clk) (rst) |=> (!valid);
endproperty
assert property (p_reset);
// P3_P... | [
{
"id": "P1_READY",
"sva_name": "p_ready",
"type": "invariant",
"natural_language": "ready is asserted exactly when the buffer is empty",
"disable": "rst",
"expression": "ready == !valid"
},
{
"id": "P2_RESET",
"sva_name": "p_reset",
"type": "next_cycle_implication",
"nat... | {"ignore_pop.sv": "module fifo_0002_mutant_ignore_pop (\n input wire clk,\n input wire rst,\n input wire push,\n input wire pop,\n input wire [1:0] din,\n output wire [1:0] dout,\n output wire valid,\n output wire ready\n);\n\n reg [1:0] data_reg;\n reg valid_reg;\n\n always @(pose... |
fifo_0003 | fifo_control | Single-entry mailbox where a new push always replaces the stored item. | canonical_next.sv | module fifo_0003_canonical_next (
input wire clk,
input wire rst,
input wire push,
input wire pop,
input wire [1:0] din,
output wire [1:0] dout,
output wire valid,
output wire ready
);
reg [1:0] data_reg;
reg valid_reg;
reg [1:0] next_data_reg;
reg next_valid_reg;
... | {
"design_id": "fifo_0003",
"category": "fifo_control",
"model_type": "multi_register_rules",
"template": "overwrite_mailbox",
"description": "Single-entry mailbox where a new push always replaces the stored item.",
"clock": {
"name": "clk",
"edge": "posedge"
},
"reset": {
"name": "rst",
... | // P1_ALWAYS_READY: the overwrite mailbox is always ready
property p_always_ready;
@(posedge clk) disable iff (rst) (ready);
endproperty
assert property (p_always_ready);
// P2_RESET: reset empties the mailbox
property p_reset;
@(posedge clk) (rst) |=> (!valid);
endproperty
assert property (p_reset);
// P3_PU... | [
{
"id": "P1_ALWAYS_READY",
"sva_name": "p_always_ready",
"type": "invariant",
"natural_language": "the overwrite mailbox is always ready",
"disable": "rst",
"expression": "ready"
},
{
"id": "P2_RESET",
"sva_name": "p_reset",
"type": "next_cycle_implication",
"natural_lang... | {"drop_push_valid.sv": "module fifo_0003_mutant_drop_push_valid (\n input wire clk,\n input wire rst,\n input wire push,\n input wire pop,\n input wire [1:0] din,\n output wire [1:0] dout,\n output wire valid,\n output wire ready\n);\n\n reg [1:0] data_reg;\n reg valid_reg;\n\n alw... |
fifo_0003 | fifo_control | Single-entry mailbox where a new push always replaces the stored item. | sequential_priority.sv | module fifo_0003_sequential_priority (
input wire clk,
input wire rst,
input wire push,
input wire pop,
input wire [1:0] din,
output wire [1:0] dout,
output wire valid,
output wire ready
);
reg [1:0] data_reg;
reg valid_reg;
always @(posedge clk) begin
if (rst)... | {
"design_id": "fifo_0003",
"category": "fifo_control",
"model_type": "multi_register_rules",
"template": "overwrite_mailbox",
"description": "Single-entry mailbox where a new push always replaces the stored item.",
"clock": {
"name": "clk",
"edge": "posedge"
},
"reset": {
"name": "rst",
... | // P1_ALWAYS_READY: the overwrite mailbox is always ready
property p_always_ready;
@(posedge clk) disable iff (rst) (ready);
endproperty
assert property (p_always_ready);
// P2_RESET: reset empties the mailbox
property p_reset;
@(posedge clk) (rst) |=> (!valid);
endproperty
assert property (p_reset);
// P3_PU... | [
{
"id": "P1_ALWAYS_READY",
"sva_name": "p_always_ready",
"type": "invariant",
"natural_language": "the overwrite mailbox is always ready",
"disable": "rst",
"expression": "ready"
},
{
"id": "P2_RESET",
"sva_name": "p_reset",
"type": "next_cycle_implication",
"natural_lang... | {"drop_push_valid.sv": "module fifo_0003_mutant_drop_push_valid (\n input wire clk,\n input wire rst,\n input wire push,\n input wire pop,\n input wire [1:0] din,\n output wire [1:0] dout,\n output wire valid,\n output wire ready\n);\n\n reg [1:0] data_reg;\n reg valid_reg;\n\n alw... |
fifo_0003 | fifo_control | Single-entry mailbox where a new push always replaces the stored item. | ternary_next.sv | module fifo_0003_ternary_next (
input wire clk,
input wire rst,
input wire push,
input wire pop,
input wire [1:0] din,
output wire [1:0] dout,
output wire valid,
output wire ready
);
reg [1:0] data_reg;
reg valid_reg;
wire [1:0] next_data_reg;
wire next_valid_reg;
... | {
"design_id": "fifo_0003",
"category": "fifo_control",
"model_type": "multi_register_rules",
"template": "overwrite_mailbox",
"description": "Single-entry mailbox where a new push always replaces the stored item.",
"clock": {
"name": "clk",
"edge": "posedge"
},
"reset": {
"name": "rst",
... | // P1_ALWAYS_READY: the overwrite mailbox is always ready
property p_always_ready;
@(posedge clk) disable iff (rst) (ready);
endproperty
assert property (p_always_ready);
// P2_RESET: reset empties the mailbox
property p_reset;
@(posedge clk) (rst) |=> (!valid);
endproperty
assert property (p_reset);
// P3_PU... | [
{
"id": "P1_ALWAYS_READY",
"sva_name": "p_always_ready",
"type": "invariant",
"natural_language": "the overwrite mailbox is always ready",
"disable": "rst",
"expression": "ready"
},
{
"id": "P2_RESET",
"sva_name": "p_reset",
"type": "next_cycle_implication",
"natural_lang... | {"drop_push_valid.sv": "module fifo_0003_mutant_drop_push_valid (\n input wire clk,\n input wire rst,\n input wire push,\n input wire pop,\n input wire [1:0] din,\n output wire [1:0] dout,\n output wire valid,\n output wire ready\n);\n\n reg [1:0] data_reg;\n reg valid_reg;\n\n alw... |
fifo_0003 | fifo_control | Single-entry mailbox where a new push always replaces the stored item. | function_update.sv | module fifo_0003_function_update (
input wire clk,
input wire rst,
input wire push,
input wire pop,
input wire [1:0] din,
output wire [1:0] dout,
output wire valid,
output wire ready
);
reg [1:0] data_reg;
reg valid_reg;
function automatic [1:0] compute_next_data_reg;
... | {
"design_id": "fifo_0003",
"category": "fifo_control",
"model_type": "multi_register_rules",
"template": "overwrite_mailbox",
"description": "Single-entry mailbox where a new push always replaces the stored item.",
"clock": {
"name": "clk",
"edge": "posedge"
},
"reset": {
"name": "rst",
... | // P1_ALWAYS_READY: the overwrite mailbox is always ready
property p_always_ready;
@(posedge clk) disable iff (rst) (ready);
endproperty
assert property (p_always_ready);
// P2_RESET: reset empties the mailbox
property p_reset;
@(posedge clk) (rst) |=> (!valid);
endproperty
assert property (p_reset);
// P3_PU... | [
{
"id": "P1_ALWAYS_READY",
"sva_name": "p_always_ready",
"type": "invariant",
"natural_language": "the overwrite mailbox is always ready",
"disable": "rst",
"expression": "ready"
},
{
"id": "P2_RESET",
"sva_name": "p_reset",
"type": "next_cycle_implication",
"natural_lang... | {"drop_push_valid.sv": "module fifo_0003_mutant_drop_push_valid (\n input wire clk,\n input wire rst,\n input wire push,\n input wire pop,\n input wire [1:0] din,\n output wire [1:0] dout,\n output wire valid,\n output wire ready\n);\n\n reg [1:0] data_reg;\n reg valid_reg;\n\n alw... |
fifo_0004 | fifo_control | Elastic one-entry buffer with a flush operation that has highest priority. | canonical_next.sv | module fifo_0004_canonical_next (
input wire clk,
input wire rst,
input wire push,
input wire pop,
input wire flush,
input wire [1:0] din,
output wire [1:0] dout,
output wire valid,
output wire ready
);
reg [1:0] data_reg;
reg valid_reg;
reg [1:0] next_data_reg;
... | {
"design_id": "fifo_0004",
"category": "fifo_control",
"model_type": "multi_register_rules",
"template": "flushable_elastic_buffer",
"description": "Elastic one-entry buffer with a flush operation that has highest priority.",
"clock": {
"name": "clk",
"edge": "posedge"
},
"reset": {
"name":... | // P1_READY: ready follows elastic-buffer availability
property p_ready;
@(posedge clk) disable iff (rst) (ready == (!valid || pop));
endproperty
assert property (p_ready);
// P2_FLUSH: flush clears both validity and stored data
property p_flush;
@(posedge clk) disable iff (rst) (flush) |=> (!valid && (dout ==... | [
{
"id": "P1_READY",
"sva_name": "p_ready",
"type": "invariant",
"natural_language": "ready follows elastic-buffer availability",
"disable": "rst",
"expression": "ready == (!valid || pop)"
},
{
"id": "P2_FLUSH",
"sva_name": "p_flush",
"type": "next_cycle_implication",
"nat... | {"ignore_flush.sv": "module fifo_0004_mutant_ignore_flush (\n input wire clk,\n input wire rst,\n input wire push,\n input wire pop,\n input wire flush,\n input wire [1:0] din,\n output wire [1:0] dout,\n output wire valid,\n output wire ready\n);\n\n reg [1:0] data_reg;\n reg val... |
fifo_0004 | fifo_control | Elastic one-entry buffer with a flush operation that has highest priority. | sequential_priority.sv | module fifo_0004_sequential_priority (
input wire clk,
input wire rst,
input wire push,
input wire pop,
input wire flush,
input wire [1:0] din,
output wire [1:0] dout,
output wire valid,
output wire ready
);
reg [1:0] data_reg;
reg valid_reg;
always @(posedge clk)... | {
"design_id": "fifo_0004",
"category": "fifo_control",
"model_type": "multi_register_rules",
"template": "flushable_elastic_buffer",
"description": "Elastic one-entry buffer with a flush operation that has highest priority.",
"clock": {
"name": "clk",
"edge": "posedge"
},
"reset": {
"name":... | // P1_READY: ready follows elastic-buffer availability
property p_ready;
@(posedge clk) disable iff (rst) (ready == (!valid || pop));
endproperty
assert property (p_ready);
// P2_FLUSH: flush clears both validity and stored data
property p_flush;
@(posedge clk) disable iff (rst) (flush) |=> (!valid && (dout ==... | [
{
"id": "P1_READY",
"sva_name": "p_ready",
"type": "invariant",
"natural_language": "ready follows elastic-buffer availability",
"disable": "rst",
"expression": "ready == (!valid || pop)"
},
{
"id": "P2_FLUSH",
"sva_name": "p_flush",
"type": "next_cycle_implication",
"nat... | {"ignore_flush.sv": "module fifo_0004_mutant_ignore_flush (\n input wire clk,\n input wire rst,\n input wire push,\n input wire pop,\n input wire flush,\n input wire [1:0] din,\n output wire [1:0] dout,\n output wire valid,\n output wire ready\n);\n\n reg [1:0] data_reg;\n reg val... |
fifo_0004 | fifo_control | Elastic one-entry buffer with a flush operation that has highest priority. | ternary_next.sv | module fifo_0004_ternary_next (
input wire clk,
input wire rst,
input wire push,
input wire pop,
input wire flush,
input wire [1:0] din,
output wire [1:0] dout,
output wire valid,
output wire ready
);
reg [1:0] data_reg;
reg valid_reg;
wire [1:0] next_data_reg;
... | {
"design_id": "fifo_0004",
"category": "fifo_control",
"model_type": "multi_register_rules",
"template": "flushable_elastic_buffer",
"description": "Elastic one-entry buffer with a flush operation that has highest priority.",
"clock": {
"name": "clk",
"edge": "posedge"
},
"reset": {
"name":... | // P1_READY: ready follows elastic-buffer availability
property p_ready;
@(posedge clk) disable iff (rst) (ready == (!valid || pop));
endproperty
assert property (p_ready);
// P2_FLUSH: flush clears both validity and stored data
property p_flush;
@(posedge clk) disable iff (rst) (flush) |=> (!valid && (dout ==... | [
{
"id": "P1_READY",
"sva_name": "p_ready",
"type": "invariant",
"natural_language": "ready follows elastic-buffer availability",
"disable": "rst",
"expression": "ready == (!valid || pop)"
},
{
"id": "P2_FLUSH",
"sva_name": "p_flush",
"type": "next_cycle_implication",
"nat... | {"ignore_flush.sv": "module fifo_0004_mutant_ignore_flush (\n input wire clk,\n input wire rst,\n input wire push,\n input wire pop,\n input wire flush,\n input wire [1:0] din,\n output wire [1:0] dout,\n output wire valid,\n output wire ready\n);\n\n reg [1:0] data_reg;\n reg val... |
fifo_0004 | fifo_control | Elastic one-entry buffer with a flush operation that has highest priority. | function_update.sv | module fifo_0004_function_update (
input wire clk,
input wire rst,
input wire push,
input wire pop,
input wire flush,
input wire [1:0] din,
output wire [1:0] dout,
output wire valid,
output wire ready
);
reg [1:0] data_reg;
reg valid_reg;
function automatic [1:0] ... | {
"design_id": "fifo_0004",
"category": "fifo_control",
"model_type": "multi_register_rules",
"template": "flushable_elastic_buffer",
"description": "Elastic one-entry buffer with a flush operation that has highest priority.",
"clock": {
"name": "clk",
"edge": "posedge"
},
"reset": {
"name":... | // P1_READY: ready follows elastic-buffer availability
property p_ready;
@(posedge clk) disable iff (rst) (ready == (!valid || pop));
endproperty
assert property (p_ready);
// P2_FLUSH: flush clears both validity and stored data
property p_flush;
@(posedge clk) disable iff (rst) (flush) |=> (!valid && (dout ==... | [
{
"id": "P1_READY",
"sva_name": "p_ready",
"type": "invariant",
"natural_language": "ready follows elastic-buffer availability",
"disable": "rst",
"expression": "ready == (!valid || pop)"
},
{
"id": "P2_FLUSH",
"sva_name": "p_flush",
"type": "next_cycle_implication",
"nat... | {"ignore_flush.sv": "module fifo_0004_mutant_ignore_flush (\n input wire clk,\n input wire rst,\n input wire push,\n input wire pop,\n input wire flush,\n input wire [1:0] din,\n output wire [1:0] dout,\n output wire valid,\n output wire ready\n);\n\n reg [1:0] data_reg;\n reg val... |
fifo_0005 | fifo_control | Two-entry queue with head, tail, and explicit occupancy tracking. | canonical_next.sv | module fifo_0005_canonical_next (
input wire clk,
input wire rst,
input wire push,
input wire pop,
input wire [1:0] din,
output wire [1:0] dout,
output wire [1:0] count,
output wire empty,
output wire full,
output wire ready
);
reg [1:0] head_reg;
reg [1:0] tail_reg... | {
"design_id": "fifo_0005",
"category": "fifo_control",
"model_type": "multi_register_rules",
"template": "two_entry_queue",
"description": "Two-entry queue with head, tail, and explicit occupancy tracking.",
"clock": {
"name": "clk",
"edge": "posedge"
},
"reset": {
"name": "rst",
"activ... | // P1_BOUNDS: queue occupancy never exceeds two
property p_bounds;
@(posedge clk) disable iff (rst) (count <= 2'd2);
endproperty
assert property (p_bounds);
// P2_FLAGS: empty full and ready agree with occupancy
property p_flags;
@(posedge clk) disable iff (rst) ((empty == (count == 2'd0)) && (full == (count =... | [
{
"id": "P1_BOUNDS",
"sva_name": "p_bounds",
"type": "invariant",
"natural_language": "queue occupancy never exceeds two",
"disable": "rst",
"expression": "count <= 2'd2"
},
{
"id": "P2_FLAGS",
"sva_name": "p_flags",
"type": "invariant",
"natural_language": "empty full an... | {"ignore_pop.sv": "module fifo_0005_mutant_ignore_pop (\n input wire clk,\n input wire rst,\n input wire push,\n input wire pop,\n input wire [1:0] din,\n output wire [1:0] dout,\n output wire [1:0] count,\n output wire empty,\n output wire full,\n output wire ready\n);\n\n reg [1:... |
fifo_0005 | fifo_control | Two-entry queue with head, tail, and explicit occupancy tracking. | sequential_priority.sv | module fifo_0005_sequential_priority (
input wire clk,
input wire rst,
input wire push,
input wire pop,
input wire [1:0] din,
output wire [1:0] dout,
output wire [1:0] count,
output wire empty,
output wire full,
output wire ready
);
reg [1:0] head_reg;
reg [1:0] tai... | {
"design_id": "fifo_0005",
"category": "fifo_control",
"model_type": "multi_register_rules",
"template": "two_entry_queue",
"description": "Two-entry queue with head, tail, and explicit occupancy tracking.",
"clock": {
"name": "clk",
"edge": "posedge"
},
"reset": {
"name": "rst",
"activ... | // P1_BOUNDS: queue occupancy never exceeds two
property p_bounds;
@(posedge clk) disable iff (rst) (count <= 2'd2);
endproperty
assert property (p_bounds);
// P2_FLAGS: empty full and ready agree with occupancy
property p_flags;
@(posedge clk) disable iff (rst) ((empty == (count == 2'd0)) && (full == (count =... | [
{
"id": "P1_BOUNDS",
"sva_name": "p_bounds",
"type": "invariant",
"natural_language": "queue occupancy never exceeds two",
"disable": "rst",
"expression": "count <= 2'd2"
},
{
"id": "P2_FLAGS",
"sva_name": "p_flags",
"type": "invariant",
"natural_language": "empty full an... | {"ignore_pop.sv": "module fifo_0005_mutant_ignore_pop (\n input wire clk,\n input wire rst,\n input wire push,\n input wire pop,\n input wire [1:0] din,\n output wire [1:0] dout,\n output wire [1:0] count,\n output wire empty,\n output wire full,\n output wire ready\n);\n\n reg [1:... |
fifo_0005 | fifo_control | Two-entry queue with head, tail, and explicit occupancy tracking. | ternary_next.sv | module fifo_0005_ternary_next (
input wire clk,
input wire rst,
input wire push,
input wire pop,
input wire [1:0] din,
output wire [1:0] dout,
output wire [1:0] count,
output wire empty,
output wire full,
output wire ready
);
reg [1:0] head_reg;
reg [1:0] tail_reg;
... | {
"design_id": "fifo_0005",
"category": "fifo_control",
"model_type": "multi_register_rules",
"template": "two_entry_queue",
"description": "Two-entry queue with head, tail, and explicit occupancy tracking.",
"clock": {
"name": "clk",
"edge": "posedge"
},
"reset": {
"name": "rst",
"activ... | // P1_BOUNDS: queue occupancy never exceeds two
property p_bounds;
@(posedge clk) disable iff (rst) (count <= 2'd2);
endproperty
assert property (p_bounds);
// P2_FLAGS: empty full and ready agree with occupancy
property p_flags;
@(posedge clk) disable iff (rst) ((empty == (count == 2'd0)) && (full == (count =... | [
{
"id": "P1_BOUNDS",
"sva_name": "p_bounds",
"type": "invariant",
"natural_language": "queue occupancy never exceeds two",
"disable": "rst",
"expression": "count <= 2'd2"
},
{
"id": "P2_FLAGS",
"sva_name": "p_flags",
"type": "invariant",
"natural_language": "empty full an... | {"ignore_pop.sv": "module fifo_0005_mutant_ignore_pop (\n input wire clk,\n input wire rst,\n input wire push,\n input wire pop,\n input wire [1:0] din,\n output wire [1:0] dout,\n output wire [1:0] count,\n output wire empty,\n output wire full,\n output wire ready\n);\n\n reg [1:... |
fifo_0005 | fifo_control | Two-entry queue with head, tail, and explicit occupancy tracking. | function_update.sv | module fifo_0005_function_update (
input wire clk,
input wire rst,
input wire push,
input wire pop,
input wire [1:0] din,
output wire [1:0] dout,
output wire [1:0] count,
output wire empty,
output wire full,
output wire ready
);
reg [1:0] head_reg;
reg [1:0] tail_re... | {
"design_id": "fifo_0005",
"category": "fifo_control",
"model_type": "multi_register_rules",
"template": "two_entry_queue",
"description": "Two-entry queue with head, tail, and explicit occupancy tracking.",
"clock": {
"name": "clk",
"edge": "posedge"
},
"reset": {
"name": "rst",
"activ... | // P1_BOUNDS: queue occupancy never exceeds two
property p_bounds;
@(posedge clk) disable iff (rst) (count <= 2'd2);
endproperty
assert property (p_bounds);
// P2_FLAGS: empty full and ready agree with occupancy
property p_flags;
@(posedge clk) disable iff (rst) ((empty == (count == 2'd0)) && (full == (count =... | [
{
"id": "P1_BOUNDS",
"sva_name": "p_bounds",
"type": "invariant",
"natural_language": "queue occupancy never exceeds two",
"disable": "rst",
"expression": "count <= 2'd2"
},
{
"id": "P2_FLAGS",
"sva_name": "p_flags",
"type": "invariant",
"natural_language": "empty full an... | {"ignore_pop.sv": "module fifo_0005_mutant_ignore_pop (\n input wire clk,\n input wire rst,\n input wire push,\n input wire pop,\n input wire [1:0] din,\n output wire [1:0] dout,\n output wire [1:0] count,\n output wire empty,\n output wire full,\n output wire ready\n);\n\n reg [1:... |
fifo_0010 | fifo_control | Four-slot FIFO occupancy counter with simultaneous push/pop cancellation and overflow/underflow protection. | canonical_next.sv | module fifo_0010_canonical_next (
input wire clk,
input wire rst,
input wire push,
input wire pop,
input wire flush,
output reg [2:0] count,
output wire empty,
output wire full,
output wire almost_full
);
reg [2:0] next_count;
always @* begin
if (flush) next_c... | {
"design_id": "fifo_0010",
"category": "fifo_control",
"model_type": "register_rules",
"template": "four_slot_occupancy_counter",
"description": "Four-slot FIFO occupancy counter with simultaneous push/pop cancellation and overflow/underflow protection.",
"clock": {
"name": "clk",
"edge": "posedge"... | // Gold interface properties for fifo_0010
// P1_EMPTY: empty reflects zero occupancy
property p_empty;
@(posedge clk) disable iff (rst) (empty == (count == 3'd0));
endproperty
assert property (p_empty);
// P2_FULL: full reflects four entries
property p_full;
@(posedge clk) disable iff (rst) (full == (count =... | [
{
"id": "P1_EMPTY",
"sva_name": "p_empty",
"type": "invariant",
"natural_language": "empty reflects zero occupancy",
"expression": "empty == (count == 3'd0)",
"disable": "rst"
},
{
"id": "P2_FULL",
"sva_name": "p_full",
"type": "invariant",
"natural_language": "full refle... | {"ignore_flush.sv": "module fifo_0010_mutant_ignore_flush (\n input wire clk,\n input wire rst,\n input wire push,\n input wire pop,\n input wire flush,\n output reg [2:0] count,\n output wire empty,\n output wire full,\n output wire almost_full\n);\n\n always @(posedge clk) begin\n ... |
fifo_0010 | fifo_control | Four-slot FIFO occupancy counter with simultaneous push/pop cancellation and overflow/underflow protection. | sequential_priority.sv | module fifo_0010_sequential_priority (
input wire clk,
input wire rst,
input wire push,
input wire pop,
input wire flush,
output reg [2:0] count,
output wire empty,
output wire full,
output wire almost_full
);
always @(posedge clk) begin
if (rst) begin
... | {
"design_id": "fifo_0010",
"category": "fifo_control",
"model_type": "register_rules",
"template": "four_slot_occupancy_counter",
"description": "Four-slot FIFO occupancy counter with simultaneous push/pop cancellation and overflow/underflow protection.",
"clock": {
"name": "clk",
"edge": "posedge"... | // Gold interface properties for fifo_0010
// P1_EMPTY: empty reflects zero occupancy
property p_empty;
@(posedge clk) disable iff (rst) (empty == (count == 3'd0));
endproperty
assert property (p_empty);
// P2_FULL: full reflects four entries
property p_full;
@(posedge clk) disable iff (rst) (full == (count =... | [
{
"id": "P1_EMPTY",
"sva_name": "p_empty",
"type": "invariant",
"natural_language": "empty reflects zero occupancy",
"expression": "empty == (count == 3'd0)",
"disable": "rst"
},
{
"id": "P2_FULL",
"sva_name": "p_full",
"type": "invariant",
"natural_language": "full refle... | {"ignore_flush.sv": "module fifo_0010_mutant_ignore_flush (\n input wire clk,\n input wire rst,\n input wire push,\n input wire pop,\n input wire flush,\n output reg [2:0] count,\n output wire empty,\n output wire full,\n output wire almost_full\n);\n\n always @(posedge clk) begin\n ... |
fifo_0010 | fifo_control | Four-slot FIFO occupancy counter with simultaneous push/pop cancellation and overflow/underflow protection. | ternary_next.sv | module fifo_0010_ternary_next (
input wire clk,
input wire rst,
input wire push,
input wire pop,
input wire flush,
output reg [2:0] count,
output wire empty,
output wire full,
output wire almost_full
);
wire [2:0] next_count;
assign next_count = (flush) ? (3'd0) : ((!... | {
"design_id": "fifo_0010",
"category": "fifo_control",
"model_type": "register_rules",
"template": "four_slot_occupancy_counter",
"description": "Four-slot FIFO occupancy counter with simultaneous push/pop cancellation and overflow/underflow protection.",
"clock": {
"name": "clk",
"edge": "posedge"... | // Gold interface properties for fifo_0010
// P1_EMPTY: empty reflects zero occupancy
property p_empty;
@(posedge clk) disable iff (rst) (empty == (count == 3'd0));
endproperty
assert property (p_empty);
// P2_FULL: full reflects four entries
property p_full;
@(posedge clk) disable iff (rst) (full == (count =... | [
{
"id": "P1_EMPTY",
"sva_name": "p_empty",
"type": "invariant",
"natural_language": "empty reflects zero occupancy",
"expression": "empty == (count == 3'd0)",
"disable": "rst"
},
{
"id": "P2_FULL",
"sva_name": "p_full",
"type": "invariant",
"natural_language": "full refle... | {"ignore_flush.sv": "module fifo_0010_mutant_ignore_flush (\n input wire clk,\n input wire rst,\n input wire push,\n input wire pop,\n input wire flush,\n output reg [2:0] count,\n output wire empty,\n output wire full,\n output wire almost_full\n);\n\n always @(posedge clk) begin\n ... |
fifo_0010 | fifo_control | Four-slot FIFO occupancy counter with simultaneous push/pop cancellation and overflow/underflow protection. | function_update.sv | module fifo_0010_function_update (
input wire clk,
input wire rst,
input wire push,
input wire pop,
input wire flush,
output reg [2:0] count,
output wire empty,
output wire full,
output wire almost_full
);
function automatic [2:0] compute_next_count;
input [2:0] cu... | {
"design_id": "fifo_0010",
"category": "fifo_control",
"model_type": "register_rules",
"template": "four_slot_occupancy_counter",
"description": "Four-slot FIFO occupancy counter with simultaneous push/pop cancellation and overflow/underflow protection.",
"clock": {
"name": "clk",
"edge": "posedge"... | // Gold interface properties for fifo_0010
// P1_EMPTY: empty reflects zero occupancy
property p_empty;
@(posedge clk) disable iff (rst) (empty == (count == 3'd0));
endproperty
assert property (p_empty);
// P2_FULL: full reflects four entries
property p_full;
@(posedge clk) disable iff (rst) (full == (count =... | [
{
"id": "P1_EMPTY",
"sva_name": "p_empty",
"type": "invariant",
"natural_language": "empty reflects zero occupancy",
"expression": "empty == (count == 3'd0)",
"disable": "rst"
},
{
"id": "P2_FULL",
"sva_name": "p_full",
"type": "invariant",
"natural_language": "full refle... | {"ignore_flush.sv": "module fifo_0010_mutant_ignore_flush (\n input wire clk,\n input wire rst,\n input wire push,\n input wire pop,\n input wire flush,\n output reg [2:0] count,\n output wire empty,\n output wire full,\n output wire almost_full\n);\n\n always @(posedge clk) begin\n ... |
handshake_0001 | handshake | Three-state request/acknowledge controller with cancellation. | canonical_case.sv | module handshake_0001_canonical_case (
input wire clk,
input wire rst,
input wire req,
input wire ready,
input wire cancel,
output reg busy,
output reg ack
);
localparam [1:0] IDLE = 2'd0;
localparam [1:0] WAIT = 2'd1;
localparam [1:0] ACK = 2'd2;
reg [1:0] state,... | {
"design_id": "handshake_0001",
"category": "handshake",
"description": "Three-state request/acknowledge controller with cancellation.",
"clock": {
"name": "clk",
"edge": "posedge"
},
"reset": {
"name": "rst",
"active": "high",
"synchronous": true,
"state": "IDLE"
},
"inputs": [... | // Generated from spec.json.
// Design: handshake_0001
// P1_MUTEX: busy and ack are never asserted together.
p_mutex: assert property (@(posedge clk) disable iff (rst)
!(busy && ack));
// P2_RESET_IDLE: a reset cycle leaves the controller idle on the following cycle.
p_reset_idle: assert property (@(posedge clk)... | [
{
"id": "P1_MUTEX",
"type": "invariant",
"natural_language": "busy and ack are never asserted together",
"disable": "rst",
"expression": "!(busy && ack)"
},
{
"id": "P2_RESET_IDLE",
"type": "next_cycle_implication",
"natural_language": "a reset cycle leaves the controller idle on... | {"ack_stuck.sv": "module handshake_0001_mutant_ack_stuck (\n input wire clk,\n input wire rst,\n input wire req,\n input wire ready,\n input wire cancel,\n output reg busy,\n output reg ack\n);\n localparam [1:0] IDLE = 2'd0;\n localparam [1:0] WAIT = 2'd1;\n localparam [1:0] ACK ... |
handshake_0001 | handshake | Three-state request/acknowledge controller with cancellation. | onehot_case.sv | module handshake_0001_onehot_case (
input wire clk,
input wire rst,
input wire req,
input wire ready,
input wire cancel,
output reg busy,
output reg ack
);
localparam [2:0] IDLE = 3'b001;
localparam [2:0] WAIT = 3'b010;
localparam [2:0] ACK = 3'b100;
reg [2:0] sta... | {
"design_id": "handshake_0001",
"category": "handshake",
"description": "Three-state request/acknowledge controller with cancellation.",
"clock": {
"name": "clk",
"edge": "posedge"
},
"reset": {
"name": "rst",
"active": "high",
"synchronous": true,
"state": "IDLE"
},
"inputs": [... | // Generated from spec.json.
// Design: handshake_0001
// P1_MUTEX: busy and ack are never asserted together.
p_mutex: assert property (@(posedge clk) disable iff (rst)
!(busy && ack));
// P2_RESET_IDLE: a reset cycle leaves the controller idle on the following cycle.
p_reset_idle: assert property (@(posedge clk)... | [
{
"id": "P1_MUTEX",
"type": "invariant",
"natural_language": "busy and ack are never asserted together",
"disable": "rst",
"expression": "!(busy && ack)"
},
{
"id": "P2_RESET_IDLE",
"type": "next_cycle_implication",
"natural_language": "a reset cycle leaves the controller idle on... | {"ack_stuck.sv": "module handshake_0001_mutant_ack_stuck (\n input wire clk,\n input wire rst,\n input wire req,\n input wire ready,\n input wire cancel,\n output reg busy,\n output reg ack\n);\n localparam [1:0] IDLE = 2'd0;\n localparam [1:0] WAIT = 2'd1;\n localparam [1:0] ACK ... |
handshake_0001 | handshake | Three-state request/acknowledge controller with cancellation. | nested_if.sv | module handshake_0001_nested_if (
input wire clk,
input wire rst,
input wire req,
input wire ready,
input wire cancel,
output wire busy,
output wire ack
);
localparam [1:0] S_IDLE = 2'd0;
localparam [1:0] S_WAIT = 2'd1;
localparam [1:0] S_ACK = 2'd2;
reg [1:0] st... | {
"design_id": "handshake_0001",
"category": "handshake",
"description": "Three-state request/acknowledge controller with cancellation.",
"clock": {
"name": "clk",
"edge": "posedge"
},
"reset": {
"name": "rst",
"active": "high",
"synchronous": true,
"state": "IDLE"
},
"inputs": [... | // Generated from spec.json.
// Design: handshake_0001
// P1_MUTEX: busy and ack are never asserted together.
p_mutex: assert property (@(posedge clk) disable iff (rst)
!(busy && ack));
// P2_RESET_IDLE: a reset cycle leaves the controller idle on the following cycle.
p_reset_idle: assert property (@(posedge clk)... | [
{
"id": "P1_MUTEX",
"type": "invariant",
"natural_language": "busy and ack are never asserted together",
"disable": "rst",
"expression": "!(busy && ack)"
},
{
"id": "P2_RESET_IDLE",
"type": "next_cycle_implication",
"natural_language": "a reset cycle leaves the controller idle on... | {"ack_stuck.sv": "module handshake_0001_mutant_ack_stuck (\n input wire clk,\n input wire rst,\n input wire req,\n input wire ready,\n input wire cancel,\n output reg busy,\n output reg ack\n);\n localparam [1:0] IDLE = 2'd0;\n localparam [1:0] WAIT = 2'd1;\n localparam [1:0] ACK ... |
handshake_0001 | handshake | Three-state request/acknowledge controller with cancellation. | factored_flags.sv | module handshake_0001_factored_flags (
input wire clk,
input wire rst,
input wire req,
input wire ready,
input wire cancel,
output reg busy,
output reg ack
);
localparam [1:0] F_IDLE = 2'd0;
localparam [1:0] F_WAIT = 2'd1;
localparam [1:0] F_ACK = ... | {
"design_id": "handshake_0001",
"category": "handshake",
"description": "Three-state request/acknowledge controller with cancellation.",
"clock": {
"name": "clk",
"edge": "posedge"
},
"reset": {
"name": "rst",
"active": "high",
"synchronous": true,
"state": "IDLE"
},
"inputs": [... | // Generated from spec.json.
// Design: handshake_0001
// P1_MUTEX: busy and ack are never asserted together.
p_mutex: assert property (@(posedge clk) disable iff (rst)
!(busy && ack));
// P2_RESET_IDLE: a reset cycle leaves the controller idle on the following cycle.
p_reset_idle: assert property (@(posedge clk)... | [
{
"id": "P1_MUTEX",
"type": "invariant",
"natural_language": "busy and ack are never asserted together",
"disable": "rst",
"expression": "!(busy && ack)"
},
{
"id": "P2_RESET_IDLE",
"type": "next_cycle_implication",
"natural_language": "a reset cycle leaves the controller idle on... | {"ack_stuck.sv": "module handshake_0001_mutant_ack_stuck (\n input wire clk,\n input wire rst,\n input wire req,\n input wire ready,\n input wire cancel,\n output reg busy,\n output reg ack\n);\n localparam [1:0] IDLE = 2'd0;\n localparam [1:0] WAIT = 2'd1;\n localparam [1:0] ACK ... |
handshake_0002 | handshake | A request starts an operation. The controller remains busy until done is observed, acknowledges completion for one cycle, then returns to idle. | canonical_case.sv | module handshake_0002_canonical_case (
input wire clk,
input wire rst,
input wire req,
input wire done,
output reg busy,
output reg ack
);
localparam [1:0] IDLE = 2'd0;
localparam [1:0] BUSY = 2'd1;
localparam [1:0] ACK = 2'd2;
reg [1:0] state, next_state;
always ... | {
"design_id": "handshake_0002",
"category": "handshake",
"template": "request_done_ack",
"description": "A request starts an operation. The controller remains busy until done is observed, acknowledges completion for one cycle, then returns to idle.",
"clock": {
"name": "clk",
"edge": "posedge"
},
... | // Generated from spec.json.
// Design: handshake_0002
// P1_MUTEX: busy and ack are never asserted together.
p_mutex: assert property (@(posedge clk) disable iff (rst)
!(busy && ack));
// P2_RESET_IDLE: reset returns the controller to idle.
p_reset_idle: assert property (@(posedge clk)
(rst) |=> (!busy && !a... | [
{
"id": "P1_MUTEX",
"type": "invariant",
"natural_language": "busy and ack are never asserted together",
"disable": "rst",
"expression": "!(busy && ack)"
},
{
"id": "P2_RESET_IDLE",
"type": "next_cycle_implication",
"natural_language": "reset returns the controller to idle",
... | {"ack_stuck.sv": "module handshake_0002_mutant_ack_stuck (\n input wire clk,\n input wire rst,\n input wire req,\n input wire done,\n output reg busy,\n output reg ack\n);\n localparam [1:0] IDLE = 2'd0;\n localparam [1:0] BUSY = 2'd1;\n localparam [1:0] ACK = 2'd2;\n\n reg [1:0]... |
handshake_0002 | handshake | A request starts an operation. The controller remains busy until done is observed, acknowledges completion for one cycle, then returns to idle. | onehot_case.sv | module handshake_0002_onehot_case (
input wire clk,
input wire rst,
input wire req,
input wire done,
output reg busy,
output reg ack
);
localparam [2:0] IDLE = 3'b001;
localparam [2:0] BUSY = 3'b010;
localparam [2:0] ACK = 3'b100;
reg [2:0] state, next_state;
alwa... | {
"design_id": "handshake_0002",
"category": "handshake",
"template": "request_done_ack",
"description": "A request starts an operation. The controller remains busy until done is observed, acknowledges completion for one cycle, then returns to idle.",
"clock": {
"name": "clk",
"edge": "posedge"
},
... | // Generated from spec.json.
// Design: handshake_0002
// P1_MUTEX: busy and ack are never asserted together.
p_mutex: assert property (@(posedge clk) disable iff (rst)
!(busy && ack));
// P2_RESET_IDLE: reset returns the controller to idle.
p_reset_idle: assert property (@(posedge clk)
(rst) |=> (!busy && !a... | [
{
"id": "P1_MUTEX",
"type": "invariant",
"natural_language": "busy and ack are never asserted together",
"disable": "rst",
"expression": "!(busy && ack)"
},
{
"id": "P2_RESET_IDLE",
"type": "next_cycle_implication",
"natural_language": "reset returns the controller to idle",
... | {"ack_stuck.sv": "module handshake_0002_mutant_ack_stuck (\n input wire clk,\n input wire rst,\n input wire req,\n input wire done,\n output reg busy,\n output reg ack\n);\n localparam [1:0] IDLE = 2'd0;\n localparam [1:0] BUSY = 2'd1;\n localparam [1:0] ACK = 2'd2;\n\n reg [1:0]... |
handshake_0002 | handshake | A request starts an operation. The controller remains busy until done is observed, acknowledges completion for one cycle, then returns to idle. | nested_if.sv | module handshake_0002_nested_if (
input wire clk,
input wire rst,
input wire req,
input wire done,
output wire busy,
output wire ack
);
localparam [1:0] S_IDLE = 2'd0;
localparam [1:0] S_BUSY = 2'd1;
localparam [1:0] S_ACK = 2'd2;
reg [1:0] state;
always @(posedg... | {
"design_id": "handshake_0002",
"category": "handshake",
"template": "request_done_ack",
"description": "A request starts an operation. The controller remains busy until done is observed, acknowledges completion for one cycle, then returns to idle.",
"clock": {
"name": "clk",
"edge": "posedge"
},
... | // Generated from spec.json.
// Design: handshake_0002
// P1_MUTEX: busy and ack are never asserted together.
p_mutex: assert property (@(posedge clk) disable iff (rst)
!(busy && ack));
// P2_RESET_IDLE: reset returns the controller to idle.
p_reset_idle: assert property (@(posedge clk)
(rst) |=> (!busy && !a... | [
{
"id": "P1_MUTEX",
"type": "invariant",
"natural_language": "busy and ack are never asserted together",
"disable": "rst",
"expression": "!(busy && ack)"
},
{
"id": "P2_RESET_IDLE",
"type": "next_cycle_implication",
"natural_language": "reset returns the controller to idle",
... | {"ack_stuck.sv": "module handshake_0002_mutant_ack_stuck (\n input wire clk,\n input wire rst,\n input wire req,\n input wire done,\n output reg busy,\n output reg ack\n);\n localparam [1:0] IDLE = 2'd0;\n localparam [1:0] BUSY = 2'd1;\n localparam [1:0] ACK = 2'd2;\n\n reg [1:0]... |
handshake_0002 | handshake | A request starts an operation. The controller remains busy until done is observed, acknowledges completion for one cycle, then returns to idle. | factored_flags.sv | module handshake_0002_factored_flags (
input wire clk,
input wire rst,
input wire req,
input wire done,
output reg busy,
output reg ack
);
localparam [1:0] F_IDLE = 2'd0;
localparam [1:0] F_BUSY = 2'd1;
localparam [1:0] F_ACK = 2'd2;
reg [1:0] stat... | {
"design_id": "handshake_0002",
"category": "handshake",
"template": "request_done_ack",
"description": "A request starts an operation. The controller remains busy until done is observed, acknowledges completion for one cycle, then returns to idle.",
"clock": {
"name": "clk",
"edge": "posedge"
},
... | // Generated from spec.json.
// Design: handshake_0002
// P1_MUTEX: busy and ack are never asserted together.
p_mutex: assert property (@(posedge clk) disable iff (rst)
!(busy && ack));
// P2_RESET_IDLE: reset returns the controller to idle.
p_reset_idle: assert property (@(posedge clk)
(rst) |=> (!busy && !a... | [
{
"id": "P1_MUTEX",
"type": "invariant",
"natural_language": "busy and ack are never asserted together",
"disable": "rst",
"expression": "!(busy && ack)"
},
{
"id": "P2_RESET_IDLE",
"type": "next_cycle_implication",
"natural_language": "reset returns the controller to idle",
... | {"ack_stuck.sv": "module handshake_0002_mutant_ack_stuck (\n input wire clk,\n input wire rst,\n input wire req,\n input wire done,\n output reg busy,\n output reg ack\n);\n localparam [1:0] IDLE = 2'd0;\n localparam [1:0] BUSY = 2'd1;\n localparam [1:0] ACK = 2'd2;\n\n reg [1:0]... |
handshake_0003 | handshake | A four-phase request/acknowledge controller. A request raises acknowledgement, acknowledgement remains asserted while request remains high, and acknowledgement drops after request is released. | canonical_case.sv | module handshake_0003_canonical_case (
input wire clk,
input wire rst,
input wire req,
output reg ack
);
localparam [0:0] IDLE = 1'd0;
localparam [0:0] ACK = 1'd1;
reg [0:0] state, next_state;
always @* begin
next_state = state;
case (state)
IDLE: nex... | {
"design_id": "handshake_0003",
"category": "handshake",
"template": "four_phase_request_ack",
"description": "A four-phase request/acknowledge controller. A request raises acknowledgement, acknowledgement remains asserted while request remains high, and acknowledgement drops after request is released.",
"cl... | // Generated from spec.json.
// Design: handshake_0003
// P1_RESET_IDLE: reset clears acknowledgement.
p_reset_idle: assert property (@(posedge clk)
(rst) |=> (!ack));
// P2_REQUEST_TO_ACK: a request while idle raises acknowledgement.
p_request_to_ack: assert property (@(posedge clk) disable iff (rst)
(!ack &... | [
{
"id": "P1_RESET_IDLE",
"type": "next_cycle_implication",
"natural_language": "reset clears acknowledgement",
"antecedent": "rst",
"consequent": "!ack",
"delay": 1
},
{
"id": "P2_REQUEST_TO_ACK",
"type": "next_cycle_implication",
"natural_language": "a request while idle rai... | {"ack_stuck.sv": "module handshake_0003_mutant_ack_stuck (\n input wire clk,\n input wire rst,\n input wire req,\n output reg ack\n);\n localparam [0:0] IDLE = 1'd0;\n localparam [0:0] ACK = 1'd1;\n\n reg [0:0] state, next_state;\n\n always @* begin\n next_state = state;\n c... |
handshake_0003 | handshake | A four-phase request/acknowledge controller. A request raises acknowledgement, acknowledgement remains asserted while request remains high, and acknowledgement drops after request is released. | onehot_case.sv | module handshake_0003_onehot_case (
input wire clk,
input wire rst,
input wire req,
output reg ack
);
localparam [1:0] IDLE = 2'b01;
localparam [1:0] ACK = 2'b10;
reg [1:0] state, next_state;
always @* begin
next_state = IDLE;
case (state)
IDLE: next_... | {
"design_id": "handshake_0003",
"category": "handshake",
"template": "four_phase_request_ack",
"description": "A four-phase request/acknowledge controller. A request raises acknowledgement, acknowledgement remains asserted while request remains high, and acknowledgement drops after request is released.",
"cl... | // Generated from spec.json.
// Design: handshake_0003
// P1_RESET_IDLE: reset clears acknowledgement.
p_reset_idle: assert property (@(posedge clk)
(rst) |=> (!ack));
// P2_REQUEST_TO_ACK: a request while idle raises acknowledgement.
p_request_to_ack: assert property (@(posedge clk) disable iff (rst)
(!ack &... | [
{
"id": "P1_RESET_IDLE",
"type": "next_cycle_implication",
"natural_language": "reset clears acknowledgement",
"antecedent": "rst",
"consequent": "!ack",
"delay": 1
},
{
"id": "P2_REQUEST_TO_ACK",
"type": "next_cycle_implication",
"natural_language": "a request while idle rai... | {"ack_stuck.sv": "module handshake_0003_mutant_ack_stuck (\n input wire clk,\n input wire rst,\n input wire req,\n output reg ack\n);\n localparam [0:0] IDLE = 1'd0;\n localparam [0:0] ACK = 1'd1;\n\n reg [0:0] state, next_state;\n\n always @* begin\n next_state = state;\n c... |
handshake_0003 | handshake | A four-phase request/acknowledge controller. A request raises acknowledgement, acknowledgement remains asserted while request remains high, and acknowledgement drops after request is released. | nested_if.sv | module handshake_0003_nested_if (
input wire clk,
input wire rst,
input wire req,
output wire ack
);
localparam [0:0] S_IDLE = 1'd0;
localparam [0:0] S_ACK = 1'd1;
reg [0:0] state;
always @(posedge clk) begin
if (rst) begin
state <= S_IDLE;
end else ... | {
"design_id": "handshake_0003",
"category": "handshake",
"template": "four_phase_request_ack",
"description": "A four-phase request/acknowledge controller. A request raises acknowledgement, acknowledgement remains asserted while request remains high, and acknowledgement drops after request is released.",
"cl... | // Generated from spec.json.
// Design: handshake_0003
// P1_RESET_IDLE: reset clears acknowledgement.
p_reset_idle: assert property (@(posedge clk)
(rst) |=> (!ack));
// P2_REQUEST_TO_ACK: a request while idle raises acknowledgement.
p_request_to_ack: assert property (@(posedge clk) disable iff (rst)
(!ack &... | [
{
"id": "P1_RESET_IDLE",
"type": "next_cycle_implication",
"natural_language": "reset clears acknowledgement",
"antecedent": "rst",
"consequent": "!ack",
"delay": 1
},
{
"id": "P2_REQUEST_TO_ACK",
"type": "next_cycle_implication",
"natural_language": "a request while idle rai... | {"ack_stuck.sv": "module handshake_0003_mutant_ack_stuck (\n input wire clk,\n input wire rst,\n input wire req,\n output reg ack\n);\n localparam [0:0] IDLE = 1'd0;\n localparam [0:0] ACK = 1'd1;\n\n reg [0:0] state, next_state;\n\n always @* begin\n next_state = state;\n c... |
handshake_0003 | handshake | A four-phase request/acknowledge controller. A request raises acknowledgement, acknowledgement remains asserted while request remains high, and acknowledgement drops after request is released. | factored_flags.sv | module handshake_0003_factored_flags (
input wire clk,
input wire rst,
input wire req,
output reg ack
);
localparam [0:0] F_IDLE = 1'd0;
localparam [0:0] F_ACK = 1'd1;
reg [0:0] state, next_state;
wire guard_idle_0 = (req);
wire guard_ack_0 = (req);
always... | {
"design_id": "handshake_0003",
"category": "handshake",
"template": "four_phase_request_ack",
"description": "A four-phase request/acknowledge controller. A request raises acknowledgement, acknowledgement remains asserted while request remains high, and acknowledgement drops after request is released.",
"cl... | // Generated from spec.json.
// Design: handshake_0003
// P1_RESET_IDLE: reset clears acknowledgement.
p_reset_idle: assert property (@(posedge clk)
(rst) |=> (!ack));
// P2_REQUEST_TO_ACK: a request while idle raises acknowledgement.
p_request_to_ack: assert property (@(posedge clk) disable iff (rst)
(!ack &... | [
{
"id": "P1_RESET_IDLE",
"type": "next_cycle_implication",
"natural_language": "reset clears acknowledgement",
"antecedent": "rst",
"consequent": "!ack",
"delay": 1
},
{
"id": "P2_REQUEST_TO_ACK",
"type": "next_cycle_implication",
"natural_language": "a request while idle rai... | {"ack_stuck.sv": "module handshake_0003_mutant_ack_stuck (\n input wire clk,\n input wire rst,\n input wire req,\n output reg ack\n);\n localparam [0:0] IDLE = 1'd0;\n localparam [0:0] ACK = 1'd1;\n\n reg [0:0] state, next_state;\n\n always @* begin\n next_state = state;\n c... |
handshake_0004 | handshake | A one-entry valid/ready buffer. A push makes data valid, valid remains asserted while the receiver is not ready, and a ready cycle consumes the entry. | canonical_case.sv | module handshake_0004_canonical_case (
input wire clk,
input wire rst,
input wire push,
input wire ready,
output reg valid
);
localparam [0:0] EMPTY = 1'd0;
localparam [0:0] FULL = 1'd1;
reg [0:0] state, next_state;
always @* begin
next_state = state;
case (st... | {
"design_id": "handshake_0004",
"category": "handshake",
"template": "valid_ready_buffer",
"description": "A one-entry valid/ready buffer. A push makes data valid, valid remains asserted while the receiver is not ready, and a ready cycle consumes the entry.",
"clock": {
"name": "clk",
"edge": "posedg... | // Generated from spec.json.
// Design: handshake_0004
// P1_RESET_EMPTY: reset clears valid.
p_reset_empty: assert property (@(posedge clk)
(rst) |=> (!valid));
// P2_PUSH_TO_VALID: a push into an empty buffer makes the output valid.
p_push_to_valid: assert property (@(posedge clk) disable iff (rst)
(!valid ... | [
{
"id": "P1_RESET_EMPTY",
"type": "next_cycle_implication",
"natural_language": "reset clears valid",
"antecedent": "rst",
"consequent": "!valid",
"delay": 1
},
{
"id": "P2_PUSH_TO_VALID",
"type": "next_cycle_implication",
"natural_language": "a push into an empty buffer make... | {"drop_without_ready.sv": "module handshake_0004_mutant_drop_without_ready (\n input wire clk,\n input wire rst,\n input wire push,\n input wire ready,\n output reg valid\n);\n localparam [0:0] EMPTY = 1'd0;\n localparam [0:0] FULL = 1'd1;\n\n reg [0:0] state, next_state;\n\n always @* ... |
handshake_0004 | handshake | A one-entry valid/ready buffer. A push makes data valid, valid remains asserted while the receiver is not ready, and a ready cycle consumes the entry. | onehot_case.sv | module handshake_0004_onehot_case (
input wire clk,
input wire rst,
input wire push,
input wire ready,
output reg valid
);
localparam [1:0] EMPTY = 2'b01;
localparam [1:0] FULL = 2'b10;
reg [1:0] state, next_state;
always @* begin
next_state = EMPTY;
case (sta... | {
"design_id": "handshake_0004",
"category": "handshake",
"template": "valid_ready_buffer",
"description": "A one-entry valid/ready buffer. A push makes data valid, valid remains asserted while the receiver is not ready, and a ready cycle consumes the entry.",
"clock": {
"name": "clk",
"edge": "posedg... | // Generated from spec.json.
// Design: handshake_0004
// P1_RESET_EMPTY: reset clears valid.
p_reset_empty: assert property (@(posedge clk)
(rst) |=> (!valid));
// P2_PUSH_TO_VALID: a push into an empty buffer makes the output valid.
p_push_to_valid: assert property (@(posedge clk) disable iff (rst)
(!valid ... | [
{
"id": "P1_RESET_EMPTY",
"type": "next_cycle_implication",
"natural_language": "reset clears valid",
"antecedent": "rst",
"consequent": "!valid",
"delay": 1
},
{
"id": "P2_PUSH_TO_VALID",
"type": "next_cycle_implication",
"natural_language": "a push into an empty buffer make... | {"drop_without_ready.sv": "module handshake_0004_mutant_drop_without_ready (\n input wire clk,\n input wire rst,\n input wire push,\n input wire ready,\n output reg valid\n);\n localparam [0:0] EMPTY = 1'd0;\n localparam [0:0] FULL = 1'd1;\n\n reg [0:0] state, next_state;\n\n always @* ... |
handshake_0004 | handshake | A one-entry valid/ready buffer. A push makes data valid, valid remains asserted while the receiver is not ready, and a ready cycle consumes the entry. | nested_if.sv | module handshake_0004_nested_if (
input wire clk,
input wire rst,
input wire push,
input wire ready,
output wire valid
);
localparam [0:0] S_EMPTY = 1'd0;
localparam [0:0] S_FULL = 1'd1;
reg [0:0] state;
always @(posedge clk) begin
if (rst) begin
state <=... | {
"design_id": "handshake_0004",
"category": "handshake",
"template": "valid_ready_buffer",
"description": "A one-entry valid/ready buffer. A push makes data valid, valid remains asserted while the receiver is not ready, and a ready cycle consumes the entry.",
"clock": {
"name": "clk",
"edge": "posedg... | // Generated from spec.json.
// Design: handshake_0004
// P1_RESET_EMPTY: reset clears valid.
p_reset_empty: assert property (@(posedge clk)
(rst) |=> (!valid));
// P2_PUSH_TO_VALID: a push into an empty buffer makes the output valid.
p_push_to_valid: assert property (@(posedge clk) disable iff (rst)
(!valid ... | [
{
"id": "P1_RESET_EMPTY",
"type": "next_cycle_implication",
"natural_language": "reset clears valid",
"antecedent": "rst",
"consequent": "!valid",
"delay": 1
},
{
"id": "P2_PUSH_TO_VALID",
"type": "next_cycle_implication",
"natural_language": "a push into an empty buffer make... | {"drop_without_ready.sv": "module handshake_0004_mutant_drop_without_ready (\n input wire clk,\n input wire rst,\n input wire push,\n input wire ready,\n output reg valid\n);\n localparam [0:0] EMPTY = 1'd0;\n localparam [0:0] FULL = 1'd1;\n\n reg [0:0] state, next_state;\n\n always @* ... |
handshake_0004 | handshake | A one-entry valid/ready buffer. A push makes data valid, valid remains asserted while the receiver is not ready, and a ready cycle consumes the entry. | factored_flags.sv | module handshake_0004_factored_flags (
input wire clk,
input wire rst,
input wire push,
input wire ready,
output reg valid
);
localparam [0:0] F_EMPTY = 1'd0;
localparam [0:0] F_FULL = 1'd1;
reg [0:0] state, next_state;
wire guard_empty_0 = (push);
wire guar... | {
"design_id": "handshake_0004",
"category": "handshake",
"template": "valid_ready_buffer",
"description": "A one-entry valid/ready buffer. A push makes data valid, valid remains asserted while the receiver is not ready, and a ready cycle consumes the entry.",
"clock": {
"name": "clk",
"edge": "posedg... | // Generated from spec.json.
// Design: handshake_0004
// P1_RESET_EMPTY: reset clears valid.
p_reset_empty: assert property (@(posedge clk)
(rst) |=> (!valid));
// P2_PUSH_TO_VALID: a push into an empty buffer makes the output valid.
p_push_to_valid: assert property (@(posedge clk) disable iff (rst)
(!valid ... | [
{
"id": "P1_RESET_EMPTY",
"type": "next_cycle_implication",
"natural_language": "reset clears valid",
"antecedent": "rst",
"consequent": "!valid",
"delay": 1
},
{
"id": "P2_PUSH_TO_VALID",
"type": "next_cycle_implication",
"natural_language": "a push into an empty buffer make... | {"drop_without_ready.sv": "module handshake_0004_mutant_drop_without_ready (\n input wire clk,\n input wire rst,\n input wire push,\n input wire ready,\n output reg valid\n);\n localparam [0:0] EMPTY = 1'd0;\n localparam [0:0] FULL = 1'd1;\n\n reg [0:0] state, next_state;\n\n always @* ... |
handshake_0005 | handshake | A request enters a pending state until grant arrives. Grant raises acknowledgement, which remains asserted until the requester releases req. | canonical_case.sv | module handshake_0005_canonical_case (
input wire clk,
input wire rst,
input wire req,
input wire grant,
output reg pending,
output reg ack
);
localparam [1:0] IDLE = 2'd0;
localparam [1:0] WAIT = 2'd1;
localparam [1:0] ACK = 2'd2;
reg [1:0] state, next_state;
alw... | {
"design_id": "handshake_0005",
"category": "handshake",
"template": "request_grant_ack_release",
"description": "A request enters a pending state until grant arrives. Grant raises acknowledgement, which remains asserted until the requester releases req.",
"clock": {
"name": "clk",
"edge": "posedge"
... | // Generated from spec.json.
// Design: handshake_0005
// P1_MUTEX: pending and ack are never asserted together.
p_mutex: assert property (@(posedge clk) disable iff (rst)
!(pending && ack));
// P2_RESET_IDLE: reset clears pending and acknowledgement.
p_reset_idle: assert property (@(posedge clk)
(rst) |=> (!... | [
{
"id": "P1_MUTEX",
"type": "invariant",
"natural_language": "pending and ack are never asserted together",
"disable": "rst",
"expression": "!(pending && ack)"
},
{
"id": "P2_RESET_IDLE",
"type": "next_cycle_implication",
"natural_language": "reset clears pending and acknowledgem... | {"ack_stuck.sv": "module handshake_0005_mutant_ack_stuck (\n input wire clk,\n input wire rst,\n input wire req,\n input wire grant,\n output reg pending,\n output reg ack\n);\n localparam [1:0] IDLE = 2'd0;\n localparam [1:0] WAIT = 2'd1;\n localparam [1:0] ACK = 2'd2;\n\n reg [... |
handshake_0005 | handshake | A request enters a pending state until grant arrives. Grant raises acknowledgement, which remains asserted until the requester releases req. | onehot_case.sv | module handshake_0005_onehot_case (
input wire clk,
input wire rst,
input wire req,
input wire grant,
output reg pending,
output reg ack
);
localparam [2:0] IDLE = 3'b001;
localparam [2:0] WAIT = 3'b010;
localparam [2:0] ACK = 3'b100;
reg [2:0] state, next_state;
... | {
"design_id": "handshake_0005",
"category": "handshake",
"template": "request_grant_ack_release",
"description": "A request enters a pending state until grant arrives. Grant raises acknowledgement, which remains asserted until the requester releases req.",
"clock": {
"name": "clk",
"edge": "posedge"
... | // Generated from spec.json.
// Design: handshake_0005
// P1_MUTEX: pending and ack are never asserted together.
p_mutex: assert property (@(posedge clk) disable iff (rst)
!(pending && ack));
// P2_RESET_IDLE: reset clears pending and acknowledgement.
p_reset_idle: assert property (@(posedge clk)
(rst) |=> (!... | [
{
"id": "P1_MUTEX",
"type": "invariant",
"natural_language": "pending and ack are never asserted together",
"disable": "rst",
"expression": "!(pending && ack)"
},
{
"id": "P2_RESET_IDLE",
"type": "next_cycle_implication",
"natural_language": "reset clears pending and acknowledgem... | {"ack_stuck.sv": "module handshake_0005_mutant_ack_stuck (\n input wire clk,\n input wire rst,\n input wire req,\n input wire grant,\n output reg pending,\n output reg ack\n);\n localparam [1:0] IDLE = 2'd0;\n localparam [1:0] WAIT = 2'd1;\n localparam [1:0] ACK = 2'd2;\n\n reg [... |
handshake_0005 | handshake | A request enters a pending state until grant arrives. Grant raises acknowledgement, which remains asserted until the requester releases req. | nested_if.sv | module handshake_0005_nested_if (
input wire clk,
input wire rst,
input wire req,
input wire grant,
output wire pending,
output wire ack
);
localparam [1:0] S_IDLE = 2'd0;
localparam [1:0] S_WAIT = 2'd1;
localparam [1:0] S_ACK = 2'd2;
reg [1:0] state;
always @(po... | {
"design_id": "handshake_0005",
"category": "handshake",
"template": "request_grant_ack_release",
"description": "A request enters a pending state until grant arrives. Grant raises acknowledgement, which remains asserted until the requester releases req.",
"clock": {
"name": "clk",
"edge": "posedge"
... | // Generated from spec.json.
// Design: handshake_0005
// P1_MUTEX: pending and ack are never asserted together.
p_mutex: assert property (@(posedge clk) disable iff (rst)
!(pending && ack));
// P2_RESET_IDLE: reset clears pending and acknowledgement.
p_reset_idle: assert property (@(posedge clk)
(rst) |=> (!... | [
{
"id": "P1_MUTEX",
"type": "invariant",
"natural_language": "pending and ack are never asserted together",
"disable": "rst",
"expression": "!(pending && ack)"
},
{
"id": "P2_RESET_IDLE",
"type": "next_cycle_implication",
"natural_language": "reset clears pending and acknowledgem... | {"ack_stuck.sv": "module handshake_0005_mutant_ack_stuck (\n input wire clk,\n input wire rst,\n input wire req,\n input wire grant,\n output reg pending,\n output reg ack\n);\n localparam [1:0] IDLE = 2'd0;\n localparam [1:0] WAIT = 2'd1;\n localparam [1:0] ACK = 2'd2;\n\n reg [... |
handshake_0005 | handshake | A request enters a pending state until grant arrives. Grant raises acknowledgement, which remains asserted until the requester releases req. | factored_flags.sv | module handshake_0005_factored_flags (
input wire clk,
input wire rst,
input wire req,
input wire grant,
output reg pending,
output reg ack
);
localparam [1:0] F_IDLE = 2'd0;
localparam [1:0] F_WAIT = 2'd1;
localparam [1:0] F_ACK = 2'd2;
reg [1:0] ... | {
"design_id": "handshake_0005",
"category": "handshake",
"template": "request_grant_ack_release",
"description": "A request enters a pending state until grant arrives. Grant raises acknowledgement, which remains asserted until the requester releases req.",
"clock": {
"name": "clk",
"edge": "posedge"
... | // Generated from spec.json.
// Design: handshake_0005
// P1_MUTEX: pending and ack are never asserted together.
p_mutex: assert property (@(posedge clk) disable iff (rst)
!(pending && ack));
// P2_RESET_IDLE: reset clears pending and acknowledgement.
p_reset_idle: assert property (@(posedge clk)
(rst) |=> (!... | [
{
"id": "P1_MUTEX",
"type": "invariant",
"natural_language": "pending and ack are never asserted together",
"disable": "rst",
"expression": "!(pending && ack)"
},
{
"id": "P2_RESET_IDLE",
"type": "next_cycle_implication",
"natural_language": "reset clears pending and acknowledgem... | {"ack_stuck.sv": "module handshake_0005_mutant_ack_stuck (\n input wire clk,\n input wire rst,\n input wire req,\n input wire grant,\n output reg pending,\n output reg ack\n);\n localparam [1:0] IDLE = 2'd0;\n localparam [1:0] WAIT = 2'd1;\n localparam [1:0] ACK = 2'd2;\n\n reg [... |
handshake_0008 | handshake | Request can be accepted, retried, or completed. | canonical_case.sv | module handshake_0008_canonical_case (
input wire clk,
input wire rst,
input wire req,
input wire accept,
input wire retry,
output reg busy,
output reg retrying,
output reg done
);
localparam [1:0] IDLE = 2'd0;
localparam [1:0] WAIT = 2'd1;
localparam [1:0] RETRY = ... | {
"design_id": "handshake_0008",
"category": "handshake",
"template": "retry_handshake",
"description": "Request can be accepted, retried, or completed.",
"clock": {
"name": "clk",
"edge": "posedge"
},
"reset": {
"name": "rst",
"active": "high",
"synchronous": true,
"state": "IDLE"... | // Generated from spec.json.
// Design: handshake_0008
// P1_STATE_ENCODING: observable state outputs always encode at most one active mode.
p_state_encoding: assert property (@(posedge clk) disable iff (rst)
$onehot0({busy, retrying, done}));
// P2_RESET: reset returns the controller to its reset behavior.
p_res... | [
{
"id": "P1_STATE_ENCODING",
"type": "invariant",
"natural_language": "observable state outputs always encode at most one active mode",
"expression": "$onehot0({busy, retrying, done})",
"disable": "rst"
},
{
"id": "P2_RESET",
"type": "next_cycle_implication",
"natural_language": ... | {"drop_t1.sv": "module handshake_0008_mutant_drop_t1 (\n input wire clk,\n input wire rst,\n input wire req,\n input wire accept,\n input wire retry,\n output reg busy,\n output reg retrying,\n output reg done\n);\n localparam [1:0] IDLE = 2'd0;\n localparam [1:0] WAIT = 2'd1;\n ... |
handshake_0008 | handshake | Request can be accepted, retried, or completed. | onehot_case.sv | module handshake_0008_onehot_case (
input wire clk,
input wire rst,
input wire req,
input wire accept,
input wire retry,
output reg busy,
output reg retrying,
output reg done
);
localparam [3:0] IDLE = 4'b0001;
localparam [3:0] WAIT = 4'b0010;
localparam [3:0] RETRY... | {
"design_id": "handshake_0008",
"category": "handshake",
"template": "retry_handshake",
"description": "Request can be accepted, retried, or completed.",
"clock": {
"name": "clk",
"edge": "posedge"
},
"reset": {
"name": "rst",
"active": "high",
"synchronous": true,
"state": "IDLE"... | // Generated from spec.json.
// Design: handshake_0008
// P1_STATE_ENCODING: observable state outputs always encode at most one active mode.
p_state_encoding: assert property (@(posedge clk) disable iff (rst)
$onehot0({busy, retrying, done}));
// P2_RESET: reset returns the controller to its reset behavior.
p_res... | [
{
"id": "P1_STATE_ENCODING",
"type": "invariant",
"natural_language": "observable state outputs always encode at most one active mode",
"expression": "$onehot0({busy, retrying, done})",
"disable": "rst"
},
{
"id": "P2_RESET",
"type": "next_cycle_implication",
"natural_language": ... | {"drop_t1.sv": "module handshake_0008_mutant_drop_t1 (\n input wire clk,\n input wire rst,\n input wire req,\n input wire accept,\n input wire retry,\n output reg busy,\n output reg retrying,\n output reg done\n);\n localparam [1:0] IDLE = 2'd0;\n localparam [1:0] WAIT = 2'd1;\n ... |
handshake_0008 | handshake | Request can be accepted, retried, or completed. | nested_if.sv | module handshake_0008_nested_if (
input wire clk,
input wire rst,
input wire req,
input wire accept,
input wire retry,
output wire busy,
output wire retrying,
output wire done
);
localparam [1:0] S_IDLE = 2'd0;
localparam [1:0] S_WAIT = 2'd1;
localparam [1:0] S_RETRY... | {
"design_id": "handshake_0008",
"category": "handshake",
"template": "retry_handshake",
"description": "Request can be accepted, retried, or completed.",
"clock": {
"name": "clk",
"edge": "posedge"
},
"reset": {
"name": "rst",
"active": "high",
"synchronous": true,
"state": "IDLE"... | // Generated from spec.json.
// Design: handshake_0008
// P1_STATE_ENCODING: observable state outputs always encode at most one active mode.
p_state_encoding: assert property (@(posedge clk) disable iff (rst)
$onehot0({busy, retrying, done}));
// P2_RESET: reset returns the controller to its reset behavior.
p_res... | [
{
"id": "P1_STATE_ENCODING",
"type": "invariant",
"natural_language": "observable state outputs always encode at most one active mode",
"expression": "$onehot0({busy, retrying, done})",
"disable": "rst"
},
{
"id": "P2_RESET",
"type": "next_cycle_implication",
"natural_language": ... | {"drop_t1.sv": "module handshake_0008_mutant_drop_t1 (\n input wire clk,\n input wire rst,\n input wire req,\n input wire accept,\n input wire retry,\n output reg busy,\n output reg retrying,\n output reg done\n);\n localparam [1:0] IDLE = 2'd0;\n localparam [1:0] WAIT = 2'd1;\n ... |
handshake_0008 | handshake | Request can be accepted, retried, or completed. | factored_flags.sv | module handshake_0008_factored_flags (
input wire clk,
input wire rst,
input wire req,
input wire accept,
input wire retry,
output reg busy,
output reg retrying,
output reg done
);
localparam [1:0] F_IDLE = 2'd0;
localparam [1:0] F_WAIT = 2'd1;
localpa... | {
"design_id": "handshake_0008",
"category": "handshake",
"template": "retry_handshake",
"description": "Request can be accepted, retried, or completed.",
"clock": {
"name": "clk",
"edge": "posedge"
},
"reset": {
"name": "rst",
"active": "high",
"synchronous": true,
"state": "IDLE"... | // Generated from spec.json.
// Design: handshake_0008
// P1_STATE_ENCODING: observable state outputs always encode at most one active mode.
p_state_encoding: assert property (@(posedge clk) disable iff (rst)
$onehot0({busy, retrying, done}));
// P2_RESET: reset returns the controller to its reset behavior.
p_res... | [
{
"id": "P1_STATE_ENCODING",
"type": "invariant",
"natural_language": "observable state outputs always encode at most one active mode",
"expression": "$onehot0({busy, retrying, done})",
"disable": "rst"
},
{
"id": "P2_RESET",
"type": "next_cycle_implication",
"natural_language": ... | {"drop_t1.sv": "module handshake_0008_mutant_drop_t1 (\n input wire clk,\n input wire rst,\n input wire req,\n input wire accept,\n input wire retry,\n output reg busy,\n output reg retrying,\n output reg done\n);\n localparam [1:0] IDLE = 2'd0;\n localparam [1:0] WAIT = 2'd1;\n ... |
interrupt_0001 | interrupt_control | Interrupt request is latched until acknowledged. | canonical_case.sv | module interrupt_0001_canonical_case (
input wire clk,
input wire rst,
input wire irq,
input wire ack,
output reg pending
);
localparam [0:0] IDLE = 1'd0;
localparam [0:0] PENDING = 1'd1;
reg [0:0] state, next_state;
always @* begin
next_state = state;
case (s... | {
"design_id": "interrupt_0001",
"category": "interrupt_control",
"template": "latched_interrupt",
"description": "Interrupt request is latched until acknowledged.",
"clock": {
"name": "clk",
"edge": "posedge"
},
"reset": {
"name": "rst",
"active": "high",
"synchronous": true,
"sta... | // Generated from spec.json.
// Design: interrupt_0001
// P1_RESET: reset leaves no interrupt pending.
p_reset: assert property (@(posedge clk)
(rst) |=> (!pending));
// P2_LATCH: an interrupt request becomes pending.
p_latch: assert property (@(posedge clk) disable iff (rst)
(!pending && irq) |=> (pending));... | [
{
"id": "P1_RESET",
"type": "next_cycle_implication",
"natural_language": "reset leaves no interrupt pending",
"antecedent": "rst",
"consequent": "!pending",
"delay": 1
},
{
"id": "P2_LATCH",
"type": "next_cycle_implication",
"natural_language": "an interrupt request becomes ... | {"ignore_ack.sv": "module interrupt_0001_mutant_ignore_ack (\n input wire clk,\n input wire rst,\n input wire irq,\n input wire ack,\n output reg pending\n);\n localparam [0:0] IDLE = 1'd0;\n localparam [0:0] PENDING = 1'd1;\n\n reg [0:0] state, next_state;\n\n always @* begin\n ... |
interrupt_0001 | interrupt_control | Interrupt request is latched until acknowledged. | onehot_case.sv | module interrupt_0001_onehot_case (
input wire clk,
input wire rst,
input wire irq,
input wire ack,
output reg pending
);
localparam [1:0] IDLE = 2'b01;
localparam [1:0] PENDING = 2'b10;
reg [1:0] state, next_state;
always @* begin
next_state = IDLE;
case (sta... | {
"design_id": "interrupt_0001",
"category": "interrupt_control",
"template": "latched_interrupt",
"description": "Interrupt request is latched until acknowledged.",
"clock": {
"name": "clk",
"edge": "posedge"
},
"reset": {
"name": "rst",
"active": "high",
"synchronous": true,
"sta... | // Generated from spec.json.
// Design: interrupt_0001
// P1_RESET: reset leaves no interrupt pending.
p_reset: assert property (@(posedge clk)
(rst) |=> (!pending));
// P2_LATCH: an interrupt request becomes pending.
p_latch: assert property (@(posedge clk) disable iff (rst)
(!pending && irq) |=> (pending));... | [
{
"id": "P1_RESET",
"type": "next_cycle_implication",
"natural_language": "reset leaves no interrupt pending",
"antecedent": "rst",
"consequent": "!pending",
"delay": 1
},
{
"id": "P2_LATCH",
"type": "next_cycle_implication",
"natural_language": "an interrupt request becomes ... | {"ignore_ack.sv": "module interrupt_0001_mutant_ignore_ack (\n input wire clk,\n input wire rst,\n input wire irq,\n input wire ack,\n output reg pending\n);\n localparam [0:0] IDLE = 1'd0;\n localparam [0:0] PENDING = 1'd1;\n\n reg [0:0] state, next_state;\n\n always @* begin\n ... |
interrupt_0001 | interrupt_control | Interrupt request is latched until acknowledged. | nested_if.sv | module interrupt_0001_nested_if (
input wire clk,
input wire rst,
input wire irq,
input wire ack,
output wire pending
);
localparam [0:0] S_IDLE = 1'd0;
localparam [0:0] S_PENDING = 1'd1;
reg [0:0] state;
always @(posedge clk) begin
if (rst) begin
state <=... | {
"design_id": "interrupt_0001",
"category": "interrupt_control",
"template": "latched_interrupt",
"description": "Interrupt request is latched until acknowledged.",
"clock": {
"name": "clk",
"edge": "posedge"
},
"reset": {
"name": "rst",
"active": "high",
"synchronous": true,
"sta... | // Generated from spec.json.
// Design: interrupt_0001
// P1_RESET: reset leaves no interrupt pending.
p_reset: assert property (@(posedge clk)
(rst) |=> (!pending));
// P2_LATCH: an interrupt request becomes pending.
p_latch: assert property (@(posedge clk) disable iff (rst)
(!pending && irq) |=> (pending));... | [
{
"id": "P1_RESET",
"type": "next_cycle_implication",
"natural_language": "reset leaves no interrupt pending",
"antecedent": "rst",
"consequent": "!pending",
"delay": 1
},
{
"id": "P2_LATCH",
"type": "next_cycle_implication",
"natural_language": "an interrupt request becomes ... | {"ignore_ack.sv": "module interrupt_0001_mutant_ignore_ack (\n input wire clk,\n input wire rst,\n input wire irq,\n input wire ack,\n output reg pending\n);\n localparam [0:0] IDLE = 1'd0;\n localparam [0:0] PENDING = 1'd1;\n\n reg [0:0] state, next_state;\n\n always @* begin\n ... |
interrupt_0001 | interrupt_control | Interrupt request is latched until acknowledged. | factored_flags.sv | module interrupt_0001_factored_flags (
input wire clk,
input wire rst,
input wire irq,
input wire ack,
output reg pending
);
localparam [0:0] F_IDLE = 1'd0;
localparam [0:0] F_PENDING = 1'd1;
reg [0:0] state, next_state;
wire guard_idle_0 = (irq);
wire guard_i... | {
"design_id": "interrupt_0001",
"category": "interrupt_control",
"template": "latched_interrupt",
"description": "Interrupt request is latched until acknowledged.",
"clock": {
"name": "clk",
"edge": "posedge"
},
"reset": {
"name": "rst",
"active": "high",
"synchronous": true,
"sta... | // Generated from spec.json.
// Design: interrupt_0001
// P1_RESET: reset leaves no interrupt pending.
p_reset: assert property (@(posedge clk)
(rst) |=> (!pending));
// P2_LATCH: an interrupt request becomes pending.
p_latch: assert property (@(posedge clk) disable iff (rst)
(!pending && irq) |=> (pending));... | [
{
"id": "P1_RESET",
"type": "next_cycle_implication",
"natural_language": "reset leaves no interrupt pending",
"antecedent": "rst",
"consequent": "!pending",
"delay": 1
},
{
"id": "P2_LATCH",
"type": "next_cycle_implication",
"natural_language": "an interrupt request becomes ... | {"ignore_ack.sv": "module interrupt_0001_mutant_ignore_ack (\n input wire clk,\n input wire rst,\n input wire irq,\n input wire ack,\n output reg pending\n);\n localparam [0:0] IDLE = 1'd0;\n localparam [0:0] PENDING = 1'd1;\n\n reg [0:0] state, next_state;\n\n always @* begin\n ... |
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