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============================================================================== |
RTL-MP MACRO CLUSTERS (design: VeriGPU) |
============================================================================== |
1 macro clusters, 12 macros |
------------------------------------------------------------------------------ |
MACRO_CLUSTERS |
------------------------------------------------------------------------------ |
[ 44] <top>.p0.p0.p0.p1/macros |
type=Macro macro_count=12 macro_types={'small_mem': 12} |
inst_58676 type=small_mem size=75.56x149.125um orient=R0 pins=L38,R39,B10,T10 |
inst_58677 type=small_mem size=75.56x149.125um orient=R0 pins=L38,R39,B10,T10 |
inst_58678 type=small_mem size=75.56x149.125um orient=R0 pins=L38,R39,B10,T10 |
inst_61847 type=small_mem size=75.56x149.125um orient=R0 pins=L38,R39,B10,T10 |
inst_61848 type=small_mem size=75.56x149.125um orient=R0 pins=L38,R39,B10,T10 |
inst_61849 type=small_mem size=75.56x149.125um orient=R0 pins=L38,R39,B10,T10 |
inst_61850 type=small_mem size=75.56x149.125um orient=R0 pins=L38,R39,B10,T10 |
inst_61851 type=small_mem size=75.56x149.125um orient=R0 pins=L38,R39,B10,T10 |
inst_61852 type=small_mem size=75.56x149.125um orient=R0 pins=L38,R39,B10,T10 |
inst_61853 type=small_mem size=75.56x149.125um orient=R0 pins=L38,R39,B10,T10 |
inst_61854 type=small_mem size=75.56x149.125um orient=R0 pins=L38,R39,B10,T10 |
inst_61855 type=small_mem size=75.56x149.125um orient=R0 pins=L38,R39,B10,T10 |
============================================================================== |
RTL-MP MACRO CLUSTERS (design: ariane133) |
============================================================================== |
14 macro clusters, 132 macros |
------------------------------------------------------------------------------ |
MACRO_CLUSTERS |
------------------------------------------------------------------------------ |
[137] i_cache_subsystem/i_icache/sram_block_0__data_sram/macros |
type=Macro macro_count=8 macro_types={'fakeram45_256x16': 8} |
i_cache_subsystem/i_icache/sram_block_0__data_sram/genblk1_0__i_ram/macro_mem_0 type=fakeram45_256x16 size=77.71x40.6um orient=R0 pins=L59,R0,B0,T0 |
i_cache_subsystem/i_icache/sram_block_0__data_sram/genblk1_0__i_ram/macro_mem_1 type=fakeram45_256x16 size=77.71x40.6um orient=R0 pins=L59,R0,B0,T0 |
i_cache_subsystem/i_icache/sram_block_0__data_sram/genblk1_0__i_ram/macro_mem_2 type=fakeram45_256x16 size=77.71x40.6um orient=R0 pins=L59,R0,B0,T0 |
i_cache_subsystem/i_icache/sram_block_0__data_sram/genblk1_0__i_ram/macro_mem_3 type=fakeram45_256x16 size=77.71x40.6um orient=R0 pins=L59,R0,B0,T0 |
i_cache_subsystem/i_icache/sram_block_0__data_sram/genblk1_1__i_ram/macro_mem_0 type=fakeram45_256x16 size=77.71x40.6um orient=R0 pins=L59,R0,B0,T0 |
i_cache_subsystem/i_icache/sram_block_0__data_sram/genblk1_1__i_ram/macro_mem_1 type=fakeram45_256x16 size=77.71x40.6um orient=R0 pins=L59,R0,B0,T0 |
i_cache_subsystem/i_icache/sram_block_0__data_sram/genblk1_1__i_ram/macro_mem_2 type=fakeram45_256x16 size=77.71x40.6um orient=R0 pins=L59,R0,B0,T0 |
i_cache_subsystem/i_icache/sram_block_0__data_sram/genblk1_1__i_ram/macro_mem_3 type=fakeram45_256x16 size=77.71x40.6um orient=R0 pins=L59,R0,B0,T0 |
------------------------------------------------------------------------------ |
[139] i_cache_subsystem/i_icache/sram_block_1__data_sram/macros |
type=Macro macro_count=8 macro_types={'fakeram45_256x16': 8} |
i_cache_subsystem/i_icache/sram_block_1__data_sram/genblk1_0__i_ram/macro_mem_0 type=fakeram45_256x16 size=77.71x40.6um orient=R0 pins=L59,R0,B0,T0 |
i_cache_subsystem/i_icache/sram_block_1__data_sram/genblk1_0__i_ram/macro_mem_1 type=fakeram45_256x16 size=77.71x40.6um orient=R0 pins=L59,R0,B0,T0 |
i_cache_subsystem/i_icache/sram_block_1__data_sram/genblk1_0__i_ram/macro_mem_2 type=fakeram45_256x16 size=77.71x40.6um orient=R0 pins=L59,R0,B0,T0 |
i_cache_subsystem/i_icache/sram_block_1__data_sram/genblk1_0__i_ram/macro_mem_3 type=fakeram45_256x16 size=77.71x40.6um orient=R0 pins=L59,R0,B0,T0 |
i_cache_subsystem/i_icache/sram_block_1__data_sram/genblk1_1__i_ram/macro_mem_0 type=fakeram45_256x16 size=77.71x40.6um orient=R0 pins=L59,R0,B0,T0 |
i_cache_subsystem/i_icache/sram_block_1__data_sram/genblk1_1__i_ram/macro_mem_1 type=fakeram45_256x16 size=77.71x40.6um orient=R0 pins=L59,R0,B0,T0 |
i_cache_subsystem/i_icache/sram_block_1__data_sram/genblk1_1__i_ram/macro_mem_2 type=fakeram45_256x16 size=77.71x40.6um orient=R0 pins=L59,R0,B0,T0 |
i_cache_subsystem/i_icache/sram_block_1__data_sram/genblk1_1__i_ram/macro_mem_3 type=fakeram45_256x16 size=77.71x40.6um orient=R0 pins=L59,R0,B0,T0 |
------------------------------------------------------------------------------ |
[141] i_cache_subsystem/i_icache/sram_block_2__data_sram/macros |
type=Macro macro_count=8 macro_types={'fakeram45_256x16': 8} |
i_cache_subsystem/i_icache/sram_block_2__data_sram/genblk1_0__i_ram/macro_mem_0 type=fakeram45_256x16 size=77.71x40.6um orient=R0 pins=L59,R0,B0,T0 |
i_cache_subsystem/i_icache/sram_block_2__data_sram/genblk1_0__i_ram/macro_mem_1 type=fakeram45_256x16 size=77.71x40.6um orient=R0 pins=L59,R0,B0,T0 |
i_cache_subsystem/i_icache/sram_block_2__data_sram/genblk1_0__i_ram/macro_mem_2 type=fakeram45_256x16 size=77.71x40.6um orient=R0 pins=L59,R0,B0,T0 |
i_cache_subsystem/i_icache/sram_block_2__data_sram/genblk1_0__i_ram/macro_mem_3 type=fakeram45_256x16 size=77.71x40.6um orient=R0 pins=L59,R0,B0,T0 |
i_cache_subsystem/i_icache/sram_block_2__data_sram/genblk1_1__i_ram/macro_mem_0 type=fakeram45_256x16 size=77.71x40.6um orient=R0 pins=L59,R0,B0,T0 |
i_cache_subsystem/i_icache/sram_block_2__data_sram/genblk1_1__i_ram/macro_mem_1 type=fakeram45_256x16 size=77.71x40.6um orient=R0 pins=L59,R0,B0,T0 |
i_cache_subsystem/i_icache/sram_block_2__data_sram/genblk1_1__i_ram/macro_mem_2 type=fakeram45_256x16 size=77.71x40.6um orient=R0 pins=L59,R0,B0,T0 |
i_cache_subsystem/i_icache/sram_block_2__data_sram/genblk1_1__i_ram/macro_mem_3 type=fakeram45_256x16 size=77.71x40.6um orient=R0 pins=L59,R0,B0,T0 |
------------------------------------------------------------------------------ |
[143] i_cache_subsystem/i_icache/sram_block_3__data_sram/macros |
type=Macro macro_count=8 macro_types={'fakeram45_256x16': 8} |
i_cache_subsystem/i_icache/sram_block_3__data_sram/genblk1_0__i_ram/macro_mem_0 type=fakeram45_256x16 size=77.71x40.6um orient=R0 pins=L59,R0,B0,T0 |
i_cache_subsystem/i_icache/sram_block_3__data_sram/genblk1_0__i_ram/macro_mem_1 type=fakeram45_256x16 size=77.71x40.6um orient=R0 pins=L59,R0,B0,T0 |
i_cache_subsystem/i_icache/sram_block_3__data_sram/genblk1_0__i_ram/macro_mem_2 type=fakeram45_256x16 size=77.71x40.6um orient=R0 pins=L59,R0,B0,T0 |
i_cache_subsystem/i_icache/sram_block_3__data_sram/genblk1_0__i_ram/macro_mem_3 type=fakeram45_256x16 size=77.71x40.6um orient=R0 pins=L59,R0,B0,T0 |
i_cache_subsystem/i_icache/sram_block_3__data_sram/genblk1_1__i_ram/macro_mem_0 type=fakeram45_256x16 size=77.71x40.6um orient=R0 pins=L59,R0,B0,T0 |
i_cache_subsystem/i_icache/sram_block_3__data_sram/genblk1_1__i_ram/macro_mem_1 type=fakeram45_256x16 size=77.71x40.6um orient=R0 pins=L59,R0,B0,T0 |
i_cache_subsystem/i_icache/sram_block_3__data_sram/genblk1_1__i_ram/macro_mem_2 type=fakeram45_256x16 size=77.71x40.6um orient=R0 pins=L59,R0,B0,T0 |
i_cache_subsystem/i_icache/sram_block_3__data_sram/genblk1_1__i_ram/macro_mem_3 type=fakeram45_256x16 size=77.71x40.6um orient=R0 pins=L59,R0,B0,T0 |
------------------------------------------------------------------------------ |
[145] i_cache_subsystem/i_nbdcache/sram_block_0__data_sram/macros |
type=Macro macro_count=8 macro_types={'fakeram45_256x16': 8} |
i_cache_subsystem/i_nbdcache/sram_block_0__data_sram/genblk1_0__i_ram/macro_mem_0 type=fakeram45_256x16 size=77.71x40.6um orient=R0 pins=L59,R0,B0,T0 |
i_cache_subsystem/i_nbdcache/sram_block_0__data_sram/genblk1_0__i_ram/macro_mem_1 type=fakeram45_256x16 size=77.71x40.6um orient=R0 pins=L59,R0,B0,T0 |
i_cache_subsystem/i_nbdcache/sram_block_0__data_sram/genblk1_0__i_ram/macro_mem_2 type=fakeram45_256x16 size=77.71x40.6um orient=R0 pins=L59,R0,B0,T0 |
i_cache_subsystem/i_nbdcache/sram_block_0__data_sram/genblk1_0__i_ram/macro_mem_3 type=fakeram45_256x16 size=77.71x40.6um orient=R0 pins=L59,R0,B0,T0 |
i_cache_subsystem/i_nbdcache/sram_block_0__data_sram/genblk1_1__i_ram/macro_mem_0 type=fakeram45_256x16 size=77.71x40.6um orient=R0 pins=L59,R0,B0,T0 |
i_cache_subsystem/i_nbdcache/sram_block_0__data_sram/genblk1_1__i_ram/macro_mem_1 type=fakeram45_256x16 size=77.71x40.6um orient=R0 pins=L59,R0,B0,T0 |
i_cache_subsystem/i_nbdcache/sram_block_0__data_sram/genblk1_1__i_ram/macro_mem_2 type=fakeram45_256x16 size=77.71x40.6um orient=R0 pins=L59,R0,B0,T0 |
i_cache_subsystem/i_nbdcache/sram_block_0__data_sram/genblk1_1__i_ram/macro_mem_3 type=fakeram45_256x16 size=77.71x40.6um orient=R0 pins=L59,R0,B0,T0 |
------------------------------------------------------------------------------ |
[147] i_cache_subsystem/i_nbdcache/sram_block_1__data_sram/macros |
type=Macro macro_count=8 macro_types={'fakeram45_256x16': 8} |
i_cache_subsystem/i_nbdcache/sram_block_1__data_sram/genblk1_0__i_ram/macro_mem_0 type=fakeram45_256x16 size=77.71x40.6um orient=R0 pins=L59,R0,B0,T0 |
i_cache_subsystem/i_nbdcache/sram_block_1__data_sram/genblk1_0__i_ram/macro_mem_1 type=fakeram45_256x16 size=77.71x40.6um orient=R0 pins=L59,R0,B0,T0 |
i_cache_subsystem/i_nbdcache/sram_block_1__data_sram/genblk1_0__i_ram/macro_mem_2 type=fakeram45_256x16 size=77.71x40.6um orient=R0 pins=L59,R0,B0,T0 |
i_cache_subsystem/i_nbdcache/sram_block_1__data_sram/genblk1_0__i_ram/macro_mem_3 type=fakeram45_256x16 size=77.71x40.6um orient=R0 pins=L59,R0,B0,T0 |
i_cache_subsystem/i_nbdcache/sram_block_1__data_sram/genblk1_1__i_ram/macro_mem_0 type=fakeram45_256x16 size=77.71x40.6um orient=R0 pins=L59,R0,B0,T0 |
i_cache_subsystem/i_nbdcache/sram_block_1__data_sram/genblk1_1__i_ram/macro_mem_1 type=fakeram45_256x16 size=77.71x40.6um orient=R0 pins=L59,R0,B0,T0 |
i_cache_subsystem/i_nbdcache/sram_block_1__data_sram/genblk1_1__i_ram/macro_mem_2 type=fakeram45_256x16 size=77.71x40.6um orient=R0 pins=L59,R0,B0,T0 |
i_cache_subsystem/i_nbdcache/sram_block_1__data_sram/genblk1_1__i_ram/macro_mem_3 type=fakeram45_256x16 size=77.71x40.6um orient=R0 pins=L59,R0,B0,T0 |
------------------------------------------------------------------------------ |
[149] i_cache_subsystem/i_nbdcache/sram_block_2__data_sram/macros |
type=Macro macro_count=8 macro_types={'fakeram45_256x16': 8} |
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