diff --git a/README.md b/README.md index 6fd42de3267af4df2844d7129396456086c7f971..441cadfc8f66a8f5624897171ebfdccf35a3ed7e 100644 --- a/README.md +++ b/README.md @@ -9,13 +9,13 @@ tags: --- # Inference Kernels -24 [FlashInfer Trace](https://github.com/flashinfer-ai/flashinfer-bench/tree/main/docs/flashinfer-trace) operator definitions, with self-contained PyTorch references, open-source baseline solutions, and workloads captured from actual SGLang inference. Model dimensions are constants. Runtime batch sizes, sequence lengths, page sizes, and image grids remain variable. +21 [FlashInfer Trace](https://github.com/flashinfer-ai/flashinfer-bench/tree/main/docs/flashinfer-trace) operator definitions, with self-contained PyTorch references, open-source baseline solutions, and workloads captured from actual inference: 19 through SGLang, and the 2 gated delta definitions from the [MLSys 2026 FlashInfer contest](https://huggingface.co/datasets/flashinfer-ai/mlsys26-contest/tree/5e832ce88dd1013032b22a0e942979d7d2769cc3). Model dimensions are constants. Runtime batch sizes, sequence lengths, page sizes, and image grids remain variable. Every published tensor input references a complete `safetensors` snapshot. Python scalar arguments use scalar descriptors. There are no random-input descriptors or synthetic activation generators. `captures.jsonl` joins each workload UUID to its model revision, request, engine operation, input adaptations, actual outputs, and validation results. -**1,383 real workloads cover all 24 definitions and pass complete-output replay:** 257 Qwen Image, 641 Qwen Flash-Next, 278 DeepSeek, and 207 LTX. The complete dataset is published at [humanfia-lab/inference-kernels](https://huggingface.co/datasets/humanfia-lab/inference-kernels), including definitions, workloads, capture records, baseline solutions, and tensors. The 6,763 tensor paths contain 6,223 unique snapshots of inputs, complete engine outputs, and auxiliary capture tensors. Fetch them with Git LFS before running workloads. +**1,104 real workloads cover all 21 definitions:** 133 Qwen Image, 384 Qwen Flash-Next, 226 DeepSeek, 207 LTX, and 154 Qwen3-Next from the MLSys 2026 contest. The 950 SGLang captures pass complete-output replay; the contest publishes no engine outputs, so its workloads are checked by running the reference. The complete dataset is published at [humanfia-lab/inference-kernels](https://huggingface.co/datasets/humanfia-lab/inference-kernels), including definitions, workloads, capture records, baseline solutions, and tensors. The 5,506 tensor paths contain 5,124 unique snapshots of inputs, complete engine outputs, and auxiliary capture tensors. Fetch them with Git LFS before running workloads. -The dataset was regenerated from full pinned checkpoints through SGLang on NVIDIA B300 GPUs. Definitions, reference code, tolerances, and baseline solutions are unchanged. +The dataset was regenerated from full pinned checkpoints through SGLang on NVIDIA B300 GPUs. Definitions, reference code, tolerances, and baseline solutions are unchanged, apart from the [curation](#curation) for kernels that real inference uses. ## Kernels @@ -23,23 +23,23 @@ BF16, FP16, FP32, and FP64 mean 16-bit Brain Floating Point, IEEE half precision | Family | Model | Fixed dimensions | Definitions | Workloads | |---|---|---|---:|---:| -| Dense matrix multiplication | Qwen Image 2.1 Turbo | `(N,K)`: `(4096,4096)`, `(12288,4096)`, `(4096,12288)`, `(4096,64)`, `(64,4096)` | 5 | 217 | -| Grouped expert matrix multiplication | DeepSeek V4.1 Flash | 384 experts; `(N,K)`: `(2304,5120)`, `(4608,5120)`, `(5120,2304)`; FP8 × FP4 | 3 | 156 | +| Dense matrix multiplication | Qwen Image 2.1 Turbo | `(N,K)`: `(4096,4096)`, `(12288,4096)`, `(4096,12288)`; `M >= 4096` | 3 | 93 | +| Grouped expert matrix multiplication | DeepSeek V4.1 Flash | 384 experts; `(N,K)`: `(4608,5120)`, `(5120,2304)`; FP8 × FP4 | 2 | 104 | | Mixed-format latent attention | DeepSeek V4.1 Flash | 64 heads × 512 dimensions; 128 FP8 window slots and 512 FP4 compressed slots | 1 | 42 | | Sparse multi-head latent attention (MLA), prefill | DeepSeek V4.1 Flash | 64 query heads × 512 dimensions; 1 shared key/value head; BF16; separate 128-slot and 640-slot definitions | 2 | 30 | -| Gated delta recurrence | Qwen 3.8 Flash-Next | 16 shared query/key heads, 48 value heads, dimensions 128; prefill and decode | 2 | 257 | -| Noncausal dense attention | LTX-2.5 | Video: 32 heads × 128; audio: 32 heads × 64 | 2 | 162 | +| Gated delta recurrence | Qwen3-Next (MLSys 2026 contest) | 4 query/key heads, 8 value heads (TP=4 shard), dimension 128; k-last state; prefill and decode | 2 | 154 | +| Noncausal dense attention | LTX-2.5 | Video: 32 heads × 128; audio: 32 heads × 64; no mask | 2 | 162 | | Qwen sparse attention | Qwen 3.8 Flash-Next | 24 query heads, 2 key/value heads, dimension 256; 512 four-token blocks | 1 | 192 | | Prefix-cached block-causal attention | Qwen Image 2.1 Turbo | 32 heads × 128; empty-prefix and cached-prefix cases | 2 | 40 | | Sparse index scoring and selection | Qwen 3.8 Flash-Next | 4 query heads × 128; Top-512 complete four-token blocks | 1 | 192 | | Expert router | DeepSeek V4.1 Flash | Hidden dimension 5120, 384 experts, Top-6 selection | 1 | 50 | | Three-dimensional neighborhood attention | LTX-2.5 diffusion decoder | Dimension 64; `(heads, window)`: `(32,3×7×7)`, `(16,3×7×7)`, `(8,3×5×5)`, `(4,11×11×11)` | 4 | 45 | -**[Shape distribution histograms for all 24 kernels](docs/shape-distributions/README.md)** show how the 1,383 workloads are distributed across exact runtime shapes. Each bar counts captured workloads with the same complete combination of variable dimensions; fixed model dimensions are listed above the plot. These counts describe this dataset, not AgentX traffic frequencies. Regenerate the figures with `python scripts/plot_shape_distributions.py` (requires Matplotlib; no GPU or tensor files needed). +**[Shape distribution histograms for all 21 kernels](docs/shape-distributions/README.md)** show how the 1,104 workloads are distributed across exact runtime shapes. Each bar counts captured workloads with the same complete combination of variable dimensions; fixed model dimensions are listed above the plot. These counts describe this dataset, not AgentX traffic frequencies. Regenerate the figures with `python scripts/plot_shape_distributions.py` (requires Matplotlib; no GPU or tensor files needed). Definitions describe complete logical operators. Captures preserve all model heads and experts; distributed shards must be gathered before publication. Backend padding, layout changes, and page remapping are recorded explicitly. Cache snapshots retain every referenced page, including its unused tail; unreachable allocator pages are omitted. Tensor strides are normalized to contiguous storage without changing values. -Gated delta prefill receives the engine's normalized BF16 Q/K, with each shared head repeated three times. Decode receives raw Q/K and gate inputs because the engine performs normalization and gating inside the kernel using FP32 arithmetic. Both interfaces use state layout `[batch, head, key_dimension, value_dimension]`. +The gated delta definitions are the MLSys 2026 contest's: Q/K/V with the gate inputs `A_log`, `a`, `dt_bias` and `b`, and the k-last state layout `[sequence, value head, value dimension, key dimension]`. Prefill takes variable-length sequences through `cu_seqlens`. These are unchanged Qwen3-Next TP=4 contest contracts, not a layout conversion of the removed Qwen Flash-Next captures. Their references do not perform Q/K L2 normalization, and they accept per-batch states rather than the original SGLang state pool and slot indices. Quantized byte carriers use `int8` because the trace schema lacks unsigned-byte and exponent-only scale types. The byte patterns remain unchanged. Grouped matrix multiplication uses logical scale layouts with one scale per 32 K elements. Mixed attention preserves the engine's physical pages: each page stores all payload rows followed by all scale rows. Both cache formats share the softmax denominator, including the zero-value attention sink. @@ -100,14 +100,14 @@ Each is submitted with 1, 2, and 4 requested outputs, at 24 frames per second. M `solutions/` contains native FlashInfer Trace Solution JSON files, with embedded source code, entry points, and pinned dependencies. Each solution accepts the definition's complete inputs and returns its complete outputs. GPU layout conversions, padding, sparse gathers, and output reordering are included in the solution call. -The existing baseline implementations and B200 measurements come from the original 768-workload dataset. They are retained unchanged. The regenerated 1,383-workload dataset has passed complete engine-output replay against the independent references; baseline solutions have not been rebenchmarked on this new dataset. +The existing baseline implementations and B200 measurements come from the original 768-workload dataset. They are retained unchanged. The regenerated dataset's SGLang captures have passed complete engine-output replay against the independent references; baseline solutions have not been rebenchmarked on this new dataset. | Kernels | Open-source implementation | |---|---| | Dense and grouped matrix multiplication | [DeepGEMM](https://github.com/deepseek-ai/DeepGEMM/tree/1fc9c66975ee322d628b3288534ca0e9ce12a64d); selected small dense shapes use [FlashInfer](https://github.com/flashinfer-ai/flashinfer) 0.7.2 CuTe DSL | | Sparse MLA prefill and mixed-format MLA decode | [FlashMLA](https://github.com/deepseek-ai/FlashMLA/tree/0f11e178da1f67becb087a324b400854931ec3e3) | | Dense, block-causal, and sparse grouped-query attention | [FlashAttention-4](https://github.com/Dao-AILab/flash-attention) 4.0.0b35, with runtime masks or sparse-input adapters | -| Gated delta recurrence | FlashInfer 0.7.2 prefill; adapted [SGLang](https://github.com/sgl-project/sglang/tree/9d394dfbd755759d3add89cfd0bc86d59b31f78c) fused Triton decode | +| Gated delta recurrence | The MLSys 2026 contest's FlashInfer prefill and decode wrappers, unchanged | | Sparse index scoring and selection | SGLang TileLang scoring, exact-threshold Top-512, and Triton compaction that preserves lower-ID ties | | Expert router | FlashInfer CUTLASS FP32-output projection and compiled PyTorch scoring/selection | | Three-dimensional neighborhood attention | [NATTEN](https://github.com/SHI-Labs/NATTEN/tree/39375ea1d2f3b1bb284315fa5f79f6ecbebb6382) 0.21.7 Blackwell fused neighborhood attention | @@ -126,6 +126,33 @@ python scripts/benchmark_solutions.py \ The runner uses the native Trace builder, validates every output element against the unchanged definition reference, then measures GPU time with CUDA events over CUDA Graph replays. Compilation and input loading occur before timing. `--solution NAME` selects a solution and `--validation-only` skips timing. `--compare-to capture` explicitly compares against saved engine outputs instead; two approximate implementations can differ beyond tolerance even when both pass against the independent reference. +### SGLang baselines + +Each SGLang-captured definition also has `solutions//sglang_.json`: SGLang's own implementation at the capture commit `684fea8a`, called the way the engine calls it, so that a kernel can be timed against what serving actually runs. The module docstring cites the engine call path. Run these solutions inside the capture image `lmsysorg/sglang@sha256:ddae0e399d3d94f7827f16183301cf8dac4cf0eae0ef25590b7dac5881d713d8`. Each module also exposes `prepare(*inputs)`, which does the host-side setup the engine does once (layouts, block masks, workspaces) and returns a zero-argument `launch`; `run(*inputs)` does both. + +The SGLang solutions adapt the dataset's independent operator interfaces to the pinned engine implementations. Those adapters include padding, layouts, per-rank calls, metadata and output ordering where needed; their module docstrings describe the boundary. A passing standalone workload does not establish that a candidate can replace an engine call without integration work. + +### KDA acceptance configs + +`kda/.json` is how KDA (Kernel Design Agents) judges a candidate kernel on that definition. The definition's reference is the truth, and the SGLang baseline above is timed live on every workload, with only `launch` timed. The fields are: +- `tolerance`: `atol` and `rtol` apply per element. A non-null `required_matched_ratio` is the fraction of elements that must pass; the LTX dense attention uses 0.9999 because fused attention kernels round the probabilities to BF16 and miss the every-element bound on 1–3 of up to 10⁹ elements. +- `dev`: at most ten representative workloads for quick iteration; final judgments use every workload. +- `group_axis` and `timing` (`warmup`, `iters`, `trials`). + +## Curation + +This revision curates inference operator tasks for KDA (Kernel Design Agents). Per-shape definitions, workload files and solution names stay separate; model dimensions remain constant axes. Captured interface adaptations are retained explicitly. +- **Removed `dense_gemm_bf16_nt_n64_k4096` and `dense_gemm_bf16_nt_n4096_k64`.** These are the image output and input projections: memory-bound 8–45 µs GEMMs that run once per forward. +- **Removed `grouped_gemm_fp8_fp4_e384_n2304_k5120_g32`.** It was cut from the columns of the concatenated gate/up GEMM; no engine runs a separate gate or up GEMM. +- **Replaced the gated delta definitions.** `gated_delta_rule_prefill_h48_dk128_dv128` pre-repeated 16 Q/K heads to 48; the old decode kept 16 raw Q/K heads and included normalization and gating. Both captures extracted states from the engine pool and transposed them to `[B, H, K, V]`. They are replaced by the [MLSys 2026 FlashInfer contest](https://huggingface.co/datasets/flashinfer-ai/mlsys26-contest/tree/5e832ce88dd1013032b22a0e942979d7d2769cc3) definitions `gdn_{decode,prefill}_qk4_v8_d128_k_last`, with their workloads and FlashInfer baselines unchanged. Each input tensor is stored in its own content-addressed file. Each receipt records the source workload, plus a check that the reference returns finite outputs of the declared shapes. +- **The three remaining dense GEMMs keep only their `M >= 4096` rows.** The `M <= 32` rows were 11–27 µs launches. +- **The LTX dense attention definitions drop the dense `[B, H, Nq, Nk]` visibility mask.** It was all True on every captured call (up to 839 MB). On one GPU the engine passes no mask, or an all-visible prompt mask. Replay against the captured engine outputs still passes. +- **Receipts and tensors.** The receipts of removed workloads are dropped, along with every tensor that nothing references. +- **Scripts.** + - `check_workload_inputs.py` evaluates constraints that read inputs, such as `cu_seqlens[-1]`. + - The replay in `capture_inputs.py` skips imported workloads, which have no engine output. + - `plot_shape_distributions.py` accepts axes without a description. + ## Reproduce The capture engine image is `lmsysorg/sglang:nightly-dev-cu13-20261014-684fea8a`, verified as `lmsysorg/sglang@sha256:ddae0e399d3d94f7827f16183301cf8dac4cf0eae0ef25590b7dac5881d713d8`. It contains PyTorch `2.14.1+cu130` and SGLang build `684fea8af3b11a5b51ec9966c02959a32ad3421c`. The native dataset checker was run with FlashInfer-Bench commit `15618a67e8d7b7f49ca61b5ba3b9f26a876d0bee`. The Modal runner defaults to its cached image in the current workspace; `--image` accepts another prepared Modal image ID. Install the Modal client locally and authenticate it before using the runner. Model downloads use a CPU worker and the task's persistent volume. @@ -176,7 +203,7 @@ CUDA_VISIBLE_DEVICES=0,1,2,3 python scripts/capture_llm.py \ To reproduce each validated LTX batch, use `--audio-sdpa-backend math --video-sdpa-backend math`, and run all three request types with `--num-outputs 1`, `2`, and `4` under distinct run names. Keep the same reference image for image editing and image-conditioned video. -The published dataset keeps every passing workload from the nine canonical runs: images 101 + 78 + 78; Qwen 193 serial + 448 concurrent; DeepSeek 278 of 279; LTX 69 + 69 + 69. The optional Modal retrieval filters (`--batch-sizes` and `--context-endpoints`) were not used for this publication. DeepSeek retains 52 workloads per grouped matrix definition, 50 router calls, 42 mixed-attention calls, and 30 sparse-prefill calls. Each grouped definition covers actual row counts 6/12/18/768/2688/11904/14592/17664/20736/24192/24576. Decode captures include early, middle, and final steps and actual concurrent batches 1/2/3. +The capture kept every passing workload from the nine canonical runs (the [curation](#curation) then removed some): images 101 + 78 + 78; Qwen 193 serial + 448 concurrent; DeepSeek 278 of 279; LTX 69 + 69 + 69. The optional Modal retrieval filters (`--batch-sizes` and `--context-endpoints`) were not used for this publication. DeepSeek retains 52 workloads per grouped matrix definition, 50 router calls, 42 mixed-attention calls, and 30 sparse-prefill calls. Each grouped definition covers actual row counts 6/12/18/768/2688/11904/14592/17664/20736/24192/24576. Decode captures include early, middle, and final steps and actual concurrent batches 1/2/3. All 768 original request/operator/step locations remain represented. New UUIDs and tensor hashes identify the regenerated values. Images, Qwen, and LTX retain every original exact runtime shape. DeepSeek mixed attention keeps the actual reachable physical pages selected by the new full-model execution: 14 calls differ in their `N4`/`N8` page counts, leaving 12 original exact storage shapes absent. These content-dependent cache footprints are not padded to imitate earlier allocations. @@ -202,7 +229,7 @@ BF16 comparisons use `rtol=0.016, atol=0.005`; FP32 uses `rtol=1e-4, atol=2e-5`; One complete router workload is excluded from the 279 DeepSeek raw captures: at two rows of a 4,096-row call, FP32 ranking ties produce different expert selections. The original FP32 reference and exact selected-set requirement remain unchanged. This call was also absent from the original dataset. No rows are removed from published tensors. All nine LTX requests pass and are included. -Tensor files are published directly as `blob/workloads//.safetensors` through Git LFS. Every workload and capture record references tensors under its definition directory. Shared snapshots have identical LFS objects across directories: 6,763 paths contain 6,223 unique snapshots totaling 168.49 GB (169.51 GB when materialized at every path). +Tensor files are published directly as `blob/workloads//.safetensors` through Git LFS. Every workload and capture record references tensors under its definition directory. Shared snapshots have identical LFS objects across directories: 5,506 paths contain 5,124 unique snapshots totaling 146.34 GB (146.44 GB when materialized at every path). ```bash git clone https://huggingface.co/datasets/humanfia-lab/inference-kernels diff --git a/blob/workloads/dense_gemm_bf16_nt_n12288_k4096/0191c80c22e505cbab4f6e0cf112d674509a9721cb4f35b7d232b99732c1d684.safetensors b/blob/workloads/dense_gemm_bf16_nt_n12288_k4096/0191c80c22e505cbab4f6e0cf112d674509a9721cb4f35b7d232b99732c1d684.safetensors deleted file mode 100644 index 5125438ac5901fa186ba2e74947bc2806b1af97b..0000000000000000000000000000000000000000 --- a/blob/workloads/dense_gemm_bf16_nt_n12288_k4096/0191c80c22e505cbab4f6e0cf112d674509a9721cb4f35b7d232b99732c1d684.safetensors +++ /dev/null @@ -1,3 +0,0 @@ -version https://git-lfs.github.com/spec/v1 -oid sha256:c408483d400eca522fe1a5c7c5b318201855361448c77bc1f70a5301b12dd86e -size 614480 diff --git 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The contest publishes no engine outputs.", "validation": {"uuid": "cd979341-7112-4887-a2f3-dfb269a49bbc", "definition": "gdn_prefill_qk4_v8_d128_k_last", "axes": {"total_seq_len": 76, "num_seqs": 2, "len_cu_seqlens": 3}, "status": "passed", "device": "cuda", "torch": "2.14.1+cu130", "seconds": 0.012277862057089806, "comparison": "reference outputs have the declared shapes and dtypes and are finite; the contest publishes no engine outputs to compare against"}} +{"uuid": "43bf9699-adb3-4161-b741-8ff07b553336", "definition": "gdn_prefill_qk4_v8_d128_k_last", "axes": {"total_seq_len": 959, "num_seqs": 4, "len_cu_seqlens": 5}, "source": "https://huggingface.co/datasets/flashinfer-ai/mlsys26-contest/tree/5e832ce88dd1013032b22a0e942979d7d2769cc3", "source_workload": "43bf9699-adb3-4161-b741-8ff07b553336", "model": "Qwen3-Next (TP=4), as recorded by the MLSys 2026 FlashInfer contest", "adapter": "Imported unchanged from the MLSys 2026 FlashInfer contest dataset; each input tensor is stored in its own content-addressed file. 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The contest publishes no engine outputs.", "validation": {"uuid": "54856fec-3b50-4866-815d-19bfa16cf58b", "definition": "gdn_prefill_qk4_v8_d128_k_last", "axes": {"total_seq_len": 959, "num_seqs": 4, "len_cu_seqlens": 5}, "status": "passed", "device": "cuda", "torch": "2.14.1+cu130", "seconds": 0.14402965921908617, "comparison": "reference outputs have the declared shapes and dtypes and are finite; the contest publishes no engine outputs to compare against"}} +{"uuid": "2ba465c0-7405-4bf1-ba4e-7d632d95f141", "definition": "gdn_prefill_qk4_v8_d128_k_last", "axes": {"total_seq_len": 28, "num_seqs": 2, "len_cu_seqlens": 3}, "source": "https://huggingface.co/datasets/flashinfer-ai/mlsys26-contest/tree/5e832ce88dd1013032b22a0e942979d7d2769cc3", "source_workload": "2ba465c0-7405-4bf1-ba4e-7d632d95f141", "model": "Qwen3-Next (TP=4), as recorded by the MLSys 2026 FlashInfer contest", "adapter": "Imported unchanged from the MLSys 2026 FlashInfer contest dataset; each input tensor is stored in its own content-addressed file. The contest publishes no engine outputs.", "validation": {"uuid": "2ba465c0-7405-4bf1-ba4e-7d632d95f141", "definition": "gdn_prefill_qk4_v8_d128_k_last", "axes": {"total_seq_len": 28, "num_seqs": 2, "len_cu_seqlens": 3}, "status": "passed", "device": "cuda", "torch": "2.14.1+cu130", "seconds": 0.005222685635089874, "comparison": "reference outputs have the declared shapes and dtypes and are finite; the contest publishes no engine outputs to compare against"}} +{"uuid": "1efaf2a9-05db-4737-8f41-6880ba1bb487", "definition": "gdn_prefill_qk4_v8_d128_k_last", "axes": {"total_seq_len": 42, "num_seqs": 2, "len_cu_seqlens": 3}, "source": "https://huggingface.co/datasets/flashinfer-ai/mlsys26-contest/tree/5e832ce88dd1013032b22a0e942979d7d2769cc3", "source_workload": "1efaf2a9-05db-4737-8f41-6880ba1bb487", "model": "Qwen3-Next (TP=4), as recorded by the MLSys 2026 FlashInfer contest", "adapter": "Imported unchanged from the MLSys 2026 FlashInfer contest dataset; each input tensor is stored in its own content-addressed file. The contest publishes no engine outputs.", "validation": {"uuid": "1efaf2a9-05db-4737-8f41-6880ba1bb487", "definition": "gdn_prefill_qk4_v8_d128_k_last", "axes": {"total_seq_len": 42, "num_seqs": 2, "len_cu_seqlens": 3}, "status": "passed", "device": "cuda", "torch": "2.14.1+cu130", "seconds": 0.0072821686044335365, "comparison": "reference outputs have the declared shapes and dtypes and are finite; the contest publishes no engine outputs to compare against"}} +{"uuid": "a01a3f93-19b0-4b12-95e3-6132a41d628e", "definition": "gdn_prefill_qk4_v8_d128_k_last", "axes": {"total_seq_len": 2284, "num_seqs": 3, "len_cu_seqlens": 4}, "source": "https://huggingface.co/datasets/flashinfer-ai/mlsys26-contest/tree/5e832ce88dd1013032b22a0e942979d7d2769cc3", "source_workload": "a01a3f93-19b0-4b12-95e3-6132a41d628e", "model": "Qwen3-Next (TP=4), as recorded by the MLSys 2026 FlashInfer contest", "adapter": "Imported unchanged from the MLSys 2026 FlashInfer contest dataset; each input tensor is stored in its own content-addressed file. The contest publishes no engine outputs.", "validation": {"uuid": "a01a3f93-19b0-4b12-95e3-6132a41d628e", "definition": "gdn_prefill_qk4_v8_d128_k_last", "axes": {"total_seq_len": 2284, "num_seqs": 3, "len_cu_seqlens": 4}, "status": "passed", "device": "cuda", "torch": "2.14.1+cu130", "seconds": 0.34308723639696836, "comparison": "reference outputs have the declared shapes and dtypes and are finite; the contest publishes no engine outputs to compare against"}} +{"uuid": "cc241d2e-f8b7-448f-95ec-1d5d2809c068", "definition": "gdn_prefill_qk4_v8_d128_k_last", "axes": {"total_seq_len": 23, "num_seqs": 1, "len_cu_seqlens": 2}, "source": "https://huggingface.co/datasets/flashinfer-ai/mlsys26-contest/tree/5e832ce88dd1013032b22a0e942979d7d2769cc3", "source_workload": "cc241d2e-f8b7-448f-95ec-1d5d2809c068", "model": "Qwen3-Next (TP=4), as recorded by the MLSys 2026 FlashInfer contest", "adapter": "Imported unchanged from the MLSys 2026 FlashInfer contest dataset; each input tensor is stored in its own content-addressed file. The contest publishes no engine outputs.", "validation": {"uuid": "cc241d2e-f8b7-448f-95ec-1d5d2809c068", "definition": "gdn_prefill_qk4_v8_d128_k_last", "axes": {"total_seq_len": 23, "num_seqs": 1, "len_cu_seqlens": 2}, "status": "passed", "device": "cuda", "torch": "2.14.1+cu130", "seconds": 0.004298948682844639, "comparison": "reference outputs have the declared shapes and dtypes and are finite; the contest publishes no engine outputs to compare against"}} diff --git a/definitions/dense_attention/noncausal_dense_attention_h32_d128.json b/definitions/dense_attention/noncausal_dense_attention_h32_d128.json index d71ebbf7457f21e6af8b0fc2bc9e210df138bdc6..398bc495d5f0786239665f47530e54d4530bef38 100644 --- a/definitions/dense_attention/noncausal_dense_attention_h32_d128.json +++ b/definitions/dense_attention/noncausal_dense_attention_h32_d128.json @@ -1,7 +1,7 @@ { "name": "noncausal_dense_attention_h32_d128", "op_type": "dense_attention", - "description": "Noncausal self/cross attention with FP32 accumulation and BF16 output. Self attention uses Nq=Nk; cross attention allows unequal lengths. No dropout. Projection, normalization, rotary embeddings and output gates are outside the definition.", + "description": "Noncausal self/cross attention with FP32 accumulation and BF16 output. Self attention uses Nq=Nk; cross attention allows unequal lengths. No dropout. Projection, normalization, rotary embeddings and output gates are outside the definition. No mask: every captured call's expanded visibility mask was all True (on one GPU the engine passes no mask, or an all-visible prompt mask), so KDA drops the dataset's mask input.", "tags": [ "model:ltx-2.5", "status:draft", @@ -57,16 +57,6 @@ ], "dtype": "bfloat16" }, - "mask": { - "shape": [ - "B", - "H", - "Nq", - "Nk" - ], - "dtype": "bool", - "description": "Expanded visibility mask. All True means no mask. Each query has a visible key." - }, "sm_scale": { "shape": null, "dtype": "float32", @@ -89,5 +79,5 @@ "Nq >= 1", "Nk >= 1" ], - "reference": "import math\nimport torch\n\n@torch.no_grad()\ndef run(Q, K, V, mask, sm_scale):\n \"\"\"Noncausal attention; the explicit boolean mask uses True for visibility.\"\"\"\n assert bool(mask.any(dim=-1).all()), \"Each query needs a visible key\"\n scores = torch.einsum(\"bqhd,bkhd->bhqk\", Q.float(), K.float())\n scores = (scores * float(sm_scale)).masked_fill(~mask, -torch.inf)\n probabilities = torch.softmax(scores, dim=-1)\n return torch.einsum(\"bhqk,bkhd->bqhd\", probabilities, V.float()).to(torch.bfloat16)\n" + "reference": "import math\nimport torch\n\n@torch.no_grad()\ndef run(Q, K, V, sm_scale):\n \"\"\"Noncausal attention without a mask.\"\"\"\n scores = torch.einsum(\"bqhd,bkhd->bhqk\", Q.float(), K.float())\n scores = scores * float(sm_scale)\n probabilities = torch.softmax(scores, dim=-1)\n return torch.einsum(\"bhqk,bkhd->bqhd\", probabilities, V.float()).to(torch.bfloat16)\n" } diff --git a/definitions/dense_attention/noncausal_dense_attention_h32_d64.json b/definitions/dense_attention/noncausal_dense_attention_h32_d64.json index 398139b801fe35e1a62e43a87d44943452bdd186..40bf10ce999a71a4a471f5c80b764c70afadc778 100644 --- a/definitions/dense_attention/noncausal_dense_attention_h32_d64.json +++ b/definitions/dense_attention/noncausal_dense_attention_h32_d64.json @@ -1,7 +1,7 @@ { "name": "noncausal_dense_attention_h32_d64", "op_type": "dense_attention", - "description": "Noncausal self/cross attention with FP32 accumulation and BF16 output. Self attention uses Nq=Nk; cross attention allows unequal lengths. No dropout. Projection, normalization, rotary embeddings and output gates are outside the definition.", + "description": "Noncausal self/cross attention with FP32 accumulation and BF16 output. Self attention uses Nq=Nk; cross attention allows unequal lengths. No dropout. Projection, normalization, rotary embeddings and output gates are outside the definition. No mask: every captured call's expanded visibility mask was all True (on one GPU the engine passes no mask, or an all-visible prompt mask), so KDA drops the dataset's mask input.", "tags": [ "model:ltx-2.5", "status:draft", @@ -57,16 +57,6 @@ ], "dtype": "bfloat16" }, - "mask": { - "shape": [ - "B", - "H", - "Nq", - "Nk" - ], - "dtype": "bool", - "description": "Expanded visibility mask. All True means no mask. Each query has a visible key." - }, "sm_scale": { "shape": null, "dtype": "float32", @@ -89,5 +79,5 @@ "Nq >= 1", "Nk >= 1" ], - "reference": "import math\nimport torch\n\n@torch.no_grad()\ndef run(Q, K, V, mask, sm_scale):\n \"\"\"Noncausal attention; the explicit boolean mask uses True for visibility.\"\"\"\n assert bool(mask.any(dim=-1).all()), \"Each query needs a visible key\"\n scores = torch.einsum(\"bqhd,bkhd->bhqk\", Q.float(), K.float())\n scores = (scores * float(sm_scale)).masked_fill(~mask, -torch.inf)\n probabilities = torch.softmax(scores, dim=-1)\n return torch.einsum(\"bhqk,bkhd->bqhd\", probabilities, V.float()).to(torch.bfloat16)\n" + "reference": "import math\nimport torch\n\n@torch.no_grad()\ndef run(Q, K, V, sm_scale):\n \"\"\"Noncausal attention without a mask.\"\"\"\n scores = torch.einsum(\"bqhd,bkhd->bhqk\", Q.float(), K.float())\n scores = scores * float(sm_scale)\n probabilities = torch.softmax(scores, dim=-1)\n return torch.einsum(\"bhqk,bkhd->bqhd\", probabilities, V.float()).to(torch.bfloat16)\n" } diff --git a/definitions/gdn/gated_delta_rule_decode_h48_dk128_dv128.json b/definitions/gdn/gated_delta_rule_decode_h48_dk128_dv128.json deleted file mode 100644 index 4aae0fbf8ad3da801bfcd544c7cb20c4bc708eab..0000000000000000000000000000000000000000 --- a/definitions/gdn/gated_delta_rule_decode_h48_dk128_dv128.json +++ /dev/null @@ -1,132 +0,0 @@ -{ - "name": "gated_delta_rule_decode_h48_dk128_dv128", - "op_type": "gdn", - "description": "Serving GDN single-token decode with raw 16-head Q/K, 48 value heads, fused FP32 L2 normalization (epsilon 1e-6), softplus decay and sigmoid update gate. The update gate is rounded to BF16 as in SGLang Triton packed decode. State uses [B,H,K,V]. Raw model tensors are retained rather than rounding the kernel-internal normalized Q/K to BF16.", - "tags": [ - "model:qwen3.8-flash-next", - "status:draft", - "parallelism:unsharded", - "stage:decode" - ], - "axes": { - "B": { - "type": "var", - "description": "Runtime batch size." - }, - "T": { - "type": "const", - "value": 1 - }, - "Hq": { - "type": "const", - "value": 16 - }, - "H": { - "type": "const", - "value": 48 - }, - "Dk": { - "type": "const", - "value": 128 - }, - "Dv": { - "type": "const", - "value": 128 - } - }, - "inputs": { - "Q": { - "shape": [ - "B", - "T", - "Hq", - "Dk" - ], - "dtype": "bfloat16" - }, - "K": { - "shape": [ - "B", - "T", - "Hq", - "Dk" - ], - "dtype": "bfloat16" - }, - "V": { - "shape": [ - "B", - "T", - "H", - "Dv" - ], - "dtype": "bfloat16" - }, - "a": { - "shape": [ - "B", - "T", - "H" - ], - "dtype": "bfloat16" - }, - "b": { - "shape": [ - "B", - "T", - "H" - ], - "dtype": "bfloat16" - }, - "A_log": { - "shape": [ - "H" - ], - "dtype": "float32" - }, - "dt_bias": { - "shape": [ - "H" - ], - "dtype": "bfloat16" - }, - "S0": { - "shape": [ - "B", - "H", - "Dk", - "Dv" - ], - "dtype": "float32" - }, - "q_scale": { - "shape": null, - "dtype": "float32", - "description": "Model default 1/sqrt(128)." - } - }, - "outputs": { - "O": { - "shape": [ - "B", - "T", - "H", - "Dv" - ], - "dtype": "bfloat16" - }, - "S_final": { - "shape": [ - "B", - "H", - "Dk", - "Dv" - ], - "dtype": "float32" - } - }, - "constraints": [ - "B >= 1" - ], - "reference": "import math\nimport torch\n\n@torch.no_grad()\ndef gated_delta(Q, K, V, beta, g, S0, q_scale):\n \"\"\"State is [B,H,Dk,Dv]; Q/K are already normalized and head-aligned.\"\"\"\n state = S0.float().clone()\n output = torch.empty_like(V)\n q, k, v = Q.float(), K.float(), V.float()\n for t in range(Q.shape[1]):\n state = state * torch.exp(g[:, t].float())[..., None, None]\n prediction = torch.einsum(\"bhk,bhkv->bhv\", k[:, t], state)\n delta = beta[:, t].float()[..., None] * (v[:, t] - prediction)\n state = state + k[:, t, :, :, None] * delta[..., None, :]\n output[:, t] = (\n torch.einsum(\"bhk,bhkv->bhv\", q[:, t] * float(q_scale), state)\n ).to(torch.bfloat16)\n return output, state\n\n\n@torch.no_grad()\ndef run(Q, K, V, a, b, A_log, dt_bias, S0, q_scale):\n \"\"\"The serving decode kernel consumes raw Q/K and fuses gate production.\"\"\"\n q, k = Q.float(), K.float()\n q = q / torch.sqrt(q.square().sum(-1, keepdim=True) + 1e-6)\n k = k / torch.sqrt(k.square().sum(-1, keepdim=True) + 1e-6)\n q = q.repeat_interleave(V.shape[2] // Q.shape[2], dim=2)\n k = k.repeat_interleave(V.shape[2] // K.shape[2], dim=2)\n x = a.float() + dt_bias.float()\n g = -A_log.float().exp() * torch.nn.functional.softplus(x, beta=1.0, threshold=20.0)\n # Triton rounds sigmoid(b) back to b's source dtype before the update.\n beta = b.float().sigmoid().to(b.dtype).float()\n return gated_delta(q, k, V, beta, g, S0, q_scale)\n" -} diff --git a/definitions/gdn/gated_delta_rule_prefill_h48_dk128_dv128.json b/definitions/gdn/gated_delta_rule_prefill_h48_dk128_dv128.json deleted file mode 100644 index f9fd9f37c8ad569e75ccbacdbca2ac9b7b82566d..0000000000000000000000000000000000000000 --- a/definitions/gdn/gated_delta_rule_prefill_h48_dk128_dv128.json +++ /dev/null @@ -1,120 +0,0 @@ -{ - "name": "gated_delta_rule_prefill_h48_dk128_dv128", - "op_type": "gdn", - "description": "Gated Delta Network recurrence with decay before delta and readout after update. Unsharded value-head count 48; the original 16 Q/K heads are already repeated 3 times. Q/K L2 normalization and gate production are outside this definition. State uses [B,H,K,V], not the contest k-last layout. Chunked prefill must implement the same recurrence.", - "tags": [ - "model:qwen3.8-flash-next", - "status:draft", - "parallelism:unsharded", - "stage:prefill" - ], - "axes": { - "B": { - "type": "var", - "description": "Runtime batch size." - }, - "T": { - "type": "var", - "description": "Runtime sequence length." - }, - "H": { - "type": "const", - "value": 48 - }, - "Dk": { - "type": "const", - "value": 128 - }, - "Dv": { - "type": "const", - "value": 128 - } - }, - "inputs": { - "Q": { - "shape": [ - "B", - "T", - "H", - "Dk" - ], - "dtype": "bfloat16" - }, - "K": { - "shape": [ - "B", - "T", - "H", - "Dk" - ], - "dtype": "bfloat16" - }, - "V": { - "shape": [ - "B", - "T", - "H", - "Dv" - ], - "dtype": "bfloat16" - }, - "beta": { - "shape": [ - "B", - "T", - "H" - ], - "dtype": "float32", - "description": "Update gate in [0,1]." - }, - "g": { - "shape": [ - "B", - "T", - "H" - ], - "dtype": "float32", - "description": "Natural-log decay, nonpositive." - }, - "S0": { - "shape": [ - "B", - "H", - "Dk", - "Dv" - ], - "dtype": "float32", - "description": "Initial state; supply zeros for a fresh sequence." - }, - "q_scale": { - "shape": null, - "dtype": "float32", - "description": "Model default 1/sqrt(128)." - } - }, - "outputs": { - "O": { - "shape": [ - "B", - "T", - "H", - "Dv" - ], - "dtype": "bfloat16" - }, - "S_final": { - "shape": [ - "B", - "H", - "Dk", - "Dv" - ], - "dtype": "float32" - } - }, - "constraints": [ - "B >= 1", - "T >= 1" - ], - "reference": "import math\nimport torch\n\n@torch.no_grad()\ndef run(Q, K, V, beta, g, S0, q_scale):\n \"\"\"State is [B,H,Dk,Dv]; Q/K are already normalized and head-aligned.\"\"\"\n state = S0.float().clone()\n output = torch.empty_like(V)\n q, k, v = Q.float(), K.float(), V.float()\n for t in range(Q.shape[1]):\n state = state * torch.exp(g[:, t].float())[..., None, None]\n prediction = torch.einsum(\"bhk,bhkv->bhv\", k[:, t], state)\n delta = beta[:, t].float()[..., None] * (v[:, t] - prediction)\n state = state + k[:, t, :, :, None] * delta[..., None, :]\n output[:, t] = (\n torch.einsum(\"bhk,bhkv->bhv\", q[:, t] * float(q_scale), state)\n ).to(torch.bfloat16)\n return output, state\n" -} diff --git a/definitions/gdn/gdn_decode_qk4_v8_d128_k_last.json b/definitions/gdn/gdn_decode_qk4_v8_d128_k_last.json new file mode 100644 index 0000000000000000000000000000000000000000..a63be8dd10570684f8092fba3ea30fb633d00b62 --- /dev/null +++ b/definitions/gdn/gdn_decode_qk4_v8_d128_k_last.json @@ -0,0 +1,149 @@ +{ + "name": "gdn_decode_qk4_v8_d128_k_last", + "description": "Gated Delta Net decode with GVA configuration and k-last state layout. Single-token generation with recurrent state update. Captured from Qwen3 Next linear attention layers (TP=4).", + "op_type": "gdn", + "tags": [ + "stage:decode", + "status:verified", + "model:qwen3-next", + "layout:k-last" + ], + "axes": { + "batch_size": { + "type": "var", + "description": "Number of sequences being decoded concurrently." + }, + "seq_len": { + "type": "const", + "value": 1, + "description": "Sequence length (always 1 for single-token decode)." + }, + "num_q_heads": { + "type": "const", + "value": 4, + "description": "Number of query heads (same as key heads in GVA mode, TP=4, 16/4=4)." + }, + "num_k_heads": { + "type": "const", + "value": 4, + "description": "Number of key heads (TP=4, 16/4=4)." + }, + "num_v_heads": { + "type": "const", + "value": 8, + "description": "Number of value heads (GVA: more value heads than query heads, TP=4, 32/4=8)." + }, + "head_size": { + "type": "const", + "value": 128 + } + }, + "constraints": [ + "num_v_heads >= num_q_heads", + "num_v_heads % num_q_heads == 0", + "num_k_heads == num_q_heads" + ], + "inputs": { + "q": { + "shape": [ + "batch_size", + "seq_len", + "num_q_heads", + "head_size" + ], + "dtype": "bfloat16", + "description": "Query tensor for single token decode." + }, + "k": { + "shape": [ + "batch_size", + "seq_len", + "num_k_heads", + "head_size" + ], + "dtype": "bfloat16", + "description": "Key tensor for single token decode." + }, + "v": { + "shape": [ + "batch_size", + "seq_len", + "num_v_heads", + "head_size" + ], + "dtype": "bfloat16", + "description": "Value tensor for single token decode." + }, + "state": { + "shape": [ + "batch_size", + "num_v_heads", + "head_size", + "head_size" + ], + "dtype": "float32", + "description": "Recurrent state in k-last layout [B, H, V, K].", + "optional": true + }, + "A_log": { + "shape": [ + "num_v_heads" + ], + "dtype": "float32", + "description": "Log decay parameter (learnable). Used to compute g = exp(-exp(A_log) * softplus(a + dt_bias))." + }, + "a": { + "shape": [ + "batch_size", + "seq_len", + "num_v_heads" + ], + "dtype": "bfloat16", + "description": "Input-dependent decay from projection." + }, + "dt_bias": { + "shape": [ + "num_v_heads" + ], + "dtype": "float32", + "description": "Decay bias (learnable). Added to 'a' before softplus." + }, + "b": { + "shape": [ + "batch_size", + "seq_len", + "num_v_heads" + ], + "dtype": "bfloat16", + "description": "Update gate input from projection. beta = sigmoid(b)." + }, + "scale": { + "shape": null, + "dtype": "float32", + "description": "Scale factor. Default is 1/sqrt(head_size)." + } + }, + "outputs": { + "output": { + "shape": [ + "batch_size", + "seq_len", + "num_v_heads", + "head_size" + ], + "dtype": "bfloat16", + "description": "Attention output. Shape follows num_v_heads in GVA mode." + }, + "new_state": { + "shape": [ + "batch_size", + "num_v_heads", + "head_size", + "head_size" + ], + "dtype": "float32", + "description": "Updated recurrent state in k-last layout [B, H, V, K]." + } + }, + "reference": "import math\nimport torch\nimport torch.nn.functional as F\n\n\ndef matmul(a: torch.Tensor, b: torch.Tensor):\n \"\"\"Float32 matmul for numerical stability.\"\"\"\n return a.float() @ b.float()\n\n\n@torch.no_grad()\ndef run(q, k, v, state, A_log, a, dt_bias, b, scale):\n \"\"\"\n Gated Delta Net decode reference implementation (k-last layout).\n \n State layout: [B, H, V, K] (k-last, K dimension at the end)\n \n Gate computation:\n g = exp(-exp(A_log) * softplus(a + dt_bias))\n beta = sigmoid(b)\n \n Delta rule update:\n state_new = g * state_old + k^T @ (beta * v + (1-beta) * k @ state_old) - k^T @ (k @ state_old)\n output = scale * q @ state_new\n \"\"\"\n B, T, num_q_heads, K = q.shape\n _, _, num_k_heads, _ = k.shape\n _, _, num_v_heads, V = v.shape\n num_heads = num_v_heads\n device = q.device\n \n assert num_q_heads == 4\n assert num_k_heads == 4\n assert num_v_heads == 8\n assert K == 128 and V == 128\n assert T == 1\n \n if scale is None or scale == 0.0:\n scale = 1.0 / math.sqrt(K)\n \n # Compute g and beta from raw parameters\n x = a.float() + dt_bias.float() # [B, 1, HV]\n g = torch.exp(-torch.exp(A_log.float()) * F.softplus(x)) # [B, 1, HV]\n beta = torch.sigmoid(b.float()) # [B, 1, HV]\n \n q_f32 = q.squeeze(1).float()\n k_f32 = k.squeeze(1).float()\n v_f32 = v.squeeze(1).float()\n g_f32 = g.squeeze(1).float()\n beta_f32 = beta.squeeze(1).float()\n \n if state is not None:\n state_f32 = state.float()\n else:\n state_f32 = torch.zeros(B, num_heads, V, K, dtype=torch.float32, device=device)\n \n q_exp = q_f32.repeat_interleave(num_v_heads // num_q_heads, dim=1)\n k_exp = k_f32.repeat_interleave(num_v_heads // num_k_heads, dim=1)\n \n new_state = torch.zeros_like(state_f32)\n output = torch.zeros(B, num_heads, V, dtype=torch.float32, device=device)\n \n for b_idx in range(B):\n for h_idx in range(num_heads):\n q_h = q_exp[b_idx, h_idx]\n k_h = k_exp[b_idx, h_idx]\n v_h = v_f32[b_idx, h_idx]\n h_state = state_f32[b_idx, h_idx].clone().transpose(-1, -2) # [V,K] -> [K,V]\n g_val = g_f32[b_idx, h_idx]\n beta_val = beta_f32[b_idx, h_idx]\n \n old_state = g_val * h_state\n old_v = k_h @ old_state\n new_v = beta_val * v_h + (1 - beta_val) * old_v\n state_remove = k_h.unsqueeze(1) @ old_v.unsqueeze(0)\n state_update = k_h.unsqueeze(1) @ new_v.unsqueeze(0)\n h_state = old_state - state_remove + state_update\n \n output[b_idx, h_idx] = scale * (q_h @ h_state)\n new_state[b_idx, h_idx] = h_state.transpose(-1, -2) # [K,V] -> [V,K]\n \n output = output.unsqueeze(1).to(torch.bfloat16)\n return output, new_state" +} diff --git a/definitions/gdn/gdn_prefill_qk4_v8_d128_k_last.json b/definitions/gdn/gdn_prefill_qk4_v8_d128_k_last.json new file mode 100644 index 0000000000000000000000000000000000000000..c225ecb36bef42fb2806611befeaa8a9d3dfe2a7 --- /dev/null +++ b/definitions/gdn/gdn_prefill_qk4_v8_d128_k_last.json @@ -0,0 +1,150 @@ +{ + "name": "gdn_prefill_qk4_v8_d128_k_last", + "description": "Gated Delta Net prefill with GVA configuration and k-last state layout. The state is in k-last layout [N, H, V, K]. Captured from Qwen3 Next linear attention layers (TP=4).", + "op_type": "gdn", + "tags": [ + "stage:prefill", + "status:verified", + "model:qwen3-next", + "layout:k-last" + ], + "axes": { + "total_seq_len": { + "type": "var" + }, + "num_seqs": { + "type": "var" + }, + "num_q_heads": { + "type": "const", + "value": 4, + "description": "Number of query heads (same as key heads in GVA mode, TP=4, 16/4=4)." + }, + "num_k_heads": { + "type": "const", + "value": 4, + "description": "Number of key heads (TP=4, 16/4=4)." + }, + "num_v_heads": { + "type": "const", + "value": 8, + "description": "Number of value heads (GVA: more value heads than query heads, TP=4, 32/4=8)." + }, + "head_size": { + "type": "const", + "value": 128 + }, + "len_cu_seqlens": { + "type": "var", + "description": "Length of cu_seqlens array (num_seqs + 1)." + } + }, + "constraints": [ + "len_cu_seqlens == num_seqs + 1", + "total_seq_len == cu_seqlens[-1].item()" + ], + "inputs": { + "q": { + "shape": [ + "total_seq_len", + "num_q_heads", + "head_size" + ], + "dtype": "bfloat16", + "description": "Query tensor." + }, + "k": { + "shape": [ + "total_seq_len", + "num_k_heads", + "head_size" + ], + "dtype": "bfloat16", + "description": "Key tensor." + }, + "v": { + "shape": [ + "total_seq_len", + "num_v_heads", + "head_size" + ], + "dtype": "bfloat16", + "description": "Value tensor." + }, + "state": { + "shape": [ + "num_seqs", + "num_v_heads", + "head_size", + "head_size" + ], + "dtype": "float32", + "description": "Recurrent state in k-last layout [N, H, V, K].", + "optional": true + }, + "A_log": { + "shape": [ + "num_v_heads" + ], + "dtype": "float32", + "description": "Log decay parameter (learnable). Used to compute g = exp(-exp(A_log) * softplus(a + dt_bias))." + }, + "a": { + "shape": [ + "total_seq_len", + "num_v_heads" + ], + "dtype": "bfloat16", + "description": "Input-dependent decay from projection." + }, + "dt_bias": { + "shape": [ + "num_v_heads" + ], + "dtype": "float32", + "description": "Decay bias (learnable). Added to 'a' before softplus." + }, + "b": { + "shape": [ + "total_seq_len", + "num_v_heads" + ], + "dtype": "bfloat16", + "description": "Update gate input from projection. beta = sigmoid(b)." + }, + "cu_seqlens": { + "shape": [ + "len_cu_seqlens" + ], + "dtype": "int64", + "description": "Cumulative sequence lengths for variable-length batching." + }, + "scale": { + "shape": null, + "dtype": "float32", + "description": "Scale factor. Default is 1/sqrt(head_size)." + } + }, + "outputs": { + "output": { + "shape": [ + "total_seq_len", + "num_v_heads", + "head_size" + ], + "dtype": "bfloat16", + "description": "Attention output. Shape follows num_v_heads in GVA mode." + }, + "new_state": { + "shape": [ + "num_seqs", + "num_v_heads", + "head_size", + "head_size" + ], + "dtype": "float32", + "description": "Updated recurrent state in k-last layout [N, H, V, K]." + } + }, + "reference": "import math\nimport torch\nimport torch.nn.functional as F\n\n\ndef matmul(a: torch.Tensor, b: torch.Tensor):\n \"\"\"Float32 matmul for numerical stability.\"\"\"\n return a.float() @ b.float()\n\n\n@torch.no_grad()\ndef run(q, k, v, state, A_log, a, dt_bias, b, cu_seqlens, scale):\n \"\"\"\n Gated Delta Net prefill reference implementation (k-last layout).\n \n State layout: [H, V, K] (k-last, K dimension at the end)\n \n Gate computation:\n g = exp(-exp(A_log) * softplus(a + dt_bias))\n beta = sigmoid(b)\n \n Delta rule update:\n state_new = g * state_old + k^T @ (beta * v + (1-beta) * k @ state_old) - k^T @ (k @ state_old)\n output = scale * q @ state_new\n \"\"\"\n total_seq_len, num_q_heads, head_size = q.shape\n num_v_heads = v.shape[1]\n num_k_heads = k.shape[1]\n num_sab_heads = max(num_q_heads, num_v_heads)\n num_seqs = cu_seqlens.size(0) - 1\n device = q.device\n\n assert num_q_heads == 4\n assert num_k_heads == 4\n assert num_v_heads == 8\n assert head_size == 128\n\n if scale is None or scale == 0.0:\n scale = 1.0 / math.sqrt(head_size)\n\n # Compute g and beta from raw parameters\n x = a.float() + dt_bias.float() # [total_seq_len, HV]\n g = torch.exp(-torch.exp(A_log.float()) * F.softplus(x)) # [total_seq_len, HV]\n beta = torch.sigmoid(b.float()) # [total_seq_len, HV]\n\n q_exp = q.repeat_interleave(num_v_heads // num_q_heads, dim=1)\n k_exp = k.repeat_interleave(num_v_heads // num_k_heads, dim=1)\n\n output = torch.zeros(\n (total_seq_len, num_sab_heads, head_size), dtype=torch.bfloat16, device=device\n )\n new_state = torch.zeros(\n (num_seqs, num_sab_heads, head_size, head_size), dtype=torch.float32, device=device\n )\n\n for seq_idx in range(num_seqs):\n seq_start = int(cu_seqlens[seq_idx].item())\n seq_end = int(cu_seqlens[seq_idx + 1].item())\n seq_len = seq_end - seq_start\n\n if seq_len <= 0:\n continue\n\n if state is not None:\n state_HKV = state[seq_idx].clone().float().transpose(-1, -2) # [H,V,K] -> [H,K,V]\n else:\n state_HKV = torch.zeros(\n (num_sab_heads, head_size, head_size), dtype=torch.float32, device=device\n )\n\n for i in range(seq_len):\n t = seq_start + i\n q_H1K = q_exp[t].unsqueeze(1).float()\n k_H1K = k_exp[t].unsqueeze(1).float()\n v_H1V = v[t].unsqueeze(1).float()\n g_H11 = g[t].unsqueeze(1).unsqueeze(2)\n beta_H11 = beta[t].unsqueeze(1).unsqueeze(2)\n\n old_state_HKV = g_H11 * state_HKV\n old_v_H1V = matmul(k_H1K, old_state_HKV)\n new_v_H1V = beta_H11 * v_H1V + (1 - beta_H11) * old_v_H1V\n state_remove = torch.einsum('hkl,hlv->hkv', k_H1K.transpose(-1, -2), old_v_H1V)\n state_update = torch.einsum('hkl,hlv->hkv', k_H1K.transpose(-1, -2), new_v_H1V)\n state_HKV = old_state_HKV - state_remove + state_update\n\n o_H1V = scale * matmul(q_H1K, state_HKV)\n output[t] = o_H1V.squeeze(1).to(torch.bfloat16)\n\n new_state[seq_idx] = state_HKV.transpose(-1, -2) # [H,K,V] -> [H,V,K]\n\n return output, new_state" +} diff --git a/definitions/gemm/dense_gemm_bf16_nt_n4096_k64.json b/definitions/gemm/dense_gemm_bf16_nt_n4096_k64.json deleted file mode 100644 index 9814131d8e0b8b8eb0432f53ecbe2e3930f379fb..0000000000000000000000000000000000000000 --- a/definitions/gemm/dense_gemm_bf16_nt_n4096_k64.json +++ /dev/null @@ -1,53 +0,0 @@ -{ - "name": "dense_gemm_bf16_nt_n4096_k64", - "op_type": "gemm", - "description": "Independent A @ W.T with FP32 accumulation and BF16 output; image input projection. Contiguous row-major inputs. No bias, activation, residual or quantization.", - "tags": [ - "model:qwen-image-2.1-turbo", - "status:draft", - "parallelism:unsharded" - ], - "axes": { - "M": { - "type": "var", - "description": "Runtime number of token rows." - }, - "N": { - "type": "const", - "value": 4096 - }, - "K": { - "type": "const", - "value": 64 - } - }, - "inputs": { - "A": { - "shape": [ - "M", - "K" - ], - "dtype": "bfloat16" - }, - "W": { - "shape": [ - "N", - "K" - ], - "dtype": "bfloat16" - } - }, - "outputs": { - "C": { - "shape": [ - "M", - "N" - ], - "dtype": "bfloat16" - } - }, - "constraints": [ - "M >= 1" - ], - "reference": "import math\nimport torch\n\n@torch.no_grad()\ndef run(A, W):\n \"\"\"BF16 inputs, FP32 accumulation, one BF16 output rounding.\"\"\"\n return (A.float() @ W.float().T).to(torch.bfloat16)\n" -} diff --git a/definitions/gemm/dense_gemm_bf16_nt_n64_k4096.json b/definitions/gemm/dense_gemm_bf16_nt_n64_k4096.json deleted file mode 100644 index 196ef083b881e1145f6dbde9b7ac2445939867db..0000000000000000000000000000000000000000 --- a/definitions/gemm/dense_gemm_bf16_nt_n64_k4096.json +++ /dev/null @@ -1,53 +0,0 @@ -{ - "name": "dense_gemm_bf16_nt_n64_k4096", - "op_type": "gemm", - "description": "Independent A @ W.T with FP32 accumulation and BF16 output; image output projection. Contiguous row-major inputs. No bias, activation, residual or quantization.", - "tags": [ - "model:qwen-image-2.1-turbo", - "status:draft", - "parallelism:unsharded" - ], - "axes": { - "M": { - "type": "var", - "description": "Runtime number of token rows." - }, - "N": { - "type": "const", - "value": 64 - }, - "K": { - "type": "const", - "value": 4096 - } - }, - "inputs": { - "A": { - "shape": [ - "M", - "K" - ], - "dtype": "bfloat16" - }, - "W": { - "shape": [ - "N", - "K" - ], - "dtype": "bfloat16" - } - }, - "outputs": { - "C": { - "shape": [ - "M", - "N" - ], - "dtype": "bfloat16" - } - }, - "constraints": [ - "M >= 1" - ], - "reference": "import math\nimport torch\n\n@torch.no_grad()\ndef run(A, W):\n \"\"\"BF16 inputs, FP32 accumulation, one BF16 output rounding.\"\"\"\n return (A.float() @ W.float().T).to(torch.bfloat16)\n" -} diff --git a/definitions/grouped_gemm/grouped_gemm_fp8_fp4_e384_n2304_k5120_g32.json b/definitions/grouped_gemm/grouped_gemm_fp8_fp4_e384_n2304_k5120_g32.json deleted file mode 100644 index 6ac7b7b54a7c515be6bb4132856cead9b430c1e8..0000000000000000000000000000000000000000 --- a/definitions/grouped_gemm/grouped_gemm_fp8_fp4_e384_n2304_k5120_g32.json +++ /dev/null @@ -1,97 +0,0 @@ -{ - "name": "grouped_gemm_fp8_fp4_e384_n2304_k5120_g32", - "op_type": "grouped_gemm", - "description": "Grouped E4M3 activation x packed E2M1 weight GEMM, separate gate or up projection. Scale groups cover 32 consecutive K values. Logical unpacked scale layout, no backend swizzle. Input rows are already routed/permuted; no activation, routing weights or scatter.", - "tags": [ - "model:deepseek-v4.1-flash", - "status:draft", - "parallelism:unsharded" - ], - "axes": { - "M": { - "type": "var", - "description": "Runtime number of token rows." - }, - "E": { - "type": "const", - "value": 384 - }, - "N": { - "type": "const", - "value": 2304 - }, - "K": { - "type": "const", - "value": 5120 - }, - "K_packed": { - "type": "const", - "value": 2560 - }, - "K_groups": { - "type": "const", - "value": 160 - }, - "group_size": { - "type": "const", - "value": 32 - } - }, - "inputs": { - "Aq": { - "shape": [ - "M", - "K" - ], - "dtype": "float8_e4m3fn" - }, - "Wq_packed": { - "shape": [ - "E", - "N", - "K_packed" - ], - "dtype": "int8", - "description": "Raw FP4 byte carrier; even K is the low nibble." - }, - "scale_A": { - "shape": [ - "M", - "K_groups" - ], - "dtype": "int8", - "description": "Raw E8M0 exponent byte carrier, not signed numeric scales." - }, - "scale_W": { - "shape": [ - "E", - "N", - "K_groups" - ], - "dtype": "int8", - "description": "Raw E8M0 exponent byte carrier, not signed numeric scales." - }, - "expert_id": { - "shape": [ - "M" - ], - "dtype": "int32", - "description": "Nondecreasing expert IDs in [0,384); empty experts are allowed." - } - }, - "outputs": { - "Y": { - "shape": [ - "M", - "N" - ], - "dtype": "bfloat16" - } - }, - "constraints": [ - "M >= 1", - "K == 2 * K_packed", - "K == group_size * K_groups" - ], - "reference": "import math\nimport torch\n\ndef unpack_e2m1(packed):\n \"\"\"Decode low-nibble-first FP4 bytes without interpreting int8 numerically.\"\"\"\n raw = packed.to(torch.int16) & 255\n codes = torch.stack((raw & 15, raw >> 4), dim=-1).flatten(-2)\n table = torch.tensor(\n [0.0, 0.5, 1.0, 1.5, 2.0, 3.0, 4.0, 6.0],\n dtype=torch.float32, device=packed.device,\n )\n return table[(codes & 7).long()] * torch.where((codes & 8) == 0, 1.0, -1.0)\n\n\ndef decode_e8m0(encoded):\n \"\"\"E8M0 raw exponent bytes: 0..254 mean 2**(byte-127); 255 is invalid.\"\"\"\n raw = encoded.to(torch.int32) & 255\n assert bool((raw < 255).all()), \"E8M0 NaN scale is outside the contract\"\n return torch.ldexp(torch.ones_like(raw, dtype=torch.float32), raw - 127)\n\n\n@torch.no_grad()\ndef run(Aq, Wq_packed, scale_A, scale_W, expert_id):\n \"\"\"Rows are sorted by expert; routing and quantization are outside this op.\"\"\"\n m, k = Aq.shape\n experts, n, packed_k = Wq_packed.shape\n assert k == 2 * packed_k and k % 32 == 0\n assert bool(((expert_id >= 0) & (expert_id < experts)).all())\n assert bool((expert_id[1:] >= expert_id[:-1]).all())\n a = Aq.float() * decode_e8m0(scale_A).repeat_interleave(32, dim=-1)\n result = torch.empty((m, n), dtype=torch.bfloat16, device=Aq.device)\n for expert in torch.unique(expert_id).tolist():\n rows = torch.nonzero(expert_id == expert, as_tuple=True)[0]\n w = unpack_e2m1(Wq_packed[expert])\n w = w * decode_e8m0(scale_W[expert]).repeat_interleave(32, dim=-1)\n result[rows] = (a[rows] @ w.T).to(torch.bfloat16)\n return result\n" -} diff --git a/docs/shape-distributions/README.md b/docs/shape-distributions/README.md index be74e00a95e806a38ca3be1ca56a357382f76271..3bfd477a20ea5f2ee48ac3792b21e6753fa78d16 100644 --- a/docs/shape-distributions/README.md +++ b/docs/shape-distributions/README.md @@ -1,12 +1,12 @@ # Kernel shape distributions -**24 kernels, 1383 captured workloads.** Each histogram counts the workload records in one kernel definition's JSONL file. Every bar is one exact combination of its runtime dimensions; identical shapes are combined. The labels retain all runtime dimensions, including dimensions that happen to have one observed value. Model constants appear above each plot. +**21 kernels, 1104 captured workloads.** Each histogram counts the workload records in one kernel definition's JSONL file. Every bar is one exact combination of its runtime dimensions; identical shapes are combined. The labels retain all runtime dimensions, including dimensions that happen to have one observed value. Model constants appear above each plot. Read bar height (or length in horizontal plots) as the number of captured workloads with that shape. Bins are equally spaced categories, sorted by the dimension values, not continuous numeric intervals. A bar of 1 means one published example; a bar of 6 means six. These are capture counts, not request probabilities, runtime invocation frequencies, or AgentX traffic weights. Multi-dimensional shapes use horizontal bars to keep every dimension readable. Dimension names are explained below each plot; the linked definition specifies complete tensor layouts. -Regenerate from the repository root with Python and Matplotlib (rendered with 3.6.3): +Regenerate from the repository root with Python and Matplotlib (rendered with 3.11.2): ```bash python scripts/plot_shape_distributions.py @@ -20,14 +20,11 @@ Only definition and workload metadata are needed; tensor snapshots and a GPU are | [prefix_cached_block_causal_h32_d128_prefix0](#prefix_cached_block_causal_h32_d128_prefix0) | 12 | 4 | | [noncausal_dense_attention_h32_d128](#noncausal_dense_attention_h32_d128) | 54 | 18 | | [noncausal_dense_attention_h32_d64](#noncausal_dense_attention_h32_d64) | 108 | 30 | -| [gated_delta_rule_decode_h48_dk128_dv128](#gated_delta_rule_decode_h48_dk128_dv128) | 192 | 22 | -| [gated_delta_rule_prefill_h48_dk128_dv128](#gated_delta_rule_prefill_h48_dk128_dv128) | 65 | 42 | -| [dense_gemm_bf16_nt_n12288_k4096](#dense_gemm_bf16_nt_n12288_k4096) | 40 | 10 | -| [dense_gemm_bf16_nt_n4096_k12288](#dense_gemm_bf16_nt_n4096_k12288) | 40 | 10 | -| [dense_gemm_bf16_nt_n4096_k4096](#dense_gemm_bf16_nt_n4096_k4096) | 79 | 13 | -| [dense_gemm_bf16_nt_n4096_k64](#dense_gemm_bf16_nt_n4096_k64) | 30 | 6 | -| [dense_gemm_bf16_nt_n64_k4096](#dense_gemm_bf16_nt_n64_k4096) | 28 | 6 | -| [grouped_gemm_fp8_fp4_e384_n2304_k5120_g32](#grouped_gemm_fp8_fp4_e384_n2304_k5120_g32) | 52 | 11 | +| [gdn_decode_qk4_v8_d128_k_last](#gdn_decode_qk4_v8_d128_k_last) | 54 | 7 | +| [gdn_prefill_qk4_v8_d128_k_last](#gdn_prefill_qk4_v8_d128_k_last) | 100 | 77 | +| [dense_gemm_bf16_nt_n12288_k4096](#dense_gemm_bf16_nt_n12288_k4096) | 31 | 7 | +| [dense_gemm_bf16_nt_n4096_k12288](#dense_gemm_bf16_nt_n4096_k12288) | 31 | 7 | +| [dense_gemm_bf16_nt_n4096_k4096](#dense_gemm_bf16_nt_n4096_k4096) | 31 | 7 | | [grouped_gemm_fp8_fp4_e384_n4608_k5120_g32](#grouped_gemm_fp8_fp4_e384_n4608_k5120_g32) | 52 | 11 | | [grouped_gemm_fp8_fp4_e384_n5120_k2304_g32](#grouped_gemm_fp8_fp4_e384_n5120_k2304_g32) | 52 | 11 | | [mixed_mla_decode_deepseek41_h64_d512_k8128_k4512](#mixed_mla_decode_deepseek41_h64_d512_k8128_k4512) | 42 | 30 | @@ -73,27 +70,27 @@ Only definition and workload metadata are needed; tensor snapshots and a GPU are **Runtime dimensions:** `B`: Runtime batch size. `Nq`: Runtime query length. `Nk`: Runtime key/value length. -## gated_delta_rule_decode_h48_dk128_dv128 +## gdn_decode_qk4_v8_d128_k_last -[Definition](../../definitions/gdn/gated_delta_rule_decode_h48_dk128_dv128.json) · [Workloads](../../workloads/gdn/gated_delta_rule_decode_h48_dk128_dv128.jsonl) · [SVG](gated_delta_rule_decode_h48_dk128_dv128.svg) +[Definition](../../definitions/gdn/gdn_decode_qk4_v8_d128_k_last.json) · [Workloads](../../workloads/gdn/gdn_decode_qk4_v8_d128_k_last.jsonl) · [SVG](gdn_decode_qk4_v8_d128_k_last.svg) -![Shape distribution for gated_delta_rule_decode_h48_dk128_dv128: 192 workloads across 22 shapes](gated_delta_rule_decode_h48_dk128_dv128.svg) +![Shape distribution for gdn_decode_qk4_v8_d128_k_last: 54 workloads across 7 shapes](gdn_decode_qk4_v8_d128_k_last.svg) -**Runtime dimensions:** `B`: Runtime batch size. +**Runtime dimensions:** `batch_size`: Number of sequences being decoded concurrently. -## gated_delta_rule_prefill_h48_dk128_dv128 +## gdn_prefill_qk4_v8_d128_k_last -[Definition](../../definitions/gdn/gated_delta_rule_prefill_h48_dk128_dv128.json) · [Workloads](../../workloads/gdn/gated_delta_rule_prefill_h48_dk128_dv128.jsonl) · [SVG](gated_delta_rule_prefill_h48_dk128_dv128.svg) +[Definition](../../definitions/gdn/gdn_prefill_qk4_v8_d128_k_last.json) · [Workloads](../../workloads/gdn/gdn_prefill_qk4_v8_d128_k_last.jsonl) · [SVG](gdn_prefill_qk4_v8_d128_k_last.svg) -![Shape distribution for gated_delta_rule_prefill_h48_dk128_dv128: 65 workloads across 42 shapes](gated_delta_rule_prefill_h48_dk128_dv128.svg) +![Shape distribution for gdn_prefill_qk4_v8_d128_k_last: 100 workloads across 77 shapes](gdn_prefill_qk4_v8_d128_k_last.svg) -**Runtime dimensions:** `B`: Runtime batch size. `T`: Runtime sequence length. +**Runtime dimensions:** `total_seq_len`: total_seq_len `num_seqs`: num_seqs `len_cu_seqlens`: Length of cu_seqlens array (num_seqs + 1). ## dense_gemm_bf16_nt_n12288_k4096 [Definition](../../definitions/gemm/dense_gemm_bf16_nt_n12288_k4096.json) · [Workloads](../../workloads/gemm/dense_gemm_bf16_nt_n12288_k4096.jsonl) · [SVG](dense_gemm_bf16_nt_n12288_k4096.svg) -![Shape distribution for dense_gemm_bf16_nt_n12288_k4096: 40 workloads across 10 shapes](dense_gemm_bf16_nt_n12288_k4096.svg) +![Shape distribution for dense_gemm_bf16_nt_n12288_k4096: 31 workloads across 7 shapes](dense_gemm_bf16_nt_n12288_k4096.svg) **Runtime dimensions:** `M`: Runtime number of token rows. @@ -101,7 +98,7 @@ Only definition and workload metadata are needed; tensor snapshots and a GPU are [Definition](../../definitions/gemm/dense_gemm_bf16_nt_n4096_k12288.json) · [Workloads](../../workloads/gemm/dense_gemm_bf16_nt_n4096_k12288.jsonl) · [SVG](dense_gemm_bf16_nt_n4096_k12288.svg) -![Shape distribution for dense_gemm_bf16_nt_n4096_k12288: 40 workloads across 10 shapes](dense_gemm_bf16_nt_n4096_k12288.svg) +![Shape distribution for dense_gemm_bf16_nt_n4096_k12288: 31 workloads across 7 shapes](dense_gemm_bf16_nt_n4096_k12288.svg) **Runtime dimensions:** `M`: Runtime number of token rows. @@ -109,31 +106,7 @@ Only definition and workload metadata are needed; tensor snapshots and a GPU are [Definition](../../definitions/gemm/dense_gemm_bf16_nt_n4096_k4096.json) · [Workloads](../../workloads/gemm/dense_gemm_bf16_nt_n4096_k4096.jsonl) · [SVG](dense_gemm_bf16_nt_n4096_k4096.svg) -![Shape distribution for dense_gemm_bf16_nt_n4096_k4096: 79 workloads across 13 shapes](dense_gemm_bf16_nt_n4096_k4096.svg) - -**Runtime dimensions:** `M`: Runtime number of token rows. - -## dense_gemm_bf16_nt_n4096_k64 - -[Definition](../../definitions/gemm/dense_gemm_bf16_nt_n4096_k64.json) · [Workloads](../../workloads/gemm/dense_gemm_bf16_nt_n4096_k64.jsonl) · [SVG](dense_gemm_bf16_nt_n4096_k64.svg) - -![Shape distribution for dense_gemm_bf16_nt_n4096_k64: 30 workloads across 6 shapes](dense_gemm_bf16_nt_n4096_k64.svg) - -**Runtime dimensions:** `M`: Runtime number of token rows. - -## dense_gemm_bf16_nt_n64_k4096 - -[Definition](../../definitions/gemm/dense_gemm_bf16_nt_n64_k4096.json) · [Workloads](../../workloads/gemm/dense_gemm_bf16_nt_n64_k4096.jsonl) · [SVG](dense_gemm_bf16_nt_n64_k4096.svg) - -![Shape distribution for dense_gemm_bf16_nt_n64_k4096: 28 workloads across 6 shapes](dense_gemm_bf16_nt_n64_k4096.svg) - -**Runtime dimensions:** `M`: Runtime number of token rows. - -## grouped_gemm_fp8_fp4_e384_n2304_k5120_g32 - -[Definition](../../definitions/grouped_gemm/grouped_gemm_fp8_fp4_e384_n2304_k5120_g32.json) · [Workloads](../../workloads/grouped_gemm/grouped_gemm_fp8_fp4_e384_n2304_k5120_g32.jsonl) · [SVG](grouped_gemm_fp8_fp4_e384_n2304_k5120_g32.svg) - -![Shape distribution for grouped_gemm_fp8_fp4_e384_n2304_k5120_g32: 52 workloads across 11 shapes](grouped_gemm_fp8_fp4_e384_n2304_k5120_g32.svg) +![Shape distribution for dense_gemm_bf16_nt_n4096_k4096: 31 workloads across 7 shapes](dense_gemm_bf16_nt_n4096_k4096.svg) **Runtime dimensions:** `M`: Runtime number of token rows. diff --git a/docs/shape-distributions/dense_gemm_bf16_nt_n12288_k4096.svg b/docs/shape-distributions/dense_gemm_bf16_nt_n12288_k4096.svg index 8329bb5db03f65df06ef0da8a489370d4969e8f1..2d4491ecb0190dc2162e1b94ba2a3442e1a0029e 100644 --- a/docs/shape-distributions/dense_gemm_bf16_nt_n12288_k4096.svg +++ b/docs/shape-distributions/dense_gemm_bf16_nt_n12288_k4096.svg @@ -42,272 +42,221 @@ z - 25 + 4096 - 30 + 4125 - 32 + 6144 - 4096 + 8192 - 4125 + 12288 - 6144 + 16384 - 8192 + 24576 - - - - 12288 - - - - - - 16384 - - - - - - 24576 - - - + M — Runtime number of token rows - + - - + + 0 - + - - + + 2 - + - - + + 4 - + - - + + 6 - + - - + + 8 - + - - + + 10 - + Captured workloads (count) - - - - - - - - - - - - - - - - + - + + + 9 + + + 3 + + + 3 + - 3 + 6 - 3 + 2 - 3 + 6 - 9 - - - 3 - - - 3 - - - 6 - - - 2 - - - 6 - - - 2 + 2 - + Shape distribution - + dense_gemm_bf16_nt_n12288_k4096 - - 40 captured workloads | 10 distinct shapes + + 31 captured workloads | 7 distinct shapes - + Fixed dimensions: N=12288, K=4096 - + One bin per exact runtime shape; equal spacing. Counts describe this dataset, not production traffic. diff --git a/docs/shape-distributions/dense_gemm_bf16_nt_n4096_k12288.svg b/docs/shape-distributions/dense_gemm_bf16_nt_n4096_k12288.svg index ce0dc1988125209dabea390470e2b3d414b8f548..26c8e61c96f66f3cf95899fe22e2f58154554d9c 100644 --- a/docs/shape-distributions/dense_gemm_bf16_nt_n4096_k12288.svg +++ b/docs/shape-distributions/dense_gemm_bf16_nt_n4096_k12288.svg @@ -42,272 +42,221 @@ z - 25 + 4096 - 30 + 4125 - 32 + 6144 - 4096 + 8192 - 4125 + 12288 - 6144 + 16384 - 8192 + 24576 - - - - 12288 - - - - - - 16384 - - - - - - 24576 - - - + M — Runtime number of token rows - + - - + + 0 - + - - + + 2 - + - - + + 4 - + - - + + 6 - + - - + + 8 - + - - + + 10 - + Captured workloads (count) - - - - - - - - - - - - - - - - + - + + + 9 + + + 3 + + + 3 + - 3 + 6 - 3 + 2 - 3 + 6 - 9 - - - 3 - - - 3 - - - 6 - - - 2 - - - 6 - - - 2 + 2 - + Shape distribution - + dense_gemm_bf16_nt_n4096_k12288 - - 40 captured workloads | 10 distinct shapes + + 31 captured workloads | 7 distinct shapes - + Fixed dimensions: N=4096, K=12288 - + One bin per exact runtime shape; equal spacing. Counts describe this dataset, not production traffic. diff --git a/docs/shape-distributions/dense_gemm_bf16_nt_n4096_k4096.svg b/docs/shape-distributions/dense_gemm_bf16_nt_n4096_k4096.svg index e9d94241984a0d865f47855e6718b0d8f6e4a108..6b083b1e13b06331dd9218eb14093076f2583a0f 100644 --- a/docs/shape-distributions/dense_gemm_bf16_nt_n4096_k4096.svg +++ b/docs/shape-distributions/dense_gemm_bf16_nt_n4096_k4096.svg @@ -42,323 +42,221 @@ z - 1 + 4096 - 2 + 4125 - 4 + 6144 - 25 + 8192 - 30 + 12288 - 32 + 16384 - 4096 + 24576 - - - - 4125 - - - - - - 6144 - - - - - - 8192 - - - - - - 12288 - - - - - - 16384 - - - - - - 24576 - - - + M — Runtime number of token rows - + - - + + 0 - - + - - - 4 + + + 2 - - + - - - 8 + + + 4 - - + - - - 12 + + + 6 - - + - - - 16 + + + 8 - - + - - - 20 + + + 10 - + Captured workloads (count) - - - - - - - - - - - - - - - - - - - - - - - - - + - + - - 20 - - - 8 - - - 8 - - - 3 + + 9 - - 6 + + 3 - - 3 + + 3 - - 9 + + 6 - - 3 + + 2 - - 3 + + 6 - - 6 - - - 2 - - - 6 - - - 2 + + 2 - + Shape distribution - + dense_gemm_bf16_nt_n4096_k4096 - - 79 captured workloads | 13 distinct shapes + + 31 captured workloads | 7 distinct shapes - + Fixed dimensions: N=4096, K=4096 - + One bin per exact runtime shape; equal spacing. Counts describe this dataset, not production traffic. diff --git a/docs/shape-distributions/dense_gemm_bf16_nt_n4096_k64.svg b/docs/shape-distributions/dense_gemm_bf16_nt_n4096_k64.svg deleted file mode 100644 index ff3b0ac10248b580cbd6138f2c90da9ae712d1f1..0000000000000000000000000000000000000000 --- a/docs/shape-distributions/dense_gemm_bf16_nt_n4096_k64.svg +++ /dev/null @@ -1,262 +0,0 @@ - - - - Shape distribution: dense_gemm_bf16_nt_n4096_k64 - - - - - Shape distribution: dense_gemm_bf16_nt_n4096_k64 - image/svg+xml - - - Matplotlib v3.11.2, https://matplotlib.org/ - - - - - - - - - - - - - - - - - - - - - 4096 - - - - - - 6144 - - - - - - 8192 - - - - - - 12288 - - - - - - 16384 - - - - - - 24576 - - - - M — Runtime number of token rows - - - - - - - - - - 0 - - - - - - - - - 2 - - - - - - - - - 4 - - - - - - - - - 6 - - - - - - - - - 8 - - - - - - - - - 10 - - - - - - - - - 12 - - - - Captured workloads (count) - - - - - - - - - - - - - - - - - - - - - - - - - - - - 11 - - - 3 - - - 6 - - - 2 - - - 6 - - - 2 - - - - Shape distribution - - - dense_gemm_bf16_nt_n4096_k64 - - - 30 captured workloads | 6 distinct shapes - - - Fixed dimensions: N=4096, K=64 - - - One bin per exact runtime shape; equal spacing. Counts describe this dataset, not production traffic. - - - - - - - - diff --git a/docs/shape-distributions/dense_gemm_bf16_nt_n64_k4096.svg b/docs/shape-distributions/dense_gemm_bf16_nt_n64_k4096.svg deleted file mode 100644 index 015b4e19734f77b81516001cbcb33aad42293ffb..0000000000000000000000000000000000000000 --- a/docs/shape-distributions/dense_gemm_bf16_nt_n64_k4096.svg +++ /dev/null @@ -1,251 +0,0 @@ - - - - Shape distribution: dense_gemm_bf16_nt_n64_k4096 - - - - - Shape distribution: dense_gemm_bf16_nt_n64_k4096 - image/svg+xml - - - Matplotlib v3.11.2, https://matplotlib.org/ - - - - - - - - - - - - - - - - - - - - - 4096 - - - - - - 6144 - - - - - - 8192 - - - - - - 12288 - - - - - - 16384 - - - - - - 24576 - - - - M — Runtime number of token rows - - - - - - - - - - 0 - - - - - - - - - 2 - - - - - - - - - 4 - - - - - - - - - 6 - - - - - - - - - 8 - - - - - - - - - 10 - - - - Captured workloads (count) - - - - - - - - - - - - - - - - - - - - - - - - - - - - 9 - - - 3 - - - 6 - - - 2 - - - 6 - - - 2 - - - - Shape distribution - - - dense_gemm_bf16_nt_n64_k4096 - - - 28 captured workloads | 6 distinct shapes - - - Fixed dimensions: N=64, K=4096 - - - One bin per exact runtime shape; equal spacing. Counts describe this dataset, not production traffic. - - - - - - - - diff --git a/docs/shape-distributions/gated_delta_rule_decode_h48_dk128_dv128.svg b/docs/shape-distributions/gated_delta_rule_decode_h48_dk128_dv128.svg deleted file mode 100644 index 895566a678ebcac55044294708b67fd409bcc056..0000000000000000000000000000000000000000 --- a/docs/shape-distributions/gated_delta_rule_decode_h48_dk128_dv128.svg +++ /dev/null @@ -1,523 +0,0 @@ - - - - Shape distribution: gated_delta_rule_decode_h48_dk128_dv128 - - - - - Shape distribution: gated_delta_rule_decode_h48_dk128_dv128 - image/svg+xml - - - Matplotlib v3.11.2, https://matplotlib.org/ - - - - - - - - - - - - - - - - - - - - - 1 - - - - - - 2 - - - - - - 3 - - - - - - 4 - - - - - - 5 - - - - - - 6 - - - - - - 7 - - - - - - 8 - - - - - - 9 - - - - - - 11 - - - - - - 12 - - - - - - 13 - - - - - - 14 - - - - - - 15 - - - - - - 16 - - - - - - 17 - - - - - - 18 - - - - - - 19 - - - - - - 20 - - - - - - 21 - - - - - - 22 - - - - - - 23 - - - - B — Runtime batch size - - - - - - - - - - 0 - - - - - - - - - 15 - - - - - - - - - 30 - - - - - - - - - 45 - - - - - - - - - 60 - - - - - - - - - 75 - - - - Captured workloads (count) - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 72 - - - 12 - - - 10 - - - 8 - - - 8 - - - 8 - - - 8 - - - 8 - - - 8 - - - 4 - - - 4 - - - 4 - - - 4 - - - 4 - - - 4 - - - 2 - - - 4 - - - 4 - - - 4 - - - 4 - - - 4 - - - 4 - - - - Shape distribution - - - gated_delta_rule_decode_h48_dk128_dv128 - - - 192 captured workloads | 22 distinct shapes - - - Fixed dimensions: T=1, Hq=16, H=48, Dk=128, Dv=128 - - - One bin per exact runtime shape; equal spacing. Counts describe this dataset, not production traffic. - - - - - - - - diff --git a/docs/shape-distributions/gated_delta_rule_prefill_h48_dk128_dv128.svg b/docs/shape-distributions/gated_delta_rule_prefill_h48_dk128_dv128.svg deleted file mode 100644 index f9f8f82709a2e3f54fe9a90127fc103dffd858cf..0000000000000000000000000000000000000000 --- a/docs/shape-distributions/gated_delta_rule_prefill_h48_dk128_dv128.svg +++ /dev/null @@ -1,852 +0,0 @@ - - - - Shape distribution: gated_delta_rule_prefill_h48_dk128_dv128 - - - - - Shape distribution: gated_delta_rule_prefill_h48_dk128_dv128 - image/svg+xml - - - Matplotlib v3.11.2, https://matplotlib.org/ - - - - - - - - - - - - - - - - - - - - - - - - 0 - - - - - - - - - 2 - - - - - - - - - 4 - - - - - - - - - 6 - - - - - - - - - 8 - - - - Captured workloads (count) - - - - - - - (1, 128) - - - - - - (1, 192) - - - - - - (1, 256) - - - - - - (1, 384) - - - - - - (1, 448) - - - - - - (1, 512) - - - - - - (1, 576) - - - - - - (1, 640) - - - - - - (1, 704) - - - - - - (1, 768) - - - - - - (1, 832) - - - - - - (1, 960) - - - - - - (1, 1024) - - - - - - (1, 1152) - - - - - - (1, 1280) - - - - - - (1, 1344) - - - - - - (1, 1408) - - - - - - (1, 1536) - - - - - - (1, 1600) - - - - - - (1, 1664) - - - - - - (1, 1792) - - - - - - (1, 1856) - - - - - - (1, 1920) - - - - - - (1, 1984) - - - - - - (1, 2112) - - - - - - (1, 2176) - - - - - - (1, 2240) - - - - - - (1, 2304) - - - - - - (1, 2368) - - - - - - (1, 2432) - - - - - - (1, 2496) - - - - - - (1, 2560) - - - - - - (1, 2688) - - - - - - (1, 2752) - - - - - - (1, 2816) - - - - - - (1, 2880) - - - - - - (1, 2944) - - - - - - (1, 3264) - - - - - - (1, 3520) - - - - - - (1, 3648) - - - - - - (1, 3840) - - - - - - (1, 4096) - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 2 - - - 1 - - - 1 - - - 2 - - - 1 - - - 2 - - - 1 - - - 2 - - - 2 - - - 2 - - - 1 - - - 1 - - - 1 - - - 3 - - - 1 - - - 1 - - - 1 - - - 1 - - - 1 - - - 1 - - - 2 - - - 1 - - - 1 - - - 1 - - - 1 - - - 1 - - - 2 - - - 2 - - - 1 - - - 1 - - - 1 - - - 2 - - - 2 - - - 1 - - - 1 - - - 1 - - - 4 - - - 1 - - - 1 - - - 1 - - - 1 - - - 8 - - - - Shape distribution - - - gated_delta_rule_prefill_h48_dk128_dv128 - - - 65 captured workloads | 42 distinct shapes - - - Fixed dimensions: H=48, Dk=128, Dv=128 - - - Runtime shape: (B, T) - - - One bin per exact runtime shape; equal spacing. Counts describe this dataset, not production traffic. - - - - - - - - diff --git a/docs/shape-distributions/gdn_decode_qk4_v8_d128_k_last.svg b/docs/shape-distributions/gdn_decode_qk4_v8_d128_k_last.svg new file mode 100644 index 0000000000000000000000000000000000000000..15a25696c08b4abfcfa216c3459d75b876d0a606 --- /dev/null +++ b/docs/shape-distributions/gdn_decode_qk4_v8_d128_k_last.svg @@ -0,0 +1,268 @@ + + + + Shape distribution: gdn_decode_qk4_v8_d128_k_last + + + + + Shape distribution: gdn_decode_qk4_v8_d128_k_last + image/svg+xml + + + Matplotlib v3.11.2, https://matplotlib.org/ + + + + + + + + + + + + + + + + + + + + + 1 + + + + + + 4 + + + + + + 8 + + + + + + 16 + + + + + + 32 + + + + + + 48 + + + + + + 64 + + + + batch_size — Number of sequences being decoded concurrently + + + + + + + + + + 0 + + + + + + + + + 2 + + + + + + + + + 4 + + + + + + + + + 6 + + + + + + + + + 8 + + + + + + + + + 10 + + + + Captured workloads (count) + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 10 + + + 8 + + + 7 + + + 7 + + + 7 + + + 7 + + + 8 + + + + Shape distribution + + + gdn_decode_qk4_v8_d128_k_last + + + 54 captured workloads | 7 distinct shapes + + + Fixed dimensions: seq_len=1, num_q_heads=4, num_k_heads=4, num_v_heads=8, head_size=128 + + + One bin per exact runtime shape; equal spacing. Counts describe this dataset, not production traffic. + + + + + + + + diff --git a/docs/shape-distributions/gdn_prefill_qk4_v8_d128_k_last.svg b/docs/shape-distributions/gdn_prefill_qk4_v8_d128_k_last.svg new file mode 100644 index 0000000000000000000000000000000000000000..cc33a5a0b3ee7439691d56cbc55735d7aa1087a9 --- /dev/null +++ b/docs/shape-distributions/gdn_prefill_qk4_v8_d128_k_last.svg @@ -0,0 +1,1436 @@ + + + + Shape distribution: gdn_prefill_qk4_v8_d128_k_last + + + + + Shape distribution: gdn_prefill_qk4_v8_d128_k_last + image/svg+xml + + + Matplotlib v3.11.2, https://matplotlib.org/ + + + + + + + + + + + + + + + + + + + + + + + + 0 + + + + + + + + + 1 + + + + + + + + + 2 + + + + + + + + + 3 + + + + Captured workloads (count) + + + + + + + (6, 1, 2) + + + + + + (12, 1, 2) + + + + + + (13, 1, 2) + + + + + + (14, 1, 2) + + + + + + (16, 1, 2) + + + + + + (18, 1, 2) + + + + + + (23, 1, 2) + + + + + + (24, 1, 2) + + + + + + (28, 2, 3) + + + + + + (30, 1, 2) + + + + + + (31, 1, 2) + + + + + + (32, 2, 3) + + + + + + (35, 1, 2) + + + + + + (35, 2, 3) + + + + + + (40, 2, 3) + + + + + + (42, 2, 3) + + + + + + (46, 2, 3) + + + + + + (48, 1, 2) + + + + + + (49, 1, 2) + + + + + + (61, 1, 2) + + + + + + (67, 1, 2) + + + + + + (68, 1, 2) + + + + + + (76, 2, 3) + + + + + + (79, 1, 2) + + + + + + (81, 2, 3) + + + + + + (82, 3, 4) + + + + + + (85, 2, 3) + + + + + + (91, 2, 3) + + + + + + (92, 1, 2) + + + + + + (97, 1, 2) + + + + + + (114, 2, 3) + + + + + + (116, 1, 2) + + + + + + (118, 2, 3) + + + + + + (132, 2, 3) + + + + + + (134, 1, 2) + + + + + + (139, 3, 4) + + + + + + (185, 2, 3) + + + + + + (202, 3, 4) + + + + + + (239, 3, 4) + + + + + + (248, 2, 3) + + + + + + (255, 3, 4) + + + + + + (294, 3, 4) + + + + + + (341, 2, 3) + + + + + + (401, 4, 5) + + + + + + (461, 2, 3) + + + + + + (525, 1, 2) + + + + + + (574, 2, 3) + + + + + + (661, 3, 4) + + + + + + (832, 4, 5) + + + + + + (959, 4, 5) + + + + + + (973, 3, 4) + + + + + + (983, 2, 3) + + + + + + (1377, 1, 2) + + + + + + (1592, 3, 4) + + + + + + (1796, 3, 4) + + + + + + (1800, 3, 4) + + + + + + (2040, 2, 3) + + + + + + (2107, 1, 2) + + + + + + (2284, 3, 4) + + + + + + (2857, 3, 4) + + + + + + (3028, 5, 6) + + + + + + (3271, 2, 3) + + + + + + (3999, 13, 14) + + + + + + (4124, 15, 16) + + + + + + (5709, 2, 3) + + + + + + (8192, 20, 21) + + + + + + (8192, 25, 26) + + + + + + (8192, 32, 33) + + + + + + (8192, 34, 35) + + + + + + (8192, 35, 36) + + + + + + (8192, 37, 38) + + + + + + (8192, 38, 39) + + + + + + (8192, 39, 40) + + + + + + (8192, 43, 44) + + + + + + (8192, 48, 49) + + + + + + (8192, 56, 57) + + + + + + (8192, 57, 58) + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 1 + + + 1 + + + 1 + + + 1 + + + 3 + + + 1 + + + 1 + + + 1 + + + 1 + + + 3 + + + 1 + + + 1 + + + 2 + + + 2 + + + 1 + + + 1 + + + 1 + + + 1 + + + 3 + + + 1 + + + 1 + + + 1 + + + 3 + + + 1 + + + 1 + + + 1 + + + 1 + + + 2 + + + 1 + + + 2 + + + 2 + + + 1 + + + 1 + + + 1 + + + 2 + + + 2 + + + 1 + + + 1 + + + 1 + + + 1 + + + 1 + + + 1 + + + 1 + + + 1 + + + 1 + + + 1 + + + 1 + + + 1 + + + 1 + + + 2 + + + 2 + + + 2 + + + 1 + + + 1 + + + 1 + + + 2 + + + 1 + + + 1 + + + 1 + + + 1 + + + 1 + + + 1 + + + 1 + + + 1 + + + 1 + + + 1 + + + 1 + + + 2 + + + 2 + + + 1 + + + 1 + + + 2 + + + 1 + + + 2 + + + 1 + + + 1 + + + 1 + + + + Shape distribution + + + gdn_prefill_qk4_v8_d128_k_last + + + 100 captured workloads | 77 distinct shapes + + + Fixed dimensions: num_q_heads=4, num_k_heads=4, num_v_heads=8, head_size=128 + + + Runtime shape: (total_seq_len, num_seqs, len_cu_seqlens) + + + One bin per exact runtime shape; equal spacing. Counts describe this dataset, not production traffic. + + + + + + + + diff --git a/docs/shape-distributions/grouped_gemm_fp8_fp4_e384_n2304_k5120_g32.svg b/docs/shape-distributions/grouped_gemm_fp8_fp4_e384_n2304_k5120_g32.svg deleted file mode 100644 index 233d102d1294ebd5b1f2866466d55cdd1d044857..0000000000000000000000000000000000000000 --- a/docs/shape-distributions/grouped_gemm_fp8_fp4_e384_n2304_k5120_g32.svg +++ /dev/null @@ -1,347 +0,0 @@ - - - - Shape distribution: grouped_gemm_fp8_fp4_e384_n2304_k5120_g32 - - - - - Shape distribution: grouped_gemm_fp8_fp4_e384_n2304_k5120_g32 - image/svg+xml - - - Matplotlib v3.11.2, https://matplotlib.org/ - - - - - - - - - - - - - - - - - - - - - 6 - - - - - - 12 - - - - - - 18 - - - - - - 768 - - - - - - 2688 - - - - - - 11904 - - - - - - 14592 - - - - - - 17664 - - - - - - 20736 - - - - - - 24192 - - - - - - 24576 - - - - M — Runtime number of token rows - - - - - - - - - - 0 - - - - - - - - - 6 - - - - - - - - - 12 - - - - - - - - - 18 - - - - - - - - - 24 - - - - - - - - - 30 - - - - - - - - - 36 - - - - Captured workloads (count) - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 34 - - - 4 - - - 4 - - - 1 - - - 1 - - - 1 - - - 1 - - - 1 - - - 1 - - - 1 - - - 3 - - - - Shape distribution - - - grouped_gemm_fp8_fp4_e384_n2304_k5120_g32 - - - 52 captured workloads | 11 distinct shapes - - - Fixed dimensions: E=384, N=2304, K=5120, K_packed=2560, K_groups=160, group_size=32 - - - One bin per exact runtime shape; equal spacing. Counts describe this dataset, not production traffic. - - - - - - - - diff --git a/kda/dense_gemm_bf16_nt_n12288_k4096.json b/kda/dense_gemm_bf16_nt_n12288_k4096.json new file mode 100644 index 0000000000000000000000000000000000000000..74daa47b6e7826c57eab27062ba9e6dae8f198a3 --- /dev/null +++ b/kda/dense_gemm_bf16_nt_n12288_k4096.json @@ -0,0 +1,27 @@ +{ + "definition": "definitions/gemm/dense_gemm_bf16_nt_n12288_k4096.json", + "workloads": [ + "workloads/gemm/dense_gemm_bf16_nt_n12288_k4096.jsonl" + ], + "baseline": "solutions/gemm/sglang_dense_gemm_bf16_nt_n12288_k4096.json", + "tolerance": { + "atol": 0.005, + "rtol": 0.016, + "required_matched_ratio": null + }, + "group_axis": "M", + "dev": [ + "ff62c8f2-f87c-586b-b295-7d130dd1a037", + "8bc7ebff-12d1-5ac5-99bb-d18a9cbdb505", + "717bab44-772a-580e-bd31-8f449703fca5", + "b571dcbc-df9a-515c-90ac-93ba5e03a0dd", + "d89ba855-bc0f-52a5-9825-2f44455164ea", + "6c24a9cf-df14-538e-9876-3431874e3701", + "8c811c7c-db79-50a4-a48d-c1e483e9418b" + ], + "timing": { + "warmup": 5, + "iters": 20, + "trials": 2 + } +} diff --git a/kda/dense_gemm_bf16_nt_n4096_k12288.json b/kda/dense_gemm_bf16_nt_n4096_k12288.json new file mode 100644 index 0000000000000000000000000000000000000000..7f6c83a14580b1c43214d3811d0bdfab0d4c8217 --- /dev/null +++ b/kda/dense_gemm_bf16_nt_n4096_k12288.json @@ -0,0 +1,27 @@ +{ + "definition": "definitions/gemm/dense_gemm_bf16_nt_n4096_k12288.json", + "workloads": [ + "workloads/gemm/dense_gemm_bf16_nt_n4096_k12288.jsonl" + ], + "baseline": "solutions/gemm/sglang_dense_gemm_bf16_nt_n4096_k12288.json", + "tolerance": { + "atol": 0.005, + "rtol": 0.016, + "required_matched_ratio": null + }, + "group_axis": "M", + "dev": [ + "1ef85b69-b938-5554-b019-1cd333110897", + "17f61747-5e4c-5e99-a7c4-f096b147fb60", + "f49b336e-43c9-5d0e-a40d-277dc443e7e1", + "d26eaeed-136a-5399-999a-baf0a72a8818", + "f53807e9-dd75-5cca-9c00-8cc6f48f3a3a", + "f567a1a4-8780-53bc-bd48-6b7d561d8eb8", + "89b32f3e-3660-5591-8885-48dffb786922" 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"definitions/dense_attention/noncausal_dense_attention_h32_d64.json", + "workloads": [ + "workloads/dense_attention/noncausal_dense_attention_h32_d64.jsonl" + ], + "baseline": "solutions/dense_attention/sglang_noncausal_dense_attention_h32_d64.json", + "tolerance": { + "atol": 0.005, + "rtol": 0.016, + "required_matched_ratio": 0.9999 + }, + "group_axis": "Nq", + "dev": [ + "8867a364-4a86-5118-aeeb-e8adc8419445", + "fe5368a5-d8b1-53b5-a6c7-24893c1a525a", + "b19d6db5-9600-536d-8f4c-543dba8b95d0", + "2f9ae066-bf34-53c8-bb42-abe64c739e10", + "12c50ef4-b8c1-5f90-88e3-8721a5aa5c70", + "9182253a-2949-52dd-8da2-d2ebea4c91fc", + "365db76e-b098-5d94-84a6-2e0791f4ea86", + "67d71bcc-ecf0-57a2-8af2-2de9f591c6e0", + "475965cf-cbad-5baa-b685-479860697719", + "efa942e5-4b8c-5cb5-9554-232fa3b7b889" + ], + "timing": { + "warmup": 5, + "iters": 20, + "trials": 1 + } +} diff --git a/kda/prefix_cached_block_causal_h32_d128.json b/kda/prefix_cached_block_causal_h32_d128.json new file mode 100644 index 0000000000000000000000000000000000000000..917989b87e4e0d5c03372f84f52b5ee6b6109d0f --- /dev/null +++ b/kda/prefix_cached_block_causal_h32_d128.json @@ -0,0 +1,25 @@ +{ + "definition": "definitions/block_causal_attention/prefix_cached_block_causal_h32_d128.json", + "workloads": [ + "workloads/block_causal_attention/prefix_cached_block_causal_h32_d128.jsonl" + ], + "baseline": "solutions/block_causal_attention/sglang_prefix_cached_block_causal_h32_d128.json", + "tolerance": { + "atol": 0.005, + "rtol": 0.016, + "required_matched_ratio": null + }, + "group_axis": "Nq", + "dev": [ + "81e94812-2329-5af8-ae49-8167cf27ca32", + "b1e89f95-4b54-5116-9a57-3c29fb4cb095", + "dc3b6e8c-6201-52c8-9d2e-a190d1562087", + "0d5a8062-d653-5f8d-89e7-c92004279f8f", + "322fac48-fa66-5a79-aa96-a99c862d24e2" + ], + "timing": { + "warmup": 5, + "iters": 20, + "trials": 3 + } +} diff --git a/kda/prefix_cached_block_causal_h32_d128_prefix0.json b/kda/prefix_cached_block_causal_h32_d128_prefix0.json new file mode 100644 index 0000000000000000000000000000000000000000..3e2ed277589b11047b8b273ebd7d42d4da16f019 --- /dev/null +++ b/kda/prefix_cached_block_causal_h32_d128_prefix0.json @@ -0,0 +1,24 @@ +{ + "definition": "definitions/block_causal_attention/prefix_cached_block_causal_h32_d128_prefix0.json", + "workloads": [ + "workloads/block_causal_attention/prefix_cached_block_causal_h32_d128_prefix0.jsonl" + ], + "baseline": "solutions/block_causal_attention/sglang_prefix_cached_block_causal_h32_d128_prefix0.json", + "tolerance": { + "atol": 0.005, + "rtol": 0.016, + "required_matched_ratio": null + }, + "group_axis": "Nq", + "dev": [ + "361da807-31fa-5a25-8b62-37752b8f3529", + "3a45e86c-e517-57d7-92c0-85586056d271", + "d90f0f73-d020-5734-8dd7-710a91a624a7", + "f2a1a8e2-460a-549a-a3d1-bdf74bf42f26" + ], + "timing": { + "warmup": 5, + "iters": 20, + "trials": 3 + } +} diff --git a/kda/qsa_index_topk_decode_qwen38_h4_d128_topk512_c4.json b/kda/qsa_index_topk_decode_qwen38_h4_d128_topk512_c4.json new file mode 100644 index 0000000000000000000000000000000000000000..a07699e8f57a6234d61fd8870f8957fc8adbcb90 --- /dev/null +++ b/kda/qsa_index_topk_decode_qwen38_h4_d128_topk512_c4.json @@ -0,0 +1,30 @@ +{ + "definition": "definitions/qsa_index/qsa_index_topk_decode_qwen38_h4_d128_topk512_c4.json", + "workloads": [ + "workloads/qsa_index/qsa_index_topk_decode_qwen38_h4_d128_topk512_c4.jsonl" + ], + "baseline": "solutions/qsa_index/sglang_qsa_index_topk_decode_qwen38_h4_d128_topk512_c4.json", + "tolerance": { + "atol": 0.0, + "rtol": 0.0, + "required_matched_ratio": null + }, + "group_axis": "B", + "dev": [ + "691b7d0c-2cf5-57f0-8008-6c37d24d2ced", + "7b70c914-edb9-5caa-be9e-5adba28327d0", + "c1169039-d7e1-58d6-8371-f9a9d899bc43", + "51b0efa4-d7c8-59f5-a9d5-b8ce0cc3463b", + "55f97d34-37c5-568a-bc45-269b1008bfb7", + "90a96bc1-3128-515b-b504-89b863fccfe5", + "801c787f-d6e1-52c1-a94e-98067513bdd5", + "28353c79-b9c0-5ca3-a37c-646b64ed5917", + "ed7d394f-ec0b-55a6-93ae-c8d88430ec2d", + "9e0e33c1-b008-5eb8-af3d-229a72ad0113" + ], + "timing": { + "warmup": 5, + "iters": 20, + "trials": 1 + } +} diff --git a/kda/qsa_sparse_gqa_decode_qwen38_h24_kv2_d256_topk512_c4.json b/kda/qsa_sparse_gqa_decode_qwen38_h24_kv2_d256_topk512_c4.json new file mode 100644 index 0000000000000000000000000000000000000000..30c1eef9f4f9a8ac69f210e2b1fbdca15d9b7bd5 --- /dev/null +++ b/kda/qsa_sparse_gqa_decode_qwen38_h24_kv2_d256_topk512_c4.json @@ -0,0 +1,30 @@ +{ + "definition": "definitions/qsa_sparse_gqa/qsa_sparse_gqa_decode_qwen38_h24_kv2_d256_topk512_c4.json", + "workloads": [ + "workloads/qsa_sparse_gqa/qsa_sparse_gqa_decode_qwen38_h24_kv2_d256_topk512_c4.jsonl" + ], + "baseline": "solutions/qsa_attention/sglang_qsa_sparse_gqa_decode_qwen38_h24_kv2_d256_topk512_c4.json", + "tolerance": { + "atol": 0.005, + "rtol": 0.016, + "required_matched_ratio": null + }, + "group_axis": "B", + "dev": [ + "80a15e07-f18a-505d-87fe-7ca5a6c99f71", + "a3c3d1cf-9da2-55cb-9148-b0a8ced14e20", + "98b37bba-29c7-56f9-8929-57e172095f9c", + "18f83437-e2f3-525e-9fb1-81bae92ff7de", + "6e544100-28fe-517e-8369-a6f4e8b214ae", + "37c2a312-b8ce-536b-8359-512c16d05bbb", + "33599fa7-eafb-5399-b847-8d714567d7b5", + "41b6e76c-f7db-5aea-bf47-854a33c9b15f", + "864c6857-c29f-53fd-a8f1-b81501f442b3", + "f89635f9-8d97-5102-a44e-8a249e9410e0" + ], + "timing": { + "warmup": 5, + "iters": 20, + "trials": 1 + } +} diff --git a/kda/sparse_mla_prefill_h64_d512_k128.json b/kda/sparse_mla_prefill_h64_d512_k128.json new file mode 100644 index 0000000000000000000000000000000000000000..2388f2c5e359b9d457c88c2aecdb0bbebe74632c --- /dev/null +++ b/kda/sparse_mla_prefill_h64_d512_k128.json @@ -0,0 +1,26 @@ +{ + "definition": "definitions/sparse_mla/sparse_mla_prefill_h64_d512_k128.json", + "workloads": [ + "workloads/sparse_mla/sparse_mla_prefill_h64_d512_k128.jsonl" + ], + "baseline": "solutions/sparse_mla/sglang_sparse_mla_prefill_h64_d512_k128.json", + "tolerance": { + "atol": 0.005, + "rtol": 0.016, + "required_matched_ratio": null + }, + "group_axis": "M", + "dev": [ + "63072e3a-2bf9-5eed-bc07-c48f323b15d4", + "d1602ca9-fae0-56ef-9bb2-a408fe19a22b", + "aa1f4b6e-c84d-5723-8007-090ffa76004f", + "ec18845f-e1bb-5eba-9649-3d90d470ce9b", + "c6c6e0c9-61e2-505e-831a-fef983c9dad9", + "d1c89357-aa68-53ac-b13f-62d900007022" + ], + "timing": { + "warmup": 5, + "iters": 20, + "trials": 3 + } +} diff --git a/kda/sparse_mla_prefill_h64_d512_k640.json b/kda/sparse_mla_prefill_h64_d512_k640.json new file mode 100644 index 0000000000000000000000000000000000000000..04c38942f635906eed269ec55ce4e2591505ed75 --- /dev/null +++ b/kda/sparse_mla_prefill_h64_d512_k640.json @@ -0,0 +1,30 @@ +{ + "definition": "definitions/sparse_mla/sparse_mla_prefill_h64_d512_k640.json", + "workloads": [ + "workloads/sparse_mla/sparse_mla_prefill_h64_d512_k640.jsonl" + ], + "baseline": "solutions/sparse_mla/sglang_sparse_mla_prefill_h64_d512_k640.json", + "tolerance": { + "atol": 0.006, + "rtol": 0.016, + "required_matched_ratio": null + }, + "group_axis": "M", + "dev": [ + "d9165058-a73b-5e77-8e61-5f92a8458b70", + "546bcf0e-32bd-5dd8-9ea9-14c58e6a52c9", + "495000a6-c8b0-5057-99f4-88ed4a96a4a1", + "0b988a7a-2b52-5f49-8c99-eaa373baf797", + "52560299-af35-5351-a4f0-cdcf97141e87", + "42f3b7ee-5af7-5dd1-bf58-71493057d3f5", + "c0332d0e-dddb-5656-a8c7-0ced515dbbfa", + "6385d1ff-f172-5c14-b73d-1c2b5943f045", + "7fd83f55-ee1c-5bec-b886-047096621576", + "b1ee31d7-328c-59af-a60c-189c90e2d248" + ], + "timing": { + "warmup": 5, + "iters": 20, + "trials": 3 + } +} diff --git a/scripts/capture_inputs.py b/scripts/capture_inputs.py index 0302ffdc0ddf38964536f9861c5fd96a080d6423..6f0915f59e446573b7bc40687f9c6adb2f8b211f 100644 --- a/scripts/capture_inputs.py +++ b/scripts/capture_inputs.py @@ -374,6 +374,8 @@ def replay(dataset_root, device): for line in path.read_text().splitlines(): trace = json.loads(line) name, workload = trace["definition"], trace["workload"] + if "expected_output" not in receipts[workload["uuid"]]: + continue # Imported workloads (the MLSys 2026 GDN) have no engine output. started = time.monotonic() result = {"definition": name, "uuid": workload["uuid"], "axes": workload["axes"]} try: diff --git a/scripts/capture_ltx.py b/scripts/capture_ltx.py index 03859835b1149f459ed963bb724f25bf4046ad2c..4ce2b807b2b043ac1f959af76156b932e5f05db1 100644 --- a/scripts/capture_ltx.py +++ b/scripts/capture_ltx.py @@ -75,24 +75,14 @@ def install(writer): sdpa_backend=audio_sdpa if modality == "audio" else video_sdpa, actual_attention_batch=int(q.shape[0]), module_path="transformer_blocks.0." + _label, - adapter="Preserve post-normalization/RoPE Q/K/V; expand the engine visibility mask without changing it.") + adapter="Preserve post-normalization/RoPE Q/K/V; verify that the engine mask is all-visible and omit the redundant mask input.") if writer.wants(name, provenance): mask = kw.get("attn_mask") - if mask is None: - mask = torch.ones((1, 1, 1, 1), dtype=torch.bool, device=q.device) - else: - if mask.is_floating_point(): - if not bool(((mask == 0) | (mask < -1e4)).all()): - raise ValueError("The boolean-mask definition cannot encode a finite attention bias") - mask = mask == 0 - else: - mask = mask.bool() - if mask.ndim == 2: - mask = mask[:, None, None, :] - elif mask.ndim == 3: - mask = mask[:, None, :, :] - mask = mask.expand(q.shape[0], q.shape[2], q.shape[1], k.shape[1]) - writer.write(name, dict(Q=q, K=k, V=v, mask=mask, sm_scale=q.shape[-1] ** -0.5), + if mask is not None: + visible = mask == 0 if mask.is_floating_point() else mask.bool() + if not bool(visible.all()): + raise ValueError("Mask-free attention capture requires an all-visible engine mask") + writer.write(name, dict(Q=q, K=k, V=v, sm_scale=q.shape[-1] ** -0.5), output.reshape_as(q), provenance) return output diff --git a/scripts/check_workload_inputs.py b/scripts/check_workload_inputs.py index 5f71050a0a96658bc08995577181e69fc5231691..07655020995e0732ecddbde6bedf51402c5ae8e5 100644 --- a/scripts/check_workload_inputs.py +++ b/scripts/check_workload_inputs.py @@ -83,7 +83,13 @@ def main(): axes = dict(definition.const_axes, **workload.axes) assert set(workload.inputs) == set(definition.inputs) for constraint in definition.constraints: - assert eval(constraint, {'__builtins__': {}}, axes), constraint + # A constraint may also read inputs, e.g. cu_seqlens[-1]. + scope = dict(axes) + for key in set(compile(constraint, name, 'eval').co_names) & set(definition.inputs): + descriptor = workload.inputs[key].model_dump() + scope[key] = (descriptor['value'] if descriptor['type'] == 'scalar' else + load_file(str(root / descriptor['path']))[descriptor['tensor_key']]) + assert eval(constraint, {'__builtins__': {}}, scope), constraint for key, spec in definition.inputs.items(): descriptor = workload.inputs[key].model_dump() if spec.shape is None: diff --git a/scripts/plot_shape_distributions.py b/scripts/plot_shape_distributions.py index cd3e6504d9c15a37f835a36aa092a1941051d087..b31d1dc84a0ed12636682ba05ccd49814bd2307e 100644 --- a/scripts/plot_shape_distributions.py +++ b/scripts/plot_shape_distributions.py @@ -78,7 +78,7 @@ def plot_distribution(definition, axes, counts): else: bars = ax.bar(range(len(shapes)), frequencies, width=0.72, color=color) ax.set_xticks(range(len(shapes)), labels, rotation=35, ha="right", fontsize=10) - description = definition["axes"][axes[0]]["description"].rstrip(".") + description = definition["axes"][axes[0]].get("description", axes[0]).rstrip(".") ax.set_xlabel(f"{axes[0]} — {description}", labelpad=12) ax.set_ylabel("Captured workloads (count)", labelpad=10) ax.set_ylim(0, max(frequencies) * 1.17) @@ -126,7 +126,7 @@ def write_gallery(distributions, output): f"[SVG]({name}.svg)", "", f"![Shape distribution for {name}: {sum(counts.values())} workloads across {len(counts)} shapes]({name}.svg)", "", "**Runtime dimensions:** " + " ".join( - f"`{axis}`: {definition['axes'][axis]['description']}" for axis in axes), + f"`{axis}`: {definition['axes'][axis].get('description', axis)}" for axis in axes), ]) (output / "README.md").write_text("\n".join(lines) + "\n") diff --git a/solutions/block_causal_attention/sglang_prefix_cached_block_causal_h32_d128.json b/solutions/block_causal_attention/sglang_prefix_cached_block_causal_h32_d128.json new file mode 100644 index 0000000000000000000000000000000000000000..99691eac652208011b81fe8475cf3a8eeaaa1826 --- /dev/null +++ b/solutions/block_causal_attention/sglang_prefix_cached_block_causal_h32_d128.json @@ -0,0 +1,23 @@ +{ + "name": "sglang_prefix_cached_block_causal_h32_d128", + "definition": "prefix_cached_block_causal_h32_d128", + "author": "kda", + "description": "SGLang's own implementation at the capture commit 684fea8a, called the way the engine calls it (see the module docstring). Run it in lmsysorg/sglang@sha256:ddae0e399d3d94f7827f16183301cf8dac4cf0eae0ef25590b7dac5881d713d8. KDA (Kernel Design Agents) times it live as the baseline: prepare(*inputs) does the host-side setup and returns a zero-argument launch, and only launch is timed; run(*inputs) does both.", + "spec": { + "language": "python", + "target_hardware": [ + "NVIDIA_B300" + ], + "entry_point": "main.py::run", + "dependencies": [ + "sglang @ git+https://github.com/sgl-project/sglang.git@684fea8af3b11a5b51ec9966c02959a32ad3421c#subdirectory=python" + ], + "destination_passing_style": false + }, + "sources": [ + { + "path": "main.py", + "content": "# Copyright 2026 Co-developed by KDA (Kernel Design Agents)\n\"\"\"SGLang 684fea8a: Qwen-Image 2.1 ``target_attn`` under ``--attention-backend torch_sdpa``.\n\nCall path (``python/sglang/multimodal_gen/runtime/``):\n``models/dits/qwen_image21.py:703`` ``target_attn.forward_with_replicated_kv_prefix``\n(or ``qwen_image21.py:629-631`` ``attend_target`` -> ``target_attn(q, k, v)`` with the\nsame packed K/V) -> on one rank, ``layers/attention/layer.py:2116-2119``: concatenate\nthe prefix and current K/V, then ``attn_impl.forward`` -> ``SDPAImpl.forward``\n(``layers/attention/backends/sdpa.py:76-114``): torch SDPA, no mask, scale\n``head_dim**-0.5``.\n\nAdapters: ``USPAttention`` needs SGLang's global server args and parallel groups, so\nthe ``SDPAImpl`` it builds (``layer.py:849-850, 874-886``) is built here with the same\narguments. ``image_ids``, ``key_valid`` and ``sm_scale`` are not arguments of SGLang's\ncall: on every captured row each query sees every key and ``sm_scale`` is\n1/sqrt(128). The transposed SDPA output is copied into an owned dense tensor.\n\"\"\"\n\nimport torch\nfrom sglang.multimodal_gen.runtime.layers.attention.backends.sdpa import SDPAImpl\n\nHEADS, HEAD_DIM = 32, 128\nTARGET_IMPL = SDPAImpl(\n num_heads=HEADS,\n head_size=HEAD_DIM,\n causal=False,\n softmax_scale=HEAD_DIM**-0.5,\n num_kv_heads=HEADS,\n)\n\n\ndef run(Q, K_current, V_current, K_prefix, V_prefix, image_ids, key_valid, sm_scale):\n # layer.py:2117-2119\n k = torch.cat([K_prefix, K_current], dim=1)\n v = torch.cat([V_prefix, V_current], dim=1)\n out = TARGET_IMPL.forward(Q, k, v, None)\n return out.clone(memory_format=torch.contiguous_format)\n" + } + ] +} diff --git a/solutions/block_causal_attention/sglang_prefix_cached_block_causal_h32_d128_prefix0.json b/solutions/block_causal_attention/sglang_prefix_cached_block_causal_h32_d128_prefix0.json new file mode 100644 index 0000000000000000000000000000000000000000..c898236cfb9c4034fed2ea8663e5771094a75062 --- /dev/null +++ b/solutions/block_causal_attention/sglang_prefix_cached_block_causal_h32_d128_prefix0.json @@ -0,0 +1,23 @@ +{ + "name": "sglang_prefix_cached_block_causal_h32_d128_prefix0", + "definition": "prefix_cached_block_causal_h32_d128_prefix0", + "author": "kda", + "description": "SGLang's own implementation at the capture commit 684fea8a, called the way the engine calls it (see the module docstring). Run it in lmsysorg/sglang@sha256:ddae0e399d3d94f7827f16183301cf8dac4cf0eae0ef25590b7dac5881d713d8. KDA (Kernel Design Agents) times it live as the baseline: prepare(*inputs) does the host-side setup and returns a zero-argument launch, and only launch is timed; run(*inputs) does both.", + "spec": { + "language": "python", + "target_hardware": [ + "NVIDIA_B300" + ], + "entry_point": "main.py::run", + "dependencies": [ + "sglang @ git+https://github.com/sgl-project/sglang.git@684fea8af3b11a5b51ec9966c02959a32ad3421c#subdirectory=python" + ], + "destination_passing_style": false + }, + "sources": [ + { + "path": "main.py", + "content": "# Copyright 2026 Co-developed by KDA (Kernel Design Agents)\n\"\"\"SGLang 684fea8a: Qwen-Image 2.1 prefix attention under ``--attention-backend torch_sdpa``.\n\nCall path (``python/sglang/multimodal_gen/runtime/``):\n``models/dits/qwen_image21.py:651-667`` ``attend_sample`` without a cache: per prefix\nsegment, ``local_attn(qp[:, start:end], kp[:, :end], vp[:, :end], attn_mask=mask)``\nwith a causal bool mask for text runs and none for image blocks, joined by\n``cat_outputs`` (``qwen_image21.py:253-255``). ``LocalAttention.forward``\n(``layers/attention/layer.py:725-801``): with a mask, the bool mask made additive in\nbf16 and torch SDPA; without, ``SDPAImpl.forward`` (``backends/sdpa.py:76-114``).\n\nAdapters: ``local_attn`` is built as ``QwenImage21Attention.__init__`` builds it\n(``qwen_image21.py:395-398``), with the CLI backend forced through SGLang's selector,\nand run in SGLang's forward context. The engine's segments are the runs of\n``image_ids`` (text = -1); ``prepare`` derives them and their masks on the host.\n``K_prefix``/``V_prefix`` are empty (Np = 0), so ``kp, vp`` are the current K/V.\n``torch.cat`` replaces ``cat_outputs``, whose one-segment shortcut would return the\ntransposed SDPA view, so the output is an owned dense tensor. ``key_valid`` and\n``sm_scale`` are not arguments of SGLang's call: every captured key is valid and\n``sm_scale`` is 1/sqrt(128).\n\"\"\"\n\nimport torch\nfrom sglang.multimodal_gen.runtime.layers.attention import LocalAttention\nfrom sglang.multimodal_gen.runtime.layers.attention.selector import (\n global_force_attn_backend_context_manager,\n)\nfrom sglang.multimodal_gen.runtime.managers.forward_context import set_forward_context\nfrom sglang.multimodal_gen.runtime.models.dits.qwen_image21 import (\n QwenImage21Transformer2DModel,\n)\nfrom sglang.multimodal_gen.runtime.platforms import AttentionBackendEnum\n\nHEADS, HEAD_DIM = 32, 128\nwith global_force_attn_backend_context_manager(AttentionBackendEnum.TORCH_SDPA):\n LOCAL_ATTN = LocalAttention(\n HEADS,\n HEAD_DIM,\n supported_attention_backends=QwenImage21Transformer2DModel._supported_attention_backends,\n )\n\n\ndef prepare(\n Q, K_current, V_current, K_prefix, V_prefix, image_ids, key_valid, sm_scale\n):\n ids = image_ids.cpu()\n ends = torch.cumsum(torch.unique_consecutive(ids, return_counts=True)[1], 0)\n segments = []\n for start, end in zip([0, *ends[:-1].tolist()], ends.tolist()):\n mask = None\n if ids[start] < 0:\n # qwen_image21.py:657-661\n mask = (\n torch.arange(end, device=Q.device)[None, :]\n <= torch.arange(start, end, device=Q.device)[:, None]\n )\n mask = mask[None, None]\n segments.append((start, end, mask))\n\n def launch():\n with set_forward_context(current_timestep=0, attn_metadata=None):\n # qwen_image21.py:654-665\n outputs = [\n LOCAL_ATTN(\n Q[:, start:end],\n K_current[:, :end],\n V_current[:, :end],\n attn_mask=mask,\n )\n for start, end, mask in segments\n ]\n return torch.cat(outputs, dim=1)\n\n return launch\n\n\ndef run(*inputs):\n return prepare(*inputs)()\n" + } + ] +} diff --git a/solutions/dense_attention/fa4_noncausal_h32_d128.json b/solutions/dense_attention/fa4_noncausal_h32_d128.json index daf5737df99af46f9dcce0919d098c34f100dbe0..e4d7dab360c080a39ca03f0ef6f2c4356f9d4639 100644 --- a/solutions/dense_attention/fa4_noncausal_h32_d128.json +++ b/solutions/dense_attention/fa4_noncausal_h32_d128.json @@ -2,7 +2,25 @@ "name": "fa4_noncausal_h32_d128", "definition": "noncausal_dense_attention_h32_d128", "author": "inference-kernels", - "description": "FlashAttention 4 CuTe DSL with a runtime Boolean visibility mask. No assumption about mask contents. Upstream: https://github.com/Dao-AILab/flash-attention (BSD-3-Clause).", - "spec": {"language": "python", "target_hardware": ["NVIDIA_B200"], "entry_point": "main.py::run", "dependencies": ["torch>=2.11", "flash-attn-4==4.0.0b35", "nvidia-cutlass-dsl[cu13]==4.7.1", "quack-kernels==0.6.5"], "destination_passing_style": false}, - "sources": [{"path": "main.py", "content": "import cutlass\nimport cutlass.cute as cute\nfrom flash_attn.cute import utils\nfrom flash_attn.cute.interface import flash_attn_func\n\n@cute.jit\ndef visible(batch, head, m_idx, n_idx, seqlen_info, aux_tensors):\n m = cutlass.min(m_idx[0], seqlen_info.seqlen_q - 1)\n n = cutlass.min(n_idx[0], seqlen_info.seqlen_k - 1)\n return utils.scalar_to_ssa(aux_tensors[0][batch[0], head[0], m, n], cutlass.Boolean)\n\ndef run(Q, K, V, mask, sm_scale):\n return flash_attn_func(Q, K, V, softmax_scale=sm_scale, mask_mod=visible, aux_tensors=[mask])[0]\n"}] + "description": "FlashAttention 4 CuTe DSL without a mask. Upstream: https://github.com/Dao-AILab/flash-attention (BSD-3-Clause).", + "spec": { + "language": "python", + "target_hardware": [ + "NVIDIA_B200" + ], + "entry_point": "main.py::run", + "dependencies": [ + "torch>=2.11", + "flash-attn-4==4.0.0b35", + "nvidia-cutlass-dsl[cu13]==4.7.1", + "quack-kernels==0.6.5" + ], + "destination_passing_style": false + }, + "sources": [ + { + "path": "main.py", + "content": "from flash_attn.cute.interface import flash_attn_func\n\ndef run(Q, K, V, sm_scale):\n return flash_attn_func(Q, K, V, softmax_scale=sm_scale)[0]\n" + } + ] } diff --git a/solutions/dense_attention/fa4_noncausal_h32_d64.json b/solutions/dense_attention/fa4_noncausal_h32_d64.json index f36898e5453880438bad659234c6ced78c651367..e29bb4d2d2cfaf6852bad0c9c8f9a85ea86f9603 100644 --- a/solutions/dense_attention/fa4_noncausal_h32_d64.json +++ b/solutions/dense_attention/fa4_noncausal_h32_d64.json @@ -2,7 +2,25 @@ "name": "fa4_noncausal_h32_d64", "definition": "noncausal_dense_attention_h32_d64", "author": "inference-kernels", - "description": "FlashAttention 4 CuTe DSL with a runtime Boolean visibility mask. Converts the captured normalized audio-attention inputs to FP16 to reduce probability-rounding error, and returns BF16. All conversions are included in the call. Upstream: https://github.com/Dao-AILab/flash-attention (BSD-3-Clause).", - "spec": {"language": "python", "target_hardware": ["NVIDIA_B200"], "entry_point": "main.py::run", "dependencies": ["torch>=2.11", "flash-attn-4==4.0.0b35", "nvidia-cutlass-dsl[cu13]==4.7.1", "quack-kernels==0.6.5"], "destination_passing_style": false}, - "sources": [{"path": "main.py", "content": "import torch\nimport cutlass\nimport cutlass.cute as cute\nfrom flash_attn.cute import utils\nfrom flash_attn.cute.interface import flash_attn_func\n\n@cute.jit\ndef visible(batch, head, m_idx, n_idx, seqlen_info, aux_tensors):\n m = cutlass.min(m_idx[0], seqlen_info.seqlen_q - 1)\n n = cutlass.min(n_idx[0], seqlen_info.seqlen_k - 1)\n return utils.scalar_to_ssa(aux_tensors[0][batch[0], head[0], m, n], cutlass.Boolean)\n\ndef run(Q, K, V, mask, sm_scale):\n output = flash_attn_func(Q.to(torch.float16), K.to(torch.float16), V.to(torch.float16), softmax_scale=sm_scale, mask_mod=visible, aux_tensors=[mask])[0]\n return output.to(Q.dtype)\n"}] + "description": "FlashAttention 4 CuTe DSL without a mask. Converts the captured normalized audio-attention inputs to FP16 to reduce probability-rounding error, and returns BF16. All conversions are included in the call. Upstream: https://github.com/Dao-AILab/flash-attention (BSD-3-Clause).", + "spec": { + "language": "python", + "target_hardware": [ + "NVIDIA_B200" + ], + "entry_point": "main.py::run", + "dependencies": [ + "torch>=2.11", + "flash-attn-4==4.0.0b35", + "nvidia-cutlass-dsl[cu13]==4.7.1", + "quack-kernels==0.6.5" + ], + "destination_passing_style": false + }, + "sources": [ + { + "path": "main.py", + "content": "import torch\nfrom flash_attn.cute.interface import flash_attn_func\n\ndef run(Q, K, V, sm_scale):\n output = flash_attn_func(Q.to(torch.float16), K.to(torch.float16), V.to(torch.float16), softmax_scale=sm_scale)[0]\n return output.to(Q.dtype)\n" + } + ] } diff --git a/solutions/dense_attention/sglang_noncausal_dense_attention_h32_d128.json b/solutions/dense_attention/sglang_noncausal_dense_attention_h32_d128.json new file mode 100644 index 0000000000000000000000000000000000000000..c52c16e69ee6de0ed92ba5e9813477f0c1be79df --- /dev/null +++ b/solutions/dense_attention/sglang_noncausal_dense_attention_h32_d128.json @@ -0,0 +1,23 @@ +{ + "name": "sglang_noncausal_dense_attention_h32_d128", + "definition": "noncausal_dense_attention_h32_d128", + "author": "kda", + "description": "SGLang's own implementation at the capture commit 684fea8a, called the way the engine calls it (see the module docstring). Run it in lmsysorg/sglang@sha256:ddae0e399d3d94f7827f16183301cf8dac4cf0eae0ef25590b7dac5881d713d8. KDA (Kernel Design Agents) times it live as the baseline: prepare(*inputs) does the host-side setup and returns a zero-argument launch, and only launch is timed; run(*inputs) does both.", + "spec": { + "language": "python", + "target_hardware": [ + "NVIDIA_B300" + ], + "entry_point": "main.py::run", + "dependencies": [ + "sglang @ git+https://github.com/sgl-project/sglang.git@684fea8af3b11a5b51ec9966c02959a32ad3421c#subdirectory=python" + ], + "destination_passing_style": false + }, + "sources": [ + { + "path": "main.py", + "content": "# Copyright 2026 Co-developed by KDA (Kernel Design Agents)\n\"\"\"SGLang baseline for noncausal_dense_attention_h32_d128: LTX-2.5 video attention.\n\nSGLang diffusion runtime at commit 684fea8a, paths under\npython/sglang/multimodal_gen/runtime/: LTX2Attention.forward\n(models/dits/ltx_2.py:997-1006) calls ``self.attn(q, k, v, attn_mask=mask)``\non [B, N, H, D] Q/K/V for ``attn1`` (USPAttention, :857-871) and ``attn2``\n(LocalAttention, :841-855); every layer has\nsoftmax_scale=None -> head_size**-0.5 and allow_cudnn_sdp=True. On one GPU the\nmask is None, except for ``attn2``'s all-ones prompt mask, whose additive\nmask is exactly zero; the definition has no mask.\n\nUSPAttention.forward (layers/attention/layer.py:1466-1468) or\nLocalAttention.forward (:799) -> SDPAImpl.forward\n(layers/attention/backends/sdpa.py:76-114): one SDPA call under\n``sdpa_kernel(_PYTORCH_DEFAULT_CUDA_SDP_BACKENDS, set_priority=True)``, which\ntries cuDNN, Flash and memory-efficient attention before math.\n\nSDPAImpl returns a [B, Nq, H, D] transpose of the SDPA output;\n``.contiguous().detach()`` hands it over dense, without a copy when the kernel\nwrote it sequence-major.\n\"\"\"\n\nfrom sglang.multimodal_gen.runtime.layers.attention.backends.sdpa import SDPAImpl\n\n\ndef prepare(Q, K, V, sm_scale):\n impl = SDPAImpl(\n num_heads=Q.shape[2],\n head_size=Q.shape[3],\n causal=False,\n softmax_scale=sm_scale,\n num_kv_heads=K.shape[2],\n allow_cudnn_sdp=True,\n )\n\n def launch():\n return impl.forward(Q, K, V, None).contiguous().detach()\n\n return launch\n\n\ndef run(Q, K, V, sm_scale):\n return prepare(Q, K, V, sm_scale)()\n" + } + ] +} diff --git a/solutions/dense_attention/sglang_noncausal_dense_attention_h32_d64.json b/solutions/dense_attention/sglang_noncausal_dense_attention_h32_d64.json new file mode 100644 index 0000000000000000000000000000000000000000..e8da2b944acabada715ac87e0b14d36327f890ed --- /dev/null +++ b/solutions/dense_attention/sglang_noncausal_dense_attention_h32_d64.json @@ -0,0 +1,23 @@ +{ + "name": "sglang_noncausal_dense_attention_h32_d64", + "definition": "noncausal_dense_attention_h32_d64", + "author": "kda", + "description": "SGLang's own implementation at the capture commit 684fea8a, called the way the engine calls it (see the module docstring). Run it in lmsysorg/sglang@sha256:ddae0e399d3d94f7827f16183301cf8dac4cf0eae0ef25590b7dac5881d713d8. KDA (Kernel Design Agents) times it live as the baseline: prepare(*inputs) does the host-side setup and returns a zero-argument launch, and only launch is timed; run(*inputs) does both.", + "spec": { + "language": "python", + "target_hardware": [ + "NVIDIA_B300" + ], + "entry_point": "main.py::run", + "dependencies": [ + "sglang @ git+https://github.com/sgl-project/sglang.git@684fea8af3b11a5b51ec9966c02959a32ad3421c#subdirectory=python" + ], + "destination_passing_style": false + }, + "sources": [ + { + "path": "main.py", + "content": "# Copyright 2026 Co-developed by KDA (Kernel Design Agents)\n\"\"\"SGLang baseline for noncausal_dense_attention_h32_d64: LTX-2.5 audio attention.\n\nSGLang diffusion runtime at commit 684fea8a, paths under\npython/sglang/multimodal_gen/runtime/: LTX2Attention.forward\n(models/dits/ltx_2.py:997-1006) calls ``self.attn(q, k, v, attn_mask=mask)``\non [B, N, H, D] Q/K/V for ``audio_attn1``, ``audio_to_video_attn`` and\n``video_to_audio_attn`` (USPAttention, :857-871, or LocalAttention) and\n``audio_attn2`` (LocalAttention, :841-855); every layer has\nsoftmax_scale=None -> head_size**-0.5 and allow_cudnn_sdp=True. On one GPU the\nmask is None, except for ``audio_attn2``'s all-ones prompt mask, whose additive\nmask is exactly zero; the definition has no mask.\n\nUSPAttention.forward (layers/attention/layer.py:1466-1468) or\nLocalAttention.forward (:799) -> SDPAImpl.forward\n(layers/attention/backends/sdpa.py:76-114): one SDPA call under\n``sdpa_kernel(_PYTORCH_DEFAULT_CUDA_SDP_BACKENDS, set_priority=True)``, which\ntries cuDNN, Flash and memory-efficient attention before math.\n\nSDPAImpl returns a [B, Nq, H, D] transpose of the SDPA output;\n``.contiguous().detach()`` hands it over dense, without a copy when the kernel\nwrote it sequence-major.\n\"\"\"\n\nfrom sglang.multimodal_gen.runtime.layers.attention.backends.sdpa import SDPAImpl\n\n\ndef prepare(Q, K, V, sm_scale):\n impl = SDPAImpl(\n num_heads=Q.shape[2],\n head_size=Q.shape[3],\n causal=False,\n softmax_scale=sm_scale,\n num_kv_heads=K.shape[2],\n allow_cudnn_sdp=True,\n )\n\n def launch():\n return impl.forward(Q, K, V, None).contiguous().detach()\n\n return launch\n\n\ndef run(Q, K, V, sm_scale):\n return prepare(Q, K, V, sm_scale)()\n" + } + ] +} diff --git a/solutions/gdn/flashinfer_gdn_prefill.json b/solutions/gdn/flashinfer_gdn_prefill.json deleted file mode 100644 index 65025f85a25a39e82a00a747c2a6f58086707867..0000000000000000000000000000000000000000 --- a/solutions/gdn/flashinfer_gdn_prefill.json +++ /dev/null @@ -1,8 +0,0 @@ -{ - "name": "flashinfer_gdn_prefill", - "definition": "gated_delta_rule_prefill_h48_dk128_dv128", - "author": "inference-kernels", - "description": "FlashInfer 0.7.2 Blackwell chunked GDN. Converts log-decay to multiplicative decay and the definition's K,V state layout to V,K. Uses the explicit open-source backend. Upstream: https://github.com/flashinfer-ai/flashinfer (Apache-2.0).", - "spec": {"language": "python", "target_hardware": ["NVIDIA_B200"], "entry_point": "main.py::run", "dependencies": ["torch>=2.11", "flashinfer-python==0.7.2", "nvidia-cutlass-dsl[cu13]==4.7.1"], "destination_passing_style": false}, - "sources": [{"path": "main.py", "content": "import torch\nfrom flashinfer.gdn_prefill import chunk_gated_delta_rule\n\ndef run(Q, K, V, beta, g, S0, q_scale):\n batch, length, heads, dim = Q.shape\n offsets = torch.arange(batch + 1, dtype=torch.int64, device=Q.device) * length\n initial = S0.transpose(-1, -2).contiguous()\n final = torch.empty_like(initial)\n output, final = chunk_gated_delta_rule(\n Q.flatten(0, 1), K.flatten(0, 1), V.flatten(0, 1),\n g=g.exp().flatten(0, 1), beta=beta.flatten(0, 1), scale=q_scale,\n initial_state=initial, output_final_state=True, output_state=final,\n cu_seqlens=offsets, use_qk_l2norm_in_kernel=False,\n backend='flashinfer', max_seqlen=length,\n )\n return output.reshape_as(V), final.transpose(-1, -2).contiguous()\n"}] -} diff --git a/solutions/gdn/flashinfer_wrapper_123ca6.json b/solutions/gdn/flashinfer_wrapper_123ca6.json new file mode 100644 index 0000000000000000000000000000000000000000..908289d8b092e4321776d4522bc037f5d326bbe9 --- /dev/null +++ b/solutions/gdn/flashinfer_wrapper_123ca6.json @@ -0,0 +1,40 @@ +{ + "name": "flashinfer_wrapper_123ca6", + "definition": "gdn_prefill_qk4_v8_d128_k_last", + "author": "flashinfer", + "spec": { + "language": "python", + "target_hardware": [ + "NVIDIA B200" + ], + "entry_point": "main.py::run", + "dependencies": [ + "cutlass", + "cuda-python" + ], + "destination_passing_style": false + }, + "sources": [ + { + "path": "main.py", + "content": "import torch\nimport torch.nn.functional as F\nfrom .gdn_blackwell.gdn import chunk_gated_delta_rule\n\n\ndef run(q, k, v, state, A_log, a, dt_bias, b, cu_seqlens, scale):\n x = a.float() + dt_bias.float()\n # Gate values in log-space: log(exp(-exp(A_log) * softplus(x))) = -exp(A_log) * softplus(x)\n g = -torch.exp(A_log.float()) * F.softplus(x)\n beta = torch.sigmoid(b.float())\n\n varlen = cu_seqlens is not None and q.dim() == 3\n if varlen:\n q = q.unsqueeze(0)\n k = k.unsqueeze(0)\n v = v.unsqueeze(0)\n\n output, new_state = chunk_gated_delta_rule(\n q=q,\n k=k,\n v=v,\n g=g,\n beta=beta,\n scale=None,\n initial_state=state,\n output_final_state=True,\n cu_seqlens=cu_seqlens,\n use_qk_l2norm_in_kernel=False,\n )\n\n if varlen:\n output = output.squeeze(0)\n\n return output, new_state\n" + }, + { + "path": "gdn_blackwell/__init__.py", + "content": "# Blackwell GDN kernel package\n" + }, + { + "path": "gdn_blackwell/gdn.py", + "content": "\"\"\"\nCopyright (c) 2026 by FlashInfer team.\n\nLicensed under the Apache License, Version 2.0 (the \"License\");\nyou may not use this file except in compliance with the License.\nYou may obtain a copy of the License at\n\n http://www.apache.org/licenses/LICENSE-2.0\n\nUnless required by applicable law or agreed to in writing, software\ndistributed under the License is distributed on an \"AS IS\" BASIS,\nWITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\nSee the License for the specific language governing permissions and\nlimitations under the License.\n\"\"\"\n\n# Gated Delta Networks (GDN) chunked linear attention kernel for NVIDIA Blackwell (SM100).\n#\n# Implements the Chunk-wise Gated Delta Rule linear attention using CuTe-DSL,\n# for Blackwell Architecture.\n#\n# Key Features:\n# - Supports Persistent & Non-persistent modes\n# - Supports fixed-length and variable-length sequences (cu_seqlens)\n# - Supports grouped value attention (GVA) where h_v is a multiple of h_q\n# - Supports head dimension (128)\n# - Supports input data types (f16/bf16)\n# - Supports output data types (f16/bf16)\n# - Supports initial_state to provide the initial state\n# - Supports output_final_state flag to return the final state\n# - State input and output are in f32 (fp16/bf16 not supported yet)\n\nimport torch\n\nfrom typing import Optional, Type, Tuple, Union\n\nimport cutlass\nimport cutlass.cute as cute\nimport cutlass.utils as utils\nimport cutlass.pipeline as pipeline\nimport cutlass.cute.nvgpu.tcgen05 as tcgen05\nimport cutlass.utils.blackwell_helpers as sm100_utils\nfrom cutlass.cute.runtime import from_dlpack\nfrom cutlass._mlir.dialects import nvvm\n\nimport cuda.bindings.driver as cuda\n\n\nfrom .gdn_tile_scheduler import *\nfrom .gdn_helpers import *\n\nimport functools\nimport warnings\n\nfrom cutlass.cute import EnableTVMFFI\n\n\ndef make_thread_cooperative_group(size: Int32):\n # return pipeline.CooperativeGroup(pipeline.Agent.Thread, size, size) # old version\n return pipeline.CooperativeGroup(pipeline.Agent.Thread, size)\n\n\nclass GDN:\n \"\"\"Blackwell (SM100) kernel for Chunk-wise Gated Delta Rule linear attention.\"\"\"\n\n def __init__(\n self,\n is_persistent: bool = False,\n chunk_size: Int32 = 128, # Only 128 is supported in current version\n head_dim: Int32 = 128, # Only 128 is supported in current version\n ):\n self.chunk_size = chunk_size\n self.is_persistent = is_persistent\n\n self.head_dim = head_dim\n self.cta_tiler = (chunk_size, chunk_size, head_dim)\n self.gate_tiler = (chunk_size, 1)\n self.beta_tiler = (chunk_size, 1)\n self.state_output_tiler = (head_dim, head_dim)\n self.o_output_tiler = (chunk_size, head_dim)\n\n self.g_beta_dtype = cutlass.Float32\n self.acc_dtype = cutlass.Float32\n self.state_dtype = cutlass.Float32\n\n self.mma_tiler = (chunk_size, chunk_size, head_dim)\n self.qk_mma_tiler = self.mma_tiler\n self.kkt_mma_tiler = self.mma_tiler\n self.kst_mma_tiler = self.mma_tiler\n self.tuw_mma_tiler = self.mma_tiler\n self.o_intra_mma_tiler = (chunk_size, head_dim, chunk_size)\n self.qs_mma_tiler = (chunk_size, head_dim, head_dim)\n self.update_s_mma_tiler = (head_dim, head_dim, chunk_size)\n\n self.epi_tile = (128, 128)\n\n self.cluster_shape_mnk = (1, 1, 1)\n\n self.buffer_align_bytes = 1024\n\n self.q_stage = 1\n self.one_stage = 1\n self.kv_stage = 1\n self.qk_stage = 2\n self.gate_stage = 1\n self.beta_stage = 1\n self.mma_cudacore_stage = 1\n self.mma_qk_stage = 2\n self.epi_stage = 1\n\n self.cudacore_warp_ids = (0, 1, 2, 3)\n self.mma_warp_id = 4\n self.load_warp_id = 5\n self.epilogue_warp_id = 6\n self.gb_warp_id = 7\n\n self.threads_per_warp = 32\n self.threads_per_cta = self.threads_per_warp * len(\n (\n *self.cudacore_warp_ids,\n self.mma_warp_id,\n self.load_warp_id,\n self.epilogue_warp_id,\n self.gb_warp_id,\n )\n )\n\n # TMEM configuration\n SM100_TMEM_CAPACITY_COLUMNS = 512\n self.tmem_alloc_cols = SM100_TMEM_CAPACITY_COLUMNS\n self.tmem_kkt_output = 0\n self.tmem_qkt_output = 384\n self.tmem_gate_qk = 384\n self.tmem_gate_q = 448 # 448\n self.tmem_k_input = 64\n self.tmem_kst_output = 256\n self.tmem_ivt_ss_l0_output = 448\n self.tmem_ivt_ts_l0_input = 320\n self.tmem_ivt_ts_l0_output = 448\n self.tmem_ivt_ss_l1_output = 320\n self.tmem_ivt_ts_l1_input = 320\n self.tmem_ivt_ts_l1_output = 256\n self.tmem_tuw_output = 256\n self.tmem_o_intra_output = 256\n self.tmem_o_inter_output = 256\n self.tmem_update_s_output = 128\n self.tmem_gamma = 256\n\n self.tmem_state = 128\n\n # Registers configuration\n self.num_regs_cudacore = 240\n self.num_regs_mma = 64\n self.num_regs_other = 64\n self.num_regs_gb = 64\n\n # Named barrier IDs\n self.cta_sync_bar_id = 0\n self.tmem_alloc_sync_bar_id = 1\n self.cudacore_mma_sync_bar_id = 2\n self.wg_sync_bar_id = 3\n self.epi_load_sync_bar_id = 4\n\n # Matrix inversion using TFloat32\n self.invert_type_ab = cutlass.TFloat32\n self.invert_acc_type = cutlass.Float32\n self.invert_mma_sub_l0_tiler = (64, 64, 32)\n self.invert_mma_sub_l1_tiler = (64, 64, 64)\n self.invert_mma_tiler = (128, 128, 64)\n self.invert_sub_stage = 1\n self.sub_stage = 9\n\n @staticmethod\n def can_implement(\n q_shape: Tuple[int, int, int, int] | Tuple[int, Tuple[int, ...], int, int],\n v_shape: Tuple[int, int, int, int] | Tuple[int, Tuple[int, ...], int, int],\n in_dtype: Type[cutlass.Numeric],\n out_dtype: Type[cutlass.Numeric],\n g_beta_dtype: Type[cutlass.Numeric],\n use_qk_l2norm_in_kernel: bool = False,\n ) -> bool:\n \"\"\"\n Check if the gdn can be implemented\n \"\"\"\n\n can_implement = True\n\n # Unpack parameters\n b, s_q, h_q, d = q_shape\n b_, _, h_v, d_ = v_shape\n\n if use_qk_l2norm_in_kernel:\n warnings.warn(\"use_qk_l2norm_in_kernel is not supported yet\", stacklevel=2)\n can_implement = False\n\n if b != b_:\n warnings.warn(\"q & k must have the same batch size\", stacklevel=2)\n can_implement = False\n\n if d != d_:\n warnings.warn(\"q & k must have the same head dimension\", stacklevel=2)\n can_implement = False\n\n # todo: maybe support more later.\n if d not in {128}:\n warnings.warn(\"head dimension must be 128\", stacklevel=2)\n can_implement = False\n\n if h_v % h_q != 0:\n warnings.warn(\"h_v must be divisible by h_q\", stacklevel=2)\n\n can_implement = False\n\n if isinstance(s_q, tuple) and len(s_q) != b:\n warnings.warn(\n \"variable_seqlen s_q must have the length of batch size\", stacklevel=2\n )\n can_implement = False\n\n if in_dtype not in {\n cutlass.BFloat16,\n cutlass.Float16,\n torch.float16,\n torch.bfloat16,\n }:\n warnings.warn(\n \"in_dtype must be BFloat16 or Float16 or torch.float16 or torch.bfloat16\",\n stacklevel=2,\n )\n can_implement = False\n\n if out_dtype not in {\n cutlass.BFloat16,\n cutlass.Float16,\n torch.float16,\n torch.bfloat16,\n }:\n warnings.warn(\n \"out_dtype must be BFloat16 or Float16 or torch.float16 or torch.bfloat16\",\n stacklevel=2,\n )\n can_implement = False\n\n if g_beta_dtype not in {cutlass.Float32, torch.float32}:\n warnings.warn(\n \"g_beta_dtype must be Float32 or torch.float32, but got {}\".format(\n g_beta_dtype\n ),\n stacklevel=2,\n )\n can_implement = False\n\n return can_implement\n\n @cute.kernel\n def kernel(\n self,\n qk_tiled_mma: cute.TiledMma,\n o_intra_tiled_mma: cute.TiledMma,\n o_intra_tiled_ts_mma_new: cute.TiledMma,\n qs_tiled_mma: cute.TiledMma,\n update_s_tiled_mma: cute.TiledMma,\n kkt_tiled_mma: cute.TiledMma,\n kst_tiled_mma: cute.TiledMma,\n fake_state_tiled_mma: cute.TiledMma,\n invert_sub_tiled_mma_ss_l0: cute.TiledMma,\n invert_sub_tiled_mma_ts_l0: cute.TiledMma,\n invert_sub_tiled_mma_ss_l1: cute.TiledMma,\n invert_sub_tiled_mma_ts_l1: cute.TiledMma,\n tuw_tiled_mma: cute.TiledMma,\n tma_atom_q: cute.CopyAtom,\n mQ_qdl: cute.Tensor,\n tma_atom_k: cute.CopyAtom,\n mK_kdl: cute.Tensor,\n tma_atom_v: cute.CopyAtom,\n mV_dkl: cute.Tensor,\n tma_atom_state_f32: Optional[cute.CopyAtom],\n mState_f32: Optional[cute.Tensor],\n gate: cute.Tensor,\n beta: cute.Tensor,\n O: cute.Tensor,\n tma_atom_state_output: Optional[cute.CopyAtom],\n mStateOutput: Optional[cute.Tensor],\n tma_atom_o_output: cute.CopyAtom,\n mO_qdl: cute.Tensor,\n cum_seqlen_q: Optional[cute.Tensor],\n q_smem_layout_staged: cute.ComposedLayout,\n k_smem_layout_staged: cute.ComposedLayout,\n qk_smem_layout_staged: cute.ComposedLayout,\n o_intra_smem_layout_staged_a: cute.ComposedLayout,\n o_intra_smem_layout_staged_b: cute.ComposedLayout,\n o_intra_smem_layout_staged_a_new: cute.ComposedLayout,\n qs_smem_layout_staged_a: cute.ComposedLayout,\n qs_smem_layout_staged_b: cute.ComposedLayout,\n update_s_smem_layout_staged_a: cute.ComposedLayout,\n update_s_smem_layout_staged_b: cute.ComposedLayout,\n state_smem_layout_staged: cute.ComposedLayout,\n state_smem_layout_f32_staged: cute.ComposedLayout,\n state_output_smem_layout_staged: cute.ComposedLayout,\n o_output_smem_layout_staged: cute.ComposedLayout,\n gate_smem_layout_staged: cute.Layout,\n beta_smem_layout_staged: cute.Layout,\n ivt_smem_layout: cute.Layout,\n sub_inner_smem_layout_staged: cute.ComposedLayout,\n invert_sub_smem_layout_staged_ss_l0_a: cute.ComposedLayout,\n invert_sub_smem_layout_staged_ss_l0_b: cute.ComposedLayout,\n invert_sub_smem_layout_staged_ts_l0_a: cute.ComposedLayout,\n invert_sub_smem_layout_staged_ts_l0_b: cute.ComposedLayout,\n invert_sub_smem_layout_staged_ss_l1_a: cute.ComposedLayout,\n invert_sub_smem_layout_staged_ss_l1_b: cute.ComposedLayout,\n invert_sub_smem_layout_staged_ts_l1_a: cute.ComposedLayout,\n invert_sub_smem_layout_staged_ts_l1_b: cute.ComposedLayout,\n tuw_smem_layout_staged_a: cute.ComposedLayout,\n tuw_smem_layout_staged_b: cute.ComposedLayout,\n v_smem_layout_staged_b: cute.ComposedLayout,\n scale: cutlass.Float32,\n tile_sched_params: GdnStaticTileSchedulerParams,\n ):\n \"\"\"Warp-specialized GDN kernel entry point.\"\"\"\n tidx, _, _ = cute.arch.thread_idx()\n warp_idx = cute.arch.make_warp_uniform(cute.arch.warp_idx())\n\n # Prefetch TMA descriptors\n if warp_idx == self.load_warp_id:\n cute.nvgpu.cpasync.prefetch_descriptor(tma_atom_q)\n cute.nvgpu.cpasync.prefetch_descriptor(tma_atom_k)\n cute.nvgpu.cpasync.prefetch_descriptor(tma_atom_v)\n cute.nvgpu.cpasync.prefetch_descriptor(tma_atom_o_output)\n if cutlass.const_expr(tma_atom_state_f32 is not None):\n cute.nvgpu.cpasync.prefetch_descriptor(tma_atom_state_f32)\n if cutlass.const_expr(tma_atom_state_output is not None):\n cute.nvgpu.cpasync.prefetch_descriptor(tma_atom_state_output)\n\n # Alloc\n smem = utils.SmemAllocator()\n storage = smem.allocate(self.shared_storage)\n\n load_qk_producer, load_qk_consumer = pipeline.PipelineTmaUmma.create(\n num_stages=self.qk_stage,\n producer_group=make_thread_cooperative_group(len([self.load_warp_id])),\n consumer_group=make_thread_cooperative_group(len([self.mma_warp_id])),\n tx_count=self.tma_copy_kv_bytes,\n barrier_storage=storage.load_qk_mbar_ptr.data_ptr(),\n ).make_participants()\n\n load_v_producer, load_v_consumer = pipeline.PipelineTmaAsync.create(\n num_stages=self.one_stage,\n producer_group=make_thread_cooperative_group(len([self.load_warp_id])),\n consumer_group=make_thread_cooperative_group(\n len(self.cudacore_warp_ids),\n ),\n tx_count=self.tma_copy_v_bytes,\n barrier_storage=storage.load_v_mbar_ptr.data_ptr(),\n ).make_participants()\n\n load_state_producer, load_state_consumer = pipeline.PipelineTmaAsync.create(\n num_stages=self.one_stage,\n producer_group=make_thread_cooperative_group(len([self.load_warp_id])),\n consumer_group=make_thread_cooperative_group(len(self.cudacore_warp_ids)),\n tx_count=self.tma_copy_state_f32_bytes,\n barrier_storage=storage.load_state_mbar_ptr.data_ptr(),\n ).make_participants()\n\n mma_qk_producer0, mma_qk_consumer0 = pipeline.PipelineUmmaAsync.create(\n num_stages=self.mma_qk_stage,\n producer_group=make_thread_cooperative_group(len([self.mma_warp_id])),\n consumer_group=make_thread_cooperative_group(\n self.threads_per_warp * len(self.cudacore_warp_ids)\n ),\n barrier_storage=storage.mma_qk_mbar_ptr0.data_ptr(),\n ).make_participants()\n\n mma_cudacore_producer0, mma_cudacore_consumer0 = (\n pipeline.PipelineUmmaAsync.create(\n num_stages=self.mma_cudacore_stage,\n producer_group=make_thread_cooperative_group(len([self.mma_warp_id])),\n consumer_group=make_thread_cooperative_group(\n self.threads_per_warp * len(self.cudacore_warp_ids)\n ),\n barrier_storage=storage.mma_cudacore_mbar_ptr0.data_ptr(),\n ).make_participants()\n )\n\n gb_w0_producer, gb_w0_consumer = pipeline.PipelineAsync.create(\n num_stages=self.gate_stage,\n producer_group=make_thread_cooperative_group(self.threads_per_warp),\n consumer_group=make_thread_cooperative_group(\n self.threads_per_warp * len(self.cudacore_warp_ids)\n ),\n barrier_storage=storage.gb_w0_mbar_ptr.data_ptr(),\n ).make_participants()\n\n epi_w0_producer, epi_w0_consumer = pipeline.PipelineAsync.create(\n num_stages=self.epi_stage,\n producer_group=make_thread_cooperative_group(self.threads_per_warp),\n consumer_group=make_thread_cooperative_group(\n self.threads_per_warp * len(self.cudacore_warp_ids)\n ),\n barrier_storage=storage.epi_w0_mbar_ptr.data_ptr(),\n ).make_participants()\n\n w0_epi_producer, w0_epi_consumer = pipeline.PipelineAsync.create(\n num_stages=self.epi_stage,\n producer_group=make_thread_cooperative_group(\n self.threads_per_warp * len(self.cudacore_warp_ids)\n ),\n consumer_group=make_thread_cooperative_group(self.threads_per_warp),\n barrier_storage=storage.w0_epi_mbar_ptr.data_ptr(),\n ).make_participants()\n\n tmem_dealloc_mbar_ptr = storage.tmem_dealloc_mbar_ptr.data_ptr()\n\n # tmem barrier init\n if warp_idx == self.gb_warp_id:\n cute.arch.mbarrier_init(\n tmem_dealloc_mbar_ptr,\n self.threads_per_warp * len((*self.cudacore_warp_ids,)),\n )\n cute.arch.mbarrier_init_fence()\n\n sQK = storage.sQK.get_tensor(\n qk_smem_layout_staged.outer, swizzle=qk_smem_layout_staged.inner\n )\n sQ = cute.make_tensor(\n cute.recast_ptr(\n sQK[None, None, None, 1].iterator,\n swizzle_=q_smem_layout_staged.inner,\n dtype=self.i_dtype,\n ),\n q_smem_layout_staged.outer,\n )\n sK = cute.make_tensor(\n cute.recast_ptr(\n sQK[None, None, None, 0].iterator,\n swizzle_=k_smem_layout_staged.inner,\n dtype=self.i_dtype,\n ),\n k_smem_layout_staged.outer,\n )\n sStateInput = cute.make_tensor(\n cute.recast_ptr(\n storage.sState.data_ptr(),\n swizzle_=state_smem_layout_staged.inner,\n dtype=self.i_dtype,\n ),\n state_smem_layout_staged.outer,\n )\n sV = cute.make_tensor(\n cute.recast_ptr(\n storage.sV.data_ptr(),\n swizzle_=v_smem_layout_staged_b.inner,\n dtype=self.i_dtype,\n ),\n v_smem_layout_staged_b.outer,\n )\n\n sGate = storage.sGate.get_tensor(gate_smem_layout_staged)\n sBeta = storage.sBeta.get_tensor(beta_smem_layout_staged)\n sGateCumsum = storage.sGateCumsum.get_tensor(\n cute.select(gate_smem_layout_staged, mode=[0, 1])\n )\n sSubInner = storage.sSubInner.get_tensor(sub_inner_smem_layout_staged)\n sInvertSubSSL0A = cute.make_tensor(\n cute.recast_ptr(\n sSubInner[None, None, None, 6].iterator,\n swizzle_=invert_sub_smem_layout_staged_ss_l0_a.inner,\n dtype=self.invert_type_ab,\n ),\n invert_sub_smem_layout_staged_ss_l0_a.outer,\n )\n\n sInvertSubSSL0B = cute.make_tensor(\n cute.recast_ptr(\n sSubInner[None, None, None, 7].iterator,\n swizzle_=invert_sub_smem_layout_staged_ss_l0_b.inner,\n dtype=self.invert_type_ab,\n ),\n invert_sub_smem_layout_staged_ss_l0_b.outer,\n )\n sInvertSubTSL0B = cute.make_tensor(\n cute.recast_ptr(\n sSubInner[None, None, None, 8].iterator,\n swizzle_=invert_sub_smem_layout_staged_ts_l0_b.inner,\n dtype=self.invert_type_ab,\n ),\n invert_sub_smem_layout_staged_ts_l0_b.outer,\n )\n sInvertSubSSL1A = cute.make_tensor(\n cute.recast_ptr(\n sSubInner[None, None, None, 0].iterator,\n swizzle_=invert_sub_smem_layout_staged_ss_l1_a.inner,\n dtype=self.invert_type_ab,\n ),\n invert_sub_smem_layout_staged_ss_l1_a.outer,\n )\n sInvertSubSSL1B = cute.make_tensor(\n cute.recast_ptr(\n sSubInner[None, None, None, 2].iterator,\n swizzle_=invert_sub_smem_layout_staged_ss_l1_b.inner,\n dtype=self.invert_type_ab,\n ),\n invert_sub_smem_layout_staged_ss_l1_b.outer,\n )\n sInvertSubTSL1B = cute.make_tensor(\n cute.recast_ptr(\n sSubInner[None, None, None, 6].iterator,\n swizzle_=invert_sub_smem_layout_staged_ts_l1_b.inner,\n dtype=self.invert_type_ab,\n ),\n invert_sub_smem_layout_staged_ts_l1_b.outer,\n )\n\n sInvertSubReg = cute.make_tensor(\n cute.recast_ptr(\n sSubInner[None, None, None, 4].iterator, dtype=self.invert_type_ab\n ),\n cute.make_layout(((4, 128), 8)),\n )\n\n sStateInputF32 = cute.make_tensor(\n cute.recast_ptr(\n sSubInner[None, None, None, 0].iterator,\n swizzle_=state_smem_layout_f32_staged.inner,\n dtype=self.state_dtype,\n ),\n state_smem_layout_f32_staged.outer,\n )\n sStateOutput = cute.make_tensor(\n cute.recast_ptr(\n sQK[None, None, None, 0].iterator,\n swizzle_=state_output_smem_layout_staged.inner,\n dtype=self.state_dtype,\n ),\n state_output_smem_layout_staged.outer,\n )\n\n sOIntraB = cute.make_tensor(\n cute.recast_ptr(\n sSubInner[None, None, None, 4].iterator,\n swizzle_=o_intra_smem_layout_staged_b.inner,\n dtype=self.i_dtype,\n ),\n o_intra_smem_layout_staged_b.outer,\n )\n sQSB = cute.make_tensor(\n cute.recast_ptr(\n storage.sState.data_ptr(),\n swizzle_=qs_smem_layout_staged_b.inner,\n dtype=self.i_dtype,\n ),\n qs_smem_layout_staged_b.outer,\n )\n\n sUpdateA = cute.make_tensor(\n cute.recast_ptr(\n sSubInner[None, None, None, 4].iterator,\n swizzle_=update_s_smem_layout_staged_a.inner,\n dtype=self.i_dtype,\n ),\n update_s_smem_layout_staged_a.outer,\n )\n sUpdateB = cute.make_tensor(\n cute.recast_ptr(\n sSubInner[None, None, None, 0].iterator,\n swizzle_=update_s_smem_layout_staged_b.inner,\n dtype=self.i_dtype,\n ),\n update_s_smem_layout_staged_b.outer,\n )\n\n sO = cute.make_tensor(\n cute.recast_ptr(\n storage.sState.data_ptr(),\n swizzle_=o_output_smem_layout_staged.inner,\n dtype=self.i_dtype,\n ),\n o_output_smem_layout_staged.outer,\n )\n sIvt = storage.sIvt.get_tensor(ivt_smem_layout)\n\n sTuwA = cute.make_tensor(\n cute.recast_ptr(\n sSubInner[None, None, None, 0].iterator,\n swizzle_=tuw_smem_layout_staged_a.inner,\n dtype=self.i_dtype,\n ),\n tuw_smem_layout_staged_a.outer,\n )\n sTuwB = cute.make_tensor(\n cute.recast_ptr(storage.sV.data_ptr(), dtype=self.k_dtype),\n tuw_smem_layout_staged_b,\n )\n sTuwAStore_layout = cute.make_layout(\n ((128, (4, 2)), 8), stride=((4, (1, 512)), 1024)\n )\n sTuwAStore = cute.make_tensor(\n cute.recast_ptr(sTuwA.iterator, dtype=cutlass.Float32), sTuwAStore_layout\n )\n\n if warp_idx == self.epilogue_warp_id:\n # Alloc tmem buffer\n tmem_alloc_cols = cutlass.Int32(self.tmem_alloc_cols)\n cute.arch.alloc_tmem(tmem_alloc_cols, storage.tmem_holding_buf)\n\n # Ensure visibility of local mbarrier inits and tmem alloc\n cute.arch.sync_threads()\n\n tmem_ptr = cute.arch.retrieve_tmem_ptr(\n self.acc_dtype,\n alignment=16,\n ptr_to_buffer_holding_addr=storage.tmem_holding_buf,\n )\n\n qk_thr_mma = qk_tiled_mma.get_slice(0) # default 1sm\n tSrQ = qk_thr_mma.make_fragment_A(sQK)\n tSrK = qk_thr_mma.make_fragment_B(sQK)\n qk_acc_shape = qk_thr_mma.partition_shape_C(\n (self.qk_mma_tiler[0], self.qk_mma_tiler[1])\n )\n tQKtQK_fake = qk_thr_mma.make_fragment_C(qk_acc_shape)\n tQKtQK = cute.make_tensor(tmem_ptr + self.tmem_qkt_output, tQKtQK_fake.layout)\n\n kkt_thr_mma = kkt_tiled_mma.get_slice(0) # default 1sm\n tArK = kkt_thr_mma.make_fragment_A(sQK)\n tArKT = kkt_thr_mma.make_fragment_B(sQK)\n kkt_acc_shape = kkt_thr_mma.partition_shape_C(\n (self.kkt_mma_tiler[0], self.kkt_mma_tiler[1])\n )\n\n fake_state_thr_mma = fake_state_tiled_mma.get_slice(0)\n\n kst_thr_mma = kst_tiled_mma.get_slice(0)\n tKSrK_0 = kst_thr_mma.make_fragment_A(sQK)\n tKSrST = kst_thr_mma.make_fragment_B(sStateInput)\n kst_acc_shape = kst_thr_mma.partition_shape_C(\n (self.kst_mma_tiler[0], self.kst_mma_tiler[1])\n )\n tKStKS_fake = kst_thr_mma.make_fragment_C(kst_acc_shape)\n tKStKS = cute.make_tensor(tmem_ptr + self.tmem_kst_output, tKStKS_fake.layout)\n # input smem A\n tKStK_layout = cute.composition(tKStKS.layout, cute.make_layout((128, 64)))\n tKtK = cute.make_tensor(tmem_ptr + self.tmem_k_input, tKStK_layout)\n\n invert_sub_thr_mma_ss_l0 = invert_sub_tiled_mma_ss_l0.get_slice(0)\n tSrD = invert_sub_thr_mma_ss_l0.make_fragment_A(sInvertSubSSL0A)\n tSrC = invert_sub_thr_mma_ss_l0.make_fragment_B(sInvertSubSSL0B)\n invert_sub_acc_shape = invert_sub_thr_mma_ss_l0.partition_shape_C(\n (self.invert_mma_sub_l0_tiler[0], self.invert_mma_sub_l0_tiler[1])\n )\n\n tKKTtKKT_fake = kkt_thr_mma.make_fragment_C(kkt_acc_shape)\n tKKTtKKT = cute.make_tensor(\n tmem_ptr + self.tmem_kkt_output, tKKTtKKT_fake.layout\n )\n\n tItSSL0_fake = invert_sub_thr_mma_ss_l0.make_fragment_C(invert_sub_acc_shape)\n tItSSL0 = cute.make_tensor(\n tmem_ptr + self.tmem_ivt_ss_l0_output, tItSSL0_fake.layout\n )\n\n # : ((128,128),1,1):((65536,1),0,0)\n tQgate_layout = cute.make_layout(((128, 64), 1, 1), stride=((65536, 1), 0, 0))\n tQgate = cute.make_tensor(tmem_ptr + self.tmem_gate_q, tQgate_layout)\n\n tGamma_layout = cute.make_layout(((128, 128), 1, 1), stride=((65536, 1), 0, 0))\n tGamma = cute.make_tensor(tmem_ptr + self.tmem_gamma, tGamma_layout)\n\n # tStage\n tStateF32_layout = cute.make_layout(\n ((128, 128), 1, 1), stride=((65536, 1), 0, 0)\n )\n tStateF32 = cute.make_tensor(tmem_ptr + self.tmem_state, tStateF32_layout)\n\n invert_sub_thr_mma_ts_l0 = invert_sub_tiled_mma_ts_l0.get_slice(0)\n tInrDCL0A_fake = invert_sub_thr_mma_ts_l0.make_fragment_A(\n invert_sub_smem_layout_staged_ts_l0_a.outer.shape\n )\n tInrDCL0A = cute.make_tensor(\n cute.recast_ptr(\n tmem_ptr,\n dtype=tInrDCL0A_fake.element_type,\n )\n + self.tmem_ivt_ts_l0_input,\n tInrDCL0A_fake.layout,\n )\n\n # input smem B\n tSrDCL0B = invert_sub_thr_mma_ts_l0.make_fragment_B(sInvertSubTSL0B)\n\n # output tmem C\n tItTSL0_fake = invert_sub_thr_mma_ts_l0.make_fragment_C(invert_sub_acc_shape)\n tItTSL0 = cute.make_tensor(\n tmem_ptr + self.tmem_ivt_ts_l0_output, tItTSL0_fake.layout\n )\n\n invert_sub_thr_mma_ss_l1 = invert_sub_tiled_mma_ss_l1.get_slice(0)\n tSrD_ivt_l1 = invert_sub_thr_mma_ss_l1.make_fragment_A(sInvertSubSSL1A)\n tSrC_ivt_l1 = invert_sub_thr_mma_ss_l1.make_fragment_B(sInvertSubSSL1B)\n invert_sub_acc_l1_shape = invert_sub_thr_mma_ss_l1.partition_shape_C(\n (self.invert_mma_sub_l1_tiler[0], self.invert_mma_sub_l1_tiler[1])\n )\n tCtAcc_ivt_l1_ss_fake = invert_sub_thr_mma_ss_l1.make_fragment_C(\n invert_sub_acc_l1_shape\n )\n tStO_ivt_l1_ss0 = cute.make_tensor(\n tmem_ptr + self.tmem_ivt_ss_l1_output, tCtAcc_ivt_l1_ss_fake.layout\n )\n\n invert_sub_thr_mma_ts_l1 = invert_sub_tiled_mma_ts_l1.get_slice(0)\n invert_acc_ts_l1_shape = invert_sub_thr_mma_ts_l1.partition_shape_C(\n (self.invert_mma_sub_l1_tiler[0], self.invert_mma_sub_l1_tiler[1])\n )\n # output tmem C\n tOtTSL1_fake = invert_sub_thr_mma_ts_l1.make_fragment_C(invert_acc_ts_l1_shape)\n tOtTSL1 = cute.make_tensor(\n tmem_ptr + self.tmem_ivt_ts_l1_output, tOtTSL1_fake.layout\n )\n\n tuw_thr_mma = tuw_tiled_mma.get_slice(0)\n # input smem A\n tTUWrA = tuw_thr_mma.make_fragment_A(sTuwA)\n # input smem B\n tTUWrB = tuw_thr_mma.make_fragment_B(sTuwB)\n # output tmem C\n tuw_acc_shape = tuw_thr_mma.partition_shape_C(\n (self.tuw_mma_tiler[0], self.tuw_mma_tiler[1])\n )\n tVtTUW_fake = tuw_thr_mma.make_fragment_C(tuw_acc_shape)\n tVtTUW = cute.make_tensor(tmem_ptr + self.tmem_tuw_output, tVtTUW_fake.layout)\n\n o_intra_thr_mma = o_intra_tiled_mma.get_slice(0)\n # input smem B\n tOIntrarB = o_intra_thr_mma.make_fragment_B(sOIntraB)\n # output tmem C\n o_intra_acc_shape = o_intra_thr_mma.partition_shape_C(\n (self.o_intra_mma_tiler[0], self.o_intra_mma_tiler[1])\n )\n\n o_intra_thr_mma_new = o_intra_tiled_ts_mma_new.get_slice(0)\n # input smem A\n tQKMtQKM_layout = cute.composition(tQKtQK.layout, cute.make_layout((128, 64)))\n tQKMtQKM = cute.make_tensor(tmem_ptr + self.tmem_gate_qk, tQKMtQKM_layout)\n\n update_s_thr_mma = update_s_tiled_mma.get_slice(0)\n tUpdateA = update_s_thr_mma.make_fragment_A(sUpdateA)\n tUpdateB = update_s_thr_mma.make_fragment_B(sUpdateB)\n update_s_acc_shape = update_s_thr_mma.partition_shape_C(\n (self.update_s_mma_tiler[0], self.update_s_mma_tiler[1])\n )\n tStUpdate_fake = update_s_thr_mma.make_fragment_C(update_s_acc_shape)\n tStUpdate = cute.make_tensor(\n tmem_ptr + self.tmem_update_s_output, tStUpdate_fake.layout\n )\n\n qs_thr_mma = qs_tiled_mma.get_slice(0)\n tQSB = qs_thr_mma.make_fragment_B(sQSB)\n qs_acc_shape = qs_thr_mma.partition_shape_C(\n (self.qs_mma_tiler[0], self.qs_mma_tiler[1])\n )\n tOintertQS_fake = qs_thr_mma.make_fragment_C(qs_acc_shape)\n tOintertQS = cute.make_tensor(\n tmem_ptr + self.tmem_o_inter_output, tOintertQS_fake.layout\n )\n\n loop_count = cute.ceil_div(mO_qdl.shape[0], self.cta_tiler[0])\n\n # ///////////////////////////////////////////////////////////////////////////////\n # Load Gate Beta\n # ///////////////////////////////////////////////////////////////////////////////\n if warp_idx == self.gb_warp_id:\n cute.arch.setmaxregister_decrease(self.num_regs_gb)\n tile_sched = create_gdn_static_tile_scheduler(\n tile_sched_params, cute.arch.block_idx(), cute.arch.grid_dim()\n )\n work_tile = tile_sched.initial_work_tile_info()\n lane_id = tidx % 32\n\n while work_tile.is_valid_tile:\n curr_block_coord = work_tile.tile_idx\n\n batch_coord = curr_block_coord[2][1]\n continue_cond = False\n cuseqlen_q = Int32(0)\n seqlen_q = mQ_qdl.shape[0]\n\n head_coord = curr_block_coord[2][0]\n\n if cutlass.const_expr(cum_seqlen_q is not None):\n cuseqlen_q = cum_seqlen_q[batch_coord]\n seqlen_q = cum_seqlen_q[batch_coord + 1] - cuseqlen_q\n continue_cond = (\n not GdnStaticTileScheduler.check_valid_work_for_seqlen_q(\n self.cta_tiler[0],\n curr_block_coord[0],\n seqlen_q,\n )\n )\n\n if not continue_cond:\n batch_base = cuseqlen_q\n gate_vals = cute.make_rmem_tensor((4), cutlass.Float32)\n beta_vals = cute.make_rmem_tensor((4), cutlass.Float32)\n\n for i in cutlass.range(loop_count, unroll=1):\n # step1: read gate beta\n for it in cutlass.range_constexpr(4):\n curr_idx = i * 128 + it * 32 + lane_id\n if curr_idx < seqlen_q:\n if cutlass.const_expr(cum_seqlen_q is not None):\n gate_vals[it] = gate[\n batch_base + curr_idx, 0, (head_coord, 0)\n ]\n beta_vals[it] = beta[\n batch_base + curr_idx, 0, (head_coord, 0)\n ]\n else:\n gate_vals[it] = gate[\n curr_idx, 0, (head_coord, batch_coord)\n ]\n beta_vals[it] = beta[\n curr_idx, 0, (head_coord, batch_coord)\n ]\n else:\n gate_vals[it] = cutlass.Float32(0)\n beta_vals[it] = cutlass.Float32(0)\n # step2: write to smem\n sGate0 = sGate[None, None, 0] # assume only one stage\n sBeta0 = sBeta[None, None, 0]\n\n gb_handle = gb_w0_producer.acquire_and_advance()\n\n for it in cutlass.range_constexpr(4):\n sGate0[it * 32 + lane_id] = gate_vals[it]\n sBeta0[it * 32 + lane_id] = beta_vals[it]\n\n # step3: notify cuda core wg\n gb_handle.commit()\n\n tile_sched.advance_to_next_work()\n work_tile = tile_sched.get_current_work()\n\n # ///////////////////////////////////////////////////////////////////////////////\n # Epilogue: Store Output\n # ///////////////////////////////////////////////////////////////////////////////\n if warp_idx == self.epilogue_warp_id:\n cute.arch.setmaxregister_decrease(self.num_regs_other)\n tile_sched = create_gdn_static_tile_scheduler(\n tile_sched_params, cute.arch.block_idx(), cute.arch.grid_dim()\n )\n work_tile = tile_sched.initial_work_tile_info()\n while work_tile.is_valid_tile:\n curr_block_coord = work_tile.tile_idx\n\n batch_coord = curr_block_coord[2][1]\n continue_cond = False\n cuseqlen_q = Int32(0)\n seqlen_q = mQ_qdl.shape[0]\n\n if cutlass.const_expr(cum_seqlen_q is not None):\n cuseqlen_q = cum_seqlen_q[batch_coord]\n seqlen_q = cum_seqlen_q[batch_coord + 1] - cuseqlen_q\n continue_cond = (\n not GdnStaticTileScheduler.check_valid_work_for_seqlen_q(\n self.cta_tiler[0],\n curr_block_coord[0],\n seqlen_q,\n )\n )\n\n if not continue_cond:\n curr_block_coord_o = curr_block_coord\n mO_qdl_ = mO_qdl\n if cutlass.const_expr(cum_seqlen_q is not None):\n logical_offset_mO = (\n mO_qdl_.shape[0] - seqlen_q,\n 0,\n (0, cuseqlen_q + seqlen_q),\n )\n mO_qdl_ = cute.domain_offset(logical_offset_mO, mO_qdl_)\n curr_block_coord_o = (\n curr_block_coord[0],\n curr_block_coord[1],\n (curr_block_coord[2][0], 0),\n )\n\n gO_mnl = cute.flat_divide(\n mO_qdl_, cute.select(self.mma_tiler, mode=[0, 1])\n )\n tOsO, tOgO_qdl = cute.nvgpu.cpasync.tma_partition(\n tma_atom_o_output,\n 0,\n cute.make_layout(1),\n cute.group_modes(sO, 0, 2),\n cute.group_modes(gO_mnl, 0, 2),\n )\n tQgO = tOgO_qdl[None, None, 0, curr_block_coord_o[2]]\n w0_handle = epi_w0_producer.acquire_and_advance()\n w0_handle.commit()\n\n for i in cutlass.range(loop_count, unroll=1):\n w0_handle = epi_w0_producer.acquire_and_advance()\n cute.copy(tma_atom_o_output, tOsO[None, 0], tQgO[None, i])\n\n cute.arch.cp_async_bulk_commit_group()\n\n # Ensure O0 buffer is ready to be released\n cute.arch.cp_async_bulk_wait_group(0, read=True)\n\n w0_handle.commit()\n\n if cutlass.const_expr(tma_atom_state_output is not None):\n gStateOutput = cute.flat_divide(\n mStateOutput,\n cute.select(self.update_s_mma_tiler, mode=[0, 1]),\n )\n tSsS, tSgS_vkl = cute.nvgpu.cpasync.tma_partition(\n tma_atom_state_output,\n 0, # no multicast\n cute.make_layout(1),\n cute.group_modes(sStateOutput, 0, 2),\n cute.group_modes(gStateOutput, 0, 4),\n )\n tSgS = tSgS_vkl[None, curr_block_coord[2]]\n w0_epi_handle = w0_epi_consumer.wait_and_advance()\n cute.copy(\n tma_atom_state_output,\n tSsS[None, 0], # only 1 stage\n tSgS[None],\n )\n cute.arch.cp_async_bulk_commit_group()\n cute.arch.cp_async_bulk_wait_group(0, read=True)\n w0_epi_handle.release()\n\n tile_sched.advance_to_next_work()\n work_tile = tile_sched.get_current_work()\n\n # The smem is reused, ensuring the State Output store is complete\n if cutlass.const_expr(\n tma_atom_state_output is not None and self.is_persistent\n ):\n cute.arch.barrier_arrive(\n barrier_id=self.epi_load_sync_bar_id,\n number_of_threads=self.threads_per_warp * 2,\n )\n # ///////////////////////////////////////////////////////////////////////////////\n # LOAD: tma load QKVS\n # ///////////////////////////////////////////////////////////////////////////////\n if warp_idx == self.load_warp_id:\n cute.arch.setmaxregister_decrease(self.num_regs_other)\n\n tile_sched = create_gdn_static_tile_scheduler(\n tile_sched_params, cute.arch.block_idx(), cute.arch.grid_dim()\n )\n work_tile = tile_sched.initial_work_tile_info()\n while work_tile.is_valid_tile:\n curr_block_coord = work_tile.tile_idx\n continue_cond = False\n cuseqlen_q = Int32(0)\n seqlen_q = mQ_qdl.shape[0]\n batch_coord = curr_block_coord[2][1]\n\n if cutlass.const_expr(cum_seqlen_q is not None):\n cuseqlen_q = cum_seqlen_q[batch_coord]\n seqlen_q = cum_seqlen_q[batch_coord + 1] - cuseqlen_q\n continue_cond = (\n not GdnStaticTileScheduler.check_valid_work_for_seqlen_q(\n self.cta_tiler[0],\n curr_block_coord[0],\n seqlen_q,\n )\n )\n\n if not continue_cond:\n mQ_qdl_ = mQ_qdl\n mK_kdl_ = mK_kdl\n mV_dkl_ = mV_dkl\n curr_block_coord_q = curr_block_coord\n curr_block_coord_kv = curr_block_coord\n curr_block_coord_state = curr_block_coord\n\n if cutlass.const_expr(cum_seqlen_q is not None):\n logical_offset_mQ = (\n cuseqlen_q,\n 0,\n (0, 0),\n )\n mQ_qdl_ = cute.domain_offset(logical_offset_mQ, mQ_qdl)\n curr_block_coord_q = (\n curr_block_coord[0],\n curr_block_coord[1],\n (curr_block_coord[2][0], Int32(0)),\n )\n logical_offset_mK = (\n cuseqlen_q,\n 0,\n (0, 0),\n )\n logical_offset_mV = (\n 0,\n cuseqlen_q,\n (0, 0),\n )\n mK_kdl_ = cute.domain_offset(logical_offset_mK, mK_kdl)\n mV_dkl_ = cute.domain_offset(logical_offset_mV, mV_dkl)\n curr_block_coord_kv = (\n curr_block_coord[0],\n curr_block_coord[1],\n (curr_block_coord[2][0], Int32(0)),\n )\n\n gQ_qdl = cute.flat_divide(\n mQ_qdl_, cute.select(self.qk_mma_tiler, mode=[0, 2])\n )\n tSgQ_qdl = qk_thr_mma.partition_A(gQ_qdl)\n\n tQsQ, tQgQ_qdl = cute.nvgpu.cpasync.tma_partition(\n tma_atom_q,\n 0, # no multicast\n cute.make_layout(1),\n cute.group_modes(sQK, 0, 3),\n cute.group_modes(tSgQ_qdl, 0, 3),\n )\n tQgQ = tQgQ_qdl[None, None, 0, curr_block_coord_q[2]]\n\n gK_kdl = cute.flat_divide(\n mK_kdl_, cute.select(self.qk_mma_tiler, mode=[1, 2])\n )\n tSgK_kdl = qk_thr_mma.partition_B(gK_kdl)\n tKsK, tKgK_kdl = cute.nvgpu.cpasync.tma_partition(\n tma_atom_k,\n 0, # no multicast\n cute.make_layout(1),\n cute.group_modes(sQK, 0, 3),\n cute.group_modes(tSgK_kdl, 0, 3),\n )\n tKgK = tKgK_kdl[None, None, 0, curr_block_coord_kv[2]]\n\n gV_kdl = cute.flat_divide(\n mV_dkl_, cute.select(self.tuw_mma_tiler, mode=[1, 2])\n )\n tSgV_kdl = tuw_thr_mma.partition_B(gV_kdl)\n tVsV, tVgV_kdl = cute.nvgpu.cpasync.tma_partition(\n tma_atom_v,\n 0, # no multicast\n cute.make_layout(1),\n cute.group_modes(sV, 0, 3),\n cute.group_modes(tSgV_kdl, 0, 3),\n )\n tVgV = tVgV_kdl[None, 0, None, curr_block_coord_kv[2]]\n\n if cutlass.const_expr(tma_atom_state_f32 is not None):\n gStateF32 = cute.flat_divide(\n mState_f32, cute.select(self.kst_mma_tiler, mode=[1, 2])\n )\n tKSgStateF32 = fake_state_thr_mma.partition_B(gStateF32)\n tSsSF32, tSgSF32_kdl = cute.nvgpu.cpasync.tma_partition(\n tma_atom_state_f32,\n 0, # no multicast\n cute.make_layout(1),\n cute.group_modes(sStateInputF32, 0, 3),\n cute.group_modes(tKSgStateF32, 0, 3),\n )\n tSgSF32 = tSgSF32_kdl[None, None, 0, curr_block_coord_state[2]]\n state_f32_handle0 = load_state_producer.acquire_and_advance()\n cute.copy(\n tma_atom_state_f32,\n tSgSF32[None, 0],\n tSsSF32[None, state_f32_handle0.index],\n tma_bar_ptr=state_f32_handle0.barrier,\n )\n\n for i in cutlass.range(loop_count, unroll=1):\n w0_coord = i\n k0_handle = load_qk_producer.acquire_and_advance()\n cute.copy(\n tma_atom_k,\n tKgK[None, w0_coord],\n tKsK[None, k0_handle.index],\n tma_bar_ptr=k0_handle.barrier,\n )\n\n q_handle = load_qk_producer.acquire_and_advance()\n cute.copy(\n tma_atom_q,\n tQgQ[None, w0_coord],\n tQsQ[None, q_handle.index],\n tma_bar_ptr=q_handle.barrier,\n )\n\n v_handle0 = load_v_producer.acquire_and_advance()\n cute.copy(\n tma_atom_v,\n tVgV[None, w0_coord],\n tVsV[None, v_handle0.index],\n tma_bar_ptr=v_handle0.barrier,\n )\n\n tile_sched.advance_to_next_work()\n work_tile = tile_sched.get_current_work()\n\n if cutlass.const_expr(\n tma_atom_state_output is not None and self.is_persistent\n ):\n cute.arch.barrier(\n barrier_id=self.epi_load_sync_bar_id,\n number_of_threads=self.threads_per_warp * 2,\n )\n # dealloc tmem buffer\n cute.arch.relinquish_tmem_alloc_permit()\n cute.arch.mbarrier_wait(tmem_dealloc_mbar_ptr, 0)\n tmem_alloc_cols = Int32(self.tmem_alloc_cols)\n # Retrieving tmem ptr and make acc\n tmem_ptr = cute.arch.retrieve_tmem_ptr(\n cutlass.Float32,\n alignment=16,\n ptr_to_buffer_holding_addr=storage.tmem_holding_buf,\n )\n cute.arch.dealloc_tmem(tmem_ptr, tmem_alloc_cols)\n\n # ///////////////////////////////////////////////////////////////////////////////\n # MMA: mma warp\n # ///////////////////////////////////////////////////////////////////////////////\n if warp_idx == self.mma_warp_id:\n cute.arch.setmaxregister_decrease(self.num_regs_mma)\n\n tile_sched = create_gdn_static_tile_scheduler(\n tile_sched_params, cute.arch.block_idx(), cute.arch.grid_dim()\n )\n work_tile = tile_sched.initial_work_tile_info()\n\n tSrDC_ivt_l1_fake = invert_sub_thr_mma_ts_l1.make_fragment_A(\n invert_sub_smem_layout_staged_ts_l1_a.outer.shape\n )\n tSrDC_ivt_l1 = cute.make_tensor(\n cute.recast_ptr(\n tmem_ptr,\n dtype=tSrDC_ivt_l1_fake.element_type,\n )\n + self.tmem_ivt_ts_l1_input,\n tSrDC_ivt_l1_fake.layout,\n )\n tSrA_ivt_l1 = invert_sub_thr_mma_ts_l1.make_fragment_B(sInvertSubTSL1B)\n\n tOrP = o_intra_thr_mma_new.make_fragment_A(\n o_intra_smem_layout_staged_a_new.outer\n )\n tOrP0 = cute.make_tensor(\n cute.recast_ptr(\n tmem_ptr,\n dtype=tOrP.element_type,\n )\n + self.tmem_gate_qk * 2,\n tOrP.layout,\n )\n\n tQSA = o_intra_thr_mma_new.make_fragment_A(qs_smem_layout_staged_a.outer)\n tQSA0 = cute.make_tensor(\n cute.recast_ptr(\n tmem_ptr,\n dtype=tQSA.element_type,\n )\n + self.tmem_gate_q * 2,\n tQSA.layout,\n )\n\n while work_tile.is_valid_tile:\n curr_block_coord = work_tile.tile_idx\n continue_cond = False\n\n if not continue_cond:\n for _i in cutlass.range(loop_count, unroll=1):\n k_handle0 = load_qk_consumer.wait_and_advance()\n qk_handle0 = mma_qk_producer0.acquire_and_advance()\n\n kkt_tiled_mma = self.exec_mma(\n kkt_tiled_mma,\n tKKTtKKT,\n tArK,\n tArKT,\n k_handle0.index,\n k_handle0.index,\n )\n\n qk_handle0.commit()\n\n q_handle = load_qk_consumer.wait_and_advance()\n\n qk_handle1 = mma_qk_producer0.acquire_and_advance()\n\n qk_tiled_mma = self.exec_mma(\n qk_tiled_mma,\n tQKtQK,\n tSrQ,\n tSrK,\n q_handle.index,\n k_handle0.index,\n )\n\n qk_handle1.commit()\n\n cs_handle = mma_cudacore_producer0.acquire_and_advance()\n cute.arch.barrier(\n barrier_id=self.cudacore_mma_sync_bar_id,\n number_of_threads=self.threads_per_warp * 5,\n )\n\n kst_tiled_mma = self.exec_mma(\n kst_tiled_mma,\n tKStKS,\n tKSrK_0,\n tKSrST,\n 0,\n 0,\n )\n\n cs_handle.commit()\n\n cs_handle = mma_cudacore_producer0.acquire_and_advance()\n\n invert_sub_tiled_mma_ss_l0 = self.exec_mma(\n invert_sub_tiled_mma_ss_l0,\n tItSSL0,\n tSrD,\n tSrC,\n 0,\n 0,\n )\n\n cs_handle.commit()\n\n c0_handle = mma_cudacore_producer0.acquire_and_advance()\n\n invert_sub_tiled_mma_ts_l0 = self.exec_mma(\n invert_sub_tiled_mma_ts_l0,\n tItTSL0,\n tInrDCL0A,\n tSrDCL0B,\n 0,\n 0,\n )\n\n c0_handle.commit()\n\n c0_handle = mma_cudacore_producer0.acquire_and_advance()\n\n invert_sub_tiled_mma_ss_l1 = self.exec_mma(\n invert_sub_tiled_mma_ss_l1,\n tStO_ivt_l1_ss0,\n tSrD_ivt_l1,\n tSrC_ivt_l1,\n 0,\n 0,\n )\n\n c0_handle.commit()\n\n c0_handle = mma_cudacore_producer0.acquire_and_advance()\n\n k_handle0.release()\n\n invert_sub_tiled_mma_ts_l1 = self.exec_mma(\n invert_sub_tiled_mma_ts_l1,\n tOtTSL1,\n tSrDC_ivt_l1,\n tSrA_ivt_l1,\n 0,\n 0,\n )\n\n c0_handle.commit()\n\n c0_handle = mma_cudacore_producer0.acquire_and_advance()\n\n tuw_tiled_mma = self.exec_mma(\n tuw_tiled_mma,\n tVtTUW,\n tTUWrA,\n tTUWrB,\n 0,\n 0,\n )\n\n c0_handle.commit()\n c0_handle = mma_cudacore_producer0.acquire_and_advance()\n\n q_handle.release()\n\n tCtAcc_o_intra_acc_shape_fake = o_intra_thr_mma.make_fragment_C(\n o_intra_acc_shape\n )\n tStO_o_intra0 = cute.make_tensor(\n tmem_ptr + self.tmem_o_intra_output,\n tCtAcc_o_intra_acc_shape_fake.layout,\n )\n\n o_intra_tiled_ts_mma_new = self.exec_mma(\n o_intra_tiled_ts_mma_new,\n tStO_o_intra0,\n tOrP0,\n tOIntrarB,\n 0,\n 0,\n )\n\n qs_tiled_mma = self.exec_mma(\n qs_tiled_mma,\n tOintertQS,\n tQSA0,\n tQSB,\n 0,\n 0,\n True,\n )\n\n c0_handle.commit()\n c0_handle = mma_cudacore_producer0.acquire_and_advance()\n\n update_s_tiled_mma = self.exec_mma(\n update_s_tiled_mma,\n tStUpdate,\n tUpdateA,\n tUpdateB,\n 0,\n 0,\n True,\n )\n\n c0_handle.commit()\n\n tile_sched.advance_to_next_work()\n work_tile = tile_sched.get_current_work()\n # End of persistent scheduler loop\n # ///////////////////////////////////////////////////////////////////////////////\n # Mainloop: mainloop warp group\n # ///////////////////////////////////////////////////////////////////////////////\n if warp_idx < 4:\n cute.arch.setmaxregister_increase(self.num_regs_cudacore)\n\n tile_sched = create_gdn_static_tile_scheduler(\n tile_sched_params, cute.arch.block_idx(), cute.arch.grid_dim()\n )\n work_tile = tile_sched.initial_work_tile_info()\n\n while work_tile.is_valid_tile:\n curr_block_coord = work_tile.tile_idx\n batch_coord = curr_block_coord[2][1]\n continue_cond = False\n if not continue_cond:\n gO_mnl = cute.flat_divide(\n O, cute.select(self.mma_tiler, mode=[0, 1])\n )\n # Use input state\n if cutlass.const_expr(tma_atom_state_f32 is not None):\n load_state_consumer.wait_and_advance()\n self.init_state_from_smem(\n kst_thr_mma,\n tStateF32,\n sStateInputF32,\n )\n load_state_consumer.release()\n else:\n self.init_state_zeros(\n kst_thr_mma,\n tStateF32,\n )\n\n # Arguments\n atom_args = (\n kkt_thr_mma,\n kst_thr_mma,\n qk_thr_mma,\n qs_thr_mma,\n )\n tensor_args = (\n sGate,\n sBeta,\n sGateCumsum,\n sStateInput,\n sIvt,\n sQ,\n sK,\n sV,\n sO,\n sInvertSubReg,\n sInvertSubSSL0A,\n sInvertSubSSL0B,\n sInvertSubSSL1B,\n sInvertSubTSL0B,\n sInvertSubSSL1A,\n sInvertSubTSL1B,\n sTuwAStore,\n sTuwA,\n sOIntraB,\n sUpdateB,\n tGamma,\n tKKTtKKT,\n tQKtQK,\n tQKMtQKM,\n tKtK,\n tKStKS,\n tItTSL0,\n tInrDCL0A,\n tOtTSL1,\n tVtTUW,\n tOintertQS,\n tItSSL0,\n tStateF32,\n tQgate,\n )\n pipeline_args = (\n gb_w0_consumer,\n epi_w0_consumer,\n mma_qk_consumer0,\n mma_cudacore_consumer0,\n load_v_consumer,\n )\n\n # Corner case\n tail_count = mO_qdl.shape[0] % self.cta_tiler[0]\n\n if tail_count == 0:\n value_args = (\n scale,\n loop_count,\n 0,\n )\n (\n gb_w0_consumer,\n epi_w0_consumer,\n mma_qk_consumer0,\n mma_cudacore_consumer0,\n load_v_consumer,\n ) = self.main_loop(\n value_args,\n atom_args,\n tensor_args,\n pipeline_args,\n )\n else:\n value_args = (\n scale,\n loop_count - 1,\n 0,\n )\n (\n gb_w0_consumer,\n epi_w0_consumer,\n mma_qk_consumer0,\n mma_cudacore_consumer0,\n load_v_consumer,\n ) = self.main_loop(\n value_args,\n atom_args,\n tensor_args,\n pipeline_args,\n )\n pipeline_args = (\n gb_w0_consumer,\n epi_w0_consumer,\n mma_qk_consumer0,\n mma_cudacore_consumer0,\n load_v_consumer,\n )\n value_args = (\n scale,\n 1,\n loop_count - 1,\n )\n (\n gb_w0_consumer,\n epi_w0_consumer,\n mma_qk_consumer0,\n mma_cudacore_consumer0,\n load_v_consumer,\n ) = self.main_loop(\n value_args,\n atom_args,\n tensor_args,\n pipeline_args,\n True,\n tail_count=tail_count,\n )\n\n # Output state\n if cutlass.const_expr(tma_atom_state_output is not None):\n w0_epi_handle = w0_epi_producer.acquire_and_advance()\n self.store_state_to_smem(\n tStUpdate, sStateOutput, update_s_thr_mma\n )\n w0_epi_handle.commit()\n\n w0_handle = epi_w0_consumer.wait_and_advance()\n w0_handle.release()\n\n tile_sched.advance_to_next_work()\n work_tile = tile_sched.get_current_work()\n\n cute.arch.mbarrier_arrive(tmem_dealloc_mbar_ptr)\n\n @cute.jit\n def main_loop(\n self,\n value_args: tuple,\n atom_args: tuple,\n tensor_args: tuple,\n pipeline_args: tuple,\n need_mask: cutlass.Constexpr[cutlass.Boolean] = False,\n tail_count: Int32 = 128,\n ) -> Tuple[\n pipeline.PipelineConsumer,\n pipeline.PipelineConsumer,\n pipeline.PipelineConsumer,\n pipeline.PipelineConsumer,\n pipeline.PipelineConsumer,\n ]:\n \"\"\"Per-chunk mainloop executed by cudacore warps (0-3).\"\"\"\n tidx, _, _ = cute.arch.thread_idx()\n\n (\n scale,\n loop_count,\n loop_base,\n ) = value_args\n\n (\n kkt_thr_mma,\n kst_thr_mma,\n qk_thr_mma,\n qs_thr_mma,\n ) = atom_args\n\n (\n sGate,\n sBeta,\n sGateCumsum,\n sStateInput,\n sIvt,\n sQ,\n sK,\n sV,\n sO,\n sInvertSubReg,\n sInvertSubSSL0A,\n sInvertSubSSL0B,\n sInvertSubSSL1B,\n sInvertSubTSL0B,\n sInvertSubSSL1A,\n sInvertSubTSL1B,\n sTuwAStore,\n sTuwA,\n sOIntraB,\n sUpdateB,\n tGamma,\n tKKTtKKT,\n tQKtQK,\n tQKMtQKM,\n tKtK,\n tKStKS,\n tItTSL0,\n tInrDCL0A,\n tOtTSL1,\n tVtTUW,\n tOintertQS,\n tItSSL0,\n tStateF32,\n tQgate,\n ) = tensor_args\n\n (\n gb_w0_consumer,\n epi_w0_consumer,\n mma_qk_consumer0,\n mma_cudacore_consumer0,\n load_v_consumer,\n ) = pipeline_args\n\n for _i in cutlass.range(loop_base, loop_base + loop_count, unroll=1):\n gb_handle = gb_w0_consumer.wait_and_advance()\n sGate0 = sGate[None, None, gb_handle.index]\n sBeta0 = sBeta[None, None, gb_handle.index]\n tval = self.chunk_local_cumsum(sGate0, sGateCumsum, self.wg_sync_bar_id)\n beta_val = sBeta0[tidx]\n gb_handle.release()\n\n self.compute_gamma_tmem(\n tval,\n sGateCumsum,\n kkt_thr_mma,\n tGamma,\n self.wg_sync_bar_id,\n need_mask,\n tail_count,\n )\n qk_handle0 = mma_qk_consumer0.wait_and_advance()\n\n self.apply_gamma_beta(\n kkt_thr_mma,\n sIvt,\n tKKTtKKT,\n beta_val,\n tGamma,\n )\n\n gate_tail = (\n sGateCumsum[tail_count - 1]\n if cutlass.const_expr(need_mask)\n else sGateCumsum[127]\n )\n w0_handle = epi_w0_consumer.wait_and_advance()\n self.load_state_apply_gate(\n kst_thr_mma,\n tStateF32,\n sStateInput,\n gate_tail,\n )\n cute.arch.fence_proxy(\n cute.arch.ProxyKind.async_shared,\n space=cute.arch.SharedSpace.shared_cta,\n )\n\n qk_handle1 = mma_qk_consumer0.wait_and_advance()\n self.load_qk_epi(\n qk_thr_mma, tQKtQK, tQKMtQKM, tGamma, need_mask, tail_count\n )\n\n cute.arch.barrier_arrive(\n barrier_id=self.cudacore_mma_sync_bar_id,\n number_of_threads=self.threads_per_warp * 5,\n )\n\n reverse_result = cute.make_rmem_tensor((32, 1), self.acc_dtype)\n\n self.reverse_smem_sub(reverse_result, sIvt)\n\n self.store_ivt_smem_l0_ss_a(\n reverse_result,\n sInvertSubReg,\n sInvertSubSSL0A,\n )\n\n self.store_ivt_smem_l0_ss_b(\n kkt_thr_mma,\n tKKTtKKT,\n sInvertSubSSL0B,\n )\n\n c0_handle = mma_cudacore_consumer0.wait_and_advance()\n c0_handle.release()\n v_handle0 = load_v_consumer.wait_and_advance()\n\n tval_exp = cute.math.exp(tval)\n self.get_uw_b(\n kst_thr_mma, tKStKS, tval_exp, beta_val, sV, need_mask, tail_count\n )\n self.store_ivt_p1(\n sInvertSubReg,\n sInvertSubTSL0B,\n )\n\n c0_handle = mma_cudacore_consumer0.wait_and_advance()\n self.load_ivt_ss_l0(tItSSL0, tInrDCL0A) # debug\n c0_handle.release()\n self.store_ivt_smem_l1_ss_b(\n kkt_thr_mma,\n tKKTtKKT,\n sInvertSubSSL1B,\n )\n\n self.store_ivt_p2(\n sInvertSubReg,\n sInvertSubSSL1A,\n )\n\n c0_handle = mma_cudacore_consumer0.wait_and_advance()\n\n self.load_ivt_ts_l0(\n tItTSL0,\n sInvertSubSSL1A,\n sInvertSubTSL1B,\n )\n\n c0_handle.release()\n\n self.store_k_epi(kkt_thr_mma, sK, tKtK, need_mask, tail_count)\n self.store_ivt_p3(\n sInvertSubReg,\n sInvertSubTSL1B,\n )\n\n c0_handle = mma_cudacore_consumer0.wait_and_advance()\n c0_handle.release()\n self.save_tmem(tItTSL0, sTuwAStore)\n self.store_ivt_ad(sInvertSubReg, sTuwA)\n self.store_ivt_c(sTuwAStore)\n\n c0_handle = mma_cudacore_consumer0.wait_and_advance()\n self.load_ivt_result(tOtTSL1, sTuwAStore)\n c0_handle.release()\n\n self.load_q_epi(qk_thr_mma, sQ, tQgate, tval_exp, need_mask, tail_count)\n cute.arch.fence_proxy(\n cute.arch.ProxyKind.async_shared,\n space=cute.arch.SharedSpace.shared_cta,\n )\n\n c0_handle = mma_cudacore_consumer0.wait_and_advance()\n v_handle0.release()\n self.load_v(tVtTUW, sOIntraB)\n c0_handle.release()\n self.load_k(tKtK, sUpdateB, gate_tail, tval)\n c0_handle = mma_cudacore_consumer0.wait_and_advance()\n qk_handle0.release()\n c0_handle.release()\n self.store_o_smem(tOintertQS, sO, qs_thr_mma, scale)\n\n w0_handle.release()\n qk_handle1.release()\n c0_handle = mma_cudacore_consumer0.wait_and_advance()\n c0_handle.release()\n\n return (\n gb_w0_consumer,\n epi_w0_consumer,\n mma_qk_consumer0,\n mma_cudacore_consumer0,\n load_v_consumer,\n )\n\n @cute.jit\n def exec_mma(\n self,\n tiled_mma,\n tCtAcc,\n tCrA,\n tCrB,\n a_consumer_index,\n b_consumer_index,\n setAcc: bool = False,\n ):\n \"\"\"Issue a tcgen05 GEMM.\"\"\"\n for kphase_idx in cutlass.range(cute.size(tCrB, mode=[2]), unroll_all=True):\n # set accu = 1\n tiled_mma.set(\n tcgen05.Field.ACCUMULATE,\n cutlass.Boolean(kphase_idx != 0 or setAcc),\n )\n cute.gemm(\n tiled_mma,\n tCtAcc,\n tCrA[None, None, kphase_idx, a_consumer_index],\n tCrB[None, None, kphase_idx, b_consumer_index],\n tCtAcc,\n )\n return tiled_mma\n\n @cute.jit\n def get_uw_b(\n self,\n thr_mma: cute.ThrMma,\n tIn: cute.Tensor,\n gate_val: cutlass.Float32,\n beta_val: cutlass.Float32,\n sV: cute.Tensor,\n mask: cutlass.Constexpr[cutlass.Boolean] = False,\n tail_count: Int32 = 128,\n ):\n \"\"\"Compute V_new = beta*V - beta*gamma*(K@S^T) in-place in smem.\"\"\"\n tidx, _, _ = cute.arch.thread_idx()\n\n thread_idx = tidx % (self.threads_per_warp * (len(self.cudacore_warp_ids)))\n\n cIn = cute.make_identity_tensor((128, 128))\n tOcO = thr_mma.partition_C(cIn)\n\n corr_tile_size = 64\n corr_tile_size_f32 = corr_tile_size // 2\n\n tIn_i_layout = cute.composition(\n tIn.layout, cute.make_layout((128, corr_tile_size))\n )\n\n cIn_i_layout = cute.composition(\n tOcO.layout, cute.make_layout((128, corr_tile_size))\n )\n\n tIn_i = cute.make_tensor(tIn.iterator, tIn_i_layout)\n cIn_i = cute.make_tensor(cIn.iterator, cIn_i_layout)\n\n tmem_load_atom = cute.make_copy_atom(\n tcgen05.copy.Ld32x32bOp(tcgen05.copy.Repetition(corr_tile_size_f32)),\n self.acc_dtype,\n )\n\n tiled_tmem_load = tcgen05.make_tmem_copy(tmem_load_atom, tIn_i)\n thr_tmem_load = tiled_tmem_load.get_slice(thread_idx)\n\n frg_tile = 8\n sV_frg = cute.logical_divide(sV, cute.make_layout(frg_tile))\n\n tTMEM_LOADtO = thr_tmem_load.partition_S(tIn_i)\n tTMEM_LOADcO = thr_tmem_load.partition_D(cIn_i)\n tTMEM_LOADrS = cute.make_rmem_tensor(tTMEM_LOADcO.shape, self.acc_dtype)\n tTMEM_LOADrS_frag = cute.logical_divide(\n tTMEM_LOADrS, cute.make_layout(frg_tile)\n )\n\n if cutlass.const_expr(mask):\n if thread_idx >= tail_count:\n beta_val = self.g_beta_dtype(0)\n\n combined_factor = gate_val * beta_val\n\n each_iter = corr_tile_size // frg_tile\n for i in cutlass.range_constexpr(128 // corr_tile_size):\n tTMEM_LOADtO_i = cute.make_tensor(\n tTMEM_LOADtO.iterator + i * corr_tile_size, tTMEM_LOADtO.layout\n )\n cute.copy(tiled_tmem_load, tTMEM_LOADtO_i, tTMEM_LOADrS)\n cute.arch.fence_view_async_tmem_load()\n\n # Load V from smem\n temp_regs = cute.make_rmem_tensor(tTMEM_LOADrS_frag.shape, self.acc_dtype)\n for it in cutlass.range_constexpr(each_iter):\n for inner_idx in cutlass.range_constexpr(0, frg_tile, 2):\n # mul2\n (\n temp_regs[inner_idx + 0, it],\n temp_regs[inner_idx + 1, it],\n ) = cute.arch.mul_packed_f32x2(\n (\n tTMEM_LOADrS_frag[inner_idx + 0, it],\n tTMEM_LOADrS_frag[inner_idx + 1, it],\n ),\n (-combined_factor, -combined_factor),\n )\n\n # fma2\n (\n temp_regs[inner_idx + 0, it],\n temp_regs[inner_idx + 1, it],\n ) = cute.arch.fma_packed_f32x2(\n (\n beta_val,\n beta_val,\n ),\n (\n cutlass.Float32(\n sV_frg[inner_idx + 0, (i * each_iter + it, thread_idx)]\n ),\n cutlass.Float32(\n sV_frg[inner_idx + 1, (i * each_iter + it, thread_idx)]\n ),\n ),\n (\n temp_regs[inner_idx + 0, it],\n temp_regs[inner_idx + 1, it],\n ),\n )\n sV_frg[None, (i * each_iter + it, thread_idx)].store(\n temp_regs[None, it].load().to(self.i_dtype)\n )\n\n @cute.jit\n def store_state_to_smem(\n self,\n tO: cute.Tensor,\n sO: cute.Tensor,\n thr_mma: cute.ThrMma,\n ):\n \"\"\"Copy final state from TMEM to smem for TMA store to global.\"\"\"\n tidx, _, _ = cute.arch.thread_idx()\n thread_idx = tidx % (self.threads_per_warp * (len(self.cudacore_warp_ids)))\n\n tOcO = thr_mma.partition_C(tO)\n tOsO = thr_mma.partition_C(sO)\n\n corr_tile_size = 32 # must >= 8\n tOsO_sub = cute.make_tensor(\n cute.recast_ptr(tOsO.iterator, dtype=self.state_dtype),\n cute.shape(tOsO)[0],\n )\n tOsO_tile = cute.logical_divide(\n tOsO_sub, (None, (None, 32 // (128 // corr_tile_size)))\n )\n\n tIn_i_layout = cute.composition(\n tO.layout, cute.make_layout((128, corr_tile_size))\n )\n cIn_i_layout = cute.composition(\n tOcO.layout, cute.make_layout((128, corr_tile_size))\n )\n sOut_i_layout = cute.composition(\n tOsO.layout, cute.make_layout((128, corr_tile_size))\n )\n\n tIn_i = cute.make_tensor(tO.iterator, tIn_i_layout)\n cIn_i = cute.make_tensor(tOcO.iterator, cIn_i_layout)\n\n tmem_load_atom = cute.make_copy_atom(\n tcgen05.copy.Ld32x32bOp(tcgen05.copy.Repetition(corr_tile_size)),\n self.acc_dtype,\n )\n\n tiled_tmem_load = tcgen05.make_tmem_copy(tmem_load_atom, tIn_i)\n thr_tmem_load = tiled_tmem_load.get_slice(thread_idx)\n\n tTMEM_LOADtO = thr_tmem_load.partition_S(tIn_i)\n tTMEM_LOADcO = thr_tmem_load.partition_D(cIn_i)\n tTMEM_LOADrS = cute.make_rmem_tensor(tTMEM_LOADcO.shape, self.acc_dtype)\n\n smem_copy_atom = sm100_utils.get_smem_store_op(\n self.s_output, self.state_dtype, self.acc_dtype, tiled_tmem_load\n )\n tiled_smem_store = cute.make_tiled_copy_D(smem_copy_atom, tiled_tmem_load)\n\n for i in cutlass.range_constexpr(128 // corr_tile_size):\n tTMEM_LOADtO_i = cute.make_tensor(\n tTMEM_LOADtO.iterator + i * corr_tile_size, tTMEM_LOADtO.layout\n )\n cute.copy(tiled_tmem_load, tTMEM_LOADtO_i, tTMEM_LOADrS)\n sOut_i_sub = cute.make_tensor(\n tOsO_tile[None, (None, (None, i))].iterator, sOut_i_layout\n )\n tTMEM_STOREsO_i = thr_tmem_load.partition_D(sOut_i_sub)\n cute.copy(tiled_smem_store, tTMEM_LOADrS, tTMEM_STOREsO_i)\n\n # fence view async shared\n cute.arch.fence_proxy(\n cute.arch.ProxyKind.async_shared,\n space=cute.arch.SharedSpace.shared_cta,\n )\n\n @cute.jit\n def store_o_smem(\n self,\n tO: cute.Tensor,\n sO: cute.Tensor,\n thr_mma: cute.ThrMma,\n scale: cutlass.Float32,\n ):\n \"\"\"Scale and convert O from TMEM (f32) to smem (f16/bf16) for TMA store.\"\"\"\n tidx, _, _ = cute.arch.thread_idx()\n thread_idx = tidx % (self.threads_per_warp * (len(self.cudacore_warp_ids)))\n\n tOcO = thr_mma.partition_C(tO)\n tOsO = thr_mma.partition_C(sO)\n\n corr_tile_size = 128 # must >= 8\n\n # ((128,(8,16)),1,1,(1,1))\n tOsO_sub = cute.make_tensor(\n cute.recast_ptr(tOsO.iterator, dtype=self.i_dtype),\n cute.shape(tOsO)[0],\n )\n tOsO_tile = cute.logical_divide(\n tOsO_sub, (None, (None, 16 // (128 // corr_tile_size)))\n )\n\n tIn_i_layout = cute.composition(\n tO.layout, cute.make_layout((128, corr_tile_size))\n )\n cIn_i_layout = cute.composition(\n tOcO.layout, cute.make_layout((128, corr_tile_size))\n )\n sOut_i_layout = cute.composition(\n tOsO.layout, cute.make_layout((128, corr_tile_size))\n )\n\n tIn_i = cute.make_tensor(tO.iterator, tIn_i_layout)\n cIn_i = cute.make_tensor(tOcO.iterator, cIn_i_layout)\n\n tmem_load_atom = cute.make_copy_atom(\n tcgen05.copy.Ld32x32bOp(tcgen05.copy.Repetition(corr_tile_size)),\n self.acc_dtype,\n )\n\n tiled_tmem_load = tcgen05.make_tmem_copy(tmem_load_atom, tIn_i)\n thr_tmem_load = tiled_tmem_load.get_slice(thread_idx)\n\n tTMEM_LOADtO = thr_tmem_load.partition_S(tIn_i)\n tTMEM_LOADcO = thr_tmem_load.partition_D(cIn_i)\n tTMEM_LOADrS = cute.make_rmem_tensor(tTMEM_LOADcO.shape, self.acc_dtype)\n\n tTMEM_STORErS_x4_e = cute.make_tensor(\n cute.recast_ptr(tTMEM_LOADrS.iterator, dtype=self.i_dtype),\n tTMEM_LOADrS.layout,\n )\n\n smem_copy_atom = sm100_utils.get_smem_store_op(\n self.o_layout, self.i_dtype, self.acc_dtype, tiled_tmem_load\n )\n tiled_smem_store = cute.make_tiled_copy_D(smem_copy_atom, tiled_tmem_load)\n\n for i in cutlass.range_constexpr(128 // corr_tile_size):\n tTMEM_LOADtO_i = cute.make_tensor(\n tTMEM_LOADtO.iterator + i * corr_tile_size, tTMEM_LOADtO.layout\n )\n cute.copy(tiled_tmem_load, tTMEM_LOADtO_i, tTMEM_LOADrS)\n\n frg_cnt = 4 # must 4\n frg_tile = cute.size(tTMEM_LOADrS) // frg_cnt\n tTMEM_LOADrS_frg = cute.logical_divide(\n tTMEM_LOADrS, cute.make_layout(frg_tile)\n )\n tTMEM_STORErS_x4_e_frg = cute.logical_divide(\n tTMEM_STORErS_x4_e, cute.make_layout(frg_tile)\n )\n\n temp_regs = cute.make_rmem_tensor(tTMEM_LOADrS_frg.shape, self.acc_dtype)\n for j in cutlass.range_constexpr(frg_cnt):\n for inner_idx in cutlass.range_constexpr(0, frg_tile, 2):\n # mul2\n (\n temp_regs[inner_idx + 0, j],\n temp_regs[inner_idx + 1, j],\n ) = cute.arch.mul_packed_f32x2(\n (\n tTMEM_LOADrS_frg[inner_idx + 0, j],\n tTMEM_LOADrS_frg[inner_idx + 1, j],\n ),\n (scale, scale),\n )\n tTMEM_STORErS_x4_e_frg[None, j].store(\n temp_regs[None, j].load().to(self.i_dtype)\n )\n\n # store\n sOut_i_sub = cute.make_tensor(\n tOsO_tile[None, (None, (None, i))].iterator, sOut_i_layout\n )\n tTMEM_STOREsO_i = thr_tmem_load.partition_D(sOut_i_sub)\n cute.copy(tiled_smem_store, tTMEM_STORErS_x4_e, tTMEM_STOREsO_i)\n\n # fence view async shared\n cute.arch.fence_proxy(\n cute.arch.ProxyKind.async_shared,\n space=cute.arch.SharedSpace.shared_cta,\n )\n\n @cute.jit\n def load_k(\n self,\n tIn: cute.Tensor,\n sUpdateB: cute.Tensor,\n gate: cutlass.Float32,\n val: cutlass.Float32,\n ):\n \"\"\"Load K from TMEM, apply per-token gate decay.\"\"\"\n tidx, _, _ = cute.arch.thread_idx()\n thread_idx = tidx % (self.threads_per_warp * (len(self.cudacore_warp_ids)))\n\n gate_val = cute.math.exp((gate - val))\n\n k = self.read_tmem_128(tIn)\n\n k_f16 = cute.make_tensor(\n cute.recast_ptr(k.iterator, dtype=self.i_dtype),\n cute.make_layout(128),\n )\n k_f16_frag = cute.logical_divide(k_f16, cute.make_layout(8))\n\n for bid in cutlass.range_constexpr(0, 2):\n for col in cutlass.range_constexpr(0, 8):\n load_row = thread_idx\n\n store_row = load_row\n store_col = bid * 8 + col\n\n store_row_bid = store_row // 16\n store_row_offset = store_row % 16\n sUpdateB[\n ((None, store_col), store_row_offset), 0, store_row_bid, 0\n ].store(\n (k_f16_frag[None, store_col].load() * gate_val).to(self.i_dtype)\n )\n\n cute.arch.fence_proxy(\n cute.arch.ProxyKind.async_shared,\n space=cute.arch.SharedSpace.shared_cta,\n )\n\n @cute.jit\n def init_state_zeros(\n self,\n thr_mma: cute.ThrMma,\n tOutF32: cute.Tensor,\n ):\n \"\"\"Zero-initialize the recurrent state in TMEM (no initial_state provided).\"\"\"\n tidx, _, _ = cute.arch.thread_idx()\n thread_idx = tidx % (self.threads_per_warp * (len(self.cudacore_warp_ids)))\n\n cIn = cute.make_identity_tensor((128, 128))\n tOcO = thr_mma.partition_C(cIn)\n corr_tile_size = 128\n\n # Apply gate State\n cInOut_i_layout = cute.composition(\n tOcO.layout, cute.make_layout((128, corr_tile_size))\n )\n tInOut_i_layout = cute.composition(\n tOutF32.layout, cute.make_layout((128, corr_tile_size))\n )\n\n tInOut_i = cute.make_tensor(tOutF32.iterator, tInOut_i_layout)\n cInOut_i = cute.make_tensor(tOcO.iterator, cInOut_i_layout)\n\n tmem_store_atom_f32 = cute.make_copy_atom(\n tcgen05.copy.St32x32bOp(tcgen05.copy.Repetition(corr_tile_size)),\n self.acc_dtype,\n )\n\n tiled_tmem_store_f32 = tcgen05.make_tmem_copy(tmem_store_atom_f32, tInOut_i)\n thr_tmem_store_f32 = tiled_tmem_store_f32.get_slice(thread_idx)\n\n tTMEM_STOREtInOut = thr_tmem_store_f32.partition_D(tInOut_i)\n tTMEM_STOREcInOut = thr_tmem_store_f32.partition_S(cInOut_i)\n tTMEM_STORErInOut = cute.make_rmem_tensor(\n tTMEM_STOREcInOut.shape, self.acc_dtype\n )\n\n frg_tile = 4\n zeros = cute.zeros_like(cute.make_layout(frg_tile), self.acc_dtype)\n\n for i in cutlass.range_constexpr(128 // corr_tile_size):\n tTMEM_STOREtInOut_i = cute.make_tensor(\n tTMEM_STOREtInOut.iterator + i * corr_tile_size,\n tTMEM_STOREtInOut.layout,\n )\n\n tTMEM_STORErInOut_frg = cute.logical_divide(\n tTMEM_STORErInOut, ((frg_tile, None), None)\n )\n\n each_iter = corr_tile_size // frg_tile\n for j in cutlass.range_constexpr(each_iter):\n tTMEM_STORErInOut_frg[((None, j), 0), 0, 0].store(zeros)\n\n # store\n cute.copy(tiled_tmem_store_f32, tTMEM_STORErInOut, tTMEM_STOREtInOut_i)\n cute.arch.fence_view_async_tmem_store()\n\n @cute.jit\n def init_state_from_smem(\n self,\n thr_mma: cute.ThrMma,\n tOutF32: cute.Tensor,\n sStateInputF32: cute.Tensor,\n ):\n \"\"\"Load initial_state from smem (f32) into TMEM.\"\"\"\n tidx, _, _ = cute.arch.thread_idx()\n thread_idx = tidx % (self.threads_per_warp * (len(self.cudacore_warp_ids)))\n\n cIn = cute.make_identity_tensor((128, 128))\n tOcO = thr_mma.partition_C(cIn)\n\n corr_tile_size = 128\n cInOut_i_layout = cute.composition(\n tOcO.layout, cute.make_layout((128, corr_tile_size))\n )\n tInOut_i_layout = cute.composition(\n tOutF32.layout, cute.make_layout((128, corr_tile_size))\n )\n\n tInOut_i = cute.make_tensor(tOutF32.iterator, tInOut_i_layout)\n cInOut_i = cute.make_tensor(tOcO.iterator, cInOut_i_layout)\n\n tmem_store_atom_f32 = cute.make_copy_atom(\n tcgen05.copy.St32x32bOp(tcgen05.copy.Repetition(corr_tile_size)),\n self.acc_dtype,\n )\n\n tiled_tmem_store_f32 = tcgen05.make_tmem_copy(tmem_store_atom_f32, tInOut_i)\n thr_tmem_store_f32 = tiled_tmem_store_f32.get_slice(thread_idx)\n\n tTMEM_STOREtInOut = thr_tmem_store_f32.partition_D(tInOut_i)\n tTMEM_STOREcInOut = thr_tmem_store_f32.partition_S(cInOut_i)\n tTMEM_STORErInOut = cute.make_rmem_tensor(\n tTMEM_STOREcInOut.shape, self.acc_dtype\n )\n\n frg_tile = 4 # must 4\n sStateInputF32_frag = cute.logical_divide(\n sStateInputF32, (((None, frg_tile), None))\n )\n tTMEM_STORErInOut_frg = cute.logical_divide(\n tTMEM_STORErInOut, ((frg_tile, None), None)\n )\n each_iter = corr_tile_size // frg_tile\n for i in cutlass.range_constexpr(128 // corr_tile_size):\n tTMEM_STOREtInOut_i = cute.make_tensor(\n tTMEM_STOREtInOut.iterator + i * corr_tile_size,\n tTMEM_STOREtInOut.layout,\n )\n\n # Load from smem\n idx_offset = i * corr_tile_size\n for j in cutlass.range_constexpr(each_iter):\n idx = idx_offset + j * frg_tile\n bid = idx // 32\n bid_inner = idx % 32 // 8\n inner_idx = idx % 8 // 4\n s_vec = sStateInputF32_frag[\n (thread_idx, (None, inner_idx)), 0, (bid_inner, bid), 0\n ].load()\n tTMEM_STORErInOut_frg[((None, j), 0), 0, 0].store(s_vec)\n\n # store\n cute.copy(tiled_tmem_store_f32, tTMEM_STORErInOut, tTMEM_STOREtInOut_i)\n cute.arch.fence_view_async_tmem_store()\n\n @cute.jit\n def load_state_apply_gate(\n self,\n thr_mma: cute.ThrMma,\n tIn: cute.Tensor,\n sStateInput: cute.Tensor,\n gate: cutlass.Float32,\n ):\n \"\"\"Apply chunk-level gate decay to state in TMEM, and copy state to smem (f16) for KST GEMM.\"\"\"\n tidx, _, _ = cute.arch.thread_idx()\n thread_idx = tidx % (self.threads_per_warp * (len(self.cudacore_warp_ids)))\n\n cIn = cute.make_identity_tensor((128, 128))\n tOcO = thr_mma.partition_C(cIn)\n\n corr_tile_size = 16\n # corr_tile_size_f32 = corr_tile_size // 2\n\n tIn_i_layout = cute.composition(\n tIn.layout, cute.make_layout((128, corr_tile_size))\n )\n cIn_i_layout = cute.composition(\n tOcO.layout, cute.make_layout((128, corr_tile_size))\n )\n\n # Apply gate State\n # cInOut_i_layout = cute.composition(tOcO.layout, cute.make_layout((128, corr_tile_size)))\n tInOut_i_layout = cute.composition(\n tIn.layout, cute.make_layout((128, corr_tile_size))\n )\n\n # fp16 state\n tIn_i = cute.make_tensor(tIn.iterator, tIn_i_layout)\n cIn_i = cute.make_tensor(cIn.iterator, cIn_i_layout)\n\n tInOut_i = cute.make_tensor(tIn.iterator, tInOut_i_layout)\n\n tmem_load_atom = cute.make_copy_atom(\n tcgen05.copy.Ld32x32bOp(tcgen05.copy.Repetition(corr_tile_size)),\n self.acc_dtype,\n )\n\n tmem_store_atom_f32 = cute.make_copy_atom(\n tcgen05.copy.St32x32bOp(tcgen05.copy.Repetition(corr_tile_size)),\n self.acc_dtype,\n )\n\n tiled_tmem_load = tcgen05.make_tmem_copy(tmem_load_atom, tIn_i)\n tiled_tmem_store_f32 = tcgen05.make_tmem_copy(tmem_store_atom_f32, tInOut_i)\n\n thr_tmem_load = tiled_tmem_load.get_slice(thread_idx)\n thr_tmem_store_f32 = tiled_tmem_store_f32.get_slice(thread_idx)\n\n tTMEM_LOADtO = thr_tmem_load.partition_S(tIn_i)\n tTMEM_LOADcO = thr_tmem_load.partition_D(cIn_i)\n tTMEM_LOADrS = cute.make_rmem_tensor(tTMEM_LOADcO.shape, self.acc_dtype)\n\n tTMEM_STOREtInOut = thr_tmem_store_f32.partition_D(tInOut_i)\n tTMEM_STORErInOut = cute.make_tensor(\n cute.recast_ptr(tTMEM_LOADrS.iterator, dtype=self.acc_dtype),\n tTMEM_LOADrS.layout,\n )\n\n gate_val = cute.math.exp(gate)\n for i in cutlass.range_constexpr(128 // corr_tile_size):\n tTMEM_LOADtO_i = cute.make_tensor(\n tTMEM_LOADtO.iterator + i * corr_tile_size, tTMEM_LOADtO.layout\n )\n tTMEM_STOREtInOut_i = cute.make_tensor(\n tTMEM_STOREtInOut.iterator + i * corr_tile_size,\n tTMEM_STOREtInOut.layout,\n )\n\n cute.copy(tiled_tmem_load, tTMEM_LOADtO_i, tTMEM_LOADrS)\n\n frg_tile = 16 # must <= 16\n tTMEM_LOADrS_frg = cute.logical_divide(\n tTMEM_LOADrS, ((frg_tile, None), None)\n )\n tTMEM_STORErInOut_frg = cute.logical_divide(\n tTMEM_STORErInOut, ((frg_tile, None), None)\n )\n sStateInput_frag = cute.logical_divide(\n sStateInput, (((None, frg_tile), None))\n )\n\n each_iter = corr_tile_size // frg_tile\n idx_offset = i * corr_tile_size\n for j in cutlass.range_constexpr(each_iter):\n s_vec = tTMEM_LOADrS_frg[((None, j), 0), 0, 0].load()\n s_vec_f16 = s_vec.to(self.q_dtype)\n idx = idx_offset + j * frg_tile\n bid = idx // 64\n bid_inner = idx % 64 // 16\n inner_idx = idx % 16 // frg_tile\n sStateInput_frag[\n (thread_idx, (None, inner_idx)), 0, (bid_inner, bid), 0\n ].store(s_vec_f16)\n # tTMEM_STORErInOut_frg[((None, j), 0), 0, 0].store(s_vec * gate_val)\n\n for inner_idx in cutlass.range_constexpr(0, frg_tile, 2):\n (\n tTMEM_STORErInOut_frg[((inner_idx + 0, j), 0), 0, 0],\n tTMEM_STORErInOut_frg[((inner_idx + 1, j), 0), 0, 0],\n ) = cute.arch.mul_packed_f32x2(\n (s_vec[inner_idx + 0], s_vec[inner_idx + 1]),\n (\n gate_val,\n gate_val,\n ),\n )\n cute.copy(tiled_tmem_store_f32, tTMEM_STORErInOut, tTMEM_STOREtInOut_i)\n cute.arch.fence_view_async_tmem_store()\n\n @cute.jit\n def load_qk_epi(\n self,\n thr_mma: cute.ThrMma,\n tIn: cute.Tensor,\n tOut: cute.Tensor,\n tGamma: cute.Tensor, # causal gate mask\n mask: cutlass.Constexpr[cutlass.Boolean] = False,\n tail_count: Int32 = 128,\n ):\n \"\"\"Apply gamma mask to QK^T.\"\"\"\n tidx, _, _ = cute.arch.thread_idx()\n thread_idx = tidx % (self.threads_per_warp * (len(self.cudacore_warp_ids)))\n\n cIn = cute.make_identity_tensor((128, 128))\n tOcO = thr_mma.partition_C(cIn)\n\n corr_tile_size = 32\n corr_tile_size_f32 = corr_tile_size // 2\n\n tIn_i_layout = cute.composition(\n tIn.layout, cute.make_layout((128, corr_tile_size))\n )\n cIn_i_layout = cute.composition(\n tOcO.layout, cute.make_layout((128, corr_tile_size))\n )\n\n cOut_i_layout = cute.composition(\n tOcO.layout, cute.make_layout((128, corr_tile_size_f32))\n )\n tOut_i_layout = cute.composition(\n tOut.layout, cute.make_layout((128, corr_tile_size_f32))\n )\n\n tIn_i = cute.make_tensor(tIn.iterator, tIn_i_layout)\n tGamma_i = cute.make_tensor(tGamma.iterator, tIn_i_layout)\n cIn_i = cute.make_tensor(cIn.iterator, cIn_i_layout)\n\n tOut_i = cute.make_tensor(tOut.iterator, tOut_i_layout)\n cOut_i = cute.make_tensor(tOcO.iterator, cOut_i_layout)\n\n tmem_load_atom = cute.make_copy_atom(\n tcgen05.copy.Ld32x32bOp(tcgen05.copy.Repetition(corr_tile_size)),\n self.acc_dtype,\n )\n tmem_store_atom = cute.make_copy_atom(\n tcgen05.copy.St32x32bOp(tcgen05.copy.Repetition(corr_tile_size_f32)),\n self.acc_dtype,\n )\n\n tiled_tmem_load = tcgen05.make_tmem_copy(tmem_load_atom, tIn_i)\n tiled_tmem_store = tcgen05.make_tmem_copy(tmem_store_atom, tOut_i)\n\n thr_tmem_load = tiled_tmem_load.get_slice(thread_idx)\n thr_tmem_store = tiled_tmem_store.get_slice(thread_idx)\n\n # Load Gamma\n tiled_tmem_load_gamma = tcgen05.make_tmem_copy(tmem_load_atom, tGamma_i)\n thr_tmem_load_gamma = tiled_tmem_load_gamma.get_slice(thread_idx)\n\n tTMEM_LOADtO = thr_tmem_load.partition_S(tIn_i)\n tTMEM_LOADcO = thr_tmem_load.partition_D(cIn_i)\n\n tTMEM_STOREcS = thr_tmem_store.partition_S(cOut_i)\n tTMEM_STOREtO = thr_tmem_store.partition_D(tOut_i)\n tTMEM_LOADrS = cute.make_rmem_tensor(tTMEM_LOADcO.shape, self.acc_dtype)\n\n tTMEM_LOADtG = thr_tmem_load_gamma.partition_S(tGamma_i)\n tTMEM_LOADrG = cute.make_rmem_tensor(tTMEM_LOADcO.shape, self.acc_dtype)\n\n tTMEM_STORErS_x4 = cute.make_rmem_tensor(tTMEM_STOREcS.shape, self.acc_dtype)\n tTMEM_STORErS_x4_e = cute.make_tensor(\n cute.recast_ptr(tTMEM_STORErS_x4.iterator, dtype=self.i_dtype),\n tTMEM_LOADrS.layout,\n )\n\n for i in cutlass.range_constexpr(128 // corr_tile_size):\n tTMEM_LOADtO_i = cute.make_tensor(\n tTMEM_LOADtO.iterator + i * corr_tile_size, tTMEM_LOADtO.layout\n )\n tTMEM_STOREtO_i = cute.make_tensor(\n tTMEM_STOREtO.iterator + i * corr_tile_size_f32, tTMEM_STOREtO.layout\n )\n tTMEM_LOADtG_i = cute.make_tensor(\n tTMEM_LOADtG.iterator + i * corr_tile_size, tTMEM_LOADrG.layout\n )\n\n cute.copy(tiled_tmem_load, tTMEM_LOADtO_i, tTMEM_LOADrS)\n cute.copy(tiled_tmem_load_gamma, tTMEM_LOADtG_i, tTMEM_LOADrG)\n\n frg_tile = 2\n tTMEM_LOADrS_frg = cute.logical_divide(\n tTMEM_LOADrS, ((frg_tile, None), None)\n )\n tTMEM_LOADrG_frg = cute.logical_divide(\n tTMEM_LOADrG, ((frg_tile, None), None)\n )\n tTMEM_STORErS_x4_e_frg = cute.logical_divide(\n tTMEM_STORErS_x4_e, cute.make_layout(frg_tile)\n )\n\n each_iter = corr_tile_size // frg_tile\n for j in cutlass.range_constexpr(each_iter):\n for it in cutlass.range_constexpr(0, frg_tile, 2):\n (\n tTMEM_LOADrS_frg[((it + 0, j), 0), 0, 0],\n tTMEM_LOADrS_frg[((it + 1, j), 0), 0, 0],\n ) = cute.arch.mul_packed_f32x2(\n (\n tTMEM_LOADrS_frg[((it + 0, j), 0), 0, 0],\n tTMEM_LOADrS_frg[((it + 1, j), 0), 0, 0],\n ),\n (\n tTMEM_LOADrG_frg[((it + 0, j), 0), 0, 0],\n tTMEM_LOADrG_frg[((it + 1, j), 0), 0, 0],\n ),\n )\n\n s_vec = tTMEM_LOADrS_frg[((None, j), 0), 0, 0].load()\n tTMEM_STORErS_x4_e_frg[None, j].store(s_vec.to(self.q_dtype))\n\n # store\n cute.copy(tiled_tmem_store, tTMEM_STORErS_x4, tTMEM_STOREtO_i)\n cute.arch.fence_view_async_tmem_store()\n\n @cute.jit\n def load_q_epi(\n self,\n thr_mma: cute.ThrMma,\n sQ: cute.Tensor,\n tOut: cute.Tensor,\n val: cutlass.Float32, # exp(cumsum_gate) for per-token gating\n mask: cutlass.Constexpr[cutlass.Boolean] = False,\n tail_count: Int32 = 128,\n ):\n \"\"\"Load Q from smem, apply per-token gate.\"\"\"\n tidx, _, _ = cute.arch.thread_idx()\n thread_idx = tidx % (self.threads_per_warp * (len(self.cudacore_warp_ids)))\n\n sQ_frag = cute.logical_divide(sQ, (((None, 8), None)))\n cIn = cute.make_identity_tensor((128, 128))\n tOcO = thr_mma.partition_C(cIn)\n\n corr_tile_size = 64\n corr_tile_size_f32 = corr_tile_size // 2\n\n cIn_i_layout = cute.composition(\n tOcO.layout, cute.make_layout((128, corr_tile_size))\n )\n cOut_i_layout = cute.composition(\n tOcO.layout, cute.make_layout((128, corr_tile_size_f32))\n )\n tOut_i_layout = cute.composition(\n tOut.layout, cute.make_layout((128, corr_tile_size_f32))\n )\n\n cIn_i = cute.make_tensor(cIn.iterator, cIn_i_layout)\n tOut_i = cute.make_tensor(tOut.iterator, tOut_i_layout)\n cOut_i = cute.make_tensor(tOcO.iterator, cOut_i_layout)\n\n tmem_store_atom = cute.make_copy_atom(\n tcgen05.copy.St32x32bOp(tcgen05.copy.Repetition(corr_tile_size_f32)),\n self.acc_dtype,\n )\n\n tiled_tmem_store = tcgen05.make_tmem_copy(tmem_store_atom, tOut_i)\n thr_tmem_store = tiled_tmem_store.get_slice(thread_idx)\n\n tTMEM_STOREcS_f16 = thr_tmem_store.partition_S(cIn_i)\n tTMEM_STOREcS = thr_tmem_store.partition_S(cOut_i)\n tTMEM_STOREtO = thr_tmem_store.partition_D(tOut_i)\n\n tTMEM_STORErS = cute.make_rmem_tensor(tTMEM_STOREcS.shape, self.acc_dtype)\n tTMEM_STORErS_x8 = cute.make_rmem_tensor(tTMEM_STOREcS_f16.shape, self.i_dtype)\n tTMEM_STORErS_x8_e = cute.make_tensor(\n cute.recast_ptr(tTMEM_STORErS.iterator, dtype=self.i_dtype),\n tTMEM_STORErS_x8.layout,\n )\n\n for i in cutlass.range_constexpr(128 // corr_tile_size):\n tTMEM_STOREtO_i = cute.make_tensor(\n tTMEM_STOREtO.iterator + i * corr_tile_size_f32, tTMEM_STOREtO.layout\n )\n\n frg_tile = 8\n tTMEM_STORErS_x8_e_frag = cute.logical_divide(\n tTMEM_STORErS_x8_e, cute.make_layout(frg_tile)\n )\n for col in cutlass.range_constexpr(0, 8):\n load_row = thread_idx\n load_col = col\n curr_val_ssa = sQ_frag[\n (load_row, (None, load_col % 2)), 0, (load_col // 2, i), 0\n ].load()\n tTMEM_STORErS_x8_e_frag[None, col].store(\n (curr_val_ssa * val).to(self.i_dtype)\n )\n # store\n if cutlass.const_expr(mask):\n if thread_idx >= tail_count:\n tTMEM_STORErS_x8_e_frag.fill(self.i_dtype(0))\n cute.copy(tiled_tmem_store, tTMEM_STORErS, tTMEM_STOREtO_i)\n\n cute.arch.fence_view_async_tmem_store()\n\n @cute.jit\n def store_k_epi(\n self,\n thr_mma: cute.ThrMma,\n sK: cute.Tensor,\n tOut: cute.Tensor,\n mask: cutlass.Constexpr[cutlass.Boolean] = False,\n tail_count: Int32 = 128,\n ):\n \"\"\"Load K from smem and store to TMEM.\"\"\"\n tidx, _, _ = cute.arch.thread_idx()\n\n thread_idx = tidx % (self.threads_per_warp * (len(self.cudacore_warp_ids)))\n\n sK_frag = cute.logical_divide(sK, (((None, 8), None)))\n cIn = cute.make_identity_tensor((128, 128))\n tOcO = thr_mma.partition_C(cIn)\n\n corr_tile_size = 64\n corr_tile_size_f32 = corr_tile_size // 2\n\n cIn_i_layout = cute.composition(\n tOcO.layout, cute.make_layout((128, corr_tile_size))\n )\n cOut_i_layout = cute.composition(\n tOcO.layout, cute.make_layout((128, corr_tile_size_f32))\n )\n tOut_i_layout = cute.composition(\n tOut.layout, cute.make_layout((128, corr_tile_size_f32))\n )\n\n cIn_i = cute.make_tensor(cIn.iterator, cIn_i_layout)\n tOut_i = cute.make_tensor(tOut.iterator, tOut_i_layout)\n cOut_i = cute.make_tensor(tOcO.iterator, cOut_i_layout)\n\n tmem_store_atom = cute.make_copy_atom(\n tcgen05.copy.St32x32bOp(tcgen05.copy.Repetition(corr_tile_size_f32)),\n self.acc_dtype,\n )\n\n tiled_tmem_store = tcgen05.make_tmem_copy(tmem_store_atom, tOut_i)\n thr_tmem_store = tiled_tmem_store.get_slice(thread_idx)\n\n tTMEM_STOREcS_f16 = thr_tmem_store.partition_S(cIn_i)\n tTMEM_STOREcS = thr_tmem_store.partition_S(cOut_i)\n tTMEM_STOREtO = thr_tmem_store.partition_D(tOut_i)\n\n tTMEM_STORErS = cute.make_rmem_tensor(tTMEM_STOREcS.shape, self.acc_dtype)\n tTMEM_STORErS_x8 = cute.make_rmem_tensor(tTMEM_STOREcS_f16.shape, self.i_dtype)\n tTMEM_STORErS_x8_e = cute.make_tensor(\n cute.recast_ptr(tTMEM_STORErS.iterator, dtype=self.i_dtype),\n tTMEM_STORErS_x8.layout,\n )\n frg_tile = 8\n tTMEM_STORErS_x8_e_frag = cute.logical_divide(\n tTMEM_STORErS_x8_e, cute.make_layout(frg_tile)\n )\n for i in cutlass.range_constexpr(128 // corr_tile_size):\n tTMEM_STOREtO_i = cute.make_tensor(\n tTMEM_STOREtO.iterator + i * corr_tile_size_f32, tTMEM_STOREtO.layout\n )\n\n for col in cutlass.range_constexpr(0, 8):\n load_row = thread_idx\n\n load_col = col\n curr_val_ssa = sK_frag[\n (load_row, (None, load_col % 2)), 0, (load_col // 2, i), 0\n ].load()\n tTMEM_STORErS_x8_e_frag[None, col].store(curr_val_ssa)\n\n # store\n if cutlass.const_expr(mask):\n if thread_idx >= tail_count:\n tTMEM_STORErS_x8_e_frag.fill(self.i_dtype(0))\n\n cute.copy(tiled_tmem_store, tTMEM_STORErS, tTMEM_STOREtO_i)\n cute.arch.fence_view_async_tmem_store()\n\n @cute.jit\n def reverse_smem_sub(\n self,\n reverse_result: cute.Tensor,\n sIvt: cute.Tensor,\n ):\n \"\"\"Compute the inverse of a 32x32 sub-block.\"\"\"\n lane_id = cute.arch.lane_idx()\n sub_widx = cute.arch.warp_idx() % 4\n\n reverse_result.fill(self.acc_dtype(0))\n\n for row in cutlass.range_constexpr(1, 32, unroll=1):\n for k in cutlass.range(1, row):\n row_i_k = sIvt[(k, row), sub_widx]\n reverse_result[row] -= reverse_result[k] * row_i_k\n row_i_lane = self.acc_dtype(0)\n if lane_id < row:\n row_i_lane = sIvt[(lane_id, row), sub_widx]\n reverse_result[row] -= row_i_lane\n reverse_result[lane_id] = self.acc_dtype(1)\n\n @cute.jit\n def store_ivt_smem_l0_ss_a(\n self,\n reverse_result: cute.Tensor,\n sReg: cute.Tensor,\n sInvertSubSSL0A: cute.Tensor,\n ):\n \"\"\"Store 32x32 sub-inverse results to smem.\"\"\"\n\n tidx, _, _ = cute.arch.thread_idx()\n widx = cute.arch.warp_idx()\n lane_id = cute.arch.lane_idx()\n\n sub_widx = widx % 4\n\n # store sub result to shared memory\n # (((4,128),8))\n for row_bid in cutlass.range_constexpr(4):\n for col_bid in cutlass.range_constexpr(8):\n row_d = (lane_id // 4 + col_bid) % 8\n row = row_bid * 8 + row_d\n col_id = lane_id // 4\n col_sub_id = lane_id % 4\n sReg[(col_sub_id, sub_widx * 32 + row), col_id] = reverse_result[row]\n\n cutlass.cute.arch.sync_warp()\n\n if sub_widx == 1 or sub_widx == 3:\n sub_id_row = sub_widx // 2\n sInvertSubSSL0A_frag = cute.logical_divide(\n sInvertSubSSL0A, ((None, 4), None)\n )\n for col in cutlass.range_constexpr(8):\n sInvertSubSSL0A_frag[\n (sub_id_row * 32 + lane_id, (None, col % 2)), 0, col // 2, 0\n ].store(sReg[(None, tidx % 128), col].load())\n\n @cute.jit\n def store_ivt_smem_l0_ss_b(\n self,\n thr_mma: cute.ThrMma,\n tIn: cute.Tensor,\n sInvertSubSSL0B: cute.Tensor,\n ):\n tidx, _, _ = cute.arch.thread_idx()\n # bidx, bidy, _ = cute.arch.block_idx()\n widx = cute.arch.warp_idx()\n lane_id = cute.arch.lane_idx()\n thread_idx = tidx % (self.threads_per_warp * (len(self.cudacore_warp_ids)))\n\n sub_widx = widx % 4\n\n # load Tmem\n cIn = cute.make_identity_tensor((128, 128))\n tOcO = thr_mma.partition_C(cIn)\n\n corr_tile_size = 32 # must <= 32\n tIn_i_layout = cute.composition(\n tIn.layout, cute.make_layout((128, corr_tile_size))\n )\n cIn_i_layout = cute.composition(\n tOcO.layout, cute.make_layout((128, corr_tile_size))\n )\n tIn_i = cute.make_tensor(tIn.iterator, tIn_i_layout)\n cIn_i = cute.make_tensor(cIn.iterator, cIn_i_layout)\n\n tmem_load_atom = cute.make_copy_atom(\n tcgen05.copy.Ld32x32bOp(tcgen05.copy.Repetition(corr_tile_size)),\n self.acc_dtype,\n )\n\n # Load In\n tiled_tmem_load = tcgen05.make_tmem_copy(tmem_load_atom, tIn_i)\n thr_tmem_load = tiled_tmem_load.get_slice(thread_idx)\n\n tTMEM_LOADtO = thr_tmem_load.partition_S(tIn_i)\n tTMEM_LOADcO = thr_tmem_load.partition_D(cIn_i)\n\n tTMEM_LOADrS = cute.make_rmem_tensor(tTMEM_LOADcO.shape, self.acc_dtype)\n\n sub_tile_size = 8\n tmem_frag = cute.logical_divide(tTMEM_LOADrS, ((sub_tile_size, None), None))\n sInvertSubSSL0B_frag = cute.logical_divide(\n sInvertSubSSL0B, ((sub_tile_size, None), None)\n )\n\n # tile 0\n tile_frags = corr_tile_size // sub_tile_size\n for i in cutlass.range_constexpr(32 // corr_tile_size):\n tTMEM_LOADtO_i = cute.make_tensor(\n tTMEM_LOADtO.iterator + i * corr_tile_size, tTMEM_LOADtO.layout\n )\n\n cute.copy(tiled_tmem_load, tTMEM_LOADtO_i, tTMEM_LOADrS)\n cute.arch.fence_view_async_tmem_load()\n if sub_widx == 1:\n idx = (i * corr_tile_size) // sub_tile_size\n for j in cutlass.range_constexpr(tile_frags):\n col_true = (idx + j) % 8\n # todo: remove smem bank conflict\n sInvertSubSSL0B_frag[\n ((None, (col_true, 0)), lane_id % 8), 0, lane_id // 8, 0\n ].store(tmem_frag[((None, j), 0), 0, 0].load())\n\n # tile 2\n for i in cutlass.range_constexpr(32 // corr_tile_size):\n tTMEM_LOADtO_i = cute.make_tensor(\n tTMEM_LOADtO.iterator + 64 + i * corr_tile_size, tTMEM_LOADtO.layout\n )\n\n cute.copy(tiled_tmem_load, tTMEM_LOADtO_i, tTMEM_LOADrS)\n cute.arch.fence_view_async_tmem_load()\n if sub_widx == 3:\n idx = (i * corr_tile_size) // sub_tile_size\n for j in cutlass.range_constexpr(tile_frags):\n col_true = (idx + j) % 8\n # todo: remove smem bank conflict\n sInvertSubSSL0B_frag[\n ((None, (col_true, 1)), lane_id % 8), 0, lane_id // 8, 0\n ].store(tmem_frag[((None, j), 0), 0, 0].load())\n\n cute.arch.fence_proxy(\n cute.arch.ProxyKind.async_shared,\n space=cute.arch.SharedSpace.shared_cta,\n )\n\n @cute.jit\n def store_ivt_smem_l1_ss_b(\n self,\n thr_mma: cute.ThrMma,\n tIn: cute.Tensor,\n sInvertSubSSL1B: cute.Tensor,\n ):\n tidx, _, _ = cute.arch.thread_idx()\n # bidx, bidy, _ = cute.arch.block_idx()\n widx = cute.arch.warp_idx()\n lane_id = cute.arch.lane_idx()\n thread_idx = tidx % (self.threads_per_warp * (len(self.cudacore_warp_ids)))\n\n sub_widx = widx % 4\n\n # load Tmem\n cIn = cute.make_identity_tensor((128, 128))\n tOcO = thr_mma.partition_C(cIn)\n\n corr_tile_size = 8\n tIn_i_layout = cute.composition(\n tIn.layout, cute.make_layout((128, corr_tile_size))\n )\n cIn_i_layout = cute.composition(\n tOcO.layout, cute.make_layout((128, corr_tile_size))\n )\n tIn_i = cute.make_tensor(tIn.iterator, tIn_i_layout)\n cIn_i = cute.make_tensor(cIn.iterator, cIn_i_layout)\n\n tmem_load_atom = cute.make_copy_atom(\n tcgen05.copy.Ld32x32bOp(tcgen05.copy.Repetition(corr_tile_size)),\n self.acc_dtype,\n )\n\n # Load In\n tiled_tmem_load = tcgen05.make_tmem_copy(tmem_load_atom, tIn_i)\n thr_tmem_load = tiled_tmem_load.get_slice(thread_idx)\n\n tTMEM_LOADtO = thr_tmem_load.partition_S(tIn_i)\n tTMEM_LOADcO = thr_tmem_load.partition_D(cIn_i)\n\n tTMEM_LOADrS = cute.make_rmem_tensor(tTMEM_LOADcO.shape, self.acc_dtype)\n\n # tile 0\n tTMEM_LOADtO_i = cute.make_tensor(tTMEM_LOADtO.iterator, tTMEM_LOADtO.layout)\n\n cute.copy(tiled_tmem_load, tTMEM_LOADtO_i, tTMEM_LOADrS)\n cute.arch.fence_view_async_tmem_load()\n sub_tile_size = 8\n tmem_frag = cute.logical_divide(tTMEM_LOADrS, ((sub_tile_size, None), None))\n sInvertSubSSL1B_frag = cute.logical_divide(\n sInvertSubSSL1B, ((sub_tile_size, None), None)\n )\n tile_frags = corr_tile_size // sub_tile_size\n if sub_widx == 2 or sub_widx == 3:\n sub_id_row = sub_widx - 2\n for col in cutlass.range_constexpr(tile_frags):\n col_true = (lane_id + col) % (tile_frags)\n sInvertSubSSL1B_frag[\n ((None, (col_true, 0)), lane_id % 8),\n 0,\n lane_id // 8 + sub_id_row * 4,\n 0,\n ].store(tmem_frag[((None, col_true), 0), 0, 0].load())\n\n # tile 0\n for i in cutlass.range_constexpr(32 // corr_tile_size):\n tTMEM_LOADtO_i = cute.make_tensor(\n tTMEM_LOADtO.iterator + i * corr_tile_size, tTMEM_LOADtO.layout\n )\n\n cute.copy(tiled_tmem_load, tTMEM_LOADtO_i, tTMEM_LOADrS)\n cute.arch.fence_view_async_tmem_load()\n if sub_widx == 2 or sub_widx == 3:\n sub_id_row = sub_widx - 2\n idx = (i * corr_tile_size) // sub_tile_size\n for j in cutlass.range_constexpr(tile_frags):\n col_true = (idx + j) % 8\n # todo: remove smem bank conflict\n sInvertSubSSL1B_frag[\n ((None, (col_true, 0)), lane_id % 8),\n 0,\n lane_id // 8 + sub_id_row * 4,\n 0,\n ].store(tmem_frag[((None, j), 0), 0, 0].load())\n # tile 1\n for i in cutlass.range_constexpr(32 // corr_tile_size):\n tTMEM_LOADtO_i = cute.make_tensor(\n tTMEM_LOADtO.iterator + 32 + i * corr_tile_size, tTMEM_LOADtO.layout\n )\n\n cute.copy(tiled_tmem_load, tTMEM_LOADtO_i, tTMEM_LOADrS)\n cute.arch.fence_view_async_tmem_load()\n if sub_widx == 2 or sub_widx == 3:\n sub_id_row = sub_widx - 2\n idx = (i * corr_tile_size) // sub_tile_size\n for j in cutlass.range_constexpr(tile_frags):\n col_true = (idx + j) % 8\n # todo: remove smem bank conflict\n sInvertSubSSL1B_frag[\n ((None, (col_true, 1)), lane_id % 8),\n 0,\n lane_id // 8 + sub_id_row * 4,\n 0,\n ].store(tmem_frag[((None, j), 0), 0, 0].load())\n\n @cute.jit\n def store_ivt_p1(\n self,\n sReg: cute.Tensor,\n sInvertSubTSL0B: cute.Tensor,\n ):\n \"\"\"Store sub-inverse register results p1 to smem.\"\"\"\n tidx, _, _ = cute.arch.thread_idx()\n widx = cute.arch.warp_idx()\n lane_id = cute.arch.lane_idx()\n\n sub_widx = widx % 4\n\n sInvertSubTSL0B_frag = cute.logical_divide(sInvertSubTSL0B, ((4, None), None))\n if sub_widx == 0 or sub_widx == 2:\n sub_id_row = sub_widx // 2\n for col in cutlass.range_constexpr(8):\n col_true = (lane_id + col) % 8\n sInvertSubTSL0B_frag[\n ((None, (col_true, sub_id_row)), lane_id % 8), 0, lane_id // 8, 0\n ].store(sReg[(None, tidx % 128), col_true].load())\n\n cute.arch.fence_proxy(\n cute.arch.ProxyKind.async_shared,\n space=cute.arch.SharedSpace.shared_cta,\n )\n\n @cute.jit\n def store_ivt_p2(\n self,\n sReg: cute.Tensor,\n sInvertSubSSL1A: cute.Tensor,\n ):\n \"\"\"Store sub-inverse register results p2 to smem.\"\"\"\n tidx, _, _ = cute.arch.thread_idx()\n widx = cute.arch.warp_idx()\n lane_id = cute.arch.lane_idx()\n\n sub_widx = widx % 4\n sInvertSubSSL1A_frag = cute.logical_divide(sInvertSubSSL1A, ((None, 4), None))\n zeros = cute.zeros_like(cute.make_layout((4, 1)), self.acc_dtype)\n if sub_widx == 2 or sub_widx == 3:\n sub_id_row = sub_widx - 2\n for col in cutlass.range_constexpr(8):\n sInvertSubSSL1A_frag[\n (sub_id_row * 32 + lane_id, (None, col % 2)),\n 0,\n (col // 2, sub_id_row),\n 0,\n ].store(sReg[(None, tidx % 128), col].load())\n\n if sub_widx == 0 or sub_widx == 1:\n for col in cutlass.range_constexpr(4):\n col_true = col + sub_widx * 4\n sInvertSubSSL1A_frag[\n (lane_id, (None, col_true % 2)), 0, (col_true // 2, 1), 0\n ].store(zeros)\n cute.arch.fence_proxy(\n cute.arch.ProxyKind.async_shared,\n space=cute.arch.SharedSpace.shared_cta,\n )\n\n @cute.jit\n def store_ivt_p3(\n self,\n sReg: cute.Tensor,\n sInvertSubTSL1B: cute.Tensor,\n ):\n \"\"\"Store sub-inverse register results p3 to smem .\"\"\"\n tidx, _, _ = cute.arch.thread_idx()\n widx = cute.arch.warp_idx()\n lane_id = cute.arch.lane_idx()\n\n sub_widx = widx % 4\n sInvertSubTSL1B_frag = cute.logical_divide(sInvertSubTSL1B, ((4, None), None))\n if sub_widx == 0 or sub_widx == 1:\n sub_id_row = sub_widx\n for col in cutlass.range_constexpr(8):\n col_true = (lane_id + col) % 8\n sInvertSubTSL1B_frag[\n ((None, (col_true, sub_id_row)), lane_id % 8),\n 0,\n lane_id // 8 + 4 * sub_id_row,\n 0,\n ].store(sReg[(None, tidx % 128), col_true].load())\n zeros = cute.zeros_like(cute.make_layout((4, 1)), self.acc_dtype)\n\n if sub_widx == 2 or sub_widx == 3:\n sub_id_row = sub_widx - 2\n for col in cutlass.range_constexpr(4):\n col_true = (lane_id + col + sub_id_row * 4) % 8\n sInvertSubTSL1B_frag[\n ((None, (col_true, 1)), lane_id % 8), 0, lane_id // 8 + 0, 0\n ].store(zeros)\n cute.arch.fence_proxy(\n cute.arch.ProxyKind.async_shared,\n space=cute.arch.SharedSpace.shared_cta,\n )\n\n @cute.jit\n def load_store_tmem_tune(\n self,\n thr_mma: cute.ThrMma,\n tIn: cute.Tensor,\n tOut: cute.Tensor, # unused utility for TMEM round-trip debugging\n ):\n tidx, _, _ = cute.arch.thread_idx()\n thread_idx = tidx % (self.threads_per_warp * (len(self.cudacore_warp_ids)))\n\n cIn = cute.make_identity_tensor((128, 128))\n tOcO = thr_mma.partition_C(cIn)\n\n corr_tile_size = 16\n tIn_i_layout = cute.composition(\n tIn.layout, cute.make_layout((128, corr_tile_size))\n )\n cIn_i_layout = cute.composition(\n tOcO.layout, cute.make_layout((128, corr_tile_size))\n )\n\n tOut_i_layout = cute.composition(\n tOut.layout, cute.make_layout((128, corr_tile_size))\n )\n\n tIn_i = cute.make_tensor(tIn.iterator, tIn_i_layout)\n cIn_i = cute.make_tensor(cIn.iterator, cIn_i_layout)\n\n tOut_i = cute.make_tensor(tOut.iterator, tOut_i_layout)\n\n tmem_load_atom = cute.make_copy_atom(\n tcgen05.copy.Ld32x32bOp(tcgen05.copy.Repetition(corr_tile_size)),\n self.acc_dtype,\n )\n tmem_store_atom = cute.make_copy_atom(\n tcgen05.copy.St32x32bOp(tcgen05.copy.Repetition(corr_tile_size)),\n self.acc_dtype,\n )\n\n tiled_tmem_load = tcgen05.make_tmem_copy(tmem_load_atom, tIn_i)\n tiled_tmem_store = tcgen05.make_tmem_copy(tmem_store_atom, tOut_i)\n\n thr_tmem_load = tiled_tmem_load.get_slice(thread_idx)\n thr_tmem_store = tiled_tmem_store.get_slice(thread_idx)\n\n tTMEM_LOADtO = thr_tmem_load.partition_S(tIn_i)\n tTMEM_LOADcO = thr_tmem_load.partition_D(cIn_i)\n\n tTMEM_STOREtO = thr_tmem_store.partition_D(tOut_i)\n\n tTMrO = cute.make_rmem_tensor(\n (tTMEM_LOADcO.shape, 128 // corr_tile_size), self.acc_dtype\n )\n\n for i in cutlass.range_constexpr(128 // corr_tile_size):\n tTMrO_i_ = tTMrO[None, i]\n tTMrO_i_layout = cute.composition(\n tTMrO_i_.layout, cute.make_layout(tTMrO.shape[0])\n )\n tTMrO_i = cute.make_tensor(tTMrO_i_.iterator, tTMrO_i_layout)\n tTMEM_LOADtO_i = cute.make_tensor(\n tTMEM_LOADtO.iterator + i * corr_tile_size, tTMEM_LOADtO.layout\n )\n tTMEM_STOREtO_i = cute.make_tensor(\n tTMEM_STOREtO.iterator + i * corr_tile_size, tTMEM_STOREtO.layout\n )\n\n cute.copy(tiled_tmem_load, tTMEM_LOADtO_i, tTMrO_i)\n\n for j in cutlass.range_constexpr(0, cute.size(tTMrO_i), 2):\n tTMrO_i[j], tTMrO_i[j + 1] = cute.arch.mul_packed_f32x2(\n (tTMrO_i[j], tTMrO_i[j + 1]),\n (cutlass.Float32(1), cutlass.Float32(1)),\n )\n\n # store\n cute.copy(tiled_tmem_store, tTMrO_i, tTMEM_STOREtO_i)\n\n @cute.jit\n def read_tmem_128(\n self,\n tIn: cute.Tensor,\n ):\n \"\"\"Read a 128-element vector from TMEM into registers.\"\"\"\n tidx, _, _ = cute.arch.thread_idx()\n\n thread_idx = tidx % (self.threads_per_warp * (len(self.cudacore_warp_ids)))\n\n tIn_layout = cute.composition(tIn.layout, cute.make_layout((tIn.shape)))\n tIn = cute.make_tensor(tIn.iterator, tIn_layout)\n\n # Load from tmem\n copy_atom_t2r = cute.make_copy_atom(\n tcgen05.copy.Ld32x32bOp(tcgen05.copy.Repetition(32)),\n self.acc_dtype,\n )\n\n tiled_copy_t2r = tcgen05.make_tmem_copy(copy_atom_t2r, tIn)\n thr_copy_t2r = tiled_copy_t2r.get_slice(thread_idx)\n tTR_tO = thr_copy_t2r.partition_S(tIn)\n tTR_cO = thr_copy_t2r.partition_D(tIn)\n\n tTR_rO = cute.make_rmem_tensor(tTR_cO.shape, self.acc_dtype)\n\n tTR_tO = cute.group_modes(tTR_tO, 1, cute.rank(tTR_tO))\n tTR_rO = cute.group_modes(tTR_rO, 1, cute.rank(tTR_rO))\n cute.copy(tiled_copy_t2r, tTR_tO, tTR_rO)\n cute.arch.fence_view_async_tmem_load()\n\n return tTR_rO\n\n @cute.jit\n def load_v(\n self,\n tIn: cute.Tensor,\n sNewV: cute.Tensor,\n ):\n \"\"\"Load V_new from TMEM, convert to f16, store to smem.\"\"\"\n tidx, _, _ = cute.arch.thread_idx()\n\n thread_idx = tidx % (self.threads_per_warp * (len(self.cudacore_warp_ids)))\n\n tIn_layout = cute.composition(tIn.layout, cute.make_layout((tIn.shape)))\n tIn = cute.make_tensor(tIn.iterator, tIn_layout)\n\n # Load from tmem\n copy_atom_t2r = cute.make_copy_atom(\n tcgen05.copy.Ld32x32bOp(tcgen05.copy.Repetition(32)),\n self.acc_dtype,\n )\n\n tiled_copy_t2r = tcgen05.make_tmem_copy(copy_atom_t2r, tIn)\n thr_copy_t2r = tiled_copy_t2r.get_slice(thread_idx)\n\n tTR_tO = thr_copy_t2r.partition_S(tIn)\n tTR_cO = thr_copy_t2r.partition_D(tIn)\n\n tTR_rO = cute.make_rmem_tensor(tTR_cO.shape, self.acc_dtype)\n\n tTR_tO = cute.group_modes(tTR_tO, 1, cute.rank(tTR_tO))\n tTR_rO = cute.group_modes(tTR_rO, 1, cute.rank(tTR_rO))\n cute.copy(tiled_copy_t2r, tTR_tO, tTR_rO)\n cute.arch.fence_view_async_tmem_load()\n\n tTR_rO_e = cute.make_rmem_tensor(tTR_cO.shape, self.i_dtype)\n frg_cnt = 16\n frg_tile = cute.size(tTR_rO) // frg_cnt\n tTR_rO_frg = cute.logical_divide(tTR_rO, cute.make_layout(frg_tile))\n tTR_rO_e_frg = cute.logical_divide(tTR_rO_e, cute.make_layout(frg_tile))\n for j in cutlass.range_constexpr(frg_cnt):\n r_vec = tTR_rO_frg[None, j].load()\n tTR_rO_e_frg[None, j].store(r_vec.to(self.i_dtype))\n\n sNewV_frg = cute.logical_divide(sNewV, cute.make_layout(frg_tile))\n for it in cutlass.range_constexpr(0, 16):\n sNewV_frg[None, (it, thread_idx)].store(tTR_rO_e_frg[None, it].load())\n\n cute.arch.fence_proxy(\n cute.arch.ProxyKind.async_shared,\n space=cute.arch.SharedSpace.shared_cta,\n )\n\n @cute.jit\n def load_ivt_result(\n self,\n tIn: cute.Tensor,\n sD: cute.Tensor,\n ):\n tidx, _, _ = cute.arch.thread_idx()\n lane_id = tidx % 32\n warp_id = cute.arch.warp_idx() % 4\n\n thread_idx = tidx % (self.threads_per_warp * (len(self.cudacore_warp_ids)))\n\n tIn_layout = cute.composition(tIn.layout, cute.make_layout((tIn.shape)))\n tIn = cute.make_tensor(tIn.iterator, tIn_layout)\n\n # Load from tmem\n copy_atom_t2r = cute.make_copy_atom(\n tcgen05.copy.Ld16x256bOp(tcgen05.copy.Repetition(4)),\n self.acc_dtype,\n )\n\n tiled_copy_t2r = tcgen05.make_tmem_copy(copy_atom_t2r, tIn)\n thr_copy_t2r = tiled_copy_t2r.get_slice(thread_idx)\n tTR_tO = thr_copy_t2r.partition_S(tIn)\n tTR_cO = thr_copy_t2r.partition_D(tIn)\n\n tTR_rO = cute.make_rmem_tensor(tTR_cO.shape, self.acc_dtype)\n\n tTR_tO = cute.group_modes(tTR_tO, 1, cute.rank(tTR_tO))\n tTR_rO = cute.group_modes(tTR_rO, 1, cute.rank(tTR_rO))\n cute.copy(tiled_copy_t2r, tTR_tO, tTR_rO)\n cute.arch.fence_view_async_tmem_load()\n\n tTR_rO_e = cute.make_rmem_tensor(tTR_cO.shape, self.q_dtype)\n\n frg_cnt = 2\n frg_tile = cute.size(tTR_rO) // frg_cnt\n tTR_rO_frg = cute.logical_divide(tTR_rO, cute.make_layout(frg_tile))\n tTR_rO_e_frg = cute.logical_divide(tTR_rO_e, cute.make_layout(frg_tile))\n for j in cutlass.range_constexpr(frg_cnt):\n r_vec = -tTR_rO_frg[None, j].load()\n tTR_rO_e_frg[None, j].store(r_vec.to(self.q_dtype))\n\n tTR_rO_e_f32 = cute.recast_tensor(src=tTR_rO_e, dtype=cutlass.Float32)\n\n for it in cutlass.range_constexpr(0, 8):\n sD[\n ((64 + warp_id * 16 + (lane_id // 4) + 0), (lane_id % 4, it % 2)),\n it // 2,\n ] = tTR_rO_e_f32[it * 2]\n sD[\n ((64 + warp_id * 16 + (lane_id // 4) + 8), (lane_id % 4, it % 2)),\n it // 2,\n ] = tTR_rO_e_f32[it * 2 + 1]\n\n cute.arch.fence_proxy(\n cute.arch.ProxyKind.async_shared,\n space=cute.arch.SharedSpace.shared_cta,\n )\n\n @cute.jit\n def apply_gamma_beta(\n self,\n thr_mma: cute.ThrMma,\n sIvt: cute.Tensor,\n tIn: cute.Tensor,\n beta_val: cutlass.Float32,\n tGamma: cute.Tensor,\n ):\n \"\"\"Apply gamma*beta to KK^T in TMEM.\"\"\"\n tidx, _, _ = cute.arch.thread_idx()\n lane_id = tidx % 32\n warp_id = cute.arch.warp_idx() % 4\n sub_widx = warp_id % 4\n thread_idx = tidx % (self.threads_per_warp * (len(self.cudacore_warp_ids)))\n\n cIn = cute.make_identity_tensor((128, 128))\n tOcO = thr_mma.partition_C(cIn)\n\n corr_tile_size = 32 # only 8 or 32\n tIn_i_layout = cute.composition(\n tIn.layout, cute.make_layout((128, corr_tile_size))\n )\n cIn_i_layout = cute.composition(\n tOcO.layout, cute.make_layout((128, corr_tile_size))\n )\n tIn_i = cute.make_tensor(tIn.iterator, tIn_i_layout)\n\n tOut_i = cute.make_tensor(tIn.iterator, tIn_i_layout)\n cOut_i = cute.make_tensor(tOcO.iterator, cIn_i_layout)\n\n tGamma_i = cute.make_tensor(tGamma.iterator, tIn_i_layout)\n cIn_i = cute.make_tensor(cIn.iterator, cIn_i_layout)\n\n tmem_load_atom = cute.make_copy_atom(\n tcgen05.copy.Ld32x32bOp(tcgen05.copy.Repetition(corr_tile_size)),\n self.acc_dtype,\n )\n\n tmem_store_atom = cute.make_copy_atom(\n tcgen05.copy.St32x32bOp(tcgen05.copy.Repetition(corr_tile_size)),\n self.acc_dtype,\n )\n\n tiled_tmem_store = tcgen05.make_tmem_copy(tmem_store_atom, tOut_i)\n thr_tmem_store = tiled_tmem_store.get_slice(thread_idx)\n\n tTMEM_STOREcS = thr_tmem_store.partition_S(cOut_i)\n tTMEM_STOREtO = thr_tmem_store.partition_D(tOut_i)\n\n tTMEM_STORErS = cute.make_rmem_tensor(tTMEM_STOREcS.shape, self.acc_dtype)\n\n # Load In\n tiled_tmem_load = tcgen05.make_tmem_copy(tmem_load_atom, tIn_i)\n thr_tmem_load = tiled_tmem_load.get_slice(thread_idx)\n\n # Load Gamma\n tiled_tmem_load_gamma = tcgen05.make_tmem_copy(tmem_load_atom, tGamma_i)\n thr_tmem_load_gamma = tiled_tmem_load_gamma.get_slice(thread_idx)\n\n tTMEM_LOADtO = thr_tmem_load.partition_S(tIn_i)\n tTMEM_LOADcO = thr_tmem_load.partition_D(cIn_i)\n\n tTMEM_LOADtG = thr_tmem_load_gamma.partition_S(tGamma_i)\n tTMEM_LOADrG = cute.make_rmem_tensor(tTMEM_LOADcO.shape, self.acc_dtype)\n\n tTMEM_LOADrS = cute.make_tensor(\n cute.recast_ptr(tTMEM_STORErS.iterator, dtype=self.acc_dtype),\n tTMEM_LOADrG.layout,\n )\n\n frg_tile = 4\n\n # Store to smem\n # ((32, 32), 4)\n lower_D_frag = cute.logical_divide(tTMEM_STORErS, ((4, None), None))\n sIvt_frag = cute.logical_divide(sIvt, ((4, None), None))\n\n for i in cutlass.range_constexpr(128 // corr_tile_size):\n tTMEM_LOADtO_i = cute.make_tensor(\n tTMEM_LOADtO.iterator + i * corr_tile_size, tTMEM_LOADtO.layout\n )\n tTMEM_LOADtG_i = cute.make_tensor(\n tTMEM_LOADtG.iterator + i * corr_tile_size, tTMEM_LOADtO.layout\n )\n\n tTMEM_STOREtO_i = cute.make_tensor(\n tTMEM_STOREtO.iterator + i * corr_tile_size, tTMEM_STOREtO.layout\n )\n\n cute.copy(tiled_tmem_load_gamma, tTMEM_LOADtG_i, tTMEM_LOADrG)\n each_iter = corr_tile_size // frg_tile\n tTMEM_LOADrG_frg = cute.logical_divide(\n tTMEM_LOADrG, ((frg_tile, None), None)\n )\n for j in cutlass.range_constexpr(each_iter):\n for inner_idx in cutlass.range_constexpr(0, frg_tile, 2):\n (\n tTMEM_LOADrG_frg[((inner_idx + 0, j), i), 0, 0],\n tTMEM_LOADrG_frg[((inner_idx + 1, j), i), 0, 0],\n ) = cute.arch.mul_packed_f32x2(\n (\n tTMEM_LOADrG_frg[((inner_idx + 0, j), i), 0, 0],\n tTMEM_LOADrG_frg[((inner_idx + 1, j), i), 0, 0],\n ),\n (\n beta_val,\n beta_val,\n ),\n )\n cute.copy(tiled_tmem_load, tTMEM_LOADtO_i, tTMEM_LOADrS)\n cute.arch.fence_view_async_tmem_load()\n\n tTMEM_LOADrS_frg = cute.logical_divide(\n tTMEM_LOADrS, ((frg_tile, None), None)\n )\n\n if (i * corr_tile_size) < ((sub_widx + 1) * 32):\n for j in cutlass.range_constexpr(each_iter):\n for inner_idx in cutlass.range_constexpr(0, frg_tile, 2):\n (\n tTMEM_LOADrS_frg[((inner_idx + 0, j), i), 0, 0],\n tTMEM_LOADrS_frg[((inner_idx + 1, j), i), 0, 0],\n ) = cute.arch.mul_packed_f32x2(\n (\n tTMEM_LOADrS_frg[((inner_idx + 0, j), i), 0, 0],\n tTMEM_LOADrS_frg[((inner_idx + 1, j), i), 0, 0],\n ),\n (\n tTMEM_LOADrG_frg[((inner_idx + 0, j), i), 0, 0],\n tTMEM_LOADrG_frg[((inner_idx + 1, j), i), 0, 0],\n ),\n )\n cute.copy(tiled_tmem_store, tTMEM_STORErS, tTMEM_STOREtO_i)\n\n tile_frags = corr_tile_size // 4\n if (i * corr_tile_size) >= sub_widx * 32 and (i * corr_tile_size) < (\n sub_widx + 1\n ) * 32:\n idx = (i * corr_tile_size - sub_widx * 32) // 4\n for j in cutlass.range_constexpr(tile_frags):\n true_col = j + idx\n sIvt_frag[((None, true_col), lane_id), sub_widx].store(\n lower_D_frag[((None, j), 0), 0, 0].load()\n )\n\n @cute.jit\n def compute_gamma_tmem(\n self,\n val: cutlass.Float32,\n sGateCumsum: cute.Tensor,\n thr_mma: cute.ThrMma,\n tOut: cute.Tensor,\n bar_id: Int32,\n mask: cutlass.Constexpr[cutlass.Boolean] = False,\n tail_count: Int32 = 128,\n ):\n \"\"\"Build the 128x128 causal gamma matrix in TMEM: gamma[i,j] = exp(cumsum[i] - cumsum[j]) for j <= i.\"\"\"\n tidx, _, _ = cute.arch.thread_idx()\n thread_idx = tidx % 128\n\n cute.arch.barrier(\n barrier_id=bar_id,\n number_of_threads=len(self.cudacore_warp_ids) * 32,\n )\n\n cIn = cute.make_identity_tensor((128, 128))\n tOcO = thr_mma.partition_C(cIn)\n\n corr_tile_size = 128\n\n cOut_i_layout = cute.composition(\n tOcO.layout, cute.make_layout((128, corr_tile_size))\n )\n tOut_i_layout = cute.composition(\n tOut.layout, cute.make_layout((128, corr_tile_size))\n )\n\n tOut_i = cute.make_tensor(tOut.iterator, tOut_i_layout)\n cOut_i = cute.make_tensor(tOcO.iterator, cOut_i_layout)\n\n tmem_store_atom = cute.make_copy_atom(\n tcgen05.copy.St32x32bOp(tcgen05.copy.Repetition(corr_tile_size)),\n self.acc_dtype,\n )\n\n tiled_tmem_store = tcgen05.make_tmem_copy(tmem_store_atom, tOut_i)\n thr_tmem_store = tiled_tmem_store.get_slice(thread_idx)\n\n tTMEM_STOREcS = thr_tmem_store.partition_S(cOut_i)\n tTMEM_STOREtO = thr_tmem_store.partition_D(tOut_i)\n\n tTMEM_STORErS = cute.make_rmem_tensor(tTMEM_STOREcS.shape, self.acc_dtype)\n\n frg_tile = 32\n sGateCumsum_tile = cute.flat_divide(\n sGateCumsum, cute.make_layout(corr_tile_size)\n )\n sGateCumsum_frag = cute.logical_divide(sGateCumsum_tile, (frg_tile, None))\n\n zeros = cute.zeros_like(cute.make_layout((frg_tile, 1)), self.acc_dtype)\n\n for i in cutlass.range_constexpr(128 // corr_tile_size):\n tTMEM_STOREtO_i = cute.make_tensor(\n tTMEM_STOREtO.iterator + i * corr_tile_size, tTMEM_STOREtO.layout\n )\n\n tTMEM_STORErS_frag = cute.logical_divide(\n tTMEM_STORErS, cute.make_layout(frg_tile)\n )\n for it in cutlass.range_constexpr(corr_tile_size // frg_tile):\n tile_offset = i * corr_tile_size + it * frg_tile\n\n if (\n (\n tile_offset <= thread_idx\n and tile_offset < tail_count\n and thread_idx < tail_count\n )\n if cutlass.const_expr(mask)\n else (tile_offset <= thread_idx)\n ):\n curr_val_frag_ssa = sGateCumsum_frag[(None, it), i].load()\n\n new_val_frag = cute.math.exp(val - curr_val_frag_ssa, fastmath=True)\n\n for inner_idx in cutlass.range_constexpr(0, frg_tile):\n offset = tile_offset + inner_idx\n curr_val = new_val_frag[inner_idx]\n\n if offset <= thread_idx:\n tTMEM_STORErS_frag[inner_idx, it] = curr_val\n else:\n tTMEM_STORErS_frag[inner_idx, it] = cutlass.Float32(0)\n else:\n tTMEM_STORErS_frag[None, it].store(zeros)\n\n # store\n cute.copy(tiled_tmem_store, tTMEM_STORErS, tTMEM_STOREtO_i)\n cute.arch.fence_view_async_tmem_store()\n\n @cute.jit\n def chunk_local_cumsum(\n self,\n sGate: cute.Tensor,\n sGateCumsum: cute.Tensor,\n bar_id: Int32,\n ) -> cutlass.Float32:\n \"\"\"Compute inclusive prefix sum of gate values within a 128-token chunk.\"\"\"\n tidx, _, _ = cute.arch.thread_idx()\n lane_id = tidx % 32\n warp_id = cute.arch.warp_idx() % 4\n tidx_in_group = tidx % 128\n\n val = sGate[tidx_in_group]\n stride = 1\n clamp_value = 0\n while stride < 32:\n shfl_value = cute.arch.shuffle_sync_op(\n value=val,\n offset=stride,\n mask_and_clamp=clamp_value,\n kind=nvvm.ShflKind.up,\n )\n if lane_id >= stride:\n val += shfl_value\n\n stride = stride << 1\n if lane_id == 31:\n sGateCumsum[warp_id] = val\n\n cute.arch.barrier(\n barrier_id=bar_id,\n number_of_threads=len(self.cudacore_warp_ids) * 32,\n )\n\n if warp_id == 1:\n pre_warp_val = sGateCumsum[0]\n val = val + pre_warp_val\n if warp_id == 2:\n sGateCumsum_f2 = cute.flat_divide(sGateCumsum, (2, 1))\n warp_sum = sGateCumsum_f2[None, 0, 0, 0]\n pre_warp_val = warp_sum[0] + warp_sum[1]\n val = val + pre_warp_val\n if warp_id == 3:\n sGateCumsum_f4 = cute.flat_divide(sGateCumsum, (4, 1))\n warp_sum = sGateCumsum_f4[None, 0, 0, 0]\n pre_warp_val = warp_sum[0] + warp_sum[1] + warp_sum[2]\n val = val + pre_warp_val\n\n cute.arch.barrier(\n barrier_id=bar_id,\n number_of_threads=len(self.cudacore_warp_ids) * 32,\n )\n\n sGateCumsum[tidx_in_group] = val\n\n return val\n\n @cute.jit\n def save_tmem(\n self,\n tSIn: cute.Tensor,\n sD: cute.Tensor,\n ) -> cute.Tensor:\n tidx, _, _ = cute.arch.thread_idx()\n widx = cute.arch.warp_idx()\n lane_id = cute.arch.lane_idx()\n sub_widx = widx % 4\n\n thread_idx = tidx % (self.threads_per_warp * (len(self.cudacore_warp_ids)))\n\n tSIn_layout = cute.composition(tSIn.layout, cute.make_layout((tSIn.shape)))\n tSIn0 = cute.make_tensor(tSIn.iterator, tSIn_layout)\n\n # Load from tmem\n copy_atom_t2r = cute.make_copy_atom(\n tcgen05.copy.Ld16x256bOp(tcgen05.copy.Repetition(4)),\n self.acc_dtype,\n )\n tiled_copy_t2r = tcgen05.make_tmem_copy(copy_atom_t2r, tSIn0)\n thr_copy_t2r = tiled_copy_t2r.get_slice(thread_idx)\n tTR_tO = thr_copy_t2r.partition_S(tSIn0)\n tTR_cO = thr_copy_t2r.partition_D(tSIn0)\n tTR_cO_one_iter = tTR_cO[None, 0, 0, 0]\n tTR_rO = cute.make_rmem_tensor(tTR_cO_one_iter.shape, self.acc_dtype)\n\n tTR_tO = cute.group_modes(tTR_tO, 1, cute.rank(tTR_tO))\n\n tTR_rO_e = cute.make_rmem_tensor(tTR_rO.shape, self.q_dtype)\n frg_cnt = 2\n frg_tile = cute.size(tTR_rO) // frg_cnt\n tTR_rO_frg = cute.logical_divide(tTR_rO, cute.make_layout(frg_tile))\n tTR_rO_e_frg = cute.logical_divide(tTR_rO_e, cute.make_layout(frg_tile))\n tTR_rO_e_f32 = cute.recast_tensor(src=tTR_rO_e, dtype=cutlass.Float32)\n for subtile_idx in cutlass.range_constexpr(2):\n tTR_tO_mn = tTR_tO[(None, subtile_idx)]\n cute.copy(tiled_copy_t2r, tTR_tO_mn, tTR_rO)\n cute.arch.fence_view_async_tmem_load()\n\n if (sub_widx == 0 or sub_widx == 1) and subtile_idx == 0:\n for j in cutlass.range_constexpr(frg_cnt):\n r_vec = -tTR_rO_frg[None, j].load()\n tTR_rO_e_frg[None, j].store(r_vec.to(self.q_dtype))\n\n for it in cutlass.range_constexpr(0, 4):\n sD[\n (\n (\n 32\n + (sub_widx // 2) * 64\n + (sub_widx % 2) * 16\n + (lane_id // 4)\n + 0\n ),\n (lane_id % 4, it % 2),\n ),\n it // 2 + (sub_widx // 2) * 4,\n ] = tTR_rO_e_f32[it * 2]\n sD[\n (\n (\n 32\n + (sub_widx // 2) * 64\n + (sub_widx % 2) * 16\n + (lane_id // 4)\n + 8\n ),\n (lane_id % 4, it % 2),\n ),\n it // 2 + (sub_widx // 2) * 4,\n ] = tTR_rO_e_f32[it * 2 + 1]\n\n if (sub_widx == 2 or sub_widx == 3) and subtile_idx == 1:\n for j in cutlass.range_constexpr(frg_cnt):\n r_vec = -tTR_rO_frg[None, j].load()\n tTR_rO_e_frg[None, j].store(r_vec.to(self.q_dtype))\n\n for it in cutlass.range_constexpr(0, 4):\n sD[\n (\n (\n 32\n + (sub_widx // 2) * 64\n + (sub_widx % 2) * 16\n + (lane_id // 4)\n + 0\n ),\n (lane_id % 4, it % 2),\n ),\n it // 2 + (sub_widx // 2) * 4,\n ] = tTR_rO_e_f32[it * 2]\n sD[\n (\n (\n 32\n + (sub_widx // 2) * 64\n + (sub_widx % 2) * 16\n + (lane_id // 4)\n + 8\n ),\n (lane_id % 4, it % 2),\n ),\n it // 2 + (sub_widx // 2) * 4,\n ] = tTR_rO_e_f32[it * 2 + 1]\n\n @cute.jit\n def load_ivt_ts_l0(\n self,\n tSIn: cute.Tensor,\n sInvertSubSSL1A: cute.Tensor,\n sInvertSubTSL1B: cute.Tensor,\n ) -> cute.Tensor:\n tidx, _, _ = cute.arch.thread_idx()\n widx = cute.arch.warp_idx()\n lane_id = cute.arch.lane_idx()\n sub_widx = widx % 4\n\n thread_idx = tidx % (self.threads_per_warp * (len(self.cudacore_warp_ids)))\n\n tSIn_layout = cute.composition(tSIn.layout, cute.make_layout((tSIn.shape)))\n tSIn0 = cute.make_tensor(tSIn.iterator, tSIn_layout)\n\n # Load from tmem\n copy_atom_t2r = cute.make_copy_atom(\n tcgen05.copy.Ld16x128bOp(tcgen05.copy.Repetition(8)), # todo\n self.acc_dtype,\n )\n tiled_copy_t2r = tcgen05.make_tmem_copy(copy_atom_t2r, tSIn0)\n thr_copy_t2r = tiled_copy_t2r.get_slice(thread_idx)\n tTR_tO = thr_copy_t2r.partition_S(tSIn0)\n tTR_cO = thr_copy_t2r.partition_D(tSIn0)\n tTR_cO_one_iter = tTR_cO[None, 0, 0, 0]\n tTR_rO = cute.make_rmem_tensor(tTR_cO_one_iter.shape, self.acc_dtype)\n\n tTR_rO_s = cute.make_tensor(\n cute.recast_ptr(tTR_rO.iterator, dtype=self.acc_dtype),\n cute.shape(tTR_cO_one_iter)[0],\n )\n\n tTR_tO = cute.group_modes(tTR_tO, 1, cute.rank(tTR_tO))\n\n for subtile_idx in cutlass.range_constexpr(2):\n tTR_tO_mn = tTR_tO[(None, subtile_idx)]\n cute.copy(tiled_copy_t2r, tTR_tO_mn, tTR_rO)\n cute.arch.fence_view_async_tmem_load()\n\n if (sub_widx == 0 or sub_widx == 1) and subtile_idx == 0:\n sInvertSubTSL1B_frag = cute.logical_divide(\n sInvertSubTSL1B, ((4, None), None)\n )\n sub_id_row = sub_widx\n for col in cutlass.range_constexpr(0, 8):\n col_true = (lane_id // 4 + col) % 8\n sInvertSubTSL1B_frag[\n ((lane_id % 4, (col_true, 0)), lane_id // 4),\n 0,\n 4 + sub_id_row * 2 + 0,\n 0,\n ] = -tTR_rO_s[(0, col_true), 0]\n sInvertSubTSL1B_frag[\n ((lane_id % 4, (col_true, 0)), lane_id // 4),\n 0,\n 4 + sub_id_row * 2 + 1,\n 0,\n ] = -tTR_rO_s[(1, col_true), 0]\n if (sub_widx == 2 or sub_widx == 3) and subtile_idx == 1:\n tTR_rO_s_frag_f1 = cute.logical_divide(\n cute.flatten(tTR_rO_s[None, 0]), (1, None)\n )\n sInvertSubSSL1A_frag_f1 = cute.logical_divide(\n sInvertSubSSL1A, ((None, 1), None)\n )\n sub_id_row = sub_widx - 2\n for it in cutlass.range_constexpr(0, 8):\n col_offset = it % 2 * 4\n sInvertSubSSL1A_frag_f1[\n (\n 32 + sub_id_row * 16 + 0 + lane_id // 4,\n (None, col_offset + lane_id % 4),\n ),\n 0,\n (it // 2, 0),\n 0,\n ].store(-tTR_rO_s_frag_f1[(None, 0), it].load())\n sInvertSubSSL1A_frag_f1[\n (\n 32 + sub_id_row * 16 + 8 + lane_id // 4,\n (None, col_offset + lane_id % 4),\n ),\n 0,\n (it // 2, 0),\n 0,\n ].store(-tTR_rO_s_frag_f1[(None, 1), it].load())\n\n cute.arch.fence_proxy(\n cute.arch.ProxyKind.async_shared,\n space=cute.arch.SharedSpace.shared_cta,\n )\n\n @cute.jit\n def store_ivt_c(\n self,\n sD: cute.Tensor,\n ):\n \"\"\"Zero out off-diagonal blocks in the assembled inverse matrix (block identity structure).\"\"\"\n widx = cute.arch.warp_idx()\n lane_id = cute.arch.lane_idx()\n sub_widx = widx % 4\n\n zeros = cute.zeros_like(cute.make_layout((4, 1)), self.acc_dtype)\n for it in cutlass.range_constexpr(0, 4):\n row = sub_widx // 2 * 32 + lane_id\n col_block_inner = it % 2\n col_block = 4 + (sub_widx % 2) * 2 + it // 2\n sD[(row, (None, col_block_inner)), col_block].store(zeros[None, 0])\n for it in cutlass.range_constexpr(0, 2):\n row = sub_widx // 2 * 64 + lane_id\n col_block_inner = sub_widx % 2\n col_block = (sub_widx // 2) * 4 + 2 + it\n sD[(row, (None, col_block_inner)), col_block].store(zeros[None, 0])\n\n @cute.jit\n def load_ivt_ss_l0(\n self,\n tSIn: cute.Tensor,\n tSOut: cute.Tensor,\n ):\n tidx, _, _ = cute.arch.thread_idx()\n widx = cute.arch.warp_idx()\n sub_widx = widx % 4\n\n thread_idx = tidx % (self.threads_per_warp * (len(self.cudacore_warp_ids)))\n\n tSIn_layout = cute.composition(tSIn.layout, cute.make_layout((tSIn.shape)))\n tSIn0 = cute.make_tensor(tSIn.iterator, tSIn_layout)\n\n # Load from tmem\n copy_atom_t2r = cute.make_copy_atom(\n tcgen05.copy.Ld16x256bOp(tcgen05.copy.Repetition(4)), # 4*8 = 32\n self.acc_dtype,\n )\n\n tiled_copy_t2r = tcgen05.make_tmem_copy(copy_atom_t2r, tSIn0)\n thr_copy_t2r = tiled_copy_t2r.get_slice(thread_idx)\n tTR_tO = thr_copy_t2r.partition_S(tSIn0)\n tTR_cO = thr_copy_t2r.partition_D(tSIn0)\n tTR_cO_one_iter = tTR_cO[(None), 0, 0, 0]\n tTR_rO = cute.make_rmem_tensor(tTR_cO_one_iter.shape, self.acc_dtype)\n\n tTR_tO = cute.group_modes(tTR_tO, 1, cute.rank(tTR_tO))\n\n tSOut_layout = cute.make_layout(\n (((16, 4), 32), 1, 1), stride=(((65536, 2097152), 1), 0, 0)\n )\n tSOut0 = cute.make_tensor(tSOut.iterator, tSOut_layout)\n copy_atom_r2t = cute.make_copy_atom(\n tcgen05.copy.St16x256bOp(tcgen05.copy.Repetition(4)),\n self.acc_dtype,\n )\n tiled_copy_r2t = tcgen05.make_tmem_copy(copy_atom_r2t, tSOut0)\n thr_copy_r2t = tiled_copy_r2t.get_slice(thread_idx)\n tRT_cO = thr_copy_r2t.partition_S(tSOut0)\n tRT_tO = thr_copy_r2t.partition_D(tSOut0)\n tRT_cO_one_iter = tRT_cO[(None), None, 0, 0] #\n tRT_rO = cute.make_rmem_tensor(tRT_cO_one_iter.shape, self.acc_dtype)\n\n for subtile_idx in cutlass.range_constexpr(2):\n tTR_tO_mn = tTR_tO[(None, subtile_idx)]\n cute.copy(tiled_copy_t2r, tTR_tO_mn, tTR_rO)\n cute.arch.fence_view_async_tmem_load()\n\n if (sub_widx == 0 or sub_widx == 1) and subtile_idx == 0:\n for eid in cutlass.range_constexpr(16):\n tRT_rO[eid] = tTR_rO[eid]\n\n if (sub_widx == 2 or sub_widx == 3) and subtile_idx == 1:\n for eid in cutlass.range_constexpr(16):\n tRT_rO[eid] = tTR_rO[eid]\n\n tRT_tO = cute.group_modes(tRT_tO, 2, cute.rank(tRT_tO))\n for subtile_idx in cutlass.range_constexpr(0, 1):\n tRT_tO_mn = tRT_tO[(None, None, subtile_idx)]\n cute.copy(tiled_copy_r2t, tRT_rO, tRT_tO_mn)\n\n cute.arch.fence_view_async_tmem_store()\n\n @cute.jit\n def store_ivt_ad(\n self,\n sReg: cute.Tensor,\n sD: cute.Tensor,\n ):\n \"\"\"Store diagonal block inverse (A/D blocks) from registers to smem.\"\"\"\n tidx, _, _ = cute.arch.thread_idx()\n widx = cute.arch.warp_idx()\n sub_widx = widx % 4\n\n reg_layout = cute.make_layout((4, 2))\n result_e = cute.make_rmem_tensor(reg_layout.shape, self.acc_dtype)\n for it in cutlass.range_constexpr(0, 4):\n result_e[None, 0].store(sReg[(None, tidx % 128), it * 2 + 0].load())\n result_e[None, 1].store(sReg[(None, tidx % 128), it * 2 + 1].load())\n sD[(tidx % 128, (None, it % 2)), 0, sub_widx * 2 + it // 2, 0].store(\n result_e[None].load().to(self.q_dtype)\n )\n\n @cute.jit\n def __call__(\n self,\n q_iter: cute.Pointer,\n k_iter: cute.Pointer,\n v_iter: cute.Pointer,\n o_iter: cute.Pointer,\n g_iter: cute.Pointer,\n beta_iter: cute.Pointer,\n problem_size: Tuple[\n cutlass.Int32,\n cutlass.Int32,\n cutlass.Int32,\n cutlass.Int32,\n cutlass.Int32,\n cutlass.Int32,\n ],\n initial_state_f32_iter: Optional[cute.Pointer],\n state_output: Optional[cute.Pointer],\n scale: Optional[float],\n cum_seqlen_q: Optional[cute.Tensor] = None,\n stream: cuda.CUstream = None,\n ):\n \"\"\"Host-side entry: build tensor layouts, TMA descriptors, smem storage, and launch the kernel.\"\"\"\n\n b, s_q, s_sum, h_q, h_v, d = problem_size\n\n h_r = h_v // h_q\n o_offset = 0 if cum_seqlen_q is None else (-s_q * d * h_r * h_q)\n b_qk = b if cum_seqlen_q is None else s_sum\n b_o = b if cum_seqlen_q is None else s_q * (1 + b)\n b_v = b if cum_seqlen_q is None else s_sum\n\n stride_b_qk = h_q * s_q * d if cum_seqlen_q is None else d * h_q\n stride_b_vo = h_r * h_q * s_q * d if cum_seqlen_q is None else d * h_q * h_r\n\n b_gb = b if cum_seqlen_q is None else 1\n stride_b_gb = h_r * h_q * s_sum if cum_seqlen_q is None else 0\n q_layout = cute.make_layout(\n (s_sum, d, ((h_r, h_q), b_qk)),\n stride=(d * h_q, 1, ((0, d), stride_b_qk)),\n )\n q = cute.make_tensor(q_iter, q_layout)\n\n k_layout = cute.make_layout(\n (s_sum, d, ((h_r, h_q), b_qk)),\n stride=(d * h_q, 1, ((0, d), stride_b_qk)),\n )\n k = cute.make_tensor(k_iter, k_layout)\n v_layout = cute.make_layout(\n (d, s_sum, ((h_r, h_q), b_v)),\n stride=(1, d * h_q * h_r, ((d, d * h_r), stride_b_vo)),\n )\n v = cute.make_tensor(v_iter, v_layout)\n o_layout = cute.make_layout(\n (s_q, d, ((h_r, h_q), b_o)),\n stride=(d * h_r * h_q, 1, ((d, d * h_r), stride_b_vo)),\n )\n o = cute.make_tensor(o_iter + o_offset, o_layout)\n\n state_layout = cute.make_layout(\n (self.head_dim, self.head_dim, ((h_r, h_q), b)),\n stride=(\n self.head_dim,\n 1,\n (\n (\n self.head_dim * self.head_dim,\n h_r * self.head_dim * self.head_dim,\n ),\n h_q * h_r * self.head_dim * self.head_dim,\n ),\n ),\n )\n\n state_input_f32 = (\n None\n if cutlass.const_expr(initial_state_f32_iter is None)\n else cute.make_tensor(initial_state_f32_iter, state_layout)\n )\n state_output = (\n None\n if cutlass.const_expr(state_output is None)\n else cute.make_tensor(state_output, state_layout)\n )\n\n gb_layout = cute.make_layout(\n (s_sum, 1, ((h_r, h_q), b_gb)),\n stride=(h_r * h_q, 0, ((1, h_r), stride_b_gb)),\n )\n gate = cute.make_tensor(g_iter, gb_layout)\n beta = cute.make_tensor(beta_iter, gb_layout)\n\n if cutlass.const_expr(scale is None):\n scale = 1.0 / cute.math.sqrt(cutlass.Float32(d))\n\n # setup static attributes before smem/grid/tma computation\n self.q_dtype = q.element_type\n self.k_dtype = k.element_type\n self.v_dtype = v.element_type\n self.o_dtype = o.element_type\n self.g_dtype = gate.element_type\n self.beta_dtype = beta.element_type\n\n self.i_dtype = self.q_dtype\n\n self.tile_sched_params, grid = self._compute_grid(\n cute.shape((s_q, d, ((h_r, h_q), b))),\n self.cta_tiler,\n self.is_persistent,\n )\n\n self.q_major_mode = utils.LayoutEnum.from_tensor(q).mma_major_mode()\n self.k_major_mode = utils.LayoutEnum.from_tensor(k).mma_major_mode()\n self.v_major_mode = utils.LayoutEnum.from_tensor(v).mma_major_mode()\n self.o_layout = utils.LayoutEnum.from_tensor(o)\n self.s_output = utils.LayoutEnum.ROW_MAJOR\n\n cta_group = tcgen05.CtaGroup.ONE\n\n qk_tiled_mma = sm100_utils.make_trivial_tiled_mma(\n self.q_dtype,\n self.q_major_mode,\n self.k_major_mode,\n self.acc_dtype,\n cta_group,\n self.qk_mma_tiler[:2],\n )\n\n update_s_tiled_mma = sm100_utils.make_trivial_tiled_mma(\n self.i_dtype,\n tcgen05.OperandMajorMode.MN,\n tcgen05.OperandMajorMode.MN,\n self.acc_dtype,\n cta_group,\n self.update_s_mma_tiler[:2],\n )\n\n o_intra_tiled_mma = sm100_utils.make_trivial_tiled_mma(\n self.i_dtype,\n tcgen05.OperandMajorMode.K,\n tcgen05.OperandMajorMode.MN,\n self.acc_dtype,\n cta_group,\n self.o_intra_mma_tiler[:2],\n )\n\n o_intra_tiled_ts_mma_new = sm100_utils.make_trivial_tiled_mma(\n self.i_dtype,\n tcgen05.OperandMajorMode.K,\n tcgen05.OperandMajorMode.MN,\n self.acc_dtype,\n cta_group,\n self.o_intra_mma_tiler[:2],\n tcgen05.OperandSource.TMEM,\n )\n\n qs_tiled_mma = sm100_utils.make_trivial_tiled_mma(\n self.i_dtype,\n tcgen05.OperandMajorMode.K,\n tcgen05.OperandMajorMode.K,\n self.acc_dtype,\n cta_group,\n self.qs_mma_tiler[:2],\n tcgen05.OperandSource.TMEM,\n )\n\n kkt_tiled_mma = sm100_utils.make_trivial_tiled_mma(\n self.k_dtype,\n self.k_major_mode,\n self.k_major_mode,\n self.acc_dtype,\n cta_group,\n self.kkt_mma_tiler[:2],\n )\n\n kst_tiled_mma = sm100_utils.make_trivial_tiled_mma(\n self.i_dtype,\n self.k_major_mode,\n self.k_major_mode,\n self.acc_dtype,\n cta_group,\n self.kst_mma_tiler[:2],\n )\n\n invert_sub_tiled_mma_ss_l0 = sm100_utils.make_trivial_tiled_mma(\n self.invert_type_ab,\n self.k_major_mode,\n tcgen05.OperandMajorMode.MN,\n self.invert_acc_type,\n cta_group,\n self.invert_mma_sub_l0_tiler[:2],\n )\n invert_sub_tiled_mma_ts_l0 = sm100_utils.make_trivial_tiled_mma(\n self.invert_type_ab,\n self.k_major_mode,\n tcgen05.OperandMajorMode.MN,\n self.invert_acc_type,\n cta_group,\n self.invert_mma_sub_l0_tiler[:2],\n tcgen05.OperandSource.TMEM,\n )\n\n invert_sub_tiled_mma_ss_l1 = sm100_utils.make_trivial_tiled_mma(\n self.invert_type_ab,\n self.k_major_mode,\n tcgen05.OperandMajorMode.MN,\n self.invert_acc_type,\n cta_group,\n self.invert_mma_sub_l1_tiler[:2],\n )\n invert_sub_tiled_mma_ts_l1 = sm100_utils.make_trivial_tiled_mma(\n self.invert_type_ab,\n self.k_major_mode,\n tcgen05.OperandMajorMode.MN,\n self.invert_acc_type,\n cta_group,\n self.invert_mma_sub_l1_tiler[:2],\n tcgen05.OperandSource.TMEM,\n )\n\n tuw_tiled_mma = sm100_utils.make_trivial_tiled_mma(\n self.k_dtype,\n self.k_major_mode,\n tcgen05.OperandMajorMode.MN,\n self.acc_dtype,\n cta_group,\n self.tuw_mma_tiler[:2],\n )\n\n self.cluster_layout_vmnk = cute.tiled_divide(\n cute.make_layout(self.cluster_shape_mnk),\n (qk_tiled_mma.thr_id.shape,),\n )\n\n q_smem_layout_staged = sm100_utils.make_smem_layout_a(\n qk_tiled_mma,\n self.qk_mma_tiler,\n self.q_dtype,\n self.q_stage,\n )\n k_smem_layout_staged = sm100_utils.make_smem_layout_b(\n qk_tiled_mma,\n self.qk_mma_tiler,\n self.k_dtype,\n self.kv_stage,\n )\n\n qk_smem_layout_staged = sm100_utils.make_smem_layout_b(\n qk_tiled_mma,\n self.qk_mma_tiler,\n self.i_dtype,\n self.qk_stage,\n )\n\n state_smem_layout_staged = sm100_utils.make_smem_layout_b(\n kst_tiled_mma,\n self.kst_mma_tiler,\n self.i_dtype,\n self.one_stage,\n )\n\n o_intra_smem_layout_staged_a = make_smem_layout_a_kind(\n o_intra_tiled_mma,\n self.o_intra_mma_tiler,\n self.i_dtype,\n self.one_stage,\n cute.nvgpu.tcgen05.SmemLayoutAtomKind.K_INTER,\n )\n\n o_intra_smem_layout_staged_b = make_smem_layout_b_kind(\n o_intra_tiled_mma,\n self.o_intra_mma_tiler,\n self.i_dtype,\n self.one_stage,\n cute.nvgpu.tcgen05.SmemLayoutAtomKind.MN_INTER,\n )\n\n o_intra_smem_layout_staged_a_new = make_smem_layout_a_kind(\n o_intra_tiled_ts_mma_new,\n self.o_intra_mma_tiler,\n self.i_dtype,\n self.one_stage,\n cute.nvgpu.tcgen05.SmemLayoutAtomKind.K_INTER,\n )\n\n qs_smem_layout_staged_a = sm100_utils.make_smem_layout_a(\n qs_tiled_mma,\n self.qs_mma_tiler,\n self.i_dtype,\n self.one_stage,\n )\n\n qs_smem_layout_staged_b = sm100_utils.make_smem_layout_b(\n qs_tiled_mma,\n self.qs_mma_tiler,\n self.i_dtype,\n self.one_stage,\n )\n\n update_s_smem_layout_staged_a = make_smem_layout_a_kind(\n update_s_tiled_mma,\n self.update_s_mma_tiler,\n self.i_dtype,\n self.one_stage,\n cute.nvgpu.tcgen05.SmemLayoutAtomKind.MN_INTER,\n )\n\n update_s_smem_layout_staged_b = make_smem_layout_b_kind(\n update_s_tiled_mma,\n self.update_s_mma_tiler,\n self.i_dtype,\n self.one_stage,\n cute.nvgpu.tcgen05.SmemLayoutAtomKind.MN_INTER,\n )\n\n state_output_smem_layout_staged = make_smem_layout_epi_kind(\n self.state_dtype,\n self.s_output,\n self.state_output_tiler,\n self.one_stage,\n cute.nvgpu.tcgen05.SmemLayoutAtomKind.K_INTER,\n )\n\n o_output_smem_layout_staged = make_smem_layout_epi_kind(\n self.i_dtype,\n self.o_layout,\n self.o_output_tiler,\n self.one_stage,\n cute.nvgpu.tcgen05.SmemLayoutAtomKind.K_INTER,\n )\n\n ivt_smem_layout = cute.make_layout(\n ((36, 32), 4)\n ) # padding, remove smem bank conflict\n # ivt_smem_layout = cute.make_layout(((32, 32), 4)) # padding, remove smem bank conflict\n\n sub_inner_smem_layout_staged = make_smem_layout_a_kind(\n invert_sub_tiled_mma_ss_l0,\n self.invert_mma_sub_l0_tiler,\n self.invert_type_ab,\n self.sub_stage,\n cute.nvgpu.tcgen05.SmemLayoutAtomKind.K_INTER,\n )\n\n invert_sub_smem_layout_staged_ss_l0_a = sm100_utils.make_smem_layout_a(\n invert_sub_tiled_mma_ss_l0,\n self.invert_mma_sub_l0_tiler,\n self.invert_type_ab,\n self.invert_sub_stage,\n )\n\n invert_sub_smem_layout_staged_ss_l0_b = sm100_utils.make_smem_layout_b(\n invert_sub_tiled_mma_ss_l0,\n self.invert_mma_sub_l0_tiler,\n self.invert_type_ab,\n self.invert_sub_stage,\n )\n\n invert_sub_smem_layout_staged_ts_l0_a = sm100_utils.make_smem_layout_a(\n invert_sub_tiled_mma_ts_l0,\n self.invert_mma_sub_l0_tiler,\n self.invert_type_ab,\n self.invert_sub_stage,\n )\n\n invert_sub_smem_layout_staged_ts_l0_b = sm100_utils.make_smem_layout_b(\n invert_sub_tiled_mma_ts_l0,\n self.invert_mma_sub_l0_tiler,\n self.invert_type_ab,\n self.invert_sub_stage,\n )\n\n invert_sub_smem_layout_staged_ss_l1_a = sm100_utils.make_smem_layout_a(\n invert_sub_tiled_mma_ss_l1,\n self.invert_mma_sub_l1_tiler,\n self.invert_type_ab,\n self.invert_sub_stage,\n )\n\n invert_sub_smem_layout_staged_ss_l1_b = sm100_utils.make_smem_layout_b(\n invert_sub_tiled_mma_ss_l1,\n self.invert_mma_sub_l1_tiler,\n self.invert_type_ab,\n self.invert_sub_stage,\n )\n\n invert_sub_smem_layout_staged_ts_l1_a = sm100_utils.make_smem_layout_a(\n invert_sub_tiled_mma_ts_l1,\n self.invert_mma_sub_l1_tiler,\n self.invert_type_ab,\n self.invert_sub_stage,\n )\n\n invert_sub_smem_layout_staged_ts_l1_b = sm100_utils.make_smem_layout_b(\n invert_sub_tiled_mma_ts_l1,\n self.invert_mma_sub_l1_tiler,\n self.invert_type_ab,\n self.invert_sub_stage,\n )\n\n # tuw\n tuw_smem_layout_staged_a = make_smem_layout_a_kind(\n tuw_tiled_mma,\n self.tuw_mma_tiler,\n self.q_dtype,\n self.one_stage,\n cute.nvgpu.tcgen05.SmemLayoutAtomKind.K_INTER,\n )\n\n tuw_smem_layout_staged_b = make_smem_layout_b_kind(\n tuw_tiled_mma,\n self.tuw_mma_tiler,\n self.q_dtype,\n self.one_stage,\n cute.nvgpu.tcgen05.SmemLayoutAtomKind.MN_INTER,\n )\n\n v_smem_layout_staged_b = make_smem_layout_b_kind(\n tuw_tiled_mma,\n self.tuw_mma_tiler,\n self.i_dtype,\n self.one_stage,\n cute.nvgpu.tcgen05.SmemLayoutAtomKind.MN_INTER,\n )\n\n # TMA\n tma_load_op = cute.nvgpu.cpasync.CopyBulkTensorTileG2SOp(cta_group)\n tma_store_op = cute.nvgpu.cpasync.CopyBulkTensorTileS2GOp()\n\n # TMA load for Q\n q_smem_layout = cute.select(q_smem_layout_staged, mode=[0, 1, 2])\n tma_atom_q, tma_tensor_q = cute.nvgpu.make_tiled_tma_atom_A(\n tma_load_op,\n q,\n q_smem_layout,\n self.qk_mma_tiler,\n qk_tiled_mma,\n self.cluster_layout_vmnk.shape,\n )\n\n # TMA load for K\n k_smem_layout = cute.select(k_smem_layout_staged, mode=[0, 1, 2])\n tma_atom_k, tma_tensor_k = cute.nvgpu.make_tiled_tma_atom_B(\n tma_load_op,\n k,\n k_smem_layout,\n self.qk_mma_tiler,\n qk_tiled_mma,\n self.cluster_layout_vmnk.shape,\n )\n\n # TMA load for V\n v_smem_layout = cute.select(v_smem_layout_staged_b, mode=[0, 1, 2])\n tma_atom_v, tma_tensor_v = cute.nvgpu.make_tiled_tma_atom_B(\n tma_load_op,\n v,\n v_smem_layout,\n self.tuw_mma_tiler,\n tuw_tiled_mma,\n self.cluster_layout_vmnk.shape,\n )\n\n fake_state_tiled_mma = sm100_utils.make_trivial_tiled_mma(\n self.state_dtype,\n self.q_major_mode,\n self.k_major_mode,\n self.state_dtype,\n cta_group,\n self.qk_mma_tiler[:2],\n )\n state_smem_layout_f32_staged = sm100_utils.make_smem_layout_b(\n fake_state_tiled_mma,\n self.qk_mma_tiler,\n self.state_dtype,\n self.one_stage,\n )\n state_smem_layout_f32 = cute.select(\n state_smem_layout_f32_staged, mode=[0, 1, 2]\n )\n tma_atom_state_f32, tma_tensor_state_f32 = (\n cute.nvgpu.make_tiled_tma_atom_B(\n tma_load_op,\n state_input_f32,\n state_smem_layout_f32,\n self.qk_mma_tiler,\n fake_state_tiled_mma,\n self.cluster_layout_vmnk.shape,\n )\n if cutlass.const_expr(state_input_f32 is not None)\n else (None, None)\n )\n\n state_smem_layout_output = cute.select(\n state_output_smem_layout_staged, mode=[0, 1]\n )\n tma_atom_state_output, tma_tensor_state_output = (\n cutlass.cute.nvgpu.cpasync.make_tiled_tma_atom(\n tma_store_op,\n state_output,\n state_smem_layout_output,\n cute.composition(\n cute.make_identity_layout(state_output.shape),\n self.state_output_tiler,\n ),\n )\n if cutlass.const_expr(state_output is not None)\n else (None, None)\n )\n\n o_cta_v_layout = cute.composition(\n cute.make_identity_layout(o.shape), self.o_output_tiler\n )\n o_smem_layout_output = cute.select(o_output_smem_layout_staged, mode=[0, 1])\n tma_atom_o_output, tma_tensor_o_output = (\n cutlass.cute.nvgpu.cpasync.make_tiled_tma_atom(\n tma_store_op,\n o,\n o_smem_layout_output,\n o_cta_v_layout,\n )\n )\n\n gate_smem_layout_staged = cute.make_layout(\n (self.chunk_size, 1, self.gate_stage)\n )\n gate_smem_layout = cute.select(gate_smem_layout_staged, mode=[0, 1])\n\n beta_smem_layout_staged = cute.make_layout(\n (self.chunk_size, 1, self.beta_stage)\n )\n beta_smem_layout = cute.select(beta_smem_layout_staged, mode=[0, 1])\n\n q_copy_size = cute.size_in_bytes(self.q_dtype, q_smem_layout)\n k_copy_size = cute.size_in_bytes(self.k_dtype, k_smem_layout)\n v_copy_size = cute.size_in_bytes(self.v_dtype, v_smem_layout)\n state_copy_size = cute.size_in_bytes(self.i_dtype, state_smem_layout_f32)\n state_f32_copy_size = cute.size_in_bytes(\n self.state_dtype, state_smem_layout_f32\n )\n gate_copy_size = cute.size_in_bytes(self.g_dtype, gate_smem_layout)\n beta_copy_size = cute.size_in_bytes(self.beta_dtype, beta_smem_layout)\n self.tma_copy_q_bytes = q_copy_size\n self.tma_copy_kv_bytes = k_copy_size\n self.tma_copy_v_bytes = v_copy_size\n self.tma_copy_state_bytes = state_copy_size\n self.tma_copy_state_f32_bytes = state_f32_copy_size\n self.tma_copy_gate_bytes = gate_copy_size\n self.tma_copy_beta_bytes = beta_copy_size\n\n # Shared memory storage\n @cute.struct\n class SharedStorage:\n load_qk_mbar_ptr: cute.struct.MemRange[Int64, self.qk_stage * 2]\n load_v_mbar_ptr: cute.struct.MemRange[Int64, self.one_stage * 2]\n load_state_mbar_ptr: cute.struct.MemRange[Int64, self.one_stage * 2]\n mma_cudacore_mbar_ptr0: cute.struct.MemRange[Int64, 2]\n mma_qk_mbar_ptr0: cute.struct.MemRange[Int64, self.mma_qk_stage * 2]\n\n w0_epi_mbar_ptr: cute.struct.MemRange[Int64, 2]\n epi_w0_mbar_ptr: cute.struct.MemRange[Int64, 2]\n gb_w0_mbar_ptr: cute.struct.MemRange[Int64, self.gate_stage * 2]\n\n tmem_dealloc_mbar_ptr: cute.struct.MemRange[Int64, 1]\n # Tmem holding buffer\n tmem_holding_buf: Int32\n\n sV: cute.struct.Align[\n cute.struct.MemRange[self.i_dtype, cute.cosize(v_smem_layout_staged_b)],\n self.buffer_align_bytes,\n ]\n\n sQK: cute.struct.Align[\n cute.struct.MemRange[self.q_dtype, cute.cosize(qk_smem_layout_staged)],\n self.buffer_align_bytes,\n ]\n\n sIvt: cute.struct.Align[\n cute.struct.MemRange[self.acc_dtype, cute.cosize(ivt_smem_layout)],\n self.buffer_align_bytes,\n ]\n\n sGate: cute.struct.Align[\n cute.struct.MemRange[\n self.g_beta_dtype, cute.cosize(gate_smem_layout_staged)\n ],\n self.buffer_align_bytes,\n ]\n sGateCumsum: cute.struct.Align[\n cute.struct.MemRange[\n self.g_beta_dtype,\n cute.cosize(cute.select(gate_smem_layout_staged, mode=[0, 1])),\n ],\n self.buffer_align_bytes,\n ]\n sBeta: cute.struct.Align[\n cute.struct.MemRange[\n self.g_beta_dtype, cute.cosize(beta_smem_layout_staged)\n ],\n self.buffer_align_bytes,\n ]\n sSubInner: cute.struct.Align[\n cute.struct.MemRange[\n self.invert_type_ab, cute.cosize(sub_inner_smem_layout_staged)\n ],\n self.buffer_align_bytes,\n ]\n\n sState: cute.struct.Align[\n cute.struct.MemRange[\n self.i_dtype, cute.cosize(state_smem_layout_staged)\n ],\n self.buffer_align_bytes,\n ]\n\n self.shared_storage = SharedStorage\n\n if cutlass.const_expr(stream is None):\n stream = cutlass.cuda.default_stream()\n\n # Launch kernel\n self.kernel(\n qk_tiled_mma,\n o_intra_tiled_mma,\n o_intra_tiled_ts_mma_new,\n qs_tiled_mma,\n update_s_tiled_mma,\n kkt_tiled_mma,\n kst_tiled_mma,\n fake_state_tiled_mma,\n invert_sub_tiled_mma_ss_l0,\n invert_sub_tiled_mma_ts_l0,\n invert_sub_tiled_mma_ss_l1,\n invert_sub_tiled_mma_ts_l1,\n tuw_tiled_mma,\n tma_atom_q,\n tma_tensor_q,\n tma_atom_k,\n tma_tensor_k,\n tma_atom_v,\n tma_tensor_v,\n tma_atom_state_f32,\n tma_tensor_state_f32,\n gate,\n beta,\n o,\n tma_atom_state_output,\n tma_tensor_state_output,\n tma_atom_o_output,\n tma_tensor_o_output,\n cum_seqlen_q,\n q_smem_layout_staged,\n k_smem_layout_staged,\n qk_smem_layout_staged,\n o_intra_smem_layout_staged_a,\n o_intra_smem_layout_staged_b,\n o_intra_smem_layout_staged_a_new,\n qs_smem_layout_staged_a,\n qs_smem_layout_staged_b,\n update_s_smem_layout_staged_a,\n update_s_smem_layout_staged_b,\n state_smem_layout_staged,\n state_smem_layout_f32_staged,\n state_output_smem_layout_staged,\n o_output_smem_layout_staged,\n gate_smem_layout_staged,\n beta_smem_layout_staged,\n ivt_smem_layout,\n sub_inner_smem_layout_staged,\n invert_sub_smem_layout_staged_ss_l0_a,\n invert_sub_smem_layout_staged_ss_l0_b,\n invert_sub_smem_layout_staged_ts_l0_a,\n invert_sub_smem_layout_staged_ts_l0_b,\n invert_sub_smem_layout_staged_ss_l1_a,\n invert_sub_smem_layout_staged_ss_l1_b,\n invert_sub_smem_layout_staged_ts_l1_a,\n invert_sub_smem_layout_staged_ts_l1_b,\n tuw_smem_layout_staged_a,\n tuw_smem_layout_staged_b,\n v_smem_layout_staged_b,\n scale,\n self.tile_sched_params,\n ).launch(\n grid=grid,\n block=[self.threads_per_cta, 1, 1],\n cluster=self.cluster_shape_mnk,\n stream=stream,\n min_blocks_per_mp=1,\n )\n\n @staticmethod\n def _compute_grid(\n o_shape: cute.Shape,\n cta_tiler: Tuple[int, int, int],\n is_persistent: bool,\n ) -> Tuple[GdnStaticTileSchedulerParams, Tuple[int, int, int]]:\n tile_sched_params = create_gdn_static_tile_scheduler_params(\n is_persistent,\n (\n cute.ceil_div(cute.size(o_shape[1]), cta_tiler[2]),\n cute.size(o_shape[2][0]),\n cute.size(o_shape[2][1]),\n ),\n )\n grid = GdnStaticTileScheduler.get_grid_shape(tile_sched_params)\n return tile_sched_params, grid\n\n\n# ============================================================================\n# FlashInfer API Layer\n# ============================================================================\n\n\n@functools.lru_cache(maxsize=128)\ndef _get_problem_size(q_shape, v_shape, cu_seqlens_tuple):\n \"\"\"Compute problem_size, cached by (q_shape, v_shape, cu_seqlens tuple).\n\n Args:\n q_shape: Tuple of (b, s_q, h_q, d).\n v_shape: Tuple of (b, s_v, h_v, d).\n cu_seqlens_tuple: Tuple of cumulative sequence lengths, or None.\n \"\"\"\n b, s_q, h_q, d = q_shape\n _, _, h_v, _ = v_shape\n max_s_q = s_q\n sum_s_q = s_q\n if cu_seqlens_tuple is not None:\n sum_s_q = cu_seqlens_tuple[-1]\n b = len(cu_seqlens_tuple) - 1\n max_s_q = max(cu_seqlens_tuple[i + 1] - cu_seqlens_tuple[i] for i in range(b))\n return (b, max_s_q, sum_s_q, h_q, h_v, d)\n return (b, max_s_q, sum_s_q, h_q, h_v, d)\n\n\n@functools.cache\ndef _get_compiled_gdn_prefill_kernel(\n problem_size,\n dtype: torch.dtype,\n is_varlen: bool,\n is_initial_state: bool,\n is_output_state: bool,\n scale: float,\n):\n \"\"\"Cache compiled kernel for given configuration.\"\"\"\n return {}\n\n\ndef chunk_gated_delta_rule(\n q: torch.Tensor,\n k: torch.Tensor,\n v: torch.Tensor,\n g: torch.Tensor,\n beta: torch.Tensor,\n scale: Optional[float] = None,\n initial_state: Optional[torch.Tensor] = None,\n output_final_state: bool = False,\n cu_seqlens: Optional[torch.Tensor] = None,\n use_qk_l2norm_in_kernel: bool = False,\n output: Optional[torch.Tensor] = None,\n output_state: Optional[torch.Tensor] = None,\n) -> Union[torch.Tensor, Tuple[torch.Tensor, torch.Tensor]]:\n \"\"\"Public API: compile (on first call) and run the GDN chunked linear attention kernel.\n\n Args:\n q, k: (B, T, H_qk, D) query and key tensors (f16/bf16).\n v: (B, T, H_v, D) value tensor (f16/bf16). H_v must be a multiple of H_qk.\n g: (1, total_seq_len, H_v) gate values (f32, log-space).\n beta: (1, total_seq_len, H_v) beta values (f32, sigmoid-space).\n scale: Scale factor for the attention scores. Defaults to 1/sqrt(D).\n initial_state: (B, H_v, D, D) recurrent state (f32), or None for zero init.\n output_final_state: If True, return the final state alongside output.\n cu_seqlens: Cumulative sequence lengths for variable-length batching.\n use_qk_l2norm_in_kernel: If True, use L2 norm of QK in the kernel.(Not supported yet)\n output: Pre-allocated output tensor, or None to allocate internally.\n output_state: Pre-allocated state output tensor, or None.\n\n Returns:\n output or (output, output_state) depending on output_final_state.\n \"\"\"\n\n # Allocate output if needed\n if output is None:\n output = torch.empty_like(v)\n\n # Check if supported\n if not GDN.can_implement(\n tuple(q.shape),\n tuple(v.shape),\n q.dtype,\n output.dtype,\n beta.dtype,\n use_qk_l2norm_in_kernel,\n ):\n raise ValueError(\"Unsupported input shape or dtype\")\n cu_seqlens_tuple = tuple(cu_seqlens.tolist()) if cu_seqlens is not None else None\n problem_size = _get_problem_size(tuple(q.shape), tuple(v.shape), cu_seqlens_tuple)\n\n # Allocate output_state if needed, current alloc both case.\n # TODO: Remove output_state when output_final_state is false.\n if output_state is None:\n output_state = torch.empty(\n (problem_size[0], problem_size[4], problem_size[5], problem_size[5]),\n dtype=torch.float32,\n device=q.device,\n )\n\n # Compile kernel with TVM FFI (cached)\n is_varlen = cu_seqlens is not None\n is_initial_state = initial_state is not None\n is_output_state = output_state is not None\n cache_key = (\n problem_size,\n q.dtype,\n is_varlen,\n is_initial_state,\n is_output_state,\n scale,\n )\n cache = _get_compiled_gdn_prefill_kernel(*cache_key)\n\n current_stream = cuda.CUstream(torch.cuda.current_stream().cuda_stream)\n\n if \"compiled_gdn\" not in cache:\n # GDN kernel\n gdn = GDN()\n q_tensor = from_dlpack(q, assumed_align=16, enable_tvm_ffi=True)\n k_tensor = from_dlpack(k, assumed_align=16, enable_tvm_ffi=True)\n v_tensor = from_dlpack(v, assumed_align=16, enable_tvm_ffi=True)\n o_tensor = from_dlpack(output, assumed_align=16, enable_tvm_ffi=True)\n gate_tensor = from_dlpack(g, assumed_align=16, enable_tvm_ffi=True)\n beta_tensor = from_dlpack(beta, assumed_align=16, enable_tvm_ffi=True)\n cu_seqlens_tensor = (\n from_dlpack(cu_seqlens, assumed_align=16, enable_tvm_ffi=True)\n if cu_seqlens is not None\n else None\n )\n state_tensor = (\n from_dlpack(initial_state, assumed_align=16, enable_tvm_ffi=True)\n if initial_state is not None\n else None\n )\n state_output_tensor = (\n from_dlpack(output_state, assumed_align=16, enable_tvm_ffi=True)\n if output_state is not None\n else None\n )\n\n # Compile GDN kernel\n options = EnableTVMFFI\n compiled_gdn = cute.compile[options](\n gdn,\n q_tensor.iterator,\n k_tensor.iterator,\n v_tensor.iterator,\n o_tensor.iterator,\n gate_tensor.iterator,\n beta_tensor.iterator,\n problem_size,\n state_tensor.iterator if state_tensor is not None else None,\n state_output_tensor.iterator if state_output_tensor is not None else None,\n scale,\n cu_seqlens_tensor,\n stream=current_stream,\n )\n cache[\"compiled_gdn\"] = compiled_gdn\n\n compiled_gdn = cache[\"compiled_gdn\"]\n\n # Run GDN kernel\n compiled_gdn(\n q.data_ptr(),\n k.data_ptr(),\n v.data_ptr(),\n output.data_ptr(),\n g.data_ptr(),\n beta.data_ptr(),\n problem_size,\n initial_state.data_ptr() if initial_state is not None else None,\n output_state.data_ptr() if output_state is not None else None,\n scale,\n cu_seqlens,\n stream=current_stream,\n )\n\n if output_final_state:\n return output, output_state\n else:\n return output\n" + }, + { + "path": "gdn_blackwell/gdn_helpers.py", + "content": "\"\"\"\nCopyright (c) 2026 by FlashInfer team.\n\nLicensed under the Apache License, Version 2.0 (the \"License\");\nyou may not use this file except in compliance with the License.\nYou may obtain a copy of the License at\n\n http://www.apache.org/licenses/LICENSE-2.0\n\nUnless required by applicable law or agreed to in writing, software\ndistributed under the License is distributed on an \"AS IS\" BASIS,\nWITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\nSee the License for the specific language governing permissions and\nlimitations under the License.\n\"\"\"\n\nfrom typing import Type, Union\n\nimport cutlass\nimport cutlass.cute as cute\n\n\ndef make_smem_layout_a_kind(\n tiled_mma: cute.TiledMma,\n mma_tiler_mnk: cute.Tile,\n a_dtype: Type[cutlass.Numeric],\n num_stages: int,\n kind: cute.nvgpu.tcgen05.SmemLayoutAtomKind,\n *,\n loc=None,\n ip=None,\n) -> Union[cute.Layout, cute.ComposedLayout]:\n \"\"\"This function helps with:\n 1. Get the partitioned shape of the A tensor based on the tiled_mma & MMA tiler.\n 2. Select the heuristic SMEM layout atom based on the A tensor's majorness, the data type, and the major mode size.\n 3. cute.Tile the SMEM layout atom to the MMA tile shape.\n 4. Stage the SMEM layout based on the number of stages.\n\n :param tiled_mma: The tiled MMA used to partition tensor A\n :type tiled_mma: cute.TiledMma\n :param mma_tiler_mnk: The MMA tile shape\n :type mma_tiler_mnk: cute.cute.Tile\n :param a_dtype: The element type for tensor A\n :type a_dtype: Type[Numeric]\n :param num_stages: The number of pipeline stages for tensor A\n :type num_stages: int\n :param kind: The kind of layout Atom\n :type kind: SmemLayoutAtomKind\n\n :return: SMEM layout for tensor A\n :rtype: Union[cute.Layout, cute.ComposedLayout]\n \"\"\"\n\n is_k_major = (\n tiled_mma.op.a_major_mode == cutlass.cute.nvgpu.tcgen05.OperandMajorMode.K\n )\n a_smem_shape = tiled_mma.partition_shape_A(\n cute.dice(mma_tiler_mnk, (1, None, 1), loc=loc, ip=ip)\n )\n a_smem_layout_atom = cute.nvgpu.tcgen05.make_smem_layout_atom(\n kind,\n a_dtype,\n loc=loc,\n ip=ip,\n )\n a_smem_layout_staged = cute.nvgpu.tcgen05.tile_to_mma_shape(\n a_smem_layout_atom,\n cute.append(a_smem_shape, num_stages, loc=loc, ip=ip),\n order=((1, 0, 2) if not is_k_major else (0, 1, 2)),\n loc=loc,\n ip=ip,\n )\n return a_smem_layout_staged\n\n\ndef make_smem_layout_b_kind(\n tiled_mma: cute.TiledMma,\n mma_tiler_mnk: cute.Tile,\n b_dtype: Type[cutlass.Numeric],\n num_stages: int,\n kind: cute.nvgpu.tcgen05.SmemLayoutAtomKind,\n *,\n loc=None,\n ip=None,\n) -> Union[cute.Layout, cute.ComposedLayout]:\n \"\"\"This function helps:\n 1. Get the partitioned shape of the B tensor based on the tiled_mma & MMA tiler.\n 2. Select the heuristic SMEM layout atom based on the B tensor's majorness, the data type, and the major mode size.\n 3. cute.Tile the SMEM layout atom to the MMA tile shape.\n 4. Stage the SMEM layout based on the number of stages.\n\n :param tiled_mma: The tiled MMA which is used to partition the B tensor.\n :type tiled_mma: cute.TiledMma\n :param mma_tiler_mnk: The MMA tile shape.\n :type mma_tiler_mnk: cute.cute.Tile\n :param b_dtype: The element type for the B tensor.\n :type b_dtype: Type[Numeric]\n :param num_stages: The stage of the B tensor.\n :type num_stages: int\n :param kind: The kind of layout Atom\n :type kind: SmemLayoutAtomKind\n\n :return: SMEM layout for the B tensor.\n :rtype: Union[cute.Layout, cute.ComposedLayout]\n \"\"\"\n\n is_k_major = (\n tiled_mma.op.b_major_mode == cutlass.cute.nvgpu.tcgen05.OperandMajorMode.K\n )\n b_smem_shape = tiled_mma.partition_shape_B(\n cute.dice(mma_tiler_mnk, (None, 1, 1), loc=loc, ip=ip)\n )\n b_smem_layout_atom = cute.nvgpu.tcgen05.make_smem_layout_atom(\n kind,\n b_dtype,\n loc=loc,\n ip=ip,\n )\n b_smem_layout_staged = cute.nvgpu.tcgen05.tile_to_mma_shape(\n b_smem_layout_atom,\n cute.append(b_smem_shape, num_stages, loc=loc, ip=ip),\n order=((1, 0, 2) if not is_k_major else (0, 1, 2)),\n loc=loc,\n ip=ip,\n )\n\n return b_smem_layout_staged\n\n\ndef make_smem_layout_epi_kind(\n epi_dtype: Type[cutlass.Numeric],\n epi_layout: cutlass.utils.LayoutEnum,\n epi_tile: cute.Tile,\n epi_stage: int,\n kind: cute.nvgpu.tcgen05.SmemLayoutAtomKind,\n *,\n loc=None,\n ip=None,\n) -> Union[cute.Layout, cute.ComposedLayout]:\n \"\"\"This function helps:\n 1. Select the heuristic SMEM layout atom based on the epilog tile shape,\n the epilog tensor's majorness, and the element type.\n 2. cute.Tile the SMEM layout atom to the epilog tile shape.\n 3. Stage the SMEM layout based on the number of stages.\n\n :param epi_dtype: The element type for the epilog tensor.\n :type epi_dtype: Type[Numeric]\n :param epi_layout: The layout enum for the epilog tensor.\n :type epi_layout: LayoutEnum\n :param epi_tile: The epilogue tile shape.\n :type epi_tile: cute.cute.Tile\n :param epi_stage: The stage of the epilog tensor.\n :type epi_stage: int\n\n :return: SMEM layout for epilog tensors (usually C & D which are processed in the epilog)\n :rtype: Union[cute.Layout, cute.ComposedLayout]\n \"\"\"\n\n epilog_shape = cute.product_each(\n cute.shape(epi_tile, loc=loc, ip=ip), loc=loc, ip=ip\n )\n\n c_smem_layout_atom = cute.nvgpu.tcgen05.make_smem_layout_atom(\n kind,\n epi_dtype,\n loc=loc,\n ip=ip,\n )\n epi_smem_layout_staged = cute.tile_to_shape(\n c_smem_layout_atom,\n cute.append(epilog_shape, epi_stage, loc=loc, ip=ip),\n order=((1, 0, 2) if not epi_layout.is_n_major_c() else (0, 1, 2)),\n loc=loc,\n ip=ip,\n )\n\n return epi_smem_layout_staged\n" + }, + { + "path": "gdn_blackwell/gdn_tile_scheduler.py", + "content": "import cutlass\nimport cutlass.cute as cute\nimport cutlass.utils as utils\n\nfrom cutlass.cute.typing import Int32, Int64, Boolean\n\n\nclass GdnStaticTileSchedulerParams:\n def __init__(\n self,\n is_persistent: bool,\n problem_shape_mbh: cute.Shape,\n *,\n loc=None,\n ip=None,\n ):\n self.is_persistent = is_persistent\n self.problem_shape_mbh = problem_shape_mbh\n self._loc = loc\n self._ip = ip\n\n def __extract_mlir_values__(self):\n values, self._values_pos = [], []\n for obj in [self.is_persistent, self.problem_shape_mbh]:\n obj_values = cutlass.extract_mlir_values(obj)\n values += obj_values\n self._values_pos.append(len(obj_values))\n return values\n\n def __new_from_mlir_values__(self, values):\n obj_list = []\n for obj, n_items in zip(\n [self.is_persistent, self.problem_shape_mbh], self._values_pos, strict=True\n ):\n obj_list.append(cutlass.new_from_mlir_values(obj, values[:n_items]))\n values = values[n_items:]\n return GdnStaticTileSchedulerParams(\n *(tuple(obj_list)), loc=self._loc, ip=self._ip\n )\n\n\ndef create_gdn_static_tile_scheduler_params(\n is_persistent: bool,\n problem_shape_mbh: cute.Shape,\n) -> GdnStaticTileSchedulerParams:\n return GdnStaticTileSchedulerParams(is_persistent, problem_shape_mbh)\n\n\nclass GdnStaticTileScheduler:\n def __init__(\n self,\n params: GdnStaticTileSchedulerParams,\n current_work_linear_idx: Int32,\n blk_coord: cute.Coord,\n grid_shape: cute.Shape,\n *,\n loc=None,\n ip=None,\n ):\n self._params = params\n self._blk_coord = blk_coord\n self._grid_shape = grid_shape\n self._is_persistent = params.is_persistent\n self._current_work_linear_idx = current_work_linear_idx\n self._problem_shape_mbh = cute.make_layout(\n params.problem_shape_mbh, loc=loc, ip=ip\n )\n self._num_blocks = cute.size(self._problem_shape_mbh, loc=loc, ip=ip)\n self._is_first_block = True\n self.num_persistent_sm = cute.size(grid_shape, loc=loc, ip=ip)\n self._loc = loc\n self._ip = ip\n\n # called by host\n @staticmethod\n def get_grid_shape(\n params: GdnStaticTileSchedulerParams,\n *,\n loc=None,\n ip=None,\n ) -> cute.Shape:\n if params.is_persistent:\n hardware_info = cutlass.utils.HardwareInfo()\n sm_count = hardware_info.get_device_multiprocessor_count()\n return (\n cutlass.min(\n sm_count, cute.size(params.problem_shape_mbh, loc=loc, ip=ip)\n ),\n 1,\n 1,\n )\n else:\n return params.problem_shape_mbh\n\n @staticmethod\n def check_valid_work_for_seqlen_q(\n q_tiler: int,\n current_idx: Int32,\n seqlen_q: Int32,\n ) -> Boolean:\n return current_idx * q_tiler < seqlen_q\n\n def get_current_work(self, *, loc=None, ip=None) -> utils.WorkTileInfo:\n is_valid = (\n self._current_work_linear_idx < self._num_blocks\n if self._is_persistent\n else self._is_first_block\n )\n\n blk_coord = (0, 0, 0)\n if self._is_persistent:\n blk_coord = self._problem_shape_mbh.get_hier_coord(\n self._current_work_linear_idx, loc=loc, ip=ip\n )\n else:\n blk_coord = self._blk_coord\n\n # cur_tile_coord is (mid, 0, (bid, hid))\n cur_tile_coord = (\n blk_coord[0],\n 0,\n (blk_coord[1], blk_coord[2]),\n )\n\n return utils.WorkTileInfo(cur_tile_coord, is_valid)\n\n def initial_work_tile_info(self, *, loc=None, ip=None):\n return self.get_current_work(loc=loc, ip=ip)\n\n def advance_to_next_work(self, *, advance_count=1, loc=None, ip=None):\n if self._is_persistent:\n self._current_work_linear_idx += advance_count * self.num_persistent_sm\n self._is_first_block = False\n\n def __extract_mlir_values__(self):\n values = cutlass.extract_mlir_values(self._params)\n values.extend(cutlass.extract_mlir_values(self._current_work_linear_idx))\n values.extend(cutlass.extract_mlir_values(self._blk_coord))\n values.extend(cutlass.extract_mlir_values(self._grid_shape))\n return values\n\n def __new_from_mlir_values__(self, values):\n assert len(values) == 10\n new_params = cutlass.new_from_mlir_values(self._params, values[0:3])\n new_current_work_linear_idx = cutlass.new_from_mlir_values(\n self._current_work_linear_idx, [values[3]]\n )\n new_blk_coord = cutlass.new_from_mlir_values(self._blk_coord, values[4:7])\n new_grid_shape = cutlass.new_from_mlir_values(self._grid_shape, values[7:])\n return GdnStaticTileScheduler(\n new_params, new_current_work_linear_idx, new_blk_coord, new_grid_shape\n )\n\n\ndef create_gdn_static_tile_scheduler(\n params: GdnStaticTileSchedulerParams,\n blk_coord: cute.Coord,\n grid_shape: cute.Shape,\n) -> GdnStaticTileScheduler:\n return GdnStaticTileScheduler(params, blk_coord[0], blk_coord, grid_shape)\n" + } + ], + "description": "Solution using FlashInfer SM100 CuTile chunk_gated_delta_rule for GDN prefill (qk4_v8_d128, k-last state layout) on NVIDIA B200 (Blackwell)." +} diff --git a/solutions/gdn/flashinfer_wrapper_9b7f1e.json b/solutions/gdn/flashinfer_wrapper_9b7f1e.json new file mode 100644 index 0000000000000000000000000000000000000000..67152cbf3297f59a1d7bdf0e57018ccfadd26f37 --- /dev/null +++ b/solutions/gdn/flashinfer_wrapper_9b7f1e.json @@ -0,0 +1,25 @@ +{ + "name": "flashinfer_wrapper_9b7f1e", + "definition": "gdn_decode_qk4_v8_d128_k_last", + "author": "flashinfer", + "spec": { + "language": "python", + "target_hardware": [ + "NVIDIA H20", + "NVIDIA H100", + "NVIDIA H200" + ], + "entry_point": "main.py::run", + "dependencies": [ + "flashinfer" + ], + "destination_passing_style": false + }, + "sources": [ + { + "path": "main.py", + "content": "import math\nimport torch\nfrom flashinfer.gdn_decode import gated_delta_rule_decode_pretranspose\n\n\ndef run(q, k, v, state, A_log, a, dt_bias, b, scale):\n if isinstance(scale, torch.Tensor):\n scale = float(scale.item())\n else:\n scale = float(scale)\n if scale == 0.0:\n scale = 1.0 / math.sqrt(q.shape[-1])\n\n B, T, num_v_heads, head_size = v.shape\n output = torch.empty(B, T, num_v_heads, head_size, dtype=q.dtype, device=q.device)\n\n out, new_state = gated_delta_rule_decode_pretranspose(\n q=q,\n k=k,\n v=v,\n state=state,\n A_log=A_log,\n a=a,\n dt_bias=dt_bias,\n b=b,\n scale=scale,\n output=output,\n use_qk_l2norm=False,\n )\n\n return out, new_state\n" + } + ], + "description": "Solution using FlashInfer gated_delta_rule_decode_pretranspose for GDN single-token decode (qk4_v8_d128, k-last state layout)." +} diff --git a/solutions/gdn/sglang_gdn_decode.json b/solutions/gdn/sglang_gdn_decode.json deleted file mode 100644 index 250129780801743406ba9661c1cf595669a0f168..0000000000000000000000000000000000000000 --- a/solutions/gdn/sglang_gdn_decode.json +++ /dev/null @@ -1,8 +0,0 @@ -{ - "name": "sglang_gdn_decode", - "definition": "gated_delta_rule_decode_h48_dk128_dv128", - "author": "inference-kernels", - "description": "Single-step adaptation of SGLang's fused Triton sigmoid-gating recurrent update. Uses the definition's K,V state layout directly and preserves its BF16 beta rounding. Upstream: https://github.com/sgl-project/sglang/blob/9d394dfbd755759d3add89cfd0bc86d59b31f78c/python/sglang/kernels/ops/attention/fla/fused_sigmoid_gating_recurrent.py (Apache-2.0).", - "spec": {"language": "triton", "target_hardware": ["NVIDIA_B200"], "entry_point": "main.py::run", "dependencies": ["torch>=2.11", "triton>=3.6"], "destination_passing_style": false}, - "sources": [{"path": "main.py", "content": "# SPDX-License-Identifier: Apache-2.0\n# Adapted from SGLang's fused sigmoid-gating recurrent delta-rule update.\n# Changes: single-step interface, K,V state layout, separate state output,\n# and explicit BF16 rounding of beta required by this definition.\nimport torch\nimport triton as tr\nimport triton.language as tl\n\n@tr.jit\ndef update(Q, K, V, A, B, Log, Bias, S0, O, S1, SCALE: tl.constexpr, BV: tl.constexpr):\n batch = tl.program_id(0)\n head = tl.program_id(1)\n block = tl.program_id(2)\n keys = tl.arange(0, 128)\n vals = block * BV + tl.arange(0, BV)\n qh = head // 3\n q = tl.load(Q + (batch * 16 + qh) * 128 + keys).to(tl.float32)\n k = tl.load(K + (batch * 16 + qh) * 128 + keys).to(tl.float32)\n q = q / tl.sqrt(tl.sum(q * q, 0) + 1e-6) * SCALE\n k = k / tl.sqrt(tl.sum(k * k, 0) + 1e-6)\n v = tl.load(V + (batch * 48 + head) * 128 + vals).to(tl.float32)\n x = tl.load(A + batch * 48 + head).to(tl.float32) + tl.load(Bias + head).to(tl.float32)\n softplus = tl.where(x <= 20.0, tl.log(1.0 + tl.exp(x)), x)\n decay = tl.exp(-tl.exp(tl.load(Log + head)) * softplus)\n b = tl.load(B + batch * 48 + head).to(tl.float32)\n beta = (1.0 / (1.0 + tl.exp(-b))).to(B.dtype.element_ty).to(tl.float32)\n offsets = (batch * 48 + head) * 16384 + keys[:, None] * 128 + vals[None, :]\n state = tl.load(S0 + offsets) * decay\n delta = (v - tl.sum(state * k[:, None], 0)) * beta\n state = state + k[:, None] * delta[None, :]\n out = tl.sum(state * q[:, None], 0)\n tl.store(S1 + offsets, state)\n tl.store(O + (batch * 48 + head) * 128 + vals, out)\n\ndef run(Q, K, V, a, b, A_log, dt_bias, S0, q_scale):\n O = torch.empty_like(V)\n S_final = torch.empty_like(S0)\n update[(Q.shape[0], 48, 4)](Q, K, V, a, b, A_log, dt_bias, S0, O, S_final, q_scale, 32, num_warps=4, enable_fp_fusion=False)\n return O, S_final\n"}] -} diff --git a/solutions/gemm/deepgemm_bf16_n4096_k64.json b/solutions/gemm/deepgemm_bf16_n4096_k64.json deleted file mode 100644 index 0726a3a85758f660f3aa429889f25f798914ea12..0000000000000000000000000000000000000000 --- a/solutions/gemm/deepgemm_bf16_n4096_k64.json +++ /dev/null @@ -1,8 +0,0 @@ -{ - "name": "deepgemm_bf16_n4096_k64", - "definition": "dense_gemm_bf16_nt_n4096_k64", - "author": "inference-kernels", - "description": "DeepGEMM Blackwell BF16 GEMM with FP32 accumulation. Selected by local B200 comparison against FlashInfer CUTLASS and cuTile. Upstream: https://github.com/deepseek-ai/DeepGEMM/tree/1fc9c66975ee322d628b3288534ca0e9ce12a64d (MIT).", - "spec": {"language": "python", "target_hardware": ["NVIDIA_B200"], "entry_point": "main.py::run", "dependencies": ["torch>=2.11", "deep-gemm @ git+https://github.com/deepseek-ai/DeepGEMM.git@1fc9c66975ee322d628b3288534ca0e9ce12a64d"], "destination_passing_style": false}, - "sources": [{"path": "main.py", "content": "import torch\nimport deep_gemm\n\ndef run(A, W):\n output = torch.empty((A.shape[0], W.shape[0]), dtype=torch.bfloat16, device=A.device)\n deep_gemm.bf16_gemm_nt(A, W, output)\n return output\n"}] -} diff --git a/solutions/gemm/deepgemm_bf16_n64_k4096.json b/solutions/gemm/deepgemm_bf16_n64_k4096.json deleted file mode 100644 index 8a49e9cab2e0e275c606d072bad4f4405c5f36f1..0000000000000000000000000000000000000000 --- a/solutions/gemm/deepgemm_bf16_n64_k4096.json +++ /dev/null @@ -1,8 +0,0 @@ -{ - "name": "deepgemm_bf16_n64_k4096", - "definition": "dense_gemm_bf16_nt_n64_k4096", - "author": "inference-kernels", - "description": "DeepGEMM Blackwell BF16 GEMM with FP32 accumulation. Selected by local B200 comparison against FlashInfer CUTLASS and cuTile. Upstream: https://github.com/deepseek-ai/DeepGEMM/tree/1fc9c66975ee322d628b3288534ca0e9ce12a64d (MIT).", - "spec": {"language": "python", "target_hardware": ["NVIDIA_B200"], "entry_point": "main.py::run", "dependencies": ["torch>=2.11", "deep-gemm @ git+https://github.com/deepseek-ai/DeepGEMM.git@1fc9c66975ee322d628b3288534ca0e9ce12a64d"], "destination_passing_style": false}, - "sources": [{"path": "main.py", "content": "import torch\nimport deep_gemm\n\ndef run(A, W):\n output = torch.empty((A.shape[0], W.shape[0]), dtype=torch.bfloat16, device=A.device)\n deep_gemm.bf16_gemm_nt(A, W, output)\n return output\n"}] -} diff --git a/solutions/gemm/sglang_dense_gemm_bf16_nt_n12288_k4096.json b/solutions/gemm/sglang_dense_gemm_bf16_nt_n12288_k4096.json new file mode 100644 index 0000000000000000000000000000000000000000..134fc9835c310d98025af4e8114786fec1bd1cdf --- /dev/null +++ b/solutions/gemm/sglang_dense_gemm_bf16_nt_n12288_k4096.json @@ -0,0 +1,23 @@ +{ + "name": "sglang_dense_gemm_bf16_nt_n12288_k4096", + "definition": "dense_gemm_bf16_nt_n12288_k4096", + "author": "kda", + "description": "SGLang's own implementation at the capture commit 684fea8a, called the way the engine calls it (see the module docstring). Run it in lmsysorg/sglang@sha256:ddae0e399d3d94f7827f16183301cf8dac4cf0eae0ef25590b7dac5881d713d8. KDA (Kernel Design Agents) times it live as the baseline: prepare(*inputs) does the host-side setup and returns a zero-argument launch, and only launch is timed; run(*inputs) does both.", + "spec": { + "language": "python", + "target_hardware": [ + "NVIDIA_B300" + ], + "entry_point": "main.py::run", + "dependencies": [ + "sglang @ git+https://github.com/sgl-project/sglang.git@684fea8af3b11a5b51ec9966c02959a32ad3421c#subdirectory=python" + ], + "destination_passing_style": false + }, + "sources": [ + { + "path": "main.py", + "content": "# Copyright 2026 Co-developed by KDA (Kernel Design Agents)\n\"\"\"SGLang baseline for dense_gemm_bf16_nt_n12288_k4096: C = A @ W.T in BF16.\n\nSGLang diffusion runtime at commit 684fea8a, paths under\npython/sglang/multimodal_gen/runtime/: the Qwen-Image-2.1 ``img_mlp.gate_layer``\nColumnParallelLinear (models/dits/qwen_image21.py:331, called at :347) ->\nColumnParallelLinear.forward (layers/linear.py:518) ->\nUnquantizedLinearMethod.apply (:203) -> apply_unquantized_linear(x, weight,\nNone) (:155) -> F.linear(x, weight, None) (:169). The batch-1 packed Q/K/V\nprojection, torch.mm(x.view(seq, C), packed.t(), out=buffer[0, prefix:])\n(models/dits/qwen_image21.py:579), gives the same bytes.\n\nAdapter: none. A is SGLang's x as [M, K] rows (the engine's [1, M, K]\nactivation gives the same bytes), W is layer.weight, bias is None. The\nworker's numerics policy (utils/numerics_policy.py:33, applied at\nmanagers/gpu_worker.py:420 with the server_args.py:510-511 defaults) keeps\nPyTorch's defaults, so nothing is set here.\n\"\"\"\n\nfrom sglang.multimodal_gen.runtime.layers.linear import apply_unquantized_linear\n\n\ndef run(A, W):\n return apply_unquantized_linear(A, W, None)\n" + } + ] +} diff --git a/solutions/gemm/sglang_dense_gemm_bf16_nt_n4096_k12288.json b/solutions/gemm/sglang_dense_gemm_bf16_nt_n4096_k12288.json new file mode 100644 index 0000000000000000000000000000000000000000..aa60eef32f6c5cbb260fa670bb699202d9f71be6 --- /dev/null +++ b/solutions/gemm/sglang_dense_gemm_bf16_nt_n4096_k12288.json @@ -0,0 +1,23 @@ +{ + "name": "sglang_dense_gemm_bf16_nt_n4096_k12288", + "definition": "dense_gemm_bf16_nt_n4096_k12288", + "author": "kda", + "description": "SGLang's own implementation at the capture commit 684fea8a, called the way the engine calls it (see the module docstring). Run it in lmsysorg/sglang@sha256:ddae0e399d3d94f7827f16183301cf8dac4cf0eae0ef25590b7dac5881d713d8. KDA (Kernel Design Agents) times it live as the baseline: prepare(*inputs) does the host-side setup and returns a zero-argument launch, and only launch is timed; run(*inputs) does both.", + "spec": { + "language": "python", + "target_hardware": [ + "NVIDIA_B300" + ], + "entry_point": "main.py::run", + "dependencies": [ + "sglang @ git+https://github.com/sgl-project/sglang.git@684fea8af3b11a5b51ec9966c02959a32ad3421c#subdirectory=python" + ], + "destination_passing_style": false + }, + "sources": [ + { + "path": "main.py", + "content": "# Copyright 2026 Co-developed by KDA (Kernel Design Agents)\n\"\"\"SGLang baseline for dense_gemm_bf16_nt_n4096_k12288: C = A @ W.T in BF16.\n\nSGLang diffusion runtime at commit 684fea8a, paths under\npython/sglang/multimodal_gen/runtime/: the Qwen-Image-2.1 ``img_mlp.out``\nRowParallelLinear (models/dits/qwen_image21.py:338, called at :356/:360) ->\nRowParallelLinear.forward (layers/linear.py:1185) ->\nUnquantizedLinearMethod.apply (:203) -> apply_unquantized_linear(x, weight,\nNone) (:155) -> F.linear(x, weight, None) (:169).\n\nAdapter: none. A is SGLang's x as [M, K] rows (the engine's [1, M, K]\nactivation gives the same bytes), W is layer.weight, bias is None. The\nworker's numerics policy (utils/numerics_policy.py:33, applied at\nmanagers/gpu_worker.py:420 with the server_args.py:510-511 defaults) keeps\nPyTorch's defaults, so nothing is set here.\n\"\"\"\n\nfrom sglang.multimodal_gen.runtime.layers.linear import apply_unquantized_linear\n\n\ndef run(A, W):\n return apply_unquantized_linear(A, W, None)\n" + } + ] +} diff --git a/solutions/gemm/sglang_dense_gemm_bf16_nt_n4096_k4096.json b/solutions/gemm/sglang_dense_gemm_bf16_nt_n4096_k4096.json new file mode 100644 index 0000000000000000000000000000000000000000..61da369d12664e7f6822781e3ca3beeb57da8656 --- /dev/null +++ b/solutions/gemm/sglang_dense_gemm_bf16_nt_n4096_k4096.json @@ -0,0 +1,23 @@ +{ + "name": "sglang_dense_gemm_bf16_nt_n4096_k4096", + "definition": "dense_gemm_bf16_nt_n4096_k4096", + "author": "kda", + "description": "SGLang's own implementation at the capture commit 684fea8a, called the way the engine calls it (see the module docstring). Run it in lmsysorg/sglang@sha256:ddae0e399d3d94f7827f16183301cf8dac4cf0eae0ef25590b7dac5881d713d8. KDA (Kernel Design Agents) times it live as the baseline: prepare(*inputs) does the host-side setup and returns a zero-argument launch, and only launch is timed; run(*inputs) does both.", + "spec": { + "language": "python", + "target_hardware": [ + "NVIDIA_B300" + ], + "entry_point": "main.py::run", + "dependencies": [ + "sglang @ git+https://github.com/sgl-project/sglang.git@684fea8af3b11a5b51ec9966c02959a32ad3421c#subdirectory=python" + ], + "destination_passing_style": false + }, + "sources": [ + { + "path": "main.py", + "content": "# Copyright 2026 Co-developed by KDA (Kernel Design Agents)\n\"\"\"SGLang baseline for dense_gemm_bf16_nt_n4096_k4096: C = A @ W.T in BF16.\n\nSGLang diffusion runtime at commit 684fea8a, paths under\npython/sglang/multimodal_gen/runtime/: the Qwen-Image-2.1 ``attn.to_q``\nColumnParallelLinear (models/dits/qwen_image21.py:369, called at :487/:723)\nand ``attn.to_out.0`` RowParallelLinear (:380, called at :741) ->\nlayers/linear.py:518/:1185 -> UnquantizedLinearMethod.apply (:203) ->\napply_unquantized_linear(x, weight, None) (:155) -> F.linear(x, weight, None)\n(:169). The nn.Linear layers ``txt_in.in_layer`` (models/dits/qwen_image21.py:294)\nand ``timestep_embedder.linear_2`` (:308) issue the same F.linear call.\n\nAdapter: none. A is SGLang's x as [M, K] rows (the engine's batched\nactivation gives the same bytes), W is layer.weight, bias is None. The\nworker's numerics policy (utils/numerics_policy.py:33, applied at\nmanagers/gpu_worker.py:420 with the server_args.py:510-511 defaults) keeps\nPyTorch's defaults, so nothing is set here.\n\"\"\"\n\nfrom sglang.multimodal_gen.runtime.layers.linear import apply_unquantized_linear\n\n\ndef run(A, W):\n return apply_unquantized_linear(A, W, None)\n" + } + ] +} diff --git a/solutions/grouped_gemm/deepgemm_n2304_k5120.json b/solutions/grouped_gemm/deepgemm_n2304_k5120.json deleted file mode 100644 index 94a5b8c9d07d92e49e4cd36fd760151b96e3a360..0000000000000000000000000000000000000000 --- a/solutions/grouped_gemm/deepgemm_n2304_k5120.json +++ /dev/null @@ -1,8 +0,0 @@ -{ - "name": "deepgemm_n2304_k5120", - "definition": "grouped_gemm_fp8_fp4_e384_n2304_k5120_g32", - "author": "inference-kernels", - "description": "DeepGEMM MXFP8 x MXFP4 grouped GEMM. Aligns expert segments, packs scales without requantization, and restores original row order. Upstream: https://github.com/deepseek-ai/DeepGEMM/tree/1fc9c66975ee322d628b3288534ca0e9ce12a64d (MIT).", - "spec": {"language": "python", "target_hardware": ["NVIDIA_B200"], "entry_point": "main.py::run", "dependencies": ["torch>=2.11", "deep-gemm @ git+https://github.com/deepseek-ai/DeepGEMM.git@1fc9c66975ee322d628b3288534ca0e9ce12a64d"], "destination_passing_style": false}, - "sources": [{"path": "main.py", "content": "import torch\nimport deep_gemm\n\ndef run(Aq, Wq_packed, scale_A, scale_W, expert_id):\n m, k = Aq.shape\n experts, n, _ = Wq_packed.shape\n alignment = deep_gemm.get_mk_alignment_for_contiguous_layout()\n capacity = ((m + min(m, experts) * (alignment - 1) + alignment - 1) // alignment) * alignment\n boundaries = torch.searchsorted(expert_id, torch.arange(experts + 1, device=Aq.device, dtype=torch.int32))\n counts = boundaries[1:] - boundaries[:-1]\n padded_counts = ((counts + alignment - 1) // alignment) * alignment\n offsets = padded_counts.cumsum(0) - padded_counts\n ids = expert_id.long()\n row_map = offsets[ids] + torch.arange(m, device=Aq.device) - boundaries[ids]\n a = torch.zeros((capacity, k), device=Aq.device, dtype=Aq.dtype)\n a.view(torch.uint8).index_copy_(0, row_map, Aq.view(torch.uint8))\n sa = torch.full((capacity, k // 32), 127, device=Aq.device, dtype=torch.int8)\n sa.index_copy_(0, row_map, scale_A)\n sa = sa.view(torch.int32).t().contiguous().t()\n sw = scale_W.view(torch.int32).transpose(-1, -2).contiguous().transpose(-1, -2)\n layout = torch.full((capacity,), -1, device=Aq.device, dtype=torch.int32)\n layout.index_copy_(0, row_map, expert_id)\n output = torch.empty((capacity, n), device=Aq.device, dtype=torch.bfloat16)\n deep_gemm.m_grouped_fp8_fp4_gemm_nt_contiguous(\n (a, sa), (Wq_packed, sw), output, layout,\n recipe_a=(1, 32), recipe_b=(1, 32),\n )\n return output.index_select(0, row_map)\n"}] -} diff --git a/solutions/grouped_gemm/sglang_grouped_gemm_fp8_fp4_e384_n4608_k5120_g32.json b/solutions/grouped_gemm/sglang_grouped_gemm_fp8_fp4_e384_n4608_k5120_g32.json new file mode 100644 index 0000000000000000000000000000000000000000..26d19dcba5ea19d281192af1fbdcb457585983eb --- /dev/null +++ b/solutions/grouped_gemm/sglang_grouped_gemm_fp8_fp4_e384_n4608_k5120_g32.json @@ -0,0 +1,23 @@ +{ + "name": "sglang_grouped_gemm_fp8_fp4_e384_n4608_k5120_g32", + "definition": "grouped_gemm_fp8_fp4_e384_n4608_k5120_g32", + "author": "kda", + "description": "SGLang's own implementation at the capture commit 684fea8a, called the way the engine calls it (see the module docstring). Run it in lmsysorg/sglang@sha256:ddae0e399d3d94f7827f16183301cf8dac4cf0eae0ef25590b7dac5881d713d8. KDA (Kernel Design Agents) times it live as the baseline: prepare(*inputs) does the host-side setup and returns a zero-argument launch, and only launch is timed; run(*inputs) does both.", + "spec": { + "language": "python", + "target_hardware": [ + "NVIDIA_B300" + ], + "entry_point": "main.py::run", + "dependencies": [ + "sglang @ git+https://github.com/sgl-project/sglang.git@684fea8af3b11a5b51ec9966c02959a32ad3421c#subdirectory=python" + ], + "destination_passing_style": false + }, + "sources": [ + { + "path": "main.py", + "content": "# Copyright 2026 Co-developed by KDA (Kernel Design Agents)\n\"\"\"SGLang's DeepGEMM MoE expert GEMM, fused gate/up projection (N=4608, K=5120).\n\nSGLang 684fea8a (paths under ``python/sglang/``), captured with ``--tp-size 4\n--ep-size 4 --moe-runner-backend deep_gemm --moe-a2a-backend none``: each of\nthe 4 EP ranks holds 96 of the 384 experts and runs, for its rows,\n\n- once at load: ``Fp8MoEMethod.process_weights_after_loading_block_quant``\n packs the fp32 group-32 weight scales with\n ``deep_gemm.transform_sf_into_required_layout(recipe=(1, 32),\n num_groups=96)`` (srt/layers/quantization/fp8.py:2132-2147);\n- per batch: ``pre_permute_standard_to_deep_gemm``\n (srt/layers/moe/moe_runner/deep_gemm.py:988) sizes the compact contiguous\n layout (``get_contiguous_layout_alignment`` :1082, ``_get_compact_all_tokens``\n :1085, ``pad_expert_counts`` :1093) and ``ep_scatter`` (:1166) writes the FP8\n rows, the MN-major packed UE8M0 scales (:1149) and ``m_indices`` (-1 on\n padding rows); ``DeepGemmRunnerCore.run`` enters\n ``contiguous_layout_alignment_scope(block_e)`` (:378) and\n ``_run_contiguous_gemm`` (:456) calls\n ``deep_gemm_wrapper.grouped_gemm_nt_f8f8bf16_contig``\n (srt/layers/deep_gemm_wrapper/entrypoint.py:132), i.e.\n ``deep_gemm.m_grouped_fp8_gemm_nt_contiguous`` (:157), with recipe_a =\n recipe_b = (1, 32): the capture's engine_adapter passes the actual\n activation group instead of the FP4-expert default (1, 128) (:337).\n\nInterface adapter: the definition's rows are already sorted by expert, so\n``prepare`` derives the layout from ``expert_id`` (each rank's padded\nsegments, row destinations, ``m_indices``), allocates the per-rank buffers,\nand does the load-time weight work; ``launch`` scatters the current FP8 rows\nand scale bytes (four UE8M0 bytes per int32) into the padded layout, runs the\nfour rank GEMMs and gathers the valid rows.\n\"\"\"\n\nimport deep_gemm\nimport torch\nfrom sglang.kernels.ops.moe.triton_pad_expert_counts import pad_expert_counts\nfrom sglang.srt.layers.deep_gemm_wrapper.entrypoint import (\n contiguous_layout_alignment_scope,\n get_contiguous_layout_alignment,\n)\nfrom sglang.srt.layers.moe.moe_runner.deep_gemm import _get_compact_all_tokens\n\nEP_SIZE = 4 # capture --ep-size\nRECIPE = (1, 32) # capture engine_adapter: actual activation group\n\n\n@torch.no_grad()\ndef prepare(Aq, Wq_packed, scale_A, scale_W, expert_id):\n m, k = Aq.shape\n num_experts, n, _ = Wq_packed.shape\n local = num_experts // EP_SIZE\n weights = [\n (\n Wq_packed[e0 : e0 + local],\n deep_gemm.transform_sf_into_required_layout(\n torch.exp2(scale_W[e0 : e0 + local].view(torch.uint8).float() - 127),\n mn=n,\n k=k,\n recipe=RECIPE,\n num_groups=local,\n disable_ue8m0_cast=False,\n ),\n )\n for e0 in range(0, num_experts, local)\n ]\n\n block_e = get_contiguous_layout_alignment(m, local)\n all_tokens = _get_compact_all_tokens(m, local, block_e)\n eid = expert_id.long()\n counts = torch.bincount(eid, minlength=num_experts)\n padded = torch.stack(\n [pad_expert_counts(c, block_e, all_tokens) for c in counts.view(-1, local)]\n ).flatten()\n rank, local_eid = eid // local, eid % local\n dst = (\n (torch.cumsum(padded, 0) - padded)[eid]\n + torch.arange(m, device=eid.device)\n - (torch.cumsum(counts, 0) - counts)[eid]\n )\n m_indices = torch.full(\n (EP_SIZE * all_tokens,), -1, dtype=torch.int32, device=Aq.device\n )\n m_indices[dst] = local_eid.int()\n a = torch.zeros(EP_SIZE * all_tokens, k, dtype=Aq.dtype, device=Aq.device)\n sfa = torch.zeros(\n EP_SIZE, k // 128, all_tokens, dtype=torch.int32, device=Aq.device\n )\n out = torch.empty(EP_SIZE * all_tokens, n, dtype=torch.bfloat16, device=Aq.device)\n y = torch.empty(m, n, dtype=torch.bfloat16, device=Aq.device)\n rows = [slice(r * all_tokens, (r + 1) * all_tokens) for r in range(EP_SIZE)]\n local_dst = dst - rank * all_tokens\n\n def launch():\n a.view(torch.uint8).index_copy_(0, dst, Aq.view(torch.uint8))\n sfa.transpose(1, 2)[rank, local_dst] = scale_A.view(torch.int32)\n with contiguous_layout_alignment_scope(block_e):\n for r, (w, sfw) in enumerate(weights):\n deep_gemm.m_grouped_fp8_gemm_nt_contiguous(\n (a[rows[r]], sfa[r].T),\n (w, sfw),\n out[rows[r]],\n m_indices[rows[r]],\n recipe_a=RECIPE,\n recipe_b=RECIPE,\n )\n torch.index_select(out, 0, dst, out=y)\n return y\n\n return launch\n\n\ndef run(Aq, Wq_packed, scale_A, scale_W, expert_id):\n return prepare(Aq, Wq_packed, scale_A, scale_W, expert_id)()\n" + } + ] +} diff --git a/solutions/grouped_gemm/sglang_grouped_gemm_fp8_fp4_e384_n5120_k2304_g32.json b/solutions/grouped_gemm/sglang_grouped_gemm_fp8_fp4_e384_n5120_k2304_g32.json new file mode 100644 index 0000000000000000000000000000000000000000..0f6fb100247e564c27ca0d4da3d1eac67df5eb1f --- /dev/null +++ b/solutions/grouped_gemm/sglang_grouped_gemm_fp8_fp4_e384_n5120_k2304_g32.json @@ -0,0 +1,23 @@ +{ + "name": "sglang_grouped_gemm_fp8_fp4_e384_n5120_k2304_g32", + "definition": "grouped_gemm_fp8_fp4_e384_n5120_k2304_g32", + "author": "kda", + "description": "SGLang's own implementation at the capture commit 684fea8a, called the way the engine calls it (see the module docstring). Run it in lmsysorg/sglang@sha256:ddae0e399d3d94f7827f16183301cf8dac4cf0eae0ef25590b7dac5881d713d8. KDA (Kernel Design Agents) times it live as the baseline: prepare(*inputs) does the host-side setup and returns a zero-argument launch, and only launch is timed; run(*inputs) does both.", + "spec": { + "language": "python", + "target_hardware": [ + "NVIDIA_B300" + ], + "entry_point": "main.py::run", + "dependencies": [ + "sglang @ git+https://github.com/sgl-project/sglang.git@684fea8af3b11a5b51ec9966c02959a32ad3421c#subdirectory=python" + ], + "destination_passing_style": false + }, + "sources": [ + { + "path": "main.py", + "content": "# Copyright 2026 Co-developed by KDA (Kernel Design Agents)\n\"\"\"SGLang's DeepGEMM MoE expert GEMM, down projection (N=5120, K=2304).\n\nSGLang 684fea8a (paths under ``python/sglang/``), captured with ``--tp-size 4\n--ep-size 4 --moe-runner-backend deep_gemm --moe-a2a-backend none``: each of\nthe 4 EP ranks holds 96 of the 384 experts and runs, for its rows,\n\n- once at load: ``Fp8MoEMethod.process_weights_after_loading_block_quant``\n packs the fp32 group-32 weight scales with\n ``deep_gemm.transform_sf_into_required_layout(recipe=(1, 32),\n num_groups=96)`` (srt/layers/quantization/fp8.py:2132-2147);\n- per batch: ``pre_permute_standard_to_deep_gemm``\n (srt/layers/moe/moe_runner/deep_gemm.py:988) sizes the compact contiguous\n layout (``get_contiguous_layout_alignment`` :1082, ``_get_compact_all_tokens``\n :1085, ``pad_expert_counts`` :1093) and ``ep_scatter`` (:1166) writes\n ``m_indices`` (-1 on padding rows); ``DeepGemmRunnerCore.run`` enters\n ``contiguous_layout_alignment_scope(block_e)`` (:378) and\n ``_run_contiguous_gemm`` quantizes the gate/up activation into the same\n padded rows (FP8 rows, MN-major packed UE8M0 scales) and, for the down\n projection, calls (:631) ``deep_gemm_wrapper.grouped_gemm_nt_f8f8bf16_contig``\n (srt/layers/deep_gemm_wrapper/entrypoint.py:132), i.e.\n ``deep_gemm.m_grouped_fp8_gemm_nt_contiguous`` (:157), with recipe_a =\n recipe_b = (1, 32): the capture's engine_adapter passes the actual\n activation group instead of the FP4-expert default (1, 128) (:337).\n\nInterface adapter: the definition's rows are already sorted by expert, so\n``prepare`` derives the layout from ``expert_id`` (each rank's padded\nsegments, row destinations, ``m_indices``), allocates the per-rank buffers,\nand does the load-time weight work; ``launch`` scatters the current FP8 rows\nand scale bytes (four UE8M0 bytes per int32) into the padded layout, runs the\nfour rank GEMMs and gathers the valid rows.\n\"\"\"\n\nimport deep_gemm\nimport torch\nfrom sglang.kernels.ops.moe.triton_pad_expert_counts import pad_expert_counts\nfrom sglang.srt.layers.deep_gemm_wrapper.entrypoint import (\n contiguous_layout_alignment_scope,\n get_contiguous_layout_alignment,\n)\nfrom sglang.srt.layers.moe.moe_runner.deep_gemm import _get_compact_all_tokens\n\nEP_SIZE = 4 # capture --ep-size\nRECIPE = (1, 32) # capture engine_adapter: actual activation group\n\n\n@torch.no_grad()\ndef prepare(Aq, Wq_packed, scale_A, scale_W, expert_id):\n m, k = Aq.shape\n num_experts, n, _ = Wq_packed.shape\n local = num_experts // EP_SIZE\n weights = [\n (\n Wq_packed[e0 : e0 + local],\n deep_gemm.transform_sf_into_required_layout(\n torch.exp2(scale_W[e0 : e0 + local].view(torch.uint8).float() - 127),\n mn=n,\n k=k,\n recipe=RECIPE,\n num_groups=local,\n disable_ue8m0_cast=False,\n ),\n )\n for e0 in range(0, num_experts, local)\n ]\n\n block_e = get_contiguous_layout_alignment(m, local)\n all_tokens = _get_compact_all_tokens(m, local, block_e)\n eid = expert_id.long()\n counts = torch.bincount(eid, minlength=num_experts)\n padded = torch.stack(\n [pad_expert_counts(c, block_e, all_tokens) for c in counts.view(-1, local)]\n ).flatten()\n rank, local_eid = eid // local, eid % local\n dst = (\n (torch.cumsum(padded, 0) - padded)[eid]\n + torch.arange(m, device=eid.device)\n - (torch.cumsum(counts, 0) - counts)[eid]\n )\n m_indices = torch.full(\n (EP_SIZE * all_tokens,), -1, dtype=torch.int32, device=Aq.device\n )\n m_indices[dst] = local_eid.int()\n a = torch.zeros(EP_SIZE * all_tokens, k, dtype=Aq.dtype, device=Aq.device)\n sfa = torch.zeros(\n EP_SIZE, k // 128, all_tokens, dtype=torch.int32, device=Aq.device\n )\n out = torch.empty(EP_SIZE * all_tokens, n, dtype=torch.bfloat16, device=Aq.device)\n y = torch.empty(m, n, dtype=torch.bfloat16, device=Aq.device)\n rows = [slice(r * all_tokens, (r + 1) * all_tokens) for r in range(EP_SIZE)]\n local_dst = dst - rank * all_tokens\n\n def launch():\n a.view(torch.uint8).index_copy_(0, dst, Aq.view(torch.uint8))\n sfa.transpose(1, 2)[rank, local_dst] = scale_A.view(torch.int32)\n with contiguous_layout_alignment_scope(block_e):\n for r, (w, sfw) in enumerate(weights):\n deep_gemm.m_grouped_fp8_gemm_nt_contiguous(\n (a[rows[r]], sfa[r].T),\n (w, sfw),\n out[rows[r]],\n m_indices[rows[r]],\n recipe_a=RECIPE,\n recipe_b=RECIPE,\n )\n torch.index_select(out, 0, dst, out=y)\n return y\n\n return launch\n\n\ndef run(Aq, Wq_packed, scale_A, scale_W, expert_id):\n return prepare(Aq, Wq_packed, scale_A, scale_W, expert_id)()\n" + } + ] +} diff --git a/solutions/mixed_mla/sglang_mixed_mla_decode_deepseek41_h64_d512_k8128_k4512.json b/solutions/mixed_mla/sglang_mixed_mla_decode_deepseek41_h64_d512_k8128_k4512.json new file mode 100644 index 0000000000000000000000000000000000000000..b23fa67deb4c7876d1e41d0b3d1dae4138e242f3 --- /dev/null +++ b/solutions/mixed_mla/sglang_mixed_mla_decode_deepseek41_h64_d512_k8128_k4512.json @@ -0,0 +1,23 @@ +{ + "name": "sglang_mixed_mla_decode_deepseek41_h64_d512_k8128_k4512", + "definition": "mixed_mla_decode_deepseek41_h64_d512_k8128_k4512", + "author": "kda", + "description": "SGLang's own implementation at the capture commit 684fea8a, called the way the engine calls it (see the module docstring). Run it in lmsysorg/sglang@sha256:ddae0e399d3d94f7827f16183301cf8dac4cf0eae0ef25590b7dac5881d713d8. KDA (Kernel Design Agents) times it live as the baseline: prepare(*inputs) does the host-side setup and returns a zero-argument launch, and only launch is timed; run(*inputs) does both.", + "spec": { + "language": "python", + "target_hardware": [ + "NVIDIA_B300" + ], + "entry_point": "main.py::run", + "dependencies": [ + "sglang @ git+https://github.com/sgl-project/sglang.git@684fea8af3b11a5b51ec9966c02959a32ad3421c#subdirectory=python" + ], + "destination_passing_style": false + }, + "sources": [ + { + "path": "main.py", + "content": "# Copyright 2026 Co-developed by KDA (Kernel Design Agents)\n\"\"\"SGLang baseline for mixed_mla_decode_deepseek41_h64_d512_k8128_k4512.\n\nSGLang 684fea8a, DeepSeek-V4.1 decode on SM100 with ``--tp-size 4``:\n``DeepseekV4AttnBackend._forward_attention``\n(sglang/srt/layers/attention/deepseek_v4_backend.py:3615) fills the batch's\nFlashMLA split schedule once with ``_maybe_precompute_flashmla_sched_meta``\n(:210, call :3818; the metadata comes from ``_create_flashmla_metadata``, :187,\nonce per batch, :878-898) and calls\n``sgl_kernel.flash_mla.flash_mla_with_kvcache(..., is_fp8_kvcache=True, ...)``\n(:3826) on the FP8 window cache and the FP4 extra cache. Each rank passes its\n16 query heads in a zero-filled 64-head buffer (models/deepseek_v4.py:2342,\nwidth :1054) with ``attn_sink`` sliced to the rank and zero-padded the same way\n(:1056-1079), and keeps its first 16 output heads (:2492).\n\nAdapter:\n\n- the four ranks run one after another and their heads are concatenated in\n rank order, as the capture gathers them;\n- the definition's pages are passed as SGLang's ``[pages, page_size, 1, bytes]``\n uint8 view (deepseek_v4_backend.py:3660), without the pool's page padding;\n- the definition has no ``topk_length``: a request's length is its last valid\n slot + 1, at least 1 (the capture set every slot past the engine's length to\n -1);\n- the schedule is computed in ``prepare`` and shared by the four rank calls,\n as the engine shares it across layers.\n\"\"\"\n\nimport torch\nfrom sgl_kernel.flash_mla import flash_mla_with_kvcache\nfrom sglang.srt.layers.attention.deepseek_v4_backend import (\n _create_flashmla_metadata,\n _maybe_precompute_flashmla_sched_meta,\n)\n\nTP = 4 # capture: --tp-size 4\n\n\ndef _topk_length(indices):\n slots = torch.arange(1, indices.shape[-1] + 1, device=indices.device)\n last = torch.where(indices[:, 0] >= 0, slots, 0).amax(1)\n return last.clamp_min(1).to(torch.int32)\n\n\ndef prepare(Q, KV8, KV4, indices8, indices4, attn_sink, sm_scale):\n heads = Q.shape[2] // TP\n k_cache = KV8.view(torch.uint8)\n extra_k_cache = KV4.view(torch.uint8)\n topk_length = _topk_length(indices8)\n extra_topk_length = _topk_length(indices4)\n q_padded = torch.zeros_like(Q)\n sink = torch.zeros_like(attn_sink)\n metadata = _create_flashmla_metadata()\n _maybe_precompute_flashmla_sched_meta(\n metadata,\n q=q_padded,\n indices=indices8,\n topk_length=topk_length,\n extra_indices=indices4,\n extra_topk_length=extra_topk_length,\n )\n\n def launch():\n out = []\n for rank in range(TP):\n local = slice(rank * heads, (rank + 1) * heads)\n q_padded[:, :, :heads] = Q[:, :, local]\n sink[:heads] = attn_sink[local]\n o = flash_mla_with_kvcache(\n q=q_padded,\n k_cache=k_cache,\n head_dim_v=Q.shape[-1],\n block_table=None,\n cache_seqlens=None,\n tile_scheduler_metadata=metadata,\n softmax_scale=float(sm_scale),\n is_fp8_kvcache=True,\n indices=indices8,\n topk_length=topk_length,\n attn_sink=sink,\n extra_k_cache=extra_k_cache,\n extra_indices_in_kvcache=indices4,\n extra_topk_length=extra_topk_length,\n )[0]\n out.append(o[:, :, :heads])\n return torch.cat(out, 2)\n\n return launch\n\n\ndef run(Q, KV8, KV4, indices8, indices4, attn_sink, sm_scale):\n return prepare(Q, KV8, KV4, indices8, indices4, attn_sink, sm_scale)()\n" + } + ] +} diff --git a/solutions/moe_router/sglang_moe_router_gemm_topk_deepseek41_d5120_e384_topk6.json b/solutions/moe_router/sglang_moe_router_gemm_topk_deepseek41_d5120_e384_topk6.json new file mode 100644 index 0000000000000000000000000000000000000000..972419352aac7b538b157426d017cb544c9255ab --- /dev/null +++ b/solutions/moe_router/sglang_moe_router_gemm_topk_deepseek41_d5120_e384_topk6.json @@ -0,0 +1,23 @@ +{ + "name": "sglang_moe_router_gemm_topk_deepseek41_d5120_e384_topk6", + "definition": "moe_router_gemm_topk_deepseek41_d5120_e384_topk6", + "author": "kda", + "description": "SGLang's own implementation at the capture commit 684fea8a, called the way the engine calls it (see the module docstring). Run it in lmsysorg/sglang@sha256:ddae0e399d3d94f7827f16183301cf8dac4cf0eae0ef25590b7dac5881d713d8. KDA (Kernel Design Agents) times it live as the baseline: prepare(*inputs) does the host-side setup and returns a zero-argument launch, and only launch is timed; run(*inputs) does both.", + "spec": { + "language": "python", + "target_hardware": [ + "NVIDIA_B300" + ], + "entry_point": "main.py::run", + "dependencies": [ + "sglang @ git+https://github.com/sgl-project/sglang.git@684fea8af3b11a5b51ec9966c02959a32ad3421c#subdirectory=python" + ], + "destination_passing_style": false + }, + "sources": [ + { + "path": "main.py", + "content": "# Copyright 2026 Co-developed by KDA (Kernel Design Agents)\n\"\"\"SGLang 684fea8a: DeepSeek-V4.1 ``MoEGate.forward`` followed by ``vision_topk``.\n\nCall path (``python/sglang/``):\n1. ``srt/models/deepseek_v2.py:572-587`` ``MoEGate.forward`` (deterministic inference\n off): ``tiny_gemm_bf16(X, W, out_dtype=float32, max_m=16)`` for M <= 16\n (``tiny_router_gemm_max_tokens``, ``srt/models/deepseek_common/utils.py:185-199``),\n else ``linear_bf16_fp32(X, W)`` (cuBLAS ``torch.mm`` with fp32 output).\n2. ``srt/multimodal/dsv41/vl_routing.py:59-75`` ``vision_topk`` -> ``moe_fused_gate``\n (``kernels/ops/moe/moe_fused_gate.py:337``) with the capture's arguments:\n sqrtsoftplus in its log1p form, the image bias selected through ``input_ids``,\n renormalization with epsilon 1e-20, the routed scale deferred, no fused shared\n experts, no packed output. ``_finish_vision_topk`` is a no-op under the capture's\n flags.\n\nAdapters (the capture's): ``is_image_token`` -> ``input_ids`` in ``prepare`` (the\nkernel only compares them with ``bias_alt_token_id``); the deferred routed scale\napplied to the selected weights (``output_adapter``); the IDs sorted ascending with\ntheir weights and cast to int64 (``selection_order``).\n\"\"\"\n\nimport torch\nfrom sglang.kernels.ops.gemm.bf16_fp32 import linear_bf16_fp32\nfrom sglang.kernels.ops.gemm.tiny_gemm import tiny_gemm_bf16\nfrom sglang.kernels.ops.moe.moe_fused_gate import moe_fused_gate\nfrom sglang.srt.layers.moe.topk import _RENORMALIZE_SUM_EPSILON\nfrom sglang.srt.models.deepseek_common.utils import tiny_router_gemm_max_tokens\n\nTOPK = 6\nTINY_MAX = tiny_router_gemm_max_tokens(\n num_experts=384, hidden_size=5120, weight_dtype=torch.bfloat16\n)\nIMAGE_TOKEN_ID = 1 # stands for config.image_token_id; the kernel only tests equality\n\n\ndef prepare(X, W, bias_text, bias_image, is_image_token, routed_scale):\n input_ids = torch.where(is_image_token, IMAGE_TOKEN_ID, IMAGE_TOKEN_ID + 1)\n\n def launch():\n # deepseek_v2.py:572-587\n if X.shape[0] <= TINY_MAX:\n logits = tiny_gemm_bf16(X, W, out_dtype=torch.float32, max_m=TINY_MAX)\n else:\n logits = linear_bf16_fp32(X, W)\n # vl_routing.py:59-75\n weights, indices = moe_fused_gate(\n logits,\n bias_text,\n topk=TOPK,\n scoring_func=\"sqrtsoftplus\",\n num_fused_shared_experts=0,\n bias_alt=bias_image,\n input_ids=input_ids,\n bias_alt_token_id=IMAGE_TOKEN_ID,\n renormalize=True,\n renormalize_epsilon=_RENORMALIZE_SUM_EPSILON,\n routed_scaling_factor=routed_scale,\n apply_routed_scaling_factor_on_output=False,\n num_token_non_padded=None,\n packed_out=None,\n sqrtsoftplus_log1p=True,\n )\n ids, order = indices.long().sort(-1)\n return ids, weights.gather(1, order) * routed_scale\n\n return launch\n\n\ndef run(*inputs):\n return prepare(*inputs)()\n" + } + ] +} diff --git a/solutions/neighborhood_attention/sglang_neighborhood_attention_3d_h16_d64_kt3_ky7_kx7.json b/solutions/neighborhood_attention/sglang_neighborhood_attention_3d_h16_d64_kt3_ky7_kx7.json new file mode 100644 index 0000000000000000000000000000000000000000..a5ddea11002b091191e3e6d2f7e7afab813ccc36 --- /dev/null +++ b/solutions/neighborhood_attention/sglang_neighborhood_attention_3d_h16_d64_kt3_ky7_kx7.json @@ -0,0 +1,23 @@ +{ + "name": "sglang_neighborhood_attention_3d_h16_d64_kt3_ky7_kx7", + "definition": "neighborhood_attention_3d_h16_d64_kt3_ky7_kx7", + "author": "kda", + "description": "SGLang's own implementation at the capture commit 684fea8a, called the way the engine calls it (see the module docstring). Run it in lmsysorg/sglang@sha256:ddae0e399d3d94f7827f16183301cf8dac4cf0eae0ef25590b7dac5881d713d8. KDA (Kernel Design Agents) times it live as the baseline: prepare(*inputs) does the host-side setup and returns a zero-argument launch, and only launch is timed; run(*inputs) does both.", + "spec": { + "language": "python", + "target_hardware": [ + "NVIDIA_B300" + ], + "entry_point": "main.py::run", + "dependencies": [ + "sglang @ git+https://github.com/sgl-project/sglang.git@684fea8af3b11a5b51ec9966c02959a32ad3421c#subdirectory=python" + ], + "destination_passing_style": false + }, + "sources": [ + { + "path": "main.py", + "content": "# Copyright 2026 Co-developed by KDA (Kernel Design Agents)\n\"\"\"SGLang baseline for neighborhood_attention_3d_h16_d64_kt3_ky7_kx7.\n\nSGLang diffusion runtime at commit 684fea8a,\npython/sglang/multimodal_gen/runtime/models/decoders/ltx_2_5_diffusion_decoder.py:\nLTX2VideoVaeNeighborhoodAttention.forward (:425) after project_qkv (:435).\nNATTEN is absent from the image, so _na3d() (:49) is None and forward takes the\nFlexAttention branch: Q/K/V viewed as (B, heads, S, head_dim) (:449-459), the\nblock mask from build_block_mask (:413) -> _neighborhood_block_mask(T, H, W,\nkernel_size, device) (:170), and _flex_attention_fn() (:104, torch.compile of\nflex_attention, dynamic=False) called with scale=1.0 (:465-467).\n\nAdapter: Q/K/V arrive as project_qkv returns them, [B, T, Y, X, H, D].\nkernel_size is the module's (Kt, Ky, Kx). The decoder builds the block mask\nonce per stage (:771, :785, :835) and passes it to every block, so prepare\nbuilds it and launch runs only the attention. The output keeps the heads\nsplit: :468-470 merges them into channels for to_out, which is not part of\nthis op; that reshape is a view of the flex output, so launch detaches it\n(no copy) to return a tensor that owns its storage.\n\"\"\"\n\nimport torch\nfrom sglang.multimodal_gen.runtime.models.decoders import (\n ltx_2_5_diffusion_decoder as ltx,\n)\n\nKERNEL_SIZE = (3, 7, 7)\n\n# The engine meets a few grids per process; one judge process meets every\n# workload's shape. Past dynamo's default limit of 8 recompiles flex_attention\n# would run uncompiled, materializing the dense S x S scores.\ntorch._dynamo.config.recompile_limit = 1024\ntorch._dynamo.config.accumulated_recompile_limit = 4096\n# The judge rejects a candidate that leaves child processes running, and\n# inductor's parallel compile pool is one; compile in-process instead.\ntorch._inductor.config.compile_threads = 1\n\n\ndef prepare(Q, K, V):\n batch_size, num_frames, height, width, heads, head_dim = Q.shape\n seq_len = num_frames * height * width\n # :451-459\n query = Q.reshape(batch_size, seq_len, heads, head_dim).transpose(1, 2)\n key = K.reshape(batch_size, seq_len, heads, head_dim).transpose(1, 2)\n value = V.reshape(batch_size, seq_len, heads, head_dim).transpose(1, 2)\n # build_block_mask, :420-423\n block_mask = ltx._neighborhood_block_mask(\n num_frames, height, width, KERNEL_SIZE, Q.device\n )\n flex_attention = ltx._flex_attention_fn()\n\n def launch():\n # :465-467\n hidden_states = flex_attention(\n query, key, value, block_mask=block_mask, scale=1.0\n )\n # :468-470, heads kept split. The reshape is a view of flex_attention's\n # own exact-sized output; detach() hands it over as a tensor of its own.\n return hidden_states.transpose(1, 2).reshape(Q.shape).detach()\n\n return launch\n\n\ndef run(Q, K, V):\n return prepare(Q, K, V)()\n" + } + ] +} diff --git a/solutions/neighborhood_attention/sglang_neighborhood_attention_3d_h32_d64_kt3_ky7_kx7.json b/solutions/neighborhood_attention/sglang_neighborhood_attention_3d_h32_d64_kt3_ky7_kx7.json new file mode 100644 index 0000000000000000000000000000000000000000..8b9470880036db80584989a5858078cac391d768 --- /dev/null +++ b/solutions/neighborhood_attention/sglang_neighborhood_attention_3d_h32_d64_kt3_ky7_kx7.json @@ -0,0 +1,23 @@ +{ + "name": "sglang_neighborhood_attention_3d_h32_d64_kt3_ky7_kx7", + "definition": "neighborhood_attention_3d_h32_d64_kt3_ky7_kx7", + "author": "kda", + "description": "SGLang's own implementation at the capture commit 684fea8a, called the way the engine calls it (see the module docstring). Run it in lmsysorg/sglang@sha256:ddae0e399d3d94f7827f16183301cf8dac4cf0eae0ef25590b7dac5881d713d8. KDA (Kernel Design Agents) times it live as the baseline: prepare(*inputs) does the host-side setup and returns a zero-argument launch, and only launch is timed; run(*inputs) does both.", + "spec": { + "language": "python", + "target_hardware": [ + "NVIDIA_B300" + ], + "entry_point": "main.py::run", + "dependencies": [ + "sglang @ git+https://github.com/sgl-project/sglang.git@684fea8af3b11a5b51ec9966c02959a32ad3421c#subdirectory=python" + ], + "destination_passing_style": false + }, + "sources": [ + { + "path": "main.py", + "content": "# Copyright 2026 Co-developed by KDA (Kernel Design Agents)\n\"\"\"SGLang baseline for neighborhood_attention_3d_h32_d64_kt3_ky7_kx7.\n\nSGLang diffusion runtime at commit 684fea8a,\npython/sglang/multimodal_gen/runtime/models/decoders/ltx_2_5_diffusion_decoder.py:\nLTX2VideoVaeNeighborhoodAttention.forward (:425) after project_qkv (:435).\nNATTEN is absent from the image, so _na3d() (:49) is None and forward takes the\nFlexAttention branch: Q/K/V viewed as (B, heads, S, head_dim) (:449-459), the\nblock mask from build_block_mask (:413) -> _neighborhood_block_mask(T, H, W,\nkernel_size, device) (:170), and _flex_attention_fn() (:104, torch.compile of\nflex_attention, dynamic=False) called with scale=1.0 (:465-467).\n\nAdapter: Q/K/V arrive as project_qkv returns them, [B, T, Y, X, H, D].\nkernel_size is the module's (Kt, Ky, Kx). The decoder builds the block mask\nonce per stage (:771, :785, :835) and passes it to every block, so prepare\nbuilds it and launch runs only the attention. The output keeps the heads\nsplit: :468-470 merges them into channels for to_out, which is not part of\nthis op; that reshape is a view of the flex output, so launch detaches it\n(no copy) to return a tensor that owns its storage.\n\"\"\"\n\nimport torch\nfrom sglang.multimodal_gen.runtime.models.decoders import (\n ltx_2_5_diffusion_decoder as ltx,\n)\n\nKERNEL_SIZE = (3, 7, 7)\n\n# The engine meets a few grids per process; one judge process meets every\n# workload's shape. Past dynamo's default limit of 8 recompiles flex_attention\n# would run uncompiled, materializing the dense S x S scores.\ntorch._dynamo.config.recompile_limit = 1024\ntorch._dynamo.config.accumulated_recompile_limit = 4096\n# The judge rejects a candidate that leaves child processes running, and\n# inductor's parallel compile pool is one; compile in-process instead.\ntorch._inductor.config.compile_threads = 1\n\n\ndef prepare(Q, K, V):\n batch_size, num_frames, height, width, heads, head_dim = Q.shape\n seq_len = num_frames * height * width\n # :451-459\n query = Q.reshape(batch_size, seq_len, heads, head_dim).transpose(1, 2)\n key = K.reshape(batch_size, seq_len, heads, head_dim).transpose(1, 2)\n value = V.reshape(batch_size, seq_len, heads, head_dim).transpose(1, 2)\n # build_block_mask, :420-423\n block_mask = ltx._neighborhood_block_mask(\n num_frames, height, width, KERNEL_SIZE, Q.device\n )\n flex_attention = ltx._flex_attention_fn()\n\n def launch():\n # :465-467\n hidden_states = flex_attention(\n query, key, value, block_mask=block_mask, scale=1.0\n )\n # :468-470, heads kept split. The reshape is a view of flex_attention's\n # own exact-sized output; detach() hands it over as a tensor of its own.\n return hidden_states.transpose(1, 2).reshape(Q.shape).detach()\n\n return launch\n\n\ndef run(Q, K, V):\n return prepare(Q, K, V)()\n" + } + ] +} diff --git a/solutions/neighborhood_attention/sglang_neighborhood_attention_3d_h4_d64_kt11_ky11_kx11.json b/solutions/neighborhood_attention/sglang_neighborhood_attention_3d_h4_d64_kt11_ky11_kx11.json new file mode 100644 index 0000000000000000000000000000000000000000..e9f99086b9e878fd32b8d305fbce77d23b915e90 --- /dev/null +++ b/solutions/neighborhood_attention/sglang_neighborhood_attention_3d_h4_d64_kt11_ky11_kx11.json @@ -0,0 +1,23 @@ +{ + "name": "sglang_neighborhood_attention_3d_h4_d64_kt11_ky11_kx11", + "definition": "neighborhood_attention_3d_h4_d64_kt11_ky11_kx11", + "author": "kda", + "description": "SGLang's own implementation at the capture commit 684fea8a, called the way the engine calls it (see the module docstring). Run it in lmsysorg/sglang@sha256:ddae0e399d3d94f7827f16183301cf8dac4cf0eae0ef25590b7dac5881d713d8. KDA (Kernel Design Agents) times it live as the baseline: prepare(*inputs) does the host-side setup and returns a zero-argument launch, and only launch is timed; run(*inputs) does both.", + "spec": { + "language": "python", + "target_hardware": [ + "NVIDIA_B300" + ], + "entry_point": "main.py::run", + "dependencies": [ + "sglang @ git+https://github.com/sgl-project/sglang.git@684fea8af3b11a5b51ec9966c02959a32ad3421c#subdirectory=python" + ], + "destination_passing_style": false + }, + "sources": [ + { + "path": "main.py", + "content": "# Copyright 2026 Co-developed by KDA (Kernel Design Agents)\n\"\"\"SGLang baseline for neighborhood_attention_3d_h4_d64_kt11_ky11_kx11.\n\nSGLang diffusion runtime at commit 684fea8a,\npython/sglang/multimodal_gen/runtime/models/decoders/ltx_2_5_diffusion_decoder.py:\nLTX2VideoVaeNeighborhoodAttention.forward (:425) after project_qkv (:435).\nNATTEN is absent from the image, so _na3d() (:49) is None and forward takes the\nFlexAttention branch: Q/K/V viewed as (B, heads, S, head_dim) (:449-459), the\nblock mask from build_block_mask (:413) -> _neighborhood_block_mask(T, H, W,\nkernel_size, device) (:170), and _flex_attention_fn() (:104, torch.compile of\nflex_attention, dynamic=False) called with scale=1.0 (:465-467).\n\nAdapter: Q/K/V arrive as project_qkv returns them, [B, T, Y, X, H, D].\nkernel_size is the module's (Kt, Ky, Kx). The decoder builds the block mask\nonce per stage (:771, :785, :835) and passes it to every block, so prepare\nbuilds it and launch runs only the attention. The output keeps the heads\nsplit: :468-470 merges them into channels for to_out, which is not part of\nthis op; that reshape is a view of the flex output, so launch detaches it\n(no copy) to return a tensor that owns its storage.\n\"\"\"\n\nimport torch\nfrom sglang.multimodal_gen.runtime.models.decoders import (\n ltx_2_5_diffusion_decoder as ltx,\n)\n\nKERNEL_SIZE = (11, 11, 11)\n\n# The engine meets a few grids per process; one judge process meets every\n# workload's shape. Past dynamo's default limit of 8 recompiles flex_attention\n# would run uncompiled, materializing the dense S x S scores.\ntorch._dynamo.config.recompile_limit = 1024\ntorch._dynamo.config.accumulated_recompile_limit = 4096\n# The judge rejects a candidate that leaves child processes running, and\n# inductor's parallel compile pool is one; compile in-process instead.\ntorch._inductor.config.compile_threads = 1\n\n\ndef prepare(Q, K, V):\n batch_size, num_frames, height, width, heads, head_dim = Q.shape\n seq_len = num_frames * height * width\n # :451-459\n query = Q.reshape(batch_size, seq_len, heads, head_dim).transpose(1, 2)\n key = K.reshape(batch_size, seq_len, heads, head_dim).transpose(1, 2)\n value = V.reshape(batch_size, seq_len, heads, head_dim).transpose(1, 2)\n # build_block_mask, :420-423\n block_mask = ltx._neighborhood_block_mask(\n num_frames, height, width, KERNEL_SIZE, Q.device\n )\n flex_attention = ltx._flex_attention_fn()\n\n def launch():\n # :465-467\n hidden_states = flex_attention(\n query, key, value, block_mask=block_mask, scale=1.0\n )\n # :468-470, heads kept split. The reshape is a view of flex_attention's\n # own exact-sized output; detach() hands it over as a tensor of its own.\n return hidden_states.transpose(1, 2).reshape(Q.shape).detach()\n\n return launch\n\n\ndef run(Q, K, V):\n return prepare(Q, K, V)()\n" + } + ] +} diff --git a/solutions/neighborhood_attention/sglang_neighborhood_attention_3d_h8_d64_kt3_ky5_kx5.json b/solutions/neighborhood_attention/sglang_neighborhood_attention_3d_h8_d64_kt3_ky5_kx5.json new file mode 100644 index 0000000000000000000000000000000000000000..d9434afd793a8666c8d97c704660419033b51f8c --- /dev/null +++ b/solutions/neighborhood_attention/sglang_neighborhood_attention_3d_h8_d64_kt3_ky5_kx5.json @@ -0,0 +1,23 @@ +{ + "name": "sglang_neighborhood_attention_3d_h8_d64_kt3_ky5_kx5", + "definition": "neighborhood_attention_3d_h8_d64_kt3_ky5_kx5", + "author": "kda", + "description": "SGLang's own implementation at the capture commit 684fea8a, called the way the engine calls it (see the module docstring). Run it in lmsysorg/sglang@sha256:ddae0e399d3d94f7827f16183301cf8dac4cf0eae0ef25590b7dac5881d713d8. KDA (Kernel Design Agents) times it live as the baseline: prepare(*inputs) does the host-side setup and returns a zero-argument launch, and only launch is timed; run(*inputs) does both.", + "spec": { + "language": "python", + "target_hardware": [ + "NVIDIA_B300" + ], + "entry_point": "main.py::run", + "dependencies": [ + "sglang @ git+https://github.com/sgl-project/sglang.git@684fea8af3b11a5b51ec9966c02959a32ad3421c#subdirectory=python" + ], + "destination_passing_style": false + }, + "sources": [ + { + "path": "main.py", + "content": "# Copyright 2026 Co-developed by KDA (Kernel Design Agents)\n\"\"\"SGLang baseline for neighborhood_attention_3d_h8_d64_kt3_ky5_kx5.\n\nSGLang diffusion runtime at commit 684fea8a,\npython/sglang/multimodal_gen/runtime/models/decoders/ltx_2_5_diffusion_decoder.py:\nLTX2VideoVaeNeighborhoodAttention.forward (:425) after project_qkv (:435).\nNATTEN is absent from the image, so _na3d() (:49) is None and forward takes the\nFlexAttention branch: Q/K/V viewed as (B, heads, S, head_dim) (:449-459), the\nblock mask from build_block_mask (:413) -> _neighborhood_block_mask(T, H, W,\nkernel_size, device) (:170), and _flex_attention_fn() (:104, torch.compile of\nflex_attention, dynamic=False) called with scale=1.0 (:465-467).\n\nAdapter: Q/K/V arrive as project_qkv returns them, [B, T, Y, X, H, D].\nkernel_size is the module's (Kt, Ky, Kx). The decoder builds the block mask\nonce per stage (:771, :785, :835) and passes it to every block, so prepare\nbuilds it and launch runs only the attention. The output keeps the heads\nsplit: :468-470 merges them into channels for to_out, which is not part of\nthis op; that reshape is a view of the flex output, so launch detaches it\n(no copy) to return a tensor that owns its storage.\n\"\"\"\n\nimport torch\nfrom sglang.multimodal_gen.runtime.models.decoders import (\n ltx_2_5_diffusion_decoder as ltx,\n)\n\nKERNEL_SIZE = (3, 5, 5)\n\n# The engine meets a few grids per process; one judge process meets every\n# workload's shape. Past dynamo's default limit of 8 recompiles flex_attention\n# would run uncompiled, materializing the dense S x S scores.\ntorch._dynamo.config.recompile_limit = 1024\ntorch._dynamo.config.accumulated_recompile_limit = 4096\n# The judge rejects a candidate that leaves child processes running, and\n# inductor's parallel compile pool is one; compile in-process instead.\ntorch._inductor.config.compile_threads = 1\n\n\ndef prepare(Q, K, V):\n batch_size, num_frames, height, width, heads, head_dim = Q.shape\n seq_len = num_frames * height * width\n # :451-459\n query = Q.reshape(batch_size, seq_len, heads, head_dim).transpose(1, 2)\n key = K.reshape(batch_size, seq_len, heads, head_dim).transpose(1, 2)\n value = V.reshape(batch_size, seq_len, heads, head_dim).transpose(1, 2)\n # build_block_mask, :420-423\n block_mask = ltx._neighborhood_block_mask(\n num_frames, height, width, KERNEL_SIZE, Q.device\n )\n flex_attention = ltx._flex_attention_fn()\n\n def launch():\n # :465-467\n hidden_states = flex_attention(\n query, key, value, block_mask=block_mask, scale=1.0\n )\n # :468-470, heads kept split. The reshape is a view of flex_attention's\n # own exact-sized output; detach() hands it over as a tensor of its own.\n return hidden_states.transpose(1, 2).reshape(Q.shape).detach()\n\n return launch\n\n\ndef run(Q, K, V):\n return prepare(Q, K, V)()\n" + } + ] +} diff --git a/solutions/qsa_attention/sglang_qsa_sparse_gqa_decode_qwen38_h24_kv2_d256_topk512_c4.json b/solutions/qsa_attention/sglang_qsa_sparse_gqa_decode_qwen38_h24_kv2_d256_topk512_c4.json new file mode 100644 index 0000000000000000000000000000000000000000..c6bd8d1808a7cc289dd8ae2d62576b7edae55b75 --- /dev/null +++ b/solutions/qsa_attention/sglang_qsa_sparse_gqa_decode_qwen38_h24_kv2_d256_topk512_c4.json @@ -0,0 +1,23 @@ +{ + "name": "sglang_qsa_sparse_gqa_decode_qwen38_h24_kv2_d256_topk512_c4", + "definition": "qsa_sparse_gqa_decode_qwen38_h24_kv2_d256_topk512_c4", + "author": "kda", + "description": "SGLang's own implementation at the capture commit 684fea8a, called the way the engine calls it (see the module docstring). Run it in lmsysorg/sglang@sha256:ddae0e399d3d94f7827f16183301cf8dac4cf0eae0ef25590b7dac5881d713d8. KDA (Kernel Design Agents) times it live as the baseline: prepare(*inputs) does the host-side setup and returns a zero-argument launch, and only launch is timed; run(*inputs) does both.", + "spec": { + "language": "python", + "target_hardware": [ + "NVIDIA_B300" + ], + "entry_point": "main.py::run", + "dependencies": [ + "sglang @ git+https://github.com/sgl-project/sglang.git@684fea8af3b11a5b51ec9966c02959a32ad3421c#subdirectory=python" + ], + "destination_passing_style": false + }, + "sources": [ + { + "path": "main.py", + "content": "# Copyright 2026 Co-developed by KDA (Kernel Design Agents)\n\"\"\"SGLang baseline for qsa_sparse_gqa_decode_qwen38_h24_kv2_d256_topk512_c4.\n\nSGLang 684fea8a, ``QwenSparseAttnBackend.forward_decode``\n(sglang/srt/layers/attention/qwen_sparse_attn_backend.py:1817) with a bf16 MHA\npool on SM100: ``_try_fused_kv_attention`` (:1363) ->\n``_forward_trtllm_sparse(new_kv=...)`` (:1682), which runs\n\n- ``fused_kv_prepare(...)`` (call :1730; qsa/fused_kv.py:131), then\n- ``flashinfer.decode.trtllm_batch_decode_with_kv_cache(...)`` (call :1804),\n with ``bmm1_scale = head_dim**-0.5`` (models/qwen3_5.py:1269).\n\nThe backend needs server state, so the two calls get the arguments that method\npasses, and its cached scratch, tables, workspace and counters\n(:1646-1680, :1788-1803) are set up in ``prepare``. Adapter:\n\n- ``req_to_token`` is built from ``page_table`` at a fixed width, as SGLang's\n pool has one (``context_len + 4``, mem_cache/kv_cache_configurator.py:1562;\n ``fused_kv_prepare`` specializes on its row stride);\n- ``loc`` is the current token's slot and its k/v are re-read from the cache:\n the capture is taken after the current-token KV write, so the kernel's\n write-back stores the values already there;\n- SGLang never places a token in slot 0 (mem_cache/allocator/paged.py:396) and\n ``fused_kv_prepare`` treats ``loc == 0`` as a padding row, so when a current\n token sits in slot 0 the pages are shifted by one behind an empty page 0.\n\"\"\"\n\nimport torch\nfrom flashinfer.decode import trtllm_batch_decode_with_kv_cache\nfrom flashinfer.utils import get_trtllm_gen_multi_ctas_kv_counter_bytes\nfrom sglang.srt.layers.attention.qsa.fused_kv import fused_kv_prepare\n\nPAGE = 64 # _TRTLLM_SPARSE_PAGE_SIZE (qwen_sparse_attn_backend.py:61)\nRATIO = 4\nTABLE_WIDTH = 262144 + 4 # a 256K context_len + 4\n_WORKSPACES = {}\n_COUNTERS = {}\n\n\ndef prepare(Q, K_pages, V_pages, page_table, block_ids, context_lens):\n batch, heads, dim = Q.shape\n page_size, kv_heads = K_pages.shape[1:3]\n device = Q.device\n rows = torch.arange(batch, device=device)\n tokens = torch.arange(page_table.shape[1] * page_size, device=device)\n slots = page_table.long()[:, tokens // page_size] * page_size + tokens % page_size\n shift = bool((slots[rows, context_lens.long() - 1] == 0).any())\n if shift:\n slots += page_size\n req_to_token = torch.zeros(\n batch, max(TABLE_WIDTH, slots.shape[1]), dtype=torch.int32, device=device\n )\n req_to_token[:, : slots.shape[1]] = slots\n loc = slots[rows, context_lens.long() - 1]\n query_positions = context_lens - 1\n\n # _forward_trtllm_sparse (:1696-1703, :1646-1680)\n topk = block_ids.shape[1] * RATIO + RATIO - 1\n pages_per_row = (topk + PAGE - 1) // PAGE\n stride = pages_per_row * PAGE\n counts = torch.empty(batch, dtype=torch.int32, device=device)\n packed_k = torch.zeros(batch * stride, kv_heads, dim, dtype=Q.dtype, device=device)\n packed_v = torch.zeros_like(packed_k)\n kv_cache = tuple(\n x.view(-1, PAGE, kv_heads, dim).permute(0, 2, 1, 3)\n for x in (packed_k, packed_v)\n )\n block_tables = (\n rows.int()[:, None] * pages_per_row\n + torch.arange(pages_per_row, dtype=torch.int32, device=device)[None, :]\n ).contiguous()\n if device not in _WORKSPACES:\n _WORKSPACES[device] = torch.zeros(\n 128 * 1024 * 1024, dtype=torch.uint8, device=device\n )\n key = (batch, heads, device)\n if key not in _COUNTERS:\n sms = torch.cuda.get_device_properties(device).multi_processor_count\n size = get_trtllm_gen_multi_ctas_kv_counter_bytes(batch, heads, sms)\n _COUNTERS[key] = torch.zeros(size, dtype=torch.uint8, device=device)\n\n def launch():\n k_buffer = K_pages.view(-1, kv_heads, dim)\n v_buffer = V_pages.view(-1, kv_heads, dim)\n if shift:\n empty = k_buffer.new_zeros(page_size, kv_heads, dim)\n k_buffer = torch.cat([empty, k_buffer])\n v_buffer = torch.cat([empty, v_buffer])\n fused_kv_prepare(\n k_buffer,\n v_buffer,\n k_buffer.index_select(0, loc),\n v_buffer.index_select(0, loc),\n loc,\n req_to_token,\n rows,\n block_ids,\n context_lens,\n counts,\n packed_k,\n packed_v,\n 1,\n compress_ratio=RATIO,\n chain_positions=True,\n query_positions=query_positions,\n visible_page_size=PAGE,\n )\n return trtllm_batch_decode_with_kv_cache(\n query=Q,\n kv_cache=kv_cache,\n workspace_buffer=_WORKSPACES[device],\n block_tables=block_tables,\n seq_lens=counts,\n max_seq_len=stride,\n bmm1_scale=dim**-0.5,\n bmm2_scale=1.0,\n multi_ctas_kv_counter_buffer=_COUNTERS[key],\n )\n\n return launch\n\n\ndef run(Q, K_pages, V_pages, page_table, block_ids, context_lens):\n return prepare(Q, K_pages, V_pages, page_table, block_ids, context_lens)()\n" + } + ] +} diff --git a/solutions/qsa_index/sglang_qsa_index_topk_decode_qwen38_h4_d128_topk512_c4.json b/solutions/qsa_index/sglang_qsa_index_topk_decode_qwen38_h4_d128_topk512_c4.json new file mode 100644 index 0000000000000000000000000000000000000000..a10b29f0045b30f6881ab39a021ca11439ecaf32 --- /dev/null +++ b/solutions/qsa_index/sglang_qsa_index_topk_decode_qwen38_h4_d128_topk512_c4.json @@ -0,0 +1,23 @@ +{ + "name": "sglang_qsa_index_topk_decode_qwen38_h4_d128_topk512_c4", + "definition": "qsa_index_topk_decode_qwen38_h4_d128_topk512_c4", + "author": "kda", + "description": "SGLang's own implementation at the capture commit 684fea8a, called the way the engine calls it (see the module docstring). Run it in lmsysorg/sglang@sha256:ddae0e399d3d94f7827f16183301cf8dac4cf0eae0ef25590b7dac5881d713d8. KDA (Kernel Design Agents) times it live as the baseline: prepare(*inputs) does the host-side setup and returns a zero-argument launch, and only launch is timed; run(*inputs) does both.", + "spec": { + "language": "python", + "target_hardware": [ + "NVIDIA_B300" + ], + "entry_point": "main.py::run", + "dependencies": [ + "sglang @ git+https://github.com/sgl-project/sglang.git@684fea8af3b11a5b51ec9966c02959a32ad3421c#subdirectory=python" + ], + "destination_passing_style": false + }, + "sources": [ + { + "path": "main.py", + "content": "# Copyright 2026 Co-developed by KDA (Kernel Design Agents)\n\"\"\"SGLang baseline for qsa_index_topk_decode_qwen38_h4_d128_topk512_c4.\n\nSGLang 684fea8a, ``QSAIndexer.select_decode_tokens``\n(sglang/srt/layers/attention/qsa/qsa_indexer.py:491) as decode calls it, with\ndeferred block expansion (qsa_indexer.py:719-727):\n\n- ``qsa_mqa_decode(q, compressed_cache, page_table, compressed_lengths,\n max_model_len, min_scored_len=512)`` (qsa_indexer.py:505; the TileLang kernel\n of qsa/mqa.py:378);\n- ``fast_topk(logits, compressed_lengths, topk=512, row_starts=None)``\n (qsa_indexer.py:518; sglang/kernels/ops/attention/fast_topk.py:38).\n\nAdapter: ``Q_idx`` is written into a zero-padded 8-head query, as\n``project_qk`` pads decode queries (qsa_indexer.py:700); ``max_model_len`` is\n``MP * P`` (qsa/metadata.py:233); the engine's unordered selection is\nserialized in increasing ID order with a -1 suffix (the capture's output\nadapter).\n\"\"\"\n\nfrom sglang.kernels.ops.attention.fast_topk import fast_topk\nfrom sglang.srt.layers.attention.qsa.mqa import qsa_mqa_decode\n\nTOPK = 512\nPADDED_HEADS = 8 # the TileLang decode kernel needs query heads in multiples of 8\n# Flipping the sign bit keeps block IDs in order and moves -1 after all of them.\n_SIGN = -(2**31)\n\n\ndef prepare(Q_idx, Kc_pages, page_table, num_complete_blocks):\n batch, heads, dim = Q_idx.shape\n q = Q_idx.new_zeros(batch, PADDED_HEADS, dim)\n max_model_len = page_table.shape[1] * Kc_pages.shape[1]\n\n def launch():\n q[:, :heads].copy_(Q_idx)\n logits = qsa_mqa_decode(\n q,\n Kc_pages,\n page_table,\n num_complete_blocks,\n max_model_len,\n min_scored_len=TOPK,\n )\n ids = fast_topk(logits, num_complete_blocks, topk=TOPK, row_starts=None)\n return ids.bitwise_xor_(_SIGN).sort(1).values.bitwise_xor_(_SIGN)\n\n return launch\n\n\ndef run(Q_idx, Kc_pages, page_table, num_complete_blocks):\n return prepare(Q_idx, Kc_pages, page_table, num_complete_blocks)()\n" + } + ] +} diff --git a/solutions/sparse_mla/sglang_sparse_mla_prefill_h64_d512_k128.json b/solutions/sparse_mla/sglang_sparse_mla_prefill_h64_d512_k128.json new file mode 100644 index 0000000000000000000000000000000000000000..5dfa3aa17314a60403a7a174afed7ed1b2bef461 --- /dev/null +++ b/solutions/sparse_mla/sglang_sparse_mla_prefill_h64_d512_k128.json @@ -0,0 +1,23 @@ +{ + "name": "sglang_sparse_mla_prefill_h64_d512_k128", + "definition": "sparse_mla_prefill_h64_d512_k128", + "author": "kda", + "description": "SGLang's own implementation at the capture commit 684fea8a, called the way the engine calls it (see the module docstring). Run it in lmsysorg/sglang@sha256:ddae0e399d3d94f7827f16183301cf8dac4cf0eae0ef25590b7dac5881d713d8. KDA (Kernel Design Agents) times it live as the baseline: prepare(*inputs) does the host-side setup and returns a zero-argument launch, and only launch is timed; run(*inputs) does both.", + "spec": { + "language": "python", + "target_hardware": [ + "NVIDIA_B300" + ], + "entry_point": "main.py::run", + "dependencies": [ + "sglang @ git+https://github.com/sgl-project/sglang.git@684fea8af3b11a5b51ec9966c02959a32ad3421c#subdirectory=python" + ], + "destination_passing_style": false + }, + "sources": [ + { + "path": "main.py", + "content": "# Copyright 2026 Co-developed by KDA (Kernel Design Agents)\n\"\"\"SGLang baseline for sparse_mla_prefill_h64_d512_k128.\n\nSGLang 684fea8a, DeepSeek-V4.1 sparse prefill with ``--tp-size 4``:\n``DeepseekV4AttnBackend._forward_prefill_sparse``\n(sglang/srt/layers/attention/deepseek_v4_backend.py:3848) calls\n``sgl_kernel.flash_mla.flash_mla_sparse_fwd(q, kv, indices, sm_scale, d_v,\nattn_sink, topk_length)`` (:3916) on the BF16 workspace. Each rank passes its\n16 query heads in a zero-filled 64-head buffer (models/deepseek_v4.py:2342,\nwidth :1054) with ``attn_sink`` sliced to the rank and zero-padded the same way\n(:1056-1079), and keeps its first 16 output heads (:2492).\n\nAdapter: the four ranks run one after another and their heads are\nconcatenated in rank order, as the capture gathers them.\n\"\"\"\n\nimport torch\nfrom sgl_kernel.flash_mla import flash_mla_sparse_fwd\n\nTP = 4 # capture: --tp-size 4\n\n\ndef prepare(Q, KV, indices, topk_length, attn_sink, sm_scale):\n heads = Q.shape[1] // TP\n q_padded = torch.zeros_like(Q)\n sink = torch.zeros_like(attn_sink)\n\n def launch():\n out = []\n for rank in range(TP):\n local = slice(rank * heads, (rank + 1) * heads)\n q_padded[:, :heads] = Q[:, local]\n sink[:heads] = attn_sink[local]\n o, _, _ = flash_mla_sparse_fwd(\n q=q_padded,\n kv=KV,\n indices=indices,\n sm_scale=float(sm_scale),\n d_v=Q.shape[-1],\n attn_sink=sink,\n topk_length=topk_length,\n )\n out.append(o[:, :heads])\n return torch.cat(out, 1)\n\n return launch\n\n\ndef run(Q, KV, indices, topk_length, attn_sink, sm_scale):\n return prepare(Q, KV, indices, topk_length, attn_sink, sm_scale)()\n" + } + ] +} diff --git a/solutions/sparse_mla/sglang_sparse_mla_prefill_h64_d512_k640.json b/solutions/sparse_mla/sglang_sparse_mla_prefill_h64_d512_k640.json new file mode 100644 index 0000000000000000000000000000000000000000..d970832ddca9352e67c3d2286e84a1db00cdb3f5 --- /dev/null +++ b/solutions/sparse_mla/sglang_sparse_mla_prefill_h64_d512_k640.json @@ -0,0 +1,23 @@ +{ + "name": "sglang_sparse_mla_prefill_h64_d512_k640", + "definition": "sparse_mla_prefill_h64_d512_k640", + "author": "kda", + "description": "SGLang's own implementation at the capture commit 684fea8a, called the way the engine calls it (see the module docstring). Run it in lmsysorg/sglang@sha256:ddae0e399d3d94f7827f16183301cf8dac4cf0eae0ef25590b7dac5881d713d8. KDA (Kernel Design Agents) times it live as the baseline: prepare(*inputs) does the host-side setup and returns a zero-argument launch, and only launch is timed; run(*inputs) does both.", + "spec": { + "language": "python", + "target_hardware": [ + "NVIDIA_B300" + ], + "entry_point": "main.py::run", + "dependencies": [ + "sglang @ git+https://github.com/sgl-project/sglang.git@684fea8af3b11a5b51ec9966c02959a32ad3421c#subdirectory=python" + ], + "destination_passing_style": false + }, + "sources": [ + { + "path": "main.py", + "content": "# Copyright 2026 Co-developed by KDA (Kernel Design Agents)\n\"\"\"SGLang baseline for sparse_mla_prefill_h64_d512_k640.\n\nSGLang 684fea8a, DeepSeek-V4.1 sparse prefill with ``--tp-size 4``:\n``DeepseekV4AttnBackend._forward_prefill_sparse``\n(sglang/srt/layers/attention/deepseek_v4_backend.py:3848) calls\n``sgl_kernel.flash_mla.flash_mla_sparse_fwd(q, kv, indices, sm_scale, d_v,\nattn_sink, topk_length)`` (:3916) on the BF16 workspace. Each rank passes its\n16 query heads in a zero-filled 64-head buffer (models/deepseek_v4.py:2342,\nwidth :1054) with ``attn_sink`` sliced to the rank and zero-padded the same way\n(:1056-1079), and keeps its first 16 output heads (:2492).\n\nAdapter: the four ranks run one after another and their heads are\nconcatenated in rank order, as the capture gathers them.\n\"\"\"\n\nimport torch\nfrom sgl_kernel.flash_mla import flash_mla_sparse_fwd\n\nTP = 4 # capture: --tp-size 4\n\n\ndef prepare(Q, KV, indices, topk_length, attn_sink, sm_scale):\n heads = Q.shape[1] // TP\n q_padded = torch.zeros_like(Q)\n sink = torch.zeros_like(attn_sink)\n\n def launch():\n out = []\n for rank in range(TP):\n local = slice(rank * heads, (rank + 1) * heads)\n q_padded[:, :heads] = Q[:, local]\n sink[:heads] = attn_sink[local]\n o, _, _ = flash_mla_sparse_fwd(\n q=q_padded,\n kv=KV,\n indices=indices,\n sm_scale=float(sm_scale),\n d_v=Q.shape[-1],\n attn_sink=sink,\n topk_length=topk_length,\n )\n out.append(o[:, :heads])\n return torch.cat(out, 1)\n\n return launch\n\n\ndef run(Q, KV, indices, topk_length, attn_sink, sm_scale):\n return prepare(Q, KV, indices, topk_length, attn_sink, sm_scale)()\n" + } + ] +} diff --git a/workloads/dense_attention/noncausal_dense_attention_h32_d128.jsonl b/workloads/dense_attention/noncausal_dense_attention_h32_d128.jsonl index f6e06e2ad6e9dff5131a381f5a2f12857e470852..f04c34faf4bb792021fee725f1dec8c04b0d022d 100644 --- a/workloads/dense_attention/noncausal_dense_attention_h32_d128.jsonl +++ b/workloads/dense_attention/noncausal_dense_attention_h32_d128.jsonl @@ -1,54 +1,54 @@ -{"definition": "noncausal_dense_attention_h32_d128", "workload": {"axes": {"B": 1, "Nk": 2352, "Nq": 2352}, "inputs": {"K": {"path": "blob/workloads/noncausal_dense_attention_h32_d128/2194b3ea3a2317a736f4819d874cf30d964a71b814ef0137f92ba9094eabdb1b.safetensors", "tensor_key": "tensor", "type": "safetensors"}, "Q": {"path": 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