diff --git a/README.md b/README.md
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--- a/README.md
+++ b/README.md
@@ -13,9 +13,9 @@ tags:
 
 Every published tensor input references a complete `safetensors` snapshot. Python scalar arguments use scalar descriptors. There are no random-input descriptors or synthetic activation generators. `captures.jsonl` joins each workload UUID to its model revision, request, engine operation, input adaptations, actual outputs, and validation results.
 
-**1,104 real workloads cover all 21 definitions:** 133 Qwen Image, 384 Qwen Flash-Next, 226 DeepSeek, 207 LTX, and 154 Qwen3-Next from the MLSys 2026 contest. The 950 SGLang captures pass complete-output replay; the contest publishes no engine outputs, so its workloads are checked by running the reference. The complete dataset is published at [humanfia-lab/inference-kernels](https://huggingface.co/datasets/humanfia-lab/inference-kernels), including definitions, workloads, capture records, baseline solutions, and tensors. The 5,506 tensor paths contain 5,124 unique snapshots of inputs, complete engine outputs, and auxiliary capture tensors. Fetch them with Git LFS before running workloads.
+**1,104 real workloads cover all 21 definitions:** 133 Qwen Image, 384 Qwen Flash-Next, 226 DeepSeek, 207 LTX, and 154 Qwen3-Next from the MLSys 2026 contest. The 950 SGLang captures pass complete-output replay; the contest publishes no engine outputs, so its workloads are checked by running the reference. The complete dataset is published at [humanfia-lab/inference-kernels](https://huggingface.co/datasets/humanfia-lab/inference-kernels), including definitions, workloads, capture records, baseline solutions, and tensors. The 5,493 tensor paths contain 5,111 unique snapshots of inputs, complete engine outputs, and auxiliary capture tensors. Fetch them with Git LFS before running workloads.
 
-The dataset was regenerated from full pinned checkpoints through SGLang on NVIDIA B300 GPUs. Definitions, reference code, tolerances, and baseline solutions are unchanged, apart from the [curation](#curation) for kernels that real inference uses.
+The dataset was regenerated from full pinned checkpoints through SGLang on NVIDIA B300 GPUs. The [interface and implementation audit](docs/interface-audit/README.md) records all 21 call boundaries, the feasible interface simplifications, current implementation updates, validation evidence and remaining integration work. This audit does not change task tolerances, dev UUIDs or input tensor values.
 
 ## Kernels
 
@@ -39,7 +39,7 @@ BF16, FP16, FP32, and FP64 mean 16-bit Brain Floating Point, IEEE half precision
 
 Definitions describe complete logical operators. Captures preserve all model heads and experts; distributed shards must be gathered before publication. Backend padding, layout changes, and page remapping are recorded explicitly. Cache snapshots retain every referenced page, including its unused tail; unreachable allocator pages are omitted. Tensor strides are normalized to contiguous storage without changing values.
 
-The gated delta definitions are the MLSys 2026 contest's: Q/K/V with the gate inputs `A_log`, `a`, `dt_bias` and `b`, and the k-last state layout `[sequence, value head, value dimension, key dimension]`. Prefill takes variable-length sequences through `cu_seqlens`. These are unchanged Qwen3-Next TP=4 contest contracts, not a layout conversion of the removed Qwen Flash-Next captures. Their references do not perform Q/K L2 normalization, and they accept per-batch states rather than the original SGLang state pool and slot indices.
+The gated delta definitions are the MLSys 2026 contest's: Q/K/V with the gate inputs `A_log`, `a`, `dt_bias` and `b`, and the k-last state layout `[sequence, value head, value dimension, key dimension]`. Prefill takes variable-length sequences through `cu_seqlens`. These are unchanged Qwen3-Next TP=4 contest contracts, not a layout conversion of the removed Qwen Flash-Next captures. Their references do not perform Q/K L2 normalization. Decode accepts per-batch states rather than the mutable SGLang state pool and slot indices. The actual SGLang FlashInfer prefill leaf already accepts gathered per-batch states, but uses normalized Q/K, precomputed gates, preallocated outputs and optional checkpoints. See the [per-definition audit](docs/interface-audit/interfaces.json).
 
 Quantized byte carriers use `int8` because the trace schema lacks unsigned-byte and exponent-only scale types. The byte patterns remain unchanged. Grouped matrix multiplication uses logical scale layouts with one scale per 32 K elements. Mixed attention preserves the engine's physical pages: each page stores all payload rows followed by all scale rows. Both cache formats share the softmax denominator, including the zero-value attention sink.
 
@@ -100,21 +100,22 @@ Each is submitted with 1, 2, and 4 requested outputs, at 24 frames per second. M
 
 `solutions/` contains native FlashInfer Trace Solution JSON files, with embedded source code, entry points, and pinned dependencies. Each solution accepts the definition's complete inputs and returns its complete outputs. GPU layout conversions, padding, sparse gathers, and output reordering are included in the solution call.
 
-The existing baseline implementations and B200 measurements come from the original 768-workload dataset. They are retained unchanged. The regenerated dataset's SGLang captures have passed complete engine-output replay against the independent references; baseline solutions have not been rebenchmarked on this new dataset.
+Historical B200 measurements below describe the original 768-workload dataset. Current B300 validation and comparisons are reported separately in the [audit](docs/interface-audit/README.md). Version currency alone does not establish a fastest implementation, and a standalone pass does not prove direct engine integration.
 
 | Kernels | Open-source implementation |
 |---|---|
-| Dense and grouped matrix multiplication | [DeepGEMM](https://github.com/deepseek-ai/DeepGEMM/tree/1fc9c66975ee322d628b3288534ca0e9ce12a64d); selected small dense shapes use [FlashInfer](https://github.com/flashinfer-ai/flashinfer) 0.7.2 CuTe DSL |
+| Dense and grouped matrix multiplication | [DeepGEMM](https://github.com/deepseek-ai/DeepGEMM/tree/1fc9c66975ee322d628b3288534ca0e9ce12a64d); native PyTorch linear is selected on three measured large-M B300 shapes |
 | Sparse MLA prefill and mixed-format MLA decode | [FlashMLA](https://github.com/deepseek-ai/FlashMLA/tree/0f11e178da1f67becb087a324b400854931ec3e3) |
-| Dense, block-causal, and sparse grouped-query attention | [FlashAttention-4](https://github.com/Dao-AILab/flash-attention) 4.0.0b35, with runtime masks or sparse-input adapters |
-| Gated delta recurrence | The MLSys 2026 contest's FlashInfer prefill and decode wrappers, unchanged |
-| Sparse index scoring and selection | SGLang TileLang scoring, exact-threshold Top-512, and Triton compaction that preserves lower-ID ties |
-| Expert router | FlashInfer CUTLASS FP32-output projection and compiled PyTorch scoring/selection |
+| Dense and block-causal attention | [FlashAttention-4](https://github.com/Dao-AILab/flash-attention) 4.0.0b35; tiny audio self-attention uses native SDPA |
+| Sparse grouped-query attention | Current SGLang/FlashInfer TRT-LLM paged attention, plus the FA4 sparse-gather alternative |
+| Gated delta recurrence | Maintained FlashInfer prefill/decode APIs; the contest recurrence, normalization boundary and state output contract remain explicit |
+| Sparse index scoring and selection | Maintained SGLang TileLang scoring, exact-threshold Top-512, stable Triton compaction, and a score-free short-context path |
+| Expert router | SGLang FP32-output projection and fused modality-aware Top-6 gate, with a combined Triton output ordering kernel |
 | Three-dimensional neighborhood attention | [NATTEN](https://github.com/SHI-Labs/NATTEN/tree/39375ea1d2f3b1bb284315fa5f79f6ecbebb6382) 0.21.7 Blackwell fused neighborhood attention |
 
-Local B200 comparisons covered 45 dense GEMM shapes across 147 backend/shape pairs, nine grouped GEMM shapes with five implementations/configurations each, and all 19 sparse-index workloads. Dense dispatch selects the fastest tested backend per captured shape; DeepGEMM won all nine grouped comparisons. The index adapter was 1.21–2.58× faster than full stable sorting while returning exactly the same IDs. These measurements describe the tested B200 configurations.
+Historical B200 comparisons covered 45 dense GEMM shapes across 147 backend/shape pairs, nine grouped GEMM shapes with five implementations/configurations each, and all 19 sparse-index workloads. Dense dispatch selects the fastest tested backend per captured shape; DeepGEMM won all nine grouped comparisons. The index adapter was 1.21–2.58× faster than full stable sorting while returning exactly the same IDs. These measurements describe the tested B200 configurations.
 
-The audio-attention solution uses FP16 computation and converts the output back to BF16 to reduce attention-probability rounding error. In the original B200 validation, all 96 audio workloads passed the unchanged reference tolerances, and their inputs remained finite after conversion with maximum conversion error below `3e-8`. These measurements refer to the original tensors.
+The current audio-attention solution uses BF16 FA4 directly, with native SDPA for self-attention tiles of at most 64 tokens. Both alternatives pass all 108 current audio workloads under the existing `required_matched_ratio=0.9999` policy. The former FP16 input/output conversions are removed; no tolerance was relaxed. Historical all-element B200 validation used different input tensors and the former FP16 computation.
 
 Install the dependencies listed in each solution's `spec` before running it. The historical B200 baseline environment used PyTorch 2.11.0, CUDA 13.2, Triton 3.6.0, CUTLASS DSL 4.7.1, Quack 0.6.5, TileLang 0.1.15, and TVM FFI 0.1.12. NATTEN and FlashMLA were built from their pinned sources for Blackwell. FlashMLA's CUDA 13.2 build required its upstream `FLASH_MLA_SKIP_REG_SPILL_CHECK=1` option; timings include that build.
 
@@ -128,13 +129,15 @@ The runner uses the native Trace builder, validates every output element against
 
 ### SGLang baselines
 
-Each SGLang-captured definition also has `solutions/<family>/sglang_<definition>.json`: SGLang's own implementation at the capture commit `684fea8a`, called the way the engine calls it, so that a kernel can be timed against what serving actually runs. The module docstring cites the engine call path. Run these solutions inside the capture image `lmsysorg/sglang@sha256:ddae0e399d3d94f7827f16183301cf8dac4cf0eae0ef25590b7dac5881d713d8`. Each module also exposes `prepare(*inputs)`, which does the host-side setup the engine does once (layouts, block masks, workspaces) and returns a zero-argument `launch`; `run(*inputs)` does both.
+Each SGLang-captured definition also has `solutions/<family>/sglang_<definition>.json`: the capture-commit SGLang implementation behind an explicit dataset-to-engine adapter. These provide a serving implementation comparison, not a declaration that the dataset already has every native interface. The module docstring cites the engine call path. Run these solutions inside the capture image `lmsysorg/sglang@sha256:ddae0e399d3d94f7827f16183301cf8dac4cf0eae0ef25590b7dac5881d713d8`. Each module also exposes `prepare(*inputs)`, which does the host-side setup the engine does once (layouts, block masks, workspaces) and returns a zero-argument `launch`; `run(*inputs)` does both.
 
 The SGLang solutions adapt the dataset's independent operator interfaces to the pinned engine implementations. Those adapters include padding, layouts, per-rank calls, metadata and output ordering where needed; their module docstrings describe the boundary. A passing standalone workload does not establish that a candidate can replace an engine call without integration work.
 
+The [audit runner](scripts/audit_solutions.py) can validate the complete packaged call, check byte-level input immutability, and compare eager and prepared-launch CUDA Graph timing under the task's exact tolerance. `scripts/benchmark_solutions.py` also reads `tasks/` for acceptance instead of applying a generic FP32 fallback.
+
 ### Task acceptance configs
 
-`tasks/<definition>.json` is how KDA (Kernel Design Agents) judges a candidate kernel on that definition. The definition's reference is the truth. SGLang tasks time their engine baseline with only `launch` timed; imported GDN tasks time the complete packaged contest baseline call. The fields are:
+`tasks/<definition>.json` is how KDA (Kernel Design Agents) judges a candidate kernel on that definition. The definition's reference is the truth. SGLang tasks time their engine baseline with only `launch` timed; imported GDN tasks time the complete maintained FlashInfer baseline call. The fields are:
 - `tolerance`: `atol` and `rtol` apply per element. A non-null `required_matched_ratio` is the fraction of elements that must pass; the LTX dense attention uses 0.9999 because fused attention kernels round the probabilities to BF16 and miss the every-element bound on 1–3 of up to 10⁹ elements.
 - `dev`: UUIDs selecting at most ten existing workloads for quick iteration. These UUIDs resolve in the listed workload files; they are not additional workloads. Final judgments use every workload, not just this subset.
 - `tolerance.comparison`: absent means `abs_error <= atol + rtol * abs(reference)`. The GDN configs explicitly use `absolute_or_relative`, matching the pinned FlashInfer-Bench evaluator: `abs_error <= atol` or `abs_error / (abs(reference) + 1e-8) <= rtol`. Nonfinite values fail.
@@ -147,7 +150,7 @@ A task config selects the definition, workload files, timed baseline and accepta
 This revision curates inference operator tasks for KDA (Kernel Design Agents). Per-shape definitions, workload files and solution names stay separate; model dimensions remain constant axes. Captured interface adaptations are retained explicitly.
 - **Removed `dense_gemm_bf16_nt_n64_k4096` and `dense_gemm_bf16_nt_n4096_k64`.** These are the image output and input projections: memory-bound 8–45 µs GEMMs that run once per forward.
 - **Removed `grouped_gemm_fp8_fp4_e384_n2304_k5120_g32`.** It was cut from the columns of the concatenated gate/up GEMM; no engine runs a separate gate or up GEMM.
-- **Replaced the gated delta definitions.** `gated_delta_rule_prefill_h48_dk128_dv128` pre-repeated 16 Q/K heads to 48; the old decode kept 16 raw Q/K heads and included normalization and gating. Both captures extracted states from the engine pool and transposed them to `[B, H, K, V]`. They are replaced by the [MLSys 2026 FlashInfer contest](https://huggingface.co/datasets/flashinfer-ai/mlsys26-contest/tree/5e832ce88dd1013032b22a0e942979d7d2769cc3) definitions `gdn_{decode,prefill}_qk4_v8_d128_k_last`, with their workloads and FlashInfer baselines unchanged. Each input tensor is stored in its own content-addressed file. Each receipt records the source workload, plus a check that the reference returns finite outputs of the declared shapes.
+- **Replaced the gated delta definitions.** `gated_delta_rule_prefill_h48_dk128_dv128` pre-repeated 16 Q/K heads to 48; the old decode kept 16 raw Q/K heads and included normalization and gating. Both captures extracted states from the engine pool and transposed them to `[B, H, K, V]`. They are replaced by the [MLSys 2026 FlashInfer contest](https://huggingface.co/datasets/flashinfer-ai/mlsys26-contest/tree/5e832ce88dd1013032b22a0e942979d7d2769cc3) definitions `gdn_{decode,prefill}_qk4_v8_d128_k_last`, with their workloads and independent references preserved. The audit subsequently replaces the legacy vendored wrappers with maintained FlashInfer API calls. Each input tensor is stored in its own content-addressed file. Each receipt records the source workload, plus a check that the reference returns finite outputs of the declared shapes.
 - **The three remaining dense GEMMs keep only their `M >= 4096` rows.** The `M <= 32` rows were 11–27 µs launches.
 - **The LTX dense attention definitions drop the dense `[B, H, Nq, Nk]` visibility mask.** It was all True on every captured call (up to 839 MB). On one GPU the engine passes no mask, or an all-visible prompt mask. Replay against the captured engine outputs still passes.
 - **Receipts and tensors.** The receipts of removed workloads are dropped, along with every tensor that nothing references.
@@ -232,7 +235,7 @@ BF16 comparisons use `rtol=0.016, atol=0.005`; FP32 uses `rtol=1e-4, atol=2e-5`;
 
 One complete router workload is excluded from the 279 DeepSeek raw captures: at two rows of a 4,096-row call, FP32 ranking ties produce different expert selections. The original FP32 reference and exact selected-set requirement remain unchanged. This call was also absent from the original dataset. No rows are removed from published tensors. All nine LTX requests pass and are included.
 
-Tensor files are published directly as `blob/workloads/<definition>/<hash>.safetensors` through Git LFS. Every workload and capture record references tensors under its definition directory. Shared snapshots have identical LFS objects across directories: 5,506 paths contain 5,124 unique snapshots totaling 146.34 GB (146.44 GB when materialized at every path).
+Tensor files are published directly as `blob/workloads/<definition>/<hash>.safetensors` through Git LFS. Every workload and capture record references tensors under its definition directory. Shared snapshots have identical LFS objects across directories: 5,493 paths contain 5,111 unique snapshots totaling 146.34 GB (146.44 GB when materialized at every path).
 
 ```bash
 git clone https://huggingface.co/datasets/humanfia-lab/inference-kernels
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 {"actual_attention_batch": 4, "adapter": "Capture the complete grid after normalization, query scaling and RoPE, before output projection.", "audio_precision_adapter": "Select PyTorch math SDPA for every dimension-64 transformer attention call; keep BF16 inputs/outputs and FP32 intermediates; normalize output storage to the engine's sequence-major flattening contract.", "audio_sdpa_backend": "math", "axes": {"B": 4, "T": 18, "X": 32, "Y": 20}, "capture_steps": [0, 4, 7], "conversion": {"conv_vae_distribution": "comfyicu/LTX-2.5", "conv_vae_revision": "1026e00f808dbd9601911479b22d65b760737dc8", "converter_revision": "efe46a5b177af67c64b3666da8ddddac7ee12163", "original_model": "Lightricks/LTX-2.5", "original_revision": "49b093a39c19169a8a81721dcc541e07e945232f", "public_distribution": "pinecoresystems/LTX-2.5-serving", "revision": "93deb76408feee57d04b3cfeed3ded56a7a068ee", "source_sha256": {"diffusion_models/ltx-2.5-22b-distilled-transformer-bf16.safetensors": "31eb3cad89b9e54e99dd3baf286f70825ac4f6c660a70d9184d895be76d7bff4", "text_encoders/gemma4-12b-with-proj-ltx-2.5-bf16.safetensors": "ef7243612fdae7a75cb4d5cee9433e81380675fb6c213bd98ae74a9cd16561d1", "vae/ltx-2.5-audio-vae-bf16.safetensors": "c52733d37f6a7fb7949c3dc0fb468c6cb2169e4d836983a73babb9f0d54837a5", "vae/ltx-2.5-video-vae-bf16.safetensors": "847e14ca7f3355debca0cea4eaa24ac0fbcdf0061da054ac89ca638a869ddba3", "vae/ltx-2.5-video-vae-conv-bf16.safetensors": "685b06ee3d9b2039647698fc4ea33175112462fc374e2777312c907897dfce8d"}, "text_encoder_adapter": "Lossless parameter-name mapping, including vision/audio embeddings and tied LM head.", "validation": "Every component loaded with strict=True; all source file SHA256 values verified."}, "decoder_adapter": "Retain the original optional keyframe tag; use the complete ordinary-video decoder path.", "definition": "neighborhood_attention_3d_h16_d64_kt3_ky7_kx7", "engine": "SGLang", "engine_version": "0.0.0.dev1+g684fea8af", "expected_output": {"path": "blob/workloads/neighborhood_attention_3d_h16_d64_kt3_ky7_kx7/af373e4f2d1695d315be0b58e993105ee1624be85e6a284e893fd116b9e9e8df.safetensors", "tensor_key": "tensor", "type": "safetensors"}, "model": "Lightricks/LTX-2.5", "model_revision": "49b093a39c19169a8a81721dcc541e07e945232f", "module_path": "diffusion_decoder.attention_h16_3x7x7", "operation": "LTX2VideoVaeNeighborhoodAttention", "request": {"enhance_prompt": false, "extra_body": {"use_diffusion_decoder": true}, "fps": 24, "guidance_scale": 1.0, "num_frames": 121, "num_inference_steps": 8, "num_outputs_per_prompt": 4, "prompt": "A small wooden boat crosses a calm lake at sunrise. The camera follows smoothly as ripples spread behind the boat. Birds call softly from the shore.", "seed": 42, "size": "512x320"}, "request_id": "ltx25_long_video_batch4", "requested_outputs": 4, "sampling_sigmas": [1, 0.99375, 0.9875, 0.98125, 0.975, 0.909375, 0.725, 0.421875], "server_command": ["sglang", "serve", "--model-path", "/task/models/ltx25", "--model-id", "LTX-2.5-Diffusers", "--host", "127.0.0.1", "--port", "30400", "--performance-mode", "speed", "--scheduler-port", "30420", "--master-port", "30421", "--attention-backend", "torch_sdpa", "--enable-torch-compile", "false", "--enable-breakable-cuda-graph", "false", "--warmup-mode", "off", "--load-diffusion-decoder", "true", "--vae-tiling", "false", "--vae-sp", "false", "--input-save-path", "/task/raw/ltx-b4-r4/results/inputs", "--diffusion-decoder-tiling", "false", "--output-path", "/task/raw/ltx-b4-r4/results/videos"], "source": "https://github.com/sgl-project/sglang/tree/684fea8a/python/sglang/multimodal_gen", "started_at": 1792242401.3913639, "step": 0, "uuid": "e8f46b73-bd40-55e5-96d0-32dc0199b4f1", "validation": {"axes": {"B": 4, "T": 18, "X": 32, "Y": 20}, "definition": "neighborhood_attention_3d_h16_d64_kt3_ky7_kx7", "device": "cuda", "max_absolute_errors": [0.0009765625], "seconds": 0.2318596919067204, "status": "passed", "tolerances": {"bfloat16": {"atol": 0.005, "rtol": 0.016}, "float32": {"atol": 2e-05, "rtol": 0.0001}, "gdn_prefill_state": {"max_head_relative_rms": 0.02, "reason": "The engine's chunk algorithm rounds intermediate matrix operands to BF16 although its final state is stored in FP32.", "relative_max": 0.015, "relative_rms": 0.01}, "integer": "exact"}, "torch": "2.14.1+cu130", "uuid": "e8f46b73-bd40-55e5-96d0-32dc0199b4f1"}, "variant": "grid_18x20x32", "video_precision_adapter": "Select PyTorch math SDPA for every dimension-128 transformer attention call; keep BF16 inputs/outputs and FP32 intermediates; normalize output storage to the engine's sequence-major flattening contract.", "video_sdpa_backend": "math"}
 {"actual_attention_batch": 4, "adapter": "Capture the complete grid after normalization, query scaling and RoPE, before output projection.", "audio_precision_adapter": "Select PyTorch math SDPA for every dimension-64 transformer attention call; keep BF16 inputs/outputs and FP32 intermediates; normalize output storage to the engine's sequence-major flattening contract.", "audio_sdpa_backend": "math", "axes": {"B": 4, "T": 35, "X": 32, "Y": 20}, "capture_steps": [0, 4, 7], "conversion": {"conv_vae_distribution": "comfyicu/LTX-2.5", "conv_vae_revision": "1026e00f808dbd9601911479b22d65b760737dc8", "converter_revision": "efe46a5b177af67c64b3666da8ddddac7ee12163", "original_model": "Lightricks/LTX-2.5", "original_revision": "49b093a39c19169a8a81721dcc541e07e945232f", "public_distribution": "pinecoresystems/LTX-2.5-serving", "revision": "93deb76408feee57d04b3cfeed3ded56a7a068ee", "source_sha256": {"diffusion_models/ltx-2.5-22b-distilled-transformer-bf16.safetensors": "31eb3cad89b9e54e99dd3baf286f70825ac4f6c660a70d9184d895be76d7bff4", "text_encoders/gemma4-12b-with-proj-ltx-2.5-bf16.safetensors": "ef7243612fdae7a75cb4d5cee9433e81380675fb6c213bd98ae74a9cd16561d1", "vae/ltx-2.5-audio-vae-bf16.safetensors": "c52733d37f6a7fb7949c3dc0fb468c6cb2169e4d836983a73babb9f0d54837a5", "vae/ltx-2.5-video-vae-bf16.safetensors": "847e14ca7f3355debca0cea4eaa24ac0fbcdf0061da054ac89ca638a869ddba3", "vae/ltx-2.5-video-vae-conv-bf16.safetensors": "685b06ee3d9b2039647698fc4ea33175112462fc374e2777312c907897dfce8d"}, "text_encoder_adapter": "Lossless parameter-name mapping, including vision/audio embeddings and tied LM head.", "validation": "Every component loaded with strict=True; all source file SHA256 values verified."}, "decoder_adapter": "Retain the original optional keyframe tag; use the complete ordinary-video decoder path.", "definition": "neighborhood_attention_3d_h8_d64_kt3_ky5_kx5", "engine": "SGLang", "engine_version": "0.0.0.dev1+g684fea8af", "expected_output": {"path": "blob/workloads/neighborhood_attention_3d_h8_d64_kt3_ky5_kx5/205af6e016173fee56a83608a06e25d1799905a1e18a1f000946968143f1431b.safetensors", "tensor_key": "tensor", "type": "safetensors"}, "model": "Lightricks/LTX-2.5", "model_revision": "49b093a39c19169a8a81721dcc541e07e945232f", "module_path": "diffusion_decoder.attention_h8_3x5x5", "operation": "LTX2VideoVaeNeighborhoodAttention", "request": {"enhance_prompt": false, "extra_body": {"use_diffusion_decoder": true}, "fps": 24, "guidance_scale": 1.0, "num_frames": 121, "num_inference_steps": 8, "num_outputs_per_prompt": 4, "prompt": "A small wooden boat crosses a calm lake at sunrise. The camera follows smoothly as ripples spread behind the boat. Birds call softly from the shore.", "seed": 42, "size": "512x320"}, "request_id": "ltx25_long_video_batch4", "requested_outputs": 4, "sampling_sigmas": [1, 0.99375, 0.9875, 0.98125, 0.975, 0.909375, 0.725, 0.421875], "server_command": ["sglang", "serve", "--model-path", "/task/models/ltx25", "--model-id", "LTX-2.5-Diffusers", "--host", "127.0.0.1", "--port", "30400", "--performance-mode", "speed", "--scheduler-port", "30420", "--master-port", "30421", "--attention-backend", "torch_sdpa", "--enable-torch-compile", "false", "--enable-breakable-cuda-graph", "false", "--warmup-mode", "off", "--load-diffusion-decoder", "true", "--vae-tiling", "false", "--vae-sp", "false", "--input-save-path", "/task/raw/ltx-b4-r4/results/inputs", "--diffusion-decoder-tiling", "false", "--output-path", "/task/raw/ltx-b4-r4/results/videos"], "source": "https://github.com/sgl-project/sglang/tree/684fea8a/python/sglang/multimodal_gen", "started_at": 1792242401.3913639, "step": 0, "uuid": "9866c54d-a157-5fdd-89d1-84af0fb714e6", "validation": {"axes": {"B": 4, "T": 35, "X": 32, "Y": 20}, "definition": "neighborhood_attention_3d_h8_d64_kt3_ky5_kx5", "device": "cuda", "max_absolute_errors": [0.0009765625], "seconds": 0.2929818043485284, "status": "passed", "tolerances": {"bfloat16": {"atol": 0.005, "rtol": 0.016}, "float32": {"atol": 2e-05, "rtol": 0.0001}, "gdn_prefill_state": {"max_head_relative_rms": 0.02, "reason": "The engine's chunk algorithm rounds intermediate matrix operands to BF16 although its final state is stored in FP32.", "relative_max": 0.015, "relative_rms": 0.01}, "integer": "exact"}, "torch": "2.14.1+cu130", "uuid": "9866c54d-a157-5fdd-89d1-84af0fb714e6"}, "variant": "grid_35x20x32", "video_precision_adapter": "Select PyTorch math SDPA for every dimension-128 transformer attention call; keep BF16 inputs/outputs and FP32 intermediates; normalize output storage to the engine's sequence-major flattening contract.", "video_sdpa_backend": "math"}
diff --git a/definitions/block_causal_attention/prefix_cached_block_causal_h32_d128.json b/definitions/block_causal_attention/prefix_cached_block_causal_h32_d128.json
index b9b37a8e4d6dcc5853bff45e2cbb912ec523f8b5..c759084fbcbb2f5cc0da3c93b06d2cbbf0b3e84c 100644
--- a/definitions/block_causal_attention/prefix_cached_block_causal_h32_d128.json
+++ b/definitions/block_causal_attention/prefix_cached_block_causal_h32_d128.json
@@ -1,7 +1,7 @@
 {
   "name": "prefix_cached_block_causal_h32_d128",
   "op_type": "block_causal_attention",
-  "description": "Prefix-cached block-causal attention: allow j <= Np+i or matching nonnegative image IDs, then intersect key_valid. Text and different image blocks are causal; same-image tokens are bidirectional. Np=0 covers initial full evaluation. Prefix K/V are already computed; changed target-image K/V must be supplied as current inputs.",
+  "description": "SGLang Qwen-Image target-image attention with a nonempty replicated KV prefix. All current queries belong to one image block and attend to every prefix/current key. Q/K/V keep the engine layout; scale is fixed to 1/sqrt(128).",
   "tags": [
     "model:qwen-image-2.1-turbo",
     "status:draft",
@@ -18,11 +18,7 @@
     },
     "Np": {
       "type": "var",
-      "description": "Runtime cached prefix length, possibly zero."
-    },
-    "Nall": {
-      "type": "var",
-      "description": "Total prefix and current length."
+      "description": "Runtime nonempty cached prefix length."
     },
     "H": {
       "type": "const",
@@ -43,61 +39,41 @@
       ],
       "dtype": "bfloat16"
     },
-    "K_current": {
+    "K_prefix": {
       "shape": [
         "B",
-        "Nq",
+        "Np",
         "H",
         "D"
       ],
       "dtype": "bfloat16"
     },
-    "V_current": {
+    "V_prefix": {
       "shape": [
         "B",
-        "Nq",
+        "Np",
         "H",
         "D"
       ],
       "dtype": "bfloat16"
     },
-    "K_prefix": {
+    "K_current": {
       "shape": [
         "B",
-        "Np",
+        "Nq",
         "H",
         "D"
       ],
       "dtype": "bfloat16"
     },
-    "V_prefix": {
+    "V_current": {
       "shape": [
         "B",
-        "Np",
+        "Nq",
         "H",
         "D"
       ],
       "dtype": "bfloat16"
-    },
-    "image_ids": {
-      "shape": [
-        "Nall"
-      ],
-      "dtype": "int32",
-      "description": "Text=-1; nonnegative IDs identify distinct contiguous image blocks. Shared batch layout."
-    },
-    "key_valid": {
-      "shape": [
-        "B",
-        "Nall"
-      ],
-      "dtype": "bool",
-      "description": "Key padding visibility mask; each query must see a key."
-    },
-    "sm_scale": {
-      "shape": null,
-      "dtype": "float32",
-      "description": "Model default 1/sqrt(128)."
     }
   },
   "outputs": {
@@ -114,8 +90,7 @@
   "constraints": [
     "B >= 1",
     "Nq >= 1",
-    "Np >= 0",
-    "Nall == Np + Nq"
+    "Np >= 1"
   ],
-  "reference": "import math\nimport torch\n\n@torch.no_grad()\ndef run(Q, K_current, V_current, K_prefix, V_prefix, image_ids, key_valid, sm_scale):\n    \"\"\"Causal across blocks/text, bidirectional within each nonnegative image ID.\"\"\"\n    nprefix, nquery = K_prefix.shape[1], Q.shape[1]\n    keys = torch.cat((K_prefix, K_current), dim=1).float()\n    values = torch.cat((V_prefix, V_current), dim=1).float()\n    positions = torch.arange(keys.shape[1], device=Q.device)\n    query_positions = positions[nprefix:]\n    query_images = image_ids[nprefix:]\n    same_image = (query_images[:, None] == image_ids[None, :]) & (query_images[:, None] >= 0)\n    allowed = (positions[None, :] <= query_positions[:, None]) | same_image\n    allowed = allowed[None, :, :] & key_valid[:, None, :]\n    assert bool(allowed.any(dim=-1).all()), \"Each query needs a visible key\"\n    scores = torch.einsum(\"bqhd,bkhd->bhqk\", Q.float(), keys) * float(sm_scale)\n    scores = scores.masked_fill(~allowed[:, None], -torch.inf)\n    return torch.einsum(\"bhqk,bkhd->bqhd\", scores.softmax(-1), values).to(torch.bfloat16)\n"
+  "reference": "import torch\n\n@torch.no_grad()\ndef run(Q, K_prefix, V_prefix, K_current, V_current):\n    \"\"\"One SGLang target-image attention call; the current image sees every key.\"\"\"\n    keys = torch.cat((K_prefix, K_current), dim=1).float()\n    values = torch.cat((V_prefix, V_current), dim=1).float()\n    scores = torch.einsum(\"bqhd,bkhd->bhqk\", Q.float(), keys) * (128 ** -0.5)\n    return torch.einsum(\"bhqk,bkhd->bqhd\", scores.softmax(-1), values).to(torch.bfloat16)\n"
 }
diff --git a/definitions/block_causal_attention/prefix_cached_block_causal_h32_d128_prefix0.json b/definitions/block_causal_attention/prefix_cached_block_causal_h32_d128_prefix0.json
index 06f1f654915b32dfb810a30d3e4900aaf6b24b06..379c2eda49fddaa566bec3d364b865744a8371ec 100644
--- a/definitions/block_causal_attention/prefix_cached_block_causal_h32_d128_prefix0.json
+++ b/definitions/block_causal_attention/prefix_cached_block_causal_h32_d128_prefix0.json
@@ -1,7 +1,7 @@
 {
   "name": "prefix_cached_block_causal_h32_d128_prefix0",
   "op_type": "block_causal_attention",
-  "description": "Prefix-cached block-causal attention: allow j <= Np+i or matching nonnegative image IDs, then intersect key_valid. Text and different image blocks are causal; same-image tokens are bidirectional. Np=0 covers initial full evaluation. Prefix K/V are already computed; changed target-image K/V must be supplied as current inputs. Empty-prefix specialization: Np is a constant zero.",
+  "description": "Prefix-cached block-causal attention: allow j <= Np+i or matching nonnegative image IDs, then intersect key_valid. Text and different image blocks are causal; same-image tokens are bidirectional. Np=0 covers initial full evaluation. Prefix K/V are already computed; changed target-image K/V must be supplied as current inputs. Empty-prefix specialization: Np is a constant zero. Empty prefix tensors, the all-visible key-valid input and the fixed scale are omitted. image_ids still represents the engine segment list, so this remains a composed operator contract.",
   "tags": [
     "model:qwen-image-2.1-turbo",
     "status:draft",
@@ -16,14 +16,6 @@
       "type": "var",
       "description": "Runtime current query/token count."
     },
-    "Np": {
-      "type": "const",
-      "value": 0
-    },
-    "Nall": {
-      "type": "var",
-      "description": "Total prefix and current length."
-    },
     "H": {
       "type": "const",
       "value": 32
@@ -61,43 +53,12 @@
       ],
       "dtype": "bfloat16"
     },
-    "K_prefix": {
-      "shape": [
-        "B",
-        "Np",
-        "H",
-        "D"
-      ],
-      "dtype": "bfloat16"
-    },
-    "V_prefix": {
-      "shape": [
-        "B",
-        "Np",
-        "H",
-        "D"
-      ],
-      "dtype": "bfloat16"
-    },
     "image_ids": {
       "shape": [
-        "Nall"
+        "Nq"
       ],
       "dtype": "int32",
       "description": "Text=-1; nonnegative IDs identify distinct contiguous image blocks. Shared batch layout."
-    },
-    "key_valid": {
-      "shape": [
-        "B",
-        "Nall"
-      ],
-      "dtype": "bool",
-      "description": "Key padding visibility mask; each query must see a key."
-    },
-    "sm_scale": {
-      "shape": null,
-      "dtype": "float32",
-      "description": "Model default 1/sqrt(128)."
     }
   },
   "outputs": {
@@ -113,8 +74,7 @@
   },
   "constraints": [
     "B >= 1",
-    "Nq >= 1",
-    "Nall == Nq"
+    "Nq >= 1"
   ],
-  "reference": "import math\nimport torch\n\n@torch.no_grad()\ndef run(Q, K_current, V_current, K_prefix, V_prefix, image_ids, key_valid, sm_scale):\n    \"\"\"Causal across blocks/text, bidirectional within each nonnegative image ID.\"\"\"\n    nprefix, nquery = K_prefix.shape[1], Q.shape[1]\n    keys = torch.cat((K_prefix, K_current), dim=1).float()\n    values = torch.cat((V_prefix, V_current), dim=1).float()\n    positions = torch.arange(keys.shape[1], device=Q.device)\n    query_positions = positions[nprefix:]\n    query_images = image_ids[nprefix:]\n    same_image = (query_images[:, None] == image_ids[None, :]) & (query_images[:, None] >= 0)\n    allowed = (positions[None, :] <= query_positions[:, None]) | same_image\n    allowed = allowed[None, :, :] & key_valid[:, None, :]\n    assert bool(allowed.any(dim=-1).all()), \"Each query needs a visible key\"\n    scores = torch.einsum(\"bqhd,bkhd->bhqk\", Q.float(), keys) * float(sm_scale)\n    scores = scores.masked_fill(~allowed[:, None], -torch.inf)\n    return torch.einsum(\"bhqk,bkhd->bqhd\", scores.softmax(-1), values).to(torch.bfloat16)\n"
+  "reference": "import torch\n\n@torch.no_grad()\ndef run(Q, K_current, V_current, image_ids):\n    \"\"\"The uncached prefix's segmented text/image visibility, without empty state inputs.\"\"\"\n    positions = torch.arange(Q.shape[1], device=Q.device)\n    same_image = (image_ids[:, None] == image_ids[None, :]) & (image_ids[:, None] >= 0)\n    allowed = (positions[None, :] <= positions[:, None]) | same_image\n    scores = torch.einsum(\"bqhd,bkhd->bhqk\", Q.float(), K_current.float()) * (128 ** -0.5)\n    scores = scores.masked_fill(~allowed[None, None], -torch.inf)\n    return torch.einsum(\"bhqk,bkhd->bqhd\", scores.softmax(-1), V_current.float()).to(torch.bfloat16)\n"
 }
diff --git a/definitions/dense_attention/noncausal_dense_attention_h32_d128.json b/definitions/dense_attention/noncausal_dense_attention_h32_d128.json
index 398bc495d5f0786239665f47530e54d4530bef38..7402c4cd873487ad87c472d1b8bc8b4cb5d37b3a 100644
--- a/definitions/dense_attention/noncausal_dense_attention_h32_d128.json
+++ b/definitions/dense_attention/noncausal_dense_attention_h32_d128.json
@@ -1,7 +1,7 @@
 {
   "name": "noncausal_dense_attention_h32_d128",
   "op_type": "dense_attention",
-  "description": "Noncausal self/cross attention with FP32 accumulation and BF16 output. Self attention uses Nq=Nk; cross attention allows unequal lengths. No dropout. Projection, normalization, rotary embeddings and output gates are outside the definition. No mask: every captured call's expanded visibility mask was all True (on one GPU the engine passes no mask, or an all-visible prompt mask), so KDA drops the dataset's mask input.",
+  "description": "Noncausal self/cross attention with FP32 accumulation and BF16 output. Self attention uses Nq=Nk; cross attention allows unequal lengths. No dropout. Projection, normalization, rotary embeddings and output gates are outside the definition. No mask: every captured call's expanded visibility mask was all True (on one GPU the engine passes no mask, or an all-visible prompt mask), so KDA drops the dataset's mask input. The SGLang call fixes scale to head_dim**-0.5; no runtime scale argument is exposed.",
   "tags": [
     "model:ltx-2.5",
     "status:draft",
@@ -56,11 +56,6 @@
         "D"
       ],
       "dtype": "bfloat16"
-    },
-    "sm_scale": {
-      "shape": null,
-      "dtype": "float32",
-      "description": "Model default 1/sqrt(128)."
     }
   },
   "outputs": {
@@ -79,5 +74,5 @@
     "Nq >= 1",
     "Nk >= 1"
   ],
-  "reference": "import math\nimport torch\n\n@torch.no_grad()\ndef run(Q, K, V, sm_scale):\n    \"\"\"Noncausal attention without a mask.\"\"\"\n    scores = torch.einsum(\"bqhd,bkhd->bhqk\", Q.float(), K.float())\n    scores = scores * float(sm_scale)\n    probabilities = torch.softmax(scores, dim=-1)\n    return torch.einsum(\"bhqk,bkhd->bqhd\", probabilities, V.float()).to(torch.bfloat16)\n"
+  "reference": "import math\nimport torch\n\n@torch.no_grad()\ndef run(Q, K, V):\n    \"\"\"Noncausal attention without a mask.\"\"\"\n    scores = torch.einsum(\"bqhd,bkhd->bhqk\", Q.float(), K.float())\n    scores = scores * (128 ** -0.5)\n    probabilities = torch.softmax(scores, dim=-1)\n    return torch.einsum(\"bhqk,bkhd->bqhd\", probabilities, V.float()).to(torch.bfloat16)\n"
 }
diff --git a/definitions/dense_attention/noncausal_dense_attention_h32_d64.json b/definitions/dense_attention/noncausal_dense_attention_h32_d64.json
index 40bf10ce999a71a4a471f5c80b764c70afadc778..052d6810e86c1ddb34c0dc1401b822691a12e4d5 100644
--- a/definitions/dense_attention/noncausal_dense_attention_h32_d64.json
+++ b/definitions/dense_attention/noncausal_dense_attention_h32_d64.json
@@ -1,7 +1,7 @@
 {
   "name": "noncausal_dense_attention_h32_d64",
   "op_type": "dense_attention",
-  "description": "Noncausal self/cross attention with FP32 accumulation and BF16 output. Self attention uses Nq=Nk; cross attention allows unequal lengths. No dropout. Projection, normalization, rotary embeddings and output gates are outside the definition. No mask: every captured call's expanded visibility mask was all True (on one GPU the engine passes no mask, or an all-visible prompt mask), so KDA drops the dataset's mask input.",
+  "description": "Noncausal self/cross attention with FP32 accumulation and BF16 output. Self attention uses Nq=Nk; cross attention allows unequal lengths. No dropout. Projection, normalization, rotary embeddings and output gates are outside the definition. No mask: every captured call's expanded visibility mask was all True (on one GPU the engine passes no mask, or an all-visible prompt mask), so KDA drops the dataset's mask input. The SGLang call fixes scale to head_dim**-0.5; no runtime scale argument is exposed.",
   "tags": [
     "model:ltx-2.5",
     "status:draft",
@@ -56,11 +56,6 @@
         "D"
       ],
       "dtype": "bfloat16"
-    },
-    "sm_scale": {
-      "shape": null,
-      "dtype": "float32",
-      "description": "Model default 1/sqrt(64)."
     }
   },
   "outputs": {
@@ -79,5 +74,5 @@
     "Nq >= 1",
     "Nk >= 1"
   ],
-  "reference": "import math\nimport torch\n\n@torch.no_grad()\ndef run(Q, K, V, sm_scale):\n    \"\"\"Noncausal attention without a mask.\"\"\"\n    scores = torch.einsum(\"bqhd,bkhd->bhqk\", Q.float(), K.float())\n    scores = scores * float(sm_scale)\n    probabilities = torch.softmax(scores, dim=-1)\n    return torch.einsum(\"bhqk,bkhd->bqhd\", probabilities, V.float()).to(torch.bfloat16)\n"
+  "reference": "import math\nimport torch\n\n@torch.no_grad()\ndef run(Q, K, V):\n    \"\"\"Noncausal attention without a mask.\"\"\"\n    scores = torch.einsum(\"bqhd,bkhd->bhqk\", Q.float(), K.float())\n    scores = scores * (64 ** -0.5)\n    probabilities = torch.softmax(scores, dim=-1)\n    return torch.einsum(\"bhqk,bkhd->bqhd\", probabilities, V.float()).to(torch.bfloat16)\n"
 }
diff --git a/docs/gdn-prefill-numerics.md b/docs/gdn-prefill-numerics.md
index 885020b8206d61b7d982a74742bb509c9c3b0abf..a76224b6a8e6f11b03e85a6502da0502066cf24b 100644
--- a/docs/gdn-prefill-numerics.md
+++ b/docs/gdn-prefill-numerics.md
@@ -1,4 +1,4 @@
-# GDN prefill numerical analysis
+# Historical GDN prefill numerical analysis
 
 The imported contest baseline returns an FP32 state but performs several state-update matrix products with BF16 intermediate operands. Returning FP32 does not make those intermediate operations FP32-accurate. The independent reference instead updates the recurrence one token at a time in FP32.
 
@@ -25,4 +25,27 @@ The earlier standalone package had no explicit GDN task configuration. It applie
 
 The [contest evaluation commands](https://github.com/flashinfer-ai/flashinfer-bench-starter-kit/blob/75ccd05cafceb0fd1f86be4cd0f2117249463c66/EVALUATION.md) do not override GDN error tolerances. The pinned [FlashInfer-Bench defaults](https://github.com/flashinfer-ai/flashinfer-bench/blob/15618a67e8d7b7f49ca61b5ba3b9f26a876d0bee/flashinfer_bench/bench/config.py) use `atol=rtol=0.01` and require all elements. Its [error test](https://github.com/flashinfer-ai/flashinfer-bench/blob/15618a67e8d7b7f49ca61b5ba3b9f26a876d0bee/flashinfer_bench/bench/utils.py) accepts an element when the absolute error is within `atol` or the relative error, divided by `abs(reference)+1e-8`, is within `rtol`. Nonfinite outputs fail.
 
-Both GDN definitions now have explicit configs in `tasks/` with that policy and pinned source links. The 19 existing SGLang task tolerances are unchanged. Definitions, references, imported baseline implementations and workload tensors are unchanged. The six-token reproduction passes the configured contest bound while continuing to fail the separately retained strict FP32 diagnostic.
+Both GDN definitions now have explicit configs in `tasks/` with that policy and pinned source links. The 19 existing SGLang task tolerances are unchanged. The audit preserves the definitions, independent references, workload tensors and tolerance policies, while replacing the legacy imported baseline implementation with maintained FlashInfer calls. The historical measurements above describe the original imported kernel. The six-token reproduction passes the configured contest bound while continuing to fail the separately retained strict FP32 diagnostic.
+
+## Maintained FlashInfer baseline in the interface audit
+
+The replacement baseline uses FlashInfer 0.7.2 with CUTLASS DSL 4.8.0. All 100
+prefill and 54 decode workloads pass the existing explicit contest policy, and
+inputs remain byte-identical. Prefill forwards the requested runtime scale;
+decode clones state before calling the maintained in-place API so the task's
+input state is not mutated.
+
+This does not make FP32 prefill state fully FP32-accurate. On the same six-token
+workload, the maintained baseline has maximum state error
+`0.0012151896953582764`; **3,909 / 131,072** elements still fail the historical
+`rtol=1e-4, atol=2e-5` diagnostic. All ten tested prefill dev workloads fail that
+strict diagnostic while passing the unchanged contest bound. The earlier
+4,143-element failure and its original measurements above remain historical
+evidence for the original imported implementation.
+
+The current FlashInfer development snapshot's raw-gate API was also evaluated
+on all ten prefill dev workloads, including a nondefault scale probe. It passed
+the contest policy but did not improve measured graph latency over the release
+API in this environment, and still failed the strict FP32 state diagnostic.
+The baseline therefore keeps the tested release API. No tolerance, reference or
+input data was changed to obtain these passes.
diff --git a/docs/interface-audit/README.md b/docs/interface-audit/README.md
new file mode 100644
index 0000000000000000000000000000000000000000..8590e0f945a1cf8786a4e6f855a517e576bda9e5
--- /dev/null
+++ b/docs/interface-audit/README.md
@@ -0,0 +1,196 @@
+# SGLang interface and implementation audit — 2026-10-19
+
+The 21 definitions are **not all direct replacements for current SGLang calls**.
+Seven have tensor operands matching a specialized attention leaf, three dense
+GEMMs flatten the engine's leading dimensions, and eleven retain structural
+adapters. No full serving run with substituted candidate kernels has been
+performed. Saved inputs are materialized contiguous tensors: original storage
+offsets, aliasing and arbitrary engine strides are not retained by safetensors.
+A matching shape/dimension order therefore does not prove storage-ABI parity.
+Standalone correctness and native tensor-layout correspondence are
+reported separately from integration.
+
+The complete, per-definition record is [interfaces.json](interfaces.json). It
+lists every native call, pinned source link, remaining adapter and required
+integration work. It covers all 21 definitions, including both GDN variants.
+
+## Sources and scope
+
+The capture used SGLang `684fea8af3b11a5b51ec9966c02959a32ad3421c`.
+Current calls were inspected at
+[`0025f939`](https://github.com/sgl-project/sglang/tree/0025f9394421451aa09ec192a4a6e7928e14736b),
+with the [0.5.22 release](https://github.com/sgl-project/sglang/releases/tag/v0.5.22)
+checked separately. New SGLang-based solutions pin the inspected commit;
+capture baselines intentionally retain their original commit. A final
+[head recheck](upstream-head-recheck.json) at 11:43 UTC found SGLang one commit
+ahead (`ed0b8f43`); its [examined diff](sglang-head-recheck-diff.json) changes
+an NPU output-gate guard and the Ascend MoE runner, not these NVIDIA operator
+boundaries. The other five upstream heads were unchanged. The tested commit
+remains pinned rather than silently replacing it with untested code.
+
+The current DeepGEMM `1fc9c669`, FlashMLA `0f11e178`, NATTEN 0.21.7 and FA4
+4.0.0b35 already match the inspected upstream snapshots/releases. FlashInfer
+0.7.2 is the current stable release. Its current development snapshot
+`f64b4ba8` was also tested for raw-gate GDN prefill; it did not beat the release
+path on the ten dev workloads. CUTLASS DSL 4.8.0 matches the tested SGLang
+runtime; this audit does not infer a speed advantage from the newer 4.8.1
+version number. Exact source metadata is in [upstreams.json](upstreams.json). The explicit
+[preferred solution list](preferred-solutions.json) identifies one measured
+choice per definition; serving baselines remain separate.
+
+These are current maintained implementations and scoped comparisons among the
+tested alternatives. This is not evidence of global optimality across all
+possible implementations, devices or serving configurations. In particular,
+the newer FlashMLA MegaAttention fusion needs pre-RoPE/normalization inputs,
+positions and weight preparation absent from the existing MLA definitions.
+It cannot be applied faithfully by changing only the packaged function.
+
+## Feasible changes
+
+- Dense attention now accepts only Q/K/V. The scale was fixed by head dimension
+  in all 162 workloads. The SGLang wrapper returns the native output view
+  without a gratuitous contiguous copy.
+- Cached-prefix attention now accepts Q, prefix K/V and current K/V in native
+  positional order. All 28 calls have full visibility; artificial image IDs,
+  the all-true key mask and fixed scale are removed. Its FA4 implementation
+  consequently needs no custom mask.
+- The twelve prefix-zero workloads drop empty prefix K/V tensors, the all-true
+  key mask and fixed scale. Their image IDs still encode a composed sequence of
+  native text/image segment calls; this remaining difference is explicit.
+- All 202 changed attention contracts were replayed against their original
+  saved engine outputs, without relaxing the replay tolerance. Workload UUIDs,
+  surviving tensor values and saved outputs are preserved. Thirteen unused
+  tensor files are removed; previous replay records remain in provenance.
+- Audio attention removes the FP16 conversions and uses BF16 FA4, with native
+  SDPA for self-attention tiles up to 64 tokens. Both paths pass all 108 current
+  workloads under the pre-existing 99.99% matched-element requirement.
+- GDN uses maintained FlashInfer calls instead of the vendored wrappers.
+  Decode copies the input state before invoking the mutating API. Both paths
+  honor runtime scale, preserve the contest's disabled Q/K normalization, and
+  pass all 154 workloads without input mutation. See the separate
+  [precision report](../gdn-prefill-numerics.md): strict FP32 prefill state
+  accuracy remains unresolved.
+- QSA index uses current SGLang scoring and native fast Top-K only to discover
+  the threshold. Deterministic Triton compaction restores lower-ID ties and
+  ascending IDs, independent of the native unordered selection. Capacities at
+  most 512 skip scoring altogether. All 192 actual workloads pass exactly;
+  all-tied, empty, short and padded rows are checked separately.
+- The router uses native FP32-output projection and fused sqrt-softplus,
+  modality selection, Top-6, normalization and routed scale. One Triton kernel
+  performs the required output ordering/int64 conversion. All 50 workloads
+  retain exact selected IDs and the original strict FP32 weight tolerance.
+- A current native TRT-LLM sparse-GQA solution is added alongside FA4; its 192
+  workloads pass. Its cache/layout preparation is explicit rather than being
+  described as a direct replacement for the serving backend.
+- The four SGLang neighborhood wrappers now honor the engine's NATTEN branch
+  when available, retaining the existing FlexAttention fallback. All 45 actual
+  workloads pass both the default NATTEN and SGLang/NATTEN paths.
+- The BF16 N=12288/K=4096 solution uses native linear on the three measured
+  large-M B300 shapes where it beat DeepGEMM; other shapes and B200 retain
+  DeepGEMM.
+- The retained dense GEMM cannot enter the old M<=4/M=32 branch, so the branch
+  and its conflicting CUTLASS dependency are removed. FA4 dependencies are
+  aligned with the tested CUTLASS DSL 4.8.0 environment.
+
+## Remaining interface differences
+
+| Definitions | Native boundary still missing or adapted |
+|---|---|
+| GDN decode | Mutable state pool and slot indices, Q/K L2 normalization, actual serving model/head configuration |
+| GDN prefill | Normalized Q/K, prepared alpha/beta, output buffers/checkpoints and serving model configuration. The native FlashInfer prefill leaf already gets gathered per-batch state; claiming it always takes a full pool would be incorrect. |
+| Two grouped GEMMs | Four global expert shards combined into one task, padding removed, logical scale bytes and row order replacing per-rank physical buffers/m_indices |
+| Two sparse MLA and mixed MLA | Four ranks' real heads combined; native per-rank zero padding/output slices, original cache pools, explicit lengths and scheduling metadata reconstructed |
+| QSA index | Zero query heads removed, live-page compaction, ordered task IDs versus native unordered IDs |
+| Sparse GQA | Snapshot after current-token KV write, compact pools, request maps and physical packing reconstructed |
+| Router | Projection plus routing combined; boolean modality replaces token IDs; int64 sorted IDs and applied scaling differ from native outputs |
+| Prefix-zero attention | Several text/image leaf calls combined into one block-causal operation |
+| Three dense GEMMs | Original batch/sequence dimensions flattened into M |
+
+Changing these definitions to the full native contracts requires new native
+captures or an explicit integration API, especially for pool side effects and
+per-rank operands. Identity indices, invented padding or fabricated missing
+inputs would not prove interface parity. The current inputs and references are
+preserved instead of silently changing the task's mathematical meaning.
+
+## Validation and timing
+
+All task tolerances, dev UUIDs, timing parameters and reference mathematical
+operations are preserved. The four attention references only specialize inputs
+whose invariants were checked for every affected workload. Both validation
+runners read the explicit task tolerance, including the GDN absolute-or-relative
+rule. Matched-element fractions use integer counts, and nonfinite outputs fail.
+The historical strict GDN diagnostic is reported separately and is not marked
+as passing.
+
+The native input checker verifies all 21 definitions, 1,104 workloads and 5,493
+tensor paths: shape, dtype, content hash, constraints, provenance and absence of
+unreferenced files. The dataset has 5,111 unique snapshots. The complete changed
+attention replay covers 202 workloads. Per-workload validation and scoped
+comparisons are summarized in [performance.md](performance.md) and recorded in
+[results.jsonl](results.jsonl) and
+[summary.json](summary.json); source hashes identify earlier and final variants.
+
+GPU measurements use B300, PyTorch 2.14.1+cu130 and the dependencies recorded in
+the summary. Eager timings and prepared-launch graph timings are separate.
+Graph timings include GPU conversions/padding/gathers within launch; only
+explicit prepare work is excluded. In particular a prepared serving baseline
+is not compared silently with an untimed preparation of the candidate.
+Compilation, reference execution and input loading occur outside timing.
+Measurements are standalone; they do not establish end-to-end serving speedups.
+
+The initial QSA compatibility experiment used TileLang 0.1.12, as required by
+current SGLang, and the old custom implementation mismatched 45 workloads.
+Rechecking its declared TileLang 0.1.15 produced **192/192 exact passes**.
+Therefore those failures are a dependency-version incompatibility, not evidence
+that the old implementation fails with its declared environment. The final
+implementation uses the current native scoring path on 0.1.12 and is compared
+with the old implementation on its actual declared 0.1.15 dependency.
+
+## Reproduce
+
+Install the selected solution's pinned dependencies and materialize the dataset
+with Git LFS. Different historical solutions can require separate environments.
+Run the audit from the repository root:
+
+```bash
+python scripts/audit_solutions.py \
+  --gpu GPU-UUID --lock-directory /path/to/locks \
+  --suite all --reference-cache --graph-timing \
+  --report results/audit.jsonl
+
+# Inspect GDN's historical strict bound in addition to formal acceptance.
+python scripts/audit_solutions.py \
+  --gpu GPU-UUID --lock-directory /path/to/locks \
+  --definition gdn_prefill_qk4_v8_d128_k_last \
+  --suite dev --strict-diagnostic --scale-probe \
+  --report results/gdn-diagnostics.jsonl
+
+python scripts/check_workload_inputs.py
+python -m unittest discover -s tests
+```
+
+`--data-root` can point to separately materialized tensors; `--cache-directory`
+selects a writable reference/module cache. `--solution` and `--definition` are
+repeatable. `--validation-only` skips timing. `--candidate /path/to/main.py`
+compares an extra implementation on one selected definition. The script exits
+nonzero on load or correctness failure; graph-capture failures are reported
+separately from numerical correctness.
+
+## Build details
+
+NATTEN 0.21.7 was built for SM103 with `CXX_STD=20` in its CMake cache:
+PyTorch 2.14 headers require C++20, while the upstream build defaults to C++17.
+The kernel sources were unchanged. `NATTEN_BUILD_DIR` must name an existing
+directory for that cache setting to be used.
+
+FlashMLA was built at the recorded commit and its CUTLASS submodule
+`4faf1a1568cf1e4ad8ff71846a13e16f2a6a6f6b`. CUDA 13.0 cannot compile that source;
+the upstream minimum is 13.1. Both isolated 13.1.115 and 13.3.73 compiler builds
+were evaluated on all 72 workloads. The 13.3 build triggered upstream's
+register-spill performance guard for sparse FP8 decode; its documented
+`FLASH_MLA_SKIP_REG_SPILL_CHECK=1` build option was used for the additional
+comparison. This skips a compiler performance guard, not output validation.
+All 72 numerical/input-immutability checks passed for both builds. The 13.3
+build gives about 3.3% geometric-mean improvement for the 42 mixed-decode
+workloads and about 0.6% for the two sparse-prefill groups in this measurement.
+These are compiler-specific results, not an algorithm or interface change.
diff --git a/docs/interface-audit/interfaces.json b/docs/interface-audit/interfaces.json
new file mode 100644
index 0000000000000000000000000000000000000000..3d30c6658d13b779675cb82bdddb59816e28bda2
--- /dev/null
+++ b/docs/interface-audit/interfaces.json
@@ -0,0 +1,345 @@
+{
+  "date": "2026-10-19",
+  "sglang_capture_commit": "684fea8af3b11a5b51ec9966c02959a32ad3421c",
+  "sglang_audit_commit": "0025f9394421451aa09ec192a4a6e7928e14736b",
+  "all_drop_in": false,
+  "full_engine_substitution_tested": false,
+  "counts": {
+    "reshaped_tensor_operands": 3,
+    "specialized_leaf_operands": 7,
+    "structural_adapter_required": 11
+  },
+  "definitions": [
+    {
+      "definition": "prefix_cached_block_causal_h32_d128",
+      "inputs": [
+        "Q",
+        "K_prefix",
+        "V_prefix",
+        "K_current",
+        "V_current"
+      ],
+      "integration_verified": false,
+      "boundary": "specialized_leaf_operands",
+      "native_call": "forward_with_replicated_kv_prefix(q, k_prefix, v_prefix, k_suffix, v_suffix)",
+      "source": "https://github.com/sgl-project/sglang/blob/0025f9394421451aa09ec192a4a6e7928e14736b/python/sglang/multimodal_gen/runtime/layers/attention/layer.py#L2134",
+      "adaptation": "After this PR all five tensor operands occur in native positional order. All 28 captured target-image calls have full visibility. The fixed scale, all-valid keys and artificial image IDs are removed. The serving method additionally obtains attention context and supports sequence parallelism; captures use one GPU.",
+      "next_step": "Integrate at this specialized single-GPU boundary and test the serving context; distributed prefix attention remains outside these captures."
+    },
+    {
+      "definition": "prefix_cached_block_causal_h32_d128_prefix0",
+      "inputs": [
+        "Q",
+        "K_current",
+        "V_current",
+        "image_ids"
+      ],
+      "integration_verified": false,
+      "boundary": "structural_adapter_required",
+      "native_call": "QwenImage21Attention.attend_sample: several local_attn calls followed by cat_outputs",
+      "source": "https://github.com/sgl-project/sglang/blob/0025f9394421451aa09ec192a4a6e7928e14736b/python/sglang/multimodal_gen/runtime/models/dits/qwen_image21.py#L719",
+      "adaptation": "The dataset combines the entire prefix into one block-causal operation. The engine calls attention once per text/image segment with different Q/K ranges and text causal masks. image_ids encodes the segment list. Empty prefix tensors, the all-true key mask and fixed scale are removed, but the composed call boundary remains.",
+      "next_step": "Recapture individual segment calls or introduce explicit segment metadata and a composed-operator integration API; do not label the existing definition a direct leaf replacement."
+    },
+    {
+      "definition": "noncausal_dense_attention_h32_d128",
+      "inputs": [
+        "Q",
+        "K",
+        "V"
+      ],
+      "integration_verified": false,
+      "boundary": "specialized_leaf_operands",
+      "native_call": "SDPAImpl.forward(query, key, value, attn_metadata)",
+      "source": "https://github.com/sgl-project/sglang/blob/0025f9394421451aa09ec192a4a6e7928e14736b/python/sglang/multimodal_gen/runtime/layers/attention/backends/sdpa.py#L89",
+      "adaptation": "The three tensor operands and their [B,N,H,D] layouts match the noncausal no-mask leaf. Head-dependent scale, dropout=0 and causal=False are fixed configuration; the engine passes its own context metadata. This PR removes the redundant runtime scale.",
+      "next_step": "Integrate the candidate through the existing attention backend/context dispatch; no full-engine replacement has been tested."
+    },
+    {
+      "definition": "noncausal_dense_attention_h32_d64",
+      "inputs": [
+        "Q",
+        "K",
+        "V"
+      ],
+      "integration_verified": false,
+      "boundary": "specialized_leaf_operands",
+      "native_call": "SDPAImpl.forward(query, key, value, attn_metadata)",
+      "source": "https://github.com/sgl-project/sglang/blob/0025f9394421451aa09ec192a4a6e7928e14736b/python/sglang/multimodal_gen/runtime/layers/attention/backends/sdpa.py#L89",
+      "adaptation": "The three tensor operands and their [B,N,H,D] layouts match the noncausal no-mask leaf. Head-dependent scale, dropout=0 and causal=False are fixed configuration; the engine passes its own context metadata. This PR removes the redundant runtime scale.",
+      "next_step": "Integrate the candidate through the existing attention backend/context dispatch; no full-engine replacement has been tested."
+    },
+    {
+      "definition": "gdn_decode_qk4_v8_d128_k_last",
+      "inputs": [
+        "q",
+        "k",
+        "v",
+        "state",
+        "A_log",
+        "a",
+        "dt_bias",
+        "b",
+        "scale"
+      ],
+      "integration_verified": false,
+      "boundary": "structural_adapter_required",
+      "native_call": "FlashInferGDNKernel.decode",
+      "source": "https://github.com/sgl-project/sglang/blob/0025f9394421451aa09ec192a4a6e7928e14736b/python/sglang/srt/layers/attention/linear/kernels/gdn_flashinfer.py#L387",
+      "adaptation": "The contest decode reads per-batch K-last state and returns a separate new_state, with Q/K normalization disabled. SM100 SGLang instead passes the complete mutable state pool plus slot indices, enables Q/K L2 normalization and writes the pool. The contest model TP/head configuration also differs.",
+      "next_step": "Capture the real current SGLang boundary, retaining normalization, pool/state-index side effects where present, prefill output buffers/checkpoints and the actual model configuration. Adding identity slot indices to contest tensors would not prove native parity."
+    },
+    {
+      "definition": "gdn_prefill_qk4_v8_d128_k_last",
+      "inputs": [
+        "q",
+        "k",
+        "v",
+        "state",
+        "A_log",
+        "a",
+        "dt_bias",
+        "b",
+        "cu_seqlens",
+        "scale"
+      ],
+      "integration_verified": false,
+      "boundary": "structural_adapter_required",
+      "native_call": "FlashInferGDNKernel.extend",
+      "source": "https://github.com/sgl-project/sglang/blob/0025f9394421451aa09ec192a4a6e7928e14736b/python/sglang/srt/layers/attention/linear/kernels/gdn_flashinfer.py#L481",
+      "adaptation": "K-last layout matches. Importantly, the actual SGLang FlashInfer prefill leaf already receives a gathered per-batch state, not the whole pool. However SGLang prepares normalized Q/K and linear decay alpha, passes preallocated output/state buffers and optional checkpoint metadata, and scatters states back. The contest definition instead accepts raw A_log/a/dt_bias/b and unnormalized Q/K, with a different model/head configuration.",
+      "next_step": "Capture the real current SGLang boundary, retaining normalization, pool/state-index side effects where present, prefill output buffers/checkpoints and the actual model configuration. Adding identity slot indices to contest tensors would not prove native parity."
+    },
+    {
+      "definition": "dense_gemm_bf16_nt_n12288_k4096",
+      "inputs": [
+        "A",
+        "W"
+      ],
+      "integration_verified": false,
+      "boundary": "reshaped_tensor_operands",
+      "native_call": "torch.nn.functional.linear(input, weight, bias=None)",
+      "source": "https://github.com/sgl-project/sglang/blob/0025f9394421451aa09ec192a4a6e7928e14736b/python/sglang/multimodal_gen/runtime/models/dits/qwen_image21.py",
+      "adaptation": "Capture flattens batch/sequence dimensions into M; restore the original leading dimensions at the model boundary. Two-dimensional GEMM operands and BF16 output match the bias-free linear leaf.",
+      "next_step": "Retain original leading shapes in per-call captures for direct high-level F.linear replacement."
+    },
+    {
+      "definition": "dense_gemm_bf16_nt_n4096_k12288",
+      "inputs": [
+        "A",
+        "W"
+      ],
+      "integration_verified": false,
+      "boundary": "reshaped_tensor_operands",
+      "native_call": "torch.nn.functional.linear(input, weight, bias=None)",
+      "source": "https://github.com/sgl-project/sglang/blob/0025f9394421451aa09ec192a4a6e7928e14736b/python/sglang/multimodal_gen/runtime/models/dits/qwen_image21.py",
+      "adaptation": "Capture flattens batch/sequence dimensions into M; restore the original leading dimensions at the model boundary. Two-dimensional GEMM operands and BF16 output match the bias-free linear leaf.",
+      "next_step": "Retain original leading shapes in per-call captures for direct high-level F.linear replacement."
+    },
+    {
+      "definition": "dense_gemm_bf16_nt_n4096_k4096",
+      "inputs": [
+        "A",
+        "W"
+      ],
+      "integration_verified": false,
+      "boundary": "reshaped_tensor_operands",
+      "native_call": "torch.nn.functional.linear(input, weight, bias=None)",
+      "source": "https://github.com/sgl-project/sglang/blob/0025f9394421451aa09ec192a4a6e7928e14736b/python/sglang/multimodal_gen/runtime/models/dits/qwen_image21.py",
+      "adaptation": "Capture flattens batch/sequence dimensions into M; restore the original leading dimensions at the model boundary. Two-dimensional GEMM operands and BF16 output match the bias-free linear leaf.",
+      "next_step": "Retain original leading shapes in per-call captures for direct high-level F.linear replacement."
+    },
+    {
+      "definition": "grouped_gemm_fp8_fp4_e384_n4608_k5120_g32",
+      "inputs": [
+        "Aq",
+        "Wq_packed",
+        "scale_A",
+        "scale_W",
+        "expert_id"
+      ],
+      "integration_verified": false,
+      "boundary": "structural_adapter_required",
+      "native_call": "deep_gemm_wrapper.grouped_gemm_nt_f8f8bf16_contig(lhs, rhs, out, m_indices, recipe_a, recipe_b)",
+      "source": "https://github.com/sgl-project/sglang/blob/0025f9394421451aa09ec192a4a6e7928e14736b/python/sglang/srt/layers/deep_gemm_wrapper/entrypoint.py#L132",
+      "adaptation": "Capture gathers four EP ranks (96 experts each) into a global 384-expert task, removes -1 padded rows, sorts valid rows by expert and serializes UE8M0 scale bytes. The native kernel consumes per-rank padded buffers, packed physical scale layouts, m_indices and a destination buffer. The packaged SGLang baseline reconstructs all four calls.",
+      "next_step": "Recapture per-rank padded operands, physical scales, output buffers and row maps. Complete logical MoE projection is preserved; the removed half-gate task is not restored.",
+      "capture_recipe_note": "The capture can expand group-128 activation scales into four identical logical group-32 scale bytes. Original physical scale layout and original group-size metadata are not native task arguments; the packaged baseline reconstructs a group-32 path."
+    },
+    {
+      "definition": "grouped_gemm_fp8_fp4_e384_n5120_k2304_g32",
+      "inputs": [
+        "Aq",
+        "Wq_packed",
+        "scale_A",
+        "scale_W",
+        "expert_id"
+      ],
+      "integration_verified": false,
+      "boundary": "structural_adapter_required",
+      "native_call": "deep_gemm_wrapper.grouped_gemm_nt_f8f8bf16_contig(lhs, rhs, out, m_indices, recipe_a, recipe_b)",
+      "source": "https://github.com/sgl-project/sglang/blob/0025f9394421451aa09ec192a4a6e7928e14736b/python/sglang/srt/layers/deep_gemm_wrapper/entrypoint.py#L132",
+      "adaptation": "Capture gathers four EP ranks (96 experts each) into a global 384-expert task, removes -1 padded rows, sorts valid rows by expert and serializes UE8M0 scale bytes. The native kernel consumes per-rank padded buffers, packed physical scale layouts, m_indices and a destination buffer. The packaged SGLang baseline reconstructs all four calls.",
+      "next_step": "Recapture per-rank padded operands, physical scales, output buffers and row maps. Complete logical MoE projection is preserved; the removed half-gate task is not restored.",
+      "capture_recipe_note": "The capture can expand group-128 activation scales into four identical logical group-32 scale bytes. Original physical scale layout and original group-size metadata are not native task arguments; the packaged baseline reconstructs a group-32 path."
+    },
+    {
+      "definition": "mixed_mla_decode_deepseek41_h64_d512_k8128_k4512",
+      "inputs": [
+        "Q",
+        "KV8",
+        "KV4",
+        "indices8",
+        "indices4",
+        "attn_sink",
+        "sm_scale"
+      ],
+      "integration_verified": false,
+      "boundary": "structural_adapter_required",
+      "native_call": "sgl_kernel.flash_mla.flash_mla_with_kvcache",
+      "source": "https://github.com/sgl-project/sglang/blob/0025f9394421451aa09ec192a4a6e7928e14736b/python/sglang/srt/layers/attention/deepseek_v4_backend.py",
+      "adaptation": "The four-rank real-head gather differs from native per-rank zero padding. Only reachable physical KV pages are retained; topk lengths and scheduler metadata are reconstructed. Upstream FlashMLA and the serving fork use different FP8 page byte layouts, requiring the packaged conversion. The engine also has mutable scheduling/workspace state.",
+      "next_step": "Recapture per-rank Q/sink, original cache pools, explicit valid lengths and scheduler metadata. The newer optional MegaAttention path needs missing pre-RoPE/normalization inputs and positions."
+    },
+    {
+      "definition": "moe_router_gemm_topk_deepseek41_d5120_e384_topk6",
+      "inputs": [
+        "X",
+        "W",
+        "bias_text",
+        "bias_image",
+        "is_image_token",
+        "routed_scale"
+      ],
+      "integration_verified": false,
+      "boundary": "structural_adapter_required",
+      "native_call": "MoEGate.forward followed by vision_topk / moe_fused_gate",
+      "source": "https://github.com/sgl-project/sglang/blob/0025f9394421451aa09ec192a4a6e7928e14736b/python/sglang/srt/multimodal/dsv41/vl_routing.py",
+      "adaptation": "One task combines projection and routing. A boolean image selector replaces original token IDs; output IDs are sorted int64 rather than native unordered int32, and deferred routed scaling is applied. The new solution uses the native projection and fused gate, accepts the boolean directly and combines output ordering in one Triton launch.",
+      "next_step": "Either integrate this composed operation with its explicit output adapter, or split projection/routing captures and retain native token IDs and output dtypes/ordering."
+    },
+    {
+      "definition": "neighborhood_attention_3d_h16_d64_kt3_ky7_kx7",
+      "inputs": [
+        "Q",
+        "K",
+        "V"
+      ],
+      "integration_verified": false,
+      "boundary": "specialized_leaf_operands",
+      "native_call": "natten.functional.na3d(query, key, value, kernel_size=self.kernel_size, scale=1.0)",
+      "source": "https://github.com/sgl-project/sglang/blob/0025f9394421451aa09ec192a4a6e7928e14736b/python/sglang/multimodal_gen/runtime/models/decoders/ltx_2_5_diffusion_decoder.py#L421",
+      "adaptation": "Tensor layout [B,T,Y,X,H,D] already matches na3d. Q includes the model scale. Kernel size and scale=1 are fixed configuration. The SGLang wrapper now selects NATTEN when installed and otherwise uses the original FlexAttention fallback.",
+      "next_step": "Bind the fixed keyword configuration and test within the VAE block; no full model substitution is claimed."
+    },
+    {
+      "definition": "neighborhood_attention_3d_h32_d64_kt3_ky7_kx7",
+      "inputs": [
+        "Q",
+        "K",
+        "V"
+      ],
+      "integration_verified": false,
+      "boundary": "specialized_leaf_operands",
+      "native_call": "natten.functional.na3d(query, key, value, kernel_size=self.kernel_size, scale=1.0)",
+      "source": "https://github.com/sgl-project/sglang/blob/0025f9394421451aa09ec192a4a6e7928e14736b/python/sglang/multimodal_gen/runtime/models/decoders/ltx_2_5_diffusion_decoder.py#L421",
+      "adaptation": "Tensor layout [B,T,Y,X,H,D] already matches na3d. Q includes the model scale. Kernel size and scale=1 are fixed configuration. The SGLang wrapper now selects NATTEN when installed and otherwise uses the original FlexAttention fallback.",
+      "next_step": "Bind the fixed keyword configuration and test within the VAE block; no full model substitution is claimed."
+    },
+    {
+      "definition": "neighborhood_attention_3d_h4_d64_kt11_ky11_kx11",
+      "inputs": [
+        "Q",
+        "K",
+        "V"
+      ],
+      "integration_verified": false,
+      "boundary": "specialized_leaf_operands",
+      "native_call": "natten.functional.na3d(query, key, value, kernel_size=self.kernel_size, scale=1.0)",
+      "source": "https://github.com/sgl-project/sglang/blob/0025f9394421451aa09ec192a4a6e7928e14736b/python/sglang/multimodal_gen/runtime/models/decoders/ltx_2_5_diffusion_decoder.py#L421",
+      "adaptation": "Tensor layout [B,T,Y,X,H,D] already matches na3d. Q includes the model scale. Kernel size and scale=1 are fixed configuration. The SGLang wrapper now selects NATTEN when installed and otherwise uses the original FlexAttention fallback.",
+      "next_step": "Bind the fixed keyword configuration and test within the VAE block; no full model substitution is claimed."
+    },
+    {
+      "definition": "neighborhood_attention_3d_h8_d64_kt3_ky5_kx5",
+      "inputs": [
+        "Q",
+        "K",
+        "V"
+      ],
+      "integration_verified": false,
+      "boundary": "specialized_leaf_operands",
+      "native_call": "natten.functional.na3d(query, key, value, kernel_size=self.kernel_size, scale=1.0)",
+      "source": "https://github.com/sgl-project/sglang/blob/0025f9394421451aa09ec192a4a6e7928e14736b/python/sglang/multimodal_gen/runtime/models/decoders/ltx_2_5_diffusion_decoder.py#L421",
+      "adaptation": "Tensor layout [B,T,Y,X,H,D] already matches na3d. Q includes the model scale. Kernel size and scale=1 are fixed configuration. The SGLang wrapper now selects NATTEN when installed and otherwise uses the original FlexAttention fallback.",
+      "next_step": "Bind the fixed keyword configuration and test within the VAE block; no full model substitution is claimed."
+    },
+    {
+      "definition": "qsa_index_topk_decode_qwen38_h4_d128_topk512_c4",
+      "inputs": [
+        "Q_idx",
+        "Kc_pages",
+        "page_table",
+        "num_complete_blocks"
+      ],
+      "integration_verified": false,
+      "boundary": "structural_adapter_required",
+      "native_call": "QSAIndexer.select_decode_tokens -> qsa_mqa_decode + fast_topk",
+      "source": "https://github.com/sgl-project/sglang/blob/0025f9394421451aa09ec192a4a6e7928e14736b/python/sglang/srt/layers/attention/qsa/qsa_indexer.py#L491",
+      "adaptation": "Capture removes four zero-padded query heads (8 to 4), compacts live cache pages and changes unordered native IDs to ascending logical IDs with -1 suffix. The new default reuses maintained scoring and exact stable compaction; its score-free short path preserves the task's output contract.",
+      "next_step": "Capture the native padded query/cache/page-table boundary and explicitly support the engine's output ordering, or keep the documented adapters. Do not weaken exact selected-set or lower-ID-tie semantics."
+    },
+    {
+      "definition": "qsa_sparse_gqa_decode_qwen38_h24_kv2_d256_topk512_c4",
+      "inputs": [
+        "Q",
+        "K_pages",
+        "V_pages",
+        "page_table",
+        "block_ids",
+        "context_lens"
+      ],
+      "integration_verified": false,
+      "boundary": "structural_adapter_required",
+      "native_call": "QwenSparseAttnBackend.forward_decode -> TRT-LLM paged attention",
+      "source": "https://github.com/sgl-project/sglang/blob/0025f9394421451aa09ec192a4a6e7928e14736b/python/sglang/srt/layers/attention/qwen_sparse_attn_backend.py",
+      "adaptation": "Inputs are compacted page snapshots after the current-token KV write. The engine receives the original pool, request-to-token metadata and current KV, and fuses sparse block expansion/cache packing. The standalone adapter reconstructs that metadata and physical packing.",
+      "next_step": "Retain the original pools, request maps, current-token KV writes and the exact fused-call metadata in new captures. The native TRT-LLM solution is provided as a faster measured alternative to FA4, with adapters still explicit."
+    },
+    {
+      "definition": "sparse_mla_prefill_h64_d512_k128",
+      "inputs": [
+        "Q",
+        "KV",
+        "indices",
+        "topk_length",
+        "attn_sink",
+        "sm_scale"
+      ],
+      "integration_verified": false,
+      "boundary": "structural_adapter_required",
+      "native_call": "sgl_kernel.flash_mla.flash_mla_sparse_fwd",
+      "source": "https://github.com/sgl-project/sglang/blob/0025f9394421451aa09ec192a4a6e7928e14736b/python/sglang/srt/layers/attention/deepseek_v4_backend.py",
+      "adaptation": "Capture gathers 16 real query heads from each of four TP ranks into 64 real heads. The engine passes each rank's 16 heads in a zero-padded 64-head buffer and keeps its first 16 outputs. The SGLang adapter repeats four native calls and concatenates their outputs.",
+      "next_step": "Recapture per-rank padded Q/sink and output slices. Current optional MegaAttention further fuses normalization/RoPE and needs pre-transform inputs not present in this definition."
+    },
+    {
+      "definition": "sparse_mla_prefill_h64_d512_k640",
+      "inputs": [
+        "Q",
+        "KV",
+        "indices",
+        "topk_length",
+        "attn_sink",
+        "sm_scale"
+      ],
+      "integration_verified": false,
+      "boundary": "structural_adapter_required",
+      "native_call": "sgl_kernel.flash_mla.flash_mla_sparse_fwd",
+      "source": "https://github.com/sgl-project/sglang/blob/0025f9394421451aa09ec192a4a6e7928e14736b/python/sglang/srt/layers/attention/deepseek_v4_backend.py",
+      "adaptation": "Capture gathers 16 real query heads from each of four TP ranks into 64 real heads. The engine passes each rank's 16 heads in a zero-padded 64-head buffer and keeps its first 16 outputs. The SGLang adapter repeats four native calls and concatenates their outputs.",
+      "next_step": "Recapture per-rank padded Q/sink and output slices. Current optional MegaAttention further fuses normalization/RoPE and needs pre-transform inputs not present in this definition."
+    }
+  ],
+  "snapshot_limit": "CaptureWriter materializes contiguous CPU tensors; original storage offsets, aliasing and arbitrary engine strides are not represented by the safetensors inputs. Tensor-dimension correspondence does not prove storage-ABI parity."
+}
diff --git a/docs/interface-audit/performance.md b/docs/interface-audit/performance.md
new file mode 100644
index 0000000000000000000000000000000000000000..69afe72d6ff59cfaf6fbe91d860518513546809c
--- /dev/null
+++ b/docs/interface-audit/performance.md
@@ -0,0 +1,17 @@
+# Recorded B300 comparisons
+
+Ratios are paired geometric-mean speedups in the recorded standalone CUDA Graph scope. Prepared launch is used where available; eager timings remain in the raw results. These are not end-to-end serving speedups or proofs of global optimality.
+
+| Comparison | Paired workloads | Speedup |
+|---|---:|---:|
+| B300 GEMM large-M native-linear dispatch versus DeepGEMM-only | 31 | 0.44× |
+| Audio final versus original FP16-conversion solution | 108 | 4.03× |
+| Current fused router versus original CUTLASS/torch solution | 50 | 5.00× |
+| Cached-prefix FA4 versus serving implementation adapter | 28 | 3.81× |
+| QSA index final versus original on its declared TileLang 0.1.15 | 10 | 2.28× |
+| Native paged sparse GQA versus FA4 sparse gather | 10 | 1.90× |
+| FlashMLA CUDA 13.3 versus CUDA 13.1 compiler build | 10 | 1.01× |
+| FlashMLA CUDA 13.3 versus CUDA 13.1 compiler build | 20 | 1.01× |
+| FlashMLA CUDA 13.3 versus CUDA 13.1 compiler build | 42 | 1.03× |
+
+The old QSA implementation is measured with its declared TileLang 0.1.15, rather than the incompatible 0.1.12 experiment. Current SGLang-based solutions use 0.1.12. See [summary.json](summary.json) for ranges, source run identifiers and coverage; [results.jsonl](results.jsonl) retains separate eager and prepared timings.
diff --git a/docs/interface-audit/preferred-solutions.json b/docs/interface-audit/preferred-solutions.json
new file mode 100644
index 0000000000000000000000000000000000000000..f1e400c874bcc10354336e597ad03658b2fd768e
--- /dev/null
+++ b/docs/interface-audit/preferred-solutions.json
@@ -0,0 +1,132 @@
+{
+  "date": "2026-10-19",
+  "hardware": "NVIDIA_B300",
+  "definitions": [
+    {
+      "definition": "prefix_cached_block_causal_h32_d128",
+      "solution": "fa4_prefix_h32_d128",
+      "path": "solutions/block_causal_attention/fa4_prefix_h32_d128.json",
+      "scope": "B300 current captured workloads; selected maintained path after scoped comparisons, not a fastest-for-every-shape or global-optimality claim"
+    },
+    {
+      "definition": "prefix_cached_block_causal_h32_d128_prefix0",
+      "solution": "fa4_prefix0_h32_d128",
+      "path": "solutions/block_causal_attention/fa4_prefix0_h32_d128.json",
+      "scope": "B300 current captured workloads; selected maintained path after scoped comparisons, not a fastest-for-every-shape or global-optimality claim"
+    },
+    {
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+      "solution": "fa4_noncausal_h32_d128",
+      "path": "solutions/dense_attention/fa4_noncausal_h32_d128.json",
+      "scope": "B300 current captured workloads; selected maintained path after scoped comparisons, not a fastest-for-every-shape or global-optimality claim"
+    },
+    {
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+      "solution": "fa4_noncausal_h32_d64",
+      "path": "solutions/dense_attention/fa4_noncausal_h32_d64.json",
+      "scope": "B300 current captured workloads; selected maintained path after scoped comparisons, not a fastest-for-every-shape or global-optimality claim"
+    },
+    {
+      "definition": "gdn_decode_qk4_v8_d128_k_last",
+      "solution": "flashinfer_gdn_decode",
+      "path": "solutions/gdn/flashinfer_gdn_decode.json",
+      "scope": "B300 current captured workloads; selected maintained path after scoped comparisons, not a fastest-for-every-shape or global-optimality claim"
+    },
+    {
+      "definition": "gdn_prefill_qk4_v8_d128_k_last",
+      "solution": "flashinfer_gdn_prefill",
+      "path": "solutions/gdn/flashinfer_gdn_prefill.json",
+      "scope": "B300 current captured workloads; selected maintained path after scoped comparisons, not a fastest-for-every-shape or global-optimality claim"
+    },
+    {
+      "definition": "dense_gemm_bf16_nt_n12288_k4096",
+      "solution": "deepgemm_bf16_n12288_k4096",
+      "path": "solutions/gemm/deepgemm_bf16_n12288_k4096.json",
+      "scope": "B300 current captured workloads; selected maintained path after scoped comparisons, not a fastest-for-every-shape or global-optimality claim"
+    },
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+      "definition": "dense_gemm_bf16_nt_n4096_k12288",
+      "solution": "deepgemm_bf16_n4096_k12288",
+      "path": "solutions/gemm/deepgemm_bf16_n4096_k12288.json",
+      "scope": "B300 current captured workloads; selected maintained path after scoped comparisons, not a fastest-for-every-shape or global-optimality claim"
+    },
+    {
+      "definition": "dense_gemm_bf16_nt_n4096_k4096",
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+      "path": "solutions/gemm/hybrid_bf16_n4096_k4096.json",
+      "scope": "B300 current captured workloads; selected maintained path after scoped comparisons, not a fastest-for-every-shape or global-optimality claim"
+    },
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+      "solution": "deepgemm_n4608_k5120",
+      "path": "solutions/grouped_gemm/deepgemm_n4608_k5120.json",
+      "scope": "B300 current captured workloads; selected maintained path after scoped comparisons, not a fastest-for-every-shape or global-optimality claim"
+    },
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+      "definition": "grouped_gemm_fp8_fp4_e384_n5120_k2304_g32",
+      "solution": "deepgemm_n5120_k2304",
+      "path": "solutions/grouped_gemm/deepgemm_n5120_k2304.json",
+      "scope": "B300 current captured workloads; selected maintained path after scoped comparisons, not a fastest-for-every-shape or global-optimality claim"
+    },
+    {
+      "definition": "mixed_mla_decode_deepseek41_h64_d512_k8128_k4512",
+      "solution": "flashmla_v41",
+      "path": "solutions/mixed_mla/flashmla_v41.json",
+      "scope": "B300 current captured workloads; selected maintained path after scoped comparisons, not a fastest-for-every-shape or global-optimality claim"
+    },
+    {
+      "definition": "moe_router_gemm_topk_deepseek41_d5120_e384_topk6",
+      "solution": "fused_router",
+      "path": "solutions/moe_router/fused_router.json",
+      "scope": "B300 current captured workloads; selected maintained path after scoped comparisons, not a fastest-for-every-shape or global-optimality claim"
+    },
+    {
+      "definition": "neighborhood_attention_3d_h16_d64_kt3_ky7_kx7",
+      "solution": "natten_blackwell_h16_3x7x7",
+      "path": "solutions/neighborhood_attention/natten_blackwell_h16_3x7x7.json",
+      "scope": "B300 current captured workloads; selected maintained path after scoped comparisons, not a fastest-for-every-shape or global-optimality claim"
+    },
+    {
+      "definition": "neighborhood_attention_3d_h32_d64_kt3_ky7_kx7",
+      "solution": "natten_blackwell_h32_3x7x7",
+      "path": "solutions/neighborhood_attention/natten_blackwell_h32_3x7x7.json",
+      "scope": "B300 current captured workloads; selected maintained path after scoped comparisons, not a fastest-for-every-shape or global-optimality claim"
+    },
+    {
+      "definition": "neighborhood_attention_3d_h4_d64_kt11_ky11_kx11",
+      "solution": "natten_blackwell_h4_11x11x11",
+      "path": "solutions/neighborhood_attention/natten_blackwell_h4_11x11x11.json",
+      "scope": "B300 current captured workloads; selected maintained path after scoped comparisons, not a fastest-for-every-shape or global-optimality claim"
+    },
+    {
+      "definition": "neighborhood_attention_3d_h8_d64_kt3_ky5_kx5",
+      "solution": "natten_blackwell_h8_3x5x5",
+      "path": "solutions/neighborhood_attention/natten_blackwell_h8_3x5x5.json",
+      "scope": "B300 current captured workloads; selected maintained path after scoped comparisons, not a fastest-for-every-shape or global-optimality claim"
+    },
+    {
+      "definition": "qsa_index_topk_decode_qwen38_h4_d128_topk512_c4",
+      "solution": "sglang_tilelang_index",
+      "path": "solutions/qsa_index/sglang_tilelang_index.json",
+      "scope": "B300 current captured workloads; selected maintained path after scoped comparisons, not a fastest-for-every-shape or global-optimality claim"
+    },
+    {
+      "definition": "qsa_sparse_gqa_decode_qwen38_h24_kv2_d256_topk512_c4",
+      "solution": "trtllm_sparse_gqa",
+      "path": "solutions/qsa_attention/trtllm_sparse_gqa.json",
+      "scope": "B300 current captured workloads; selected maintained path after scoped comparisons, not a fastest-for-every-shape or global-optimality claim"
+    },
+    {
+      "definition": "sparse_mla_prefill_h64_d512_k128",
+      "solution": "flashmla_prefill_k128",
+      "path": "solutions/sparse_mla/flashmla_prefill_k128.json",
+      "scope": "B300 current captured workloads; selected maintained path after scoped comparisons, not a fastest-for-every-shape or global-optimality claim"
+    },
+    {
+      "definition": "sparse_mla_prefill_h64_d512_k640",
+      "solution": "flashmla_prefill_k640",
+      "path": "solutions/sparse_mla/flashmla_prefill_k640.json",
+      "scope": "B300 current captured workloads; selected maintained path after scoped comparisons, not a fastest-for-every-shape or global-optimality claim"
+    }
+  ]
+}
diff --git a/docs/interface-audit/qsa-tie-edge-cases.json b/docs/interface-audit/qsa-tie-edge-cases.json
new file mode 100644
index 0000000000000000000000000000000000000000..95868c41b25c4afa191728dd15d92cf285d199ac
--- /dev/null
+++ b/docs/interface-audit/qsa-tie-edge-cases.json
@@ -0,0 +1,42 @@
+{
+  "checks": [
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+        0,
+        1,
+        32
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+      "all_scores_equal": true,
+      "lower_ids_exact": true,
+      "status": "passed"
+    },
+    {
+      "capacity": 640,
+      "lengths": [
+        0,
+        511,
+        512,
+        513,
+        640
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+      "all_scores_equal": true,
+      "lower_ids_exact": true,
+      "status": "passed"
+    },
+    {
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+        511,
+        512,
+        513,
+        65536
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+      "all_scores_equal": true,
+      "lower_ids_exact": true,
+      "status": "passed"
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+}
diff --git a/docs/interface-audit/results.jsonl b/docs/interface-audit/results.jsonl
new file mode 100644
index 0000000000000000000000000000000000000000..3699296bd501433a74a8877b4a32cf370180fd52
--- /dev/null
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diff --git a/docs/interface-audit/sglang-head-recheck-diff.json b/docs/interface-audit/sglang-head-recheck-diff.json
new file mode 100644
index 0000000000000000000000000000000000000000..e5502d60ee50b90afbc822b86028b2d9f2fee6c0
--- /dev/null
+++ b/docs/interface-audit/sglang-head-recheck-diff.json
@@ -0,0 +1,21 @@
+{
+  "base": "0025f9394421451aa09ec192a4a6e7928e14736b",
+  "head": "ed0b8f433f887995b1ce361b15aaf9f6ca93483f",
+  "ahead_by": 1,
+  "files": [
+    {
+      "path": "python/sglang/kernels/ops/attention/mla_output_gate.py",
+      "status": "modified"
+    },
+    {
+      "path": "python/sglang/srt/layers/moe/moe_runner/ascend.py",
+      "status": "modified"
+    }
+  ],
+  "commits": [
+    {
+      "sha": "ed0b8f433f887995b1ce361b15aaf9f6ca93483f",
+      "title": "[Fix] [NPU] kimi-k3: skip fused gmm1 for situ activation in Ascend runner (#43837)"
+    }
+  ]
+}
diff --git a/docs/interface-audit/summary.json b/docs/interface-audit/summary.json
new file mode 100644
index 0000000000000000000000000000000000000000..5b770448c9ef5e1aaded01e9aa0550b0c541de00
--- /dev/null
+++ b/docs/interface-audit/summary.json
@@ -0,0 +1,493 @@
+{
+  "date": "2026-10-19",
+  "status": "passed",
+  "secondary_baseline_cases_remaining": 0,
+  "scope": "One current preferred solution per definition, all captured workloads; not full serving integration or proof of global optimality",
+  "gpu": "NVIDIA B300",
+  "torch": "2.14.1+cu130",
+  "cutlass_dsl": "4.8.0",
+  "flashinfer_release": "0.7.2",
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+  "tilelang_original_declared": "0.1.15",
+  "sglang_current_commit": "0025f9394421451aa09ec192a4a6e7928e14736b",
+  "solutions": 41,
+  "preferred_definitions": 21,
+  "preferred_workloads": 1104,
+  "tolerance_dev_and_timing_unchanged": true,
+  "native_input_check": {
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+    "workloads": 1104,
+    "tensors": 5493,
+    "missing_capture_definitions": [],
+    "errors": []
+  },
+  "changed_attention_engine_output_replay": {
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+    "passed": 202
+  },
+  "coverage": [
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+      "solution": "fa4_prefix_h32_d128",
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+      "status": "passed",
+      "main_source_sha256": "ea9b3c887ea916e45144176d5efc9689f67e0f2c358b6550878ef474d534cf6c",
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+      "runs": [
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+      ]
+    },
+    {
+      "definition": "prefix_cached_block_causal_h32_d128_prefix0",
+      "solution": "fa4_prefix0_h32_d128",
+      "workloads": 12,
+      "status": "passed",
+      "main_source_sha256": "c5742cde113a0e610300650857ae0221928e7242d8710efbb28d53bab066e9a0",
+      "source_bundle_sha256": "b781309fee9fc3fa9f4e73770754b79465b48f148fc4acaea8668704690fe360",
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+      "solution": "fa4_noncausal_h32_d128",
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+      "status": "passed",
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+      "source_bundle_sha256": "dac275c646d983cc090a1427ddcad9972899893be035e5390d36d540cd87b1d4",
+      "runs": [
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+      ]
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+      "definition": "noncausal_dense_attention_h32_d64",
+      "solution": "fa4_noncausal_h32_d64",
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+      "status": "passed",
+      "main_source_sha256": "7d5c98b3052f60560e52eb49d5802ac386c1da61009ec7faf723d0b055bfd85f",
+      "source_bundle_sha256": "ab47824774752abebf2fca278f38fd3506cbd76f45e74eb9027b7655f12f3978",
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+      "main_source_sha256": "63a37b167c6496eee8519318a73177a1d2df07df3da6a9c0debd3c871f0c7b09",
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+      "solution": "deepgemm_bf16_n4096_k12288",
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+      "runs": [
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+      "solution": "hybrid_bf16_n4096_k4096",
+      "workloads": 31,
+      "status": "passed",
+      "main_source_sha256": "8e1358895cda9eaa10258759ae3fe3a57c93731c731f73e7772b46b90c26e6b6",
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+      "main_source_sha256": "d9814eacc8b50a38371ca250faf9a2c751bf66ac09b32b487c98117a8106ba21",
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+      "status": "passed",
+      "main_source_sha256": "d9814eacc8b50a38371ca250faf9a2c751bf66ac09b32b487c98117a8106ba21",
+      "source_bundle_sha256": "6b1a58f383b9682ae06b21b4feadc7c1c9ec82ea15a464de1b9f4b72f6fce978",
+      "runs": [
+        "gemm-all"
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+      "solution": "flashmla_v41",
+      "workloads": 42,
+      "status": "passed",
+      "main_source_sha256": "05b199f80930fd87851c1b45d18248bc9a51943ceee9554af3dead121af80cea",
+      "source_bundle_sha256": "354ab160017c821ee197ae5741cb263ecb75fb0ad1d53d8fc427e26c0c63a8a6",
+      "runs": [
+        "mla-cu133-all"
+      ]
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+    {
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+      "solution": "fused_router",
+      "workloads": 50,
+      "status": "passed",
+      "main_source_sha256": "278e9e41c9dd4d35607fbc760fbaaac583c7d4f75cbf0fe1353903b7ddd0d890",
+      "source_bundle_sha256": "41251abb5f27fbb587d28c2dbce5280775b403156f4f04cc1d2e85e1bef0018d",
+      "runs": [
+        "router-latest-all"
+      ]
+    },
+    {
+      "definition": "neighborhood_attention_3d_h16_d64_kt3_ky7_kx7",
+      "solution": "natten_blackwell_h16_3x7x7",
+      "workloads": 9,
+      "status": "passed",
+      "main_source_sha256": "1e37321ed835300fa3550a6fe29506bd28412d019581dbc9fbc10ccc8fff4a4c",
+      "source_bundle_sha256": "a8718b4b8210c509699cf4a17a4158a6f0f569236fa3c26aa3dd81278e71e376",
+      "runs": [
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+      ]
+    },
+    {
+      "definition": "neighborhood_attention_3d_h32_d64_kt3_ky7_kx7",
+      "solution": "natten_blackwell_h32_3x7x7",
+      "workloads": 9,
+      "status": "passed",
+      "main_source_sha256": "1e37321ed835300fa3550a6fe29506bd28412d019581dbc9fbc10ccc8fff4a4c",
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+      "runs": [
+        "na-all"
+      ]
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+    {
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+      "solution": "natten_blackwell_h4_11x11x11",
+      "workloads": 9,
+      "status": "passed",
+      "main_source_sha256": "c85ab6b43433432b5371920884c95ae14aeef6ead1354d4e60f7080195d0136f",
+      "source_bundle_sha256": "ee62e513b334c9e6dd2cf33cba16b1a615d52c2a5b619d0cf89c19a047b47a95",
+      "runs": [
+        "na-all"
+      ]
+    },
+    {
+      "definition": "neighborhood_attention_3d_h8_d64_kt3_ky5_kx5",
+      "solution": "natten_blackwell_h8_3x5x5",
+      "workloads": 18,
+      "status": "passed",
+      "main_source_sha256": "21d8e807c408bb8a5027ab6154e83bfb2ba06591f13b3cc8c454cc50000c937c",
+      "source_bundle_sha256": "161df7053b7218c4cadbb657165152edd38a897efa768c64a51332c0ee97c06f",
+      "runs": [
+        "na-all"
+      ]
+    },
+    {
+      "definition": "qsa_index_topk_decode_qwen38_h4_d128_topk512_c4",
+      "solution": "sglang_tilelang_index",
+      "workloads": 192,
+      "status": "passed",
+      "main_source_sha256": "ab3dd97e9595fbcb16e57423b8bac278f46dcb2b30472cdcf0d40f72c3e81561",
+      "source_bundle_sha256": "ab7d4df3cdefdaf1dc506f714ce3146c85927b8f58bbe3e964be15b7af8a6098",
+      "runs": [
+        "qsa-index-final-all"
+      ]
+    },
+    {
+      "definition": "qsa_sparse_gqa_decode_qwen38_h24_kv2_d256_topk512_c4",
+      "solution": "trtllm_sparse_gqa",
+      "workloads": 192,
+      "status": "passed",
+      "main_source_sha256": "517707b2c5fbf0e2eca4d038ff27704187ed97d3ff989e0270c887d8727200fc",
+      "source_bundle_sha256": "94954a8fc35eb4f5afa451ddb19f7eea4666d6d490d2ef43c95798ab12dbeddc",
+      "runs": [
+        "qsa-attention-native-all"
+      ]
+    },
+    {
+      "definition": "sparse_mla_prefill_h64_d512_k128",
+      "solution": "flashmla_prefill_k128",
+      "workloads": 10,
+      "status": "passed",
+      "main_source_sha256": "a4b0d38ef8c7f9c663d42dbb7423252c16052b0ad27ea390edd7c63bb9c71114",
+      "source_bundle_sha256": "bd8060d017ae6f67ab1e8f5ce6537b43b93827c612961fa0345dbfd5d4447904",
+      "runs": [
+        "mla-cu133-all"
+      ]
+    },
+    {
+      "definition": "sparse_mla_prefill_h64_d512_k640",
+      "solution": "flashmla_prefill_k640",
+      "workloads": 20,
+      "status": "passed",
+      "main_source_sha256": "a4b0d38ef8c7f9c663d42dbb7423252c16052b0ad27ea390edd7c63bb9c71114",
+      "source_bundle_sha256": "bd8060d017ae6f67ab1e8f5ce6537b43b93827c612961fa0345dbfd5d4447904",
+      "runs": [
+        "mla-cu133-all"
+      ]
+    }
+  ],
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+      "comparison": "B300 GEMM large-M native-linear dispatch versus DeepGEMM-only",
+      "new_run": "dense-n12288-final-all",
+      "new_solution": "deepgemm_bf16_n12288_k4096",
+      "old_run": "gemm-all",
+      "old_solution": "deepgemm_bf16_n12288_k4096",
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+      "range": [
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+        0.5396676753908549
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+      "faster_workloads": 0
+    },
+    {
+      "comparison": "Audio final versus original FP16-conversion solution",
+      "new_run": "attention-final-contracts",
+      "new_solution": "fa4_noncausal_h32_d64",
+      "old_run": "attention-all",
+      "old_solution": "fa4_noncausal_h32_d64",
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+      "range": [
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+        7.552192866046962
+      ],
+      "faster_workloads": 108
+    },
+    {
+      "comparison": "Current fused router versus original CUTLASS/torch solution",
+      "new_run": "router-latest-all",
+      "new_solution": "fused_router",
+      "old_run": "router-alternatives-all",
+      "old_solution": "cutlass_router",
+      "paired_workloads": 50,
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+      "range": [
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+      "new_run": "attention-final-contracts",
+      "new_solution": "fa4_prefix_h32_d128",
+      "old_run": "attention-all",
+      "old_solution": "sglang_prefix_cached_block_causal_h32_d128",
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+      "range": [
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+        4.082322533722384
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+      "faster_workloads": 28
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+    {
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+      "new_run": "qsa-index-final-all",
+      "new_solution": "sglang_tilelang_index",
+      "old_run": "qsa-original-declared-015-dev-timing",
+      "old_solution": "main",
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+      "faster_workloads": 10
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+    {
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+      "new_run": "qsa-attention-native-all",
+      "new_solution": "trtllm_sparse_gqa",
+      "old_run": "gemm-qsa-dev",
+      "old_solution": "fa4_sparse_gqa",
+      "paired_workloads": 10,
+      "method": "prepared launch where available; CUDA graph, iters calls per replay",
+      "geometric_mean_speedup": 1.900678441525543,
+      "range": [
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+        2.403390206583776
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+      "faster_workloads": 10
+    },
+    {
+      "comparison": "FlashMLA CUDA 13.3 versus CUDA 13.1 compiler build",
+      "new_run": "mla-cu133-all",
+      "new_solution": "flashmla_prefill_k128",
+      "old_run": "mla-all",
+      "old_solution": "flashmla_prefill_k128",
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+      "method": "prepared launch where available; CUDA graph, iters calls per replay",
+      "geometric_mean_speedup": 1.005949932930726,
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+      "faster_workloads": 8
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+    {
+      "comparison": "FlashMLA CUDA 13.3 versus CUDA 13.1 compiler build",
+      "new_run": "mla-cu133-all",
+      "new_solution": "flashmla_prefill_k640",
+      "old_run": "mla-all",
+      "old_solution": "flashmla_prefill_k640",
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+      "geometric_mean_speedup": 1.0059326934459807,
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+      "faster_workloads": 19
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+    {
+      "comparison": "FlashMLA CUDA 13.3 versus CUDA 13.1 compiler build",
+      "new_run": "mla-cu133-all",
+      "new_solution": "flashmla_v41",
+      "old_run": "mla-all",
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+      "faster_workloads": 42
+    }
+  ],
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+    "modern_six_token_new_state_max_abs_error": 0.0012151896953582764,
+    "modern_six_token_failing_elements": 3909,
+    "elements": 131072,
+    "rtol": 0.0001,
+    "atol": 2e-05,
+    "prefill_dev_strict_failures": 10,
+    "prefill_dev_checked": 10
+  },
+  "known_diagnostic_failures": {
+    "old_qsa_on_undeclared_tilelang_0_1_12": 45,
+    "old_qsa_on_declared_tilelang_0_1_15": 0,
+    "explanation": "The old custom scorer is dependency-sensitive, not proven incorrect in its declared environment. Final current scorer passes all 192 on SGLang-required 0.1.12."
+  },
+  "run_counts": {
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+    "attention-final-contracts": {
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+      "passed": 136
+    },
+    "router-alternatives-all": {
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+      "passed": 50
+    },
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+      "passed": 339,
+      "failed": 45
+    },
+    "qsa-original-declared-015-all": {
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+      "passed": 192
+    },
+    "qsa-original-declared-015-dev-timing": {
+      "environment": 1,
+      "passed": 10
+    },
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+      "passed": 192
+    },
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+      "passed": 192
+    },
+    "gemm-qsa-dev": {
+      "environment": 1,
+      "passed": 100
+    },
+    "gemm-all": {
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+      "passed": 394
+    },
+    "na-all": {
+      "environment": 1,
+      "passed": 90
+    },
+    "mla-all": {
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+      "passed": 144
+    },
+    "mla-cu133-all": {
+      "environment": 1,
+      "passed": 72
+    },
+    "gdn-stable-dev-timing": {
+      "environment": 1,
+      "passed": 17
+    },
+    "gdn-prefill-current-dev": {
+      "environment": 1,
+      "passed": 20
+    },
+    "native-builder-gdn-first": {
+      "environment": 1,
+      "passed": 2
+    }
+  }
+}
diff --git a/docs/interface-audit/upstream-head-recheck.json b/docs/interface-audit/upstream-head-recheck.json
new file mode 100644
index 0000000000000000000000000000000000000000..89d5f3a0c0f07304c30734f7fff980df60cc9671
--- /dev/null
+++ b/docs/interface-audit/upstream-head-recheck.json
@@ -0,0 +1,41 @@
+{
+  "checked_at": "2026-10-19T11:43:24.213060+00:00",
+  "repositories": [
+    {
+      "repository": "sgl-project/sglang",
+      "audited_commit": "0025f9394421451aa09ec192a4a6e7928e14736b",
+      "current_commit": "ed0b8f433f887995b1ce361b15aaf9f6ca93483f",
+      "unchanged": false
+    },
+    {
+      "repository": "flashinfer-ai/flashinfer",
+      "audited_commit": "f64b4ba8762ded12a4f4b9a2092974c9a395e7ca",
+      "current_commit": "f64b4ba8762ded12a4f4b9a2092974c9a395e7ca",
+      "unchanged": true
+    },
+    {
+      "repository": "Dao-AILab/flash-attention",
+      "audited_commit": "e7a6402a9ff099de5eb628ce207a88a3f0aa5378",
+      "current_commit": "e7a6402a9ff099de5eb628ce207a88a3f0aa5378",
+      "unchanged": true
+    },
+    {
+      "repository": "deepseek-ai/DeepGEMM",
+      "audited_commit": "1fc9c66975ee322d628b3288534ca0e9ce12a64d",
+      "current_commit": "1fc9c66975ee322d628b3288534ca0e9ce12a64d",
+      "unchanged": true
+    },
+    {
+      "repository": "deepseek-ai/FlashMLA",
+      "audited_commit": "0f11e178da1f67becb087a324b400854931ec3e3",
+      "current_commit": "0f11e178da1f67becb087a324b400854931ec3e3",
+      "unchanged": true
+    },
+    {
+      "repository": "SHI-Labs/NATTEN",
+      "audited_commit": "39375ea1d2f3b1bb284315fa5f79f6ecbebb6382",
+      "current_commit": "39375ea1d2f3b1bb284315fa5f79f6ecbebb6382",
+      "unchanged": true
+    }
+  ]
+}
diff --git a/docs/interface-audit/upstreams.json b/docs/interface-audit/upstreams.json
new file mode 100644
index 0000000000000000000000000000000000000000..6df3cf855f9d4eb455fb25a15a2f1131328e0976
--- /dev/null
+++ b/docs/interface-audit/upstreams.json
@@ -0,0 +1,112 @@
+{
+  "repositories": [
+    {
+      "repository": "sgl-project/sglang",
+      "commit": "0025f9394421451aa09ec192a4a6e7928e14736b",
+      "date": "2026-10-19T10:24:17Z",
+      "title": "[Fix] sgl-router: Refuse prefill workers that cannot compute before bootstrap under --decode-dispatch-limit (#45120)",
+      "latest_release": {
+        "tag": "v0.5.22",
+        "date": "2026-10-19T02:55:19Z",
+        "url": "https://github.com/sgl-project/sglang/releases/tag/v0.5.22"
+      }
+    },
+    {
+      "repository": "flashinfer-ai/flashinfer",
+      "commit": "f64b4ba8762ded12a4f4b9a2092974c9a395e7ca",
+      "date": "2026-10-19T10:50:33Z",
+      "title": "perf(cake_all_gather_matmul): SM103a CTA-pair main kernel for two measured gate/up shapes (region table with column ranges) (#6566)",
+      "latest_release": {
+        "tag": "v0.7.2",
+        "date": "2026-10-15T20:36:26Z",
+        "url": "https://github.com/flashinfer-ai/flashinfer/releases/tag/v0.7.2"
+      }
+    },
+    {
+      "repository": "Dao-AILab/flash-attention",
+      "commit": "e7a6402a9ff099de5eb628ce207a88a3f0aa5378",
+      "date": "2026-10-19T02:35:33Z",
+      "title": "[CuTe] Add typed forward configurations (#2732)",
+      "latest_release": {
+        "tag": "v2.8.3.post2",
+        "date": "2026-10-13T05:41:17Z",
+        "url": "https://github.com/Dao-AILab/flash-attention/releases/tag/v2.8.3.post2"
+      }
+    },
+    {
+      "repository": "deepseek-ai/DeepGEMM",
+      "commit": "1fc9c66975ee322d628b3288534ca0e9ce12a64d",
+      "date": "2026-10-14T05:35:55Z",
+      "title": "Update FP8 epilogues and paged sparse MQA alignment (#471)",
+      "latest_release": {
+        "tag": "v2.1.1.post3",
+        "date": "2025-10-15T14:30:54Z",
+        "url": "https://github.com/deepseek-ai/DeepGEMM/releases/tag/v2.1.1.post3"
+      }
+    },
+    {
+      "repository": "deepseek-ai/FlashMLA",
+      "commit": "0f11e178da1f67becb087a324b400854931ec3e3",
+      "date": "2026-10-15T13:47:29Z",
+      "title": "Make FlashMLA CPython and LibTorch ABI stable (#230)"
+    },
+    {
+      "repository": "SHI-Labs/NATTEN",
+      "commit": "39375ea1d2f3b1bb284315fa5f79f6ecbebb6382",
+      "date": "2026-07-26T18:07:00Z",
+      "title": "0.21.7 release (#344)",
+      "latest_release": {
+        "tag": "v0.21.7",
+        "date": "2026-07-26T18:35:17Z",
+        "url": "https://github.com/SHI-Labs/NATTEN/releases/tag/v0.21.7"
+      }
+    }
+  ],
+  "packages": {
+    "flash-attn-4": {
+      "latest": "4.0.0b35",
+      "project_urls": {
+        "Homepage": "https://github.com/Dao-AILab/flash-attention",
+        "Repository": "https://github.com/Dao-AILab/flash-attention"
+      }
+    },
+    "flashinfer-python": {
+      "latest": "0.7.2",
+      "project_urls": {
+        "Homepage": "https://github.com/flashinfer-ai/flashinfer"
+      }
+    },
+    "nvidia-cutlass-dsl": {
+      "latest": "4.8.1",
+      "project_urls": {
+        "Documentation": "https://github.com/NVIDIA/cutlass",
+        "Issues": "https://github.com/NVIDIA/cutlass/issues",
+        "License": "https://docs.nvidia.com/cutlass/latest/media/docs/pythonDSL/license.html",
+        "Repository": "https://github.com/NVIDIA/cutlass"
+      }
+    },
+    "quack-kernels": {
+      "latest": "0.6.5",
+      "project_urls": null
+    },
+    "natten": {
+      "latest": "0.21.7",
+      "project_urls": {
+        "Changelog": "https://github.com/SHI-Labs/NATTEN/blob/main/CHANGELOG.md",
+        "Documentation": "https://natten.org",
+        "Homepage": "https://natten.org",
+        "Repository": "https://github.com/SHI-Labs/NATTEN.git"
+      }
+    },
+    "torch": {
+      "latest": "2.14.1",
+      "project_urls": {
+        "Documentation": "https://pytorch.org/docs",
+        "Forum": "https://discuss.pytorch.org",
+        "Homepage": "https://pytorch.org",
+        "Issue Tracker": "https://github.com/pytorch/pytorch/issues",
+        "Repository": "https://github.com/pytorch/pytorch"
+      }
+    }
+  }
+}
diff --git a/scripts/audit_solutions.py b/scripts/audit_solutions.py
new file mode 100644
index 0000000000000000000000000000000000000000..135dc820e9e317bc3530dbf544de618db86be605
--- /dev/null
+++ b/scripts/audit_solutions.py
@@ -0,0 +1,395 @@
+"""Validate and time actual solutions against independent task references."""
+
+import argparse
+import contextlib
+import fcntl
+import hashlib
+import importlib.util
+import json
+import os
+from pathlib import Path
+import statistics
+import sys
+import time
+import traceback
+
+from task_acceptance import compare_output
+
+parser = argparse.ArgumentParser(description=__doc__)
+parser.add_argument("--root", type=Path, default=Path(__file__).resolve().parents[1])
+parser.add_argument(
+    "--data-root", type=Path, help="Optional materialized dataset with the same paths"
+)
+parser.add_argument("--lock-directory", type=Path, required=True)
+parser.add_argument(
+    "--cache-directory", type=Path, help="Writable module and reference cache"
+)
+parser.add_argument("--definition", action="append")
+parser.add_argument("--suite", choices=["first", "dev", "all"], default="first")
+parser.add_argument("--only-default", action="store_true")
+parser.add_argument("--report", required=True, type=Path)
+parser.add_argument("--validation-only", action="store_true")
+parser.add_argument("--scale-probe", action="store_true")
+parser.add_argument("--gpu", required=True)
+parser.add_argument("--workload", action="append")
+parser.add_argument("--solution", action="append")
+parser.add_argument(
+    "--candidate",
+    action="append",
+    default=[],
+    help="Extra run() module for comparing a candidate on one selected definition",
+)
+parser.add_argument("--reference-cache", action="store_true")
+parser.add_argument("--graph-timing", action="store_true")
+parser.add_argument(
+    "--strict-diagnostic",
+    action="store_true",
+    help="Also report the historical FP32 bound for GDN; does not affect task acceptance",
+)
+args = parser.parse_args()
+SOURCE = args.root.resolve()
+DATA = args.data_root.resolve() if args.data_root else SOURCE
+CACHE = (
+    args.cache_directory.resolve()
+    if args.cache_directory
+    else SOURCE / "results/audit-cache"
+)
+GPU = args.gpu
+LOCKS = args.lock_directory
+LOCKS.mkdir(exist_ok=True, parents=True)
+os.environ["CUDA_VISIBLE_DEVICES"] = GPU
+stack = contextlib.ExitStack()
+for suffix in ["", ".lock"]:
+    handle = stack.enter_context((LOCKS / (GPU + suffix)).open("a+"))
+    fcntl.flock(handle.fileno(), fcntl.LOCK_EX | fcntl.LOCK_NB)
+
+import torch
+from safetensors.torch import load_file
+
+torch.set_num_threads(8)
+torch.backends.cuda.matmul.allow_tf32 = False
+torch._inductor.config.compile_threads = 1
+
+
+def load_function(name, path):
+    identifier = "_audit_" + hashlib.sha256(name.encode()).hexdigest()[:20]
+    package = path.parent
+    spec = importlib.util.spec_from_file_location(
+        identifier, package / "__init__.py", submodule_search_locations=[str(package)]
+    )
+    if path.name != "main.py":
+        spec = importlib.util.spec_from_file_location(identifier, path)
+    module = importlib.util.module_from_spec(spec)
+    sys.modules[identifier] = module
+    spec.loader.exec_module(module)
+    if path.name == "main.py":
+        spec = importlib.util.spec_from_file_location(identifier + ".main", path)
+        child = importlib.util.module_from_spec(spec)
+        sys.modules[spec.name] = child
+        spec.loader.exec_module(child)
+        module = child
+    return module.run, getattr(module, "prepare", None)
+
+
+def normalize(result, definition):
+    return (
+        list(result.values())
+        if isinstance(result, dict)
+        else list(result)
+        if isinstance(result, (tuple, list))
+        else [result]
+    )
+
+
+def compare(actual, expected, definition, config):
+    values = normalize(actual, definition)
+    assert len(values) == len(expected)
+    metrics = {}
+    for name, value, reference in zip(definition["outputs"], values, expected):
+        metrics[name] = compare_output(value, reference, config["tolerance"])
+    return metrics
+
+
+def measure(function, inputs, timing):
+    for _ in range(timing["warmup"]):
+        _result = function(*inputs)
+    torch.cuda.synchronize()
+    samples = []
+    for _ in range(timing["iters"] * timing["trials"]):
+        start = torch.cuda.Event(enable_timing=True)
+        end = torch.cuda.Event(enable_timing=True)
+        start.record()
+        _result = function(*inputs)
+        end.record()
+        end.synchronize()
+        samples.append(start.elapsed_time(end) * 1000)
+    return {
+        "median_us": statistics.median(samples),
+        "samples_us": samples,
+        "method": "CUDA events over eager calls",
+    }
+
+
+def measure_graph(function, inputs, timing, definition, config, expected):
+    for _ in range(max(3, timing["warmup"])):
+        result = function(*inputs)
+    torch.cuda.synchronize()
+    graph = torch.cuda.CUDAGraph()
+    with torch.cuda.graph(graph):
+        for _ in range(timing["iters"]):
+            result = function(*inputs)
+    graph.replay()
+    torch.cuda.synchronize()
+    compare(result, expected, definition, config)
+    samples = []
+    for _ in range(timing["trials"]):
+        start = torch.cuda.Event(enable_timing=True)
+        end = torch.cuda.Event(enable_timing=True)
+        start.record()
+        graph.replay()
+        end.record()
+        end.synchronize()
+        samples.append(start.elapsed_time(end) * 1000 / timing["iters"])
+    return {
+        "median_us": statistics.median(samples),
+        "samples_us": samples,
+        "method": "CUDA graph, iters calls per replay",
+        "calls_per_replay": timing["iters"],
+    }
+
+
+definitions = {
+    json.loads(f.read_text())["name"]: json.loads(f.read_text())
+    for f in (SOURCE / "definitions").rglob("*.json")
+}
+solutions = {}
+for f in (SOURCE / "solutions").rglob("*.json"):
+    s = json.loads(f.read_text())
+    solutions.setdefault(s["definition"], []).append(s)
+rows_by_name = {
+    f.stem: [json.loads(l)["workload"] for l in f.read_text().splitlines()]
+    for f in (SOURCE / "workloads").rglob("*.jsonl")
+}
+args.report.parent.mkdir(exist_ok=True, parents=True)
+failures = 0
+with args.report.open("w") as report, torch.inference_mode():
+
+    def emit(row):
+        report.write(json.dumps(row) + "\n")
+        report.flush()
+
+    emit(
+        {
+            "type": "environment",
+            "gpu": torch.cuda.get_device_name(),
+            "torch": torch.__version__,
+            "suite": args.suite,
+            "pythonpath": os.environ.get("PYTHONPATH"),
+            "started_at": time.time(),
+        }
+    )
+    for name, definition in definitions.items():
+        if args.definition and name not in args.definition:
+            continue
+        config = json.loads((SOURCE / "tasks" / f"{name}.json").read_text())
+        rows = rows_by_name[name]
+        if args.suite == "dev":
+            rows = [row for row in rows if row["uuid"] in config["dev"]]
+        if args.suite == "first":
+            rows = rows[:1]
+        if args.workload:
+            rows = [row for row in rows if row["uuid"] in args.workload]
+        candidates = []
+        for solution in solutions[name]:
+            if args.only_default and solution["name"] == "sglang_" + name:
+                continue
+            digest = hashlib.sha256(
+                json.dumps(solution, sort_keys=True).encode()
+            ).hexdigest()
+            package = CACHE / "modules" / digest
+            for source in solution["sources"]:
+                target = package / source["path"]
+                if not target.resolve().is_relative_to(package.resolve()):
+                    raise ValueError("Source path escapes package")
+                target.parent.mkdir(parents=True, exist_ok=True)
+                target.write_text(source["content"])
+            (package / "__init__.py").touch()
+            entry = solution["spec"]["entry_point"].split("::")[0]
+            candidates.append((solution["name"], package / entry))
+        if args.candidate:
+            assert args.definition and len(args.definition) == 1
+            candidates.extend((Path(p).stem, Path(p)) for p in args.candidate)
+        if args.solution:
+            candidates = [(s, p) for s, p in candidates if s in args.solution]
+        ns = {}
+        exec(definition["reference"], ns)
+        reference = ns["run"]
+        for solution, path in candidates:
+            try:
+                function, prepare = load_function(solution, path)
+            except Exception:
+                failures += 1
+                emit(
+                    {
+                        "type": "load",
+                        "definition": name,
+                        "solution": solution,
+                        "status": "failed",
+                        "error": traceback.format_exc(),
+                    }
+                )
+                print("LOAD FAILED", name, solution, flush=True)
+                continue
+            for row in rows:
+                inputs = []
+                saved = []
+                expected = []
+                result = {
+                    "type": "workload",
+                    "definition": name,
+                    "solution": solution,
+                    "uuid": row["uuid"],
+                    "axes": row["axes"],
+                    "solution_sha256": hashlib.sha256(path.read_bytes()).hexdigest(),
+                    "definition_sha256": hashlib.sha256(
+                        json.dumps(definition, sort_keys=True).encode()
+                    ).hexdigest(),
+                    "task_sha256": hashlib.sha256(
+                        json.dumps(config, sort_keys=True).encode()
+                    ).hexdigest(),
+                }
+                try:
+                    for key in definition["inputs"]:
+                        desc = row["inputs"][key]
+                        value = (
+                            desc["value"]
+                            if desc["type"] == "scalar"
+                            else load_file(str(DATA / desc["path"]), device="cuda")[
+                                desc["tensor_key"]
+                            ]
+                        )
+                        inputs.append(value)
+                        saved.append(
+                            value.clone() if isinstance(value, torch.Tensor) else value
+                        )
+                    cache_key = hashlib.sha256(
+                        json.dumps(
+                            {
+                                "reference": definition["reference"],
+                                "row": row,
+                                "torch": torch.__version__,
+                            },
+                            sort_keys=True,
+                        ).encode()
+                    ).hexdigest()
+                    cache = CACHE / "references" / (cache_key + ".pt")
+                    if args.reference_cache and cache.exists():
+                        expected = [
+                            value.to("cuda")
+                            for value in torch.load(cache, weights_only=True)
+                        ]
+                    else:
+                        expected = [
+                            value.clone()
+                            for value in normalize(reference(*inputs), definition)
+                        ]
+                        if args.reference_cache:
+                            cache.parent.mkdir(exist_ok=True, parents=True)
+                            torch.save([value.cpu() for value in expected], cache)
+                    actual_result = function(*inputs)
+                    result["errors"] = compare(
+                        actual_result, expected, definition, config
+                    )
+                    if args.strict_diagnostic and name.startswith("gdn_"):
+                        result["strict_fp32_diagnostic"] = {}
+                        for key, value, target in zip(
+                            definition["outputs"],
+                            normalize(actual_result, definition),
+                            expected,
+                        ):
+                            if value.dtype == torch.float32:
+                                close = torch.isclose(
+                                    value, target, rtol=1e-4, atol=2e-5
+                                )
+                                result["strict_fp32_diagnostic"][key] = {
+                                    "rtol": 1e-4,
+                                    "atol": 2e-5,
+                                    "mismatched_elements": int((~close).sum()),
+                                    "elements": close.numel(),
+                                    "passes": bool(close.all()),
+                                }
+                    for key, value, original in zip(
+                        definition["inputs"], inputs, saved
+                    ):
+                        if isinstance(value, torch.Tensor):
+                            assert torch.equal(
+                                value.contiguous().view(torch.uint8),
+                                original.contiguous().view(torch.uint8),
+                            ), key + " input mutated"
+                    if args.scale_probe and "scale" in definition["inputs"]:
+                        index = list(definition["inputs"]).index("scale")
+                        original = inputs[index]
+                        inputs[index] = (
+                            definition["axes"]["head_size"]["value"] ** -0.5
+                            if original is None or original == 0
+                            else original
+                        ) * 0.5
+                        target = [
+                            value.clone()
+                            for value in normalize(reference(*inputs), definition)
+                        ]
+                        result["scale_probe"] = compare(
+                            function(*inputs), target, definition, config
+                        )
+                        inputs[index] = original
+                    if not args.validation_only:
+                        result["run_timing"] = measure(
+                            function, inputs, config["timing"]
+                        )
+                        if prepare:
+                            launch = prepare(*inputs)
+                            result["prepared_timing"] = measure(
+                                lambda *unused: launch(), inputs, config["timing"]
+                            )
+                        if args.graph_timing:
+                            try:
+                                launch_function = (
+                                    (lambda *unused: launch()) if prepare else function
+                                )
+                                result["graph_timing"] = measure_graph(
+                                    launch_function,
+                                    inputs,
+                                    config["timing"],
+                                    definition,
+                                    config,
+                                    expected,
+                                )
+                            except Exception:
+                                result["graph_error"] = traceback.format_exc()
+                    for key, value, original in zip(
+                        definition["inputs"], inputs, saved
+                    ):
+                        if isinstance(value, torch.Tensor):
+                            assert torch.equal(
+                                value.contiguous().view(torch.uint8),
+                                original.contiguous().view(torch.uint8),
+                            ), key + " input mutated during timing"
+                    result["inputs_unchanged"] = True
+                    result["status"] = "passed"
+                except Exception:
+                    failures += 1
+                    result.update(status="failed", error=traceback.format_exc())
+                emit(result)
+                print(
+                    result["status"],
+                    name,
+                    solution,
+                    row["axes"],
+                    result.get("run_timing", {}).get("median_us"),
+                    flush=True,
+                )
+                inputs = saved = expected = actual_result = None
+            function = prepare = None
+
+if failures:
+    raise SystemExit(f"{failures} failed cases; see {args.report}")
diff --git a/scripts/benchmark_solutions.py b/scripts/benchmark_solutions.py
index b29ace328b5391a9292233f7f0c4ecef946eaa78..abb3ccae09ba73c9c9eb58caacfdd5d57ce63fb3 100644
--- a/scripts/benchmark_solutions.py
+++ b/scripts/benchmark_solutions.py
@@ -10,6 +10,8 @@ import statistics
 import time
 import traceback
 
+from task_acceptance import compare_output
+
 
 def main():
     parser = argparse.ArgumentParser(description=__doc__)
@@ -85,30 +87,8 @@ def main():
             return load_file(str(data_root / descriptor["path"]), device="cuda")[descriptor["tensor_key"]]
 
         def compare(actual, expected, definition, output_name):
-            if actual.shape != expected.shape or actual.dtype != expected.dtype:
-                raise AssertionError(f"{output_name}: output shape or dtype differs")
-            if not actual.is_floating_point():
-                torch.testing.assert_close(actual, expected, rtol=0, atol=0)
-                return {"comparison": "exact"}
-            if not torch.isfinite(actual).all() or not torch.isfinite(expected).all():
-                raise AssertionError(f"{output_name}: nonfinite output")
-            difference = actual.float() - expected.float()
-            metrics = {"max_absolute_error": difference.abs().max().item() if actual.numel() else 0.0}
-            if definition.startswith("gated_delta_rule_prefill_") and output_name == "S_final":
-                metrics.update(
-                    relative_rms=(difference.norm() / expected.norm().clamp_min(1e-12)).item(),
-                    relative_max=(difference.abs().max() / expected.abs().max().clamp_min(1e-12)).item(),
-                    max_head_relative_rms=(difference.norm(dim=(-2, -1)) /
-                        expected.norm(dim=(-2, -1)).clamp_min(1e-12)).max().item(),
-                )
-                for key, bound in {"relative_rms": .01, "relative_max": .015,
-                                   "max_head_relative_rms": .02}.items():
-                    if metrics[key] > bound:
-                        raise AssertionError(f"{output_name}: {key}={metrics[key]} > {bound}")
-            else:
-                rtol, atol = (.016, .005) if actual.dtype == torch.bfloat16 else (1e-4, 2e-5)
-                torch.testing.assert_close(actual, expected, rtol=rtol, atol=atol)
-            return metrics
+            config = json.loads((root / 'tasks' / f'{definition}.json').read_text())
+            return compare_output(actual, expected, config['tolerance'])
 
         def measure(function):
             for _ in range(3):
@@ -170,8 +150,10 @@ def main():
                         inputs = [load(workload["inputs"][key]) for key in definition.inputs]
                         actual = runnable(*inputs)
                         outputs = list(actual) if isinstance(actual, (tuple, list)) else [actual]
-                        descriptors = receipts[workload["uuid"]]["expected_output"]
-                        if "type" in descriptors:
+                        descriptors = receipts[workload["uuid"]].get("expected_output")
+                        if reference is None and descriptors is None:
+                            raise ValueError("This imported workload has no saved engine output; compare to reference")
+                        if descriptors is not None and "type" in descriptors:
                             descriptors = {next(iter(definition.outputs)): descriptors}
                         if len(outputs) != len(definition.outputs):
                             raise AssertionError("Output count differs")
diff --git a/scripts/capture_inputs.py b/scripts/capture_inputs.py
index 6f0915f59e446573b7bc40687f9c6adb2f8b211f..bc5cb26999884543ff4347592f53dfc64a44762e 100644
--- a/scripts/capture_inputs.py
+++ b/scripts/capture_inputs.py
@@ -138,14 +138,13 @@ def _gemm(a, weight, output, operation):
 
 
 def _block_attention(q, k, v, prefix_length, segments, output, context, operation):
-    import math
     import torch
 
     name = "prefix_cached_block_causal_h32_d128"
     if not prefix_length:
         name += "_prefix0"
     provenance = _provenance(context, operation, prefix_segments=segments,
-                            adapter="Preserve post-normalization/RoPE tensors; materialize the engine's segment visibility.")
+                            adapter="Preserve post-normalization/RoPE tensors; specialize fully visible target attention or encode prefix segment visibility.")
     if not _WRITER.wants(name, provenance):
         return
     image_ids = torch.full((k.shape[1],), -1, dtype=torch.int32, device=q.device)
@@ -156,11 +155,15 @@ def _block_attention(q, k, v, prefix_length, segments, output, context, operatio
             next_image += 1
     if prefix_length:
         image_ids[prefix_length:] = next_image
-    inputs = dict(Q=q, K_current=k[:, prefix_length:], V_current=v[:, prefix_length:],
-                  K_prefix=k[:, :prefix_length], V_prefix=v[:, :prefix_length],
-                  image_ids=image_ids,
-                  key_valid=torch.ones((q.shape[0], k.shape[1]), dtype=torch.bool, device=q.device),
-                  sm_scale=1 / math.sqrt(q.shape[-1]))
+    if q.shape[-1] != 128:
+        raise ValueError("The image attention contract fixes head dimension and scale")
+    inputs = dict(Q=q, K_current=k[:, prefix_length:], V_current=v[:, prefix_length:])
+    if prefix_length:
+        if not bool((image_ids[prefix_length:] == next_image).all()):
+            raise ValueError("Target-image attention must expose one fully visible image block")
+        inputs.update(K_prefix=k[:, :prefix_length], V_prefix=v[:, :prefix_length])
+    else:
+        inputs["image_ids"] = image_ids
     _WRITER.write(name, inputs, output, provenance)
 
 
@@ -340,7 +343,7 @@ def install():
         install_deepseek(_WRITER)
 
 
-def replay(dataset_root, device):
+def replay(dataset_root, device, selected_definitions=None):
     """Compare full reference outputs against the captured serving outputs."""
     import time
     import traceback
@@ -374,6 +377,8 @@ def replay(dataset_root, device):
         for line in path.read_text().splitlines():
             trace = json.loads(line)
             name, workload = trace["definition"], trace["workload"]
+            if selected_definitions and name not in selected_definitions:
+                continue
             if "expected_output" not in receipts[workload["uuid"]]:
                 continue  # Imported workloads (the MLSys 2026 GDN) have no engine output.
             started = time.monotonic()
@@ -488,6 +493,7 @@ def main():
     parser.add_argument("--model-path", type=Path)
     parser.add_argument("--output-root", type=Path)
     parser.add_argument("--replay-root", type=Path)
+    parser.add_argument("--replay-definition", action="append", help="Replay only these definitions; repeatable")
     parser.add_argument("--import-capture", type=Path)
     parser.add_argument("--device", default="cuda")
     parser.add_argument("--port", type=int, default=30000)
@@ -501,7 +507,7 @@ def main():
             parser.error("Import requires --output-root")
         return import_capture(args.import_capture, args.output_root)
     if args.replay_root:
-        return replay(args.replay_root, args.device)
+        return replay(args.replay_root, args.device, args.replay_definition)
     if args.model_path is None or args.output_root is None:
         parser.error("Serving capture requires --model-path and --output-root")
     root = args.output_root.resolve()
diff --git a/scripts/capture_ltx.py b/scripts/capture_ltx.py
index 4ce2b807b2b043ac1f959af76156b932e5f05db1..0290a420b7431a674df50b0b0e0f6fc3dde201bb 100644
--- a/scripts/capture_ltx.py
+++ b/scripts/capture_ltx.py
@@ -82,7 +82,7 @@ def install(writer):
                         visible = mask == 0 if mask.is_floating_point() else mask.bool()
                         if not bool(visible.all()):
                             raise ValueError("Mask-free attention capture requires an all-visible engine mask")
-                    writer.write(name, dict(Q=q, K=k, V=v, sm_scale=q.shape[-1] ** -0.5),
+                    writer.write(name, dict(Q=q, K=k, V=v),
                                  output.reshape_as(q), provenance)
                 return output
 
diff --git a/scripts/task_acceptance.py b/scripts/task_acceptance.py
new file mode 100644
index 0000000000000000000000000000000000000000..29f224872aeebdc4d80f44ccc9ae0ebaae0efb9f
--- /dev/null
+++ b/scripts/task_acceptance.py
@@ -0,0 +1,41 @@
+"""Evaluate one output using the task's explicit, unchanged acceptance policy."""
+
+
+def compare_output(actual, expected, tolerance):
+    import torch
+
+    if (
+        actual.shape != expected.shape
+        or actual.dtype != expected.dtype
+        or actual.device != expected.device
+    ):
+        raise AssertionError("Output shape, dtype or device differs")
+    if not actual.is_floating_point():
+        if not torch.equal(actual, expected):
+            raise AssertionError("Integer output differs")
+        return {"exact": True}
+    if not bool(torch.isfinite(actual).all()) or not bool(
+        torch.isfinite(expected).all()
+    ):
+        raise AssertionError("Nonfinite output")
+    error = (actual.float() - expected.float()).abs()
+    if tolerance.get("comparison") == "absolute_or_relative":
+        close = (error <= tolerance["atol"]) | (
+            error / (expected.float().abs() + 1e-8) <= tolerance["rtol"]
+        )
+    else:
+        close = error <= tolerance["atol"] + tolerance["rtol"] * expected.float().abs()
+    # Count in integer arithmetic; a floating-point mean can round below 1
+    # even when every element passes.
+    matched = int(close.sum())
+    ratio = matched / close.numel() if close.numel() else 1.0
+    required = tolerance.get("required_matched_ratio")
+    if ratio < (1.0 if required is None else required):
+        raise AssertionError(
+            f"Matched {matched}/{close.numel()} output elements ({ratio})"
+        )
+    return {
+        "max_absolute_error": error.max().item() if error.numel() else 0.0,
+        "matched_ratio": ratio,
+        "mismatched_elements": close.numel() - matched,
+    }
diff --git a/solutions/block_causal_attention/fa4_prefix0_h32_d128.json b/solutions/block_causal_attention/fa4_prefix0_h32_d128.json
index 2e957daa3c495970b5b50d1684c57d7aed0ddaba..f179330c9cd0dd5b2c2bc0bf2375e1987f238663 100644
--- a/solutions/block_causal_attention/fa4_prefix0_h32_d128.json
+++ b/solutions/block_causal_attention/fa4_prefix0_h32_d128.json
@@ -3,6 +3,25 @@
   "definition": "prefix_cached_block_causal_h32_d128_prefix0",
   "author": "inference-kernels",
   "description": "FlashAttention 4 with causal-or-same-image visibility and runtime key validity. Upstream: https://github.com/Dao-AILab/flash-attention (BSD-3-Clause).",
-  "spec": {"language": "python", "target_hardware": ["NVIDIA_B200"], "entry_point": "main.py::run", "dependencies": ["torch>=2.11", "flash-attn-4==4.0.0b35", "nvidia-cutlass-dsl[cu13]==4.7.1", "quack-kernels==0.6.5"], "destination_passing_style": false},
-  "sources": [{"path": "main.py", "content": "import cutlass\nimport cutlass.cute as cute\nfrom flash_attn.cute import utils\nfrom flash_attn.cute.interface import flash_attn_func\n\n@cute.jit\ndef visible(batch, head, m_idx, n_idx, seqlen_info, aux_tensors):\n    m = cutlass.min(m_idx[0], seqlen_info.seqlen_q - 1)\n    n = cutlass.min(n_idx[0], seqlen_info.seqlen_k - 1)\n    image_q = aux_tensors[0][m]\n    image_k = aux_tensors[0][n]\n    same_image = (image_q >= 0) & (image_q == image_k)\n    allowed = ((n_idx[0] <= m_idx[0]) | same_image) & aux_tensors[1][batch[0], n]\n    return utils.scalar_to_ssa(allowed, cutlass.Boolean)\n\ndef run(Q, K_current, V_current, K_prefix, V_prefix, image_ids, key_valid, sm_scale):\n    return flash_attn_func(Q, K_current, V_current, softmax_scale=sm_scale, mask_mod=visible, aux_tensors=[image_ids, key_valid])[0]\n"}]
+  "spec": {
+    "language": "python",
+    "target_hardware": [
+      "NVIDIA_B200",
+      "NVIDIA_B300"
+    ],
+    "entry_point": "main.py::run",
+    "dependencies": [
+      "torch>=2.11",
+      "flash-attn-4==4.0.0b35",
+      "nvidia-cutlass-dsl[cu13]==4.8.0",
+      "quack-kernels==0.6.5"
+    ],
+    "destination_passing_style": false
+  },
+  "sources": [
+    {
+      "path": "main.py",
+      "content": "import cutlass\nimport cutlass.cute as cute\nfrom flash_attn.cute import utils\nfrom flash_attn.cute.interface import flash_attn_func\n\n@cute.jit\ndef visible(batch, head, m_idx, n_idx, seqlen_info, aux_tensors):\n    m = cutlass.min(m_idx[0], seqlen_info.seqlen_q - 1)\n    n = cutlass.min(n_idx[0], seqlen_info.seqlen_k - 1)\n    image_q = aux_tensors[0][m]\n    image_k = aux_tensors[0][n]\n    same_image = (image_q >= 0) & (image_q == image_k)\n    allowed = ((n_idx[0] <= m_idx[0]) | same_image) & (n_idx[0] < seqlen_info.seqlen_k)\n    return utils.scalar_to_ssa(allowed, cutlass.Boolean)\n\ndef run(Q, K_current, V_current, image_ids):\n    return flash_attn_func(Q, K_current, V_current, softmax_scale=128 ** -0.5, mask_mod=visible, aux_tensors=[image_ids])[0]\n"
+    }
+  ]
 }
diff --git a/solutions/block_causal_attention/fa4_prefix_h32_d128.json b/solutions/block_causal_attention/fa4_prefix_h32_d128.json
index b58b69edf1e5a0a542a90af3bf50f0918132a7a2..9bb999aedea92198cb5cc81a3659f07f6991a9d1 100644
--- a/solutions/block_causal_attention/fa4_prefix_h32_d128.json
+++ b/solutions/block_causal_attention/fa4_prefix_h32_d128.json
@@ -2,7 +2,26 @@
   "name": "fa4_prefix_h32_d128",
   "definition": "prefix_cached_block_causal_h32_d128",
   "author": "inference-kernels",
-  "description": "FlashAttention 4 with causal-or-same-image visibility and runtime key validity. Prefix concatenation is part of the solution call. Upstream: https://github.com/Dao-AILab/flash-attention (BSD-3-Clause).",
-  "spec": {"language": "python", "target_hardware": ["NVIDIA_B200"], "entry_point": "main.py::run", "dependencies": ["torch>=2.11", "flash-attn-4==4.0.0b35", "nvidia-cutlass-dsl[cu13]==4.7.1", "quack-kernels==0.6.5"], "destination_passing_style": false},
-  "sources": [{"path": "main.py", "content": "import torch\nimport cutlass\nimport cutlass.cute as cute\nfrom flash_attn.cute import utils\nfrom flash_attn.cute.interface import flash_attn_func\n\n@cute.jit\ndef visible(batch, head, m_idx, n_idx, seqlen_info, aux_tensors):\n    offset = seqlen_info.seqlen_k - seqlen_info.seqlen_q\n    m = cutlass.min(m_idx[0] + offset, seqlen_info.seqlen_k - 1)\n    n = cutlass.min(n_idx[0], seqlen_info.seqlen_k - 1)\n    image_q = aux_tensors[0][m]\n    image_k = aux_tensors[0][n]\n    same_image = (image_q >= 0) & (image_q == image_k)\n    allowed = ((n_idx[0] <= m_idx[0] + offset) | same_image) & aux_tensors[1][batch[0], n]\n    return utils.scalar_to_ssa(allowed, cutlass.Boolean)\n\ndef run(Q, K_current, V_current, K_prefix, V_prefix, image_ids, key_valid, sm_scale):\n    K = torch.cat((K_prefix, K_current), dim=1) if K_prefix.shape[1] else K_current\n    V = torch.cat((V_prefix, V_current), dim=1) if V_prefix.shape[1] else V_current\n    return flash_attn_func(Q, K, V, softmax_scale=sm_scale, mask_mod=visible, aux_tensors=[image_ids, key_valid])[0]\n"}]
+  "description": "FlashAttention 4 for the engine target-image call, with its replicated KV prefix. All keys are visible; concatenation is included in run. Upstream: https://github.com/Dao-AILab/flash-attention (BSD-3-Clause).",
+  "spec": {
+    "language": "python",
+    "target_hardware": [
+      "NVIDIA_B200",
+      "NVIDIA_B300"
+    ],
+    "entry_point": "main.py::run",
+    "dependencies": [
+      "torch>=2.11",
+      "flash-attn-4==4.0.0b35",
+      "nvidia-cutlass-dsl[cu13]==4.8.0",
+      "quack-kernels==0.6.5"
+    ],
+    "destination_passing_style": false
+  },
+  "sources": [
+    {
+      "path": "main.py",
+      "content": "import torch\nfrom flash_attn.cute.interface import flash_attn_func\n\ndef run(Q, K_prefix, V_prefix, K_current, V_current):\n    keys = torch.cat((K_prefix, K_current), dim=1)\n    values = torch.cat((V_prefix, V_current), dim=1)\n    return flash_attn_func(Q, keys, values, softmax_scale=128 ** -0.5)[0]\n"
+    }
+  ]
 }
diff --git a/solutions/block_causal_attention/sglang_prefix_cached_block_causal_h32_d128.json b/solutions/block_causal_attention/sglang_prefix_cached_block_causal_h32_d128.json
index 99691eac652208011b81fe8475cf3a8eeaaa1826..a494d1d079fd15e87fd792e36bf254db9ee01e2c 100644
--- a/solutions/block_causal_attention/sglang_prefix_cached_block_causal_h32_d128.json
+++ b/solutions/block_causal_attention/sglang_prefix_cached_block_causal_h32_d128.json
@@ -17,7 +17,7 @@
   "sources": [
     {
       "path": "main.py",
-      "content": "# Copyright 2026 Co-developed by KDA (Kernel Design Agents)\n\"\"\"SGLang 684fea8a: Qwen-Image 2.1 ``target_attn`` under ``--attention-backend torch_sdpa``.\n\nCall path (``python/sglang/multimodal_gen/runtime/``):\n``models/dits/qwen_image21.py:703`` ``target_attn.forward_with_replicated_kv_prefix``\n(or ``qwen_image21.py:629-631`` ``attend_target`` -> ``target_attn(q, k, v)`` with the\nsame packed K/V) -> on one rank, ``layers/attention/layer.py:2116-2119``: concatenate\nthe prefix and current K/V, then ``attn_impl.forward`` -> ``SDPAImpl.forward``\n(``layers/attention/backends/sdpa.py:76-114``): torch SDPA, no mask, scale\n``head_dim**-0.5``.\n\nAdapters: ``USPAttention`` needs SGLang's global server args and parallel groups, so\nthe ``SDPAImpl`` it builds (``layer.py:849-850, 874-886``) is built here with the same\narguments. ``image_ids``, ``key_valid`` and ``sm_scale`` are not arguments of SGLang's\ncall: on every captured row each query sees every key and ``sm_scale`` is\n1/sqrt(128). The transposed SDPA output is copied into an owned dense tensor.\n\"\"\"\n\nimport torch\nfrom sglang.multimodal_gen.runtime.layers.attention.backends.sdpa import SDPAImpl\n\nHEADS, HEAD_DIM = 32, 128\nTARGET_IMPL = SDPAImpl(\n    num_heads=HEADS,\n    head_size=HEAD_DIM,\n    causal=False,\n    softmax_scale=HEAD_DIM**-0.5,\n    num_kv_heads=HEADS,\n)\n\n\ndef run(Q, K_current, V_current, K_prefix, V_prefix, image_ids, key_valid, sm_scale):\n    # layer.py:2117-2119\n    k = torch.cat([K_prefix, K_current], dim=1)\n    v = torch.cat([V_prefix, V_current], dim=1)\n    out = TARGET_IMPL.forward(Q, k, v, None)\n    return out.clone(memory_format=torch.contiguous_format)\n"
+      "content": "# Copyright 2026 Co-developed by KDA (Kernel Design Agents)\n\"\"\"SGLang 684fea8a: Qwen-Image 2.1 ``target_attn`` under ``--attention-backend torch_sdpa``.\n\nCall path (``python/sglang/multimodal_gen/runtime/``):\n``models/dits/qwen_image21.py:703`` ``target_attn.forward_with_replicated_kv_prefix``\n(or ``qwen_image21.py:629-631`` ``attend_target`` -> ``target_attn(q, k, v)`` with the\nsame packed K/V) -> on one rank, ``layers/attention/layer.py:2116-2119``: concatenate\nthe prefix and current K/V, then ``attn_impl.forward`` -> ``SDPAImpl.forward``\n(``layers/attention/backends/sdpa.py:76-114``): torch SDPA, no mask, scale\n``head_dim**-0.5``.\n\nAdapters: ``USPAttention`` needs SGLang's global server args and parallel groups, so\nthe ``SDPAImpl`` it builds (``layer.py:849-850, 874-886``) is built here with the same\narguments. Each captured target query sees every prefix/current key. The fixed scale is\n1/sqrt(128); redundant visibility/scale metadata is omitted. The native SDPA\noutput view is returned without an extra layout copy.\n\"\"\"\n\nimport torch\nfrom sglang.multimodal_gen.runtime.layers.attention.backends.sdpa import SDPAImpl\n\nHEADS, HEAD_DIM = 32, 128\nTARGET_IMPL = SDPAImpl(\n    num_heads=HEADS,\n    head_size=HEAD_DIM,\n    causal=False,\n    softmax_scale=HEAD_DIM**-0.5,\n    num_kv_heads=HEADS,\n)\n\n\ndef run(Q, K_prefix, V_prefix, K_current, V_current):\n    # layer.py:2117-2119\n    k = torch.cat([K_prefix, K_current], dim=1)\n    v = torch.cat([V_prefix, V_current], dim=1)\n    out = TARGET_IMPL.forward(Q, k, v, None)\n    return out.detach()\n"
     }
   ]
 }
diff --git a/solutions/block_causal_attention/sglang_prefix_cached_block_causal_h32_d128_prefix0.json b/solutions/block_causal_attention/sglang_prefix_cached_block_causal_h32_d128_prefix0.json
index c898236cfb9c4034fed2ea8663e5771094a75062..a92fde4472330f31273cd7c833c93ff5a47da58d 100644
--- a/solutions/block_causal_attention/sglang_prefix_cached_block_causal_h32_d128_prefix0.json
+++ b/solutions/block_causal_attention/sglang_prefix_cached_block_causal_h32_d128_prefix0.json
@@ -17,7 +17,7 @@
   "sources": [
     {
       "path": "main.py",
-      "content": "# Copyright 2026 Co-developed by KDA (Kernel Design Agents)\n\"\"\"SGLang 684fea8a: Qwen-Image 2.1 prefix attention under ``--attention-backend torch_sdpa``.\n\nCall path (``python/sglang/multimodal_gen/runtime/``):\n``models/dits/qwen_image21.py:651-667`` ``attend_sample`` without a cache: per prefix\nsegment, ``local_attn(qp[:, start:end], kp[:, :end], vp[:, :end], attn_mask=mask)``\nwith a causal bool mask for text runs and none for image blocks, joined by\n``cat_outputs`` (``qwen_image21.py:253-255``). ``LocalAttention.forward``\n(``layers/attention/layer.py:725-801``): with a mask, the bool mask made additive in\nbf16 and torch SDPA; without, ``SDPAImpl.forward`` (``backends/sdpa.py:76-114``).\n\nAdapters: ``local_attn`` is built as ``QwenImage21Attention.__init__`` builds it\n(``qwen_image21.py:395-398``), with the CLI backend forced through SGLang's selector,\nand run in SGLang's forward context. The engine's segments are the runs of\n``image_ids`` (text = -1); ``prepare`` derives them and their masks on the host.\n``K_prefix``/``V_prefix`` are empty (Np = 0), so ``kp, vp`` are the current K/V.\n``torch.cat`` replaces ``cat_outputs``, whose one-segment shortcut would return the\ntransposed SDPA view, so the output is an owned dense tensor. ``key_valid`` and\n``sm_scale`` are not arguments of SGLang's call: every captured key is valid and\n``sm_scale`` is 1/sqrt(128).\n\"\"\"\n\nimport torch\nfrom sglang.multimodal_gen.runtime.layers.attention import LocalAttention\nfrom sglang.multimodal_gen.runtime.layers.attention.selector import (\n    global_force_attn_backend_context_manager,\n)\nfrom sglang.multimodal_gen.runtime.managers.forward_context import set_forward_context\nfrom sglang.multimodal_gen.runtime.models.dits.qwen_image21 import (\n    QwenImage21Transformer2DModel,\n)\nfrom sglang.multimodal_gen.runtime.platforms import AttentionBackendEnum\n\nHEADS, HEAD_DIM = 32, 128\nwith global_force_attn_backend_context_manager(AttentionBackendEnum.TORCH_SDPA):\n    LOCAL_ATTN = LocalAttention(\n        HEADS,\n        HEAD_DIM,\n        supported_attention_backends=QwenImage21Transformer2DModel._supported_attention_backends,\n    )\n\n\ndef prepare(\n    Q, K_current, V_current, K_prefix, V_prefix, image_ids, key_valid, sm_scale\n):\n    ids = image_ids.cpu()\n    ends = torch.cumsum(torch.unique_consecutive(ids, return_counts=True)[1], 0)\n    segments = []\n    for start, end in zip([0, *ends[:-1].tolist()], ends.tolist()):\n        mask = None\n        if ids[start] < 0:\n            # qwen_image21.py:657-661\n            mask = (\n                torch.arange(end, device=Q.device)[None, :]\n                <= torch.arange(start, end, device=Q.device)[:, None]\n            )\n            mask = mask[None, None]\n        segments.append((start, end, mask))\n\n    def launch():\n        with set_forward_context(current_timestep=0, attn_metadata=None):\n            # qwen_image21.py:654-665\n            outputs = [\n                LOCAL_ATTN(\n                    Q[:, start:end],\n                    K_current[:, :end],\n                    V_current[:, :end],\n                    attn_mask=mask,\n                )\n                for start, end, mask in segments\n            ]\n        return torch.cat(outputs, dim=1)\n\n    return launch\n\n\ndef run(*inputs):\n    return prepare(*inputs)()\n"
+      "content": "# Copyright 2026 Co-developed by KDA (Kernel Design Agents)\n\"\"\"SGLang 684fea8a: Qwen-Image 2.1 prefix attention under ``--attention-backend torch_sdpa``.\n\nCall path (``python/sglang/multimodal_gen/runtime/``):\n``models/dits/qwen_image21.py:651-667`` ``attend_sample`` without a cache: per prefix\nsegment, ``local_attn(qp[:, start:end], kp[:, :end], vp[:, :end], attn_mask=mask)``\nwith a causal bool mask for text runs and none for image blocks, joined by\n``cat_outputs`` (``qwen_image21.py:253-255``). ``LocalAttention.forward``\n(``layers/attention/layer.py:725-801``): with a mask, the bool mask made additive in\nbf16 and torch SDPA; without, ``SDPAImpl.forward`` (``backends/sdpa.py:76-114``).\n\nAdapters: ``local_attn`` is built as ``QwenImage21Attention.__init__`` builds it\n(``qwen_image21.py:395-398``), with the CLI backend forced through SGLang's selector,\nand run in SGLang's forward context. The engine's segments are the runs of\n``image_ids`` (text = -1); ``prepare`` derives them and their masks on the host.\nThe current K/V are the complete uncached prefix; empty prefix inputs are omitted.\nThe one-segment shortcut matches ``cat_outputs`` and preserves the native output view. Every captured key is valid and scale is the engine's fixed 1/sqrt(128).\n\"\"\"\n\nimport torch\nfrom sglang.multimodal_gen.runtime.layers.attention import LocalAttention\nfrom sglang.multimodal_gen.runtime.layers.attention.selector import (\n    global_force_attn_backend_context_manager,\n)\nfrom sglang.multimodal_gen.runtime.managers.forward_context import set_forward_context\nfrom sglang.multimodal_gen.runtime.models.dits.qwen_image21 import (\n    QwenImage21Transformer2DModel,\n)\nfrom sglang.multimodal_gen.runtime.platforms import AttentionBackendEnum\n\nHEADS, HEAD_DIM = 32, 128\nwith global_force_attn_backend_context_manager(AttentionBackendEnum.TORCH_SDPA):\n    LOCAL_ATTN = LocalAttention(\n        HEADS,\n        HEAD_DIM,\n        supported_attention_backends=QwenImage21Transformer2DModel._supported_attention_backends,\n    )\n\n\ndef prepare(\n    Q, K_current, V_current, image_ids\n):\n    ids = image_ids.cpu()\n    ends = torch.cumsum(torch.unique_consecutive(ids, return_counts=True)[1], 0)\n    segments = []\n    for start, end in zip([0, *ends[:-1].tolist()], ends.tolist()):\n        mask = None\n        if ids[start] < 0:\n            # qwen_image21.py:657-661\n            mask = (\n                torch.arange(end, device=Q.device)[None, :]\n                <= torch.arange(start, end, device=Q.device)[:, None]\n            )\n            mask = mask[None, None]\n        segments.append((start, end, mask))\n\n    def launch():\n        with set_forward_context(current_timestep=0, attn_metadata=None):\n            # qwen_image21.py:654-665\n            outputs = [\n                LOCAL_ATTN(\n                    Q[:, start:end],\n                    K_current[:, :end],\n                    V_current[:, :end],\n                    attn_mask=mask,\n                )\n                for start, end, mask in segments\n            ]\n        return outputs[0] if len(outputs) == 1 else torch.cat(outputs, dim=1)\n\n    return launch\n\n\ndef run(Q, K_current, V_current, image_ids):\n    return prepare(Q, K_current, V_current, image_ids)()\n"
     }
   ]
 }
diff --git a/solutions/dense_attention/fa4_noncausal_h32_d128.json b/solutions/dense_attention/fa4_noncausal_h32_d128.json
index e4d7dab360c080a39ca03f0ef6f2c4356f9d4639..f8cdd11c0e0bdefbb2dcb7817967e1146fcb76ee 100644
--- a/solutions/dense_attention/fa4_noncausal_h32_d128.json
+++ b/solutions/dense_attention/fa4_noncausal_h32_d128.json
@@ -6,13 +6,14 @@
   "spec": {
     "language": "python",
     "target_hardware": [
-      "NVIDIA_B200"
+      "NVIDIA_B200",
+      "NVIDIA_B300"
     ],
     "entry_point": "main.py::run",
     "dependencies": [
       "torch>=2.11",
       "flash-attn-4==4.0.0b35",
-      "nvidia-cutlass-dsl[cu13]==4.7.1",
+      "nvidia-cutlass-dsl[cu13]==4.8.0",
       "quack-kernels==0.6.5"
     ],
     "destination_passing_style": false
@@ -20,7 +21,7 @@
   "sources": [
     {
       "path": "main.py",
-      "content": "from flash_attn.cute.interface import flash_attn_func\n\ndef run(Q, K, V, sm_scale):\n    return flash_attn_func(Q, K, V, softmax_scale=sm_scale)[0]\n"
+      "content": "from flash_attn.cute.interface import flash_attn_func\n\ndef run(Q, K, V):\n    return flash_attn_func(Q, K, V, softmax_scale=128 ** -0.5)[0]\n"
     }
   ]
 }
diff --git a/solutions/dense_attention/fa4_noncausal_h32_d64.json b/solutions/dense_attention/fa4_noncausal_h32_d64.json
index e29bb4d2d2cfaf6852bad0c9c8f9a85ea86f9603..4db8bafade873b429ade1d19c3a6df947de7f4ab 100644
--- a/solutions/dense_attention/fa4_noncausal_h32_d64.json
+++ b/solutions/dense_attention/fa4_noncausal_h32_d64.json
@@ -2,17 +2,18 @@
   "name": "fa4_noncausal_h32_d64",
   "definition": "noncausal_dense_attention_h32_d64",
   "author": "inference-kernels",
-  "description": "FlashAttention 4 CuTe DSL without a mask. Converts the captured normalized audio-attention inputs to FP16 to reduce probability-rounding error, and returns BF16. All conversions are included in the call. Upstream: https://github.com/Dao-AILab/flash-attention (BSD-3-Clause).",
+  "description": "BF16 FlashAttention-4 with native SDPA for self-attention tiles of at most 64 tokens. Removes the former FP16 input/output conversions. Every current workload passes the existing 99.99% element acceptance policy on B300; dispatch is based on runtime shape.",
   "spec": {
     "language": "python",
     "target_hardware": [
-      "NVIDIA_B200"
+      "NVIDIA_B200",
+      "NVIDIA_B300"
     ],
     "entry_point": "main.py::run",
     "dependencies": [
       "torch>=2.11",
       "flash-attn-4==4.0.0b35",
-      "nvidia-cutlass-dsl[cu13]==4.7.1",
+      "nvidia-cutlass-dsl[cu13]==4.8.0",
       "quack-kernels==0.6.5"
     ],
     "destination_passing_style": false
@@ -20,7 +21,7 @@
   "sources": [
     {
       "path": "main.py",
-      "content": "import torch\nfrom flash_attn.cute.interface import flash_attn_func\n\ndef run(Q, K, V, sm_scale):\n    output = flash_attn_func(Q.to(torch.float16), K.to(torch.float16), V.to(torch.float16), softmax_scale=sm_scale)[0]\n    return output.to(Q.dtype)\n"
+      "content": "import torch\nfrom torch.nn import functional as F\nfrom torch.nn.attention import SDPBackend, sdpa_kernel\nfrom flash_attn.cute.interface import flash_attn_func\n\n\ndef run(Q, K, V):\n    # B300 measurements favor native SDPA on the tiny self-attention tile.\n    if max(Q.shape[1], K.shape[1]) <= 64:\n        with sdpa_kernel([SDPBackend.CUDNN_ATTENTION, SDPBackend.FLASH_ATTENTION,\n                          SDPBackend.EFFICIENT_ATTENTION, SDPBackend.MATH],\n                         set_priority=True):\n            out = F.scaled_dot_product_attention(\n                Q.transpose(1, 2), K.transpose(1, 2), V.transpose(1, 2),\n                dropout_p=0.0, is_causal=False, scale=64 ** -0.5,\n            )\n        return out.transpose(1, 2)\n    return flash_attn_func(Q, K, V, softmax_scale=64 ** -0.5)[0]\n"
     }
   ]
 }
diff --git a/solutions/dense_attention/sglang_noncausal_dense_attention_h32_d128.json b/solutions/dense_attention/sglang_noncausal_dense_attention_h32_d128.json
index c52c16e69ee6de0ed92ba5e9813477f0c1be79df..db723d931f67f7490d565b6048c97748dd63b1db 100644
--- a/solutions/dense_attention/sglang_noncausal_dense_attention_h32_d128.json
+++ b/solutions/dense_attention/sglang_noncausal_dense_attention_h32_d128.json
@@ -17,7 +17,7 @@
   "sources": [
     {
       "path": "main.py",
-      "content": "# Copyright 2026 Co-developed by KDA (Kernel Design Agents)\n\"\"\"SGLang baseline for noncausal_dense_attention_h32_d128: LTX-2.5 video attention.\n\nSGLang diffusion runtime at commit 684fea8a, paths under\npython/sglang/multimodal_gen/runtime/: LTX2Attention.forward\n(models/dits/ltx_2.py:997-1006) calls ``self.attn(q, k, v, attn_mask=mask)``\non [B, N, H, D] Q/K/V for ``attn1`` (USPAttention, :857-871) and ``attn2``\n(LocalAttention, :841-855); every layer has\nsoftmax_scale=None -> head_size**-0.5 and allow_cudnn_sdp=True. On one GPU the\nmask is None, except for ``attn2``'s all-ones prompt mask, whose additive\nmask is exactly zero; the definition has no mask.\n\nUSPAttention.forward (layers/attention/layer.py:1466-1468) or\nLocalAttention.forward (:799) -> SDPAImpl.forward\n(layers/attention/backends/sdpa.py:76-114): one SDPA call under\n``sdpa_kernel(_PYTORCH_DEFAULT_CUDA_SDP_BACKENDS, set_priority=True)``, which\ntries cuDNN, Flash and memory-efficient attention before math.\n\nSDPAImpl returns a [B, Nq, H, D] transpose of the SDPA output;\n``.contiguous().detach()`` hands it over dense, without a copy when the kernel\nwrote it sequence-major.\n\"\"\"\n\nfrom sglang.multimodal_gen.runtime.layers.attention.backends.sdpa import SDPAImpl\n\n\ndef prepare(Q, K, V, sm_scale):\n    impl = SDPAImpl(\n        num_heads=Q.shape[2],\n        head_size=Q.shape[3],\n        causal=False,\n        softmax_scale=sm_scale,\n        num_kv_heads=K.shape[2],\n        allow_cudnn_sdp=True,\n    )\n\n    def launch():\n        return impl.forward(Q, K, V, None).contiguous().detach()\n\n    return launch\n\n\ndef run(Q, K, V, sm_scale):\n    return prepare(Q, K, V, sm_scale)()\n"
+      "content": "# Copyright 2026 Co-developed by KDA (Kernel Design Agents)\n\"\"\"SGLang baseline for noncausal_dense_attention_h32_d128: LTX-2.5 video attention.\n\nSGLang diffusion runtime at commit 684fea8a, paths under\npython/sglang/multimodal_gen/runtime/: LTX2Attention.forward\n(models/dits/ltx_2.py:997-1006) calls ``self.attn(q, k, v, attn_mask=mask)``\non [B, N, H, D] Q/K/V for ``attn1`` (USPAttention, :857-871) and ``attn2``\n(LocalAttention, :841-855); every layer has\nsoftmax_scale=None -> head_size**-0.5 and allow_cudnn_sdp=True. On one GPU the\nmask is None, except for ``attn2``'s all-ones prompt mask, whose additive\nmask is exactly zero; the definition has no mask.\n\nUSPAttention.forward (layers/attention/layer.py:1466-1468) or\nLocalAttention.forward (:799) -> SDPAImpl.forward\n(layers/attention/backends/sdpa.py:76-114): one SDPA call under\n``sdpa_kernel(_PYTORCH_DEFAULT_CUDA_SDP_BACKENDS, set_priority=True)``, which\ntries cuDNN, Flash and memory-efficient attention before math.\n\nSDPAImpl returns a [B, Nq, H, D] transpose of the SDPA output;\n``.detach()`` returns that native output view without adding a layout copy.\n\"\"\"\n\nfrom sglang.multimodal_gen.runtime.layers.attention.backends.sdpa import SDPAImpl\n\n\ndef prepare(Q, K, V):\n    impl = SDPAImpl(\n        num_heads=Q.shape[2],\n        head_size=Q.shape[3],\n        causal=False,\n        softmax_scale=128 ** -0.5,\n        num_kv_heads=K.shape[2],\n        allow_cudnn_sdp=True,\n    )\n\n    def launch():\n        return impl.forward(Q, K, V, None).detach()\n\n    return launch\n\n\ndef run(Q, K, V):\n    return prepare(Q, K, V)()\n"
     }
   ]
 }
diff --git a/solutions/dense_attention/sglang_noncausal_dense_attention_h32_d64.json b/solutions/dense_attention/sglang_noncausal_dense_attention_h32_d64.json
index e8da2b944acabada715ac87e0b14d36327f890ed..24019a4c8ea2ffb987849bfada33993ccb18c93f 100644
--- a/solutions/dense_attention/sglang_noncausal_dense_attention_h32_d64.json
+++ b/solutions/dense_attention/sglang_noncausal_dense_attention_h32_d64.json
@@ -17,7 +17,7 @@
   "sources": [
     {
       "path": "main.py",
-      "content": "# Copyright 2026 Co-developed by KDA (Kernel Design Agents)\n\"\"\"SGLang baseline for noncausal_dense_attention_h32_d64: LTX-2.5 audio attention.\n\nSGLang diffusion runtime at commit 684fea8a, paths under\npython/sglang/multimodal_gen/runtime/: LTX2Attention.forward\n(models/dits/ltx_2.py:997-1006) calls ``self.attn(q, k, v, attn_mask=mask)``\non [B, N, H, D] Q/K/V for ``audio_attn1``, ``audio_to_video_attn`` and\n``video_to_audio_attn`` (USPAttention, :857-871, or LocalAttention) and\n``audio_attn2`` (LocalAttention, :841-855); every layer has\nsoftmax_scale=None -> head_size**-0.5 and allow_cudnn_sdp=True. On one GPU the\nmask is None, except for ``audio_attn2``'s all-ones prompt mask, whose additive\nmask is exactly zero; the definition has no mask.\n\nUSPAttention.forward (layers/attention/layer.py:1466-1468) or\nLocalAttention.forward (:799) -> SDPAImpl.forward\n(layers/attention/backends/sdpa.py:76-114): one SDPA call under\n``sdpa_kernel(_PYTORCH_DEFAULT_CUDA_SDP_BACKENDS, set_priority=True)``, which\ntries cuDNN, Flash and memory-efficient attention before math.\n\nSDPAImpl returns a [B, Nq, H, D] transpose of the SDPA output;\n``.contiguous().detach()`` hands it over dense, without a copy when the kernel\nwrote it sequence-major.\n\"\"\"\n\nfrom sglang.multimodal_gen.runtime.layers.attention.backends.sdpa import SDPAImpl\n\n\ndef prepare(Q, K, V, sm_scale):\n    impl = SDPAImpl(\n        num_heads=Q.shape[2],\n        head_size=Q.shape[3],\n        causal=False,\n        softmax_scale=sm_scale,\n        num_kv_heads=K.shape[2],\n        allow_cudnn_sdp=True,\n    )\n\n    def launch():\n        return impl.forward(Q, K, V, None).contiguous().detach()\n\n    return launch\n\n\ndef run(Q, K, V, sm_scale):\n    return prepare(Q, K, V, sm_scale)()\n"
+      "content": "# Copyright 2026 Co-developed by KDA (Kernel Design Agents)\n\"\"\"SGLang baseline for noncausal_dense_attention_h32_d64: LTX-2.5 audio attention.\n\nSGLang diffusion runtime at commit 684fea8a, paths under\npython/sglang/multimodal_gen/runtime/: LTX2Attention.forward\n(models/dits/ltx_2.py:997-1006) calls ``self.attn(q, k, v, attn_mask=mask)``\non [B, N, H, D] Q/K/V for ``audio_attn1``, ``audio_to_video_attn`` and\n``video_to_audio_attn`` (USPAttention, :857-871, or LocalAttention) and\n``audio_attn2`` (LocalAttention, :841-855); every layer has\nsoftmax_scale=None -> head_size**-0.5 and allow_cudnn_sdp=True. On one GPU the\nmask is None, except for ``audio_attn2``'s all-ones prompt mask, whose additive\nmask is exactly zero; the definition has no mask.\n\nUSPAttention.forward (layers/attention/layer.py:1466-1468) or\nLocalAttention.forward (:799) -> SDPAImpl.forward\n(layers/attention/backends/sdpa.py:76-114): one SDPA call under\n``sdpa_kernel(_PYTORCH_DEFAULT_CUDA_SDP_BACKENDS, set_priority=True)``, which\ntries cuDNN, Flash and memory-efficient attention before math.\n\nSDPAImpl returns a [B, Nq, H, D] transpose of the SDPA output;\n``.detach()`` returns that native output view without adding a layout copy.\n\"\"\"\n\nfrom sglang.multimodal_gen.runtime.layers.attention.backends.sdpa import SDPAImpl\n\n\ndef prepare(Q, K, V):\n    impl = SDPAImpl(\n        num_heads=Q.shape[2],\n        head_size=Q.shape[3],\n        causal=False,\n        softmax_scale=64 ** -0.5,\n        num_kv_heads=K.shape[2],\n        allow_cudnn_sdp=True,\n    )\n\n    def launch():\n        return impl.forward(Q, K, V, None).detach()\n\n    return launch\n\n\ndef run(Q, K, V):\n    return prepare(Q, K, V)()\n"
     }
   ]
 }
diff --git a/solutions/gdn/flashinfer_gdn_decode.json b/solutions/gdn/flashinfer_gdn_decode.json
new file mode 100644
index 0000000000000000000000000000000000000000..8a1c2ac1d775002a0aa41a63f98bcd13f7976b09
--- /dev/null
+++ b/solutions/gdn/flashinfer_gdn_decode.json
@@ -0,0 +1,26 @@
+{
+  "name": "flashinfer_gdn_decode",
+  "definition": "gdn_decode_qk4_v8_d128_k_last",
+  "author": "inference-kernels",
+  "spec": {
+    "language": "python",
+    "target_hardware": [
+      "NVIDIA_B200",
+      "NVIDIA_B300"
+    ],
+    "entry_point": "main.py::run",
+    "dependencies": [
+      "torch>=2.14.1",
+      "flashinfer-python==0.7.2",
+      "nvidia-cutlass-dsl[cu13]==4.8.0"
+    ],
+    "destination_passing_style": false
+  },
+  "sources": [
+    {
+      "path": "main.py",
+      "content": "# SPDX-License-Identifier: Apache-2.0\nfrom flashinfer.gdn_decode import gated_delta_rule_decode_pretranspose\n\n\ndef run(q, k, v, state, A_log, a, dt_bias, b, scale):\n    effective_scale = q.shape[-1] ** -0.5 if scale is None or scale == 0 else scale\n    return gated_delta_rule_decode_pretranspose(\n        q=q, k=k, v=v, state=state.clone(), A_log=A_log, a=a,\n        dt_bias=dt_bias, b=b, scale=effective_scale, use_qk_l2norm=False,\n    )\n"
+    }
+  ],
+  "description": "FlashInfer 0.7.2 maintained GDN decode implementation. Honors the task scale and preserves input state. The contest task keeps its Q/K normalization and per-batch-state boundary; this is not the full SGLang state-pool interface. Upstream: https://github.com/flashinfer-ai/flashinfer/tree/d84335d8c54e0c8f9f7e22faa15c7e34a58abf94 (Apache-2.0)."
+}
diff --git a/solutions/gdn/flashinfer_gdn_prefill.json b/solutions/gdn/flashinfer_gdn_prefill.json
new file mode 100644
index 0000000000000000000000000000000000000000..353f27fd6f891186a7fce6c7033e3cc5e476a976
--- /dev/null
+++ b/solutions/gdn/flashinfer_gdn_prefill.json
@@ -0,0 +1,26 @@
+{
+  "name": "flashinfer_gdn_prefill",
+  "definition": "gdn_prefill_qk4_v8_d128_k_last",
+  "author": "inference-kernels",
+  "spec": {
+    "language": "python",
+    "target_hardware": [
+      "NVIDIA_B200",
+      "NVIDIA_B300"
+    ],
+    "entry_point": "main.py::run",
+    "dependencies": [
+      "torch>=2.14.1",
+      "flashinfer-python==0.7.2",
+      "nvidia-cutlass-dsl[cu13]==4.8.0"
+    ],
+    "destination_passing_style": false
+  },
+  "sources": [
+    {
+      "path": "main.py",
+      "content": "# SPDX-License-Identifier: Apache-2.0\nimport torch\nimport torch.nn.functional as F\nfrom flashinfer.gdn_prefill import chunk_gated_delta_rule\n\n\ndef run(q, k, v, state, A_log, a, dt_bias, b, cu_seqlens, scale):\n    alpha = torch.exp(-torch.exp(A_log.float()) * F.softplus(a.float() + dt_bias.float()))\n    beta = torch.sigmoid(b.float())\n    effective_scale = q.shape[-1] ** -0.5 if scale is None or scale == 0 else scale\n    return chunk_gated_delta_rule(\n        q=q, k=k, v=v, g=alpha, beta=beta, scale=effective_scale,\n        initial_state=state, output_final_state=True, cu_seqlens=cu_seqlens,\n        use_qk_l2norm_in_kernel=False,\n    )\n"
+    }
+  ],
+  "description": "FlashInfer 0.7.2 maintained GDN prefill implementation. Honors the task scale and preserves input state. The contest task keeps its Q/K normalization and per-batch-state boundary; this is not the full SGLang state-pool interface. Upstream: https://github.com/flashinfer-ai/flashinfer/tree/d84335d8c54e0c8f9f7e22faa15c7e34a58abf94 (Apache-2.0)."
+}
diff --git a/solutions/gdn/flashinfer_wrapper_123ca6.json b/solutions/gdn/flashinfer_wrapper_123ca6.json
deleted file mode 100644
index 908289d8b092e4321776d4522bc037f5d326bbe9..0000000000000000000000000000000000000000
--- a/solutions/gdn/flashinfer_wrapper_123ca6.json
+++ /dev/null
@@ -1,40 +0,0 @@
-{
-  "name": "flashinfer_wrapper_123ca6",
-  "definition": "gdn_prefill_qk4_v8_d128_k_last",
-  "author": "flashinfer",
-  "spec": {
-    "language": "python",
-    "target_hardware": [
-      "NVIDIA B200"
-    ],
-    "entry_point": "main.py::run",
-    "dependencies": [
-      "cutlass",
-      "cuda-python"
-    ],
-    "destination_passing_style": false
-  },
-  "sources": [
-    {
-      "path": "main.py",
-      "content": "import torch\nimport torch.nn.functional as F\nfrom .gdn_blackwell.gdn import chunk_gated_delta_rule\n\n\ndef run(q, k, v, state, A_log, a, dt_bias, b, cu_seqlens, scale):\n    x = a.float() + dt_bias.float()\n    # Gate values in log-space: log(exp(-exp(A_log) * softplus(x))) = -exp(A_log) * softplus(x)\n    g = -torch.exp(A_log.float()) * F.softplus(x)\n    beta = torch.sigmoid(b.float())\n\n    varlen = cu_seqlens is not None and q.dim() == 3\n    if varlen:\n        q = q.unsqueeze(0)\n        k = k.unsqueeze(0)\n        v = v.unsqueeze(0)\n\n    output, new_state = chunk_gated_delta_rule(\n        q=q,\n        k=k,\n        v=v,\n        g=g,\n        beta=beta,\n        scale=None,\n        initial_state=state,\n        output_final_state=True,\n        cu_seqlens=cu_seqlens,\n        use_qk_l2norm_in_kernel=False,\n    )\n\n    if varlen:\n        output = output.squeeze(0)\n\n    return output, new_state\n"
-    },
-    {
-      "path": "gdn_blackwell/__init__.py",
-      "content": "# Blackwell GDN kernel package\n"
-    },
-    {
-      "path": "gdn_blackwell/gdn.py",
-      "content": "\"\"\"\nCopyright (c) 2026 by FlashInfer team.\n\nLicensed under the Apache License, Version 2.0 (the \"License\");\nyou may not use this file except in compliance with the License.\nYou may obtain a copy of the License at\n\n  http://www.apache.org/licenses/LICENSE-2.0\n\nUnless required by applicable law or agreed to in writing, software\ndistributed under the License is distributed on an \"AS IS\" BASIS,\nWITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\nSee the License for the specific language governing permissions and\nlimitations under the License.\n\"\"\"\n\n# Gated Delta Networks (GDN) chunked linear attention kernel for NVIDIA Blackwell (SM100).\n#\n# Implements the Chunk-wise Gated Delta Rule linear attention using CuTe-DSL,\n# for Blackwell Architecture.\n#\n# Key Features:\n#   - Supports Persistent & Non-persistent modes\n#   - Supports fixed-length and variable-length sequences (cu_seqlens)\n#   - Supports grouped value attention (GVA) where h_v is a multiple of h_q\n#   - Supports head dimension (128)\n#   - Supports input data types (f16/bf16)\n#   - Supports output data types (f16/bf16)\n#   - Supports initial_state to provide the initial state\n#   - Supports output_final_state flag to return the final state\n#   - State input and output are in f32 (fp16/bf16 not supported yet)\n\nimport torch\n\nfrom typing import Optional, Type, Tuple, Union\n\nimport cutlass\nimport cutlass.cute as cute\nimport cutlass.utils as utils\nimport cutlass.pipeline as pipeline\nimport cutlass.cute.nvgpu.tcgen05 as tcgen05\nimport cutlass.utils.blackwell_helpers as sm100_utils\nfrom cutlass.cute.runtime import from_dlpack\nfrom cutlass._mlir.dialects import nvvm\n\nimport cuda.bindings.driver as cuda\n\n\nfrom .gdn_tile_scheduler import *\nfrom .gdn_helpers import *\n\nimport functools\nimport warnings\n\nfrom cutlass.cute import EnableTVMFFI\n\n\ndef make_thread_cooperative_group(size: Int32):\n    # return pipeline.CooperativeGroup(pipeline.Agent.Thread, size, size) # old version\n    return pipeline.CooperativeGroup(pipeline.Agent.Thread, size)\n\n\nclass GDN:\n    \"\"\"Blackwell (SM100) kernel for Chunk-wise Gated Delta Rule linear attention.\"\"\"\n\n    def __init__(\n        self,\n        is_persistent: bool = False,\n        chunk_size: Int32 = 128,  # Only 128 is supported in current version\n        head_dim: Int32 = 128,  # Only 128 is supported in current version\n    ):\n        self.chunk_size = chunk_size\n        self.is_persistent = is_persistent\n\n        self.head_dim = head_dim\n        self.cta_tiler = (chunk_size, chunk_size, head_dim)\n        self.gate_tiler = (chunk_size, 1)\n        self.beta_tiler = (chunk_size, 1)\n        self.state_output_tiler = (head_dim, head_dim)\n        self.o_output_tiler = (chunk_size, head_dim)\n\n        self.g_beta_dtype = cutlass.Float32\n        self.acc_dtype = cutlass.Float32\n        self.state_dtype = cutlass.Float32\n\n        self.mma_tiler = (chunk_size, chunk_size, head_dim)\n        self.qk_mma_tiler = self.mma_tiler\n        self.kkt_mma_tiler = self.mma_tiler\n        self.kst_mma_tiler = self.mma_tiler\n        self.tuw_mma_tiler = self.mma_tiler\n        self.o_intra_mma_tiler = (chunk_size, head_dim, chunk_size)\n        self.qs_mma_tiler = (chunk_size, head_dim, head_dim)\n        self.update_s_mma_tiler = (head_dim, head_dim, chunk_size)\n\n        self.epi_tile = (128, 128)\n\n        self.cluster_shape_mnk = (1, 1, 1)\n\n        self.buffer_align_bytes = 1024\n\n        self.q_stage = 1\n        self.one_stage = 1\n        self.kv_stage = 1\n        self.qk_stage = 2\n        self.gate_stage = 1\n        self.beta_stage = 1\n        self.mma_cudacore_stage = 1\n        self.mma_qk_stage = 2\n        self.epi_stage = 1\n\n        self.cudacore_warp_ids = (0, 1, 2, 3)\n        self.mma_warp_id = 4\n        self.load_warp_id = 5\n        self.epilogue_warp_id = 6\n        self.gb_warp_id = 7\n\n        self.threads_per_warp = 32\n        self.threads_per_cta = self.threads_per_warp * len(\n            (\n                *self.cudacore_warp_ids,\n                self.mma_warp_id,\n                self.load_warp_id,\n                self.epilogue_warp_id,\n                self.gb_warp_id,\n            )\n        )\n\n        # TMEM configuration\n        SM100_TMEM_CAPACITY_COLUMNS = 512\n        self.tmem_alloc_cols = SM100_TMEM_CAPACITY_COLUMNS\n        self.tmem_kkt_output = 0\n        self.tmem_qkt_output = 384\n        self.tmem_gate_qk = 384\n        self.tmem_gate_q = 448  # 448\n        self.tmem_k_input = 64\n        self.tmem_kst_output = 256\n        self.tmem_ivt_ss_l0_output = 448\n        self.tmem_ivt_ts_l0_input = 320\n        self.tmem_ivt_ts_l0_output = 448\n        self.tmem_ivt_ss_l1_output = 320\n        self.tmem_ivt_ts_l1_input = 320\n        self.tmem_ivt_ts_l1_output = 256\n        self.tmem_tuw_output = 256\n        self.tmem_o_intra_output = 256\n        self.tmem_o_inter_output = 256\n        self.tmem_update_s_output = 128\n        self.tmem_gamma = 256\n\n        self.tmem_state = 128\n\n        # Registers configuration\n        self.num_regs_cudacore = 240\n        self.num_regs_mma = 64\n        self.num_regs_other = 64\n        self.num_regs_gb = 64\n\n        # Named barrier IDs\n        self.cta_sync_bar_id = 0\n        self.tmem_alloc_sync_bar_id = 1\n        self.cudacore_mma_sync_bar_id = 2\n        self.wg_sync_bar_id = 3\n        self.epi_load_sync_bar_id = 4\n\n        # Matrix inversion using TFloat32\n        self.invert_type_ab = cutlass.TFloat32\n        self.invert_acc_type = cutlass.Float32\n        self.invert_mma_sub_l0_tiler = (64, 64, 32)\n        self.invert_mma_sub_l1_tiler = (64, 64, 64)\n        self.invert_mma_tiler = (128, 128, 64)\n        self.invert_sub_stage = 1\n        self.sub_stage = 9\n\n    @staticmethod\n    def can_implement(\n        q_shape: Tuple[int, int, int, int] | Tuple[int, Tuple[int, ...], int, int],\n        v_shape: Tuple[int, int, int, int] | Tuple[int, Tuple[int, ...], int, int],\n        in_dtype: Type[cutlass.Numeric],\n        out_dtype: Type[cutlass.Numeric],\n        g_beta_dtype: Type[cutlass.Numeric],\n        use_qk_l2norm_in_kernel: bool = False,\n    ) -> bool:\n        \"\"\"\n        Check if the gdn can be implemented\n        \"\"\"\n\n        can_implement = True\n\n        # Unpack parameters\n        b, s_q, h_q, d = q_shape\n        b_, _, h_v, d_ = v_shape\n\n        if use_qk_l2norm_in_kernel:\n            warnings.warn(\"use_qk_l2norm_in_kernel is not supported yet\", stacklevel=2)\n            can_implement = False\n\n        if b != b_:\n            warnings.warn(\"q & k must have the same batch size\", stacklevel=2)\n            can_implement = False\n\n        if d != d_:\n            warnings.warn(\"q & k must have the same head dimension\", stacklevel=2)\n            can_implement = False\n\n        # todo: maybe support more later.\n        if d not in {128}:\n            warnings.warn(\"head dimension must be 128\", stacklevel=2)\n            can_implement = False\n\n        if h_v % h_q != 0:\n            warnings.warn(\"h_v must be divisible by h_q\", stacklevel=2)\n\n            can_implement = False\n\n        if isinstance(s_q, tuple) and len(s_q) != b:\n            warnings.warn(\n                \"variable_seqlen s_q must have the length of batch size\", stacklevel=2\n            )\n            can_implement = False\n\n        if in_dtype not in {\n            cutlass.BFloat16,\n            cutlass.Float16,\n            torch.float16,\n            torch.bfloat16,\n        }:\n            warnings.warn(\n                \"in_dtype must be BFloat16 or Float16 or torch.float16 or torch.bfloat16\",\n                stacklevel=2,\n            )\n            can_implement = False\n\n        if out_dtype not in {\n            cutlass.BFloat16,\n            cutlass.Float16,\n            torch.float16,\n            torch.bfloat16,\n        }:\n            warnings.warn(\n                \"out_dtype must be BFloat16 or Float16 or torch.float16 or torch.bfloat16\",\n                stacklevel=2,\n            )\n            can_implement = False\n\n        if g_beta_dtype not in {cutlass.Float32, torch.float32}:\n            warnings.warn(\n                \"g_beta_dtype must be Float32 or torch.float32, but got {}\".format(\n                    g_beta_dtype\n                ),\n                stacklevel=2,\n            )\n            can_implement = False\n\n        return can_implement\n\n    @cute.kernel\n    def kernel(\n        self,\n        qk_tiled_mma: cute.TiledMma,\n        o_intra_tiled_mma: cute.TiledMma,\n        o_intra_tiled_ts_mma_new: cute.TiledMma,\n        qs_tiled_mma: cute.TiledMma,\n        update_s_tiled_mma: cute.TiledMma,\n        kkt_tiled_mma: cute.TiledMma,\n        kst_tiled_mma: cute.TiledMma,\n        fake_state_tiled_mma: cute.TiledMma,\n        invert_sub_tiled_mma_ss_l0: cute.TiledMma,\n        invert_sub_tiled_mma_ts_l0: cute.TiledMma,\n        invert_sub_tiled_mma_ss_l1: cute.TiledMma,\n        invert_sub_tiled_mma_ts_l1: cute.TiledMma,\n        tuw_tiled_mma: cute.TiledMma,\n        tma_atom_q: cute.CopyAtom,\n        mQ_qdl: cute.Tensor,\n        tma_atom_k: cute.CopyAtom,\n        mK_kdl: cute.Tensor,\n        tma_atom_v: cute.CopyAtom,\n        mV_dkl: cute.Tensor,\n        tma_atom_state_f32: Optional[cute.CopyAtom],\n        mState_f32: Optional[cute.Tensor],\n        gate: cute.Tensor,\n        beta: cute.Tensor,\n        O: cute.Tensor,\n        tma_atom_state_output: Optional[cute.CopyAtom],\n        mStateOutput: Optional[cute.Tensor],\n        tma_atom_o_output: cute.CopyAtom,\n        mO_qdl: cute.Tensor,\n        cum_seqlen_q: Optional[cute.Tensor],\n        q_smem_layout_staged: cute.ComposedLayout,\n        k_smem_layout_staged: cute.ComposedLayout,\n        qk_smem_layout_staged: cute.ComposedLayout,\n        o_intra_smem_layout_staged_a: cute.ComposedLayout,\n        o_intra_smem_layout_staged_b: cute.ComposedLayout,\n        o_intra_smem_layout_staged_a_new: cute.ComposedLayout,\n        qs_smem_layout_staged_a: cute.ComposedLayout,\n        qs_smem_layout_staged_b: cute.ComposedLayout,\n        update_s_smem_layout_staged_a: cute.ComposedLayout,\n        update_s_smem_layout_staged_b: cute.ComposedLayout,\n        state_smem_layout_staged: cute.ComposedLayout,\n        state_smem_layout_f32_staged: cute.ComposedLayout,\n        state_output_smem_layout_staged: cute.ComposedLayout,\n        o_output_smem_layout_staged: cute.ComposedLayout,\n        gate_smem_layout_staged: cute.Layout,\n        beta_smem_layout_staged: cute.Layout,\n        ivt_smem_layout: cute.Layout,\n        sub_inner_smem_layout_staged: cute.ComposedLayout,\n        invert_sub_smem_layout_staged_ss_l0_a: cute.ComposedLayout,\n        invert_sub_smem_layout_staged_ss_l0_b: cute.ComposedLayout,\n        invert_sub_smem_layout_staged_ts_l0_a: cute.ComposedLayout,\n        invert_sub_smem_layout_staged_ts_l0_b: cute.ComposedLayout,\n        invert_sub_smem_layout_staged_ss_l1_a: cute.ComposedLayout,\n        invert_sub_smem_layout_staged_ss_l1_b: cute.ComposedLayout,\n        invert_sub_smem_layout_staged_ts_l1_a: cute.ComposedLayout,\n        invert_sub_smem_layout_staged_ts_l1_b: cute.ComposedLayout,\n        tuw_smem_layout_staged_a: cute.ComposedLayout,\n        tuw_smem_layout_staged_b: cute.ComposedLayout,\n        v_smem_layout_staged_b: cute.ComposedLayout,\n        scale: cutlass.Float32,\n        tile_sched_params: GdnStaticTileSchedulerParams,\n    ):\n        \"\"\"Warp-specialized GDN kernel entry point.\"\"\"\n        tidx, _, _ = cute.arch.thread_idx()\n        warp_idx = cute.arch.make_warp_uniform(cute.arch.warp_idx())\n\n        # Prefetch TMA descriptors\n        if warp_idx == self.load_warp_id:\n            cute.nvgpu.cpasync.prefetch_descriptor(tma_atom_q)\n            cute.nvgpu.cpasync.prefetch_descriptor(tma_atom_k)\n            cute.nvgpu.cpasync.prefetch_descriptor(tma_atom_v)\n            cute.nvgpu.cpasync.prefetch_descriptor(tma_atom_o_output)\n            if cutlass.const_expr(tma_atom_state_f32 is not None):\n                cute.nvgpu.cpasync.prefetch_descriptor(tma_atom_state_f32)\n            if cutlass.const_expr(tma_atom_state_output is not None):\n                cute.nvgpu.cpasync.prefetch_descriptor(tma_atom_state_output)\n\n        # Alloc\n        smem = utils.SmemAllocator()\n        storage = smem.allocate(self.shared_storage)\n\n        load_qk_producer, load_qk_consumer = pipeline.PipelineTmaUmma.create(\n            num_stages=self.qk_stage,\n            producer_group=make_thread_cooperative_group(len([self.load_warp_id])),\n            consumer_group=make_thread_cooperative_group(len([self.mma_warp_id])),\n            tx_count=self.tma_copy_kv_bytes,\n            barrier_storage=storage.load_qk_mbar_ptr.data_ptr(),\n        ).make_participants()\n\n        load_v_producer, load_v_consumer = pipeline.PipelineTmaAsync.create(\n            num_stages=self.one_stage,\n            producer_group=make_thread_cooperative_group(len([self.load_warp_id])),\n            consumer_group=make_thread_cooperative_group(\n                len(self.cudacore_warp_ids),\n            ),\n            tx_count=self.tma_copy_v_bytes,\n            barrier_storage=storage.load_v_mbar_ptr.data_ptr(),\n        ).make_participants()\n\n        load_state_producer, load_state_consumer = pipeline.PipelineTmaAsync.create(\n            num_stages=self.one_stage,\n            producer_group=make_thread_cooperative_group(len([self.load_warp_id])),\n            consumer_group=make_thread_cooperative_group(len(self.cudacore_warp_ids)),\n            tx_count=self.tma_copy_state_f32_bytes,\n            barrier_storage=storage.load_state_mbar_ptr.data_ptr(),\n        ).make_participants()\n\n        mma_qk_producer0, mma_qk_consumer0 = pipeline.PipelineUmmaAsync.create(\n            num_stages=self.mma_qk_stage,\n            producer_group=make_thread_cooperative_group(len([self.mma_warp_id])),\n            consumer_group=make_thread_cooperative_group(\n                self.threads_per_warp * len(self.cudacore_warp_ids)\n            ),\n            barrier_storage=storage.mma_qk_mbar_ptr0.data_ptr(),\n        ).make_participants()\n\n        mma_cudacore_producer0, mma_cudacore_consumer0 = (\n            pipeline.PipelineUmmaAsync.create(\n                num_stages=self.mma_cudacore_stage,\n                producer_group=make_thread_cooperative_group(len([self.mma_warp_id])),\n                consumer_group=make_thread_cooperative_group(\n                    self.threads_per_warp * len(self.cudacore_warp_ids)\n                ),\n                barrier_storage=storage.mma_cudacore_mbar_ptr0.data_ptr(),\n            ).make_participants()\n        )\n\n        gb_w0_producer, gb_w0_consumer = pipeline.PipelineAsync.create(\n            num_stages=self.gate_stage,\n            producer_group=make_thread_cooperative_group(self.threads_per_warp),\n            consumer_group=make_thread_cooperative_group(\n                self.threads_per_warp * len(self.cudacore_warp_ids)\n            ),\n            barrier_storage=storage.gb_w0_mbar_ptr.data_ptr(),\n        ).make_participants()\n\n        epi_w0_producer, epi_w0_consumer = pipeline.PipelineAsync.create(\n            num_stages=self.epi_stage,\n            producer_group=make_thread_cooperative_group(self.threads_per_warp),\n            consumer_group=make_thread_cooperative_group(\n                self.threads_per_warp * len(self.cudacore_warp_ids)\n            ),\n            barrier_storage=storage.epi_w0_mbar_ptr.data_ptr(),\n        ).make_participants()\n\n        w0_epi_producer, w0_epi_consumer = pipeline.PipelineAsync.create(\n            num_stages=self.epi_stage,\n            producer_group=make_thread_cooperative_group(\n                self.threads_per_warp * len(self.cudacore_warp_ids)\n            ),\n            consumer_group=make_thread_cooperative_group(self.threads_per_warp),\n            barrier_storage=storage.w0_epi_mbar_ptr.data_ptr(),\n        ).make_participants()\n\n        tmem_dealloc_mbar_ptr = storage.tmem_dealloc_mbar_ptr.data_ptr()\n\n        #  tmem barrier init\n        if warp_idx == self.gb_warp_id:\n            cute.arch.mbarrier_init(\n                tmem_dealloc_mbar_ptr,\n                self.threads_per_warp * len((*self.cudacore_warp_ids,)),\n            )\n        cute.arch.mbarrier_init_fence()\n\n        sQK = storage.sQK.get_tensor(\n            qk_smem_layout_staged.outer, swizzle=qk_smem_layout_staged.inner\n        )\n        sQ = cute.make_tensor(\n            cute.recast_ptr(\n                sQK[None, None, None, 1].iterator,\n                swizzle_=q_smem_layout_staged.inner,\n                dtype=self.i_dtype,\n            ),\n            q_smem_layout_staged.outer,\n        )\n        sK = cute.make_tensor(\n            cute.recast_ptr(\n                sQK[None, None, None, 0].iterator,\n                swizzle_=k_smem_layout_staged.inner,\n                dtype=self.i_dtype,\n            ),\n            k_smem_layout_staged.outer,\n        )\n        sStateInput = cute.make_tensor(\n            cute.recast_ptr(\n                storage.sState.data_ptr(),\n                swizzle_=state_smem_layout_staged.inner,\n                dtype=self.i_dtype,\n            ),\n            state_smem_layout_staged.outer,\n        )\n        sV = cute.make_tensor(\n            cute.recast_ptr(\n                storage.sV.data_ptr(),\n                swizzle_=v_smem_layout_staged_b.inner,\n                dtype=self.i_dtype,\n            ),\n            v_smem_layout_staged_b.outer,\n        )\n\n        sGate = storage.sGate.get_tensor(gate_smem_layout_staged)\n        sBeta = storage.sBeta.get_tensor(beta_smem_layout_staged)\n        sGateCumsum = storage.sGateCumsum.get_tensor(\n            cute.select(gate_smem_layout_staged, mode=[0, 1])\n        )\n        sSubInner = storage.sSubInner.get_tensor(sub_inner_smem_layout_staged)\n        sInvertSubSSL0A = cute.make_tensor(\n            cute.recast_ptr(\n                sSubInner[None, None, None, 6].iterator,\n                swizzle_=invert_sub_smem_layout_staged_ss_l0_a.inner,\n                dtype=self.invert_type_ab,\n            ),\n            invert_sub_smem_layout_staged_ss_l0_a.outer,\n        )\n\n        sInvertSubSSL0B = cute.make_tensor(\n            cute.recast_ptr(\n                sSubInner[None, None, None, 7].iterator,\n                swizzle_=invert_sub_smem_layout_staged_ss_l0_b.inner,\n                dtype=self.invert_type_ab,\n            ),\n            invert_sub_smem_layout_staged_ss_l0_b.outer,\n        )\n        sInvertSubTSL0B = cute.make_tensor(\n            cute.recast_ptr(\n                sSubInner[None, None, None, 8].iterator,\n                swizzle_=invert_sub_smem_layout_staged_ts_l0_b.inner,\n                dtype=self.invert_type_ab,\n            ),\n            invert_sub_smem_layout_staged_ts_l0_b.outer,\n        )\n        sInvertSubSSL1A = cute.make_tensor(\n            cute.recast_ptr(\n                sSubInner[None, None, None, 0].iterator,\n                swizzle_=invert_sub_smem_layout_staged_ss_l1_a.inner,\n                dtype=self.invert_type_ab,\n            ),\n            invert_sub_smem_layout_staged_ss_l1_a.outer,\n        )\n        sInvertSubSSL1B = cute.make_tensor(\n            cute.recast_ptr(\n                sSubInner[None, None, None, 2].iterator,\n                swizzle_=invert_sub_smem_layout_staged_ss_l1_b.inner,\n                dtype=self.invert_type_ab,\n            ),\n            invert_sub_smem_layout_staged_ss_l1_b.outer,\n        )\n        sInvertSubTSL1B = cute.make_tensor(\n            cute.recast_ptr(\n                sSubInner[None, None, None, 6].iterator,\n                swizzle_=invert_sub_smem_layout_staged_ts_l1_b.inner,\n                dtype=self.invert_type_ab,\n            ),\n            invert_sub_smem_layout_staged_ts_l1_b.outer,\n        )\n\n        sInvertSubReg = cute.make_tensor(\n            cute.recast_ptr(\n                sSubInner[None, None, None, 4].iterator, dtype=self.invert_type_ab\n            ),\n            cute.make_layout(((4, 128), 8)),\n        )\n\n        sStateInputF32 = cute.make_tensor(\n            cute.recast_ptr(\n                sSubInner[None, None, None, 0].iterator,\n                swizzle_=state_smem_layout_f32_staged.inner,\n                dtype=self.state_dtype,\n            ),\n            state_smem_layout_f32_staged.outer,\n        )\n        sStateOutput = cute.make_tensor(\n            cute.recast_ptr(\n                sQK[None, None, None, 0].iterator,\n                swizzle_=state_output_smem_layout_staged.inner,\n                dtype=self.state_dtype,\n            ),\n            state_output_smem_layout_staged.outer,\n        )\n\n        sOIntraB = cute.make_tensor(\n            cute.recast_ptr(\n                sSubInner[None, None, None, 4].iterator,\n                swizzle_=o_intra_smem_layout_staged_b.inner,\n                dtype=self.i_dtype,\n            ),\n            o_intra_smem_layout_staged_b.outer,\n        )\n        sQSB = cute.make_tensor(\n            cute.recast_ptr(\n                storage.sState.data_ptr(),\n                swizzle_=qs_smem_layout_staged_b.inner,\n                dtype=self.i_dtype,\n            ),\n            qs_smem_layout_staged_b.outer,\n        )\n\n        sUpdateA = cute.make_tensor(\n            cute.recast_ptr(\n                sSubInner[None, None, None, 4].iterator,\n                swizzle_=update_s_smem_layout_staged_a.inner,\n                dtype=self.i_dtype,\n            ),\n            update_s_smem_layout_staged_a.outer,\n        )\n        sUpdateB = cute.make_tensor(\n            cute.recast_ptr(\n                sSubInner[None, None, None, 0].iterator,\n                swizzle_=update_s_smem_layout_staged_b.inner,\n                dtype=self.i_dtype,\n            ),\n            update_s_smem_layout_staged_b.outer,\n        )\n\n        sO = cute.make_tensor(\n            cute.recast_ptr(\n                storage.sState.data_ptr(),\n                swizzle_=o_output_smem_layout_staged.inner,\n                dtype=self.i_dtype,\n            ),\n            o_output_smem_layout_staged.outer,\n        )\n        sIvt = storage.sIvt.get_tensor(ivt_smem_layout)\n\n        sTuwA = cute.make_tensor(\n            cute.recast_ptr(\n                sSubInner[None, None, None, 0].iterator,\n                swizzle_=tuw_smem_layout_staged_a.inner,\n                dtype=self.i_dtype,\n            ),\n            tuw_smem_layout_staged_a.outer,\n        )\n        sTuwB = cute.make_tensor(\n            cute.recast_ptr(storage.sV.data_ptr(), dtype=self.k_dtype),\n            tuw_smem_layout_staged_b,\n        )\n        sTuwAStore_layout = cute.make_layout(\n            ((128, (4, 2)), 8), stride=((4, (1, 512)), 1024)\n        )\n        sTuwAStore = cute.make_tensor(\n            cute.recast_ptr(sTuwA.iterator, dtype=cutlass.Float32), sTuwAStore_layout\n        )\n\n        if warp_idx == self.epilogue_warp_id:\n            # Alloc tmem buffer\n            tmem_alloc_cols = cutlass.Int32(self.tmem_alloc_cols)\n            cute.arch.alloc_tmem(tmem_alloc_cols, storage.tmem_holding_buf)\n\n        # Ensure visibility of local mbarrier inits and tmem alloc\n        cute.arch.sync_threads()\n\n        tmem_ptr = cute.arch.retrieve_tmem_ptr(\n            self.acc_dtype,\n            alignment=16,\n            ptr_to_buffer_holding_addr=storage.tmem_holding_buf,\n        )\n\n        qk_thr_mma = qk_tiled_mma.get_slice(0)  # default 1sm\n        tSrQ = qk_thr_mma.make_fragment_A(sQK)\n        tSrK = qk_thr_mma.make_fragment_B(sQK)\n        qk_acc_shape = qk_thr_mma.partition_shape_C(\n            (self.qk_mma_tiler[0], self.qk_mma_tiler[1])\n        )\n        tQKtQK_fake = qk_thr_mma.make_fragment_C(qk_acc_shape)\n        tQKtQK = cute.make_tensor(tmem_ptr + self.tmem_qkt_output, tQKtQK_fake.layout)\n\n        kkt_thr_mma = kkt_tiled_mma.get_slice(0)  # default 1sm\n        tArK = kkt_thr_mma.make_fragment_A(sQK)\n        tArKT = kkt_thr_mma.make_fragment_B(sQK)\n        kkt_acc_shape = kkt_thr_mma.partition_shape_C(\n            (self.kkt_mma_tiler[0], self.kkt_mma_tiler[1])\n        )\n\n        fake_state_thr_mma = fake_state_tiled_mma.get_slice(0)\n\n        kst_thr_mma = kst_tiled_mma.get_slice(0)\n        tKSrK_0 = kst_thr_mma.make_fragment_A(sQK)\n        tKSrST = kst_thr_mma.make_fragment_B(sStateInput)\n        kst_acc_shape = kst_thr_mma.partition_shape_C(\n            (self.kst_mma_tiler[0], self.kst_mma_tiler[1])\n        )\n        tKStKS_fake = kst_thr_mma.make_fragment_C(kst_acc_shape)\n        tKStKS = cute.make_tensor(tmem_ptr + self.tmem_kst_output, tKStKS_fake.layout)\n        # input smem A\n        tKStK_layout = cute.composition(tKStKS.layout, cute.make_layout((128, 64)))\n        tKtK = cute.make_tensor(tmem_ptr + self.tmem_k_input, tKStK_layout)\n\n        invert_sub_thr_mma_ss_l0 = invert_sub_tiled_mma_ss_l0.get_slice(0)\n        tSrD = invert_sub_thr_mma_ss_l0.make_fragment_A(sInvertSubSSL0A)\n        tSrC = invert_sub_thr_mma_ss_l0.make_fragment_B(sInvertSubSSL0B)\n        invert_sub_acc_shape = invert_sub_thr_mma_ss_l0.partition_shape_C(\n            (self.invert_mma_sub_l0_tiler[0], self.invert_mma_sub_l0_tiler[1])\n        )\n\n        tKKTtKKT_fake = kkt_thr_mma.make_fragment_C(kkt_acc_shape)\n        tKKTtKKT = cute.make_tensor(\n            tmem_ptr + self.tmem_kkt_output, tKKTtKKT_fake.layout\n        )\n\n        tItSSL0_fake = invert_sub_thr_mma_ss_l0.make_fragment_C(invert_sub_acc_shape)\n        tItSSL0 = cute.make_tensor(\n            tmem_ptr + self.tmem_ivt_ss_l0_output, tItSSL0_fake.layout\n        )\n\n        # : ((128,128),1,1):((65536,1),0,0)\n        tQgate_layout = cute.make_layout(((128, 64), 1, 1), stride=((65536, 1), 0, 0))\n        tQgate = cute.make_tensor(tmem_ptr + self.tmem_gate_q, tQgate_layout)\n\n        tGamma_layout = cute.make_layout(((128, 128), 1, 1), stride=((65536, 1), 0, 0))\n        tGamma = cute.make_tensor(tmem_ptr + self.tmem_gamma, tGamma_layout)\n\n        # tStage\n        tStateF32_layout = cute.make_layout(\n            ((128, 128), 1, 1), stride=((65536, 1), 0, 0)\n        )\n        tStateF32 = cute.make_tensor(tmem_ptr + self.tmem_state, tStateF32_layout)\n\n        invert_sub_thr_mma_ts_l0 = invert_sub_tiled_mma_ts_l0.get_slice(0)\n        tInrDCL0A_fake = invert_sub_thr_mma_ts_l0.make_fragment_A(\n            invert_sub_smem_layout_staged_ts_l0_a.outer.shape\n        )\n        tInrDCL0A = cute.make_tensor(\n            cute.recast_ptr(\n                tmem_ptr,\n                dtype=tInrDCL0A_fake.element_type,\n            )\n            + self.tmem_ivt_ts_l0_input,\n            tInrDCL0A_fake.layout,\n        )\n\n        # input smem B\n        tSrDCL0B = invert_sub_thr_mma_ts_l0.make_fragment_B(sInvertSubTSL0B)\n\n        # output tmem C\n        tItTSL0_fake = invert_sub_thr_mma_ts_l0.make_fragment_C(invert_sub_acc_shape)\n        tItTSL0 = cute.make_tensor(\n            tmem_ptr + self.tmem_ivt_ts_l0_output, tItTSL0_fake.layout\n        )\n\n        invert_sub_thr_mma_ss_l1 = invert_sub_tiled_mma_ss_l1.get_slice(0)\n        tSrD_ivt_l1 = invert_sub_thr_mma_ss_l1.make_fragment_A(sInvertSubSSL1A)\n        tSrC_ivt_l1 = invert_sub_thr_mma_ss_l1.make_fragment_B(sInvertSubSSL1B)\n        invert_sub_acc_l1_shape = invert_sub_thr_mma_ss_l1.partition_shape_C(\n            (self.invert_mma_sub_l1_tiler[0], self.invert_mma_sub_l1_tiler[1])\n        )\n        tCtAcc_ivt_l1_ss_fake = invert_sub_thr_mma_ss_l1.make_fragment_C(\n            invert_sub_acc_l1_shape\n        )\n        tStO_ivt_l1_ss0 = cute.make_tensor(\n            tmem_ptr + self.tmem_ivt_ss_l1_output, tCtAcc_ivt_l1_ss_fake.layout\n        )\n\n        invert_sub_thr_mma_ts_l1 = invert_sub_tiled_mma_ts_l1.get_slice(0)\n        invert_acc_ts_l1_shape = invert_sub_thr_mma_ts_l1.partition_shape_C(\n            (self.invert_mma_sub_l1_tiler[0], self.invert_mma_sub_l1_tiler[1])\n        )\n        # output tmem C\n        tOtTSL1_fake = invert_sub_thr_mma_ts_l1.make_fragment_C(invert_acc_ts_l1_shape)\n        tOtTSL1 = cute.make_tensor(\n            tmem_ptr + self.tmem_ivt_ts_l1_output, tOtTSL1_fake.layout\n        )\n\n        tuw_thr_mma = tuw_tiled_mma.get_slice(0)\n        # input smem A\n        tTUWrA = tuw_thr_mma.make_fragment_A(sTuwA)\n        # input smem B\n        tTUWrB = tuw_thr_mma.make_fragment_B(sTuwB)\n        # output tmem C\n        tuw_acc_shape = tuw_thr_mma.partition_shape_C(\n            (self.tuw_mma_tiler[0], self.tuw_mma_tiler[1])\n        )\n        tVtTUW_fake = tuw_thr_mma.make_fragment_C(tuw_acc_shape)\n        tVtTUW = cute.make_tensor(tmem_ptr + self.tmem_tuw_output, tVtTUW_fake.layout)\n\n        o_intra_thr_mma = o_intra_tiled_mma.get_slice(0)\n        # input smem B\n        tOIntrarB = o_intra_thr_mma.make_fragment_B(sOIntraB)\n        # output tmem C\n        o_intra_acc_shape = o_intra_thr_mma.partition_shape_C(\n            (self.o_intra_mma_tiler[0], self.o_intra_mma_tiler[1])\n        )\n\n        o_intra_thr_mma_new = o_intra_tiled_ts_mma_new.get_slice(0)\n        # input smem A\n        tQKMtQKM_layout = cute.composition(tQKtQK.layout, cute.make_layout((128, 64)))\n        tQKMtQKM = cute.make_tensor(tmem_ptr + self.tmem_gate_qk, tQKMtQKM_layout)\n\n        update_s_thr_mma = update_s_tiled_mma.get_slice(0)\n        tUpdateA = update_s_thr_mma.make_fragment_A(sUpdateA)\n        tUpdateB = update_s_thr_mma.make_fragment_B(sUpdateB)\n        update_s_acc_shape = update_s_thr_mma.partition_shape_C(\n            (self.update_s_mma_tiler[0], self.update_s_mma_tiler[1])\n        )\n        tStUpdate_fake = update_s_thr_mma.make_fragment_C(update_s_acc_shape)\n        tStUpdate = cute.make_tensor(\n            tmem_ptr + self.tmem_update_s_output, tStUpdate_fake.layout\n        )\n\n        qs_thr_mma = qs_tiled_mma.get_slice(0)\n        tQSB = qs_thr_mma.make_fragment_B(sQSB)\n        qs_acc_shape = qs_thr_mma.partition_shape_C(\n            (self.qs_mma_tiler[0], self.qs_mma_tiler[1])\n        )\n        tOintertQS_fake = qs_thr_mma.make_fragment_C(qs_acc_shape)\n        tOintertQS = cute.make_tensor(\n            tmem_ptr + self.tmem_o_inter_output, tOintertQS_fake.layout\n        )\n\n        loop_count = cute.ceil_div(mO_qdl.shape[0], self.cta_tiler[0])\n\n        # ///////////////////////////////////////////////////////////////////////////////\n        #  Load Gate Beta\n        # ///////////////////////////////////////////////////////////////////////////////\n        if warp_idx == self.gb_warp_id:\n            cute.arch.setmaxregister_decrease(self.num_regs_gb)\n            tile_sched = create_gdn_static_tile_scheduler(\n                tile_sched_params, cute.arch.block_idx(), cute.arch.grid_dim()\n            )\n            work_tile = tile_sched.initial_work_tile_info()\n            lane_id = tidx % 32\n\n            while work_tile.is_valid_tile:\n                curr_block_coord = work_tile.tile_idx\n\n                batch_coord = curr_block_coord[2][1]\n                continue_cond = False\n                cuseqlen_q = Int32(0)\n                seqlen_q = mQ_qdl.shape[0]\n\n                head_coord = curr_block_coord[2][0]\n\n                if cutlass.const_expr(cum_seqlen_q is not None):\n                    cuseqlen_q = cum_seqlen_q[batch_coord]\n                    seqlen_q = cum_seqlen_q[batch_coord + 1] - cuseqlen_q\n                    continue_cond = (\n                        not GdnStaticTileScheduler.check_valid_work_for_seqlen_q(\n                            self.cta_tiler[0],\n                            curr_block_coord[0],\n                            seqlen_q,\n                        )\n                    )\n\n                if not continue_cond:\n                    batch_base = cuseqlen_q\n                    gate_vals = cute.make_rmem_tensor((4), cutlass.Float32)\n                    beta_vals = cute.make_rmem_tensor((4), cutlass.Float32)\n\n                    for i in cutlass.range(loop_count, unroll=1):\n                        # step1: read gate beta\n                        for it in cutlass.range_constexpr(4):\n                            curr_idx = i * 128 + it * 32 + lane_id\n                            if curr_idx < seqlen_q:\n                                if cutlass.const_expr(cum_seqlen_q is not None):\n                                    gate_vals[it] = gate[\n                                        batch_base + curr_idx, 0, (head_coord, 0)\n                                    ]\n                                    beta_vals[it] = beta[\n                                        batch_base + curr_idx, 0, (head_coord, 0)\n                                    ]\n                                else:\n                                    gate_vals[it] = gate[\n                                        curr_idx, 0, (head_coord, batch_coord)\n                                    ]\n                                    beta_vals[it] = beta[\n                                        curr_idx, 0, (head_coord, batch_coord)\n                                    ]\n                            else:\n                                gate_vals[it] = cutlass.Float32(0)\n                                beta_vals[it] = cutlass.Float32(0)\n                        # step2: write to smem\n                        sGate0 = sGate[None, None, 0]  # assume only one stage\n                        sBeta0 = sBeta[None, None, 0]\n\n                        gb_handle = gb_w0_producer.acquire_and_advance()\n\n                        for it in cutlass.range_constexpr(4):\n                            sGate0[it * 32 + lane_id] = gate_vals[it]\n                            sBeta0[it * 32 + lane_id] = beta_vals[it]\n\n                        # step3: notify cuda core wg\n                        gb_handle.commit()\n\n                tile_sched.advance_to_next_work()\n                work_tile = tile_sched.get_current_work()\n\n        # ///////////////////////////////////////////////////////////////////////////////\n        #  Epilogue: Store Output\n        # ///////////////////////////////////////////////////////////////////////////////\n        if warp_idx == self.epilogue_warp_id:\n            cute.arch.setmaxregister_decrease(self.num_regs_other)\n            tile_sched = create_gdn_static_tile_scheduler(\n                tile_sched_params, cute.arch.block_idx(), cute.arch.grid_dim()\n            )\n            work_tile = tile_sched.initial_work_tile_info()\n            while work_tile.is_valid_tile:\n                curr_block_coord = work_tile.tile_idx\n\n                batch_coord = curr_block_coord[2][1]\n                continue_cond = False\n                cuseqlen_q = Int32(0)\n                seqlen_q = mQ_qdl.shape[0]\n\n                if cutlass.const_expr(cum_seqlen_q is not None):\n                    cuseqlen_q = cum_seqlen_q[batch_coord]\n                    seqlen_q = cum_seqlen_q[batch_coord + 1] - cuseqlen_q\n                    continue_cond = (\n                        not GdnStaticTileScheduler.check_valid_work_for_seqlen_q(\n                            self.cta_tiler[0],\n                            curr_block_coord[0],\n                            seqlen_q,\n                        )\n                    )\n\n                if not continue_cond:\n                    curr_block_coord_o = curr_block_coord\n                    mO_qdl_ = mO_qdl\n                    if cutlass.const_expr(cum_seqlen_q is not None):\n                        logical_offset_mO = (\n                            mO_qdl_.shape[0] - seqlen_q,\n                            0,\n                            (0, cuseqlen_q + seqlen_q),\n                        )\n                        mO_qdl_ = cute.domain_offset(logical_offset_mO, mO_qdl_)\n                        curr_block_coord_o = (\n                            curr_block_coord[0],\n                            curr_block_coord[1],\n                            (curr_block_coord[2][0], 0),\n                        )\n\n                    gO_mnl = cute.flat_divide(\n                        mO_qdl_, cute.select(self.mma_tiler, mode=[0, 1])\n                    )\n                    tOsO, tOgO_qdl = cute.nvgpu.cpasync.tma_partition(\n                        tma_atom_o_output,\n                        0,\n                        cute.make_layout(1),\n                        cute.group_modes(sO, 0, 2),\n                        cute.group_modes(gO_mnl, 0, 2),\n                    )\n                    tQgO = tOgO_qdl[None, None, 0, curr_block_coord_o[2]]\n                    w0_handle = epi_w0_producer.acquire_and_advance()\n                    w0_handle.commit()\n\n                    for i in cutlass.range(loop_count, unroll=1):\n                        w0_handle = epi_w0_producer.acquire_and_advance()\n                        cute.copy(tma_atom_o_output, tOsO[None, 0], tQgO[None, i])\n\n                        cute.arch.cp_async_bulk_commit_group()\n\n                        # Ensure O0 buffer is ready to be released\n                        cute.arch.cp_async_bulk_wait_group(0, read=True)\n\n                        w0_handle.commit()\n\n                    if cutlass.const_expr(tma_atom_state_output is not None):\n                        gStateOutput = cute.flat_divide(\n                            mStateOutput,\n                            cute.select(self.update_s_mma_tiler, mode=[0, 1]),\n                        )\n                        tSsS, tSgS_vkl = cute.nvgpu.cpasync.tma_partition(\n                            tma_atom_state_output,\n                            0,  # no multicast\n                            cute.make_layout(1),\n                            cute.group_modes(sStateOutput, 0, 2),\n                            cute.group_modes(gStateOutput, 0, 4),\n                        )\n                        tSgS = tSgS_vkl[None, curr_block_coord[2]]\n                        w0_epi_handle = w0_epi_consumer.wait_and_advance()\n                        cute.copy(\n                            tma_atom_state_output,\n                            tSsS[None, 0],  # only 1 stage\n                            tSgS[None],\n                        )\n                        cute.arch.cp_async_bulk_commit_group()\n                        cute.arch.cp_async_bulk_wait_group(0, read=True)\n                        w0_epi_handle.release()\n\n                tile_sched.advance_to_next_work()\n                work_tile = tile_sched.get_current_work()\n\n                # The smem is reused, ensuring the State Output store is complete\n                if cutlass.const_expr(\n                    tma_atom_state_output is not None and self.is_persistent\n                ):\n                    cute.arch.barrier_arrive(\n                        barrier_id=self.epi_load_sync_bar_id,\n                        number_of_threads=self.threads_per_warp * 2,\n                    )\n        # ///////////////////////////////////////////////////////////////////////////////\n        #  LOAD: tma load QKVS\n        # ///////////////////////////////////////////////////////////////////////////////\n        if warp_idx == self.load_warp_id:\n            cute.arch.setmaxregister_decrease(self.num_regs_other)\n\n            tile_sched = create_gdn_static_tile_scheduler(\n                tile_sched_params, cute.arch.block_idx(), cute.arch.grid_dim()\n            )\n            work_tile = tile_sched.initial_work_tile_info()\n            while work_tile.is_valid_tile:\n                curr_block_coord = work_tile.tile_idx\n                continue_cond = False\n                cuseqlen_q = Int32(0)\n                seqlen_q = mQ_qdl.shape[0]\n                batch_coord = curr_block_coord[2][1]\n\n                if cutlass.const_expr(cum_seqlen_q is not None):\n                    cuseqlen_q = cum_seqlen_q[batch_coord]\n                    seqlen_q = cum_seqlen_q[batch_coord + 1] - cuseqlen_q\n                    continue_cond = (\n                        not GdnStaticTileScheduler.check_valid_work_for_seqlen_q(\n                            self.cta_tiler[0],\n                            curr_block_coord[0],\n                            seqlen_q,\n                        )\n                    )\n\n                if not continue_cond:\n                    mQ_qdl_ = mQ_qdl\n                    mK_kdl_ = mK_kdl\n                    mV_dkl_ = mV_dkl\n                    curr_block_coord_q = curr_block_coord\n                    curr_block_coord_kv = curr_block_coord\n                    curr_block_coord_state = curr_block_coord\n\n                    if cutlass.const_expr(cum_seqlen_q is not None):\n                        logical_offset_mQ = (\n                            cuseqlen_q,\n                            0,\n                            (0, 0),\n                        )\n                        mQ_qdl_ = cute.domain_offset(logical_offset_mQ, mQ_qdl)\n                        curr_block_coord_q = (\n                            curr_block_coord[0],\n                            curr_block_coord[1],\n                            (curr_block_coord[2][0], Int32(0)),\n                        )\n                        logical_offset_mK = (\n                            cuseqlen_q,\n                            0,\n                            (0, 0),\n                        )\n                        logical_offset_mV = (\n                            0,\n                            cuseqlen_q,\n                            (0, 0),\n                        )\n                        mK_kdl_ = cute.domain_offset(logical_offset_mK, mK_kdl)\n                        mV_dkl_ = cute.domain_offset(logical_offset_mV, mV_dkl)\n                        curr_block_coord_kv = (\n                            curr_block_coord[0],\n                            curr_block_coord[1],\n                            (curr_block_coord[2][0], Int32(0)),\n                        )\n\n                    gQ_qdl = cute.flat_divide(\n                        mQ_qdl_, cute.select(self.qk_mma_tiler, mode=[0, 2])\n                    )\n                    tSgQ_qdl = qk_thr_mma.partition_A(gQ_qdl)\n\n                    tQsQ, tQgQ_qdl = cute.nvgpu.cpasync.tma_partition(\n                        tma_atom_q,\n                        0,  # no multicast\n                        cute.make_layout(1),\n                        cute.group_modes(sQK, 0, 3),\n                        cute.group_modes(tSgQ_qdl, 0, 3),\n                    )\n                    tQgQ = tQgQ_qdl[None, None, 0, curr_block_coord_q[2]]\n\n                    gK_kdl = cute.flat_divide(\n                        mK_kdl_, cute.select(self.qk_mma_tiler, mode=[1, 2])\n                    )\n                    tSgK_kdl = qk_thr_mma.partition_B(gK_kdl)\n                    tKsK, tKgK_kdl = cute.nvgpu.cpasync.tma_partition(\n                        tma_atom_k,\n                        0,  # no multicast\n                        cute.make_layout(1),\n                        cute.group_modes(sQK, 0, 3),\n                        cute.group_modes(tSgK_kdl, 0, 3),\n                    )\n                    tKgK = tKgK_kdl[None, None, 0, curr_block_coord_kv[2]]\n\n                    gV_kdl = cute.flat_divide(\n                        mV_dkl_, cute.select(self.tuw_mma_tiler, mode=[1, 2])\n                    )\n                    tSgV_kdl = tuw_thr_mma.partition_B(gV_kdl)\n                    tVsV, tVgV_kdl = cute.nvgpu.cpasync.tma_partition(\n                        tma_atom_v,\n                        0,  # no multicast\n                        cute.make_layout(1),\n                        cute.group_modes(sV, 0, 3),\n                        cute.group_modes(tSgV_kdl, 0, 3),\n                    )\n                    tVgV = tVgV_kdl[None, 0, None, curr_block_coord_kv[2]]\n\n                    if cutlass.const_expr(tma_atom_state_f32 is not None):\n                        gStateF32 = cute.flat_divide(\n                            mState_f32, cute.select(self.kst_mma_tiler, mode=[1, 2])\n                        )\n                        tKSgStateF32 = fake_state_thr_mma.partition_B(gStateF32)\n                        tSsSF32, tSgSF32_kdl = cute.nvgpu.cpasync.tma_partition(\n                            tma_atom_state_f32,\n                            0,  # no multicast\n                            cute.make_layout(1),\n                            cute.group_modes(sStateInputF32, 0, 3),\n                            cute.group_modes(tKSgStateF32, 0, 3),\n                        )\n                        tSgSF32 = tSgSF32_kdl[None, None, 0, curr_block_coord_state[2]]\n                        state_f32_handle0 = load_state_producer.acquire_and_advance()\n                        cute.copy(\n                            tma_atom_state_f32,\n                            tSgSF32[None, 0],\n                            tSsSF32[None, state_f32_handle0.index],\n                            tma_bar_ptr=state_f32_handle0.barrier,\n                        )\n\n                    for i in cutlass.range(loop_count, unroll=1):\n                        w0_coord = i\n                        k0_handle = load_qk_producer.acquire_and_advance()\n                        cute.copy(\n                            tma_atom_k,\n                            tKgK[None, w0_coord],\n                            tKsK[None, k0_handle.index],\n                            tma_bar_ptr=k0_handle.barrier,\n                        )\n\n                        q_handle = load_qk_producer.acquire_and_advance()\n                        cute.copy(\n                            tma_atom_q,\n                            tQgQ[None, w0_coord],\n                            tQsQ[None, q_handle.index],\n                            tma_bar_ptr=q_handle.barrier,\n                        )\n\n                        v_handle0 = load_v_producer.acquire_and_advance()\n                        cute.copy(\n                            tma_atom_v,\n                            tVgV[None, w0_coord],\n                            tVsV[None, v_handle0.index],\n                            tma_bar_ptr=v_handle0.barrier,\n                        )\n\n                tile_sched.advance_to_next_work()\n                work_tile = tile_sched.get_current_work()\n\n                if cutlass.const_expr(\n                    tma_atom_state_output is not None and self.is_persistent\n                ):\n                    cute.arch.barrier(\n                        barrier_id=self.epi_load_sync_bar_id,\n                        number_of_threads=self.threads_per_warp * 2,\n                    )\n            # dealloc tmem buffer\n            cute.arch.relinquish_tmem_alloc_permit()\n            cute.arch.mbarrier_wait(tmem_dealloc_mbar_ptr, 0)\n            tmem_alloc_cols = Int32(self.tmem_alloc_cols)\n            #  Retrieving tmem ptr and make acc\n            tmem_ptr = cute.arch.retrieve_tmem_ptr(\n                cutlass.Float32,\n                alignment=16,\n                ptr_to_buffer_holding_addr=storage.tmem_holding_buf,\n            )\n            cute.arch.dealloc_tmem(tmem_ptr, tmem_alloc_cols)\n\n        # ///////////////////////////////////////////////////////////////////////////////\n        #  MMA: mma warp\n        # ///////////////////////////////////////////////////////////////////////////////\n        if warp_idx == self.mma_warp_id:\n            cute.arch.setmaxregister_decrease(self.num_regs_mma)\n\n            tile_sched = create_gdn_static_tile_scheduler(\n                tile_sched_params, cute.arch.block_idx(), cute.arch.grid_dim()\n            )\n            work_tile = tile_sched.initial_work_tile_info()\n\n            tSrDC_ivt_l1_fake = invert_sub_thr_mma_ts_l1.make_fragment_A(\n                invert_sub_smem_layout_staged_ts_l1_a.outer.shape\n            )\n            tSrDC_ivt_l1 = cute.make_tensor(\n                cute.recast_ptr(\n                    tmem_ptr,\n                    dtype=tSrDC_ivt_l1_fake.element_type,\n                )\n                + self.tmem_ivt_ts_l1_input,\n                tSrDC_ivt_l1_fake.layout,\n            )\n            tSrA_ivt_l1 = invert_sub_thr_mma_ts_l1.make_fragment_B(sInvertSubTSL1B)\n\n            tOrP = o_intra_thr_mma_new.make_fragment_A(\n                o_intra_smem_layout_staged_a_new.outer\n            )\n            tOrP0 = cute.make_tensor(\n                cute.recast_ptr(\n                    tmem_ptr,\n                    dtype=tOrP.element_type,\n                )\n                + self.tmem_gate_qk * 2,\n                tOrP.layout,\n            )\n\n            tQSA = o_intra_thr_mma_new.make_fragment_A(qs_smem_layout_staged_a.outer)\n            tQSA0 = cute.make_tensor(\n                cute.recast_ptr(\n                    tmem_ptr,\n                    dtype=tQSA.element_type,\n                )\n                + self.tmem_gate_q * 2,\n                tQSA.layout,\n            )\n\n            while work_tile.is_valid_tile:\n                curr_block_coord = work_tile.tile_idx\n                continue_cond = False\n\n                if not continue_cond:\n                    for _i in cutlass.range(loop_count, unroll=1):\n                        k_handle0 = load_qk_consumer.wait_and_advance()\n                        qk_handle0 = mma_qk_producer0.acquire_and_advance()\n\n                        kkt_tiled_mma = self.exec_mma(\n                            kkt_tiled_mma,\n                            tKKTtKKT,\n                            tArK,\n                            tArKT,\n                            k_handle0.index,\n                            k_handle0.index,\n                        )\n\n                        qk_handle0.commit()\n\n                        q_handle = load_qk_consumer.wait_and_advance()\n\n                        qk_handle1 = mma_qk_producer0.acquire_and_advance()\n\n                        qk_tiled_mma = self.exec_mma(\n                            qk_tiled_mma,\n                            tQKtQK,\n                            tSrQ,\n                            tSrK,\n                            q_handle.index,\n                            k_handle0.index,\n                        )\n\n                        qk_handle1.commit()\n\n                        cs_handle = mma_cudacore_producer0.acquire_and_advance()\n                        cute.arch.barrier(\n                            barrier_id=self.cudacore_mma_sync_bar_id,\n                            number_of_threads=self.threads_per_warp * 5,\n                        )\n\n                        kst_tiled_mma = self.exec_mma(\n                            kst_tiled_mma,\n                            tKStKS,\n                            tKSrK_0,\n                            tKSrST,\n                            0,\n                            0,\n                        )\n\n                        cs_handle.commit()\n\n                        cs_handle = mma_cudacore_producer0.acquire_and_advance()\n\n                        invert_sub_tiled_mma_ss_l0 = self.exec_mma(\n                            invert_sub_tiled_mma_ss_l0,\n                            tItSSL0,\n                            tSrD,\n                            tSrC,\n                            0,\n                            0,\n                        )\n\n                        cs_handle.commit()\n\n                        c0_handle = mma_cudacore_producer0.acquire_and_advance()\n\n                        invert_sub_tiled_mma_ts_l0 = self.exec_mma(\n                            invert_sub_tiled_mma_ts_l0,\n                            tItTSL0,\n                            tInrDCL0A,\n                            tSrDCL0B,\n                            0,\n                            0,\n                        )\n\n                        c0_handle.commit()\n\n                        c0_handle = mma_cudacore_producer0.acquire_and_advance()\n\n                        invert_sub_tiled_mma_ss_l1 = self.exec_mma(\n                            invert_sub_tiled_mma_ss_l1,\n                            tStO_ivt_l1_ss0,\n                            tSrD_ivt_l1,\n                            tSrC_ivt_l1,\n                            0,\n                            0,\n                        )\n\n                        c0_handle.commit()\n\n                        c0_handle = mma_cudacore_producer0.acquire_and_advance()\n\n                        k_handle0.release()\n\n                        invert_sub_tiled_mma_ts_l1 = self.exec_mma(\n                            invert_sub_tiled_mma_ts_l1,\n                            tOtTSL1,\n                            tSrDC_ivt_l1,\n                            tSrA_ivt_l1,\n                            0,\n                            0,\n                        )\n\n                        c0_handle.commit()\n\n                        c0_handle = mma_cudacore_producer0.acquire_and_advance()\n\n                        tuw_tiled_mma = self.exec_mma(\n                            tuw_tiled_mma,\n                            tVtTUW,\n                            tTUWrA,\n                            tTUWrB,\n                            0,\n                            0,\n                        )\n\n                        c0_handle.commit()\n                        c0_handle = mma_cudacore_producer0.acquire_and_advance()\n\n                        q_handle.release()\n\n                        tCtAcc_o_intra_acc_shape_fake = o_intra_thr_mma.make_fragment_C(\n                            o_intra_acc_shape\n                        )\n                        tStO_o_intra0 = cute.make_tensor(\n                            tmem_ptr + self.tmem_o_intra_output,\n                            tCtAcc_o_intra_acc_shape_fake.layout,\n                        )\n\n                        o_intra_tiled_ts_mma_new = self.exec_mma(\n                            o_intra_tiled_ts_mma_new,\n                            tStO_o_intra0,\n                            tOrP0,\n                            tOIntrarB,\n                            0,\n                            0,\n                        )\n\n                        qs_tiled_mma = self.exec_mma(\n                            qs_tiled_mma,\n                            tOintertQS,\n                            tQSA0,\n                            tQSB,\n                            0,\n                            0,\n                            True,\n                        )\n\n                        c0_handle.commit()\n                        c0_handle = mma_cudacore_producer0.acquire_and_advance()\n\n                        update_s_tiled_mma = self.exec_mma(\n                            update_s_tiled_mma,\n                            tStUpdate,\n                            tUpdateA,\n                            tUpdateB,\n                            0,\n                            0,\n                            True,\n                        )\n\n                        c0_handle.commit()\n\n                tile_sched.advance_to_next_work()\n                work_tile = tile_sched.get_current_work()\n                # End of persistent scheduler loop\n        # ///////////////////////////////////////////////////////////////////////////////\n        #  Mainloop: mainloop warp group\n        # ///////////////////////////////////////////////////////////////////////////////\n        if warp_idx < 4:\n            cute.arch.setmaxregister_increase(self.num_regs_cudacore)\n\n            tile_sched = create_gdn_static_tile_scheduler(\n                tile_sched_params, cute.arch.block_idx(), cute.arch.grid_dim()\n            )\n            work_tile = tile_sched.initial_work_tile_info()\n\n            while work_tile.is_valid_tile:\n                curr_block_coord = work_tile.tile_idx\n                batch_coord = curr_block_coord[2][1]\n                continue_cond = False\n                if not continue_cond:\n                    gO_mnl = cute.flat_divide(\n                        O, cute.select(self.mma_tiler, mode=[0, 1])\n                    )\n                    # Use input state\n                    if cutlass.const_expr(tma_atom_state_f32 is not None):\n                        load_state_consumer.wait_and_advance()\n                        self.init_state_from_smem(\n                            kst_thr_mma,\n                            tStateF32,\n                            sStateInputF32,\n                        )\n                        load_state_consumer.release()\n                    else:\n                        self.init_state_zeros(\n                            kst_thr_mma,\n                            tStateF32,\n                        )\n\n                    # Arguments\n                    atom_args = (\n                        kkt_thr_mma,\n                        kst_thr_mma,\n                        qk_thr_mma,\n                        qs_thr_mma,\n                    )\n                    tensor_args = (\n                        sGate,\n                        sBeta,\n                        sGateCumsum,\n                        sStateInput,\n                        sIvt,\n                        sQ,\n                        sK,\n                        sV,\n                        sO,\n                        sInvertSubReg,\n                        sInvertSubSSL0A,\n                        sInvertSubSSL0B,\n                        sInvertSubSSL1B,\n                        sInvertSubTSL0B,\n                        sInvertSubSSL1A,\n                        sInvertSubTSL1B,\n                        sTuwAStore,\n                        sTuwA,\n                        sOIntraB,\n                        sUpdateB,\n                        tGamma,\n                        tKKTtKKT,\n                        tQKtQK,\n                        tQKMtQKM,\n                        tKtK,\n                        tKStKS,\n                        tItTSL0,\n                        tInrDCL0A,\n                        tOtTSL1,\n                        tVtTUW,\n                        tOintertQS,\n                        tItSSL0,\n                        tStateF32,\n                        tQgate,\n                    )\n                    pipeline_args = (\n                        gb_w0_consumer,\n                        epi_w0_consumer,\n                        mma_qk_consumer0,\n                        mma_cudacore_consumer0,\n                        load_v_consumer,\n                    )\n\n                    # Corner case\n                    tail_count = mO_qdl.shape[0] % self.cta_tiler[0]\n\n                    if tail_count == 0:\n                        value_args = (\n                            scale,\n                            loop_count,\n                            0,\n                        )\n                        (\n                            gb_w0_consumer,\n                            epi_w0_consumer,\n                            mma_qk_consumer0,\n                            mma_cudacore_consumer0,\n                            load_v_consumer,\n                        ) = self.main_loop(\n                            value_args,\n                            atom_args,\n                            tensor_args,\n                            pipeline_args,\n                        )\n                    else:\n                        value_args = (\n                            scale,\n                            loop_count - 1,\n                            0,\n                        )\n                        (\n                            gb_w0_consumer,\n                            epi_w0_consumer,\n                            mma_qk_consumer0,\n                            mma_cudacore_consumer0,\n                            load_v_consumer,\n                        ) = self.main_loop(\n                            value_args,\n                            atom_args,\n                            tensor_args,\n                            pipeline_args,\n                        )\n                        pipeline_args = (\n                            gb_w0_consumer,\n                            epi_w0_consumer,\n                            mma_qk_consumer0,\n                            mma_cudacore_consumer0,\n                            load_v_consumer,\n                        )\n                        value_args = (\n                            scale,\n                            1,\n                            loop_count - 1,\n                        )\n                        (\n                            gb_w0_consumer,\n                            epi_w0_consumer,\n                            mma_qk_consumer0,\n                            mma_cudacore_consumer0,\n                            load_v_consumer,\n                        ) = self.main_loop(\n                            value_args,\n                            atom_args,\n                            tensor_args,\n                            pipeline_args,\n                            True,\n                            tail_count=tail_count,\n                        )\n\n                    # Output state\n                    if cutlass.const_expr(tma_atom_state_output is not None):\n                        w0_epi_handle = w0_epi_producer.acquire_and_advance()\n                        self.store_state_to_smem(\n                            tStUpdate, sStateOutput, update_s_thr_mma\n                        )\n                        w0_epi_handle.commit()\n\n                    w0_handle = epi_w0_consumer.wait_and_advance()\n                    w0_handle.release()\n\n                tile_sched.advance_to_next_work()\n                work_tile = tile_sched.get_current_work()\n\n            cute.arch.mbarrier_arrive(tmem_dealloc_mbar_ptr)\n\n    @cute.jit\n    def main_loop(\n        self,\n        value_args: tuple,\n        atom_args: tuple,\n        tensor_args: tuple,\n        pipeline_args: tuple,\n        need_mask: cutlass.Constexpr[cutlass.Boolean] = False,\n        tail_count: Int32 = 128,\n    ) -> Tuple[\n        pipeline.PipelineConsumer,\n        pipeline.PipelineConsumer,\n        pipeline.PipelineConsumer,\n        pipeline.PipelineConsumer,\n        pipeline.PipelineConsumer,\n    ]:\n        \"\"\"Per-chunk mainloop executed by cudacore warps (0-3).\"\"\"\n        tidx, _, _ = cute.arch.thread_idx()\n\n        (\n            scale,\n            loop_count,\n            loop_base,\n        ) = value_args\n\n        (\n            kkt_thr_mma,\n            kst_thr_mma,\n            qk_thr_mma,\n            qs_thr_mma,\n        ) = atom_args\n\n        (\n            sGate,\n            sBeta,\n            sGateCumsum,\n            sStateInput,\n            sIvt,\n            sQ,\n            sK,\n            sV,\n            sO,\n            sInvertSubReg,\n            sInvertSubSSL0A,\n            sInvertSubSSL0B,\n            sInvertSubSSL1B,\n            sInvertSubTSL0B,\n            sInvertSubSSL1A,\n            sInvertSubTSL1B,\n            sTuwAStore,\n            sTuwA,\n            sOIntraB,\n            sUpdateB,\n            tGamma,\n            tKKTtKKT,\n            tQKtQK,\n            tQKMtQKM,\n            tKtK,\n            tKStKS,\n            tItTSL0,\n            tInrDCL0A,\n            tOtTSL1,\n            tVtTUW,\n            tOintertQS,\n            tItSSL0,\n            tStateF32,\n            tQgate,\n        ) = tensor_args\n\n        (\n            gb_w0_consumer,\n            epi_w0_consumer,\n            mma_qk_consumer0,\n            mma_cudacore_consumer0,\n            load_v_consumer,\n        ) = pipeline_args\n\n        for _i in cutlass.range(loop_base, loop_base + loop_count, unroll=1):\n            gb_handle = gb_w0_consumer.wait_and_advance()\n            sGate0 = sGate[None, None, gb_handle.index]\n            sBeta0 = sBeta[None, None, gb_handle.index]\n            tval = self.chunk_local_cumsum(sGate0, sGateCumsum, self.wg_sync_bar_id)\n            beta_val = sBeta0[tidx]\n            gb_handle.release()\n\n            self.compute_gamma_tmem(\n                tval,\n                sGateCumsum,\n                kkt_thr_mma,\n                tGamma,\n                self.wg_sync_bar_id,\n                need_mask,\n                tail_count,\n            )\n            qk_handle0 = mma_qk_consumer0.wait_and_advance()\n\n            self.apply_gamma_beta(\n                kkt_thr_mma,\n                sIvt,\n                tKKTtKKT,\n                beta_val,\n                tGamma,\n            )\n\n            gate_tail = (\n                sGateCumsum[tail_count - 1]\n                if cutlass.const_expr(need_mask)\n                else sGateCumsum[127]\n            )\n            w0_handle = epi_w0_consumer.wait_and_advance()\n            self.load_state_apply_gate(\n                kst_thr_mma,\n                tStateF32,\n                sStateInput,\n                gate_tail,\n            )\n            cute.arch.fence_proxy(\n                cute.arch.ProxyKind.async_shared,\n                space=cute.arch.SharedSpace.shared_cta,\n            )\n\n            qk_handle1 = mma_qk_consumer0.wait_and_advance()\n            self.load_qk_epi(\n                qk_thr_mma, tQKtQK, tQKMtQKM, tGamma, need_mask, tail_count\n            )\n\n            cute.arch.barrier_arrive(\n                barrier_id=self.cudacore_mma_sync_bar_id,\n                number_of_threads=self.threads_per_warp * 5,\n            )\n\n            reverse_result = cute.make_rmem_tensor((32, 1), self.acc_dtype)\n\n            self.reverse_smem_sub(reverse_result, sIvt)\n\n            self.store_ivt_smem_l0_ss_a(\n                reverse_result,\n                sInvertSubReg,\n                sInvertSubSSL0A,\n            )\n\n            self.store_ivt_smem_l0_ss_b(\n                kkt_thr_mma,\n                tKKTtKKT,\n                sInvertSubSSL0B,\n            )\n\n            c0_handle = mma_cudacore_consumer0.wait_and_advance()\n            c0_handle.release()\n            v_handle0 = load_v_consumer.wait_and_advance()\n\n            tval_exp = cute.math.exp(tval)\n            self.get_uw_b(\n                kst_thr_mma, tKStKS, tval_exp, beta_val, sV, need_mask, tail_count\n            )\n            self.store_ivt_p1(\n                sInvertSubReg,\n                sInvertSubTSL0B,\n            )\n\n            c0_handle = mma_cudacore_consumer0.wait_and_advance()\n            self.load_ivt_ss_l0(tItSSL0, tInrDCL0A)  # debug\n            c0_handle.release()\n            self.store_ivt_smem_l1_ss_b(\n                kkt_thr_mma,\n                tKKTtKKT,\n                sInvertSubSSL1B,\n            )\n\n            self.store_ivt_p2(\n                sInvertSubReg,\n                sInvertSubSSL1A,\n            )\n\n            c0_handle = mma_cudacore_consumer0.wait_and_advance()\n\n            self.load_ivt_ts_l0(\n                tItTSL0,\n                sInvertSubSSL1A,\n                sInvertSubTSL1B,\n            )\n\n            c0_handle.release()\n\n            self.store_k_epi(kkt_thr_mma, sK, tKtK, need_mask, tail_count)\n            self.store_ivt_p3(\n                sInvertSubReg,\n                sInvertSubTSL1B,\n            )\n\n            c0_handle = mma_cudacore_consumer0.wait_and_advance()\n            c0_handle.release()\n            self.save_tmem(tItTSL0, sTuwAStore)\n            self.store_ivt_ad(sInvertSubReg, sTuwA)\n            self.store_ivt_c(sTuwAStore)\n\n            c0_handle = mma_cudacore_consumer0.wait_and_advance()\n            self.load_ivt_result(tOtTSL1, sTuwAStore)\n            c0_handle.release()\n\n            self.load_q_epi(qk_thr_mma, sQ, tQgate, tval_exp, need_mask, tail_count)\n            cute.arch.fence_proxy(\n                cute.arch.ProxyKind.async_shared,\n                space=cute.arch.SharedSpace.shared_cta,\n            )\n\n            c0_handle = mma_cudacore_consumer0.wait_and_advance()\n            v_handle0.release()\n            self.load_v(tVtTUW, sOIntraB)\n            c0_handle.release()\n            self.load_k(tKtK, sUpdateB, gate_tail, tval)\n            c0_handle = mma_cudacore_consumer0.wait_and_advance()\n            qk_handle0.release()\n            c0_handle.release()\n            self.store_o_smem(tOintertQS, sO, qs_thr_mma, scale)\n\n            w0_handle.release()\n            qk_handle1.release()\n            c0_handle = mma_cudacore_consumer0.wait_and_advance()\n            c0_handle.release()\n\n        return (\n            gb_w0_consumer,\n            epi_w0_consumer,\n            mma_qk_consumer0,\n            mma_cudacore_consumer0,\n            load_v_consumer,\n        )\n\n    @cute.jit\n    def exec_mma(\n        self,\n        tiled_mma,\n        tCtAcc,\n        tCrA,\n        tCrB,\n        a_consumer_index,\n        b_consumer_index,\n        setAcc: bool = False,\n    ):\n        \"\"\"Issue a tcgen05 GEMM.\"\"\"\n        for kphase_idx in cutlass.range(cute.size(tCrB, mode=[2]), unroll_all=True):\n            # set accu = 1\n            tiled_mma.set(\n                tcgen05.Field.ACCUMULATE,\n                cutlass.Boolean(kphase_idx != 0 or setAcc),\n            )\n            cute.gemm(\n                tiled_mma,\n                tCtAcc,\n                tCrA[None, None, kphase_idx, a_consumer_index],\n                tCrB[None, None, kphase_idx, b_consumer_index],\n                tCtAcc,\n            )\n        return tiled_mma\n\n    @cute.jit\n    def get_uw_b(\n        self,\n        thr_mma: cute.ThrMma,\n        tIn: cute.Tensor,\n        gate_val: cutlass.Float32,\n        beta_val: cutlass.Float32,\n        sV: cute.Tensor,\n        mask: cutlass.Constexpr[cutlass.Boolean] = False,\n        tail_count: Int32 = 128,\n    ):\n        \"\"\"Compute V_new = beta*V - beta*gamma*(K@S^T) in-place in smem.\"\"\"\n        tidx, _, _ = cute.arch.thread_idx()\n\n        thread_idx = tidx % (self.threads_per_warp * (len(self.cudacore_warp_ids)))\n\n        cIn = cute.make_identity_tensor((128, 128))\n        tOcO = thr_mma.partition_C(cIn)\n\n        corr_tile_size = 64\n        corr_tile_size_f32 = corr_tile_size // 2\n\n        tIn_i_layout = cute.composition(\n            tIn.layout, cute.make_layout((128, corr_tile_size))\n        )\n\n        cIn_i_layout = cute.composition(\n            tOcO.layout, cute.make_layout((128, corr_tile_size))\n        )\n\n        tIn_i = cute.make_tensor(tIn.iterator, tIn_i_layout)\n        cIn_i = cute.make_tensor(cIn.iterator, cIn_i_layout)\n\n        tmem_load_atom = cute.make_copy_atom(\n            tcgen05.copy.Ld32x32bOp(tcgen05.copy.Repetition(corr_tile_size_f32)),\n            self.acc_dtype,\n        )\n\n        tiled_tmem_load = tcgen05.make_tmem_copy(tmem_load_atom, tIn_i)\n        thr_tmem_load = tiled_tmem_load.get_slice(thread_idx)\n\n        frg_tile = 8\n        sV_frg = cute.logical_divide(sV, cute.make_layout(frg_tile))\n\n        tTMEM_LOADtO = thr_tmem_load.partition_S(tIn_i)\n        tTMEM_LOADcO = thr_tmem_load.partition_D(cIn_i)\n        tTMEM_LOADrS = cute.make_rmem_tensor(tTMEM_LOADcO.shape, self.acc_dtype)\n        tTMEM_LOADrS_frag = cute.logical_divide(\n            tTMEM_LOADrS, cute.make_layout(frg_tile)\n        )\n\n        if cutlass.const_expr(mask):\n            if thread_idx >= tail_count:\n                beta_val = self.g_beta_dtype(0)\n\n        combined_factor = gate_val * beta_val\n\n        each_iter = corr_tile_size // frg_tile\n        for i in cutlass.range_constexpr(128 // corr_tile_size):\n            tTMEM_LOADtO_i = cute.make_tensor(\n                tTMEM_LOADtO.iterator + i * corr_tile_size, tTMEM_LOADtO.layout\n            )\n            cute.copy(tiled_tmem_load, tTMEM_LOADtO_i, tTMEM_LOADrS)\n            cute.arch.fence_view_async_tmem_load()\n\n            # Load V from smem\n            temp_regs = cute.make_rmem_tensor(tTMEM_LOADrS_frag.shape, self.acc_dtype)\n            for it in cutlass.range_constexpr(each_iter):\n                for inner_idx in cutlass.range_constexpr(0, frg_tile, 2):\n                    # mul2\n                    (\n                        temp_regs[inner_idx + 0, it],\n                        temp_regs[inner_idx + 1, it],\n                    ) = cute.arch.mul_packed_f32x2(\n                        (\n                            tTMEM_LOADrS_frag[inner_idx + 0, it],\n                            tTMEM_LOADrS_frag[inner_idx + 1, it],\n                        ),\n                        (-combined_factor, -combined_factor),\n                    )\n\n                    # fma2\n                    (\n                        temp_regs[inner_idx + 0, it],\n                        temp_regs[inner_idx + 1, it],\n                    ) = cute.arch.fma_packed_f32x2(\n                        (\n                            beta_val,\n                            beta_val,\n                        ),\n                        (\n                            cutlass.Float32(\n                                sV_frg[inner_idx + 0, (i * each_iter + it, thread_idx)]\n                            ),\n                            cutlass.Float32(\n                                sV_frg[inner_idx + 1, (i * each_iter + it, thread_idx)]\n                            ),\n                        ),\n                        (\n                            temp_regs[inner_idx + 0, it],\n                            temp_regs[inner_idx + 1, it],\n                        ),\n                    )\n                sV_frg[None, (i * each_iter + it, thread_idx)].store(\n                    temp_regs[None, it].load().to(self.i_dtype)\n                )\n\n    @cute.jit\n    def store_state_to_smem(\n        self,\n        tO: cute.Tensor,\n        sO: cute.Tensor,\n        thr_mma: cute.ThrMma,\n    ):\n        \"\"\"Copy final state from TMEM to smem for TMA store to global.\"\"\"\n        tidx, _, _ = cute.arch.thread_idx()\n        thread_idx = tidx % (self.threads_per_warp * (len(self.cudacore_warp_ids)))\n\n        tOcO = thr_mma.partition_C(tO)\n        tOsO = thr_mma.partition_C(sO)\n\n        corr_tile_size = 32  # must >= 8\n        tOsO_sub = cute.make_tensor(\n            cute.recast_ptr(tOsO.iterator, dtype=self.state_dtype),\n            cute.shape(tOsO)[0],\n        )\n        tOsO_tile = cute.logical_divide(\n            tOsO_sub, (None, (None, 32 // (128 // corr_tile_size)))\n        )\n\n        tIn_i_layout = cute.composition(\n            tO.layout, cute.make_layout((128, corr_tile_size))\n        )\n        cIn_i_layout = cute.composition(\n            tOcO.layout, cute.make_layout((128, corr_tile_size))\n        )\n        sOut_i_layout = cute.composition(\n            tOsO.layout, cute.make_layout((128, corr_tile_size))\n        )\n\n        tIn_i = cute.make_tensor(tO.iterator, tIn_i_layout)\n        cIn_i = cute.make_tensor(tOcO.iterator, cIn_i_layout)\n\n        tmem_load_atom = cute.make_copy_atom(\n            tcgen05.copy.Ld32x32bOp(tcgen05.copy.Repetition(corr_tile_size)),\n            self.acc_dtype,\n        )\n\n        tiled_tmem_load = tcgen05.make_tmem_copy(tmem_load_atom, tIn_i)\n        thr_tmem_load = tiled_tmem_load.get_slice(thread_idx)\n\n        tTMEM_LOADtO = thr_tmem_load.partition_S(tIn_i)\n        tTMEM_LOADcO = thr_tmem_load.partition_D(cIn_i)\n        tTMEM_LOADrS = cute.make_rmem_tensor(tTMEM_LOADcO.shape, self.acc_dtype)\n\n        smem_copy_atom = sm100_utils.get_smem_store_op(\n            self.s_output, self.state_dtype, self.acc_dtype, tiled_tmem_load\n        )\n        tiled_smem_store = cute.make_tiled_copy_D(smem_copy_atom, tiled_tmem_load)\n\n        for i in cutlass.range_constexpr(128 // corr_tile_size):\n            tTMEM_LOADtO_i = cute.make_tensor(\n                tTMEM_LOADtO.iterator + i * corr_tile_size, tTMEM_LOADtO.layout\n            )\n            cute.copy(tiled_tmem_load, tTMEM_LOADtO_i, tTMEM_LOADrS)\n            sOut_i_sub = cute.make_tensor(\n                tOsO_tile[None, (None, (None, i))].iterator, sOut_i_layout\n            )\n            tTMEM_STOREsO_i = thr_tmem_load.partition_D(sOut_i_sub)\n            cute.copy(tiled_smem_store, tTMEM_LOADrS, tTMEM_STOREsO_i)\n\n        # fence view async shared\n        cute.arch.fence_proxy(\n            cute.arch.ProxyKind.async_shared,\n            space=cute.arch.SharedSpace.shared_cta,\n        )\n\n    @cute.jit\n    def store_o_smem(\n        self,\n        tO: cute.Tensor,\n        sO: cute.Tensor,\n        thr_mma: cute.ThrMma,\n        scale: cutlass.Float32,\n    ):\n        \"\"\"Scale and convert O from TMEM (f32) to smem (f16/bf16) for TMA store.\"\"\"\n        tidx, _, _ = cute.arch.thread_idx()\n        thread_idx = tidx % (self.threads_per_warp * (len(self.cudacore_warp_ids)))\n\n        tOcO = thr_mma.partition_C(tO)\n        tOsO = thr_mma.partition_C(sO)\n\n        corr_tile_size = 128  # must >= 8\n\n        # ((128,(8,16)),1,1,(1,1))\n        tOsO_sub = cute.make_tensor(\n            cute.recast_ptr(tOsO.iterator, dtype=self.i_dtype),\n            cute.shape(tOsO)[0],\n        )\n        tOsO_tile = cute.logical_divide(\n            tOsO_sub, (None, (None, 16 // (128 // corr_tile_size)))\n        )\n\n        tIn_i_layout = cute.composition(\n            tO.layout, cute.make_layout((128, corr_tile_size))\n        )\n        cIn_i_layout = cute.composition(\n            tOcO.layout, cute.make_layout((128, corr_tile_size))\n        )\n        sOut_i_layout = cute.composition(\n            tOsO.layout, cute.make_layout((128, corr_tile_size))\n        )\n\n        tIn_i = cute.make_tensor(tO.iterator, tIn_i_layout)\n        cIn_i = cute.make_tensor(tOcO.iterator, cIn_i_layout)\n\n        tmem_load_atom = cute.make_copy_atom(\n            tcgen05.copy.Ld32x32bOp(tcgen05.copy.Repetition(corr_tile_size)),\n            self.acc_dtype,\n        )\n\n        tiled_tmem_load = tcgen05.make_tmem_copy(tmem_load_atom, tIn_i)\n        thr_tmem_load = tiled_tmem_load.get_slice(thread_idx)\n\n        tTMEM_LOADtO = thr_tmem_load.partition_S(tIn_i)\n        tTMEM_LOADcO = thr_tmem_load.partition_D(cIn_i)\n        tTMEM_LOADrS = cute.make_rmem_tensor(tTMEM_LOADcO.shape, self.acc_dtype)\n\n        tTMEM_STORErS_x4_e = cute.make_tensor(\n            cute.recast_ptr(tTMEM_LOADrS.iterator, dtype=self.i_dtype),\n            tTMEM_LOADrS.layout,\n        )\n\n        smem_copy_atom = sm100_utils.get_smem_store_op(\n            self.o_layout, self.i_dtype, self.acc_dtype, tiled_tmem_load\n        )\n        tiled_smem_store = cute.make_tiled_copy_D(smem_copy_atom, tiled_tmem_load)\n\n        for i in cutlass.range_constexpr(128 // corr_tile_size):\n            tTMEM_LOADtO_i = cute.make_tensor(\n                tTMEM_LOADtO.iterator + i * corr_tile_size, tTMEM_LOADtO.layout\n            )\n            cute.copy(tiled_tmem_load, tTMEM_LOADtO_i, tTMEM_LOADrS)\n\n            frg_cnt = 4  # must 4\n            frg_tile = cute.size(tTMEM_LOADrS) // frg_cnt\n            tTMEM_LOADrS_frg = cute.logical_divide(\n                tTMEM_LOADrS, cute.make_layout(frg_tile)\n            )\n            tTMEM_STORErS_x4_e_frg = cute.logical_divide(\n                tTMEM_STORErS_x4_e, cute.make_layout(frg_tile)\n            )\n\n            temp_regs = cute.make_rmem_tensor(tTMEM_LOADrS_frg.shape, self.acc_dtype)\n            for j in cutlass.range_constexpr(frg_cnt):\n                for inner_idx in cutlass.range_constexpr(0, frg_tile, 2):\n                    # mul2\n                    (\n                        temp_regs[inner_idx + 0, j],\n                        temp_regs[inner_idx + 1, j],\n                    ) = cute.arch.mul_packed_f32x2(\n                        (\n                            tTMEM_LOADrS_frg[inner_idx + 0, j],\n                            tTMEM_LOADrS_frg[inner_idx + 1, j],\n                        ),\n                        (scale, scale),\n                    )\n                tTMEM_STORErS_x4_e_frg[None, j].store(\n                    temp_regs[None, j].load().to(self.i_dtype)\n                )\n\n            # store\n            sOut_i_sub = cute.make_tensor(\n                tOsO_tile[None, (None, (None, i))].iterator, sOut_i_layout\n            )\n            tTMEM_STOREsO_i = thr_tmem_load.partition_D(sOut_i_sub)\n            cute.copy(tiled_smem_store, tTMEM_STORErS_x4_e, tTMEM_STOREsO_i)\n\n        # fence view async shared\n        cute.arch.fence_proxy(\n            cute.arch.ProxyKind.async_shared,\n            space=cute.arch.SharedSpace.shared_cta,\n        )\n\n    @cute.jit\n    def load_k(\n        self,\n        tIn: cute.Tensor,\n        sUpdateB: cute.Tensor,\n        gate: cutlass.Float32,\n        val: cutlass.Float32,\n    ):\n        \"\"\"Load K from TMEM, apply per-token gate decay.\"\"\"\n        tidx, _, _ = cute.arch.thread_idx()\n        thread_idx = tidx % (self.threads_per_warp * (len(self.cudacore_warp_ids)))\n\n        gate_val = cute.math.exp((gate - val))\n\n        k = self.read_tmem_128(tIn)\n\n        k_f16 = cute.make_tensor(\n            cute.recast_ptr(k.iterator, dtype=self.i_dtype),\n            cute.make_layout(128),\n        )\n        k_f16_frag = cute.logical_divide(k_f16, cute.make_layout(8))\n\n        for bid in cutlass.range_constexpr(0, 2):\n            for col in cutlass.range_constexpr(0, 8):\n                load_row = thread_idx\n\n                store_row = load_row\n                store_col = bid * 8 + col\n\n                store_row_bid = store_row // 16\n                store_row_offset = store_row % 16\n                sUpdateB[\n                    ((None, store_col), store_row_offset), 0, store_row_bid, 0\n                ].store(\n                    (k_f16_frag[None, store_col].load() * gate_val).to(self.i_dtype)\n                )\n\n        cute.arch.fence_proxy(\n            cute.arch.ProxyKind.async_shared,\n            space=cute.arch.SharedSpace.shared_cta,\n        )\n\n    @cute.jit\n    def init_state_zeros(\n        self,\n        thr_mma: cute.ThrMma,\n        tOutF32: cute.Tensor,\n    ):\n        \"\"\"Zero-initialize the recurrent state in TMEM (no initial_state provided).\"\"\"\n        tidx, _, _ = cute.arch.thread_idx()\n        thread_idx = tidx % (self.threads_per_warp * (len(self.cudacore_warp_ids)))\n\n        cIn = cute.make_identity_tensor((128, 128))\n        tOcO = thr_mma.partition_C(cIn)\n        corr_tile_size = 128\n\n        # Apply gate State\n        cInOut_i_layout = cute.composition(\n            tOcO.layout, cute.make_layout((128, corr_tile_size))\n        )\n        tInOut_i_layout = cute.composition(\n            tOutF32.layout, cute.make_layout((128, corr_tile_size))\n        )\n\n        tInOut_i = cute.make_tensor(tOutF32.iterator, tInOut_i_layout)\n        cInOut_i = cute.make_tensor(tOcO.iterator, cInOut_i_layout)\n\n        tmem_store_atom_f32 = cute.make_copy_atom(\n            tcgen05.copy.St32x32bOp(tcgen05.copy.Repetition(corr_tile_size)),\n            self.acc_dtype,\n        )\n\n        tiled_tmem_store_f32 = tcgen05.make_tmem_copy(tmem_store_atom_f32, tInOut_i)\n        thr_tmem_store_f32 = tiled_tmem_store_f32.get_slice(thread_idx)\n\n        tTMEM_STOREtInOut = thr_tmem_store_f32.partition_D(tInOut_i)\n        tTMEM_STOREcInOut = thr_tmem_store_f32.partition_S(cInOut_i)\n        tTMEM_STORErInOut = cute.make_rmem_tensor(\n            tTMEM_STOREcInOut.shape, self.acc_dtype\n        )\n\n        frg_tile = 4\n        zeros = cute.zeros_like(cute.make_layout(frg_tile), self.acc_dtype)\n\n        for i in cutlass.range_constexpr(128 // corr_tile_size):\n            tTMEM_STOREtInOut_i = cute.make_tensor(\n                tTMEM_STOREtInOut.iterator + i * corr_tile_size,\n                tTMEM_STOREtInOut.layout,\n            )\n\n            tTMEM_STORErInOut_frg = cute.logical_divide(\n                tTMEM_STORErInOut, ((frg_tile, None), None)\n            )\n\n            each_iter = corr_tile_size // frg_tile\n            for j in cutlass.range_constexpr(each_iter):\n                tTMEM_STORErInOut_frg[((None, j), 0), 0, 0].store(zeros)\n\n            # store\n            cute.copy(tiled_tmem_store_f32, tTMEM_STORErInOut, tTMEM_STOREtInOut_i)\n            cute.arch.fence_view_async_tmem_store()\n\n    @cute.jit\n    def init_state_from_smem(\n        self,\n        thr_mma: cute.ThrMma,\n        tOutF32: cute.Tensor,\n        sStateInputF32: cute.Tensor,\n    ):\n        \"\"\"Load initial_state from smem (f32) into TMEM.\"\"\"\n        tidx, _, _ = cute.arch.thread_idx()\n        thread_idx = tidx % (self.threads_per_warp * (len(self.cudacore_warp_ids)))\n\n        cIn = cute.make_identity_tensor((128, 128))\n        tOcO = thr_mma.partition_C(cIn)\n\n        corr_tile_size = 128\n        cInOut_i_layout = cute.composition(\n            tOcO.layout, cute.make_layout((128, corr_tile_size))\n        )\n        tInOut_i_layout = cute.composition(\n            tOutF32.layout, cute.make_layout((128, corr_tile_size))\n        )\n\n        tInOut_i = cute.make_tensor(tOutF32.iterator, tInOut_i_layout)\n        cInOut_i = cute.make_tensor(tOcO.iterator, cInOut_i_layout)\n\n        tmem_store_atom_f32 = cute.make_copy_atom(\n            tcgen05.copy.St32x32bOp(tcgen05.copy.Repetition(corr_tile_size)),\n            self.acc_dtype,\n        )\n\n        tiled_tmem_store_f32 = tcgen05.make_tmem_copy(tmem_store_atom_f32, tInOut_i)\n        thr_tmem_store_f32 = tiled_tmem_store_f32.get_slice(thread_idx)\n\n        tTMEM_STOREtInOut = thr_tmem_store_f32.partition_D(tInOut_i)\n        tTMEM_STOREcInOut = thr_tmem_store_f32.partition_S(cInOut_i)\n        tTMEM_STORErInOut = cute.make_rmem_tensor(\n            tTMEM_STOREcInOut.shape, self.acc_dtype\n        )\n\n        frg_tile = 4  # must 4\n        sStateInputF32_frag = cute.logical_divide(\n            sStateInputF32, (((None, frg_tile), None))\n        )\n        tTMEM_STORErInOut_frg = cute.logical_divide(\n            tTMEM_STORErInOut, ((frg_tile, None), None)\n        )\n        each_iter = corr_tile_size // frg_tile\n        for i in cutlass.range_constexpr(128 // corr_tile_size):\n            tTMEM_STOREtInOut_i = cute.make_tensor(\n                tTMEM_STOREtInOut.iterator + i * corr_tile_size,\n                tTMEM_STOREtInOut.layout,\n            )\n\n            # Load from smem\n            idx_offset = i * corr_tile_size\n            for j in cutlass.range_constexpr(each_iter):\n                idx = idx_offset + j * frg_tile\n                bid = idx // 32\n                bid_inner = idx % 32 // 8\n                inner_idx = idx % 8 // 4\n                s_vec = sStateInputF32_frag[\n                    (thread_idx, (None, inner_idx)), 0, (bid_inner, bid), 0\n                ].load()\n                tTMEM_STORErInOut_frg[((None, j), 0), 0, 0].store(s_vec)\n\n            # store\n            cute.copy(tiled_tmem_store_f32, tTMEM_STORErInOut, tTMEM_STOREtInOut_i)\n            cute.arch.fence_view_async_tmem_store()\n\n    @cute.jit\n    def load_state_apply_gate(\n        self,\n        thr_mma: cute.ThrMma,\n        tIn: cute.Tensor,\n        sStateInput: cute.Tensor,\n        gate: cutlass.Float32,\n    ):\n        \"\"\"Apply chunk-level gate decay to state in TMEM, and copy state to smem (f16) for KST GEMM.\"\"\"\n        tidx, _, _ = cute.arch.thread_idx()\n        thread_idx = tidx % (self.threads_per_warp * (len(self.cudacore_warp_ids)))\n\n        cIn = cute.make_identity_tensor((128, 128))\n        tOcO = thr_mma.partition_C(cIn)\n\n        corr_tile_size = 16\n        # corr_tile_size_f32 = corr_tile_size // 2\n\n        tIn_i_layout = cute.composition(\n            tIn.layout, cute.make_layout((128, corr_tile_size))\n        )\n        cIn_i_layout = cute.composition(\n            tOcO.layout, cute.make_layout((128, corr_tile_size))\n        )\n\n        # Apply gate State\n        # cInOut_i_layout = cute.composition(tOcO.layout, cute.make_layout((128, corr_tile_size)))\n        tInOut_i_layout = cute.composition(\n            tIn.layout, cute.make_layout((128, corr_tile_size))\n        )\n\n        # fp16 state\n        tIn_i = cute.make_tensor(tIn.iterator, tIn_i_layout)\n        cIn_i = cute.make_tensor(cIn.iterator, cIn_i_layout)\n\n        tInOut_i = cute.make_tensor(tIn.iterator, tInOut_i_layout)\n\n        tmem_load_atom = cute.make_copy_atom(\n            tcgen05.copy.Ld32x32bOp(tcgen05.copy.Repetition(corr_tile_size)),\n            self.acc_dtype,\n        )\n\n        tmem_store_atom_f32 = cute.make_copy_atom(\n            tcgen05.copy.St32x32bOp(tcgen05.copy.Repetition(corr_tile_size)),\n            self.acc_dtype,\n        )\n\n        tiled_tmem_load = tcgen05.make_tmem_copy(tmem_load_atom, tIn_i)\n        tiled_tmem_store_f32 = tcgen05.make_tmem_copy(tmem_store_atom_f32, tInOut_i)\n\n        thr_tmem_load = tiled_tmem_load.get_slice(thread_idx)\n        thr_tmem_store_f32 = tiled_tmem_store_f32.get_slice(thread_idx)\n\n        tTMEM_LOADtO = thr_tmem_load.partition_S(tIn_i)\n        tTMEM_LOADcO = thr_tmem_load.partition_D(cIn_i)\n        tTMEM_LOADrS = cute.make_rmem_tensor(tTMEM_LOADcO.shape, self.acc_dtype)\n\n        tTMEM_STOREtInOut = thr_tmem_store_f32.partition_D(tInOut_i)\n        tTMEM_STORErInOut = cute.make_tensor(\n            cute.recast_ptr(tTMEM_LOADrS.iterator, dtype=self.acc_dtype),\n            tTMEM_LOADrS.layout,\n        )\n\n        gate_val = cute.math.exp(gate)\n        for i in cutlass.range_constexpr(128 // corr_tile_size):\n            tTMEM_LOADtO_i = cute.make_tensor(\n                tTMEM_LOADtO.iterator + i * corr_tile_size, tTMEM_LOADtO.layout\n            )\n            tTMEM_STOREtInOut_i = cute.make_tensor(\n                tTMEM_STOREtInOut.iterator + i * corr_tile_size,\n                tTMEM_STOREtInOut.layout,\n            )\n\n            cute.copy(tiled_tmem_load, tTMEM_LOADtO_i, tTMEM_LOADrS)\n\n            frg_tile = 16  # must <= 16\n            tTMEM_LOADrS_frg = cute.logical_divide(\n                tTMEM_LOADrS, ((frg_tile, None), None)\n            )\n            tTMEM_STORErInOut_frg = cute.logical_divide(\n                tTMEM_STORErInOut, ((frg_tile, None), None)\n            )\n            sStateInput_frag = cute.logical_divide(\n                sStateInput, (((None, frg_tile), None))\n            )\n\n            each_iter = corr_tile_size // frg_tile\n            idx_offset = i * corr_tile_size\n            for j in cutlass.range_constexpr(each_iter):\n                s_vec = tTMEM_LOADrS_frg[((None, j), 0), 0, 0].load()\n                s_vec_f16 = s_vec.to(self.q_dtype)\n                idx = idx_offset + j * frg_tile\n                bid = idx // 64\n                bid_inner = idx % 64 // 16\n                inner_idx = idx % 16 // frg_tile\n                sStateInput_frag[\n                    (thread_idx, (None, inner_idx)), 0, (bid_inner, bid), 0\n                ].store(s_vec_f16)\n                # tTMEM_STORErInOut_frg[((None, j), 0), 0, 0].store(s_vec * gate_val)\n\n                for inner_idx in cutlass.range_constexpr(0, frg_tile, 2):\n                    (\n                        tTMEM_STORErInOut_frg[((inner_idx + 0, j), 0), 0, 0],\n                        tTMEM_STORErInOut_frg[((inner_idx + 1, j), 0), 0, 0],\n                    ) = cute.arch.mul_packed_f32x2(\n                        (s_vec[inner_idx + 0], s_vec[inner_idx + 1]),\n                        (\n                            gate_val,\n                            gate_val,\n                        ),\n                    )\n            cute.copy(tiled_tmem_store_f32, tTMEM_STORErInOut, tTMEM_STOREtInOut_i)\n            cute.arch.fence_view_async_tmem_store()\n\n    @cute.jit\n    def load_qk_epi(\n        self,\n        thr_mma: cute.ThrMma,\n        tIn: cute.Tensor,\n        tOut: cute.Tensor,\n        tGamma: cute.Tensor,  # causal gate mask\n        mask: cutlass.Constexpr[cutlass.Boolean] = False,\n        tail_count: Int32 = 128,\n    ):\n        \"\"\"Apply gamma mask to QK^T.\"\"\"\n        tidx, _, _ = cute.arch.thread_idx()\n        thread_idx = tidx % (self.threads_per_warp * (len(self.cudacore_warp_ids)))\n\n        cIn = cute.make_identity_tensor((128, 128))\n        tOcO = thr_mma.partition_C(cIn)\n\n        corr_tile_size = 32\n        corr_tile_size_f32 = corr_tile_size // 2\n\n        tIn_i_layout = cute.composition(\n            tIn.layout, cute.make_layout((128, corr_tile_size))\n        )\n        cIn_i_layout = cute.composition(\n            tOcO.layout, cute.make_layout((128, corr_tile_size))\n        )\n\n        cOut_i_layout = cute.composition(\n            tOcO.layout, cute.make_layout((128, corr_tile_size_f32))\n        )\n        tOut_i_layout = cute.composition(\n            tOut.layout, cute.make_layout((128, corr_tile_size_f32))\n        )\n\n        tIn_i = cute.make_tensor(tIn.iterator, tIn_i_layout)\n        tGamma_i = cute.make_tensor(tGamma.iterator, tIn_i_layout)\n        cIn_i = cute.make_tensor(cIn.iterator, cIn_i_layout)\n\n        tOut_i = cute.make_tensor(tOut.iterator, tOut_i_layout)\n        cOut_i = cute.make_tensor(tOcO.iterator, cOut_i_layout)\n\n        tmem_load_atom = cute.make_copy_atom(\n            tcgen05.copy.Ld32x32bOp(tcgen05.copy.Repetition(corr_tile_size)),\n            self.acc_dtype,\n        )\n        tmem_store_atom = cute.make_copy_atom(\n            tcgen05.copy.St32x32bOp(tcgen05.copy.Repetition(corr_tile_size_f32)),\n            self.acc_dtype,\n        )\n\n        tiled_tmem_load = tcgen05.make_tmem_copy(tmem_load_atom, tIn_i)\n        tiled_tmem_store = tcgen05.make_tmem_copy(tmem_store_atom, tOut_i)\n\n        thr_tmem_load = tiled_tmem_load.get_slice(thread_idx)\n        thr_tmem_store = tiled_tmem_store.get_slice(thread_idx)\n\n        # Load Gamma\n        tiled_tmem_load_gamma = tcgen05.make_tmem_copy(tmem_load_atom, tGamma_i)\n        thr_tmem_load_gamma = tiled_tmem_load_gamma.get_slice(thread_idx)\n\n        tTMEM_LOADtO = thr_tmem_load.partition_S(tIn_i)\n        tTMEM_LOADcO = thr_tmem_load.partition_D(cIn_i)\n\n        tTMEM_STOREcS = thr_tmem_store.partition_S(cOut_i)\n        tTMEM_STOREtO = thr_tmem_store.partition_D(tOut_i)\n        tTMEM_LOADrS = cute.make_rmem_tensor(tTMEM_LOADcO.shape, self.acc_dtype)\n\n        tTMEM_LOADtG = thr_tmem_load_gamma.partition_S(tGamma_i)\n        tTMEM_LOADrG = cute.make_rmem_tensor(tTMEM_LOADcO.shape, self.acc_dtype)\n\n        tTMEM_STORErS_x4 = cute.make_rmem_tensor(tTMEM_STOREcS.shape, self.acc_dtype)\n        tTMEM_STORErS_x4_e = cute.make_tensor(\n            cute.recast_ptr(tTMEM_STORErS_x4.iterator, dtype=self.i_dtype),\n            tTMEM_LOADrS.layout,\n        )\n\n        for i in cutlass.range_constexpr(128 // corr_tile_size):\n            tTMEM_LOADtO_i = cute.make_tensor(\n                tTMEM_LOADtO.iterator + i * corr_tile_size, tTMEM_LOADtO.layout\n            )\n            tTMEM_STOREtO_i = cute.make_tensor(\n                tTMEM_STOREtO.iterator + i * corr_tile_size_f32, tTMEM_STOREtO.layout\n            )\n            tTMEM_LOADtG_i = cute.make_tensor(\n                tTMEM_LOADtG.iterator + i * corr_tile_size, tTMEM_LOADrG.layout\n            )\n\n            cute.copy(tiled_tmem_load, tTMEM_LOADtO_i, tTMEM_LOADrS)\n            cute.copy(tiled_tmem_load_gamma, tTMEM_LOADtG_i, tTMEM_LOADrG)\n\n            frg_tile = 2\n            tTMEM_LOADrS_frg = cute.logical_divide(\n                tTMEM_LOADrS, ((frg_tile, None), None)\n            )\n            tTMEM_LOADrG_frg = cute.logical_divide(\n                tTMEM_LOADrG, ((frg_tile, None), None)\n            )\n            tTMEM_STORErS_x4_e_frg = cute.logical_divide(\n                tTMEM_STORErS_x4_e, cute.make_layout(frg_tile)\n            )\n\n            each_iter = corr_tile_size // frg_tile\n            for j in cutlass.range_constexpr(each_iter):\n                for it in cutlass.range_constexpr(0, frg_tile, 2):\n                    (\n                        tTMEM_LOADrS_frg[((it + 0, j), 0), 0, 0],\n                        tTMEM_LOADrS_frg[((it + 1, j), 0), 0, 0],\n                    ) = cute.arch.mul_packed_f32x2(\n                        (\n                            tTMEM_LOADrS_frg[((it + 0, j), 0), 0, 0],\n                            tTMEM_LOADrS_frg[((it + 1, j), 0), 0, 0],\n                        ),\n                        (\n                            tTMEM_LOADrG_frg[((it + 0, j), 0), 0, 0],\n                            tTMEM_LOADrG_frg[((it + 1, j), 0), 0, 0],\n                        ),\n                    )\n\n                s_vec = tTMEM_LOADrS_frg[((None, j), 0), 0, 0].load()\n                tTMEM_STORErS_x4_e_frg[None, j].store(s_vec.to(self.q_dtype))\n\n            # store\n            cute.copy(tiled_tmem_store, tTMEM_STORErS_x4, tTMEM_STOREtO_i)\n            cute.arch.fence_view_async_tmem_store()\n\n    @cute.jit\n    def load_q_epi(\n        self,\n        thr_mma: cute.ThrMma,\n        sQ: cute.Tensor,\n        tOut: cute.Tensor,\n        val: cutlass.Float32,  # exp(cumsum_gate) for per-token gating\n        mask: cutlass.Constexpr[cutlass.Boolean] = False,\n        tail_count: Int32 = 128,\n    ):\n        \"\"\"Load Q from smem, apply per-token gate.\"\"\"\n        tidx, _, _ = cute.arch.thread_idx()\n        thread_idx = tidx % (self.threads_per_warp * (len(self.cudacore_warp_ids)))\n\n        sQ_frag = cute.logical_divide(sQ, (((None, 8), None)))\n        cIn = cute.make_identity_tensor((128, 128))\n        tOcO = thr_mma.partition_C(cIn)\n\n        corr_tile_size = 64\n        corr_tile_size_f32 = corr_tile_size // 2\n\n        cIn_i_layout = cute.composition(\n            tOcO.layout, cute.make_layout((128, corr_tile_size))\n        )\n        cOut_i_layout = cute.composition(\n            tOcO.layout, cute.make_layout((128, corr_tile_size_f32))\n        )\n        tOut_i_layout = cute.composition(\n            tOut.layout, cute.make_layout((128, corr_tile_size_f32))\n        )\n\n        cIn_i = cute.make_tensor(cIn.iterator, cIn_i_layout)\n        tOut_i = cute.make_tensor(tOut.iterator, tOut_i_layout)\n        cOut_i = cute.make_tensor(tOcO.iterator, cOut_i_layout)\n\n        tmem_store_atom = cute.make_copy_atom(\n            tcgen05.copy.St32x32bOp(tcgen05.copy.Repetition(corr_tile_size_f32)),\n            self.acc_dtype,\n        )\n\n        tiled_tmem_store = tcgen05.make_tmem_copy(tmem_store_atom, tOut_i)\n        thr_tmem_store = tiled_tmem_store.get_slice(thread_idx)\n\n        tTMEM_STOREcS_f16 = thr_tmem_store.partition_S(cIn_i)\n        tTMEM_STOREcS = thr_tmem_store.partition_S(cOut_i)\n        tTMEM_STOREtO = thr_tmem_store.partition_D(tOut_i)\n\n        tTMEM_STORErS = cute.make_rmem_tensor(tTMEM_STOREcS.shape, self.acc_dtype)\n        tTMEM_STORErS_x8 = cute.make_rmem_tensor(tTMEM_STOREcS_f16.shape, self.i_dtype)\n        tTMEM_STORErS_x8_e = cute.make_tensor(\n            cute.recast_ptr(tTMEM_STORErS.iterator, dtype=self.i_dtype),\n            tTMEM_STORErS_x8.layout,\n        )\n\n        for i in cutlass.range_constexpr(128 // corr_tile_size):\n            tTMEM_STOREtO_i = cute.make_tensor(\n                tTMEM_STOREtO.iterator + i * corr_tile_size_f32, tTMEM_STOREtO.layout\n            )\n\n            frg_tile = 8\n            tTMEM_STORErS_x8_e_frag = cute.logical_divide(\n                tTMEM_STORErS_x8_e, cute.make_layout(frg_tile)\n            )\n            for col in cutlass.range_constexpr(0, 8):\n                load_row = thread_idx\n                load_col = col\n                curr_val_ssa = sQ_frag[\n                    (load_row, (None, load_col % 2)), 0, (load_col // 2, i), 0\n                ].load()\n                tTMEM_STORErS_x8_e_frag[None, col].store(\n                    (curr_val_ssa * val).to(self.i_dtype)\n                )\n            # store\n            if cutlass.const_expr(mask):\n                if thread_idx >= tail_count:\n                    tTMEM_STORErS_x8_e_frag.fill(self.i_dtype(0))\n            cute.copy(tiled_tmem_store, tTMEM_STORErS, tTMEM_STOREtO_i)\n\n        cute.arch.fence_view_async_tmem_store()\n\n    @cute.jit\n    def store_k_epi(\n        self,\n        thr_mma: cute.ThrMma,\n        sK: cute.Tensor,\n        tOut: cute.Tensor,\n        mask: cutlass.Constexpr[cutlass.Boolean] = False,\n        tail_count: Int32 = 128,\n    ):\n        \"\"\"Load K from smem and store to TMEM.\"\"\"\n        tidx, _, _ = cute.arch.thread_idx()\n\n        thread_idx = tidx % (self.threads_per_warp * (len(self.cudacore_warp_ids)))\n\n        sK_frag = cute.logical_divide(sK, (((None, 8), None)))\n        cIn = cute.make_identity_tensor((128, 128))\n        tOcO = thr_mma.partition_C(cIn)\n\n        corr_tile_size = 64\n        corr_tile_size_f32 = corr_tile_size // 2\n\n        cIn_i_layout = cute.composition(\n            tOcO.layout, cute.make_layout((128, corr_tile_size))\n        )\n        cOut_i_layout = cute.composition(\n            tOcO.layout, cute.make_layout((128, corr_tile_size_f32))\n        )\n        tOut_i_layout = cute.composition(\n            tOut.layout, cute.make_layout((128, corr_tile_size_f32))\n        )\n\n        cIn_i = cute.make_tensor(cIn.iterator, cIn_i_layout)\n        tOut_i = cute.make_tensor(tOut.iterator, tOut_i_layout)\n        cOut_i = cute.make_tensor(tOcO.iterator, cOut_i_layout)\n\n        tmem_store_atom = cute.make_copy_atom(\n            tcgen05.copy.St32x32bOp(tcgen05.copy.Repetition(corr_tile_size_f32)),\n            self.acc_dtype,\n        )\n\n        tiled_tmem_store = tcgen05.make_tmem_copy(tmem_store_atom, tOut_i)\n        thr_tmem_store = tiled_tmem_store.get_slice(thread_idx)\n\n        tTMEM_STOREcS_f16 = thr_tmem_store.partition_S(cIn_i)\n        tTMEM_STOREcS = thr_tmem_store.partition_S(cOut_i)\n        tTMEM_STOREtO = thr_tmem_store.partition_D(tOut_i)\n\n        tTMEM_STORErS = cute.make_rmem_tensor(tTMEM_STOREcS.shape, self.acc_dtype)\n        tTMEM_STORErS_x8 = cute.make_rmem_tensor(tTMEM_STOREcS_f16.shape, self.i_dtype)\n        tTMEM_STORErS_x8_e = cute.make_tensor(\n            cute.recast_ptr(tTMEM_STORErS.iterator, dtype=self.i_dtype),\n            tTMEM_STORErS_x8.layout,\n        )\n        frg_tile = 8\n        tTMEM_STORErS_x8_e_frag = cute.logical_divide(\n            tTMEM_STORErS_x8_e, cute.make_layout(frg_tile)\n        )\n        for i in cutlass.range_constexpr(128 // corr_tile_size):\n            tTMEM_STOREtO_i = cute.make_tensor(\n                tTMEM_STOREtO.iterator + i * corr_tile_size_f32, tTMEM_STOREtO.layout\n            )\n\n            for col in cutlass.range_constexpr(0, 8):\n                load_row = thread_idx\n\n                load_col = col\n                curr_val_ssa = sK_frag[\n                    (load_row, (None, load_col % 2)), 0, (load_col // 2, i), 0\n                ].load()\n                tTMEM_STORErS_x8_e_frag[None, col].store(curr_val_ssa)\n\n            # store\n            if cutlass.const_expr(mask):\n                if thread_idx >= tail_count:\n                    tTMEM_STORErS_x8_e_frag.fill(self.i_dtype(0))\n\n            cute.copy(tiled_tmem_store, tTMEM_STORErS, tTMEM_STOREtO_i)\n        cute.arch.fence_view_async_tmem_store()\n\n    @cute.jit\n    def reverse_smem_sub(\n        self,\n        reverse_result: cute.Tensor,\n        sIvt: cute.Tensor,\n    ):\n        \"\"\"Compute the inverse of a 32x32 sub-block.\"\"\"\n        lane_id = cute.arch.lane_idx()\n        sub_widx = cute.arch.warp_idx() % 4\n\n        reverse_result.fill(self.acc_dtype(0))\n\n        for row in cutlass.range_constexpr(1, 32, unroll=1):\n            for k in cutlass.range(1, row):\n                row_i_k = sIvt[(k, row), sub_widx]\n                reverse_result[row] -= reverse_result[k] * row_i_k\n            row_i_lane = self.acc_dtype(0)\n            if lane_id < row:\n                row_i_lane = sIvt[(lane_id, row), sub_widx]\n            reverse_result[row] -= row_i_lane\n        reverse_result[lane_id] = self.acc_dtype(1)\n\n    @cute.jit\n    def store_ivt_smem_l0_ss_a(\n        self,\n        reverse_result: cute.Tensor,\n        sReg: cute.Tensor,\n        sInvertSubSSL0A: cute.Tensor,\n    ):\n        \"\"\"Store 32x32 sub-inverse results to smem.\"\"\"\n\n        tidx, _, _ = cute.arch.thread_idx()\n        widx = cute.arch.warp_idx()\n        lane_id = cute.arch.lane_idx()\n\n        sub_widx = widx % 4\n\n        # store sub result to shared memory\n        # (((4,128),8))\n        for row_bid in cutlass.range_constexpr(4):\n            for col_bid in cutlass.range_constexpr(8):\n                row_d = (lane_id // 4 + col_bid) % 8\n                row = row_bid * 8 + row_d\n                col_id = lane_id // 4\n                col_sub_id = lane_id % 4\n                sReg[(col_sub_id, sub_widx * 32 + row), col_id] = reverse_result[row]\n\n        cutlass.cute.arch.sync_warp()\n\n        if sub_widx == 1 or sub_widx == 3:\n            sub_id_row = sub_widx // 2\n            sInvertSubSSL0A_frag = cute.logical_divide(\n                sInvertSubSSL0A, ((None, 4), None)\n            )\n            for col in cutlass.range_constexpr(8):\n                sInvertSubSSL0A_frag[\n                    (sub_id_row * 32 + lane_id, (None, col % 2)), 0, col // 2, 0\n                ].store(sReg[(None, tidx % 128), col].load())\n\n    @cute.jit\n    def store_ivt_smem_l0_ss_b(\n        self,\n        thr_mma: cute.ThrMma,\n        tIn: cute.Tensor,\n        sInvertSubSSL0B: cute.Tensor,\n    ):\n        tidx, _, _ = cute.arch.thread_idx()\n        # bidx, bidy, _ = cute.arch.block_idx()\n        widx = cute.arch.warp_idx()\n        lane_id = cute.arch.lane_idx()\n        thread_idx = tidx % (self.threads_per_warp * (len(self.cudacore_warp_ids)))\n\n        sub_widx = widx % 4\n\n        # load Tmem\n        cIn = cute.make_identity_tensor((128, 128))\n        tOcO = thr_mma.partition_C(cIn)\n\n        corr_tile_size = 32  # must <= 32\n        tIn_i_layout = cute.composition(\n            tIn.layout, cute.make_layout((128, corr_tile_size))\n        )\n        cIn_i_layout = cute.composition(\n            tOcO.layout, cute.make_layout((128, corr_tile_size))\n        )\n        tIn_i = cute.make_tensor(tIn.iterator, tIn_i_layout)\n        cIn_i = cute.make_tensor(cIn.iterator, cIn_i_layout)\n\n        tmem_load_atom = cute.make_copy_atom(\n            tcgen05.copy.Ld32x32bOp(tcgen05.copy.Repetition(corr_tile_size)),\n            self.acc_dtype,\n        )\n\n        # Load In\n        tiled_tmem_load = tcgen05.make_tmem_copy(tmem_load_atom, tIn_i)\n        thr_tmem_load = tiled_tmem_load.get_slice(thread_idx)\n\n        tTMEM_LOADtO = thr_tmem_load.partition_S(tIn_i)\n        tTMEM_LOADcO = thr_tmem_load.partition_D(cIn_i)\n\n        tTMEM_LOADrS = cute.make_rmem_tensor(tTMEM_LOADcO.shape, self.acc_dtype)\n\n        sub_tile_size = 8\n        tmem_frag = cute.logical_divide(tTMEM_LOADrS, ((sub_tile_size, None), None))\n        sInvertSubSSL0B_frag = cute.logical_divide(\n            sInvertSubSSL0B, ((sub_tile_size, None), None)\n        )\n\n        # tile 0\n        tile_frags = corr_tile_size // sub_tile_size\n        for i in cutlass.range_constexpr(32 // corr_tile_size):\n            tTMEM_LOADtO_i = cute.make_tensor(\n                tTMEM_LOADtO.iterator + i * corr_tile_size, tTMEM_LOADtO.layout\n            )\n\n            cute.copy(tiled_tmem_load, tTMEM_LOADtO_i, tTMEM_LOADrS)\n            cute.arch.fence_view_async_tmem_load()\n            if sub_widx == 1:\n                idx = (i * corr_tile_size) // sub_tile_size\n                for j in cutlass.range_constexpr(tile_frags):\n                    col_true = (idx + j) % 8\n                    # todo: remove smem bank conflict\n                    sInvertSubSSL0B_frag[\n                        ((None, (col_true, 0)), lane_id % 8), 0, lane_id // 8, 0\n                    ].store(tmem_frag[((None, j), 0), 0, 0].load())\n\n        # tile 2\n        for i in cutlass.range_constexpr(32 // corr_tile_size):\n            tTMEM_LOADtO_i = cute.make_tensor(\n                tTMEM_LOADtO.iterator + 64 + i * corr_tile_size, tTMEM_LOADtO.layout\n            )\n\n            cute.copy(tiled_tmem_load, tTMEM_LOADtO_i, tTMEM_LOADrS)\n            cute.arch.fence_view_async_tmem_load()\n            if sub_widx == 3:\n                idx = (i * corr_tile_size) // sub_tile_size\n                for j in cutlass.range_constexpr(tile_frags):\n                    col_true = (idx + j) % 8\n                    # todo: remove smem bank conflict\n                    sInvertSubSSL0B_frag[\n                        ((None, (col_true, 1)), lane_id % 8), 0, lane_id // 8, 0\n                    ].store(tmem_frag[((None, j), 0), 0, 0].load())\n\n        cute.arch.fence_proxy(\n            cute.arch.ProxyKind.async_shared,\n            space=cute.arch.SharedSpace.shared_cta,\n        )\n\n    @cute.jit\n    def store_ivt_smem_l1_ss_b(\n        self,\n        thr_mma: cute.ThrMma,\n        tIn: cute.Tensor,\n        sInvertSubSSL1B: cute.Tensor,\n    ):\n        tidx, _, _ = cute.arch.thread_idx()\n        # bidx, bidy, _ = cute.arch.block_idx()\n        widx = cute.arch.warp_idx()\n        lane_id = cute.arch.lane_idx()\n        thread_idx = tidx % (self.threads_per_warp * (len(self.cudacore_warp_ids)))\n\n        sub_widx = widx % 4\n\n        # load Tmem\n        cIn = cute.make_identity_tensor((128, 128))\n        tOcO = thr_mma.partition_C(cIn)\n\n        corr_tile_size = 8\n        tIn_i_layout = cute.composition(\n            tIn.layout, cute.make_layout((128, corr_tile_size))\n        )\n        cIn_i_layout = cute.composition(\n            tOcO.layout, cute.make_layout((128, corr_tile_size))\n        )\n        tIn_i = cute.make_tensor(tIn.iterator, tIn_i_layout)\n        cIn_i = cute.make_tensor(cIn.iterator, cIn_i_layout)\n\n        tmem_load_atom = cute.make_copy_atom(\n            tcgen05.copy.Ld32x32bOp(tcgen05.copy.Repetition(corr_tile_size)),\n            self.acc_dtype,\n        )\n\n        # Load In\n        tiled_tmem_load = tcgen05.make_tmem_copy(tmem_load_atom, tIn_i)\n        thr_tmem_load = tiled_tmem_load.get_slice(thread_idx)\n\n        tTMEM_LOADtO = thr_tmem_load.partition_S(tIn_i)\n        tTMEM_LOADcO = thr_tmem_load.partition_D(cIn_i)\n\n        tTMEM_LOADrS = cute.make_rmem_tensor(tTMEM_LOADcO.shape, self.acc_dtype)\n\n        # tile 0\n        tTMEM_LOADtO_i = cute.make_tensor(tTMEM_LOADtO.iterator, tTMEM_LOADtO.layout)\n\n        cute.copy(tiled_tmem_load, tTMEM_LOADtO_i, tTMEM_LOADrS)\n        cute.arch.fence_view_async_tmem_load()\n        sub_tile_size = 8\n        tmem_frag = cute.logical_divide(tTMEM_LOADrS, ((sub_tile_size, None), None))\n        sInvertSubSSL1B_frag = cute.logical_divide(\n            sInvertSubSSL1B, ((sub_tile_size, None), None)\n        )\n        tile_frags = corr_tile_size // sub_tile_size\n        if sub_widx == 2 or sub_widx == 3:\n            sub_id_row = sub_widx - 2\n            for col in cutlass.range_constexpr(tile_frags):\n                col_true = (lane_id + col) % (tile_frags)\n                sInvertSubSSL1B_frag[\n                    ((None, (col_true, 0)), lane_id % 8),\n                    0,\n                    lane_id // 8 + sub_id_row * 4,\n                    0,\n                ].store(tmem_frag[((None, col_true), 0), 0, 0].load())\n\n        # tile 0\n        for i in cutlass.range_constexpr(32 // corr_tile_size):\n            tTMEM_LOADtO_i = cute.make_tensor(\n                tTMEM_LOADtO.iterator + i * corr_tile_size, tTMEM_LOADtO.layout\n            )\n\n            cute.copy(tiled_tmem_load, tTMEM_LOADtO_i, tTMEM_LOADrS)\n            cute.arch.fence_view_async_tmem_load()\n            if sub_widx == 2 or sub_widx == 3:\n                sub_id_row = sub_widx - 2\n                idx = (i * corr_tile_size) // sub_tile_size\n                for j in cutlass.range_constexpr(tile_frags):\n                    col_true = (idx + j) % 8\n                    # todo: remove smem bank conflict\n                    sInvertSubSSL1B_frag[\n                        ((None, (col_true, 0)), lane_id % 8),\n                        0,\n                        lane_id // 8 + sub_id_row * 4,\n                        0,\n                    ].store(tmem_frag[((None, j), 0), 0, 0].load())\n        # tile 1\n        for i in cutlass.range_constexpr(32 // corr_tile_size):\n            tTMEM_LOADtO_i = cute.make_tensor(\n                tTMEM_LOADtO.iterator + 32 + i * corr_tile_size, tTMEM_LOADtO.layout\n            )\n\n            cute.copy(tiled_tmem_load, tTMEM_LOADtO_i, tTMEM_LOADrS)\n            cute.arch.fence_view_async_tmem_load()\n            if sub_widx == 2 or sub_widx == 3:\n                sub_id_row = sub_widx - 2\n                idx = (i * corr_tile_size) // sub_tile_size\n                for j in cutlass.range_constexpr(tile_frags):\n                    col_true = (idx + j) % 8\n                    # todo: remove smem bank conflict\n                    sInvertSubSSL1B_frag[\n                        ((None, (col_true, 1)), lane_id % 8),\n                        0,\n                        lane_id // 8 + sub_id_row * 4,\n                        0,\n                    ].store(tmem_frag[((None, j), 0), 0, 0].load())\n\n    @cute.jit\n    def store_ivt_p1(\n        self,\n        sReg: cute.Tensor,\n        sInvertSubTSL0B: cute.Tensor,\n    ):\n        \"\"\"Store sub-inverse register results p1 to smem.\"\"\"\n        tidx, _, _ = cute.arch.thread_idx()\n        widx = cute.arch.warp_idx()\n        lane_id = cute.arch.lane_idx()\n\n        sub_widx = widx % 4\n\n        sInvertSubTSL0B_frag = cute.logical_divide(sInvertSubTSL0B, ((4, None), None))\n        if sub_widx == 0 or sub_widx == 2:\n            sub_id_row = sub_widx // 2\n            for col in cutlass.range_constexpr(8):\n                col_true = (lane_id + col) % 8\n                sInvertSubTSL0B_frag[\n                    ((None, (col_true, sub_id_row)), lane_id % 8), 0, lane_id // 8, 0\n                ].store(sReg[(None, tidx % 128), col_true].load())\n\n        cute.arch.fence_proxy(\n            cute.arch.ProxyKind.async_shared,\n            space=cute.arch.SharedSpace.shared_cta,\n        )\n\n    @cute.jit\n    def store_ivt_p2(\n        self,\n        sReg: cute.Tensor,\n        sInvertSubSSL1A: cute.Tensor,\n    ):\n        \"\"\"Store sub-inverse register results p2 to smem.\"\"\"\n        tidx, _, _ = cute.arch.thread_idx()\n        widx = cute.arch.warp_idx()\n        lane_id = cute.arch.lane_idx()\n\n        sub_widx = widx % 4\n        sInvertSubSSL1A_frag = cute.logical_divide(sInvertSubSSL1A, ((None, 4), None))\n        zeros = cute.zeros_like(cute.make_layout((4, 1)), self.acc_dtype)\n        if sub_widx == 2 or sub_widx == 3:\n            sub_id_row = sub_widx - 2\n            for col in cutlass.range_constexpr(8):\n                sInvertSubSSL1A_frag[\n                    (sub_id_row * 32 + lane_id, (None, col % 2)),\n                    0,\n                    (col // 2, sub_id_row),\n                    0,\n                ].store(sReg[(None, tidx % 128), col].load())\n\n        if sub_widx == 0 or sub_widx == 1:\n            for col in cutlass.range_constexpr(4):\n                col_true = col + sub_widx * 4\n                sInvertSubSSL1A_frag[\n                    (lane_id, (None, col_true % 2)), 0, (col_true // 2, 1), 0\n                ].store(zeros)\n        cute.arch.fence_proxy(\n            cute.arch.ProxyKind.async_shared,\n            space=cute.arch.SharedSpace.shared_cta,\n        )\n\n    @cute.jit\n    def store_ivt_p3(\n        self,\n        sReg: cute.Tensor,\n        sInvertSubTSL1B: cute.Tensor,\n    ):\n        \"\"\"Store sub-inverse register results p3 to smem .\"\"\"\n        tidx, _, _ = cute.arch.thread_idx()\n        widx = cute.arch.warp_idx()\n        lane_id = cute.arch.lane_idx()\n\n        sub_widx = widx % 4\n        sInvertSubTSL1B_frag = cute.logical_divide(sInvertSubTSL1B, ((4, None), None))\n        if sub_widx == 0 or sub_widx == 1:\n            sub_id_row = sub_widx\n            for col in cutlass.range_constexpr(8):\n                col_true = (lane_id + col) % 8\n                sInvertSubTSL1B_frag[\n                    ((None, (col_true, sub_id_row)), lane_id % 8),\n                    0,\n                    lane_id // 8 + 4 * sub_id_row,\n                    0,\n                ].store(sReg[(None, tidx % 128), col_true].load())\n        zeros = cute.zeros_like(cute.make_layout((4, 1)), self.acc_dtype)\n\n        if sub_widx == 2 or sub_widx == 3:\n            sub_id_row = sub_widx - 2\n            for col in cutlass.range_constexpr(4):\n                col_true = (lane_id + col + sub_id_row * 4) % 8\n                sInvertSubTSL1B_frag[\n                    ((None, (col_true, 1)), lane_id % 8), 0, lane_id // 8 + 0, 0\n                ].store(zeros)\n        cute.arch.fence_proxy(\n            cute.arch.ProxyKind.async_shared,\n            space=cute.arch.SharedSpace.shared_cta,\n        )\n\n    @cute.jit\n    def load_store_tmem_tune(\n        self,\n        thr_mma: cute.ThrMma,\n        tIn: cute.Tensor,\n        tOut: cute.Tensor,  # unused utility for TMEM round-trip debugging\n    ):\n        tidx, _, _ = cute.arch.thread_idx()\n        thread_idx = tidx % (self.threads_per_warp * (len(self.cudacore_warp_ids)))\n\n        cIn = cute.make_identity_tensor((128, 128))\n        tOcO = thr_mma.partition_C(cIn)\n\n        corr_tile_size = 16\n        tIn_i_layout = cute.composition(\n            tIn.layout, cute.make_layout((128, corr_tile_size))\n        )\n        cIn_i_layout = cute.composition(\n            tOcO.layout, cute.make_layout((128, corr_tile_size))\n        )\n\n        tOut_i_layout = cute.composition(\n            tOut.layout, cute.make_layout((128, corr_tile_size))\n        )\n\n        tIn_i = cute.make_tensor(tIn.iterator, tIn_i_layout)\n        cIn_i = cute.make_tensor(cIn.iterator, cIn_i_layout)\n\n        tOut_i = cute.make_tensor(tOut.iterator, tOut_i_layout)\n\n        tmem_load_atom = cute.make_copy_atom(\n            tcgen05.copy.Ld32x32bOp(tcgen05.copy.Repetition(corr_tile_size)),\n            self.acc_dtype,\n        )\n        tmem_store_atom = cute.make_copy_atom(\n            tcgen05.copy.St32x32bOp(tcgen05.copy.Repetition(corr_tile_size)),\n            self.acc_dtype,\n        )\n\n        tiled_tmem_load = tcgen05.make_tmem_copy(tmem_load_atom, tIn_i)\n        tiled_tmem_store = tcgen05.make_tmem_copy(tmem_store_atom, tOut_i)\n\n        thr_tmem_load = tiled_tmem_load.get_slice(thread_idx)\n        thr_tmem_store = tiled_tmem_store.get_slice(thread_idx)\n\n        tTMEM_LOADtO = thr_tmem_load.partition_S(tIn_i)\n        tTMEM_LOADcO = thr_tmem_load.partition_D(cIn_i)\n\n        tTMEM_STOREtO = thr_tmem_store.partition_D(tOut_i)\n\n        tTMrO = cute.make_rmem_tensor(\n            (tTMEM_LOADcO.shape, 128 // corr_tile_size), self.acc_dtype\n        )\n\n        for i in cutlass.range_constexpr(128 // corr_tile_size):\n            tTMrO_i_ = tTMrO[None, i]\n            tTMrO_i_layout = cute.composition(\n                tTMrO_i_.layout, cute.make_layout(tTMrO.shape[0])\n            )\n            tTMrO_i = cute.make_tensor(tTMrO_i_.iterator, tTMrO_i_layout)\n            tTMEM_LOADtO_i = cute.make_tensor(\n                tTMEM_LOADtO.iterator + i * corr_tile_size, tTMEM_LOADtO.layout\n            )\n            tTMEM_STOREtO_i = cute.make_tensor(\n                tTMEM_STOREtO.iterator + i * corr_tile_size, tTMEM_STOREtO.layout\n            )\n\n            cute.copy(tiled_tmem_load, tTMEM_LOADtO_i, tTMrO_i)\n\n            for j in cutlass.range_constexpr(0, cute.size(tTMrO_i), 2):\n                tTMrO_i[j], tTMrO_i[j + 1] = cute.arch.mul_packed_f32x2(\n                    (tTMrO_i[j], tTMrO_i[j + 1]),\n                    (cutlass.Float32(1), cutlass.Float32(1)),\n                )\n\n            # store\n            cute.copy(tiled_tmem_store, tTMrO_i, tTMEM_STOREtO_i)\n\n    @cute.jit\n    def read_tmem_128(\n        self,\n        tIn: cute.Tensor,\n    ):\n        \"\"\"Read a 128-element vector from TMEM into registers.\"\"\"\n        tidx, _, _ = cute.arch.thread_idx()\n\n        thread_idx = tidx % (self.threads_per_warp * (len(self.cudacore_warp_ids)))\n\n        tIn_layout = cute.composition(tIn.layout, cute.make_layout((tIn.shape)))\n        tIn = cute.make_tensor(tIn.iterator, tIn_layout)\n\n        # Load from tmem\n        copy_atom_t2r = cute.make_copy_atom(\n            tcgen05.copy.Ld32x32bOp(tcgen05.copy.Repetition(32)),\n            self.acc_dtype,\n        )\n\n        tiled_copy_t2r = tcgen05.make_tmem_copy(copy_atom_t2r, tIn)\n        thr_copy_t2r = tiled_copy_t2r.get_slice(thread_idx)\n        tTR_tO = thr_copy_t2r.partition_S(tIn)\n        tTR_cO = thr_copy_t2r.partition_D(tIn)\n\n        tTR_rO = cute.make_rmem_tensor(tTR_cO.shape, self.acc_dtype)\n\n        tTR_tO = cute.group_modes(tTR_tO, 1, cute.rank(tTR_tO))\n        tTR_rO = cute.group_modes(tTR_rO, 1, cute.rank(tTR_rO))\n        cute.copy(tiled_copy_t2r, tTR_tO, tTR_rO)\n        cute.arch.fence_view_async_tmem_load()\n\n        return tTR_rO\n\n    @cute.jit\n    def load_v(\n        self,\n        tIn: cute.Tensor,\n        sNewV: cute.Tensor,\n    ):\n        \"\"\"Load V_new from TMEM, convert to f16, store to smem.\"\"\"\n        tidx, _, _ = cute.arch.thread_idx()\n\n        thread_idx = tidx % (self.threads_per_warp * (len(self.cudacore_warp_ids)))\n\n        tIn_layout = cute.composition(tIn.layout, cute.make_layout((tIn.shape)))\n        tIn = cute.make_tensor(tIn.iterator, tIn_layout)\n\n        # Load from tmem\n        copy_atom_t2r = cute.make_copy_atom(\n            tcgen05.copy.Ld32x32bOp(tcgen05.copy.Repetition(32)),\n            self.acc_dtype,\n        )\n\n        tiled_copy_t2r = tcgen05.make_tmem_copy(copy_atom_t2r, tIn)\n        thr_copy_t2r = tiled_copy_t2r.get_slice(thread_idx)\n\n        tTR_tO = thr_copy_t2r.partition_S(tIn)\n        tTR_cO = thr_copy_t2r.partition_D(tIn)\n\n        tTR_rO = cute.make_rmem_tensor(tTR_cO.shape, self.acc_dtype)\n\n        tTR_tO = cute.group_modes(tTR_tO, 1, cute.rank(tTR_tO))\n        tTR_rO = cute.group_modes(tTR_rO, 1, cute.rank(tTR_rO))\n        cute.copy(tiled_copy_t2r, tTR_tO, tTR_rO)\n        cute.arch.fence_view_async_tmem_load()\n\n        tTR_rO_e = cute.make_rmem_tensor(tTR_cO.shape, self.i_dtype)\n        frg_cnt = 16\n        frg_tile = cute.size(tTR_rO) // frg_cnt\n        tTR_rO_frg = cute.logical_divide(tTR_rO, cute.make_layout(frg_tile))\n        tTR_rO_e_frg = cute.logical_divide(tTR_rO_e, cute.make_layout(frg_tile))\n        for j in cutlass.range_constexpr(frg_cnt):\n            r_vec = tTR_rO_frg[None, j].load()\n            tTR_rO_e_frg[None, j].store(r_vec.to(self.i_dtype))\n\n        sNewV_frg = cute.logical_divide(sNewV, cute.make_layout(frg_tile))\n        for it in cutlass.range_constexpr(0, 16):\n            sNewV_frg[None, (it, thread_idx)].store(tTR_rO_e_frg[None, it].load())\n\n        cute.arch.fence_proxy(\n            cute.arch.ProxyKind.async_shared,\n            space=cute.arch.SharedSpace.shared_cta,\n        )\n\n    @cute.jit\n    def load_ivt_result(\n        self,\n        tIn: cute.Tensor,\n        sD: cute.Tensor,\n    ):\n        tidx, _, _ = cute.arch.thread_idx()\n        lane_id = tidx % 32\n        warp_id = cute.arch.warp_idx() % 4\n\n        thread_idx = tidx % (self.threads_per_warp * (len(self.cudacore_warp_ids)))\n\n        tIn_layout = cute.composition(tIn.layout, cute.make_layout((tIn.shape)))\n        tIn = cute.make_tensor(tIn.iterator, tIn_layout)\n\n        # Load from tmem\n        copy_atom_t2r = cute.make_copy_atom(\n            tcgen05.copy.Ld16x256bOp(tcgen05.copy.Repetition(4)),\n            self.acc_dtype,\n        )\n\n        tiled_copy_t2r = tcgen05.make_tmem_copy(copy_atom_t2r, tIn)\n        thr_copy_t2r = tiled_copy_t2r.get_slice(thread_idx)\n        tTR_tO = thr_copy_t2r.partition_S(tIn)\n        tTR_cO = thr_copy_t2r.partition_D(tIn)\n\n        tTR_rO = cute.make_rmem_tensor(tTR_cO.shape, self.acc_dtype)\n\n        tTR_tO = cute.group_modes(tTR_tO, 1, cute.rank(tTR_tO))\n        tTR_rO = cute.group_modes(tTR_rO, 1, cute.rank(tTR_rO))\n        cute.copy(tiled_copy_t2r, tTR_tO, tTR_rO)\n        cute.arch.fence_view_async_tmem_load()\n\n        tTR_rO_e = cute.make_rmem_tensor(tTR_cO.shape, self.q_dtype)\n\n        frg_cnt = 2\n        frg_tile = cute.size(tTR_rO) // frg_cnt\n        tTR_rO_frg = cute.logical_divide(tTR_rO, cute.make_layout(frg_tile))\n        tTR_rO_e_frg = cute.logical_divide(tTR_rO_e, cute.make_layout(frg_tile))\n        for j in cutlass.range_constexpr(frg_cnt):\n            r_vec = -tTR_rO_frg[None, j].load()\n            tTR_rO_e_frg[None, j].store(r_vec.to(self.q_dtype))\n\n        tTR_rO_e_f32 = cute.recast_tensor(src=tTR_rO_e, dtype=cutlass.Float32)\n\n        for it in cutlass.range_constexpr(0, 8):\n            sD[\n                ((64 + warp_id * 16 + (lane_id // 4) + 0), (lane_id % 4, it % 2)),\n                it // 2,\n            ] = tTR_rO_e_f32[it * 2]\n            sD[\n                ((64 + warp_id * 16 + (lane_id // 4) + 8), (lane_id % 4, it % 2)),\n                it // 2,\n            ] = tTR_rO_e_f32[it * 2 + 1]\n\n        cute.arch.fence_proxy(\n            cute.arch.ProxyKind.async_shared,\n            space=cute.arch.SharedSpace.shared_cta,\n        )\n\n    @cute.jit\n    def apply_gamma_beta(\n        self,\n        thr_mma: cute.ThrMma,\n        sIvt: cute.Tensor,\n        tIn: cute.Tensor,\n        beta_val: cutlass.Float32,\n        tGamma: cute.Tensor,\n    ):\n        \"\"\"Apply gamma*beta to KK^T in TMEM.\"\"\"\n        tidx, _, _ = cute.arch.thread_idx()\n        lane_id = tidx % 32\n        warp_id = cute.arch.warp_idx() % 4\n        sub_widx = warp_id % 4\n        thread_idx = tidx % (self.threads_per_warp * (len(self.cudacore_warp_ids)))\n\n        cIn = cute.make_identity_tensor((128, 128))\n        tOcO = thr_mma.partition_C(cIn)\n\n        corr_tile_size = 32  # only 8  or 32\n        tIn_i_layout = cute.composition(\n            tIn.layout, cute.make_layout((128, corr_tile_size))\n        )\n        cIn_i_layout = cute.composition(\n            tOcO.layout, cute.make_layout((128, corr_tile_size))\n        )\n        tIn_i = cute.make_tensor(tIn.iterator, tIn_i_layout)\n\n        tOut_i = cute.make_tensor(tIn.iterator, tIn_i_layout)\n        cOut_i = cute.make_tensor(tOcO.iterator, cIn_i_layout)\n\n        tGamma_i = cute.make_tensor(tGamma.iterator, tIn_i_layout)\n        cIn_i = cute.make_tensor(cIn.iterator, cIn_i_layout)\n\n        tmem_load_atom = cute.make_copy_atom(\n            tcgen05.copy.Ld32x32bOp(tcgen05.copy.Repetition(corr_tile_size)),\n            self.acc_dtype,\n        )\n\n        tmem_store_atom = cute.make_copy_atom(\n            tcgen05.copy.St32x32bOp(tcgen05.copy.Repetition(corr_tile_size)),\n            self.acc_dtype,\n        )\n\n        tiled_tmem_store = tcgen05.make_tmem_copy(tmem_store_atom, tOut_i)\n        thr_tmem_store = tiled_tmem_store.get_slice(thread_idx)\n\n        tTMEM_STOREcS = thr_tmem_store.partition_S(cOut_i)\n        tTMEM_STOREtO = thr_tmem_store.partition_D(tOut_i)\n\n        tTMEM_STORErS = cute.make_rmem_tensor(tTMEM_STOREcS.shape, self.acc_dtype)\n\n        # Load In\n        tiled_tmem_load = tcgen05.make_tmem_copy(tmem_load_atom, tIn_i)\n        thr_tmem_load = tiled_tmem_load.get_slice(thread_idx)\n\n        # Load Gamma\n        tiled_tmem_load_gamma = tcgen05.make_tmem_copy(tmem_load_atom, tGamma_i)\n        thr_tmem_load_gamma = tiled_tmem_load_gamma.get_slice(thread_idx)\n\n        tTMEM_LOADtO = thr_tmem_load.partition_S(tIn_i)\n        tTMEM_LOADcO = thr_tmem_load.partition_D(cIn_i)\n\n        tTMEM_LOADtG = thr_tmem_load_gamma.partition_S(tGamma_i)\n        tTMEM_LOADrG = cute.make_rmem_tensor(tTMEM_LOADcO.shape, self.acc_dtype)\n\n        tTMEM_LOADrS = cute.make_tensor(\n            cute.recast_ptr(tTMEM_STORErS.iterator, dtype=self.acc_dtype),\n            tTMEM_LOADrG.layout,\n        )\n\n        frg_tile = 4\n\n        # Store to smem\n        # ((32, 32), 4)\n        lower_D_frag = cute.logical_divide(tTMEM_STORErS, ((4, None), None))\n        sIvt_frag = cute.logical_divide(sIvt, ((4, None), None))\n\n        for i in cutlass.range_constexpr(128 // corr_tile_size):\n            tTMEM_LOADtO_i = cute.make_tensor(\n                tTMEM_LOADtO.iterator + i * corr_tile_size, tTMEM_LOADtO.layout\n            )\n            tTMEM_LOADtG_i = cute.make_tensor(\n                tTMEM_LOADtG.iterator + i * corr_tile_size, tTMEM_LOADtO.layout\n            )\n\n            tTMEM_STOREtO_i = cute.make_tensor(\n                tTMEM_STOREtO.iterator + i * corr_tile_size, tTMEM_STOREtO.layout\n            )\n\n            cute.copy(tiled_tmem_load_gamma, tTMEM_LOADtG_i, tTMEM_LOADrG)\n            each_iter = corr_tile_size // frg_tile\n            tTMEM_LOADrG_frg = cute.logical_divide(\n                tTMEM_LOADrG, ((frg_tile, None), None)\n            )\n            for j in cutlass.range_constexpr(each_iter):\n                for inner_idx in cutlass.range_constexpr(0, frg_tile, 2):\n                    (\n                        tTMEM_LOADrG_frg[((inner_idx + 0, j), i), 0, 0],\n                        tTMEM_LOADrG_frg[((inner_idx + 1, j), i), 0, 0],\n                    ) = cute.arch.mul_packed_f32x2(\n                        (\n                            tTMEM_LOADrG_frg[((inner_idx + 0, j), i), 0, 0],\n                            tTMEM_LOADrG_frg[((inner_idx + 1, j), i), 0, 0],\n                        ),\n                        (\n                            beta_val,\n                            beta_val,\n                        ),\n                    )\n            cute.copy(tiled_tmem_load, tTMEM_LOADtO_i, tTMEM_LOADrS)\n            cute.arch.fence_view_async_tmem_load()\n\n            tTMEM_LOADrS_frg = cute.logical_divide(\n                tTMEM_LOADrS, ((frg_tile, None), None)\n            )\n\n            if (i * corr_tile_size) < ((sub_widx + 1) * 32):\n                for j in cutlass.range_constexpr(each_iter):\n                    for inner_idx in cutlass.range_constexpr(0, frg_tile, 2):\n                        (\n                            tTMEM_LOADrS_frg[((inner_idx + 0, j), i), 0, 0],\n                            tTMEM_LOADrS_frg[((inner_idx + 1, j), i), 0, 0],\n                        ) = cute.arch.mul_packed_f32x2(\n                            (\n                                tTMEM_LOADrS_frg[((inner_idx + 0, j), i), 0, 0],\n                                tTMEM_LOADrS_frg[((inner_idx + 1, j), i), 0, 0],\n                            ),\n                            (\n                                tTMEM_LOADrG_frg[((inner_idx + 0, j), i), 0, 0],\n                                tTMEM_LOADrG_frg[((inner_idx + 1, j), i), 0, 0],\n                            ),\n                        )\n            cute.copy(tiled_tmem_store, tTMEM_STORErS, tTMEM_STOREtO_i)\n\n            tile_frags = corr_tile_size // 4\n            if (i * corr_tile_size) >= sub_widx * 32 and (i * corr_tile_size) < (\n                sub_widx + 1\n            ) * 32:\n                idx = (i * corr_tile_size - sub_widx * 32) // 4\n                for j in cutlass.range_constexpr(tile_frags):\n                    true_col = j + idx\n                    sIvt_frag[((None, true_col), lane_id), sub_widx].store(\n                        lower_D_frag[((None, j), 0), 0, 0].load()\n                    )\n\n    @cute.jit\n    def compute_gamma_tmem(\n        self,\n        val: cutlass.Float32,\n        sGateCumsum: cute.Tensor,\n        thr_mma: cute.ThrMma,\n        tOut: cute.Tensor,\n        bar_id: Int32,\n        mask: cutlass.Constexpr[cutlass.Boolean] = False,\n        tail_count: Int32 = 128,\n    ):\n        \"\"\"Build the 128x128 causal gamma matrix in TMEM: gamma[i,j] = exp(cumsum[i] - cumsum[j]) for j <= i.\"\"\"\n        tidx, _, _ = cute.arch.thread_idx()\n        thread_idx = tidx % 128\n\n        cute.arch.barrier(\n            barrier_id=bar_id,\n            number_of_threads=len(self.cudacore_warp_ids) * 32,\n        )\n\n        cIn = cute.make_identity_tensor((128, 128))\n        tOcO = thr_mma.partition_C(cIn)\n\n        corr_tile_size = 128\n\n        cOut_i_layout = cute.composition(\n            tOcO.layout, cute.make_layout((128, corr_tile_size))\n        )\n        tOut_i_layout = cute.composition(\n            tOut.layout, cute.make_layout((128, corr_tile_size))\n        )\n\n        tOut_i = cute.make_tensor(tOut.iterator, tOut_i_layout)\n        cOut_i = cute.make_tensor(tOcO.iterator, cOut_i_layout)\n\n        tmem_store_atom = cute.make_copy_atom(\n            tcgen05.copy.St32x32bOp(tcgen05.copy.Repetition(corr_tile_size)),\n            self.acc_dtype,\n        )\n\n        tiled_tmem_store = tcgen05.make_tmem_copy(tmem_store_atom, tOut_i)\n        thr_tmem_store = tiled_tmem_store.get_slice(thread_idx)\n\n        tTMEM_STOREcS = thr_tmem_store.partition_S(cOut_i)\n        tTMEM_STOREtO = thr_tmem_store.partition_D(tOut_i)\n\n        tTMEM_STORErS = cute.make_rmem_tensor(tTMEM_STOREcS.shape, self.acc_dtype)\n\n        frg_tile = 32\n        sGateCumsum_tile = cute.flat_divide(\n            sGateCumsum, cute.make_layout(corr_tile_size)\n        )\n        sGateCumsum_frag = cute.logical_divide(sGateCumsum_tile, (frg_tile, None))\n\n        zeros = cute.zeros_like(cute.make_layout((frg_tile, 1)), self.acc_dtype)\n\n        for i in cutlass.range_constexpr(128 // corr_tile_size):\n            tTMEM_STOREtO_i = cute.make_tensor(\n                tTMEM_STOREtO.iterator + i * corr_tile_size, tTMEM_STOREtO.layout\n            )\n\n            tTMEM_STORErS_frag = cute.logical_divide(\n                tTMEM_STORErS, cute.make_layout(frg_tile)\n            )\n            for it in cutlass.range_constexpr(corr_tile_size // frg_tile):\n                tile_offset = i * corr_tile_size + it * frg_tile\n\n                if (\n                    (\n                        tile_offset <= thread_idx\n                        and tile_offset < tail_count\n                        and thread_idx < tail_count\n                    )\n                    if cutlass.const_expr(mask)\n                    else (tile_offset <= thread_idx)\n                ):\n                    curr_val_frag_ssa = sGateCumsum_frag[(None, it), i].load()\n\n                    new_val_frag = cute.math.exp(val - curr_val_frag_ssa, fastmath=True)\n\n                    for inner_idx in cutlass.range_constexpr(0, frg_tile):\n                        offset = tile_offset + inner_idx\n                        curr_val = new_val_frag[inner_idx]\n\n                        if offset <= thread_idx:\n                            tTMEM_STORErS_frag[inner_idx, it] = curr_val\n                        else:\n                            tTMEM_STORErS_frag[inner_idx, it] = cutlass.Float32(0)\n                else:\n                    tTMEM_STORErS_frag[None, it].store(zeros)\n\n            # store\n            cute.copy(tiled_tmem_store, tTMEM_STORErS, tTMEM_STOREtO_i)\n        cute.arch.fence_view_async_tmem_store()\n\n    @cute.jit\n    def chunk_local_cumsum(\n        self,\n        sGate: cute.Tensor,\n        sGateCumsum: cute.Tensor,\n        bar_id: Int32,\n    ) -> cutlass.Float32:\n        \"\"\"Compute inclusive prefix sum of gate values within a 128-token chunk.\"\"\"\n        tidx, _, _ = cute.arch.thread_idx()\n        lane_id = tidx % 32\n        warp_id = cute.arch.warp_idx() % 4\n        tidx_in_group = tidx % 128\n\n        val = sGate[tidx_in_group]\n        stride = 1\n        clamp_value = 0\n        while stride < 32:\n            shfl_value = cute.arch.shuffle_sync_op(\n                value=val,\n                offset=stride,\n                mask_and_clamp=clamp_value,\n                kind=nvvm.ShflKind.up,\n            )\n            if lane_id >= stride:\n                val += shfl_value\n\n            stride = stride << 1\n        if lane_id == 31:\n            sGateCumsum[warp_id] = val\n\n        cute.arch.barrier(\n            barrier_id=bar_id,\n            number_of_threads=len(self.cudacore_warp_ids) * 32,\n        )\n\n        if warp_id == 1:\n            pre_warp_val = sGateCumsum[0]\n            val = val + pre_warp_val\n        if warp_id == 2:\n            sGateCumsum_f2 = cute.flat_divide(sGateCumsum, (2, 1))\n            warp_sum = sGateCumsum_f2[None, 0, 0, 0]\n            pre_warp_val = warp_sum[0] + warp_sum[1]\n            val = val + pre_warp_val\n        if warp_id == 3:\n            sGateCumsum_f4 = cute.flat_divide(sGateCumsum, (4, 1))\n            warp_sum = sGateCumsum_f4[None, 0, 0, 0]\n            pre_warp_val = warp_sum[0] + warp_sum[1] + warp_sum[2]\n            val = val + pre_warp_val\n\n        cute.arch.barrier(\n            barrier_id=bar_id,\n            number_of_threads=len(self.cudacore_warp_ids) * 32,\n        )\n\n        sGateCumsum[tidx_in_group] = val\n\n        return val\n\n    @cute.jit\n    def save_tmem(\n        self,\n        tSIn: cute.Tensor,\n        sD: cute.Tensor,\n    ) -> cute.Tensor:\n        tidx, _, _ = cute.arch.thread_idx()\n        widx = cute.arch.warp_idx()\n        lane_id = cute.arch.lane_idx()\n        sub_widx = widx % 4\n\n        thread_idx = tidx % (self.threads_per_warp * (len(self.cudacore_warp_ids)))\n\n        tSIn_layout = cute.composition(tSIn.layout, cute.make_layout((tSIn.shape)))\n        tSIn0 = cute.make_tensor(tSIn.iterator, tSIn_layout)\n\n        # Load from tmem\n        copy_atom_t2r = cute.make_copy_atom(\n            tcgen05.copy.Ld16x256bOp(tcgen05.copy.Repetition(4)),\n            self.acc_dtype,\n        )\n        tiled_copy_t2r = tcgen05.make_tmem_copy(copy_atom_t2r, tSIn0)\n        thr_copy_t2r = tiled_copy_t2r.get_slice(thread_idx)\n        tTR_tO = thr_copy_t2r.partition_S(tSIn0)\n        tTR_cO = thr_copy_t2r.partition_D(tSIn0)\n        tTR_cO_one_iter = tTR_cO[None, 0, 0, 0]\n        tTR_rO = cute.make_rmem_tensor(tTR_cO_one_iter.shape, self.acc_dtype)\n\n        tTR_tO = cute.group_modes(tTR_tO, 1, cute.rank(tTR_tO))\n\n        tTR_rO_e = cute.make_rmem_tensor(tTR_rO.shape, self.q_dtype)\n        frg_cnt = 2\n        frg_tile = cute.size(tTR_rO) // frg_cnt\n        tTR_rO_frg = cute.logical_divide(tTR_rO, cute.make_layout(frg_tile))\n        tTR_rO_e_frg = cute.logical_divide(tTR_rO_e, cute.make_layout(frg_tile))\n        tTR_rO_e_f32 = cute.recast_tensor(src=tTR_rO_e, dtype=cutlass.Float32)\n        for subtile_idx in cutlass.range_constexpr(2):\n            tTR_tO_mn = tTR_tO[(None, subtile_idx)]\n            cute.copy(tiled_copy_t2r, tTR_tO_mn, tTR_rO)\n            cute.arch.fence_view_async_tmem_load()\n\n            if (sub_widx == 0 or sub_widx == 1) and subtile_idx == 0:\n                for j in cutlass.range_constexpr(frg_cnt):\n                    r_vec = -tTR_rO_frg[None, j].load()\n                    tTR_rO_e_frg[None, j].store(r_vec.to(self.q_dtype))\n\n                for it in cutlass.range_constexpr(0, 4):\n                    sD[\n                        (\n                            (\n                                32\n                                + (sub_widx // 2) * 64\n                                + (sub_widx % 2) * 16\n                                + (lane_id // 4)\n                                + 0\n                            ),\n                            (lane_id % 4, it % 2),\n                        ),\n                        it // 2 + (sub_widx // 2) * 4,\n                    ] = tTR_rO_e_f32[it * 2]\n                    sD[\n                        (\n                            (\n                                32\n                                + (sub_widx // 2) * 64\n                                + (sub_widx % 2) * 16\n                                + (lane_id // 4)\n                                + 8\n                            ),\n                            (lane_id % 4, it % 2),\n                        ),\n                        it // 2 + (sub_widx // 2) * 4,\n                    ] = tTR_rO_e_f32[it * 2 + 1]\n\n            if (sub_widx == 2 or sub_widx == 3) and subtile_idx == 1:\n                for j in cutlass.range_constexpr(frg_cnt):\n                    r_vec = -tTR_rO_frg[None, j].load()\n                    tTR_rO_e_frg[None, j].store(r_vec.to(self.q_dtype))\n\n                for it in cutlass.range_constexpr(0, 4):\n                    sD[\n                        (\n                            (\n                                32\n                                + (sub_widx // 2) * 64\n                                + (sub_widx % 2) * 16\n                                + (lane_id // 4)\n                                + 0\n                            ),\n                            (lane_id % 4, it % 2),\n                        ),\n                        it // 2 + (sub_widx // 2) * 4,\n                    ] = tTR_rO_e_f32[it * 2]\n                    sD[\n                        (\n                            (\n                                32\n                                + (sub_widx // 2) * 64\n                                + (sub_widx % 2) * 16\n                                + (lane_id // 4)\n                                + 8\n                            ),\n                            (lane_id % 4, it % 2),\n                        ),\n                        it // 2 + (sub_widx // 2) * 4,\n                    ] = tTR_rO_e_f32[it * 2 + 1]\n\n    @cute.jit\n    def load_ivt_ts_l0(\n        self,\n        tSIn: cute.Tensor,\n        sInvertSubSSL1A: cute.Tensor,\n        sInvertSubTSL1B: cute.Tensor,\n    ) -> cute.Tensor:\n        tidx, _, _ = cute.arch.thread_idx()\n        widx = cute.arch.warp_idx()\n        lane_id = cute.arch.lane_idx()\n        sub_widx = widx % 4\n\n        thread_idx = tidx % (self.threads_per_warp * (len(self.cudacore_warp_ids)))\n\n        tSIn_layout = cute.composition(tSIn.layout, cute.make_layout((tSIn.shape)))\n        tSIn0 = cute.make_tensor(tSIn.iterator, tSIn_layout)\n\n        # Load from tmem\n        copy_atom_t2r = cute.make_copy_atom(\n            tcgen05.copy.Ld16x128bOp(tcgen05.copy.Repetition(8)),  # todo\n            self.acc_dtype,\n        )\n        tiled_copy_t2r = tcgen05.make_tmem_copy(copy_atom_t2r, tSIn0)\n        thr_copy_t2r = tiled_copy_t2r.get_slice(thread_idx)\n        tTR_tO = thr_copy_t2r.partition_S(tSIn0)\n        tTR_cO = thr_copy_t2r.partition_D(tSIn0)\n        tTR_cO_one_iter = tTR_cO[None, 0, 0, 0]\n        tTR_rO = cute.make_rmem_tensor(tTR_cO_one_iter.shape, self.acc_dtype)\n\n        tTR_rO_s = cute.make_tensor(\n            cute.recast_ptr(tTR_rO.iterator, dtype=self.acc_dtype),\n            cute.shape(tTR_cO_one_iter)[0],\n        )\n\n        tTR_tO = cute.group_modes(tTR_tO, 1, cute.rank(tTR_tO))\n\n        for subtile_idx in cutlass.range_constexpr(2):\n            tTR_tO_mn = tTR_tO[(None, subtile_idx)]\n            cute.copy(tiled_copy_t2r, tTR_tO_mn, tTR_rO)\n            cute.arch.fence_view_async_tmem_load()\n\n            if (sub_widx == 0 or sub_widx == 1) and subtile_idx == 0:\n                sInvertSubTSL1B_frag = cute.logical_divide(\n                    sInvertSubTSL1B, ((4, None), None)\n                )\n                sub_id_row = sub_widx\n                for col in cutlass.range_constexpr(0, 8):\n                    col_true = (lane_id // 4 + col) % 8\n                    sInvertSubTSL1B_frag[\n                        ((lane_id % 4, (col_true, 0)), lane_id // 4),\n                        0,\n                        4 + sub_id_row * 2 + 0,\n                        0,\n                    ] = -tTR_rO_s[(0, col_true), 0]\n                    sInvertSubTSL1B_frag[\n                        ((lane_id % 4, (col_true, 0)), lane_id // 4),\n                        0,\n                        4 + sub_id_row * 2 + 1,\n                        0,\n                    ] = -tTR_rO_s[(1, col_true), 0]\n            if (sub_widx == 2 or sub_widx == 3) and subtile_idx == 1:\n                tTR_rO_s_frag_f1 = cute.logical_divide(\n                    cute.flatten(tTR_rO_s[None, 0]), (1, None)\n                )\n                sInvertSubSSL1A_frag_f1 = cute.logical_divide(\n                    sInvertSubSSL1A, ((None, 1), None)\n                )\n                sub_id_row = sub_widx - 2\n                for it in cutlass.range_constexpr(0, 8):\n                    col_offset = it % 2 * 4\n                    sInvertSubSSL1A_frag_f1[\n                        (\n                            32 + sub_id_row * 16 + 0 + lane_id // 4,\n                            (None, col_offset + lane_id % 4),\n                        ),\n                        0,\n                        (it // 2, 0),\n                        0,\n                    ].store(-tTR_rO_s_frag_f1[(None, 0), it].load())\n                    sInvertSubSSL1A_frag_f1[\n                        (\n                            32 + sub_id_row * 16 + 8 + lane_id // 4,\n                            (None, col_offset + lane_id % 4),\n                        ),\n                        0,\n                        (it // 2, 0),\n                        0,\n                    ].store(-tTR_rO_s_frag_f1[(None, 1), it].load())\n\n        cute.arch.fence_proxy(\n            cute.arch.ProxyKind.async_shared,\n            space=cute.arch.SharedSpace.shared_cta,\n        )\n\n    @cute.jit\n    def store_ivt_c(\n        self,\n        sD: cute.Tensor,\n    ):\n        \"\"\"Zero out off-diagonal blocks in the assembled inverse matrix (block identity structure).\"\"\"\n        widx = cute.arch.warp_idx()\n        lane_id = cute.arch.lane_idx()\n        sub_widx = widx % 4\n\n        zeros = cute.zeros_like(cute.make_layout((4, 1)), self.acc_dtype)\n        for it in cutlass.range_constexpr(0, 4):\n            row = sub_widx // 2 * 32 + lane_id\n            col_block_inner = it % 2\n            col_block = 4 + (sub_widx % 2) * 2 + it // 2\n            sD[(row, (None, col_block_inner)), col_block].store(zeros[None, 0])\n        for it in cutlass.range_constexpr(0, 2):\n            row = sub_widx // 2 * 64 + lane_id\n            col_block_inner = sub_widx % 2\n            col_block = (sub_widx // 2) * 4 + 2 + it\n            sD[(row, (None, col_block_inner)), col_block].store(zeros[None, 0])\n\n    @cute.jit\n    def load_ivt_ss_l0(\n        self,\n        tSIn: cute.Tensor,\n        tSOut: cute.Tensor,\n    ):\n        tidx, _, _ = cute.arch.thread_idx()\n        widx = cute.arch.warp_idx()\n        sub_widx = widx % 4\n\n        thread_idx = tidx % (self.threads_per_warp * (len(self.cudacore_warp_ids)))\n\n        tSIn_layout = cute.composition(tSIn.layout, cute.make_layout((tSIn.shape)))\n        tSIn0 = cute.make_tensor(tSIn.iterator, tSIn_layout)\n\n        # Load from tmem\n        copy_atom_t2r = cute.make_copy_atom(\n            tcgen05.copy.Ld16x256bOp(tcgen05.copy.Repetition(4)),  # 4*8 = 32\n            self.acc_dtype,\n        )\n\n        tiled_copy_t2r = tcgen05.make_tmem_copy(copy_atom_t2r, tSIn0)\n        thr_copy_t2r = tiled_copy_t2r.get_slice(thread_idx)\n        tTR_tO = thr_copy_t2r.partition_S(tSIn0)\n        tTR_cO = thr_copy_t2r.partition_D(tSIn0)\n        tTR_cO_one_iter = tTR_cO[(None), 0, 0, 0]\n        tTR_rO = cute.make_rmem_tensor(tTR_cO_one_iter.shape, self.acc_dtype)\n\n        tTR_tO = cute.group_modes(tTR_tO, 1, cute.rank(tTR_tO))\n\n        tSOut_layout = cute.make_layout(\n            (((16, 4), 32), 1, 1), stride=(((65536, 2097152), 1), 0, 0)\n        )\n        tSOut0 = cute.make_tensor(tSOut.iterator, tSOut_layout)\n        copy_atom_r2t = cute.make_copy_atom(\n            tcgen05.copy.St16x256bOp(tcgen05.copy.Repetition(4)),\n            self.acc_dtype,\n        )\n        tiled_copy_r2t = tcgen05.make_tmem_copy(copy_atom_r2t, tSOut0)\n        thr_copy_r2t = tiled_copy_r2t.get_slice(thread_idx)\n        tRT_cO = thr_copy_r2t.partition_S(tSOut0)\n        tRT_tO = thr_copy_r2t.partition_D(tSOut0)\n        tRT_cO_one_iter = tRT_cO[(None), None, 0, 0]  #\n        tRT_rO = cute.make_rmem_tensor(tRT_cO_one_iter.shape, self.acc_dtype)\n\n        for subtile_idx in cutlass.range_constexpr(2):\n            tTR_tO_mn = tTR_tO[(None, subtile_idx)]\n            cute.copy(tiled_copy_t2r, tTR_tO_mn, tTR_rO)\n            cute.arch.fence_view_async_tmem_load()\n\n            if (sub_widx == 0 or sub_widx == 1) and subtile_idx == 0:\n                for eid in cutlass.range_constexpr(16):\n                    tRT_rO[eid] = tTR_rO[eid]\n\n            if (sub_widx == 2 or sub_widx == 3) and subtile_idx == 1:\n                for eid in cutlass.range_constexpr(16):\n                    tRT_rO[eid] = tTR_rO[eid]\n\n        tRT_tO = cute.group_modes(tRT_tO, 2, cute.rank(tRT_tO))\n        for subtile_idx in cutlass.range_constexpr(0, 1):\n            tRT_tO_mn = tRT_tO[(None, None, subtile_idx)]\n            cute.copy(tiled_copy_r2t, tRT_rO, tRT_tO_mn)\n\n        cute.arch.fence_view_async_tmem_store()\n\n    @cute.jit\n    def store_ivt_ad(\n        self,\n        sReg: cute.Tensor,\n        sD: cute.Tensor,\n    ):\n        \"\"\"Store diagonal block inverse (A/D blocks) from registers to smem.\"\"\"\n        tidx, _, _ = cute.arch.thread_idx()\n        widx = cute.arch.warp_idx()\n        sub_widx = widx % 4\n\n        reg_layout = cute.make_layout((4, 2))\n        result_e = cute.make_rmem_tensor(reg_layout.shape, self.acc_dtype)\n        for it in cutlass.range_constexpr(0, 4):\n            result_e[None, 0].store(sReg[(None, tidx % 128), it * 2 + 0].load())\n            result_e[None, 1].store(sReg[(None, tidx % 128), it * 2 + 1].load())\n            sD[(tidx % 128, (None, it % 2)), 0, sub_widx * 2 + it // 2, 0].store(\n                result_e[None].load().to(self.q_dtype)\n            )\n\n    @cute.jit\n    def __call__(\n        self,\n        q_iter: cute.Pointer,\n        k_iter: cute.Pointer,\n        v_iter: cute.Pointer,\n        o_iter: cute.Pointer,\n        g_iter: cute.Pointer,\n        beta_iter: cute.Pointer,\n        problem_size: Tuple[\n            cutlass.Int32,\n            cutlass.Int32,\n            cutlass.Int32,\n            cutlass.Int32,\n            cutlass.Int32,\n            cutlass.Int32,\n        ],\n        initial_state_f32_iter: Optional[cute.Pointer],\n        state_output: Optional[cute.Pointer],\n        scale: Optional[float],\n        cum_seqlen_q: Optional[cute.Tensor] = None,\n        stream: cuda.CUstream = None,\n    ):\n        \"\"\"Host-side entry: build tensor layouts, TMA descriptors, smem storage, and launch the kernel.\"\"\"\n\n        b, s_q, s_sum, h_q, h_v, d = problem_size\n\n        h_r = h_v // h_q\n        o_offset = 0 if cum_seqlen_q is None else (-s_q * d * h_r * h_q)\n        b_qk = b if cum_seqlen_q is None else s_sum\n        b_o = b if cum_seqlen_q is None else s_q * (1 + b)\n        b_v = b if cum_seqlen_q is None else s_sum\n\n        stride_b_qk = h_q * s_q * d if cum_seqlen_q is None else d * h_q\n        stride_b_vo = h_r * h_q * s_q * d if cum_seqlen_q is None else d * h_q * h_r\n\n        b_gb = b if cum_seqlen_q is None else 1\n        stride_b_gb = h_r * h_q * s_sum if cum_seqlen_q is None else 0\n        q_layout = cute.make_layout(\n            (s_sum, d, ((h_r, h_q), b_qk)),\n            stride=(d * h_q, 1, ((0, d), stride_b_qk)),\n        )\n        q = cute.make_tensor(q_iter, q_layout)\n\n        k_layout = cute.make_layout(\n            (s_sum, d, ((h_r, h_q), b_qk)),\n            stride=(d * h_q, 1, ((0, d), stride_b_qk)),\n        )\n        k = cute.make_tensor(k_iter, k_layout)\n        v_layout = cute.make_layout(\n            (d, s_sum, ((h_r, h_q), b_v)),\n            stride=(1, d * h_q * h_r, ((d, d * h_r), stride_b_vo)),\n        )\n        v = cute.make_tensor(v_iter, v_layout)\n        o_layout = cute.make_layout(\n            (s_q, d, ((h_r, h_q), b_o)),\n            stride=(d * h_r * h_q, 1, ((d, d * h_r), stride_b_vo)),\n        )\n        o = cute.make_tensor(o_iter + o_offset, o_layout)\n\n        state_layout = cute.make_layout(\n            (self.head_dim, self.head_dim, ((h_r, h_q), b)),\n            stride=(\n                self.head_dim,\n                1,\n                (\n                    (\n                        self.head_dim * self.head_dim,\n                        h_r * self.head_dim * self.head_dim,\n                    ),\n                    h_q * h_r * self.head_dim * self.head_dim,\n                ),\n            ),\n        )\n\n        state_input_f32 = (\n            None\n            if cutlass.const_expr(initial_state_f32_iter is None)\n            else cute.make_tensor(initial_state_f32_iter, state_layout)\n        )\n        state_output = (\n            None\n            if cutlass.const_expr(state_output is None)\n            else cute.make_tensor(state_output, state_layout)\n        )\n\n        gb_layout = cute.make_layout(\n            (s_sum, 1, ((h_r, h_q), b_gb)),\n            stride=(h_r * h_q, 0, ((1, h_r), stride_b_gb)),\n        )\n        gate = cute.make_tensor(g_iter, gb_layout)\n        beta = cute.make_tensor(beta_iter, gb_layout)\n\n        if cutlass.const_expr(scale is None):\n            scale = 1.0 / cute.math.sqrt(cutlass.Float32(d))\n\n        # setup static attributes before smem/grid/tma computation\n        self.q_dtype = q.element_type\n        self.k_dtype = k.element_type\n        self.v_dtype = v.element_type\n        self.o_dtype = o.element_type\n        self.g_dtype = gate.element_type\n        self.beta_dtype = beta.element_type\n\n        self.i_dtype = self.q_dtype\n\n        self.tile_sched_params, grid = self._compute_grid(\n            cute.shape((s_q, d, ((h_r, h_q), b))),\n            self.cta_tiler,\n            self.is_persistent,\n        )\n\n        self.q_major_mode = utils.LayoutEnum.from_tensor(q).mma_major_mode()\n        self.k_major_mode = utils.LayoutEnum.from_tensor(k).mma_major_mode()\n        self.v_major_mode = utils.LayoutEnum.from_tensor(v).mma_major_mode()\n        self.o_layout = utils.LayoutEnum.from_tensor(o)\n        self.s_output = utils.LayoutEnum.ROW_MAJOR\n\n        cta_group = tcgen05.CtaGroup.ONE\n\n        qk_tiled_mma = sm100_utils.make_trivial_tiled_mma(\n            self.q_dtype,\n            self.q_major_mode,\n            self.k_major_mode,\n            self.acc_dtype,\n            cta_group,\n            self.qk_mma_tiler[:2],\n        )\n\n        update_s_tiled_mma = sm100_utils.make_trivial_tiled_mma(\n            self.i_dtype,\n            tcgen05.OperandMajorMode.MN,\n            tcgen05.OperandMajorMode.MN,\n            self.acc_dtype,\n            cta_group,\n            self.update_s_mma_tiler[:2],\n        )\n\n        o_intra_tiled_mma = sm100_utils.make_trivial_tiled_mma(\n            self.i_dtype,\n            tcgen05.OperandMajorMode.K,\n            tcgen05.OperandMajorMode.MN,\n            self.acc_dtype,\n            cta_group,\n            self.o_intra_mma_tiler[:2],\n        )\n\n        o_intra_tiled_ts_mma_new = sm100_utils.make_trivial_tiled_mma(\n            self.i_dtype,\n            tcgen05.OperandMajorMode.K,\n            tcgen05.OperandMajorMode.MN,\n            self.acc_dtype,\n            cta_group,\n            self.o_intra_mma_tiler[:2],\n            tcgen05.OperandSource.TMEM,\n        )\n\n        qs_tiled_mma = sm100_utils.make_trivial_tiled_mma(\n            self.i_dtype,\n            tcgen05.OperandMajorMode.K,\n            tcgen05.OperandMajorMode.K,\n            self.acc_dtype,\n            cta_group,\n            self.qs_mma_tiler[:2],\n            tcgen05.OperandSource.TMEM,\n        )\n\n        kkt_tiled_mma = sm100_utils.make_trivial_tiled_mma(\n            self.k_dtype,\n            self.k_major_mode,\n            self.k_major_mode,\n            self.acc_dtype,\n            cta_group,\n            self.kkt_mma_tiler[:2],\n        )\n\n        kst_tiled_mma = sm100_utils.make_trivial_tiled_mma(\n            self.i_dtype,\n            self.k_major_mode,\n            self.k_major_mode,\n            self.acc_dtype,\n            cta_group,\n            self.kst_mma_tiler[:2],\n        )\n\n        invert_sub_tiled_mma_ss_l0 = sm100_utils.make_trivial_tiled_mma(\n            self.invert_type_ab,\n            self.k_major_mode,\n            tcgen05.OperandMajorMode.MN,\n            self.invert_acc_type,\n            cta_group,\n            self.invert_mma_sub_l0_tiler[:2],\n        )\n        invert_sub_tiled_mma_ts_l0 = sm100_utils.make_trivial_tiled_mma(\n            self.invert_type_ab,\n            self.k_major_mode,\n            tcgen05.OperandMajorMode.MN,\n            self.invert_acc_type,\n            cta_group,\n            self.invert_mma_sub_l0_tiler[:2],\n            tcgen05.OperandSource.TMEM,\n        )\n\n        invert_sub_tiled_mma_ss_l1 = sm100_utils.make_trivial_tiled_mma(\n            self.invert_type_ab,\n            self.k_major_mode,\n            tcgen05.OperandMajorMode.MN,\n            self.invert_acc_type,\n            cta_group,\n            self.invert_mma_sub_l1_tiler[:2],\n        )\n        invert_sub_tiled_mma_ts_l1 = sm100_utils.make_trivial_tiled_mma(\n            self.invert_type_ab,\n            self.k_major_mode,\n            tcgen05.OperandMajorMode.MN,\n            self.invert_acc_type,\n            cta_group,\n            self.invert_mma_sub_l1_tiler[:2],\n            tcgen05.OperandSource.TMEM,\n        )\n\n        tuw_tiled_mma = sm100_utils.make_trivial_tiled_mma(\n            self.k_dtype,\n            self.k_major_mode,\n            tcgen05.OperandMajorMode.MN,\n            self.acc_dtype,\n            cta_group,\n            self.tuw_mma_tiler[:2],\n        )\n\n        self.cluster_layout_vmnk = cute.tiled_divide(\n            cute.make_layout(self.cluster_shape_mnk),\n            (qk_tiled_mma.thr_id.shape,),\n        )\n\n        q_smem_layout_staged = sm100_utils.make_smem_layout_a(\n            qk_tiled_mma,\n            self.qk_mma_tiler,\n            self.q_dtype,\n            self.q_stage,\n        )\n        k_smem_layout_staged = sm100_utils.make_smem_layout_b(\n            qk_tiled_mma,\n            self.qk_mma_tiler,\n            self.k_dtype,\n            self.kv_stage,\n        )\n\n        qk_smem_layout_staged = sm100_utils.make_smem_layout_b(\n            qk_tiled_mma,\n            self.qk_mma_tiler,\n            self.i_dtype,\n            self.qk_stage,\n        )\n\n        state_smem_layout_staged = sm100_utils.make_smem_layout_b(\n            kst_tiled_mma,\n            self.kst_mma_tiler,\n            self.i_dtype,\n            self.one_stage,\n        )\n\n        o_intra_smem_layout_staged_a = make_smem_layout_a_kind(\n            o_intra_tiled_mma,\n            self.o_intra_mma_tiler,\n            self.i_dtype,\n            self.one_stage,\n            cute.nvgpu.tcgen05.SmemLayoutAtomKind.K_INTER,\n        )\n\n        o_intra_smem_layout_staged_b = make_smem_layout_b_kind(\n            o_intra_tiled_mma,\n            self.o_intra_mma_tiler,\n            self.i_dtype,\n            self.one_stage,\n            cute.nvgpu.tcgen05.SmemLayoutAtomKind.MN_INTER,\n        )\n\n        o_intra_smem_layout_staged_a_new = make_smem_layout_a_kind(\n            o_intra_tiled_ts_mma_new,\n            self.o_intra_mma_tiler,\n            self.i_dtype,\n            self.one_stage,\n            cute.nvgpu.tcgen05.SmemLayoutAtomKind.K_INTER,\n        )\n\n        qs_smem_layout_staged_a = sm100_utils.make_smem_layout_a(\n            qs_tiled_mma,\n            self.qs_mma_tiler,\n            self.i_dtype,\n            self.one_stage,\n        )\n\n        qs_smem_layout_staged_b = sm100_utils.make_smem_layout_b(\n            qs_tiled_mma,\n            self.qs_mma_tiler,\n            self.i_dtype,\n            self.one_stage,\n        )\n\n        update_s_smem_layout_staged_a = make_smem_layout_a_kind(\n            update_s_tiled_mma,\n            self.update_s_mma_tiler,\n            self.i_dtype,\n            self.one_stage,\n            cute.nvgpu.tcgen05.SmemLayoutAtomKind.MN_INTER,\n        )\n\n        update_s_smem_layout_staged_b = make_smem_layout_b_kind(\n            update_s_tiled_mma,\n            self.update_s_mma_tiler,\n            self.i_dtype,\n            self.one_stage,\n            cute.nvgpu.tcgen05.SmemLayoutAtomKind.MN_INTER,\n        )\n\n        state_output_smem_layout_staged = make_smem_layout_epi_kind(\n            self.state_dtype,\n            self.s_output,\n            self.state_output_tiler,\n            self.one_stage,\n            cute.nvgpu.tcgen05.SmemLayoutAtomKind.K_INTER,\n        )\n\n        o_output_smem_layout_staged = make_smem_layout_epi_kind(\n            self.i_dtype,\n            self.o_layout,\n            self.o_output_tiler,\n            self.one_stage,\n            cute.nvgpu.tcgen05.SmemLayoutAtomKind.K_INTER,\n        )\n\n        ivt_smem_layout = cute.make_layout(\n            ((36, 32), 4)\n        )  # padding, remove smem bank conflict\n        # ivt_smem_layout = cute.make_layout(((32, 32), 4))  # padding, remove smem bank conflict\n\n        sub_inner_smem_layout_staged = make_smem_layout_a_kind(\n            invert_sub_tiled_mma_ss_l0,\n            self.invert_mma_sub_l0_tiler,\n            self.invert_type_ab,\n            self.sub_stage,\n            cute.nvgpu.tcgen05.SmemLayoutAtomKind.K_INTER,\n        )\n\n        invert_sub_smem_layout_staged_ss_l0_a = sm100_utils.make_smem_layout_a(\n            invert_sub_tiled_mma_ss_l0,\n            self.invert_mma_sub_l0_tiler,\n            self.invert_type_ab,\n            self.invert_sub_stage,\n        )\n\n        invert_sub_smem_layout_staged_ss_l0_b = sm100_utils.make_smem_layout_b(\n            invert_sub_tiled_mma_ss_l0,\n            self.invert_mma_sub_l0_tiler,\n            self.invert_type_ab,\n            self.invert_sub_stage,\n        )\n\n        invert_sub_smem_layout_staged_ts_l0_a = sm100_utils.make_smem_layout_a(\n            invert_sub_tiled_mma_ts_l0,\n            self.invert_mma_sub_l0_tiler,\n            self.invert_type_ab,\n            self.invert_sub_stage,\n        )\n\n        invert_sub_smem_layout_staged_ts_l0_b = sm100_utils.make_smem_layout_b(\n            invert_sub_tiled_mma_ts_l0,\n            self.invert_mma_sub_l0_tiler,\n            self.invert_type_ab,\n            self.invert_sub_stage,\n        )\n\n        invert_sub_smem_layout_staged_ss_l1_a = sm100_utils.make_smem_layout_a(\n            invert_sub_tiled_mma_ss_l1,\n            self.invert_mma_sub_l1_tiler,\n            self.invert_type_ab,\n            self.invert_sub_stage,\n        )\n\n        invert_sub_smem_layout_staged_ss_l1_b = sm100_utils.make_smem_layout_b(\n            invert_sub_tiled_mma_ss_l1,\n            self.invert_mma_sub_l1_tiler,\n            self.invert_type_ab,\n            self.invert_sub_stage,\n        )\n\n        invert_sub_smem_layout_staged_ts_l1_a = sm100_utils.make_smem_layout_a(\n            invert_sub_tiled_mma_ts_l1,\n            self.invert_mma_sub_l1_tiler,\n            self.invert_type_ab,\n            self.invert_sub_stage,\n        )\n\n        invert_sub_smem_layout_staged_ts_l1_b = sm100_utils.make_smem_layout_b(\n            invert_sub_tiled_mma_ts_l1,\n            self.invert_mma_sub_l1_tiler,\n            self.invert_type_ab,\n            self.invert_sub_stage,\n        )\n\n        # tuw\n        tuw_smem_layout_staged_a = make_smem_layout_a_kind(\n            tuw_tiled_mma,\n            self.tuw_mma_tiler,\n            self.q_dtype,\n            self.one_stage,\n            cute.nvgpu.tcgen05.SmemLayoutAtomKind.K_INTER,\n        )\n\n        tuw_smem_layout_staged_b = make_smem_layout_b_kind(\n            tuw_tiled_mma,\n            self.tuw_mma_tiler,\n            self.q_dtype,\n            self.one_stage,\n            cute.nvgpu.tcgen05.SmemLayoutAtomKind.MN_INTER,\n        )\n\n        v_smem_layout_staged_b = make_smem_layout_b_kind(\n            tuw_tiled_mma,\n            self.tuw_mma_tiler,\n            self.i_dtype,\n            self.one_stage,\n            cute.nvgpu.tcgen05.SmemLayoutAtomKind.MN_INTER,\n        )\n\n        # TMA\n        tma_load_op = cute.nvgpu.cpasync.CopyBulkTensorTileG2SOp(cta_group)\n        tma_store_op = cute.nvgpu.cpasync.CopyBulkTensorTileS2GOp()\n\n        # TMA load for Q\n        q_smem_layout = cute.select(q_smem_layout_staged, mode=[0, 1, 2])\n        tma_atom_q, tma_tensor_q = cute.nvgpu.make_tiled_tma_atom_A(\n            tma_load_op,\n            q,\n            q_smem_layout,\n            self.qk_mma_tiler,\n            qk_tiled_mma,\n            self.cluster_layout_vmnk.shape,\n        )\n\n        # TMA load for K\n        k_smem_layout = cute.select(k_smem_layout_staged, mode=[0, 1, 2])\n        tma_atom_k, tma_tensor_k = cute.nvgpu.make_tiled_tma_atom_B(\n            tma_load_op,\n            k,\n            k_smem_layout,\n            self.qk_mma_tiler,\n            qk_tiled_mma,\n            self.cluster_layout_vmnk.shape,\n        )\n\n        # TMA load for V\n        v_smem_layout = cute.select(v_smem_layout_staged_b, mode=[0, 1, 2])\n        tma_atom_v, tma_tensor_v = cute.nvgpu.make_tiled_tma_atom_B(\n            tma_load_op,\n            v,\n            v_smem_layout,\n            self.tuw_mma_tiler,\n            tuw_tiled_mma,\n            self.cluster_layout_vmnk.shape,\n        )\n\n        fake_state_tiled_mma = sm100_utils.make_trivial_tiled_mma(\n            self.state_dtype,\n            self.q_major_mode,\n            self.k_major_mode,\n            self.state_dtype,\n            cta_group,\n            self.qk_mma_tiler[:2],\n        )\n        state_smem_layout_f32_staged = sm100_utils.make_smem_layout_b(\n            fake_state_tiled_mma,\n            self.qk_mma_tiler,\n            self.state_dtype,\n            self.one_stage,\n        )\n        state_smem_layout_f32 = cute.select(\n            state_smem_layout_f32_staged, mode=[0, 1, 2]\n        )\n        tma_atom_state_f32, tma_tensor_state_f32 = (\n            cute.nvgpu.make_tiled_tma_atom_B(\n                tma_load_op,\n                state_input_f32,\n                state_smem_layout_f32,\n                self.qk_mma_tiler,\n                fake_state_tiled_mma,\n                self.cluster_layout_vmnk.shape,\n            )\n            if cutlass.const_expr(state_input_f32 is not None)\n            else (None, None)\n        )\n\n        state_smem_layout_output = cute.select(\n            state_output_smem_layout_staged, mode=[0, 1]\n        )\n        tma_atom_state_output, tma_tensor_state_output = (\n            cutlass.cute.nvgpu.cpasync.make_tiled_tma_atom(\n                tma_store_op,\n                state_output,\n                state_smem_layout_output,\n                cute.composition(\n                    cute.make_identity_layout(state_output.shape),\n                    self.state_output_tiler,\n                ),\n            )\n            if cutlass.const_expr(state_output is not None)\n            else (None, None)\n        )\n\n        o_cta_v_layout = cute.composition(\n            cute.make_identity_layout(o.shape), self.o_output_tiler\n        )\n        o_smem_layout_output = cute.select(o_output_smem_layout_staged, mode=[0, 1])\n        tma_atom_o_output, tma_tensor_o_output = (\n            cutlass.cute.nvgpu.cpasync.make_tiled_tma_atom(\n                tma_store_op,\n                o,\n                o_smem_layout_output,\n                o_cta_v_layout,\n            )\n        )\n\n        gate_smem_layout_staged = cute.make_layout(\n            (self.chunk_size, 1, self.gate_stage)\n        )\n        gate_smem_layout = cute.select(gate_smem_layout_staged, mode=[0, 1])\n\n        beta_smem_layout_staged = cute.make_layout(\n            (self.chunk_size, 1, self.beta_stage)\n        )\n        beta_smem_layout = cute.select(beta_smem_layout_staged, mode=[0, 1])\n\n        q_copy_size = cute.size_in_bytes(self.q_dtype, q_smem_layout)\n        k_copy_size = cute.size_in_bytes(self.k_dtype, k_smem_layout)\n        v_copy_size = cute.size_in_bytes(self.v_dtype, v_smem_layout)\n        state_copy_size = cute.size_in_bytes(self.i_dtype, state_smem_layout_f32)\n        state_f32_copy_size = cute.size_in_bytes(\n            self.state_dtype, state_smem_layout_f32\n        )\n        gate_copy_size = cute.size_in_bytes(self.g_dtype, gate_smem_layout)\n        beta_copy_size = cute.size_in_bytes(self.beta_dtype, beta_smem_layout)\n        self.tma_copy_q_bytes = q_copy_size\n        self.tma_copy_kv_bytes = k_copy_size\n        self.tma_copy_v_bytes = v_copy_size\n        self.tma_copy_state_bytes = state_copy_size\n        self.tma_copy_state_f32_bytes = state_f32_copy_size\n        self.tma_copy_gate_bytes = gate_copy_size\n        self.tma_copy_beta_bytes = beta_copy_size\n\n        # Shared memory storage\n        @cute.struct\n        class SharedStorage:\n            load_qk_mbar_ptr: cute.struct.MemRange[Int64, self.qk_stage * 2]\n            load_v_mbar_ptr: cute.struct.MemRange[Int64, self.one_stage * 2]\n            load_state_mbar_ptr: cute.struct.MemRange[Int64, self.one_stage * 2]\n            mma_cudacore_mbar_ptr0: cute.struct.MemRange[Int64, 2]\n            mma_qk_mbar_ptr0: cute.struct.MemRange[Int64, self.mma_qk_stage * 2]\n\n            w0_epi_mbar_ptr: cute.struct.MemRange[Int64, 2]\n            epi_w0_mbar_ptr: cute.struct.MemRange[Int64, 2]\n            gb_w0_mbar_ptr: cute.struct.MemRange[Int64, self.gate_stage * 2]\n\n            tmem_dealloc_mbar_ptr: cute.struct.MemRange[Int64, 1]\n            # Tmem holding buffer\n            tmem_holding_buf: Int32\n\n            sV: cute.struct.Align[\n                cute.struct.MemRange[self.i_dtype, cute.cosize(v_smem_layout_staged_b)],\n                self.buffer_align_bytes,\n            ]\n\n            sQK: cute.struct.Align[\n                cute.struct.MemRange[self.q_dtype, cute.cosize(qk_smem_layout_staged)],\n                self.buffer_align_bytes,\n            ]\n\n            sIvt: cute.struct.Align[\n                cute.struct.MemRange[self.acc_dtype, cute.cosize(ivt_smem_layout)],\n                self.buffer_align_bytes,\n            ]\n\n            sGate: cute.struct.Align[\n                cute.struct.MemRange[\n                    self.g_beta_dtype, cute.cosize(gate_smem_layout_staged)\n                ],\n                self.buffer_align_bytes,\n            ]\n            sGateCumsum: cute.struct.Align[\n                cute.struct.MemRange[\n                    self.g_beta_dtype,\n                    cute.cosize(cute.select(gate_smem_layout_staged, mode=[0, 1])),\n                ],\n                self.buffer_align_bytes,\n            ]\n            sBeta: cute.struct.Align[\n                cute.struct.MemRange[\n                    self.g_beta_dtype, cute.cosize(beta_smem_layout_staged)\n                ],\n                self.buffer_align_bytes,\n            ]\n            sSubInner: cute.struct.Align[\n                cute.struct.MemRange[\n                    self.invert_type_ab, cute.cosize(sub_inner_smem_layout_staged)\n                ],\n                self.buffer_align_bytes,\n            ]\n\n            sState: cute.struct.Align[\n                cute.struct.MemRange[\n                    self.i_dtype, cute.cosize(state_smem_layout_staged)\n                ],\n                self.buffer_align_bytes,\n            ]\n\n        self.shared_storage = SharedStorage\n\n        if cutlass.const_expr(stream is None):\n            stream = cutlass.cuda.default_stream()\n\n        # Launch kernel\n        self.kernel(\n            qk_tiled_mma,\n            o_intra_tiled_mma,\n            o_intra_tiled_ts_mma_new,\n            qs_tiled_mma,\n            update_s_tiled_mma,\n            kkt_tiled_mma,\n            kst_tiled_mma,\n            fake_state_tiled_mma,\n            invert_sub_tiled_mma_ss_l0,\n            invert_sub_tiled_mma_ts_l0,\n            invert_sub_tiled_mma_ss_l1,\n            invert_sub_tiled_mma_ts_l1,\n            tuw_tiled_mma,\n            tma_atom_q,\n            tma_tensor_q,\n            tma_atom_k,\n            tma_tensor_k,\n            tma_atom_v,\n            tma_tensor_v,\n            tma_atom_state_f32,\n            tma_tensor_state_f32,\n            gate,\n            beta,\n            o,\n            tma_atom_state_output,\n            tma_tensor_state_output,\n            tma_atom_o_output,\n            tma_tensor_o_output,\n            cum_seqlen_q,\n            q_smem_layout_staged,\n            k_smem_layout_staged,\n            qk_smem_layout_staged,\n            o_intra_smem_layout_staged_a,\n            o_intra_smem_layout_staged_b,\n            o_intra_smem_layout_staged_a_new,\n            qs_smem_layout_staged_a,\n            qs_smem_layout_staged_b,\n            update_s_smem_layout_staged_a,\n            update_s_smem_layout_staged_b,\n            state_smem_layout_staged,\n            state_smem_layout_f32_staged,\n            state_output_smem_layout_staged,\n            o_output_smem_layout_staged,\n            gate_smem_layout_staged,\n            beta_smem_layout_staged,\n            ivt_smem_layout,\n            sub_inner_smem_layout_staged,\n            invert_sub_smem_layout_staged_ss_l0_a,\n            invert_sub_smem_layout_staged_ss_l0_b,\n            invert_sub_smem_layout_staged_ts_l0_a,\n            invert_sub_smem_layout_staged_ts_l0_b,\n            invert_sub_smem_layout_staged_ss_l1_a,\n            invert_sub_smem_layout_staged_ss_l1_b,\n            invert_sub_smem_layout_staged_ts_l1_a,\n            invert_sub_smem_layout_staged_ts_l1_b,\n            tuw_smem_layout_staged_a,\n            tuw_smem_layout_staged_b,\n            v_smem_layout_staged_b,\n            scale,\n            self.tile_sched_params,\n        ).launch(\n            grid=grid,\n            block=[self.threads_per_cta, 1, 1],\n            cluster=self.cluster_shape_mnk,\n            stream=stream,\n            min_blocks_per_mp=1,\n        )\n\n    @staticmethod\n    def _compute_grid(\n        o_shape: cute.Shape,\n        cta_tiler: Tuple[int, int, int],\n        is_persistent: bool,\n    ) -> Tuple[GdnStaticTileSchedulerParams, Tuple[int, int, int]]:\n        tile_sched_params = create_gdn_static_tile_scheduler_params(\n            is_persistent,\n            (\n                cute.ceil_div(cute.size(o_shape[1]), cta_tiler[2]),\n                cute.size(o_shape[2][0]),\n                cute.size(o_shape[2][1]),\n            ),\n        )\n        grid = GdnStaticTileScheduler.get_grid_shape(tile_sched_params)\n        return tile_sched_params, grid\n\n\n# ============================================================================\n# FlashInfer API Layer\n# ============================================================================\n\n\n@functools.lru_cache(maxsize=128)\ndef _get_problem_size(q_shape, v_shape, cu_seqlens_tuple):\n    \"\"\"Compute problem_size, cached by (q_shape, v_shape, cu_seqlens tuple).\n\n    Args:\n        q_shape: Tuple of (b, s_q, h_q, d).\n        v_shape: Tuple of (b, s_v, h_v, d).\n        cu_seqlens_tuple: Tuple of cumulative sequence lengths, or None.\n    \"\"\"\n    b, s_q, h_q, d = q_shape\n    _, _, h_v, _ = v_shape\n    max_s_q = s_q\n    sum_s_q = s_q\n    if cu_seqlens_tuple is not None:\n        sum_s_q = cu_seqlens_tuple[-1]\n        b = len(cu_seqlens_tuple) - 1\n        max_s_q = max(cu_seqlens_tuple[i + 1] - cu_seqlens_tuple[i] for i in range(b))\n        return (b, max_s_q, sum_s_q, h_q, h_v, d)\n    return (b, max_s_q, sum_s_q, h_q, h_v, d)\n\n\n@functools.cache\ndef _get_compiled_gdn_prefill_kernel(\n    problem_size,\n    dtype: torch.dtype,\n    is_varlen: bool,\n    is_initial_state: bool,\n    is_output_state: bool,\n    scale: float,\n):\n    \"\"\"Cache compiled kernel for given configuration.\"\"\"\n    return {}\n\n\ndef chunk_gated_delta_rule(\n    q: torch.Tensor,\n    k: torch.Tensor,\n    v: torch.Tensor,\n    g: torch.Tensor,\n    beta: torch.Tensor,\n    scale: Optional[float] = None,\n    initial_state: Optional[torch.Tensor] = None,\n    output_final_state: bool = False,\n    cu_seqlens: Optional[torch.Tensor] = None,\n    use_qk_l2norm_in_kernel: bool = False,\n    output: Optional[torch.Tensor] = None,\n    output_state: Optional[torch.Tensor] = None,\n) -> Union[torch.Tensor, Tuple[torch.Tensor, torch.Tensor]]:\n    \"\"\"Public API: compile (on first call) and run the GDN chunked linear attention kernel.\n\n    Args:\n        q, k: (B, T, H_qk, D) query and key tensors (f16/bf16).\n        v:     (B, T, H_v, D) value tensor (f16/bf16). H_v must be a multiple of H_qk.\n        g:     (1, total_seq_len, H_v) gate values (f32, log-space).\n        beta:  (1, total_seq_len, H_v) beta values (f32, sigmoid-space).\n        scale: Scale factor for the attention scores. Defaults to 1/sqrt(D).\n        initial_state: (B, H_v, D, D) recurrent state (f32), or None for zero init.\n        output_final_state: If True, return the final state alongside output.\n        cu_seqlens: Cumulative sequence lengths for variable-length batching.\n        use_qk_l2norm_in_kernel: If True, use L2 norm of QK in the kernel.(Not supported yet)\n        output: Pre-allocated output tensor, or None to allocate internally.\n        output_state: Pre-allocated state output tensor, or None.\n\n    Returns:\n        output or (output, output_state) depending on output_final_state.\n    \"\"\"\n\n    # Allocate output if needed\n    if output is None:\n        output = torch.empty_like(v)\n\n    # Check if supported\n    if not GDN.can_implement(\n        tuple(q.shape),\n        tuple(v.shape),\n        q.dtype,\n        output.dtype,\n        beta.dtype,\n        use_qk_l2norm_in_kernel,\n    ):\n        raise ValueError(\"Unsupported input shape or dtype\")\n    cu_seqlens_tuple = tuple(cu_seqlens.tolist()) if cu_seqlens is not None else None\n    problem_size = _get_problem_size(tuple(q.shape), tuple(v.shape), cu_seqlens_tuple)\n\n    # Allocate output_state if needed, current alloc both case.\n    # TODO: Remove output_state when output_final_state is false.\n    if output_state is None:\n        output_state = torch.empty(\n            (problem_size[0], problem_size[4], problem_size[5], problem_size[5]),\n            dtype=torch.float32,\n            device=q.device,\n        )\n\n    # Compile kernel with TVM FFI (cached)\n    is_varlen = cu_seqlens is not None\n    is_initial_state = initial_state is not None\n    is_output_state = output_state is not None\n    cache_key = (\n        problem_size,\n        q.dtype,\n        is_varlen,\n        is_initial_state,\n        is_output_state,\n        scale,\n    )\n    cache = _get_compiled_gdn_prefill_kernel(*cache_key)\n\n    current_stream = cuda.CUstream(torch.cuda.current_stream().cuda_stream)\n\n    if \"compiled_gdn\" not in cache:\n        # GDN kernel\n        gdn = GDN()\n        q_tensor = from_dlpack(q, assumed_align=16, enable_tvm_ffi=True)\n        k_tensor = from_dlpack(k, assumed_align=16, enable_tvm_ffi=True)\n        v_tensor = from_dlpack(v, assumed_align=16, enable_tvm_ffi=True)\n        o_tensor = from_dlpack(output, assumed_align=16, enable_tvm_ffi=True)\n        gate_tensor = from_dlpack(g, assumed_align=16, enable_tvm_ffi=True)\n        beta_tensor = from_dlpack(beta, assumed_align=16, enable_tvm_ffi=True)\n        cu_seqlens_tensor = (\n            from_dlpack(cu_seqlens, assumed_align=16, enable_tvm_ffi=True)\n            if cu_seqlens is not None\n            else None\n        )\n        state_tensor = (\n            from_dlpack(initial_state, assumed_align=16, enable_tvm_ffi=True)\n            if initial_state is not None\n            else None\n        )\n        state_output_tensor = (\n            from_dlpack(output_state, assumed_align=16, enable_tvm_ffi=True)\n            if output_state is not None\n            else None\n        )\n\n        # Compile GDN kernel\n        options = EnableTVMFFI\n        compiled_gdn = cute.compile[options](\n            gdn,\n            q_tensor.iterator,\n            k_tensor.iterator,\n            v_tensor.iterator,\n            o_tensor.iterator,\n            gate_tensor.iterator,\n            beta_tensor.iterator,\n            problem_size,\n            state_tensor.iterator if state_tensor is not None else None,\n            state_output_tensor.iterator if state_output_tensor is not None else None,\n            scale,\n            cu_seqlens_tensor,\n            stream=current_stream,\n        )\n        cache[\"compiled_gdn\"] = compiled_gdn\n\n    compiled_gdn = cache[\"compiled_gdn\"]\n\n    # Run GDN kernel\n    compiled_gdn(\n        q.data_ptr(),\n        k.data_ptr(),\n        v.data_ptr(),\n        output.data_ptr(),\n        g.data_ptr(),\n        beta.data_ptr(),\n        problem_size,\n        initial_state.data_ptr() if initial_state is not None else None,\n        output_state.data_ptr() if output_state is not None else None,\n        scale,\n        cu_seqlens,\n        stream=current_stream,\n    )\n\n    if output_final_state:\n        return output, output_state\n    else:\n        return output\n"
-    },
-    {
-      "path": "gdn_blackwell/gdn_helpers.py",
-      "content": "\"\"\"\nCopyright (c) 2026 by FlashInfer team.\n\nLicensed under the Apache License, Version 2.0 (the \"License\");\nyou may not use this file except in compliance with the License.\nYou may obtain a copy of the License at\n\n  http://www.apache.org/licenses/LICENSE-2.0\n\nUnless required by applicable law or agreed to in writing, software\ndistributed under the License is distributed on an \"AS IS\" BASIS,\nWITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\nSee the License for the specific language governing permissions and\nlimitations under the License.\n\"\"\"\n\nfrom typing import Type, Union\n\nimport cutlass\nimport cutlass.cute as cute\n\n\ndef make_smem_layout_a_kind(\n    tiled_mma: cute.TiledMma,\n    mma_tiler_mnk: cute.Tile,\n    a_dtype: Type[cutlass.Numeric],\n    num_stages: int,\n    kind: cute.nvgpu.tcgen05.SmemLayoutAtomKind,\n    *,\n    loc=None,\n    ip=None,\n) -> Union[cute.Layout, cute.ComposedLayout]:\n    \"\"\"This function helps with:\n    1. Get the partitioned shape of the A tensor based on the tiled_mma & MMA tiler.\n    2. Select the heuristic SMEM layout atom based on the A tensor's majorness, the data type, and the major mode size.\n    3. cute.Tile the SMEM layout atom to the MMA tile shape.\n    4. Stage the SMEM layout based on the number of stages.\n\n    :param tiled_mma: The tiled MMA used to partition tensor A\n    :type tiled_mma: cute.TiledMma\n    :param mma_tiler_mnk: The MMA tile shape\n    :type mma_tiler_mnk: cute.cute.Tile\n    :param a_dtype: The element type for tensor A\n    :type a_dtype: Type[Numeric]\n    :param num_stages: The number of pipeline stages for tensor A\n    :type num_stages: int\n    :param kind:         The kind of layout Atom\n    :type kind:          SmemLayoutAtomKind\n\n    :return: SMEM layout for tensor A\n    :rtype: Union[cute.Layout, cute.ComposedLayout]\n    \"\"\"\n\n    is_k_major = (\n        tiled_mma.op.a_major_mode == cutlass.cute.nvgpu.tcgen05.OperandMajorMode.K\n    )\n    a_smem_shape = tiled_mma.partition_shape_A(\n        cute.dice(mma_tiler_mnk, (1, None, 1), loc=loc, ip=ip)\n    )\n    a_smem_layout_atom = cute.nvgpu.tcgen05.make_smem_layout_atom(\n        kind,\n        a_dtype,\n        loc=loc,\n        ip=ip,\n    )\n    a_smem_layout_staged = cute.nvgpu.tcgen05.tile_to_mma_shape(\n        a_smem_layout_atom,\n        cute.append(a_smem_shape, num_stages, loc=loc, ip=ip),\n        order=((1, 0, 2) if not is_k_major else (0, 1, 2)),\n        loc=loc,\n        ip=ip,\n    )\n    return a_smem_layout_staged\n\n\ndef make_smem_layout_b_kind(\n    tiled_mma: cute.TiledMma,\n    mma_tiler_mnk: cute.Tile,\n    b_dtype: Type[cutlass.Numeric],\n    num_stages: int,\n    kind: cute.nvgpu.tcgen05.SmemLayoutAtomKind,\n    *,\n    loc=None,\n    ip=None,\n) -> Union[cute.Layout, cute.ComposedLayout]:\n    \"\"\"This function helps:\n    1. Get the partitioned shape of the B tensor based on the tiled_mma & MMA tiler.\n    2. Select the heuristic SMEM layout atom based on the B tensor's majorness, the data type, and the major mode size.\n    3. cute.Tile the SMEM layout atom to the MMA tile shape.\n    4. Stage the SMEM layout based on the number of stages.\n\n    :param tiled_mma: The tiled MMA which is used to partition the B tensor.\n    :type tiled_mma: cute.TiledMma\n    :param mma_tiler_mnk: The MMA tile shape.\n    :type mma_tiler_mnk: cute.cute.Tile\n    :param b_dtype: The element type for the B tensor.\n    :type b_dtype: Type[Numeric]\n    :param num_stages: The stage of the B tensor.\n    :type num_stages: int\n    :param kind:         The kind of layout Atom\n    :type kind:          SmemLayoutAtomKind\n\n    :return: SMEM layout for the B tensor.\n    :rtype: Union[cute.Layout, cute.ComposedLayout]\n    \"\"\"\n\n    is_k_major = (\n        tiled_mma.op.b_major_mode == cutlass.cute.nvgpu.tcgen05.OperandMajorMode.K\n    )\n    b_smem_shape = tiled_mma.partition_shape_B(\n        cute.dice(mma_tiler_mnk, (None, 1, 1), loc=loc, ip=ip)\n    )\n    b_smem_layout_atom = cute.nvgpu.tcgen05.make_smem_layout_atom(\n        kind,\n        b_dtype,\n        loc=loc,\n        ip=ip,\n    )\n    b_smem_layout_staged = cute.nvgpu.tcgen05.tile_to_mma_shape(\n        b_smem_layout_atom,\n        cute.append(b_smem_shape, num_stages, loc=loc, ip=ip),\n        order=((1, 0, 2) if not is_k_major else (0, 1, 2)),\n        loc=loc,\n        ip=ip,\n    )\n\n    return b_smem_layout_staged\n\n\ndef make_smem_layout_epi_kind(\n    epi_dtype: Type[cutlass.Numeric],\n    epi_layout: cutlass.utils.LayoutEnum,\n    epi_tile: cute.Tile,\n    epi_stage: int,\n    kind: cute.nvgpu.tcgen05.SmemLayoutAtomKind,\n    *,\n    loc=None,\n    ip=None,\n) -> Union[cute.Layout, cute.ComposedLayout]:\n    \"\"\"This function helps:\n    1. Select the heuristic SMEM layout atom based on the epilog tile shape,\n       the epilog tensor's majorness, and the element type.\n    2. cute.Tile the SMEM layout atom to the epilog tile shape.\n    3. Stage the SMEM layout based on the number of stages.\n\n    :param epi_dtype: The element type for the epilog tensor.\n    :type epi_dtype: Type[Numeric]\n    :param epi_layout: The layout enum for the epilog tensor.\n    :type epi_layout: LayoutEnum\n    :param epi_tile: The epilogue tile shape.\n    :type epi_tile: cute.cute.Tile\n    :param epi_stage: The stage of the epilog tensor.\n    :type epi_stage: int\n\n    :return: SMEM layout for epilog tensors (usually C & D which are processed in the epilog)\n    :rtype: Union[cute.Layout, cute.ComposedLayout]\n    \"\"\"\n\n    epilog_shape = cute.product_each(\n        cute.shape(epi_tile, loc=loc, ip=ip), loc=loc, ip=ip\n    )\n\n    c_smem_layout_atom = cute.nvgpu.tcgen05.make_smem_layout_atom(\n        kind,\n        epi_dtype,\n        loc=loc,\n        ip=ip,\n    )\n    epi_smem_layout_staged = cute.tile_to_shape(\n        c_smem_layout_atom,\n        cute.append(epilog_shape, epi_stage, loc=loc, ip=ip),\n        order=((1, 0, 2) if not epi_layout.is_n_major_c() else (0, 1, 2)),\n        loc=loc,\n        ip=ip,\n    )\n\n    return epi_smem_layout_staged\n"
-    },
-    {
-      "path": "gdn_blackwell/gdn_tile_scheduler.py",
-      "content": "import cutlass\nimport cutlass.cute as cute\nimport cutlass.utils as utils\n\nfrom cutlass.cute.typing import Int32, Int64, Boolean\n\n\nclass GdnStaticTileSchedulerParams:\n    def __init__(\n        self,\n        is_persistent: bool,\n        problem_shape_mbh: cute.Shape,\n        *,\n        loc=None,\n        ip=None,\n    ):\n        self.is_persistent = is_persistent\n        self.problem_shape_mbh = problem_shape_mbh\n        self._loc = loc\n        self._ip = ip\n\n    def __extract_mlir_values__(self):\n        values, self._values_pos = [], []\n        for obj in [self.is_persistent, self.problem_shape_mbh]:\n            obj_values = cutlass.extract_mlir_values(obj)\n            values += obj_values\n            self._values_pos.append(len(obj_values))\n        return values\n\n    def __new_from_mlir_values__(self, values):\n        obj_list = []\n        for obj, n_items in zip(\n            [self.is_persistent, self.problem_shape_mbh], self._values_pos, strict=True\n        ):\n            obj_list.append(cutlass.new_from_mlir_values(obj, values[:n_items]))\n            values = values[n_items:]\n        return GdnStaticTileSchedulerParams(\n            *(tuple(obj_list)), loc=self._loc, ip=self._ip\n        )\n\n\ndef create_gdn_static_tile_scheduler_params(\n    is_persistent: bool,\n    problem_shape_mbh: cute.Shape,\n) -> GdnStaticTileSchedulerParams:\n    return GdnStaticTileSchedulerParams(is_persistent, problem_shape_mbh)\n\n\nclass GdnStaticTileScheduler:\n    def __init__(\n        self,\n        params: GdnStaticTileSchedulerParams,\n        current_work_linear_idx: Int32,\n        blk_coord: cute.Coord,\n        grid_shape: cute.Shape,\n        *,\n        loc=None,\n        ip=None,\n    ):\n        self._params = params\n        self._blk_coord = blk_coord\n        self._grid_shape = grid_shape\n        self._is_persistent = params.is_persistent\n        self._current_work_linear_idx = current_work_linear_idx\n        self._problem_shape_mbh = cute.make_layout(\n            params.problem_shape_mbh, loc=loc, ip=ip\n        )\n        self._num_blocks = cute.size(self._problem_shape_mbh, loc=loc, ip=ip)\n        self._is_first_block = True\n        self.num_persistent_sm = cute.size(grid_shape, loc=loc, ip=ip)\n        self._loc = loc\n        self._ip = ip\n\n    # called by host\n    @staticmethod\n    def get_grid_shape(\n        params: GdnStaticTileSchedulerParams,\n        *,\n        loc=None,\n        ip=None,\n    ) -> cute.Shape:\n        if params.is_persistent:\n            hardware_info = cutlass.utils.HardwareInfo()\n            sm_count = hardware_info.get_device_multiprocessor_count()\n            return (\n                cutlass.min(\n                    sm_count, cute.size(params.problem_shape_mbh, loc=loc, ip=ip)\n                ),\n                1,\n                1,\n            )\n        else:\n            return params.problem_shape_mbh\n\n    @staticmethod\n    def check_valid_work_for_seqlen_q(\n        q_tiler: int,\n        current_idx: Int32,\n        seqlen_q: Int32,\n    ) -> Boolean:\n        return current_idx * q_tiler < seqlen_q\n\n    def get_current_work(self, *, loc=None, ip=None) -> utils.WorkTileInfo:\n        is_valid = (\n            self._current_work_linear_idx < self._num_blocks\n            if self._is_persistent\n            else self._is_first_block\n        )\n\n        blk_coord = (0, 0, 0)\n        if self._is_persistent:\n            blk_coord = self._problem_shape_mbh.get_hier_coord(\n                self._current_work_linear_idx, loc=loc, ip=ip\n            )\n        else:\n            blk_coord = self._blk_coord\n\n        # cur_tile_coord is (mid, 0, (bid, hid))\n        cur_tile_coord = (\n            blk_coord[0],\n            0,\n            (blk_coord[1], blk_coord[2]),\n        )\n\n        return utils.WorkTileInfo(cur_tile_coord, is_valid)\n\n    def initial_work_tile_info(self, *, loc=None, ip=None):\n        return self.get_current_work(loc=loc, ip=ip)\n\n    def advance_to_next_work(self, *, advance_count=1, loc=None, ip=None):\n        if self._is_persistent:\n            self._current_work_linear_idx += advance_count * self.num_persistent_sm\n        self._is_first_block = False\n\n    def __extract_mlir_values__(self):\n        values = cutlass.extract_mlir_values(self._params)\n        values.extend(cutlass.extract_mlir_values(self._current_work_linear_idx))\n        values.extend(cutlass.extract_mlir_values(self._blk_coord))\n        values.extend(cutlass.extract_mlir_values(self._grid_shape))\n        return values\n\n    def __new_from_mlir_values__(self, values):\n        assert len(values) == 10\n        new_params = cutlass.new_from_mlir_values(self._params, values[0:3])\n        new_current_work_linear_idx = cutlass.new_from_mlir_values(\n            self._current_work_linear_idx, [values[3]]\n        )\n        new_blk_coord = cutlass.new_from_mlir_values(self._blk_coord, values[4:7])\n        new_grid_shape = cutlass.new_from_mlir_values(self._grid_shape, values[7:])\n        return GdnStaticTileScheduler(\n            new_params, new_current_work_linear_idx, new_blk_coord, new_grid_shape\n        )\n\n\ndef create_gdn_static_tile_scheduler(\n    params: GdnStaticTileSchedulerParams,\n    blk_coord: cute.Coord,\n    grid_shape: cute.Shape,\n) -> GdnStaticTileScheduler:\n    return GdnStaticTileScheduler(params, blk_coord[0], blk_coord, grid_shape)\n"
-    }
-  ],
-  "description": "Solution using FlashInfer SM100 CuTile chunk_gated_delta_rule for GDN prefill (qk4_v8_d128, k-last state layout) on NVIDIA B200 (Blackwell)."
-}
diff --git a/solutions/gdn/flashinfer_wrapper_9b7f1e.json b/solutions/gdn/flashinfer_wrapper_9b7f1e.json
deleted file mode 100644
index 67152cbf3297f59a1d7bdf0e57018ccfadd26f37..0000000000000000000000000000000000000000
--- a/solutions/gdn/flashinfer_wrapper_9b7f1e.json
+++ /dev/null
@@ -1,25 +0,0 @@
-{
-  "name": "flashinfer_wrapper_9b7f1e",
-  "definition": "gdn_decode_qk4_v8_d128_k_last",
-  "author": "flashinfer",
-  "spec": {
-    "language": "python",
-    "target_hardware": [
-      "NVIDIA H20",
-      "NVIDIA H100",
-      "NVIDIA H200"
-    ],
-    "entry_point": "main.py::run",
-    "dependencies": [
-      "flashinfer"
-    ],
-    "destination_passing_style": false
-  },
-  "sources": [
-    {
-      "path": "main.py",
-      "content": "import math\nimport torch\nfrom flashinfer.gdn_decode import gated_delta_rule_decode_pretranspose\n\n\ndef run(q, k, v, state, A_log, a, dt_bias, b, scale):\n    if isinstance(scale, torch.Tensor):\n        scale = float(scale.item())\n    else:\n        scale = float(scale)\n    if scale == 0.0:\n        scale = 1.0 / math.sqrt(q.shape[-1])\n\n    B, T, num_v_heads, head_size = v.shape\n    output = torch.empty(B, T, num_v_heads, head_size, dtype=q.dtype, device=q.device)\n\n    out, new_state = gated_delta_rule_decode_pretranspose(\n        q=q,\n        k=k,\n        v=v,\n        state=state,\n        A_log=A_log,\n        a=a,\n        dt_bias=dt_bias,\n        b=b,\n        scale=scale,\n        output=output,\n        use_qk_l2norm=False,\n    )\n\n    return out, new_state\n"
-    }
-  ],
-  "description": "Solution using FlashInfer gated_delta_rule_decode_pretranspose for GDN single-token decode (qk4_v8_d128, k-last state layout)."
-}
diff --git a/solutions/gemm/deepgemm_bf16_n12288_k4096.json b/solutions/gemm/deepgemm_bf16_n12288_k4096.json
index c1200e57b64adbe807576f292a122960b0738a77..1319d330e5adae157b579d0f570cea1b652fabe6 100644
--- a/solutions/gemm/deepgemm_bf16_n12288_k4096.json
+++ b/solutions/gemm/deepgemm_bf16_n12288_k4096.json
@@ -2,7 +2,24 @@
   "name": "deepgemm_bf16_n12288_k4096",
   "definition": "dense_gemm_bf16_nt_n12288_k4096",
   "author": "inference-kernels",
-  "description": "DeepGEMM Blackwell BF16 GEMM with FP32 accumulation. Selected by local B200 comparison against FlashInfer CUTLASS, cuTile, and small-row CuTe DSL. Upstream: https://github.com/deepseek-ai/DeepGEMM/tree/1fc9c66975ee322d628b3288534ca0e9ce12a64d (MIT).",
-  "spec": {"language": "python", "target_hardware": ["NVIDIA_B200"], "entry_point": "main.py::run", "dependencies": ["torch>=2.11", "deep-gemm @ git+https://github.com/deepseek-ai/DeepGEMM.git@1fc9c66975ee322d628b3288534ca0e9ce12a64d"], "destination_passing_style": false},
-  "sources": [{"path": "main.py", "content": "import torch\nimport deep_gemm\n\ndef run(A, W):\n    output = torch.empty((A.shape[0], W.shape[0]), dtype=torch.bfloat16, device=A.device)\n    deep_gemm.bf16_gemm_nt(A, W, output)\n    return output\n"}]
+  "description": "DeepGEMM BF16 NT GEMM with native linear on the B300 large-row shapes M=12288/16384/24576 that won the current paired comparisons. Other shapes and B200 retain DeepGEMM. All captured workloads are validated against the unchanged reference; no tolerance change.",
+  "spec": {
+    "language": "python",
+    "target_hardware": [
+      "NVIDIA_B200",
+      "NVIDIA_B300"
+    ],
+    "entry_point": "main.py::run",
+    "dependencies": [
+      "torch>=2.11",
+      "deep-gemm @ git+https://github.com/deepseek-ai/DeepGEMM.git@1fc9c66975ee322d628b3288534ca0e9ce12a64d"
+    ],
+    "destination_passing_style": false
+  },
+  "sources": [
+    {
+      "path": "main.py",
+      "content": "import torch\nimport deep_gemm\nfrom torch.nn import functional as F\n\n\ndef run(A, W):\n    # B300 comparisons favor native linear on these retained large-row shapes.\n    if (torch.cuda.get_device_capability(A.device) == (10, 3)\n            and A.shape[0] in (12288, 16384, 24576)):\n        return F.linear(A, W)\n    output = torch.empty((A.shape[0], W.shape[0]), dtype=torch.bfloat16, device=A.device)\n    deep_gemm.bf16_gemm_nt(A, W, output)\n    return output\n"
+    }
+  ]
 }
diff --git a/solutions/gemm/deepgemm_bf16_n4096_k12288.json b/solutions/gemm/deepgemm_bf16_n4096_k12288.json
index 7b5660eda40a624135e4eb7383adb8f4a59b8118..e267b7b5600338906b8ffe694bf609388b26c52b 100644
--- a/solutions/gemm/deepgemm_bf16_n4096_k12288.json
+++ b/solutions/gemm/deepgemm_bf16_n4096_k12288.json
@@ -3,6 +3,23 @@
   "definition": "dense_gemm_bf16_nt_n4096_k12288",
   "author": "inference-kernels",
   "description": "DeepGEMM Blackwell BF16 GEMM with FP32 accumulation. Selected by local B200 comparison against FlashInfer CUTLASS, cuTile, and small-row CuTe DSL. Upstream: https://github.com/deepseek-ai/DeepGEMM/tree/1fc9c66975ee322d628b3288534ca0e9ce12a64d (MIT).",
-  "spec": {"language": "python", "target_hardware": ["NVIDIA_B200"], "entry_point": "main.py::run", "dependencies": ["torch>=2.11", "deep-gemm @ git+https://github.com/deepseek-ai/DeepGEMM.git@1fc9c66975ee322d628b3288534ca0e9ce12a64d"], "destination_passing_style": false},
-  "sources": [{"path": "main.py", "content": "import torch\nimport deep_gemm\n\ndef run(A, W):\n    output = torch.empty((A.shape[0], W.shape[0]), dtype=torch.bfloat16, device=A.device)\n    deep_gemm.bf16_gemm_nt(A, W, output)\n    return output\n"}]
+  "spec": {
+    "language": "python",
+    "target_hardware": [
+      "NVIDIA_B200",
+      "NVIDIA_B300"
+    ],
+    "entry_point": "main.py::run",
+    "dependencies": [
+      "torch>=2.11",
+      "deep-gemm @ git+https://github.com/deepseek-ai/DeepGEMM.git@1fc9c66975ee322d628b3288534ca0e9ce12a64d"
+    ],
+    "destination_passing_style": false
+  },
+  "sources": [
+    {
+      "path": "main.py",
+      "content": "import torch\nimport deep_gemm\n\ndef run(A, W):\n    output = torch.empty((A.shape[0], W.shape[0]), dtype=torch.bfloat16, device=A.device)\n    deep_gemm.bf16_gemm_nt(A, W, output)\n    return output\n"
+    }
+  ]
 }
diff --git a/solutions/gemm/hybrid_bf16_n4096_k4096.json b/solutions/gemm/hybrid_bf16_n4096_k4096.json
index 6e03ae0ebb992f6ab2bcf9f1f8b0d36b389b237c..e5b163a7ccc7dc8f1b4ee1bd9794301e736ae189 100644
--- a/solutions/gemm/hybrid_bf16_n4096_k4096.json
+++ b/solutions/gemm/hybrid_bf16_n4096_k4096.json
@@ -2,7 +2,24 @@
   "name": "hybrid_bf16_n4096_k4096",
   "definition": "dense_gemm_bf16_nt_n4096_k4096",
   "author": "inference-kernels",
-  "description": "Shape-based B200 dispatch between FlashInfer CuTe DSL for 1-4 or 32 rows and DeepGEMM otherwise. Selected by local comparisons on actual captured shapes. Upstreams: https://github.com/flashinfer-ai/flashinfer (Apache-2.0), https://github.com/deepseek-ai/DeepGEMM/tree/1fc9c66975ee322d628b3288534ca0e9ce12a64d (MIT).",
-  "spec": {"language": "python", "target_hardware": ["NVIDIA_B200"], "entry_point": "main.py::run", "dependencies": ["torch>=2.11", "flashinfer-python==0.7.2", "nvidia-cutlass-dsl[cu13]==4.7.1", "deep-gemm @ git+https://github.com/deepseek-ai/DeepGEMM.git@1fc9c66975ee322d628b3288534ca0e9ce12a64d"], "destination_passing_style": false},
-  "sources": [{"path": "main.py", "content": "import torch\nimport deep_gemm\nfrom flashinfer.gemm import mm_bf16\n\ndef run(A, W):\n    rows = A.shape[0]\n    if rows <= 4 or rows == 32:\n        return mm_bf16(A, W.T, backend='cute-dsl')\n    output = torch.empty((rows, W.shape[0]), dtype=torch.bfloat16, device=A.device)\n    deep_gemm.bf16_gemm_nt(A, W, output)\n    return output\n"}]
+  "description": "DeepGEMM BF16 NT GEMM for the retained M >= 4096 workloads. Removed the unreachable small-M FlashInfer branch and its conflicting CUTLASS dependency. Upstream: https://github.com/deepseek-ai/DeepGEMM/tree/1fc9c66975ee322d628b3288534ca0e9ce12a64d (MIT).",
+  "spec": {
+    "language": "python",
+    "target_hardware": [
+      "NVIDIA_B200",
+      "NVIDIA_B300"
+    ],
+    "entry_point": "main.py::run",
+    "dependencies": [
+      "torch>=2.11",
+      "deep-gemm @ git+https://github.com/deepseek-ai/DeepGEMM.git@1fc9c66975ee322d628b3288534ca0e9ce12a64d"
+    ],
+    "destination_passing_style": false
+  },
+  "sources": [
+    {
+      "path": "main.py",
+      "content": "import torch\nimport deep_gemm\n\n\ndef run(A, W):\n    output = torch.empty((A.shape[0], W.shape[0]), dtype=torch.bfloat16, device=A.device)\n    deep_gemm.bf16_gemm_nt(A, W, output)\n    return output\n"
+    }
+  ]
 }
diff --git a/solutions/grouped_gemm/deepgemm_n4608_k5120.json b/solutions/grouped_gemm/deepgemm_n4608_k5120.json
index 28e0db26c95a343aae319334f13355fa939d3658..8c8639abb58299f1ad210027a25aed666557253a 100644
--- a/solutions/grouped_gemm/deepgemm_n4608_k5120.json
+++ b/solutions/grouped_gemm/deepgemm_n4608_k5120.json
@@ -3,6 +3,23 @@
   "definition": "grouped_gemm_fp8_fp4_e384_n4608_k5120_g32",
   "author": "inference-kernels",
   "description": "DeepGEMM MXFP8 x MXFP4 grouped GEMM. Aligns expert segments, packs scales without requantization, and restores original row order. Upstream: https://github.com/deepseek-ai/DeepGEMM/tree/1fc9c66975ee322d628b3288534ca0e9ce12a64d (MIT).",
-  "spec": {"language": "python", "target_hardware": ["NVIDIA_B200"], "entry_point": "main.py::run", "dependencies": ["torch>=2.11", "deep-gemm @ git+https://github.com/deepseek-ai/DeepGEMM.git@1fc9c66975ee322d628b3288534ca0e9ce12a64d"], "destination_passing_style": false},
-  "sources": [{"path": "main.py", "content": "import torch\nimport deep_gemm\n\ndef run(Aq, Wq_packed, scale_A, scale_W, expert_id):\n    m, k = Aq.shape\n    experts, n, _ = Wq_packed.shape\n    alignment = deep_gemm.get_mk_alignment_for_contiguous_layout()\n    capacity = ((m + min(m, experts) * (alignment - 1) + alignment - 1) // alignment) * alignment\n    boundaries = torch.searchsorted(expert_id, torch.arange(experts + 1, device=Aq.device, dtype=torch.int32))\n    counts = boundaries[1:] - boundaries[:-1]\n    padded_counts = ((counts + alignment - 1) // alignment) * alignment\n    offsets = padded_counts.cumsum(0) - padded_counts\n    ids = expert_id.long()\n    row_map = offsets[ids] + torch.arange(m, device=Aq.device) - boundaries[ids]\n    a = torch.zeros((capacity, k), device=Aq.device, dtype=Aq.dtype)\n    a.view(torch.uint8).index_copy_(0, row_map, Aq.view(torch.uint8))\n    sa = torch.full((capacity, k // 32), 127, device=Aq.device, dtype=torch.int8)\n    sa.index_copy_(0, row_map, scale_A)\n    sa = sa.view(torch.int32).t().contiguous().t()\n    sw = scale_W.view(torch.int32).transpose(-1, -2).contiguous().transpose(-1, -2)\n    layout = torch.full((capacity,), -1, device=Aq.device, dtype=torch.int32)\n    layout.index_copy_(0, row_map, expert_id)\n    output = torch.empty((capacity, n), device=Aq.device, dtype=torch.bfloat16)\n    deep_gemm.m_grouped_fp8_fp4_gemm_nt_contiguous(\n        (a, sa), (Wq_packed, sw), output, layout,\n        recipe_a=(1, 32), recipe_b=(1, 32),\n    )\n    return output.index_select(0, row_map)\n"}]
+  "spec": {
+    "language": "python",
+    "target_hardware": [
+      "NVIDIA_B200",
+      "NVIDIA_B300"
+    ],
+    "entry_point": "main.py::run",
+    "dependencies": [
+      "torch>=2.11",
+      "deep-gemm @ git+https://github.com/deepseek-ai/DeepGEMM.git@1fc9c66975ee322d628b3288534ca0e9ce12a64d"
+    ],
+    "destination_passing_style": false
+  },
+  "sources": [
+    {
+      "path": "main.py",
+      "content": "import torch\nimport deep_gemm\n\ndef run(Aq, Wq_packed, scale_A, scale_W, expert_id):\n    m, k = Aq.shape\n    experts, n, _ = Wq_packed.shape\n    alignment = deep_gemm.get_mk_alignment_for_contiguous_layout()\n    capacity = ((m + min(m, experts) * (alignment - 1) + alignment - 1) // alignment) * alignment\n    boundaries = torch.searchsorted(expert_id, torch.arange(experts + 1, device=Aq.device, dtype=torch.int32))\n    counts = boundaries[1:] - boundaries[:-1]\n    padded_counts = ((counts + alignment - 1) // alignment) * alignment\n    offsets = padded_counts.cumsum(0) - padded_counts\n    ids = expert_id.long()\n    row_map = offsets[ids] + torch.arange(m, device=Aq.device) - boundaries[ids]\n    a = torch.zeros((capacity, k), device=Aq.device, dtype=Aq.dtype)\n    a.view(torch.uint8).index_copy_(0, row_map, Aq.view(torch.uint8))\n    sa = torch.full((capacity, k // 32), 127, device=Aq.device, dtype=torch.int8)\n    sa.index_copy_(0, row_map, scale_A)\n    sa = sa.view(torch.int32).t().contiguous().t()\n    sw = scale_W.view(torch.int32).transpose(-1, -2).contiguous().transpose(-1, -2)\n    layout = torch.full((capacity,), -1, device=Aq.device, dtype=torch.int32)\n    layout.index_copy_(0, row_map, expert_id)\n    output = torch.empty((capacity, n), device=Aq.device, dtype=torch.bfloat16)\n    deep_gemm.m_grouped_fp8_fp4_gemm_nt_contiguous(\n        (a, sa), (Wq_packed, sw), output, layout,\n        recipe_a=(1, 32), recipe_b=(1, 32),\n    )\n    return output.index_select(0, row_map)\n"
+    }
+  ]
 }
diff --git a/solutions/grouped_gemm/deepgemm_n5120_k2304.json b/solutions/grouped_gemm/deepgemm_n5120_k2304.json
index 755f86c0ecdeb0ee4a07fd869ba398ebf03a49ba..5f8d0d02462876515977767e9be7288cc04822e3 100644
--- a/solutions/grouped_gemm/deepgemm_n5120_k2304.json
+++ b/solutions/grouped_gemm/deepgemm_n5120_k2304.json
@@ -3,6 +3,23 @@
   "definition": "grouped_gemm_fp8_fp4_e384_n5120_k2304_g32",
   "author": "inference-kernels",
   "description": "DeepGEMM MXFP8 x MXFP4 grouped GEMM. Aligns expert segments, packs scales without requantization, and restores original row order. Upstream: https://github.com/deepseek-ai/DeepGEMM/tree/1fc9c66975ee322d628b3288534ca0e9ce12a64d (MIT).",
-  "spec": {"language": "python", "target_hardware": ["NVIDIA_B200"], "entry_point": "main.py::run", "dependencies": ["torch>=2.11", "deep-gemm @ git+https://github.com/deepseek-ai/DeepGEMM.git@1fc9c66975ee322d628b3288534ca0e9ce12a64d"], "destination_passing_style": false},
-  "sources": [{"path": "main.py", "content": "import torch\nimport deep_gemm\n\ndef run(Aq, Wq_packed, scale_A, scale_W, expert_id):\n    m, k = Aq.shape\n    experts, n, _ = Wq_packed.shape\n    alignment = deep_gemm.get_mk_alignment_for_contiguous_layout()\n    capacity = ((m + min(m, experts) * (alignment - 1) + alignment - 1) // alignment) * alignment\n    boundaries = torch.searchsorted(expert_id, torch.arange(experts + 1, device=Aq.device, dtype=torch.int32))\n    counts = boundaries[1:] - boundaries[:-1]\n    padded_counts = ((counts + alignment - 1) // alignment) * alignment\n    offsets = padded_counts.cumsum(0) - padded_counts\n    ids = expert_id.long()\n    row_map = offsets[ids] + torch.arange(m, device=Aq.device) - boundaries[ids]\n    a = torch.zeros((capacity, k), device=Aq.device, dtype=Aq.dtype)\n    a.view(torch.uint8).index_copy_(0, row_map, Aq.view(torch.uint8))\n    sa = torch.full((capacity, k // 32), 127, device=Aq.device, dtype=torch.int8)\n    sa.index_copy_(0, row_map, scale_A)\n    sa = sa.view(torch.int32).t().contiguous().t()\n    sw = scale_W.view(torch.int32).transpose(-1, -2).contiguous().transpose(-1, -2)\n    layout = torch.full((capacity,), -1, device=Aq.device, dtype=torch.int32)\n    layout.index_copy_(0, row_map, expert_id)\n    output = torch.empty((capacity, n), device=Aq.device, dtype=torch.bfloat16)\n    deep_gemm.m_grouped_fp8_fp4_gemm_nt_contiguous(\n        (a, sa), (Wq_packed, sw), output, layout,\n        recipe_a=(1, 32), recipe_b=(1, 32),\n    )\n    return output.index_select(0, row_map)\n"}]
+  "spec": {
+    "language": "python",
+    "target_hardware": [
+      "NVIDIA_B200",
+      "NVIDIA_B300"
+    ],
+    "entry_point": "main.py::run",
+    "dependencies": [
+      "torch>=2.11",
+      "deep-gemm @ git+https://github.com/deepseek-ai/DeepGEMM.git@1fc9c66975ee322d628b3288534ca0e9ce12a64d"
+    ],
+    "destination_passing_style": false
+  },
+  "sources": [
+    {
+      "path": "main.py",
+      "content": "import torch\nimport deep_gemm\n\ndef run(Aq, Wq_packed, scale_A, scale_W, expert_id):\n    m, k = Aq.shape\n    experts, n, _ = Wq_packed.shape\n    alignment = deep_gemm.get_mk_alignment_for_contiguous_layout()\n    capacity = ((m + min(m, experts) * (alignment - 1) + alignment - 1) // alignment) * alignment\n    boundaries = torch.searchsorted(expert_id, torch.arange(experts + 1, device=Aq.device, dtype=torch.int32))\n    counts = boundaries[1:] - boundaries[:-1]\n    padded_counts = ((counts + alignment - 1) // alignment) * alignment\n    offsets = padded_counts.cumsum(0) - padded_counts\n    ids = expert_id.long()\n    row_map = offsets[ids] + torch.arange(m, device=Aq.device) - boundaries[ids]\n    a = torch.zeros((capacity, k), device=Aq.device, dtype=Aq.dtype)\n    a.view(torch.uint8).index_copy_(0, row_map, Aq.view(torch.uint8))\n    sa = torch.full((capacity, k // 32), 127, device=Aq.device, dtype=torch.int8)\n    sa.index_copy_(0, row_map, scale_A)\n    sa = sa.view(torch.int32).t().contiguous().t()\n    sw = scale_W.view(torch.int32).transpose(-1, -2).contiguous().transpose(-1, -2)\n    layout = torch.full((capacity,), -1, device=Aq.device, dtype=torch.int32)\n    layout.index_copy_(0, row_map, expert_id)\n    output = torch.empty((capacity, n), device=Aq.device, dtype=torch.bfloat16)\n    deep_gemm.m_grouped_fp8_fp4_gemm_nt_contiguous(\n        (a, sa), (Wq_packed, sw), output, layout,\n        recipe_a=(1, 32), recipe_b=(1, 32),\n    )\n    return output.index_select(0, row_map)\n"
+    }
+  ]
 }
diff --git a/solutions/mixed_mla/flashmla_v41.json b/solutions/mixed_mla/flashmla_v41.json
index ef8845db54675a1c9ce435d6204dd448d63bb192..32d99cd2af141594f04ea1f95e9736e80e6eb882 100644
--- a/solutions/mixed_mla/flashmla_v41.json
+++ b/solutions/mixed_mla/flashmla_v41.json
@@ -3,6 +3,23 @@
   "definition": "mixed_mla_decode_deepseek41_h64_d512_k8128_k4512",
   "author": "inference-kernels",
   "description": "FlashMLA V4.1 sparse mixed FP8/FP4 attention. Adapts the captured page-planar layout to upstream's token-interleaved layout without requantization. Upstream: https://github.com/deepseek-ai/FlashMLA/tree/0f11e178da1f67becb087a324b400854931ec3e3 (MIT).",
-  "spec": {"language": "python", "target_hardware": ["NVIDIA_B200"], "entry_point": "main.py::run", "dependencies": ["torch>=2.11", "flash-mla @ git+https://github.com/deepseek-ai/FlashMLA.git@0f11e178da1f67becb087a324b400854931ec3e3"], "destination_passing_style": false},
-  "sources": [{"path": "main.py", "content": "from functools import lru_cache\nimport torch\nfrom flash_mla import flash_mla_with_kvcache, get_mla_metadata\n\n@lru_cache(maxsize=64)\ndef metadata(device, batch, queries, heads, page8, page4):\n    # No per-request top-k lengths are passed; scheduling depends only on shapes.\n    return get_mla_metadata()[0]\n\ndef interleave(cache, payload):\n    pages, page_size, _, record = cache.shape\n    flat = cache.reshape(pages, -1)\n    values = flat[:, :page_size * payload].reshape(pages, page_size, 1, payload)\n    scales = flat[:, page_size * payload:].reshape(pages, page_size, 1, record - payload)\n    return torch.cat((values, scales), dim=-1)\n\ndef run(Q, KV8, KV4, indices8, indices4, attn_sink, sm_scale):\n    cache8 = interleave(KV8, 512)\n    cache4 = interleave(KV4, 256)\n    plan = metadata(Q.device, *Q.shape[:3], KV8.shape[1], KV4.shape[1])\n    return flash_mla_with_kvcache(\n        Q, cache8, None, None, 512, plan, softmax_scale=sm_scale,\n        indices=indices8, attn_sink=attn_sink, extra_k_cache=cache4,\n        extra_indices_in_kvcache=indices4,\n    )[0]\n"}]
+  "spec": {
+    "language": "python",
+    "target_hardware": [
+      "NVIDIA_B200",
+      "NVIDIA_B300"
+    ],
+    "entry_point": "main.py::run",
+    "dependencies": [
+      "torch>=2.11",
+      "flash-mla @ git+https://github.com/deepseek-ai/FlashMLA.git@0f11e178da1f67becb087a324b400854931ec3e3"
+    ],
+    "destination_passing_style": false
+  },
+  "sources": [
+    {
+      "path": "main.py",
+      "content": "from functools import lru_cache\nimport torch\nfrom flash_mla import flash_mla_with_kvcache, get_mla_metadata\n\n@lru_cache(maxsize=64)\ndef metadata(device, batch, queries, heads, page8, page4):\n    # No per-request top-k lengths are passed; scheduling depends only on shapes.\n    return get_mla_metadata()[0]\n\ndef interleave(cache, payload):\n    pages, page_size, _, record = cache.shape\n    flat = cache.reshape(pages, -1)\n    values = flat[:, :page_size * payload].reshape(pages, page_size, 1, payload)\n    scales = flat[:, page_size * payload:].reshape(pages, page_size, 1, record - payload)\n    return torch.cat((values, scales), dim=-1)\n\ndef run(Q, KV8, KV4, indices8, indices4, attn_sink, sm_scale):\n    cache8 = interleave(KV8, 512)\n    cache4 = interleave(KV4, 256)\n    plan = metadata(Q.device, *Q.shape[:3], KV8.shape[1], KV4.shape[1])\n    return flash_mla_with_kvcache(\n        Q, cache8, None, None, 512, plan, softmax_scale=sm_scale,\n        indices=indices8, attn_sink=attn_sink, extra_k_cache=cache4,\n        extra_indices_in_kvcache=indices4,\n    )[0]\n"
+    }
+  ]
 }
diff --git a/solutions/moe_router/cutlass_router.json b/solutions/moe_router/cutlass_router.json
deleted file mode 100644
index dc226d1db6ee1a347066c1d2a7bc9abc23fea698..0000000000000000000000000000000000000000
--- a/solutions/moe_router/cutlass_router.json
+++ /dev/null
@@ -1,8 +0,0 @@
-{
-  "name": "cutlass_router",
-  "definition": "moe_router_gemm_topk_deepseek41_d5120_e384_topk6",
-  "author": "inference-kernels",
-  "description": "FlashInfer CUTLASS BF16-input, FP32-output GEMM and PyTorch Inductor routing with stable selection. Bias affects ranking only; returned expert IDs are ascending. Upstream: https://github.com/flashinfer-ai/flashinfer (Apache-2.0), https://github.com/pytorch/pytorch (BSD-3-Clause).",
-  "spec": {"language": "python", "target_hardware": ["NVIDIA_B200"], "entry_point": "main.py::run", "dependencies": ["torch==2.11.0", "flashinfer-python==0.7.2", "triton>=3.6"], "destination_passing_style": false},
-  "sources": [{"path": "main.py", "content": "import torch\nfrom flashinfer.gemm import mm_bf16\n\n@torch.compile(fullgraph=True)\ndef select(logits, bias_text, bias_image, is_image_token, routed_scale):\n    scores = torch.sqrt(torch.log1p(torch.exp(-logits.abs())) + logits.clamp_min(0))\n    bias = torch.where(is_image_token[:, None], bias_image[None], bias_text[None])\n    ids = torch.argsort(scores + bias, dim=-1, descending=True, stable=True)[:, :6]\n    ids = ids.sort(dim=-1).values\n    selected = scores.gather(1, ids)\n    weights = selected / (selected.sum(dim=-1, keepdim=True) + 1e-20) * routed_scale\n    return ids, weights\n\ndef run(X, W, bias_text, bias_image, is_image_token, routed_scale):\n    logits = mm_bf16(X, W.T, out_dtype=torch.float32, backend='cutlass')\n    return select(logits, bias_text, bias_image, is_image_token, routed_scale)\n"}]
-}
diff --git a/solutions/moe_router/fused_router.json b/solutions/moe_router/fused_router.json
new file mode 100644
index 0000000000000000000000000000000000000000..43efa0d18d68dde7641fac8646187080b361cb7a
--- /dev/null
+++ b/solutions/moe_router/fused_router.json
@@ -0,0 +1,26 @@
+{
+  "name": "fused_router",
+  "definition": "moe_router_gemm_topk_deepseek41_d5120_e384_topk6",
+  "author": "inference-kernels",
+  "description": "SGLang BF16-to-FP32 projection (tiny GEMM for M <= 16), fused sqrt-softplus modality-aware Top-6 routing with normalization and routed scaling, and one Triton output ordering kernel. Accepts the image-token boolean directly. All 50 current workloads pass the existing strict FP32 and exact-ID policy on B300.",
+  "spec": {
+    "language": "python",
+    "target_hardware": [
+      "NVIDIA_B200",
+      "NVIDIA_B300"
+    ],
+    "entry_point": "main.py::run",
+    "dependencies": [
+      "torch>=2.14.1",
+      "sglang @ git+https://github.com/sgl-project/sglang.git@0025f9394421451aa09ec192a4a6e7928e14736b#subdirectory=python",
+      "triton>=3.8"
+    ],
+    "destination_passing_style": false
+  },
+  "sources": [
+    {
+      "path": "main.py",
+      "content": "import torch\nimport triton as tr\nimport triton.language as tl\nfrom sglang.kernels.ops.gemm.bf16_fp32 import linear_bf16_fp32\nfrom sglang.kernels.ops.gemm.tiny_gemm import tiny_gemm_bf16\nfrom sglang.kernels.ops.moe.moe_fused_gate import moe_fused_gate\nfrom sglang.srt.layers.moe.topk import _RENORMALIZE_SUM_EPSILON\n\n@tr.jit\ndef order_ids(Ids, Weights, OutIds, OutWeights):\n    b=tl.program_id(0)\n    k=tl.arange(0,8)\n    ids=tl.load(Ids+b*6+k,k<6,other=2147483647)\n    weights=tl.load(Weights+b*6+k,k<6,other=0.)\n    ordered=tl.sort(ids,descending=False)\n    values=tl.sum(tl.where(ordered[:,None]==ids[None,:],weights[None,:],0.),1)\n    tl.store(OutIds+b*6+k,ordered.to(tl.int64),k<6)\n    tl.store(OutWeights+b*6+k,values,k<6)\n\ndef run(X,W,bias_text,bias_image,is_image_token,routed_scale):\n    logits=tiny_gemm_bf16(X,W,out_dtype=torch.float32,max_m=16) if X.shape[0]<=16 else linear_bf16_fp32(X,W)\n    weights,ids=moe_fused_gate(logits,bias_text,topk=6,scoring_func='sqrtsoftplus',\n        num_fused_shared_experts=0,bias_alt=bias_image,input_ids=is_image_token,bias_alt_token_id=1,\n        renormalize=True,renormalize_epsilon=_RENORMALIZE_SUM_EPSILON,\n        routed_scaling_factor=routed_scale,apply_routed_scaling_factor_on_output=True,\n        num_token_non_padded=None,packed_out=None,sqrtsoftplus_log1p=True)\n    out_ids=torch.empty((X.shape[0],6),device=X.device,dtype=torch.int64)\n    out_weights=torch.empty_like(weights)\n    order_ids[(X.shape[0],)](ids,weights,out_ids,out_weights)\n    return out_ids,out_weights\n"
+    }
+  ]
+}
diff --git a/solutions/neighborhood_attention/natten_blackwell_h16_3x7x7.json b/solutions/neighborhood_attention/natten_blackwell_h16_3x7x7.json
index fd5496b286b0e80354b9faea18b6cc99a3587b91..8e5541c5da4071767b897a98f5b18503f609b2d2 100644
--- a/solutions/neighborhood_attention/natten_blackwell_h16_3x7x7.json
+++ b/solutions/neighborhood_attention/natten_blackwell_h16_3x7x7.json
@@ -3,6 +3,23 @@
   "definition": "neighborhood_attention_3d_h16_d64_kt3_ky7_kx7",
   "author": "inference-kernels",
   "description": "NATTEN 0.21.7 Blackwell fused neighborhood attention with inward-shifted boundary windows. Queries already include the model scale. Upstream: https://github.com/SHI-Labs/NATTEN/tree/39375ea1d2f3b1bb284315fa5f79f6ecbebb6382 (MIT).",
-  "spec": {"language": "python", "target_hardware": ["NVIDIA_B200"], "entry_point": "main.py::run", "dependencies": ["torch>=2.11", "natten==0.21.7"], "destination_passing_style": false},
-  "sources": [{"path": "main.py", "content": "from natten.functional import na3d\n\ndef run(Q, K, V):\n    return na3d(Q, K, V, kernel_size=(3, 7, 7), scale=1.0, backend='blackwell-fna')\n"}]
+  "spec": {
+    "language": "python",
+    "target_hardware": [
+      "NVIDIA_B200",
+      "NVIDIA_B300"
+    ],
+    "entry_point": "main.py::run",
+    "dependencies": [
+      "torch>=2.11",
+      "natten==0.21.7"
+    ],
+    "destination_passing_style": false
+  },
+  "sources": [
+    {
+      "path": "main.py",
+      "content": "from natten.functional import na3d\n\ndef run(Q, K, V):\n    return na3d(Q, K, V, kernel_size=(3, 7, 7), scale=1.0, backend='blackwell-fna')\n"
+    }
+  ]
 }
diff --git a/solutions/neighborhood_attention/natten_blackwell_h32_3x7x7.json b/solutions/neighborhood_attention/natten_blackwell_h32_3x7x7.json
index 9b9622008ca25df88da5c39a15a90de15c0e6790..ba8323370ac16977ddc35a7dff4ce32c66d96ffd 100644
--- a/solutions/neighborhood_attention/natten_blackwell_h32_3x7x7.json
+++ b/solutions/neighborhood_attention/natten_blackwell_h32_3x7x7.json
@@ -3,6 +3,23 @@
   "definition": "neighborhood_attention_3d_h32_d64_kt3_ky7_kx7",
   "author": "inference-kernels",
   "description": "NATTEN 0.21.7 Blackwell fused neighborhood attention with inward-shifted boundary windows. Queries already include the model scale. Upstream: https://github.com/SHI-Labs/NATTEN/tree/39375ea1d2f3b1bb284315fa5f79f6ecbebb6382 (MIT).",
-  "spec": {"language": "python", "target_hardware": ["NVIDIA_B200"], "entry_point": "main.py::run", "dependencies": ["torch>=2.11", "natten==0.21.7"], "destination_passing_style": false},
-  "sources": [{"path": "main.py", "content": "from natten.functional import na3d\n\ndef run(Q, K, V):\n    return na3d(Q, K, V, kernel_size=(3, 7, 7), scale=1.0, backend='blackwell-fna')\n"}]
+  "spec": {
+    "language": "python",
+    "target_hardware": [
+      "NVIDIA_B200",
+      "NVIDIA_B300"
+    ],
+    "entry_point": "main.py::run",
+    "dependencies": [
+      "torch>=2.11",
+      "natten==0.21.7"
+    ],
+    "destination_passing_style": false
+  },
+  "sources": [
+    {
+      "path": "main.py",
+      "content": "from natten.functional import na3d\n\ndef run(Q, K, V):\n    return na3d(Q, K, V, kernel_size=(3, 7, 7), scale=1.0, backend='blackwell-fna')\n"
+    }
+  ]
 }
diff --git a/solutions/neighborhood_attention/natten_blackwell_h4_11x11x11.json b/solutions/neighborhood_attention/natten_blackwell_h4_11x11x11.json
index e9b1831193ac5f4b2f1dda35da7b4d801b84e3f4..fb36d69a93f8edfeee4ce57f1aa40501b50e1bf9 100644
--- a/solutions/neighborhood_attention/natten_blackwell_h4_11x11x11.json
+++ b/solutions/neighborhood_attention/natten_blackwell_h4_11x11x11.json
@@ -3,6 +3,23 @@
   "definition": "neighborhood_attention_3d_h4_d64_kt11_ky11_kx11",
   "author": "inference-kernels",
   "description": "NATTEN 0.21.7 Blackwell fused neighborhood attention with inward-shifted boundary windows. Queries already include the model scale. Upstream: https://github.com/SHI-Labs/NATTEN/tree/39375ea1d2f3b1bb284315fa5f79f6ecbebb6382 (MIT).",
-  "spec": {"language": "python", "target_hardware": ["NVIDIA_B200"], "entry_point": "main.py::run", "dependencies": ["torch>=2.11", "natten==0.21.7"], "destination_passing_style": false},
-  "sources": [{"path": "main.py", "content": "from natten.functional import na3d\n\ndef run(Q, K, V):\n    return na3d(Q, K, V, kernel_size=(11, 11, 11), scale=1.0, backend='blackwell-fna')\n"}]
+  "spec": {
+    "language": "python",
+    "target_hardware": [
+      "NVIDIA_B200",
+      "NVIDIA_B300"
+    ],
+    "entry_point": "main.py::run",
+    "dependencies": [
+      "torch>=2.11",
+      "natten==0.21.7"
+    ],
+    "destination_passing_style": false
+  },
+  "sources": [
+    {
+      "path": "main.py",
+      "content": "from natten.functional import na3d\n\ndef run(Q, K, V):\n    return na3d(Q, K, V, kernel_size=(11, 11, 11), scale=1.0, backend='blackwell-fna')\n"
+    }
+  ]
 }
diff --git a/solutions/neighborhood_attention/natten_blackwell_h8_3x5x5.json b/solutions/neighborhood_attention/natten_blackwell_h8_3x5x5.json
index a10e46f94822e92088a79657ba19aa5a6eb4312e..6c08866b63cac2733eb8781e139f7d4ec0590d30 100644
--- a/solutions/neighborhood_attention/natten_blackwell_h8_3x5x5.json
+++ b/solutions/neighborhood_attention/natten_blackwell_h8_3x5x5.json
@@ -3,6 +3,23 @@
   "definition": "neighborhood_attention_3d_h8_d64_kt3_ky5_kx5",
   "author": "inference-kernels",
   "description": "NATTEN 0.21.7 Blackwell fused neighborhood attention with inward-shifted boundary windows. Queries already include the model scale. Upstream: https://github.com/SHI-Labs/NATTEN/tree/39375ea1d2f3b1bb284315fa5f79f6ecbebb6382 (MIT).",
-  "spec": {"language": "python", "target_hardware": ["NVIDIA_B200"], "entry_point": "main.py::run", "dependencies": ["torch>=2.11", "natten==0.21.7"], "destination_passing_style": false},
-  "sources": [{"path": "main.py", "content": "from natten.functional import na3d\n\ndef run(Q, K, V):\n    return na3d(Q, K, V, kernel_size=(3, 5, 5), scale=1.0, backend='blackwell-fna')\n"}]
+  "spec": {
+    "language": "python",
+    "target_hardware": [
+      "NVIDIA_B200",
+      "NVIDIA_B300"
+    ],
+    "entry_point": "main.py::run",
+    "dependencies": [
+      "torch>=2.11",
+      "natten==0.21.7"
+    ],
+    "destination_passing_style": false
+  },
+  "sources": [
+    {
+      "path": "main.py",
+      "content": "from natten.functional import na3d\n\ndef run(Q, K, V):\n    return na3d(Q, K, V, kernel_size=(3, 5, 5), scale=1.0, backend='blackwell-fna')\n"
+    }
+  ]
 }
diff --git a/solutions/neighborhood_attention/sglang_neighborhood_attention_3d_h16_d64_kt3_ky7_kx7.json b/solutions/neighborhood_attention/sglang_neighborhood_attention_3d_h16_d64_kt3_ky7_kx7.json
index a5ddea11002b091191e3e6d2f7e7afab813ccc36..566cfbbc40a1476de1b6a3e8e4e5d36ade330667 100644
--- a/solutions/neighborhood_attention/sglang_neighborhood_attention_3d_h16_d64_kt3_ky7_kx7.json
+++ b/solutions/neighborhood_attention/sglang_neighborhood_attention_3d_h16_d64_kt3_ky7_kx7.json
@@ -17,7 +17,7 @@
   "sources": [
     {
       "path": "main.py",
-      "content": "# Copyright 2026 Co-developed by KDA (Kernel Design Agents)\n\"\"\"SGLang baseline for neighborhood_attention_3d_h16_d64_kt3_ky7_kx7.\n\nSGLang diffusion runtime at commit 684fea8a,\npython/sglang/multimodal_gen/runtime/models/decoders/ltx_2_5_diffusion_decoder.py:\nLTX2VideoVaeNeighborhoodAttention.forward (:425) after project_qkv (:435).\nNATTEN is absent from the image, so _na3d() (:49) is None and forward takes the\nFlexAttention branch: Q/K/V viewed as (B, heads, S, head_dim) (:449-459), the\nblock mask from build_block_mask (:413) -> _neighborhood_block_mask(T, H, W,\nkernel_size, device) (:170), and _flex_attention_fn() (:104, torch.compile of\nflex_attention, dynamic=False) called with scale=1.0 (:465-467).\n\nAdapter: Q/K/V arrive as project_qkv returns them, [B, T, Y, X, H, D].\nkernel_size is the module's (Kt, Ky, Kx). The decoder builds the block mask\nonce per stage (:771, :785, :835) and passes it to every block, so prepare\nbuilds it and launch runs only the attention. The output keeps the heads\nsplit: :468-470 merges them into channels for to_out, which is not part of\nthis op; that reshape is a view of the flex output, so launch detaches it\n(no copy) to return a tensor that owns its storage.\n\"\"\"\n\nimport torch\nfrom sglang.multimodal_gen.runtime.models.decoders import (\n    ltx_2_5_diffusion_decoder as ltx,\n)\n\nKERNEL_SIZE = (3, 7, 7)\n\n# The engine meets a few grids per process; one judge process meets every\n# workload's shape. Past dynamo's default limit of 8 recompiles flex_attention\n# would run uncompiled, materializing the dense S x S scores.\ntorch._dynamo.config.recompile_limit = 1024\ntorch._dynamo.config.accumulated_recompile_limit = 4096\n# The judge rejects a candidate that leaves child processes running, and\n# inductor's parallel compile pool is one; compile in-process instead.\ntorch._inductor.config.compile_threads = 1\n\n\ndef prepare(Q, K, V):\n    batch_size, num_frames, height, width, heads, head_dim = Q.shape\n    seq_len = num_frames * height * width\n    # :451-459\n    query = Q.reshape(batch_size, seq_len, heads, head_dim).transpose(1, 2)\n    key = K.reshape(batch_size, seq_len, heads, head_dim).transpose(1, 2)\n    value = V.reshape(batch_size, seq_len, heads, head_dim).transpose(1, 2)\n    # build_block_mask, :420-423\n    block_mask = ltx._neighborhood_block_mask(\n        num_frames, height, width, KERNEL_SIZE, Q.device\n    )\n    flex_attention = ltx._flex_attention_fn()\n\n    def launch():\n        # :465-467\n        hidden_states = flex_attention(\n            query, key, value, block_mask=block_mask, scale=1.0\n        )\n        # :468-470, heads kept split. The reshape is a view of flex_attention's\n        # own exact-sized output; detach() hands it over as a tensor of its own.\n        return hidden_states.transpose(1, 2).reshape(Q.shape).detach()\n\n    return launch\n\n\ndef run(Q, K, V):\n    return prepare(Q, K, V)()\n"
+      "content": "# Copyright 2026 Co-developed by KDA (Kernel Design Agents)\n\"\"\"SGLang baseline for neighborhood_attention_3d_h16_d64_kt3_ky7_kx7.\n\nSGLang diffusion runtime at commit 684fea8a,\npython/sglang/multimodal_gen/runtime/models/decoders/ltx_2_5_diffusion_decoder.py:\nLTX2VideoVaeNeighborhoodAttention.forward (:425) after project_qkv (:435).\nWhen NATTEN is installed, _na3d() selects its native Q/K/V call with scale=1.0.\nOtherwise (including the pinned capture image), forward takes the\nFlexAttention branch: Q/K/V viewed as (B, heads, S, head_dim) (:449-459), the\nblock mask from build_block_mask (:413) -> _neighborhood_block_mask(T, H, W,\nkernel_size, device) (:170), and _flex_attention_fn() (:104, torch.compile of\nflex_attention, dynamic=False) called with scale=1.0 (:465-467).\n\nAdapter: Q/K/V arrive as project_qkv returns them, [B, T, Y, X, H, D].\nkernel_size is the module's (Kt, Ky, Kx). The decoder builds the block mask\nonce per stage (:771, :785, :835) and passes it to every block, so prepare\nbuilds it and launch runs only the attention. The output keeps the heads\nsplit: :468-470 merges them into channels for to_out, which is not part of\nthis op; that reshape is a view of the flex output, so launch detaches it\n(no copy) to return a tensor that owns its storage.\n\"\"\"\n\nimport torch\nfrom sglang.multimodal_gen.runtime.models.decoders import (\n    ltx_2_5_diffusion_decoder as ltx,\n)\n\nKERNEL_SIZE = (3, 7, 7)\n\n# The engine meets a few grids per process; one judge process meets every\n# workload's shape. Past dynamo's default limit of 8 recompiles flex_attention\n# would run uncompiled, materializing the dense S x S scores.\ntorch._dynamo.config.recompile_limit = 1024\ntorch._dynamo.config.accumulated_recompile_limit = 4096\n# The judge rejects a candidate that leaves child processes running, and\n# inductor's parallel compile pool is one; compile in-process instead.\ntorch._inductor.config.compile_threads = 1\n\n\ndef prepare(Q, K, V):\n    na3d = ltx._na3d()\n    if na3d is not None:\n        # Match the engine branch when the faster optional backend is installed.\n        return lambda: na3d(Q, K, V, kernel_size=KERNEL_SIZE, scale=1.0).detach()\n\n    batch_size, num_frames, height, width, heads, head_dim = Q.shape\n    seq_len = num_frames * height * width\n    # :451-459\n    query = Q.reshape(batch_size, seq_len, heads, head_dim).transpose(1, 2)\n    key = K.reshape(batch_size, seq_len, heads, head_dim).transpose(1, 2)\n    value = V.reshape(batch_size, seq_len, heads, head_dim).transpose(1, 2)\n    # build_block_mask, :420-423\n    block_mask = ltx._neighborhood_block_mask(\n        num_frames, height, width, KERNEL_SIZE, Q.device\n    )\n    flex_attention = ltx._flex_attention_fn()\n\n    def launch():\n        # :465-467\n        hidden_states = flex_attention(\n            query, key, value, block_mask=block_mask, scale=1.0\n        )\n        # :468-470, heads kept split. The reshape is a view of flex_attention's\n        # own exact-sized output; detach() hands it over as a tensor of its own.\n        return hidden_states.transpose(1, 2).reshape(Q.shape).detach()\n\n    return launch\n\n\ndef run(Q, K, V):\n    return prepare(Q, K, V)()\n"
     }
   ]
 }
diff --git a/solutions/neighborhood_attention/sglang_neighborhood_attention_3d_h32_d64_kt3_ky7_kx7.json b/solutions/neighborhood_attention/sglang_neighborhood_attention_3d_h32_d64_kt3_ky7_kx7.json
index 8b9470880036db80584989a5858078cac391d768..51dd827bd2ca2bfc28a3afaaf41f9203f0628b4d 100644
--- a/solutions/neighborhood_attention/sglang_neighborhood_attention_3d_h32_d64_kt3_ky7_kx7.json
+++ b/solutions/neighborhood_attention/sglang_neighborhood_attention_3d_h32_d64_kt3_ky7_kx7.json
@@ -17,7 +17,7 @@
   "sources": [
     {
       "path": "main.py",
-      "content": "# Copyright 2026 Co-developed by KDA (Kernel Design Agents)\n\"\"\"SGLang baseline for neighborhood_attention_3d_h32_d64_kt3_ky7_kx7.\n\nSGLang diffusion runtime at commit 684fea8a,\npython/sglang/multimodal_gen/runtime/models/decoders/ltx_2_5_diffusion_decoder.py:\nLTX2VideoVaeNeighborhoodAttention.forward (:425) after project_qkv (:435).\nNATTEN is absent from the image, so _na3d() (:49) is None and forward takes the\nFlexAttention branch: Q/K/V viewed as (B, heads, S, head_dim) (:449-459), the\nblock mask from build_block_mask (:413) -> _neighborhood_block_mask(T, H, W,\nkernel_size, device) (:170), and _flex_attention_fn() (:104, torch.compile of\nflex_attention, dynamic=False) called with scale=1.0 (:465-467).\n\nAdapter: Q/K/V arrive as project_qkv returns them, [B, T, Y, X, H, D].\nkernel_size is the module's (Kt, Ky, Kx). The decoder builds the block mask\nonce per stage (:771, :785, :835) and passes it to every block, so prepare\nbuilds it and launch runs only the attention. The output keeps the heads\nsplit: :468-470 merges them into channels for to_out, which is not part of\nthis op; that reshape is a view of the flex output, so launch detaches it\n(no copy) to return a tensor that owns its storage.\n\"\"\"\n\nimport torch\nfrom sglang.multimodal_gen.runtime.models.decoders import (\n    ltx_2_5_diffusion_decoder as ltx,\n)\n\nKERNEL_SIZE = (3, 7, 7)\n\n# The engine meets a few grids per process; one judge process meets every\n# workload's shape. Past dynamo's default limit of 8 recompiles flex_attention\n# would run uncompiled, materializing the dense S x S scores.\ntorch._dynamo.config.recompile_limit = 1024\ntorch._dynamo.config.accumulated_recompile_limit = 4096\n# The judge rejects a candidate that leaves child processes running, and\n# inductor's parallel compile pool is one; compile in-process instead.\ntorch._inductor.config.compile_threads = 1\n\n\ndef prepare(Q, K, V):\n    batch_size, num_frames, height, width, heads, head_dim = Q.shape\n    seq_len = num_frames * height * width\n    # :451-459\n    query = Q.reshape(batch_size, seq_len, heads, head_dim).transpose(1, 2)\n    key = K.reshape(batch_size, seq_len, heads, head_dim).transpose(1, 2)\n    value = V.reshape(batch_size, seq_len, heads, head_dim).transpose(1, 2)\n    # build_block_mask, :420-423\n    block_mask = ltx._neighborhood_block_mask(\n        num_frames, height, width, KERNEL_SIZE, Q.device\n    )\n    flex_attention = ltx._flex_attention_fn()\n\n    def launch():\n        # :465-467\n        hidden_states = flex_attention(\n            query, key, value, block_mask=block_mask, scale=1.0\n        )\n        # :468-470, heads kept split. The reshape is a view of flex_attention's\n        # own exact-sized output; detach() hands it over as a tensor of its own.\n        return hidden_states.transpose(1, 2).reshape(Q.shape).detach()\n\n    return launch\n\n\ndef run(Q, K, V):\n    return prepare(Q, K, V)()\n"
+      "content": "# Copyright 2026 Co-developed by KDA (Kernel Design Agents)\n\"\"\"SGLang baseline for neighborhood_attention_3d_h32_d64_kt3_ky7_kx7.\n\nSGLang diffusion runtime at commit 684fea8a,\npython/sglang/multimodal_gen/runtime/models/decoders/ltx_2_5_diffusion_decoder.py:\nLTX2VideoVaeNeighborhoodAttention.forward (:425) after project_qkv (:435).\nWhen NATTEN is installed, _na3d() selects its native Q/K/V call with scale=1.0.\nOtherwise (including the pinned capture image), forward takes the\nFlexAttention branch: Q/K/V viewed as (B, heads, S, head_dim) (:449-459), the\nblock mask from build_block_mask (:413) -> _neighborhood_block_mask(T, H, W,\nkernel_size, device) (:170), and _flex_attention_fn() (:104, torch.compile of\nflex_attention, dynamic=False) called with scale=1.0 (:465-467).\n\nAdapter: Q/K/V arrive as project_qkv returns them, [B, T, Y, X, H, D].\nkernel_size is the module's (Kt, Ky, Kx). The decoder builds the block mask\nonce per stage (:771, :785, :835) and passes it to every block, so prepare\nbuilds it and launch runs only the attention. The output keeps the heads\nsplit: :468-470 merges them into channels for to_out, which is not part of\nthis op; that reshape is a view of the flex output, so launch detaches it\n(no copy) to return a tensor that owns its storage.\n\"\"\"\n\nimport torch\nfrom sglang.multimodal_gen.runtime.models.decoders import (\n    ltx_2_5_diffusion_decoder as ltx,\n)\n\nKERNEL_SIZE = (3, 7, 7)\n\n# The engine meets a few grids per process; one judge process meets every\n# workload's shape. Past dynamo's default limit of 8 recompiles flex_attention\n# would run uncompiled, materializing the dense S x S scores.\ntorch._dynamo.config.recompile_limit = 1024\ntorch._dynamo.config.accumulated_recompile_limit = 4096\n# The judge rejects a candidate that leaves child processes running, and\n# inductor's parallel compile pool is one; compile in-process instead.\ntorch._inductor.config.compile_threads = 1\n\n\ndef prepare(Q, K, V):\n    na3d = ltx._na3d()\n    if na3d is not None:\n        # Match the engine branch when the faster optional backend is installed.\n        return lambda: na3d(Q, K, V, kernel_size=KERNEL_SIZE, scale=1.0).detach()\n\n    batch_size, num_frames, height, width, heads, head_dim = Q.shape\n    seq_len = num_frames * height * width\n    # :451-459\n    query = Q.reshape(batch_size, seq_len, heads, head_dim).transpose(1, 2)\n    key = K.reshape(batch_size, seq_len, heads, head_dim).transpose(1, 2)\n    value = V.reshape(batch_size, seq_len, heads, head_dim).transpose(1, 2)\n    # build_block_mask, :420-423\n    block_mask = ltx._neighborhood_block_mask(\n        num_frames, height, width, KERNEL_SIZE, Q.device\n    )\n    flex_attention = ltx._flex_attention_fn()\n\n    def launch():\n        # :465-467\n        hidden_states = flex_attention(\n            query, key, value, block_mask=block_mask, scale=1.0\n        )\n        # :468-470, heads kept split. The reshape is a view of flex_attention's\n        # own exact-sized output; detach() hands it over as a tensor of its own.\n        return hidden_states.transpose(1, 2).reshape(Q.shape).detach()\n\n    return launch\n\n\ndef run(Q, K, V):\n    return prepare(Q, K, V)()\n"
     }
   ]
 }
diff --git a/solutions/neighborhood_attention/sglang_neighborhood_attention_3d_h4_d64_kt11_ky11_kx11.json b/solutions/neighborhood_attention/sglang_neighborhood_attention_3d_h4_d64_kt11_ky11_kx11.json
index e9f99086b9e878fd32b8d305fbce77d23b915e90..72474f8e3c46f93d057eb62a80f092fd86c28912 100644
--- a/solutions/neighborhood_attention/sglang_neighborhood_attention_3d_h4_d64_kt11_ky11_kx11.json
+++ b/solutions/neighborhood_attention/sglang_neighborhood_attention_3d_h4_d64_kt11_ky11_kx11.json
@@ -17,7 +17,7 @@
   "sources": [
     {
       "path": "main.py",
-      "content": "# Copyright 2026 Co-developed by KDA (Kernel Design Agents)\n\"\"\"SGLang baseline for neighborhood_attention_3d_h4_d64_kt11_ky11_kx11.\n\nSGLang diffusion runtime at commit 684fea8a,\npython/sglang/multimodal_gen/runtime/models/decoders/ltx_2_5_diffusion_decoder.py:\nLTX2VideoVaeNeighborhoodAttention.forward (:425) after project_qkv (:435).\nNATTEN is absent from the image, so _na3d() (:49) is None and forward takes the\nFlexAttention branch: Q/K/V viewed as (B, heads, S, head_dim) (:449-459), the\nblock mask from build_block_mask (:413) -> _neighborhood_block_mask(T, H, W,\nkernel_size, device) (:170), and _flex_attention_fn() (:104, torch.compile of\nflex_attention, dynamic=False) called with scale=1.0 (:465-467).\n\nAdapter: Q/K/V arrive as project_qkv returns them, [B, T, Y, X, H, D].\nkernel_size is the module's (Kt, Ky, Kx). The decoder builds the block mask\nonce per stage (:771, :785, :835) and passes it to every block, so prepare\nbuilds it and launch runs only the attention. The output keeps the heads\nsplit: :468-470 merges them into channels for to_out, which is not part of\nthis op; that reshape is a view of the flex output, so launch detaches it\n(no copy) to return a tensor that owns its storage.\n\"\"\"\n\nimport torch\nfrom sglang.multimodal_gen.runtime.models.decoders import (\n    ltx_2_5_diffusion_decoder as ltx,\n)\n\nKERNEL_SIZE = (11, 11, 11)\n\n# The engine meets a few grids per process; one judge process meets every\n# workload's shape. Past dynamo's default limit of 8 recompiles flex_attention\n# would run uncompiled, materializing the dense S x S scores.\ntorch._dynamo.config.recompile_limit = 1024\ntorch._dynamo.config.accumulated_recompile_limit = 4096\n# The judge rejects a candidate that leaves child processes running, and\n# inductor's parallel compile pool is one; compile in-process instead.\ntorch._inductor.config.compile_threads = 1\n\n\ndef prepare(Q, K, V):\n    batch_size, num_frames, height, width, heads, head_dim = Q.shape\n    seq_len = num_frames * height * width\n    # :451-459\n    query = Q.reshape(batch_size, seq_len, heads, head_dim).transpose(1, 2)\n    key = K.reshape(batch_size, seq_len, heads, head_dim).transpose(1, 2)\n    value = V.reshape(batch_size, seq_len, heads, head_dim).transpose(1, 2)\n    # build_block_mask, :420-423\n    block_mask = ltx._neighborhood_block_mask(\n        num_frames, height, width, KERNEL_SIZE, Q.device\n    )\n    flex_attention = ltx._flex_attention_fn()\n\n    def launch():\n        # :465-467\n        hidden_states = flex_attention(\n            query, key, value, block_mask=block_mask, scale=1.0\n        )\n        # :468-470, heads kept split. The reshape is a view of flex_attention's\n        # own exact-sized output; detach() hands it over as a tensor of its own.\n        return hidden_states.transpose(1, 2).reshape(Q.shape).detach()\n\n    return launch\n\n\ndef run(Q, K, V):\n    return prepare(Q, K, V)()\n"
+      "content": "# Copyright 2026 Co-developed by KDA (Kernel Design Agents)\n\"\"\"SGLang baseline for neighborhood_attention_3d_h4_d64_kt11_ky11_kx11.\n\nSGLang diffusion runtime at commit 684fea8a,\npython/sglang/multimodal_gen/runtime/models/decoders/ltx_2_5_diffusion_decoder.py:\nLTX2VideoVaeNeighborhoodAttention.forward (:425) after project_qkv (:435).\nWhen NATTEN is installed, _na3d() selects its native Q/K/V call with scale=1.0.\nOtherwise (including the pinned capture image), forward takes the\nFlexAttention branch: Q/K/V viewed as (B, heads, S, head_dim) (:449-459), the\nblock mask from build_block_mask (:413) -> _neighborhood_block_mask(T, H, W,\nkernel_size, device) (:170), and _flex_attention_fn() (:104, torch.compile of\nflex_attention, dynamic=False) called with scale=1.0 (:465-467).\n\nAdapter: Q/K/V arrive as project_qkv returns them, [B, T, Y, X, H, D].\nkernel_size is the module's (Kt, Ky, Kx). The decoder builds the block mask\nonce per stage (:771, :785, :835) and passes it to every block, so prepare\nbuilds it and launch runs only the attention. The output keeps the heads\nsplit: :468-470 merges them into channels for to_out, which is not part of\nthis op; that reshape is a view of the flex output, so launch detaches it\n(no copy) to return a tensor that owns its storage.\n\"\"\"\n\nimport torch\nfrom sglang.multimodal_gen.runtime.models.decoders import (\n    ltx_2_5_diffusion_decoder as ltx,\n)\n\nKERNEL_SIZE = (11, 11, 11)\n\n# The engine meets a few grids per process; one judge process meets every\n# workload's shape. Past dynamo's default limit of 8 recompiles flex_attention\n# would run uncompiled, materializing the dense S x S scores.\ntorch._dynamo.config.recompile_limit = 1024\ntorch._dynamo.config.accumulated_recompile_limit = 4096\n# The judge rejects a candidate that leaves child processes running, and\n# inductor's parallel compile pool is one; compile in-process instead.\ntorch._inductor.config.compile_threads = 1\n\n\ndef prepare(Q, K, V):\n    na3d = ltx._na3d()\n    if na3d is not None:\n        # Match the engine branch when the faster optional backend is installed.\n        return lambda: na3d(Q, K, V, kernel_size=KERNEL_SIZE, scale=1.0).detach()\n\n    batch_size, num_frames, height, width, heads, head_dim = Q.shape\n    seq_len = num_frames * height * width\n    # :451-459\n    query = Q.reshape(batch_size, seq_len, heads, head_dim).transpose(1, 2)\n    key = K.reshape(batch_size, seq_len, heads, head_dim).transpose(1, 2)\n    value = V.reshape(batch_size, seq_len, heads, head_dim).transpose(1, 2)\n    # build_block_mask, :420-423\n    block_mask = ltx._neighborhood_block_mask(\n        num_frames, height, width, KERNEL_SIZE, Q.device\n    )\n    flex_attention = ltx._flex_attention_fn()\n\n    def launch():\n        # :465-467\n        hidden_states = flex_attention(\n            query, key, value, block_mask=block_mask, scale=1.0\n        )\n        # :468-470, heads kept split. The reshape is a view of flex_attention's\n        # own exact-sized output; detach() hands it over as a tensor of its own.\n        return hidden_states.transpose(1, 2).reshape(Q.shape).detach()\n\n    return launch\n\n\ndef run(Q, K, V):\n    return prepare(Q, K, V)()\n"
     }
   ]
 }
diff --git a/solutions/neighborhood_attention/sglang_neighborhood_attention_3d_h8_d64_kt3_ky5_kx5.json b/solutions/neighborhood_attention/sglang_neighborhood_attention_3d_h8_d64_kt3_ky5_kx5.json
index d9434afd793a8666c8d97c704660419033b51f8c..94629ad2e39457e4625a6c1caa4553ce99148797 100644
--- a/solutions/neighborhood_attention/sglang_neighborhood_attention_3d_h8_d64_kt3_ky5_kx5.json
+++ b/solutions/neighborhood_attention/sglang_neighborhood_attention_3d_h8_d64_kt3_ky5_kx5.json
@@ -17,7 +17,7 @@
   "sources": [
     {
       "path": "main.py",
-      "content": "# Copyright 2026 Co-developed by KDA (Kernel Design Agents)\n\"\"\"SGLang baseline for neighborhood_attention_3d_h8_d64_kt3_ky5_kx5.\n\nSGLang diffusion runtime at commit 684fea8a,\npython/sglang/multimodal_gen/runtime/models/decoders/ltx_2_5_diffusion_decoder.py:\nLTX2VideoVaeNeighborhoodAttention.forward (:425) after project_qkv (:435).\nNATTEN is absent from the image, so _na3d() (:49) is None and forward takes the\nFlexAttention branch: Q/K/V viewed as (B, heads, S, head_dim) (:449-459), the\nblock mask from build_block_mask (:413) -> _neighborhood_block_mask(T, H, W,\nkernel_size, device) (:170), and _flex_attention_fn() (:104, torch.compile of\nflex_attention, dynamic=False) called with scale=1.0 (:465-467).\n\nAdapter: Q/K/V arrive as project_qkv returns them, [B, T, Y, X, H, D].\nkernel_size is the module's (Kt, Ky, Kx). The decoder builds the block mask\nonce per stage (:771, :785, :835) and passes it to every block, so prepare\nbuilds it and launch runs only the attention. The output keeps the heads\nsplit: :468-470 merges them into channels for to_out, which is not part of\nthis op; that reshape is a view of the flex output, so launch detaches it\n(no copy) to return a tensor that owns its storage.\n\"\"\"\n\nimport torch\nfrom sglang.multimodal_gen.runtime.models.decoders import (\n    ltx_2_5_diffusion_decoder as ltx,\n)\n\nKERNEL_SIZE = (3, 5, 5)\n\n# The engine meets a few grids per process; one judge process meets every\n# workload's shape. Past dynamo's default limit of 8 recompiles flex_attention\n# would run uncompiled, materializing the dense S x S scores.\ntorch._dynamo.config.recompile_limit = 1024\ntorch._dynamo.config.accumulated_recompile_limit = 4096\n# The judge rejects a candidate that leaves child processes running, and\n# inductor's parallel compile pool is one; compile in-process instead.\ntorch._inductor.config.compile_threads = 1\n\n\ndef prepare(Q, K, V):\n    batch_size, num_frames, height, width, heads, head_dim = Q.shape\n    seq_len = num_frames * height * width\n    # :451-459\n    query = Q.reshape(batch_size, seq_len, heads, head_dim).transpose(1, 2)\n    key = K.reshape(batch_size, seq_len, heads, head_dim).transpose(1, 2)\n    value = V.reshape(batch_size, seq_len, heads, head_dim).transpose(1, 2)\n    # build_block_mask, :420-423\n    block_mask = ltx._neighborhood_block_mask(\n        num_frames, height, width, KERNEL_SIZE, Q.device\n    )\n    flex_attention = ltx._flex_attention_fn()\n\n    def launch():\n        # :465-467\n        hidden_states = flex_attention(\n            query, key, value, block_mask=block_mask, scale=1.0\n        )\n        # :468-470, heads kept split. The reshape is a view of flex_attention's\n        # own exact-sized output; detach() hands it over as a tensor of its own.\n        return hidden_states.transpose(1, 2).reshape(Q.shape).detach()\n\n    return launch\n\n\ndef run(Q, K, V):\n    return prepare(Q, K, V)()\n"
+      "content": "# Copyright 2026 Co-developed by KDA (Kernel Design Agents)\n\"\"\"SGLang baseline for neighborhood_attention_3d_h8_d64_kt3_ky5_kx5.\n\nSGLang diffusion runtime at commit 684fea8a,\npython/sglang/multimodal_gen/runtime/models/decoders/ltx_2_5_diffusion_decoder.py:\nLTX2VideoVaeNeighborhoodAttention.forward (:425) after project_qkv (:435).\nWhen NATTEN is installed, _na3d() selects its native Q/K/V call with scale=1.0.\nOtherwise (including the pinned capture image), forward takes the\nFlexAttention branch: Q/K/V viewed as (B, heads, S, head_dim) (:449-459), the\nblock mask from build_block_mask (:413) -> _neighborhood_block_mask(T, H, W,\nkernel_size, device) (:170), and _flex_attention_fn() (:104, torch.compile of\nflex_attention, dynamic=False) called with scale=1.0 (:465-467).\n\nAdapter: Q/K/V arrive as project_qkv returns them, [B, T, Y, X, H, D].\nkernel_size is the module's (Kt, Ky, Kx). The decoder builds the block mask\nonce per stage (:771, :785, :835) and passes it to every block, so prepare\nbuilds it and launch runs only the attention. The output keeps the heads\nsplit: :468-470 merges them into channels for to_out, which is not part of\nthis op; that reshape is a view of the flex output, so launch detaches it\n(no copy) to return a tensor that owns its storage.\n\"\"\"\n\nimport torch\nfrom sglang.multimodal_gen.runtime.models.decoders import (\n    ltx_2_5_diffusion_decoder as ltx,\n)\n\nKERNEL_SIZE = (3, 5, 5)\n\n# The engine meets a few grids per process; one judge process meets every\n# workload's shape. Past dynamo's default limit of 8 recompiles flex_attention\n# would run uncompiled, materializing the dense S x S scores.\ntorch._dynamo.config.recompile_limit = 1024\ntorch._dynamo.config.accumulated_recompile_limit = 4096\n# The judge rejects a candidate that leaves child processes running, and\n# inductor's parallel compile pool is one; compile in-process instead.\ntorch._inductor.config.compile_threads = 1\n\n\ndef prepare(Q, K, V):\n    na3d = ltx._na3d()\n    if na3d is not None:\n        # Match the engine branch when the faster optional backend is installed.\n        return lambda: na3d(Q, K, V, kernel_size=KERNEL_SIZE, scale=1.0).detach()\n\n    batch_size, num_frames, height, width, heads, head_dim = Q.shape\n    seq_len = num_frames * height * width\n    # :451-459\n    query = Q.reshape(batch_size, seq_len, heads, head_dim).transpose(1, 2)\n    key = K.reshape(batch_size, seq_len, heads, head_dim).transpose(1, 2)\n    value = V.reshape(batch_size, seq_len, heads, head_dim).transpose(1, 2)\n    # build_block_mask, :420-423\n    block_mask = ltx._neighborhood_block_mask(\n        num_frames, height, width, KERNEL_SIZE, Q.device\n    )\n    flex_attention = ltx._flex_attention_fn()\n\n    def launch():\n        # :465-467\n        hidden_states = flex_attention(\n            query, key, value, block_mask=block_mask, scale=1.0\n        )\n        # :468-470, heads kept split. The reshape is a view of flex_attention's\n        # own exact-sized output; detach() hands it over as a tensor of its own.\n        return hidden_states.transpose(1, 2).reshape(Q.shape).detach()\n\n    return launch\n\n\ndef run(Q, K, V):\n    return prepare(Q, K, V)()\n"
     }
   ]
 }
diff --git a/solutions/qsa_attention/fa4_sparse_gqa.json b/solutions/qsa_attention/fa4_sparse_gqa.json
index fee1c8f14de3594239f532adc95cbe30a14ad2cb..1af6feaebc2c5a3d6deda35b4f5deb9dfac7e4b8 100644
--- a/solutions/qsa_attention/fa4_sparse_gqa.json
+++ b/solutions/qsa_attention/fa4_sparse_gqa.json
@@ -3,6 +3,26 @@
   "definition": "qsa_sparse_gqa_decode_qwen38_h24_kv2_d256_topk512_c4",
   "author": "inference-kernels",
   "description": "FlashAttention-4 with a Triton adapter that gathers selected four-token blocks and the incomplete tail into a compact KV sequence. Upstream: https://github.com/Dao-AILab/flash-attention/tree/e9d8944c855489e03c66262d07ba4c81d9d8dd31 (BSD-3-Clause). All input adaptation is part of the solution call.",
-  "spec": {"language": "triton", "target_hardware": ["NVIDIA_B200"], "entry_point": "main.py::run", "dependencies": ["torch>=2.11", "triton>=3.6", "flash-attn-4==4.0.0b35", "nvidia-cutlass-dsl==4.7.1", "quack-kernels==0.6.5"], "destination_passing_style": false},
-  "sources": [{"path": "main.py", "content": "import torch\nimport triton as tr\nimport triton.language as tl\nfrom flash_attn.cute.interface import flash_attn_varlen_func\n\n@tr.jit\ndef gather(K, V, Table, Blocks, Context, Counts, OutK, OutV, P: tl.constexpr, Columns: tl.constexpr, Capacity: tl.constexpr):\n    b = tl.program_id(0)\n    slots = tl.program_id(1) * 16 + tl.arange(0, 16)\n    channel = tl.arange(0, 512)\n    count = tl.load(Counts + b)\n    context = tl.load(Context + b)\n    length = count * 4 + context % 4\n    block = tl.load(Blocks + b * 512 + slots // 4, (slots < count * 4) & (slots < Capacity), other=0)\n    logical = tl.where(slots < count * 4, block * 4 + slots % 4, context - context % 4 + slots - count * 4)\n    valid = (slots < length) & (slots < Capacity)\n    page = tl.load(Table + b * Columns + logical // P, valid, other=0)\n    source = ((page * P + logical % P)[:, None] * 512 + channel[None, :])\n    key = tl.load(K + source, valid[:, None], other=0)\n    value = tl.load(V + source, valid[:, None], other=0)\n    target = ((b * Capacity + slots)[:, None] * 512 + channel[None, :])\n    tl.store(OutK + target, key, (slots < Capacity)[:, None])\n    tl.store(OutV + target, value, (slots < Capacity)[:, None])\n\ndef run(Q, K_pages, V_pages, page_table, block_ids, context_lens):\n    batch, capacity = Q.shape[0], 2052\n    counts = (block_ids >= 0).sum(-1).to(torch.int32)\n    lengths = counts * 4 + context_lens % 4\n    keys = torch.empty((batch, capacity, 2, 256), device=Q.device, dtype=Q.dtype)\n    values = torch.empty_like(keys)\n    gather[(batch, tr.cdiv(capacity, 16))](K_pages, V_pages, page_table, block_ids, context_lens, counts, keys, values, K_pages.shape[1], page_table.shape[1], capacity, num_warps=8)\n    used_q = torch.ones((batch,), dtype=torch.int32, device=Q.device)\n    output = flash_attn_varlen_func(Q[:, None], keys, values, seqused_q=used_q, seqused_k=lengths, max_seqlen_q=1, max_seqlen_k=capacity, softmax_scale=0.0625, num_splits=0)[0]\n    return output[:, 0]\n"}]
+  "spec": {
+    "language": "triton",
+    "target_hardware": [
+      "NVIDIA_B200",
+      "NVIDIA_B300"
+    ],
+    "entry_point": "main.py::run",
+    "dependencies": [
+      "torch>=2.11",
+      "triton>=3.6",
+      "flash-attn-4==4.0.0b35",
+      "nvidia-cutlass-dsl[cu13]==4.8.0",
+      "quack-kernels==0.6.5"
+    ],
+    "destination_passing_style": false
+  },
+  "sources": [
+    {
+      "path": "main.py",
+      "content": "import torch\nimport triton as tr\nimport triton.language as tl\nfrom flash_attn.cute.interface import flash_attn_varlen_func\n\n@tr.jit\ndef gather(K, V, Table, Blocks, Context, Counts, OutK, OutV, P: tl.constexpr, Columns: tl.constexpr, Capacity: tl.constexpr):\n    b = tl.program_id(0)\n    slots = tl.program_id(1) * 16 + tl.arange(0, 16)\n    channel = tl.arange(0, 512)\n    count = tl.load(Counts + b)\n    context = tl.load(Context + b)\n    length = count * 4 + context % 4\n    block = tl.load(Blocks + b * 512 + slots // 4, (slots < count * 4) & (slots < Capacity), other=0)\n    logical = tl.where(slots < count * 4, block * 4 + slots % 4, context - context % 4 + slots - count * 4)\n    valid = (slots < length) & (slots < Capacity)\n    page = tl.load(Table + b * Columns + logical // P, valid, other=0)\n    source = ((page * P + logical % P)[:, None] * 512 + channel[None, :])\n    key = tl.load(K + source, valid[:, None], other=0)\n    value = tl.load(V + source, valid[:, None], other=0)\n    target = ((b * Capacity + slots)[:, None] * 512 + channel[None, :])\n    tl.store(OutK + target, key, (slots < Capacity)[:, None])\n    tl.store(OutV + target, value, (slots < Capacity)[:, None])\n\ndef run(Q, K_pages, V_pages, page_table, block_ids, context_lens):\n    batch, capacity = Q.shape[0], 2052\n    counts = (block_ids >= 0).sum(-1).to(torch.int32)\n    lengths = counts * 4 + context_lens % 4\n    keys = torch.empty((batch, capacity, 2, 256), device=Q.device, dtype=Q.dtype)\n    values = torch.empty_like(keys)\n    gather[(batch, tr.cdiv(capacity, 16))](K_pages, V_pages, page_table, block_ids, context_lens, counts, keys, values, K_pages.shape[1], page_table.shape[1], capacity, num_warps=8)\n    used_q = torch.ones((batch,), dtype=torch.int32, device=Q.device)\n    output = flash_attn_varlen_func(Q[:, None], keys, values, seqused_q=used_q, seqused_k=lengths, max_seqlen_q=1, max_seqlen_k=capacity, softmax_scale=0.0625, num_splits=0)[0]\n    return output[:, 0]\n"
+    }
+  ]
 }
diff --git a/solutions/qsa_attention/trtllm_sparse_gqa.json b/solutions/qsa_attention/trtllm_sparse_gqa.json
new file mode 100644
index 0000000000000000000000000000000000000000..246b005f8ffe1523775fbaa696920aedb1bb647e
--- /dev/null
+++ b/solutions/qsa_attention/trtllm_sparse_gqa.json
@@ -0,0 +1,26 @@
+{
+  "name": "trtllm_sparse_gqa",
+  "definition": "qsa_sparse_gqa_decode_qwen38_h24_kv2_d256_topk512_c4",
+  "author": "inference-kernels",
+  "description": "SGLang current TRT-LLM sparse GQA decode path with paged-cache preparation. Uses the same native leaf as the serving engine; the dataset still requires compact-cache, page-map and post-KV-write adapters. B300 graph measurements favor this path over sparse-gather FlashAttention-4.",
+  "spec": {
+    "language": "python",
+    "target_hardware": [
+      "NVIDIA_B200",
+      "NVIDIA_B300"
+    ],
+    "entry_point": "main.py::run",
+    "dependencies": [
+      "torch>=2.14.1",
+      "sglang @ git+https://github.com/sgl-project/sglang.git@0025f9394421451aa09ec192a4a6e7928e14736b#subdirectory=python",
+      "flashinfer-python==0.7.2"
+    ],
+    "destination_passing_style": false
+  },
+  "sources": [
+    {
+      "path": "main.py",
+      "content": "# Copyright 2026 Co-developed by KDA (Kernel Design Agents)\n\"\"\"SGLang baseline for qsa_sparse_gqa_decode_qwen38_h24_kv2_d256_topk512_c4.\n\nSGLang 684fea8a, ``QwenSparseAttnBackend.forward_decode``\n(sglang/srt/layers/attention/qwen_sparse_attn_backend.py:1817) with a bf16 MHA\npool on SM100: ``_try_fused_kv_attention`` (:1363) ->\n``_forward_trtllm_sparse(new_kv=...)`` (:1682), which runs\n\n- ``fused_kv_prepare(...)`` (call :1730; qsa/fused_kv.py:131), then\n- ``flashinfer.decode.trtllm_batch_decode_with_kv_cache(...)`` (call :1804),\n  with ``bmm1_scale = head_dim**-0.5`` (models/qwen3_5.py:1269).\n\nThe backend needs server state, so the two calls get the arguments that method\npasses, and its cached scratch, tables, workspace and counters\n(:1646-1680, :1788-1803) are set up in ``prepare``. Adapter:\n\n- ``req_to_token`` is built from ``page_table`` at a fixed width, as SGLang's\n  pool has one (``context_len + 4``, mem_cache/kv_cache_configurator.py:1562;\n  ``fused_kv_prepare`` specializes on its row stride);\n- ``loc`` is the current token's slot and its k/v are re-read from the cache:\n  the capture is taken after the current-token KV write, so the kernel's\n  write-back stores the values already there;\n- SGLang never places a token in slot 0 (mem_cache/allocator/paged.py:396) and\n  ``fused_kv_prepare`` treats ``loc == 0`` as a padding row, so when a current\n  token sits in slot 0 the pages are shifted by one behind an empty page 0.\n\"\"\"\n\nimport torch\nfrom flashinfer.decode import trtllm_batch_decode_with_kv_cache\nfrom flashinfer.utils import get_trtllm_gen_multi_ctas_kv_counter_bytes\nfrom sglang.srt.layers.attention.qsa.fused_kv import fused_kv_prepare\n\nPAGE = 64  # _TRTLLM_SPARSE_PAGE_SIZE (qwen_sparse_attn_backend.py:61)\nRATIO = 4\nTABLE_WIDTH = 262144 + 4  # a 256K context_len + 4\n_WORKSPACES = {}\n_COUNTERS = {}\n\n\ndef prepare(Q, K_pages, V_pages, page_table, block_ids, context_lens):\n    batch, heads, dim = Q.shape\n    page_size, kv_heads = K_pages.shape[1:3]\n    device = Q.device\n    rows = torch.arange(batch, device=device)\n    tokens = torch.arange(page_table.shape[1] * page_size, device=device)\n    slots = page_table.long()[:, tokens // page_size] * page_size + tokens % page_size\n    shift = bool((slots[rows, context_lens.long() - 1] == 0).any())\n    if shift:\n        slots += page_size\n    req_to_token = torch.zeros(\n        batch, max(TABLE_WIDTH, slots.shape[1]), dtype=torch.int32, device=device\n    )\n    req_to_token[:, : slots.shape[1]] = slots\n    loc = slots[rows, context_lens.long() - 1]\n    query_positions = context_lens - 1\n\n    # _forward_trtllm_sparse (:1696-1703, :1646-1680)\n    topk = block_ids.shape[1] * RATIO + RATIO - 1\n    pages_per_row = (topk + PAGE - 1) // PAGE\n    stride = pages_per_row * PAGE\n    counts = torch.empty(batch, dtype=torch.int32, device=device)\n    packed_k = torch.zeros(batch * stride, kv_heads, dim, dtype=Q.dtype, device=device)\n    packed_v = torch.zeros_like(packed_k)\n    kv_cache = tuple(\n        x.view(-1, PAGE, kv_heads, dim).permute(0, 2, 1, 3)\n        for x in (packed_k, packed_v)\n    )\n    block_tables = (\n        rows.int()[:, None] * pages_per_row\n        + torch.arange(pages_per_row, dtype=torch.int32, device=device)[None, :]\n    ).contiguous()\n    if device not in _WORKSPACES:\n        _WORKSPACES[device] = torch.zeros(\n            128 * 1024 * 1024, dtype=torch.uint8, device=device\n        )\n    key = (batch, heads, device)\n    if key not in _COUNTERS:\n        sms = torch.cuda.get_device_properties(device).multi_processor_count\n        size = get_trtllm_gen_multi_ctas_kv_counter_bytes(batch, heads, sms)\n        _COUNTERS[key] = torch.zeros(size, dtype=torch.uint8, device=device)\n\n    def launch():\n        k_buffer = K_pages.view(-1, kv_heads, dim)\n        v_buffer = V_pages.view(-1, kv_heads, dim)\n        if shift:\n            empty = k_buffer.new_zeros(page_size, kv_heads, dim)\n            k_buffer = torch.cat([empty, k_buffer])\n            v_buffer = torch.cat([empty, v_buffer])\n        fused_kv_prepare(\n            k_buffer,\n            v_buffer,\n            k_buffer.index_select(0, loc),\n            v_buffer.index_select(0, loc),\n            loc,\n            req_to_token,\n            rows,\n            block_ids,\n            context_lens,\n            counts,\n            packed_k,\n            packed_v,\n            1,\n            compress_ratio=RATIO,\n            chain_positions=True,\n            query_positions=query_positions,\n            visible_page_size=PAGE,\n        )\n        return trtllm_batch_decode_with_kv_cache(\n            query=Q,\n            kv_cache=kv_cache,\n            workspace_buffer=_WORKSPACES[device],\n            block_tables=block_tables,\n            seq_lens=counts,\n            max_seq_len=stride,\n            bmm1_scale=dim**-0.5,\n            bmm2_scale=1.0,\n            multi_ctas_kv_counter_buffer=_COUNTERS[key],\n        )\n\n    return launch\n\n\ndef run(Q, K_pages, V_pages, page_table, block_ids, context_lens):\n    return prepare(Q, K_pages, V_pages, page_table, block_ids, context_lens)()\n"
+    }
+  ]
+}
diff --git a/solutions/qsa_index/sglang_tilelang_index.json b/solutions/qsa_index/sglang_tilelang_index.json
index 513d77858297748ccb20bd4703d095dc0ca66ca1..df86a8c33c1ce65d5e42ecbeaa576a503d764bb0 100644
--- a/solutions/qsa_index/sglang_tilelang_index.json
+++ b/solutions/qsa_index/sglang_tilelang_index.json
@@ -2,8 +2,29 @@
   "name": "sglang_tilelang_index",
   "definition": "qsa_index_topk_decode_qwen38_h4_d128_topk512_c4",
   "author": "inference-kernels",
-  "description": "SGLang TileLang paged QSA index scoring with exact-threshold Top-512 and ordered Triton compaction. Preserves lower-ID ties and ascending output without sorting the whole context. Scoring adapted from https://github.com/sgl-project/sglang/blob/9d394dfbd755759d3add89cfd0bc86d59b31f78c/python/sglang/srt/layers/attention/qsa/mqa.py (Apache-2.0).",
-  "spec": {"language": "triton", "target_hardware": ["NVIDIA_B200"], "entry_point": "main.py::run", "dependencies": ["torch>=2.11", "triton>=3.6", "tilelang==0.1.15"], "destination_passing_style": false},
-  "sources": [{"path": "main.py", "content": "# SPDX-License-Identifier: Apache-2.0\nimport torch\nimport tilelang\nfrom tilelang import language as T\nfrom .selection import select\n\n@tilelang.jit\ndef scoring(page_size: int):\n    batch, pages, columns, width = T.dynamic('batch'), T.dynamic('pages'), T.dynamic('columns'), T.dynamic('width')\n    subpages = 64 // page_size\n    @T.prim_func\n    def kernel(Q: T.Tensor([batch, 8, 128], T.bfloat16), K: T.Tensor([pages, page_size, 1, 128], T.bfloat16), Table: T.Tensor([batch, columns], T.int32), Length: T.Tensor([batch], T.int32), Scores: T.Tensor([batch, width], T.float32)):\n        with T.Kernel(batch, T.ceildiv(columns, subpages), threads=128) as (b, group):\n            q = T.alloc_shared([8, 128], T.bfloat16)\n            k = T.alloc_shared([64, 128], T.bfloat16)\n            dots = T.alloc_fragment([64, 8], T.float32)\n            summed = T.alloc_fragment([64], T.float32)\n            T.copy(Q[b, :, :], q)\n            if group * 64 < Length[b]:\n                T.clear(k)\n                for sp in range(subpages):\n                    if (group * subpages + sp) * page_size < Length[b]:\n                        T.copy(K[Table[b, group * subpages + sp], :, 0, :], k[sp * page_size:(sp + 1) * page_size, :])\n                T.gemm(k, q, dots, transpose_B=True, clear_accum=True, policy=T.GemmWarpPolicy.FullCol)\n                for token, head in T.Parallel(64, 8):\n                    dots[token, head] = T.max(dots[token, head], 0.0)\n                T.reduce_sum(dots, summed, dim=1, clear=True)\n                for token in T.Parallel(64):\n                    if group * 64 + token < Length[b]:\n                        Scores[b, group * 64 + token] = summed[token] / 11.313708498984761\n    return kernel\n\ndef run(Q_idx, Kc_pages, page_table, num_complete_blocks):\n    batch = Q_idx.shape[0]\n    width = max(512, page_table.shape[1] * Kc_pages.shape[1])\n    query = torch.cat((Q_idx, torch.zeros_like(Q_idx)), dim=1)\n    scores = torch.full((batch, width), -torch.inf, device=Q_idx.device, dtype=torch.float32)\n    scoring(Kc_pages.shape[1])(query, Kc_pages, page_table, num_complete_blocks, scores)\n    return select(scores, num_complete_blocks)\n"},
-    {"path": "selection.py", "content": "import torch\nimport triton as tr\nimport triton.language as tl\n\n@tr.jit\ndef count(Scores, Lengths, Threshold, Counts, N: tl.constexpr, C: tl.constexpr):\n    b, block = tl.program_id(0), tl.program_id(1)\n    positions = block * 1024 + tl.arange(0, 1024)\n    length = tl.load(Lengths + b)\n    threshold = tl.load(Threshold + b)\n    values = tl.load(Scores + b * N + positions, positions < N, other=-float('inf'))\n    valid = (positions < N) & (positions < length)\n    tl.store(Counts + (b * C + block) * 2, tl.sum((valid & (values > threshold)).to(tl.int32), 0))\n    tl.store(Counts + (b * C + block) * 2 + 1, tl.sum((valid & (values == threshold)).to(tl.int32), 0))\n\n@tr.jit\ndef compact(Scores, Lengths, Threshold, Counts, Output, N: tl.constexpr, C: tl.constexpr, CC: tl.constexpr):\n    b, block = tl.program_id(0), tl.program_id(1)\n    columns = tl.arange(0, CC)\n    greater = tl.load(Counts + (b * C + columns) * 2, columns < C, other=0)\n    equal = tl.load(Counts + (b * C + columns) * 2 + 1, columns < C, other=0)\n    gap = tl.maximum(0, 512 - tl.sum(greater, 0))\n    prior_equal = tl.sum(tl.where(columns < block, equal, 0), 0)\n    prior = tl.sum(tl.where(columns < block, greater, 0), 0) + tl.minimum(prior_equal, gap)\n    positions = block * 1024 + tl.arange(0, 1024)\n    length = tl.load(Lengths + b)\n    threshold = tl.load(Threshold + b)\n    values = tl.load(Scores + b * N + positions, positions < N, other=-float('inf'))\n    valid = (positions < N) & (positions < length)\n    ties = valid & (values == threshold)\n    accepted = valid & ((values > threshold) | (ties & (tl.cumsum(ties.to(tl.int32), 0) + prior_equal <= gap)))\n    offsets = prior + tl.cumsum(accepted.to(tl.int32), 0) - 1\n    tl.store(Output + b * 512 + offsets, positions, accepted & (offsets < 512))\n\ndef select(scores, lengths):\n    threshold = torch.topk(scores, 512, dim=-1, sorted=False).values.amin(-1)\n    batch, width = scores.shape\n    columns = tr.cdiv(width, 1024)\n    counts = torch.empty((batch, columns, 2), device=scores.device, dtype=torch.int32)\n    output = torch.full((batch, 512), -1, device=scores.device, dtype=torch.int32)\n    count[(batch, columns)](scores, lengths, threshold, counts, width, columns)\n    compact[(batch, columns)](scores, lengths, threshold, counts, output, width, columns, tr.next_power_of_2(columns))\n    return output\n"}]
+  "description": "Maintained SGLang paged scoring and native fast Top-512 threshold discovery, followed by exact lower-ID tie handling and ascending Triton compaction. A score-free path handles capacities at most 512. Native unordered tie choices affect only threshold discovery, not the final selected set.",
+  "spec": {
+    "language": "triton",
+    "target_hardware": [
+      "NVIDIA_B200",
+      "NVIDIA_B300"
+    ],
+    "entry_point": "main.py::run",
+    "dependencies": [
+      "sglang @ git+https://github.com/sgl-project/sglang.git@0025f9394421451aa09ec192a4a6e7928e14736b#subdirectory=python",
+      "triton>=3.8",
+      "tilelang==0.1.12"
+    ],
+    "destination_passing_style": false
+  },
+  "sources": [
+    {
+      "path": "main.py",
+      "content": "# SPDX-License-Identifier: Apache-2.0\n\"\"\"Use maintained SGLang scoring and stable, exact selected-set compaction.\n\nThe engine scoring source is unchanged between capture commit 684fea8a and\nSGLang 0.5.22 / audit commit 0025f939. For capacities at most TOPK every valid\nblock is selected, so no scores are needed.\n\"\"\"\nfrom sglang.srt.layers.attention.qsa.mqa import qsa_mqa_decode\nfrom .selection import select, short_context\n\n\ndef run(Q_idx, Kc_pages, page_table, num_complete_blocks):\n    capacity = page_table.shape[1] * Kc_pages.shape[1]\n    if capacity <= 512:\n        return short_context(num_complete_blocks)\n    scores = qsa_mqa_decode(\n        Q_idx, Kc_pages, page_table, num_complete_blocks,\n        max(512, capacity), min_scored_len=0,\n    )\n    return select(scores, num_complete_blocks)\n"
+    },
+    {
+      "path": "selection.py",
+      "content": "import torch\nimport triton as tr\nimport triton.language as tl\nfrom sglang.kernels.ops.attention.fast_topk import fast_topk\n\n@tr.jit\ndef count(Scores, Lengths, Threshold, Counts, N: tl.constexpr, C: tl.constexpr):\n    b, block = tl.program_id(0), tl.program_id(1)\n    positions = block * 1024 + tl.arange(0, 1024)\n    length = tl.load(Lengths + b)\n    threshold = tl.load(Threshold + b)\n    values = tl.load(Scores + b * N + positions, positions < N, other=-float('inf'))\n    valid = (positions < N) & (positions < length)\n    tl.store(Counts + (b * C + block) * 2, tl.sum((valid & (values > threshold)).to(tl.int32), 0))\n    tl.store(Counts + (b * C + block) * 2 + 1, tl.sum((valid & (values == threshold)).to(tl.int32), 0))\n\n@tr.jit\ndef compact(Scores, Lengths, Threshold, Counts, Output, N: tl.constexpr, C: tl.constexpr, CC: tl.constexpr):\n    b, block = tl.program_id(0), tl.program_id(1)\n    columns = tl.arange(0, CC)\n    greater = tl.load(Counts + (b * C + columns) * 2, columns < C, other=0)\n    equal = tl.load(Counts + (b * C + columns) * 2 + 1, columns < C, other=0)\n    gap = tl.maximum(0, 512 - tl.sum(greater, 0))\n    prior_equal = tl.sum(tl.where(columns < block, equal, 0), 0)\n    prior = tl.sum(tl.where(columns < block, greater, 0), 0) + tl.minimum(prior_equal, gap)\n    positions = block * 1024 + tl.arange(0, 1024)\n    length = tl.load(Lengths + b)\n    threshold = tl.load(Threshold + b)\n    values = tl.load(Scores + b * N + positions, positions < N, other=-float('inf'))\n    valid = (positions < N) & (positions < length)\n    ties = valid & (values == threshold)\n    accepted = valid & ((values > threshold) | (ties & (tl.cumsum(ties.to(tl.int32), 0) + prior_equal <= gap)))\n    offsets = prior + tl.cumsum(accepted.to(tl.int32), 0) - 1\n    tl.store(Output + b * 512 + offsets, positions, accepted & (offsets < 512))\n\n@tr.jit\ndef kth_threshold(Scores, Ids, Threshold, N: tl.constexpr):\n    b = tl.program_id(0)\n    positions = tl.arange(0, 512)\n    ids = tl.load(Ids + b * 512 + positions)\n    values = tl.load(Scores + b * N + ids, ids >= 0, other=-float('inf'))\n    tl.store(Threshold + b, tl.min(values, 0))\n\ndef select(scores, lengths):\n    # Native selection supplies only the threshold; its unordered tie choices\n    # are discarded. Compaction below restores the exact lower-ID tie rule.\n    ids = fast_topk(scores, lengths, topk=512)\n    threshold = torch.empty((scores.shape[0],), device=scores.device, dtype=torch.float32)\n    kth_threshold[(scores.shape[0],)](scores, ids, threshold, scores.shape[1])\n    batch, width = scores.shape\n    columns = tr.cdiv(width, 1024)\n    counts = torch.empty((batch, columns, 2), device=scores.device, dtype=torch.int32)\n    output = torch.full((batch, 512), -1, device=scores.device, dtype=torch.int32)\n    count[(batch, columns)](scores, lengths, threshold, counts, width, columns)\n    compact[(batch, columns)](scores, lengths, threshold, counts, output, width, columns, tr.next_power_of_2(columns))\n    return output\n\n@tr.jit\ndef fill_short(Lengths, Output):\n    b = tl.program_id(0)\n    ids = tl.arange(0, 512)\n    length = tl.load(Lengths + b)\n    tl.store(Output + b * 512 + ids, tl.where(ids < length, ids, -1))\n\ndef short_context(lengths):\n    output = torch.empty((lengths.shape[0], 512), device=lengths.device, dtype=torch.int32)\n    fill_short[(lengths.shape[0],)](lengths, output)\n    return output\n"
+    }
+  ]
 }
diff --git a/solutions/sparse_mla/flashmla_prefill_k128.json b/solutions/sparse_mla/flashmla_prefill_k128.json
index a443b0fd8f001c3dbe6bb6eb9d5719bfeaed7bfc..f90742066b41e67a474ab2d79489f271f28ee793 100644
--- a/solutions/sparse_mla/flashmla_prefill_k128.json
+++ b/solutions/sparse_mla/flashmla_prefill_k128.json
@@ -3,6 +3,23 @@
   "definition": "sparse_mla_prefill_h64_d512_k128",
   "author": "inference-kernels",
   "description": "FlashMLA Blackwell BF16 sparse prefill with 128 index slots, per-query sparse lengths and attention sinks. Upstream: https://github.com/deepseek-ai/FlashMLA/tree/0f11e178da1f67becb087a324b400854931ec3e3 (MIT).",
-  "spec": {"language": "python", "target_hardware": ["NVIDIA_B200"], "entry_point": "main.py::run", "dependencies": ["torch>=2.11", "flash-mla @ git+https://github.com/deepseek-ai/FlashMLA.git@0f11e178da1f67becb087a324b400854931ec3e3"], "destination_passing_style": false},
-  "sources": [{"path": "main.py", "content": "from flash_mla import flash_mla_sparse_fwd\n\ndef run(Q, KV, indices, topk_length, attn_sink, sm_scale):\n    return flash_mla_sparse_fwd(\n        Q, KV, indices, sm_scale, d_v=512,\n        attn_sink=attn_sink, topk_length=topk_length,\n    )[0]\n"}]
+  "spec": {
+    "language": "python",
+    "target_hardware": [
+      "NVIDIA_B200",
+      "NVIDIA_B300"
+    ],
+    "entry_point": "main.py::run",
+    "dependencies": [
+      "torch>=2.11",
+      "flash-mla @ git+https://github.com/deepseek-ai/FlashMLA.git@0f11e178da1f67becb087a324b400854931ec3e3"
+    ],
+    "destination_passing_style": false
+  },
+  "sources": [
+    {
+      "path": "main.py",
+      "content": "from flash_mla import flash_mla_sparse_fwd\n\ndef run(Q, KV, indices, topk_length, attn_sink, sm_scale):\n    return flash_mla_sparse_fwd(\n        Q, KV, indices, sm_scale, d_v=512,\n        attn_sink=attn_sink, topk_length=topk_length,\n    )[0]\n"
+    }
+  ]
 }
diff --git a/solutions/sparse_mla/flashmla_prefill_k640.json b/solutions/sparse_mla/flashmla_prefill_k640.json
index cabcb2ae2d2554b06a004d80ab804d6444abcd94..c735b0559d8d21a93315e6b891142ec7a9a74cd1 100644
--- a/solutions/sparse_mla/flashmla_prefill_k640.json
+++ b/solutions/sparse_mla/flashmla_prefill_k640.json
@@ -3,6 +3,23 @@
   "definition": "sparse_mla_prefill_h64_d512_k640",
   "author": "inference-kernels",
   "description": "FlashMLA Blackwell BF16 sparse prefill with 640 index slots, per-query sparse lengths and attention sinks. Upstream: https://github.com/deepseek-ai/FlashMLA/tree/0f11e178da1f67becb087a324b400854931ec3e3 (MIT).",
-  "spec": {"language": "python", "target_hardware": ["NVIDIA_B200"], "entry_point": "main.py::run", "dependencies": ["torch>=2.11", "flash-mla @ git+https://github.com/deepseek-ai/FlashMLA.git@0f11e178da1f67becb087a324b400854931ec3e3"], "destination_passing_style": false},
-  "sources": [{"path": "main.py", "content": "from flash_mla import flash_mla_sparse_fwd\n\ndef run(Q, KV, indices, topk_length, attn_sink, sm_scale):\n    return flash_mla_sparse_fwd(\n        Q, KV, indices, sm_scale, d_v=512,\n        attn_sink=attn_sink, topk_length=topk_length,\n    )[0]\n"}]
+  "spec": {
+    "language": "python",
+    "target_hardware": [
+      "NVIDIA_B200",
+      "NVIDIA_B300"
+    ],
+    "entry_point": "main.py::run",
+    "dependencies": [
+      "torch>=2.11",
+      "flash-mla @ git+https://github.com/deepseek-ai/FlashMLA.git@0f11e178da1f67becb087a324b400854931ec3e3"
+    ],
+    "destination_passing_style": false
+  },
+  "sources": [
+    {
+      "path": "main.py",
+      "content": "from flash_mla import flash_mla_sparse_fwd\n\ndef run(Q, KV, indices, topk_length, attn_sink, sm_scale):\n    return flash_mla_sparse_fwd(\n        Q, KV, indices, sm_scale, d_v=512,\n        attn_sink=attn_sink, topk_length=topk_length,\n    )[0]\n"
+    }
+  ]
 }
diff --git a/tasks/gdn_decode_qk4_v8_d128_k_last.json b/tasks/gdn_decode_qk4_v8_d128_k_last.json
index 6d93c7e389ea26558b880c178412cce77103fd2a..a524e455c53e66d81972ab8dc27d2dbe30ca108b 100644
--- a/tasks/gdn_decode_qk4_v8_d128_k_last.json
+++ b/tasks/gdn_decode_qk4_v8_d128_k_last.json
@@ -3,7 +3,7 @@
   "workloads": [
     "workloads/gdn/gdn_decode_qk4_v8_d128_k_last.jsonl"
   ],
-  "baseline": "solutions/gdn/flashinfer_wrapper_9b7f1e.json",
+  "baseline": "solutions/gdn/flashinfer_gdn_decode.json",
   "tolerance": {
     "atol": 0.01,
     "rtol": 0.01,
diff --git a/tasks/gdn_prefill_qk4_v8_d128_k_last.json b/tasks/gdn_prefill_qk4_v8_d128_k_last.json
index 06e6f66abfa0bbd31e9cd43f309ec4cf761d5a61..ae1c6b3423175a45381e66771018562efa70736a 100644
--- a/tasks/gdn_prefill_qk4_v8_d128_k_last.json
+++ b/tasks/gdn_prefill_qk4_v8_d128_k_last.json
@@ -3,7 +3,7 @@
   "workloads": [
     "workloads/gdn/gdn_prefill_qk4_v8_d128_k_last.jsonl"
   ],
-  "baseline": "solutions/gdn/flashinfer_wrapper_123ca6.json",
+  "baseline": "solutions/gdn/flashinfer_gdn_prefill.json",
   "tolerance": {
     "atol": 0.01,
     "rtol": 0.01,
diff --git a/tests/test_task_acceptance.py b/tests/test_task_acceptance.py
new file mode 100644
index 0000000000000000000000000000000000000000..58c4611bbf7d86468c041034eb0de91e46ff4a3a
--- /dev/null
+++ b/tests/test_task_acceptance.py
@@ -0,0 +1,68 @@
+"""Regression cases for the task policies used by both validation runners."""
+
+import sys
+import unittest
+from pathlib import Path
+
+import torch
+
+sys.path.insert(0, str(Path(__file__).resolve().parents[1] / "scripts"))
+from task_acceptance import compare_output
+
+
+class TaskAcceptanceTests(unittest.TestCase):
+    def test_contest_or_is_not_additive_tolerance(self):
+        expected = torch.tensor([100.0])
+        actual = torch.tensor([115.0])
+        additive = dict(atol=10.0, rtol=0.1)
+        compare_output(actual, expected, additive)
+        with self.assertRaises(AssertionError):
+            compare_output(
+                actual, expected, dict(additive, comparison="absolute_or_relative")
+            )
+
+    def test_strict_gdn_diagnostic_is_distinct_from_contest(self):
+        expected, actual = torch.tensor([0.05]), torch.tensor([0.05151])
+        with self.assertRaises(AssertionError):
+            compare_output(actual, expected, dict(atol=2e-5, rtol=1e-4))
+        compare_output(
+            actual,
+            expected,
+            dict(atol=0.01, rtol=0.01, comparison="absolute_or_relative"),
+        )
+
+    def test_matched_ratio_boundary_uses_integer_counts(self):
+        expected = torch.zeros(10000)
+        actual = expected.clone()
+        actual[0] = 1.0
+        metrics = compare_output(
+            actual, expected, dict(atol=0.0, rtol=0.0, required_matched_ratio=0.9999)
+        )
+        self.assertEqual(metrics["mismatched_elements"], 1)
+        actual[1] = 1.0
+        with self.assertRaises(AssertionError):
+            compare_output(
+                actual,
+                expected,
+                dict(atol=0.0, rtol=0.0, required_matched_ratio=0.9999),
+            )
+        metrics = compare_output(expected, expected, dict(atol=0.0, rtol=0.0))
+        self.assertEqual(metrics["matched_ratio"], 1.0)
+
+    def test_nonfinite_values_and_integer_mismatches_fail(self):
+        for value in [float("nan"), float("inf")]:
+            with self.assertRaises(AssertionError):
+                compare_output(
+                    torch.tensor([value]),
+                    torch.tensor([value]),
+                    dict(atol=1.0, rtol=1.0),
+                )
+        with self.assertRaises(AssertionError):
+            compare_output(
+                torch.tensor([1]), torch.tensor([2]), dict(atol=100.0, rtol=100.0)
+            )
+        compare_output(torch.tensor([1]), torch.tensor([1]), dict(atol=0.0, rtol=0.0))
+
+
+if __name__ == "__main__":
+    unittest.main()
diff --git a/workloads/block_causal_attention/prefix_cached_block_causal_h32_d128.jsonl b/workloads/block_causal_attention/prefix_cached_block_causal_h32_d128.jsonl
index abd14a6d7139b69ba38fd2f8be416190978395a0..55cd47ed81737dcae702b48b2c67b13219b8bbef 100644
--- a/workloads/block_causal_attention/prefix_cached_block_causal_h32_d128.jsonl
+++ b/workloads/block_causal_attention/prefix_cached_block_causal_h32_d128.jsonl
@@ -1,28 +1,28 @@
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diff --git a/workloads/block_causal_attention/prefix_cached_block_causal_h32_d128_prefix0.jsonl b/workloads/block_causal_attention/prefix_cached_block_causal_h32_d128_prefix0.jsonl
index fc70cce251fda602a25e40a786135b524be69d25..6b43442ba3229b557b03fc46d753ef2f607ee1f6 100644
--- a/workloads/block_causal_attention/prefix_cached_block_causal_h32_d128_prefix0.jsonl
+++ b/workloads/block_causal_attention/prefix_cached_block_causal_h32_d128_prefix0.jsonl
@@ -1,12 +1,12 @@
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diff --git a/workloads/dense_attention/noncausal_dense_attention_h32_d128.jsonl b/workloads/dense_attention/noncausal_dense_attention_h32_d128.jsonl
index f04c34faf4bb792021fee725f1dec8c04b0d022d..45b959a14860e20d7dbaccc94e317d4d178c68e2 100644
--- a/workloads/dense_attention/noncausal_dense_attention_h32_d128.jsonl
+++ b/workloads/dense_attention/noncausal_dense_attention_h32_d128.jsonl
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diff --git a/workloads/dense_attention/noncausal_dense_attention_h32_d64.jsonl b/workloads/dense_attention/noncausal_dense_attention_h32_d64.jsonl
index 86cd1f1f105f0734be3e2d84bd52d41042f830cf..d736b4fe006da3e60e436e8c15d5a8a7d7d35911 100644
--- a/workloads/dense_attention/noncausal_dense_attention_h32_d64.jsonl
+++ b/workloads/dense_attention/noncausal_dense_attention_h32_d64.jsonl
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